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KVM: Always report x2apic as supported feature
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
674eea0f
AK		 80static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
ed85c068
AP		 86int ignore_msrs = 0;
87module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
417bc304 89struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 102 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 110 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 111 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 119 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 121 { "largepages", VM_STAT(lpages) },
417bc304
HB		 122 { NULL }
123};
124
5fb76f9b
CO		 125unsigned long segment_base(u16 selector)
126{
127 struct descriptor_table gdt;
a5f61300 128 struct desc_struct *d;
5fb76f9b
CO		 129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
135 asm("sgdt %0" : "=m"(gdt));
136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
139 u16 ldt_selector;
140
141 asm("sldt %0" : "=g"(ldt_selector));
142 table_base = segment_base(ldt_selector);
143 }
a5f61300
AK		 144 d = (struct desc_struct *)(table_base + (selector & ~7));
145 v = d->base0 | ((unsigned long)d->base1 << 16) |
146 ((unsigned long)d->base2 << 24);
5fb76f9b 147#ifdef CONFIG_X86_64
a5f61300
AK		 148 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
149 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 150#endif
151 return v;
152}
153EXPORT_SYMBOL_GPL(segment_base);
154
6866b83e
CO		 155u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
156{
157 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 158 return vcpu->arch.apic_base;
6866b83e 159 else
ad312c7c 160 return vcpu->arch.apic_base;
6866b83e
CO		 161}
162EXPORT_SYMBOL_GPL(kvm_get_apic_base);
163
164void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
165{
166 /* TODO: reserve bits check */
167 if (irqchip_in_kernel(vcpu->kvm))
168 kvm_lapic_set_base(vcpu, data);
169 else
ad312c7c 170 vcpu->arch.apic_base = data;
6866b83e
CO		 171}
172EXPORT_SYMBOL_GPL(kvm_set_apic_base);
173
298101da
AK		 174void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
175{
ad312c7c
ZX		 176 WARN_ON(vcpu->arch.exception.pending);
177 vcpu->arch.exception.pending = true;
178 vcpu->arch.exception.has_error_code = false;
179 vcpu->arch.exception.nr = nr;
298101da
AK		 180}
181EXPORT_SYMBOL_GPL(kvm_queue_exception);
182
c3c91fee
AK		 183void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
184 u32 error_code)
185{
186 ++vcpu->stat.pf_guest;
d8017474 187
71c4dfaf 188 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 189 switch(vcpu->arch.exception.nr) {
190 case DF_VECTOR:
71c4dfaf
JR		 191 /* triple fault -> shutdown */
192 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 193 return;
194 case PF_VECTOR:
195 vcpu->arch.exception.nr = DF_VECTOR;
196 vcpu->arch.exception.error_code = 0;
197 return;
198 default:
199 /* replace previous exception with a new one in a hope
200 that instruction re-execution will regenerate lost
201 exception */
202 vcpu->arch.exception.pending = false;
203 break;
71c4dfaf 204 }
c3c91fee 205 }
ad312c7c 206 vcpu->arch.cr2 = addr;
c3c91fee
AK		 207 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
208}
209
3419ffc8
SY		 210void kvm_inject_nmi(struct kvm_vcpu *vcpu)
211{
212 vcpu->arch.nmi_pending = 1;
213}
214EXPORT_SYMBOL_GPL(kvm_inject_nmi);
215
298101da
AK		 216void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
217{
ad312c7c
ZX		 218 WARN_ON(vcpu->arch.exception.pending);
219 vcpu->arch.exception.pending = true;
220 vcpu->arch.exception.has_error_code = true;
221 vcpu->arch.exception.nr = nr;
222 vcpu->arch.exception.error_code = error_code;
298101da
AK		 223}
224EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
225
226static void __queue_exception(struct kvm_vcpu *vcpu)
227{
ad312c7c
ZX		 228 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
229 vcpu->arch.exception.has_error_code,
230 vcpu->arch.exception.error_code);
298101da
AK		 231}
232
a03490ed
CO		 233/*
234 * Load the pae pdptrs. Return true is they are all valid.
235 */
236int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
237{
238 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
239 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
240 int i;
241 int ret;
ad312c7c 242 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 243
a03490ed
CO		 244 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
245 offset * sizeof(u64), sizeof(pdpte));
246 if (ret < 0) {
247 ret = 0;
248 goto out;
249 }
250 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 251 if (is_present_gpte(pdpte[i]) &&
20c466b5 252 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 253 ret = 0;
254 goto out;
255 }
256 }
257 ret = 1;
258
ad312c7c 259 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 260 __set_bit(VCPU_EXREG_PDPTR,
261 (unsigned long *)&vcpu->arch.regs_avail);
262 __set_bit(VCPU_EXREG_PDPTR,
263 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 264out:
a03490ed
CO		 265
266 return ret;
267}
cc4b6871 268EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 269
d835dfec
AK		 270static bool pdptrs_changed(struct kvm_vcpu *vcpu)
271{
ad312c7c 272 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 273 bool changed = true;
274 int r;
275
276 if (is_long_mode(vcpu) || !is_pae(vcpu))
277 return false;
278
6de4f3ad
AK		 279 if (!test_bit(VCPU_EXREG_PDPTR,
280 (unsigned long *)&vcpu->arch.regs_avail))
281 return true;
282
ad312c7c 283 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 284 if (r < 0)
285 goto out;
ad312c7c 286 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 287out:
d835dfec
AK		 288
289 return changed;
290}
291
2d3ad1f4 292void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 293{
294 if (cr0 & CR0_RESERVED_BITS) {
295 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 296 cr0, vcpu->arch.cr0);
c1a5d4f9 297 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 298 return;
299 }
300
301 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
302 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 303 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 304 return;
305 }
306
307 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
308 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
309 "and a clear PE flag\n");
c1a5d4f9 310 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 311 return;
312 }
313
314 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
315#ifdef CONFIG_X86_64
ad312c7c 316 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 317 int cs_db, cs_l;
318
319 if (!is_pae(vcpu)) {
320 printk(KERN_DEBUG "set_cr0: #GP, start paging "
321 "in long mode while PAE is disabled\n");
c1a5d4f9 322 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 323 return;
324 }
325 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
326 if (cs_l) {
327 printk(KERN_DEBUG "set_cr0: #GP, start paging "
328 "in long mode while CS.L == 1\n");
c1a5d4f9 329 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 330 return;
331
332 }
333 } else
334#endif
ad312c7c 335 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 336 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
337 "reserved bits\n");
c1a5d4f9 338 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 339 return;
340 }
341
342 }
343
344 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 345 vcpu->arch.cr0 = cr0;
a03490ed 346
a03490ed 347 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 348 return;
349}
2d3ad1f4 350EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 351
2d3ad1f4 352void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 353{
2d3ad1f4 354 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 355}
2d3ad1f4 356EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 357
2d3ad1f4 358void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 359{
a2edf57f
AK		 360 unsigned long old_cr4 = vcpu->arch.cr4;
361 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
362
a03490ed
CO		 363 if (cr4 & CR4_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
368
369 if (is_long_mode(vcpu)) {
370 if (!(cr4 & X86_CR4_PAE)) {
371 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
372 "in long mode\n");
c1a5d4f9 373 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 374 return;
375 }
a2edf57f
AK		 376 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
377 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 378 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 379 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 380 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 381 return;
382 }
383
384 if (cr4 & X86_CR4_VMXE) {
385 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 386 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 387 return;
388 }
389 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 390 vcpu->arch.cr4 = cr4;
5a41accd 391 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 392 kvm_mmu_reset_context(vcpu);
a03490ed 393}
2d3ad1f4 394EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 395
2d3ad1f4 396void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 397{
ad312c7c 398 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 399 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 400 kvm_mmu_flush_tlb(vcpu);
401 return;
402 }
403
a03490ed
CO		 404 if (is_long_mode(vcpu)) {
405 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
406 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 407 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 408 return;
409 }
410 } else {
411 if (is_pae(vcpu)) {
412 if (cr3 & CR3_PAE_RESERVED_BITS) {
413 printk(KERN_DEBUG
414 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 415 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 416 return;
417 }
418 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
419 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
420 "reserved bits\n");
c1a5d4f9 421 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 422 return;
423 }
424 }
425 /*
426 * We don't check reserved bits in nonpae mode, because
427 * this isn't enforced, and VMware depends on this.
428 */
429 }
430
a03490ed
CO		 431 /*
432 * Does the new cr3 value map to physical memory? (Note, we
433 * catch an invalid cr3 even in real-mode, because it would
434 * cause trouble later on when we turn on paging anyway.)
435 *
436 * A real CPU would silently accept an invalid cr3 and would
437 * attempt to use it - with largely undefined (and often hard
438 * to debug) behavior on the guest side.
439 */
440 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 441 kvm_inject_gp(vcpu, 0);
a03490ed 442 else {
ad312c7c
ZX		 443 vcpu->arch.cr3 = cr3;
444 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 445 }
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 448
2d3ad1f4 449void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 450{
451 if (cr8 & CR8_RESERVED_BITS) {
452 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 453 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 454 return;
455 }
456 if (irqchip_in_kernel(vcpu->kvm))
457 kvm_lapic_set_tpr(vcpu, cr8);
458 else
ad312c7c 459 vcpu->arch.cr8 = cr8;
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 462
2d3ad1f4 463unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 464{
465 if (irqchip_in_kernel(vcpu->kvm))
466 return kvm_lapic_get_cr8(vcpu);
467 else
ad312c7c 468 return vcpu->arch.cr8;
a03490ed 469}
2d3ad1f4 470EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 471
d8017474
AG		 472static inline u32 bit(int bitno)
473{
474 return 1 << (bitno & 31);
475}
476
043405e1
CO		 477/*
478 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
479 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
480 *
481 * This list is modified at module load time to reflect the
482 * capabilities of the host cpu.
483 */
484static u32 msrs_to_save[] = {
485 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
486 MSR_K6_STAR,
487#ifdef CONFIG_X86_64
488 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
489#endif
af24a4e4 490 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 491 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 492};
493
494static unsigned num_msrs_to_save;
495
496static u32 emulated_msrs[] = {
497 MSR_IA32_MISC_ENABLE,
498};
499
15c4a640
CO		 500static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
501{
f2b4b7dd 502 if (efer & efer_reserved_bits) {
15c4a640
CO		 503 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
504 efer);
c1a5d4f9 505 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 506 return;
507 }
508
509 if (is_paging(vcpu)
ad312c7c 510 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 511 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 512 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 513 return;
514 }
515
1b2fd70c
AG		 516 if (efer & EFER_FFXSR) {
517 struct kvm_cpuid_entry2 *feat;
518
519 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
520 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
521 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
522 kvm_inject_gp(vcpu, 0);
523 return;
524 }
525 }
526
d8017474
AG		 527 if (efer & EFER_SVME) {
528 struct kvm_cpuid_entry2 *feat;
529
530 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
531 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
532 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
533 kvm_inject_gp(vcpu, 0);
534 return;
535 }
536 }
537
15c4a640
CO		 538 kvm_x86_ops->set_efer(vcpu, efer);
539
540 efer &= ~EFER_LMA;
ad312c7c 541 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 542
ad312c7c 543 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 544
545 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
546 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 547}
548
f2b4b7dd
JR		 549void kvm_enable_efer_bits(u64 mask)
550{
551 efer_reserved_bits &= ~mask;
552}
553EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
554
555
15c4a640
CO		 556/*
557 * Writes msr value into into the appropriate "register".
558 * Returns 0 on success, non-0 otherwise.
559 * Assumes vcpu_load() was already called.
560 */
561int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
562{
563 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
564}
565
313a3dc7
CO		 566/*
567 * Adapt set_msr() to msr_io()'s calling convention
568 */
569static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
570{
571 return kvm_set_msr(vcpu, index, *data);
572}
573
18068523
GOC		 574static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
575{
576 static int version;
50d0a0f9
GH		 577 struct pvclock_wall_clock wc;
578 struct timespec now, sys, boot;
18068523
GOC		 579
580 if (!wall_clock)
581 return;
582
583 version++;
584
18068523
GOC		 585 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
586
50d0a0f9
GH		 587 /*
588 * The guest calculates current wall clock time by adding
589 * system time (updated by kvm_write_guest_time below) to the
590 * wall clock specified here. guest system time equals host
591 * system time for us, thus we must fill in host boot time here.
592 */
593 now = current_kernel_time();
594 ktime_get_ts(&sys);
595 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
596
597 wc.sec = boot.tv_sec;
598 wc.nsec = boot.tv_nsec;
599 wc.version = version;
18068523
GOC		 600
601 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
602
603 version++;
604 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 605}
606
50d0a0f9
GH		 607static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
608{
609 uint32_t quotient, remainder;
610
611 /* Don't try to replace with do_div(), this one calculates
612 * "(dividend << 32) / divisor" */
613 __asm__ ( "divl %4"
614 : "=a" (quotient), "=d" (remainder)
615 : "0" (0), "1" (dividend), "r" (divisor) );
616 return quotient;
617}
618
619static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
620{
621 uint64_t nsecs = 1000000000LL;
622 int32_t shift = 0;
623 uint64_t tps64;
624 uint32_t tps32;
625
626 tps64 = tsc_khz * 1000LL;
627 while (tps64 > nsecs*2) {
628 tps64 >>= 1;
629 shift--;
630 }
631
632 tps32 = (uint32_t)tps64;
633 while (tps32 <= (uint32_t)nsecs) {
634 tps32 <<= 1;
635 shift++;
636 }
637
638 hv_clock->tsc_shift = shift;
639 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
640
641 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 642 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 643 hv_clock->tsc_to_system_mul);
644}
645
c8076604
GH		 646static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
647
18068523
GOC		 648static void kvm_write_guest_time(struct kvm_vcpu *v)
649{
650 struct timespec ts;
651 unsigned long flags;
652 struct kvm_vcpu_arch *vcpu = &v->arch;
653 void *shared_kaddr;
463656c0 654 unsigned long this_tsc_khz;
18068523
GOC		 655
656 if ((!vcpu->time_page))
657 return;
658
463656c0
AK		 659 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
660 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
661 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
662 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 663 }
463656c0 664 put_cpu_var(cpu_tsc_khz);
50d0a0f9 665
18068523
GOC		 666 /* Keep irq disabled to prevent changes to the clock */
667 local_irq_save(flags);
af24a4e4 668 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 669 ktime_get_ts(&ts);
670 local_irq_restore(flags);
671
672 /* With all the info we got, fill in the values */
673
674 vcpu->hv_clock.system_time = ts.tv_nsec +
675 (NSEC_PER_SEC * (u64)ts.tv_sec);
676 /*
677 * The interface expects us to write an even number signaling that the
678 * update is finished. Since the guest won't see the intermediate
50d0a0f9 679 * state, we just increase by 2 at the end.
18068523 680 */
50d0a0f9 681 vcpu->hv_clock.version += 2;
18068523
GOC		 682
683 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
684
685 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 686 sizeof(vcpu->hv_clock));
18068523
GOC		 687
688 kunmap_atomic(shared_kaddr, KM_USER0);
689
690 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
691}
692
c8076604
GH		 693static int kvm_request_guest_time_update(struct kvm_vcpu *v)
694{
695 struct kvm_vcpu_arch *vcpu = &v->arch;
696
697 if (!vcpu->time_page)
698 return 0;
699 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
700 return 1;
701}
702
9ba075a6
AK		 703static bool msr_mtrr_valid(unsigned msr)
704{
705 switch (msr) {
706 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
707 case MSR_MTRRfix64K_00000:
708 case MSR_MTRRfix16K_80000:
709 case MSR_MTRRfix16K_A0000:
710 case MSR_MTRRfix4K_C0000:
711 case MSR_MTRRfix4K_C8000:
712 case MSR_MTRRfix4K_D0000:
713 case MSR_MTRRfix4K_D8000:
714 case MSR_MTRRfix4K_E0000:
715 case MSR_MTRRfix4K_E8000:
716 case MSR_MTRRfix4K_F0000:
717 case MSR_MTRRfix4K_F8000:
718 case MSR_MTRRdefType:
719 case MSR_IA32_CR_PAT:
720 return true;
721 case 0x2f8:
722 return true;
723 }
724 return false;
725}
726
d6289b93
MT		 727static bool valid_pat_type(unsigned t)
728{
729 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
730}
731
732static bool valid_mtrr_type(unsigned t)
733{
734 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
735}
736
737static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
738{
739 int i;
740
741 if (!msr_mtrr_valid(msr))
742 return false;
743
744 if (msr == MSR_IA32_CR_PAT) {
745 for (i = 0; i < 8; i++)
746 if (!valid_pat_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 } else if (msr == MSR_MTRRdefType) {
750 if (data & ~0xcff)
751 return false;
752 return valid_mtrr_type(data & 0xff);
753 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
754 for (i = 0; i < 8 ; i++)
755 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
756 return false;
757 return true;
758 }
759
760 /* variable MTRRs */
761 return valid_mtrr_type(data & 0xff);
762}
763
9ba075a6
AK		 764static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
765{
0bed3b56
SY		 766 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
767
d6289b93 768 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 769 return 1;
770
0bed3b56
SY		 771 if (msr == MSR_MTRRdefType) {
772 vcpu->arch.mtrr_state.def_type = data;
773 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
774 } else if (msr == MSR_MTRRfix64K_00000)
775 p[0] = data;
776 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
777 p[1 + msr - MSR_MTRRfix16K_80000] = data;
778 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
779 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
780 else if (msr == MSR_IA32_CR_PAT)
781 vcpu->arch.pat = data;
782 else { /* Variable MTRRs */
783 int idx, is_mtrr_mask;
784 u64 *pt;
785
786 idx = (msr - 0x200) / 2;
787 is_mtrr_mask = msr - 0x200 - 2 * idx;
788 if (!is_mtrr_mask)
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
791 else
792 pt =
793 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
794 *pt = data;
795 }
796
797 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 798 return 0;
799}
15c4a640 800
890ca9ae 801static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 802{
890ca9ae
HY		 803 u64 mcg_cap = vcpu->arch.mcg_cap;
804 unsigned bank_num = mcg_cap & 0xff;
805
15c4a640 806 switch (msr) {
15c4a640 807 case MSR_IA32_MCG_STATUS:
890ca9ae 808 vcpu->arch.mcg_status = data;
15c4a640 809 break;
c7ac679c 810 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 811 if (!(mcg_cap & MCG_CTL_P))
812 return 1;
813 if (data != 0 && data != ~(u64)0)
814 return -1;
815 vcpu->arch.mcg_ctl = data;
816 break;
817 default:
818 if (msr >= MSR_IA32_MC0_CTL &&
819 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
820 u32 offset = msr - MSR_IA32_MC0_CTL;
821 /* only 0 or all 1s can be written to IA32_MCi_CTL */
822 if ((offset & 0x3) == 0 &&
823 data != 0 && data != ~(u64)0)
824 return -1;
825 vcpu->arch.mce_banks[offset] = data;
826 break;
827 }
828 return 1;
829 }
830 return 0;
831}
832
833int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
834{
835 switch (msr) {
836 case MSR_EFER:
837 set_efer(vcpu, data);
c7ac679c 838 break;
8f1589d9
AP		 839 case MSR_K7_HWCR:
840 data &= ~(u64)0x40; /* ignore flush filter disable */
841 if (data != 0) {
842 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
843 data);
844 return 1;
845 }
846 break;
f7c6d140
AP		 847 case MSR_FAM10H_MMIO_CONF_BASE:
848 if (data != 0) {
849 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
850 "0x%llx\n", data);
851 return 1;
852 }
853 break;
c323c0e5
AP		 854 case MSR_AMD64_NB_CFG:
855 break;
b5e2fec0
AG		 856 case MSR_IA32_DEBUGCTLMSR:
857 if (!data) {
858 /* We support the non-activated case already */
859 break;
860 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
861 /* Values other than LBR and BTF are vendor-specific,
862 thus reserved and should throw a #GP */
863 return 1;
864 }
865 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
866 __func__, data);
867 break;
15c4a640
CO		 868 case MSR_IA32_UCODE_REV:
869 case MSR_IA32_UCODE_WRITE:
61a6bd67 870 case MSR_VM_HSAVE_PA:
6098ca93 871 case MSR_AMD64_PATCH_LOADER:
15c4a640 872 break;
9ba075a6
AK		 873 case 0x200 ... 0x2ff:
874 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 875 case MSR_IA32_APICBASE:
876 kvm_set_apic_base(vcpu, data);
877 break;
0105d1a5
GN		 878 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
879 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 880 case MSR_IA32_MISC_ENABLE:
ad312c7c 881 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 882 break;
18068523
GOC		 883 case MSR_KVM_WALL_CLOCK:
884 vcpu->kvm->arch.wall_clock = data;
885 kvm_write_wall_clock(vcpu->kvm, data);
886 break;
887 case MSR_KVM_SYSTEM_TIME: {
888 if (vcpu->arch.time_page) {
889 kvm_release_page_dirty(vcpu->arch.time_page);
890 vcpu->arch.time_page = NULL;
891 }
892
893 vcpu->arch.time = data;
894
895 /* we verify if the enable bit is set... */
896 if (!(data & 1))
897 break;
898
899 /* ...but clean it before doing the actual write */
900 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
901
18068523
GOC		 902 vcpu->arch.time_page =
903 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 904
905 if (is_error_page(vcpu->arch.time_page)) {
906 kvm_release_page_clean(vcpu->arch.time_page);
907 vcpu->arch.time_page = NULL;
908 }
909
c8076604 910 kvm_request_guest_time_update(vcpu);
18068523
GOC		 911 break;
912 }
890ca9ae
HY		 913 case MSR_IA32_MCG_CTL:
914 case MSR_IA32_MCG_STATUS:
915 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
916 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 917
918 /* Performance counters are not protected by a CPUID bit,
919 * so we should check all of them in the generic path for the sake of
920 * cross vendor migration.
921 * Writing a zero into the event select MSRs disables them,
922 * which we perfectly emulate ;-). Any other value should be at least
923 * reported, some guests depend on them.
924 */
925 case MSR_P6_EVNTSEL0:
926 case MSR_P6_EVNTSEL1:
927 case MSR_K7_EVNTSEL0:
928 case MSR_K7_EVNTSEL1:
929 case MSR_K7_EVNTSEL2:
930 case MSR_K7_EVNTSEL3:
931 if (data != 0)
932 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
933 "0x%x data 0x%llx\n", msr, data);
934 break;
935 /* at least RHEL 4 unconditionally writes to the perfctr registers,
936 * so we ignore writes to make it happy.
937 */
938 case MSR_P6_PERFCTR0:
939 case MSR_P6_PERFCTR1:
940 case MSR_K7_PERFCTR0:
941 case MSR_K7_PERFCTR1:
942 case MSR_K7_PERFCTR2:
943 case MSR_K7_PERFCTR3:
944 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
945 "0x%x data 0x%llx\n", msr, data);
946 break;
15c4a640 947 default:
ed85c068
AP		 948 if (!ignore_msrs) {
949 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
950 msr, data);
951 return 1;
952 } else {
953 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
954 msr, data);
955 break;
956 }
15c4a640
CO		 957 }
958 return 0;
959}
960EXPORT_SYMBOL_GPL(kvm_set_msr_common);
961
962
963/*
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
967 */
968int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
969{
970 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
971}
972
9ba075a6
AK		 973static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
974{
0bed3b56
SY		 975 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
976
9ba075a6
AK		 977 if (!msr_mtrr_valid(msr))
978 return 1;
979
0bed3b56
SY		 980 if (msr == MSR_MTRRdefType)
981 *pdata = vcpu->arch.mtrr_state.def_type +
982 (vcpu->arch.mtrr_state.enabled << 10);
983 else if (msr == MSR_MTRRfix64K_00000)
984 *pdata = p[0];
985 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
986 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
987 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
988 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
989 else if (msr == MSR_IA32_CR_PAT)
990 *pdata = vcpu->arch.pat;
991 else { /* Variable MTRRs */
992 int idx, is_mtrr_mask;
993 u64 *pt;
994
995 idx = (msr - 0x200) / 2;
996 is_mtrr_mask = msr - 0x200 - 2 * idx;
997 if (!is_mtrr_mask)
998 pt =
999 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1000 else
1001 pt =
1002 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1003 *pdata = *pt;
1004 }
1005
9ba075a6
AK		 1006 return 0;
1007}
1008
890ca9ae 1009static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1010{
1011 u64 data;
890ca9ae
HY		 1012 u64 mcg_cap = vcpu->arch.mcg_cap;
1013 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1014
1015 switch (msr) {
15c4a640
CO		 1016 case MSR_IA32_P5_MC_ADDR:
1017 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1018 data = 0;
1019 break;
15c4a640 1020 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1021 data = vcpu->arch.mcg_cap;
1022 break;
c7ac679c 1023 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1024 if (!(mcg_cap & MCG_CTL_P))
1025 return 1;
1026 data = vcpu->arch.mcg_ctl;
1027 break;
1028 case MSR_IA32_MCG_STATUS:
1029 data = vcpu->arch.mcg_status;
1030 break;
1031 default:
1032 if (msr >= MSR_IA32_MC0_CTL &&
1033 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1034 u32 offset = msr - MSR_IA32_MC0_CTL;
1035 data = vcpu->arch.mce_banks[offset];
1036 break;
1037 }
1038 return 1;
1039 }
1040 *pdata = data;
1041 return 0;
1042}
1043
1044int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1045{
1046 u64 data;
1047
1048 switch (msr) {
890ca9ae 1049 case MSR_IA32_PLATFORM_ID:
15c4a640 1050 case MSR_IA32_UCODE_REV:
15c4a640 1051 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1052 case MSR_IA32_DEBUGCTLMSR:
1053 case MSR_IA32_LASTBRANCHFROMIP:
1054 case MSR_IA32_LASTBRANCHTOIP:
1055 case MSR_IA32_LASTINTFROMIP:
1056 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1057 case MSR_K8_SYSCFG:
1058 case MSR_K7_HWCR:
61a6bd67 1059 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1060 case MSR_P6_EVNTSEL0:
1061 case MSR_P6_EVNTSEL1:
9e699624 1062 case MSR_K7_EVNTSEL0:
1fdbd48c 1063 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1064 case MSR_AMD64_NB_CFG:
f7c6d140 1065 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1066 data = 0;
1067 break;
9ba075a6
AK		 1068 case MSR_MTRRcap:
1069 data = 0x500 | KVM_NR_VAR_MTRR;
1070 break;
1071 case 0x200 ... 0x2ff:
1072 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1073 case 0xcd: /* fsb frequency */
1074 data = 3;
1075 break;
1076 case MSR_IA32_APICBASE:
1077 data = kvm_get_apic_base(vcpu);
1078 break;
0105d1a5
GN		 1079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1080 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1081 break;
15c4a640 1082 case MSR_IA32_MISC_ENABLE:
ad312c7c 1083 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1084 break;
847f0ad8
AG		 1085 case MSR_IA32_PERF_STATUS:
1086 /* TSC increment by tick */
1087 data = 1000ULL;
1088 /* CPU multiplier */
1089 data |= (((uint64_t)4ULL) << 40);
1090 break;
15c4a640 1091 case MSR_EFER:
ad312c7c 1092 data = vcpu->arch.shadow_efer;
15c4a640 1093 break;
18068523
GOC		 1094 case MSR_KVM_WALL_CLOCK:
1095 data = vcpu->kvm->arch.wall_clock;
1096 break;
1097 case MSR_KVM_SYSTEM_TIME:
1098 data = vcpu->arch.time;
1099 break;
890ca9ae
HY		 1100 case MSR_IA32_P5_MC_ADDR:
1101 case MSR_IA32_P5_MC_TYPE:
1102 case MSR_IA32_MCG_CAP:
1103 case MSR_IA32_MCG_CTL:
1104 case MSR_IA32_MCG_STATUS:
1105 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1106 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1107 default:
ed85c068
AP		 1108 if (!ignore_msrs) {
1109 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1110 return 1;
1111 } else {
1112 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1113 data = 0;
1114 }
1115 break;
15c4a640
CO		 1116 }
1117 *pdata = data;
1118 return 0;
1119}
1120EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1121
313a3dc7
CO		 1122/*
1123 * Read or write a bunch of msrs. All parameters are kernel addresses.
1124 *
1125 * @return number of msrs set successfully.
1126 */
1127static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1128 struct kvm_msr_entry *entries,
1129 int (*do_msr)(struct kvm_vcpu *vcpu,
1130 unsigned index, u64 *data))
1131{
1132 int i;
1133
1134 vcpu_load(vcpu);
1135
3200f405 1136 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1137 for (i = 0; i < msrs->nmsrs; ++i)
1138 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1139 break;
3200f405 1140 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1141
1142 vcpu_put(vcpu);
1143
1144 return i;
1145}
1146
1147/*
1148 * Read or write a bunch of msrs. Parameters are user addresses.
1149 *
1150 * @return number of msrs set successfully.
1151 */
1152static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1153 int (*do_msr)(struct kvm_vcpu *vcpu,
1154 unsigned index, u64 *data),
1155 int writeback)
1156{
1157 struct kvm_msrs msrs;
1158 struct kvm_msr_entry *entries;
1159 int r, n;
1160 unsigned size;
1161
1162 r = -EFAULT;
1163 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1164 goto out;
1165
1166 r = -E2BIG;
1167 if (msrs.nmsrs >= MAX_IO_MSRS)
1168 goto out;
1169
1170 r = -ENOMEM;
1171 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1172 entries = vmalloc(size);
1173 if (!entries)
1174 goto out;
1175
1176 r = -EFAULT;
1177 if (copy_from_user(entries, user_msrs->entries, size))
1178 goto out_free;
1179
1180 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1181 if (r < 0)
1182 goto out_free;
1183
1184 r = -EFAULT;
1185 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1186 goto out_free;
1187
1188 r = n;
1189
1190out_free:
1191 vfree(entries);
1192out:
1193 return r;
1194}
1195
018d00d2
ZX		 1196int kvm_dev_ioctl_check_extension(long ext)
1197{
1198 int r;
1199
1200 switch (ext) {
1201 case KVM_CAP_IRQCHIP:
1202 case KVM_CAP_HLT:
1203 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1204 case KVM_CAP_SET_TSS_ADDR:
07716717 1205 case KVM_CAP_EXT_CPUID:
c8076604 1206 case KVM_CAP_CLOCKSOURCE:
7837699f 1207 case KVM_CAP_PIT:
a28e4f5a 1208 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1209 case KVM_CAP_MP_STATE:
ed848624 1210 case KVM_CAP_SYNC_MMU:
52d939a0 1211 case KVM_CAP_REINJECT_CONTROL:
4925663a 1212 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1213 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1214 case KVM_CAP_IRQFD:
c5ff41ce 1215 case KVM_CAP_PIT2:
018d00d2
ZX		 1216 r = 1;
1217 break;
542472b5
LV		 1218 case KVM_CAP_COALESCED_MMIO:
1219 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1220 break;
774ead3a
AK		 1221 case KVM_CAP_VAPIC:
1222 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1223 break;
f725230a
AK		 1224 case KVM_CAP_NR_VCPUS:
1225 r = KVM_MAX_VCPUS;
1226 break;
a988b910
AK		 1227 case KVM_CAP_NR_MEMSLOTS:
1228 r = KVM_MEMORY_SLOTS;
1229 break;
2f333bcb
MT		 1230 case KVM_CAP_PV_MMU:
1231 r = !tdp_enabled;
1232 break;
62c476c7 1233 case KVM_CAP_IOMMU:
19de40a8 1234 r = iommu_found();
62c476c7 1235 break;
890ca9ae
HY		 1236 case KVM_CAP_MCE:
1237 r = KVM_MAX_MCE_BANKS;
1238 break;
018d00d2
ZX		 1239 default:
1240 r = 0;
1241 break;
1242 }
1243 return r;
1244
1245}
1246
043405e1
CO		 1247long kvm_arch_dev_ioctl(struct file *filp,
1248 unsigned int ioctl, unsigned long arg)
1249{
1250 void __user *argp = (void __user *)arg;
1251 long r;
1252
1253 switch (ioctl) {
1254 case KVM_GET_MSR_INDEX_LIST: {
1255 struct kvm_msr_list __user *user_msr_list = argp;
1256 struct kvm_msr_list msr_list;
1257 unsigned n;
1258
1259 r = -EFAULT;
1260 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1261 goto out;
1262 n = msr_list.nmsrs;
1263 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1264 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1265 goto out;
1266 r = -E2BIG;
e125e7b6 1267 if (n < msr_list.nmsrs)
043405e1
CO		 1268 goto out;
1269 r = -EFAULT;
1270 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1271 num_msrs_to_save * sizeof(u32)))
1272 goto out;
e125e7b6 1273 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1274 &emulated_msrs,
1275 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1276 goto out;
1277 r = 0;
1278 break;
1279 }
674eea0f
AK		 1280 case KVM_GET_SUPPORTED_CPUID: {
1281 struct kvm_cpuid2 __user *cpuid_arg = argp;
1282 struct kvm_cpuid2 cpuid;
1283
1284 r = -EFAULT;
1285 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1286 goto out;
1287 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1288 cpuid_arg->entries);
674eea0f
AK		 1289 if (r)
1290 goto out;
1291
1292 r = -EFAULT;
1293 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1294 goto out;
1295 r = 0;
1296 break;
1297 }
890ca9ae
HY		 1298 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1299 u64 mce_cap;
1300
1301 mce_cap = KVM_MCE_CAP_SUPPORTED;
1302 r = -EFAULT;
1303 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1304 goto out;
1305 r = 0;
1306 break;
1307 }
043405e1
CO		 1308 default:
1309 r = -EINVAL;
1310 }
1311out:
1312 return r;
1313}
1314
313a3dc7
CO		 1315void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1316{
1317 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1318 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1319}
1320
1321void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1322{
1323 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1324 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1325}
1326
07716717 1327static int is_efer_nx(void)
313a3dc7 1328{
e286e86e 1329 unsigned long long efer = 0;
313a3dc7 1330
e286e86e 1331 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1332 return efer & EFER_NX;
1333}
1334
1335static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1336{
1337 int i;
1338 struct kvm_cpuid_entry2 *e, *entry;
1339
313a3dc7 1340 entry = NULL;
ad312c7c
ZX		 1341 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1342 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1343 if (e->function == 0x80000001) {
1344 entry = e;
1345 break;
1346 }
1347 }
07716717 1348 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1349 entry->edx &= ~(1 << 20);
1350 printk(KERN_INFO "kvm: guest NX capability removed\n");
1351 }
1352}
1353
07716717 1354/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1355static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1356 struct kvm_cpuid *cpuid,
1357 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1358{
1359 int r, i;
1360 struct kvm_cpuid_entry *cpuid_entries;
1361
1362 r = -E2BIG;
1363 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1364 goto out;
1365 r = -ENOMEM;
1366 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1367 if (!cpuid_entries)
1368 goto out;
1369 r = -EFAULT;
1370 if (copy_from_user(cpuid_entries, entries,
1371 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1372 goto out_free;
1373 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1374 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1375 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1376 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1377 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1378 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1379 vcpu->arch.cpuid_entries[i].index = 0;
1380 vcpu->arch.cpuid_entries[i].flags = 0;
1381 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1382 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1383 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1384 }
1385 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1386 cpuid_fix_nx_cap(vcpu);
1387 r = 0;
fc61b800 1388 kvm_apic_set_version(vcpu);
07716717
DK		 1389
1390out_free:
1391 vfree(cpuid_entries);
1392out:
1393 return r;
1394}
1395
1396static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1397 struct kvm_cpuid2 *cpuid,
1398 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1399{
1400 int r;
1401
1402 r = -E2BIG;
1403 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1404 goto out;
1405 r = -EFAULT;
ad312c7c 1406 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1407 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1408 goto out;
ad312c7c 1409 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1410 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1411 return 0;
1412
1413out:
1414 return r;
1415}
1416
07716717 1417static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1418 struct kvm_cpuid2 *cpuid,
1419 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1420{
1421 int r;
1422
1423 r = -E2BIG;
ad312c7c 1424 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1425 goto out;
1426 r = -EFAULT;
ad312c7c 1427 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1428 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1429 goto out;
1430 return 0;
1431
1432out:
ad312c7c 1433 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1434 return r;
1435}
1436
07716717 1437static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1438 u32 index)
07716717
DK		 1439{
1440 entry->function = function;
1441 entry->index = index;
1442 cpuid_count(entry->function, entry->index,
19355475 1443 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1444 entry->flags = 0;
1445}
1446
7faa4ee1
AK		 1447#define F(x) bit(X86_FEATURE_##x)
1448
07716717
DK		 1449static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1450 u32 index, int *nent, int maxnent)
1451{
7faa4ee1 1452 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1453#ifdef CONFIG_X86_64
7faa4ee1
AK		 1454 unsigned f_lm = F(LM);
1455#else
1456 unsigned f_lm = 0;
07716717 1457#endif
7faa4ee1
AK		 1458
1459 /* cpuid 1.edx */
1460 const u32 kvm_supported_word0_x86_features =
1461 F(FPU) | F(VME) | F(DE) | F(PSE) |
1462 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1463 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1464 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1465 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1466 0 /* Reserved, DS, ACPI */ | F(MMX) |
1467 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1468 0 /* HTT, TM, Reserved, PBE */;
1469 /* cpuid 0x80000001.edx */
1470 const u32 kvm_supported_word1_x86_features =
1471 F(FPU) | F(VME) | F(DE) | F(PSE) |
1472 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1473 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1474 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1475 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1476 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1477 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1478 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1479 /* cpuid 1.ecx */
1480 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1481 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1482 0 /* DS-CPL, VMX, SMX, EST */ |
1483 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1484 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1485 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1486 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1487 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1488 /* cpuid 0x80000001.ecx */
07716717 1489 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1490 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1491 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1492 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1493 0 /* SKINIT */ | 0 /* WDT */;
07716717 1494
19355475 1495 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1496 get_cpu();
1497 do_cpuid_1_ent(entry, function, index);
1498 ++*nent;
1499
1500 switch (function) {
1501 case 0:
1502 entry->eax = min(entry->eax, (u32)0xb);
1503 break;
1504 case 1:
1505 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1506 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1507 /* we support x2apic emulation even if host does not support
1508 * it since we emulate x2apic in software */
1509 entry->ecx |= F(X2APIC);
07716717
DK		 1510 break;
1511 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1512 * may return different values. This forces us to get_cpu() before
1513 * issuing the first command, and also to emulate this annoying behavior
1514 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1515 case 2: {
1516 int t, times = entry->eax & 0xff;
1517
1518 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1519 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1520 for (t = 1; t < times && *nent < maxnent; ++t) {
1521 do_cpuid_1_ent(&entry[t], function, 0);
1522 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1523 ++*nent;
1524 }
1525 break;
1526 }
1527 /* function 4 and 0xb have additional index. */
1528 case 4: {
14af3f3c 1529 int i, cache_type;
07716717
DK		 1530
1531 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1532 /* read more entries until cache_type is zero */
14af3f3c
HH		 1533 for (i = 1; *nent < maxnent; ++i) {
1534 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1535 if (!cache_type)
1536 break;
14af3f3c
HH		 1537 do_cpuid_1_ent(&entry[i], function, i);
1538 entry[i].flags |=
07716717
DK		 1539 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1540 ++*nent;
1541 }
1542 break;
1543 }
1544 case 0xb: {
14af3f3c 1545 int i, level_type;
07716717
DK		 1546
1547 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1548 /* read more entries until level_type is zero */
14af3f3c 1549 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1550 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1551 if (!level_type)
1552 break;
14af3f3c
HH		 1553 do_cpuid_1_ent(&entry[i], function, i);
1554 entry[i].flags |=
07716717
DK		 1555 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1556 ++*nent;
1557 }
1558 break;
1559 }
1560 case 0x80000000:
1561 entry->eax = min(entry->eax, 0x8000001a);
1562 break;
1563 case 0x80000001:
1564 entry->edx &= kvm_supported_word1_x86_features;
1565 entry->ecx &= kvm_supported_word6_x86_features;
1566 break;
1567 }
1568 put_cpu();
1569}
1570
7faa4ee1
AK		 1571#undef F
1572
674eea0f 1573static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1574 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1575{
1576 struct kvm_cpuid_entry2 *cpuid_entries;
1577 int limit, nent = 0, r = -E2BIG;
1578 u32 func;
1579
1580 if (cpuid->nent < 1)
1581 goto out;
1582 r = -ENOMEM;
1583 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1584 if (!cpuid_entries)
1585 goto out;
1586
1587 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1588 limit = cpuid_entries[0].eax;
1589 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1590 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1591 &nent, cpuid->nent);
07716717
DK		 1592 r = -E2BIG;
1593 if (nent >= cpuid->nent)
1594 goto out_free;
1595
1596 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1597 limit = cpuid_entries[nent - 1].eax;
1598 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1599 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1600 &nent, cpuid->nent);
cb007648
MM		 1601 r = -E2BIG;
1602 if (nent >= cpuid->nent)
1603 goto out_free;
1604
07716717
DK		 1605 r = -EFAULT;
1606 if (copy_to_user(entries, cpuid_entries,
19355475 1607 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1608 goto out_free;
1609 cpuid->nent = nent;
1610 r = 0;
1611
1612out_free:
1613 vfree(cpuid_entries);
1614out:
1615 return r;
1616}
1617
313a3dc7
CO		 1618static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1619 struct kvm_lapic_state *s)
1620{
1621 vcpu_load(vcpu);
ad312c7c 1622 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1623 vcpu_put(vcpu);
1624
1625 return 0;
1626}
1627
1628static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1629 struct kvm_lapic_state *s)
1630{
1631 vcpu_load(vcpu);
ad312c7c 1632 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1633 kvm_apic_post_state_restore(vcpu);
1634 vcpu_put(vcpu);
1635
1636 return 0;
1637}
1638
f77bc6a4
ZX		 1639static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1640 struct kvm_interrupt *irq)
1641{
1642 if (irq->irq < 0 || irq->irq >= 256)
1643 return -EINVAL;
1644 if (irqchip_in_kernel(vcpu->kvm))
1645 return -ENXIO;
1646 vcpu_load(vcpu);
1647
66fd3f7f 1648 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1649
1650 vcpu_put(vcpu);
1651
1652 return 0;
1653}
1654
c4abb7c9
JK		 1655static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1656{
1657 vcpu_load(vcpu);
1658 kvm_inject_nmi(vcpu);
1659 vcpu_put(vcpu);
1660
1661 return 0;
1662}
1663
b209749f
AK		 1664static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1665 struct kvm_tpr_access_ctl *tac)
1666{
1667 if (tac->flags)
1668 return -EINVAL;
1669 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1670 return 0;
1671}
1672
890ca9ae
HY		 1673static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1674 u64 mcg_cap)
1675{
1676 int r;
1677 unsigned bank_num = mcg_cap & 0xff, bank;
1678
1679 r = -EINVAL;
1680 if (!bank_num)
1681 goto out;
1682 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1683 goto out;
1684 r = 0;
1685 vcpu->arch.mcg_cap = mcg_cap;
1686 /* Init IA32_MCG_CTL to all 1s */
1687 if (mcg_cap & MCG_CTL_P)
1688 vcpu->arch.mcg_ctl = ~(u64)0;
1689 /* Init IA32_MCi_CTL to all 1s */
1690 for (bank = 0; bank < bank_num; bank++)
1691 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1692out:
1693 return r;
1694}
1695
1696static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1697 struct kvm_x86_mce *mce)
1698{
1699 u64 mcg_cap = vcpu->arch.mcg_cap;
1700 unsigned bank_num = mcg_cap & 0xff;
1701 u64 *banks = vcpu->arch.mce_banks;
1702
1703 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1704 return -EINVAL;
1705 /*
1706 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1707 * reporting is disabled
1708 */
1709 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1710 vcpu->arch.mcg_ctl != ~(u64)0)
1711 return 0;
1712 banks += 4 * mce->bank;
1713 /*
1714 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1715 * reporting is disabled for the bank
1716 */
1717 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1718 return 0;
1719 if (mce->status & MCI_STATUS_UC) {
1720 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1721 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1722 printk(KERN_DEBUG "kvm: set_mce: "
1723 "injects mce exception while "
1724 "previous one is in progress!\n");
1725 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1726 return 0;
1727 }
1728 if (banks[1] & MCI_STATUS_VAL)
1729 mce->status |= MCI_STATUS_OVER;
1730 banks[2] = mce->addr;
1731 banks[3] = mce->misc;
1732 vcpu->arch.mcg_status = mce->mcg_status;
1733 banks[1] = mce->status;
1734 kvm_queue_exception(vcpu, MC_VECTOR);
1735 } else if (!(banks[1] & MCI_STATUS_VAL)
1736 || !(banks[1] & MCI_STATUS_UC)) {
1737 if (banks[1] & MCI_STATUS_VAL)
1738 mce->status |= MCI_STATUS_OVER;
1739 banks[2] = mce->addr;
1740 banks[3] = mce->misc;
1741 banks[1] = mce->status;
1742 } else
1743 banks[1] |= MCI_STATUS_OVER;
1744 return 0;
1745}
1746
313a3dc7
CO		 1747long kvm_arch_vcpu_ioctl(struct file *filp,
1748 unsigned int ioctl, unsigned long arg)
1749{
1750 struct kvm_vcpu *vcpu = filp->private_data;
1751 void __user *argp = (void __user *)arg;
1752 int r;
b772ff36 1753 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1754
1755 switch (ioctl) {
1756 case KVM_GET_LAPIC: {
b772ff36 1757 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1758
b772ff36
DH		 1759 r = -ENOMEM;
1760 if (!lapic)
1761 goto out;
1762 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1763 if (r)
1764 goto out;
1765 r = -EFAULT;
b772ff36 1766 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1767 goto out;
1768 r = 0;
1769 break;
1770 }
1771 case KVM_SET_LAPIC: {
b772ff36
DH		 1772 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1773 r = -ENOMEM;
1774 if (!lapic)
1775 goto out;
313a3dc7 1776 r = -EFAULT;
b772ff36 1777 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1778 goto out;
b772ff36 1779 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1780 if (r)
1781 goto out;
1782 r = 0;
1783 break;
1784 }
f77bc6a4
ZX		 1785 case KVM_INTERRUPT: {
1786 struct kvm_interrupt irq;
1787
1788 r = -EFAULT;
1789 if (copy_from_user(&irq, argp, sizeof irq))
1790 goto out;
1791 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1792 if (r)
1793 goto out;
1794 r = 0;
1795 break;
1796 }
c4abb7c9
JK		 1797 case KVM_NMI: {
1798 r = kvm_vcpu_ioctl_nmi(vcpu);
1799 if (r)
1800 goto out;
1801 r = 0;
1802 break;
1803 }
313a3dc7
CO		 1804 case KVM_SET_CPUID: {
1805 struct kvm_cpuid __user *cpuid_arg = argp;
1806 struct kvm_cpuid cpuid;
1807
1808 r = -EFAULT;
1809 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1810 goto out;
1811 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1812 if (r)
1813 goto out;
1814 break;
1815 }
07716717
DK		 1816 case KVM_SET_CPUID2: {
1817 struct kvm_cpuid2 __user *cpuid_arg = argp;
1818 struct kvm_cpuid2 cpuid;
1819
1820 r = -EFAULT;
1821 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1822 goto out;
1823 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1824 cpuid_arg->entries);
07716717
DK		 1825 if (r)
1826 goto out;
1827 break;
1828 }
1829 case KVM_GET_CPUID2: {
1830 struct kvm_cpuid2 __user *cpuid_arg = argp;
1831 struct kvm_cpuid2 cpuid;
1832
1833 r = -EFAULT;
1834 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1835 goto out;
1836 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1837 cpuid_arg->entries);
07716717
DK		 1838 if (r)
1839 goto out;
1840 r = -EFAULT;
1841 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1842 goto out;
1843 r = 0;
1844 break;
1845 }
313a3dc7
CO		 1846 case KVM_GET_MSRS:
1847 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1848 break;
1849 case KVM_SET_MSRS:
1850 r = msr_io(vcpu, argp, do_set_msr, 0);
1851 break;
b209749f
AK		 1852 case KVM_TPR_ACCESS_REPORTING: {
1853 struct kvm_tpr_access_ctl tac;
1854
1855 r = -EFAULT;
1856 if (copy_from_user(&tac, argp, sizeof tac))
1857 goto out;
1858 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1859 if (r)
1860 goto out;
1861 r = -EFAULT;
1862 if (copy_to_user(argp, &tac, sizeof tac))
1863 goto out;
1864 r = 0;
1865 break;
1866 };
b93463aa
AK		 1867 case KVM_SET_VAPIC_ADDR: {
1868 struct kvm_vapic_addr va;
1869
1870 r = -EINVAL;
1871 if (!irqchip_in_kernel(vcpu->kvm))
1872 goto out;
1873 r = -EFAULT;
1874 if (copy_from_user(&va, argp, sizeof va))
1875 goto out;
1876 r = 0;
1877 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1878 break;
1879 }
890ca9ae
HY		 1880 case KVM_X86_SETUP_MCE: {
1881 u64 mcg_cap;
1882
1883 r = -EFAULT;
1884 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1885 goto out;
1886 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1887 break;
1888 }
1889 case KVM_X86_SET_MCE: {
1890 struct kvm_x86_mce mce;
1891
1892 r = -EFAULT;
1893 if (copy_from_user(&mce, argp, sizeof mce))
1894 goto out;
1895 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1896 break;
1897 }
313a3dc7
CO		 1898 default:
1899 r = -EINVAL;
1900 }
1901out:
7a6ce84c 1902 kfree(lapic);
313a3dc7
CO		 1903 return r;
1904}
1905
1fe779f8
CO		 1906static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1907{
1908 int ret;
1909
1910 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1911 return -1;
1912 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1913 return ret;
1914}
1915
1916static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1917 u32 kvm_nr_mmu_pages)
1918{
1919 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1920 return -EINVAL;
1921
72dc67a6 1922 down_write(&kvm->slots_lock);
7c8a83b7 1923 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1924
1925 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1926 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1927
7c8a83b7 1928 spin_unlock(&kvm->mmu_lock);
72dc67a6 1929 up_write(&kvm->slots_lock);
1fe779f8
CO		 1930 return 0;
1931}
1932
1933static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1934{
f05e70ac 1935 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1936}
1937
e9f85cde
ZX		 1938gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1939{
1940 int i;
1941 struct kvm_mem_alias *alias;
1942
d69fb81f
ZX		 1943 for (i = 0; i < kvm->arch.naliases; ++i) {
1944 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1945 if (gfn >= alias->base_gfn
1946 && gfn < alias->base_gfn + alias->npages)
1947 return alias->target_gfn + gfn - alias->base_gfn;
1948 }
1949 return gfn;
1950}
1951
1fe779f8
CO		 1952/*
1953 * Set a new alias region. Aliases map a portion of physical memory into
1954 * another portion. This is useful for memory windows, for example the PC
1955 * VGA region.
1956 */
1957static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1958 struct kvm_memory_alias *alias)
1959{
1960 int r, n;
1961 struct kvm_mem_alias *p;
1962
1963 r = -EINVAL;
1964 /* General sanity checks */
1965 if (alias->memory_size & (PAGE_SIZE - 1))
1966 goto out;
1967 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1968 goto out;
1969 if (alias->slot >= KVM_ALIAS_SLOTS)
1970 goto out;
1971 if (alias->guest_phys_addr + alias->memory_size
1972 < alias->guest_phys_addr)
1973 goto out;
1974 if (alias->target_phys_addr + alias->memory_size
1975 < alias->target_phys_addr)
1976 goto out;
1977
72dc67a6 1978 down_write(&kvm->slots_lock);
a1708ce8 1979 spin_lock(&kvm->mmu_lock);
1fe779f8 1980
d69fb81f 1981 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1982 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1983 p->npages = alias->memory_size >> PAGE_SHIFT;
1984 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1985
1986 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1987 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1988 break;
d69fb81f 1989 kvm->arch.naliases = n;
1fe779f8 1990
a1708ce8 1991 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1992 kvm_mmu_zap_all(kvm);
1993
72dc67a6 1994 up_write(&kvm->slots_lock);
1fe779f8
CO		 1995
1996 return 0;
1997
1998out:
1999 return r;
2000}
2001
2002static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2003{
2004 int r;
2005
2006 r = 0;
2007 switch (chip->chip_id) {
2008 case KVM_IRQCHIP_PIC_MASTER:
2009 memcpy(&chip->chip.pic,
2010 &pic_irqchip(kvm)->pics[0],
2011 sizeof(struct kvm_pic_state));
2012 break;
2013 case KVM_IRQCHIP_PIC_SLAVE:
2014 memcpy(&chip->chip.pic,
2015 &pic_irqchip(kvm)->pics[1],
2016 sizeof(struct kvm_pic_state));
2017 break;
2018 case KVM_IRQCHIP_IOAPIC:
2019 memcpy(&chip->chip.ioapic,
2020 ioapic_irqchip(kvm),
2021 sizeof(struct kvm_ioapic_state));
2022 break;
2023 default:
2024 r = -EINVAL;
2025 break;
2026 }
2027 return r;
2028}
2029
2030static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2031{
2032 int r;
2033
2034 r = 0;
2035 switch (chip->chip_id) {
2036 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2037 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2038 memcpy(&pic_irqchip(kvm)->pics[0],
2039 &chip->chip.pic,
2040 sizeof(struct kvm_pic_state));
894a9c55 2041 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2042 break;
2043 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2044 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2045 memcpy(&pic_irqchip(kvm)->pics[1],
2046 &chip->chip.pic,
2047 sizeof(struct kvm_pic_state));
894a9c55 2048 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2049 break;
2050 case KVM_IRQCHIP_IOAPIC:
894a9c55 2051 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2052 memcpy(ioapic_irqchip(kvm),
2053 &chip->chip.ioapic,
2054 sizeof(struct kvm_ioapic_state));
894a9c55 2055 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2056 break;
2057 default:
2058 r = -EINVAL;
2059 break;
2060 }
2061 kvm_pic_update_irq(pic_irqchip(kvm));
2062 return r;
2063}
2064
e0f63cb9
SY		 2065static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2066{
2067 int r = 0;
2068
894a9c55 2069 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2070 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2071 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2072 return r;
2073}
2074
2075static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2076{
2077 int r = 0;
2078
894a9c55 2079 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2080 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2081 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
894a9c55 2082 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2083 return r;
2084}
2085
52d939a0
MT		 2086static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2087 struct kvm_reinject_control *control)
2088{
2089 if (!kvm->arch.vpit)
2090 return -ENXIO;
894a9c55 2091 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2092 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2093 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2094 return 0;
2095}
2096
5bb064dc
ZX		 2097/*
2098 * Get (and clear) the dirty memory log for a memory slot.
2099 */
2100int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2101 struct kvm_dirty_log *log)
2102{
2103 int r;
2104 int n;
2105 struct kvm_memory_slot *memslot;
2106 int is_dirty = 0;
2107
72dc67a6 2108 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2109
2110 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2111 if (r)
2112 goto out;
2113
2114 /* If nothing is dirty, don't bother messing with page tables. */
2115 if (is_dirty) {
7c8a83b7 2116 spin_lock(&kvm->mmu_lock);
5bb064dc 2117 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2118 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2119 kvm_flush_remote_tlbs(kvm);
2120 memslot = &kvm->memslots[log->slot];
2121 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2122 memset(memslot->dirty_bitmap, 0, n);
2123 }
2124 r = 0;
2125out:
72dc67a6 2126 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2127 return r;
2128}
2129
1fe779f8
CO		 2130long kvm_arch_vm_ioctl(struct file *filp,
2131 unsigned int ioctl, unsigned long arg)
2132{
2133 struct kvm *kvm = filp->private_data;
2134 void __user *argp = (void __user *)arg;
2135 int r = -EINVAL;
f0d66275
DH		 2136 /*
2137 * This union makes it completely explicit to gcc-3.x
2138 * that these two variables' stack usage should be
2139 * combined, not added together.
2140 */
2141 union {
2142 struct kvm_pit_state ps;
2143 struct kvm_memory_alias alias;
c5ff41ce 2144 struct kvm_pit_config pit_config;
f0d66275 2145 } u;
1fe779f8
CO		 2146
2147 switch (ioctl) {
2148 case KVM_SET_TSS_ADDR:
2149 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2150 if (r < 0)
2151 goto out;
2152 break;
2153 case KVM_SET_MEMORY_REGION: {
2154 struct kvm_memory_region kvm_mem;
2155 struct kvm_userspace_memory_region kvm_userspace_mem;
2156
2157 r = -EFAULT;
2158 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2159 goto out;
2160 kvm_userspace_mem.slot = kvm_mem.slot;
2161 kvm_userspace_mem.flags = kvm_mem.flags;
2162 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2163 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2164 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2165 if (r)
2166 goto out;
2167 break;
2168 }
2169 case KVM_SET_NR_MMU_PAGES:
2170 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2171 if (r)
2172 goto out;
2173 break;
2174 case KVM_GET_NR_MMU_PAGES:
2175 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2176 break;
f0d66275 2177 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2178 r = -EFAULT;
f0d66275 2179 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2180 goto out;
f0d66275 2181 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2182 if (r)
2183 goto out;
2184 break;
1fe779f8
CO		 2185 case KVM_CREATE_IRQCHIP:
2186 r = -ENOMEM;
d7deeeb0
ZX		 2187 kvm->arch.vpic = kvm_create_pic(kvm);
2188 if (kvm->arch.vpic) {
1fe779f8
CO		 2189 r = kvm_ioapic_init(kvm);
2190 if (r) {
d7deeeb0
ZX		 2191 kfree(kvm->arch.vpic);
2192 kvm->arch.vpic = NULL;
1fe779f8
CO		 2193 goto out;
2194 }
2195 } else
2196 goto out;
399ec807
AK		 2197 r = kvm_setup_default_irq_routing(kvm);
2198 if (r) {
2199 kfree(kvm->arch.vpic);
2200 kfree(kvm->arch.vioapic);
2201 goto out;
2202 }
1fe779f8 2203 break;
7837699f 2204 case KVM_CREATE_PIT:
c5ff41ce
JK		 2205 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2206 goto create_pit;
2207 case KVM_CREATE_PIT2:
2208 r = -EFAULT;
2209 if (copy_from_user(&u.pit_config, argp,
2210 sizeof(struct kvm_pit_config)))
2211 goto out;
2212 create_pit:
108b5669 2213 down_write(&kvm->slots_lock);
269e05e4
AK		 2214 r = -EEXIST;
2215 if (kvm->arch.vpit)
2216 goto create_pit_unlock;
7837699f 2217 r = -ENOMEM;
c5ff41ce 2218 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2219 if (kvm->arch.vpit)
2220 r = 0;
269e05e4 2221 create_pit_unlock:
108b5669 2222 up_write(&kvm->slots_lock);
7837699f 2223 break;
4925663a 2224 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2225 case KVM_IRQ_LINE: {
2226 struct kvm_irq_level irq_event;
2227
2228 r = -EFAULT;
2229 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2230 goto out;
2231 if (irqchip_in_kernel(kvm)) {
4925663a 2232 __s32 status;
fa40a821 2233 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2234 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2235 irq_event.irq, irq_event.level);
fa40a821 2236 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2237 if (ioctl == KVM_IRQ_LINE_STATUS) {
2238 irq_event.status = status;
2239 if (copy_to_user(argp, &irq_event,
2240 sizeof irq_event))
2241 goto out;
2242 }
1fe779f8
CO		 2243 r = 0;
2244 }
2245 break;
2246 }
2247 case KVM_GET_IRQCHIP: {
2248 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2249 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2250
f0d66275
DH		 2251 r = -ENOMEM;
2252 if (!chip)
1fe779f8 2253 goto out;
f0d66275
DH		 2254 r = -EFAULT;
2255 if (copy_from_user(chip, argp, sizeof *chip))
2256 goto get_irqchip_out;
1fe779f8
CO		 2257 r = -ENXIO;
2258 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2259 goto get_irqchip_out;
2260 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2261 if (r)
f0d66275 2262 goto get_irqchip_out;
1fe779f8 2263 r = -EFAULT;
f0d66275
DH		 2264 if (copy_to_user(argp, chip, sizeof *chip))
2265 goto get_irqchip_out;
1fe779f8 2266 r = 0;
f0d66275
DH		 2267 get_irqchip_out:
2268 kfree(chip);
2269 if (r)
2270 goto out;
1fe779f8
CO		 2271 break;
2272 }
2273 case KVM_SET_IRQCHIP: {
2274 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2275 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2276
f0d66275
DH		 2277 r = -ENOMEM;
2278 if (!chip)
1fe779f8 2279 goto out;
f0d66275
DH		 2280 r = -EFAULT;
2281 if (copy_from_user(chip, argp, sizeof *chip))
2282 goto set_irqchip_out;
1fe779f8
CO		 2283 r = -ENXIO;
2284 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2285 goto set_irqchip_out;
2286 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2287 if (r)
f0d66275 2288 goto set_irqchip_out;
1fe779f8 2289 r = 0;
f0d66275
DH		 2290 set_irqchip_out:
2291 kfree(chip);
2292 if (r)
2293 goto out;
1fe779f8
CO		 2294 break;
2295 }
e0f63cb9 2296 case KVM_GET_PIT: {
e0f63cb9 2297 r = -EFAULT;
f0d66275 2298 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2299 goto out;
2300 r = -ENXIO;
2301 if (!kvm->arch.vpit)
2302 goto out;
f0d66275 2303 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2304 if (r)
2305 goto out;
2306 r = -EFAULT;
f0d66275 2307 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2308 goto out;
2309 r = 0;
2310 break;
2311 }
2312 case KVM_SET_PIT: {
e0f63cb9 2313 r = -EFAULT;
f0d66275 2314 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2315 goto out;
2316 r = -ENXIO;
2317 if (!kvm->arch.vpit)
2318 goto out;
f0d66275 2319 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2320 if (r)
2321 goto out;
2322 r = 0;
2323 break;
2324 }
52d939a0
MT		 2325 case KVM_REINJECT_CONTROL: {
2326 struct kvm_reinject_control control;
2327 r = -EFAULT;
2328 if (copy_from_user(&control, argp, sizeof(control)))
2329 goto out;
2330 r = kvm_vm_ioctl_reinject(kvm, &control);
2331 if (r)
2332 goto out;
2333 r = 0;
2334 break;
2335 }
1fe779f8
CO		 2336 default:
2337 ;
2338 }
2339out:
2340 return r;
2341}
2342
a16b043c 2343static void kvm_init_msr_list(void)
043405e1
CO		 2344{
2345 u32 dummy[2];
2346 unsigned i, j;
2347
2348 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2349 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2350 continue;
2351 if (j < i)
2352 msrs_to_save[j] = msrs_to_save[i];
2353 j++;
2354 }
2355 num_msrs_to_save = j;
2356}
2357
bda9020e
MT		 2358static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2359 const void *v)
bbd9b64e 2360{
bda9020e
MT		 2361 if (vcpu->arch.apic &&
2362 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2363 return 0;
bbd9b64e 2364
bda9020e 2365 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2366}
2367
bda9020e 2368static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2369{
bda9020e
MT		 2370 if (vcpu->arch.apic &&
2371 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2372 return 0;
bbd9b64e 2373
bda9020e 2374 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2375}
2376
cded19f3
HE		 2377static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2378 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2379{
2380 void *data = val;
10589a46 2381 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2382
2383 while (bytes) {
ad312c7c 2384 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2385 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2386 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2387 int ret;
2388
10589a46
MT		 2389 if (gpa == UNMAPPED_GVA) {
2390 r = X86EMUL_PROPAGATE_FAULT;
2391 goto out;
2392 }
77c2002e 2393 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2394 if (ret < 0) {
2395 r = X86EMUL_UNHANDLEABLE;
2396 goto out;
2397 }
bbd9b64e 2398
77c2002e
IE		 2399 bytes -= toread;
2400 data += toread;
2401 addr += toread;
bbd9b64e 2402 }
10589a46 2403out:
10589a46 2404 return r;
bbd9b64e 2405}
77c2002e 2406
cded19f3
HE		 2407static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2408 struct kvm_vcpu *vcpu)
77c2002e
IE		 2409{
2410 void *data = val;
2411 int r = X86EMUL_CONTINUE;
2412
2413 while (bytes) {
2414 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2415 unsigned offset = addr & (PAGE_SIZE-1);
2416 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2417 int ret;
2418
2419 if (gpa == UNMAPPED_GVA) {
2420 r = X86EMUL_PROPAGATE_FAULT;
2421 goto out;
2422 }
2423 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2424 if (ret < 0) {
2425 r = X86EMUL_UNHANDLEABLE;
2426 goto out;
2427 }
2428
2429 bytes -= towrite;
2430 data += towrite;
2431 addr += towrite;
2432 }
2433out:
2434 return r;
2435}
2436
bbd9b64e 2437
bbd9b64e
CO		 2438static int emulator_read_emulated(unsigned long addr,
2439 void *val,
2440 unsigned int bytes,
2441 struct kvm_vcpu *vcpu)
2442{
bbd9b64e
CO		 2443 gpa_t gpa;
2444
2445 if (vcpu->mmio_read_completed) {
2446 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2447 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2448 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2449 vcpu->mmio_read_completed = 0;
2450 return X86EMUL_CONTINUE;
2451 }
2452
ad312c7c 2453 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2454
2455 /* For APIC access vmexit */
2456 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2457 goto mmio;
2458
77c2002e
IE		 2459 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2460 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2461 return X86EMUL_CONTINUE;
2462 if (gpa == UNMAPPED_GVA)
2463 return X86EMUL_PROPAGATE_FAULT;
2464
2465mmio:
2466 /*
2467 * Is this MMIO handled locally?
2468 */
aec51dc4
AK		 2469 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2470 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2471 return X86EMUL_CONTINUE;
aec51dc4
AK		 2472 }
2473
2474 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2475
2476 vcpu->mmio_needed = 1;
2477 vcpu->mmio_phys_addr = gpa;
2478 vcpu->mmio_size = bytes;
2479 vcpu->mmio_is_write = 0;
2480
2481 return X86EMUL_UNHANDLEABLE;
2482}
2483
3200f405 2484int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2485 const void *val, int bytes)
bbd9b64e
CO		 2486{
2487 int ret;
2488
2489 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2490 if (ret < 0)
bbd9b64e 2491 return 0;
ad218f85 2492 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2493 return 1;
2494}
2495
2496static int emulator_write_emulated_onepage(unsigned long addr,
2497 const void *val,
2498 unsigned int bytes,
2499 struct kvm_vcpu *vcpu)
2500{
10589a46
MT		 2501 gpa_t gpa;
2502
10589a46 2503 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2504
2505 if (gpa == UNMAPPED_GVA) {
c3c91fee 2506 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2507 return X86EMUL_PROPAGATE_FAULT;
2508 }
2509
2510 /* For APIC access vmexit */
2511 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2512 goto mmio;
2513
2514 if (emulator_write_phys(vcpu, gpa, val, bytes))
2515 return X86EMUL_CONTINUE;
2516
2517mmio:
aec51dc4 2518 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2519 /*
2520 * Is this MMIO handled locally?
2521 */
bda9020e 2522 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2523 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2524
2525 vcpu->mmio_needed = 1;
2526 vcpu->mmio_phys_addr = gpa;
2527 vcpu->mmio_size = bytes;
2528 vcpu->mmio_is_write = 1;
2529 memcpy(vcpu->mmio_data, val, bytes);
2530
2531 return X86EMUL_CONTINUE;
2532}
2533
2534int emulator_write_emulated(unsigned long addr,
2535 const void *val,
2536 unsigned int bytes,
2537 struct kvm_vcpu *vcpu)
2538{
2539 /* Crossing a page boundary? */
2540 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2541 int rc, now;
2542
2543 now = -addr & ~PAGE_MASK;
2544 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2545 if (rc != X86EMUL_CONTINUE)
2546 return rc;
2547 addr += now;
2548 val += now;
2549 bytes -= now;
2550 }
2551 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2552}
2553EXPORT_SYMBOL_GPL(emulator_write_emulated);
2554
2555static int emulator_cmpxchg_emulated(unsigned long addr,
2556 const void *old,
2557 const void *new,
2558 unsigned int bytes,
2559 struct kvm_vcpu *vcpu)
2560{
2561 static int reported;
2562
2563 if (!reported) {
2564 reported = 1;
2565 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2566 }
2bacc55c
MT		 2567#ifndef CONFIG_X86_64
2568 /* guests cmpxchg8b have to be emulated atomically */
2569 if (bytes == 8) {
10589a46 2570 gpa_t gpa;
2bacc55c 2571 struct page *page;
c0b49b0d 2572 char *kaddr;
2bacc55c
MT		 2573 u64 val;
2574
10589a46
MT		 2575 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2576
2bacc55c
MT		 2577 if (gpa == UNMAPPED_GVA ||
2578 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2579 goto emul_write;
2580
2581 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2582 goto emul_write;
2583
2584 val = *(u64 *)new;
72dc67a6 2585
2bacc55c 2586 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2587
c0b49b0d
AM		 2588 kaddr = kmap_atomic(page, KM_USER0);
2589 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2590 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2591 kvm_release_page_dirty(page);
2592 }
3200f405 2593emul_write:
2bacc55c
MT		 2594#endif
2595
bbd9b64e
CO		 2596 return emulator_write_emulated(addr, new, bytes, vcpu);
2597}
2598
2599static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2600{
2601 return kvm_x86_ops->get_segment_base(vcpu, seg);
2602}
2603
2604int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2605{
a7052897 2606 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2607 return X86EMUL_CONTINUE;
2608}
2609
2610int emulate_clts(struct kvm_vcpu *vcpu)
2611{
ad312c7c 2612 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2613 return X86EMUL_CONTINUE;
2614}
2615
2616int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2617{
2618 struct kvm_vcpu *vcpu = ctxt->vcpu;
2619
2620 switch (dr) {
2621 case 0 ... 3:
2622 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2623 return X86EMUL_CONTINUE;
2624 default:
b8688d51 2625 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2626 return X86EMUL_UNHANDLEABLE;
2627 }
2628}
2629
2630int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2631{
2632 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2633 int exception;
2634
2635 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2636 if (exception) {
2637 /* FIXME: better handling */
2638 return X86EMUL_UNHANDLEABLE;
2639 }
2640 return X86EMUL_CONTINUE;
2641}
2642
2643void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2644{
bbd9b64e 2645 u8 opcodes[4];
5fdbf976 2646 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2647 unsigned long rip_linear;
2648
f76c710d 2649 if (!printk_ratelimit())
bbd9b64e
CO		 2650 return;
2651
25be4608
GC		 2652 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2653
77c2002e 2654 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2655
2656 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2657 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2658}
2659EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2660
14af3f3c 2661static struct x86_emulate_ops emulate_ops = {
77c2002e 2662 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2663 .read_emulated = emulator_read_emulated,
2664 .write_emulated = emulator_write_emulated,
2665 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2666};
2667
5fdbf976
MT		 2668static void cache_all_regs(struct kvm_vcpu *vcpu)
2669{
2670 kvm_register_read(vcpu, VCPU_REGS_RAX);
2671 kvm_register_read(vcpu, VCPU_REGS_RSP);
2672 kvm_register_read(vcpu, VCPU_REGS_RIP);
2673 vcpu->arch.regs_dirty = ~0;
2674}
2675
bbd9b64e
CO		 2676int emulate_instruction(struct kvm_vcpu *vcpu,
2677 struct kvm_run *run,
2678 unsigned long cr2,
2679 u16 error_code,
571008da 2680 int emulation_type)
bbd9b64e 2681{
310b5d30 2682 int r, shadow_mask;
571008da 2683 struct decode_cache *c;
bbd9b64e 2684
26eef70c 2685 kvm_clear_exception_queue(vcpu);
ad312c7c 2686 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2687 /*
2688 * TODO: fix x86_emulate.c to use guest_read/write_register
2689 * instead of direct ->regs accesses, can save hundred cycles
2690 * on Intel for instructions that don't read/change RSP, for
2691 * for example.
2692 */
2693 cache_all_regs(vcpu);
bbd9b64e
CO		 2694
2695 vcpu->mmio_is_write = 0;
ad312c7c 2696 vcpu->arch.pio.string = 0;
bbd9b64e 2697
571008da 2698 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2699 int cs_db, cs_l;
2700 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2701
ad312c7c
ZX		 2702 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2703 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2704 vcpu->arch.emulate_ctxt.mode =
2705 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2706 ? X86EMUL_MODE_REAL : cs_l
2707 ? X86EMUL_MODE_PROT64 : cs_db
2708 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2709
ad312c7c 2710 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2711
0cb5762e
AP		 2712 /* Only allow emulation of specific instructions on #UD
2713 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2714 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2715 if (emulation_type & EMULTYPE_TRAP_UD) {
2716 if (!c->twobyte)
2717 return EMULATE_FAIL;
2718 switch (c->b) {
2719 case 0x01: /* VMMCALL */
2720 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2721 return EMULATE_FAIL;
2722 break;
2723 case 0x34: /* sysenter */
2724 case 0x35: /* sysexit */
2725 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2726 return EMULATE_FAIL;
2727 break;
2728 case 0x05: /* syscall */
2729 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2730 return EMULATE_FAIL;
2731 break;
2732 default:
2733 return EMULATE_FAIL;
2734 }
2735
2736 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2737 return EMULATE_FAIL;
2738 }
571008da 2739
f2b5756b 2740 ++vcpu->stat.insn_emulation;
bbd9b64e 2741 if (r) {
f2b5756b 2742 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2743 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2744 return EMULATE_DONE;
2745 return EMULATE_FAIL;
2746 }
2747 }
2748
ba8afb6b
GN		 2749 if (emulation_type & EMULTYPE_SKIP) {
2750 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2751 return EMULATE_DONE;
2752 }
2753
ad312c7c 2754 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2755 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2756
2757 if (r == 0)
2758 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2759
ad312c7c 2760 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2761 return EMULATE_DO_MMIO;
2762
2763 if ((r || vcpu->mmio_is_write) && run) {
2764 run->exit_reason = KVM_EXIT_MMIO;
2765 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2766 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2767 run->mmio.len = vcpu->mmio_size;
2768 run->mmio.is_write = vcpu->mmio_is_write;
2769 }
2770
2771 if (r) {
2772 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2773 return EMULATE_DONE;
2774 if (!vcpu->mmio_needed) {
2775 kvm_report_emulation_failure(vcpu, "mmio");
2776 return EMULATE_FAIL;
2777 }
2778 return EMULATE_DO_MMIO;
2779 }
2780
ad312c7c 2781 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2782
2783 if (vcpu->mmio_is_write) {
2784 vcpu->mmio_needed = 0;
2785 return EMULATE_DO_MMIO;
2786 }
2787
2788 return EMULATE_DONE;
2789}
2790EXPORT_SYMBOL_GPL(emulate_instruction);
2791
de7d789a
CO		 2792static int pio_copy_data(struct kvm_vcpu *vcpu)
2793{
ad312c7c 2794 void *p = vcpu->arch.pio_data;
0f346074 2795 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2796 unsigned bytes;
0f346074 2797 int ret;
de7d789a 2798
ad312c7c
ZX		 2799 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2800 if (vcpu->arch.pio.in)
0f346074 2801 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2802 else
0f346074
IE		 2803 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2804 return ret;
de7d789a
CO		 2805}
2806
2807int complete_pio(struct kvm_vcpu *vcpu)
2808{
ad312c7c 2809 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2810 long delta;
2811 int r;
5fdbf976 2812 unsigned long val;
de7d789a
CO		 2813
2814 if (!io->string) {
5fdbf976
MT		 2815 if (io->in) {
2816 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2817 memcpy(&val, vcpu->arch.pio_data, io->size);
2818 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2819 }
de7d789a
CO		 2820 } else {
2821 if (io->in) {
2822 r = pio_copy_data(vcpu);
5fdbf976 2823 if (r)
de7d789a 2824 return r;
de7d789a
CO		 2825 }
2826
2827 delta = 1;
2828 if (io->rep) {
2829 delta *= io->cur_count;
2830 /*
2831 * The size of the register should really depend on
2832 * current address size.
2833 */
5fdbf976
MT		 2834 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2835 val -= delta;
2836 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2837 }
2838 if (io->down)
2839 delta = -delta;
2840 delta *= io->size;
5fdbf976
MT		 2841 if (io->in) {
2842 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2843 val += delta;
2844 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2845 } else {
2846 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2847 val += delta;
2848 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2849 }
de7d789a
CO		 2850 }
2851
de7d789a
CO		 2852 io->count -= io->cur_count;
2853 io->cur_count = 0;
2854
2855 return 0;
2856}
2857
bda9020e 2858static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2859{
2860 /* TODO: String I/O for in kernel device */
bda9020e 2861 int r;
de7d789a 2862
ad312c7c 2863 if (vcpu->arch.pio.in)
bda9020e
MT		 2864 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2865 vcpu->arch.pio.size, pd);
de7d789a 2866 else
bda9020e
MT		 2867 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2868 vcpu->arch.pio.size, pd);
2869 return r;
de7d789a
CO		 2870}
2871
bda9020e 2872static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2873{
ad312c7c
ZX		 2874 struct kvm_pio_request *io = &vcpu->arch.pio;
2875 void *pd = vcpu->arch.pio_data;
bda9020e 2876 int i, r = 0;
de7d789a 2877
de7d789a 2878 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2879 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2880 io->port, io->size, pd)) {
2881 r = -EOPNOTSUPP;
2882 break;
2883 }
de7d789a
CO		 2884 pd += io->size;
2885 }
bda9020e 2886 return r;
de7d789a
CO		 2887}
2888
2889int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2890 int size, unsigned port)
2891{
5fdbf976 2892 unsigned long val;
de7d789a
CO		 2893
2894 vcpu->run->exit_reason = KVM_EXIT_IO;
2895 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2896 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2897 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2898 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2899 vcpu->run->io.port = vcpu->arch.pio.port = port;
2900 vcpu->arch.pio.in = in;
2901 vcpu->arch.pio.string = 0;
2902 vcpu->arch.pio.down = 0;
ad312c7c 2903 vcpu->arch.pio.rep = 0;
de7d789a 2904
229456fc
MT		 2905 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2906 size, 1);
2714d1d3 2907
5fdbf976
MT		 2908 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2909 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2910
bda9020e 2911 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2912 complete_pio(vcpu);
2913 return 1;
2914 }
2915 return 0;
2916}
2917EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2918
2919int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2920 int size, unsigned long count, int down,
2921 gva_t address, int rep, unsigned port)
2922{
2923 unsigned now, in_page;
0f346074 2924 int ret = 0;
de7d789a
CO		 2925
2926 vcpu->run->exit_reason = KVM_EXIT_IO;
2927 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2928 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2929 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2930 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2931 vcpu->run->io.port = vcpu->arch.pio.port = port;
2932 vcpu->arch.pio.in = in;
2933 vcpu->arch.pio.string = 1;
2934 vcpu->arch.pio.down = down;
ad312c7c 2935 vcpu->arch.pio.rep = rep;
de7d789a 2936
229456fc
MT		 2937 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2938 size, count);
2714d1d3 2939
de7d789a
CO		 2940 if (!count) {
2941 kvm_x86_ops->skip_emulated_instruction(vcpu);
2942 return 1;
2943 }
2944
2945 if (!down)
2946 in_page = PAGE_SIZE - offset_in_page(address);
2947 else
2948 in_page = offset_in_page(address) + size;
2949 now = min(count, (unsigned long)in_page / size);
0f346074 2950 if (!now)
de7d789a 2951 now = 1;
de7d789a
CO		 2952 if (down) {
2953 /*
2954 * String I/O in reverse. Yuck. Kill the guest, fix later.
2955 */
2956 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2957 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2958 return 1;
2959 }
2960 vcpu->run->io.count = now;
ad312c7c 2961 vcpu->arch.pio.cur_count = now;
de7d789a 2962
ad312c7c 2963 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2964 kvm_x86_ops->skip_emulated_instruction(vcpu);
2965
0f346074 2966 vcpu->arch.pio.guest_gva = address;
de7d789a 2967
ad312c7c 2968 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2969 /* string PIO write */
2970 ret = pio_copy_data(vcpu);
0f346074
IE		 2971 if (ret == X86EMUL_PROPAGATE_FAULT) {
2972 kvm_inject_gp(vcpu, 0);
2973 return 1;
2974 }
bda9020e 2975 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 2976 complete_pio(vcpu);
ad312c7c 2977 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2978 ret = 1;
2979 }
bda9020e
MT		 2980 }
2981 /* no string PIO read support yet */
de7d789a
CO		 2982
2983 return ret;
2984}
2985EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2986
c8076604
GH		 2987static void bounce_off(void *info)
2988{
2989 /* nothing */
2990}
2991
2992static unsigned int ref_freq;
2993static unsigned long tsc_khz_ref;
2994
2995static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2996 void *data)
2997{
2998 struct cpufreq_freqs *freq = data;
2999 struct kvm *kvm;
3000 struct kvm_vcpu *vcpu;
3001 int i, send_ipi = 0;
3002
3003 if (!ref_freq)
3004 ref_freq = freq->old;
3005
3006 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3007 return 0;
3008 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3009 return 0;
3010 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3011
3012 spin_lock(&kvm_lock);
3013 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3014 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3015 if (vcpu->cpu != freq->cpu)
3016 continue;
3017 if (!kvm_request_guest_time_update(vcpu))
3018 continue;
3019 if (vcpu->cpu != smp_processor_id())
3020 send_ipi++;
3021 }
3022 }
3023 spin_unlock(&kvm_lock);
3024
3025 if (freq->old < freq->new && send_ipi) {
3026 /*
3027 * We upscale the frequency. Must make the guest
3028 * doesn't see old kvmclock values while running with
3029 * the new frequency, otherwise we risk the guest sees
3030 * time go backwards.
3031 *
3032 * In case we update the frequency for another cpu
3033 * (which might be in guest context) send an interrupt
3034 * to kick the cpu out of guest context. Next time
3035 * guest context is entered kvmclock will be updated,
3036 * so the guest will not see stale values.
3037 */
3038 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3039 }
3040 return 0;
3041}
3042
3043static struct notifier_block kvmclock_cpufreq_notifier_block = {
3044 .notifier_call = kvmclock_cpufreq_notifier
3045};
3046
f8c16bba 3047int kvm_arch_init(void *opaque)
043405e1 3048{
c8076604 3049 int r, cpu;
f8c16bba
ZX		 3050 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3051
f8c16bba
ZX		 3052 if (kvm_x86_ops) {
3053 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3054 r = -EEXIST;
3055 goto out;
f8c16bba
ZX		 3056 }
3057
3058 if (!ops->cpu_has_kvm_support()) {
3059 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3060 r = -EOPNOTSUPP;
3061 goto out;
f8c16bba
ZX		 3062 }
3063 if (ops->disabled_by_bios()) {
3064 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3065 r = -EOPNOTSUPP;
3066 goto out;
f8c16bba
ZX		 3067 }
3068
97db56ce
AK		 3069 r = kvm_mmu_module_init();
3070 if (r)
3071 goto out;
3072
3073 kvm_init_msr_list();
3074
f8c16bba 3075 kvm_x86_ops = ops;
56c6d28a 3076 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3077 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3078 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3079 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3080
3081 for_each_possible_cpu(cpu)
3082 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3083 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3084 tsc_khz_ref = tsc_khz;
3085 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3086 CPUFREQ_TRANSITION_NOTIFIER);
3087 }
3088
f8c16bba 3089 return 0;
56c6d28a
ZX		 3090
3091out:
56c6d28a 3092 return r;
043405e1 3093}
8776e519 3094
f8c16bba
ZX		 3095void kvm_arch_exit(void)
3096{
888d256e
JK		 3097 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3098 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3099 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3100 kvm_x86_ops = NULL;
56c6d28a
ZX		 3101 kvm_mmu_module_exit();
3102}
f8c16bba 3103
8776e519
HB		 3104int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3105{
3106 ++vcpu->stat.halt_exits;
3107 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3108 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3109 return 1;
3110 } else {
3111 vcpu->run->exit_reason = KVM_EXIT_HLT;
3112 return 0;
3113 }
3114}
3115EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3116
2f333bcb
MT		 3117static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3118 unsigned long a1)
3119{
3120 if (is_long_mode(vcpu))
3121 return a0;
3122 else
3123 return a0 | ((gpa_t)a1 << 32);
3124}
3125
8776e519
HB		 3126int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3127{
3128 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3129 int r = 1;
8776e519 3130
5fdbf976
MT		 3131 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3132 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3133 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3134 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3135 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3136
229456fc 3137 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3138
8776e519
HB		 3139 if (!is_long_mode(vcpu)) {
3140 nr &= 0xFFFFFFFF;
3141 a0 &= 0xFFFFFFFF;
3142 a1 &= 0xFFFFFFFF;
3143 a2 &= 0xFFFFFFFF;
3144 a3 &= 0xFFFFFFFF;
3145 }
3146
3147 switch (nr) {
b93463aa
AK		 3148 case KVM_HC_VAPIC_POLL_IRQ:
3149 ret = 0;
3150 break;
2f333bcb
MT		 3151 case KVM_HC_MMU_OP:
3152 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3153 break;
8776e519
HB		 3154 default:
3155 ret = -KVM_ENOSYS;
3156 break;
3157 }
5fdbf976 3158 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3159 ++vcpu->stat.hypercalls;
2f333bcb 3160 return r;
8776e519
HB		 3161}
3162EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3163
3164int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3165{
3166 char instruction[3];
3167 int ret = 0;
5fdbf976 3168 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3169
8776e519
HB		 3170
3171 /*
3172 * Blow out the MMU to ensure that no other VCPU has an active mapping
3173 * to ensure that the updated hypercall appears atomically across all
3174 * VCPUs.
3175 */
3176 kvm_mmu_zap_all(vcpu->kvm);
3177
8776e519 3178 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3179 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3180 != X86EMUL_CONTINUE)
3181 ret = -EFAULT;
3182
8776e519
HB		 3183 return ret;
3184}
3185
3186static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3187{
3188 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3189}
3190
3191void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3192{
3193 struct descriptor_table dt = { limit, base };
3194
3195 kvm_x86_ops->set_gdt(vcpu, &dt);
3196}
3197
3198void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3199{
3200 struct descriptor_table dt = { limit, base };
3201
3202 kvm_x86_ops->set_idt(vcpu, &dt);
3203}
3204
3205void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3206 unsigned long *rflags)
3207{
2d3ad1f4 3208 kvm_lmsw(vcpu, msw);
8776e519
HB		 3209 *rflags = kvm_x86_ops->get_rflags(vcpu);
3210}
3211
3212unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3213{
54e445ca
JR		 3214 unsigned long value;
3215
8776e519
HB		 3216 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3217 switch (cr) {
3218 case 0:
54e445ca
JR		 3219 value = vcpu->arch.cr0;
3220 break;
8776e519 3221 case 2:
54e445ca
JR		 3222 value = vcpu->arch.cr2;
3223 break;
8776e519 3224 case 3:
54e445ca
JR		 3225 value = vcpu->arch.cr3;
3226 break;
8776e519 3227 case 4:
54e445ca
JR		 3228 value = vcpu->arch.cr4;
3229 break;
152ff9be 3230 case 8:
54e445ca
JR		 3231 value = kvm_get_cr8(vcpu);
3232 break;
8776e519 3233 default:
b8688d51 3234 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3235 return 0;
3236 }
54e445ca
JR		 3237
3238 return value;
8776e519
HB		 3239}
3240
3241void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3242 unsigned long *rflags)
3243{
3244 switch (cr) {
3245 case 0:
2d3ad1f4 3246 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3247 *rflags = kvm_x86_ops->get_rflags(vcpu);
3248 break;
3249 case 2:
ad312c7c 3250 vcpu->arch.cr2 = val;
8776e519
HB		 3251 break;
3252 case 3:
2d3ad1f4 3253 kvm_set_cr3(vcpu, val);
8776e519
HB		 3254 break;
3255 case 4:
2d3ad1f4 3256 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3257 break;
152ff9be 3258 case 8:
2d3ad1f4 3259 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3260 break;
8776e519 3261 default:
b8688d51 3262 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3263 }
3264}
3265
07716717
DK		 3266static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3267{
ad312c7c
ZX		 3268 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3269 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3270
3271 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3272 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3273 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3274 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3275 if (ej->function == e->function) {
3276 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3277 return j;
3278 }
3279 }
3280 return 0; /* silence gcc, even though control never reaches here */
3281}
3282
3283/* find an entry with matching function, matching index (if needed), and that
3284 * should be read next (if it's stateful) */
3285static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3286 u32 function, u32 index)
3287{
3288 if (e->function != function)
3289 return 0;
3290 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3291 return 0;
3292 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3293 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3294 return 0;
3295 return 1;
3296}
3297
d8017474
AG		 3298struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3299 u32 function, u32 index)
8776e519
HB		 3300{
3301 int i;
d8017474 3302 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3303
ad312c7c 3304 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3305 struct kvm_cpuid_entry2 *e;
3306
ad312c7c 3307 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3308 if (is_matching_cpuid_entry(e, function, index)) {
3309 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3310 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3311 best = e;
3312 break;
3313 }
3314 /*
3315 * Both basic or both extended?
3316 */
3317 if (((e->function ^ function) & 0x80000000) == 0)
3318 if (!best || e->function > best->function)
3319 best = e;
3320 }
d8017474
AG		 3321 return best;
3322}
3323
82725b20
DE		 3324int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3325{
3326 struct kvm_cpuid_entry2 *best;
3327
3328 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3329 if (best)
3330 return best->eax & 0xff;
3331 return 36;
3332}
3333
d8017474
AG		 3334void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3335{
3336 u32 function, index;
3337 struct kvm_cpuid_entry2 *best;
3338
3339 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3340 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3341 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3342 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3343 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3344 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3345 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3346 if (best) {
5fdbf976
MT		 3347 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3348 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3349 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3350 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3351 }
8776e519 3352 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3353 trace_kvm_cpuid(function,
3354 kvm_register_read(vcpu, VCPU_REGS_RAX),
3355 kvm_register_read(vcpu, VCPU_REGS_RBX),
3356 kvm_register_read(vcpu, VCPU_REGS_RCX),
3357 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3358}
3359EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3360
b6c7a5dc
HB		 3361/*
3362 * Check if userspace requested an interrupt window, and that the
3363 * interrupt window is open.
3364 *
3365 * No need to exit to userspace if we already have an interrupt queued.
3366 */
3367static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3368 struct kvm_run *kvm_run)
3369{
8061823a 3370 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3371 kvm_run->request_interrupt_window &&
5df56646 3372 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3373}
3374
3375static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3376 struct kvm_run *kvm_run)
3377{
3378 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3379 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3380 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3381 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3382 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3383 else
b6c7a5dc 3384 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3385 kvm_arch_interrupt_allowed(vcpu) &&
3386 !kvm_cpu_has_interrupt(vcpu) &&
3387 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3388}
3389
b93463aa
AK		 3390static void vapic_enter(struct kvm_vcpu *vcpu)
3391{
3392 struct kvm_lapic *apic = vcpu->arch.apic;
3393 struct page *page;
3394
3395 if (!apic || !apic->vapic_addr)
3396 return;
3397
3398 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3399
3400 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3401}
3402
3403static void vapic_exit(struct kvm_vcpu *vcpu)
3404{
3405 struct kvm_lapic *apic = vcpu->arch.apic;
3406
3407 if (!apic || !apic->vapic_addr)
3408 return;
3409
f8b78fa3 3410 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3411 kvm_release_page_dirty(apic->vapic_page);
3412 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3413 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3414}
3415
95ba8273
GN		 3416static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3417{
3418 int max_irr, tpr;
3419
3420 if (!kvm_x86_ops->update_cr8_intercept)
3421 return;
3422
8db3baa2
GN		 3423 if (!vcpu->arch.apic->vapic_addr)
3424 max_irr = kvm_lapic_find_highest_irr(vcpu);
3425 else
3426 max_irr = -1;
95ba8273
GN		 3427
3428 if (max_irr != -1)
3429 max_irr >>= 4;
3430
3431 tpr = kvm_lapic_get_cr8(vcpu);
3432
3433 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3434}
3435
6a8b1d13 3436static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3437{
3438 /* try to reinject previous events if any */
3439 if (vcpu->arch.nmi_injected) {
3440 kvm_x86_ops->set_nmi(vcpu);
3441 return;
3442 }
3443
3444 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3445 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3446 return;
3447 }
3448
3449 /* try to inject new event if pending */
3450 if (vcpu->arch.nmi_pending) {
3451 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3452 vcpu->arch.nmi_pending = false;
3453 vcpu->arch.nmi_injected = true;
3454 kvm_x86_ops->set_nmi(vcpu);
3455 }
3456 } else if (kvm_cpu_has_interrupt(vcpu)) {
3457 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3458 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3459 false);
3460 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3461 }
3462 }
3463}
3464
d7690175 3465static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3466{
3467 int r;
6a8b1d13
GN		 3468 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3469 kvm_run->request_interrupt_window;
b6c7a5dc 3470
2e53d63a
MT		 3471 if (vcpu->requests)
3472 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3473 kvm_mmu_unload(vcpu);
3474
b6c7a5dc
HB		 3475 r = kvm_mmu_reload(vcpu);
3476 if (unlikely(r))
3477 goto out;
3478
2f52d58c
AK		 3479 if (vcpu->requests) {
3480 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3481 __kvm_migrate_timers(vcpu);
c8076604
GH		 3482 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3483 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3484 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3485 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3486 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3487 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3488 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3489 &vcpu->requests)) {
3490 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3491 r = 0;
3492 goto out;
3493 }
71c4dfaf
JR		 3494 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3495 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3496 r = 0;
3497 goto out;
3498 }
2f52d58c 3499 }
b93463aa 3500
b6c7a5dc
HB		 3501 preempt_disable();
3502
3503 kvm_x86_ops->prepare_guest_switch(vcpu);
3504 kvm_load_guest_fpu(vcpu);
3505
3506 local_irq_disable();
3507
32f88400
MT		 3508 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3509 smp_mb__after_clear_bit();
3510
d7690175 3511 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3512 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3513 local_irq_enable();
3514 preempt_enable();
3515 r = 1;
3516 goto out;
3517 }
3518
ad312c7c 3519 if (vcpu->arch.exception.pending)
298101da 3520 __queue_exception(vcpu);
eb9774f0 3521 else
95ba8273 3522 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3523
6a8b1d13
GN		 3524 /* enable NMI/IRQ window open exits if needed */
3525 if (vcpu->arch.nmi_pending)
3526 kvm_x86_ops->enable_nmi_window(vcpu);
3527 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3528 kvm_x86_ops->enable_irq_window(vcpu);
3529
95ba8273 3530 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3531 update_cr8_intercept(vcpu);
3532 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3533 }
b93463aa 3534
3200f405
MT		 3535 up_read(&vcpu->kvm->slots_lock);
3536
b6c7a5dc
HB		 3537 kvm_guest_enter();
3538
42dbaa5a
JK		 3539 get_debugreg(vcpu->arch.host_dr6, 6);
3540 get_debugreg(vcpu->arch.host_dr7, 7);
3541 if (unlikely(vcpu->arch.switch_db_regs)) {
3542 get_debugreg(vcpu->arch.host_db[0], 0);
3543 get_debugreg(vcpu->arch.host_db[1], 1);
3544 get_debugreg(vcpu->arch.host_db[2], 2);
3545 get_debugreg(vcpu->arch.host_db[3], 3);
3546
3547 set_debugreg(0, 7);
3548 set_debugreg(vcpu->arch.eff_db[0], 0);
3549 set_debugreg(vcpu->arch.eff_db[1], 1);
3550 set_debugreg(vcpu->arch.eff_db[2], 2);
3551 set_debugreg(vcpu->arch.eff_db[3], 3);
3552 }
b6c7a5dc 3553
229456fc 3554 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3555 kvm_x86_ops->run(vcpu, kvm_run);
3556
42dbaa5a
JK		 3557 if (unlikely(vcpu->arch.switch_db_regs)) {
3558 set_debugreg(0, 7);
3559 set_debugreg(vcpu->arch.host_db[0], 0);
3560 set_debugreg(vcpu->arch.host_db[1], 1);
3561 set_debugreg(vcpu->arch.host_db[2], 2);
3562 set_debugreg(vcpu->arch.host_db[3], 3);
3563 }
3564 set_debugreg(vcpu->arch.host_dr6, 6);
3565 set_debugreg(vcpu->arch.host_dr7, 7);
3566
32f88400 3567 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3568 local_irq_enable();
3569
3570 ++vcpu->stat.exits;
3571
3572 /*
3573 * We must have an instruction between local_irq_enable() and
3574 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3575 * the interrupt shadow. The stat.exits increment will do nicely.
3576 * But we need to prevent reordering, hence this barrier():
3577 */
3578 barrier();
3579
3580 kvm_guest_exit();
3581
3582 preempt_enable();
3583
3200f405
MT		 3584 down_read(&vcpu->kvm->slots_lock);
3585
b6c7a5dc
HB		 3586 /*
3587 * Profile KVM exit RIPs:
3588 */
3589 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3590 unsigned long rip = kvm_rip_read(vcpu);
3591 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3592 }
3593
298101da 3594
b93463aa
AK		 3595 kvm_lapic_sync_from_vapic(vcpu);
3596
b6c7a5dc 3597 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3598out:
3599 return r;
3600}
b6c7a5dc 3601
09cec754 3602
d7690175
MT		 3603static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3604{
3605 int r;
3606
3607 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3608 pr_debug("vcpu %d received sipi with vector # %x\n",
3609 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3610 kvm_lapic_reset(vcpu);
5f179287 3611 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3612 if (r)
3613 return r;
3614 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3615 }
3616
d7690175
MT		 3617 down_read(&vcpu->kvm->slots_lock);
3618 vapic_enter(vcpu);
3619
3620 r = 1;
3621 while (r > 0) {
af2152f5 3622 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3623 r = vcpu_enter_guest(vcpu, kvm_run);
3624 else {
3625 up_read(&vcpu->kvm->slots_lock);
3626 kvm_vcpu_block(vcpu);
3627 down_read(&vcpu->kvm->slots_lock);
3628 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3629 {
3630 switch(vcpu->arch.mp_state) {
3631 case KVM_MP_STATE_HALTED:
d7690175 3632 vcpu->arch.mp_state =
09cec754
GN		 3633 KVM_MP_STATE_RUNNABLE;
3634 case KVM_MP_STATE_RUNNABLE:
3635 break;
3636 case KVM_MP_STATE_SIPI_RECEIVED:
3637 default:
3638 r = -EINTR;
3639 break;
3640 }
3641 }
d7690175
MT		 3642 }
3643
09cec754
GN		 3644 if (r <= 0)
3645 break;
3646
3647 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3648 if (kvm_cpu_has_pending_timer(vcpu))
3649 kvm_inject_pending_timer_irqs(vcpu);
3650
3651 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3652 r = -EINTR;
3653 kvm_run->exit_reason = KVM_EXIT_INTR;
3654 ++vcpu->stat.request_irq_exits;
3655 }
3656 if (signal_pending(current)) {
3657 r = -EINTR;
3658 kvm_run->exit_reason = KVM_EXIT_INTR;
3659 ++vcpu->stat.signal_exits;
3660 }
3661 if (need_resched()) {
3662 up_read(&vcpu->kvm->slots_lock);
3663 kvm_resched(vcpu);
3664 down_read(&vcpu->kvm->slots_lock);
d7690175 3665 }
b6c7a5dc
HB		 3666 }
3667
d7690175 3668 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3669 post_kvm_run_save(vcpu, kvm_run);
3670
b93463aa
AK		 3671 vapic_exit(vcpu);
3672
b6c7a5dc
HB		 3673 return r;
3674}
3675
3676int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3677{
3678 int r;
3679 sigset_t sigsaved;
3680
3681 vcpu_load(vcpu);
3682
ac9f6dc0
AK		 3683 if (vcpu->sigset_active)
3684 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3685
a4535290 3686 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3687 kvm_vcpu_block(vcpu);
d7690175 3688 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3689 r = -EAGAIN;
3690 goto out;
b6c7a5dc
HB		 3691 }
3692
b6c7a5dc
HB		 3693 /* re-sync apic's tpr */
3694 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3695 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3696
ad312c7c 3697 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3698 r = complete_pio(vcpu);
3699 if (r)
3700 goto out;
3701 }
3702#if CONFIG_HAS_IOMEM
3703 if (vcpu->mmio_needed) {
3704 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3705 vcpu->mmio_read_completed = 1;
3706 vcpu->mmio_needed = 0;
3200f405
MT		 3707
3708 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3709 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3710 vcpu->arch.mmio_fault_cr2, 0,
3711 EMULTYPE_NO_DECODE);
3200f405 3712 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3713 if (r == EMULATE_DO_MMIO) {
3714 /*
3715 * Read-modify-write. Back to userspace.
3716 */
3717 r = 0;
3718 goto out;
3719 }
3720 }
3721#endif
5fdbf976
MT		 3722 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3723 kvm_register_write(vcpu, VCPU_REGS_RAX,
3724 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3725
3726 r = __vcpu_run(vcpu, kvm_run);
3727
3728out:
3729 if (vcpu->sigset_active)
3730 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3731
3732 vcpu_put(vcpu);
3733 return r;
3734}
3735
3736int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3737{
3738 vcpu_load(vcpu);
3739
5fdbf976
MT		 3740 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3741 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3742 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3743 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3744 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3745 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3746 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3747 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3748#ifdef CONFIG_X86_64
5fdbf976
MT		 3749 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3750 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3751 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3752 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3753 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3754 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3755 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3756 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3757#endif
3758
5fdbf976 3759 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3760 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3761
3762 /*
3763 * Don't leak debug flags in case they were set for guest debugging
3764 */
d0bfb940 3765 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3766 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3767
3768 vcpu_put(vcpu);
3769
3770 return 0;
3771}
3772
3773int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3774{
3775 vcpu_load(vcpu);
3776
5fdbf976
MT		 3777 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3778 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3779 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3780 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3781 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3782 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3783 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3784 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3785#ifdef CONFIG_X86_64
5fdbf976
MT		 3786 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3787 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3788 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3789 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3790 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3791 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3792 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3793 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3794
b6c7a5dc
HB		 3795#endif
3796
5fdbf976 3797 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3798 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3799
b6c7a5dc 3800
b4f14abd
JK		 3801 vcpu->arch.exception.pending = false;
3802
b6c7a5dc
HB		 3803 vcpu_put(vcpu);
3804
3805 return 0;
3806}
3807
3e6e0aab
GT		 3808void kvm_get_segment(struct kvm_vcpu *vcpu,
3809 struct kvm_segment *var, int seg)
b6c7a5dc 3810{
14af3f3c 3811 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3812}
3813
3814void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3815{
3816 struct kvm_segment cs;
3817
3e6e0aab 3818 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3819 *db = cs.db;
3820 *l = cs.l;
3821}
3822EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3823
3824int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3825 struct kvm_sregs *sregs)
3826{
3827 struct descriptor_table dt;
b6c7a5dc
HB		 3828
3829 vcpu_load(vcpu);
3830
3e6e0aab
GT		 3831 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3832 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3833 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3834 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3835 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3836 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3837
3e6e0aab
GT		 3838 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3839 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3840
3841 kvm_x86_ops->get_idt(vcpu, &dt);
3842 sregs->idt.limit = dt.limit;
3843 sregs->idt.base = dt.base;
3844 kvm_x86_ops->get_gdt(vcpu, &dt);
3845 sregs->gdt.limit = dt.limit;
3846 sregs->gdt.base = dt.base;
3847
3848 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3849 sregs->cr0 = vcpu->arch.cr0;
3850 sregs->cr2 = vcpu->arch.cr2;
3851 sregs->cr3 = vcpu->arch.cr3;
3852 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3853 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3854 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3855 sregs->apic_base = kvm_get_apic_base(vcpu);
3856
923c61bb 3857 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3858
36752c9b 3859 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3860 set_bit(vcpu->arch.interrupt.nr,
3861 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3862
b6c7a5dc
HB		 3863 vcpu_put(vcpu);
3864
3865 return 0;
3866}
3867
62d9f0db
MT		 3868int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3869 struct kvm_mp_state *mp_state)
3870{
3871 vcpu_load(vcpu);
3872 mp_state->mp_state = vcpu->arch.mp_state;
3873 vcpu_put(vcpu);
3874 return 0;
3875}
3876
3877int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3878 struct kvm_mp_state *mp_state)
3879{
3880 vcpu_load(vcpu);
3881 vcpu->arch.mp_state = mp_state->mp_state;
3882 vcpu_put(vcpu);
3883 return 0;
3884}
3885
3e6e0aab 3886static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3887 struct kvm_segment *var, int seg)
3888{
14af3f3c 3889 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3890}
3891
37817f29
IE		 3892static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3893 struct kvm_segment *kvm_desct)
3894{
3895 kvm_desct->base = seg_desc->base0;
3896 kvm_desct->base |= seg_desc->base1 << 16;
3897 kvm_desct->base |= seg_desc->base2 << 24;
3898 kvm_desct->limit = seg_desc->limit0;
3899 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3900 if (seg_desc->g) {
3901 kvm_desct->limit <<= 12;
3902 kvm_desct->limit |= 0xfff;
3903 }
37817f29
IE		 3904 kvm_desct->selector = selector;
3905 kvm_desct->type = seg_desc->type;
3906 kvm_desct->present = seg_desc->p;
3907 kvm_desct->dpl = seg_desc->dpl;
3908 kvm_desct->db = seg_desc->d;
3909 kvm_desct->s = seg_desc->s;
3910 kvm_desct->l = seg_desc->l;
3911 kvm_desct->g = seg_desc->g;
3912 kvm_desct->avl = seg_desc->avl;
3913 if (!selector)
3914 kvm_desct->unusable = 1;
3915 else
3916 kvm_desct->unusable = 0;
3917 kvm_desct->padding = 0;
3918}
3919
b8222ad2
AS		 3920static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3921 u16 selector,
3922 struct descriptor_table *dtable)
37817f29
IE		 3923{
3924 if (selector & 1 << 2) {
3925 struct kvm_segment kvm_seg;
3926
3e6e0aab 3927 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3928
3929 if (kvm_seg.unusable)
3930 dtable->limit = 0;
3931 else
3932 dtable->limit = kvm_seg.limit;
3933 dtable->base = kvm_seg.base;
3934 }
3935 else
3936 kvm_x86_ops->get_gdt(vcpu, dtable);
3937}
3938
3939/* allowed just for 8 bytes segments */
3940static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3941 struct desc_struct *seg_desc)
3942{
98899aa0 3943 gpa_t gpa;
37817f29
IE		 3944 struct descriptor_table dtable;
3945 u16 index = selector >> 3;
3946
b8222ad2 3947 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3948
3949 if (dtable.limit < index * 8 + 7) {
3950 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3951 return 1;
3952 }
98899aa0
MT		 3953 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3954 gpa += index * 8;
3955 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3956}
3957
3958/* allowed just for 8 bytes segments */
3959static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3960 struct desc_struct *seg_desc)
3961{
98899aa0 3962 gpa_t gpa;
37817f29
IE		 3963 struct descriptor_table dtable;
3964 u16 index = selector >> 3;
3965
b8222ad2 3966 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3967
3968 if (dtable.limit < index * 8 + 7)
3969 return 1;
98899aa0
MT		 3970 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3971 gpa += index * 8;
3972 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3973}
3974
3975static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3976 struct desc_struct *seg_desc)
3977{
3978 u32 base_addr;
3979
3980 base_addr = seg_desc->base0;
3981 base_addr |= (seg_desc->base1 << 16);
3982 base_addr |= (seg_desc->base2 << 24);
3983
98899aa0 3984 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3985}
3986
37817f29
IE		 3987static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3988{
3989 struct kvm_segment kvm_seg;
3990
3e6e0aab 3991 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3992 return kvm_seg.selector;
3993}
3994
3995static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3996 u16 selector,
3997 struct kvm_segment *kvm_seg)
3998{
3999 struct desc_struct seg_desc;
4000
4001 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4002 return 1;
4003 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4004 return 0;
4005}
4006
2259e3a7 4007static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4008{
4009 struct kvm_segment segvar = {
4010 .base = selector << 4,
4011 .limit = 0xffff,
4012 .selector = selector,
4013 .type = 3,
4014 .present = 1,
4015 .dpl = 3,
4016 .db = 0,
4017 .s = 1,
4018 .l = 0,
4019 .g = 0,
4020 .avl = 0,
4021 .unusable = 0,
4022 };
4023 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4024 return 0;
4025}
4026
3e6e0aab
GT		 4027int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4028 int type_bits, int seg)
37817f29
IE		 4029{
4030 struct kvm_segment kvm_seg;
4031
f4bbd9aa
AK		 4032 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4033 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4034 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4035 return 1;
4036 kvm_seg.type |= type_bits;
4037
4038 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4039 seg != VCPU_SREG_LDTR)
4040 if (!kvm_seg.s)
4041 kvm_seg.unusable = 1;
4042
3e6e0aab 4043 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4044 return 0;
4045}
4046
4047static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4048 struct tss_segment_32 *tss)
4049{
4050 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4051 tss->eip = kvm_rip_read(vcpu);
37817f29 4052 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4053 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4054 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4055 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4056 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4057 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4058 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4059 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4060 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4061 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4062 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4063 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4064 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4065 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4066 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4067 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4068}
4069
4070static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4071 struct tss_segment_32 *tss)
4072{
4073 kvm_set_cr3(vcpu, tss->cr3);
4074
5fdbf976 4075 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4076 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4077
5fdbf976
MT		 4078 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4079 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4080 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4081 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4082 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4083 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4084 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4085 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4086
3e6e0aab 4087 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4088 return 1;
4089
3e6e0aab 4090 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4091 return 1;
4092
3e6e0aab 4093 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4094 return 1;
4095
3e6e0aab 4096 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4097 return 1;
4098
3e6e0aab 4099 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4100 return 1;
4101
3e6e0aab 4102 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4103 return 1;
4104
3e6e0aab 4105 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4106 return 1;
4107 return 0;
4108}
4109
4110static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4111 struct tss_segment_16 *tss)
4112{
5fdbf976 4113 tss->ip = kvm_rip_read(vcpu);
37817f29 4114 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4115 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4116 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4117 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4118 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4119 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4120 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4121 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4122 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4123
4124 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4125 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4126 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4127 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4128 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4129 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4130}
4131
4132static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4133 struct tss_segment_16 *tss)
4134{
5fdbf976 4135 kvm_rip_write(vcpu, tss->ip);
37817f29 4136 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4137 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4138 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4139 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4140 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4141 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4142 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4143 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4144 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4145
3e6e0aab 4146 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4147 return 1;
4148
3e6e0aab 4149 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4150 return 1;
4151
3e6e0aab 4152 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4153 return 1;
4154
3e6e0aab 4155 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4156 return 1;
4157
3e6e0aab 4158 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4159 return 1;
4160 return 0;
4161}
4162
8b2cf73c 4163static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4164 u16 old_tss_sel, u32 old_tss_base,
4165 struct desc_struct *nseg_desc)
37817f29
IE		 4166{
4167 struct tss_segment_16 tss_segment_16;
4168 int ret = 0;
4169
34198bf8
MT		 4170 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4171 sizeof tss_segment_16))
37817f29
IE		 4172 goto out;
4173
4174 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4175
34198bf8
MT		 4176 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4177 sizeof tss_segment_16))
37817f29 4178 goto out;
34198bf8
MT		 4179
4180 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4181 &tss_segment_16, sizeof tss_segment_16))
4182 goto out;
4183
b237ac37
GN		 4184 if (old_tss_sel != 0xffff) {
4185 tss_segment_16.prev_task_link = old_tss_sel;
4186
4187 if (kvm_write_guest(vcpu->kvm,
4188 get_tss_base_addr(vcpu, nseg_desc),
4189 &tss_segment_16.prev_task_link,
4190 sizeof tss_segment_16.prev_task_link))
4191 goto out;
4192 }
4193
37817f29
IE		 4194 if (load_state_from_tss16(vcpu, &tss_segment_16))
4195 goto out;
4196
4197 ret = 1;
4198out:
4199 return ret;
4200}
4201
8b2cf73c 4202static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4203 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4204 struct desc_struct *nseg_desc)
4205{
4206 struct tss_segment_32 tss_segment_32;
4207 int ret = 0;
4208
34198bf8
MT		 4209 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4210 sizeof tss_segment_32))
37817f29
IE		 4211 goto out;
4212
4213 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4214
34198bf8
MT		 4215 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4216 sizeof tss_segment_32))
4217 goto out;
4218
4219 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4220 &tss_segment_32, sizeof tss_segment_32))
37817f29 4221 goto out;
34198bf8 4222
b237ac37
GN		 4223 if (old_tss_sel != 0xffff) {
4224 tss_segment_32.prev_task_link = old_tss_sel;
4225
4226 if (kvm_write_guest(vcpu->kvm,
4227 get_tss_base_addr(vcpu, nseg_desc),
4228 &tss_segment_32.prev_task_link,
4229 sizeof tss_segment_32.prev_task_link))
4230 goto out;
4231 }
4232
37817f29
IE		 4233 if (load_state_from_tss32(vcpu, &tss_segment_32))
4234 goto out;
4235
4236 ret = 1;
4237out:
4238 return ret;
4239}
4240
4241int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4242{
4243 struct kvm_segment tr_seg;
4244 struct desc_struct cseg_desc;
4245 struct desc_struct nseg_desc;
4246 int ret = 0;
34198bf8
MT		 4247 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4248 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4249
34198bf8 4250 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4251
34198bf8
MT		 4252 /* FIXME: Handle errors. Failure to read either TSS or their
4253 * descriptors should generate a pagefault.
4254 */
37817f29
IE		 4255 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4256 goto out;
4257
34198bf8 4258 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4259 goto out;
4260
37817f29
IE		 4261 if (reason != TASK_SWITCH_IRET) {
4262 int cpl;
4263
4264 cpl = kvm_x86_ops->get_cpl(vcpu);
4265 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4266 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4267 return 1;
4268 }
4269 }
4270
4271 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4272 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4273 return 1;
4274 }
4275
4276 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4277 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4278 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4279 }
4280
4281 if (reason == TASK_SWITCH_IRET) {
4282 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4283 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4284 }
4285
64a7ec06
GN		 4286 /* set back link to prev task only if NT bit is set in eflags
4287 note that old_tss_sel is not used afetr this point */
4288 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4289 old_tss_sel = 0xffff;
37817f29 4290
b237ac37
GN		 4291 /* set back link to prev task only if NT bit is set in eflags
4292 note that old_tss_sel is not used afetr this point */
4293 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4294 old_tss_sel = 0xffff;
4295
37817f29 4296 if (nseg_desc.type & 8)
b237ac37
GN		 4297 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4298 old_tss_base, &nseg_desc);
37817f29 4299 else
b237ac37
GN		 4300 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4301 old_tss_base, &nseg_desc);
37817f29
IE		 4302
4303 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4304 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4305 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4306 }
4307
4308 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4309 nseg_desc.type |= (1 << 1);
37817f29
IE		 4310 save_guest_segment_descriptor(vcpu, tss_selector,
4311 &nseg_desc);
4312 }
4313
4314 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4315 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4316 tr_seg.type = 11;
3e6e0aab 4317 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4318out:
37817f29
IE		 4319 return ret;
4320}
4321EXPORT_SYMBOL_GPL(kvm_task_switch);
4322
b6c7a5dc
HB		 4323int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4324 struct kvm_sregs *sregs)
4325{
4326 int mmu_reset_needed = 0;
923c61bb 4327 int pending_vec, max_bits;
b6c7a5dc
HB		 4328 struct descriptor_table dt;
4329
4330 vcpu_load(vcpu);
4331
4332 dt.limit = sregs->idt.limit;
4333 dt.base = sregs->idt.base;
4334 kvm_x86_ops->set_idt(vcpu, &dt);
4335 dt.limit = sregs->gdt.limit;
4336 dt.base = sregs->gdt.base;
4337 kvm_x86_ops->set_gdt(vcpu, &dt);
4338
ad312c7c
ZX		 4339 vcpu->arch.cr2 = sregs->cr2;
4340 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4341 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4342
2d3ad1f4 4343 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4344
ad312c7c 4345 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4346 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4347 kvm_set_apic_base(vcpu, sregs->apic_base);
4348
4349 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4350
ad312c7c 4351 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4352 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4353 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4354
ad312c7c 4355 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4356 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4357 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4358 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4359
4360 if (mmu_reset_needed)
4361 kvm_mmu_reset_context(vcpu);
4362
923c61bb
GN		 4363 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4364 pending_vec = find_first_bit(
4365 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4366 if (pending_vec < max_bits) {
66fd3f7f 4367 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4368 pr_debug("Set back pending irq %d\n", pending_vec);
4369 if (irqchip_in_kernel(vcpu->kvm))
4370 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4371 }
4372
3e6e0aab
GT		 4373 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4374 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4375 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4376 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4377 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4378 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4379
3e6e0aab
GT		 4380 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4381 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4382
9c3e4aab 4383 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4384 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4385 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4386 !(vcpu->arch.cr0 & X86_CR0_PE))
4387 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4388
b6c7a5dc
HB		 4389 vcpu_put(vcpu);
4390
4391 return 0;
4392}
4393
d0bfb940
JK		 4394int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4395 struct kvm_guest_debug *dbg)
b6c7a5dc 4396{
ae675ef0 4397 int i, r;
b6c7a5dc
HB		 4398
4399 vcpu_load(vcpu);
4400
ae675ef0
JK		 4401 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4402 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4403 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4404 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4405 vcpu->arch.switch_db_regs =
4406 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4407 } else {
4408 for (i = 0; i < KVM_NR_DB_REGS; i++)
4409 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4410 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4411 }
4412
b6c7a5dc
HB		 4413 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4414
d0bfb940
JK		 4415 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4416 kvm_queue_exception(vcpu, DB_VECTOR);
4417 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4418 kvm_queue_exception(vcpu, BP_VECTOR);
4419
b6c7a5dc
HB		 4420 vcpu_put(vcpu);
4421
4422 return r;
4423}
4424
d0752060
HB		 4425/*
4426 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4427 * we have asm/x86/processor.h
4428 */
4429struct fxsave {
4430 u16 cwd;
4431 u16 swd;
4432 u16 twd;
4433 u16 fop;
4434 u64 rip;
4435 u64 rdp;
4436 u32 mxcsr;
4437 u32 mxcsr_mask;
4438 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4439#ifdef CONFIG_X86_64
4440 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4441#else
4442 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4443#endif
4444};
4445
8b006791
ZX		 4446/*
4447 * Translate a guest virtual address to a guest physical address.
4448 */
4449int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4450 struct kvm_translation *tr)
4451{
4452 unsigned long vaddr = tr->linear_address;
4453 gpa_t gpa;
4454
4455 vcpu_load(vcpu);
72dc67a6 4456 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4457 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4458 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4459 tr->physical_address = gpa;
4460 tr->valid = gpa != UNMAPPED_GVA;
4461 tr->writeable = 1;
4462 tr->usermode = 0;
8b006791
ZX		 4463 vcpu_put(vcpu);
4464
4465 return 0;
4466}
4467
d0752060
HB		 4468int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4469{
ad312c7c 4470 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4471
4472 vcpu_load(vcpu);
4473
4474 memcpy(fpu->fpr, fxsave->st_space, 128);
4475 fpu->fcw = fxsave->cwd;
4476 fpu->fsw = fxsave->swd;
4477 fpu->ftwx = fxsave->twd;
4478 fpu->last_opcode = fxsave->fop;
4479 fpu->last_ip = fxsave->rip;
4480 fpu->last_dp = fxsave->rdp;
4481 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4482
4483 vcpu_put(vcpu);
4484
4485 return 0;
4486}
4487
4488int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4489{
ad312c7c 4490 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4491
4492 vcpu_load(vcpu);
4493
4494 memcpy(fxsave->st_space, fpu->fpr, 128);
4495 fxsave->cwd = fpu->fcw;
4496 fxsave->swd = fpu->fsw;
4497 fxsave->twd = fpu->ftwx;
4498 fxsave->fop = fpu->last_opcode;
4499 fxsave->rip = fpu->last_ip;
4500 fxsave->rdp = fpu->last_dp;
4501 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4502
4503 vcpu_put(vcpu);
4504
4505 return 0;
4506}
4507
4508void fx_init(struct kvm_vcpu *vcpu)
4509{
4510 unsigned after_mxcsr_mask;
4511
bc1a34f1
AA		 4512 /*
4513 * Touch the fpu the first time in non atomic context as if
4514 * this is the first fpu instruction the exception handler
4515 * will fire before the instruction returns and it'll have to
4516 * allocate ram with GFP_KERNEL.
4517 */
4518 if (!used_math())
d6e88aec 4519 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4520
d0752060
HB		 4521 /* Initialize guest FPU by resetting ours and saving into guest's */
4522 preempt_disable();
d6e88aec
AK		 4523 kvm_fx_save(&vcpu->arch.host_fx_image);
4524 kvm_fx_finit();
4525 kvm_fx_save(&vcpu->arch.guest_fx_image);
4526 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4527 preempt_enable();
4528
ad312c7c 4529 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4530 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4531 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4532 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4533 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4534}
4535EXPORT_SYMBOL_GPL(fx_init);
4536
4537void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4538{
4539 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4540 return;
4541
4542 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4543 kvm_fx_save(&vcpu->arch.host_fx_image);
4544 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4545}
4546EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4547
4548void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4549{
4550 if (!vcpu->guest_fpu_loaded)
4551 return;
4552
4553 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4554 kvm_fx_save(&vcpu->arch.guest_fx_image);
4555 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4556 ++vcpu->stat.fpu_reload;
d0752060
HB		 4557}
4558EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4559
4560void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4561{
7f1ea208
JR		 4562 if (vcpu->arch.time_page) {
4563 kvm_release_page_dirty(vcpu->arch.time_page);
4564 vcpu->arch.time_page = NULL;
4565 }
4566
e9b11c17
ZX		 4567 kvm_x86_ops->vcpu_free(vcpu);
4568}
4569
4570struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4571 unsigned int id)
4572{
26e5215f
AK		 4573 return kvm_x86_ops->vcpu_create(kvm, id);
4574}
e9b11c17 4575
26e5215f
AK		 4576int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4577{
4578 int r;
e9b11c17
ZX		 4579
4580 /* We do fxsave: this must be aligned. */
ad312c7c 4581 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4582
0bed3b56 4583 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4584 vcpu_load(vcpu);
4585 r = kvm_arch_vcpu_reset(vcpu);
4586 if (r == 0)
4587 r = kvm_mmu_setup(vcpu);
4588 vcpu_put(vcpu);
4589 if (r < 0)
4590 goto free_vcpu;
4591
26e5215f 4592 return 0;
e9b11c17
ZX		 4593free_vcpu:
4594 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4595 return r;
e9b11c17
ZX		 4596}
4597
d40ccc62 4598void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4599{
4600 vcpu_load(vcpu);
4601 kvm_mmu_unload(vcpu);
4602 vcpu_put(vcpu);
4603
4604 kvm_x86_ops->vcpu_free(vcpu);
4605}
4606
4607int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4608{
448fa4a9
JK		 4609 vcpu->arch.nmi_pending = false;
4610 vcpu->arch.nmi_injected = false;
4611
42dbaa5a
JK		 4612 vcpu->arch.switch_db_regs = 0;
4613 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4614 vcpu->arch.dr6 = DR6_FIXED_1;
4615 vcpu->arch.dr7 = DR7_FIXED_1;
4616
e9b11c17
ZX		 4617 return kvm_x86_ops->vcpu_reset(vcpu);
4618}
4619
4620void kvm_arch_hardware_enable(void *garbage)
4621{
4622 kvm_x86_ops->hardware_enable(garbage);
4623}
4624
4625void kvm_arch_hardware_disable(void *garbage)
4626{
4627 kvm_x86_ops->hardware_disable(garbage);
4628}
4629
4630int kvm_arch_hardware_setup(void)
4631{
4632 return kvm_x86_ops->hardware_setup();
4633}
4634
4635void kvm_arch_hardware_unsetup(void)
4636{
4637 kvm_x86_ops->hardware_unsetup();
4638}
4639
4640void kvm_arch_check_processor_compat(void *rtn)
4641{
4642 kvm_x86_ops->check_processor_compatibility(rtn);
4643}
4644
4645int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4646{
4647 struct page *page;
4648 struct kvm *kvm;
4649 int r;
4650
4651 BUG_ON(vcpu->kvm == NULL);
4652 kvm = vcpu->kvm;
4653
ad312c7c 4654 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4655 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4656 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4657 else
a4535290 4658 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4659
4660 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4661 if (!page) {
4662 r = -ENOMEM;
4663 goto fail;
4664 }
ad312c7c 4665 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4666
4667 r = kvm_mmu_create(vcpu);
4668 if (r < 0)
4669 goto fail_free_pio_data;
4670
4671 if (irqchip_in_kernel(kvm)) {
4672 r = kvm_create_lapic(vcpu);
4673 if (r < 0)
4674 goto fail_mmu_destroy;
4675 }
4676
890ca9ae
HY		 4677 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4678 GFP_KERNEL);
4679 if (!vcpu->arch.mce_banks) {
4680 r = -ENOMEM;
4681 goto fail_mmu_destroy;
4682 }
4683 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4684
e9b11c17
ZX		 4685 return 0;
4686
4687fail_mmu_destroy:
4688 kvm_mmu_destroy(vcpu);
4689fail_free_pio_data:
ad312c7c 4690 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4691fail:
4692 return r;
4693}
4694
4695void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4696{
4697 kvm_free_lapic(vcpu);
3200f405 4698 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4699 kvm_mmu_destroy(vcpu);
3200f405 4700 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4701 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4702}
d19a9cd2
ZX		 4703
4704struct kvm *kvm_arch_create_vm(void)
4705{
4706 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4707
4708 if (!kvm)
4709 return ERR_PTR(-ENOMEM);
4710
f05e70ac 4711 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4712 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4713
5550af4d
SY		 4714 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4715 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4716
53f658b3
MT		 4717 rdtscll(kvm->arch.vm_init_tsc);
4718
d19a9cd2
ZX		 4719 return kvm;
4720}
4721
4722static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4723{
4724 vcpu_load(vcpu);
4725 kvm_mmu_unload(vcpu);
4726 vcpu_put(vcpu);
4727}
4728
4729static void kvm_free_vcpus(struct kvm *kvm)
4730{
4731 unsigned int i;
988a2cae 4732 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4733
4734 /*
4735 * Unpin any mmu pages first.
4736 */
988a2cae
GN		 4737 kvm_for_each_vcpu(i, vcpu, kvm)
4738 kvm_unload_vcpu_mmu(vcpu);
4739 kvm_for_each_vcpu(i, vcpu, kvm)
4740 kvm_arch_vcpu_free(vcpu);
4741
4742 mutex_lock(&kvm->lock);
4743 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4744 kvm->vcpus[i] = NULL;
d19a9cd2 4745
988a2cae
GN		 4746 atomic_set(&kvm->online_vcpus, 0);
4747 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4748}
4749
ad8ba2cd
SY		 4750void kvm_arch_sync_events(struct kvm *kvm)
4751{
ba4cef31 4752 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4753}
4754
d19a9cd2
ZX		 4755void kvm_arch_destroy_vm(struct kvm *kvm)
4756{
6eb55818 4757 kvm_iommu_unmap_guest(kvm);
7837699f 4758 kvm_free_pit(kvm);
d7deeeb0
ZX		 4759 kfree(kvm->arch.vpic);
4760 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4761 kvm_free_vcpus(kvm);
4762 kvm_free_physmem(kvm);
3d45830c
AK		 4763 if (kvm->arch.apic_access_page)
4764 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4765 if (kvm->arch.ept_identity_pagetable)
4766 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4767 kfree(kvm);
4768}
0de10343
ZX		 4769
4770int kvm_arch_set_memory_region(struct kvm *kvm,
4771 struct kvm_userspace_memory_region *mem,
4772 struct kvm_memory_slot old,
4773 int user_alloc)
4774{
4775 int npages = mem->memory_size >> PAGE_SHIFT;
4776 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4777
4778 /*To keep backward compatibility with older userspace,
4779 *x86 needs to hanlde !user_alloc case.
4780 */
4781 if (!user_alloc) {
4782 if (npages && !old.rmap) {
604b38ac
AA		 4783 unsigned long userspace_addr;
4784
72dc67a6 4785 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4786 userspace_addr = do_mmap(NULL, 0,
4787 npages * PAGE_SIZE,
4788 PROT_READ | PROT_WRITE,
acee3c04 4789 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4790 0);
72dc67a6 4791 up_write(&current->mm->mmap_sem);
0de10343 4792
604b38ac
AA		 4793 if (IS_ERR((void *)userspace_addr))
4794 return PTR_ERR((void *)userspace_addr);
4795
4796 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4797 spin_lock(&kvm->mmu_lock);
4798 memslot->userspace_addr = userspace_addr;
4799 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4800 } else {
4801 if (!old.user_alloc && old.rmap) {
4802 int ret;
4803
72dc67a6 4804 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4805 ret = do_munmap(current->mm, old.userspace_addr,
4806 old.npages * PAGE_SIZE);
72dc67a6 4807 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4808 if (ret < 0)
4809 printk(KERN_WARNING
4810 "kvm_vm_ioctl_set_memory_region: "
4811 "failed to munmap memory\n");
4812 }
4813 }
4814 }
4815
7c8a83b7 4816 spin_lock(&kvm->mmu_lock);
f05e70ac 4817 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4818 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4819 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4820 }
4821
4822 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4823 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4824 kvm_flush_remote_tlbs(kvm);
4825
4826 return 0;
4827}
1d737c8a 4828
34d4cb8f
MT		 4829void kvm_arch_flush_shadow(struct kvm *kvm)
4830{
4831 kvm_mmu_zap_all(kvm);
8986ecc0 4832 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4833}
4834
1d737c8a
ZX		 4835int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4836{
a4535290 4837 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4838 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4839 || vcpu->arch.nmi_pending;
1d737c8a 4840}
5736199a 4841
5736199a
ZX		 4842void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4843{
32f88400
MT		 4844 int me;
4845 int cpu = vcpu->cpu;
5736199a
ZX		 4846
4847 if (waitqueue_active(&vcpu->wq)) {
4848 wake_up_interruptible(&vcpu->wq);
4849 ++vcpu->stat.halt_wakeup;
4850 }
32f88400
MT		 4851
4852 me = get_cpu();
4853 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4854 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4855 smp_send_reschedule(cpu);
e9571ed5 4856 put_cpu();
5736199a 4857}
78646121
GN		 4858
4859int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4860{
4861 return kvm_x86_ops->interrupt_allowed(vcpu);
4862}
229456fc
MT		 4863
4864EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4865EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4866EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4867EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4868EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux kernel - Deliverables
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