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KVM: x86: Clear CR2 on VCPU reset
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
92a1f12d
JR		 102bool kvm_has_tsc_control;
103EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104u32 kvm_max_guest_tsc_khz;
105EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
cc578287
ZA		 107/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108static u32 tsc_tolerance_ppm = 250;
109module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
d0659d94
MT		 111/* lapic timer advance (tscdeadline mode only) in nanoseconds */
112unsigned int lapic_timer_advance_ns = 0;
113module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
16a96021
MT		 115static bool backwards_tsc_observed = false;
116
18863bdd
AK		 117#define KVM_NR_SHARED_MSRS 16
118
119struct kvm_shared_msrs_global {
120 int nr;
2bf78fa7 121 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 122};
123
124struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
2bf78fa7
SY		 127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 131};
132
133static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 134static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 135
417bc304 136struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 147 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 149 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 150 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 151 { "request_irq", VCPU_STAT(request_irq_exits) },
152 { "irq_exits", VCPU_STAT(irq_exits) },
153 { "host_state_reload", VCPU_STAT(host_state_reload) },
154 { "efer_reload", VCPU_STAT(efer_reload) },
155 { "fpu_reload", VCPU_STAT(fpu_reload) },
156 { "insn_emulation", VCPU_STAT(insn_emulation) },
157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 158 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 159 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164 { "mmu_flooded", VM_STAT(mmu_flooded) },
165 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 167 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 169 { "largepages", VM_STAT(lpages) },
417bc304
HB		 170 { NULL }
171};
172
2acf923e
DC		 173u64 __read_mostly host_xcr0;
174
b6785def 175static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 176
af585b92
GN		 177static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178{
179 int i;
180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181 vcpu->arch.apf.gfns[i] = ~0;
182}
183
18863bdd
AK		 184static void kvm_on_user_return(struct user_return_notifier *urn)
185{
186 unsigned slot;
18863bdd
AK		 187 struct kvm_shared_msrs *locals
188 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 189 struct kvm_shared_msr_values *values;
18863bdd
AK		 190
191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 192 values = &locals->values[slot];
193 if (values->host != values->curr) {
194 wrmsrl(shared_msrs_global.msrs[slot], values->host);
195 values->curr = values->host;
18863bdd
AK		 196 }
197 }
198 locals->registered = false;
199 user_return_notifier_unregister(urn);
200}
201
2bf78fa7 202static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 203{
18863bdd 204 u64 value;
013f6a5d
MT		 205 unsigned int cpu = smp_processor_id();
206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 207
2bf78fa7
SY		 208 /* only read, and nobody should modify it at this time,
209 * so don't need lock */
210 if (slot >= shared_msrs_global.nr) {
211 printk(KERN_ERR "kvm: invalid MSR slot!");
212 return;
213 }
214 rdmsrl_safe(msr, &value);
215 smsr->values[slot].host = value;
216 smsr->values[slot].curr = value;
217}
218
219void kvm_define_shared_msr(unsigned slot, u32 msr)
220{
0123be42 221 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 222 if (slot >= shared_msrs_global.nr)
223 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 224 shared_msrs_global.msrs[slot] = msr;
225 /* we need ensured the shared_msr_global have been updated */
226 smp_wmb();
18863bdd
AK		 227}
228EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230static void kvm_shared_msr_cpu_online(void)
231{
232 unsigned i;
18863bdd
AK		 233
234 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 235 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 236}
237
8b3c3104 238int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 239{
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 242 int err;
18863bdd 243
2bf78fa7 244 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 245 return 0;
2bf78fa7 246 smsr->values[slot].curr = value;
8b3c3104
AH		 247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248 if (err)
249 return 1;
250
18863bdd
AK		 251 if (!smsr->registered) {
252 smsr->urn.on_user_return = kvm_on_user_return;
253 user_return_notifier_register(&smsr->urn);
254 smsr->registered = true;
255 }
8b3c3104 256 return 0;
18863bdd
AK		 257}
258EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
13a34e06 260static void drop_user_return_notifiers(void)
3548bab5 261{
013f6a5d
MT		 262 unsigned int cpu = smp_processor_id();
263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 264
265 if (smsr->registered)
266 kvm_on_user_return(&smsr->urn);
267}
268
6866b83e
CO		 269u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270{
8a5a87d9 271 return vcpu->arch.apic_base;
6866b83e
CO		 272}
273EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
58cb628d
JK		 275int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276{
277 u64 old_state = vcpu->arch.apic_base &
278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279 u64 new_state = msr_info->data &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284 if (!msr_info->host_initiated &&
285 ((msr_info->data & reserved_bits) != 0 ||
286 new_state == X2APIC_ENABLE ||
287 (new_state == MSR_IA32_APICBASE_ENABLE &&
288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290 old_state == 0)))
291 return 1;
292
293 kvm_lapic_set_base(vcpu, msr_info->data);
294 return 0;
6866b83e
CO		 295}
296EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
2605fc21 298asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 299{
300 /* Fault while not rebooting. We want the trace. */
301 BUG();
302}
303EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
3fd28fce
ED		 305#define EXCPT_BENIGN 0
306#define EXCPT_CONTRIBUTORY 1
307#define EXCPT_PF 2
308
309static int exception_class(int vector)
310{
311 switch (vector) {
312 case PF_VECTOR:
313 return EXCPT_PF;
314 case DE_VECTOR:
315 case TS_VECTOR:
316 case NP_VECTOR:
317 case SS_VECTOR:
318 case GP_VECTOR:
319 return EXCPT_CONTRIBUTORY;
320 default:
321 break;
322 }
323 return EXCPT_BENIGN;
324}
325
d6e8c854
NA		 326#define EXCPT_FAULT 0
327#define EXCPT_TRAP 1
328#define EXCPT_ABORT 2
329#define EXCPT_INTERRUPT 3
330
331static int exception_type(int vector)
332{
333 unsigned int mask;
334
335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336 return EXCPT_INTERRUPT;
337
338 mask = 1 << vector;
339
340 /* #DB is trap, as instruction watchpoints are handled elsewhere */
341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342 return EXCPT_TRAP;
343
344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345 return EXCPT_ABORT;
346
347 /* Reserved exceptions will result in fault */
348 return EXCPT_FAULT;
349}
350
3fd28fce 351static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 352 unsigned nr, bool has_error, u32 error_code,
353 bool reinject)
3fd28fce
ED		 354{
355 u32 prev_nr;
356 int class1, class2;
357
3842d135
AK		 358 kvm_make_request(KVM_REQ_EVENT, vcpu);
359
3fd28fce
ED		 360 if (!vcpu->arch.exception.pending) {
361 queue:
3ffb2468
NA		 362 if (has_error && !is_protmode(vcpu))
363 has_error = false;
3fd28fce
ED		 364 vcpu->arch.exception.pending = true;
365 vcpu->arch.exception.has_error_code = has_error;
366 vcpu->arch.exception.nr = nr;
367 vcpu->arch.exception.error_code = error_code;
3f0fd292 368 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 369 return;
370 }
371
372 /* to check exception */
373 prev_nr = vcpu->arch.exception.nr;
374 if (prev_nr == DF_VECTOR) {
375 /* triple fault -> shutdown */
a8eeb04a 376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 377 return;
378 }
379 class1 = exception_class(prev_nr);
380 class2 = exception_class(nr);
381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383 /* generate double fault per SDM Table 5-5 */
384 vcpu->arch.exception.pending = true;
385 vcpu->arch.exception.has_error_code = true;
386 vcpu->arch.exception.nr = DF_VECTOR;
387 vcpu->arch.exception.error_code = 0;
388 } else
389 /* replace previous exception with a new one in a hope
390 that instruction re-execution will regenerate lost
391 exception */
392 goto queue;
393}
394
298101da
AK		 395void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396{
ce7ddec4 397 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 398}
399EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
ce7ddec4
JR		 401void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402{
403 kvm_multiple_exception(vcpu, nr, false, 0, true);
404}
405EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
db8fcefa 407void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 408{
db8fcefa
AP		 409 if (err)
410 kvm_inject_gp(vcpu, 0);
411 else
412 kvm_x86_ops->skip_emulated_instruction(vcpu);
413}
414EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 415
6389ee94 416void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 417{
418 ++vcpu->stat.pf_guest;
6389ee94
AK		 419 vcpu->arch.cr2 = fault->address;
420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 421}
27d6c865 422EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 423
ef54bcfe 424static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 425{
6389ee94
AK		 426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 428 else
6389ee94 429 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 430
431 return fault->nested_page_fault;
d4f8cf66
JR		 432}
433
3419ffc8
SY		 434void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435{
7460fb4a
AK		 436 atomic_inc(&vcpu->arch.nmi_queued);
437 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 438}
439EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
298101da
AK		 441void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442{
ce7ddec4 443 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 444}
445EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
ce7ddec4
JR		 447void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448{
449 kvm_multiple_exception(vcpu, nr, true, error_code, true);
450}
451EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
0a79b009
AK		 453/*
454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
455 * a #GP and return false.
456 */
457bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 458{
0a79b009
AK		 459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460 return true;
461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462 return false;
298101da 463}
0a79b009 464EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 465
16f8a6f9
NA		 466bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467{
468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469 return true;
470
471 kvm_queue_exception(vcpu, UD_VECTOR);
472 return false;
473}
474EXPORT_SYMBOL_GPL(kvm_require_dr);
475
ec92fe44
JR		 476/*
477 * This function will be used to read from the physical memory of the currently
478 * running guest. The difference to kvm_read_guest_page is that this function
479 * can read from guest physical or from the guest's guest physical memory.
480 */
481int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482 gfn_t ngfn, void *data, int offset, int len,
483 u32 access)
484{
54987b7a 485 struct x86_exception exception;
ec92fe44
JR		 486 gfn_t real_gfn;
487 gpa_t ngpa;
488
489 ngpa = gfn_to_gpa(ngfn);
54987b7a 490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 491 if (real_gfn == UNMAPPED_GVA)
492 return -EFAULT;
493
494 real_gfn = gpa_to_gfn(real_gfn);
495
496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497}
498EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
69b0049a 500static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 501 void *data, int offset, int len, u32 access)
502{
503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504 data, offset, len, access);
505}
506
a03490ed
CO		 507/*
508 * Load the pae pdptrs. Return true is they are all valid.
509 */
ff03a073 510int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 511{
512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514 int i;
515 int ret;
ff03a073 516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 517
ff03a073
JR		 518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519 offset * sizeof(u64), sizeof(pdpte),
520 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 521 if (ret < 0) {
522 ret = 0;
523 goto out;
524 }
525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 526 if (is_present_gpte(pdpte[i]) &&
20c466b5 527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 528 ret = 0;
529 goto out;
530 }
531 }
532 ret = 1;
533
ff03a073 534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 535 __set_bit(VCPU_EXREG_PDPTR,
536 (unsigned long *)&vcpu->arch.regs_avail);
537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 539out:
a03490ed
CO		 540
541 return ret;
542}
cc4b6871 543EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 544
d835dfec
AK		 545static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546{
ff03a073 547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 548 bool changed = true;
3d06b8bf
JR		 549 int offset;
550 gfn_t gfn;
d835dfec
AK		 551 int r;
552
553 if (is_long_mode(vcpu) || !is_pae(vcpu))
554 return false;
555
6de4f3ad
AK		 556 if (!test_bit(VCPU_EXREG_PDPTR,
557 (unsigned long *)&vcpu->arch.regs_avail))
558 return true;
559
9f8fe504
AK		 560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 564 if (r < 0)
565 goto out;
ff03a073 566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 567out:
d835dfec
AK		 568
569 return changed;
570}
571
49a9b07e 572int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 573{
aad82703
SY		 574 unsigned long old_cr0 = kvm_read_cr0(vcpu);
575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
576 X86_CR0_CD | X86_CR0_NW;
577
f9a48e6a
AK		 578 cr0 |= X86_CR0_ET;
579
ab344828 580#ifdef CONFIG_X86_64
0f12244f
GN		 581 if (cr0 & 0xffffffff00000000UL)
582 return 1;
ab344828
GN		 583#endif
584
585 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 586
0f12244f
GN		 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588 return 1;
a03490ed 589
0f12244f
GN		 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591 return 1;
a03490ed
CO		 592
593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594#ifdef CONFIG_X86_64
f6801dff 595 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 596 int cs_db, cs_l;
597
0f12244f
GN		 598 if (!is_pae(vcpu))
599 return 1;
a03490ed 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 601 if (cs_l)
602 return 1;
a03490ed
CO		 603 } else
604#endif
ff03a073 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 606 kvm_read_cr3(vcpu)))
0f12244f 607 return 1;
a03490ed
CO		 608 }
609
ad756a16
MJ		 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611 return 1;
612
a03490ed 613 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 614
d170c419 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 616 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 617 kvm_async_pf_hash_reset(vcpu);
618 }
e5f3f027 619
aad82703
SY		 620 if ((cr0 ^ old_cr0) & update_bits)
621 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 622 return 0;
623}
2d3ad1f4 624EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 625
2d3ad1f4 626void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 627{
49a9b07e 628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 629}
2d3ad1f4 630EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 631
42bdf991
MT		 632static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633{
634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
635 !vcpu->guest_xcr0_loaded) {
636 /* kvm_set_xcr() also depends on this */
637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
638 vcpu->guest_xcr0_loaded = 1;
639 }
640}
641
642static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643{
644 if (vcpu->guest_xcr0_loaded) {
645 if (vcpu->arch.xcr0 != host_xcr0)
646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
647 vcpu->guest_xcr0_loaded = 0;
648 }
649}
650
69b0049a 651static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 652{
56c103ec
LJ		 653 u64 xcr0 = xcr;
654 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 655 u64 valid_bits;
2acf923e
DC		 656
657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
658 if (index != XCR_XFEATURE_ENABLED_MASK)
659 return 1;
2acf923e
DC		 660 if (!(xcr0 & XSTATE_FP))
661 return 1;
662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
663 return 1;
46c34cb0
PB		 664
665 /*
666 * Do not allow the guest to set bits that we do not support
667 * saving. However, xcr0 bit 0 is always set, even if the
668 * emulated CPU does not support XSAVE (see fx_init).
669 */
670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
671 if (xcr0 & ~valid_bits)
2acf923e 672 return 1;
46c34cb0 673
390bd528
LJ		 674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
675 return 1;
676
612263b3
CP		 677 if (xcr0 & XSTATE_AVX512) {
678 if (!(xcr0 & XSTATE_YMM))
679 return 1;
680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
681 return 1;
682 }
42bdf991 683 kvm_put_guest_xcr0(vcpu);
2acf923e 684 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 685
686 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
687 kvm_update_cpuid(vcpu);
2acf923e
DC		 688 return 0;
689}
690
691int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
692{
764bcbc5
Z		 693 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
694 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 695 kvm_inject_gp(vcpu, 0);
696 return 1;
697 }
698 return 0;
699}
700EXPORT_SYMBOL_GPL(kvm_set_xcr);
701
a83b29c6 702int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 703{
fc78f519 704 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 705 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
706 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 707 if (cr4 & CR4_RESERVED_BITS)
708 return 1;
a03490ed 709
2acf923e
DC		 710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711 return 1;
712
c68b734f
YW		 713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714 return 1;
715
97ec8c06
FW		 716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717 return 1;
718
afcbf13f 719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 720 return 1;
721
a03490ed 722 if (is_long_mode(vcpu)) {
0f12244f
GN		 723 if (!(cr4 & X86_CR4_PAE))
724 return 1;
a2edf57f
AK		 725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728 kvm_read_cr3(vcpu)))
0f12244f
GN		 729 return 1;
730
ad756a16
MJ		 731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732 if (!guest_cpuid_has_pcid(vcpu))
733 return 1;
734
735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737 return 1;
738 }
739
5e1746d6 740 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 741 return 1;
a03490ed 742
ad756a16
MJ		 743 if (((cr4 ^ old_cr4) & pdptr_bits) ||
744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 745 kvm_mmu_reset_context(vcpu);
0f12244f 746
97ec8c06
FW		 747 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
748 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
749
2acf923e 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 751 kvm_update_cpuid(vcpu);
2acf923e 752
0f12244f
GN		 753 return 0;
754}
2d3ad1f4 755EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 756
2390218b 757int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 758{
ac146235 759#ifdef CONFIG_X86_64
9d88fca7 760 cr3 &= ~CR3_PCID_INVD;
ac146235 761#endif
9d88fca7 762
9f8fe504 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 764 kvm_mmu_sync_roots(vcpu);
77c3913b 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 766 return 0;
d835dfec
AK		 767 }
768
a03490ed 769 if (is_long_mode(vcpu)) {
d9f89b88
JK		 770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 774 return 1;
a03490ed 775
0f12244f 776 vcpu->arch.cr3 = cr3;
aff48baa 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 778 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 782
eea1cff9 783int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 784{
0f12244f
GN		 785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
a03490ed
CO		 787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
ad312c7c 790 vcpu->arch.cr8 = cr8;
0f12244f
GN		 791 return 0;
792}
2d3ad1f4 793EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 794
2d3ad1f4 795unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 796{
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
ad312c7c 800 return vcpu->arch.cr8;
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 803
ae561ede
NA		 804static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805{
806 int i;
807
808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809 for (i = 0; i < KVM_NR_DB_REGS; i++)
810 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 }
813}
814
73aaf249
JK		 815static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816{
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819}
820
c8639010
JK		 821static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822{
823 unsigned long dr7;
824
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 dr7 = vcpu->arch.guest_debug_dr7;
827 else
828 dr7 = vcpu->arch.dr7;
829 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831 if (dr7 & DR7_BP_EN_MASK)
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 833}
834
6f43ed01
NA		 835static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836{
837 u64 fixed = DR6_FIXED_1;
838
839 if (!guest_cpuid_has_rtm(vcpu))
840 fixed |= DR6_RTM;
841 return fixed;
842}
843
338dbc97 844static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 vcpu->arch.db[dr] = val;
849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850 vcpu->arch.eff_db[dr] = val;
851 break;
852 case 4:
020df079
GN		 853 /* fall through */
854 case 6:
338dbc97
GN		 855 if (val & 0xffffffff00000000ULL)
856 return -1; /* #GP */
6f43ed01 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 858 kvm_update_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
020df079
GN		 861 /* fall through */
862 default: /* 7 */
338dbc97
GN		 863 if (val & 0xffffffff00000000ULL)
864 return -1; /* #GP */
020df079 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 866 kvm_update_dr7(vcpu);
020df079
GN		 867 break;
868 }
869
870 return 0;
871}
338dbc97
GN		 872
873int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874{
16f8a6f9 875 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 876 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 877 return 1;
878 }
879 return 0;
338dbc97 880}
020df079
GN		 881EXPORT_SYMBOL_GPL(kvm_set_dr);
882
16f8a6f9 883int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 884{
885 switch (dr) {
886 case 0 ... 3:
887 *val = vcpu->arch.db[dr];
888 break;
889 case 4:
020df079
GN		 890 /* fall through */
891 case 6:
73aaf249
JK		 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893 *val = vcpu->arch.dr6;
894 else
895 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 896 break;
897 case 5:
020df079
GN		 898 /* fall through */
899 default: /* 7 */
900 *val = vcpu->arch.dr7;
901 break;
902 }
338dbc97
GN		 903 return 0;
904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_get_dr);
906
022cd0e8
AK		 907bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908{
909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 u64 data;
911 int err;
912
913 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914 if (err)
915 return err;
916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918 return err;
919}
920EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
043405e1
CO		 922/*
923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925 *
926 * This list is modified at module load time to reflect the
e3267cbb
GC		 927 * capabilities of the host cpu. This capabilities test skips MSRs that are
928 * kvm-specific. Those are put in the beginning of the list.
043405e1 929 */
e3267cbb 930
e984097b 931#define KVM_SAVE_MSRS_BEGIN 12
043405e1 932static u32 msrs_to_save[] = {
e3267cbb 933 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 934 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 935 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 936 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 937 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 938 MSR_KVM_PV_EOI_EN,
043405e1 939 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 940 MSR_STAR,
043405e1
CO		 941#ifdef CONFIG_X86_64
942 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
943#endif
b3897a49 944 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 945 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 946};
947
948static unsigned num_msrs_to_save;
949
f1d24831 950static const u32 emulated_msrs[] = {
ba904635 951 MSR_IA32_TSC_ADJUST,
a3e06bbe 952 MSR_IA32_TSCDEADLINE,
043405e1 953 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 954 MSR_IA32_MCG_STATUS,
955 MSR_IA32_MCG_CTL,
043405e1
CO		 956};
957
384bb783 958bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 959{
b69e8cae 960 if (efer & efer_reserved_bits)
384bb783 961 return false;
15c4a640 962
1b2fd70c
AG		 963 if (efer & EFER_FFXSR) {
964 struct kvm_cpuid_entry2 *feat;
965
966 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 967 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 968 return false;
1b2fd70c
AG		 969 }
970
d8017474
AG		 971 if (efer & EFER_SVME) {
972 struct kvm_cpuid_entry2 *feat;
973
974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 975 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 976 return false;
d8017474
AG		 977 }
978
384bb783
JK		 979 return true;
980}
981EXPORT_SYMBOL_GPL(kvm_valid_efer);
982
983static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
984{
985 u64 old_efer = vcpu->arch.efer;
986
987 if (!kvm_valid_efer(vcpu, efer))
988 return 1;
989
990 if (is_paging(vcpu)
991 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
992 return 1;
993
15c4a640 994 efer &= ~EFER_LMA;
f6801dff 995 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 996
a3d204e2
SY		 997 kvm_x86_ops->set_efer(vcpu, efer);
998
aad82703
SY		 999 /* Update reserved bits */
1000 if ((efer ^ old_efer) & EFER_NX)
1001 kvm_mmu_reset_context(vcpu);
1002
b69e8cae 1003 return 0;
15c4a640
CO		 1004}
1005
f2b4b7dd
JR		 1006void kvm_enable_efer_bits(u64 mask)
1007{
1008 efer_reserved_bits &= ~mask;
1009}
1010EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1011
15c4a640
CO		 1012/*
1013 * Writes msr value into into the appropriate "register".
1014 * Returns 0 on success, non-0 otherwise.
1015 * Assumes vcpu_load() was already called.
1016 */
8fe8ab46 1017int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1018{
854e8bb1
NA		 1019 switch (msr->index) {
1020 case MSR_FS_BASE:
1021 case MSR_GS_BASE:
1022 case MSR_KERNEL_GS_BASE:
1023 case MSR_CSTAR:
1024 case MSR_LSTAR:
1025 if (is_noncanonical_address(msr->data))
1026 return 1;
1027 break;
1028 case MSR_IA32_SYSENTER_EIP:
1029 case MSR_IA32_SYSENTER_ESP:
1030 /*
1031 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1032 * non-canonical address is written on Intel but not on
1033 * AMD (which ignores the top 32-bits, because it does
1034 * not implement 64-bit SYSENTER).
1035 *
1036 * 64-bit code should hence be able to write a non-canonical
1037 * value on AMD. Making the address canonical ensures that
1038 * vmentry does not fail on Intel after writing a non-canonical
1039 * value, and that something deterministic happens if the guest
1040 * invokes 64-bit SYSENTER.
1041 */
1042 msr->data = get_canonical(msr->data);
1043 }
8fe8ab46 1044 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1045}
854e8bb1 1046EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1047
313a3dc7
CO		 1048/*
1049 * Adapt set_msr() to msr_io()'s calling convention
1050 */
1051static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1052{
8fe8ab46
WA		 1053 struct msr_data msr;
1054
1055 msr.data = *data;
1056 msr.index = index;
1057 msr.host_initiated = true;
1058 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1059}
1060
16e8d74d
MT		 1061#ifdef CONFIG_X86_64
1062struct pvclock_gtod_data {
1063 seqcount_t seq;
1064
1065 struct { /* extract of a clocksource struct */
1066 int vclock_mode;
1067 cycle_t cycle_last;
1068 cycle_t mask;
1069 u32 mult;
1070 u32 shift;
1071 } clock;
1072
cbcf2dd3
TG		 1073 u64 boot_ns;
1074 u64 nsec_base;
16e8d74d
MT		 1075};
1076
1077static struct pvclock_gtod_data pvclock_gtod_data;
1078
1079static void update_pvclock_gtod(struct timekeeper *tk)
1080{
1081 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1082 u64 boot_ns;
1083
d28ede83 1084 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1085
1086 write_seqcount_begin(&vdata->seq);
1087
1088 /* copy pvclock gtod data */
d28ede83
TG		 1089 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1090 vdata->clock.cycle_last = tk->tkr.cycle_last;
1091 vdata->clock.mask = tk->tkr.mask;
1092 vdata->clock.mult = tk->tkr.mult;
1093 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1094
cbcf2dd3 1095 vdata->boot_ns = boot_ns;
d28ede83 1096 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1097
1098 write_seqcount_end(&vdata->seq);
1099}
1100#endif
1101
bab5bb39
NK		 1102void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1103{
1104 /*
1105 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1106 * vcpu_enter_guest. This function is only called from
1107 * the physical CPU that is running vcpu.
1108 */
1109 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1110}
16e8d74d 1111
18068523
GOC		 1112static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1113{
9ed3c444
AK		 1114 int version;
1115 int r;
50d0a0f9 1116 struct pvclock_wall_clock wc;
923de3cf 1117 struct timespec boot;
18068523
GOC		 1118
1119 if (!wall_clock)
1120 return;
1121
9ed3c444
AK		 1122 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1123 if (r)
1124 return;
1125
1126 if (version & 1)
1127 ++version; /* first time write, random junk */
1128
1129 ++version;
18068523 1130
18068523
GOC		 1131 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1132
50d0a0f9
GH		 1133 /*
1134 * The guest calculates current wall clock time by adding
34c238a1 1135 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1136 * wall clock specified here. guest system time equals host
1137 * system time for us, thus we must fill in host boot time here.
1138 */
923de3cf 1139 getboottime(&boot);
50d0a0f9 1140
4b648665
BR		 1141 if (kvm->arch.kvmclock_offset) {
1142 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1143 boot = timespec_sub(boot, ts);
1144 }
50d0a0f9
GH		 1145 wc.sec = boot.tv_sec;
1146 wc.nsec = boot.tv_nsec;
1147 wc.version = version;
18068523
GOC		 1148
1149 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1150
1151 version++;
1152 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1153}
1154
50d0a0f9
GH		 1155static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1156{
1157 uint32_t quotient, remainder;
1158
1159 /* Don't try to replace with do_div(), this one calculates
1160 * "(dividend << 32) / divisor" */
1161 __asm__ ( "divl %4"
1162 : "=a" (quotient), "=d" (remainder)
1163 : "0" (0), "1" (dividend), "r" (divisor) );
1164 return quotient;
1165}
1166
5f4e3f88
ZA		 1167static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1168 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1169{
5f4e3f88 1170 uint64_t scaled64;
50d0a0f9
GH		 1171 int32_t shift = 0;
1172 uint64_t tps64;
1173 uint32_t tps32;
1174
5f4e3f88
ZA		 1175 tps64 = base_khz * 1000LL;
1176 scaled64 = scaled_khz * 1000LL;
50933623 1177 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1178 tps64 >>= 1;
1179 shift--;
1180 }
1181
1182 tps32 = (uint32_t)tps64;
50933623
JK		 1183 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1184 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1185 scaled64 >>= 1;
1186 else
1187 tps32 <<= 1;
50d0a0f9
GH		 1188 shift++;
1189 }
1190
5f4e3f88
ZA		 1191 *pshift = shift;
1192 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1193
5f4e3f88
ZA		 1194 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1195 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1196}
1197
759379dd
ZA		 1198static inline u64 get_kernel_ns(void)
1199{
bb0b5812 1200 return ktime_get_boot_ns();
50d0a0f9
GH		 1201}
1202
d828199e 1203#ifdef CONFIG_X86_64
16e8d74d 1204static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1205#endif
16e8d74d 1206
c8076604 1207static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1208static unsigned long max_tsc_khz;
c8076604 1209
cc578287 1210static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1211{
cc578287
ZA		 1212 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1213 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1214}
1215
cc578287 1216static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1217{
cc578287
ZA		 1218 u64 v = (u64)khz * (1000000 + ppm);
1219 do_div(v, 1000000);
1220 return v;
1e993611
JR		 1221}
1222
cc578287 1223static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1224{
cc578287
ZA		 1225 u32 thresh_lo, thresh_hi;
1226 int use_scaling = 0;
217fc9cf 1227
03ba32ca
MT		 1228 /* tsc_khz can be zero if TSC calibration fails */
1229 if (this_tsc_khz == 0)
1230 return;
1231
c285545f
ZA		 1232 /* Compute a scale to convert nanoseconds in TSC cycles */
1233 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1234 &vcpu->arch.virtual_tsc_shift,
1235 &vcpu->arch.virtual_tsc_mult);
1236 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1237
1238 /*
1239 * Compute the variation in TSC rate which is acceptable
1240 * within the range of tolerance and decide if the
1241 * rate being applied is within that bounds of the hardware
1242 * rate. If so, no scaling or compensation need be done.
1243 */
1244 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1245 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1246 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1247 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1248 use_scaling = 1;
1249 }
1250 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1251}
1252
1253static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1254{
e26101b1 1255 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1256 vcpu->arch.virtual_tsc_mult,
1257 vcpu->arch.virtual_tsc_shift);
e26101b1 1258 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1259 return tsc;
1260}
1261
69b0049a 1262static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1263{
1264#ifdef CONFIG_X86_64
1265 bool vcpus_matched;
b48aa97e
MT		 1266 struct kvm_arch *ka = &vcpu->kvm->arch;
1267 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1268
1269 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1270 atomic_read(&vcpu->kvm->online_vcpus));
1271
7f187922
MT		 1272 /*
1273 * Once the masterclock is enabled, always perform request in
1274 * order to update it.
1275 *
1276 * In order to enable masterclock, the host clocksource must be TSC
1277 * and the vcpus need to have matched TSCs. When that happens,
1278 * perform request to enable masterclock.
1279 */
1280 if (ka->use_master_clock ||
1281 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1282 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1283
1284 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1285 atomic_read(&vcpu->kvm->online_vcpus),
1286 ka->use_master_clock, gtod->clock.vclock_mode);
1287#endif
1288}
1289
ba904635
WA		 1290static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1291{
1292 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1293 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1294}
1295
8fe8ab46 1296void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1297{
1298 struct kvm *kvm = vcpu->kvm;
f38e098f 1299 u64 offset, ns, elapsed;
99e3e30a 1300 unsigned long flags;
02626b6a 1301 s64 usdiff;
b48aa97e 1302 bool matched;
0d3da0d2 1303 bool already_matched;
8fe8ab46 1304 u64 data = msr->data;
99e3e30a 1305
038f8c11 1306 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1308 ns = get_kernel_ns();
f38e098f 1309 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1310
03ba32ca 1311 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1312 int faulted = 0;
1313
03ba32ca
MT		 1314 /* n.b - signed multiplication and division required */
1315 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1316#ifdef CONFIG_X86_64
03ba32ca 1317 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1318#else
03ba32ca 1319 /* do_div() only does unsigned */
8915aa27
MT		 1320 asm("1: idivl %[divisor]\n"
1321 "2: xor %%edx, %%edx\n"
1322 " movl $0, %[faulted]\n"
1323 "3:\n"
1324 ".section .fixup,\"ax\"\n"
1325 "4: movl $1, %[faulted]\n"
1326 " jmp 3b\n"
1327 ".previous\n"
1328
1329 _ASM_EXTABLE(1b, 4b)
1330
1331 : "=A"(usdiff), [faulted] "=r" (faulted)
1332 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1333
5d3cb0f6 1334#endif
03ba32ca
MT		 1335 do_div(elapsed, 1000);
1336 usdiff -= elapsed;
1337 if (usdiff < 0)
1338 usdiff = -usdiff;
8915aa27
MT		 1339
1340 /* idivl overflow => difference is larger than USEC_PER_SEC */
1341 if (faulted)
1342 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1343 } else
1344 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1345
1346 /*
5d3cb0f6
ZA		 1347 * Special case: TSC write with a small delta (1 second) of virtual
1348 * cycle time against real time is interpreted as an attempt to
1349 * synchronize the CPU.
1350 *
1351 * For a reliable TSC, we can match TSC offsets, and for an unstable
1352 * TSC, we add elapsed time in this computation. We could let the
1353 * compensation code attempt to catch up if we fall behind, but
1354 * it's better to try to match offsets from the beginning.
1355 */
02626b6a 1356 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1357 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1358 if (!check_tsc_unstable()) {
e26101b1 1359 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1360 pr_debug("kvm: matched tsc offset for %llu\n", data);
1361 } else {
857e4099 1362 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1363 data += delta;
1364 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1365 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1366 }
b48aa97e 1367 matched = true;
0d3da0d2 1368 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1369 } else {
1370 /*
1371 * We split periods of matched TSC writes into generations.
1372 * For each generation, we track the original measured
1373 * nanosecond time, offset, and write, so if TSCs are in
1374 * sync, we can match exact offset, and if not, we can match
4a969980 1375 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1376 *
1377 * These values are tracked in kvm->arch.cur_xxx variables.
1378 */
1379 kvm->arch.cur_tsc_generation++;
1380 kvm->arch.cur_tsc_nsec = ns;
1381 kvm->arch.cur_tsc_write = data;
1382 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1383 matched = false;
0d3da0d2 1384 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1385 kvm->arch.cur_tsc_generation, data);
f38e098f 1386 }
e26101b1
ZA		 1387
1388 /*
1389 * We also track th most recent recorded KHZ, write and time to
1390 * allow the matching interval to be extended at each write.
1391 */
f38e098f
ZA		 1392 kvm->arch.last_tsc_nsec = ns;
1393 kvm->arch.last_tsc_write = data;
5d3cb0f6 1394 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1395
b183aa58 1396 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1397
1398 /* Keep track of which generation this VCPU has synchronized to */
1399 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1400 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1401 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1402
ba904635
WA		 1403 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1404 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1405 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1406 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1407
1408 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1409 if (!matched) {
b48aa97e 1410 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1411 } else if (!already_matched) {
1412 kvm->arch.nr_vcpus_matched_tsc++;
1413 }
b48aa97e
MT		 1414
1415 kvm_track_tsc_matching(vcpu);
1416 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1417}
e26101b1 1418
99e3e30a
ZA		 1419EXPORT_SYMBOL_GPL(kvm_write_tsc);
1420
d828199e
MT		 1421#ifdef CONFIG_X86_64
1422
1423static cycle_t read_tsc(void)
1424{
1425 cycle_t ret;
1426 u64 last;
1427
1428 /*
1429 * Empirically, a fence (of type that depends on the CPU)
1430 * before rdtsc is enough to ensure that rdtsc is ordered
1431 * with respect to loads. The various CPU manuals are unclear
1432 * as to whether rdtsc can be reordered with later loads,
1433 * but no one has ever seen it happen.
1434 */
1435 rdtsc_barrier();
1436 ret = (cycle_t)vget_cycles();
1437
1438 last = pvclock_gtod_data.clock.cycle_last;
1439
1440 if (likely(ret >= last))
1441 return ret;
1442
1443 /*
1444 * GCC likes to generate cmov here, but this branch is extremely
1445 * predictable (it's just a funciton of time and the likely is
1446 * very likely) and there's a data dependence, so force GCC
1447 * to generate a branch instead. I don't barrier() because
1448 * we don't actually need a barrier, and if this function
1449 * ever gets inlined it will generate worse code.
1450 */
1451 asm volatile ("");
1452 return last;
1453}
1454
1455static inline u64 vgettsc(cycle_t *cycle_now)
1456{
1457 long v;
1458 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1459
1460 *cycle_now = read_tsc();
1461
1462 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1463 return v * gtod->clock.mult;
1464}
1465
cbcf2dd3 1466static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1467{
cbcf2dd3 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1469 unsigned long seq;
d828199e 1470 int mode;
cbcf2dd3 1471 u64 ns;
d828199e 1472
d828199e
MT		 1473 do {
1474 seq = read_seqcount_begin(&gtod->seq);
1475 mode = gtod->clock.vclock_mode;
cbcf2dd3 1476 ns = gtod->nsec_base;
d828199e
MT		 1477 ns += vgettsc(cycle_now);
1478 ns >>= gtod->clock.shift;
cbcf2dd3 1479 ns += gtod->boot_ns;
d828199e 1480 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1481 *t = ns;
d828199e
MT		 1482
1483 return mode;
1484}
1485
1486/* returns true if host is using tsc clocksource */
1487static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1488{
d828199e
MT		 1489 /* checked again under seqlock below */
1490 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1491 return false;
1492
cbcf2dd3 1493 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1494}
1495#endif
1496
1497/*
1498 *
b48aa97e
MT		 1499 * Assuming a stable TSC across physical CPUS, and a stable TSC
1500 * across virtual CPUs, the following condition is possible.
1501 * Each numbered line represents an event visible to both
d828199e
MT		 1502 * CPUs at the next numbered event.
1503 *
1504 * "timespecX" represents host monotonic time. "tscX" represents
1505 * RDTSC value.
1506 *
1507 * VCPU0 on CPU0 | VCPU1 on CPU1
1508 *
1509 * 1. read timespec0,tsc0
1510 * 2. | timespec1 = timespec0 + N
1511 * | tsc1 = tsc0 + M
1512 * 3. transition to guest | transition to guest
1513 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1514 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1515 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1516 *
1517 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1518 *
1519 * - ret0 < ret1
1520 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1521 * ...
1522 * - 0 < N - M => M < N
1523 *
1524 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1525 * always the case (the difference between two distinct xtime instances
1526 * might be smaller then the difference between corresponding TSC reads,
1527 * when updating guest vcpus pvclock areas).
1528 *
1529 * To avoid that problem, do not allow visibility of distinct
1530 * system_timestamp/tsc_timestamp values simultaneously: use a master
1531 * copy of host monotonic time values. Update that master copy
1532 * in lockstep.
1533 *
b48aa97e 1534 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1535 *
1536 */
1537
1538static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1539{
1540#ifdef CONFIG_X86_64
1541 struct kvm_arch *ka = &kvm->arch;
1542 int vclock_mode;
b48aa97e
MT		 1543 bool host_tsc_clocksource, vcpus_matched;
1544
1545 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1546 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1547
1548 /*
1549 * If the host uses TSC clock, then passthrough TSC as stable
1550 * to the guest.
1551 */
b48aa97e 1552 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1553 &ka->master_kernel_ns,
1554 &ka->master_cycle_now);
1555
16a96021 1556 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1557 && !backwards_tsc_observed
1558 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1559
d828199e
MT		 1560 if (ka->use_master_clock)
1561 atomic_set(&kvm_guest_has_master_clock, 1);
1562
1563 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1564 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1565 vcpus_matched);
d828199e
MT		 1566#endif
1567}
1568
2e762ff7
MT		 1569static void kvm_gen_update_masterclock(struct kvm *kvm)
1570{
1571#ifdef CONFIG_X86_64
1572 int i;
1573 struct kvm_vcpu *vcpu;
1574 struct kvm_arch *ka = &kvm->arch;
1575
1576 spin_lock(&ka->pvclock_gtod_sync_lock);
1577 kvm_make_mclock_inprogress_request(kvm);
1578 /* no guest entries from this point */
1579 pvclock_update_vm_gtod_copy(kvm);
1580
1581 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1582 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1583
1584 /* guest entries allowed */
1585 kvm_for_each_vcpu(i, vcpu, kvm)
1586 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1587
1588 spin_unlock(&ka->pvclock_gtod_sync_lock);
1589#endif
1590}
1591
34c238a1 1592static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1593{
d828199e 1594 unsigned long flags, this_tsc_khz;
18068523 1595 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1596 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1597 s64 kernel_ns;
d828199e 1598 u64 tsc_timestamp, host_tsc;
0b79459b 1599 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1600 u8 pvclock_flags;
d828199e
MT		 1601 bool use_master_clock;
1602
1603 kernel_ns = 0;
1604 host_tsc = 0;
18068523 1605
d828199e
MT		 1606 /*
1607 * If the host uses TSC clock, then passthrough TSC as stable
1608 * to the guest.
1609 */
1610 spin_lock(&ka->pvclock_gtod_sync_lock);
1611 use_master_clock = ka->use_master_clock;
1612 if (use_master_clock) {
1613 host_tsc = ka->master_cycle_now;
1614 kernel_ns = ka->master_kernel_ns;
1615 }
1616 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1617
1618 /* Keep irq disabled to prevent changes to the clock */
1619 local_irq_save(flags);
89cbc767 1620 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1621 if (unlikely(this_tsc_khz == 0)) {
1622 local_irq_restore(flags);
1623 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1624 return 1;
1625 }
d828199e
MT		 1626 if (!use_master_clock) {
1627 host_tsc = native_read_tsc();
1628 kernel_ns = get_kernel_ns();
1629 }
1630
1631 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1632
c285545f
ZA		 1633 /*
1634 * We may have to catch up the TSC to match elapsed wall clock
1635 * time for two reasons, even if kvmclock is used.
1636 * 1) CPU could have been running below the maximum TSC rate
1637 * 2) Broken TSC compensation resets the base at each VCPU
1638 * entry to avoid unknown leaps of TSC even when running
1639 * again on the same CPU. This may cause apparent elapsed
1640 * time to disappear, and the guest to stand still or run
1641 * very slowly.
1642 */
1643 if (vcpu->tsc_catchup) {
1644 u64 tsc = compute_guest_tsc(v, kernel_ns);
1645 if (tsc > tsc_timestamp) {
f1e2b260 1646 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1647 tsc_timestamp = tsc;
1648 }
50d0a0f9
GH		 1649 }
1650
18068523
GOC		 1651 local_irq_restore(flags);
1652
0b79459b 1653 if (!vcpu->pv_time_enabled)
c285545f 1654 return 0;
18068523 1655
e48672fa 1656 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1657 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1658 &vcpu->hv_clock.tsc_shift,
1659 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1660 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1661 }
1662
1663 /* With all the info we got, fill in the values */
1d5f066e 1664 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1665 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1666 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1667
09a0c3f1
OH		 1668 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1669 &guest_hv_clock, sizeof(guest_hv_clock))))
1670 return 0;
1671
18068523
GOC		 1672 /*
1673 * The interface expects us to write an even number signaling that the
1674 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1675 * state, we just increase by 2 at the end.
18068523 1676 */
09a0c3f1 1677 vcpu->hv_clock.version = guest_hv_clock.version + 2;
78c0337a
MT		 1678
1679 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1680 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1681
1682 if (vcpu->pvclock_set_guest_stopped_request) {
1683 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1684 vcpu->pvclock_set_guest_stopped_request = false;
1685 }
1686
d828199e
MT		 1687 /* If the host uses TSC clocksource, then it is stable */
1688 if (use_master_clock)
1689 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1690
78c0337a
MT		 1691 vcpu->hv_clock.flags = pvclock_flags;
1692
ce1a5e60
DM		 1693 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1694
0b79459b
AH		 1695 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1696 &vcpu->hv_clock,
1697 sizeof(vcpu->hv_clock));
8cfdc000 1698 return 0;
c8076604
GH		 1699}
1700
0061d53d
MT		 1701/*
1702 * kvmclock updates which are isolated to a given vcpu, such as
1703 * vcpu->cpu migration, should not allow system_timestamp from
1704 * the rest of the vcpus to remain static. Otherwise ntp frequency
1705 * correction applies to one vcpu's system_timestamp but not
1706 * the others.
1707 *
1708 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1709 * We need to rate-limit these requests though, as they can
1710 * considerably slow guests that have a large number of vcpus.
1711 * The time for a remote vcpu to update its kvmclock is bound
1712 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1713 */
1714
7e44e449
AJ		 1715#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1716
1717static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1718{
1719 int i;
7e44e449
AJ		 1720 struct delayed_work *dwork = to_delayed_work(work);
1721 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1722 kvmclock_update_work);
1723 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1724 struct kvm_vcpu *vcpu;
1725
1726 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1728 kvm_vcpu_kick(vcpu);
1729 }
1730}
1731
7e44e449
AJ		 1732static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1733{
1734 struct kvm *kvm = v->kvm;
1735
105b21bb 1736 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1737 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1738 KVMCLOCK_UPDATE_DELAY);
1739}
1740
332967a3
AJ		 1741#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1742
1743static void kvmclock_sync_fn(struct work_struct *work)
1744{
1745 struct delayed_work *dwork = to_delayed_work(work);
1746 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1747 kvmclock_sync_work);
1748 struct kvm *kvm = container_of(ka, struct kvm, arch);
1749
1750 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1751 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1752 KVMCLOCK_SYNC_PERIOD);
1753}
1754
9ba075a6
AK		 1755static bool msr_mtrr_valid(unsigned msr)
1756{
1757 switch (msr) {
1758 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1759 case MSR_MTRRfix64K_00000:
1760 case MSR_MTRRfix16K_80000:
1761 case MSR_MTRRfix16K_A0000:
1762 case MSR_MTRRfix4K_C0000:
1763 case MSR_MTRRfix4K_C8000:
1764 case MSR_MTRRfix4K_D0000:
1765 case MSR_MTRRfix4K_D8000:
1766 case MSR_MTRRfix4K_E0000:
1767 case MSR_MTRRfix4K_E8000:
1768 case MSR_MTRRfix4K_F0000:
1769 case MSR_MTRRfix4K_F8000:
1770 case MSR_MTRRdefType:
1771 case MSR_IA32_CR_PAT:
1772 return true;
1773 case 0x2f8:
1774 return true;
1775 }
1776 return false;
1777}
1778
d6289b93
MT		 1779static bool valid_pat_type(unsigned t)
1780{
1781 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1782}
1783
1784static bool valid_mtrr_type(unsigned t)
1785{
1786 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1787}
1788
4566654b 1789bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1790{
1791 int i;
fd275235 1792 u64 mask;
d6289b93
MT		 1793
1794 if (!msr_mtrr_valid(msr))
1795 return false;
1796
1797 if (msr == MSR_IA32_CR_PAT) {
1798 for (i = 0; i < 8; i++)
1799 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1800 return false;
1801 return true;
1802 } else if (msr == MSR_MTRRdefType) {
1803 if (data & ~0xcff)
1804 return false;
1805 return valid_mtrr_type(data & 0xff);
1806 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1807 for (i = 0; i < 8 ; i++)
1808 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1809 return false;
1810 return true;
1811 }
1812
1813 /* variable MTRRs */
adfb5d27
WL		 1814 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1815
fd275235 1816 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1817 if ((msr & 1) == 0) {
adfb5d27 1818 /* MTRR base */
d7a2a246
WL		 1819 if (!valid_mtrr_type(data & 0xff))
1820 return false;
1821 mask |= 0xf00;
1822 } else
1823 /* MTRR mask */
1824 mask |= 0x7ff;
1825 if (data & mask) {
1826 kvm_inject_gp(vcpu, 0);
1827 return false;
1828 }
1829
adfb5d27 1830 return true;
d6289b93 1831}
4566654b 1832EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1833
9ba075a6
AK		 1834static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1835{
0bed3b56
SY		 1836 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1837
4566654b 1838 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1839 return 1;
1840
0bed3b56
SY		 1841 if (msr == MSR_MTRRdefType) {
1842 vcpu->arch.mtrr_state.def_type = data;
1843 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1844 } else if (msr == MSR_MTRRfix64K_00000)
1845 p[0] = data;
1846 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1847 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1848 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1849 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1850 else if (msr == MSR_IA32_CR_PAT)
1851 vcpu->arch.pat = data;
1852 else { /* Variable MTRRs */
1853 int idx, is_mtrr_mask;
1854 u64 *pt;
1855
1856 idx = (msr - 0x200) / 2;
1857 is_mtrr_mask = msr - 0x200 - 2 * idx;
1858 if (!is_mtrr_mask)
1859 pt =
1860 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1861 else
1862 pt =
1863 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1864 *pt = data;
1865 }
1866
1867 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1868 return 0;
1869}
15c4a640 1870
890ca9ae 1871static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1872{
890ca9ae
HY		 1873 u64 mcg_cap = vcpu->arch.mcg_cap;
1874 unsigned bank_num = mcg_cap & 0xff;
1875
15c4a640 1876 switch (msr) {
15c4a640 1877 case MSR_IA32_MCG_STATUS:
890ca9ae 1878 vcpu->arch.mcg_status = data;
15c4a640 1879 break;
c7ac679c 1880 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1881 if (!(mcg_cap & MCG_CTL_P))
1882 return 1;
1883 if (data != 0 && data != ~(u64)0)
1884 return -1;
1885 vcpu->arch.mcg_ctl = data;
1886 break;
1887 default:
1888 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1889 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1890 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1891 /* only 0 or all 1s can be written to IA32_MCi_CTL
1892 * some Linux kernels though clear bit 10 in bank 4 to
1893 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1894 * this to avoid an uncatched #GP in the guest
1895 */
890ca9ae 1896 if ((offset & 0x3) == 0 &&
114be429 1897 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1898 return -1;
1899 vcpu->arch.mce_banks[offset] = data;
1900 break;
1901 }
1902 return 1;
1903 }
1904 return 0;
1905}
1906
ffde22ac
ES		 1907static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1908{
1909 struct kvm *kvm = vcpu->kvm;
1910 int lm = is_long_mode(vcpu);
1911 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1912 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1913 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1914 : kvm->arch.xen_hvm_config.blob_size_32;
1915 u32 page_num = data & ~PAGE_MASK;
1916 u64 page_addr = data & PAGE_MASK;
1917 u8 *page;
1918 int r;
1919
1920 r = -E2BIG;
1921 if (page_num >= blob_size)
1922 goto out;
1923 r = -ENOMEM;
ff5c2c03
SL		 1924 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1925 if (IS_ERR(page)) {
1926 r = PTR_ERR(page);
ffde22ac 1927 goto out;
ff5c2c03 1928 }
ffde22ac
ES		 1929 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1930 goto out_free;
1931 r = 0;
1932out_free:
1933 kfree(page);
1934out:
1935 return r;
1936}
1937
55cd8e5a
GN		 1938static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1939{
1940 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1941}
1942
1943static bool kvm_hv_msr_partition_wide(u32 msr)
1944{
1945 bool r = false;
1946 switch (msr) {
1947 case HV_X64_MSR_GUEST_OS_ID:
1948 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1949 case HV_X64_MSR_REFERENCE_TSC:
1950 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1951 r = true;
1952 break;
1953 }
1954
1955 return r;
1956}
1957
1958static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1959{
1960 struct kvm *kvm = vcpu->kvm;
1961
1962 switch (msr) {
1963 case HV_X64_MSR_GUEST_OS_ID:
1964 kvm->arch.hv_guest_os_id = data;
1965 /* setting guest os id to zero disables hypercall page */
1966 if (!kvm->arch.hv_guest_os_id)
1967 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1968 break;
1969 case HV_X64_MSR_HYPERCALL: {
1970 u64 gfn;
1971 unsigned long addr;
1972 u8 instructions[4];
1973
1974 /* if guest os id is not set hypercall should remain disabled */
1975 if (!kvm->arch.hv_guest_os_id)
1976 break;
1977 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1978 kvm->arch.hv_hypercall = data;
1979 break;
1980 }
1981 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1982 addr = gfn_to_hva(kvm, gfn);
1983 if (kvm_is_error_hva(addr))
1984 return 1;
1985 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1986 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1987 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1988 return 1;
1989 kvm->arch.hv_hypercall = data;
b94b64c9 1990 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1991 break;
1992 }
e984097b
VR		 1993 case HV_X64_MSR_REFERENCE_TSC: {
1994 u64 gfn;
1995 HV_REFERENCE_TSC_PAGE tsc_ref;
1996 memset(&tsc_ref, 0, sizeof(tsc_ref));
1997 kvm->arch.hv_tsc_page = data;
1998 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1999 break;
2000 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2001 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2002 &tsc_ref, sizeof(tsc_ref)))
2003 return 1;
2004 mark_page_dirty(kvm, gfn);
2005 break;
2006 }
55cd8e5a 2007 default:
a737f256
CD		 2008 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2009 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2010 return 1;
2011 }
2012 return 0;
2013}
2014
2015static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2016{
10388a07
GN		 2017 switch (msr) {
2018 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2019 u64 gfn;
10388a07 2020 unsigned long addr;
55cd8e5a 2021
10388a07
GN		 2022 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2023 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2024 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2025 return 1;
10388a07
GN		 2026 break;
2027 }
b3af1e88
VR		 2028 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2029 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2030 if (kvm_is_error_hva(addr))
2031 return 1;
8b0cedff 2032 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2033 return 1;
2034 vcpu->arch.hv_vapic = data;
b3af1e88 2035 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2036 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2037 return 1;
10388a07
GN		 2038 break;
2039 }
2040 case HV_X64_MSR_EOI:
2041 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2042 case HV_X64_MSR_ICR:
2043 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2044 case HV_X64_MSR_TPR:
2045 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2046 default:
a737f256
CD		 2047 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2048 "data 0x%llx\n", msr, data);
10388a07
GN		 2049 return 1;
2050 }
2051
2052 return 0;
55cd8e5a
GN		 2053}
2054
344d9588
GN		 2055static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2056{
2057 gpa_t gpa = data & ~0x3f;
2058
4a969980 2059 /* Bits 2:5 are reserved, Should be zero */
6adba527 2060 if (data & 0x3c)
344d9588
GN		 2061 return 1;
2062
2063 vcpu->arch.apf.msr_val = data;
2064
2065 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2066 kvm_clear_async_pf_completion_queue(vcpu);
2067 kvm_async_pf_hash_reset(vcpu);
2068 return 0;
2069 }
2070
8f964525
AH		 2071 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2072 sizeof(u32)))
344d9588
GN		 2073 return 1;
2074
6adba527 2075 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2076 kvm_async_pf_wakeup_all(vcpu);
2077 return 0;
2078}
2079
12f9a48f
GC		 2080static void kvmclock_reset(struct kvm_vcpu *vcpu)
2081{
0b79459b 2082 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2083}
2084
c9aaa895
GC		 2085static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2086{
2087 u64 delta;
2088
2089 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2090 return;
2091
2092 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2093 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2094 vcpu->arch.st.accum_steal = delta;
2095}
2096
2097static void record_steal_time(struct kvm_vcpu *vcpu)
2098{
2099 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2100 return;
2101
2102 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2103 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2104 return;
2105
2106 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2107 vcpu->arch.st.steal.version += 2;
2108 vcpu->arch.st.accum_steal = 0;
2109
2110 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2111 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2112}
2113
8fe8ab46 2114int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2115{
5753785f 2116 bool pr = false;
8fe8ab46
WA		 2117 u32 msr = msr_info->index;
2118 u64 data = msr_info->data;
5753785f 2119
15c4a640 2120 switch (msr) {
2e32b719
BP		 2121 case MSR_AMD64_NB_CFG:
2122 case MSR_IA32_UCODE_REV:
2123 case MSR_IA32_UCODE_WRITE:
2124 case MSR_VM_HSAVE_PA:
2125 case MSR_AMD64_PATCH_LOADER:
2126 case MSR_AMD64_BU_CFG2:
2127 break;
2128
15c4a640 2129 case MSR_EFER:
b69e8cae 2130 return set_efer(vcpu, data);
8f1589d9
AP		 2131 case MSR_K7_HWCR:
2132 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2133 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2134 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2135 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2136 if (data != 0) {
a737f256
CD		 2137 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2138 data);
8f1589d9
AP		 2139 return 1;
2140 }
15c4a640 2141 break;
f7c6d140
AP		 2142 case MSR_FAM10H_MMIO_CONF_BASE:
2143 if (data != 0) {
a737f256
CD		 2144 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2145 "0x%llx\n", data);
f7c6d140
AP		 2146 return 1;
2147 }
15c4a640 2148 break;
b5e2fec0
AG		 2149 case MSR_IA32_DEBUGCTLMSR:
2150 if (!data) {
2151 /* We support the non-activated case already */
2152 break;
2153 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2154 /* Values other than LBR and BTF are vendor-specific,
2155 thus reserved and should throw a #GP */
2156 return 1;
2157 }
a737f256
CD		 2158 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2159 __func__, data);
b5e2fec0 2160 break;
9ba075a6
AK		 2161 case 0x200 ... 0x2ff:
2162 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2163 case MSR_IA32_APICBASE:
58cb628d 2164 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2165 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2166 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2167 case MSR_IA32_TSCDEADLINE:
2168 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2169 break;
ba904635
WA		 2170 case MSR_IA32_TSC_ADJUST:
2171 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2172 if (!msr_info->host_initiated) {
d913b904 2173 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2174 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2175 }
2176 vcpu->arch.ia32_tsc_adjust_msr = data;
2177 }
2178 break;
15c4a640 2179 case MSR_IA32_MISC_ENABLE:
ad312c7c 2180 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2181 break;
11c6bffa 2182 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2183 case MSR_KVM_WALL_CLOCK:
2184 vcpu->kvm->arch.wall_clock = data;
2185 kvm_write_wall_clock(vcpu->kvm, data);
2186 break;
11c6bffa 2187 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2188 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2189 u64 gpa_offset;
54750f2c
MT		 2190 struct kvm_arch *ka = &vcpu->kvm->arch;
2191
12f9a48f 2192 kvmclock_reset(vcpu);
18068523 2193
54750f2c
MT		 2194 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2195 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2196
2197 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2198 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2199 &vcpu->requests);
2200
2201 ka->boot_vcpu_runs_old_kvmclock = tmp;
2202 }
2203
18068523 2204 vcpu->arch.time = data;
0061d53d 2205 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2206
2207 /* we verify if the enable bit is set... */
2208 if (!(data & 1))
2209 break;
2210
0b79459b 2211 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2212
0b79459b 2213 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2214 &vcpu->arch.pv_time, data & ~1ULL,
2215 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2216 vcpu->arch.pv_time_enabled = false;
2217 else
2218 vcpu->arch.pv_time_enabled = true;
32cad84f 2219
18068523
GOC		 2220 break;
2221 }
344d9588
GN		 2222 case MSR_KVM_ASYNC_PF_EN:
2223 if (kvm_pv_enable_async_pf(vcpu, data))
2224 return 1;
2225 break;
c9aaa895
GC		 2226 case MSR_KVM_STEAL_TIME:
2227
2228 if (unlikely(!sched_info_on()))
2229 return 1;
2230
2231 if (data & KVM_STEAL_RESERVED_MASK)
2232 return 1;
2233
2234 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2235 data & KVM_STEAL_VALID_BITS,
2236 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2237 return 1;
2238
2239 vcpu->arch.st.msr_val = data;
2240
2241 if (!(data & KVM_MSR_ENABLED))
2242 break;
2243
2244 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2245
2246 preempt_disable();
2247 accumulate_steal_time(vcpu);
2248 preempt_enable();
2249
2250 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2251
2252 break;
ae7a2a3f
MT		 2253 case MSR_KVM_PV_EOI_EN:
2254 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2255 return 1;
2256 break;
c9aaa895 2257
890ca9ae
HY		 2258 case MSR_IA32_MCG_CTL:
2259 case MSR_IA32_MCG_STATUS:
81760dcc 2260 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2261 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2262
2263 /* Performance counters are not protected by a CPUID bit,
2264 * so we should check all of them in the generic path for the sake of
2265 * cross vendor migration.
2266 * Writing a zero into the event select MSRs disables them,
2267 * which we perfectly emulate ;-). Any other value should be at least
2268 * reported, some guests depend on them.
2269 */
71db6023
AP		 2270 case MSR_K7_EVNTSEL0:
2271 case MSR_K7_EVNTSEL1:
2272 case MSR_K7_EVNTSEL2:
2273 case MSR_K7_EVNTSEL3:
2274 if (data != 0)
a737f256
CD		 2275 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2276 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2277 break;
2278 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2279 * so we ignore writes to make it happy.
2280 */
71db6023
AP		 2281 case MSR_K7_PERFCTR0:
2282 case MSR_K7_PERFCTR1:
2283 case MSR_K7_PERFCTR2:
2284 case MSR_K7_PERFCTR3:
a737f256
CD		 2285 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2286 "0x%x data 0x%llx\n", msr, data);
71db6023 2287 break;
5753785f
GN		 2288 case MSR_P6_PERFCTR0:
2289 case MSR_P6_PERFCTR1:
2290 pr = true;
2291 case MSR_P6_EVNTSEL0:
2292 case MSR_P6_EVNTSEL1:
2293 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2294 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2295
2296 if (pr || data != 0)
a737f256
CD		 2297 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2298 "0x%x data 0x%llx\n", msr, data);
5753785f 2299 break;
84e0cefa
JS		 2300 case MSR_K7_CLK_CTL:
2301 /*
2302 * Ignore all writes to this no longer documented MSR.
2303 * Writes are only relevant for old K7 processors,
2304 * all pre-dating SVM, but a recommended workaround from
4a969980 2305 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2306 * affected processor models on the command line, hence
2307 * the need to ignore the workaround.
2308 */
2309 break;
55cd8e5a
GN		 2310 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2311 if (kvm_hv_msr_partition_wide(msr)) {
2312 int r;
2313 mutex_lock(&vcpu->kvm->lock);
2314 r = set_msr_hyperv_pw(vcpu, msr, data);
2315 mutex_unlock(&vcpu->kvm->lock);
2316 return r;
2317 } else
2318 return set_msr_hyperv(vcpu, msr, data);
2319 break;
91c9c3ed 2320 case MSR_IA32_BBL_CR_CTL3:
2321 /* Drop writes to this legacy MSR -- see rdmsr
2322 * counterpart for further detail.
2323 */
a737f256 2324 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2325 break;
2b036c6b
BO		 2326 case MSR_AMD64_OSVW_ID_LENGTH:
2327 if (!guest_cpuid_has_osvw(vcpu))
2328 return 1;
2329 vcpu->arch.osvw.length = data;
2330 break;
2331 case MSR_AMD64_OSVW_STATUS:
2332 if (!guest_cpuid_has_osvw(vcpu))
2333 return 1;
2334 vcpu->arch.osvw.status = data;
2335 break;
15c4a640 2336 default:
ffde22ac
ES		 2337 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2338 return xen_hvm_config(vcpu, data);
f5132b01 2339 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2340 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2341 if (!ignore_msrs) {
a737f256
CD		 2342 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2343 msr, data);
ed85c068
AP		 2344 return 1;
2345 } else {
a737f256
CD		 2346 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2347 msr, data);
ed85c068
AP		 2348 break;
2349 }
15c4a640
CO		 2350 }
2351 return 0;
2352}
2353EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2354
2355
2356/*
2357 * Reads an msr value (of 'msr_index') into 'pdata'.
2358 * Returns 0 on success, non-0 otherwise.
2359 * Assumes vcpu_load() was already called.
2360 */
2361int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2362{
2363 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2364}
ff651cb6 2365EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2366
9ba075a6
AK		 2367static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2368{
0bed3b56
SY		 2369 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2370
9ba075a6
AK		 2371 if (!msr_mtrr_valid(msr))
2372 return 1;
2373
0bed3b56
SY		 2374 if (msr == MSR_MTRRdefType)
2375 *pdata = vcpu->arch.mtrr_state.def_type +
2376 (vcpu->arch.mtrr_state.enabled << 10);
2377 else if (msr == MSR_MTRRfix64K_00000)
2378 *pdata = p[0];
2379 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2380 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2381 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2382 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2383 else if (msr == MSR_IA32_CR_PAT)
2384 *pdata = vcpu->arch.pat;
2385 else { /* Variable MTRRs */
2386 int idx, is_mtrr_mask;
2387 u64 *pt;
2388
2389 idx = (msr - 0x200) / 2;
2390 is_mtrr_mask = msr - 0x200 - 2 * idx;
2391 if (!is_mtrr_mask)
2392 pt =
2393 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2394 else
2395 pt =
2396 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2397 *pdata = *pt;
2398 }
2399
9ba075a6
AK		 2400 return 0;
2401}
2402
890ca9ae 2403static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2404{
2405 u64 data;
890ca9ae
HY		 2406 u64 mcg_cap = vcpu->arch.mcg_cap;
2407 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2408
2409 switch (msr) {
15c4a640
CO		 2410 case MSR_IA32_P5_MC_ADDR:
2411 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2412 data = 0;
2413 break;
15c4a640 2414 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2415 data = vcpu->arch.mcg_cap;
2416 break;
c7ac679c 2417 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2418 if (!(mcg_cap & MCG_CTL_P))
2419 return 1;
2420 data = vcpu->arch.mcg_ctl;
2421 break;
2422 case MSR_IA32_MCG_STATUS:
2423 data = vcpu->arch.mcg_status;
2424 break;
2425 default:
2426 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2427 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2428 u32 offset = msr - MSR_IA32_MC0_CTL;
2429 data = vcpu->arch.mce_banks[offset];
2430 break;
2431 }
2432 return 1;
2433 }
2434 *pdata = data;
2435 return 0;
2436}
2437
55cd8e5a
GN		 2438static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2439{
2440 u64 data = 0;
2441 struct kvm *kvm = vcpu->kvm;
2442
2443 switch (msr) {
2444 case HV_X64_MSR_GUEST_OS_ID:
2445 data = kvm->arch.hv_guest_os_id;
2446 break;
2447 case HV_X64_MSR_HYPERCALL:
2448 data = kvm->arch.hv_hypercall;
2449 break;
e984097b
VR		 2450 case HV_X64_MSR_TIME_REF_COUNT: {
2451 data =
2452 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2453 break;
2454 }
2455 case HV_X64_MSR_REFERENCE_TSC:
2456 data = kvm->arch.hv_tsc_page;
2457 break;
55cd8e5a 2458 default:
a737f256 2459 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2460 return 1;
2461 }
2462
2463 *pdata = data;
2464 return 0;
2465}
2466
2467static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2468{
2469 u64 data = 0;
2470
2471 switch (msr) {
2472 case HV_X64_MSR_VP_INDEX: {
2473 int r;
2474 struct kvm_vcpu *v;
684851a1
TY		 2475 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2476 if (v == vcpu) {
55cd8e5a 2477 data = r;
684851a1
TY		 2478 break;
2479 }
2480 }
55cd8e5a
GN		 2481 break;
2482 }
10388a07
GN		 2483 case HV_X64_MSR_EOI:
2484 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2485 case HV_X64_MSR_ICR:
2486 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2487 case HV_X64_MSR_TPR:
2488 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2489 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2490 data = vcpu->arch.hv_vapic;
2491 break;
55cd8e5a 2492 default:
a737f256 2493 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2494 return 1;
2495 }
2496 *pdata = data;
2497 return 0;
2498}
2499
890ca9ae
HY		 2500int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2501{
2502 u64 data;
2503
2504 switch (msr) {
890ca9ae 2505 case MSR_IA32_PLATFORM_ID:
15c4a640 2506 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2507 case MSR_IA32_DEBUGCTLMSR:
2508 case MSR_IA32_LASTBRANCHFROMIP:
2509 case MSR_IA32_LASTBRANCHTOIP:
2510 case MSR_IA32_LASTINTFROMIP:
2511 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2512 case MSR_K8_SYSCFG:
2513 case MSR_K7_HWCR:
61a6bd67 2514 case MSR_VM_HSAVE_PA:
9e699624 2515 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2516 case MSR_K7_EVNTSEL1:
2517 case MSR_K7_EVNTSEL2:
2518 case MSR_K7_EVNTSEL3:
1f3ee616 2519 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2520 case MSR_K7_PERFCTR1:
2521 case MSR_K7_PERFCTR2:
2522 case MSR_K7_PERFCTR3:
1fdbd48c 2523 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2524 case MSR_AMD64_NB_CFG:
f7c6d140 2525 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2526 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2527 data = 0;
2528 break;
5753785f
GN		 2529 case MSR_P6_PERFCTR0:
2530 case MSR_P6_PERFCTR1:
2531 case MSR_P6_EVNTSEL0:
2532 case MSR_P6_EVNTSEL1:
2533 if (kvm_pmu_msr(vcpu, msr))
2534 return kvm_pmu_get_msr(vcpu, msr, pdata);
2535 data = 0;
2536 break;
742bc670
MT		 2537 case MSR_IA32_UCODE_REV:
2538 data = 0x100000000ULL;
2539 break;
9ba075a6
AK		 2540 case MSR_MTRRcap:
2541 data = 0x500 | KVM_NR_VAR_MTRR;
2542 break;
2543 case 0x200 ... 0x2ff:
2544 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2545 case 0xcd: /* fsb frequency */
2546 data = 3;
2547 break;
7b914098
JS		 2548 /*
2549 * MSR_EBC_FREQUENCY_ID
2550 * Conservative value valid for even the basic CPU models.
2551 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2552 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2553 * and 266MHz for model 3, or 4. Set Core Clock
2554 * Frequency to System Bus Frequency Ratio to 1 (bits
2555 * 31:24) even though these are only valid for CPU
2556 * models > 2, however guests may end up dividing or
2557 * multiplying by zero otherwise.
2558 */
2559 case MSR_EBC_FREQUENCY_ID:
2560 data = 1 << 24;
2561 break;
15c4a640
CO		 2562 case MSR_IA32_APICBASE:
2563 data = kvm_get_apic_base(vcpu);
2564 break;
0105d1a5
GN		 2565 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2566 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2567 break;
a3e06bbe
LJ		 2568 case MSR_IA32_TSCDEADLINE:
2569 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2570 break;
ba904635
WA		 2571 case MSR_IA32_TSC_ADJUST:
2572 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2573 break;
15c4a640 2574 case MSR_IA32_MISC_ENABLE:
ad312c7c 2575 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2576 break;
847f0ad8
AG		 2577 case MSR_IA32_PERF_STATUS:
2578 /* TSC increment by tick */
2579 data = 1000ULL;
2580 /* CPU multiplier */
2581 data |= (((uint64_t)4ULL) << 40);
2582 break;
15c4a640 2583 case MSR_EFER:
f6801dff 2584 data = vcpu->arch.efer;
15c4a640 2585 break;
18068523 2586 case MSR_KVM_WALL_CLOCK:
11c6bffa 2587 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2588 data = vcpu->kvm->arch.wall_clock;
2589 break;
2590 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2591 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2592 data = vcpu->arch.time;
2593 break;
344d9588
GN		 2594 case MSR_KVM_ASYNC_PF_EN:
2595 data = vcpu->arch.apf.msr_val;
2596 break;
c9aaa895
GC		 2597 case MSR_KVM_STEAL_TIME:
2598 data = vcpu->arch.st.msr_val;
2599 break;
1d92128f
MT		 2600 case MSR_KVM_PV_EOI_EN:
2601 data = vcpu->arch.pv_eoi.msr_val;
2602 break;
890ca9ae
HY		 2603 case MSR_IA32_P5_MC_ADDR:
2604 case MSR_IA32_P5_MC_TYPE:
2605 case MSR_IA32_MCG_CAP:
2606 case MSR_IA32_MCG_CTL:
2607 case MSR_IA32_MCG_STATUS:
81760dcc 2608 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2609 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2610 case MSR_K7_CLK_CTL:
2611 /*
2612 * Provide expected ramp-up count for K7. All other
2613 * are set to zero, indicating minimum divisors for
2614 * every field.
2615 *
2616 * This prevents guest kernels on AMD host with CPU
2617 * type 6, model 8 and higher from exploding due to
2618 * the rdmsr failing.
2619 */
2620 data = 0x20000000;
2621 break;
55cd8e5a
GN		 2622 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2623 if (kvm_hv_msr_partition_wide(msr)) {
2624 int r;
2625 mutex_lock(&vcpu->kvm->lock);
2626 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2627 mutex_unlock(&vcpu->kvm->lock);
2628 return r;
2629 } else
2630 return get_msr_hyperv(vcpu, msr, pdata);
2631 break;
91c9c3ed 2632 case MSR_IA32_BBL_CR_CTL3:
2633 /* This legacy MSR exists but isn't fully documented in current
2634 * silicon. It is however accessed by winxp in very narrow
2635 * scenarios where it sets bit #19, itself documented as
2636 * a "reserved" bit. Best effort attempt to source coherent
2637 * read data here should the balance of the register be
2638 * interpreted by the guest:
2639 *
2640 * L2 cache control register 3: 64GB range, 256KB size,
2641 * enabled, latency 0x1, configured
2642 */
2643 data = 0xbe702111;
2644 break;
2b036c6b
BO		 2645 case MSR_AMD64_OSVW_ID_LENGTH:
2646 if (!guest_cpuid_has_osvw(vcpu))
2647 return 1;
2648 data = vcpu->arch.osvw.length;
2649 break;
2650 case MSR_AMD64_OSVW_STATUS:
2651 if (!guest_cpuid_has_osvw(vcpu))
2652 return 1;
2653 data = vcpu->arch.osvw.status;
2654 break;
15c4a640 2655 default:
f5132b01
GN		 2656 if (kvm_pmu_msr(vcpu, msr))
2657 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2658 if (!ignore_msrs) {
a737f256 2659 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2660 return 1;
2661 } else {
a737f256 2662 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2663 data = 0;
2664 }
2665 break;
15c4a640
CO		 2666 }
2667 *pdata = data;
2668 return 0;
2669}
2670EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2671
313a3dc7
CO		 2672/*
2673 * Read or write a bunch of msrs. All parameters are kernel addresses.
2674 *
2675 * @return number of msrs set successfully.
2676 */
2677static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2678 struct kvm_msr_entry *entries,
2679 int (*do_msr)(struct kvm_vcpu *vcpu,
2680 unsigned index, u64 *data))
2681{
f656ce01 2682 int i, idx;
313a3dc7 2683
f656ce01 2684 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2685 for (i = 0; i < msrs->nmsrs; ++i)
2686 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2687 break;
f656ce01 2688 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2689
313a3dc7
CO		 2690 return i;
2691}
2692
2693/*
2694 * Read or write a bunch of msrs. Parameters are user addresses.
2695 *
2696 * @return number of msrs set successfully.
2697 */
2698static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2699 int (*do_msr)(struct kvm_vcpu *vcpu,
2700 unsigned index, u64 *data),
2701 int writeback)
2702{
2703 struct kvm_msrs msrs;
2704 struct kvm_msr_entry *entries;
2705 int r, n;
2706 unsigned size;
2707
2708 r = -EFAULT;
2709 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2710 goto out;
2711
2712 r = -E2BIG;
2713 if (msrs.nmsrs >= MAX_IO_MSRS)
2714 goto out;
2715
313a3dc7 2716 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2717 entries = memdup_user(user_msrs->entries, size);
2718 if (IS_ERR(entries)) {
2719 r = PTR_ERR(entries);
313a3dc7 2720 goto out;
ff5c2c03 2721 }
313a3dc7
CO		 2722
2723 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2724 if (r < 0)
2725 goto out_free;
2726
2727 r = -EFAULT;
2728 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2729 goto out_free;
2730
2731 r = n;
2732
2733out_free:
7a73c028 2734 kfree(entries);
313a3dc7
CO		 2735out:
2736 return r;
2737}
2738
784aa3d7 2739int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2740{
2741 int r;
2742
2743 switch (ext) {
2744 case KVM_CAP_IRQCHIP:
2745 case KVM_CAP_HLT:
2746 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2747 case KVM_CAP_SET_TSS_ADDR:
07716717 2748 case KVM_CAP_EXT_CPUID:
9c15bb1d 2749 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2750 case KVM_CAP_CLOCKSOURCE:
7837699f 2751 case KVM_CAP_PIT:
a28e4f5a 2752 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2753 case KVM_CAP_MP_STATE:
ed848624 2754 case KVM_CAP_SYNC_MMU:
a355c85c 2755 case KVM_CAP_USER_NMI:
52d939a0 2756 case KVM_CAP_REINJECT_CONTROL:
4925663a 2757 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2758 case KVM_CAP_IRQFD:
d34e6b17 2759 case KVM_CAP_IOEVENTFD:
f848a5a8 2760 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2761 case KVM_CAP_PIT2:
e9f42757 2762 case KVM_CAP_PIT_STATE2:
b927a3ce 2763 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2764 case KVM_CAP_XEN_HVM:
afbcf7ab 2765 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2766 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2767 case KVM_CAP_HYPERV:
10388a07 2768 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2769 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2770 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2771 case KVM_CAP_DEBUGREGS:
d2be1651 2772 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2773 case KVM_CAP_XSAVE:
344d9588 2774 case KVM_CAP_ASYNC_PF:
92a1f12d 2775 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2776 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2777 case KVM_CAP_READONLY_MEM:
5f66b620 2778 case KVM_CAP_HYPERV_TIME:
100943c5 2779 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2780 case KVM_CAP_TSC_DEADLINE_TIMER:
2a5bab10
AW		 2781#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2782 case KVM_CAP_ASSIGN_DEV_IRQ:
2783 case KVM_CAP_PCI_2_3:
2784#endif
018d00d2
ZX		 2785 r = 1;
2786 break;
542472b5
LV		 2787 case KVM_CAP_COALESCED_MMIO:
2788 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2789 break;
774ead3a
AK		 2790 case KVM_CAP_VAPIC:
2791 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2792 break;
f725230a 2793 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2794 r = KVM_SOFT_MAX_VCPUS;
2795 break;
2796 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2797 r = KVM_MAX_VCPUS;
2798 break;
a988b910 2799 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2800 r = KVM_USER_MEM_SLOTS;
a988b910 2801 break;
a68a6a72
MT		 2802 case KVM_CAP_PV_MMU: /* obsolete */
2803 r = 0;
2f333bcb 2804 break;
4cee4b72 2805#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2806 case KVM_CAP_IOMMU:
a1b60c1c 2807 r = iommu_present(&pci_bus_type);
62c476c7 2808 break;
4cee4b72 2809#endif
890ca9ae
HY		 2810 case KVM_CAP_MCE:
2811 r = KVM_MAX_MCE_BANKS;
2812 break;
2d5b5a66
SY		 2813 case KVM_CAP_XCRS:
2814 r = cpu_has_xsave;
2815 break;
92a1f12d
JR		 2816 case KVM_CAP_TSC_CONTROL:
2817 r = kvm_has_tsc_control;
2818 break;
018d00d2
ZX		 2819 default:
2820 r = 0;
2821 break;
2822 }
2823 return r;
2824
2825}
2826
043405e1
CO		 2827long kvm_arch_dev_ioctl(struct file *filp,
2828 unsigned int ioctl, unsigned long arg)
2829{
2830 void __user *argp = (void __user *)arg;
2831 long r;
2832
2833 switch (ioctl) {
2834 case KVM_GET_MSR_INDEX_LIST: {
2835 struct kvm_msr_list __user *user_msr_list = argp;
2836 struct kvm_msr_list msr_list;
2837 unsigned n;
2838
2839 r = -EFAULT;
2840 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2841 goto out;
2842 n = msr_list.nmsrs;
2843 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2844 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2845 goto out;
2846 r = -E2BIG;
e125e7b6 2847 if (n < msr_list.nmsrs)
043405e1
CO		 2848 goto out;
2849 r = -EFAULT;
2850 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2851 num_msrs_to_save * sizeof(u32)))
2852 goto out;
e125e7b6 2853 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2854 &emulated_msrs,
2855 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2856 goto out;
2857 r = 0;
2858 break;
2859 }
9c15bb1d
BP		 2860 case KVM_GET_SUPPORTED_CPUID:
2861 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2862 struct kvm_cpuid2 __user *cpuid_arg = argp;
2863 struct kvm_cpuid2 cpuid;
2864
2865 r = -EFAULT;
2866 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2867 goto out;
9c15bb1d
BP		 2868
2869 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2870 ioctl);
674eea0f
AK		 2871 if (r)
2872 goto out;
2873
2874 r = -EFAULT;
2875 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2876 goto out;
2877 r = 0;
2878 break;
2879 }
890ca9ae
HY		 2880 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2881 u64 mce_cap;
2882
2883 mce_cap = KVM_MCE_CAP_SUPPORTED;
2884 r = -EFAULT;
2885 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2886 goto out;
2887 r = 0;
2888 break;
2889 }
043405e1
CO		 2890 default:
2891 r = -EINVAL;
2892 }
2893out:
2894 return r;
2895}
2896
f5f48ee1
SY		 2897static void wbinvd_ipi(void *garbage)
2898{
2899 wbinvd();
2900}
2901
2902static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2903{
e0f0bbc5 2904 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2905}
2906
313a3dc7
CO		 2907void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2908{
f5f48ee1
SY		 2909 /* Address WBINVD may be executed by guest */
2910 if (need_emulate_wbinvd(vcpu)) {
2911 if (kvm_x86_ops->has_wbinvd_exit())
2912 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2913 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2914 smp_call_function_single(vcpu->cpu,
2915 wbinvd_ipi, NULL, 1);
2916 }
2917
313a3dc7 2918 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2919
0dd6a6ed
ZA		 2920 /* Apply any externally detected TSC adjustments (due to suspend) */
2921 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2922 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2923 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2924 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2925 }
8f6055cb 2926
48434c20 2927 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2928 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2929 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2930 if (tsc_delta < 0)
2931 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2932 if (check_tsc_unstable()) {
b183aa58
ZA		 2933 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2934 vcpu->arch.last_guest_tsc);
2935 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2936 vcpu->arch.tsc_catchup = 1;
c285545f 2937 }
d98d07ca
MT		 2938 /*
2939 * On a host with synchronized TSC, there is no need to update
2940 * kvmclock on vcpu->cpu migration
2941 */
2942 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2943 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2944 if (vcpu->cpu != cpu)
2945 kvm_migrate_timers(vcpu);
e48672fa 2946 vcpu->cpu = cpu;
6b7d7e76 2947 }
c9aaa895
GC		 2948
2949 accumulate_steal_time(vcpu);
2950 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2951}
2952
2953void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2954{
02daab21 2955 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2956 kvm_put_guest_fpu(vcpu);
6f526ec5 2957 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2958}
2959
313a3dc7
CO		 2960static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2961 struct kvm_lapic_state *s)
2962{
5a71785d 2963 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2964 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2965
2966 return 0;
2967}
2968
2969static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2970 struct kvm_lapic_state *s)
2971{
64eb0620 2972 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2973 update_cr8_intercept(vcpu);
313a3dc7
CO		 2974
2975 return 0;
2976}
2977
f77bc6a4
ZX		 2978static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2979 struct kvm_interrupt *irq)
2980{
02cdb50f 2981 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2982 return -EINVAL;
2983 if (irqchip_in_kernel(vcpu->kvm))
2984 return -ENXIO;
f77bc6a4 2985
66fd3f7f 2986 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2987 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2988
f77bc6a4
ZX		 2989 return 0;
2990}
2991
c4abb7c9
JK		 2992static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2993{
c4abb7c9 2994 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2995
2996 return 0;
2997}
2998
b209749f
AK		 2999static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3000 struct kvm_tpr_access_ctl *tac)
3001{
3002 if (tac->flags)
3003 return -EINVAL;
3004 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3005 return 0;
3006}
3007
890ca9ae
HY		 3008static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3009 u64 mcg_cap)
3010{
3011 int r;
3012 unsigned bank_num = mcg_cap & 0xff, bank;
3013
3014 r = -EINVAL;
a9e38c3e 3015 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3016 goto out;
3017 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3018 goto out;
3019 r = 0;
3020 vcpu->arch.mcg_cap = mcg_cap;
3021 /* Init IA32_MCG_CTL to all 1s */
3022 if (mcg_cap & MCG_CTL_P)
3023 vcpu->arch.mcg_ctl = ~(u64)0;
3024 /* Init IA32_MCi_CTL to all 1s */
3025 for (bank = 0; bank < bank_num; bank++)
3026 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3027out:
3028 return r;
3029}
3030
3031static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3032 struct kvm_x86_mce *mce)
3033{
3034 u64 mcg_cap = vcpu->arch.mcg_cap;
3035 unsigned bank_num = mcg_cap & 0xff;
3036 u64 *banks = vcpu->arch.mce_banks;
3037
3038 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3039 return -EINVAL;
3040 /*
3041 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3042 * reporting is disabled
3043 */
3044 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3045 vcpu->arch.mcg_ctl != ~(u64)0)
3046 return 0;
3047 banks += 4 * mce->bank;
3048 /*
3049 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3050 * reporting is disabled for the bank
3051 */
3052 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3053 return 0;
3054 if (mce->status & MCI_STATUS_UC) {
3055 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3056 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3057 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3058 return 0;
3059 }
3060 if (banks[1] & MCI_STATUS_VAL)
3061 mce->status |= MCI_STATUS_OVER;
3062 banks[2] = mce->addr;
3063 banks[3] = mce->misc;
3064 vcpu->arch.mcg_status = mce->mcg_status;
3065 banks[1] = mce->status;
3066 kvm_queue_exception(vcpu, MC_VECTOR);
3067 } else if (!(banks[1] & MCI_STATUS_VAL)
3068 || !(banks[1] & MCI_STATUS_UC)) {
3069 if (banks[1] & MCI_STATUS_VAL)
3070 mce->status |= MCI_STATUS_OVER;
3071 banks[2] = mce->addr;
3072 banks[3] = mce->misc;
3073 banks[1] = mce->status;
3074 } else
3075 banks[1] |= MCI_STATUS_OVER;
3076 return 0;
3077}
3078
3cfc3092
JK		 3079static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3080 struct kvm_vcpu_events *events)
3081{
7460fb4a 3082 process_nmi(vcpu);
03b82a30
JK		 3083 events->exception.injected =
3084 vcpu->arch.exception.pending &&
3085 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3086 events->exception.nr = vcpu->arch.exception.nr;
3087 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3088 events->exception.pad = 0;
3cfc3092
JK		 3089 events->exception.error_code = vcpu->arch.exception.error_code;
3090
03b82a30
JK		 3091 events->interrupt.injected =
3092 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3093 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3094 events->interrupt.soft = 0;
37ccdcbe 3095 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3096
3097 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3098 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3099 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3100 events->nmi.pad = 0;
3cfc3092 3101
66450a21 3102 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3103
dab4b911 3104 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3105 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3106 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3107}
3108
3109static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3110 struct kvm_vcpu_events *events)
3111{
dab4b911 3112 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3113 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3114 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3115 return -EINVAL;
3116
7460fb4a 3117 process_nmi(vcpu);
3cfc3092
JK		 3118 vcpu->arch.exception.pending = events->exception.injected;
3119 vcpu->arch.exception.nr = events->exception.nr;
3120 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3121 vcpu->arch.exception.error_code = events->exception.error_code;
3122
3123 vcpu->arch.interrupt.pending = events->interrupt.injected;
3124 vcpu->arch.interrupt.nr = events->interrupt.nr;
3125 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3126 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3127 kvm_x86_ops->set_interrupt_shadow(vcpu,
3128 events->interrupt.shadow);
3cfc3092
JK		 3129
3130 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3131 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3132 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3133 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3134
66450a21
JK		 3135 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3136 kvm_vcpu_has_lapic(vcpu))
3137 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3138
3842d135
AK		 3139 kvm_make_request(KVM_REQ_EVENT, vcpu);
3140
3cfc3092
JK		 3141 return 0;
3142}
3143
a1efbe77
JK		 3144static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3145 struct kvm_debugregs *dbgregs)
3146{
73aaf249
JK		 3147 unsigned long val;
3148
a1efbe77 3149 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3150 kvm_get_dr(vcpu, 6, &val);
73aaf249 3151 dbgregs->dr6 = val;
a1efbe77
JK		 3152 dbgregs->dr7 = vcpu->arch.dr7;
3153 dbgregs->flags = 0;
97e69aa6 3154 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3155}
3156
3157static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3158 struct kvm_debugregs *dbgregs)
3159{
3160 if (dbgregs->flags)
3161 return -EINVAL;
3162
a1efbe77 3163 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3164 kvm_update_dr0123(vcpu);
a1efbe77 3165 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3166 kvm_update_dr6(vcpu);
a1efbe77 3167 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3168 kvm_update_dr7(vcpu);
a1efbe77 3169
a1efbe77
JK		 3170 return 0;
3171}
3172
df1daba7
PB		 3173#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3174
3175static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3176{
3177 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3178 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3179 u64 valid;
3180
3181 /*
3182 * Copy legacy XSAVE area, to avoid complications with CPUID
3183 * leaves 0 and 1 in the loop below.
3184 */
3185 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3186
3187 /* Set XSTATE_BV */
3188 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3189
3190 /*
3191 * Copy each region from the possibly compacted offset to the
3192 * non-compacted offset.
3193 */
3194 valid = xstate_bv & ~XSTATE_FPSSE;
3195 while (valid) {
3196 u64 feature = valid & -valid;
3197 int index = fls64(feature) - 1;
3198 void *src = get_xsave_addr(xsave, feature);
3199
3200 if (src) {
3201 u32 size, offset, ecx, edx;
3202 cpuid_count(XSTATE_CPUID, index,
3203 &size, &offset, &ecx, &edx);
3204 memcpy(dest + offset, src, size);
3205 }
3206
3207 valid -= feature;
3208 }
3209}
3210
3211static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3212{
3213 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3214 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3215 u64 valid;
3216
3217 /*
3218 * Copy legacy XSAVE area, to avoid complications with CPUID
3219 * leaves 0 and 1 in the loop below.
3220 */
3221 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3222
3223 /* Set XSTATE_BV and possibly XCOMP_BV. */
3224 xsave->xsave_hdr.xstate_bv = xstate_bv;
3225 if (cpu_has_xsaves)
3226 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3227
3228 /*
3229 * Copy each region from the non-compacted offset to the
3230 * possibly compacted offset.
3231 */
3232 valid = xstate_bv & ~XSTATE_FPSSE;
3233 while (valid) {
3234 u64 feature = valid & -valid;
3235 int index = fls64(feature) - 1;
3236 void *dest = get_xsave_addr(xsave, feature);
3237
3238 if (dest) {
3239 u32 size, offset, ecx, edx;
3240 cpuid_count(XSTATE_CPUID, index,
3241 &size, &offset, &ecx, &edx);
3242 memcpy(dest, src + offset, size);
3243 } else
3244 WARN_ON_ONCE(1);
3245
3246 valid -= feature;
3247 }
3248}
3249
2d5b5a66
SY		 3250static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3251 struct kvm_xsave *guest_xsave)
3252{
4344ee98 3253 if (cpu_has_xsave) {
df1daba7
PB		 3254 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3255 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3256 } else {
2d5b5a66
SY		 3257 memcpy(guest_xsave->region,
3258 &vcpu->arch.guest_fpu.state->fxsave,
3259 sizeof(struct i387_fxsave_struct));
3260 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3261 XSTATE_FPSSE;
3262 }
3263}
3264
3265static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3266 struct kvm_xsave *guest_xsave)
3267{
3268 u64 xstate_bv =
3269 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3270
d7876f1b
PB		 3271 if (cpu_has_xsave) {
3272 /*
3273 * Here we allow setting states that are not present in
3274 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3275 * with old userspace.
3276 */
4ff41732 3277 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3278 return -EINVAL;
df1daba7 3279 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3280 } else {
2d5b5a66
SY		 3281 if (xstate_bv & ~XSTATE_FPSSE)
3282 return -EINVAL;
3283 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3284 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3285 }
3286 return 0;
3287}
3288
3289static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3290 struct kvm_xcrs *guest_xcrs)
3291{
3292 if (!cpu_has_xsave) {
3293 guest_xcrs->nr_xcrs = 0;
3294 return;
3295 }
3296
3297 guest_xcrs->nr_xcrs = 1;
3298 guest_xcrs->flags = 0;
3299 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3300 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3301}
3302
3303static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3304 struct kvm_xcrs *guest_xcrs)
3305{
3306 int i, r = 0;
3307
3308 if (!cpu_has_xsave)
3309 return -EINVAL;
3310
3311 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3312 return -EINVAL;
3313
3314 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3315 /* Only support XCR0 currently */
c67a04cb 3316 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3317 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3318 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3319 break;
3320 }
3321 if (r)
3322 r = -EINVAL;
3323 return r;
3324}
3325
1c0b28c2
EM		 3326/*
3327 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3328 * stopped by the hypervisor. This function will be called from the host only.
3329 * EINVAL is returned when the host attempts to set the flag for a guest that
3330 * does not support pv clocks.
3331 */
3332static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3333{
0b79459b 3334 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3335 return -EINVAL;
51d59c6b 3336 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3337 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3338 return 0;
3339}
3340
313a3dc7
CO		 3341long kvm_arch_vcpu_ioctl(struct file *filp,
3342 unsigned int ioctl, unsigned long arg)
3343{
3344 struct kvm_vcpu *vcpu = filp->private_data;
3345 void __user *argp = (void __user *)arg;
3346 int r;
d1ac91d8
AK		 3347 union {
3348 struct kvm_lapic_state *lapic;
3349 struct kvm_xsave *xsave;
3350 struct kvm_xcrs *xcrs;
3351 void *buffer;
3352 } u;
3353
3354 u.buffer = NULL;
313a3dc7
CO		 3355 switch (ioctl) {
3356 case KVM_GET_LAPIC: {
2204ae3c
MT		 3357 r = -EINVAL;
3358 if (!vcpu->arch.apic)
3359 goto out;
d1ac91d8 3360 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3361
b772ff36 3362 r = -ENOMEM;
d1ac91d8 3363 if (!u.lapic)
b772ff36 3364 goto out;
d1ac91d8 3365 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3366 if (r)
3367 goto out;
3368 r = -EFAULT;
d1ac91d8 3369 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3370 goto out;
3371 r = 0;
3372 break;
3373 }
3374 case KVM_SET_LAPIC: {
2204ae3c
MT		 3375 r = -EINVAL;
3376 if (!vcpu->arch.apic)
3377 goto out;
ff5c2c03 3378 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3379 if (IS_ERR(u.lapic))
3380 return PTR_ERR(u.lapic);
ff5c2c03 3381
d1ac91d8 3382 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3383 break;
3384 }
f77bc6a4
ZX		 3385 case KVM_INTERRUPT: {
3386 struct kvm_interrupt irq;
3387
3388 r = -EFAULT;
3389 if (copy_from_user(&irq, argp, sizeof irq))
3390 goto out;
3391 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3392 break;
3393 }
c4abb7c9
JK		 3394 case KVM_NMI: {
3395 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3396 break;
3397 }
313a3dc7
CO		 3398 case KVM_SET_CPUID: {
3399 struct kvm_cpuid __user *cpuid_arg = argp;
3400 struct kvm_cpuid cpuid;
3401
3402 r = -EFAULT;
3403 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3404 goto out;
3405 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3406 break;
3407 }
07716717
DK		 3408 case KVM_SET_CPUID2: {
3409 struct kvm_cpuid2 __user *cpuid_arg = argp;
3410 struct kvm_cpuid2 cpuid;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3414 goto out;
3415 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3416 cpuid_arg->entries);
07716717
DK		 3417 break;
3418 }
3419 case KVM_GET_CPUID2: {
3420 struct kvm_cpuid2 __user *cpuid_arg = argp;
3421 struct kvm_cpuid2 cpuid;
3422
3423 r = -EFAULT;
3424 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3425 goto out;
3426 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3427 cpuid_arg->entries);
07716717
DK		 3428 if (r)
3429 goto out;
3430 r = -EFAULT;
3431 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3432 goto out;
3433 r = 0;
3434 break;
3435 }
313a3dc7
CO		 3436 case KVM_GET_MSRS:
3437 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3438 break;
3439 case KVM_SET_MSRS:
3440 r = msr_io(vcpu, argp, do_set_msr, 0);
3441 break;
b209749f
AK		 3442 case KVM_TPR_ACCESS_REPORTING: {
3443 struct kvm_tpr_access_ctl tac;
3444
3445 r = -EFAULT;
3446 if (copy_from_user(&tac, argp, sizeof tac))
3447 goto out;
3448 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3449 if (r)
3450 goto out;
3451 r = -EFAULT;
3452 if (copy_to_user(argp, &tac, sizeof tac))
3453 goto out;
3454 r = 0;
3455 break;
3456 };
b93463aa
AK		 3457 case KVM_SET_VAPIC_ADDR: {
3458 struct kvm_vapic_addr va;
3459
3460 r = -EINVAL;
3461 if (!irqchip_in_kernel(vcpu->kvm))
3462 goto out;
3463 r = -EFAULT;
3464 if (copy_from_user(&va, argp, sizeof va))
3465 goto out;
fda4e2e8 3466 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3467 break;
3468 }
890ca9ae
HY		 3469 case KVM_X86_SETUP_MCE: {
3470 u64 mcg_cap;
3471
3472 r = -EFAULT;
3473 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3474 goto out;
3475 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3476 break;
3477 }
3478 case KVM_X86_SET_MCE: {
3479 struct kvm_x86_mce mce;
3480
3481 r = -EFAULT;
3482 if (copy_from_user(&mce, argp, sizeof mce))
3483 goto out;
3484 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3485 break;
3486 }
3cfc3092
JK		 3487 case KVM_GET_VCPU_EVENTS: {
3488 struct kvm_vcpu_events events;
3489
3490 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3491
3492 r = -EFAULT;
3493 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3494 break;
3495 r = 0;
3496 break;
3497 }
3498 case KVM_SET_VCPU_EVENTS: {
3499 struct kvm_vcpu_events events;
3500
3501 r = -EFAULT;
3502 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3503 break;
3504
3505 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3506 break;
3507 }
a1efbe77
JK		 3508 case KVM_GET_DEBUGREGS: {
3509 struct kvm_debugregs dbgregs;
3510
3511 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3512
3513 r = -EFAULT;
3514 if (copy_to_user(argp, &dbgregs,
3515 sizeof(struct kvm_debugregs)))
3516 break;
3517 r = 0;
3518 break;
3519 }
3520 case KVM_SET_DEBUGREGS: {
3521 struct kvm_debugregs dbgregs;
3522
3523 r = -EFAULT;
3524 if (copy_from_user(&dbgregs, argp,
3525 sizeof(struct kvm_debugregs)))
3526 break;
3527
3528 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3529 break;
3530 }
2d5b5a66 3531 case KVM_GET_XSAVE: {
d1ac91d8 3532 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3533 r = -ENOMEM;
d1ac91d8 3534 if (!u.xsave)
2d5b5a66
SY		 3535 break;
3536
d1ac91d8 3537 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3538
3539 r = -EFAULT;
d1ac91d8 3540 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3541 break;
3542 r = 0;
3543 break;
3544 }
3545 case KVM_SET_XSAVE: {
ff5c2c03 3546 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3547 if (IS_ERR(u.xsave))
3548 return PTR_ERR(u.xsave);
2d5b5a66 3549
d1ac91d8 3550 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3551 break;
3552 }
3553 case KVM_GET_XCRS: {
d1ac91d8 3554 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3555 r = -ENOMEM;
d1ac91d8 3556 if (!u.xcrs)
2d5b5a66
SY		 3557 break;
3558
d1ac91d8 3559 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3560
3561 r = -EFAULT;
d1ac91d8 3562 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3563 sizeof(struct kvm_xcrs)))
3564 break;
3565 r = 0;
3566 break;
3567 }
3568 case KVM_SET_XCRS: {
ff5c2c03 3569 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3570 if (IS_ERR(u.xcrs))
3571 return PTR_ERR(u.xcrs);
2d5b5a66 3572
d1ac91d8 3573 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3574 break;
3575 }
92a1f12d
JR		 3576 case KVM_SET_TSC_KHZ: {
3577 u32 user_tsc_khz;
3578
3579 r = -EINVAL;
92a1f12d
JR		 3580 user_tsc_khz = (u32)arg;
3581
3582 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3583 goto out;
3584
cc578287
ZA		 3585 if (user_tsc_khz == 0)
3586 user_tsc_khz = tsc_khz;
3587
3588 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3589
3590 r = 0;
3591 goto out;
3592 }
3593 case KVM_GET_TSC_KHZ: {
cc578287 3594 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3595 goto out;
3596 }
1c0b28c2
EM		 3597 case KVM_KVMCLOCK_CTRL: {
3598 r = kvm_set_guest_paused(vcpu);
3599 goto out;
3600 }
313a3dc7
CO		 3601 default:
3602 r = -EINVAL;
3603 }
3604out:
d1ac91d8 3605 kfree(u.buffer);
313a3dc7
CO		 3606 return r;
3607}
3608
5b1c1493
CO		 3609int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3610{
3611 return VM_FAULT_SIGBUS;
3612}
3613
1fe779f8
CO		 3614static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3615{
3616 int ret;
3617
3618 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3619 return -EINVAL;
1fe779f8
CO		 3620 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3621 return ret;
3622}
3623
b927a3ce
SY		 3624static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3625 u64 ident_addr)
3626{
3627 kvm->arch.ept_identity_map_addr = ident_addr;
3628 return 0;
3629}
3630
1fe779f8
CO		 3631static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3632 u32 kvm_nr_mmu_pages)
3633{
3634 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3635 return -EINVAL;
3636
79fac95e 3637 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3638
3639 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3640 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3641
79fac95e 3642 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3643 return 0;
3644}
3645
3646static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3647{
39de71ec 3648 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3649}
3650
1fe779f8
CO		 3651static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3652{
3653 int r;
3654
3655 r = 0;
3656 switch (chip->chip_id) {
3657 case KVM_IRQCHIP_PIC_MASTER:
3658 memcpy(&chip->chip.pic,
3659 &pic_irqchip(kvm)->pics[0],
3660 sizeof(struct kvm_pic_state));
3661 break;
3662 case KVM_IRQCHIP_PIC_SLAVE:
3663 memcpy(&chip->chip.pic,
3664 &pic_irqchip(kvm)->pics[1],
3665 sizeof(struct kvm_pic_state));
3666 break;
3667 case KVM_IRQCHIP_IOAPIC:
eba0226b 3668 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3669 break;
3670 default:
3671 r = -EINVAL;
3672 break;
3673 }
3674 return r;
3675}
3676
3677static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3678{
3679 int r;
3680
3681 r = 0;
3682 switch (chip->chip_id) {
3683 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3684 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3685 memcpy(&pic_irqchip(kvm)->pics[0],
3686 &chip->chip.pic,
3687 sizeof(struct kvm_pic_state));
f4f51050 3688 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3689 break;
3690 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3691 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3692 memcpy(&pic_irqchip(kvm)->pics[1],
3693 &chip->chip.pic,
3694 sizeof(struct kvm_pic_state));
f4f51050 3695 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3696 break;
3697 case KVM_IRQCHIP_IOAPIC:
eba0226b 3698 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3699 break;
3700 default:
3701 r = -EINVAL;
3702 break;
3703 }
3704 kvm_pic_update_irq(pic_irqchip(kvm));
3705 return r;
3706}
3707
e0f63cb9
SY		 3708static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3709{
3710 int r = 0;
3711
894a9c55 3712 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3713 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3714 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3715 return r;
3716}
3717
3718static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3719{
3720 int r = 0;
3721
894a9c55 3722 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3723 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3724 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3725 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3726 return r;
3727}
3728
3729static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3730{
3731 int r = 0;
3732
3733 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3734 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3735 sizeof(ps->channels));
3736 ps->flags = kvm->arch.vpit->pit_state.flags;
3737 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3738 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3739 return r;
3740}
3741
3742static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3743{
3744 int r = 0, start = 0;
3745 u32 prev_legacy, cur_legacy;
3746 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3747 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3748 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3749 if (!prev_legacy && cur_legacy)
3750 start = 1;
3751 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3752 sizeof(kvm->arch.vpit->pit_state.channels));
3753 kvm->arch.vpit->pit_state.flags = ps->flags;
3754 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3755 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3756 return r;
3757}
3758
52d939a0
MT		 3759static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3760 struct kvm_reinject_control *control)
3761{
3762 if (!kvm->arch.vpit)
3763 return -ENXIO;
894a9c55 3764 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3765 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3766 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3767 return 0;
3768}
3769
95d4c16c 3770/**
60c34612
TY		 3771 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3772 * @kvm: kvm instance
3773 * @log: slot id and address to which we copy the log
95d4c16c 3774 *
e108ff2f
PB		 3775 * Steps 1-4 below provide general overview of dirty page logging. See
3776 * kvm_get_dirty_log_protect() function description for additional details.
3777 *
3778 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3779 * always flush the TLB (step 4) even if previous step failed and the dirty
3780 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3781 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3782 * writes will be marked dirty for next log read.
95d4c16c 3783 *
60c34612
TY		 3784 * 1. Take a snapshot of the bit and clear it if needed.
3785 * 2. Write protect the corresponding page.
e108ff2f
PB		 3786 * 3. Copy the snapshot to the userspace.
3787 * 4. Flush TLB's if needed.
5bb064dc 3788 */
60c34612 3789int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3790{
60c34612 3791 bool is_dirty = false;
e108ff2f 3792 int r;
5bb064dc 3793
79fac95e 3794 mutex_lock(&kvm->slots_lock);
5bb064dc 3795
88178fd4
KH		 3796 /*
3797 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3798 */
3799 if (kvm_x86_ops->flush_log_dirty)
3800 kvm_x86_ops->flush_log_dirty(kvm);
3801
e108ff2f 3802 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3803
3804 /*
3805 * All the TLBs can be flushed out of mmu lock, see the comments in
3806 * kvm_mmu_slot_remove_write_access().
3807 */
e108ff2f 3808 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3809 if (is_dirty)
3810 kvm_flush_remote_tlbs(kvm);
3811
79fac95e 3812 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3813 return r;
3814}
3815
aa2fbe6d
YZ		 3816int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3817 bool line_status)
23d43cf9
CD		 3818{
3819 if (!irqchip_in_kernel(kvm))
3820 return -ENXIO;
3821
3822 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3823 irq_event->irq, irq_event->level,
3824 line_status);
23d43cf9
CD		 3825 return 0;
3826}
3827
1fe779f8
CO		 3828long kvm_arch_vm_ioctl(struct file *filp,
3829 unsigned int ioctl, unsigned long arg)
3830{
3831 struct kvm *kvm = filp->private_data;
3832 void __user *argp = (void __user *)arg;
367e1319 3833 int r = -ENOTTY;
f0d66275
DH		 3834 /*
3835 * This union makes it completely explicit to gcc-3.x
3836 * that these two variables' stack usage should be
3837 * combined, not added together.
3838 */
3839 union {
3840 struct kvm_pit_state ps;
e9f42757 3841 struct kvm_pit_state2 ps2;
c5ff41ce 3842 struct kvm_pit_config pit_config;
f0d66275 3843 } u;
1fe779f8
CO		 3844
3845 switch (ioctl) {
3846 case KVM_SET_TSS_ADDR:
3847 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3848 break;
b927a3ce
SY		 3849 case KVM_SET_IDENTITY_MAP_ADDR: {
3850 u64 ident_addr;
3851
3852 r = -EFAULT;
3853 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3854 goto out;
3855 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3856 break;
3857 }
1fe779f8
CO		 3858 case KVM_SET_NR_MMU_PAGES:
3859 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3860 break;
3861 case KVM_GET_NR_MMU_PAGES:
3862 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3863 break;
3ddea128
MT		 3864 case KVM_CREATE_IRQCHIP: {
3865 struct kvm_pic *vpic;
3866
3867 mutex_lock(&kvm->lock);
3868 r = -EEXIST;
3869 if (kvm->arch.vpic)
3870 goto create_irqchip_unlock;
3e515705
AK		 3871 r = -EINVAL;
3872 if (atomic_read(&kvm->online_vcpus))
3873 goto create_irqchip_unlock;
1fe779f8 3874 r = -ENOMEM;
3ddea128
MT		 3875 vpic = kvm_create_pic(kvm);
3876 if (vpic) {
1fe779f8
CO		 3877 r = kvm_ioapic_init(kvm);
3878 if (r) {
175504cd 3879 mutex_lock(&kvm->slots_lock);
72bb2fcd 3880 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3881 &vpic->dev_master);
3882 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3883 &vpic->dev_slave);
3884 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3885 &vpic->dev_eclr);
175504cd 3886 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3887 kfree(vpic);
3888 goto create_irqchip_unlock;
1fe779f8
CO		 3889 }
3890 } else
3ddea128
MT		 3891 goto create_irqchip_unlock;
3892 smp_wmb();
3893 kvm->arch.vpic = vpic;
3894 smp_wmb();
399ec807
AK		 3895 r = kvm_setup_default_irq_routing(kvm);
3896 if (r) {
175504cd 3897 mutex_lock(&kvm->slots_lock);
3ddea128 3898 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3899 kvm_ioapic_destroy(kvm);
3900 kvm_destroy_pic(kvm);
3ddea128 3901 mutex_unlock(&kvm->irq_lock);
175504cd 3902 mutex_unlock(&kvm->slots_lock);
399ec807 3903 }
3ddea128
MT		 3904 create_irqchip_unlock:
3905 mutex_unlock(&kvm->lock);
1fe779f8 3906 break;
3ddea128 3907 }
7837699f 3908 case KVM_CREATE_PIT:
c5ff41ce
JK		 3909 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3910 goto create_pit;
3911 case KVM_CREATE_PIT2:
3912 r = -EFAULT;
3913 if (copy_from_user(&u.pit_config, argp,
3914 sizeof(struct kvm_pit_config)))
3915 goto out;
3916 create_pit:
79fac95e 3917 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3918 r = -EEXIST;
3919 if (kvm->arch.vpit)
3920 goto create_pit_unlock;
7837699f 3921 r = -ENOMEM;
c5ff41ce 3922 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3923 if (kvm->arch.vpit)
3924 r = 0;
269e05e4 3925 create_pit_unlock:
79fac95e 3926 mutex_unlock(&kvm->slots_lock);
7837699f 3927 break;
1fe779f8
CO		 3928 case KVM_GET_IRQCHIP: {
3929 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3930 struct kvm_irqchip *chip;
1fe779f8 3931
ff5c2c03
SL		 3932 chip = memdup_user(argp, sizeof(*chip));
3933 if (IS_ERR(chip)) {
3934 r = PTR_ERR(chip);
1fe779f8 3935 goto out;
ff5c2c03
SL		 3936 }
3937
1fe779f8
CO		 3938 r = -ENXIO;
3939 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3940 goto get_irqchip_out;
3941 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3942 if (r)
f0d66275 3943 goto get_irqchip_out;
1fe779f8 3944 r = -EFAULT;
f0d66275
DH		 3945 if (copy_to_user(argp, chip, sizeof *chip))
3946 goto get_irqchip_out;
1fe779f8 3947 r = 0;
f0d66275
DH		 3948 get_irqchip_out:
3949 kfree(chip);
1fe779f8
CO		 3950 break;
3951 }
3952 case KVM_SET_IRQCHIP: {
3953 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3954 struct kvm_irqchip *chip;
1fe779f8 3955
ff5c2c03
SL		 3956 chip = memdup_user(argp, sizeof(*chip));
3957 if (IS_ERR(chip)) {
3958 r = PTR_ERR(chip);
1fe779f8 3959 goto out;
ff5c2c03
SL		 3960 }
3961
1fe779f8
CO		 3962 r = -ENXIO;
3963 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3964 goto set_irqchip_out;
3965 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3966 if (r)
f0d66275 3967 goto set_irqchip_out;
1fe779f8 3968 r = 0;
f0d66275
DH		 3969 set_irqchip_out:
3970 kfree(chip);
1fe779f8
CO		 3971 break;
3972 }
e0f63cb9 3973 case KVM_GET_PIT: {
e0f63cb9 3974 r = -EFAULT;
f0d66275 3975 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3976 goto out;
3977 r = -ENXIO;
3978 if (!kvm->arch.vpit)
3979 goto out;
f0d66275 3980 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3981 if (r)
3982 goto out;
3983 r = -EFAULT;
f0d66275 3984 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3985 goto out;
3986 r = 0;
3987 break;
3988 }
3989 case KVM_SET_PIT: {
e0f63cb9 3990 r = -EFAULT;
f0d66275 3991 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3992 goto out;
3993 r = -ENXIO;
3994 if (!kvm->arch.vpit)
3995 goto out;
f0d66275 3996 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3997 break;
3998 }
e9f42757
BK		 3999 case KVM_GET_PIT2: {
4000 r = -ENXIO;
4001 if (!kvm->arch.vpit)
4002 goto out;
4003 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4004 if (r)
4005 goto out;
4006 r = -EFAULT;
4007 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4008 goto out;
4009 r = 0;
4010 break;
4011 }
4012 case KVM_SET_PIT2: {
4013 r = -EFAULT;
4014 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4015 goto out;
4016 r = -ENXIO;
4017 if (!kvm->arch.vpit)
4018 goto out;
4019 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4020 break;
4021 }
52d939a0
MT		 4022 case KVM_REINJECT_CONTROL: {
4023 struct kvm_reinject_control control;
4024 r = -EFAULT;
4025 if (copy_from_user(&control, argp, sizeof(control)))
4026 goto out;
4027 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4028 break;
4029 }
ffde22ac
ES		 4030 case KVM_XEN_HVM_CONFIG: {
4031 r = -EFAULT;
4032 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4033 sizeof(struct kvm_xen_hvm_config)))
4034 goto out;
4035 r = -EINVAL;
4036 if (kvm->arch.xen_hvm_config.flags)
4037 goto out;
4038 r = 0;
4039 break;
4040 }
afbcf7ab 4041 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4042 struct kvm_clock_data user_ns;
4043 u64 now_ns;
4044 s64 delta;
4045
4046 r = -EFAULT;
4047 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4048 goto out;
4049
4050 r = -EINVAL;
4051 if (user_ns.flags)
4052 goto out;
4053
4054 r = 0;
395c6b0a 4055 local_irq_disable();
759379dd 4056 now_ns = get_kernel_ns();
afbcf7ab 4057 delta = user_ns.clock - now_ns;
395c6b0a 4058 local_irq_enable();
afbcf7ab 4059 kvm->arch.kvmclock_offset = delta;
2e762ff7 4060 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4061 break;
4062 }
4063 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4064 struct kvm_clock_data user_ns;
4065 u64 now_ns;
4066
395c6b0a 4067 local_irq_disable();
759379dd 4068 now_ns = get_kernel_ns();
afbcf7ab 4069 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4070 local_irq_enable();
afbcf7ab 4071 user_ns.flags = 0;
97e69aa6 4072 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4073
4074 r = -EFAULT;
4075 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4076 goto out;
4077 r = 0;
4078 break;
4079 }
4080
1fe779f8 4081 default:
c274e03a 4082 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4083 }
4084out:
4085 return r;
4086}
4087
a16b043c 4088static void kvm_init_msr_list(void)
043405e1
CO		 4089{
4090 u32 dummy[2];
4091 unsigned i, j;
4092
e3267cbb
GC		 4093 /* skip the first msrs in the list. KVM-specific */
4094 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4095 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4096 continue;
93c4adc7
PB		 4097
4098 /*
4099 * Even MSRs that are valid in the host may not be exposed
4100 * to the guests in some cases. We could work around this
4101 * in VMX with the generic MSR save/load machinery, but it
4102 * is not really worthwhile since it will really only
4103 * happen with nested virtualization.
4104 */
4105 switch (msrs_to_save[i]) {
4106 case MSR_IA32_BNDCFGS:
4107 if (!kvm_x86_ops->mpx_supported())
4108 continue;
4109 break;
4110 default:
4111 break;
4112 }
4113
043405e1
CO		 4114 if (j < i)
4115 msrs_to_save[j] = msrs_to_save[i];
4116 j++;
4117 }
4118 num_msrs_to_save = j;
4119}
4120
bda9020e
MT		 4121static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4122 const void *v)
bbd9b64e 4123{
70252a10
AK		 4124 int handled = 0;
4125 int n;
4126
4127 do {
4128 n = min(len, 8);
4129 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4130 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4131 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4132 break;
4133 handled += n;
4134 addr += n;
4135 len -= n;
4136 v += n;
4137 } while (len);
bbd9b64e 4138
70252a10 4139 return handled;
bbd9b64e
CO		 4140}
4141
bda9020e 4142static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4143{
70252a10
AK		 4144 int handled = 0;
4145 int n;
4146
4147 do {
4148 n = min(len, 8);
4149 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4150 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4151 addr, n, v))
4152 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4153 break;
4154 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4155 handled += n;
4156 addr += n;
4157 len -= n;
4158 v += n;
4159 } while (len);
bbd9b64e 4160
70252a10 4161 return handled;
bbd9b64e
CO		 4162}
4163
2dafc6c2
GN		 4164static void kvm_set_segment(struct kvm_vcpu *vcpu,
4165 struct kvm_segment *var, int seg)
4166{
4167 kvm_x86_ops->set_segment(vcpu, var, seg);
4168}
4169
4170void kvm_get_segment(struct kvm_vcpu *vcpu,
4171 struct kvm_segment *var, int seg)
4172{
4173 kvm_x86_ops->get_segment(vcpu, var, seg);
4174}
4175
54987b7a
PB		 4176gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4177 struct x86_exception *exception)
02f59dc9
JR		 4178{
4179 gpa_t t_gpa;
02f59dc9
JR		 4180
4181 BUG_ON(!mmu_is_nested(vcpu));
4182
4183 /* NPT walks are always user-walks */
4184 access |= PFERR_USER_MASK;
54987b7a 4185 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4186
4187 return t_gpa;
4188}
4189
ab9ae313
AK		 4190gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4191 struct x86_exception *exception)
1871c602
GN		 4192{
4193 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4194 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4195}
4196
ab9ae313
AK		 4197 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4198 struct x86_exception *exception)
1871c602
GN		 4199{
4200 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4201 access |= PFERR_FETCH_MASK;
ab9ae313 4202 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4203}
4204
ab9ae313
AK		 4205gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4206 struct x86_exception *exception)
1871c602
GN		 4207{
4208 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4209 access |= PFERR_WRITE_MASK;
ab9ae313 4210 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4211}
4212
4213/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4214gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4215 struct x86_exception *exception)
1871c602 4216{
ab9ae313 4217 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4218}
4219
4220static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4221 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4222 struct x86_exception *exception)
bbd9b64e
CO		 4223{
4224 void *data = val;
10589a46 4225 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4226
4227 while (bytes) {
14dfe855 4228 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4229 exception);
bbd9b64e 4230 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4231 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4232 int ret;
4233
bcc55cba 4234 if (gpa == UNMAPPED_GVA)
ab9ae313 4235 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4236 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4237 offset, toread);
10589a46 4238 if (ret < 0) {
c3cd7ffa 4239 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4240 goto out;
4241 }
bbd9b64e 4242
77c2002e
IE		 4243 bytes -= toread;
4244 data += toread;
4245 addr += toread;
bbd9b64e 4246 }
10589a46 4247out:
10589a46 4248 return r;
bbd9b64e 4249}
77c2002e 4250
1871c602 4251/* used for instruction fetching */
0f65dd70
AK		 4252static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4253 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4254 struct x86_exception *exception)
1871c602 4255{
0f65dd70 4256 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4257 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4258 unsigned offset;
4259 int ret;
0f65dd70 4260
44583cba
PB		 4261 /* Inline kvm_read_guest_virt_helper for speed. */
4262 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4263 exception);
4264 if (unlikely(gpa == UNMAPPED_GVA))
4265 return X86EMUL_PROPAGATE_FAULT;
4266
4267 offset = addr & (PAGE_SIZE-1);
4268 if (WARN_ON(offset + bytes > PAGE_SIZE))
4269 bytes = (unsigned)PAGE_SIZE - offset;
4270 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4271 offset, bytes);
4272 if (unlikely(ret < 0))
4273 return X86EMUL_IO_NEEDED;
4274
4275 return X86EMUL_CONTINUE;
1871c602
GN		 4276}
4277
064aea77 4278int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4279 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4280 struct x86_exception *exception)
1871c602 4281{
0f65dd70 4282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4283 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4284
1871c602 4285 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4286 exception);
1871c602 4287}
064aea77 4288EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4289
0f65dd70
AK		 4290static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4291 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4292 struct x86_exception *exception)
1871c602 4293{
0f65dd70 4294 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4295 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4296}
4297
6a4d7550 4298int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4299 gva_t addr, void *val,
2dafc6c2 4300 unsigned int bytes,
bcc55cba 4301 struct x86_exception *exception)
77c2002e 4302{
0f65dd70 4303 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4304 void *data = val;
4305 int r = X86EMUL_CONTINUE;
4306
4307 while (bytes) {
14dfe855
JR		 4308 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4309 PFERR_WRITE_MASK,
ab9ae313 4310 exception);
77c2002e
IE		 4311 unsigned offset = addr & (PAGE_SIZE-1);
4312 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4313 int ret;
4314
bcc55cba 4315 if (gpa == UNMAPPED_GVA)
ab9ae313 4316 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4317 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4318 if (ret < 0) {
c3cd7ffa 4319 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4320 goto out;
4321 }
4322
4323 bytes -= towrite;
4324 data += towrite;
4325 addr += towrite;
4326 }
4327out:
4328 return r;
4329}
6a4d7550 4330EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4331
af7cc7d1
XG		 4332static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4333 gpa_t *gpa, struct x86_exception *exception,
4334 bool write)
4335{
97d64b78
AK		 4336 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4337 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4338
97d64b78 4339 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4340 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4341 vcpu->arch.access, access)) {
bebb106a
XG		 4342 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4343 (gva & (PAGE_SIZE - 1));
4f022648 4344 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4345 return 1;
4346 }
4347
af7cc7d1
XG		 4348 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4349
4350 if (*gpa == UNMAPPED_GVA)
4351 return -1;
4352
4353 /* For APIC access vmexit */
4354 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4355 return 1;
4356
4f022648
XG		 4357 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4358 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4359 return 1;
4f022648 4360 }
bebb106a 4361
af7cc7d1
XG		 4362 return 0;
4363}
4364
3200f405 4365int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4366 const void *val, int bytes)
bbd9b64e
CO		 4367{
4368 int ret;
4369
4370 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4371 if (ret < 0)
bbd9b64e 4372 return 0;
f57f2ef5 4373 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4374 return 1;
4375}
4376
77d197b2
XG		 4377struct read_write_emulator_ops {
4378 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4379 int bytes);
4380 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 void *val, int bytes);
4382 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 int bytes, void *val);
4384 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4385 void *val, int bytes);
4386 bool write;
4387};
4388
4389static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4390{
4391 if (vcpu->mmio_read_completed) {
77d197b2 4392 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4393 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4394 vcpu->mmio_read_completed = 0;
4395 return 1;
4396 }
4397
4398 return 0;
4399}
4400
4401static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4402 void *val, int bytes)
4403{
4404 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4405}
4406
4407static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 void *val, int bytes)
4409{
4410 return emulator_write_phys(vcpu, gpa, val, bytes);
4411}
4412
4413static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4414{
4415 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4416 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4417}
4418
4419static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4420 void *val, int bytes)
4421{
4422 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4423 return X86EMUL_IO_NEEDED;
4424}
4425
4426static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4427 void *val, int bytes)
4428{
f78146b0
AK		 4429 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4430
87da7e66 4431 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4432 return X86EMUL_CONTINUE;
4433}
4434
0fbe9b0b 4435static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4436 .read_write_prepare = read_prepare,
4437 .read_write_emulate = read_emulate,
4438 .read_write_mmio = vcpu_mmio_read,
4439 .read_write_exit_mmio = read_exit_mmio,
4440};
4441
0fbe9b0b 4442static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4443 .read_write_emulate = write_emulate,
4444 .read_write_mmio = write_mmio,
4445 .read_write_exit_mmio = write_exit_mmio,
4446 .write = true,
4447};
4448
22388a3c
XG		 4449static int emulator_read_write_onepage(unsigned long addr, void *val,
4450 unsigned int bytes,
4451 struct x86_exception *exception,
4452 struct kvm_vcpu *vcpu,
0fbe9b0b 4453 const struct read_write_emulator_ops *ops)
bbd9b64e 4454{
af7cc7d1
XG		 4455 gpa_t gpa;
4456 int handled, ret;
22388a3c 4457 bool write = ops->write;
f78146b0 4458 struct kvm_mmio_fragment *frag;
10589a46 4459
22388a3c 4460 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4461
af7cc7d1 4462 if (ret < 0)
bbd9b64e 4463 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4464
4465 /* For APIC access vmexit */
af7cc7d1 4466 if (ret)
bbd9b64e
CO		 4467 goto mmio;
4468
22388a3c 4469 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4470 return X86EMUL_CONTINUE;
4471
4472mmio:
4473 /*
4474 * Is this MMIO handled locally?
4475 */
22388a3c 4476 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4477 if (handled == bytes)
bbd9b64e 4478 return X86EMUL_CONTINUE;
bbd9b64e 4479
70252a10
AK		 4480 gpa += handled;
4481 bytes -= handled;
4482 val += handled;
4483
87da7e66
XG		 4484 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4485 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4486 frag->gpa = gpa;
4487 frag->data = val;
4488 frag->len = bytes;
f78146b0 4489 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4490}
4491
52eb5a6d
XL		 4492static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4493 unsigned long addr,
22388a3c
XG		 4494 void *val, unsigned int bytes,
4495 struct x86_exception *exception,
0fbe9b0b 4496 const struct read_write_emulator_ops *ops)
bbd9b64e 4497{
0f65dd70 4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4499 gpa_t gpa;
4500 int rc;
4501
4502 if (ops->read_write_prepare &&
4503 ops->read_write_prepare(vcpu, val, bytes))
4504 return X86EMUL_CONTINUE;
4505
4506 vcpu->mmio_nr_fragments = 0;
0f65dd70 4507
bbd9b64e
CO		 4508 /* Crossing a page boundary? */
4509 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4510 int now;
bbd9b64e
CO		 4511
4512 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4513 rc = emulator_read_write_onepage(addr, val, now, exception,
4514 vcpu, ops);
4515
bbd9b64e
CO		 4516 if (rc != X86EMUL_CONTINUE)
4517 return rc;
4518 addr += now;
bac15531
NA		 4519 if (ctxt->mode != X86EMUL_MODE_PROT64)
4520 addr = (u32)addr;
bbd9b64e
CO		 4521 val += now;
4522 bytes -= now;
4523 }
22388a3c 4524
f78146b0
AK		 4525 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4526 vcpu, ops);
4527 if (rc != X86EMUL_CONTINUE)
4528 return rc;
4529
4530 if (!vcpu->mmio_nr_fragments)
4531 return rc;
4532
4533 gpa = vcpu->mmio_fragments[0].gpa;
4534
4535 vcpu->mmio_needed = 1;
4536 vcpu->mmio_cur_fragment = 0;
4537
87da7e66 4538 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4539 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4540 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4541 vcpu->run->mmio.phys_addr = gpa;
4542
4543 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4544}
4545
4546static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4547 unsigned long addr,
4548 void *val,
4549 unsigned int bytes,
4550 struct x86_exception *exception)
4551{
4552 return emulator_read_write(ctxt, addr, val, bytes,
4553 exception, &read_emultor);
4554}
4555
52eb5a6d 4556static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4557 unsigned long addr,
4558 const void *val,
4559 unsigned int bytes,
4560 struct x86_exception *exception)
4561{
4562 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4563 exception, &write_emultor);
bbd9b64e 4564}
bbd9b64e 4565
daea3e73
AK		 4566#define CMPXCHG_TYPE(t, ptr, old, new) \
4567 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4568
4569#ifdef CONFIG_X86_64
4570# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4571#else
4572# define CMPXCHG64(ptr, old, new) \
9749a6c0 4573 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4574#endif
4575
0f65dd70
AK		 4576static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4577 unsigned long addr,
bbd9b64e
CO		 4578 const void *old,
4579 const void *new,
4580 unsigned int bytes,
0f65dd70 4581 struct x86_exception *exception)
bbd9b64e 4582{
0f65dd70 4583 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4584 gpa_t gpa;
4585 struct page *page;
4586 char *kaddr;
4587 bool exchanged;
2bacc55c 4588
daea3e73
AK		 4589 /* guests cmpxchg8b have to be emulated atomically */
4590 if (bytes > 8 || (bytes & (bytes - 1)))
4591 goto emul_write;
10589a46 4592
daea3e73 4593 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4594
daea3e73
AK		 4595 if (gpa == UNMAPPED_GVA ||
4596 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4597 goto emul_write;
2bacc55c 4598
daea3e73
AK		 4599 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4600 goto emul_write;
72dc67a6 4601
daea3e73 4602 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4603 if (is_error_page(page))
c19b8bd6 4604 goto emul_write;
72dc67a6 4605
8fd75e12 4606 kaddr = kmap_atomic(page);
daea3e73
AK		 4607 kaddr += offset_in_page(gpa);
4608 switch (bytes) {
4609 case 1:
4610 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4611 break;
4612 case 2:
4613 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4614 break;
4615 case 4:
4616 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4617 break;
4618 case 8:
4619 exchanged = CMPXCHG64(kaddr, old, new);
4620 break;
4621 default:
4622 BUG();
2bacc55c 4623 }
8fd75e12 4624 kunmap_atomic(kaddr);
daea3e73
AK		 4625 kvm_release_page_dirty(page);
4626
4627 if (!exchanged)
4628 return X86EMUL_CMPXCHG_FAILED;
4629
d3714010 4630 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4631 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4632
4633 return X86EMUL_CONTINUE;
4a5f48f6 4634
3200f405 4635emul_write:
daea3e73 4636 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4637
0f65dd70 4638 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4639}
4640
cf8f70bf
GN		 4641static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4642{
4643 /* TODO: String I/O for in kernel device */
4644 int r;
4645
4646 if (vcpu->arch.pio.in)
e32edf4f 4647 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4648 vcpu->arch.pio.size, pd);
4649 else
e32edf4f 4650 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4651 vcpu->arch.pio.port, vcpu->arch.pio.size,
4652 pd);
4653 return r;
4654}
4655
6f6fbe98
XG		 4656static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4657 unsigned short port, void *val,
4658 unsigned int count, bool in)
cf8f70bf 4659{
cf8f70bf 4660 vcpu->arch.pio.port = port;
6f6fbe98 4661 vcpu->arch.pio.in = in;
7972995b 4662 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4663 vcpu->arch.pio.size = size;
4664
4665 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4666 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4667 return 1;
4668 }
4669
4670 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4671 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4672 vcpu->run->io.size = size;
4673 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4674 vcpu->run->io.count = count;
4675 vcpu->run->io.port = port;
4676
4677 return 0;
4678}
4679
6f6fbe98
XG		 4680static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4681 int size, unsigned short port, void *val,
4682 unsigned int count)
cf8f70bf 4683{
ca1d4a9e 4684 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4685 int ret;
ca1d4a9e 4686
6f6fbe98
XG		 4687 if (vcpu->arch.pio.count)
4688 goto data_avail;
cf8f70bf 4689
6f6fbe98
XG		 4690 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4691 if (ret) {
4692data_avail:
4693 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4694 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4695 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4696 return 1;
4697 }
4698
cf8f70bf
GN		 4699 return 0;
4700}
4701
6f6fbe98
XG		 4702static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4703 int size, unsigned short port,
4704 const void *val, unsigned int count)
4705{
4706 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4707
4708 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4709 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4710 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4711}
4712
bbd9b64e
CO		 4713static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4714{
4715 return kvm_x86_ops->get_segment_base(vcpu, seg);
4716}
4717
3cb16fe7 4718static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4719{
3cb16fe7 4720 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4721}
4722
5cb56059 4723int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4724{
4725 if (!need_emulate_wbinvd(vcpu))
4726 return X86EMUL_CONTINUE;
4727
4728 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4729 int cpu = get_cpu();
4730
4731 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4732 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4733 wbinvd_ipi, NULL, 1);
2eec7343 4734 put_cpu();
f5f48ee1 4735 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4736 } else
4737 wbinvd();
f5f48ee1
SY		 4738 return X86EMUL_CONTINUE;
4739}
5cb56059
JS		 4740
4741int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4742{
4743 kvm_x86_ops->skip_emulated_instruction(vcpu);
4744 return kvm_emulate_wbinvd_noskip(vcpu);
4745}
f5f48ee1
SY		 4746EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4747
5cb56059
JS		 4748
4749
bcaf5cc5
AK		 4750static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4751{
5cb56059 4752 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4753}
4754
52eb5a6d
XL		 4755static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4756 unsigned long *dest)
bbd9b64e 4757{
16f8a6f9 4758 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4759}
4760
52eb5a6d
XL		 4761static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4762 unsigned long value)
bbd9b64e 4763{
338dbc97 4764
717746e3 4765 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4766}
4767
52a46617 4768static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4769{
52a46617 4770 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4771}
4772
717746e3 4773static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4774{
717746e3 4775 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4776 unsigned long value;
4777
4778 switch (cr) {
4779 case 0:
4780 value = kvm_read_cr0(vcpu);
4781 break;
4782 case 2:
4783 value = vcpu->arch.cr2;
4784 break;
4785 case 3:
9f8fe504 4786 value = kvm_read_cr3(vcpu);
52a46617
GN		 4787 break;
4788 case 4:
4789 value = kvm_read_cr4(vcpu);
4790 break;
4791 case 8:
4792 value = kvm_get_cr8(vcpu);
4793 break;
4794 default:
a737f256 4795 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4796 return 0;
4797 }
4798
4799 return value;
4800}
4801
717746e3 4802static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4803{
717746e3 4804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4805 int res = 0;
4806
52a46617
GN		 4807 switch (cr) {
4808 case 0:
49a9b07e 4809 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4810 break;
4811 case 2:
4812 vcpu->arch.cr2 = val;
4813 break;
4814 case 3:
2390218b 4815 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4816 break;
4817 case 4:
a83b29c6 4818 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4819 break;
4820 case 8:
eea1cff9 4821 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4822 break;
4823 default:
a737f256 4824 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4825 res = -1;
52a46617 4826 }
0f12244f
GN		 4827
4828 return res;
52a46617
GN		 4829}
4830
717746e3 4831static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4832{
717746e3 4833 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4834}
4835
4bff1e86 4836static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4837{
4bff1e86 4838 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4839}
4840
4bff1e86 4841static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4842{
4bff1e86 4843 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4844}
4845
1ac9d0cf
AK		 4846static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4847{
4848 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4849}
4850
4851static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4852{
4853 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4854}
4855
4bff1e86
AK		 4856static unsigned long emulator_get_cached_segment_base(
4857 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4858{
4bff1e86 4859 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4860}
4861
1aa36616
AK		 4862static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4863 struct desc_struct *desc, u32 *base3,
4864 int seg)
2dafc6c2
GN		 4865{
4866 struct kvm_segment var;
4867
4bff1e86 4868 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4869 *selector = var.selector;
2dafc6c2 4870
378a8b09
GN		 4871 if (var.unusable) {
4872 memset(desc, 0, sizeof(*desc));
2dafc6c2 4873 return false;
378a8b09 4874 }
2dafc6c2
GN		 4875
4876 if (var.g)
4877 var.limit >>= 12;
4878 set_desc_limit(desc, var.limit);
4879 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4880#ifdef CONFIG_X86_64
4881 if (base3)
4882 *base3 = var.base >> 32;
4883#endif
2dafc6c2
GN		 4884 desc->type = var.type;
4885 desc->s = var.s;
4886 desc->dpl = var.dpl;
4887 desc->p = var.present;
4888 desc->avl = var.avl;
4889 desc->l = var.l;
4890 desc->d = var.db;
4891 desc->g = var.g;
4892
4893 return true;
4894}
4895
1aa36616
AK		 4896static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4897 struct desc_struct *desc, u32 base3,
4898 int seg)
2dafc6c2 4899{
4bff1e86 4900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4901 struct kvm_segment var;
4902
1aa36616 4903 var.selector = selector;
2dafc6c2 4904 var.base = get_desc_base(desc);
5601d05b
GN		 4905#ifdef CONFIG_X86_64
4906 var.base |= ((u64)base3) << 32;
4907#endif
2dafc6c2
GN		 4908 var.limit = get_desc_limit(desc);
4909 if (desc->g)
4910 var.limit = (var.limit << 12) | 0xfff;
4911 var.type = desc->type;
2dafc6c2
GN		 4912 var.dpl = desc->dpl;
4913 var.db = desc->d;
4914 var.s = desc->s;
4915 var.l = desc->l;
4916 var.g = desc->g;
4917 var.avl = desc->avl;
4918 var.present = desc->p;
4919 var.unusable = !var.present;
4920 var.padding = 0;
4921
4922 kvm_set_segment(vcpu, &var, seg);
4923 return;
4924}
4925
717746e3
AK		 4926static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4927 u32 msr_index, u64 *pdata)
4928{
4929 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4930}
4931
4932static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4933 u32 msr_index, u64 data)
4934{
8fe8ab46
WA		 4935 struct msr_data msr;
4936
4937 msr.data = data;
4938 msr.index = msr_index;
4939 msr.host_initiated = false;
4940 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4941}
4942
67f4d428
NA		 4943static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4944 u32 pmc)
4945{
4946 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4947}
4948
222d21aa
AK		 4949static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4950 u32 pmc, u64 *pdata)
4951{
4952 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4953}
4954
6c3287f7
AK		 4955static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4956{
4957 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4958}
4959
5037f6f3
AK		 4960static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4961{
4962 preempt_disable();
5197b808 4963 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4964 /*
4965 * CR0.TS may reference the host fpu state, not the guest fpu state,
4966 * so it may be clear at this point.
4967 */
4968 clts();
4969}
4970
4971static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4972{
4973 preempt_enable();
4974}
4975
2953538e 4976static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4977 struct x86_instruction_info *info,
c4f035c6
AK		 4978 enum x86_intercept_stage stage)
4979{
2953538e 4980 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4981}
4982
0017f93a 4983static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4984 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4985{
0017f93a 4986 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4987}
4988
dd856efa
AK		 4989static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4990{
4991 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4992}
4993
4994static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4995{
4996 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4997}
4998
801806d9
NA		 4999static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5000{
5001 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5002}
5003
0225fb50 5004static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5005 .read_gpr = emulator_read_gpr,
5006 .write_gpr = emulator_write_gpr,
1871c602 5007 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5008 .write_std = kvm_write_guest_virt_system,
1871c602 5009 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5010 .read_emulated = emulator_read_emulated,
5011 .write_emulated = emulator_write_emulated,
5012 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5013 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5014 .pio_in_emulated = emulator_pio_in_emulated,
5015 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5016 .get_segment = emulator_get_segment,
5017 .set_segment = emulator_set_segment,
5951c442 5018 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5019 .get_gdt = emulator_get_gdt,
160ce1f1 5020 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5021 .set_gdt = emulator_set_gdt,
5022 .set_idt = emulator_set_idt,
52a46617
GN		 5023 .get_cr = emulator_get_cr,
5024 .set_cr = emulator_set_cr,
9c537244 5025 .cpl = emulator_get_cpl,
35aa5375
GN		 5026 .get_dr = emulator_get_dr,
5027 .set_dr = emulator_set_dr,
717746e3
AK		 5028 .set_msr = emulator_set_msr,
5029 .get_msr = emulator_get_msr,
67f4d428 5030 .check_pmc = emulator_check_pmc,
222d21aa 5031 .read_pmc = emulator_read_pmc,
6c3287f7 5032 .halt = emulator_halt,
bcaf5cc5 5033 .wbinvd = emulator_wbinvd,
d6aa1000 5034 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5035 .get_fpu = emulator_get_fpu,
5036 .put_fpu = emulator_put_fpu,
c4f035c6 5037 .intercept = emulator_intercept,
bdb42f5a 5038 .get_cpuid = emulator_get_cpuid,
801806d9 5039 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5040};
5041
95cb2295
GN		 5042static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5043{
37ccdcbe 5044 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5045 /*
5046 * an sti; sti; sequence only disable interrupts for the first
5047 * instruction. So, if the last instruction, be it emulated or
5048 * not, left the system with the INT_STI flag enabled, it
5049 * means that the last instruction is an sti. We should not
5050 * leave the flag on in this case. The same goes for mov ss
5051 */
37ccdcbe
PB		 5052 if (int_shadow & mask)
5053 mask = 0;
6addfc42 5054 if (unlikely(int_shadow || mask)) {
95cb2295 5055 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5056 if (!mask)
5057 kvm_make_request(KVM_REQ_EVENT, vcpu);
5058 }
95cb2295
GN		 5059}
5060
ef54bcfe 5061static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5062{
5063 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5064 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5065 return kvm_propagate_fault(vcpu, &ctxt->exception);
5066
5067 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5068 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5069 ctxt->exception.error_code);
54b8486f 5070 else
da9cb575 5071 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5072 return false;
54b8486f
GN		 5073}
5074
8ec4722d
MG		 5075static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5076{
adf52235 5077 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5078 int cs_db, cs_l;
5079
8ec4722d
MG		 5080 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5081
adf52235
TY		 5082 ctxt->eflags = kvm_get_rflags(vcpu);
5083 ctxt->eip = kvm_rip_read(vcpu);
5084 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5085 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5086 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5087 cs_db ? X86EMUL_MODE_PROT32 :
5088 X86EMUL_MODE_PROT16;
5089 ctxt->guest_mode = is_guest_mode(vcpu);
5090
dd856efa 5091 init_decode_cache(ctxt);
7ae441ea 5092 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5093}
5094
71f9833b 5095int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5096{
9d74191a 5097 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5098 int ret;
5099
5100 init_emulate_ctxt(vcpu);
5101
9dac77fa
AK		 5102 ctxt->op_bytes = 2;
5103 ctxt->ad_bytes = 2;
5104 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5105 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5106
5107 if (ret != X86EMUL_CONTINUE)
5108 return EMULATE_FAIL;
5109
9dac77fa 5110 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5111 kvm_rip_write(vcpu, ctxt->eip);
5112 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5113
5114 if (irq == NMI_VECTOR)
7460fb4a 5115 vcpu->arch.nmi_pending = 0;
63995653
MG		 5116 else
5117 vcpu->arch.interrupt.pending = false;
5118
5119 return EMULATE_DONE;
5120}
5121EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5122
6d77dbfc
GN		 5123static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5124{
fc3a9157
JR		 5125 int r = EMULATE_DONE;
5126
6d77dbfc
GN		 5127 ++vcpu->stat.insn_emulation_fail;
5128 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5129 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5130 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5131 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5132 vcpu->run->internal.ndata = 0;
5133 r = EMULATE_FAIL;
5134 }
6d77dbfc 5135 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5136
5137 return r;
6d77dbfc
GN		 5138}
5139
93c05d3e 5140static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5141 bool write_fault_to_shadow_pgtable,
5142 int emulation_type)
a6f177ef 5143{
95b3cf69 5144 gpa_t gpa = cr2;
8e3d9d06 5145 pfn_t pfn;
a6f177ef 5146
991eebf9
GN		 5147 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5148 return false;
5149
95b3cf69
XG		 5150 if (!vcpu->arch.mmu.direct_map) {
5151 /*
5152 * Write permission should be allowed since only
5153 * write access need to be emulated.
5154 */
5155 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5156
95b3cf69
XG		 5157 /*
5158 * If the mapping is invalid in guest, let cpu retry
5159 * it to generate fault.
5160 */
5161 if (gpa == UNMAPPED_GVA)
5162 return true;
5163 }
a6f177ef 5164
8e3d9d06
XG		 5165 /*
5166 * Do not retry the unhandleable instruction if it faults on the
5167 * readonly host memory, otherwise it will goto a infinite loop:
5168 * retry instruction -> write #PF -> emulation fail -> retry
5169 * instruction -> ...
5170 */
5171 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5172
5173 /*
5174 * If the instruction failed on the error pfn, it can not be fixed,
5175 * report the error to userspace.
5176 */
5177 if (is_error_noslot_pfn(pfn))
5178 return false;
5179
5180 kvm_release_pfn_clean(pfn);
5181
5182 /* The instructions are well-emulated on direct mmu. */
5183 if (vcpu->arch.mmu.direct_map) {
5184 unsigned int indirect_shadow_pages;
5185
5186 spin_lock(&vcpu->kvm->mmu_lock);
5187 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5188 spin_unlock(&vcpu->kvm->mmu_lock);
5189
5190 if (indirect_shadow_pages)
5191 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5192
a6f177ef 5193 return true;
8e3d9d06 5194 }
a6f177ef 5195
95b3cf69
XG		 5196 /*
5197 * if emulation was due to access to shadowed page table
5198 * and it failed try to unshadow page and re-enter the
5199 * guest to let CPU execute the instruction.
5200 */
5201 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5202
5203 /*
5204 * If the access faults on its page table, it can not
5205 * be fixed by unprotecting shadow page and it should
5206 * be reported to userspace.
5207 */
5208 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5209}
5210
1cb3f3ae
XG		 5211static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5212 unsigned long cr2, int emulation_type)
5213{
5214 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5215 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5216
5217 last_retry_eip = vcpu->arch.last_retry_eip;
5218 last_retry_addr = vcpu->arch.last_retry_addr;
5219
5220 /*
5221 * If the emulation is caused by #PF and it is non-page_table
5222 * writing instruction, it means the VM-EXIT is caused by shadow
5223 * page protected, we can zap the shadow page and retry this
5224 * instruction directly.
5225 *
5226 * Note: if the guest uses a non-page-table modifying instruction
5227 * on the PDE that points to the instruction, then we will unmap
5228 * the instruction and go to an infinite loop. So, we cache the
5229 * last retried eip and the last fault address, if we meet the eip
5230 * and the address again, we can break out of the potential infinite
5231 * loop.
5232 */
5233 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5234
5235 if (!(emulation_type & EMULTYPE_RETRY))
5236 return false;
5237
5238 if (x86_page_table_writing_insn(ctxt))
5239 return false;
5240
5241 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5242 return false;
5243
5244 vcpu->arch.last_retry_eip = ctxt->eip;
5245 vcpu->arch.last_retry_addr = cr2;
5246
5247 if (!vcpu->arch.mmu.direct_map)
5248 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5249
22368028 5250 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5251
5252 return true;
5253}
5254
716d51ab
GN		 5255static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5256static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5257
4a1e10d5
PB		 5258static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5259 unsigned long *db)
5260{
5261 u32 dr6 = 0;
5262 int i;
5263 u32 enable, rwlen;
5264
5265 enable = dr7;
5266 rwlen = dr7 >> 16;
5267 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5268 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5269 dr6 |= (1 << i);
5270 return dr6;
5271}
5272
6addfc42 5273static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5274{
5275 struct kvm_run *kvm_run = vcpu->run;
5276
5277 /*
6addfc42
PB		 5278 * rflags is the old, "raw" value of the flags. The new value has
5279 * not been saved yet.
663f4c61
PB		 5280 *
5281 * This is correct even for TF set by the guest, because "the
5282 * processor will not generate this exception after the instruction
5283 * that sets the TF flag".
5284 */
663f4c61
PB		 5285 if (unlikely(rflags & X86_EFLAGS_TF)) {
5286 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5287 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5288 DR6_RTM;
663f4c61
PB		 5289 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5290 kvm_run->debug.arch.exception = DB_VECTOR;
5291 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5292 *r = EMULATE_USER_EXIT;
5293 } else {
5294 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5295 /*
5296 * "Certain debug exceptions may clear bit 0-3. The
5297 * remaining contents of the DR6 register are never
5298 * cleared by the processor".
5299 */
5300 vcpu->arch.dr6 &= ~15;
6f43ed01 5301 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5302 kvm_queue_exception(vcpu, DB_VECTOR);
5303 }
5304 }
5305}
5306
4a1e10d5
PB		 5307static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5308{
4a1e10d5
PB		 5309 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5310 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5311 struct kvm_run *kvm_run = vcpu->run;
5312 unsigned long eip = kvm_get_linear_rip(vcpu);
5313 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5314 vcpu->arch.guest_debug_dr7,
5315 vcpu->arch.eff_db);
5316
5317 if (dr6 != 0) {
6f43ed01 5318 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5319 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5320 kvm_run->debug.arch.exception = DB_VECTOR;
5321 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5322 *r = EMULATE_USER_EXIT;
5323 return true;
5324 }
5325 }
5326
4161a569
NA		 5327 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5328 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5329 unsigned long eip = kvm_get_linear_rip(vcpu);
5330 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5331 vcpu->arch.dr7,
5332 vcpu->arch.db);
5333
5334 if (dr6 != 0) {
5335 vcpu->arch.dr6 &= ~15;
6f43ed01 5336 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5337 kvm_queue_exception(vcpu, DB_VECTOR);
5338 *r = EMULATE_DONE;
5339 return true;
5340 }
5341 }
5342
5343 return false;
5344}
5345
51d8b661
AP		 5346int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5347 unsigned long cr2,
dc25e89e
AP		 5348 int emulation_type,
5349 void *insn,
5350 int insn_len)
bbd9b64e 5351{
95cb2295 5352 int r;
9d74191a 5353 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5354 bool writeback = true;
93c05d3e 5355 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5356
93c05d3e
XG		 5357 /*
5358 * Clear write_fault_to_shadow_pgtable here to ensure it is
5359 * never reused.
5360 */
5361 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5362 kvm_clear_exception_queue(vcpu);
8d7d8102 5363
571008da 5364 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5365 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5366
5367 /*
5368 * We will reenter on the same instruction since
5369 * we do not set complete_userspace_io. This does not
5370 * handle watchpoints yet, those would be handled in
5371 * the emulate_ops.
5372 */
5373 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5374 return r;
5375
9d74191a
TY		 5376 ctxt->interruptibility = 0;
5377 ctxt->have_exception = false;
e0ad0b47 5378 ctxt->exception.vector = -1;
9d74191a 5379 ctxt->perm_ok = false;
bbd9b64e 5380
b51e974f 5381 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5382
9d74191a 5383 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5384
e46479f8 5385 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5386 ++vcpu->stat.insn_emulation;
1d2887e2 5387 if (r != EMULATION_OK) {
4005996e
AK		 5388 if (emulation_type & EMULTYPE_TRAP_UD)
5389 return EMULATE_FAIL;
991eebf9
GN		 5390 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5391 emulation_type))
bbd9b64e 5392 return EMULATE_DONE;
6d77dbfc
GN		 5393 if (emulation_type & EMULTYPE_SKIP)
5394 return EMULATE_FAIL;
5395 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5396 }
5397 }
5398
ba8afb6b 5399 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5400 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5401 if (ctxt->eflags & X86_EFLAGS_RF)
5402 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5403 return EMULATE_DONE;
5404 }
5405
1cb3f3ae
XG		 5406 if (retry_instruction(ctxt, cr2, emulation_type))
5407 return EMULATE_DONE;
5408
7ae441ea 5409 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5410 changes registers values during IO operation */
7ae441ea
GN		 5411 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5412 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5413 emulator_invalidate_register_cache(ctxt);
7ae441ea 5414 }
4d2179e1 5415
5cd21917 5416restart:
9d74191a 5417 r = x86_emulate_insn(ctxt);
bbd9b64e 5418
775fde86
JR		 5419 if (r == EMULATION_INTERCEPTED)
5420 return EMULATE_DONE;
5421
d2ddd1c4 5422 if (r == EMULATION_FAILED) {
991eebf9
GN		 5423 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5424 emulation_type))
c3cd7ffa
GN		 5425 return EMULATE_DONE;
5426
6d77dbfc 5427 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5428 }
5429
9d74191a 5430 if (ctxt->have_exception) {
d2ddd1c4 5431 r = EMULATE_DONE;
ef54bcfe
PB		 5432 if (inject_emulated_exception(vcpu))
5433 return r;
d2ddd1c4 5434 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5435 if (!vcpu->arch.pio.in) {
5436 /* FIXME: return into emulator if single-stepping. */
3457e419 5437 vcpu->arch.pio.count = 0;
0912c977 5438 } else {
7ae441ea 5439 writeback = false;
716d51ab
GN		 5440 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5441 }
ac0a48c3 5442 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5443 } else if (vcpu->mmio_needed) {
5444 if (!vcpu->mmio_is_write)
5445 writeback = false;
ac0a48c3 5446 r = EMULATE_USER_EXIT;
716d51ab 5447 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5448 } else if (r == EMULATION_RESTART)
5cd21917 5449 goto restart;
d2ddd1c4
GN		 5450 else
5451 r = EMULATE_DONE;
f850e2e6 5452
7ae441ea 5453 if (writeback) {
6addfc42 5454 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5455 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5456 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5457 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5458 if (r == EMULATE_DONE)
6addfc42 5459 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5460 if (!ctxt->have_exception ||
5461 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5462 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5463
5464 /*
5465 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5466 * do nothing, and it will be requested again as soon as
5467 * the shadow expires. But we still need to check here,
5468 * because POPF has no interrupt shadow.
5469 */
5470 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5471 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5472 } else
5473 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5474
5475 return r;
de7d789a 5476}
51d8b661 5477EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5478
cf8f70bf 5479int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5480{
cf8f70bf 5481 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5482 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5483 size, port, &val, 1);
cf8f70bf 5484 /* do not return to emulator after return from userspace */
7972995b 5485 vcpu->arch.pio.count = 0;
de7d789a
CO		 5486 return ret;
5487}
cf8f70bf 5488EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5489
8cfdc000
ZA		 5490static void tsc_bad(void *info)
5491{
0a3aee0d 5492 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5493}
5494
5495static void tsc_khz_changed(void *data)
c8076604 5496{
8cfdc000
ZA		 5497 struct cpufreq_freqs *freq = data;
5498 unsigned long khz = 0;
5499
5500 if (data)
5501 khz = freq->new;
5502 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5503 khz = cpufreq_quick_get(raw_smp_processor_id());
5504 if (!khz)
5505 khz = tsc_khz;
0a3aee0d 5506 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5507}
5508
c8076604
GH		 5509static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5510 void *data)
5511{
5512 struct cpufreq_freqs *freq = data;
5513 struct kvm *kvm;
5514 struct kvm_vcpu *vcpu;
5515 int i, send_ipi = 0;
5516
8cfdc000
ZA		 5517 /*
5518 * We allow guests to temporarily run on slowing clocks,
5519 * provided we notify them after, or to run on accelerating
5520 * clocks, provided we notify them before. Thus time never
5521 * goes backwards.
5522 *
5523 * However, we have a problem. We can't atomically update
5524 * the frequency of a given CPU from this function; it is
5525 * merely a notifier, which can be called from any CPU.
5526 * Changing the TSC frequency at arbitrary points in time
5527 * requires a recomputation of local variables related to
5528 * the TSC for each VCPU. We must flag these local variables
5529 * to be updated and be sure the update takes place with the
5530 * new frequency before any guests proceed.
5531 *
5532 * Unfortunately, the combination of hotplug CPU and frequency
5533 * change creates an intractable locking scenario; the order
5534 * of when these callouts happen is undefined with respect to
5535 * CPU hotplug, and they can race with each other. As such,
5536 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5537 * undefined; you can actually have a CPU frequency change take
5538 * place in between the computation of X and the setting of the
5539 * variable. To protect against this problem, all updates of
5540 * the per_cpu tsc_khz variable are done in an interrupt
5541 * protected IPI, and all callers wishing to update the value
5542 * must wait for a synchronous IPI to complete (which is trivial
5543 * if the caller is on the CPU already). This establishes the
5544 * necessary total order on variable updates.
5545 *
5546 * Note that because a guest time update may take place
5547 * anytime after the setting of the VCPU's request bit, the
5548 * correct TSC value must be set before the request. However,
5549 * to ensure the update actually makes it to any guest which
5550 * starts running in hardware virtualization between the set
5551 * and the acquisition of the spinlock, we must also ping the
5552 * CPU after setting the request bit.
5553 *
5554 */
5555
c8076604
GH		 5556 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5557 return 0;
5558 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5559 return 0;
8cfdc000
ZA		 5560
5561 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5562
2f303b74 5563 spin_lock(&kvm_lock);
c8076604 5564 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5565 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5566 if (vcpu->cpu != freq->cpu)
5567 continue;
c285545f 5568 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5569 if (vcpu->cpu != smp_processor_id())
8cfdc000 5570 send_ipi = 1;
c8076604
GH		 5571 }
5572 }
2f303b74 5573 spin_unlock(&kvm_lock);
c8076604
GH		 5574
5575 if (freq->old < freq->new && send_ipi) {
5576 /*
5577 * We upscale the frequency. Must make the guest
5578 * doesn't see old kvmclock values while running with
5579 * the new frequency, otherwise we risk the guest sees
5580 * time go backwards.
5581 *
5582 * In case we update the frequency for another cpu
5583 * (which might be in guest context) send an interrupt
5584 * to kick the cpu out of guest context. Next time
5585 * guest context is entered kvmclock will be updated,
5586 * so the guest will not see stale values.
5587 */
8cfdc000 5588 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5589 }
5590 return 0;
5591}
5592
5593static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5594 .notifier_call = kvmclock_cpufreq_notifier
5595};
5596
5597static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5598 unsigned long action, void *hcpu)
5599{
5600 unsigned int cpu = (unsigned long)hcpu;
5601
5602 switch (action) {
5603 case CPU_ONLINE:
5604 case CPU_DOWN_FAILED:
5605 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5606 break;
5607 case CPU_DOWN_PREPARE:
5608 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5609 break;
5610 }
5611 return NOTIFY_OK;
5612}
5613
5614static struct notifier_block kvmclock_cpu_notifier_block = {
5615 .notifier_call = kvmclock_cpu_notifier,
5616 .priority = -INT_MAX
c8076604
GH		 5617};
5618
b820cc0c
ZA		 5619static void kvm_timer_init(void)
5620{
5621 int cpu;
5622
c285545f 5623 max_tsc_khz = tsc_khz;
460dd42e
SB		 5624
5625 cpu_notifier_register_begin();
b820cc0c 5626 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5627#ifdef CONFIG_CPU_FREQ
5628 struct cpufreq_policy policy;
5629 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5630 cpu = get_cpu();
5631 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5632 if (policy.cpuinfo.max_freq)
5633 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5634 put_cpu();
c285545f 5635#endif
b820cc0c
ZA		 5636 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5637 CPUFREQ_TRANSITION_NOTIFIER);
5638 }
c285545f 5639 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5640 for_each_online_cpu(cpu)
5641 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5642
5643 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5644 cpu_notifier_register_done();
5645
b820cc0c
ZA		 5646}
5647
ff9d07a0
ZY		 5648static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5649
f5132b01 5650int kvm_is_in_guest(void)
ff9d07a0 5651{
086c9855 5652 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5653}
5654
5655static int kvm_is_user_mode(void)
5656{
5657 int user_mode = 3;
dcf46b94 5658
086c9855
AS		 5659 if (__this_cpu_read(current_vcpu))
5660 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5661
ff9d07a0
ZY		 5662 return user_mode != 0;
5663}
5664
5665static unsigned long kvm_get_guest_ip(void)
5666{
5667 unsigned long ip = 0;
dcf46b94 5668
086c9855
AS		 5669 if (__this_cpu_read(current_vcpu))
5670 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5671
ff9d07a0
ZY		 5672 return ip;
5673}
5674
5675static struct perf_guest_info_callbacks kvm_guest_cbs = {
5676 .is_in_guest = kvm_is_in_guest,
5677 .is_user_mode = kvm_is_user_mode,
5678 .get_guest_ip = kvm_get_guest_ip,
5679};
5680
5681void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5682{
086c9855 5683 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5684}
5685EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5686
5687void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5688{
086c9855 5689 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5690}
5691EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5692
ce88decf
XG		 5693static void kvm_set_mmio_spte_mask(void)
5694{
5695 u64 mask;
5696 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5697
5698 /*
5699 * Set the reserved bits and the present bit of an paging-structure
5700 * entry to generate page fault with PFER.RSV = 1.
5701 */
885032b9 5702 /* Mask the reserved physical address bits. */
d1431483 5703 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5704
5705 /* Bit 62 is always reserved for 32bit host. */
5706 mask |= 0x3ull << 62;
5707
5708 /* Set the present bit. */
ce88decf
XG		 5709 mask |= 1ull;
5710
5711#ifdef CONFIG_X86_64
5712 /*
5713 * If reserved bit is not supported, clear the present bit to disable
5714 * mmio page fault.
5715 */
5716 if (maxphyaddr == 52)
5717 mask &= ~1ull;
5718#endif
5719
5720 kvm_mmu_set_mmio_spte_mask(mask);
5721}
5722
16e8d74d
MT		 5723#ifdef CONFIG_X86_64
5724static void pvclock_gtod_update_fn(struct work_struct *work)
5725{
d828199e
MT		 5726 struct kvm *kvm;
5727
5728 struct kvm_vcpu *vcpu;
5729 int i;
5730
2f303b74 5731 spin_lock(&kvm_lock);
d828199e
MT		 5732 list_for_each_entry(kvm, &vm_list, vm_list)
5733 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5734 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5735 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5736 spin_unlock(&kvm_lock);
16e8d74d
MT		 5737}
5738
5739static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5740
5741/*
5742 * Notification about pvclock gtod data update.
5743 */
5744static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5745 void *priv)
5746{
5747 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5748 struct timekeeper *tk = priv;
5749
5750 update_pvclock_gtod(tk);
5751
5752 /* disable master clock if host does not trust, or does not
5753 * use, TSC clocksource
5754 */
5755 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5756 atomic_read(&kvm_guest_has_master_clock) != 0)
5757 queue_work(system_long_wq, &pvclock_gtod_work);
5758
5759 return 0;
5760}
5761
5762static struct notifier_block pvclock_gtod_notifier = {
5763 .notifier_call = pvclock_gtod_notify,
5764};
5765#endif
5766
f8c16bba 5767int kvm_arch_init(void *opaque)
043405e1 5768{
b820cc0c 5769 int r;
6b61edf7 5770 struct kvm_x86_ops *ops = opaque;
f8c16bba 5771
f8c16bba
ZX		 5772 if (kvm_x86_ops) {
5773 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5774 r = -EEXIST;
5775 goto out;
f8c16bba
ZX		 5776 }
5777
5778 if (!ops->cpu_has_kvm_support()) {
5779 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5780 r = -EOPNOTSUPP;
5781 goto out;
f8c16bba
ZX		 5782 }
5783 if (ops->disabled_by_bios()) {
5784 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5785 r = -EOPNOTSUPP;
5786 goto out;
f8c16bba
ZX		 5787 }
5788
013f6a5d
MT		 5789 r = -ENOMEM;
5790 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5791 if (!shared_msrs) {
5792 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5793 goto out;
5794 }
5795
97db56ce
AK		 5796 r = kvm_mmu_module_init();
5797 if (r)
013f6a5d 5798 goto out_free_percpu;
97db56ce 5799
ce88decf 5800 kvm_set_mmio_spte_mask();
97db56ce 5801
f8c16bba 5802 kvm_x86_ops = ops;
920c8377
PB		 5803 kvm_init_msr_list();
5804
7b52345e 5805 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5806 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5807
b820cc0c 5808 kvm_timer_init();
c8076604 5809
ff9d07a0
ZY		 5810 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5811
2acf923e
DC		 5812 if (cpu_has_xsave)
5813 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5814
c5cc421b 5815 kvm_lapic_init();
16e8d74d
MT		 5816#ifdef CONFIG_X86_64
5817 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5818#endif
5819
f8c16bba 5820 return 0;
56c6d28a 5821
013f6a5d
MT		 5822out_free_percpu:
5823 free_percpu(shared_msrs);
56c6d28a 5824out:
56c6d28a 5825 return r;
043405e1 5826}
8776e519 5827
f8c16bba
ZX		 5828void kvm_arch_exit(void)
5829{
ff9d07a0
ZY		 5830 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5831
888d256e
JK		 5832 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5833 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5834 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5835 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5836#ifdef CONFIG_X86_64
5837 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5838#endif
f8c16bba 5839 kvm_x86_ops = NULL;
56c6d28a 5840 kvm_mmu_module_exit();
013f6a5d 5841 free_percpu(shared_msrs);
56c6d28a 5842}
f8c16bba 5843
5cb56059 5844int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5845{
5846 ++vcpu->stat.halt_exits;
5847 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5848 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5849 return 1;
5850 } else {
5851 vcpu->run->exit_reason = KVM_EXIT_HLT;
5852 return 0;
5853 }
5854}
5cb56059
JS		 5855EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5856
5857int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5858{
5859 kvm_x86_ops->skip_emulated_instruction(vcpu);
5860 return kvm_vcpu_halt(vcpu);
5861}
8776e519
HB		 5862EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5863
55cd8e5a
GN		 5864int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5865{
5866 u64 param, ingpa, outgpa, ret;
5867 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5868 bool fast, longmode;
55cd8e5a
GN		 5869
5870 /*
5871 * hypercall generates UD from non zero cpl and real mode
5872 * per HYPER-V spec
5873 */
3eeb3288 5874 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5875 kvm_queue_exception(vcpu, UD_VECTOR);
5876 return 0;
5877 }
5878
a449c7aa 5879 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5880
5881 if (!longmode) {
ccd46936
GN		 5882 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5883 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5884 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5885 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5886 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5887 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5888 }
5889#ifdef CONFIG_X86_64
5890 else {
5891 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5892 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5893 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5894 }
5895#endif
5896
5897 code = param & 0xffff;
5898 fast = (param >> 16) & 0x1;
5899 rep_cnt = (param >> 32) & 0xfff;
5900 rep_idx = (param >> 48) & 0xfff;
5901
5902 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5903
c25bc163
GN		 5904 switch (code) {
5905 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5906 kvm_vcpu_on_spin(vcpu);
5907 break;
5908 default:
5909 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5910 break;
5911 }
55cd8e5a
GN		 5912
5913 ret = res | (((u64)rep_done & 0xfff) << 32);
5914 if (longmode) {
5915 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5916 } else {
5917 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5918 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5919 }
5920
5921 return 1;
5922}
5923
6aef266c
SV		 5924/*
5925 * kvm_pv_kick_cpu_op: Kick a vcpu.
5926 *
5927 * @apicid - apicid of vcpu to be kicked.
5928 */
5929static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5930{
24d2166b 5931 struct kvm_lapic_irq lapic_irq;
6aef266c 5932
24d2166b
R		 5933 lapic_irq.shorthand = 0;
5934 lapic_irq.dest_mode = 0;
5935 lapic_irq.dest_id = apicid;
6aef266c 5936
24d2166b 5937 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5938 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5939}
5940
8776e519
HB		 5941int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5942{
5943 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5944 int op_64_bit, r = 1;
8776e519 5945
5cb56059
JS		 5946 kvm_x86_ops->skip_emulated_instruction(vcpu);
5947
55cd8e5a
GN		 5948 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5949 return kvm_hv_hypercall(vcpu);
5950
5fdbf976
MT		 5951 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5952 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5953 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5954 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5955 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5956
229456fc 5957 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5958
a449c7aa
NA		 5959 op_64_bit = is_64_bit_mode(vcpu);
5960 if (!op_64_bit) {
8776e519
HB		 5961 nr &= 0xFFFFFFFF;
5962 a0 &= 0xFFFFFFFF;
5963 a1 &= 0xFFFFFFFF;
5964 a2 &= 0xFFFFFFFF;
5965 a3 &= 0xFFFFFFFF;
5966 }
5967
07708c4a
JK		 5968 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5969 ret = -KVM_EPERM;
5970 goto out;
5971 }
5972
8776e519 5973 switch (nr) {
b93463aa
AK		 5974 case KVM_HC_VAPIC_POLL_IRQ:
5975 ret = 0;
5976 break;
6aef266c
SV		 5977 case KVM_HC_KICK_CPU:
5978 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5979 ret = 0;
5980 break;
8776e519
HB		 5981 default:
5982 ret = -KVM_ENOSYS;
5983 break;
5984 }
07708c4a 5985out:
a449c7aa
NA		 5986 if (!op_64_bit)
5987 ret = (u32)ret;
5fdbf976 5988 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5989 ++vcpu->stat.hypercalls;
2f333bcb 5990 return r;
8776e519
HB		 5991}
5992EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5993
b6785def 5994static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5995{
d6aa1000 5996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5997 char instruction[3];
5fdbf976 5998 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5999
8776e519 6000 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6001
9d74191a 6002 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6003}
6004
b6c7a5dc
HB		 6005/*
6006 * Check if userspace requested an interrupt window, and that the
6007 * interrupt window is open.
6008 *
6009 * No need to exit to userspace if we already have an interrupt queued.
6010 */
851ba692 6011static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6012{
8061823a 6013 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6014 vcpu->run->request_interrupt_window &&
5df56646 6015 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6016}
6017
851ba692 6018static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6019{
851ba692
AK		 6020 struct kvm_run *kvm_run = vcpu->run;
6021
91586a3b 6022 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6023 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6024 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6025 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6026 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6027 else
b6c7a5dc 6028 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6029 kvm_arch_interrupt_allowed(vcpu) &&
6030 !kvm_cpu_has_interrupt(vcpu) &&
6031 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6032}
6033
95ba8273
GN		 6034static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6035{
6036 int max_irr, tpr;
6037
6038 if (!kvm_x86_ops->update_cr8_intercept)
6039 return;
6040
88c808fd
AK		 6041 if (!vcpu->arch.apic)
6042 return;
6043
8db3baa2
GN		 6044 if (!vcpu->arch.apic->vapic_addr)
6045 max_irr = kvm_lapic_find_highest_irr(vcpu);
6046 else
6047 max_irr = -1;
95ba8273
GN		 6048
6049 if (max_irr != -1)
6050 max_irr >>= 4;
6051
6052 tpr = kvm_lapic_get_cr8(vcpu);
6053
6054 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6055}
6056
b6b8a145 6057static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6058{
b6b8a145
JK		 6059 int r;
6060
95ba8273 6061 /* try to reinject previous events if any */
b59bb7bd 6062 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6063 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6064 vcpu->arch.exception.has_error_code,
6065 vcpu->arch.exception.error_code);
d6e8c854
NA		 6066
6067 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6068 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6069 X86_EFLAGS_RF);
6070
6bdf0662
NA		 6071 if (vcpu->arch.exception.nr == DB_VECTOR &&
6072 (vcpu->arch.dr7 & DR7_GD)) {
6073 vcpu->arch.dr7 &= ~DR7_GD;
6074 kvm_update_dr7(vcpu);
6075 }
6076
b59bb7bd
GN		 6077 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6078 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6079 vcpu->arch.exception.error_code,
6080 vcpu->arch.exception.reinject);
b6b8a145 6081 return 0;
b59bb7bd
GN		 6082 }
6083
95ba8273
GN		 6084 if (vcpu->arch.nmi_injected) {
6085 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6086 return 0;
95ba8273
GN		 6087 }
6088
6089 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6090 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6091 return 0;
6092 }
6093
6094 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6095 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6096 if (r != 0)
6097 return r;
95ba8273
GN		 6098 }
6099
6100 /* try to inject new event if pending */
6101 if (vcpu->arch.nmi_pending) {
6102 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6103 --vcpu->arch.nmi_pending;
95ba8273
GN		 6104 vcpu->arch.nmi_injected = true;
6105 kvm_x86_ops->set_nmi(vcpu);
6106 }
c7c9c56c 6107 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6108 /*
6109 * Because interrupts can be injected asynchronously, we are
6110 * calling check_nested_events again here to avoid a race condition.
6111 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6112 * proposal and current concerns. Perhaps we should be setting
6113 * KVM_REQ_EVENT only on certain events and not unconditionally?
6114 */
6115 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6116 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6117 if (r != 0)
6118 return r;
6119 }
95ba8273 6120 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6121 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6122 false);
6123 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6124 }
6125 }
b6b8a145 6126 return 0;
95ba8273
GN		 6127}
6128
7460fb4a
AK		 6129static void process_nmi(struct kvm_vcpu *vcpu)
6130{
6131 unsigned limit = 2;
6132
6133 /*
6134 * x86 is limited to one NMI running, and one NMI pending after it.
6135 * If an NMI is already in progress, limit further NMIs to just one.
6136 * Otherwise, allow two (and we'll inject the first one immediately).
6137 */
6138 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6139 limit = 1;
6140
6141 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6142 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6143 kvm_make_request(KVM_REQ_EVENT, vcpu);
6144}
6145
3d81bc7e 6146static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6147{
6148 u64 eoi_exit_bitmap[4];
cf9e65b7 6149 u32 tmr[8];
c7c9c56c 6150
3d81bc7e
YZ		 6151 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6152 return;
c7c9c56c
YZ		 6153
6154 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6155 memset(tmr, 0, 32);
c7c9c56c 6156
cf9e65b7 6157 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6158 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6159 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6160}
6161
a70656b6
RK		 6162static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6163{
6164 ++vcpu->stat.tlb_flush;
6165 kvm_x86_ops->tlb_flush(vcpu);
6166}
6167
4256f43f
TC		 6168void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6169{
c24ae0dc
TC		 6170 struct page *page = NULL;
6171
f439ed27
PB		 6172 if (!irqchip_in_kernel(vcpu->kvm))
6173 return;
6174
4256f43f
TC		 6175 if (!kvm_x86_ops->set_apic_access_page_addr)
6176 return;
6177
c24ae0dc
TC		 6178 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6179 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6180
6181 /*
6182 * Do not pin apic access page in memory, the MMU notifier
6183 * will call us again if it is migrated or swapped out.
6184 */
6185 put_page(page);
4256f43f
TC		 6186}
6187EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6188
fe71557a
TC		 6189void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6190 unsigned long address)
6191{
c24ae0dc
TC		 6192 /*
6193 * The physical address of apic access page is stored in the VMCS.
6194 * Update it when it becomes invalid.
6195 */
6196 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6197 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6198}
6199
9357d939 6200/*
362c698f 6201 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6202 * exiting to the userspace. Otherwise, the value will be returned to the
6203 * userspace.
6204 */
851ba692 6205static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6206{
6207 int r;
6a8b1d13 6208 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6209 vcpu->run->request_interrupt_window;
730dca42 6210 bool req_immediate_exit = false;
b6c7a5dc 6211
3e007509 6212 if (vcpu->requests) {
a8eeb04a 6213 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6214 kvm_mmu_unload(vcpu);
a8eeb04a 6215 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6216 __kvm_migrate_timers(vcpu);
d828199e
MT		 6217 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6218 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6219 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6220 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6221 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6222 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6223 if (unlikely(r))
6224 goto out;
6225 }
a8eeb04a 6226 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6227 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6228 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6229 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6230 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6231 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6232 r = 0;
6233 goto out;
6234 }
a8eeb04a 6235 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6236 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6237 r = 0;
6238 goto out;
6239 }
a8eeb04a 6240 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6241 vcpu->fpu_active = 0;
6242 kvm_x86_ops->fpu_deactivate(vcpu);
6243 }
af585b92
GN		 6244 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6245 /* Page is swapped out. Do synthetic halt */
6246 vcpu->arch.apf.halted = true;
6247 r = 1;
6248 goto out;
6249 }
c9aaa895
GC		 6250 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6251 record_steal_time(vcpu);
7460fb4a
AK		 6252 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6253 process_nmi(vcpu);
f5132b01
GN		 6254 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6255 kvm_handle_pmu_event(vcpu);
6256 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6257 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6258 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6259 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6260 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6261 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6262 }
b93463aa 6263
b463a6f7 6264 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6265 kvm_apic_accept_events(vcpu);
6266 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6267 r = 1;
6268 goto out;
6269 }
6270
b6b8a145
JK		 6271 if (inject_pending_event(vcpu, req_int_win) != 0)
6272 req_immediate_exit = true;
b463a6f7 6273 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6274 else if (vcpu->arch.nmi_pending)
c9a7953f 6275 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6276 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6277 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6278
6279 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6280 /*
6281 * Update architecture specific hints for APIC
6282 * virtual interrupt delivery.
6283 */
6284 if (kvm_x86_ops->hwapic_irr_update)
6285 kvm_x86_ops->hwapic_irr_update(vcpu,
6286 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6287 update_cr8_intercept(vcpu);
6288 kvm_lapic_sync_to_vapic(vcpu);
6289 }
6290 }
6291
d8368af8
AK		 6292 r = kvm_mmu_reload(vcpu);
6293 if (unlikely(r)) {
d905c069 6294 goto cancel_injection;
d8368af8
AK		 6295 }
6296
b6c7a5dc
HB		 6297 preempt_disable();
6298
6299 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6300 if (vcpu->fpu_active)
6301 kvm_load_guest_fpu(vcpu);
2acf923e 6302 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6303
6b7e2d09
XG		 6304 vcpu->mode = IN_GUEST_MODE;
6305
01b71917
MT		 6306 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6307
6b7e2d09
XG		 6308 /* We should set ->mode before check ->requests,
6309 * see the comment in make_all_cpus_request.
6310 */
01b71917 6311 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6312
d94e1dc9 6313 local_irq_disable();
32f88400 6314
6b7e2d09 6315 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6316 || need_resched() || signal_pending(current)) {
6b7e2d09 6317 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6318 smp_wmb();
6c142801
AK		 6319 local_irq_enable();
6320 preempt_enable();
01b71917 6321 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6322 r = 1;
d905c069 6323 goto cancel_injection;
6c142801
AK		 6324 }
6325
d6185f20
NHE		 6326 if (req_immediate_exit)
6327 smp_send_reschedule(vcpu->cpu);
6328
b6c7a5dc
HB		 6329 kvm_guest_enter();
6330
42dbaa5a 6331 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6332 set_debugreg(0, 7);
6333 set_debugreg(vcpu->arch.eff_db[0], 0);
6334 set_debugreg(vcpu->arch.eff_db[1], 1);
6335 set_debugreg(vcpu->arch.eff_db[2], 2);
6336 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6337 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6338 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6339 }
b6c7a5dc 6340
229456fc 6341 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6342 wait_lapic_expire(vcpu);
851ba692 6343 kvm_x86_ops->run(vcpu);
b6c7a5dc 6344
c77fb5fe
PB		 6345 /*
6346 * Do this here before restoring debug registers on the host. And
6347 * since we do this before handling the vmexit, a DR access vmexit
6348 * can (a) read the correct value of the debug registers, (b) set
6349 * KVM_DEBUGREG_WONT_EXIT again.
6350 */
6351 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6352 int i;
6353
6354 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6355 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6356 for (i = 0; i < KVM_NR_DB_REGS; i++)
6357 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6358 }
6359
24f1e32c
FW		 6360 /*
6361 * If the guest has used debug registers, at least dr7
6362 * will be disabled while returning to the host.
6363 * If we don't have active breakpoints in the host, we don't
6364 * care about the messed up debug address registers. But if
6365 * we have some of them active, restore the old state.
6366 */
59d8eb53 6367 if (hw_breakpoint_active())
24f1e32c 6368 hw_breakpoint_restore();
42dbaa5a 6369
886b470c
MT		 6370 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6371 native_read_tsc());
1d5f066e 6372
6b7e2d09 6373 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6374 smp_wmb();
a547c6db
YZ		 6375
6376 /* Interrupt is enabled by handle_external_intr() */
6377 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6378
6379 ++vcpu->stat.exits;
6380
6381 /*
6382 * We must have an instruction between local_irq_enable() and
6383 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6384 * the interrupt shadow. The stat.exits increment will do nicely.
6385 * But we need to prevent reordering, hence this barrier():
6386 */
6387 barrier();
6388
6389 kvm_guest_exit();
6390
6391 preempt_enable();
6392
f656ce01 6393 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6394
b6c7a5dc
HB		 6395 /*
6396 * Profile KVM exit RIPs:
6397 */
6398 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6399 unsigned long rip = kvm_rip_read(vcpu);
6400 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6401 }
6402
cc578287
ZA		 6403 if (unlikely(vcpu->arch.tsc_always_catchup))
6404 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6405
5cfb1d5a
MT		 6406 if (vcpu->arch.apic_attention)
6407 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6408
851ba692 6409 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6410 return r;
6411
6412cancel_injection:
6413 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6414 if (unlikely(vcpu->arch.apic_attention))
6415 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6416out:
6417 return r;
6418}
b6c7a5dc 6419
362c698f
PB		 6420static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6421{
9c8fd1ba
PB		 6422 if (!kvm_arch_vcpu_runnable(vcpu)) {
6423 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6424 kvm_vcpu_block(vcpu);
6425 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6426 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6427 return 1;
6428 }
362c698f
PB		 6429
6430 kvm_apic_accept_events(vcpu);
6431 switch(vcpu->arch.mp_state) {
6432 case KVM_MP_STATE_HALTED:
6433 vcpu->arch.pv.pv_unhalted = false;
6434 vcpu->arch.mp_state =
6435 KVM_MP_STATE_RUNNABLE;
6436 case KVM_MP_STATE_RUNNABLE:
6437 vcpu->arch.apf.halted = false;
6438 break;
6439 case KVM_MP_STATE_INIT_RECEIVED:
6440 break;
6441 default:
6442 return -EINTR;
6443 break;
6444 }
6445 return 1;
6446}
6447
6448static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6449{
6450 int r;
f656ce01 6451 struct kvm *kvm = vcpu->kvm;
d7690175 6452
f656ce01 6453 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6454
362c698f 6455 for (;;) {
af585b92
GN		 6456 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6457 !vcpu->arch.apf.halted)
851ba692 6458 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6459 else
6460 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6461 if (r <= 0)
6462 break;
6463
6464 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6465 if (kvm_cpu_has_pending_timer(vcpu))
6466 kvm_inject_pending_timer_irqs(vcpu);
6467
851ba692 6468 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6469 r = -EINTR;
851ba692 6470 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6471 ++vcpu->stat.request_irq_exits;
362c698f 6472 break;
09cec754 6473 }
af585b92
GN		 6474
6475 kvm_check_async_pf_completion(vcpu);
6476
09cec754
GN		 6477 if (signal_pending(current)) {
6478 r = -EINTR;
851ba692 6479 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6480 ++vcpu->stat.signal_exits;
362c698f 6481 break;
09cec754
GN		 6482 }
6483 if (need_resched()) {
f656ce01 6484 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6485 cond_resched();
f656ce01 6486 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6487 }
b6c7a5dc
HB		 6488 }
6489
f656ce01 6490 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6491
6492 return r;
6493}
6494
716d51ab
GN		 6495static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6496{
6497 int r;
6498 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6499 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6500 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6501 if (r != EMULATE_DONE)
6502 return 0;
6503 return 1;
6504}
6505
6506static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6507{
6508 BUG_ON(!vcpu->arch.pio.count);
6509
6510 return complete_emulated_io(vcpu);
6511}
6512
f78146b0
AK		 6513/*
6514 * Implements the following, as a state machine:
6515 *
6516 * read:
6517 * for each fragment
87da7e66
XG		 6518 * for each mmio piece in the fragment
6519 * write gpa, len
6520 * exit
6521 * copy data
f78146b0
AK		 6522 * execute insn
6523 *
6524 * write:
6525 * for each fragment
87da7e66
XG		 6526 * for each mmio piece in the fragment
6527 * write gpa, len
6528 * copy data
6529 * exit
f78146b0 6530 */
716d51ab 6531static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6532{
6533 struct kvm_run *run = vcpu->run;
f78146b0 6534 struct kvm_mmio_fragment *frag;
87da7e66 6535 unsigned len;
5287f194 6536
716d51ab 6537 BUG_ON(!vcpu->mmio_needed);
5287f194 6538
716d51ab 6539 /* Complete previous fragment */
87da7e66
XG		 6540 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6541 len = min(8u, frag->len);
716d51ab 6542 if (!vcpu->mmio_is_write)
87da7e66
XG		 6543 memcpy(frag->data, run->mmio.data, len);
6544
6545 if (frag->len <= 8) {
6546 /* Switch to the next fragment. */
6547 frag++;
6548 vcpu->mmio_cur_fragment++;
6549 } else {
6550 /* Go forward to the next mmio piece. */
6551 frag->data += len;
6552 frag->gpa += len;
6553 frag->len -= len;
6554 }
6555
a08d3b3b 6556 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6557 vcpu->mmio_needed = 0;
0912c977
PB		 6558
6559 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6560 if (vcpu->mmio_is_write)
716d51ab
GN		 6561 return 1;
6562 vcpu->mmio_read_completed = 1;
6563 return complete_emulated_io(vcpu);
6564 }
87da7e66 6565
716d51ab
GN		 6566 run->exit_reason = KVM_EXIT_MMIO;
6567 run->mmio.phys_addr = frag->gpa;
6568 if (vcpu->mmio_is_write)
87da7e66
XG		 6569 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6570 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6571 run->mmio.is_write = vcpu->mmio_is_write;
6572 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6573 return 0;
5287f194
AK		 6574}
6575
716d51ab 6576
b6c7a5dc
HB		 6577int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6578{
6579 int r;
6580 sigset_t sigsaved;
6581
e5c30142
AK		 6582 if (!tsk_used_math(current) && init_fpu(current))
6583 return -ENOMEM;
6584
ac9f6dc0
AK		 6585 if (vcpu->sigset_active)
6586 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6587
a4535290 6588 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6589 kvm_vcpu_block(vcpu);
66450a21 6590 kvm_apic_accept_events(vcpu);
d7690175 6591 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6592 r = -EAGAIN;
6593 goto out;
b6c7a5dc
HB		 6594 }
6595
b6c7a5dc 6596 /* re-sync apic's tpr */
eea1cff9
AP		 6597 if (!irqchip_in_kernel(vcpu->kvm)) {
6598 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6599 r = -EINVAL;
6600 goto out;
6601 }
6602 }
b6c7a5dc 6603
716d51ab
GN		 6604 if (unlikely(vcpu->arch.complete_userspace_io)) {
6605 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6606 vcpu->arch.complete_userspace_io = NULL;
6607 r = cui(vcpu);
6608 if (r <= 0)
6609 goto out;
6610 } else
6611 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6612
362c698f 6613 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6614
6615out:
f1d86e46 6616 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6617 if (vcpu->sigset_active)
6618 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6619
b6c7a5dc
HB		 6620 return r;
6621}
6622
6623int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6624{
7ae441ea
GN		 6625 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6626 /*
6627 * We are here if userspace calls get_regs() in the middle of
6628 * instruction emulation. Registers state needs to be copied
4a969980 6629 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6630 * that usually, but some bad designed PV devices (vmware
6631 * backdoor interface) need this to work
6632 */
dd856efa 6633 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6634 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6635 }
5fdbf976
MT		 6636 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6637 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6638 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6639 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6640 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6641 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6642 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6643 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6644#ifdef CONFIG_X86_64
5fdbf976
MT		 6645 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6646 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6647 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6648 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6649 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6650 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6651 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6652 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6653#endif
6654
5fdbf976 6655 regs->rip = kvm_rip_read(vcpu);
91586a3b 6656 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6657
b6c7a5dc
HB		 6658 return 0;
6659}
6660
6661int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6662{
7ae441ea
GN		 6663 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6664 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6665
5fdbf976
MT		 6666 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6667 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6668 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6669 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6670 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6671 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6672 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6673 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6674#ifdef CONFIG_X86_64
5fdbf976
MT		 6675 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6676 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6677 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6678 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6679 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6680 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6681 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6682 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6683#endif
6684
5fdbf976 6685 kvm_rip_write(vcpu, regs->rip);
91586a3b 6686 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6687
b4f14abd
JK		 6688 vcpu->arch.exception.pending = false;
6689
3842d135
AK		 6690 kvm_make_request(KVM_REQ_EVENT, vcpu);
6691
b6c7a5dc
HB		 6692 return 0;
6693}
6694
b6c7a5dc
HB		 6695void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6696{
6697 struct kvm_segment cs;
6698
3e6e0aab 6699 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6700 *db = cs.db;
6701 *l = cs.l;
6702}
6703EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6704
6705int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6706 struct kvm_sregs *sregs)
6707{
89a27f4d 6708 struct desc_ptr dt;
b6c7a5dc 6709
3e6e0aab
GT		 6710 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6711 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6712 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6713 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6714 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6715 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6716
3e6e0aab
GT		 6717 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6718 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6719
6720 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6721 sregs->idt.limit = dt.size;
6722 sregs->idt.base = dt.address;
b6c7a5dc 6723 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6724 sregs->gdt.limit = dt.size;
6725 sregs->gdt.base = dt.address;
b6c7a5dc 6726
4d4ec087 6727 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6728 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6729 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6730 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6731 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6732 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6733 sregs->apic_base = kvm_get_apic_base(vcpu);
6734
923c61bb 6735 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6736
36752c9b 6737 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6738 set_bit(vcpu->arch.interrupt.nr,
6739 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6740
b6c7a5dc
HB		 6741 return 0;
6742}
6743
62d9f0db
MT		 6744int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6745 struct kvm_mp_state *mp_state)
6746{
66450a21 6747 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6748 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6749 vcpu->arch.pv.pv_unhalted)
6750 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6751 else
6752 mp_state->mp_state = vcpu->arch.mp_state;
6753
62d9f0db
MT		 6754 return 0;
6755}
6756
6757int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6758 struct kvm_mp_state *mp_state)
6759{
66450a21
JK		 6760 if (!kvm_vcpu_has_lapic(vcpu) &&
6761 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6762 return -EINVAL;
6763
6764 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6765 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6766 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6767 } else
6768 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6769 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6770 return 0;
6771}
6772
7f3d35fd
KW		 6773int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6774 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6775{
9d74191a 6776 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6777 int ret;
e01c2426 6778
8ec4722d 6779 init_emulate_ctxt(vcpu);
c697518a 6780
7f3d35fd 6781 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6782 has_error_code, error_code);
c697518a 6783
c697518a 6784 if (ret)
19d04437 6785 return EMULATE_FAIL;
37817f29 6786
9d74191a
TY		 6787 kvm_rip_write(vcpu, ctxt->eip);
6788 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6789 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6790 return EMULATE_DONE;
37817f29
IE		 6791}
6792EXPORT_SYMBOL_GPL(kvm_task_switch);
6793
b6c7a5dc
HB		 6794int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6795 struct kvm_sregs *sregs)
6796{
58cb628d 6797 struct msr_data apic_base_msr;
b6c7a5dc 6798 int mmu_reset_needed = 0;
63f42e02 6799 int pending_vec, max_bits, idx;
89a27f4d 6800 struct desc_ptr dt;
b6c7a5dc 6801
6d1068b3
PM		 6802 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6803 return -EINVAL;
6804
89a27f4d
GN		 6805 dt.size = sregs->idt.limit;
6806 dt.address = sregs->idt.base;
b6c7a5dc 6807 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6808 dt.size = sregs->gdt.limit;
6809 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6810 kvm_x86_ops->set_gdt(vcpu, &dt);
6811
ad312c7c 6812 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6813 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6814 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6815 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6816
2d3ad1f4 6817 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6818
f6801dff 6819 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6820 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6821 apic_base_msr.data = sregs->apic_base;
6822 apic_base_msr.host_initiated = true;
6823 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6824
4d4ec087 6825 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6826 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6827 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6828
fc78f519 6829 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6830 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6831 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6832 kvm_update_cpuid(vcpu);
63f42e02
XG		 6833
6834 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6835 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6836 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6837 mmu_reset_needed = 1;
6838 }
63f42e02 6839 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6840
6841 if (mmu_reset_needed)
6842 kvm_mmu_reset_context(vcpu);
6843
a50abc3b 6844 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6845 pending_vec = find_first_bit(
6846 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6847 if (pending_vec < max_bits) {
66fd3f7f 6848 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6849 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6850 }
6851
3e6e0aab
GT		 6852 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6853 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6854 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6855 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6856 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6857 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6858
3e6e0aab
GT		 6859 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6860 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6861
5f0269f5
ME		 6862 update_cr8_intercept(vcpu);
6863
9c3e4aab 6864 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6865 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6866 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6867 !is_protmode(vcpu))
9c3e4aab
MT		 6868 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6869
3842d135
AK		 6870 kvm_make_request(KVM_REQ_EVENT, vcpu);
6871
b6c7a5dc
HB		 6872 return 0;
6873}
6874
d0bfb940
JK		 6875int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6876 struct kvm_guest_debug *dbg)
b6c7a5dc 6877{
355be0b9 6878 unsigned long rflags;
ae675ef0 6879 int i, r;
b6c7a5dc 6880
4f926bf2
JK		 6881 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6882 r = -EBUSY;
6883 if (vcpu->arch.exception.pending)
2122ff5e 6884 goto out;
4f926bf2
JK		 6885 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6886 kvm_queue_exception(vcpu, DB_VECTOR);
6887 else
6888 kvm_queue_exception(vcpu, BP_VECTOR);
6889 }
6890
91586a3b
JK		 6891 /*
6892 * Read rflags as long as potentially injected trace flags are still
6893 * filtered out.
6894 */
6895 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6896
6897 vcpu->guest_debug = dbg->control;
6898 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6899 vcpu->guest_debug = 0;
6900
6901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6902 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6903 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6904 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6905 } else {
6906 for (i = 0; i < KVM_NR_DB_REGS; i++)
6907 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6908 }
c8639010 6909 kvm_update_dr7(vcpu);
ae675ef0 6910
f92653ee
JK		 6911 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6912 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6913 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6914
91586a3b
JK		 6915 /*
6916 * Trigger an rflags update that will inject or remove the trace
6917 * flags.
6918 */
6919 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6920
c8639010 6921 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6922
4f926bf2 6923 r = 0;
d0bfb940 6924
2122ff5e 6925out:
b6c7a5dc
HB		 6926
6927 return r;
6928}
6929
8b006791
ZX		 6930/*
6931 * Translate a guest virtual address to a guest physical address.
6932 */
6933int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6934 struct kvm_translation *tr)
6935{
6936 unsigned long vaddr = tr->linear_address;
6937 gpa_t gpa;
f656ce01 6938 int idx;
8b006791 6939
f656ce01 6940 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6941 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6942 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6943 tr->physical_address = gpa;
6944 tr->valid = gpa != UNMAPPED_GVA;
6945 tr->writeable = 1;
6946 tr->usermode = 0;
8b006791
ZX		 6947
6948 return 0;
6949}
6950
d0752060
HB		 6951int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6952{
98918833
SY		 6953 struct i387_fxsave_struct *fxsave =
6954 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6955
d0752060
HB		 6956 memcpy(fpu->fpr, fxsave->st_space, 128);
6957 fpu->fcw = fxsave->cwd;
6958 fpu->fsw = fxsave->swd;
6959 fpu->ftwx = fxsave->twd;
6960 fpu->last_opcode = fxsave->fop;
6961 fpu->last_ip = fxsave->rip;
6962 fpu->last_dp = fxsave->rdp;
6963 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6964
d0752060
HB		 6965 return 0;
6966}
6967
6968int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6969{
98918833
SY		 6970 struct i387_fxsave_struct *fxsave =
6971 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6972
d0752060
HB		 6973 memcpy(fxsave->st_space, fpu->fpr, 128);
6974 fxsave->cwd = fpu->fcw;
6975 fxsave->swd = fpu->fsw;
6976 fxsave->twd = fpu->ftwx;
6977 fxsave->fop = fpu->last_opcode;
6978 fxsave->rip = fpu->last_ip;
6979 fxsave->rdp = fpu->last_dp;
6980 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6981
d0752060
HB		 6982 return 0;
6983}
6984
10ab25cd 6985int fx_init(struct kvm_vcpu *vcpu)
d0752060 6986{
10ab25cd
JK		 6987 int err;
6988
6989 err = fpu_alloc(&vcpu->arch.guest_fpu);
6990 if (err)
6991 return err;
6992
98918833 6993 fpu_finit(&vcpu->arch.guest_fpu);
df1daba7
PB		 6994 if (cpu_has_xsaves)
6995 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
6996 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 6997
2acf923e
DC		 6998 /*
6999 * Ensure guest xcr0 is valid for loading
7000 */
7001 vcpu->arch.xcr0 = XSTATE_FP;
7002
ad312c7c 7003 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7004
7005 return 0;
d0752060
HB		 7006}
7007EXPORT_SYMBOL_GPL(fx_init);
7008
98918833
SY		 7009static void fx_free(struct kvm_vcpu *vcpu)
7010{
7011 fpu_free(&vcpu->arch.guest_fpu);
7012}
7013
d0752060
HB		 7014void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7015{
2608d7a1 7016 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7017 return;
7018
2acf923e
DC		 7019 /*
7020 * Restore all possible states in the guest,
7021 * and assume host would use all available bits.
7022 * Guest xcr0 would be loaded later.
7023 */
7024 kvm_put_guest_xcr0(vcpu);
d0752060 7025 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7026 __kernel_fpu_begin();
98918833 7027 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7028 trace_kvm_fpu(1);
d0752060 7029}
d0752060
HB		 7030
7031void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7032{
2acf923e
DC		 7033 kvm_put_guest_xcr0(vcpu);
7034
d0752060
HB		 7035 if (!vcpu->guest_fpu_loaded)
7036 return;
7037
7038 vcpu->guest_fpu_loaded = 0;
98918833 7039 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7040 __kernel_fpu_end();
f096ed85 7041 ++vcpu->stat.fpu_reload;
a8eeb04a 7042 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 7043 trace_kvm_fpu(0);
d0752060 7044}
e9b11c17
ZX		 7045
7046void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7047{
12f9a48f 7048 kvmclock_reset(vcpu);
7f1ea208 7049
f5f48ee1 7050 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7051 fx_free(vcpu);
e9b11c17
ZX		 7052 kvm_x86_ops->vcpu_free(vcpu);
7053}
7054
7055struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7056 unsigned int id)
7057{
6755bae8
ZA		 7058 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7059 printk_once(KERN_WARNING
7060 "kvm: SMP vm created on host with unstable TSC; "
7061 "guest TSC will not be reliable\n");
26e5215f
AK		 7062 return kvm_x86_ops->vcpu_create(kvm, id);
7063}
e9b11c17 7064
26e5215f
AK		 7065int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7066{
7067 int r;
e9b11c17 7068
0bed3b56 7069 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7070 r = vcpu_load(vcpu);
7071 if (r)
7072 return r;
57f252f2 7073 kvm_vcpu_reset(vcpu);
8a3c1a33 7074 kvm_mmu_setup(vcpu);
e9b11c17 7075 vcpu_put(vcpu);
e9b11c17 7076
26e5215f 7077 return r;
e9b11c17
ZX		 7078}
7079
31928aa5 7080void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7081{
8fe8ab46 7082 struct msr_data msr;
332967a3 7083 struct kvm *kvm = vcpu->kvm;
42897d86 7084
31928aa5
DD		 7085 if (vcpu_load(vcpu))
7086 return;
8fe8ab46
WA		 7087 msr.data = 0x0;
7088 msr.index = MSR_IA32_TSC;
7089 msr.host_initiated = true;
7090 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7091 vcpu_put(vcpu);
7092
332967a3
AJ		 7093 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7094 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7095}
7096
d40ccc62 7097void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7098{
9fc77441 7099 int r;
344d9588
GN		 7100 vcpu->arch.apf.msr_val = 0;
7101
9fc77441
MT		 7102 r = vcpu_load(vcpu);
7103 BUG_ON(r);
e9b11c17
ZX		 7104 kvm_mmu_unload(vcpu);
7105 vcpu_put(vcpu);
7106
98918833 7107 fx_free(vcpu);
e9b11c17
ZX		 7108 kvm_x86_ops->vcpu_free(vcpu);
7109}
7110
66450a21 7111void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 7112{
7460fb4a
AK		 7113 atomic_set(&vcpu->arch.nmi_queued, 0);
7114 vcpu->arch.nmi_pending = 0;
448fa4a9 7115 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7116 kvm_clear_interrupt_queue(vcpu);
7117 kvm_clear_exception_queue(vcpu);
448fa4a9 7118
42dbaa5a 7119 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7120 kvm_update_dr0123(vcpu);
6f43ed01 7121 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7122 kvm_update_dr6(vcpu);
42dbaa5a 7123 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7124 kvm_update_dr7(vcpu);
42dbaa5a 7125
1119022c
NA		 7126 vcpu->arch.cr2 = 0;
7127
3842d135 7128 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7129 vcpu->arch.apf.msr_val = 0;
c9aaa895 7130 vcpu->arch.st.msr_val = 0;
3842d135 7131
12f9a48f
GC		 7132 kvmclock_reset(vcpu);
7133
af585b92
GN		 7134 kvm_clear_async_pf_completion_queue(vcpu);
7135 kvm_async_pf_hash_reset(vcpu);
7136 vcpu->arch.apf.halted = false;
3842d135 7137
f5132b01
GN		 7138 kvm_pmu_reset(vcpu);
7139
66f7b72e
JS		 7140 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7141 vcpu->arch.regs_avail = ~0;
7142 vcpu->arch.regs_dirty = ~0;
7143
57f252f2 7144 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7145}
7146
2b4a273b 7147void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7148{
7149 struct kvm_segment cs;
7150
7151 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7152 cs.selector = vector << 8;
7153 cs.base = vector << 12;
7154 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7155 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7156}
7157
13a34e06 7158int kvm_arch_hardware_enable(void)
e9b11c17 7159{
ca84d1a2
ZA		 7160 struct kvm *kvm;
7161 struct kvm_vcpu *vcpu;
7162 int i;
0dd6a6ed
ZA		 7163 int ret;
7164 u64 local_tsc;
7165 u64 max_tsc = 0;
7166 bool stable, backwards_tsc = false;
18863bdd
AK		 7167
7168 kvm_shared_msr_cpu_online();
13a34e06 7169 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7170 if (ret != 0)
7171 return ret;
7172
7173 local_tsc = native_read_tsc();
7174 stable = !check_tsc_unstable();
7175 list_for_each_entry(kvm, &vm_list, vm_list) {
7176 kvm_for_each_vcpu(i, vcpu, kvm) {
7177 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7178 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7179 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7180 backwards_tsc = true;
7181 if (vcpu->arch.last_host_tsc > max_tsc)
7182 max_tsc = vcpu->arch.last_host_tsc;
7183 }
7184 }
7185 }
7186
7187 /*
7188 * Sometimes, even reliable TSCs go backwards. This happens on
7189 * platforms that reset TSC during suspend or hibernate actions, but
7190 * maintain synchronization. We must compensate. Fortunately, we can
7191 * detect that condition here, which happens early in CPU bringup,
7192 * before any KVM threads can be running. Unfortunately, we can't
7193 * bring the TSCs fully up to date with real time, as we aren't yet far
7194 * enough into CPU bringup that we know how much real time has actually
7195 * elapsed; our helper function, get_kernel_ns() will be using boot
7196 * variables that haven't been updated yet.
7197 *
7198 * So we simply find the maximum observed TSC above, then record the
7199 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7200 * the adjustment will be applied. Note that we accumulate
7201 * adjustments, in case multiple suspend cycles happen before some VCPU
7202 * gets a chance to run again. In the event that no KVM threads get a
7203 * chance to run, we will miss the entire elapsed period, as we'll have
7204 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7205 * loose cycle time. This isn't too big a deal, since the loss will be
7206 * uniform across all VCPUs (not to mention the scenario is extremely
7207 * unlikely). It is possible that a second hibernate recovery happens
7208 * much faster than a first, causing the observed TSC here to be
7209 * smaller; this would require additional padding adjustment, which is
7210 * why we set last_host_tsc to the local tsc observed here.
7211 *
7212 * N.B. - this code below runs only on platforms with reliable TSC,
7213 * as that is the only way backwards_tsc is set above. Also note
7214 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7215 * have the same delta_cyc adjustment applied if backwards_tsc
7216 * is detected. Note further, this adjustment is only done once,
7217 * as we reset last_host_tsc on all VCPUs to stop this from being
7218 * called multiple times (one for each physical CPU bringup).
7219 *
4a969980 7220 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7221 * will be compensated by the logic in vcpu_load, which sets the TSC to
7222 * catchup mode. This will catchup all VCPUs to real time, but cannot
7223 * guarantee that they stay in perfect synchronization.
7224 */
7225 if (backwards_tsc) {
7226 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7227 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7228 list_for_each_entry(kvm, &vm_list, vm_list) {
7229 kvm_for_each_vcpu(i, vcpu, kvm) {
7230 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7231 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7232 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7233 }
7234
7235 /*
7236 * We have to disable TSC offset matching.. if you were
7237 * booting a VM while issuing an S4 host suspend....
7238 * you may have some problem. Solving this issue is
7239 * left as an exercise to the reader.
7240 */
7241 kvm->arch.last_tsc_nsec = 0;
7242 kvm->arch.last_tsc_write = 0;
7243 }
7244
7245 }
7246 return 0;
e9b11c17
ZX		 7247}
7248
13a34e06 7249void kvm_arch_hardware_disable(void)
e9b11c17 7250{
13a34e06
RK		 7251 kvm_x86_ops->hardware_disable();
7252 drop_user_return_notifiers();
e9b11c17
ZX		 7253}
7254
7255int kvm_arch_hardware_setup(void)
7256{
7257 return kvm_x86_ops->hardware_setup();
7258}
7259
7260void kvm_arch_hardware_unsetup(void)
7261{
7262 kvm_x86_ops->hardware_unsetup();
7263}
7264
7265void kvm_arch_check_processor_compat(void *rtn)
7266{
7267 kvm_x86_ops->check_processor_compatibility(rtn);
7268}
7269
3e515705
AK		 7270bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7271{
7272 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7273}
7274
54e9818f
GN		 7275struct static_key kvm_no_apic_vcpu __read_mostly;
7276
e9b11c17
ZX		 7277int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7278{
7279 struct page *page;
7280 struct kvm *kvm;
7281 int r;
7282
7283 BUG_ON(vcpu->kvm == NULL);
7284 kvm = vcpu->kvm;
7285
6aef266c 7286 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7287 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7288 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7289 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7290 else
a4535290 7291 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7292
7293 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7294 if (!page) {
7295 r = -ENOMEM;
7296 goto fail;
7297 }
ad312c7c 7298 vcpu->arch.pio_data = page_address(page);
e9b11c17 7299
cc578287 7300 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7301
e9b11c17
ZX		 7302 r = kvm_mmu_create(vcpu);
7303 if (r < 0)
7304 goto fail_free_pio_data;
7305
7306 if (irqchip_in_kernel(kvm)) {
7307 r = kvm_create_lapic(vcpu);
7308 if (r < 0)
7309 goto fail_mmu_destroy;
54e9818f
GN		 7310 } else
7311 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7312
890ca9ae
HY		 7313 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7314 GFP_KERNEL);
7315 if (!vcpu->arch.mce_banks) {
7316 r = -ENOMEM;
443c39bc 7317 goto fail_free_lapic;
890ca9ae
HY		 7318 }
7319 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7320
f1797359
WY		 7321 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7322 r = -ENOMEM;
f5f48ee1 7323 goto fail_free_mce_banks;
f1797359 7324 }
f5f48ee1 7325
66f7b72e
JS		 7326 r = fx_init(vcpu);
7327 if (r)
7328 goto fail_free_wbinvd_dirty_mask;
7329
ba904635 7330 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7331 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7332
7333 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7334 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7335
5a4f55cd
EK		 7336 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7337
af585b92 7338 kvm_async_pf_hash_reset(vcpu);
f5132b01 7339 kvm_pmu_init(vcpu);
af585b92 7340
e9b11c17 7341 return 0;
66f7b72e
JS		 7342fail_free_wbinvd_dirty_mask:
7343 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7344fail_free_mce_banks:
7345 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7346fail_free_lapic:
7347 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7348fail_mmu_destroy:
7349 kvm_mmu_destroy(vcpu);
7350fail_free_pio_data:
ad312c7c 7351 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7352fail:
7353 return r;
7354}
7355
7356void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7357{
f656ce01
MT		 7358 int idx;
7359
f5132b01 7360 kvm_pmu_destroy(vcpu);
36cb93fd 7361 kfree(vcpu->arch.mce_banks);
e9b11c17 7362 kvm_free_lapic(vcpu);
f656ce01 7363 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7364 kvm_mmu_destroy(vcpu);
f656ce01 7365 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7366 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7367 if (!irqchip_in_kernel(vcpu->kvm))
7368 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7369}
d19a9cd2 7370
e790d9ef
RK		 7371void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7372{
ae97a3b8 7373 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7374}
7375
e08b9637 7376int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7377{
e08b9637
CO		 7378 if (type)
7379 return -EINVAL;
7380
6ef768fa 7381 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7382 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7383 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7384 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7385 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7386
5550af4d
SY		 7387 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7388 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7389 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7390 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7391 &kvm->arch.irq_sources_bitmap);
5550af4d 7392
038f8c11 7393 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7394 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7395 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7396
7397 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7398
7e44e449 7399 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7400 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7401
d89f5eff 7402 return 0;
d19a9cd2
ZX		 7403}
7404
7405static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7406{
9fc77441
MT		 7407 int r;
7408 r = vcpu_load(vcpu);
7409 BUG_ON(r);
d19a9cd2
ZX		 7410 kvm_mmu_unload(vcpu);
7411 vcpu_put(vcpu);
7412}
7413
7414static void kvm_free_vcpus(struct kvm *kvm)
7415{
7416 unsigned int i;
988a2cae 7417 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7418
7419 /*
7420 * Unpin any mmu pages first.
7421 */
af585b92
GN		 7422 kvm_for_each_vcpu(i, vcpu, kvm) {
7423 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7424 kvm_unload_vcpu_mmu(vcpu);
af585b92 7425 }
988a2cae
GN		 7426 kvm_for_each_vcpu(i, vcpu, kvm)
7427 kvm_arch_vcpu_free(vcpu);
7428
7429 mutex_lock(&kvm->lock);
7430 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7431 kvm->vcpus[i] = NULL;
d19a9cd2 7432
988a2cae
GN		 7433 atomic_set(&kvm->online_vcpus, 0);
7434 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7435}
7436
ad8ba2cd
SY		 7437void kvm_arch_sync_events(struct kvm *kvm)
7438{
332967a3 7439 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7440 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7441 kvm_free_all_assigned_devices(kvm);
aea924f6 7442 kvm_free_pit(kvm);
ad8ba2cd
SY		 7443}
7444
d19a9cd2
ZX		 7445void kvm_arch_destroy_vm(struct kvm *kvm)
7446{
27469d29
AH		 7447 if (current->mm == kvm->mm) {
7448 /*
7449 * Free memory regions allocated on behalf of userspace,
7450 * unless the the memory map has changed due to process exit
7451 * or fd copying.
7452 */
7453 struct kvm_userspace_memory_region mem;
7454 memset(&mem, 0, sizeof(mem));
7455 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7456 kvm_set_memory_region(kvm, &mem);
7457
7458 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7459 kvm_set_memory_region(kvm, &mem);
7460
7461 mem.slot = TSS_PRIVATE_MEMSLOT;
7462 kvm_set_memory_region(kvm, &mem);
7463 }
6eb55818 7464 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7465 kfree(kvm->arch.vpic);
7466 kfree(kvm->arch.vioapic);
d19a9cd2 7467 kvm_free_vcpus(kvm);
1e08ec4a 7468 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7469}
0de10343 7470
5587027c 7471void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7472 struct kvm_memory_slot *dont)
7473{
7474 int i;
7475
d89cc617
TY		 7476 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7477 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7478 kvfree(free->arch.rmap[i]);
d89cc617 7479 free->arch.rmap[i] = NULL;
77d11309 7480 }
d89cc617
TY		 7481 if (i == 0)
7482 continue;
7483
7484 if (!dont || free->arch.lpage_info[i - 1] !=
7485 dont->arch.lpage_info[i - 1]) {
548ef284 7486 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7487 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7488 }
7489 }
7490}
7491
5587027c
AK		 7492int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7493 unsigned long npages)
db3fe4eb
TY		 7494{
7495 int i;
7496
d89cc617 7497 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7498 unsigned long ugfn;
7499 int lpages;
d89cc617 7500 int level = i + 1;
db3fe4eb
TY		 7501
7502 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7503 slot->base_gfn, level) + 1;
7504
d89cc617
TY		 7505 slot->arch.rmap[i] =
7506 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7507 if (!slot->arch.rmap[i])
77d11309 7508 goto out_free;
d89cc617
TY		 7509 if (i == 0)
7510 continue;
77d11309 7511
d89cc617
TY		 7512 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7513 sizeof(*slot->arch.lpage_info[i - 1]));
7514 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7515 goto out_free;
7516
7517 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7518 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7519 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7520 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7521 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7522 /*
7523 * If the gfn and userspace address are not aligned wrt each
7524 * other, or if explicitly asked to, disable large page
7525 * support for this slot
7526 */
7527 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7528 !kvm_largepages_enabled()) {
7529 unsigned long j;
7530
7531 for (j = 0; j < lpages; ++j)
d89cc617 7532 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7533 }
7534 }
7535
7536 return 0;
7537
7538out_free:
d89cc617 7539 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7540 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7541 slot->arch.rmap[i] = NULL;
7542 if (i == 0)
7543 continue;
7544
548ef284 7545 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7546 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7547 }
7548 return -ENOMEM;
7549}
7550
e59dbe09
TY		 7551void kvm_arch_memslots_updated(struct kvm *kvm)
7552{
e6dff7d1
TY		 7553 /*
7554 * memslots->generation has been incremented.
7555 * mmio generation may have reached its maximum value.
7556 */
7557 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7558}
7559
f7784b8e
MT		 7560int kvm_arch_prepare_memory_region(struct kvm *kvm,
7561 struct kvm_memory_slot *memslot,
f7784b8e 7562 struct kvm_userspace_memory_region *mem,
7b6195a9 7563 enum kvm_mr_change change)
0de10343 7564{
7a905b14
TY		 7565 /*
7566 * Only private memory slots need to be mapped here since
7567 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7568 */
7b6195a9 7569 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7570 unsigned long userspace_addr;
604b38ac 7571
7a905b14
TY		 7572 /*
7573 * MAP_SHARED to prevent internal slot pages from being moved
7574 * by fork()/COW.
7575 */
7b6195a9 7576 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7577 PROT_READ | PROT_WRITE,
7578 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7579
7a905b14
TY		 7580 if (IS_ERR((void *)userspace_addr))
7581 return PTR_ERR((void *)userspace_addr);
604b38ac 7582
7a905b14 7583 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7584 }
7585
f7784b8e
MT		 7586 return 0;
7587}
7588
88178fd4
KH		 7589static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7590 struct kvm_memory_slot *new)
7591{
7592 /* Still write protect RO slot */
7593 if (new->flags & KVM_MEM_READONLY) {
7594 kvm_mmu_slot_remove_write_access(kvm, new);
7595 return;
7596 }
7597
7598 /*
7599 * Call kvm_x86_ops dirty logging hooks when they are valid.
7600 *
7601 * kvm_x86_ops->slot_disable_log_dirty is called when:
7602 *
7603 * - KVM_MR_CREATE with dirty logging is disabled
7604 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7605 *
7606 * The reason is, in case of PML, we need to set D-bit for any slots
7607 * with dirty logging disabled in order to eliminate unnecessary GPA
7608 * logging in PML buffer (and potential PML buffer full VMEXT). This
7609 * guarantees leaving PML enabled during guest's lifetime won't have
7610 * any additonal overhead from PML when guest is running with dirty
7611 * logging disabled for memory slots.
7612 *
7613 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7614 * to dirty logging mode.
7615 *
7616 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7617 *
7618 * In case of write protect:
7619 *
7620 * Write protect all pages for dirty logging.
7621 *
7622 * All the sptes including the large sptes which point to this
7623 * slot are set to readonly. We can not create any new large
7624 * spte on this slot until the end of the logging.
7625 *
7626 * See the comments in fast_page_fault().
7627 */
7628 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7629 if (kvm_x86_ops->slot_enable_log_dirty)
7630 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7631 else
7632 kvm_mmu_slot_remove_write_access(kvm, new);
7633 } else {
7634 if (kvm_x86_ops->slot_disable_log_dirty)
7635 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7636 }
7637}
7638
f7784b8e
MT		 7639void kvm_arch_commit_memory_region(struct kvm *kvm,
7640 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7641 const struct kvm_memory_slot *old,
7642 enum kvm_mr_change change)
f7784b8e 7643{
1c91cad4 7644 struct kvm_memory_slot *new;
8482644a 7645 int nr_mmu_pages = 0;
f7784b8e 7646
8482644a 7647 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7648 int ret;
7649
8482644a
TY		 7650 ret = vm_munmap(old->userspace_addr,
7651 old->npages * PAGE_SIZE);
f7784b8e
MT		 7652 if (ret < 0)
7653 printk(KERN_WARNING
7654 "kvm_vm_ioctl_set_memory_region: "
7655 "failed to munmap memory\n");
7656 }
7657
48c0e4e9
XG		 7658 if (!kvm->arch.n_requested_mmu_pages)
7659 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7660
48c0e4e9 7661 if (nr_mmu_pages)
0de10343 7662 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4
KH		 7663
7664 /* It's OK to get 'new' slot here as it has already been installed */
7665 new = id_to_memslot(kvm->memslots, mem->slot);
7666
c972f3b1 7667 /*
88178fd4 7668 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7669 *
88178fd4
KH		 7670 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7671 * been zapped so no dirty logging staff is needed for old slot. For
7672 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7673 * new and it's also covered when dealing with the new slot.
c972f3b1 7674 */
88178fd4
KH		 7675 if (change != KVM_MR_DELETE)
7676 kvm_mmu_slot_apply_flags(kvm, new);
0de10343 7677}
1d737c8a 7678
2df72e9b 7679void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7680{
6ca18b69 7681 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7682}
7683
2df72e9b
MT		 7684void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7685 struct kvm_memory_slot *slot)
7686{
6ca18b69 7687 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7688}
7689
1d737c8a
ZX		 7690int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7691{
b6b8a145
JK		 7692 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7693 kvm_x86_ops->check_nested_events(vcpu, false);
7694
af585b92
GN		 7695 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7696 !vcpu->arch.apf.halted)
7697 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7698 || kvm_apic_has_events(vcpu)
6aef266c 7699 || vcpu->arch.pv.pv_unhalted
7460fb4a 7700 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7701 (kvm_arch_interrupt_allowed(vcpu) &&
7702 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7703}
5736199a 7704
b6d33834 7705int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7706{
b6d33834 7707 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7708}
78646121
GN		 7709
7710int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7711{
7712 return kvm_x86_ops->interrupt_allowed(vcpu);
7713}
229456fc 7714
82b32774 7715unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7716{
82b32774
NA		 7717 if (is_64_bit_mode(vcpu))
7718 return kvm_rip_read(vcpu);
7719 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7720 kvm_rip_read(vcpu));
7721}
7722EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7723
82b32774
NA		 7724bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7725{
7726 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7727}
7728EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7729
94fe45da
JK		 7730unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7731{
7732 unsigned long rflags;
7733
7734 rflags = kvm_x86_ops->get_rflags(vcpu);
7735 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7736 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7737 return rflags;
7738}
7739EXPORT_SYMBOL_GPL(kvm_get_rflags);
7740
6addfc42 7741static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7742{
7743 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7744 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7745 rflags |= X86_EFLAGS_TF;
94fe45da 7746 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7747}
7748
7749void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7750{
7751 __kvm_set_rflags(vcpu, rflags);
3842d135 7752 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7753}
7754EXPORT_SYMBOL_GPL(kvm_set_rflags);
7755
56028d08
GN		 7756void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7757{
7758 int r;
7759
fb67e14f 7760 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7761 work->wakeup_all)
56028d08
GN		 7762 return;
7763
7764 r = kvm_mmu_reload(vcpu);
7765 if (unlikely(r))
7766 return;
7767
fb67e14f
XG		 7768 if (!vcpu->arch.mmu.direct_map &&
7769 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7770 return;
7771
56028d08
GN		 7772 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7773}
7774
af585b92
GN		 7775static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7776{
7777 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7778}
7779
7780static inline u32 kvm_async_pf_next_probe(u32 key)
7781{
7782 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7783}
7784
7785static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7786{
7787 u32 key = kvm_async_pf_hash_fn(gfn);
7788
7789 while (vcpu->arch.apf.gfns[key] != ~0)
7790 key = kvm_async_pf_next_probe(key);
7791
7792 vcpu->arch.apf.gfns[key] = gfn;
7793}
7794
7795static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7796{
7797 int i;
7798 u32 key = kvm_async_pf_hash_fn(gfn);
7799
7800 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7801 (vcpu->arch.apf.gfns[key] != gfn &&
7802 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7803 key = kvm_async_pf_next_probe(key);
7804
7805 return key;
7806}
7807
7808bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7809{
7810 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7811}
7812
7813static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7814{
7815 u32 i, j, k;
7816
7817 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7818 while (true) {
7819 vcpu->arch.apf.gfns[i] = ~0;
7820 do {
7821 j = kvm_async_pf_next_probe(j);
7822 if (vcpu->arch.apf.gfns[j] == ~0)
7823 return;
7824 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7825 /*
7826 * k lies cyclically in ]i,j]
7827 * | i.k.j |
7828 * |....j i.k.| or |.k..j i...|
7829 */
7830 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7831 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7832 i = j;
7833 }
7834}
7835
7c90705b
GN		 7836static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7837{
7838
7839 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7840 sizeof(val));
7841}
7842
af585b92
GN		 7843void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7844 struct kvm_async_pf *work)
7845{
6389ee94
AK		 7846 struct x86_exception fault;
7847
7c90705b 7848 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7849 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7850
7851 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7852 (vcpu->arch.apf.send_user_only &&
7853 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7854 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7855 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7856 fault.vector = PF_VECTOR;
7857 fault.error_code_valid = true;
7858 fault.error_code = 0;
7859 fault.nested_page_fault = false;
7860 fault.address = work->arch.token;
7861 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7862 }
af585b92
GN		 7863}
7864
7865void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7866 struct kvm_async_pf *work)
7867{
6389ee94
AK		 7868 struct x86_exception fault;
7869
7c90705b 7870 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7871 if (work->wakeup_all)
7c90705b
GN		 7872 work->arch.token = ~0; /* broadcast wakeup */
7873 else
7874 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7875
7876 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7877 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7878 fault.vector = PF_VECTOR;
7879 fault.error_code_valid = true;
7880 fault.error_code = 0;
7881 fault.nested_page_fault = false;
7882 fault.address = work->arch.token;
7883 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7884 }
e6d53e3b 7885 vcpu->arch.apf.halted = false;
a4fa1635 7886 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7887}
7888
7889bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7890{
7891 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7892 return true;
7893 else
7894 return !kvm_event_needs_reinjection(vcpu) &&
7895 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7896}
7897
e0f0bbc5
AW		 7898void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7899{
7900 atomic_inc(&kvm->arch.noncoherent_dma_count);
7901}
7902EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7903
7904void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7905{
7906 atomic_dec(&kvm->arch.noncoherent_dma_count);
7907}
7908EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7909
7910bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7911{
7912 return atomic_read(&kvm->arch.noncoherent_dma_count);
7913}
7914EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7915
229456fc
MT		 7916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7925EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7926EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7927EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7928EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7929EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 7930EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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