projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: Wrong operand size for far ret
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
92a1f12d
JR		 102bool kvm_has_tsc_control;
103EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104u32 kvm_max_guest_tsc_khz;
105EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
cc578287
ZA		 107/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108static u32 tsc_tolerance_ppm = 250;
109module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
d0659d94
MT		 111/* lapic timer advance (tscdeadline mode only) in nanoseconds */
112unsigned int lapic_timer_advance_ns = 0;
113module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
16a96021
MT		 115static bool backwards_tsc_observed = false;
116
18863bdd
AK		 117#define KVM_NR_SHARED_MSRS 16
118
119struct kvm_shared_msrs_global {
120 int nr;
2bf78fa7 121 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 122};
123
124struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
2bf78fa7
SY		 127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 131};
132
133static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 134static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 135
417bc304 136struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 147 { "halt_exits", VCPU_STAT(halt_exits) },
148 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 149 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 150 { "request_irq", VCPU_STAT(request_irq_exits) },
151 { "irq_exits", VCPU_STAT(irq_exits) },
152 { "host_state_reload", VCPU_STAT(host_state_reload) },
153 { "efer_reload", VCPU_STAT(efer_reload) },
154 { "fpu_reload", VCPU_STAT(fpu_reload) },
155 { "insn_emulation", VCPU_STAT(insn_emulation) },
156 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 157 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 158 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 159 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
160 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
161 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
162 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
163 { "mmu_flooded", VM_STAT(mmu_flooded) },
164 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 165 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 166 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 167 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 168 { "largepages", VM_STAT(lpages) },
417bc304
HB		 169 { NULL }
170};
171
2acf923e
DC		 172u64 __read_mostly host_xcr0;
173
b6785def 174static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 175
af585b92
GN		 176static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
177{
178 int i;
179 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
180 vcpu->arch.apf.gfns[i] = ~0;
181}
182
18863bdd
AK		 183static void kvm_on_user_return(struct user_return_notifier *urn)
184{
185 unsigned slot;
18863bdd
AK		 186 struct kvm_shared_msrs *locals
187 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 188 struct kvm_shared_msr_values *values;
18863bdd
AK		 189
190 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 191 values = &locals->values[slot];
192 if (values->host != values->curr) {
193 wrmsrl(shared_msrs_global.msrs[slot], values->host);
194 values->curr = values->host;
18863bdd
AK		 195 }
196 }
197 locals->registered = false;
198 user_return_notifier_unregister(urn);
199}
200
2bf78fa7 201static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 202{
18863bdd 203 u64 value;
013f6a5d
MT		 204 unsigned int cpu = smp_processor_id();
205 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 206
2bf78fa7
SY		 207 /* only read, and nobody should modify it at this time,
208 * so don't need lock */
209 if (slot >= shared_msrs_global.nr) {
210 printk(KERN_ERR "kvm: invalid MSR slot!");
211 return;
212 }
213 rdmsrl_safe(msr, &value);
214 smsr->values[slot].host = value;
215 smsr->values[slot].curr = value;
216}
217
218void kvm_define_shared_msr(unsigned slot, u32 msr)
219{
0123be42 220 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 221 if (slot >= shared_msrs_global.nr)
222 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 223 shared_msrs_global.msrs[slot] = msr;
224 /* we need ensured the shared_msr_global have been updated */
225 smp_wmb();
18863bdd
AK		 226}
227EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
228
229static void kvm_shared_msr_cpu_online(void)
230{
231 unsigned i;
18863bdd
AK		 232
233 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 234 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 235}
236
8b3c3104 237int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 238{
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 241 int err;
18863bdd 242
2bf78fa7 243 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 244 return 0;
2bf78fa7 245 smsr->values[slot].curr = value;
8b3c3104
AH		 246 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
247 if (err)
248 return 1;
249
18863bdd
AK		 250 if (!smsr->registered) {
251 smsr->urn.on_user_return = kvm_on_user_return;
252 user_return_notifier_register(&smsr->urn);
253 smsr->registered = true;
254 }
8b3c3104 255 return 0;
18863bdd
AK		 256}
257EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
258
13a34e06 259static void drop_user_return_notifiers(void)
3548bab5 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 263
264 if (smsr->registered)
265 kvm_on_user_return(&smsr->urn);
266}
267
6866b83e
CO		 268u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
269{
8a5a87d9 270 return vcpu->arch.apic_base;
6866b83e
CO		 271}
272EXPORT_SYMBOL_GPL(kvm_get_apic_base);
273
58cb628d
JK		 274int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
275{
276 u64 old_state = vcpu->arch.apic_base &
277 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
278 u64 new_state = msr_info->data &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
281 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
282
283 if (!msr_info->host_initiated &&
284 ((msr_info->data & reserved_bits) != 0 ||
285 new_state == X2APIC_ENABLE ||
286 (new_state == MSR_IA32_APICBASE_ENABLE &&
287 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
288 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
289 old_state == 0)))
290 return 1;
291
292 kvm_lapic_set_base(vcpu, msr_info->data);
293 return 0;
6866b83e
CO		 294}
295EXPORT_SYMBOL_GPL(kvm_set_apic_base);
296
2605fc21 297asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 298{
299 /* Fault while not rebooting. We want the trace. */
300 BUG();
301}
302EXPORT_SYMBOL_GPL(kvm_spurious_fault);
303
3fd28fce
ED		 304#define EXCPT_BENIGN 0
305#define EXCPT_CONTRIBUTORY 1
306#define EXCPT_PF 2
307
308static int exception_class(int vector)
309{
310 switch (vector) {
311 case PF_VECTOR:
312 return EXCPT_PF;
313 case DE_VECTOR:
314 case TS_VECTOR:
315 case NP_VECTOR:
316 case SS_VECTOR:
317 case GP_VECTOR:
318 return EXCPT_CONTRIBUTORY;
319 default:
320 break;
321 }
322 return EXCPT_BENIGN;
323}
324
d6e8c854
NA		 325#define EXCPT_FAULT 0
326#define EXCPT_TRAP 1
327#define EXCPT_ABORT 2
328#define EXCPT_INTERRUPT 3
329
330static int exception_type(int vector)
331{
332 unsigned int mask;
333
334 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
335 return EXCPT_INTERRUPT;
336
337 mask = 1 << vector;
338
339 /* #DB is trap, as instruction watchpoints are handled elsewhere */
340 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
341 return EXCPT_TRAP;
342
343 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
344 return EXCPT_ABORT;
345
346 /* Reserved exceptions will result in fault */
347 return EXCPT_FAULT;
348}
349
3fd28fce 350static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 351 unsigned nr, bool has_error, u32 error_code,
352 bool reinject)
3fd28fce
ED		 353{
354 u32 prev_nr;
355 int class1, class2;
356
3842d135
AK		 357 kvm_make_request(KVM_REQ_EVENT, vcpu);
358
3fd28fce
ED		 359 if (!vcpu->arch.exception.pending) {
360 queue:
3ffb2468
NA		 361 if (has_error && !is_protmode(vcpu))
362 has_error = false;
3fd28fce
ED		 363 vcpu->arch.exception.pending = true;
364 vcpu->arch.exception.has_error_code = has_error;
365 vcpu->arch.exception.nr = nr;
366 vcpu->arch.exception.error_code = error_code;
3f0fd292 367 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 368 return;
369 }
370
371 /* to check exception */
372 prev_nr = vcpu->arch.exception.nr;
373 if (prev_nr == DF_VECTOR) {
374 /* triple fault -> shutdown */
a8eeb04a 375 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 376 return;
377 }
378 class1 = exception_class(prev_nr);
379 class2 = exception_class(nr);
380 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
381 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
382 /* generate double fault per SDM Table 5-5 */
383 vcpu->arch.exception.pending = true;
384 vcpu->arch.exception.has_error_code = true;
385 vcpu->arch.exception.nr = DF_VECTOR;
386 vcpu->arch.exception.error_code = 0;
387 } else
388 /* replace previous exception with a new one in a hope
389 that instruction re-execution will regenerate lost
390 exception */
391 goto queue;
392}
393
298101da
AK		 394void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
395{
ce7ddec4 396 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 397}
398EXPORT_SYMBOL_GPL(kvm_queue_exception);
399
ce7ddec4
JR		 400void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
401{
402 kvm_multiple_exception(vcpu, nr, false, 0, true);
403}
404EXPORT_SYMBOL_GPL(kvm_requeue_exception);
405
db8fcefa 406void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 407{
db8fcefa
AP		 408 if (err)
409 kvm_inject_gp(vcpu, 0);
410 else
411 kvm_x86_ops->skip_emulated_instruction(vcpu);
412}
413EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 414
6389ee94 415void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 416{
417 ++vcpu->stat.pf_guest;
6389ee94
AK		 418 vcpu->arch.cr2 = fault->address;
419 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 420}
27d6c865 421EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 422
ef54bcfe 423static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 424{
6389ee94
AK		 425 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
426 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 427 else
6389ee94 428 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 429
430 return fault->nested_page_fault;
d4f8cf66
JR		 431}
432
3419ffc8
SY		 433void kvm_inject_nmi(struct kvm_vcpu *vcpu)
434{
7460fb4a
AK		 435 atomic_inc(&vcpu->arch.nmi_queued);
436 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 437}
438EXPORT_SYMBOL_GPL(kvm_inject_nmi);
439
298101da
AK		 440void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
441{
ce7ddec4 442 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 443}
444EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
445
ce7ddec4
JR		 446void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
447{
448 kvm_multiple_exception(vcpu, nr, true, error_code, true);
449}
450EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
451
0a79b009
AK		 452/*
453 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
454 * a #GP and return false.
455 */
456bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 457{
0a79b009
AK		 458 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
459 return true;
460 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
461 return false;
298101da 462}
0a79b009 463EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 464
16f8a6f9
NA		 465bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
466{
467 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
468 return true;
469
470 kvm_queue_exception(vcpu, UD_VECTOR);
471 return false;
472}
473EXPORT_SYMBOL_GPL(kvm_require_dr);
474
ec92fe44
JR		 475/*
476 * This function will be used to read from the physical memory of the currently
477 * running guest. The difference to kvm_read_guest_page is that this function
478 * can read from guest physical or from the guest's guest physical memory.
479 */
480int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
481 gfn_t ngfn, void *data, int offset, int len,
482 u32 access)
483{
54987b7a 484 struct x86_exception exception;
ec92fe44
JR		 485 gfn_t real_gfn;
486 gpa_t ngpa;
487
488 ngpa = gfn_to_gpa(ngfn);
54987b7a 489 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 490 if (real_gfn == UNMAPPED_GVA)
491 return -EFAULT;
492
493 real_gfn = gpa_to_gfn(real_gfn);
494
495 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
496}
497EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
498
69b0049a 499static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 500 void *data, int offset, int len, u32 access)
501{
502 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
503 data, offset, len, access);
504}
505
a03490ed
CO		 506/*
507 * Load the pae pdptrs. Return true is they are all valid.
508 */
ff03a073 509int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 510{
511 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
512 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
513 int i;
514 int ret;
ff03a073 515 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 516
ff03a073
JR		 517 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
518 offset * sizeof(u64), sizeof(pdpte),
519 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 520 if (ret < 0) {
521 ret = 0;
522 goto out;
523 }
524 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 525 if (is_present_gpte(pdpte[i]) &&
20c466b5 526 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 527 ret = 0;
528 goto out;
529 }
530 }
531 ret = 1;
532
ff03a073 533 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 534 __set_bit(VCPU_EXREG_PDPTR,
535 (unsigned long *)&vcpu->arch.regs_avail);
536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 538out:
a03490ed
CO		 539
540 return ret;
541}
cc4b6871 542EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 543
d835dfec
AK		 544static bool pdptrs_changed(struct kvm_vcpu *vcpu)
545{
ff03a073 546 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 547 bool changed = true;
3d06b8bf
JR		 548 int offset;
549 gfn_t gfn;
d835dfec
AK		 550 int r;
551
552 if (is_long_mode(vcpu) || !is_pae(vcpu))
553 return false;
554
6de4f3ad
AK		 555 if (!test_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_avail))
557 return true;
558
9f8fe504
AK		 559 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
560 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 561 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
562 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 563 if (r < 0)
564 goto out;
ff03a073 565 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 566out:
d835dfec
AK		 567
568 return changed;
569}
570
49a9b07e 571int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 572{
aad82703
SY		 573 unsigned long old_cr0 = kvm_read_cr0(vcpu);
574 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
575 X86_CR0_CD | X86_CR0_NW;
576
f9a48e6a
AK		 577 cr0 |= X86_CR0_ET;
578
ab344828 579#ifdef CONFIG_X86_64
0f12244f
GN		 580 if (cr0 & 0xffffffff00000000UL)
581 return 1;
ab344828
GN		 582#endif
583
584 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 585
0f12244f
GN		 586 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
587 return 1;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
590 return 1;
a03490ed
CO		 591
592 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
593#ifdef CONFIG_X86_64
f6801dff 594 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 595 int cs_db, cs_l;
596
0f12244f
GN		 597 if (!is_pae(vcpu))
598 return 1;
a03490ed 599 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 600 if (cs_l)
601 return 1;
a03490ed
CO		 602 } else
603#endif
ff03a073 604 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 605 kvm_read_cr3(vcpu)))
0f12244f 606 return 1;
a03490ed
CO		 607 }
608
ad756a16
MJ		 609 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
610 return 1;
611
a03490ed 612 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 613
d170c419 614 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 615 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 616 kvm_async_pf_hash_reset(vcpu);
617 }
e5f3f027 618
aad82703
SY		 619 if ((cr0 ^ old_cr0) & update_bits)
620 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 621 return 0;
622}
2d3ad1f4 623EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 624
2d3ad1f4 625void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 626{
49a9b07e 627 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 630
42bdf991
MT		 631static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
632{
633 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
634 !vcpu->guest_xcr0_loaded) {
635 /* kvm_set_xcr() also depends on this */
636 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
637 vcpu->guest_xcr0_loaded = 1;
638 }
639}
640
641static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
642{
643 if (vcpu->guest_xcr0_loaded) {
644 if (vcpu->arch.xcr0 != host_xcr0)
645 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
646 vcpu->guest_xcr0_loaded = 0;
647 }
648}
649
69b0049a 650static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 651{
56c103ec
LJ		 652 u64 xcr0 = xcr;
653 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 654 u64 valid_bits;
2acf923e
DC		 655
656 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
657 if (index != XCR_XFEATURE_ENABLED_MASK)
658 return 1;
2acf923e
DC		 659 if (!(xcr0 & XSTATE_FP))
660 return 1;
661 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
662 return 1;
46c34cb0
PB		 663
664 /*
665 * Do not allow the guest to set bits that we do not support
666 * saving. However, xcr0 bit 0 is always set, even if the
667 * emulated CPU does not support XSAVE (see fx_init).
668 */
669 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
670 if (xcr0 & ~valid_bits)
2acf923e 671 return 1;
46c34cb0 672
390bd528
LJ		 673 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
674 return 1;
675
612263b3
CP		 676 if (xcr0 & XSTATE_AVX512) {
677 if (!(xcr0 & XSTATE_YMM))
678 return 1;
679 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
680 return 1;
681 }
42bdf991 682 kvm_put_guest_xcr0(vcpu);
2acf923e 683 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 684
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
2acf923e
DC		 687 return 0;
688}
689
690int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
691{
764bcbc5
Z		 692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 694 kvm_inject_gp(vcpu, 0);
695 return 1;
696 }
697 return 0;
698}
699EXPORT_SYMBOL_GPL(kvm_set_xcr);
700
a83b29c6 701int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 702{
fc78f519 703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
705 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 706 if (cr4 & CR4_RESERVED_BITS)
707 return 1;
a03490ed 708
2acf923e
DC		 709 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
710 return 1;
711
c68b734f
YW		 712 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
713 return 1;
714
97ec8c06
FW		 715 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
716 return 1;
717
afcbf13f 718 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 719 return 1;
720
a03490ed 721 if (is_long_mode(vcpu)) {
0f12244f
GN		 722 if (!(cr4 & X86_CR4_PAE))
723 return 1;
a2edf57f
AK		 724 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
725 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 726 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
727 kvm_read_cr3(vcpu)))
0f12244f
GN		 728 return 1;
729
ad756a16
MJ		 730 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
731 if (!guest_cpuid_has_pcid(vcpu))
732 return 1;
733
734 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
735 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
736 return 1;
737 }
738
5e1746d6 739 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 740 return 1;
a03490ed 741
ad756a16
MJ		 742 if (((cr4 ^ old_cr4) & pdptr_bits) ||
743 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 744 kvm_mmu_reset_context(vcpu);
0f12244f 745
97ec8c06
FW		 746 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
747 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
748
2acf923e 749 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 750 kvm_update_cpuid(vcpu);
2acf923e 751
0f12244f
GN		 752 return 0;
753}
2d3ad1f4 754EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 755
2390218b 756int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 757{
ac146235 758#ifdef CONFIG_X86_64
9d88fca7 759 cr3 &= ~CR3_PCID_INVD;
ac146235 760#endif
9d88fca7 761
9f8fe504 762 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 763 kvm_mmu_sync_roots(vcpu);
77c3913b 764 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 765 return 0;
d835dfec
AK		 766 }
767
a03490ed 768 if (is_long_mode(vcpu)) {
d9f89b88
JK		 769 if (cr3 & CR3_L_MODE_RESERVED_BITS)
770 return 1;
771 } else if (is_pae(vcpu) && is_paging(vcpu) &&
772 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 773 return 1;
a03490ed 774
0f12244f 775 vcpu->arch.cr3 = cr3;
aff48baa 776 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 777 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 778 return 0;
779}
2d3ad1f4 780EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 781
eea1cff9 782int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 783{
0f12244f
GN		 784 if (cr8 & CR8_RESERVED_BITS)
785 return 1;
a03490ed
CO		 786 if (irqchip_in_kernel(vcpu->kvm))
787 kvm_lapic_set_tpr(vcpu, cr8);
788 else
ad312c7c 789 vcpu->arch.cr8 = cr8;
0f12244f
GN		 790 return 0;
791}
2d3ad1f4 792EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 793
2d3ad1f4 794unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 795{
796 if (irqchip_in_kernel(vcpu->kvm))
797 return kvm_lapic_get_cr8(vcpu);
798 else
ad312c7c 799 return vcpu->arch.cr8;
a03490ed 800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 802
73aaf249
JK		 803static void kvm_update_dr6(struct kvm_vcpu *vcpu)
804{
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
807}
808
c8639010
JK		 809static void kvm_update_dr7(struct kvm_vcpu *vcpu)
810{
811 unsigned long dr7;
812
813 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
814 dr7 = vcpu->arch.guest_debug_dr7;
815 else
816 dr7 = vcpu->arch.dr7;
817 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 818 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
819 if (dr7 & DR7_BP_EN_MASK)
820 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 821}
822
6f43ed01
NA		 823static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
824{
825 u64 fixed = DR6_FIXED_1;
826
827 if (!guest_cpuid_has_rtm(vcpu))
828 fixed |= DR6_RTM;
829 return fixed;
830}
831
338dbc97 832static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 833{
834 switch (dr) {
835 case 0 ... 3:
836 vcpu->arch.db[dr] = val;
837 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
838 vcpu->arch.eff_db[dr] = val;
839 break;
840 case 4:
020df079
GN		 841 /* fall through */
842 case 6:
338dbc97
GN		 843 if (val & 0xffffffff00000000ULL)
844 return -1; /* #GP */
6f43ed01 845 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 846 kvm_update_dr6(vcpu);
020df079
GN		 847 break;
848 case 5:
020df079
GN		 849 /* fall through */
850 default: /* 7 */
338dbc97
GN		 851 if (val & 0xffffffff00000000ULL)
852 return -1; /* #GP */
020df079 853 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 854 kvm_update_dr7(vcpu);
020df079
GN		 855 break;
856 }
857
858 return 0;
859}
338dbc97
GN		 860
861int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
862{
16f8a6f9 863 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 864 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 865 return 1;
866 }
867 return 0;
338dbc97 868}
020df079
GN		 869EXPORT_SYMBOL_GPL(kvm_set_dr);
870
16f8a6f9 871int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 872{
873 switch (dr) {
874 case 0 ... 3:
875 *val = vcpu->arch.db[dr];
876 break;
877 case 4:
020df079
GN		 878 /* fall through */
879 case 6:
73aaf249
JK		 880 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
881 *val = vcpu->arch.dr6;
882 else
883 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 884 break;
885 case 5:
020df079
GN		 886 /* fall through */
887 default: /* 7 */
888 *val = vcpu->arch.dr7;
889 break;
890 }
338dbc97
GN		 891 return 0;
892}
020df079
GN		 893EXPORT_SYMBOL_GPL(kvm_get_dr);
894
022cd0e8
AK		 895bool kvm_rdpmc(struct kvm_vcpu *vcpu)
896{
897 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
898 u64 data;
899 int err;
900
901 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
902 if (err)
903 return err;
904 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
905 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
906 return err;
907}
908EXPORT_SYMBOL_GPL(kvm_rdpmc);
909
043405e1
CO		 910/*
911 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
912 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
913 *
914 * This list is modified at module load time to reflect the
e3267cbb
GC		 915 * capabilities of the host cpu. This capabilities test skips MSRs that are
916 * kvm-specific. Those are put in the beginning of the list.
043405e1 917 */
e3267cbb 918
e984097b 919#define KVM_SAVE_MSRS_BEGIN 12
043405e1 920static u32 msrs_to_save[] = {
e3267cbb 921 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 922 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 923 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 924 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 925 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 926 MSR_KVM_PV_EOI_EN,
043405e1 927 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 928 MSR_STAR,
043405e1
CO		 929#ifdef CONFIG_X86_64
930 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
931#endif
b3897a49 932 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 933 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 934};
935
936static unsigned num_msrs_to_save;
937
f1d24831 938static const u32 emulated_msrs[] = {
ba904635 939 MSR_IA32_TSC_ADJUST,
a3e06bbe 940 MSR_IA32_TSCDEADLINE,
043405e1 941 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 942 MSR_IA32_MCG_STATUS,
943 MSR_IA32_MCG_CTL,
043405e1
CO		 944};
945
384bb783 946bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 947{
b69e8cae 948 if (efer & efer_reserved_bits)
384bb783 949 return false;
15c4a640 950
1b2fd70c
AG		 951 if (efer & EFER_FFXSR) {
952 struct kvm_cpuid_entry2 *feat;
953
954 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 955 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 956 return false;
1b2fd70c
AG		 957 }
958
d8017474
AG		 959 if (efer & EFER_SVME) {
960 struct kvm_cpuid_entry2 *feat;
961
962 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 963 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 964 return false;
d8017474
AG		 965 }
966
384bb783
JK		 967 return true;
968}
969EXPORT_SYMBOL_GPL(kvm_valid_efer);
970
971static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
972{
973 u64 old_efer = vcpu->arch.efer;
974
975 if (!kvm_valid_efer(vcpu, efer))
976 return 1;
977
978 if (is_paging(vcpu)
979 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
980 return 1;
981
15c4a640 982 efer &= ~EFER_LMA;
f6801dff 983 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 984
a3d204e2
SY		 985 kvm_x86_ops->set_efer(vcpu, efer);
986
aad82703
SY		 987 /* Update reserved bits */
988 if ((efer ^ old_efer) & EFER_NX)
989 kvm_mmu_reset_context(vcpu);
990
b69e8cae 991 return 0;
15c4a640
CO		 992}
993
f2b4b7dd
JR		 994void kvm_enable_efer_bits(u64 mask)
995{
996 efer_reserved_bits &= ~mask;
997}
998EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
999
15c4a640
CO		 1000/*
1001 * Writes msr value into into the appropriate "register".
1002 * Returns 0 on success, non-0 otherwise.
1003 * Assumes vcpu_load() was already called.
1004 */
8fe8ab46 1005int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1006{
854e8bb1
NA		 1007 switch (msr->index) {
1008 case MSR_FS_BASE:
1009 case MSR_GS_BASE:
1010 case MSR_KERNEL_GS_BASE:
1011 case MSR_CSTAR:
1012 case MSR_LSTAR:
1013 if (is_noncanonical_address(msr->data))
1014 return 1;
1015 break;
1016 case MSR_IA32_SYSENTER_EIP:
1017 case MSR_IA32_SYSENTER_ESP:
1018 /*
1019 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1020 * non-canonical address is written on Intel but not on
1021 * AMD (which ignores the top 32-bits, because it does
1022 * not implement 64-bit SYSENTER).
1023 *
1024 * 64-bit code should hence be able to write a non-canonical
1025 * value on AMD. Making the address canonical ensures that
1026 * vmentry does not fail on Intel after writing a non-canonical
1027 * value, and that something deterministic happens if the guest
1028 * invokes 64-bit SYSENTER.
1029 */
1030 msr->data = get_canonical(msr->data);
1031 }
8fe8ab46 1032 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1033}
854e8bb1 1034EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1035
313a3dc7
CO		 1036/*
1037 * Adapt set_msr() to msr_io()'s calling convention
1038 */
1039static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1040{
8fe8ab46
WA		 1041 struct msr_data msr;
1042
1043 msr.data = *data;
1044 msr.index = index;
1045 msr.host_initiated = true;
1046 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1047}
1048
16e8d74d
MT		 1049#ifdef CONFIG_X86_64
1050struct pvclock_gtod_data {
1051 seqcount_t seq;
1052
1053 struct { /* extract of a clocksource struct */
1054 int vclock_mode;
1055 cycle_t cycle_last;
1056 cycle_t mask;
1057 u32 mult;
1058 u32 shift;
1059 } clock;
1060
cbcf2dd3
TG		 1061 u64 boot_ns;
1062 u64 nsec_base;
16e8d74d
MT		 1063};
1064
1065static struct pvclock_gtod_data pvclock_gtod_data;
1066
1067static void update_pvclock_gtod(struct timekeeper *tk)
1068{
1069 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1070 u64 boot_ns;
1071
d28ede83 1072 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1073
1074 write_seqcount_begin(&vdata->seq);
1075
1076 /* copy pvclock gtod data */
d28ede83
TG		 1077 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1078 vdata->clock.cycle_last = tk->tkr.cycle_last;
1079 vdata->clock.mask = tk->tkr.mask;
1080 vdata->clock.mult = tk->tkr.mult;
1081 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1082
cbcf2dd3 1083 vdata->boot_ns = boot_ns;
d28ede83 1084 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1085
1086 write_seqcount_end(&vdata->seq);
1087}
1088#endif
1089
bab5bb39
NK		 1090void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1091{
1092 /*
1093 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1094 * vcpu_enter_guest. This function is only called from
1095 * the physical CPU that is running vcpu.
1096 */
1097 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1098}
16e8d74d 1099
18068523
GOC		 1100static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1101{
9ed3c444
AK		 1102 int version;
1103 int r;
50d0a0f9 1104 struct pvclock_wall_clock wc;
923de3cf 1105 struct timespec boot;
18068523
GOC		 1106
1107 if (!wall_clock)
1108 return;
1109
9ed3c444
AK		 1110 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1111 if (r)
1112 return;
1113
1114 if (version & 1)
1115 ++version; /* first time write, random junk */
1116
1117 ++version;
18068523 1118
18068523
GOC		 1119 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1120
50d0a0f9
GH		 1121 /*
1122 * The guest calculates current wall clock time by adding
34c238a1 1123 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1124 * wall clock specified here. guest system time equals host
1125 * system time for us, thus we must fill in host boot time here.
1126 */
923de3cf 1127 getboottime(&boot);
50d0a0f9 1128
4b648665
BR		 1129 if (kvm->arch.kvmclock_offset) {
1130 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1131 boot = timespec_sub(boot, ts);
1132 }
50d0a0f9
GH		 1133 wc.sec = boot.tv_sec;
1134 wc.nsec = boot.tv_nsec;
1135 wc.version = version;
18068523
GOC		 1136
1137 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1138
1139 version++;
1140 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1141}
1142
50d0a0f9
GH		 1143static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1144{
1145 uint32_t quotient, remainder;
1146
1147 /* Don't try to replace with do_div(), this one calculates
1148 * "(dividend << 32) / divisor" */
1149 __asm__ ( "divl %4"
1150 : "=a" (quotient), "=d" (remainder)
1151 : "0" (0), "1" (dividend), "r" (divisor) );
1152 return quotient;
1153}
1154
5f4e3f88
ZA		 1155static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1156 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1157{
5f4e3f88 1158 uint64_t scaled64;
50d0a0f9
GH		 1159 int32_t shift = 0;
1160 uint64_t tps64;
1161 uint32_t tps32;
1162
5f4e3f88
ZA		 1163 tps64 = base_khz * 1000LL;
1164 scaled64 = scaled_khz * 1000LL;
50933623 1165 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1166 tps64 >>= 1;
1167 shift--;
1168 }
1169
1170 tps32 = (uint32_t)tps64;
50933623
JK		 1171 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1172 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1173 scaled64 >>= 1;
1174 else
1175 tps32 <<= 1;
50d0a0f9
GH		 1176 shift++;
1177 }
1178
5f4e3f88
ZA		 1179 *pshift = shift;
1180 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1181
5f4e3f88
ZA		 1182 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1183 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1184}
1185
759379dd
ZA		 1186static inline u64 get_kernel_ns(void)
1187{
bb0b5812 1188 return ktime_get_boot_ns();
50d0a0f9
GH		 1189}
1190
d828199e 1191#ifdef CONFIG_X86_64
16e8d74d 1192static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1193#endif
16e8d74d 1194
c8076604 1195static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1196static unsigned long max_tsc_khz;
c8076604 1197
cc578287 1198static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1199{
cc578287
ZA		 1200 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1201 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1202}
1203
cc578287 1204static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1205{
cc578287
ZA		 1206 u64 v = (u64)khz * (1000000 + ppm);
1207 do_div(v, 1000000);
1208 return v;
1e993611
JR		 1209}
1210
cc578287 1211static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1212{
cc578287
ZA		 1213 u32 thresh_lo, thresh_hi;
1214 int use_scaling = 0;
217fc9cf 1215
03ba32ca
MT		 1216 /* tsc_khz can be zero if TSC calibration fails */
1217 if (this_tsc_khz == 0)
1218 return;
1219
c285545f
ZA		 1220 /* Compute a scale to convert nanoseconds in TSC cycles */
1221 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1222 &vcpu->arch.virtual_tsc_shift,
1223 &vcpu->arch.virtual_tsc_mult);
1224 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1225
1226 /*
1227 * Compute the variation in TSC rate which is acceptable
1228 * within the range of tolerance and decide if the
1229 * rate being applied is within that bounds of the hardware
1230 * rate. If so, no scaling or compensation need be done.
1231 */
1232 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1233 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1234 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1235 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1236 use_scaling = 1;
1237 }
1238 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1239}
1240
1241static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1242{
e26101b1 1243 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1244 vcpu->arch.virtual_tsc_mult,
1245 vcpu->arch.virtual_tsc_shift);
e26101b1 1246 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1247 return tsc;
1248}
1249
69b0049a 1250static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1251{
1252#ifdef CONFIG_X86_64
1253 bool vcpus_matched;
b48aa97e
MT		 1254 struct kvm_arch *ka = &vcpu->kvm->arch;
1255 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1256
1257 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1258 atomic_read(&vcpu->kvm->online_vcpus));
1259
7f187922
MT		 1260 /*
1261 * Once the masterclock is enabled, always perform request in
1262 * order to update it.
1263 *
1264 * In order to enable masterclock, the host clocksource must be TSC
1265 * and the vcpus need to have matched TSCs. When that happens,
1266 * perform request to enable masterclock.
1267 */
1268 if (ka->use_master_clock ||
1269 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1270 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1271
1272 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1273 atomic_read(&vcpu->kvm->online_vcpus),
1274 ka->use_master_clock, gtod->clock.vclock_mode);
1275#endif
1276}
1277
ba904635
WA		 1278static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1279{
1280 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1281 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1282}
1283
8fe8ab46 1284void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1285{
1286 struct kvm *kvm = vcpu->kvm;
f38e098f 1287 u64 offset, ns, elapsed;
99e3e30a 1288 unsigned long flags;
02626b6a 1289 s64 usdiff;
b48aa97e 1290 bool matched;
0d3da0d2 1291 bool already_matched;
8fe8ab46 1292 u64 data = msr->data;
99e3e30a 1293
038f8c11 1294 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1295 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1296 ns = get_kernel_ns();
f38e098f 1297 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1298
03ba32ca 1299 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1300 int faulted = 0;
1301
03ba32ca
MT		 1302 /* n.b - signed multiplication and division required */
1303 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1304#ifdef CONFIG_X86_64
03ba32ca 1305 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1306#else
03ba32ca 1307 /* do_div() only does unsigned */
8915aa27
MT		 1308 asm("1: idivl %[divisor]\n"
1309 "2: xor %%edx, %%edx\n"
1310 " movl $0, %[faulted]\n"
1311 "3:\n"
1312 ".section .fixup,\"ax\"\n"
1313 "4: movl $1, %[faulted]\n"
1314 " jmp 3b\n"
1315 ".previous\n"
1316
1317 _ASM_EXTABLE(1b, 4b)
1318
1319 : "=A"(usdiff), [faulted] "=r" (faulted)
1320 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1321
5d3cb0f6 1322#endif
03ba32ca
MT		 1323 do_div(elapsed, 1000);
1324 usdiff -= elapsed;
1325 if (usdiff < 0)
1326 usdiff = -usdiff;
8915aa27
MT		 1327
1328 /* idivl overflow => difference is larger than USEC_PER_SEC */
1329 if (faulted)
1330 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1331 } else
1332 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1333
1334 /*
5d3cb0f6
ZA		 1335 * Special case: TSC write with a small delta (1 second) of virtual
1336 * cycle time against real time is interpreted as an attempt to
1337 * synchronize the CPU.
1338 *
1339 * For a reliable TSC, we can match TSC offsets, and for an unstable
1340 * TSC, we add elapsed time in this computation. We could let the
1341 * compensation code attempt to catch up if we fall behind, but
1342 * it's better to try to match offsets from the beginning.
1343 */
02626b6a 1344 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1345 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1346 if (!check_tsc_unstable()) {
e26101b1 1347 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1348 pr_debug("kvm: matched tsc offset for %llu\n", data);
1349 } else {
857e4099 1350 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1351 data += delta;
1352 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1353 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1354 }
b48aa97e 1355 matched = true;
0d3da0d2 1356 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1357 } else {
1358 /*
1359 * We split periods of matched TSC writes into generations.
1360 * For each generation, we track the original measured
1361 * nanosecond time, offset, and write, so if TSCs are in
1362 * sync, we can match exact offset, and if not, we can match
4a969980 1363 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1364 *
1365 * These values are tracked in kvm->arch.cur_xxx variables.
1366 */
1367 kvm->arch.cur_tsc_generation++;
1368 kvm->arch.cur_tsc_nsec = ns;
1369 kvm->arch.cur_tsc_write = data;
1370 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1371 matched = false;
0d3da0d2 1372 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1373 kvm->arch.cur_tsc_generation, data);
f38e098f 1374 }
e26101b1
ZA		 1375
1376 /*
1377 * We also track th most recent recorded KHZ, write and time to
1378 * allow the matching interval to be extended at each write.
1379 */
f38e098f
ZA		 1380 kvm->arch.last_tsc_nsec = ns;
1381 kvm->arch.last_tsc_write = data;
5d3cb0f6 1382 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1383
b183aa58 1384 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1385
1386 /* Keep track of which generation this VCPU has synchronized to */
1387 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1388 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1389 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1390
ba904635
WA		 1391 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1392 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1393 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1394 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1395
1396 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1397 if (!matched) {
b48aa97e 1398 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1399 } else if (!already_matched) {
1400 kvm->arch.nr_vcpus_matched_tsc++;
1401 }
b48aa97e
MT		 1402
1403 kvm_track_tsc_matching(vcpu);
1404 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1405}
e26101b1 1406
99e3e30a
ZA		 1407EXPORT_SYMBOL_GPL(kvm_write_tsc);
1408
d828199e
MT		 1409#ifdef CONFIG_X86_64
1410
1411static cycle_t read_tsc(void)
1412{
1413 cycle_t ret;
1414 u64 last;
1415
1416 /*
1417 * Empirically, a fence (of type that depends on the CPU)
1418 * before rdtsc is enough to ensure that rdtsc is ordered
1419 * with respect to loads. The various CPU manuals are unclear
1420 * as to whether rdtsc can be reordered with later loads,
1421 * but no one has ever seen it happen.
1422 */
1423 rdtsc_barrier();
1424 ret = (cycle_t)vget_cycles();
1425
1426 last = pvclock_gtod_data.clock.cycle_last;
1427
1428 if (likely(ret >= last))
1429 return ret;
1430
1431 /*
1432 * GCC likes to generate cmov here, but this branch is extremely
1433 * predictable (it's just a funciton of time and the likely is
1434 * very likely) and there's a data dependence, so force GCC
1435 * to generate a branch instead. I don't barrier() because
1436 * we don't actually need a barrier, and if this function
1437 * ever gets inlined it will generate worse code.
1438 */
1439 asm volatile ("");
1440 return last;
1441}
1442
1443static inline u64 vgettsc(cycle_t *cycle_now)
1444{
1445 long v;
1446 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1447
1448 *cycle_now = read_tsc();
1449
1450 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1451 return v * gtod->clock.mult;
1452}
1453
cbcf2dd3 1454static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1455{
cbcf2dd3 1456 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1457 unsigned long seq;
d828199e 1458 int mode;
cbcf2dd3 1459 u64 ns;
d828199e 1460
d828199e
MT		 1461 do {
1462 seq = read_seqcount_begin(&gtod->seq);
1463 mode = gtod->clock.vclock_mode;
cbcf2dd3 1464 ns = gtod->nsec_base;
d828199e
MT		 1465 ns += vgettsc(cycle_now);
1466 ns >>= gtod->clock.shift;
cbcf2dd3 1467 ns += gtod->boot_ns;
d828199e 1468 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1469 *t = ns;
d828199e
MT		 1470
1471 return mode;
1472}
1473
1474/* returns true if host is using tsc clocksource */
1475static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1476{
d828199e
MT		 1477 /* checked again under seqlock below */
1478 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1479 return false;
1480
cbcf2dd3 1481 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1482}
1483#endif
1484
1485/*
1486 *
b48aa97e
MT		 1487 * Assuming a stable TSC across physical CPUS, and a stable TSC
1488 * across virtual CPUs, the following condition is possible.
1489 * Each numbered line represents an event visible to both
d828199e
MT		 1490 * CPUs at the next numbered event.
1491 *
1492 * "timespecX" represents host monotonic time. "tscX" represents
1493 * RDTSC value.
1494 *
1495 * VCPU0 on CPU0 | VCPU1 on CPU1
1496 *
1497 * 1. read timespec0,tsc0
1498 * 2. | timespec1 = timespec0 + N
1499 * | tsc1 = tsc0 + M
1500 * 3. transition to guest | transition to guest
1501 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1502 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1503 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1504 *
1505 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1506 *
1507 * - ret0 < ret1
1508 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1509 * ...
1510 * - 0 < N - M => M < N
1511 *
1512 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1513 * always the case (the difference between two distinct xtime instances
1514 * might be smaller then the difference between corresponding TSC reads,
1515 * when updating guest vcpus pvclock areas).
1516 *
1517 * To avoid that problem, do not allow visibility of distinct
1518 * system_timestamp/tsc_timestamp values simultaneously: use a master
1519 * copy of host monotonic time values. Update that master copy
1520 * in lockstep.
1521 *
b48aa97e 1522 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1523 *
1524 */
1525
1526static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1527{
1528#ifdef CONFIG_X86_64
1529 struct kvm_arch *ka = &kvm->arch;
1530 int vclock_mode;
b48aa97e
MT		 1531 bool host_tsc_clocksource, vcpus_matched;
1532
1533 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1534 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1535
1536 /*
1537 * If the host uses TSC clock, then passthrough TSC as stable
1538 * to the guest.
1539 */
b48aa97e 1540 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1541 &ka->master_kernel_ns,
1542 &ka->master_cycle_now);
1543
16a96021 1544 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1545 && !backwards_tsc_observed
1546 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1547
d828199e
MT		 1548 if (ka->use_master_clock)
1549 atomic_set(&kvm_guest_has_master_clock, 1);
1550
1551 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1552 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1553 vcpus_matched);
d828199e
MT		 1554#endif
1555}
1556
2e762ff7
MT		 1557static void kvm_gen_update_masterclock(struct kvm *kvm)
1558{
1559#ifdef CONFIG_X86_64
1560 int i;
1561 struct kvm_vcpu *vcpu;
1562 struct kvm_arch *ka = &kvm->arch;
1563
1564 spin_lock(&ka->pvclock_gtod_sync_lock);
1565 kvm_make_mclock_inprogress_request(kvm);
1566 /* no guest entries from this point */
1567 pvclock_update_vm_gtod_copy(kvm);
1568
1569 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1570 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1571
1572 /* guest entries allowed */
1573 kvm_for_each_vcpu(i, vcpu, kvm)
1574 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1575
1576 spin_unlock(&ka->pvclock_gtod_sync_lock);
1577#endif
1578}
1579
34c238a1 1580static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1581{
d828199e 1582 unsigned long flags, this_tsc_khz;
18068523 1583 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1584 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1585 s64 kernel_ns;
d828199e 1586 u64 tsc_timestamp, host_tsc;
0b79459b 1587 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1588 u8 pvclock_flags;
d828199e
MT		 1589 bool use_master_clock;
1590
1591 kernel_ns = 0;
1592 host_tsc = 0;
18068523 1593
d828199e
MT		 1594 /*
1595 * If the host uses TSC clock, then passthrough TSC as stable
1596 * to the guest.
1597 */
1598 spin_lock(&ka->pvclock_gtod_sync_lock);
1599 use_master_clock = ka->use_master_clock;
1600 if (use_master_clock) {
1601 host_tsc = ka->master_cycle_now;
1602 kernel_ns = ka->master_kernel_ns;
1603 }
1604 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1605
1606 /* Keep irq disabled to prevent changes to the clock */
1607 local_irq_save(flags);
89cbc767 1608 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1609 if (unlikely(this_tsc_khz == 0)) {
1610 local_irq_restore(flags);
1611 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1612 return 1;
1613 }
d828199e
MT		 1614 if (!use_master_clock) {
1615 host_tsc = native_read_tsc();
1616 kernel_ns = get_kernel_ns();
1617 }
1618
1619 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1620
c285545f
ZA		 1621 /*
1622 * We may have to catch up the TSC to match elapsed wall clock
1623 * time for two reasons, even if kvmclock is used.
1624 * 1) CPU could have been running below the maximum TSC rate
1625 * 2) Broken TSC compensation resets the base at each VCPU
1626 * entry to avoid unknown leaps of TSC even when running
1627 * again on the same CPU. This may cause apparent elapsed
1628 * time to disappear, and the guest to stand still or run
1629 * very slowly.
1630 */
1631 if (vcpu->tsc_catchup) {
1632 u64 tsc = compute_guest_tsc(v, kernel_ns);
1633 if (tsc > tsc_timestamp) {
f1e2b260 1634 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1635 tsc_timestamp = tsc;
1636 }
50d0a0f9
GH		 1637 }
1638
18068523
GOC		 1639 local_irq_restore(flags);
1640
0b79459b 1641 if (!vcpu->pv_time_enabled)
c285545f 1642 return 0;
18068523 1643
e48672fa 1644 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1645 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1646 &vcpu->hv_clock.tsc_shift,
1647 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1648 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1649 }
1650
1651 /* With all the info we got, fill in the values */
1d5f066e 1652 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1653 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1654 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1655
09a0c3f1
OH		 1656 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1657 &guest_hv_clock, sizeof(guest_hv_clock))))
1658 return 0;
1659
18068523
GOC		 1660 /*
1661 * The interface expects us to write an even number signaling that the
1662 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1663 * state, we just increase by 2 at the end.
18068523 1664 */
09a0c3f1 1665 vcpu->hv_clock.version = guest_hv_clock.version + 2;
78c0337a
MT		 1666
1667 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1668 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1669
1670 if (vcpu->pvclock_set_guest_stopped_request) {
1671 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1672 vcpu->pvclock_set_guest_stopped_request = false;
1673 }
1674
d828199e
MT		 1675 /* If the host uses TSC clocksource, then it is stable */
1676 if (use_master_clock)
1677 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1678
78c0337a
MT		 1679 vcpu->hv_clock.flags = pvclock_flags;
1680
ce1a5e60
DM		 1681 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1682
0b79459b
AH		 1683 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1684 &vcpu->hv_clock,
1685 sizeof(vcpu->hv_clock));
8cfdc000 1686 return 0;
c8076604
GH		 1687}
1688
0061d53d
MT		 1689/*
1690 * kvmclock updates which are isolated to a given vcpu, such as
1691 * vcpu->cpu migration, should not allow system_timestamp from
1692 * the rest of the vcpus to remain static. Otherwise ntp frequency
1693 * correction applies to one vcpu's system_timestamp but not
1694 * the others.
1695 *
1696 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1697 * We need to rate-limit these requests though, as they can
1698 * considerably slow guests that have a large number of vcpus.
1699 * The time for a remote vcpu to update its kvmclock is bound
1700 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1701 */
1702
7e44e449
AJ		 1703#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1704
1705static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1706{
1707 int i;
7e44e449
AJ		 1708 struct delayed_work *dwork = to_delayed_work(work);
1709 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1710 kvmclock_update_work);
1711 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1712 struct kvm_vcpu *vcpu;
1713
1714 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1715 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1716 kvm_vcpu_kick(vcpu);
1717 }
1718}
1719
7e44e449
AJ		 1720static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1721{
1722 struct kvm *kvm = v->kvm;
1723
105b21bb 1724 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1725 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1726 KVMCLOCK_UPDATE_DELAY);
1727}
1728
332967a3
AJ		 1729#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1730
1731static void kvmclock_sync_fn(struct work_struct *work)
1732{
1733 struct delayed_work *dwork = to_delayed_work(work);
1734 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1735 kvmclock_sync_work);
1736 struct kvm *kvm = container_of(ka, struct kvm, arch);
1737
1738 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1739 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1740 KVMCLOCK_SYNC_PERIOD);
1741}
1742
9ba075a6
AK		 1743static bool msr_mtrr_valid(unsigned msr)
1744{
1745 switch (msr) {
1746 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1747 case MSR_MTRRfix64K_00000:
1748 case MSR_MTRRfix16K_80000:
1749 case MSR_MTRRfix16K_A0000:
1750 case MSR_MTRRfix4K_C0000:
1751 case MSR_MTRRfix4K_C8000:
1752 case MSR_MTRRfix4K_D0000:
1753 case MSR_MTRRfix4K_D8000:
1754 case MSR_MTRRfix4K_E0000:
1755 case MSR_MTRRfix4K_E8000:
1756 case MSR_MTRRfix4K_F0000:
1757 case MSR_MTRRfix4K_F8000:
1758 case MSR_MTRRdefType:
1759 case MSR_IA32_CR_PAT:
1760 return true;
1761 case 0x2f8:
1762 return true;
1763 }
1764 return false;
1765}
1766
d6289b93
MT		 1767static bool valid_pat_type(unsigned t)
1768{
1769 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1770}
1771
1772static bool valid_mtrr_type(unsigned t)
1773{
1774 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1775}
1776
4566654b 1777bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1778{
1779 int i;
fd275235 1780 u64 mask;
d6289b93
MT		 1781
1782 if (!msr_mtrr_valid(msr))
1783 return false;
1784
1785 if (msr == MSR_IA32_CR_PAT) {
1786 for (i = 0; i < 8; i++)
1787 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1788 return false;
1789 return true;
1790 } else if (msr == MSR_MTRRdefType) {
1791 if (data & ~0xcff)
1792 return false;
1793 return valid_mtrr_type(data & 0xff);
1794 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1795 for (i = 0; i < 8 ; i++)
1796 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1797 return false;
1798 return true;
1799 }
1800
1801 /* variable MTRRs */
adfb5d27
WL		 1802 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1803
fd275235 1804 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1805 if ((msr & 1) == 0) {
adfb5d27 1806 /* MTRR base */
d7a2a246
WL		 1807 if (!valid_mtrr_type(data & 0xff))
1808 return false;
1809 mask |= 0xf00;
1810 } else
1811 /* MTRR mask */
1812 mask |= 0x7ff;
1813 if (data & mask) {
1814 kvm_inject_gp(vcpu, 0);
1815 return false;
1816 }
1817
adfb5d27 1818 return true;
d6289b93 1819}
4566654b 1820EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1821
9ba075a6
AK		 1822static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1823{
0bed3b56
SY		 1824 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1825
4566654b 1826 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1827 return 1;
1828
0bed3b56
SY		 1829 if (msr == MSR_MTRRdefType) {
1830 vcpu->arch.mtrr_state.def_type = data;
1831 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1832 } else if (msr == MSR_MTRRfix64K_00000)
1833 p[0] = data;
1834 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1835 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1836 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1837 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1838 else if (msr == MSR_IA32_CR_PAT)
1839 vcpu->arch.pat = data;
1840 else { /* Variable MTRRs */
1841 int idx, is_mtrr_mask;
1842 u64 *pt;
1843
1844 idx = (msr - 0x200) / 2;
1845 is_mtrr_mask = msr - 0x200 - 2 * idx;
1846 if (!is_mtrr_mask)
1847 pt =
1848 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1849 else
1850 pt =
1851 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1852 *pt = data;
1853 }
1854
1855 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1856 return 0;
1857}
15c4a640 1858
890ca9ae 1859static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1860{
890ca9ae
HY		 1861 u64 mcg_cap = vcpu->arch.mcg_cap;
1862 unsigned bank_num = mcg_cap & 0xff;
1863
15c4a640 1864 switch (msr) {
15c4a640 1865 case MSR_IA32_MCG_STATUS:
890ca9ae 1866 vcpu->arch.mcg_status = data;
15c4a640 1867 break;
c7ac679c 1868 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1869 if (!(mcg_cap & MCG_CTL_P))
1870 return 1;
1871 if (data != 0 && data != ~(u64)0)
1872 return -1;
1873 vcpu->arch.mcg_ctl = data;
1874 break;
1875 default:
1876 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1877 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1878 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1879 /* only 0 or all 1s can be written to IA32_MCi_CTL
1880 * some Linux kernels though clear bit 10 in bank 4 to
1881 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1882 * this to avoid an uncatched #GP in the guest
1883 */
890ca9ae 1884 if ((offset & 0x3) == 0 &&
114be429 1885 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1886 return -1;
1887 vcpu->arch.mce_banks[offset] = data;
1888 break;
1889 }
1890 return 1;
1891 }
1892 return 0;
1893}
1894
ffde22ac
ES		 1895static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1896{
1897 struct kvm *kvm = vcpu->kvm;
1898 int lm = is_long_mode(vcpu);
1899 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1900 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1901 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1902 : kvm->arch.xen_hvm_config.blob_size_32;
1903 u32 page_num = data & ~PAGE_MASK;
1904 u64 page_addr = data & PAGE_MASK;
1905 u8 *page;
1906 int r;
1907
1908 r = -E2BIG;
1909 if (page_num >= blob_size)
1910 goto out;
1911 r = -ENOMEM;
ff5c2c03
SL		 1912 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1913 if (IS_ERR(page)) {
1914 r = PTR_ERR(page);
ffde22ac 1915 goto out;
ff5c2c03 1916 }
ffde22ac
ES		 1917 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1918 goto out_free;
1919 r = 0;
1920out_free:
1921 kfree(page);
1922out:
1923 return r;
1924}
1925
55cd8e5a
GN		 1926static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1927{
1928 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1929}
1930
1931static bool kvm_hv_msr_partition_wide(u32 msr)
1932{
1933 bool r = false;
1934 switch (msr) {
1935 case HV_X64_MSR_GUEST_OS_ID:
1936 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1937 case HV_X64_MSR_REFERENCE_TSC:
1938 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1939 r = true;
1940 break;
1941 }
1942
1943 return r;
1944}
1945
1946static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1947{
1948 struct kvm *kvm = vcpu->kvm;
1949
1950 switch (msr) {
1951 case HV_X64_MSR_GUEST_OS_ID:
1952 kvm->arch.hv_guest_os_id = data;
1953 /* setting guest os id to zero disables hypercall page */
1954 if (!kvm->arch.hv_guest_os_id)
1955 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1956 break;
1957 case HV_X64_MSR_HYPERCALL: {
1958 u64 gfn;
1959 unsigned long addr;
1960 u8 instructions[4];
1961
1962 /* if guest os id is not set hypercall should remain disabled */
1963 if (!kvm->arch.hv_guest_os_id)
1964 break;
1965 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1966 kvm->arch.hv_hypercall = data;
1967 break;
1968 }
1969 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1970 addr = gfn_to_hva(kvm, gfn);
1971 if (kvm_is_error_hva(addr))
1972 return 1;
1973 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1974 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1975 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1976 return 1;
1977 kvm->arch.hv_hypercall = data;
b94b64c9 1978 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1979 break;
1980 }
e984097b
VR		 1981 case HV_X64_MSR_REFERENCE_TSC: {
1982 u64 gfn;
1983 HV_REFERENCE_TSC_PAGE tsc_ref;
1984 memset(&tsc_ref, 0, sizeof(tsc_ref));
1985 kvm->arch.hv_tsc_page = data;
1986 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1987 break;
1988 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1989 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1990 &tsc_ref, sizeof(tsc_ref)))
1991 return 1;
1992 mark_page_dirty(kvm, gfn);
1993 break;
1994 }
55cd8e5a 1995 default:
a737f256
CD		 1996 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1997 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1998 return 1;
1999 }
2000 return 0;
2001}
2002
2003static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2004{
10388a07
GN		 2005 switch (msr) {
2006 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2007 u64 gfn;
10388a07 2008 unsigned long addr;
55cd8e5a 2009
10388a07
GN		 2010 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2011 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2012 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2013 return 1;
10388a07
GN		 2014 break;
2015 }
b3af1e88
VR		 2016 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2017 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2018 if (kvm_is_error_hva(addr))
2019 return 1;
8b0cedff 2020 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2021 return 1;
2022 vcpu->arch.hv_vapic = data;
b3af1e88 2023 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2024 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2025 return 1;
10388a07
GN		 2026 break;
2027 }
2028 case HV_X64_MSR_EOI:
2029 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2030 case HV_X64_MSR_ICR:
2031 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2032 case HV_X64_MSR_TPR:
2033 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2034 default:
a737f256
CD		 2035 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2036 "data 0x%llx\n", msr, data);
10388a07
GN		 2037 return 1;
2038 }
2039
2040 return 0;
55cd8e5a
GN		 2041}
2042
344d9588
GN		 2043static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2044{
2045 gpa_t gpa = data & ~0x3f;
2046
4a969980 2047 /* Bits 2:5 are reserved, Should be zero */
6adba527 2048 if (data & 0x3c)
344d9588
GN		 2049 return 1;
2050
2051 vcpu->arch.apf.msr_val = data;
2052
2053 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2054 kvm_clear_async_pf_completion_queue(vcpu);
2055 kvm_async_pf_hash_reset(vcpu);
2056 return 0;
2057 }
2058
8f964525
AH		 2059 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2060 sizeof(u32)))
344d9588
GN		 2061 return 1;
2062
6adba527 2063 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2064 kvm_async_pf_wakeup_all(vcpu);
2065 return 0;
2066}
2067
12f9a48f
GC		 2068static void kvmclock_reset(struct kvm_vcpu *vcpu)
2069{
0b79459b 2070 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2071}
2072
c9aaa895
GC		 2073static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2074{
2075 u64 delta;
2076
2077 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2078 return;
2079
2080 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2081 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2082 vcpu->arch.st.accum_steal = delta;
2083}
2084
2085static void record_steal_time(struct kvm_vcpu *vcpu)
2086{
2087 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2088 return;
2089
2090 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2091 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2092 return;
2093
2094 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2095 vcpu->arch.st.steal.version += 2;
2096 vcpu->arch.st.accum_steal = 0;
2097
2098 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2099 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2100}
2101
8fe8ab46 2102int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2103{
5753785f 2104 bool pr = false;
8fe8ab46
WA		 2105 u32 msr = msr_info->index;
2106 u64 data = msr_info->data;
5753785f 2107
15c4a640 2108 switch (msr) {
2e32b719
BP		 2109 case MSR_AMD64_NB_CFG:
2110 case MSR_IA32_UCODE_REV:
2111 case MSR_IA32_UCODE_WRITE:
2112 case MSR_VM_HSAVE_PA:
2113 case MSR_AMD64_PATCH_LOADER:
2114 case MSR_AMD64_BU_CFG2:
2115 break;
2116
15c4a640 2117 case MSR_EFER:
b69e8cae 2118 return set_efer(vcpu, data);
8f1589d9
AP		 2119 case MSR_K7_HWCR:
2120 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2121 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2122 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2123 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2124 if (data != 0) {
a737f256
CD		 2125 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2126 data);
8f1589d9
AP		 2127 return 1;
2128 }
15c4a640 2129 break;
f7c6d140
AP		 2130 case MSR_FAM10H_MMIO_CONF_BASE:
2131 if (data != 0) {
a737f256
CD		 2132 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2133 "0x%llx\n", data);
f7c6d140
AP		 2134 return 1;
2135 }
15c4a640 2136 break;
b5e2fec0
AG		 2137 case MSR_IA32_DEBUGCTLMSR:
2138 if (!data) {
2139 /* We support the non-activated case already */
2140 break;
2141 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2142 /* Values other than LBR and BTF are vendor-specific,
2143 thus reserved and should throw a #GP */
2144 return 1;
2145 }
a737f256
CD		 2146 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2147 __func__, data);
b5e2fec0 2148 break;
9ba075a6
AK		 2149 case 0x200 ... 0x2ff:
2150 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2151 case MSR_IA32_APICBASE:
58cb628d 2152 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2153 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2154 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2155 case MSR_IA32_TSCDEADLINE:
2156 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2157 break;
ba904635
WA		 2158 case MSR_IA32_TSC_ADJUST:
2159 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2160 if (!msr_info->host_initiated) {
d913b904 2161 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2162 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2163 }
2164 vcpu->arch.ia32_tsc_adjust_msr = data;
2165 }
2166 break;
15c4a640 2167 case MSR_IA32_MISC_ENABLE:
ad312c7c 2168 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2169 break;
11c6bffa 2170 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2171 case MSR_KVM_WALL_CLOCK:
2172 vcpu->kvm->arch.wall_clock = data;
2173 kvm_write_wall_clock(vcpu->kvm, data);
2174 break;
11c6bffa 2175 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2176 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2177 u64 gpa_offset;
54750f2c
MT		 2178 struct kvm_arch *ka = &vcpu->kvm->arch;
2179
12f9a48f 2180 kvmclock_reset(vcpu);
18068523 2181
54750f2c
MT		 2182 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2183 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2184
2185 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2186 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2187 &vcpu->requests);
2188
2189 ka->boot_vcpu_runs_old_kvmclock = tmp;
2190 }
2191
18068523 2192 vcpu->arch.time = data;
0061d53d 2193 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2194
2195 /* we verify if the enable bit is set... */
2196 if (!(data & 1))
2197 break;
2198
0b79459b 2199 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2200
0b79459b 2201 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2202 &vcpu->arch.pv_time, data & ~1ULL,
2203 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2204 vcpu->arch.pv_time_enabled = false;
2205 else
2206 vcpu->arch.pv_time_enabled = true;
32cad84f 2207
18068523
GOC		 2208 break;
2209 }
344d9588
GN		 2210 case MSR_KVM_ASYNC_PF_EN:
2211 if (kvm_pv_enable_async_pf(vcpu, data))
2212 return 1;
2213 break;
c9aaa895
GC		 2214 case MSR_KVM_STEAL_TIME:
2215
2216 if (unlikely(!sched_info_on()))
2217 return 1;
2218
2219 if (data & KVM_STEAL_RESERVED_MASK)
2220 return 1;
2221
2222 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2223 data & KVM_STEAL_VALID_BITS,
2224 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2225 return 1;
2226
2227 vcpu->arch.st.msr_val = data;
2228
2229 if (!(data & KVM_MSR_ENABLED))
2230 break;
2231
2232 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2233
2234 preempt_disable();
2235 accumulate_steal_time(vcpu);
2236 preempt_enable();
2237
2238 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2239
2240 break;
ae7a2a3f
MT		 2241 case MSR_KVM_PV_EOI_EN:
2242 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2243 return 1;
2244 break;
c9aaa895 2245
890ca9ae
HY		 2246 case MSR_IA32_MCG_CTL:
2247 case MSR_IA32_MCG_STATUS:
81760dcc 2248 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2249 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2250
2251 /* Performance counters are not protected by a CPUID bit,
2252 * so we should check all of them in the generic path for the sake of
2253 * cross vendor migration.
2254 * Writing a zero into the event select MSRs disables them,
2255 * which we perfectly emulate ;-). Any other value should be at least
2256 * reported, some guests depend on them.
2257 */
71db6023
AP		 2258 case MSR_K7_EVNTSEL0:
2259 case MSR_K7_EVNTSEL1:
2260 case MSR_K7_EVNTSEL2:
2261 case MSR_K7_EVNTSEL3:
2262 if (data != 0)
a737f256
CD		 2263 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2264 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2265 break;
2266 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2267 * so we ignore writes to make it happy.
2268 */
71db6023
AP		 2269 case MSR_K7_PERFCTR0:
2270 case MSR_K7_PERFCTR1:
2271 case MSR_K7_PERFCTR2:
2272 case MSR_K7_PERFCTR3:
a737f256
CD		 2273 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2274 "0x%x data 0x%llx\n", msr, data);
71db6023 2275 break;
5753785f
GN		 2276 case MSR_P6_PERFCTR0:
2277 case MSR_P6_PERFCTR1:
2278 pr = true;
2279 case MSR_P6_EVNTSEL0:
2280 case MSR_P6_EVNTSEL1:
2281 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2282 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2283
2284 if (pr || data != 0)
a737f256
CD		 2285 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2286 "0x%x data 0x%llx\n", msr, data);
5753785f 2287 break;
84e0cefa
JS		 2288 case MSR_K7_CLK_CTL:
2289 /*
2290 * Ignore all writes to this no longer documented MSR.
2291 * Writes are only relevant for old K7 processors,
2292 * all pre-dating SVM, but a recommended workaround from
4a969980 2293 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2294 * affected processor models on the command line, hence
2295 * the need to ignore the workaround.
2296 */
2297 break;
55cd8e5a
GN		 2298 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2299 if (kvm_hv_msr_partition_wide(msr)) {
2300 int r;
2301 mutex_lock(&vcpu->kvm->lock);
2302 r = set_msr_hyperv_pw(vcpu, msr, data);
2303 mutex_unlock(&vcpu->kvm->lock);
2304 return r;
2305 } else
2306 return set_msr_hyperv(vcpu, msr, data);
2307 break;
91c9c3ed 2308 case MSR_IA32_BBL_CR_CTL3:
2309 /* Drop writes to this legacy MSR -- see rdmsr
2310 * counterpart for further detail.
2311 */
a737f256 2312 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2313 break;
2b036c6b
BO		 2314 case MSR_AMD64_OSVW_ID_LENGTH:
2315 if (!guest_cpuid_has_osvw(vcpu))
2316 return 1;
2317 vcpu->arch.osvw.length = data;
2318 break;
2319 case MSR_AMD64_OSVW_STATUS:
2320 if (!guest_cpuid_has_osvw(vcpu))
2321 return 1;
2322 vcpu->arch.osvw.status = data;
2323 break;
15c4a640 2324 default:
ffde22ac
ES		 2325 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2326 return xen_hvm_config(vcpu, data);
f5132b01 2327 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2328 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2329 if (!ignore_msrs) {
a737f256
CD		 2330 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2331 msr, data);
ed85c068
AP		 2332 return 1;
2333 } else {
a737f256
CD		 2334 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2335 msr, data);
ed85c068
AP		 2336 break;
2337 }
15c4a640
CO		 2338 }
2339 return 0;
2340}
2341EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2342
2343
2344/*
2345 * Reads an msr value (of 'msr_index') into 'pdata'.
2346 * Returns 0 on success, non-0 otherwise.
2347 * Assumes vcpu_load() was already called.
2348 */
2349int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2350{
2351 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2352}
ff651cb6 2353EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2354
9ba075a6
AK		 2355static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2356{
0bed3b56
SY		 2357 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2358
9ba075a6
AK		 2359 if (!msr_mtrr_valid(msr))
2360 return 1;
2361
0bed3b56
SY		 2362 if (msr == MSR_MTRRdefType)
2363 *pdata = vcpu->arch.mtrr_state.def_type +
2364 (vcpu->arch.mtrr_state.enabled << 10);
2365 else if (msr == MSR_MTRRfix64K_00000)
2366 *pdata = p[0];
2367 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2368 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2369 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2370 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2371 else if (msr == MSR_IA32_CR_PAT)
2372 *pdata = vcpu->arch.pat;
2373 else { /* Variable MTRRs */
2374 int idx, is_mtrr_mask;
2375 u64 *pt;
2376
2377 idx = (msr - 0x200) / 2;
2378 is_mtrr_mask = msr - 0x200 - 2 * idx;
2379 if (!is_mtrr_mask)
2380 pt =
2381 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2382 else
2383 pt =
2384 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2385 *pdata = *pt;
2386 }
2387
9ba075a6
AK		 2388 return 0;
2389}
2390
890ca9ae 2391static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2392{
2393 u64 data;
890ca9ae
HY		 2394 u64 mcg_cap = vcpu->arch.mcg_cap;
2395 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2396
2397 switch (msr) {
15c4a640
CO		 2398 case MSR_IA32_P5_MC_ADDR:
2399 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2400 data = 0;
2401 break;
15c4a640 2402 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2403 data = vcpu->arch.mcg_cap;
2404 break;
c7ac679c 2405 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2406 if (!(mcg_cap & MCG_CTL_P))
2407 return 1;
2408 data = vcpu->arch.mcg_ctl;
2409 break;
2410 case MSR_IA32_MCG_STATUS:
2411 data = vcpu->arch.mcg_status;
2412 break;
2413 default:
2414 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2415 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2416 u32 offset = msr - MSR_IA32_MC0_CTL;
2417 data = vcpu->arch.mce_banks[offset];
2418 break;
2419 }
2420 return 1;
2421 }
2422 *pdata = data;
2423 return 0;
2424}
2425
55cd8e5a
GN		 2426static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2427{
2428 u64 data = 0;
2429 struct kvm *kvm = vcpu->kvm;
2430
2431 switch (msr) {
2432 case HV_X64_MSR_GUEST_OS_ID:
2433 data = kvm->arch.hv_guest_os_id;
2434 break;
2435 case HV_X64_MSR_HYPERCALL:
2436 data = kvm->arch.hv_hypercall;
2437 break;
e984097b
VR		 2438 case HV_X64_MSR_TIME_REF_COUNT: {
2439 data =
2440 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2441 break;
2442 }
2443 case HV_X64_MSR_REFERENCE_TSC:
2444 data = kvm->arch.hv_tsc_page;
2445 break;
55cd8e5a 2446 default:
a737f256 2447 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2448 return 1;
2449 }
2450
2451 *pdata = data;
2452 return 0;
2453}
2454
2455static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2456{
2457 u64 data = 0;
2458
2459 switch (msr) {
2460 case HV_X64_MSR_VP_INDEX: {
2461 int r;
2462 struct kvm_vcpu *v;
684851a1
TY		 2463 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2464 if (v == vcpu) {
55cd8e5a 2465 data = r;
684851a1
TY		 2466 break;
2467 }
2468 }
55cd8e5a
GN		 2469 break;
2470 }
10388a07
GN		 2471 case HV_X64_MSR_EOI:
2472 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2473 case HV_X64_MSR_ICR:
2474 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2475 case HV_X64_MSR_TPR:
2476 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2477 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2478 data = vcpu->arch.hv_vapic;
2479 break;
55cd8e5a 2480 default:
a737f256 2481 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2482 return 1;
2483 }
2484 *pdata = data;
2485 return 0;
2486}
2487
890ca9ae
HY		 2488int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2489{
2490 u64 data;
2491
2492 switch (msr) {
890ca9ae 2493 case MSR_IA32_PLATFORM_ID:
15c4a640 2494 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2495 case MSR_IA32_DEBUGCTLMSR:
2496 case MSR_IA32_LASTBRANCHFROMIP:
2497 case MSR_IA32_LASTBRANCHTOIP:
2498 case MSR_IA32_LASTINTFROMIP:
2499 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2500 case MSR_K8_SYSCFG:
2501 case MSR_K7_HWCR:
61a6bd67 2502 case MSR_VM_HSAVE_PA:
9e699624 2503 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2504 case MSR_K7_EVNTSEL1:
2505 case MSR_K7_EVNTSEL2:
2506 case MSR_K7_EVNTSEL3:
1f3ee616 2507 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2508 case MSR_K7_PERFCTR1:
2509 case MSR_K7_PERFCTR2:
2510 case MSR_K7_PERFCTR3:
1fdbd48c 2511 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2512 case MSR_AMD64_NB_CFG:
f7c6d140 2513 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2514 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2515 data = 0;
2516 break;
5753785f
GN		 2517 case MSR_P6_PERFCTR0:
2518 case MSR_P6_PERFCTR1:
2519 case MSR_P6_EVNTSEL0:
2520 case MSR_P6_EVNTSEL1:
2521 if (kvm_pmu_msr(vcpu, msr))
2522 return kvm_pmu_get_msr(vcpu, msr, pdata);
2523 data = 0;
2524 break;
742bc670
MT		 2525 case MSR_IA32_UCODE_REV:
2526 data = 0x100000000ULL;
2527 break;
9ba075a6
AK		 2528 case MSR_MTRRcap:
2529 data = 0x500 | KVM_NR_VAR_MTRR;
2530 break;
2531 case 0x200 ... 0x2ff:
2532 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2533 case 0xcd: /* fsb frequency */
2534 data = 3;
2535 break;
7b914098
JS		 2536 /*
2537 * MSR_EBC_FREQUENCY_ID
2538 * Conservative value valid for even the basic CPU models.
2539 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2540 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2541 * and 266MHz for model 3, or 4. Set Core Clock
2542 * Frequency to System Bus Frequency Ratio to 1 (bits
2543 * 31:24) even though these are only valid for CPU
2544 * models > 2, however guests may end up dividing or
2545 * multiplying by zero otherwise.
2546 */
2547 case MSR_EBC_FREQUENCY_ID:
2548 data = 1 << 24;
2549 break;
15c4a640
CO		 2550 case MSR_IA32_APICBASE:
2551 data = kvm_get_apic_base(vcpu);
2552 break;
0105d1a5
GN		 2553 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2554 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2555 break;
a3e06bbe
LJ		 2556 case MSR_IA32_TSCDEADLINE:
2557 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2558 break;
ba904635
WA		 2559 case MSR_IA32_TSC_ADJUST:
2560 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2561 break;
15c4a640 2562 case MSR_IA32_MISC_ENABLE:
ad312c7c 2563 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2564 break;
847f0ad8
AG		 2565 case MSR_IA32_PERF_STATUS:
2566 /* TSC increment by tick */
2567 data = 1000ULL;
2568 /* CPU multiplier */
2569 data |= (((uint64_t)4ULL) << 40);
2570 break;
15c4a640 2571 case MSR_EFER:
f6801dff 2572 data = vcpu->arch.efer;
15c4a640 2573 break;
18068523 2574 case MSR_KVM_WALL_CLOCK:
11c6bffa 2575 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2576 data = vcpu->kvm->arch.wall_clock;
2577 break;
2578 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2579 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2580 data = vcpu->arch.time;
2581 break;
344d9588
GN		 2582 case MSR_KVM_ASYNC_PF_EN:
2583 data = vcpu->arch.apf.msr_val;
2584 break;
c9aaa895
GC		 2585 case MSR_KVM_STEAL_TIME:
2586 data = vcpu->arch.st.msr_val;
2587 break;
1d92128f
MT		 2588 case MSR_KVM_PV_EOI_EN:
2589 data = vcpu->arch.pv_eoi.msr_val;
2590 break;
890ca9ae
HY		 2591 case MSR_IA32_P5_MC_ADDR:
2592 case MSR_IA32_P5_MC_TYPE:
2593 case MSR_IA32_MCG_CAP:
2594 case MSR_IA32_MCG_CTL:
2595 case MSR_IA32_MCG_STATUS:
81760dcc 2596 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2597 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2598 case MSR_K7_CLK_CTL:
2599 /*
2600 * Provide expected ramp-up count for K7. All other
2601 * are set to zero, indicating minimum divisors for
2602 * every field.
2603 *
2604 * This prevents guest kernels on AMD host with CPU
2605 * type 6, model 8 and higher from exploding due to
2606 * the rdmsr failing.
2607 */
2608 data = 0x20000000;
2609 break;
55cd8e5a
GN		 2610 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2611 if (kvm_hv_msr_partition_wide(msr)) {
2612 int r;
2613 mutex_lock(&vcpu->kvm->lock);
2614 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2615 mutex_unlock(&vcpu->kvm->lock);
2616 return r;
2617 } else
2618 return get_msr_hyperv(vcpu, msr, pdata);
2619 break;
91c9c3ed 2620 case MSR_IA32_BBL_CR_CTL3:
2621 /* This legacy MSR exists but isn't fully documented in current
2622 * silicon. It is however accessed by winxp in very narrow
2623 * scenarios where it sets bit #19, itself documented as
2624 * a "reserved" bit. Best effort attempt to source coherent
2625 * read data here should the balance of the register be
2626 * interpreted by the guest:
2627 *
2628 * L2 cache control register 3: 64GB range, 256KB size,
2629 * enabled, latency 0x1, configured
2630 */
2631 data = 0xbe702111;
2632 break;
2b036c6b
BO		 2633 case MSR_AMD64_OSVW_ID_LENGTH:
2634 if (!guest_cpuid_has_osvw(vcpu))
2635 return 1;
2636 data = vcpu->arch.osvw.length;
2637 break;
2638 case MSR_AMD64_OSVW_STATUS:
2639 if (!guest_cpuid_has_osvw(vcpu))
2640 return 1;
2641 data = vcpu->arch.osvw.status;
2642 break;
15c4a640 2643 default:
f5132b01
GN		 2644 if (kvm_pmu_msr(vcpu, msr))
2645 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2646 if (!ignore_msrs) {
a737f256 2647 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2648 return 1;
2649 } else {
a737f256 2650 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2651 data = 0;
2652 }
2653 break;
15c4a640
CO		 2654 }
2655 *pdata = data;
2656 return 0;
2657}
2658EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2659
313a3dc7
CO		 2660/*
2661 * Read or write a bunch of msrs. All parameters are kernel addresses.
2662 *
2663 * @return number of msrs set successfully.
2664 */
2665static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2666 struct kvm_msr_entry *entries,
2667 int (*do_msr)(struct kvm_vcpu *vcpu,
2668 unsigned index, u64 *data))
2669{
f656ce01 2670 int i, idx;
313a3dc7 2671
f656ce01 2672 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2673 for (i = 0; i < msrs->nmsrs; ++i)
2674 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2675 break;
f656ce01 2676 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2677
313a3dc7
CO		 2678 return i;
2679}
2680
2681/*
2682 * Read or write a bunch of msrs. Parameters are user addresses.
2683 *
2684 * @return number of msrs set successfully.
2685 */
2686static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2687 int (*do_msr)(struct kvm_vcpu *vcpu,
2688 unsigned index, u64 *data),
2689 int writeback)
2690{
2691 struct kvm_msrs msrs;
2692 struct kvm_msr_entry *entries;
2693 int r, n;
2694 unsigned size;
2695
2696 r = -EFAULT;
2697 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2698 goto out;
2699
2700 r = -E2BIG;
2701 if (msrs.nmsrs >= MAX_IO_MSRS)
2702 goto out;
2703
313a3dc7 2704 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2705 entries = memdup_user(user_msrs->entries, size);
2706 if (IS_ERR(entries)) {
2707 r = PTR_ERR(entries);
313a3dc7 2708 goto out;
ff5c2c03 2709 }
313a3dc7
CO		 2710
2711 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2712 if (r < 0)
2713 goto out_free;
2714
2715 r = -EFAULT;
2716 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2717 goto out_free;
2718
2719 r = n;
2720
2721out_free:
7a73c028 2722 kfree(entries);
313a3dc7
CO		 2723out:
2724 return r;
2725}
2726
784aa3d7 2727int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2728{
2729 int r;
2730
2731 switch (ext) {
2732 case KVM_CAP_IRQCHIP:
2733 case KVM_CAP_HLT:
2734 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2735 case KVM_CAP_SET_TSS_ADDR:
07716717 2736 case KVM_CAP_EXT_CPUID:
9c15bb1d 2737 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2738 case KVM_CAP_CLOCKSOURCE:
7837699f 2739 case KVM_CAP_PIT:
a28e4f5a 2740 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2741 case KVM_CAP_MP_STATE:
ed848624 2742 case KVM_CAP_SYNC_MMU:
a355c85c 2743 case KVM_CAP_USER_NMI:
52d939a0 2744 case KVM_CAP_REINJECT_CONTROL:
4925663a 2745 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2746 case KVM_CAP_IRQFD:
d34e6b17 2747 case KVM_CAP_IOEVENTFD:
f848a5a8 2748 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2749 case KVM_CAP_PIT2:
e9f42757 2750 case KVM_CAP_PIT_STATE2:
b927a3ce 2751 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2752 case KVM_CAP_XEN_HVM:
afbcf7ab 2753 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2754 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2755 case KVM_CAP_HYPERV:
10388a07 2756 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2757 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2758 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2759 case KVM_CAP_DEBUGREGS:
d2be1651 2760 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2761 case KVM_CAP_XSAVE:
344d9588 2762 case KVM_CAP_ASYNC_PF:
92a1f12d 2763 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2764 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2765 case KVM_CAP_READONLY_MEM:
5f66b620 2766 case KVM_CAP_HYPERV_TIME:
100943c5 2767 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2768 case KVM_CAP_TSC_DEADLINE_TIMER:
2a5bab10
AW		 2769#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2770 case KVM_CAP_ASSIGN_DEV_IRQ:
2771 case KVM_CAP_PCI_2_3:
2772#endif
018d00d2
ZX		 2773 r = 1;
2774 break;
542472b5
LV		 2775 case KVM_CAP_COALESCED_MMIO:
2776 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2777 break;
774ead3a
AK		 2778 case KVM_CAP_VAPIC:
2779 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2780 break;
f725230a 2781 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2782 r = KVM_SOFT_MAX_VCPUS;
2783 break;
2784 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2785 r = KVM_MAX_VCPUS;
2786 break;
a988b910 2787 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2788 r = KVM_USER_MEM_SLOTS;
a988b910 2789 break;
a68a6a72
MT		 2790 case KVM_CAP_PV_MMU: /* obsolete */
2791 r = 0;
2f333bcb 2792 break;
4cee4b72 2793#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2794 case KVM_CAP_IOMMU:
a1b60c1c 2795 r = iommu_present(&pci_bus_type);
62c476c7 2796 break;
4cee4b72 2797#endif
890ca9ae
HY		 2798 case KVM_CAP_MCE:
2799 r = KVM_MAX_MCE_BANKS;
2800 break;
2d5b5a66
SY		 2801 case KVM_CAP_XCRS:
2802 r = cpu_has_xsave;
2803 break;
92a1f12d
JR		 2804 case KVM_CAP_TSC_CONTROL:
2805 r = kvm_has_tsc_control;
2806 break;
018d00d2
ZX		 2807 default:
2808 r = 0;
2809 break;
2810 }
2811 return r;
2812
2813}
2814
043405e1
CO		 2815long kvm_arch_dev_ioctl(struct file *filp,
2816 unsigned int ioctl, unsigned long arg)
2817{
2818 void __user *argp = (void __user *)arg;
2819 long r;
2820
2821 switch (ioctl) {
2822 case KVM_GET_MSR_INDEX_LIST: {
2823 struct kvm_msr_list __user *user_msr_list = argp;
2824 struct kvm_msr_list msr_list;
2825 unsigned n;
2826
2827 r = -EFAULT;
2828 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2829 goto out;
2830 n = msr_list.nmsrs;
2831 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2832 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2833 goto out;
2834 r = -E2BIG;
e125e7b6 2835 if (n < msr_list.nmsrs)
043405e1
CO		 2836 goto out;
2837 r = -EFAULT;
2838 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2839 num_msrs_to_save * sizeof(u32)))
2840 goto out;
e125e7b6 2841 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2842 &emulated_msrs,
2843 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2844 goto out;
2845 r = 0;
2846 break;
2847 }
9c15bb1d
BP		 2848 case KVM_GET_SUPPORTED_CPUID:
2849 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2850 struct kvm_cpuid2 __user *cpuid_arg = argp;
2851 struct kvm_cpuid2 cpuid;
2852
2853 r = -EFAULT;
2854 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2855 goto out;
9c15bb1d
BP		 2856
2857 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2858 ioctl);
674eea0f
AK		 2859 if (r)
2860 goto out;
2861
2862 r = -EFAULT;
2863 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2864 goto out;
2865 r = 0;
2866 break;
2867 }
890ca9ae
HY		 2868 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2869 u64 mce_cap;
2870
2871 mce_cap = KVM_MCE_CAP_SUPPORTED;
2872 r = -EFAULT;
2873 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2874 goto out;
2875 r = 0;
2876 break;
2877 }
043405e1
CO		 2878 default:
2879 r = -EINVAL;
2880 }
2881out:
2882 return r;
2883}
2884
f5f48ee1
SY		 2885static void wbinvd_ipi(void *garbage)
2886{
2887 wbinvd();
2888}
2889
2890static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2891{
e0f0bbc5 2892 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2893}
2894
313a3dc7
CO		 2895void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2896{
f5f48ee1
SY		 2897 /* Address WBINVD may be executed by guest */
2898 if (need_emulate_wbinvd(vcpu)) {
2899 if (kvm_x86_ops->has_wbinvd_exit())
2900 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2901 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2902 smp_call_function_single(vcpu->cpu,
2903 wbinvd_ipi, NULL, 1);
2904 }
2905
313a3dc7 2906 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2907
0dd6a6ed
ZA		 2908 /* Apply any externally detected TSC adjustments (due to suspend) */
2909 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2910 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2911 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2912 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2913 }
8f6055cb 2914
48434c20 2915 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2916 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2917 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2918 if (tsc_delta < 0)
2919 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2920 if (check_tsc_unstable()) {
b183aa58
ZA		 2921 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2922 vcpu->arch.last_guest_tsc);
2923 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2924 vcpu->arch.tsc_catchup = 1;
c285545f 2925 }
d98d07ca
MT		 2926 /*
2927 * On a host with synchronized TSC, there is no need to update
2928 * kvmclock on vcpu->cpu migration
2929 */
2930 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2931 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2932 if (vcpu->cpu != cpu)
2933 kvm_migrate_timers(vcpu);
e48672fa 2934 vcpu->cpu = cpu;
6b7d7e76 2935 }
c9aaa895
GC		 2936
2937 accumulate_steal_time(vcpu);
2938 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2939}
2940
2941void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2942{
02daab21 2943 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2944 kvm_put_guest_fpu(vcpu);
6f526ec5 2945 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2946}
2947
313a3dc7
CO		 2948static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2949 struct kvm_lapic_state *s)
2950{
5a71785d 2951 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2952 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2953
2954 return 0;
2955}
2956
2957static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2958 struct kvm_lapic_state *s)
2959{
64eb0620 2960 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2961 update_cr8_intercept(vcpu);
313a3dc7
CO		 2962
2963 return 0;
2964}
2965
f77bc6a4
ZX		 2966static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2967 struct kvm_interrupt *irq)
2968{
02cdb50f 2969 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2970 return -EINVAL;
2971 if (irqchip_in_kernel(vcpu->kvm))
2972 return -ENXIO;
f77bc6a4 2973
66fd3f7f 2974 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2975 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2976
f77bc6a4
ZX		 2977 return 0;
2978}
2979
c4abb7c9
JK		 2980static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2981{
c4abb7c9 2982 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2983
2984 return 0;
2985}
2986
b209749f
AK		 2987static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2988 struct kvm_tpr_access_ctl *tac)
2989{
2990 if (tac->flags)
2991 return -EINVAL;
2992 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2993 return 0;
2994}
2995
890ca9ae
HY		 2996static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2997 u64 mcg_cap)
2998{
2999 int r;
3000 unsigned bank_num = mcg_cap & 0xff, bank;
3001
3002 r = -EINVAL;
a9e38c3e 3003 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3004 goto out;
3005 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3006 goto out;
3007 r = 0;
3008 vcpu->arch.mcg_cap = mcg_cap;
3009 /* Init IA32_MCG_CTL to all 1s */
3010 if (mcg_cap & MCG_CTL_P)
3011 vcpu->arch.mcg_ctl = ~(u64)0;
3012 /* Init IA32_MCi_CTL to all 1s */
3013 for (bank = 0; bank < bank_num; bank++)
3014 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3015out:
3016 return r;
3017}
3018
3019static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3020 struct kvm_x86_mce *mce)
3021{
3022 u64 mcg_cap = vcpu->arch.mcg_cap;
3023 unsigned bank_num = mcg_cap & 0xff;
3024 u64 *banks = vcpu->arch.mce_banks;
3025
3026 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3027 return -EINVAL;
3028 /*
3029 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3030 * reporting is disabled
3031 */
3032 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3033 vcpu->arch.mcg_ctl != ~(u64)0)
3034 return 0;
3035 banks += 4 * mce->bank;
3036 /*
3037 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3038 * reporting is disabled for the bank
3039 */
3040 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3041 return 0;
3042 if (mce->status & MCI_STATUS_UC) {
3043 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3044 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3045 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3046 return 0;
3047 }
3048 if (banks[1] & MCI_STATUS_VAL)
3049 mce->status |= MCI_STATUS_OVER;
3050 banks[2] = mce->addr;
3051 banks[3] = mce->misc;
3052 vcpu->arch.mcg_status = mce->mcg_status;
3053 banks[1] = mce->status;
3054 kvm_queue_exception(vcpu, MC_VECTOR);
3055 } else if (!(banks[1] & MCI_STATUS_VAL)
3056 || !(banks[1] & MCI_STATUS_UC)) {
3057 if (banks[1] & MCI_STATUS_VAL)
3058 mce->status |= MCI_STATUS_OVER;
3059 banks[2] = mce->addr;
3060 banks[3] = mce->misc;
3061 banks[1] = mce->status;
3062 } else
3063 banks[1] |= MCI_STATUS_OVER;
3064 return 0;
3065}
3066
3cfc3092
JK		 3067static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3068 struct kvm_vcpu_events *events)
3069{
7460fb4a 3070 process_nmi(vcpu);
03b82a30
JK		 3071 events->exception.injected =
3072 vcpu->arch.exception.pending &&
3073 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3074 events->exception.nr = vcpu->arch.exception.nr;
3075 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3076 events->exception.pad = 0;
3cfc3092
JK		 3077 events->exception.error_code = vcpu->arch.exception.error_code;
3078
03b82a30
JK		 3079 events->interrupt.injected =
3080 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3081 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3082 events->interrupt.soft = 0;
37ccdcbe 3083 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3084
3085 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3086 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3087 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3088 events->nmi.pad = 0;
3cfc3092 3089
66450a21 3090 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3091
dab4b911 3092 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3093 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3094 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3095}
3096
3097static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3098 struct kvm_vcpu_events *events)
3099{
dab4b911 3100 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3101 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3102 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3103 return -EINVAL;
3104
7460fb4a 3105 process_nmi(vcpu);
3cfc3092
JK		 3106 vcpu->arch.exception.pending = events->exception.injected;
3107 vcpu->arch.exception.nr = events->exception.nr;
3108 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3109 vcpu->arch.exception.error_code = events->exception.error_code;
3110
3111 vcpu->arch.interrupt.pending = events->interrupt.injected;
3112 vcpu->arch.interrupt.nr = events->interrupt.nr;
3113 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3114 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3115 kvm_x86_ops->set_interrupt_shadow(vcpu,
3116 events->interrupt.shadow);
3cfc3092
JK		 3117
3118 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3119 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3120 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3121 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3122
66450a21
JK		 3123 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3124 kvm_vcpu_has_lapic(vcpu))
3125 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3126
3842d135
AK		 3127 kvm_make_request(KVM_REQ_EVENT, vcpu);
3128
3cfc3092
JK		 3129 return 0;
3130}
3131
a1efbe77
JK		 3132static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3133 struct kvm_debugregs *dbgregs)
3134{
73aaf249
JK		 3135 unsigned long val;
3136
a1efbe77 3137 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3138 kvm_get_dr(vcpu, 6, &val);
73aaf249 3139 dbgregs->dr6 = val;
a1efbe77
JK		 3140 dbgregs->dr7 = vcpu->arch.dr7;
3141 dbgregs->flags = 0;
97e69aa6 3142 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3143}
3144
3145static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3146 struct kvm_debugregs *dbgregs)
3147{
3148 if (dbgregs->flags)
3149 return -EINVAL;
3150
a1efbe77
JK		 3151 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3152 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3153 kvm_update_dr6(vcpu);
a1efbe77 3154 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3155 kvm_update_dr7(vcpu);
a1efbe77 3156
a1efbe77
JK		 3157 return 0;
3158}
3159
df1daba7
PB		 3160#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3161
3162static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3163{
3164 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3165 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3166 u64 valid;
3167
3168 /*
3169 * Copy legacy XSAVE area, to avoid complications with CPUID
3170 * leaves 0 and 1 in the loop below.
3171 */
3172 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3173
3174 /* Set XSTATE_BV */
3175 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3176
3177 /*
3178 * Copy each region from the possibly compacted offset to the
3179 * non-compacted offset.
3180 */
3181 valid = xstate_bv & ~XSTATE_FPSSE;
3182 while (valid) {
3183 u64 feature = valid & -valid;
3184 int index = fls64(feature) - 1;
3185 void *src = get_xsave_addr(xsave, feature);
3186
3187 if (src) {
3188 u32 size, offset, ecx, edx;
3189 cpuid_count(XSTATE_CPUID, index,
3190 &size, &offset, &ecx, &edx);
3191 memcpy(dest + offset, src, size);
3192 }
3193
3194 valid -= feature;
3195 }
3196}
3197
3198static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3199{
3200 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3201 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3202 u64 valid;
3203
3204 /*
3205 * Copy legacy XSAVE area, to avoid complications with CPUID
3206 * leaves 0 and 1 in the loop below.
3207 */
3208 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3209
3210 /* Set XSTATE_BV and possibly XCOMP_BV. */
3211 xsave->xsave_hdr.xstate_bv = xstate_bv;
3212 if (cpu_has_xsaves)
3213 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3214
3215 /*
3216 * Copy each region from the non-compacted offset to the
3217 * possibly compacted offset.
3218 */
3219 valid = xstate_bv & ~XSTATE_FPSSE;
3220 while (valid) {
3221 u64 feature = valid & -valid;
3222 int index = fls64(feature) - 1;
3223 void *dest = get_xsave_addr(xsave, feature);
3224
3225 if (dest) {
3226 u32 size, offset, ecx, edx;
3227 cpuid_count(XSTATE_CPUID, index,
3228 &size, &offset, &ecx, &edx);
3229 memcpy(dest, src + offset, size);
3230 } else
3231 WARN_ON_ONCE(1);
3232
3233 valid -= feature;
3234 }
3235}
3236
2d5b5a66
SY		 3237static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3238 struct kvm_xsave *guest_xsave)
3239{
4344ee98 3240 if (cpu_has_xsave) {
df1daba7
PB		 3241 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3242 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3243 } else {
2d5b5a66
SY		 3244 memcpy(guest_xsave->region,
3245 &vcpu->arch.guest_fpu.state->fxsave,
3246 sizeof(struct i387_fxsave_struct));
3247 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3248 XSTATE_FPSSE;
3249 }
3250}
3251
3252static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3253 struct kvm_xsave *guest_xsave)
3254{
3255 u64 xstate_bv =
3256 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3257
d7876f1b
PB		 3258 if (cpu_has_xsave) {
3259 /*
3260 * Here we allow setting states that are not present in
3261 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3262 * with old userspace.
3263 */
4ff41732 3264 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3265 return -EINVAL;
df1daba7 3266 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3267 } else {
2d5b5a66
SY		 3268 if (xstate_bv & ~XSTATE_FPSSE)
3269 return -EINVAL;
3270 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3271 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3272 }
3273 return 0;
3274}
3275
3276static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3277 struct kvm_xcrs *guest_xcrs)
3278{
3279 if (!cpu_has_xsave) {
3280 guest_xcrs->nr_xcrs = 0;
3281 return;
3282 }
3283
3284 guest_xcrs->nr_xcrs = 1;
3285 guest_xcrs->flags = 0;
3286 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3287 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3288}
3289
3290static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3291 struct kvm_xcrs *guest_xcrs)
3292{
3293 int i, r = 0;
3294
3295 if (!cpu_has_xsave)
3296 return -EINVAL;
3297
3298 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3299 return -EINVAL;
3300
3301 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3302 /* Only support XCR0 currently */
c67a04cb 3303 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3304 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3305 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3306 break;
3307 }
3308 if (r)
3309 r = -EINVAL;
3310 return r;
3311}
3312
1c0b28c2
EM		 3313/*
3314 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3315 * stopped by the hypervisor. This function will be called from the host only.
3316 * EINVAL is returned when the host attempts to set the flag for a guest that
3317 * does not support pv clocks.
3318 */
3319static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3320{
0b79459b 3321 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3322 return -EINVAL;
51d59c6b 3323 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3324 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3325 return 0;
3326}
3327
313a3dc7
CO		 3328long kvm_arch_vcpu_ioctl(struct file *filp,
3329 unsigned int ioctl, unsigned long arg)
3330{
3331 struct kvm_vcpu *vcpu = filp->private_data;
3332 void __user *argp = (void __user *)arg;
3333 int r;
d1ac91d8
AK		 3334 union {
3335 struct kvm_lapic_state *lapic;
3336 struct kvm_xsave *xsave;
3337 struct kvm_xcrs *xcrs;
3338 void *buffer;
3339 } u;
3340
3341 u.buffer = NULL;
313a3dc7
CO		 3342 switch (ioctl) {
3343 case KVM_GET_LAPIC: {
2204ae3c
MT		 3344 r = -EINVAL;
3345 if (!vcpu->arch.apic)
3346 goto out;
d1ac91d8 3347 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3348
b772ff36 3349 r = -ENOMEM;
d1ac91d8 3350 if (!u.lapic)
b772ff36 3351 goto out;
d1ac91d8 3352 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3353 if (r)
3354 goto out;
3355 r = -EFAULT;
d1ac91d8 3356 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3357 goto out;
3358 r = 0;
3359 break;
3360 }
3361 case KVM_SET_LAPIC: {
2204ae3c
MT		 3362 r = -EINVAL;
3363 if (!vcpu->arch.apic)
3364 goto out;
ff5c2c03 3365 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3366 if (IS_ERR(u.lapic))
3367 return PTR_ERR(u.lapic);
ff5c2c03 3368
d1ac91d8 3369 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3370 break;
3371 }
f77bc6a4
ZX		 3372 case KVM_INTERRUPT: {
3373 struct kvm_interrupt irq;
3374
3375 r = -EFAULT;
3376 if (copy_from_user(&irq, argp, sizeof irq))
3377 goto out;
3378 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3379 break;
3380 }
c4abb7c9
JK		 3381 case KVM_NMI: {
3382 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3383 break;
3384 }
313a3dc7
CO		 3385 case KVM_SET_CPUID: {
3386 struct kvm_cpuid __user *cpuid_arg = argp;
3387 struct kvm_cpuid cpuid;
3388
3389 r = -EFAULT;
3390 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3391 goto out;
3392 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3393 break;
3394 }
07716717
DK		 3395 case KVM_SET_CPUID2: {
3396 struct kvm_cpuid2 __user *cpuid_arg = argp;
3397 struct kvm_cpuid2 cpuid;
3398
3399 r = -EFAULT;
3400 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3401 goto out;
3402 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3403 cpuid_arg->entries);
07716717
DK		 3404 break;
3405 }
3406 case KVM_GET_CPUID2: {
3407 struct kvm_cpuid2 __user *cpuid_arg = argp;
3408 struct kvm_cpuid2 cpuid;
3409
3410 r = -EFAULT;
3411 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3412 goto out;
3413 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3414 cpuid_arg->entries);
07716717
DK		 3415 if (r)
3416 goto out;
3417 r = -EFAULT;
3418 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3419 goto out;
3420 r = 0;
3421 break;
3422 }
313a3dc7
CO		 3423 case KVM_GET_MSRS:
3424 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3425 break;
3426 case KVM_SET_MSRS:
3427 r = msr_io(vcpu, argp, do_set_msr, 0);
3428 break;
b209749f
AK		 3429 case KVM_TPR_ACCESS_REPORTING: {
3430 struct kvm_tpr_access_ctl tac;
3431
3432 r = -EFAULT;
3433 if (copy_from_user(&tac, argp, sizeof tac))
3434 goto out;
3435 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3436 if (r)
3437 goto out;
3438 r = -EFAULT;
3439 if (copy_to_user(argp, &tac, sizeof tac))
3440 goto out;
3441 r = 0;
3442 break;
3443 };
b93463aa
AK		 3444 case KVM_SET_VAPIC_ADDR: {
3445 struct kvm_vapic_addr va;
3446
3447 r = -EINVAL;
3448 if (!irqchip_in_kernel(vcpu->kvm))
3449 goto out;
3450 r = -EFAULT;
3451 if (copy_from_user(&va, argp, sizeof va))
3452 goto out;
fda4e2e8 3453 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3454 break;
3455 }
890ca9ae
HY		 3456 case KVM_X86_SETUP_MCE: {
3457 u64 mcg_cap;
3458
3459 r = -EFAULT;
3460 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3461 goto out;
3462 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3463 break;
3464 }
3465 case KVM_X86_SET_MCE: {
3466 struct kvm_x86_mce mce;
3467
3468 r = -EFAULT;
3469 if (copy_from_user(&mce, argp, sizeof mce))
3470 goto out;
3471 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3472 break;
3473 }
3cfc3092
JK		 3474 case KVM_GET_VCPU_EVENTS: {
3475 struct kvm_vcpu_events events;
3476
3477 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3478
3479 r = -EFAULT;
3480 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3481 break;
3482 r = 0;
3483 break;
3484 }
3485 case KVM_SET_VCPU_EVENTS: {
3486 struct kvm_vcpu_events events;
3487
3488 r = -EFAULT;
3489 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3490 break;
3491
3492 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3493 break;
3494 }
a1efbe77
JK		 3495 case KVM_GET_DEBUGREGS: {
3496 struct kvm_debugregs dbgregs;
3497
3498 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3499
3500 r = -EFAULT;
3501 if (copy_to_user(argp, &dbgregs,
3502 sizeof(struct kvm_debugregs)))
3503 break;
3504 r = 0;
3505 break;
3506 }
3507 case KVM_SET_DEBUGREGS: {
3508 struct kvm_debugregs dbgregs;
3509
3510 r = -EFAULT;
3511 if (copy_from_user(&dbgregs, argp,
3512 sizeof(struct kvm_debugregs)))
3513 break;
3514
3515 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3516 break;
3517 }
2d5b5a66 3518 case KVM_GET_XSAVE: {
d1ac91d8 3519 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3520 r = -ENOMEM;
d1ac91d8 3521 if (!u.xsave)
2d5b5a66
SY		 3522 break;
3523
d1ac91d8 3524 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3525
3526 r = -EFAULT;
d1ac91d8 3527 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3528 break;
3529 r = 0;
3530 break;
3531 }
3532 case KVM_SET_XSAVE: {
ff5c2c03 3533 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3534 if (IS_ERR(u.xsave))
3535 return PTR_ERR(u.xsave);
2d5b5a66 3536
d1ac91d8 3537 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3538 break;
3539 }
3540 case KVM_GET_XCRS: {
d1ac91d8 3541 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3542 r = -ENOMEM;
d1ac91d8 3543 if (!u.xcrs)
2d5b5a66
SY		 3544 break;
3545
d1ac91d8 3546 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3547
3548 r = -EFAULT;
d1ac91d8 3549 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3550 sizeof(struct kvm_xcrs)))
3551 break;
3552 r = 0;
3553 break;
3554 }
3555 case KVM_SET_XCRS: {
ff5c2c03 3556 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3557 if (IS_ERR(u.xcrs))
3558 return PTR_ERR(u.xcrs);
2d5b5a66 3559
d1ac91d8 3560 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3561 break;
3562 }
92a1f12d
JR		 3563 case KVM_SET_TSC_KHZ: {
3564 u32 user_tsc_khz;
3565
3566 r = -EINVAL;
92a1f12d
JR		 3567 user_tsc_khz = (u32)arg;
3568
3569 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3570 goto out;
3571
cc578287
ZA		 3572 if (user_tsc_khz == 0)
3573 user_tsc_khz = tsc_khz;
3574
3575 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3576
3577 r = 0;
3578 goto out;
3579 }
3580 case KVM_GET_TSC_KHZ: {
cc578287 3581 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3582 goto out;
3583 }
1c0b28c2
EM		 3584 case KVM_KVMCLOCK_CTRL: {
3585 r = kvm_set_guest_paused(vcpu);
3586 goto out;
3587 }
313a3dc7
CO		 3588 default:
3589 r = -EINVAL;
3590 }
3591out:
d1ac91d8 3592 kfree(u.buffer);
313a3dc7
CO		 3593 return r;
3594}
3595
5b1c1493
CO		 3596int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3597{
3598 return VM_FAULT_SIGBUS;
3599}
3600
1fe779f8
CO		 3601static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3602{
3603 int ret;
3604
3605 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3606 return -EINVAL;
1fe779f8
CO		 3607 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3608 return ret;
3609}
3610
b927a3ce
SY		 3611static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3612 u64 ident_addr)
3613{
3614 kvm->arch.ept_identity_map_addr = ident_addr;
3615 return 0;
3616}
3617
1fe779f8
CO		 3618static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3619 u32 kvm_nr_mmu_pages)
3620{
3621 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3622 return -EINVAL;
3623
79fac95e 3624 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3625
3626 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3627 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3628
79fac95e 3629 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3630 return 0;
3631}
3632
3633static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3634{
39de71ec 3635 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3636}
3637
1fe779f8
CO		 3638static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3639{
3640 int r;
3641
3642 r = 0;
3643 switch (chip->chip_id) {
3644 case KVM_IRQCHIP_PIC_MASTER:
3645 memcpy(&chip->chip.pic,
3646 &pic_irqchip(kvm)->pics[0],
3647 sizeof(struct kvm_pic_state));
3648 break;
3649 case KVM_IRQCHIP_PIC_SLAVE:
3650 memcpy(&chip->chip.pic,
3651 &pic_irqchip(kvm)->pics[1],
3652 sizeof(struct kvm_pic_state));
3653 break;
3654 case KVM_IRQCHIP_IOAPIC:
eba0226b 3655 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3656 break;
3657 default:
3658 r = -EINVAL;
3659 break;
3660 }
3661 return r;
3662}
3663
3664static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3665{
3666 int r;
3667
3668 r = 0;
3669 switch (chip->chip_id) {
3670 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3671 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3672 memcpy(&pic_irqchip(kvm)->pics[0],
3673 &chip->chip.pic,
3674 sizeof(struct kvm_pic_state));
f4f51050 3675 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3676 break;
3677 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3678 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3679 memcpy(&pic_irqchip(kvm)->pics[1],
3680 &chip->chip.pic,
3681 sizeof(struct kvm_pic_state));
f4f51050 3682 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3683 break;
3684 case KVM_IRQCHIP_IOAPIC:
eba0226b 3685 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3686 break;
3687 default:
3688 r = -EINVAL;
3689 break;
3690 }
3691 kvm_pic_update_irq(pic_irqchip(kvm));
3692 return r;
3693}
3694
e0f63cb9
SY		 3695static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3696{
3697 int r = 0;
3698
894a9c55 3699 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3700 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3701 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3702 return r;
3703}
3704
3705static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3706{
3707 int r = 0;
3708
894a9c55 3709 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3710 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3711 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3712 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3713 return r;
3714}
3715
3716static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3717{
3718 int r = 0;
3719
3720 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3721 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3722 sizeof(ps->channels));
3723 ps->flags = kvm->arch.vpit->pit_state.flags;
3724 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3725 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3726 return r;
3727}
3728
3729static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3730{
3731 int r = 0, start = 0;
3732 u32 prev_legacy, cur_legacy;
3733 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3734 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3735 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3736 if (!prev_legacy && cur_legacy)
3737 start = 1;
3738 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3739 sizeof(kvm->arch.vpit->pit_state.channels));
3740 kvm->arch.vpit->pit_state.flags = ps->flags;
3741 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3742 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3743 return r;
3744}
3745
52d939a0
MT		 3746static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3747 struct kvm_reinject_control *control)
3748{
3749 if (!kvm->arch.vpit)
3750 return -ENXIO;
894a9c55 3751 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3752 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3753 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3754 return 0;
3755}
3756
95d4c16c 3757/**
60c34612
TY		 3758 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3759 * @kvm: kvm instance
3760 * @log: slot id and address to which we copy the log
95d4c16c 3761 *
e108ff2f
PB		 3762 * Steps 1-4 below provide general overview of dirty page logging. See
3763 * kvm_get_dirty_log_protect() function description for additional details.
3764 *
3765 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3766 * always flush the TLB (step 4) even if previous step failed and the dirty
3767 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3768 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3769 * writes will be marked dirty for next log read.
95d4c16c 3770 *
60c34612
TY		 3771 * 1. Take a snapshot of the bit and clear it if needed.
3772 * 2. Write protect the corresponding page.
e108ff2f
PB		 3773 * 3. Copy the snapshot to the userspace.
3774 * 4. Flush TLB's if needed.
5bb064dc 3775 */
60c34612 3776int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3777{
60c34612 3778 bool is_dirty = false;
e108ff2f 3779 int r;
5bb064dc 3780
79fac95e 3781 mutex_lock(&kvm->slots_lock);
5bb064dc 3782
e108ff2f 3783 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3784
3785 /*
3786 * All the TLBs can be flushed out of mmu lock, see the comments in
3787 * kvm_mmu_slot_remove_write_access().
3788 */
e108ff2f 3789 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3790 if (is_dirty)
3791 kvm_flush_remote_tlbs(kvm);
3792
79fac95e 3793 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3794 return r;
3795}
3796
aa2fbe6d
YZ		 3797int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3798 bool line_status)
23d43cf9
CD		 3799{
3800 if (!irqchip_in_kernel(kvm))
3801 return -ENXIO;
3802
3803 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3804 irq_event->irq, irq_event->level,
3805 line_status);
23d43cf9
CD		 3806 return 0;
3807}
3808
1fe779f8
CO		 3809long kvm_arch_vm_ioctl(struct file *filp,
3810 unsigned int ioctl, unsigned long arg)
3811{
3812 struct kvm *kvm = filp->private_data;
3813 void __user *argp = (void __user *)arg;
367e1319 3814 int r = -ENOTTY;
f0d66275
DH		 3815 /*
3816 * This union makes it completely explicit to gcc-3.x
3817 * that these two variables' stack usage should be
3818 * combined, not added together.
3819 */
3820 union {
3821 struct kvm_pit_state ps;
e9f42757 3822 struct kvm_pit_state2 ps2;
c5ff41ce 3823 struct kvm_pit_config pit_config;
f0d66275 3824 } u;
1fe779f8
CO		 3825
3826 switch (ioctl) {
3827 case KVM_SET_TSS_ADDR:
3828 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3829 break;
b927a3ce
SY		 3830 case KVM_SET_IDENTITY_MAP_ADDR: {
3831 u64 ident_addr;
3832
3833 r = -EFAULT;
3834 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3835 goto out;
3836 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3837 break;
3838 }
1fe779f8
CO		 3839 case KVM_SET_NR_MMU_PAGES:
3840 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3841 break;
3842 case KVM_GET_NR_MMU_PAGES:
3843 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3844 break;
3ddea128
MT		 3845 case KVM_CREATE_IRQCHIP: {
3846 struct kvm_pic *vpic;
3847
3848 mutex_lock(&kvm->lock);
3849 r = -EEXIST;
3850 if (kvm->arch.vpic)
3851 goto create_irqchip_unlock;
3e515705
AK		 3852 r = -EINVAL;
3853 if (atomic_read(&kvm->online_vcpus))
3854 goto create_irqchip_unlock;
1fe779f8 3855 r = -ENOMEM;
3ddea128
MT		 3856 vpic = kvm_create_pic(kvm);
3857 if (vpic) {
1fe779f8
CO		 3858 r = kvm_ioapic_init(kvm);
3859 if (r) {
175504cd 3860 mutex_lock(&kvm->slots_lock);
72bb2fcd 3861 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3862 &vpic->dev_master);
3863 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3864 &vpic->dev_slave);
3865 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3866 &vpic->dev_eclr);
175504cd 3867 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3868 kfree(vpic);
3869 goto create_irqchip_unlock;
1fe779f8
CO		 3870 }
3871 } else
3ddea128
MT		 3872 goto create_irqchip_unlock;
3873 smp_wmb();
3874 kvm->arch.vpic = vpic;
3875 smp_wmb();
399ec807
AK		 3876 r = kvm_setup_default_irq_routing(kvm);
3877 if (r) {
175504cd 3878 mutex_lock(&kvm->slots_lock);
3ddea128 3879 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3880 kvm_ioapic_destroy(kvm);
3881 kvm_destroy_pic(kvm);
3ddea128 3882 mutex_unlock(&kvm->irq_lock);
175504cd 3883 mutex_unlock(&kvm->slots_lock);
399ec807 3884 }
3ddea128
MT		 3885 create_irqchip_unlock:
3886 mutex_unlock(&kvm->lock);
1fe779f8 3887 break;
3ddea128 3888 }
7837699f 3889 case KVM_CREATE_PIT:
c5ff41ce
JK		 3890 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3891 goto create_pit;
3892 case KVM_CREATE_PIT2:
3893 r = -EFAULT;
3894 if (copy_from_user(&u.pit_config, argp,
3895 sizeof(struct kvm_pit_config)))
3896 goto out;
3897 create_pit:
79fac95e 3898 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3899 r = -EEXIST;
3900 if (kvm->arch.vpit)
3901 goto create_pit_unlock;
7837699f 3902 r = -ENOMEM;
c5ff41ce 3903 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3904 if (kvm->arch.vpit)
3905 r = 0;
269e05e4 3906 create_pit_unlock:
79fac95e 3907 mutex_unlock(&kvm->slots_lock);
7837699f 3908 break;
1fe779f8
CO		 3909 case KVM_GET_IRQCHIP: {
3910 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3911 struct kvm_irqchip *chip;
1fe779f8 3912
ff5c2c03
SL		 3913 chip = memdup_user(argp, sizeof(*chip));
3914 if (IS_ERR(chip)) {
3915 r = PTR_ERR(chip);
1fe779f8 3916 goto out;
ff5c2c03
SL		 3917 }
3918
1fe779f8
CO		 3919 r = -ENXIO;
3920 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3921 goto get_irqchip_out;
3922 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3923 if (r)
f0d66275 3924 goto get_irqchip_out;
1fe779f8 3925 r = -EFAULT;
f0d66275
DH		 3926 if (copy_to_user(argp, chip, sizeof *chip))
3927 goto get_irqchip_out;
1fe779f8 3928 r = 0;
f0d66275
DH		 3929 get_irqchip_out:
3930 kfree(chip);
1fe779f8
CO		 3931 break;
3932 }
3933 case KVM_SET_IRQCHIP: {
3934 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3935 struct kvm_irqchip *chip;
1fe779f8 3936
ff5c2c03
SL		 3937 chip = memdup_user(argp, sizeof(*chip));
3938 if (IS_ERR(chip)) {
3939 r = PTR_ERR(chip);
1fe779f8 3940 goto out;
ff5c2c03
SL		 3941 }
3942
1fe779f8
CO		 3943 r = -ENXIO;
3944 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3945 goto set_irqchip_out;
3946 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3947 if (r)
f0d66275 3948 goto set_irqchip_out;
1fe779f8 3949 r = 0;
f0d66275
DH		 3950 set_irqchip_out:
3951 kfree(chip);
1fe779f8
CO		 3952 break;
3953 }
e0f63cb9 3954 case KVM_GET_PIT: {
e0f63cb9 3955 r = -EFAULT;
f0d66275 3956 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3957 goto out;
3958 r = -ENXIO;
3959 if (!kvm->arch.vpit)
3960 goto out;
f0d66275 3961 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3962 if (r)
3963 goto out;
3964 r = -EFAULT;
f0d66275 3965 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3966 goto out;
3967 r = 0;
3968 break;
3969 }
3970 case KVM_SET_PIT: {
e0f63cb9 3971 r = -EFAULT;
f0d66275 3972 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3973 goto out;
3974 r = -ENXIO;
3975 if (!kvm->arch.vpit)
3976 goto out;
f0d66275 3977 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3978 break;
3979 }
e9f42757
BK		 3980 case KVM_GET_PIT2: {
3981 r = -ENXIO;
3982 if (!kvm->arch.vpit)
3983 goto out;
3984 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3985 if (r)
3986 goto out;
3987 r = -EFAULT;
3988 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3989 goto out;
3990 r = 0;
3991 break;
3992 }
3993 case KVM_SET_PIT2: {
3994 r = -EFAULT;
3995 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3996 goto out;
3997 r = -ENXIO;
3998 if (!kvm->arch.vpit)
3999 goto out;
4000 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4001 break;
4002 }
52d939a0
MT		 4003 case KVM_REINJECT_CONTROL: {
4004 struct kvm_reinject_control control;
4005 r = -EFAULT;
4006 if (copy_from_user(&control, argp, sizeof(control)))
4007 goto out;
4008 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4009 break;
4010 }
ffde22ac
ES		 4011 case KVM_XEN_HVM_CONFIG: {
4012 r = -EFAULT;
4013 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4014 sizeof(struct kvm_xen_hvm_config)))
4015 goto out;
4016 r = -EINVAL;
4017 if (kvm->arch.xen_hvm_config.flags)
4018 goto out;
4019 r = 0;
4020 break;
4021 }
afbcf7ab 4022 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4023 struct kvm_clock_data user_ns;
4024 u64 now_ns;
4025 s64 delta;
4026
4027 r = -EFAULT;
4028 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4029 goto out;
4030
4031 r = -EINVAL;
4032 if (user_ns.flags)
4033 goto out;
4034
4035 r = 0;
395c6b0a 4036 local_irq_disable();
759379dd 4037 now_ns = get_kernel_ns();
afbcf7ab 4038 delta = user_ns.clock - now_ns;
395c6b0a 4039 local_irq_enable();
afbcf7ab 4040 kvm->arch.kvmclock_offset = delta;
2e762ff7 4041 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4042 break;
4043 }
4044 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4045 struct kvm_clock_data user_ns;
4046 u64 now_ns;
4047
395c6b0a 4048 local_irq_disable();
759379dd 4049 now_ns = get_kernel_ns();
afbcf7ab 4050 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4051 local_irq_enable();
afbcf7ab 4052 user_ns.flags = 0;
97e69aa6 4053 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4054
4055 r = -EFAULT;
4056 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4057 goto out;
4058 r = 0;
4059 break;
4060 }
4061
1fe779f8 4062 default:
c274e03a 4063 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4064 }
4065out:
4066 return r;
4067}
4068
a16b043c 4069static void kvm_init_msr_list(void)
043405e1
CO		 4070{
4071 u32 dummy[2];
4072 unsigned i, j;
4073
e3267cbb
GC		 4074 /* skip the first msrs in the list. KVM-specific */
4075 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4076 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4077 continue;
93c4adc7
PB		 4078
4079 /*
4080 * Even MSRs that are valid in the host may not be exposed
4081 * to the guests in some cases. We could work around this
4082 * in VMX with the generic MSR save/load machinery, but it
4083 * is not really worthwhile since it will really only
4084 * happen with nested virtualization.
4085 */
4086 switch (msrs_to_save[i]) {
4087 case MSR_IA32_BNDCFGS:
4088 if (!kvm_x86_ops->mpx_supported())
4089 continue;
4090 break;
4091 default:
4092 break;
4093 }
4094
043405e1
CO		 4095 if (j < i)
4096 msrs_to_save[j] = msrs_to_save[i];
4097 j++;
4098 }
4099 num_msrs_to_save = j;
4100}
4101
bda9020e
MT		 4102static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4103 const void *v)
bbd9b64e 4104{
70252a10
AK		 4105 int handled = 0;
4106 int n;
4107
4108 do {
4109 n = min(len, 8);
4110 if (!(vcpu->arch.apic &&
4111 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4112 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4113 break;
4114 handled += n;
4115 addr += n;
4116 len -= n;
4117 v += n;
4118 } while (len);
bbd9b64e 4119
70252a10 4120 return handled;
bbd9b64e
CO		 4121}
4122
bda9020e 4123static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4124{
70252a10
AK		 4125 int handled = 0;
4126 int n;
4127
4128 do {
4129 n = min(len, 8);
4130 if (!(vcpu->arch.apic &&
4131 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4132 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4133 break;
4134 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4135 handled += n;
4136 addr += n;
4137 len -= n;
4138 v += n;
4139 } while (len);
bbd9b64e 4140
70252a10 4141 return handled;
bbd9b64e
CO		 4142}
4143
2dafc6c2
GN		 4144static void kvm_set_segment(struct kvm_vcpu *vcpu,
4145 struct kvm_segment *var, int seg)
4146{
4147 kvm_x86_ops->set_segment(vcpu, var, seg);
4148}
4149
4150void kvm_get_segment(struct kvm_vcpu *vcpu,
4151 struct kvm_segment *var, int seg)
4152{
4153 kvm_x86_ops->get_segment(vcpu, var, seg);
4154}
4155
54987b7a
PB		 4156gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4157 struct x86_exception *exception)
02f59dc9
JR		 4158{
4159 gpa_t t_gpa;
02f59dc9
JR		 4160
4161 BUG_ON(!mmu_is_nested(vcpu));
4162
4163 /* NPT walks are always user-walks */
4164 access |= PFERR_USER_MASK;
54987b7a 4165 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4166
4167 return t_gpa;
4168}
4169
ab9ae313
AK		 4170gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4171 struct x86_exception *exception)
1871c602
GN		 4172{
4173 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4174 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4175}
4176
ab9ae313
AK		 4177 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4178 struct x86_exception *exception)
1871c602
GN		 4179{
4180 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4181 access |= PFERR_FETCH_MASK;
ab9ae313 4182 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4183}
4184
ab9ae313
AK		 4185gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4186 struct x86_exception *exception)
1871c602
GN		 4187{
4188 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4189 access |= PFERR_WRITE_MASK;
ab9ae313 4190 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4191}
4192
4193/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4194gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4195 struct x86_exception *exception)
1871c602 4196{
ab9ae313 4197 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4198}
4199
4200static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4201 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4202 struct x86_exception *exception)
bbd9b64e
CO		 4203{
4204 void *data = val;
10589a46 4205 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4206
4207 while (bytes) {
14dfe855 4208 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4209 exception);
bbd9b64e 4210 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4211 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4212 int ret;
4213
bcc55cba 4214 if (gpa == UNMAPPED_GVA)
ab9ae313 4215 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4216 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4217 offset, toread);
10589a46 4218 if (ret < 0) {
c3cd7ffa 4219 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4220 goto out;
4221 }
bbd9b64e 4222
77c2002e
IE		 4223 bytes -= toread;
4224 data += toread;
4225 addr += toread;
bbd9b64e 4226 }
10589a46 4227out:
10589a46 4228 return r;
bbd9b64e 4229}
77c2002e 4230
1871c602 4231/* used for instruction fetching */
0f65dd70
AK		 4232static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4233 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4234 struct x86_exception *exception)
1871c602 4235{
0f65dd70 4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4237 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4238 unsigned offset;
4239 int ret;
0f65dd70 4240
44583cba
PB		 4241 /* Inline kvm_read_guest_virt_helper for speed. */
4242 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4243 exception);
4244 if (unlikely(gpa == UNMAPPED_GVA))
4245 return X86EMUL_PROPAGATE_FAULT;
4246
4247 offset = addr & (PAGE_SIZE-1);
4248 if (WARN_ON(offset + bytes > PAGE_SIZE))
4249 bytes = (unsigned)PAGE_SIZE - offset;
4250 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4251 offset, bytes);
4252 if (unlikely(ret < 0))
4253 return X86EMUL_IO_NEEDED;
4254
4255 return X86EMUL_CONTINUE;
1871c602
GN		 4256}
4257
064aea77 4258int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4259 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4260 struct x86_exception *exception)
1871c602 4261{
0f65dd70 4262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4263 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4264
1871c602 4265 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4266 exception);
1871c602 4267}
064aea77 4268EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4269
0f65dd70
AK		 4270static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4271 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4272 struct x86_exception *exception)
1871c602 4273{
0f65dd70 4274 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4275 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4276}
4277
6a4d7550 4278int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4279 gva_t addr, void *val,
2dafc6c2 4280 unsigned int bytes,
bcc55cba 4281 struct x86_exception *exception)
77c2002e 4282{
0f65dd70 4283 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4284 void *data = val;
4285 int r = X86EMUL_CONTINUE;
4286
4287 while (bytes) {
14dfe855
JR		 4288 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4289 PFERR_WRITE_MASK,
ab9ae313 4290 exception);
77c2002e
IE		 4291 unsigned offset = addr & (PAGE_SIZE-1);
4292 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4293 int ret;
4294
bcc55cba 4295 if (gpa == UNMAPPED_GVA)
ab9ae313 4296 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4297 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4298 if (ret < 0) {
c3cd7ffa 4299 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4300 goto out;
4301 }
4302
4303 bytes -= towrite;
4304 data += towrite;
4305 addr += towrite;
4306 }
4307out:
4308 return r;
4309}
6a4d7550 4310EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4311
af7cc7d1
XG		 4312static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4313 gpa_t *gpa, struct x86_exception *exception,
4314 bool write)
4315{
97d64b78
AK		 4316 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4317 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4318
97d64b78 4319 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4320 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4321 vcpu->arch.access, access)) {
bebb106a
XG		 4322 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4323 (gva & (PAGE_SIZE - 1));
4f022648 4324 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4325 return 1;
4326 }
4327
af7cc7d1
XG		 4328 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4329
4330 if (*gpa == UNMAPPED_GVA)
4331 return -1;
4332
4333 /* For APIC access vmexit */
4334 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4335 return 1;
4336
4f022648
XG		 4337 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4338 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4339 return 1;
4f022648 4340 }
bebb106a 4341
af7cc7d1
XG		 4342 return 0;
4343}
4344
3200f405 4345int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4346 const void *val, int bytes)
bbd9b64e
CO		 4347{
4348 int ret;
4349
4350 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4351 if (ret < 0)
bbd9b64e 4352 return 0;
f57f2ef5 4353 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4354 return 1;
4355}
4356
77d197b2
XG		 4357struct read_write_emulator_ops {
4358 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4359 int bytes);
4360 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4361 void *val, int bytes);
4362 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4363 int bytes, void *val);
4364 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4365 void *val, int bytes);
4366 bool write;
4367};
4368
4369static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4370{
4371 if (vcpu->mmio_read_completed) {
77d197b2 4372 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4373 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4374 vcpu->mmio_read_completed = 0;
4375 return 1;
4376 }
4377
4378 return 0;
4379}
4380
4381static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4382 void *val, int bytes)
4383{
4384 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4385}
4386
4387static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4388 void *val, int bytes)
4389{
4390 return emulator_write_phys(vcpu, gpa, val, bytes);
4391}
4392
4393static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4394{
4395 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4396 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4397}
4398
4399static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4400 void *val, int bytes)
4401{
4402 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4403 return X86EMUL_IO_NEEDED;
4404}
4405
4406static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4407 void *val, int bytes)
4408{
f78146b0
AK		 4409 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4410
87da7e66 4411 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4412 return X86EMUL_CONTINUE;
4413}
4414
0fbe9b0b 4415static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4416 .read_write_prepare = read_prepare,
4417 .read_write_emulate = read_emulate,
4418 .read_write_mmio = vcpu_mmio_read,
4419 .read_write_exit_mmio = read_exit_mmio,
4420};
4421
0fbe9b0b 4422static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4423 .read_write_emulate = write_emulate,
4424 .read_write_mmio = write_mmio,
4425 .read_write_exit_mmio = write_exit_mmio,
4426 .write = true,
4427};
4428
22388a3c
XG		 4429static int emulator_read_write_onepage(unsigned long addr, void *val,
4430 unsigned int bytes,
4431 struct x86_exception *exception,
4432 struct kvm_vcpu *vcpu,
0fbe9b0b 4433 const struct read_write_emulator_ops *ops)
bbd9b64e 4434{
af7cc7d1
XG		 4435 gpa_t gpa;
4436 int handled, ret;
22388a3c 4437 bool write = ops->write;
f78146b0 4438 struct kvm_mmio_fragment *frag;
10589a46 4439
22388a3c 4440 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4441
af7cc7d1 4442 if (ret < 0)
bbd9b64e 4443 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4444
4445 /* For APIC access vmexit */
af7cc7d1 4446 if (ret)
bbd9b64e
CO		 4447 goto mmio;
4448
22388a3c 4449 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4450 return X86EMUL_CONTINUE;
4451
4452mmio:
4453 /*
4454 * Is this MMIO handled locally?
4455 */
22388a3c 4456 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4457 if (handled == bytes)
bbd9b64e 4458 return X86EMUL_CONTINUE;
bbd9b64e 4459
70252a10
AK		 4460 gpa += handled;
4461 bytes -= handled;
4462 val += handled;
4463
87da7e66
XG		 4464 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4465 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4466 frag->gpa = gpa;
4467 frag->data = val;
4468 frag->len = bytes;
f78146b0 4469 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4470}
4471
22388a3c
XG		 4472int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4473 void *val, unsigned int bytes,
4474 struct x86_exception *exception,
0fbe9b0b 4475 const struct read_write_emulator_ops *ops)
bbd9b64e 4476{
0f65dd70 4477 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4478 gpa_t gpa;
4479 int rc;
4480
4481 if (ops->read_write_prepare &&
4482 ops->read_write_prepare(vcpu, val, bytes))
4483 return X86EMUL_CONTINUE;
4484
4485 vcpu->mmio_nr_fragments = 0;
0f65dd70 4486
bbd9b64e
CO		 4487 /* Crossing a page boundary? */
4488 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4489 int now;
bbd9b64e
CO		 4490
4491 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4492 rc = emulator_read_write_onepage(addr, val, now, exception,
4493 vcpu, ops);
4494
bbd9b64e
CO		 4495 if (rc != X86EMUL_CONTINUE)
4496 return rc;
4497 addr += now;
4498 val += now;
4499 bytes -= now;
4500 }
22388a3c 4501
f78146b0
AK		 4502 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4503 vcpu, ops);
4504 if (rc != X86EMUL_CONTINUE)
4505 return rc;
4506
4507 if (!vcpu->mmio_nr_fragments)
4508 return rc;
4509
4510 gpa = vcpu->mmio_fragments[0].gpa;
4511
4512 vcpu->mmio_needed = 1;
4513 vcpu->mmio_cur_fragment = 0;
4514
87da7e66 4515 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4516 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4517 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4518 vcpu->run->mmio.phys_addr = gpa;
4519
4520 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4521}
4522
4523static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4524 unsigned long addr,
4525 void *val,
4526 unsigned int bytes,
4527 struct x86_exception *exception)
4528{
4529 return emulator_read_write(ctxt, addr, val, bytes,
4530 exception, &read_emultor);
4531}
4532
4533int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4534 unsigned long addr,
4535 const void *val,
4536 unsigned int bytes,
4537 struct x86_exception *exception)
4538{
4539 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4540 exception, &write_emultor);
bbd9b64e 4541}
bbd9b64e 4542
daea3e73
AK		 4543#define CMPXCHG_TYPE(t, ptr, old, new) \
4544 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4545
4546#ifdef CONFIG_X86_64
4547# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4548#else
4549# define CMPXCHG64(ptr, old, new) \
9749a6c0 4550 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4551#endif
4552
0f65dd70
AK		 4553static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4554 unsigned long addr,
bbd9b64e
CO		 4555 const void *old,
4556 const void *new,
4557 unsigned int bytes,
0f65dd70 4558 struct x86_exception *exception)
bbd9b64e 4559{
0f65dd70 4560 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4561 gpa_t gpa;
4562 struct page *page;
4563 char *kaddr;
4564 bool exchanged;
2bacc55c 4565
daea3e73
AK		 4566 /* guests cmpxchg8b have to be emulated atomically */
4567 if (bytes > 8 || (bytes & (bytes - 1)))
4568 goto emul_write;
10589a46 4569
daea3e73 4570 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4571
daea3e73
AK		 4572 if (gpa == UNMAPPED_GVA ||
4573 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4574 goto emul_write;
2bacc55c 4575
daea3e73
AK		 4576 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4577 goto emul_write;
72dc67a6 4578
daea3e73 4579 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4580 if (is_error_page(page))
c19b8bd6 4581 goto emul_write;
72dc67a6 4582
8fd75e12 4583 kaddr = kmap_atomic(page);
daea3e73
AK		 4584 kaddr += offset_in_page(gpa);
4585 switch (bytes) {
4586 case 1:
4587 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4588 break;
4589 case 2:
4590 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4591 break;
4592 case 4:
4593 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4594 break;
4595 case 8:
4596 exchanged = CMPXCHG64(kaddr, old, new);
4597 break;
4598 default:
4599 BUG();
2bacc55c 4600 }
8fd75e12 4601 kunmap_atomic(kaddr);
daea3e73
AK		 4602 kvm_release_page_dirty(page);
4603
4604 if (!exchanged)
4605 return X86EMUL_CMPXCHG_FAILED;
4606
d3714010 4607 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4608 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4609
4610 return X86EMUL_CONTINUE;
4a5f48f6 4611
3200f405 4612emul_write:
daea3e73 4613 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4614
0f65dd70 4615 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4616}
4617
cf8f70bf
GN		 4618static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4619{
4620 /* TODO: String I/O for in kernel device */
4621 int r;
4622
4623 if (vcpu->arch.pio.in)
4624 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4625 vcpu->arch.pio.size, pd);
4626 else
4627 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4628 vcpu->arch.pio.port, vcpu->arch.pio.size,
4629 pd);
4630 return r;
4631}
4632
6f6fbe98
XG		 4633static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4634 unsigned short port, void *val,
4635 unsigned int count, bool in)
cf8f70bf 4636{
cf8f70bf 4637 vcpu->arch.pio.port = port;
6f6fbe98 4638 vcpu->arch.pio.in = in;
7972995b 4639 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4640 vcpu->arch.pio.size = size;
4641
4642 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4643 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4644 return 1;
4645 }
4646
4647 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4648 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4649 vcpu->run->io.size = size;
4650 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4651 vcpu->run->io.count = count;
4652 vcpu->run->io.port = port;
4653
4654 return 0;
4655}
4656
6f6fbe98
XG		 4657static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4658 int size, unsigned short port, void *val,
4659 unsigned int count)
cf8f70bf 4660{
ca1d4a9e 4661 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4662 int ret;
ca1d4a9e 4663
6f6fbe98
XG		 4664 if (vcpu->arch.pio.count)
4665 goto data_avail;
cf8f70bf 4666
6f6fbe98
XG		 4667 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4668 if (ret) {
4669data_avail:
4670 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4671 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4672 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4673 return 1;
4674 }
4675
cf8f70bf
GN		 4676 return 0;
4677}
4678
6f6fbe98
XG		 4679static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4680 int size, unsigned short port,
4681 const void *val, unsigned int count)
4682{
4683 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4684
4685 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4686 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4687 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4688}
4689
bbd9b64e
CO		 4690static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4691{
4692 return kvm_x86_ops->get_segment_base(vcpu, seg);
4693}
4694
3cb16fe7 4695static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4696{
3cb16fe7 4697 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4698}
4699
f5f48ee1
SY		 4700int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4701{
4702 if (!need_emulate_wbinvd(vcpu))
4703 return X86EMUL_CONTINUE;
4704
4705 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4706 int cpu = get_cpu();
4707
4708 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4709 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4710 wbinvd_ipi, NULL, 1);
2eec7343 4711 put_cpu();
f5f48ee1 4712 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4713 } else
4714 wbinvd();
f5f48ee1
SY		 4715 return X86EMUL_CONTINUE;
4716}
4717EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4718
bcaf5cc5
AK		 4719static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4720{
4721 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4722}
4723
717746e3 4724int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4725{
16f8a6f9 4726 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4727}
4728
717746e3 4729int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4730{
338dbc97 4731
717746e3 4732 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4733}
4734
52a46617 4735static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4736{
52a46617 4737 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4738}
4739
717746e3 4740static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4741{
717746e3 4742 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4743 unsigned long value;
4744
4745 switch (cr) {
4746 case 0:
4747 value = kvm_read_cr0(vcpu);
4748 break;
4749 case 2:
4750 value = vcpu->arch.cr2;
4751 break;
4752 case 3:
9f8fe504 4753 value = kvm_read_cr3(vcpu);
52a46617
GN		 4754 break;
4755 case 4:
4756 value = kvm_read_cr4(vcpu);
4757 break;
4758 case 8:
4759 value = kvm_get_cr8(vcpu);
4760 break;
4761 default:
a737f256 4762 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4763 return 0;
4764 }
4765
4766 return value;
4767}
4768
717746e3 4769static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4770{
717746e3 4771 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4772 int res = 0;
4773
52a46617
GN		 4774 switch (cr) {
4775 case 0:
49a9b07e 4776 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4777 break;
4778 case 2:
4779 vcpu->arch.cr2 = val;
4780 break;
4781 case 3:
2390218b 4782 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4783 break;
4784 case 4:
a83b29c6 4785 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4786 break;
4787 case 8:
eea1cff9 4788 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4789 break;
4790 default:
a737f256 4791 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4792 res = -1;
52a46617 4793 }
0f12244f
GN		 4794
4795 return res;
52a46617
GN		 4796}
4797
717746e3 4798static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4799{
717746e3 4800 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4801}
4802
4bff1e86 4803static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4804{
4bff1e86 4805 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4806}
4807
4bff1e86 4808static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4809{
4bff1e86 4810 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4811}
4812
1ac9d0cf
AK		 4813static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4814{
4815 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4816}
4817
4818static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4819{
4820 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4821}
4822
4bff1e86
AK		 4823static unsigned long emulator_get_cached_segment_base(
4824 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4825{
4bff1e86 4826 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4827}
4828
1aa36616
AK		 4829static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4830 struct desc_struct *desc, u32 *base3,
4831 int seg)
2dafc6c2
GN		 4832{
4833 struct kvm_segment var;
4834
4bff1e86 4835 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4836 *selector = var.selector;
2dafc6c2 4837
378a8b09
GN		 4838 if (var.unusable) {
4839 memset(desc, 0, sizeof(*desc));
2dafc6c2 4840 return false;
378a8b09 4841 }
2dafc6c2
GN		 4842
4843 if (var.g)
4844 var.limit >>= 12;
4845 set_desc_limit(desc, var.limit);
4846 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4847#ifdef CONFIG_X86_64
4848 if (base3)
4849 *base3 = var.base >> 32;
4850#endif
2dafc6c2
GN		 4851 desc->type = var.type;
4852 desc->s = var.s;
4853 desc->dpl = var.dpl;
4854 desc->p = var.present;
4855 desc->avl = var.avl;
4856 desc->l = var.l;
4857 desc->d = var.db;
4858 desc->g = var.g;
4859
4860 return true;
4861}
4862
1aa36616
AK		 4863static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4864 struct desc_struct *desc, u32 base3,
4865 int seg)
2dafc6c2 4866{
4bff1e86 4867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4868 struct kvm_segment var;
4869
1aa36616 4870 var.selector = selector;
2dafc6c2 4871 var.base = get_desc_base(desc);
5601d05b
GN		 4872#ifdef CONFIG_X86_64
4873 var.base |= ((u64)base3) << 32;
4874#endif
2dafc6c2
GN		 4875 var.limit = get_desc_limit(desc);
4876 if (desc->g)
4877 var.limit = (var.limit << 12) | 0xfff;
4878 var.type = desc->type;
2dafc6c2
GN		 4879 var.dpl = desc->dpl;
4880 var.db = desc->d;
4881 var.s = desc->s;
4882 var.l = desc->l;
4883 var.g = desc->g;
4884 var.avl = desc->avl;
4885 var.present = desc->p;
4886 var.unusable = !var.present;
4887 var.padding = 0;
4888
4889 kvm_set_segment(vcpu, &var, seg);
4890 return;
4891}
4892
717746e3
AK		 4893static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4894 u32 msr_index, u64 *pdata)
4895{
4896 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4897}
4898
4899static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4900 u32 msr_index, u64 data)
4901{
8fe8ab46
WA		 4902 struct msr_data msr;
4903
4904 msr.data = data;
4905 msr.index = msr_index;
4906 msr.host_initiated = false;
4907 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4908}
4909
67f4d428
NA		 4910static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4911 u32 pmc)
4912{
4913 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4914}
4915
222d21aa
AK		 4916static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4917 u32 pmc, u64 *pdata)
4918{
4919 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4920}
4921
6c3287f7
AK		 4922static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4923{
4924 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4925}
4926
5037f6f3
AK		 4927static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4928{
4929 preempt_disable();
5197b808 4930 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4931 /*
4932 * CR0.TS may reference the host fpu state, not the guest fpu state,
4933 * so it may be clear at this point.
4934 */
4935 clts();
4936}
4937
4938static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4939{
4940 preempt_enable();
4941}
4942
2953538e 4943static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4944 struct x86_instruction_info *info,
c4f035c6
AK		 4945 enum x86_intercept_stage stage)
4946{
2953538e 4947 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4948}
4949
0017f93a 4950static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4951 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4952{
0017f93a 4953 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4954}
4955
dd856efa
AK		 4956static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4957{
4958 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4959}
4960
4961static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4962{
4963 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4964}
4965
0225fb50 4966static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4967 .read_gpr = emulator_read_gpr,
4968 .write_gpr = emulator_write_gpr,
1871c602 4969 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4970 .write_std = kvm_write_guest_virt_system,
1871c602 4971 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4972 .read_emulated = emulator_read_emulated,
4973 .write_emulated = emulator_write_emulated,
4974 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4975 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4976 .pio_in_emulated = emulator_pio_in_emulated,
4977 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4978 .get_segment = emulator_get_segment,
4979 .set_segment = emulator_set_segment,
5951c442 4980 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4981 .get_gdt = emulator_get_gdt,
160ce1f1 4982 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4983 .set_gdt = emulator_set_gdt,
4984 .set_idt = emulator_set_idt,
52a46617
GN		 4985 .get_cr = emulator_get_cr,
4986 .set_cr = emulator_set_cr,
9c537244 4987 .cpl = emulator_get_cpl,
35aa5375
GN		 4988 .get_dr = emulator_get_dr,
4989 .set_dr = emulator_set_dr,
717746e3
AK		 4990 .set_msr = emulator_set_msr,
4991 .get_msr = emulator_get_msr,
67f4d428 4992 .check_pmc = emulator_check_pmc,
222d21aa 4993 .read_pmc = emulator_read_pmc,
6c3287f7 4994 .halt = emulator_halt,
bcaf5cc5 4995 .wbinvd = emulator_wbinvd,
d6aa1000 4996 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4997 .get_fpu = emulator_get_fpu,
4998 .put_fpu = emulator_put_fpu,
c4f035c6 4999 .intercept = emulator_intercept,
bdb42f5a 5000 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 5001};
5002
95cb2295
GN		 5003static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5004{
37ccdcbe 5005 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5006 /*
5007 * an sti; sti; sequence only disable interrupts for the first
5008 * instruction. So, if the last instruction, be it emulated or
5009 * not, left the system with the INT_STI flag enabled, it
5010 * means that the last instruction is an sti. We should not
5011 * leave the flag on in this case. The same goes for mov ss
5012 */
37ccdcbe
PB		 5013 if (int_shadow & mask)
5014 mask = 0;
6addfc42 5015 if (unlikely(int_shadow || mask)) {
95cb2295 5016 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5017 if (!mask)
5018 kvm_make_request(KVM_REQ_EVENT, vcpu);
5019 }
95cb2295
GN		 5020}
5021
ef54bcfe 5022static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5023{
5024 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5025 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5026 return kvm_propagate_fault(vcpu, &ctxt->exception);
5027
5028 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5029 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5030 ctxt->exception.error_code);
54b8486f 5031 else
da9cb575 5032 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5033 return false;
54b8486f
GN		 5034}
5035
8ec4722d
MG		 5036static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5037{
adf52235 5038 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5039 int cs_db, cs_l;
5040
8ec4722d
MG		 5041 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5042
adf52235
TY		 5043 ctxt->eflags = kvm_get_rflags(vcpu);
5044 ctxt->eip = kvm_rip_read(vcpu);
5045 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5046 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5047 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5048 cs_db ? X86EMUL_MODE_PROT32 :
5049 X86EMUL_MODE_PROT16;
5050 ctxt->guest_mode = is_guest_mode(vcpu);
5051
dd856efa 5052 init_decode_cache(ctxt);
7ae441ea 5053 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5054}
5055
71f9833b 5056int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5057{
9d74191a 5058 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5059 int ret;
5060
5061 init_emulate_ctxt(vcpu);
5062
9dac77fa
AK		 5063 ctxt->op_bytes = 2;
5064 ctxt->ad_bytes = 2;
5065 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5066 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5067
5068 if (ret != X86EMUL_CONTINUE)
5069 return EMULATE_FAIL;
5070
9dac77fa 5071 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5072 kvm_rip_write(vcpu, ctxt->eip);
5073 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5074
5075 if (irq == NMI_VECTOR)
7460fb4a 5076 vcpu->arch.nmi_pending = 0;
63995653
MG		 5077 else
5078 vcpu->arch.interrupt.pending = false;
5079
5080 return EMULATE_DONE;
5081}
5082EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5083
6d77dbfc
GN		 5084static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5085{
fc3a9157
JR		 5086 int r = EMULATE_DONE;
5087
6d77dbfc
GN		 5088 ++vcpu->stat.insn_emulation_fail;
5089 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5090 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5091 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5092 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5093 vcpu->run->internal.ndata = 0;
5094 r = EMULATE_FAIL;
5095 }
6d77dbfc 5096 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5097
5098 return r;
6d77dbfc
GN		 5099}
5100
93c05d3e 5101static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5102 bool write_fault_to_shadow_pgtable,
5103 int emulation_type)
a6f177ef 5104{
95b3cf69 5105 gpa_t gpa = cr2;
8e3d9d06 5106 pfn_t pfn;
a6f177ef 5107
991eebf9
GN		 5108 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5109 return false;
5110
95b3cf69
XG		 5111 if (!vcpu->arch.mmu.direct_map) {
5112 /*
5113 * Write permission should be allowed since only
5114 * write access need to be emulated.
5115 */
5116 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5117
95b3cf69
XG		 5118 /*
5119 * If the mapping is invalid in guest, let cpu retry
5120 * it to generate fault.
5121 */
5122 if (gpa == UNMAPPED_GVA)
5123 return true;
5124 }
a6f177ef 5125
8e3d9d06
XG		 5126 /*
5127 * Do not retry the unhandleable instruction if it faults on the
5128 * readonly host memory, otherwise it will goto a infinite loop:
5129 * retry instruction -> write #PF -> emulation fail -> retry
5130 * instruction -> ...
5131 */
5132 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5133
5134 /*
5135 * If the instruction failed on the error pfn, it can not be fixed,
5136 * report the error to userspace.
5137 */
5138 if (is_error_noslot_pfn(pfn))
5139 return false;
5140
5141 kvm_release_pfn_clean(pfn);
5142
5143 /* The instructions are well-emulated on direct mmu. */
5144 if (vcpu->arch.mmu.direct_map) {
5145 unsigned int indirect_shadow_pages;
5146
5147 spin_lock(&vcpu->kvm->mmu_lock);
5148 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5149 spin_unlock(&vcpu->kvm->mmu_lock);
5150
5151 if (indirect_shadow_pages)
5152 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5153
a6f177ef 5154 return true;
8e3d9d06 5155 }
a6f177ef 5156
95b3cf69
XG		 5157 /*
5158 * if emulation was due to access to shadowed page table
5159 * and it failed try to unshadow page and re-enter the
5160 * guest to let CPU execute the instruction.
5161 */
5162 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5163
5164 /*
5165 * If the access faults on its page table, it can not
5166 * be fixed by unprotecting shadow page and it should
5167 * be reported to userspace.
5168 */
5169 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5170}
5171
1cb3f3ae
XG		 5172static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5173 unsigned long cr2, int emulation_type)
5174{
5175 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5176 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5177
5178 last_retry_eip = vcpu->arch.last_retry_eip;
5179 last_retry_addr = vcpu->arch.last_retry_addr;
5180
5181 /*
5182 * If the emulation is caused by #PF and it is non-page_table
5183 * writing instruction, it means the VM-EXIT is caused by shadow
5184 * page protected, we can zap the shadow page and retry this
5185 * instruction directly.
5186 *
5187 * Note: if the guest uses a non-page-table modifying instruction
5188 * on the PDE that points to the instruction, then we will unmap
5189 * the instruction and go to an infinite loop. So, we cache the
5190 * last retried eip and the last fault address, if we meet the eip
5191 * and the address again, we can break out of the potential infinite
5192 * loop.
5193 */
5194 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5195
5196 if (!(emulation_type & EMULTYPE_RETRY))
5197 return false;
5198
5199 if (x86_page_table_writing_insn(ctxt))
5200 return false;
5201
5202 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5203 return false;
5204
5205 vcpu->arch.last_retry_eip = ctxt->eip;
5206 vcpu->arch.last_retry_addr = cr2;
5207
5208 if (!vcpu->arch.mmu.direct_map)
5209 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5210
22368028 5211 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5212
5213 return true;
5214}
5215
716d51ab
GN		 5216static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5217static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5218
4a1e10d5
PB		 5219static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5220 unsigned long *db)
5221{
5222 u32 dr6 = 0;
5223 int i;
5224 u32 enable, rwlen;
5225
5226 enable = dr7;
5227 rwlen = dr7 >> 16;
5228 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5229 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5230 dr6 |= (1 << i);
5231 return dr6;
5232}
5233
6addfc42 5234static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5235{
5236 struct kvm_run *kvm_run = vcpu->run;
5237
5238 /*
6addfc42
PB		 5239 * rflags is the old, "raw" value of the flags. The new value has
5240 * not been saved yet.
663f4c61
PB		 5241 *
5242 * This is correct even for TF set by the guest, because "the
5243 * processor will not generate this exception after the instruction
5244 * that sets the TF flag".
5245 */
663f4c61
PB		 5246 if (unlikely(rflags & X86_EFLAGS_TF)) {
5247 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5248 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5249 DR6_RTM;
663f4c61
PB		 5250 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5251 kvm_run->debug.arch.exception = DB_VECTOR;
5252 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5253 *r = EMULATE_USER_EXIT;
5254 } else {
5255 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5256 /*
5257 * "Certain debug exceptions may clear bit 0-3. The
5258 * remaining contents of the DR6 register are never
5259 * cleared by the processor".
5260 */
5261 vcpu->arch.dr6 &= ~15;
6f43ed01 5262 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5263 kvm_queue_exception(vcpu, DB_VECTOR);
5264 }
5265 }
5266}
5267
4a1e10d5
PB		 5268static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5269{
4a1e10d5
PB		 5270 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5271 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5272 struct kvm_run *kvm_run = vcpu->run;
5273 unsigned long eip = kvm_get_linear_rip(vcpu);
5274 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5275 vcpu->arch.guest_debug_dr7,
5276 vcpu->arch.eff_db);
5277
5278 if (dr6 != 0) {
6f43ed01 5279 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5280 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5281 kvm_run->debug.arch.exception = DB_VECTOR;
5282 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5283 *r = EMULATE_USER_EXIT;
5284 return true;
5285 }
5286 }
5287
4161a569
NA		 5288 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5289 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5290 unsigned long eip = kvm_get_linear_rip(vcpu);
5291 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5292 vcpu->arch.dr7,
5293 vcpu->arch.db);
5294
5295 if (dr6 != 0) {
5296 vcpu->arch.dr6 &= ~15;
6f43ed01 5297 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5298 kvm_queue_exception(vcpu, DB_VECTOR);
5299 *r = EMULATE_DONE;
5300 return true;
5301 }
5302 }
5303
5304 return false;
5305}
5306
51d8b661
AP		 5307int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5308 unsigned long cr2,
dc25e89e
AP		 5309 int emulation_type,
5310 void *insn,
5311 int insn_len)
bbd9b64e 5312{
95cb2295 5313 int r;
9d74191a 5314 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5315 bool writeback = true;
93c05d3e 5316 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5317
93c05d3e
XG		 5318 /*
5319 * Clear write_fault_to_shadow_pgtable here to ensure it is
5320 * never reused.
5321 */
5322 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5323 kvm_clear_exception_queue(vcpu);
8d7d8102 5324
571008da 5325 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5326 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5327
5328 /*
5329 * We will reenter on the same instruction since
5330 * we do not set complete_userspace_io. This does not
5331 * handle watchpoints yet, those would be handled in
5332 * the emulate_ops.
5333 */
5334 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5335 return r;
5336
9d74191a
TY		 5337 ctxt->interruptibility = 0;
5338 ctxt->have_exception = false;
e0ad0b47 5339 ctxt->exception.vector = -1;
9d74191a 5340 ctxt->perm_ok = false;
bbd9b64e 5341
b51e974f 5342 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5343
9d74191a 5344 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5345
e46479f8 5346 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5347 ++vcpu->stat.insn_emulation;
1d2887e2 5348 if (r != EMULATION_OK) {
4005996e
AK		 5349 if (emulation_type & EMULTYPE_TRAP_UD)
5350 return EMULATE_FAIL;
991eebf9
GN		 5351 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5352 emulation_type))
bbd9b64e 5353 return EMULATE_DONE;
6d77dbfc
GN		 5354 if (emulation_type & EMULTYPE_SKIP)
5355 return EMULATE_FAIL;
5356 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5357 }
5358 }
5359
ba8afb6b 5360 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5361 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5362 if (ctxt->eflags & X86_EFLAGS_RF)
5363 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5364 return EMULATE_DONE;
5365 }
5366
1cb3f3ae
XG		 5367 if (retry_instruction(ctxt, cr2, emulation_type))
5368 return EMULATE_DONE;
5369
7ae441ea 5370 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5371 changes registers values during IO operation */
7ae441ea
GN		 5372 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5373 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5374 emulator_invalidate_register_cache(ctxt);
7ae441ea 5375 }
4d2179e1 5376
5cd21917 5377restart:
9d74191a 5378 r = x86_emulate_insn(ctxt);
bbd9b64e 5379
775fde86
JR		 5380 if (r == EMULATION_INTERCEPTED)
5381 return EMULATE_DONE;
5382
d2ddd1c4 5383 if (r == EMULATION_FAILED) {
991eebf9
GN		 5384 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5385 emulation_type))
c3cd7ffa
GN		 5386 return EMULATE_DONE;
5387
6d77dbfc 5388 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5389 }
5390
9d74191a 5391 if (ctxt->have_exception) {
d2ddd1c4 5392 r = EMULATE_DONE;
ef54bcfe
PB		 5393 if (inject_emulated_exception(vcpu))
5394 return r;
d2ddd1c4 5395 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5396 if (!vcpu->arch.pio.in) {
5397 /* FIXME: return into emulator if single-stepping. */
3457e419 5398 vcpu->arch.pio.count = 0;
0912c977 5399 } else {
7ae441ea 5400 writeback = false;
716d51ab
GN		 5401 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5402 }
ac0a48c3 5403 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5404 } else if (vcpu->mmio_needed) {
5405 if (!vcpu->mmio_is_write)
5406 writeback = false;
ac0a48c3 5407 r = EMULATE_USER_EXIT;
716d51ab 5408 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5409 } else if (r == EMULATION_RESTART)
5cd21917 5410 goto restart;
d2ddd1c4
GN		 5411 else
5412 r = EMULATE_DONE;
f850e2e6 5413
7ae441ea 5414 if (writeback) {
6addfc42 5415 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5416 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5417 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5418 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5419 if (r == EMULATE_DONE)
6addfc42 5420 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5421 if (!ctxt->have_exception ||
5422 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5423 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5424
5425 /*
5426 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5427 * do nothing, and it will be requested again as soon as
5428 * the shadow expires. But we still need to check here,
5429 * because POPF has no interrupt shadow.
5430 */
5431 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5432 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5433 } else
5434 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5435
5436 return r;
de7d789a 5437}
51d8b661 5438EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5439
cf8f70bf 5440int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5441{
cf8f70bf 5442 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5443 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5444 size, port, &val, 1);
cf8f70bf 5445 /* do not return to emulator after return from userspace */
7972995b 5446 vcpu->arch.pio.count = 0;
de7d789a
CO		 5447 return ret;
5448}
cf8f70bf 5449EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5450
8cfdc000
ZA		 5451static void tsc_bad(void *info)
5452{
0a3aee0d 5453 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5454}
5455
5456static void tsc_khz_changed(void *data)
c8076604 5457{
8cfdc000
ZA		 5458 struct cpufreq_freqs *freq = data;
5459 unsigned long khz = 0;
5460
5461 if (data)
5462 khz = freq->new;
5463 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5464 khz = cpufreq_quick_get(raw_smp_processor_id());
5465 if (!khz)
5466 khz = tsc_khz;
0a3aee0d 5467 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5468}
5469
c8076604
GH		 5470static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5471 void *data)
5472{
5473 struct cpufreq_freqs *freq = data;
5474 struct kvm *kvm;
5475 struct kvm_vcpu *vcpu;
5476 int i, send_ipi = 0;
5477
8cfdc000
ZA		 5478 /*
5479 * We allow guests to temporarily run on slowing clocks,
5480 * provided we notify them after, or to run on accelerating
5481 * clocks, provided we notify them before. Thus time never
5482 * goes backwards.
5483 *
5484 * However, we have a problem. We can't atomically update
5485 * the frequency of a given CPU from this function; it is
5486 * merely a notifier, which can be called from any CPU.
5487 * Changing the TSC frequency at arbitrary points in time
5488 * requires a recomputation of local variables related to
5489 * the TSC for each VCPU. We must flag these local variables
5490 * to be updated and be sure the update takes place with the
5491 * new frequency before any guests proceed.
5492 *
5493 * Unfortunately, the combination of hotplug CPU and frequency
5494 * change creates an intractable locking scenario; the order
5495 * of when these callouts happen is undefined with respect to
5496 * CPU hotplug, and they can race with each other. As such,
5497 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5498 * undefined; you can actually have a CPU frequency change take
5499 * place in between the computation of X and the setting of the
5500 * variable. To protect against this problem, all updates of
5501 * the per_cpu tsc_khz variable are done in an interrupt
5502 * protected IPI, and all callers wishing to update the value
5503 * must wait for a synchronous IPI to complete (which is trivial
5504 * if the caller is on the CPU already). This establishes the
5505 * necessary total order on variable updates.
5506 *
5507 * Note that because a guest time update may take place
5508 * anytime after the setting of the VCPU's request bit, the
5509 * correct TSC value must be set before the request. However,
5510 * to ensure the update actually makes it to any guest which
5511 * starts running in hardware virtualization between the set
5512 * and the acquisition of the spinlock, we must also ping the
5513 * CPU after setting the request bit.
5514 *
5515 */
5516
c8076604
GH		 5517 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5518 return 0;
5519 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5520 return 0;
8cfdc000
ZA		 5521
5522 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5523
2f303b74 5524 spin_lock(&kvm_lock);
c8076604 5525 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5526 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5527 if (vcpu->cpu != freq->cpu)
5528 continue;
c285545f 5529 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5530 if (vcpu->cpu != smp_processor_id())
8cfdc000 5531 send_ipi = 1;
c8076604
GH		 5532 }
5533 }
2f303b74 5534 spin_unlock(&kvm_lock);
c8076604
GH		 5535
5536 if (freq->old < freq->new && send_ipi) {
5537 /*
5538 * We upscale the frequency. Must make the guest
5539 * doesn't see old kvmclock values while running with
5540 * the new frequency, otherwise we risk the guest sees
5541 * time go backwards.
5542 *
5543 * In case we update the frequency for another cpu
5544 * (which might be in guest context) send an interrupt
5545 * to kick the cpu out of guest context. Next time
5546 * guest context is entered kvmclock will be updated,
5547 * so the guest will not see stale values.
5548 */
8cfdc000 5549 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5550 }
5551 return 0;
5552}
5553
5554static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5555 .notifier_call = kvmclock_cpufreq_notifier
5556};
5557
5558static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5559 unsigned long action, void *hcpu)
5560{
5561 unsigned int cpu = (unsigned long)hcpu;
5562
5563 switch (action) {
5564 case CPU_ONLINE:
5565 case CPU_DOWN_FAILED:
5566 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5567 break;
5568 case CPU_DOWN_PREPARE:
5569 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5570 break;
5571 }
5572 return NOTIFY_OK;
5573}
5574
5575static struct notifier_block kvmclock_cpu_notifier_block = {
5576 .notifier_call = kvmclock_cpu_notifier,
5577 .priority = -INT_MAX
c8076604
GH		 5578};
5579
b820cc0c
ZA		 5580static void kvm_timer_init(void)
5581{
5582 int cpu;
5583
c285545f 5584 max_tsc_khz = tsc_khz;
460dd42e
SB		 5585
5586 cpu_notifier_register_begin();
b820cc0c 5587 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5588#ifdef CONFIG_CPU_FREQ
5589 struct cpufreq_policy policy;
5590 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5591 cpu = get_cpu();
5592 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5593 if (policy.cpuinfo.max_freq)
5594 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5595 put_cpu();
c285545f 5596#endif
b820cc0c
ZA		 5597 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5598 CPUFREQ_TRANSITION_NOTIFIER);
5599 }
c285545f 5600 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5601 for_each_online_cpu(cpu)
5602 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5603
5604 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5605 cpu_notifier_register_done();
5606
b820cc0c
ZA		 5607}
5608
ff9d07a0
ZY		 5609static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5610
f5132b01 5611int kvm_is_in_guest(void)
ff9d07a0 5612{
086c9855 5613 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5614}
5615
5616static int kvm_is_user_mode(void)
5617{
5618 int user_mode = 3;
dcf46b94 5619
086c9855
AS		 5620 if (__this_cpu_read(current_vcpu))
5621 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5622
ff9d07a0
ZY		 5623 return user_mode != 0;
5624}
5625
5626static unsigned long kvm_get_guest_ip(void)
5627{
5628 unsigned long ip = 0;
dcf46b94 5629
086c9855
AS		 5630 if (__this_cpu_read(current_vcpu))
5631 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5632
ff9d07a0
ZY		 5633 return ip;
5634}
5635
5636static struct perf_guest_info_callbacks kvm_guest_cbs = {
5637 .is_in_guest = kvm_is_in_guest,
5638 .is_user_mode = kvm_is_user_mode,
5639 .get_guest_ip = kvm_get_guest_ip,
5640};
5641
5642void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5643{
086c9855 5644 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5645}
5646EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5647
5648void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5649{
086c9855 5650 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5651}
5652EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5653
ce88decf
XG		 5654static void kvm_set_mmio_spte_mask(void)
5655{
5656 u64 mask;
5657 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5658
5659 /*
5660 * Set the reserved bits and the present bit of an paging-structure
5661 * entry to generate page fault with PFER.RSV = 1.
5662 */
885032b9 5663 /* Mask the reserved physical address bits. */
d1431483 5664 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5665
5666 /* Bit 62 is always reserved for 32bit host. */
5667 mask |= 0x3ull << 62;
5668
5669 /* Set the present bit. */
ce88decf
XG		 5670 mask |= 1ull;
5671
5672#ifdef CONFIG_X86_64
5673 /*
5674 * If reserved bit is not supported, clear the present bit to disable
5675 * mmio page fault.
5676 */
5677 if (maxphyaddr == 52)
5678 mask &= ~1ull;
5679#endif
5680
5681 kvm_mmu_set_mmio_spte_mask(mask);
5682}
5683
16e8d74d
MT		 5684#ifdef CONFIG_X86_64
5685static void pvclock_gtod_update_fn(struct work_struct *work)
5686{
d828199e
MT		 5687 struct kvm *kvm;
5688
5689 struct kvm_vcpu *vcpu;
5690 int i;
5691
2f303b74 5692 spin_lock(&kvm_lock);
d828199e
MT		 5693 list_for_each_entry(kvm, &vm_list, vm_list)
5694 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5695 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5696 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5697 spin_unlock(&kvm_lock);
16e8d74d
MT		 5698}
5699
5700static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5701
5702/*
5703 * Notification about pvclock gtod data update.
5704 */
5705static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5706 void *priv)
5707{
5708 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5709 struct timekeeper *tk = priv;
5710
5711 update_pvclock_gtod(tk);
5712
5713 /* disable master clock if host does not trust, or does not
5714 * use, TSC clocksource
5715 */
5716 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5717 atomic_read(&kvm_guest_has_master_clock) != 0)
5718 queue_work(system_long_wq, &pvclock_gtod_work);
5719
5720 return 0;
5721}
5722
5723static struct notifier_block pvclock_gtod_notifier = {
5724 .notifier_call = pvclock_gtod_notify,
5725};
5726#endif
5727
f8c16bba 5728int kvm_arch_init(void *opaque)
043405e1 5729{
b820cc0c 5730 int r;
6b61edf7 5731 struct kvm_x86_ops *ops = opaque;
f8c16bba 5732
f8c16bba
ZX		 5733 if (kvm_x86_ops) {
5734 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5735 r = -EEXIST;
5736 goto out;
f8c16bba
ZX		 5737 }
5738
5739 if (!ops->cpu_has_kvm_support()) {
5740 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5741 r = -EOPNOTSUPP;
5742 goto out;
f8c16bba
ZX		 5743 }
5744 if (ops->disabled_by_bios()) {
5745 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5746 r = -EOPNOTSUPP;
5747 goto out;
f8c16bba
ZX		 5748 }
5749
013f6a5d
MT		 5750 r = -ENOMEM;
5751 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5752 if (!shared_msrs) {
5753 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5754 goto out;
5755 }
5756
97db56ce
AK		 5757 r = kvm_mmu_module_init();
5758 if (r)
013f6a5d 5759 goto out_free_percpu;
97db56ce 5760
ce88decf 5761 kvm_set_mmio_spte_mask();
97db56ce 5762
f8c16bba 5763 kvm_x86_ops = ops;
920c8377
PB		 5764 kvm_init_msr_list();
5765
7b52345e 5766 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5767 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5768
b820cc0c 5769 kvm_timer_init();
c8076604 5770
ff9d07a0
ZY		 5771 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5772
2acf923e
DC		 5773 if (cpu_has_xsave)
5774 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5775
c5cc421b 5776 kvm_lapic_init();
16e8d74d
MT		 5777#ifdef CONFIG_X86_64
5778 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5779#endif
5780
f8c16bba 5781 return 0;
56c6d28a 5782
013f6a5d
MT		 5783out_free_percpu:
5784 free_percpu(shared_msrs);
56c6d28a 5785out:
56c6d28a 5786 return r;
043405e1 5787}
8776e519 5788
f8c16bba
ZX		 5789void kvm_arch_exit(void)
5790{
ff9d07a0
ZY		 5791 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5792
888d256e
JK		 5793 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5794 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5795 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5796 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5797#ifdef CONFIG_X86_64
5798 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5799#endif
f8c16bba 5800 kvm_x86_ops = NULL;
56c6d28a 5801 kvm_mmu_module_exit();
013f6a5d 5802 free_percpu(shared_msrs);
56c6d28a 5803}
f8c16bba 5804
8776e519
HB		 5805int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5806{
5807 ++vcpu->stat.halt_exits;
5808 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5809 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5810 return 1;
5811 } else {
5812 vcpu->run->exit_reason = KVM_EXIT_HLT;
5813 return 0;
5814 }
5815}
5816EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5817
55cd8e5a
GN		 5818int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5819{
5820 u64 param, ingpa, outgpa, ret;
5821 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5822 bool fast, longmode;
55cd8e5a
GN		 5823
5824 /*
5825 * hypercall generates UD from non zero cpl and real mode
5826 * per HYPER-V spec
5827 */
3eeb3288 5828 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5829 kvm_queue_exception(vcpu, UD_VECTOR);
5830 return 0;
5831 }
5832
a449c7aa 5833 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5834
5835 if (!longmode) {
ccd46936
GN		 5836 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5837 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5838 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5839 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5840 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5841 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5842 }
5843#ifdef CONFIG_X86_64
5844 else {
5845 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5846 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5847 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5848 }
5849#endif
5850
5851 code = param & 0xffff;
5852 fast = (param >> 16) & 0x1;
5853 rep_cnt = (param >> 32) & 0xfff;
5854 rep_idx = (param >> 48) & 0xfff;
5855
5856 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5857
c25bc163
GN		 5858 switch (code) {
5859 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5860 kvm_vcpu_on_spin(vcpu);
5861 break;
5862 default:
5863 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5864 break;
5865 }
55cd8e5a
GN		 5866
5867 ret = res | (((u64)rep_done & 0xfff) << 32);
5868 if (longmode) {
5869 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5870 } else {
5871 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5872 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5873 }
5874
5875 return 1;
5876}
5877
6aef266c
SV		 5878/*
5879 * kvm_pv_kick_cpu_op: Kick a vcpu.
5880 *
5881 * @apicid - apicid of vcpu to be kicked.
5882 */
5883static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5884{
24d2166b 5885 struct kvm_lapic_irq lapic_irq;
6aef266c 5886
24d2166b
R		 5887 lapic_irq.shorthand = 0;
5888 lapic_irq.dest_mode = 0;
5889 lapic_irq.dest_id = apicid;
6aef266c 5890
24d2166b
R		 5891 lapic_irq.delivery_mode = APIC_DM_REMRD;
5892 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5893}
5894
8776e519
HB		 5895int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5896{
5897 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5898 int op_64_bit, r = 1;
8776e519 5899
55cd8e5a
GN		 5900 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5901 return kvm_hv_hypercall(vcpu);
5902
5fdbf976
MT		 5903 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5904 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5905 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5906 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5907 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5908
229456fc 5909 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5910
a449c7aa
NA		 5911 op_64_bit = is_64_bit_mode(vcpu);
5912 if (!op_64_bit) {
8776e519
HB		 5913 nr &= 0xFFFFFFFF;
5914 a0 &= 0xFFFFFFFF;
5915 a1 &= 0xFFFFFFFF;
5916 a2 &= 0xFFFFFFFF;
5917 a3 &= 0xFFFFFFFF;
5918 }
5919
07708c4a
JK		 5920 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5921 ret = -KVM_EPERM;
5922 goto out;
5923 }
5924
8776e519 5925 switch (nr) {
b93463aa
AK		 5926 case KVM_HC_VAPIC_POLL_IRQ:
5927 ret = 0;
5928 break;
6aef266c
SV		 5929 case KVM_HC_KICK_CPU:
5930 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5931 ret = 0;
5932 break;
8776e519
HB		 5933 default:
5934 ret = -KVM_ENOSYS;
5935 break;
5936 }
07708c4a 5937out:
a449c7aa
NA		 5938 if (!op_64_bit)
5939 ret = (u32)ret;
5fdbf976 5940 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5941 ++vcpu->stat.hypercalls;
2f333bcb 5942 return r;
8776e519
HB		 5943}
5944EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5945
b6785def 5946static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5947{
d6aa1000 5948 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5949 char instruction[3];
5fdbf976 5950 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5951
8776e519 5952 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5953
9d74191a 5954 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5955}
5956
b6c7a5dc
HB		 5957/*
5958 * Check if userspace requested an interrupt window, and that the
5959 * interrupt window is open.
5960 *
5961 * No need to exit to userspace if we already have an interrupt queued.
5962 */
851ba692 5963static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5964{
8061823a 5965 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5966 vcpu->run->request_interrupt_window &&
5df56646 5967 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5968}
5969
851ba692 5970static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5971{
851ba692
AK		 5972 struct kvm_run *kvm_run = vcpu->run;
5973
91586a3b 5974 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5975 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5976 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5977 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5978 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5979 else
b6c7a5dc 5980 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5981 kvm_arch_interrupt_allowed(vcpu) &&
5982 !kvm_cpu_has_interrupt(vcpu) &&
5983 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5984}
5985
95ba8273
GN		 5986static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5987{
5988 int max_irr, tpr;
5989
5990 if (!kvm_x86_ops->update_cr8_intercept)
5991 return;
5992
88c808fd
AK		 5993 if (!vcpu->arch.apic)
5994 return;
5995
8db3baa2
GN		 5996 if (!vcpu->arch.apic->vapic_addr)
5997 max_irr = kvm_lapic_find_highest_irr(vcpu);
5998 else
5999 max_irr = -1;
95ba8273
GN		 6000
6001 if (max_irr != -1)
6002 max_irr >>= 4;
6003
6004 tpr = kvm_lapic_get_cr8(vcpu);
6005
6006 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6007}
6008
b6b8a145 6009static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6010{
b6b8a145
JK		 6011 int r;
6012
95ba8273 6013 /* try to reinject previous events if any */
b59bb7bd 6014 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6015 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6016 vcpu->arch.exception.has_error_code,
6017 vcpu->arch.exception.error_code);
d6e8c854
NA		 6018
6019 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6020 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6021 X86_EFLAGS_RF);
6022
6bdf0662
NA		 6023 if (vcpu->arch.exception.nr == DB_VECTOR &&
6024 (vcpu->arch.dr7 & DR7_GD)) {
6025 vcpu->arch.dr7 &= ~DR7_GD;
6026 kvm_update_dr7(vcpu);
6027 }
6028
b59bb7bd
GN		 6029 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6030 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6031 vcpu->arch.exception.error_code,
6032 vcpu->arch.exception.reinject);
b6b8a145 6033 return 0;
b59bb7bd
GN		 6034 }
6035
95ba8273
GN		 6036 if (vcpu->arch.nmi_injected) {
6037 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6038 return 0;
95ba8273
GN		 6039 }
6040
6041 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6042 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6043 return 0;
6044 }
6045
6046 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6047 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6048 if (r != 0)
6049 return r;
95ba8273
GN		 6050 }
6051
6052 /* try to inject new event if pending */
6053 if (vcpu->arch.nmi_pending) {
6054 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6055 --vcpu->arch.nmi_pending;
95ba8273
GN		 6056 vcpu->arch.nmi_injected = true;
6057 kvm_x86_ops->set_nmi(vcpu);
6058 }
c7c9c56c 6059 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6060 /*
6061 * Because interrupts can be injected asynchronously, we are
6062 * calling check_nested_events again here to avoid a race condition.
6063 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6064 * proposal and current concerns. Perhaps we should be setting
6065 * KVM_REQ_EVENT only on certain events and not unconditionally?
6066 */
6067 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6068 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6069 if (r != 0)
6070 return r;
6071 }
95ba8273 6072 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6073 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6074 false);
6075 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6076 }
6077 }
b6b8a145 6078 return 0;
95ba8273
GN		 6079}
6080
7460fb4a
AK		 6081static void process_nmi(struct kvm_vcpu *vcpu)
6082{
6083 unsigned limit = 2;
6084
6085 /*
6086 * x86 is limited to one NMI running, and one NMI pending after it.
6087 * If an NMI is already in progress, limit further NMIs to just one.
6088 * Otherwise, allow two (and we'll inject the first one immediately).
6089 */
6090 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6091 limit = 1;
6092
6093 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6094 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6095 kvm_make_request(KVM_REQ_EVENT, vcpu);
6096}
6097
3d81bc7e 6098static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6099{
6100 u64 eoi_exit_bitmap[4];
cf9e65b7 6101 u32 tmr[8];
c7c9c56c 6102
3d81bc7e
YZ		 6103 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6104 return;
c7c9c56c
YZ		 6105
6106 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6107 memset(tmr, 0, 32);
c7c9c56c 6108
cf9e65b7 6109 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6110 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6111 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6112}
6113
a70656b6
RK		 6114static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6115{
6116 ++vcpu->stat.tlb_flush;
6117 kvm_x86_ops->tlb_flush(vcpu);
6118}
6119
4256f43f
TC		 6120void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6121{
c24ae0dc
TC		 6122 struct page *page = NULL;
6123
f439ed27
PB		 6124 if (!irqchip_in_kernel(vcpu->kvm))
6125 return;
6126
4256f43f
TC		 6127 if (!kvm_x86_ops->set_apic_access_page_addr)
6128 return;
6129
c24ae0dc
TC		 6130 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6131 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6132
6133 /*
6134 * Do not pin apic access page in memory, the MMU notifier
6135 * will call us again if it is migrated or swapped out.
6136 */
6137 put_page(page);
4256f43f
TC		 6138}
6139EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6140
fe71557a
TC		 6141void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6142 unsigned long address)
6143{
c24ae0dc
TC		 6144 /*
6145 * The physical address of apic access page is stored in the VMCS.
6146 * Update it when it becomes invalid.
6147 */
6148 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6149 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6150}
6151
9357d939
TY		 6152/*
6153 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6154 * exiting to the userspace. Otherwise, the value will be returned to the
6155 * userspace.
6156 */
851ba692 6157static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6158{
6159 int r;
6a8b1d13 6160 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6161 vcpu->run->request_interrupt_window;
730dca42 6162 bool req_immediate_exit = false;
b6c7a5dc 6163
3e007509 6164 if (vcpu->requests) {
a8eeb04a 6165 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6166 kvm_mmu_unload(vcpu);
a8eeb04a 6167 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6168 __kvm_migrate_timers(vcpu);
d828199e
MT		 6169 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6170 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6171 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6172 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6173 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6174 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6175 if (unlikely(r))
6176 goto out;
6177 }
a8eeb04a 6178 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6179 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6180 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6181 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6182 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6183 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6184 r = 0;
6185 goto out;
6186 }
a8eeb04a 6187 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6188 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6189 r = 0;
6190 goto out;
6191 }
a8eeb04a 6192 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6193 vcpu->fpu_active = 0;
6194 kvm_x86_ops->fpu_deactivate(vcpu);
6195 }
af585b92
GN		 6196 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6197 /* Page is swapped out. Do synthetic halt */
6198 vcpu->arch.apf.halted = true;
6199 r = 1;
6200 goto out;
6201 }
c9aaa895
GC		 6202 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6203 record_steal_time(vcpu);
7460fb4a
AK		 6204 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6205 process_nmi(vcpu);
f5132b01
GN		 6206 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6207 kvm_handle_pmu_event(vcpu);
6208 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6209 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6210 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6211 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6212 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6213 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6214 }
b93463aa 6215
b463a6f7 6216 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6217 kvm_apic_accept_events(vcpu);
6218 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6219 r = 1;
6220 goto out;
6221 }
6222
b6b8a145
JK		 6223 if (inject_pending_event(vcpu, req_int_win) != 0)
6224 req_immediate_exit = true;
b463a6f7 6225 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6226 else if (vcpu->arch.nmi_pending)
c9a7953f 6227 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6228 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6229 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6230
6231 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6232 /*
6233 * Update architecture specific hints for APIC
6234 * virtual interrupt delivery.
6235 */
6236 if (kvm_x86_ops->hwapic_irr_update)
6237 kvm_x86_ops->hwapic_irr_update(vcpu,
6238 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6239 update_cr8_intercept(vcpu);
6240 kvm_lapic_sync_to_vapic(vcpu);
6241 }
6242 }
6243
d8368af8
AK		 6244 r = kvm_mmu_reload(vcpu);
6245 if (unlikely(r)) {
d905c069 6246 goto cancel_injection;
d8368af8
AK		 6247 }
6248
b6c7a5dc
HB		 6249 preempt_disable();
6250
6251 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6252 if (vcpu->fpu_active)
6253 kvm_load_guest_fpu(vcpu);
2acf923e 6254 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6255
6b7e2d09
XG		 6256 vcpu->mode = IN_GUEST_MODE;
6257
01b71917
MT		 6258 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6259
6b7e2d09
XG		 6260 /* We should set ->mode before check ->requests,
6261 * see the comment in make_all_cpus_request.
6262 */
01b71917 6263 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6264
d94e1dc9 6265 local_irq_disable();
32f88400 6266
6b7e2d09 6267 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6268 || need_resched() || signal_pending(current)) {
6b7e2d09 6269 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6270 smp_wmb();
6c142801
AK		 6271 local_irq_enable();
6272 preempt_enable();
01b71917 6273 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6274 r = 1;
d905c069 6275 goto cancel_injection;
6c142801
AK		 6276 }
6277
d6185f20
NHE		 6278 if (req_immediate_exit)
6279 smp_send_reschedule(vcpu->cpu);
6280
b6c7a5dc
HB		 6281 kvm_guest_enter();
6282
42dbaa5a 6283 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6284 set_debugreg(0, 7);
6285 set_debugreg(vcpu->arch.eff_db[0], 0);
6286 set_debugreg(vcpu->arch.eff_db[1], 1);
6287 set_debugreg(vcpu->arch.eff_db[2], 2);
6288 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6289 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6290 }
b6c7a5dc 6291
229456fc 6292 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6293 wait_lapic_expire(vcpu);
851ba692 6294 kvm_x86_ops->run(vcpu);
b6c7a5dc 6295
c77fb5fe
PB		 6296 /*
6297 * Do this here before restoring debug registers on the host. And
6298 * since we do this before handling the vmexit, a DR access vmexit
6299 * can (a) read the correct value of the debug registers, (b) set
6300 * KVM_DEBUGREG_WONT_EXIT again.
6301 */
6302 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6303 int i;
6304
6305 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6306 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6307 for (i = 0; i < KVM_NR_DB_REGS; i++)
6308 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6309 }
6310
24f1e32c
FW		 6311 /*
6312 * If the guest has used debug registers, at least dr7
6313 * will be disabled while returning to the host.
6314 * If we don't have active breakpoints in the host, we don't
6315 * care about the messed up debug address registers. But if
6316 * we have some of them active, restore the old state.
6317 */
59d8eb53 6318 if (hw_breakpoint_active())
24f1e32c 6319 hw_breakpoint_restore();
42dbaa5a 6320
886b470c
MT		 6321 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6322 native_read_tsc());
1d5f066e 6323
6b7e2d09 6324 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6325 smp_wmb();
a547c6db
YZ		 6326
6327 /* Interrupt is enabled by handle_external_intr() */
6328 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6329
6330 ++vcpu->stat.exits;
6331
6332 /*
6333 * We must have an instruction between local_irq_enable() and
6334 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6335 * the interrupt shadow. The stat.exits increment will do nicely.
6336 * But we need to prevent reordering, hence this barrier():
6337 */
6338 barrier();
6339
6340 kvm_guest_exit();
6341
6342 preempt_enable();
6343
f656ce01 6344 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6345
b6c7a5dc
HB		 6346 /*
6347 * Profile KVM exit RIPs:
6348 */
6349 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6350 unsigned long rip = kvm_rip_read(vcpu);
6351 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6352 }
6353
cc578287
ZA		 6354 if (unlikely(vcpu->arch.tsc_always_catchup))
6355 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6356
5cfb1d5a
MT		 6357 if (vcpu->arch.apic_attention)
6358 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6359
851ba692 6360 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6361 return r;
6362
6363cancel_injection:
6364 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6365 if (unlikely(vcpu->arch.apic_attention))
6366 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6367out:
6368 return r;
6369}
b6c7a5dc 6370
09cec754 6371
851ba692 6372static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6373{
6374 int r;
f656ce01 6375 struct kvm *kvm = vcpu->kvm;
d7690175 6376
f656ce01 6377 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6378
6379 r = 1;
6380 while (r > 0) {
af585b92
GN		 6381 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6382 !vcpu->arch.apf.halted)
851ba692 6383 r = vcpu_enter_guest(vcpu);
d7690175 6384 else {
f656ce01 6385 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6386 kvm_vcpu_block(vcpu);
f656ce01 6387 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6388 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6389 kvm_apic_accept_events(vcpu);
09cec754
GN		 6390 switch(vcpu->arch.mp_state) {
6391 case KVM_MP_STATE_HALTED:
6aef266c 6392 vcpu->arch.pv.pv_unhalted = false;
d7690175 6393 vcpu->arch.mp_state =
09cec754
GN		 6394 KVM_MP_STATE_RUNNABLE;
6395 case KVM_MP_STATE_RUNNABLE:
af585b92 6396 vcpu->arch.apf.halted = false;
09cec754 6397 break;
66450a21
JK		 6398 case KVM_MP_STATE_INIT_RECEIVED:
6399 break;
09cec754
GN		 6400 default:
6401 r = -EINTR;
6402 break;
6403 }
6404 }
d7690175
MT		 6405 }
6406
09cec754
GN		 6407 if (r <= 0)
6408 break;
6409
6410 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6411 if (kvm_cpu_has_pending_timer(vcpu))
6412 kvm_inject_pending_timer_irqs(vcpu);
6413
851ba692 6414 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6415 r = -EINTR;
851ba692 6416 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6417 ++vcpu->stat.request_irq_exits;
6418 }
af585b92
GN		 6419
6420 kvm_check_async_pf_completion(vcpu);
6421
09cec754
GN		 6422 if (signal_pending(current)) {
6423 r = -EINTR;
851ba692 6424 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6425 ++vcpu->stat.signal_exits;
6426 }
6427 if (need_resched()) {
f656ce01 6428 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6429 cond_resched();
f656ce01 6430 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6431 }
b6c7a5dc
HB		 6432 }
6433
f656ce01 6434 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6435
6436 return r;
6437}
6438
716d51ab
GN		 6439static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6440{
6441 int r;
6442 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6443 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6444 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6445 if (r != EMULATE_DONE)
6446 return 0;
6447 return 1;
6448}
6449
6450static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6451{
6452 BUG_ON(!vcpu->arch.pio.count);
6453
6454 return complete_emulated_io(vcpu);
6455}
6456
f78146b0
AK		 6457/*
6458 * Implements the following, as a state machine:
6459 *
6460 * read:
6461 * for each fragment
87da7e66
XG		 6462 * for each mmio piece in the fragment
6463 * write gpa, len
6464 * exit
6465 * copy data
f78146b0
AK		 6466 * execute insn
6467 *
6468 * write:
6469 * for each fragment
87da7e66
XG		 6470 * for each mmio piece in the fragment
6471 * write gpa, len
6472 * copy data
6473 * exit
f78146b0 6474 */
716d51ab 6475static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6476{
6477 struct kvm_run *run = vcpu->run;
f78146b0 6478 struct kvm_mmio_fragment *frag;
87da7e66 6479 unsigned len;
5287f194 6480
716d51ab 6481 BUG_ON(!vcpu->mmio_needed);
5287f194 6482
716d51ab 6483 /* Complete previous fragment */
87da7e66
XG		 6484 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6485 len = min(8u, frag->len);
716d51ab 6486 if (!vcpu->mmio_is_write)
87da7e66
XG		 6487 memcpy(frag->data, run->mmio.data, len);
6488
6489 if (frag->len <= 8) {
6490 /* Switch to the next fragment. */
6491 frag++;
6492 vcpu->mmio_cur_fragment++;
6493 } else {
6494 /* Go forward to the next mmio piece. */
6495 frag->data += len;
6496 frag->gpa += len;
6497 frag->len -= len;
6498 }
6499
a08d3b3b 6500 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6501 vcpu->mmio_needed = 0;
0912c977
PB		 6502
6503 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6504 if (vcpu->mmio_is_write)
716d51ab
GN		 6505 return 1;
6506 vcpu->mmio_read_completed = 1;
6507 return complete_emulated_io(vcpu);
6508 }
87da7e66 6509
716d51ab
GN		 6510 run->exit_reason = KVM_EXIT_MMIO;
6511 run->mmio.phys_addr = frag->gpa;
6512 if (vcpu->mmio_is_write)
87da7e66
XG		 6513 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6514 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6515 run->mmio.is_write = vcpu->mmio_is_write;
6516 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6517 return 0;
5287f194
AK		 6518}
6519
716d51ab 6520
b6c7a5dc
HB		 6521int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6522{
6523 int r;
6524 sigset_t sigsaved;
6525
e5c30142
AK		 6526 if (!tsk_used_math(current) && init_fpu(current))
6527 return -ENOMEM;
6528
ac9f6dc0
AK		 6529 if (vcpu->sigset_active)
6530 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6531
a4535290 6532 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6533 kvm_vcpu_block(vcpu);
66450a21 6534 kvm_apic_accept_events(vcpu);
d7690175 6535 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6536 r = -EAGAIN;
6537 goto out;
b6c7a5dc
HB		 6538 }
6539
b6c7a5dc 6540 /* re-sync apic's tpr */
eea1cff9
AP		 6541 if (!irqchip_in_kernel(vcpu->kvm)) {
6542 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6543 r = -EINVAL;
6544 goto out;
6545 }
6546 }
b6c7a5dc 6547
716d51ab
GN		 6548 if (unlikely(vcpu->arch.complete_userspace_io)) {
6549 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6550 vcpu->arch.complete_userspace_io = NULL;
6551 r = cui(vcpu);
6552 if (r <= 0)
6553 goto out;
6554 } else
6555 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6556
851ba692 6557 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6558
6559out:
f1d86e46 6560 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6561 if (vcpu->sigset_active)
6562 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6563
b6c7a5dc
HB		 6564 return r;
6565}
6566
6567int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6568{
7ae441ea
GN		 6569 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6570 /*
6571 * We are here if userspace calls get_regs() in the middle of
6572 * instruction emulation. Registers state needs to be copied
4a969980 6573 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6574 * that usually, but some bad designed PV devices (vmware
6575 * backdoor interface) need this to work
6576 */
dd856efa 6577 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6578 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6579 }
5fdbf976
MT		 6580 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6581 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6582 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6583 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6584 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6585 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6586 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6587 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6588#ifdef CONFIG_X86_64
5fdbf976
MT		 6589 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6590 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6591 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6592 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6593 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6594 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6595 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6596 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6597#endif
6598
5fdbf976 6599 regs->rip = kvm_rip_read(vcpu);
91586a3b 6600 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6601
b6c7a5dc
HB		 6602 return 0;
6603}
6604
6605int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6606{
7ae441ea
GN		 6607 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6608 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6609
5fdbf976
MT		 6610 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6611 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6612 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6613 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6614 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6615 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6616 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6617 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6618#ifdef CONFIG_X86_64
5fdbf976
MT		 6619 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6620 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6621 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6622 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6623 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6624 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6625 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6626 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6627#endif
6628
5fdbf976 6629 kvm_rip_write(vcpu, regs->rip);
91586a3b 6630 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6631
b4f14abd
JK		 6632 vcpu->arch.exception.pending = false;
6633
3842d135
AK		 6634 kvm_make_request(KVM_REQ_EVENT, vcpu);
6635
b6c7a5dc
HB		 6636 return 0;
6637}
6638
b6c7a5dc
HB		 6639void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6640{
6641 struct kvm_segment cs;
6642
3e6e0aab 6643 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6644 *db = cs.db;
6645 *l = cs.l;
6646}
6647EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6648
6649int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6650 struct kvm_sregs *sregs)
6651{
89a27f4d 6652 struct desc_ptr dt;
b6c7a5dc 6653
3e6e0aab
GT		 6654 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6655 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6656 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6657 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6658 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6659 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6660
3e6e0aab
GT		 6661 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6662 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6663
6664 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6665 sregs->idt.limit = dt.size;
6666 sregs->idt.base = dt.address;
b6c7a5dc 6667 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6668 sregs->gdt.limit = dt.size;
6669 sregs->gdt.base = dt.address;
b6c7a5dc 6670
4d4ec087 6671 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6672 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6673 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6674 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6675 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6676 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6677 sregs->apic_base = kvm_get_apic_base(vcpu);
6678
923c61bb 6679 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6680
36752c9b 6681 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6682 set_bit(vcpu->arch.interrupt.nr,
6683 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6684
b6c7a5dc
HB		 6685 return 0;
6686}
6687
62d9f0db
MT		 6688int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6689 struct kvm_mp_state *mp_state)
6690{
66450a21 6691 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6692 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6693 vcpu->arch.pv.pv_unhalted)
6694 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6695 else
6696 mp_state->mp_state = vcpu->arch.mp_state;
6697
62d9f0db
MT		 6698 return 0;
6699}
6700
6701int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6702 struct kvm_mp_state *mp_state)
6703{
66450a21
JK		 6704 if (!kvm_vcpu_has_lapic(vcpu) &&
6705 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6706 return -EINVAL;
6707
6708 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6709 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6710 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6711 } else
6712 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6713 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6714 return 0;
6715}
6716
7f3d35fd
KW		 6717int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6718 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6719{
9d74191a 6720 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6721 int ret;
e01c2426 6722
8ec4722d 6723 init_emulate_ctxt(vcpu);
c697518a 6724
7f3d35fd 6725 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6726 has_error_code, error_code);
c697518a 6727
c697518a 6728 if (ret)
19d04437 6729 return EMULATE_FAIL;
37817f29 6730
9d74191a
TY		 6731 kvm_rip_write(vcpu, ctxt->eip);
6732 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6733 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6734 return EMULATE_DONE;
37817f29
IE		 6735}
6736EXPORT_SYMBOL_GPL(kvm_task_switch);
6737
b6c7a5dc
HB		 6738int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6739 struct kvm_sregs *sregs)
6740{
58cb628d 6741 struct msr_data apic_base_msr;
b6c7a5dc 6742 int mmu_reset_needed = 0;
63f42e02 6743 int pending_vec, max_bits, idx;
89a27f4d 6744 struct desc_ptr dt;
b6c7a5dc 6745
6d1068b3
PM		 6746 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6747 return -EINVAL;
6748
89a27f4d
GN		 6749 dt.size = sregs->idt.limit;
6750 dt.address = sregs->idt.base;
b6c7a5dc 6751 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6752 dt.size = sregs->gdt.limit;
6753 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6754 kvm_x86_ops->set_gdt(vcpu, &dt);
6755
ad312c7c 6756 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6757 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6758 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6759 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6760
2d3ad1f4 6761 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6762
f6801dff 6763 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6764 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6765 apic_base_msr.data = sregs->apic_base;
6766 apic_base_msr.host_initiated = true;
6767 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6768
4d4ec087 6769 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6770 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6771 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6772
fc78f519 6773 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6774 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6775 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6776 kvm_update_cpuid(vcpu);
63f42e02
XG		 6777
6778 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6779 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6780 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6781 mmu_reset_needed = 1;
6782 }
63f42e02 6783 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6784
6785 if (mmu_reset_needed)
6786 kvm_mmu_reset_context(vcpu);
6787
a50abc3b 6788 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6789 pending_vec = find_first_bit(
6790 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6791 if (pending_vec < max_bits) {
66fd3f7f 6792 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6793 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6794 }
6795
3e6e0aab
GT		 6796 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6797 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6798 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6799 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6800 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6801 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6802
3e6e0aab
GT		 6803 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6804 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6805
5f0269f5
ME		 6806 update_cr8_intercept(vcpu);
6807
9c3e4aab 6808 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6809 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6810 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6811 !is_protmode(vcpu))
9c3e4aab
MT		 6812 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6813
3842d135
AK		 6814 kvm_make_request(KVM_REQ_EVENT, vcpu);
6815
b6c7a5dc
HB		 6816 return 0;
6817}
6818
d0bfb940
JK		 6819int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6820 struct kvm_guest_debug *dbg)
b6c7a5dc 6821{
355be0b9 6822 unsigned long rflags;
ae675ef0 6823 int i, r;
b6c7a5dc 6824
4f926bf2
JK		 6825 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6826 r = -EBUSY;
6827 if (vcpu->arch.exception.pending)
2122ff5e 6828 goto out;
4f926bf2
JK		 6829 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6830 kvm_queue_exception(vcpu, DB_VECTOR);
6831 else
6832 kvm_queue_exception(vcpu, BP_VECTOR);
6833 }
6834
91586a3b
JK		 6835 /*
6836 * Read rflags as long as potentially injected trace flags are still
6837 * filtered out.
6838 */
6839 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6840
6841 vcpu->guest_debug = dbg->control;
6842 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6843 vcpu->guest_debug = 0;
6844
6845 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6846 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6847 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6848 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6849 } else {
6850 for (i = 0; i < KVM_NR_DB_REGS; i++)
6851 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6852 }
c8639010 6853 kvm_update_dr7(vcpu);
ae675ef0 6854
f92653ee
JK		 6855 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6856 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6857 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6858
91586a3b
JK		 6859 /*
6860 * Trigger an rflags update that will inject or remove the trace
6861 * flags.
6862 */
6863 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6864
c8639010 6865 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6866
4f926bf2 6867 r = 0;
d0bfb940 6868
2122ff5e 6869out:
b6c7a5dc
HB		 6870
6871 return r;
6872}
6873
8b006791
ZX		 6874/*
6875 * Translate a guest virtual address to a guest physical address.
6876 */
6877int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6878 struct kvm_translation *tr)
6879{
6880 unsigned long vaddr = tr->linear_address;
6881 gpa_t gpa;
f656ce01 6882 int idx;
8b006791 6883
f656ce01 6884 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6885 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6886 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6887 tr->physical_address = gpa;
6888 tr->valid = gpa != UNMAPPED_GVA;
6889 tr->writeable = 1;
6890 tr->usermode = 0;
8b006791
ZX		 6891
6892 return 0;
6893}
6894
d0752060
HB		 6895int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6896{
98918833
SY		 6897 struct i387_fxsave_struct *fxsave =
6898 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6899
d0752060
HB		 6900 memcpy(fpu->fpr, fxsave->st_space, 128);
6901 fpu->fcw = fxsave->cwd;
6902 fpu->fsw = fxsave->swd;
6903 fpu->ftwx = fxsave->twd;
6904 fpu->last_opcode = fxsave->fop;
6905 fpu->last_ip = fxsave->rip;
6906 fpu->last_dp = fxsave->rdp;
6907 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6908
d0752060
HB		 6909 return 0;
6910}
6911
6912int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6913{
98918833
SY		 6914 struct i387_fxsave_struct *fxsave =
6915 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6916
d0752060
HB		 6917 memcpy(fxsave->st_space, fpu->fpr, 128);
6918 fxsave->cwd = fpu->fcw;
6919 fxsave->swd = fpu->fsw;
6920 fxsave->twd = fpu->ftwx;
6921 fxsave->fop = fpu->last_opcode;
6922 fxsave->rip = fpu->last_ip;
6923 fxsave->rdp = fpu->last_dp;
6924 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6925
d0752060
HB		 6926 return 0;
6927}
6928
10ab25cd 6929int fx_init(struct kvm_vcpu *vcpu)
d0752060 6930{
10ab25cd
JK		 6931 int err;
6932
6933 err = fpu_alloc(&vcpu->arch.guest_fpu);
6934 if (err)
6935 return err;
6936
98918833 6937 fpu_finit(&vcpu->arch.guest_fpu);
df1daba7
PB		 6938 if (cpu_has_xsaves)
6939 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
6940 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 6941
2acf923e
DC		 6942 /*
6943 * Ensure guest xcr0 is valid for loading
6944 */
6945 vcpu->arch.xcr0 = XSTATE_FP;
6946
ad312c7c 6947 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6948
6949 return 0;
d0752060
HB		 6950}
6951EXPORT_SYMBOL_GPL(fx_init);
6952
98918833
SY		 6953static void fx_free(struct kvm_vcpu *vcpu)
6954{
6955 fpu_free(&vcpu->arch.guest_fpu);
6956}
6957
d0752060
HB		 6958void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6959{
2608d7a1 6960 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6961 return;
6962
2acf923e
DC		 6963 /*
6964 * Restore all possible states in the guest,
6965 * and assume host would use all available bits.
6966 * Guest xcr0 would be loaded later.
6967 */
6968 kvm_put_guest_xcr0(vcpu);
d0752060 6969 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6970 __kernel_fpu_begin();
98918833 6971 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6972 trace_kvm_fpu(1);
d0752060 6973}
d0752060
HB		 6974
6975void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6976{
2acf923e
DC		 6977 kvm_put_guest_xcr0(vcpu);
6978
d0752060
HB		 6979 if (!vcpu->guest_fpu_loaded)
6980 return;
6981
6982 vcpu->guest_fpu_loaded = 0;
98918833 6983 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6984 __kernel_fpu_end();
f096ed85 6985 ++vcpu->stat.fpu_reload;
a8eeb04a 6986 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6987 trace_kvm_fpu(0);
d0752060 6988}
e9b11c17
ZX		 6989
6990void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6991{
12f9a48f 6992 kvmclock_reset(vcpu);
7f1ea208 6993
f5f48ee1 6994 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6995 fx_free(vcpu);
e9b11c17
ZX		 6996 kvm_x86_ops->vcpu_free(vcpu);
6997}
6998
6999struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7000 unsigned int id)
7001{
6755bae8
ZA		 7002 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7003 printk_once(KERN_WARNING
7004 "kvm: SMP vm created on host with unstable TSC; "
7005 "guest TSC will not be reliable\n");
26e5215f
AK		 7006 return kvm_x86_ops->vcpu_create(kvm, id);
7007}
e9b11c17 7008
26e5215f
AK		 7009int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7010{
7011 int r;
e9b11c17 7012
0bed3b56 7013 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7014 r = vcpu_load(vcpu);
7015 if (r)
7016 return r;
57f252f2 7017 kvm_vcpu_reset(vcpu);
8a3c1a33 7018 kvm_mmu_setup(vcpu);
e9b11c17 7019 vcpu_put(vcpu);
e9b11c17 7020
26e5215f 7021 return r;
e9b11c17
ZX		 7022}
7023
31928aa5 7024void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7025{
8fe8ab46 7026 struct msr_data msr;
332967a3 7027 struct kvm *kvm = vcpu->kvm;
42897d86 7028
31928aa5
DD		 7029 if (vcpu_load(vcpu))
7030 return;
8fe8ab46
WA		 7031 msr.data = 0x0;
7032 msr.index = MSR_IA32_TSC;
7033 msr.host_initiated = true;
7034 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7035 vcpu_put(vcpu);
7036
332967a3
AJ		 7037 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7038 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7039}
7040
d40ccc62 7041void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7042{
9fc77441 7043 int r;
344d9588
GN		 7044 vcpu->arch.apf.msr_val = 0;
7045
9fc77441
MT		 7046 r = vcpu_load(vcpu);
7047 BUG_ON(r);
e9b11c17
ZX		 7048 kvm_mmu_unload(vcpu);
7049 vcpu_put(vcpu);
7050
98918833 7051 fx_free(vcpu);
e9b11c17
ZX		 7052 kvm_x86_ops->vcpu_free(vcpu);
7053}
7054
66450a21 7055void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 7056{
7460fb4a
AK		 7057 atomic_set(&vcpu->arch.nmi_queued, 0);
7058 vcpu->arch.nmi_pending = 0;
448fa4a9 7059 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7060 kvm_clear_interrupt_queue(vcpu);
7061 kvm_clear_exception_queue(vcpu);
448fa4a9 7062
42dbaa5a 7063 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 7064 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7065 kvm_update_dr6(vcpu);
42dbaa5a 7066 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7067 kvm_update_dr7(vcpu);
42dbaa5a 7068
3842d135 7069 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7070 vcpu->arch.apf.msr_val = 0;
c9aaa895 7071 vcpu->arch.st.msr_val = 0;
3842d135 7072
12f9a48f
GC		 7073 kvmclock_reset(vcpu);
7074
af585b92
GN		 7075 kvm_clear_async_pf_completion_queue(vcpu);
7076 kvm_async_pf_hash_reset(vcpu);
7077 vcpu->arch.apf.halted = false;
3842d135 7078
f5132b01
GN		 7079 kvm_pmu_reset(vcpu);
7080
66f7b72e
JS		 7081 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7082 vcpu->arch.regs_avail = ~0;
7083 vcpu->arch.regs_dirty = ~0;
7084
57f252f2 7085 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7086}
7087
2b4a273b 7088void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7089{
7090 struct kvm_segment cs;
7091
7092 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7093 cs.selector = vector << 8;
7094 cs.base = vector << 12;
7095 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7096 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7097}
7098
13a34e06 7099int kvm_arch_hardware_enable(void)
e9b11c17 7100{
ca84d1a2
ZA		 7101 struct kvm *kvm;
7102 struct kvm_vcpu *vcpu;
7103 int i;
0dd6a6ed
ZA		 7104 int ret;
7105 u64 local_tsc;
7106 u64 max_tsc = 0;
7107 bool stable, backwards_tsc = false;
18863bdd
AK		 7108
7109 kvm_shared_msr_cpu_online();
13a34e06 7110 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7111 if (ret != 0)
7112 return ret;
7113
7114 local_tsc = native_read_tsc();
7115 stable = !check_tsc_unstable();
7116 list_for_each_entry(kvm, &vm_list, vm_list) {
7117 kvm_for_each_vcpu(i, vcpu, kvm) {
7118 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7119 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7120 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7121 backwards_tsc = true;
7122 if (vcpu->arch.last_host_tsc > max_tsc)
7123 max_tsc = vcpu->arch.last_host_tsc;
7124 }
7125 }
7126 }
7127
7128 /*
7129 * Sometimes, even reliable TSCs go backwards. This happens on
7130 * platforms that reset TSC during suspend or hibernate actions, but
7131 * maintain synchronization. We must compensate. Fortunately, we can
7132 * detect that condition here, which happens early in CPU bringup,
7133 * before any KVM threads can be running. Unfortunately, we can't
7134 * bring the TSCs fully up to date with real time, as we aren't yet far
7135 * enough into CPU bringup that we know how much real time has actually
7136 * elapsed; our helper function, get_kernel_ns() will be using boot
7137 * variables that haven't been updated yet.
7138 *
7139 * So we simply find the maximum observed TSC above, then record the
7140 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7141 * the adjustment will be applied. Note that we accumulate
7142 * adjustments, in case multiple suspend cycles happen before some VCPU
7143 * gets a chance to run again. In the event that no KVM threads get a
7144 * chance to run, we will miss the entire elapsed period, as we'll have
7145 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7146 * loose cycle time. This isn't too big a deal, since the loss will be
7147 * uniform across all VCPUs (not to mention the scenario is extremely
7148 * unlikely). It is possible that a second hibernate recovery happens
7149 * much faster than a first, causing the observed TSC here to be
7150 * smaller; this would require additional padding adjustment, which is
7151 * why we set last_host_tsc to the local tsc observed here.
7152 *
7153 * N.B. - this code below runs only on platforms with reliable TSC,
7154 * as that is the only way backwards_tsc is set above. Also note
7155 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7156 * have the same delta_cyc adjustment applied if backwards_tsc
7157 * is detected. Note further, this adjustment is only done once,
7158 * as we reset last_host_tsc on all VCPUs to stop this from being
7159 * called multiple times (one for each physical CPU bringup).
7160 *
4a969980 7161 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7162 * will be compensated by the logic in vcpu_load, which sets the TSC to
7163 * catchup mode. This will catchup all VCPUs to real time, but cannot
7164 * guarantee that they stay in perfect synchronization.
7165 */
7166 if (backwards_tsc) {
7167 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7168 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7169 list_for_each_entry(kvm, &vm_list, vm_list) {
7170 kvm_for_each_vcpu(i, vcpu, kvm) {
7171 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7172 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7173 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7174 }
7175
7176 /*
7177 * We have to disable TSC offset matching.. if you were
7178 * booting a VM while issuing an S4 host suspend....
7179 * you may have some problem. Solving this issue is
7180 * left as an exercise to the reader.
7181 */
7182 kvm->arch.last_tsc_nsec = 0;
7183 kvm->arch.last_tsc_write = 0;
7184 }
7185
7186 }
7187 return 0;
e9b11c17
ZX		 7188}
7189
13a34e06 7190void kvm_arch_hardware_disable(void)
e9b11c17 7191{
13a34e06
RK		 7192 kvm_x86_ops->hardware_disable();
7193 drop_user_return_notifiers();
e9b11c17
ZX		 7194}
7195
7196int kvm_arch_hardware_setup(void)
7197{
7198 return kvm_x86_ops->hardware_setup();
7199}
7200
7201void kvm_arch_hardware_unsetup(void)
7202{
7203 kvm_x86_ops->hardware_unsetup();
7204}
7205
7206void kvm_arch_check_processor_compat(void *rtn)
7207{
7208 kvm_x86_ops->check_processor_compatibility(rtn);
7209}
7210
3e515705
AK		 7211bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7212{
7213 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7214}
7215
54e9818f
GN		 7216struct static_key kvm_no_apic_vcpu __read_mostly;
7217
e9b11c17
ZX		 7218int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7219{
7220 struct page *page;
7221 struct kvm *kvm;
7222 int r;
7223
7224 BUG_ON(vcpu->kvm == NULL);
7225 kvm = vcpu->kvm;
7226
6aef266c 7227 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7228 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7229 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7230 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7231 else
a4535290 7232 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7233
7234 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7235 if (!page) {
7236 r = -ENOMEM;
7237 goto fail;
7238 }
ad312c7c 7239 vcpu->arch.pio_data = page_address(page);
e9b11c17 7240
cc578287 7241 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7242
e9b11c17
ZX		 7243 r = kvm_mmu_create(vcpu);
7244 if (r < 0)
7245 goto fail_free_pio_data;
7246
7247 if (irqchip_in_kernel(kvm)) {
7248 r = kvm_create_lapic(vcpu);
7249 if (r < 0)
7250 goto fail_mmu_destroy;
54e9818f
GN		 7251 } else
7252 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7253
890ca9ae
HY		 7254 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7255 GFP_KERNEL);
7256 if (!vcpu->arch.mce_banks) {
7257 r = -ENOMEM;
443c39bc 7258 goto fail_free_lapic;
890ca9ae
HY		 7259 }
7260 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7261
f1797359
WY		 7262 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7263 r = -ENOMEM;
f5f48ee1 7264 goto fail_free_mce_banks;
f1797359 7265 }
f5f48ee1 7266
66f7b72e
JS		 7267 r = fx_init(vcpu);
7268 if (r)
7269 goto fail_free_wbinvd_dirty_mask;
7270
ba904635 7271 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7272 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7273
7274 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7275 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7276
af585b92 7277 kvm_async_pf_hash_reset(vcpu);
f5132b01 7278 kvm_pmu_init(vcpu);
af585b92 7279
e9b11c17 7280 return 0;
66f7b72e
JS		 7281fail_free_wbinvd_dirty_mask:
7282 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7283fail_free_mce_banks:
7284 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7285fail_free_lapic:
7286 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7287fail_mmu_destroy:
7288 kvm_mmu_destroy(vcpu);
7289fail_free_pio_data:
ad312c7c 7290 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7291fail:
7292 return r;
7293}
7294
7295void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7296{
f656ce01
MT		 7297 int idx;
7298
f5132b01 7299 kvm_pmu_destroy(vcpu);
36cb93fd 7300 kfree(vcpu->arch.mce_banks);
e9b11c17 7301 kvm_free_lapic(vcpu);
f656ce01 7302 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7303 kvm_mmu_destroy(vcpu);
f656ce01 7304 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7305 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7306 if (!irqchip_in_kernel(vcpu->kvm))
7307 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7308}
d19a9cd2 7309
e790d9ef
RK		 7310void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7311{
ae97a3b8 7312 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7313}
7314
e08b9637 7315int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7316{
e08b9637
CO		 7317 if (type)
7318 return -EINVAL;
7319
6ef768fa 7320 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7321 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7322 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7323 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7324 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7325
5550af4d
SY		 7326 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7327 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7328 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7329 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7330 &kvm->arch.irq_sources_bitmap);
5550af4d 7331
038f8c11 7332 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7333 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7334 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7335
7336 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7337
7e44e449 7338 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7339 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7340
d89f5eff 7341 return 0;
d19a9cd2
ZX		 7342}
7343
7344static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7345{
9fc77441
MT		 7346 int r;
7347 r = vcpu_load(vcpu);
7348 BUG_ON(r);
d19a9cd2
ZX		 7349 kvm_mmu_unload(vcpu);
7350 vcpu_put(vcpu);
7351}
7352
7353static void kvm_free_vcpus(struct kvm *kvm)
7354{
7355 unsigned int i;
988a2cae 7356 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7357
7358 /*
7359 * Unpin any mmu pages first.
7360 */
af585b92
GN		 7361 kvm_for_each_vcpu(i, vcpu, kvm) {
7362 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7363 kvm_unload_vcpu_mmu(vcpu);
af585b92 7364 }
988a2cae
GN		 7365 kvm_for_each_vcpu(i, vcpu, kvm)
7366 kvm_arch_vcpu_free(vcpu);
7367
7368 mutex_lock(&kvm->lock);
7369 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7370 kvm->vcpus[i] = NULL;
d19a9cd2 7371
988a2cae
GN		 7372 atomic_set(&kvm->online_vcpus, 0);
7373 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7374}
7375
ad8ba2cd
SY		 7376void kvm_arch_sync_events(struct kvm *kvm)
7377{
332967a3 7378 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7379 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7380 kvm_free_all_assigned_devices(kvm);
aea924f6 7381 kvm_free_pit(kvm);
ad8ba2cd
SY		 7382}
7383
d19a9cd2
ZX		 7384void kvm_arch_destroy_vm(struct kvm *kvm)
7385{
27469d29
AH		 7386 if (current->mm == kvm->mm) {
7387 /*
7388 * Free memory regions allocated on behalf of userspace,
7389 * unless the the memory map has changed due to process exit
7390 * or fd copying.
7391 */
7392 struct kvm_userspace_memory_region mem;
7393 memset(&mem, 0, sizeof(mem));
7394 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7395 kvm_set_memory_region(kvm, &mem);
7396
7397 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7398 kvm_set_memory_region(kvm, &mem);
7399
7400 mem.slot = TSS_PRIVATE_MEMSLOT;
7401 kvm_set_memory_region(kvm, &mem);
7402 }
6eb55818 7403 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7404 kfree(kvm->arch.vpic);
7405 kfree(kvm->arch.vioapic);
d19a9cd2 7406 kvm_free_vcpus(kvm);
1e08ec4a 7407 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7408}
0de10343 7409
5587027c 7410void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7411 struct kvm_memory_slot *dont)
7412{
7413 int i;
7414
d89cc617
TY		 7415 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7416 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7417 kvm_kvfree(free->arch.rmap[i]);
7418 free->arch.rmap[i] = NULL;
77d11309 7419 }
d89cc617
TY		 7420 if (i == 0)
7421 continue;
7422
7423 if (!dont || free->arch.lpage_info[i - 1] !=
7424 dont->arch.lpage_info[i - 1]) {
7425 kvm_kvfree(free->arch.lpage_info[i - 1]);
7426 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7427 }
7428 }
7429}
7430
5587027c
AK		 7431int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7432 unsigned long npages)
db3fe4eb
TY		 7433{
7434 int i;
7435
d89cc617 7436 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7437 unsigned long ugfn;
7438 int lpages;
d89cc617 7439 int level = i + 1;
db3fe4eb
TY		 7440
7441 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7442 slot->base_gfn, level) + 1;
7443
d89cc617
TY		 7444 slot->arch.rmap[i] =
7445 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7446 if (!slot->arch.rmap[i])
77d11309 7447 goto out_free;
d89cc617
TY		 7448 if (i == 0)
7449 continue;
77d11309 7450
d89cc617
TY		 7451 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7452 sizeof(*slot->arch.lpage_info[i - 1]));
7453 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7454 goto out_free;
7455
7456 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7457 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7458 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7459 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7460 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7461 /*
7462 * If the gfn and userspace address are not aligned wrt each
7463 * other, or if explicitly asked to, disable large page
7464 * support for this slot
7465 */
7466 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7467 !kvm_largepages_enabled()) {
7468 unsigned long j;
7469
7470 for (j = 0; j < lpages; ++j)
d89cc617 7471 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7472 }
7473 }
7474
7475 return 0;
7476
7477out_free:
d89cc617
TY		 7478 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7479 kvm_kvfree(slot->arch.rmap[i]);
7480 slot->arch.rmap[i] = NULL;
7481 if (i == 0)
7482 continue;
7483
7484 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7485 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7486 }
7487 return -ENOMEM;
7488}
7489
e59dbe09
TY		 7490void kvm_arch_memslots_updated(struct kvm *kvm)
7491{
e6dff7d1
TY		 7492 /*
7493 * memslots->generation has been incremented.
7494 * mmio generation may have reached its maximum value.
7495 */
7496 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7497}
7498
f7784b8e
MT		 7499int kvm_arch_prepare_memory_region(struct kvm *kvm,
7500 struct kvm_memory_slot *memslot,
f7784b8e 7501 struct kvm_userspace_memory_region *mem,
7b6195a9 7502 enum kvm_mr_change change)
0de10343 7503{
7a905b14
TY		 7504 /*
7505 * Only private memory slots need to be mapped here since
7506 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7507 */
7b6195a9 7508 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7509 unsigned long userspace_addr;
604b38ac 7510
7a905b14
TY		 7511 /*
7512 * MAP_SHARED to prevent internal slot pages from being moved
7513 * by fork()/COW.
7514 */
7b6195a9 7515 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7516 PROT_READ | PROT_WRITE,
7517 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7518
7a905b14
TY		 7519 if (IS_ERR((void *)userspace_addr))
7520 return PTR_ERR((void *)userspace_addr);
604b38ac 7521
7a905b14 7522 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7523 }
7524
f7784b8e
MT		 7525 return 0;
7526}
7527
7528void kvm_arch_commit_memory_region(struct kvm *kvm,
7529 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7530 const struct kvm_memory_slot *old,
7531 enum kvm_mr_change change)
f7784b8e
MT		 7532{
7533
8482644a 7534 int nr_mmu_pages = 0;
f7784b8e 7535
8482644a 7536 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7537 int ret;
7538
8482644a
TY		 7539 ret = vm_munmap(old->userspace_addr,
7540 old->npages * PAGE_SIZE);
f7784b8e
MT		 7541 if (ret < 0)
7542 printk(KERN_WARNING
7543 "kvm_vm_ioctl_set_memory_region: "
7544 "failed to munmap memory\n");
7545 }
7546
48c0e4e9
XG		 7547 if (!kvm->arch.n_requested_mmu_pages)
7548 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7549
48c0e4e9 7550 if (nr_mmu_pages)
0de10343 7551 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7552 /*
7553 * Write protect all pages for dirty logging.
c126d94f
XG		 7554 *
7555 * All the sptes including the large sptes which point to this
7556 * slot are set to readonly. We can not create any new large
7557 * spte on this slot until the end of the logging.
7558 *
7559 * See the comments in fast_page_fault().
c972f3b1 7560 */
8482644a 7561 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7562 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7563}
1d737c8a 7564
2df72e9b 7565void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7566{
6ca18b69 7567 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7568}
7569
2df72e9b
MT		 7570void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7571 struct kvm_memory_slot *slot)
7572{
6ca18b69 7573 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7574}
7575
1d737c8a
ZX		 7576int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7577{
b6b8a145
JK		 7578 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7579 kvm_x86_ops->check_nested_events(vcpu, false);
7580
af585b92
GN		 7581 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7582 !vcpu->arch.apf.halted)
7583 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7584 || kvm_apic_has_events(vcpu)
6aef266c 7585 || vcpu->arch.pv.pv_unhalted
7460fb4a 7586 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7587 (kvm_arch_interrupt_allowed(vcpu) &&
7588 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7589}
5736199a 7590
b6d33834 7591int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7592{
b6d33834 7593 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7594}
78646121
GN		 7595
7596int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7597{
7598 return kvm_x86_ops->interrupt_allowed(vcpu);
7599}
229456fc 7600
82b32774 7601unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7602{
82b32774
NA		 7603 if (is_64_bit_mode(vcpu))
7604 return kvm_rip_read(vcpu);
7605 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7606 kvm_rip_read(vcpu));
7607}
7608EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7609
82b32774
NA		 7610bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7611{
7612 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7613}
7614EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7615
94fe45da
JK		 7616unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7617{
7618 unsigned long rflags;
7619
7620 rflags = kvm_x86_ops->get_rflags(vcpu);
7621 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7622 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7623 return rflags;
7624}
7625EXPORT_SYMBOL_GPL(kvm_get_rflags);
7626
6addfc42 7627static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7628{
7629 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7630 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7631 rflags |= X86_EFLAGS_TF;
94fe45da 7632 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7633}
7634
7635void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7636{
7637 __kvm_set_rflags(vcpu, rflags);
3842d135 7638 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7639}
7640EXPORT_SYMBOL_GPL(kvm_set_rflags);
7641
56028d08
GN		 7642void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7643{
7644 int r;
7645
fb67e14f 7646 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7647 work->wakeup_all)
56028d08
GN		 7648 return;
7649
7650 r = kvm_mmu_reload(vcpu);
7651 if (unlikely(r))
7652 return;
7653
fb67e14f
XG		 7654 if (!vcpu->arch.mmu.direct_map &&
7655 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7656 return;
7657
56028d08
GN		 7658 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7659}
7660
af585b92
GN		 7661static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7662{
7663 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7664}
7665
7666static inline u32 kvm_async_pf_next_probe(u32 key)
7667{
7668 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7669}
7670
7671static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7672{
7673 u32 key = kvm_async_pf_hash_fn(gfn);
7674
7675 while (vcpu->arch.apf.gfns[key] != ~0)
7676 key = kvm_async_pf_next_probe(key);
7677
7678 vcpu->arch.apf.gfns[key] = gfn;
7679}
7680
7681static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7682{
7683 int i;
7684 u32 key = kvm_async_pf_hash_fn(gfn);
7685
7686 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7687 (vcpu->arch.apf.gfns[key] != gfn &&
7688 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7689 key = kvm_async_pf_next_probe(key);
7690
7691 return key;
7692}
7693
7694bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7695{
7696 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7697}
7698
7699static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7700{
7701 u32 i, j, k;
7702
7703 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7704 while (true) {
7705 vcpu->arch.apf.gfns[i] = ~0;
7706 do {
7707 j = kvm_async_pf_next_probe(j);
7708 if (vcpu->arch.apf.gfns[j] == ~0)
7709 return;
7710 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7711 /*
7712 * k lies cyclically in ]i,j]
7713 * | i.k.j |
7714 * |....j i.k.| or |.k..j i...|
7715 */
7716 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7717 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7718 i = j;
7719 }
7720}
7721
7c90705b
GN		 7722static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7723{
7724
7725 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7726 sizeof(val));
7727}
7728
af585b92
GN		 7729void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7730 struct kvm_async_pf *work)
7731{
6389ee94
AK		 7732 struct x86_exception fault;
7733
7c90705b 7734 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7735 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7736
7737 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7738 (vcpu->arch.apf.send_user_only &&
7739 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7740 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7741 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7742 fault.vector = PF_VECTOR;
7743 fault.error_code_valid = true;
7744 fault.error_code = 0;
7745 fault.nested_page_fault = false;
7746 fault.address = work->arch.token;
7747 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7748 }
af585b92
GN		 7749}
7750
7751void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7752 struct kvm_async_pf *work)
7753{
6389ee94
AK		 7754 struct x86_exception fault;
7755
7c90705b 7756 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7757 if (work->wakeup_all)
7c90705b
GN		 7758 work->arch.token = ~0; /* broadcast wakeup */
7759 else
7760 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7761
7762 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7763 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7764 fault.vector = PF_VECTOR;
7765 fault.error_code_valid = true;
7766 fault.error_code = 0;
7767 fault.nested_page_fault = false;
7768 fault.address = work->arch.token;
7769 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7770 }
e6d53e3b 7771 vcpu->arch.apf.halted = false;
a4fa1635 7772 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7773}
7774
7775bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7776{
7777 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7778 return true;
7779 else
7780 return !kvm_event_needs_reinjection(vcpu) &&
7781 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7782}
7783
e0f0bbc5
AW		 7784void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7785{
7786 atomic_inc(&kvm->arch.noncoherent_dma_count);
7787}
7788EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7789
7790void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7791{
7792 atomic_dec(&kvm->arch.noncoherent_dma_count);
7793}
7794EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7795
7796bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7797{
7798 return atomic_read(&kvm->arch.noncoherent_dma_count);
7799}
7800EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7801
229456fc
MT		 7802EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7803EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7804EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7805EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7806EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7807EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7808EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7809EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7810EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7811EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7812EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7813EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7814EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7815EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux kernel - Deliverables
This page took 1.336326 seconds and 5 git commands to generate.