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KVM: x86: cleanup unused local variable
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 268 unsigned nr, bool has_error, u32 error_code,
269 bool reinject)
3fd28fce
ED		 270{
271 u32 prev_nr;
272 int class1, class2;
273
274 if (!vcpu->arch.exception.pending) {
275 queue:
276 vcpu->arch.exception.pending = true;
277 vcpu->arch.exception.has_error_code = has_error;
278 vcpu->arch.exception.nr = nr;
279 vcpu->arch.exception.error_code = error_code;
3f0fd292 280 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 281 return;
282 }
283
284 /* to check exception */
285 prev_nr = vcpu->arch.exception.nr;
286 if (prev_nr == DF_VECTOR) {
287 /* triple fault -> shutdown */
288 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
289 return;
290 }
291 class1 = exception_class(prev_nr);
292 class2 = exception_class(nr);
293 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
294 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
295 /* generate double fault per SDM Table 5-5 */
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = true;
298 vcpu->arch.exception.nr = DF_VECTOR;
299 vcpu->arch.exception.error_code = 0;
300 } else
301 /* replace previous exception with a new one in a hope
302 that instruction re-execution will regenerate lost
303 exception */
304 goto queue;
305}
306
298101da
AK		 307void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
308{
ce7ddec4 309 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 310}
311EXPORT_SYMBOL_GPL(kvm_queue_exception);
312
ce7ddec4
JR		 313void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
315 kvm_multiple_exception(vcpu, nr, false, 0, true);
316}
317EXPORT_SYMBOL_GPL(kvm_requeue_exception);
318
c3c91fee
AK		 319void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
320 u32 error_code)
321{
322 ++vcpu->stat.pf_guest;
ad312c7c 323 vcpu->arch.cr2 = addr;
c3c91fee
AK		 324 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
325}
326
3419ffc8
SY		 327void kvm_inject_nmi(struct kvm_vcpu *vcpu)
328{
329 vcpu->arch.nmi_pending = 1;
330}
331EXPORT_SYMBOL_GPL(kvm_inject_nmi);
332
298101da
AK		 333void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
334{
ce7ddec4 335 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
338
ce7ddec4
JR		 339void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
340{
341 kvm_multiple_exception(vcpu, nr, true, error_code, true);
342}
343EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
344
0a79b009
AK		 345/*
346 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
347 * a #GP and return false.
348 */
349bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 350{
0a79b009
AK		 351 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
352 return true;
353 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
354 return false;
298101da 355}
0a79b009 356EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 357
a03490ed
CO		 358/*
359 * Load the pae pdptrs. Return true is they are all valid.
360 */
361int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
362{
363 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
364 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
365 int i;
366 int ret;
ad312c7c 367 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 368
a03490ed
CO		 369 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
370 offset * sizeof(u64), sizeof(pdpte));
371 if (ret < 0) {
372 ret = 0;
373 goto out;
374 }
375 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 376 if (is_present_gpte(pdpte[i]) &&
20c466b5 377 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 378 ret = 0;
379 goto out;
380 }
381 }
382 ret = 1;
383
ad312c7c 384 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 385 __set_bit(VCPU_EXREG_PDPTR,
386 (unsigned long *)&vcpu->arch.regs_avail);
387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 389out:
a03490ed
CO		 390
391 return ret;
392}
cc4b6871 393EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 394
d835dfec
AK		 395static bool pdptrs_changed(struct kvm_vcpu *vcpu)
396{
ad312c7c 397 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 398 bool changed = true;
399 int r;
400
401 if (is_long_mode(vcpu) || !is_pae(vcpu))
402 return false;
403
6de4f3ad
AK		 404 if (!test_bit(VCPU_EXREG_PDPTR,
405 (unsigned long *)&vcpu->arch.regs_avail))
406 return true;
407
ad312c7c 408 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 409 if (r < 0)
410 goto out;
ad312c7c 411 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 412out:
d835dfec
AK		 413
414 return changed;
415}
416
0f12244f 417static int __kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 418{
aad82703
SY		 419 unsigned long old_cr0 = kvm_read_cr0(vcpu);
420 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
421 X86_CR0_CD | X86_CR0_NW;
422
f9a48e6a
AK		 423 cr0 |= X86_CR0_ET;
424
ab344828 425#ifdef CONFIG_X86_64
0f12244f
GN		 426 if (cr0 & 0xffffffff00000000UL)
427 return 1;
ab344828
GN		 428#endif
429
430 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 431
0f12244f
GN		 432 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
433 return 1;
a03490ed 434
0f12244f
GN		 435 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
436 return 1;
a03490ed
CO		 437
438 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
439#ifdef CONFIG_X86_64
f6801dff 440 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 441 int cs_db, cs_l;
442
0f12244f
GN		 443 if (!is_pae(vcpu))
444 return 1;
a03490ed 445 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 446 if (cs_l)
447 return 1;
a03490ed
CO		 448 } else
449#endif
0f12244f
GN		 450 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
451 return 1;
a03490ed
CO		 452 }
453
454 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 455
aad82703
SY		 456 if ((cr0 ^ old_cr0) & update_bits)
457 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 458 return 0;
459}
460
461void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
462{
463 if (__kvm_set_cr0(vcpu, cr0))
464 kvm_inject_gp(vcpu, 0);
a03490ed 465}
2d3ad1f4 466EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 467
2d3ad1f4 468void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 469{
f78e9176 470 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 471}
2d3ad1f4 472EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 473
0f12244f 474int __kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 475{
fc78f519 476 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 477 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
478
0f12244f
GN		 479 if (cr4 & CR4_RESERVED_BITS)
480 return 1;
a03490ed
CO		 481
482 if (is_long_mode(vcpu)) {
0f12244f
GN		 483 if (!(cr4 & X86_CR4_PAE))
484 return 1;
a2edf57f
AK		 485 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
486 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 487 && !load_pdptrs(vcpu, vcpu->arch.cr3))
488 return 1;
489
490 if (cr4 & X86_CR4_VMXE)
491 return 1;
a03490ed 492
a03490ed 493 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 494
aad82703
SY		 495 if ((cr4 ^ old_cr4) & pdptr_bits)
496 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 497
498 return 0;
499}
500
501void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
502{
503 if (__kvm_set_cr4(vcpu, cr4))
504 kvm_inject_gp(vcpu, 0);
a03490ed 505}
2d3ad1f4 506EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 507
0f12244f 508static int __kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 509{
ad312c7c 510 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 511 kvm_mmu_sync_roots(vcpu);
d835dfec 512 kvm_mmu_flush_tlb(vcpu);
0f12244f 513 return 0;
d835dfec
AK		 514 }
515
a03490ed 516 if (is_long_mode(vcpu)) {
0f12244f
GN		 517 if (cr3 & CR3_L_MODE_RESERVED_BITS)
518 return 1;
a03490ed
CO		 519 } else {
520 if (is_pae(vcpu)) {
0f12244f
GN		 521 if (cr3 & CR3_PAE_RESERVED_BITS)
522 return 1;
523 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
524 return 1;
a03490ed
CO		 525 }
526 /*
527 * We don't check reserved bits in nonpae mode, because
528 * this isn't enforced, and VMware depends on this.
529 */
530 }
531
a03490ed
CO		 532 /*
533 * Does the new cr3 value map to physical memory? (Note, we
534 * catch an invalid cr3 even in real-mode, because it would
535 * cause trouble later on when we turn on paging anyway.)
536 *
537 * A real CPU would silently accept an invalid cr3 and would
538 * attempt to use it - with largely undefined (and often hard
539 * to debug) behavior on the guest side.
540 */
541 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 542 return 1;
543 vcpu->arch.cr3 = cr3;
544 vcpu->arch.mmu.new_cr3(vcpu);
545 return 0;
546}
547
548void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
549{
550 if (__kvm_set_cr3(vcpu, cr3))
c1a5d4f9 551 kvm_inject_gp(vcpu, 0);
a03490ed 552}
2d3ad1f4 553EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 554
0f12244f 555int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 556{
0f12244f
GN		 557 if (cr8 & CR8_RESERVED_BITS)
558 return 1;
a03490ed
CO		 559 if (irqchip_in_kernel(vcpu->kvm))
560 kvm_lapic_set_tpr(vcpu, cr8);
561 else
ad312c7c 562 vcpu->arch.cr8 = cr8;
0f12244f
GN		 563 return 0;
564}
565
566void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
567{
568 if (__kvm_set_cr8(vcpu, cr8))
569 kvm_inject_gp(vcpu, 0);
a03490ed 570}
2d3ad1f4 571EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 572
2d3ad1f4 573unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 574{
575 if (irqchip_in_kernel(vcpu->kvm))
576 return kvm_lapic_get_cr8(vcpu);
577 else
ad312c7c 578 return vcpu->arch.cr8;
a03490ed 579}
2d3ad1f4 580EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 581
338dbc97 582static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 583{
584 switch (dr) {
585 case 0 ... 3:
586 vcpu->arch.db[dr] = val;
587 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
588 vcpu->arch.eff_db[dr] = val;
589 break;
590 case 4:
338dbc97
GN		 591 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
592 return 1; /* #UD */
020df079
GN		 593 /* fall through */
594 case 6:
338dbc97
GN		 595 if (val & 0xffffffff00000000ULL)
596 return -1; /* #GP */
020df079
GN		 597 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
598 break;
599 case 5:
338dbc97
GN		 600 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
601 return 1; /* #UD */
020df079
GN		 602 /* fall through */
603 default: /* 7 */
338dbc97
GN		 604 if (val & 0xffffffff00000000ULL)
605 return -1; /* #GP */
020df079
GN		 606 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
607 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
608 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
609 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
610 }
611 break;
612 }
613
614 return 0;
615}
338dbc97
GN		 616
617int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
618{
619 int res;
620
621 res = __kvm_set_dr(vcpu, dr, val);
622 if (res > 0)
623 kvm_queue_exception(vcpu, UD_VECTOR);
624 else if (res < 0)
625 kvm_inject_gp(vcpu, 0);
626
627 return res;
628}
020df079
GN		 629EXPORT_SYMBOL_GPL(kvm_set_dr);
630
338dbc97 631static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 632{
633 switch (dr) {
634 case 0 ... 3:
635 *val = vcpu->arch.db[dr];
636 break;
637 case 4:
338dbc97 638 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 639 return 1;
020df079
GN		 640 /* fall through */
641 case 6:
642 *val = vcpu->arch.dr6;
643 break;
644 case 5:
338dbc97 645 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 646 return 1;
020df079
GN		 647 /* fall through */
648 default: /* 7 */
649 *val = vcpu->arch.dr7;
650 break;
651 }
652
653 return 0;
654}
338dbc97
GN		 655
656int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
657{
658 if (_kvm_get_dr(vcpu, dr, val)) {
659 kvm_queue_exception(vcpu, UD_VECTOR);
660 return 1;
661 }
662 return 0;
663}
020df079
GN		 664EXPORT_SYMBOL_GPL(kvm_get_dr);
665
d8017474
AG		 666static inline u32 bit(int bitno)
667{
668 return 1 << (bitno & 31);
669}
670
043405e1
CO		 671/*
672 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
673 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
674 *
675 * This list is modified at module load time to reflect the
e3267cbb
GC		 676 * capabilities of the host cpu. This capabilities test skips MSRs that are
677 * kvm-specific. Those are put in the beginning of the list.
043405e1 678 */
e3267cbb 679
11c6bffa 680#define KVM_SAVE_MSRS_BEGIN 7
043405e1 681static u32 msrs_to_save[] = {
e3267cbb 682 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 683 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 684 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 685 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 686 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
687 MSR_K6_STAR,
688#ifdef CONFIG_X86_64
689 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
690#endif
e3267cbb 691 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 692};
693
694static unsigned num_msrs_to_save;
695
696static u32 emulated_msrs[] = {
697 MSR_IA32_MISC_ENABLE,
698};
699
b69e8cae 700static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 701{
aad82703
SY		 702 u64 old_efer = vcpu->arch.efer;
703
b69e8cae
RJ		 704 if (efer & efer_reserved_bits)
705 return 1;
15c4a640
CO		 706
707 if (is_paging(vcpu)
b69e8cae
RJ		 708 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
709 return 1;
15c4a640 710
1b2fd70c
AG		 711 if (efer & EFER_FFXSR) {
712 struct kvm_cpuid_entry2 *feat;
713
714 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 715 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
716 return 1;
1b2fd70c
AG		 717 }
718
d8017474
AG		 719 if (efer & EFER_SVME) {
720 struct kvm_cpuid_entry2 *feat;
721
722 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 723 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
724 return 1;
d8017474
AG		 725 }
726
15c4a640 727 efer &= ~EFER_LMA;
f6801dff 728 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 729
a3d204e2
SY		 730 kvm_x86_ops->set_efer(vcpu, efer);
731
9645bb56
AK		 732 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
733 kvm_mmu_reset_context(vcpu);
b69e8cae 734
aad82703
SY		 735 /* Update reserved bits */
736 if ((efer ^ old_efer) & EFER_NX)
737 kvm_mmu_reset_context(vcpu);
738
b69e8cae 739 return 0;
15c4a640
CO		 740}
741
f2b4b7dd
JR		 742void kvm_enable_efer_bits(u64 mask)
743{
744 efer_reserved_bits &= ~mask;
745}
746EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
747
748
15c4a640
CO		 749/*
750 * Writes msr value into into the appropriate "register".
751 * Returns 0 on success, non-0 otherwise.
752 * Assumes vcpu_load() was already called.
753 */
754int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
755{
756 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
757}
758
313a3dc7
CO		 759/*
760 * Adapt set_msr() to msr_io()'s calling convention
761 */
762static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
763{
764 return kvm_set_msr(vcpu, index, *data);
765}
766
18068523
GOC		 767static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
768{
9ed3c444
AK		 769 int version;
770 int r;
50d0a0f9 771 struct pvclock_wall_clock wc;
923de3cf 772 struct timespec boot;
18068523
GOC		 773
774 if (!wall_clock)
775 return;
776
9ed3c444
AK		 777 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
778 if (r)
779 return;
780
781 if (version & 1)
782 ++version; /* first time write, random junk */
783
784 ++version;
18068523 785
18068523
GOC		 786 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
787
50d0a0f9
GH		 788 /*
789 * The guest calculates current wall clock time by adding
790 * system time (updated by kvm_write_guest_time below) to the
791 * wall clock specified here. guest system time equals host
792 * system time for us, thus we must fill in host boot time here.
793 */
923de3cf 794 getboottime(&boot);
50d0a0f9
GH		 795
796 wc.sec = boot.tv_sec;
797 wc.nsec = boot.tv_nsec;
798 wc.version = version;
18068523
GOC		 799
800 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
801
802 version++;
803 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 804}
805
50d0a0f9
GH		 806static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
807{
808 uint32_t quotient, remainder;
809
810 /* Don't try to replace with do_div(), this one calculates
811 * "(dividend << 32) / divisor" */
812 __asm__ ( "divl %4"
813 : "=a" (quotient), "=d" (remainder)
814 : "0" (0), "1" (dividend), "r" (divisor) );
815 return quotient;
816}
817
818static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
819{
820 uint64_t nsecs = 1000000000LL;
821 int32_t shift = 0;
822 uint64_t tps64;
823 uint32_t tps32;
824
825 tps64 = tsc_khz * 1000LL;
826 while (tps64 > nsecs*2) {
827 tps64 >>= 1;
828 shift--;
829 }
830
831 tps32 = (uint32_t)tps64;
832 while (tps32 <= (uint32_t)nsecs) {
833 tps32 <<= 1;
834 shift++;
835 }
836
837 hv_clock->tsc_shift = shift;
838 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
839
840 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 841 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 842 hv_clock->tsc_to_system_mul);
843}
844
c8076604
GH		 845static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
846
18068523
GOC		 847static void kvm_write_guest_time(struct kvm_vcpu *v)
848{
849 struct timespec ts;
850 unsigned long flags;
851 struct kvm_vcpu_arch *vcpu = &v->arch;
852 void *shared_kaddr;
463656c0 853 unsigned long this_tsc_khz;
18068523
GOC		 854
855 if ((!vcpu->time_page))
856 return;
857
463656c0
AK		 858 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
859 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
860 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
861 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 862 }
463656c0 863 put_cpu_var(cpu_tsc_khz);
50d0a0f9 864
18068523
GOC		 865 /* Keep irq disabled to prevent changes to the clock */
866 local_irq_save(flags);
af24a4e4 867 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 868 ktime_get_ts(&ts);
923de3cf 869 monotonic_to_bootbased(&ts);
18068523
GOC		 870 local_irq_restore(flags);
871
872 /* With all the info we got, fill in the values */
873
874 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 875 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
876
371bcf64
GC		 877 vcpu->hv_clock.flags = 0;
878
18068523
GOC		 879 /*
880 * The interface expects us to write an even number signaling that the
881 * update is finished. Since the guest won't see the intermediate
50d0a0f9 882 * state, we just increase by 2 at the end.
18068523 883 */
50d0a0f9 884 vcpu->hv_clock.version += 2;
18068523
GOC		 885
886 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
887
888 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 889 sizeof(vcpu->hv_clock));
18068523
GOC		 890
891 kunmap_atomic(shared_kaddr, KM_USER0);
892
893 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
894}
895
c8076604
GH		 896static int kvm_request_guest_time_update(struct kvm_vcpu *v)
897{
898 struct kvm_vcpu_arch *vcpu = &v->arch;
899
900 if (!vcpu->time_page)
901 return 0;
902 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
903 return 1;
904}
905
9ba075a6
AK		 906static bool msr_mtrr_valid(unsigned msr)
907{
908 switch (msr) {
909 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
910 case MSR_MTRRfix64K_00000:
911 case MSR_MTRRfix16K_80000:
912 case MSR_MTRRfix16K_A0000:
913 case MSR_MTRRfix4K_C0000:
914 case MSR_MTRRfix4K_C8000:
915 case MSR_MTRRfix4K_D0000:
916 case MSR_MTRRfix4K_D8000:
917 case MSR_MTRRfix4K_E0000:
918 case MSR_MTRRfix4K_E8000:
919 case MSR_MTRRfix4K_F0000:
920 case MSR_MTRRfix4K_F8000:
921 case MSR_MTRRdefType:
922 case MSR_IA32_CR_PAT:
923 return true;
924 case 0x2f8:
925 return true;
926 }
927 return false;
928}
929
d6289b93
MT		 930static bool valid_pat_type(unsigned t)
931{
932 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
933}
934
935static bool valid_mtrr_type(unsigned t)
936{
937 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
938}
939
940static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
941{
942 int i;
943
944 if (!msr_mtrr_valid(msr))
945 return false;
946
947 if (msr == MSR_IA32_CR_PAT) {
948 for (i = 0; i < 8; i++)
949 if (!valid_pat_type((data >> (i * 8)) & 0xff))
950 return false;
951 return true;
952 } else if (msr == MSR_MTRRdefType) {
953 if (data & ~0xcff)
954 return false;
955 return valid_mtrr_type(data & 0xff);
956 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
957 for (i = 0; i < 8 ; i++)
958 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
959 return false;
960 return true;
961 }
962
963 /* variable MTRRs */
964 return valid_mtrr_type(data & 0xff);
965}
966
9ba075a6
AK		 967static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
968{
0bed3b56
SY		 969 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
970
d6289b93 971 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 972 return 1;
973
0bed3b56
SY		 974 if (msr == MSR_MTRRdefType) {
975 vcpu->arch.mtrr_state.def_type = data;
976 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
977 } else if (msr == MSR_MTRRfix64K_00000)
978 p[0] = data;
979 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
980 p[1 + msr - MSR_MTRRfix16K_80000] = data;
981 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
982 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
983 else if (msr == MSR_IA32_CR_PAT)
984 vcpu->arch.pat = data;
985 else { /* Variable MTRRs */
986 int idx, is_mtrr_mask;
987 u64 *pt;
988
989 idx = (msr - 0x200) / 2;
990 is_mtrr_mask = msr - 0x200 - 2 * idx;
991 if (!is_mtrr_mask)
992 pt =
993 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
994 else
995 pt =
996 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
997 *pt = data;
998 }
999
1000 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1001 return 0;
1002}
15c4a640 1003
890ca9ae 1004static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1005{
890ca9ae
HY		 1006 u64 mcg_cap = vcpu->arch.mcg_cap;
1007 unsigned bank_num = mcg_cap & 0xff;
1008
15c4a640 1009 switch (msr) {
15c4a640 1010 case MSR_IA32_MCG_STATUS:
890ca9ae 1011 vcpu->arch.mcg_status = data;
15c4a640 1012 break;
c7ac679c 1013 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1014 if (!(mcg_cap & MCG_CTL_P))
1015 return 1;
1016 if (data != 0 && data != ~(u64)0)
1017 return -1;
1018 vcpu->arch.mcg_ctl = data;
1019 break;
1020 default:
1021 if (msr >= MSR_IA32_MC0_CTL &&
1022 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1023 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1024 /* only 0 or all 1s can be written to IA32_MCi_CTL
1025 * some Linux kernels though clear bit 10 in bank 4 to
1026 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1027 * this to avoid an uncatched #GP in the guest
1028 */
890ca9ae 1029 if ((offset & 0x3) == 0 &&
114be429 1030 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1031 return -1;
1032 vcpu->arch.mce_banks[offset] = data;
1033 break;
1034 }
1035 return 1;
1036 }
1037 return 0;
1038}
1039
ffde22ac
ES		 1040static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1041{
1042 struct kvm *kvm = vcpu->kvm;
1043 int lm = is_long_mode(vcpu);
1044 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1045 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1046 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1047 : kvm->arch.xen_hvm_config.blob_size_32;
1048 u32 page_num = data & ~PAGE_MASK;
1049 u64 page_addr = data & PAGE_MASK;
1050 u8 *page;
1051 int r;
1052
1053 r = -E2BIG;
1054 if (page_num >= blob_size)
1055 goto out;
1056 r = -ENOMEM;
1057 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1058 if (!page)
1059 goto out;
1060 r = -EFAULT;
1061 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1062 goto out_free;
1063 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1064 goto out_free;
1065 r = 0;
1066out_free:
1067 kfree(page);
1068out:
1069 return r;
1070}
1071
55cd8e5a
GN		 1072static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1073{
1074 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1075}
1076
1077static bool kvm_hv_msr_partition_wide(u32 msr)
1078{
1079 bool r = false;
1080 switch (msr) {
1081 case HV_X64_MSR_GUEST_OS_ID:
1082 case HV_X64_MSR_HYPERCALL:
1083 r = true;
1084 break;
1085 }
1086
1087 return r;
1088}
1089
1090static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1091{
1092 struct kvm *kvm = vcpu->kvm;
1093
1094 switch (msr) {
1095 case HV_X64_MSR_GUEST_OS_ID:
1096 kvm->arch.hv_guest_os_id = data;
1097 /* setting guest os id to zero disables hypercall page */
1098 if (!kvm->arch.hv_guest_os_id)
1099 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1100 break;
1101 case HV_X64_MSR_HYPERCALL: {
1102 u64 gfn;
1103 unsigned long addr;
1104 u8 instructions[4];
1105
1106 /* if guest os id is not set hypercall should remain disabled */
1107 if (!kvm->arch.hv_guest_os_id)
1108 break;
1109 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1110 kvm->arch.hv_hypercall = data;
1111 break;
1112 }
1113 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1114 addr = gfn_to_hva(kvm, gfn);
1115 if (kvm_is_error_hva(addr))
1116 return 1;
1117 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1118 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1119 if (copy_to_user((void __user *)addr, instructions, 4))
1120 return 1;
1121 kvm->arch.hv_hypercall = data;
1122 break;
1123 }
1124 default:
1125 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1126 "data 0x%llx\n", msr, data);
1127 return 1;
1128 }
1129 return 0;
1130}
1131
1132static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1133{
10388a07
GN		 1134 switch (msr) {
1135 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1136 unsigned long addr;
55cd8e5a 1137
10388a07
GN		 1138 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1139 vcpu->arch.hv_vapic = data;
1140 break;
1141 }
1142 addr = gfn_to_hva(vcpu->kvm, data >>
1143 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1144 if (kvm_is_error_hva(addr))
1145 return 1;
1146 if (clear_user((void __user *)addr, PAGE_SIZE))
1147 return 1;
1148 vcpu->arch.hv_vapic = data;
1149 break;
1150 }
1151 case HV_X64_MSR_EOI:
1152 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1153 case HV_X64_MSR_ICR:
1154 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1155 case HV_X64_MSR_TPR:
1156 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1157 default:
1158 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1159 "data 0x%llx\n", msr, data);
1160 return 1;
1161 }
1162
1163 return 0;
55cd8e5a
GN		 1164}
1165
15c4a640
CO		 1166int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1167{
1168 switch (msr) {
15c4a640 1169 case MSR_EFER:
b69e8cae 1170 return set_efer(vcpu, data);
8f1589d9
AP		 1171 case MSR_K7_HWCR:
1172 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1173 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1174 if (data != 0) {
1175 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1176 data);
1177 return 1;
1178 }
15c4a640 1179 break;
f7c6d140
AP		 1180 case MSR_FAM10H_MMIO_CONF_BASE:
1181 if (data != 0) {
1182 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1183 "0x%llx\n", data);
1184 return 1;
1185 }
15c4a640 1186 break;
c323c0e5 1187 case MSR_AMD64_NB_CFG:
c7ac679c 1188 break;
b5e2fec0
AG		 1189 case MSR_IA32_DEBUGCTLMSR:
1190 if (!data) {
1191 /* We support the non-activated case already */
1192 break;
1193 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1194 /* Values other than LBR and BTF are vendor-specific,
1195 thus reserved and should throw a #GP */
1196 return 1;
1197 }
1198 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1199 __func__, data);
1200 break;
15c4a640
CO		 1201 case MSR_IA32_UCODE_REV:
1202 case MSR_IA32_UCODE_WRITE:
61a6bd67 1203 case MSR_VM_HSAVE_PA:
6098ca93 1204 case MSR_AMD64_PATCH_LOADER:
15c4a640 1205 break;
9ba075a6
AK		 1206 case 0x200 ... 0x2ff:
1207 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1208 case MSR_IA32_APICBASE:
1209 kvm_set_apic_base(vcpu, data);
1210 break;
0105d1a5
GN		 1211 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1212 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1213 case MSR_IA32_MISC_ENABLE:
ad312c7c 1214 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1215 break;
11c6bffa 1216 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1217 case MSR_KVM_WALL_CLOCK:
1218 vcpu->kvm->arch.wall_clock = data;
1219 kvm_write_wall_clock(vcpu->kvm, data);
1220 break;
11c6bffa 1221 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1222 case MSR_KVM_SYSTEM_TIME: {
1223 if (vcpu->arch.time_page) {
1224 kvm_release_page_dirty(vcpu->arch.time_page);
1225 vcpu->arch.time_page = NULL;
1226 }
1227
1228 vcpu->arch.time = data;
1229
1230 /* we verify if the enable bit is set... */
1231 if (!(data & 1))
1232 break;
1233
1234 /* ...but clean it before doing the actual write */
1235 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1236
18068523
GOC		 1237 vcpu->arch.time_page =
1238 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1239
1240 if (is_error_page(vcpu->arch.time_page)) {
1241 kvm_release_page_clean(vcpu->arch.time_page);
1242 vcpu->arch.time_page = NULL;
1243 }
1244
c8076604 1245 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1246 break;
1247 }
890ca9ae
HY		 1248 case MSR_IA32_MCG_CTL:
1249 case MSR_IA32_MCG_STATUS:
1250 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1251 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1252
1253 /* Performance counters are not protected by a CPUID bit,
1254 * so we should check all of them in the generic path for the sake of
1255 * cross vendor migration.
1256 * Writing a zero into the event select MSRs disables them,
1257 * which we perfectly emulate ;-). Any other value should be at least
1258 * reported, some guests depend on them.
1259 */
1260 case MSR_P6_EVNTSEL0:
1261 case MSR_P6_EVNTSEL1:
1262 case MSR_K7_EVNTSEL0:
1263 case MSR_K7_EVNTSEL1:
1264 case MSR_K7_EVNTSEL2:
1265 case MSR_K7_EVNTSEL3:
1266 if (data != 0)
1267 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1268 "0x%x data 0x%llx\n", msr, data);
1269 break;
1270 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1271 * so we ignore writes to make it happy.
1272 */
1273 case MSR_P6_PERFCTR0:
1274 case MSR_P6_PERFCTR1:
1275 case MSR_K7_PERFCTR0:
1276 case MSR_K7_PERFCTR1:
1277 case MSR_K7_PERFCTR2:
1278 case MSR_K7_PERFCTR3:
1279 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1280 "0x%x data 0x%llx\n", msr, data);
1281 break;
55cd8e5a
GN		 1282 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1283 if (kvm_hv_msr_partition_wide(msr)) {
1284 int r;
1285 mutex_lock(&vcpu->kvm->lock);
1286 r = set_msr_hyperv_pw(vcpu, msr, data);
1287 mutex_unlock(&vcpu->kvm->lock);
1288 return r;
1289 } else
1290 return set_msr_hyperv(vcpu, msr, data);
1291 break;
15c4a640 1292 default:
ffde22ac
ES		 1293 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1294 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1295 if (!ignore_msrs) {
1296 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1297 msr, data);
1298 return 1;
1299 } else {
1300 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1301 msr, data);
1302 break;
1303 }
15c4a640
CO		 1304 }
1305 return 0;
1306}
1307EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1308
1309
1310/*
1311 * Reads an msr value (of 'msr_index') into 'pdata'.
1312 * Returns 0 on success, non-0 otherwise.
1313 * Assumes vcpu_load() was already called.
1314 */
1315int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1316{
1317 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1318}
1319
9ba075a6
AK		 1320static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1321{
0bed3b56
SY		 1322 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1323
9ba075a6
AK		 1324 if (!msr_mtrr_valid(msr))
1325 return 1;
1326
0bed3b56
SY		 1327 if (msr == MSR_MTRRdefType)
1328 *pdata = vcpu->arch.mtrr_state.def_type +
1329 (vcpu->arch.mtrr_state.enabled << 10);
1330 else if (msr == MSR_MTRRfix64K_00000)
1331 *pdata = p[0];
1332 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1333 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1334 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1335 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1336 else if (msr == MSR_IA32_CR_PAT)
1337 *pdata = vcpu->arch.pat;
1338 else { /* Variable MTRRs */
1339 int idx, is_mtrr_mask;
1340 u64 *pt;
1341
1342 idx = (msr - 0x200) / 2;
1343 is_mtrr_mask = msr - 0x200 - 2 * idx;
1344 if (!is_mtrr_mask)
1345 pt =
1346 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1347 else
1348 pt =
1349 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1350 *pdata = *pt;
1351 }
1352
9ba075a6
AK		 1353 return 0;
1354}
1355
890ca9ae 1356static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1357{
1358 u64 data;
890ca9ae
HY		 1359 u64 mcg_cap = vcpu->arch.mcg_cap;
1360 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1361
1362 switch (msr) {
15c4a640
CO		 1363 case MSR_IA32_P5_MC_ADDR:
1364 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1365 data = 0;
1366 break;
15c4a640 1367 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1368 data = vcpu->arch.mcg_cap;
1369 break;
c7ac679c 1370 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1371 if (!(mcg_cap & MCG_CTL_P))
1372 return 1;
1373 data = vcpu->arch.mcg_ctl;
1374 break;
1375 case MSR_IA32_MCG_STATUS:
1376 data = vcpu->arch.mcg_status;
1377 break;
1378 default:
1379 if (msr >= MSR_IA32_MC0_CTL &&
1380 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1381 u32 offset = msr - MSR_IA32_MC0_CTL;
1382 data = vcpu->arch.mce_banks[offset];
1383 break;
1384 }
1385 return 1;
1386 }
1387 *pdata = data;
1388 return 0;
1389}
1390
55cd8e5a
GN		 1391static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1392{
1393 u64 data = 0;
1394 struct kvm *kvm = vcpu->kvm;
1395
1396 switch (msr) {
1397 case HV_X64_MSR_GUEST_OS_ID:
1398 data = kvm->arch.hv_guest_os_id;
1399 break;
1400 case HV_X64_MSR_HYPERCALL:
1401 data = kvm->arch.hv_hypercall;
1402 break;
1403 default:
1404 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1405 return 1;
1406 }
1407
1408 *pdata = data;
1409 return 0;
1410}
1411
1412static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1413{
1414 u64 data = 0;
1415
1416 switch (msr) {
1417 case HV_X64_MSR_VP_INDEX: {
1418 int r;
1419 struct kvm_vcpu *v;
1420 kvm_for_each_vcpu(r, v, vcpu->kvm)
1421 if (v == vcpu)
1422 data = r;
1423 break;
1424 }
10388a07
GN		 1425 case HV_X64_MSR_EOI:
1426 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1427 case HV_X64_MSR_ICR:
1428 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1429 case HV_X64_MSR_TPR:
1430 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1431 default:
1432 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1433 return 1;
1434 }
1435 *pdata = data;
1436 return 0;
1437}
1438
890ca9ae
HY		 1439int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1440{
1441 u64 data;
1442
1443 switch (msr) {
890ca9ae 1444 case MSR_IA32_PLATFORM_ID:
15c4a640 1445 case MSR_IA32_UCODE_REV:
15c4a640 1446 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1447 case MSR_IA32_DEBUGCTLMSR:
1448 case MSR_IA32_LASTBRANCHFROMIP:
1449 case MSR_IA32_LASTBRANCHTOIP:
1450 case MSR_IA32_LASTINTFROMIP:
1451 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1452 case MSR_K8_SYSCFG:
1453 case MSR_K7_HWCR:
61a6bd67 1454 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1455 case MSR_P6_PERFCTR0:
1456 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1457 case MSR_P6_EVNTSEL0:
1458 case MSR_P6_EVNTSEL1:
9e699624 1459 case MSR_K7_EVNTSEL0:
1f3ee616 1460 case MSR_K7_PERFCTR0:
1fdbd48c 1461 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1462 case MSR_AMD64_NB_CFG:
f7c6d140 1463 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1464 data = 0;
1465 break;
9ba075a6
AK		 1466 case MSR_MTRRcap:
1467 data = 0x500 | KVM_NR_VAR_MTRR;
1468 break;
1469 case 0x200 ... 0x2ff:
1470 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1471 case 0xcd: /* fsb frequency */
1472 data = 3;
1473 break;
1474 case MSR_IA32_APICBASE:
1475 data = kvm_get_apic_base(vcpu);
1476 break;
0105d1a5
GN		 1477 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1478 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1479 break;
15c4a640 1480 case MSR_IA32_MISC_ENABLE:
ad312c7c 1481 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1482 break;
847f0ad8
AG		 1483 case MSR_IA32_PERF_STATUS:
1484 /* TSC increment by tick */
1485 data = 1000ULL;
1486 /* CPU multiplier */
1487 data |= (((uint64_t)4ULL) << 40);
1488 break;
15c4a640 1489 case MSR_EFER:
f6801dff 1490 data = vcpu->arch.efer;
15c4a640 1491 break;
18068523 1492 case MSR_KVM_WALL_CLOCK:
11c6bffa 1493 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1494 data = vcpu->kvm->arch.wall_clock;
1495 break;
1496 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1497 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1498 data = vcpu->arch.time;
1499 break;
890ca9ae
HY		 1500 case MSR_IA32_P5_MC_ADDR:
1501 case MSR_IA32_P5_MC_TYPE:
1502 case MSR_IA32_MCG_CAP:
1503 case MSR_IA32_MCG_CTL:
1504 case MSR_IA32_MCG_STATUS:
1505 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1506 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1507 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1508 if (kvm_hv_msr_partition_wide(msr)) {
1509 int r;
1510 mutex_lock(&vcpu->kvm->lock);
1511 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1512 mutex_unlock(&vcpu->kvm->lock);
1513 return r;
1514 } else
1515 return get_msr_hyperv(vcpu, msr, pdata);
1516 break;
15c4a640 1517 default:
ed85c068
AP		 1518 if (!ignore_msrs) {
1519 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1520 return 1;
1521 } else {
1522 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1523 data = 0;
1524 }
1525 break;
15c4a640
CO		 1526 }
1527 *pdata = data;
1528 return 0;
1529}
1530EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1531
313a3dc7
CO		 1532/*
1533 * Read or write a bunch of msrs. All parameters are kernel addresses.
1534 *
1535 * @return number of msrs set successfully.
1536 */
1537static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1538 struct kvm_msr_entry *entries,
1539 int (*do_msr)(struct kvm_vcpu *vcpu,
1540 unsigned index, u64 *data))
1541{
f656ce01 1542 int i, idx;
313a3dc7
CO		 1543
1544 vcpu_load(vcpu);
1545
f656ce01 1546 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1547 for (i = 0; i < msrs->nmsrs; ++i)
1548 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1549 break;
f656ce01 1550 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1551
1552 vcpu_put(vcpu);
1553
1554 return i;
1555}
1556
1557/*
1558 * Read or write a bunch of msrs. Parameters are user addresses.
1559 *
1560 * @return number of msrs set successfully.
1561 */
1562static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1563 int (*do_msr)(struct kvm_vcpu *vcpu,
1564 unsigned index, u64 *data),
1565 int writeback)
1566{
1567 struct kvm_msrs msrs;
1568 struct kvm_msr_entry *entries;
1569 int r, n;
1570 unsigned size;
1571
1572 r = -EFAULT;
1573 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1574 goto out;
1575
1576 r = -E2BIG;
1577 if (msrs.nmsrs >= MAX_IO_MSRS)
1578 goto out;
1579
1580 r = -ENOMEM;
1581 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1582 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1583 if (!entries)
1584 goto out;
1585
1586 r = -EFAULT;
1587 if (copy_from_user(entries, user_msrs->entries, size))
1588 goto out_free;
1589
1590 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1591 if (r < 0)
1592 goto out_free;
1593
1594 r = -EFAULT;
1595 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1596 goto out_free;
1597
1598 r = n;
1599
1600out_free:
7a73c028 1601 kfree(entries);
313a3dc7
CO		 1602out:
1603 return r;
1604}
1605
018d00d2
ZX		 1606int kvm_dev_ioctl_check_extension(long ext)
1607{
1608 int r;
1609
1610 switch (ext) {
1611 case KVM_CAP_IRQCHIP:
1612 case KVM_CAP_HLT:
1613 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1614 case KVM_CAP_SET_TSS_ADDR:
07716717 1615 case KVM_CAP_EXT_CPUID:
c8076604 1616 case KVM_CAP_CLOCKSOURCE:
7837699f 1617 case KVM_CAP_PIT:
a28e4f5a 1618 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1619 case KVM_CAP_MP_STATE:
ed848624 1620 case KVM_CAP_SYNC_MMU:
52d939a0 1621 case KVM_CAP_REINJECT_CONTROL:
4925663a 1622 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1623 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1624 case KVM_CAP_IRQFD:
d34e6b17 1625 case KVM_CAP_IOEVENTFD:
c5ff41ce 1626 case KVM_CAP_PIT2:
e9f42757 1627 case KVM_CAP_PIT_STATE2:
b927a3ce 1628 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1629 case KVM_CAP_XEN_HVM:
afbcf7ab 1630 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1631 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1632 case KVM_CAP_HYPERV:
10388a07 1633 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1634 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1635 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1636 case KVM_CAP_DEBUGREGS:
d2be1651 1637 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1638 r = 1;
1639 break;
542472b5
LV		 1640 case KVM_CAP_COALESCED_MMIO:
1641 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1642 break;
774ead3a
AK		 1643 case KVM_CAP_VAPIC:
1644 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1645 break;
f725230a
AK		 1646 case KVM_CAP_NR_VCPUS:
1647 r = KVM_MAX_VCPUS;
1648 break;
a988b910
AK		 1649 case KVM_CAP_NR_MEMSLOTS:
1650 r = KVM_MEMORY_SLOTS;
1651 break;
a68a6a72
MT		 1652 case KVM_CAP_PV_MMU: /* obsolete */
1653 r = 0;
2f333bcb 1654 break;
62c476c7 1655 case KVM_CAP_IOMMU:
19de40a8 1656 r = iommu_found();
62c476c7 1657 break;
890ca9ae
HY		 1658 case KVM_CAP_MCE:
1659 r = KVM_MAX_MCE_BANKS;
1660 break;
018d00d2
ZX		 1661 default:
1662 r = 0;
1663 break;
1664 }
1665 return r;
1666
1667}
1668
043405e1
CO		 1669long kvm_arch_dev_ioctl(struct file *filp,
1670 unsigned int ioctl, unsigned long arg)
1671{
1672 void __user *argp = (void __user *)arg;
1673 long r;
1674
1675 switch (ioctl) {
1676 case KVM_GET_MSR_INDEX_LIST: {
1677 struct kvm_msr_list __user *user_msr_list = argp;
1678 struct kvm_msr_list msr_list;
1679 unsigned n;
1680
1681 r = -EFAULT;
1682 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1683 goto out;
1684 n = msr_list.nmsrs;
1685 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1686 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1687 goto out;
1688 r = -E2BIG;
e125e7b6 1689 if (n < msr_list.nmsrs)
043405e1
CO		 1690 goto out;
1691 r = -EFAULT;
1692 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1693 num_msrs_to_save * sizeof(u32)))
1694 goto out;
e125e7b6 1695 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1696 &emulated_msrs,
1697 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1698 goto out;
1699 r = 0;
1700 break;
1701 }
674eea0f
AK		 1702 case KVM_GET_SUPPORTED_CPUID: {
1703 struct kvm_cpuid2 __user *cpuid_arg = argp;
1704 struct kvm_cpuid2 cpuid;
1705
1706 r = -EFAULT;
1707 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1708 goto out;
1709 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1710 cpuid_arg->entries);
674eea0f
AK		 1711 if (r)
1712 goto out;
1713
1714 r = -EFAULT;
1715 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1716 goto out;
1717 r = 0;
1718 break;
1719 }
890ca9ae
HY		 1720 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1721 u64 mce_cap;
1722
1723 mce_cap = KVM_MCE_CAP_SUPPORTED;
1724 r = -EFAULT;
1725 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1726 goto out;
1727 r = 0;
1728 break;
1729 }
043405e1
CO		 1730 default:
1731 r = -EINVAL;
1732 }
1733out:
1734 return r;
1735}
1736
313a3dc7
CO		 1737void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1738{
1739 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1740 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1741 unsigned long khz = cpufreq_quick_get(cpu);
1742 if (!khz)
1743 khz = tsc_khz;
1744 per_cpu(cpu_tsc_khz, cpu) = khz;
1745 }
c8076604 1746 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1747}
1748
1749void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1750{
02daab21 1751 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1752 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1753}
1754
07716717 1755static int is_efer_nx(void)
313a3dc7 1756{
e286e86e 1757 unsigned long long efer = 0;
313a3dc7 1758
e286e86e 1759 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1760 return efer & EFER_NX;
1761}
1762
1763static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1764{
1765 int i;
1766 struct kvm_cpuid_entry2 *e, *entry;
1767
313a3dc7 1768 entry = NULL;
ad312c7c
ZX		 1769 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1770 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1771 if (e->function == 0x80000001) {
1772 entry = e;
1773 break;
1774 }
1775 }
07716717 1776 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1777 entry->edx &= ~(1 << 20);
1778 printk(KERN_INFO "kvm: guest NX capability removed\n");
1779 }
1780}
1781
07716717 1782/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1783static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1784 struct kvm_cpuid *cpuid,
1785 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1786{
1787 int r, i;
1788 struct kvm_cpuid_entry *cpuid_entries;
1789
1790 r = -E2BIG;
1791 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1792 goto out;
1793 r = -ENOMEM;
1794 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1795 if (!cpuid_entries)
1796 goto out;
1797 r = -EFAULT;
1798 if (copy_from_user(cpuid_entries, entries,
1799 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1800 goto out_free;
fe19c5a4 1801 vcpu_load(vcpu);
07716717 1802 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1803 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1804 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1805 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1806 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1807 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1808 vcpu->arch.cpuid_entries[i].index = 0;
1809 vcpu->arch.cpuid_entries[i].flags = 0;
1810 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1811 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1812 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1813 }
1814 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1815 cpuid_fix_nx_cap(vcpu);
1816 r = 0;
fc61b800 1817 kvm_apic_set_version(vcpu);
0e851880 1818 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1819 vcpu_put(vcpu);
07716717
DK		 1820
1821out_free:
1822 vfree(cpuid_entries);
1823out:
1824 return r;
1825}
1826
1827static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1828 struct kvm_cpuid2 *cpuid,
1829 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1830{
1831 int r;
1832
1833 r = -E2BIG;
1834 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1835 goto out;
1836 r = -EFAULT;
ad312c7c 1837 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1838 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1839 goto out;
fe19c5a4 1840 vcpu_load(vcpu);
ad312c7c 1841 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1842 kvm_apic_set_version(vcpu);
0e851880 1843 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1844 vcpu_put(vcpu);
313a3dc7
CO		 1845 return 0;
1846
1847out:
1848 return r;
1849}
1850
07716717 1851static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1852 struct kvm_cpuid2 *cpuid,
1853 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1854{
1855 int r;
1856
8fbf065d 1857 vcpu_load(vcpu);
07716717 1858 r = -E2BIG;
ad312c7c 1859 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1860 goto out;
1861 r = -EFAULT;
ad312c7c 1862 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1863 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1864 goto out;
1865 return 0;
1866
1867out:
ad312c7c 1868 cpuid->nent = vcpu->arch.cpuid_nent;
8fbf065d 1869 vcpu_put(vcpu);
07716717
DK		 1870 return r;
1871}
1872
07716717 1873static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1874 u32 index)
07716717
DK		 1875{
1876 entry->function = function;
1877 entry->index = index;
1878 cpuid_count(entry->function, entry->index,
19355475 1879 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1880 entry->flags = 0;
1881}
1882
7faa4ee1
AK		 1883#define F(x) bit(X86_FEATURE_##x)
1884
07716717
DK		 1885static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1886 u32 index, int *nent, int maxnent)
1887{
7faa4ee1 1888 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1889#ifdef CONFIG_X86_64
17cc3935
SY		 1890 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1891 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1892 unsigned f_lm = F(LM);
1893#else
17cc3935 1894 unsigned f_gbpages = 0;
7faa4ee1 1895 unsigned f_lm = 0;
07716717 1896#endif
4e47c7a6 1897 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1898
1899 /* cpuid 1.edx */
1900 const u32 kvm_supported_word0_x86_features =
1901 F(FPU) | F(VME) | F(DE) | F(PSE) |
1902 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1903 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1904 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1905 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1906 0 /* Reserved, DS, ACPI */ | F(MMX) |
1907 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1908 0 /* HTT, TM, Reserved, PBE */;
1909 /* cpuid 0x80000001.edx */
1910 const u32 kvm_supported_word1_x86_features =
1911 F(FPU) | F(VME) | F(DE) | F(PSE) |
1912 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1913 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1914 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1915 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1916 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1917 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1918 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1919 /* cpuid 1.ecx */
1920 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1921 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1922 0 /* DS-CPL, VMX, SMX, EST */ |
1923 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1924 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1925 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1926 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1927 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1928 /* cpuid 0x80000001.ecx */
07716717 1929 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1930 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1931 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1932 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1933 0 /* SKINIT */ | 0 /* WDT */;
07716717 1934
19355475 1935 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1936 get_cpu();
1937 do_cpuid_1_ent(entry, function, index);
1938 ++*nent;
1939
1940 switch (function) {
1941 case 0:
1942 entry->eax = min(entry->eax, (u32)0xb);
1943 break;
1944 case 1:
1945 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1946 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1947 /* we support x2apic emulation even if host does not support
1948 * it since we emulate x2apic in software */
1949 entry->ecx |= F(X2APIC);
07716717
DK		 1950 break;
1951 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1952 * may return different values. This forces us to get_cpu() before
1953 * issuing the first command, and also to emulate this annoying behavior
1954 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1955 case 2: {
1956 int t, times = entry->eax & 0xff;
1957
1958 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1959 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1960 for (t = 1; t < times && *nent < maxnent; ++t) {
1961 do_cpuid_1_ent(&entry[t], function, 0);
1962 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1963 ++*nent;
1964 }
1965 break;
1966 }
1967 /* function 4 and 0xb have additional index. */
1968 case 4: {
14af3f3c 1969 int i, cache_type;
07716717
DK		 1970
1971 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1972 /* read more entries until cache_type is zero */
14af3f3c
HH		 1973 for (i = 1; *nent < maxnent; ++i) {
1974 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1975 if (!cache_type)
1976 break;
14af3f3c
HH		 1977 do_cpuid_1_ent(&entry[i], function, i);
1978 entry[i].flags |=
07716717
DK		 1979 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1980 ++*nent;
1981 }
1982 break;
1983 }
1984 case 0xb: {
14af3f3c 1985 int i, level_type;
07716717
DK		 1986
1987 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1988 /* read more entries until level_type is zero */
14af3f3c 1989 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1990 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1991 if (!level_type)
1992 break;
14af3f3c
HH		 1993 do_cpuid_1_ent(&entry[i], function, i);
1994 entry[i].flags |=
07716717
DK		 1995 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1996 ++*nent;
1997 }
1998 break;
1999 }
84478c82
GC		 2000 case KVM_CPUID_SIGNATURE: {
2001 char signature[12] = "KVMKVMKVM\0\0";
2002 u32 *sigptr = (u32 *)signature;
2003 entry->eax = 0;
2004 entry->ebx = sigptr[0];
2005 entry->ecx = sigptr[1];
2006 entry->edx = sigptr[2];
2007 break;
2008 }
2009 case KVM_CPUID_FEATURES:
2010 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2011 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2012 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2013 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2014 entry->ebx = 0;
2015 entry->ecx = 0;
2016 entry->edx = 0;
2017 break;
07716717
DK		 2018 case 0x80000000:
2019 entry->eax = min(entry->eax, 0x8000001a);
2020 break;
2021 case 0x80000001:
2022 entry->edx &= kvm_supported_word1_x86_features;
2023 entry->ecx &= kvm_supported_word6_x86_features;
2024 break;
2025 }
d4330ef2
JR		 2026
2027 kvm_x86_ops->set_supported_cpuid(function, entry);
2028
07716717
DK		 2029 put_cpu();
2030}
2031
7faa4ee1
AK		 2032#undef F
2033
674eea0f 2034static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2035 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2036{
2037 struct kvm_cpuid_entry2 *cpuid_entries;
2038 int limit, nent = 0, r = -E2BIG;
2039 u32 func;
2040
2041 if (cpuid->nent < 1)
2042 goto out;
6a544355
AK		 2043 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2044 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2045 r = -ENOMEM;
2046 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2047 if (!cpuid_entries)
2048 goto out;
2049
2050 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2051 limit = cpuid_entries[0].eax;
2052 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2053 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2054 &nent, cpuid->nent);
07716717
DK		 2055 r = -E2BIG;
2056 if (nent >= cpuid->nent)
2057 goto out_free;
2058
2059 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2060 limit = cpuid_entries[nent - 1].eax;
2061 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2062 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2063 &nent, cpuid->nent);
84478c82
GC		 2064
2065
2066
2067 r = -E2BIG;
2068 if (nent >= cpuid->nent)
2069 goto out_free;
2070
2071 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2072 cpuid->nent);
2073
2074 r = -E2BIG;
2075 if (nent >= cpuid->nent)
2076 goto out_free;
2077
2078 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2079 cpuid->nent);
2080
cb007648
MM		 2081 r = -E2BIG;
2082 if (nent >= cpuid->nent)
2083 goto out_free;
2084
07716717
DK		 2085 r = -EFAULT;
2086 if (copy_to_user(entries, cpuid_entries,
19355475 2087 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2088 goto out_free;
2089 cpuid->nent = nent;
2090 r = 0;
2091
2092out_free:
2093 vfree(cpuid_entries);
2094out:
2095 return r;
2096}
2097
313a3dc7
CO		 2098static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2099 struct kvm_lapic_state *s)
2100{
2101 vcpu_load(vcpu);
ad312c7c 2102 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2103 vcpu_put(vcpu);
2104
2105 return 0;
2106}
2107
2108static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2109 struct kvm_lapic_state *s)
2110{
2111 vcpu_load(vcpu);
ad312c7c 2112 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2113 kvm_apic_post_state_restore(vcpu);
cb142eb7 2114 update_cr8_intercept(vcpu);
313a3dc7
CO		 2115 vcpu_put(vcpu);
2116
2117 return 0;
2118}
2119
f77bc6a4
ZX		 2120static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2121 struct kvm_interrupt *irq)
2122{
2123 if (irq->irq < 0 || irq->irq >= 256)
2124 return -EINVAL;
2125 if (irqchip_in_kernel(vcpu->kvm))
2126 return -ENXIO;
2127 vcpu_load(vcpu);
2128
66fd3f7f 2129 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2130
2131 vcpu_put(vcpu);
2132
2133 return 0;
2134}
2135
c4abb7c9
JK		 2136static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2137{
2138 vcpu_load(vcpu);
2139 kvm_inject_nmi(vcpu);
2140 vcpu_put(vcpu);
2141
2142 return 0;
2143}
2144
b209749f
AK		 2145static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2146 struct kvm_tpr_access_ctl *tac)
2147{
2148 if (tac->flags)
2149 return -EINVAL;
2150 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2151 return 0;
2152}
2153
890ca9ae
HY		 2154static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2155 u64 mcg_cap)
2156{
2157 int r;
2158 unsigned bank_num = mcg_cap & 0xff, bank;
2159
8fbf065d 2160 vcpu_load(vcpu);
890ca9ae 2161 r = -EINVAL;
a9e38c3e 2162 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2163 goto out;
2164 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2165 goto out;
2166 r = 0;
2167 vcpu->arch.mcg_cap = mcg_cap;
2168 /* Init IA32_MCG_CTL to all 1s */
2169 if (mcg_cap & MCG_CTL_P)
2170 vcpu->arch.mcg_ctl = ~(u64)0;
2171 /* Init IA32_MCi_CTL to all 1s */
2172 for (bank = 0; bank < bank_num; bank++)
2173 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2174out:
8fbf065d 2175 vcpu_put(vcpu);
890ca9ae
HY		 2176 return r;
2177}
2178
2179static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2180 struct kvm_x86_mce *mce)
2181{
2182 u64 mcg_cap = vcpu->arch.mcg_cap;
2183 unsigned bank_num = mcg_cap & 0xff;
2184 u64 *banks = vcpu->arch.mce_banks;
2185
2186 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2187 return -EINVAL;
2188 /*
2189 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2190 * reporting is disabled
2191 */
2192 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2193 vcpu->arch.mcg_ctl != ~(u64)0)
2194 return 0;
2195 banks += 4 * mce->bank;
2196 /*
2197 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2198 * reporting is disabled for the bank
2199 */
2200 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2201 return 0;
2202 if (mce->status & MCI_STATUS_UC) {
2203 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2204 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2205 printk(KERN_DEBUG "kvm: set_mce: "
2206 "injects mce exception while "
2207 "previous one is in progress!\n");
2208 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2209 return 0;
2210 }
2211 if (banks[1] & MCI_STATUS_VAL)
2212 mce->status |= MCI_STATUS_OVER;
2213 banks[2] = mce->addr;
2214 banks[3] = mce->misc;
2215 vcpu->arch.mcg_status = mce->mcg_status;
2216 banks[1] = mce->status;
2217 kvm_queue_exception(vcpu, MC_VECTOR);
2218 } else if (!(banks[1] & MCI_STATUS_VAL)
2219 || !(banks[1] & MCI_STATUS_UC)) {
2220 if (banks[1] & MCI_STATUS_VAL)
2221 mce->status |= MCI_STATUS_OVER;
2222 banks[2] = mce->addr;
2223 banks[3] = mce->misc;
2224 banks[1] = mce->status;
2225 } else
2226 banks[1] |= MCI_STATUS_OVER;
2227 return 0;
2228}
2229
3cfc3092
JK		 2230static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2231 struct kvm_vcpu_events *events)
2232{
2233 vcpu_load(vcpu);
2234
03b82a30
JK		 2235 events->exception.injected =
2236 vcpu->arch.exception.pending &&
2237 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2238 events->exception.nr = vcpu->arch.exception.nr;
2239 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2240 events->exception.error_code = vcpu->arch.exception.error_code;
2241
03b82a30
JK		 2242 events->interrupt.injected =
2243 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2244 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2245 events->interrupt.soft = 0;
48005f64
JK		 2246 events->interrupt.shadow =
2247 kvm_x86_ops->get_interrupt_shadow(vcpu,
2248 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2249
2250 events->nmi.injected = vcpu->arch.nmi_injected;
2251 events->nmi.pending = vcpu->arch.nmi_pending;
2252 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2253
2254 events->sipi_vector = vcpu->arch.sipi_vector;
2255
dab4b911 2256 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2257 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2258 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2259
2260 vcpu_put(vcpu);
2261}
2262
2263static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2264 struct kvm_vcpu_events *events)
2265{
dab4b911 2266 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2267 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2268 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2269 return -EINVAL;
2270
2271 vcpu_load(vcpu);
2272
2273 vcpu->arch.exception.pending = events->exception.injected;
2274 vcpu->arch.exception.nr = events->exception.nr;
2275 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2276 vcpu->arch.exception.error_code = events->exception.error_code;
2277
2278 vcpu->arch.interrupt.pending = events->interrupt.injected;
2279 vcpu->arch.interrupt.nr = events->interrupt.nr;
2280 vcpu->arch.interrupt.soft = events->interrupt.soft;
2281 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2282 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2283 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2284 kvm_x86_ops->set_interrupt_shadow(vcpu,
2285 events->interrupt.shadow);
3cfc3092
JK		 2286
2287 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2288 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2289 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2290 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2291
dab4b911
JK		 2292 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2293 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2294
2295 vcpu_put(vcpu);
2296
2297 return 0;
2298}
2299
a1efbe77
JK		 2300static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2301 struct kvm_debugregs *dbgregs)
2302{
2303 vcpu_load(vcpu);
2304
2305 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2306 dbgregs->dr6 = vcpu->arch.dr6;
2307 dbgregs->dr7 = vcpu->arch.dr7;
2308 dbgregs->flags = 0;
2309
2310 vcpu_put(vcpu);
2311}
2312
2313static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2314 struct kvm_debugregs *dbgregs)
2315{
2316 if (dbgregs->flags)
2317 return -EINVAL;
2318
2319 vcpu_load(vcpu);
2320
2321 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2322 vcpu->arch.dr6 = dbgregs->dr6;
2323 vcpu->arch.dr7 = dbgregs->dr7;
2324
2325 vcpu_put(vcpu);
2326
2327 return 0;
2328}
2329
313a3dc7
CO		 2330long kvm_arch_vcpu_ioctl(struct file *filp,
2331 unsigned int ioctl, unsigned long arg)
2332{
2333 struct kvm_vcpu *vcpu = filp->private_data;
2334 void __user *argp = (void __user *)arg;
2335 int r;
b772ff36 2336 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2337
2338 switch (ioctl) {
2339 case KVM_GET_LAPIC: {
2204ae3c
MT		 2340 r = -EINVAL;
2341 if (!vcpu->arch.apic)
2342 goto out;
b772ff36 2343 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2344
b772ff36
DH		 2345 r = -ENOMEM;
2346 if (!lapic)
2347 goto out;
2348 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2349 if (r)
2350 goto out;
2351 r = -EFAULT;
b772ff36 2352 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2353 goto out;
2354 r = 0;
2355 break;
2356 }
2357 case KVM_SET_LAPIC: {
2204ae3c
MT		 2358 r = -EINVAL;
2359 if (!vcpu->arch.apic)
2360 goto out;
b772ff36
DH		 2361 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2362 r = -ENOMEM;
2363 if (!lapic)
2364 goto out;
313a3dc7 2365 r = -EFAULT;
b772ff36 2366 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2367 goto out;
b772ff36 2368 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2369 if (r)
2370 goto out;
2371 r = 0;
2372 break;
2373 }
f77bc6a4
ZX		 2374 case KVM_INTERRUPT: {
2375 struct kvm_interrupt irq;
2376
2377 r = -EFAULT;
2378 if (copy_from_user(&irq, argp, sizeof irq))
2379 goto out;
2380 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2381 if (r)
2382 goto out;
2383 r = 0;
2384 break;
2385 }
c4abb7c9
JK		 2386 case KVM_NMI: {
2387 r = kvm_vcpu_ioctl_nmi(vcpu);
2388 if (r)
2389 goto out;
2390 r = 0;
2391 break;
2392 }
313a3dc7
CO		 2393 case KVM_SET_CPUID: {
2394 struct kvm_cpuid __user *cpuid_arg = argp;
2395 struct kvm_cpuid cpuid;
2396
2397 r = -EFAULT;
2398 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2399 goto out;
2400 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2401 if (r)
2402 goto out;
2403 break;
2404 }
07716717
DK		 2405 case KVM_SET_CPUID2: {
2406 struct kvm_cpuid2 __user *cpuid_arg = argp;
2407 struct kvm_cpuid2 cpuid;
2408
2409 r = -EFAULT;
2410 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2411 goto out;
2412 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2413 cpuid_arg->entries);
07716717
DK		 2414 if (r)
2415 goto out;
2416 break;
2417 }
2418 case KVM_GET_CPUID2: {
2419 struct kvm_cpuid2 __user *cpuid_arg = argp;
2420 struct kvm_cpuid2 cpuid;
2421
2422 r = -EFAULT;
2423 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2424 goto out;
2425 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2426 cpuid_arg->entries);
07716717
DK		 2427 if (r)
2428 goto out;
2429 r = -EFAULT;
2430 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2431 goto out;
2432 r = 0;
2433 break;
2434 }
313a3dc7
CO		 2435 case KVM_GET_MSRS:
2436 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2437 break;
2438 case KVM_SET_MSRS:
2439 r = msr_io(vcpu, argp, do_set_msr, 0);
2440 break;
b209749f
AK		 2441 case KVM_TPR_ACCESS_REPORTING: {
2442 struct kvm_tpr_access_ctl tac;
2443
2444 r = -EFAULT;
2445 if (copy_from_user(&tac, argp, sizeof tac))
2446 goto out;
2447 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2448 if (r)
2449 goto out;
2450 r = -EFAULT;
2451 if (copy_to_user(argp, &tac, sizeof tac))
2452 goto out;
2453 r = 0;
2454 break;
2455 };
b93463aa
AK		 2456 case KVM_SET_VAPIC_ADDR: {
2457 struct kvm_vapic_addr va;
2458
2459 r = -EINVAL;
2460 if (!irqchip_in_kernel(vcpu->kvm))
2461 goto out;
2462 r = -EFAULT;
2463 if (copy_from_user(&va, argp, sizeof va))
2464 goto out;
2465 r = 0;
2466 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2467 break;
2468 }
890ca9ae
HY		 2469 case KVM_X86_SETUP_MCE: {
2470 u64 mcg_cap;
2471
2472 r = -EFAULT;
2473 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2474 goto out;
2475 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2476 break;
2477 }
2478 case KVM_X86_SET_MCE: {
2479 struct kvm_x86_mce mce;
2480
2481 r = -EFAULT;
2482 if (copy_from_user(&mce, argp, sizeof mce))
2483 goto out;
8fbf065d 2484 vcpu_load(vcpu);
890ca9ae 2485 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
8fbf065d 2486 vcpu_put(vcpu);
890ca9ae
HY		 2487 break;
2488 }
3cfc3092
JK		 2489 case KVM_GET_VCPU_EVENTS: {
2490 struct kvm_vcpu_events events;
2491
2492 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2493
2494 r = -EFAULT;
2495 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2496 break;
2497 r = 0;
2498 break;
2499 }
2500 case KVM_SET_VCPU_EVENTS: {
2501 struct kvm_vcpu_events events;
2502
2503 r = -EFAULT;
2504 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2505 break;
2506
2507 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2508 break;
2509 }
a1efbe77
JK		 2510 case KVM_GET_DEBUGREGS: {
2511 struct kvm_debugregs dbgregs;
2512
2513 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2514
2515 r = -EFAULT;
2516 if (copy_to_user(argp, &dbgregs,
2517 sizeof(struct kvm_debugregs)))
2518 break;
2519 r = 0;
2520 break;
2521 }
2522 case KVM_SET_DEBUGREGS: {
2523 struct kvm_debugregs dbgregs;
2524
2525 r = -EFAULT;
2526 if (copy_from_user(&dbgregs, argp,
2527 sizeof(struct kvm_debugregs)))
2528 break;
2529
2530 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2531 break;
2532 }
313a3dc7
CO		 2533 default:
2534 r = -EINVAL;
2535 }
2536out:
7a6ce84c 2537 kfree(lapic);
313a3dc7
CO		 2538 return r;
2539}
2540
1fe779f8
CO		 2541static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2542{
2543 int ret;
2544
2545 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2546 return -1;
2547 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2548 return ret;
2549}
2550
b927a3ce
SY		 2551static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2552 u64 ident_addr)
2553{
2554 kvm->arch.ept_identity_map_addr = ident_addr;
2555 return 0;
2556}
2557
1fe779f8
CO		 2558static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2559 u32 kvm_nr_mmu_pages)
2560{
2561 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2562 return -EINVAL;
2563
79fac95e 2564 mutex_lock(&kvm->slots_lock);
7c8a83b7 2565 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2566
2567 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2568 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2569
7c8a83b7 2570 spin_unlock(&kvm->mmu_lock);
79fac95e 2571 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2572 return 0;
2573}
2574
2575static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2576{
f05e70ac 2577 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2578}
2579
a983fb23
MT		 2580gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2581{
2582 int i;
2583 struct kvm_mem_alias *alias;
2584 struct kvm_mem_aliases *aliases;
2585
90d83dc3 2586 aliases = kvm_aliases(kvm);
a983fb23
MT		 2587
2588 for (i = 0; i < aliases->naliases; ++i) {
2589 alias = &aliases->aliases[i];
2590 if (alias->flags & KVM_ALIAS_INVALID)
2591 continue;
2592 if (gfn >= alias->base_gfn
2593 && gfn < alias->base_gfn + alias->npages)
2594 return alias->target_gfn + gfn - alias->base_gfn;
2595 }
2596 return gfn;
2597}
2598
e9f85cde
ZX		 2599gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2600{
2601 int i;
2602 struct kvm_mem_alias *alias;
a983fb23
MT		 2603 struct kvm_mem_aliases *aliases;
2604
90d83dc3 2605 aliases = kvm_aliases(kvm);
e9f85cde 2606
fef9cce0
MT		 2607 for (i = 0; i < aliases->naliases; ++i) {
2608 alias = &aliases->aliases[i];
e9f85cde
ZX		 2609 if (gfn >= alias->base_gfn
2610 && gfn < alias->base_gfn + alias->npages)
2611 return alias->target_gfn + gfn - alias->base_gfn;
2612 }
2613 return gfn;
2614}
2615
1fe779f8
CO		 2616/*
2617 * Set a new alias region. Aliases map a portion of physical memory into
2618 * another portion. This is useful for memory windows, for example the PC
2619 * VGA region.
2620 */
2621static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2622 struct kvm_memory_alias *alias)
2623{
2624 int r, n;
2625 struct kvm_mem_alias *p;
a983fb23 2626 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2627
2628 r = -EINVAL;
2629 /* General sanity checks */
2630 if (alias->memory_size & (PAGE_SIZE - 1))
2631 goto out;
2632 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2633 goto out;
2634 if (alias->slot >= KVM_ALIAS_SLOTS)
2635 goto out;
2636 if (alias->guest_phys_addr + alias->memory_size
2637 < alias->guest_phys_addr)
2638 goto out;
2639 if (alias->target_phys_addr + alias->memory_size
2640 < alias->target_phys_addr)
2641 goto out;
2642
a983fb23
MT		 2643 r = -ENOMEM;
2644 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2645 if (!aliases)
2646 goto out;
2647
79fac95e 2648 mutex_lock(&kvm->slots_lock);
1fe779f8 2649
a983fb23
MT		 2650 /* invalidate any gfn reference in case of deletion/shrinking */
2651 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2652 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2653 old_aliases = kvm->arch.aliases;
2654 rcu_assign_pointer(kvm->arch.aliases, aliases);
2655 synchronize_srcu_expedited(&kvm->srcu);
2656 kvm_mmu_zap_all(kvm);
2657 kfree(old_aliases);
2658
2659 r = -ENOMEM;
2660 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2661 if (!aliases)
2662 goto out_unlock;
2663
2664 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2665
2666 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2667 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2668 p->npages = alias->memory_size >> PAGE_SHIFT;
2669 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2670 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2671
2672 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2673 if (aliases->aliases[n - 1].npages)
1fe779f8 2674 break;
fef9cce0 2675 aliases->naliases = n;
1fe779f8 2676
a983fb23
MT		 2677 old_aliases = kvm->arch.aliases;
2678 rcu_assign_pointer(kvm->arch.aliases, aliases);
2679 synchronize_srcu_expedited(&kvm->srcu);
2680 kfree(old_aliases);
2681 r = 0;
1fe779f8 2682
a983fb23 2683out_unlock:
79fac95e 2684 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2685out:
2686 return r;
2687}
2688
2689static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2690{
2691 int r;
2692
2693 r = 0;
2694 switch (chip->chip_id) {
2695 case KVM_IRQCHIP_PIC_MASTER:
2696 memcpy(&chip->chip.pic,
2697 &pic_irqchip(kvm)->pics[0],
2698 sizeof(struct kvm_pic_state));
2699 break;
2700 case KVM_IRQCHIP_PIC_SLAVE:
2701 memcpy(&chip->chip.pic,
2702 &pic_irqchip(kvm)->pics[1],
2703 sizeof(struct kvm_pic_state));
2704 break;
2705 case KVM_IRQCHIP_IOAPIC:
eba0226b 2706 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2707 break;
2708 default:
2709 r = -EINVAL;
2710 break;
2711 }
2712 return r;
2713}
2714
2715static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2716{
2717 int r;
2718
2719 r = 0;
2720 switch (chip->chip_id) {
2721 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2722 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2723 memcpy(&pic_irqchip(kvm)->pics[0],
2724 &chip->chip.pic,
2725 sizeof(struct kvm_pic_state));
fa8273e9 2726 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2727 break;
2728 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2729 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2730 memcpy(&pic_irqchip(kvm)->pics[1],
2731 &chip->chip.pic,
2732 sizeof(struct kvm_pic_state));
fa8273e9 2733 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2734 break;
2735 case KVM_IRQCHIP_IOAPIC:
eba0226b 2736 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2737 break;
2738 default:
2739 r = -EINVAL;
2740 break;
2741 }
2742 kvm_pic_update_irq(pic_irqchip(kvm));
2743 return r;
2744}
2745
e0f63cb9
SY		 2746static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2747{
2748 int r = 0;
2749
894a9c55 2750 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2751 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2752 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2753 return r;
2754}
2755
2756static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2757{
2758 int r = 0;
2759
894a9c55 2760 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2761 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2762 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2763 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2764 return r;
2765}
2766
2767static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2768{
2769 int r = 0;
2770
2771 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2772 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2773 sizeof(ps->channels));
2774 ps->flags = kvm->arch.vpit->pit_state.flags;
2775 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2776 return r;
2777}
2778
2779static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2780{
2781 int r = 0, start = 0;
2782 u32 prev_legacy, cur_legacy;
2783 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2784 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2785 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2786 if (!prev_legacy && cur_legacy)
2787 start = 1;
2788 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2789 sizeof(kvm->arch.vpit->pit_state.channels));
2790 kvm->arch.vpit->pit_state.flags = ps->flags;
2791 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2792 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2793 return r;
2794}
2795
52d939a0
MT		 2796static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2797 struct kvm_reinject_control *control)
2798{
2799 if (!kvm->arch.vpit)
2800 return -ENXIO;
894a9c55 2801 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2802 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2803 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2804 return 0;
2805}
2806
5bb064dc
ZX		 2807/*
2808 * Get (and clear) the dirty memory log for a memory slot.
2809 */
2810int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2811 struct kvm_dirty_log *log)
2812{
87bf6e7d 2813 int r, i;
5bb064dc 2814 struct kvm_memory_slot *memslot;
87bf6e7d 2815 unsigned long n;
b050b015 2816 unsigned long is_dirty = 0;
5bb064dc 2817
79fac95e 2818 mutex_lock(&kvm->slots_lock);
5bb064dc 2819
b050b015
MT		 2820 r = -EINVAL;
2821 if (log->slot >= KVM_MEMORY_SLOTS)
2822 goto out;
2823
2824 memslot = &kvm->memslots->memslots[log->slot];
2825 r = -ENOENT;
2826 if (!memslot->dirty_bitmap)
2827 goto out;
2828
87bf6e7d 2829 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2830
b050b015
MT		 2831 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2832 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2833
2834 /* If nothing is dirty, don't bother messing with page tables. */
2835 if (is_dirty) {
b050b015 2836 struct kvm_memslots *slots, *old_slots;
914ebccd 2837 unsigned long *dirty_bitmap;
b050b015 2838
7c8a83b7 2839 spin_lock(&kvm->mmu_lock);
5bb064dc 2840 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2841 spin_unlock(&kvm->mmu_lock);
b050b015 2842
914ebccd
TY		 2843 r = -ENOMEM;
2844 dirty_bitmap = vmalloc(n);
2845 if (!dirty_bitmap)
2846 goto out;
2847 memset(dirty_bitmap, 0, n);
b050b015 2848
914ebccd
TY		 2849 r = -ENOMEM;
2850 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2851 if (!slots) {
2852 vfree(dirty_bitmap);
2853 goto out;
2854 }
b050b015
MT		 2855 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2856 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2857
2858 old_slots = kvm->memslots;
2859 rcu_assign_pointer(kvm->memslots, slots);
2860 synchronize_srcu_expedited(&kvm->srcu);
2861 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2862 kfree(old_slots);
914ebccd
TY		 2863
2864 r = -EFAULT;
2865 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2866 vfree(dirty_bitmap);
2867 goto out;
2868 }
2869 vfree(dirty_bitmap);
2870 } else {
2871 r = -EFAULT;
2872 if (clear_user(log->dirty_bitmap, n))
2873 goto out;
5bb064dc 2874 }
b050b015 2875
5bb064dc
ZX		 2876 r = 0;
2877out:
79fac95e 2878 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2879 return r;
2880}
2881
1fe779f8
CO		 2882long kvm_arch_vm_ioctl(struct file *filp,
2883 unsigned int ioctl, unsigned long arg)
2884{
2885 struct kvm *kvm = filp->private_data;
2886 void __user *argp = (void __user *)arg;
367e1319 2887 int r = -ENOTTY;
f0d66275
DH		 2888 /*
2889 * This union makes it completely explicit to gcc-3.x
2890 * that these two variables' stack usage should be
2891 * combined, not added together.
2892 */
2893 union {
2894 struct kvm_pit_state ps;
e9f42757 2895 struct kvm_pit_state2 ps2;
f0d66275 2896 struct kvm_memory_alias alias;
c5ff41ce 2897 struct kvm_pit_config pit_config;
f0d66275 2898 } u;
1fe779f8
CO		 2899
2900 switch (ioctl) {
2901 case KVM_SET_TSS_ADDR:
2902 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2903 if (r < 0)
2904 goto out;
2905 break;
b927a3ce
SY		 2906 case KVM_SET_IDENTITY_MAP_ADDR: {
2907 u64 ident_addr;
2908
2909 r = -EFAULT;
2910 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2911 goto out;
2912 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2913 if (r < 0)
2914 goto out;
2915 break;
2916 }
1fe779f8
CO		 2917 case KVM_SET_MEMORY_REGION: {
2918 struct kvm_memory_region kvm_mem;
2919 struct kvm_userspace_memory_region kvm_userspace_mem;
2920
2921 r = -EFAULT;
2922 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2923 goto out;
2924 kvm_userspace_mem.slot = kvm_mem.slot;
2925 kvm_userspace_mem.flags = kvm_mem.flags;
2926 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2927 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2928 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2929 if (r)
2930 goto out;
2931 break;
2932 }
2933 case KVM_SET_NR_MMU_PAGES:
2934 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2935 if (r)
2936 goto out;
2937 break;
2938 case KVM_GET_NR_MMU_PAGES:
2939 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2940 break;
f0d66275 2941 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2942 r = -EFAULT;
f0d66275 2943 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2944 goto out;
f0d66275 2945 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2946 if (r)
2947 goto out;
2948 break;
3ddea128
MT		 2949 case KVM_CREATE_IRQCHIP: {
2950 struct kvm_pic *vpic;
2951
2952 mutex_lock(&kvm->lock);
2953 r = -EEXIST;
2954 if (kvm->arch.vpic)
2955 goto create_irqchip_unlock;
1fe779f8 2956 r = -ENOMEM;
3ddea128
MT		 2957 vpic = kvm_create_pic(kvm);
2958 if (vpic) {
1fe779f8
CO		 2959 r = kvm_ioapic_init(kvm);
2960 if (r) {
72bb2fcd
WY		 2961 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2962 &vpic->dev);
3ddea128
MT		 2963 kfree(vpic);
2964 goto create_irqchip_unlock;
1fe779f8
CO		 2965 }
2966 } else
3ddea128
MT		 2967 goto create_irqchip_unlock;
2968 smp_wmb();
2969 kvm->arch.vpic = vpic;
2970 smp_wmb();
399ec807
AK		 2971 r = kvm_setup_default_irq_routing(kvm);
2972 if (r) {
3ddea128 2973 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2974 kvm_ioapic_destroy(kvm);
2975 kvm_destroy_pic(kvm);
3ddea128 2976 mutex_unlock(&kvm->irq_lock);
399ec807 2977 }
3ddea128
MT		 2978 create_irqchip_unlock:
2979 mutex_unlock(&kvm->lock);
1fe779f8 2980 break;
3ddea128 2981 }
7837699f 2982 case KVM_CREATE_PIT:
c5ff41ce
JK		 2983 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2984 goto create_pit;
2985 case KVM_CREATE_PIT2:
2986 r = -EFAULT;
2987 if (copy_from_user(&u.pit_config, argp,
2988 sizeof(struct kvm_pit_config)))
2989 goto out;
2990 create_pit:
79fac95e 2991 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2992 r = -EEXIST;
2993 if (kvm->arch.vpit)
2994 goto create_pit_unlock;
7837699f 2995 r = -ENOMEM;
c5ff41ce 2996 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2997 if (kvm->arch.vpit)
2998 r = 0;
269e05e4 2999 create_pit_unlock:
79fac95e 3000 mutex_unlock(&kvm->slots_lock);
7837699f 3001 break;
4925663a 3002 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3003 case KVM_IRQ_LINE: {
3004 struct kvm_irq_level irq_event;
3005
3006 r = -EFAULT;
3007 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3008 goto out;
160d2f6c 3009 r = -ENXIO;
1fe779f8 3010 if (irqchip_in_kernel(kvm)) {
4925663a 3011 __s32 status;
4925663a
GN		 3012 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3013 irq_event.irq, irq_event.level);
4925663a 3014 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3015 r = -EFAULT;
4925663a
GN		 3016 irq_event.status = status;
3017 if (copy_to_user(argp, &irq_event,
3018 sizeof irq_event))
3019 goto out;
3020 }
1fe779f8
CO		 3021 r = 0;
3022 }
3023 break;
3024 }
3025 case KVM_GET_IRQCHIP: {
3026 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3027 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3028
f0d66275
DH		 3029 r = -ENOMEM;
3030 if (!chip)
1fe779f8 3031 goto out;
f0d66275
DH		 3032 r = -EFAULT;
3033 if (copy_from_user(chip, argp, sizeof *chip))
3034 goto get_irqchip_out;
1fe779f8
CO		 3035 r = -ENXIO;
3036 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3037 goto get_irqchip_out;
3038 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3039 if (r)
f0d66275 3040 goto get_irqchip_out;
1fe779f8 3041 r = -EFAULT;
f0d66275
DH		 3042 if (copy_to_user(argp, chip, sizeof *chip))
3043 goto get_irqchip_out;
1fe779f8 3044 r = 0;
f0d66275
DH		 3045 get_irqchip_out:
3046 kfree(chip);
3047 if (r)
3048 goto out;
1fe779f8
CO		 3049 break;
3050 }
3051 case KVM_SET_IRQCHIP: {
3052 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3053 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3054
f0d66275
DH		 3055 r = -ENOMEM;
3056 if (!chip)
1fe779f8 3057 goto out;
f0d66275
DH		 3058 r = -EFAULT;
3059 if (copy_from_user(chip, argp, sizeof *chip))
3060 goto set_irqchip_out;
1fe779f8
CO		 3061 r = -ENXIO;
3062 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3063 goto set_irqchip_out;
3064 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3065 if (r)
f0d66275 3066 goto set_irqchip_out;
1fe779f8 3067 r = 0;
f0d66275
DH		 3068 set_irqchip_out:
3069 kfree(chip);
3070 if (r)
3071 goto out;
1fe779f8
CO		 3072 break;
3073 }
e0f63cb9 3074 case KVM_GET_PIT: {
e0f63cb9 3075 r = -EFAULT;
f0d66275 3076 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3077 goto out;
3078 r = -ENXIO;
3079 if (!kvm->arch.vpit)
3080 goto out;
f0d66275 3081 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3082 if (r)
3083 goto out;
3084 r = -EFAULT;
f0d66275 3085 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3086 goto out;
3087 r = 0;
3088 break;
3089 }
3090 case KVM_SET_PIT: {
e0f63cb9 3091 r = -EFAULT;
f0d66275 3092 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3093 goto out;
3094 r = -ENXIO;
3095 if (!kvm->arch.vpit)
3096 goto out;
f0d66275 3097 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3098 if (r)
3099 goto out;
3100 r = 0;
3101 break;
3102 }
e9f42757
BK		 3103 case KVM_GET_PIT2: {
3104 r = -ENXIO;
3105 if (!kvm->arch.vpit)
3106 goto out;
3107 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3108 if (r)
3109 goto out;
3110 r = -EFAULT;
3111 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3112 goto out;
3113 r = 0;
3114 break;
3115 }
3116 case KVM_SET_PIT2: {
3117 r = -EFAULT;
3118 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3119 goto out;
3120 r = -ENXIO;
3121 if (!kvm->arch.vpit)
3122 goto out;
3123 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3124 if (r)
3125 goto out;
3126 r = 0;
3127 break;
3128 }
52d939a0
MT		 3129 case KVM_REINJECT_CONTROL: {
3130 struct kvm_reinject_control control;
3131 r = -EFAULT;
3132 if (copy_from_user(&control, argp, sizeof(control)))
3133 goto out;
3134 r = kvm_vm_ioctl_reinject(kvm, &control);
3135 if (r)
3136 goto out;
3137 r = 0;
3138 break;
3139 }
ffde22ac
ES		 3140 case KVM_XEN_HVM_CONFIG: {
3141 r = -EFAULT;
3142 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3143 sizeof(struct kvm_xen_hvm_config)))
3144 goto out;
3145 r = -EINVAL;
3146 if (kvm->arch.xen_hvm_config.flags)
3147 goto out;
3148 r = 0;
3149 break;
3150 }
afbcf7ab
GC		 3151 case KVM_SET_CLOCK: {
3152 struct timespec now;
3153 struct kvm_clock_data user_ns;
3154 u64 now_ns;
3155 s64 delta;
3156
3157 r = -EFAULT;
3158 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3159 goto out;
3160
3161 r = -EINVAL;
3162 if (user_ns.flags)
3163 goto out;
3164
3165 r = 0;
3166 ktime_get_ts(&now);
3167 now_ns = timespec_to_ns(&now);
3168 delta = user_ns.clock - now_ns;
3169 kvm->arch.kvmclock_offset = delta;
3170 break;
3171 }
3172 case KVM_GET_CLOCK: {
3173 struct timespec now;
3174 struct kvm_clock_data user_ns;
3175 u64 now_ns;
3176
3177 ktime_get_ts(&now);
3178 now_ns = timespec_to_ns(&now);
3179 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3180 user_ns.flags = 0;
3181
3182 r = -EFAULT;
3183 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3184 goto out;
3185 r = 0;
3186 break;
3187 }
3188
1fe779f8
CO		 3189 default:
3190 ;
3191 }
3192out:
3193 return r;
3194}
3195
a16b043c 3196static void kvm_init_msr_list(void)
043405e1
CO		 3197{
3198 u32 dummy[2];
3199 unsigned i, j;
3200
e3267cbb
GC		 3201 /* skip the first msrs in the list. KVM-specific */
3202 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3203 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3204 continue;
3205 if (j < i)
3206 msrs_to_save[j] = msrs_to_save[i];
3207 j++;
3208 }
3209 num_msrs_to_save = j;
3210}
3211
bda9020e
MT		 3212static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3213 const void *v)
bbd9b64e 3214{
bda9020e
MT		 3215 if (vcpu->arch.apic &&
3216 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3217 return 0;
bbd9b64e 3218
e93f8a0f 3219 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3220}
3221
bda9020e 3222static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3223{
bda9020e
MT		 3224 if (vcpu->arch.apic &&
3225 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3226 return 0;
bbd9b64e 3227
e93f8a0f 3228 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3229}
3230
2dafc6c2
GN		 3231static void kvm_set_segment(struct kvm_vcpu *vcpu,
3232 struct kvm_segment *var, int seg)
3233{
3234 kvm_x86_ops->set_segment(vcpu, var, seg);
3235}
3236
3237void kvm_get_segment(struct kvm_vcpu *vcpu,
3238 struct kvm_segment *var, int seg)
3239{
3240 kvm_x86_ops->get_segment(vcpu, var, seg);
3241}
3242
1871c602
GN		 3243gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3244{
3245 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3246 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3247}
3248
3249 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3250{
3251 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3252 access |= PFERR_FETCH_MASK;
3253 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3254}
3255
3256gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3257{
3258 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3259 access |= PFERR_WRITE_MASK;
3260 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3261}
3262
3263/* uses this to access any guest's mapped memory without checking CPL */
3264gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3265{
3266 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3267}
3268
3269static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3270 struct kvm_vcpu *vcpu, u32 access,
3271 u32 *error)
bbd9b64e
CO		 3272{
3273 void *data = val;
10589a46 3274 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3275
3276 while (bytes) {
1871c602 3277 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3278 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3279 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3280 int ret;
3281
10589a46
MT		 3282 if (gpa == UNMAPPED_GVA) {
3283 r = X86EMUL_PROPAGATE_FAULT;
3284 goto out;
3285 }
77c2002e 3286 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3287 if (ret < 0) {
c3cd7ffa 3288 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3289 goto out;
3290 }
bbd9b64e 3291
77c2002e
IE		 3292 bytes -= toread;
3293 data += toread;
3294 addr += toread;
bbd9b64e 3295 }
10589a46 3296out:
10589a46 3297 return r;
bbd9b64e 3298}
77c2002e 3299
1871c602
GN		 3300/* used for instruction fetching */
3301static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3302 struct kvm_vcpu *vcpu, u32 *error)
3303{
3304 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3305 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3306 access | PFERR_FETCH_MASK, error);
3307}
3308
3309static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3310 struct kvm_vcpu *vcpu, u32 *error)
3311{
3312 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3313 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3314 error);
3315}
3316
3317static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3318 struct kvm_vcpu *vcpu, u32 *error)
3319{
3320 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3321}
3322
7972995b 3323static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3324 unsigned int bytes,
7972995b 3325 struct kvm_vcpu *vcpu,
2dafc6c2 3326 u32 *error)
77c2002e
IE		 3327{
3328 void *data = val;
3329 int r = X86EMUL_CONTINUE;
3330
3331 while (bytes) {
7972995b
GN		 3332 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3333 PFERR_WRITE_MASK, error);
77c2002e
IE		 3334 unsigned offset = addr & (PAGE_SIZE-1);
3335 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3336 int ret;
3337
3338 if (gpa == UNMAPPED_GVA) {
3339 r = X86EMUL_PROPAGATE_FAULT;
3340 goto out;
3341 }
3342 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3343 if (ret < 0) {
c3cd7ffa 3344 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3345 goto out;
3346 }
3347
3348 bytes -= towrite;
3349 data += towrite;
3350 addr += towrite;
3351 }
3352out:
3353 return r;
3354}
3355
bbd9b64e
CO		 3356static int emulator_read_emulated(unsigned long addr,
3357 void *val,
3358 unsigned int bytes,
8fe681e9 3359 unsigned int *error_code,
bbd9b64e
CO		 3360 struct kvm_vcpu *vcpu)
3361{
bbd9b64e
CO		 3362 gpa_t gpa;
3363
3364 if (vcpu->mmio_read_completed) {
3365 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3366 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3367 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3368 vcpu->mmio_read_completed = 0;
3369 return X86EMUL_CONTINUE;
3370 }
3371
8fe681e9 3372 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3373
8fe681e9 3374 if (gpa == UNMAPPED_GVA)
1871c602 3375 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3376
3377 /* For APIC access vmexit */
3378 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3379 goto mmio;
3380
1871c602 3381 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3382 == X86EMUL_CONTINUE)
bbd9b64e 3383 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3384
3385mmio:
3386 /*
3387 * Is this MMIO handled locally?
3388 */
aec51dc4
AK		 3389 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3390 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3391 return X86EMUL_CONTINUE;
3392 }
aec51dc4
AK		 3393
3394 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3395
3396 vcpu->mmio_needed = 1;
411c35b7
GN		 3397 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3398 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3399 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3400 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3401
c3cd7ffa 3402 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3403}
3404
3200f405 3405int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3406 const void *val, int bytes)
bbd9b64e
CO		 3407{
3408 int ret;
3409
3410 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3411 if (ret < 0)
bbd9b64e 3412 return 0;
ad218f85 3413 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3414 return 1;
3415}
3416
3417static int emulator_write_emulated_onepage(unsigned long addr,
3418 const void *val,
3419 unsigned int bytes,
8fe681e9 3420 unsigned int *error_code,
bbd9b64e
CO		 3421 struct kvm_vcpu *vcpu)
3422{
10589a46
MT		 3423 gpa_t gpa;
3424
8fe681e9 3425 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3426
8fe681e9 3427 if (gpa == UNMAPPED_GVA)
bbd9b64e 3428 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3429
3430 /* For APIC access vmexit */
3431 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3432 goto mmio;
3433
3434 if (emulator_write_phys(vcpu, gpa, val, bytes))
3435 return X86EMUL_CONTINUE;
3436
3437mmio:
aec51dc4 3438 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3439 /*
3440 * Is this MMIO handled locally?
3441 */
bda9020e 3442 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3443 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3444
3445 vcpu->mmio_needed = 1;
411c35b7
GN		 3446 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3447 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3448 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3449 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3450 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3451
3452 return X86EMUL_CONTINUE;
3453}
3454
3455int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3456 const void *val,
3457 unsigned int bytes,
8fe681e9 3458 unsigned int *error_code,
8f6abd06 3459 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3460{
3461 /* Crossing a page boundary? */
3462 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3463 int rc, now;
3464
3465 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3466 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3467 vcpu);
bbd9b64e
CO		 3468 if (rc != X86EMUL_CONTINUE)
3469 return rc;
3470 addr += now;
3471 val += now;
3472 bytes -= now;
3473 }
8fe681e9
GN		 3474 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3475 vcpu);
bbd9b64e 3476}
bbd9b64e 3477
daea3e73
AK		 3478#define CMPXCHG_TYPE(t, ptr, old, new) \
3479 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3480
3481#ifdef CONFIG_X86_64
3482# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3483#else
3484# define CMPXCHG64(ptr, old, new) \
9749a6c0 3485 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3486#endif
3487
bbd9b64e
CO		 3488static int emulator_cmpxchg_emulated(unsigned long addr,
3489 const void *old,
3490 const void *new,
3491 unsigned int bytes,
8fe681e9 3492 unsigned int *error_code,
bbd9b64e
CO		 3493 struct kvm_vcpu *vcpu)
3494{
daea3e73
AK		 3495 gpa_t gpa;
3496 struct page *page;
3497 char *kaddr;
3498 bool exchanged;
2bacc55c 3499
daea3e73
AK		 3500 /* guests cmpxchg8b have to be emulated atomically */
3501 if (bytes > 8 || (bytes & (bytes - 1)))
3502 goto emul_write;
10589a46 3503
daea3e73 3504 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3505
daea3e73
AK		 3506 if (gpa == UNMAPPED_GVA ||
3507 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3508 goto emul_write;
2bacc55c 3509
daea3e73
AK		 3510 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3511 goto emul_write;
72dc67a6 3512
daea3e73 3513 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3514
daea3e73
AK		 3515 kaddr = kmap_atomic(page, KM_USER0);
3516 kaddr += offset_in_page(gpa);
3517 switch (bytes) {
3518 case 1:
3519 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3520 break;
3521 case 2:
3522 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3523 break;
3524 case 4:
3525 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3526 break;
3527 case 8:
3528 exchanged = CMPXCHG64(kaddr, old, new);
3529 break;
3530 default:
3531 BUG();
2bacc55c 3532 }
daea3e73
AK		 3533 kunmap_atomic(kaddr, KM_USER0);
3534 kvm_release_page_dirty(page);
3535
3536 if (!exchanged)
3537 return X86EMUL_CMPXCHG_FAILED;
3538
8f6abd06
GN		 3539 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3540
3541 return X86EMUL_CONTINUE;
4a5f48f6 3542
3200f405 3543emul_write:
daea3e73 3544 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3545
8fe681e9 3546 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3547}
3548
cf8f70bf
GN		 3549static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3550{
3551 /* TODO: String I/O for in kernel device */
3552 int r;
3553
3554 if (vcpu->arch.pio.in)
3555 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3556 vcpu->arch.pio.size, pd);
3557 else
3558 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3559 vcpu->arch.pio.port, vcpu->arch.pio.size,
3560 pd);
3561 return r;
3562}
3563
3564
3565static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3566 unsigned int count, struct kvm_vcpu *vcpu)
3567{
7972995b 3568 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3569 goto data_avail;
3570
3571 trace_kvm_pio(1, port, size, 1);
3572
3573 vcpu->arch.pio.port = port;
3574 vcpu->arch.pio.in = 1;
7972995b 3575 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3576 vcpu->arch.pio.size = size;
3577
3578 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3579 data_avail:
3580 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3581 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3582 return 1;
3583 }
3584
3585 vcpu->run->exit_reason = KVM_EXIT_IO;
3586 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3587 vcpu->run->io.size = size;
3588 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3589 vcpu->run->io.count = count;
3590 vcpu->run->io.port = port;
3591
3592 return 0;
3593}
3594
3595static int emulator_pio_out_emulated(int size, unsigned short port,
3596 const void *val, unsigned int count,
3597 struct kvm_vcpu *vcpu)
3598{
3599 trace_kvm_pio(0, port, size, 1);
3600
3601 vcpu->arch.pio.port = port;
3602 vcpu->arch.pio.in = 0;
7972995b 3603 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3604 vcpu->arch.pio.size = size;
3605
3606 memcpy(vcpu->arch.pio_data, val, size * count);
3607
3608 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3609 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3610 return 1;
3611 }
3612
3613 vcpu->run->exit_reason = KVM_EXIT_IO;
3614 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3615 vcpu->run->io.size = size;
3616 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3617 vcpu->run->io.count = count;
3618 vcpu->run->io.port = port;
3619
3620 return 0;
3621}
3622
bbd9b64e
CO		 3623static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3624{
3625 return kvm_x86_ops->get_segment_base(vcpu, seg);
3626}
3627
3628int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3629{
a7052897 3630 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3631 return X86EMUL_CONTINUE;
3632}
3633
3634int emulate_clts(struct kvm_vcpu *vcpu)
3635{
4d4ec087 3636 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3637 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3638 return X86EMUL_CONTINUE;
3639}
3640
35aa5375 3641int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3642{
338dbc97 3643 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3644}
3645
35aa5375 3646int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3647{
338dbc97
GN		 3648
3649 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3650}
3651
52a46617 3652static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3653{
52a46617 3654 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3655}
3656
52a46617 3657static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3658{
52a46617
GN		 3659 unsigned long value;
3660
3661 switch (cr) {
3662 case 0:
3663 value = kvm_read_cr0(vcpu);
3664 break;
3665 case 2:
3666 value = vcpu->arch.cr2;
3667 break;
3668 case 3:
3669 value = vcpu->arch.cr3;
3670 break;
3671 case 4:
3672 value = kvm_read_cr4(vcpu);
3673 break;
3674 case 8:
3675 value = kvm_get_cr8(vcpu);
3676 break;
3677 default:
3678 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3679 return 0;
3680 }
3681
3682 return value;
3683}
3684
0f12244f 3685static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3686{
0f12244f
GN		 3687 int res = 0;
3688
52a46617
GN		 3689 switch (cr) {
3690 case 0:
0f12244f 3691 res = __kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3692 break;
3693 case 2:
3694 vcpu->arch.cr2 = val;
3695 break;
3696 case 3:
0f12244f 3697 res = __kvm_set_cr3(vcpu, val);
52a46617
GN		 3698 break;
3699 case 4:
0f12244f 3700 res = __kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3701 break;
3702 case 8:
0f12244f 3703 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3704 break;
3705 default:
3706 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3707 res = -1;
52a46617 3708 }
0f12244f
GN		 3709
3710 return res;
52a46617
GN		 3711}
3712
9c537244
GN		 3713static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3714{
3715 return kvm_x86_ops->get_cpl(vcpu);
3716}
3717
2dafc6c2
GN		 3718static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3719{
3720 kvm_x86_ops->get_gdt(vcpu, dt);
3721}
3722
5951c442
GN		 3723static unsigned long emulator_get_cached_segment_base(int seg,
3724 struct kvm_vcpu *vcpu)
3725{
3726 return get_segment_base(vcpu, seg);
3727}
3728
2dafc6c2
GN		 3729static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3730 struct kvm_vcpu *vcpu)
3731{
3732 struct kvm_segment var;
3733
3734 kvm_get_segment(vcpu, &var, seg);
3735
3736 if (var.unusable)
3737 return false;
3738
3739 if (var.g)
3740 var.limit >>= 12;
3741 set_desc_limit(desc, var.limit);
3742 set_desc_base(desc, (unsigned long)var.base);
3743 desc->type = var.type;
3744 desc->s = var.s;
3745 desc->dpl = var.dpl;
3746 desc->p = var.present;
3747 desc->avl = var.avl;
3748 desc->l = var.l;
3749 desc->d = var.db;
3750 desc->g = var.g;
3751
3752 return true;
3753}
3754
3755static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3756 struct kvm_vcpu *vcpu)
3757{
3758 struct kvm_segment var;
3759
3760 /* needed to preserve selector */
3761 kvm_get_segment(vcpu, &var, seg);
3762
3763 var.base = get_desc_base(desc);
3764 var.limit = get_desc_limit(desc);
3765 if (desc->g)
3766 var.limit = (var.limit << 12) | 0xfff;
3767 var.type = desc->type;
3768 var.present = desc->p;
3769 var.dpl = desc->dpl;
3770 var.db = desc->d;
3771 var.s = desc->s;
3772 var.l = desc->l;
3773 var.g = desc->g;
3774 var.avl = desc->avl;
3775 var.present = desc->p;
3776 var.unusable = !var.present;
3777 var.padding = 0;
3778
3779 kvm_set_segment(vcpu, &var, seg);
3780 return;
3781}
3782
3783static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3784{
3785 struct kvm_segment kvm_seg;
3786
3787 kvm_get_segment(vcpu, &kvm_seg, seg);
3788 return kvm_seg.selector;
3789}
3790
3791static void emulator_set_segment_selector(u16 sel, int seg,
3792 struct kvm_vcpu *vcpu)
3793{
3794 struct kvm_segment kvm_seg;
3795
3796 kvm_get_segment(vcpu, &kvm_seg, seg);
3797 kvm_seg.selector = sel;
3798 kvm_set_segment(vcpu, &kvm_seg, seg);
3799}
3800
14af3f3c 3801static struct x86_emulate_ops emulate_ops = {
1871c602 3802 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3803 .write_std = kvm_write_guest_virt_system,
1871c602 3804 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3805 .read_emulated = emulator_read_emulated,
3806 .write_emulated = emulator_write_emulated,
3807 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3808 .pio_in_emulated = emulator_pio_in_emulated,
3809 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3810 .get_cached_descriptor = emulator_get_cached_descriptor,
3811 .set_cached_descriptor = emulator_set_cached_descriptor,
3812 .get_segment_selector = emulator_get_segment_selector,
3813 .set_segment_selector = emulator_set_segment_selector,
5951c442 3814 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3815 .get_gdt = emulator_get_gdt,
52a46617
GN		 3816 .get_cr = emulator_get_cr,
3817 .set_cr = emulator_set_cr,
9c537244 3818 .cpl = emulator_get_cpl,
35aa5375
GN		 3819 .get_dr = emulator_get_dr,
3820 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3821 .set_msr = kvm_set_msr,
3822 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3823};
3824
5fdbf976
MT		 3825static void cache_all_regs(struct kvm_vcpu *vcpu)
3826{
3827 kvm_register_read(vcpu, VCPU_REGS_RAX);
3828 kvm_register_read(vcpu, VCPU_REGS_RSP);
3829 kvm_register_read(vcpu, VCPU_REGS_RIP);
3830 vcpu->arch.regs_dirty = ~0;
3831}
3832
95cb2295
GN		 3833static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3834{
3835 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3836 /*
3837 * an sti; sti; sequence only disable interrupts for the first
3838 * instruction. So, if the last instruction, be it emulated or
3839 * not, left the system with the INT_STI flag enabled, it
3840 * means that the last instruction is an sti. We should not
3841 * leave the flag on in this case. The same goes for mov ss
3842 */
3843 if (!(int_shadow & mask))
3844 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3845}
3846
54b8486f
GN		 3847static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3848{
3849 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3850 if (ctxt->exception == PF_VECTOR)
3851 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3852 else if (ctxt->error_code_valid)
3853 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3854 else
3855 kvm_queue_exception(vcpu, ctxt->exception);
3856}
3857
6d77dbfc
GN		 3858static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3859{
6d77dbfc
GN		 3860 ++vcpu->stat.insn_emulation_fail;
3861 trace_kvm_emulate_insn_failed(vcpu);
3862 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3863 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3864 vcpu->run->internal.ndata = 0;
3865 kvm_queue_exception(vcpu, UD_VECTOR);
3866 return EMULATE_FAIL;
3867}
3868
bbd9b64e 3869int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3870 unsigned long cr2,
3871 u16 error_code,
571008da 3872 int emulation_type)
bbd9b64e 3873{
95cb2295 3874 int r;
4d2179e1 3875 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3876
26eef70c 3877 kvm_clear_exception_queue(vcpu);
ad312c7c 3878 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3879 /*
56e82318 3880 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3881 * instead of direct ->regs accesses, can save hundred cycles
3882 * on Intel for instructions that don't read/change RSP, for
3883 * for example.
3884 */
3885 cache_all_regs(vcpu);
bbd9b64e 3886
571008da 3887 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3888 int cs_db, cs_l;
3889 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3890
ad312c7c 3891 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3892 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3893 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3894 vcpu->arch.emulate_ctxt.mode =
a0044755 3895 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3896 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3897 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3898 ? X86EMUL_MODE_PROT64 : cs_db
3899 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3900 memset(c, 0, sizeof(struct decode_cache));
3901 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3902 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 3903 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 3904
ad312c7c 3905 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3906 trace_kvm_emulate_insn_start(vcpu);
571008da 3907
0cb5762e
AP		 3908 /* Only allow emulation of specific instructions on #UD
3909 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 3910 if (emulation_type & EMULTYPE_TRAP_UD) {
3911 if (!c->twobyte)
3912 return EMULATE_FAIL;
3913 switch (c->b) {
3914 case 0x01: /* VMMCALL */
3915 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3916 return EMULATE_FAIL;
3917 break;
3918 case 0x34: /* sysenter */
3919 case 0x35: /* sysexit */
3920 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3921 return EMULATE_FAIL;
3922 break;
3923 case 0x05: /* syscall */
3924 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3925 return EMULATE_FAIL;
3926 break;
3927 default:
3928 return EMULATE_FAIL;
3929 }
3930
3931 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3932 return EMULATE_FAIL;
3933 }
571008da 3934
f2b5756b 3935 ++vcpu->stat.insn_emulation;
bbd9b64e
CO		 3936 if (r) {
3937 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3938 return EMULATE_DONE;
6d77dbfc
GN		 3939 if (emulation_type & EMULTYPE_SKIP)
3940 return EMULATE_FAIL;
3941 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3942 }
3943 }
3944
ba8afb6b
GN		 3945 if (emulation_type & EMULTYPE_SKIP) {
3946 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3947 return EMULATE_DONE;
3948 }
3949
4d2179e1
GN		 3950 /* this is needed for vmware backdor interface to work since it
3951 changes registers values during IO operation */
3952 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
3953
5cd21917 3954restart:
ad312c7c 3955 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 3956
c3cd7ffa
GN		 3957 if (r) { /* emulation failed */
3958 /*
3959 * if emulation was due to access to shadowed page table
3960 * and it failed try to unshadow page and re-entetr the
3961 * guest to let CPU execute the instruction.
3962 */
3963 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3964 return EMULATE_DONE;
3965
6d77dbfc 3966 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3967 }
3968
95cb2295 3969 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 3970 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 3971 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 3972 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 3973
54b8486f
GN		 3974 if (vcpu->arch.emulate_ctxt.exception >= 0) {
3975 inject_emulated_exception(vcpu);
3976 return EMULATE_DONE;
3977 }
3978
3457e419
GN		 3979 if (vcpu->arch.pio.count) {
3980 if (!vcpu->arch.pio.in)
3981 vcpu->arch.pio.count = 0;
3982 return EMULATE_DO_MMIO;
3983 }
3984
3985 if (vcpu->mmio_needed) {
3986 if (vcpu->mmio_is_write)
3987 vcpu->mmio_needed = 0;
3988 return EMULATE_DO_MMIO;
3989 }
3990
5cd21917
GN		 3991 if (vcpu->arch.emulate_ctxt.restart)
3992 goto restart;
f850e2e6 3993
bbd9b64e 3994 return EMULATE_DONE;
de7d789a 3995}
bbd9b64e 3996EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 3997
cf8f70bf 3998int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 3999{
cf8f70bf
GN		 4000 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4001 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4002 /* do not return to emulator after return from userspace */
7972995b 4003 vcpu->arch.pio.count = 0;
de7d789a
CO		 4004 return ret;
4005}
cf8f70bf 4006EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4007
c8076604
GH		 4008static void bounce_off(void *info)
4009{
4010 /* nothing */
4011}
4012
c8076604
GH		 4013static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4014 void *data)
4015{
4016 struct cpufreq_freqs *freq = data;
4017 struct kvm *kvm;
4018 struct kvm_vcpu *vcpu;
4019 int i, send_ipi = 0;
4020
c8076604
GH		 4021 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4022 return 0;
4023 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4024 return 0;
0cca7907 4025 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 4026
4027 spin_lock(&kvm_lock);
4028 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4029 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4030 if (vcpu->cpu != freq->cpu)
4031 continue;
4032 if (!kvm_request_guest_time_update(vcpu))
4033 continue;
4034 if (vcpu->cpu != smp_processor_id())
4035 send_ipi++;
4036 }
4037 }
4038 spin_unlock(&kvm_lock);
4039
4040 if (freq->old < freq->new && send_ipi) {
4041 /*
4042 * We upscale the frequency. Must make the guest
4043 * doesn't see old kvmclock values while running with
4044 * the new frequency, otherwise we risk the guest sees
4045 * time go backwards.
4046 *
4047 * In case we update the frequency for another cpu
4048 * (which might be in guest context) send an interrupt
4049 * to kick the cpu out of guest context. Next time
4050 * guest context is entered kvmclock will be updated,
4051 * so the guest will not see stale values.
4052 */
4053 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4054 }
4055 return 0;
4056}
4057
4058static struct notifier_block kvmclock_cpufreq_notifier_block = {
4059 .notifier_call = kvmclock_cpufreq_notifier
4060};
4061
b820cc0c
ZA		 4062static void kvm_timer_init(void)
4063{
4064 int cpu;
4065
b820cc0c 4066 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4067 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4068 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4069 for_each_online_cpu(cpu) {
4070 unsigned long khz = cpufreq_get(cpu);
4071 if (!khz)
4072 khz = tsc_khz;
4073 per_cpu(cpu_tsc_khz, cpu) = khz;
4074 }
0cca7907
ZA		 4075 } else {
4076 for_each_possible_cpu(cpu)
4077 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4078 }
4079}
4080
ff9d07a0
ZY		 4081static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4082
4083static int kvm_is_in_guest(void)
4084{
4085 return percpu_read(current_vcpu) != NULL;
4086}
4087
4088static int kvm_is_user_mode(void)
4089{
4090 int user_mode = 3;
dcf46b94 4091
ff9d07a0
ZY		 4092 if (percpu_read(current_vcpu))
4093 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4094
ff9d07a0
ZY		 4095 return user_mode != 0;
4096}
4097
4098static unsigned long kvm_get_guest_ip(void)
4099{
4100 unsigned long ip = 0;
dcf46b94 4101
ff9d07a0
ZY		 4102 if (percpu_read(current_vcpu))
4103 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4104
ff9d07a0
ZY		 4105 return ip;
4106}
4107
4108static struct perf_guest_info_callbacks kvm_guest_cbs = {
4109 .is_in_guest = kvm_is_in_guest,
4110 .is_user_mode = kvm_is_user_mode,
4111 .get_guest_ip = kvm_get_guest_ip,
4112};
4113
4114void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4115{
4116 percpu_write(current_vcpu, vcpu);
4117}
4118EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4119
4120void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4121{
4122 percpu_write(current_vcpu, NULL);
4123}
4124EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4125
f8c16bba 4126int kvm_arch_init(void *opaque)
043405e1 4127{
b820cc0c 4128 int r;
f8c16bba
ZX		 4129 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4130
f8c16bba
ZX		 4131 if (kvm_x86_ops) {
4132 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4133 r = -EEXIST;
4134 goto out;
f8c16bba
ZX		 4135 }
4136
4137 if (!ops->cpu_has_kvm_support()) {
4138 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4139 r = -EOPNOTSUPP;
4140 goto out;
f8c16bba
ZX		 4141 }
4142 if (ops->disabled_by_bios()) {
4143 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4144 r = -EOPNOTSUPP;
4145 goto out;
f8c16bba
ZX		 4146 }
4147
97db56ce
AK		 4148 r = kvm_mmu_module_init();
4149 if (r)
4150 goto out;
4151
4152 kvm_init_msr_list();
4153
f8c16bba 4154 kvm_x86_ops = ops;
56c6d28a 4155 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4156 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4157 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4158 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4159
b820cc0c 4160 kvm_timer_init();
c8076604 4161
ff9d07a0
ZY		 4162 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4163
f8c16bba 4164 return 0;
56c6d28a
ZX		 4165
4166out:
56c6d28a 4167 return r;
043405e1 4168}
8776e519 4169
f8c16bba
ZX		 4170void kvm_arch_exit(void)
4171{
ff9d07a0
ZY		 4172 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4173
888d256e
JK		 4174 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4175 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4176 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4177 kvm_x86_ops = NULL;
56c6d28a
ZX		 4178 kvm_mmu_module_exit();
4179}
f8c16bba 4180
8776e519
HB		 4181int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4182{
4183 ++vcpu->stat.halt_exits;
4184 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4185 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4186 return 1;
4187 } else {
4188 vcpu->run->exit_reason = KVM_EXIT_HLT;
4189 return 0;
4190 }
4191}
4192EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4193
2f333bcb
MT		 4194static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4195 unsigned long a1)
4196{
4197 if (is_long_mode(vcpu))
4198 return a0;
4199 else
4200 return a0 | ((gpa_t)a1 << 32);
4201}
4202
55cd8e5a
GN		 4203int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4204{
4205 u64 param, ingpa, outgpa, ret;
4206 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4207 bool fast, longmode;
4208 int cs_db, cs_l;
4209
4210 /*
4211 * hypercall generates UD from non zero cpl and real mode
4212 * per HYPER-V spec
4213 */
3eeb3288 4214 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4215 kvm_queue_exception(vcpu, UD_VECTOR);
4216 return 0;
4217 }
4218
4219 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4220 longmode = is_long_mode(vcpu) && cs_l == 1;
4221
4222 if (!longmode) {
ccd46936
GN		 4223 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4224 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4225 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4226 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4227 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4228 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4229 }
4230#ifdef CONFIG_X86_64
4231 else {
4232 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4233 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4234 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4235 }
4236#endif
4237
4238 code = param & 0xffff;
4239 fast = (param >> 16) & 0x1;
4240 rep_cnt = (param >> 32) & 0xfff;
4241 rep_idx = (param >> 48) & 0xfff;
4242
4243 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4244
c25bc163
GN		 4245 switch (code) {
4246 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4247 kvm_vcpu_on_spin(vcpu);
4248 break;
4249 default:
4250 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4251 break;
4252 }
55cd8e5a
GN		 4253
4254 ret = res | (((u64)rep_done & 0xfff) << 32);
4255 if (longmode) {
4256 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4257 } else {
4258 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4259 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4260 }
4261
4262 return 1;
4263}
4264
8776e519
HB		 4265int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4266{
4267 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4268 int r = 1;
8776e519 4269
55cd8e5a
GN		 4270 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4271 return kvm_hv_hypercall(vcpu);
4272
5fdbf976
MT		 4273 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4274 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4275 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4276 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4277 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4278
229456fc 4279 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4280
8776e519
HB		 4281 if (!is_long_mode(vcpu)) {
4282 nr &= 0xFFFFFFFF;
4283 a0 &= 0xFFFFFFFF;
4284 a1 &= 0xFFFFFFFF;
4285 a2 &= 0xFFFFFFFF;
4286 a3 &= 0xFFFFFFFF;
4287 }
4288
07708c4a
JK		 4289 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4290 ret = -KVM_EPERM;
4291 goto out;
4292 }
4293
8776e519 4294 switch (nr) {
b93463aa
AK		 4295 case KVM_HC_VAPIC_POLL_IRQ:
4296 ret = 0;
4297 break;
2f333bcb
MT		 4298 case KVM_HC_MMU_OP:
4299 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4300 break;
8776e519
HB		 4301 default:
4302 ret = -KVM_ENOSYS;
4303 break;
4304 }
07708c4a 4305out:
5fdbf976 4306 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4307 ++vcpu->stat.hypercalls;
2f333bcb 4308 return r;
8776e519
HB		 4309}
4310EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4311
4312int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4313{
4314 char instruction[3];
5fdbf976 4315 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4316
8776e519
HB		 4317 /*
4318 * Blow out the MMU to ensure that no other VCPU has an active mapping
4319 * to ensure that the updated hypercall appears atomically across all
4320 * VCPUs.
4321 */
4322 kvm_mmu_zap_all(vcpu->kvm);
4323
8776e519 4324 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4325
8fe681e9 4326 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4327}
4328
8776e519
HB		 4329void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4330{
89a27f4d 4331 struct desc_ptr dt = { limit, base };
8776e519
HB		 4332
4333 kvm_x86_ops->set_gdt(vcpu, &dt);
4334}
4335
4336void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4337{
89a27f4d 4338 struct desc_ptr dt = { limit, base };
8776e519
HB		 4339
4340 kvm_x86_ops->set_idt(vcpu, &dt);
4341}
4342
07716717
DK		 4343static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4344{
ad312c7c
ZX		 4345 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4346 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4347
4348 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4349 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4350 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4351 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4352 if (ej->function == e->function) {
4353 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4354 return j;
4355 }
4356 }
4357 return 0; /* silence gcc, even though control never reaches here */
4358}
4359
4360/* find an entry with matching function, matching index (if needed), and that
4361 * should be read next (if it's stateful) */
4362static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4363 u32 function, u32 index)
4364{
4365 if (e->function != function)
4366 return 0;
4367 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4368 return 0;
4369 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4370 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4371 return 0;
4372 return 1;
4373}
4374
d8017474
AG		 4375struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4376 u32 function, u32 index)
8776e519
HB		 4377{
4378 int i;
d8017474 4379 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4380
ad312c7c 4381 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4382 struct kvm_cpuid_entry2 *e;
4383
ad312c7c 4384 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4385 if (is_matching_cpuid_entry(e, function, index)) {
4386 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4387 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4388 best = e;
4389 break;
4390 }
4391 /*
4392 * Both basic or both extended?
4393 */
4394 if (((e->function ^ function) & 0x80000000) == 0)
4395 if (!best || e->function > best->function)
4396 best = e;
4397 }
d8017474
AG		 4398 return best;
4399}
0e851880 4400EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4401
82725b20
DE		 4402int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4403{
4404 struct kvm_cpuid_entry2 *best;
4405
f7a71197
AK		 4406 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4407 if (!best || best->eax < 0x80000008)
4408 goto not_found;
82725b20
DE		 4409 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4410 if (best)
4411 return best->eax & 0xff;
f7a71197 4412not_found:
82725b20
DE		 4413 return 36;
4414}
4415
d8017474
AG		 4416void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4417{
4418 u32 function, index;
4419 struct kvm_cpuid_entry2 *best;
4420
4421 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4422 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4423 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4424 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4425 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4426 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4427 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4428 if (best) {
5fdbf976
MT		 4429 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4430 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4431 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4432 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4433 }
8776e519 4434 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4435 trace_kvm_cpuid(function,
4436 kvm_register_read(vcpu, VCPU_REGS_RAX),
4437 kvm_register_read(vcpu, VCPU_REGS_RBX),
4438 kvm_register_read(vcpu, VCPU_REGS_RCX),
4439 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4440}
4441EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4442
b6c7a5dc
HB		 4443/*
4444 * Check if userspace requested an interrupt window, and that the
4445 * interrupt window is open.
4446 *
4447 * No need to exit to userspace if we already have an interrupt queued.
4448 */
851ba692 4449static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4450{
8061823a 4451 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4452 vcpu->run->request_interrupt_window &&
5df56646 4453 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4454}
4455
851ba692 4456static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4457{
851ba692
AK		 4458 struct kvm_run *kvm_run = vcpu->run;
4459
91586a3b 4460 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4461 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4462 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4463 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4464 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4465 else
b6c7a5dc 4466 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4467 kvm_arch_interrupt_allowed(vcpu) &&
4468 !kvm_cpu_has_interrupt(vcpu) &&
4469 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4470}
4471
b93463aa
AK		 4472static void vapic_enter(struct kvm_vcpu *vcpu)
4473{
4474 struct kvm_lapic *apic = vcpu->arch.apic;
4475 struct page *page;
4476
4477 if (!apic || !apic->vapic_addr)
4478 return;
4479
4480 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4481
4482 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4483}
4484
4485static void vapic_exit(struct kvm_vcpu *vcpu)
4486{
4487 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4488 int idx;
b93463aa
AK		 4489
4490 if (!apic || !apic->vapic_addr)
4491 return;
4492
f656ce01 4493 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4494 kvm_release_page_dirty(apic->vapic_page);
4495 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4496 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4497}
4498
95ba8273
GN		 4499static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4500{
4501 int max_irr, tpr;
4502
4503 if (!kvm_x86_ops->update_cr8_intercept)
4504 return;
4505
88c808fd
AK		 4506 if (!vcpu->arch.apic)
4507 return;
4508
8db3baa2
GN		 4509 if (!vcpu->arch.apic->vapic_addr)
4510 max_irr = kvm_lapic_find_highest_irr(vcpu);
4511 else
4512 max_irr = -1;
95ba8273
GN		 4513
4514 if (max_irr != -1)
4515 max_irr >>= 4;
4516
4517 tpr = kvm_lapic_get_cr8(vcpu);
4518
4519 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4520}
4521
851ba692 4522static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4523{
4524 /* try to reinject previous events if any */
b59bb7bd 4525 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4526 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4527 vcpu->arch.exception.has_error_code,
4528 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4529 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4530 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4531 vcpu->arch.exception.error_code,
4532 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4533 return;
4534 }
4535
95ba8273
GN		 4536 if (vcpu->arch.nmi_injected) {
4537 kvm_x86_ops->set_nmi(vcpu);
4538 return;
4539 }
4540
4541 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4542 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4543 return;
4544 }
4545
4546 /* try to inject new event if pending */
4547 if (vcpu->arch.nmi_pending) {
4548 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4549 vcpu->arch.nmi_pending = false;
4550 vcpu->arch.nmi_injected = true;
4551 kvm_x86_ops->set_nmi(vcpu);
4552 }
4553 } else if (kvm_cpu_has_interrupt(vcpu)) {
4554 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4555 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4556 false);
4557 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4558 }
4559 }
4560}
4561
851ba692 4562static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4563{
4564 int r;
6a8b1d13 4565 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4566 vcpu->run->request_interrupt_window;
b6c7a5dc 4567
2e53d63a
MT		 4568 if (vcpu->requests)
4569 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4570 kvm_mmu_unload(vcpu);
4571
b6c7a5dc
HB		 4572 r = kvm_mmu_reload(vcpu);
4573 if (unlikely(r))
4574 goto out;
4575
2f52d58c
AK		 4576 if (vcpu->requests) {
4577 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4578 __kvm_migrate_timers(vcpu);
c8076604
GH		 4579 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4580 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4581 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4582 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4583 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4584 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4585 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4586 &vcpu->requests)) {
851ba692 4587 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4588 r = 0;
4589 goto out;
4590 }
71c4dfaf 4591 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4592 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4593 r = 0;
4594 goto out;
4595 }
02daab21
AK		 4596 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4597 vcpu->fpu_active = 0;
4598 kvm_x86_ops->fpu_deactivate(vcpu);
4599 }
2f52d58c 4600 }
b93463aa 4601
b6c7a5dc
HB		 4602 preempt_disable();
4603
4604 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4605 if (vcpu->fpu_active)
4606 kvm_load_guest_fpu(vcpu);
b6c7a5dc 4607
d94e1dc9
AK		 4608 atomic_set(&vcpu->guest_mode, 1);
4609 smp_wmb();
b6c7a5dc 4610
d94e1dc9 4611 local_irq_disable();
32f88400 4612
d94e1dc9
AK		 4613 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4614 || need_resched() || signal_pending(current)) {
4615 atomic_set(&vcpu->guest_mode, 0);
4616 smp_wmb();
6c142801
AK		 4617 local_irq_enable();
4618 preempt_enable();
4619 r = 1;
4620 goto out;
4621 }
4622
851ba692 4623 inject_pending_event(vcpu);
b6c7a5dc 4624
6a8b1d13
GN		 4625 /* enable NMI/IRQ window open exits if needed */
4626 if (vcpu->arch.nmi_pending)
4627 kvm_x86_ops->enable_nmi_window(vcpu);
4628 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4629 kvm_x86_ops->enable_irq_window(vcpu);
4630
95ba8273 4631 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4632 update_cr8_intercept(vcpu);
4633 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4634 }
b93463aa 4635
f656ce01 4636 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4637
b6c7a5dc
HB		 4638 kvm_guest_enter();
4639
42dbaa5a 4640 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4641 set_debugreg(0, 7);
4642 set_debugreg(vcpu->arch.eff_db[0], 0);
4643 set_debugreg(vcpu->arch.eff_db[1], 1);
4644 set_debugreg(vcpu->arch.eff_db[2], 2);
4645 set_debugreg(vcpu->arch.eff_db[3], 3);
4646 }
b6c7a5dc 4647
229456fc 4648 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4649 kvm_x86_ops->run(vcpu);
b6c7a5dc 4650
24f1e32c
FW		 4651 /*
4652 * If the guest has used debug registers, at least dr7
4653 * will be disabled while returning to the host.
4654 * If we don't have active breakpoints in the host, we don't
4655 * care about the messed up debug address registers. But if
4656 * we have some of them active, restore the old state.
4657 */
59d8eb53 4658 if (hw_breakpoint_active())
24f1e32c 4659 hw_breakpoint_restore();
42dbaa5a 4660
d94e1dc9
AK		 4661 atomic_set(&vcpu->guest_mode, 0);
4662 smp_wmb();
b6c7a5dc
HB		 4663 local_irq_enable();
4664
4665 ++vcpu->stat.exits;
4666
4667 /*
4668 * We must have an instruction between local_irq_enable() and
4669 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4670 * the interrupt shadow. The stat.exits increment will do nicely.
4671 * But we need to prevent reordering, hence this barrier():
4672 */
4673 barrier();
4674
4675 kvm_guest_exit();
4676
4677 preempt_enable();
4678
f656ce01 4679 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4680
b6c7a5dc
HB		 4681 /*
4682 * Profile KVM exit RIPs:
4683 */
4684 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4685 unsigned long rip = kvm_rip_read(vcpu);
4686 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4687 }
4688
298101da 4689
b93463aa
AK		 4690 kvm_lapic_sync_from_vapic(vcpu);
4691
851ba692 4692 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4693out:
4694 return r;
4695}
b6c7a5dc 4696
09cec754 4697
851ba692 4698static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4699{
4700 int r;
f656ce01 4701 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4702
4703 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4704 pr_debug("vcpu %d received sipi with vector # %x\n",
4705 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4706 kvm_lapic_reset(vcpu);
5f179287 4707 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4708 if (r)
4709 return r;
4710 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4711 }
4712
f656ce01 4713 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4714 vapic_enter(vcpu);
4715
4716 r = 1;
4717 while (r > 0) {
af2152f5 4718 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4719 r = vcpu_enter_guest(vcpu);
d7690175 4720 else {
f656ce01 4721 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4722 kvm_vcpu_block(vcpu);
f656ce01 4723 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4724 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4725 {
4726 switch(vcpu->arch.mp_state) {
4727 case KVM_MP_STATE_HALTED:
d7690175 4728 vcpu->arch.mp_state =
09cec754
GN		 4729 KVM_MP_STATE_RUNNABLE;
4730 case KVM_MP_STATE_RUNNABLE:
4731 break;
4732 case KVM_MP_STATE_SIPI_RECEIVED:
4733 default:
4734 r = -EINTR;
4735 break;
4736 }
4737 }
d7690175
MT		 4738 }
4739
09cec754
GN		 4740 if (r <= 0)
4741 break;
4742
4743 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4744 if (kvm_cpu_has_pending_timer(vcpu))
4745 kvm_inject_pending_timer_irqs(vcpu);
4746
851ba692 4747 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4748 r = -EINTR;
851ba692 4749 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4750 ++vcpu->stat.request_irq_exits;
4751 }
4752 if (signal_pending(current)) {
4753 r = -EINTR;
851ba692 4754 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4755 ++vcpu->stat.signal_exits;
4756 }
4757 if (need_resched()) {
f656ce01 4758 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4759 kvm_resched(vcpu);
f656ce01 4760 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4761 }
b6c7a5dc
HB		 4762 }
4763
f656ce01 4764 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4765
b93463aa
AK		 4766 vapic_exit(vcpu);
4767
b6c7a5dc
HB		 4768 return r;
4769}
4770
4771int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4772{
4773 int r;
4774 sigset_t sigsaved;
4775
4776 vcpu_load(vcpu);
4777
ac9f6dc0
AK		 4778 if (vcpu->sigset_active)
4779 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4780
a4535290 4781 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4782 kvm_vcpu_block(vcpu);
d7690175 4783 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4784 r = -EAGAIN;
4785 goto out;
b6c7a5dc
HB		 4786 }
4787
b6c7a5dc
HB		 4788 /* re-sync apic's tpr */
4789 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4790 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4791
92bf9748
GN		 4792 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4793 vcpu->arch.emulate_ctxt.restart) {
4794 if (vcpu->mmio_needed) {
4795 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4796 vcpu->mmio_read_completed = 1;
4797 vcpu->mmio_needed = 0;
b6c7a5dc 4798 }
f656ce01 4799 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4800 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4801 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4802 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4803 r = 0;
4804 goto out;
4805 }
4806 }
5fdbf976
MT		 4807 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4808 kvm_register_write(vcpu, VCPU_REGS_RAX,
4809 kvm_run->hypercall.ret);
b6c7a5dc 4810
851ba692 4811 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4812
4813out:
f1d86e46 4814 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4815 if (vcpu->sigset_active)
4816 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4817
4818 vcpu_put(vcpu);
4819 return r;
4820}
4821
4822int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4823{
4824 vcpu_load(vcpu);
4825
5fdbf976
MT		 4826 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4827 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4828 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4829 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4830 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4831 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4832 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4833 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4834#ifdef CONFIG_X86_64
5fdbf976
MT		 4835 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4836 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4837 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4838 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4839 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4840 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4841 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4842 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4843#endif
4844
5fdbf976 4845 regs->rip = kvm_rip_read(vcpu);
91586a3b 4846 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4847
4848 vcpu_put(vcpu);
4849
4850 return 0;
4851}
4852
4853int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4854{
4855 vcpu_load(vcpu);
4856
5fdbf976
MT		 4857 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4858 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4859 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4860 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4861 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4862 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4863 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4864 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4865#ifdef CONFIG_X86_64
5fdbf976
MT		 4866 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4867 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4868 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4869 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4870 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4871 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4872 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4873 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4874#endif
4875
5fdbf976 4876 kvm_rip_write(vcpu, regs->rip);
91586a3b 4877 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4878
b4f14abd
JK		 4879 vcpu->arch.exception.pending = false;
4880
b6c7a5dc
HB		 4881 vcpu_put(vcpu);
4882
4883 return 0;
4884}
4885
b6c7a5dc
HB		 4886void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4887{
4888 struct kvm_segment cs;
4889
3e6e0aab 4890 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4891 *db = cs.db;
4892 *l = cs.l;
4893}
4894EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4895
4896int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4897 struct kvm_sregs *sregs)
4898{
89a27f4d 4899 struct desc_ptr dt;
b6c7a5dc
HB		 4900
4901 vcpu_load(vcpu);
4902
3e6e0aab
GT		 4903 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4904 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4905 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4906 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4907 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4908 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4909
3e6e0aab
GT		 4910 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4911 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4912
4913 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4914 sregs->idt.limit = dt.size;
4915 sregs->idt.base = dt.address;
b6c7a5dc 4916 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4917 sregs->gdt.limit = dt.size;
4918 sregs->gdt.base = dt.address;
b6c7a5dc 4919
4d4ec087 4920 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4921 sregs->cr2 = vcpu->arch.cr2;
4922 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4923 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4924 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4925 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4926 sregs->apic_base = kvm_get_apic_base(vcpu);
4927
923c61bb 4928 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4929
36752c9b 4930 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4931 set_bit(vcpu->arch.interrupt.nr,
4932 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4933
b6c7a5dc
HB		 4934 vcpu_put(vcpu);
4935
4936 return 0;
4937}
4938
62d9f0db
MT		 4939int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4940 struct kvm_mp_state *mp_state)
4941{
4942 vcpu_load(vcpu);
4943 mp_state->mp_state = vcpu->arch.mp_state;
4944 vcpu_put(vcpu);
4945 return 0;
4946}
4947
4948int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4949 struct kvm_mp_state *mp_state)
4950{
4951 vcpu_load(vcpu);
4952 vcpu->arch.mp_state = mp_state->mp_state;
4953 vcpu_put(vcpu);
4954 return 0;
4955}
4956
e269fb21
JK		 4957int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4958 bool has_error_code, u32 error_code)
b6c7a5dc 4959{
4d2179e1 4960 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 4961 int cs_db, cs_l, ret;
4962 cache_all_regs(vcpu);
37817f29 4963
ceffb459 4964 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 4965
ceffb459
GN		 4966 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4967 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4968 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4969 vcpu->arch.emulate_ctxt.mode =
4970 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4971 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4972 ? X86EMUL_MODE_VM86 : cs_l
4973 ? X86EMUL_MODE_PROT64 : cs_db
4974 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 4975 memset(c, 0, sizeof(struct decode_cache));
4976 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 4977
ceffb459 4978 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4979 tss_selector, reason, has_error_code,
4980 error_code);
c697518a 4981
c697518a 4982 if (ret)
19d04437 4983 return EMULATE_FAIL;
37817f29 4984
4d2179e1 4985 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4986 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 4987 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4988 return EMULATE_DONE;
37817f29
IE		 4989}
4990EXPORT_SYMBOL_GPL(kvm_task_switch);
4991
b6c7a5dc
HB		 4992int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4993 struct kvm_sregs *sregs)
4994{
4995 int mmu_reset_needed = 0;
923c61bb 4996 int pending_vec, max_bits;
89a27f4d 4997 struct desc_ptr dt;
b6c7a5dc
HB		 4998
4999 vcpu_load(vcpu);
5000
89a27f4d
GN		 5001 dt.size = sregs->idt.limit;
5002 dt.address = sregs->idt.base;
b6c7a5dc 5003 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5004 dt.size = sregs->gdt.limit;
5005 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5006 kvm_x86_ops->set_gdt(vcpu, &dt);
5007
ad312c7c
ZX		 5008 vcpu->arch.cr2 = sregs->cr2;
5009 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5010 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5011
2d3ad1f4 5012 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5013
f6801dff 5014 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5015 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5016 kvm_set_apic_base(vcpu, sregs->apic_base);
5017
4d4ec087 5018 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5019 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5020 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5021
fc78f519 5022 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5023 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5024 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5025 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5026 mmu_reset_needed = 1;
5027 }
b6c7a5dc
HB		 5028
5029 if (mmu_reset_needed)
5030 kvm_mmu_reset_context(vcpu);
5031
923c61bb
GN		 5032 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5033 pending_vec = find_first_bit(
5034 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5035 if (pending_vec < max_bits) {
66fd3f7f 5036 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5037 pr_debug("Set back pending irq %d\n", pending_vec);
5038 if (irqchip_in_kernel(vcpu->kvm))
5039 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5040 }
5041
3e6e0aab
GT		 5042 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5043 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5044 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5045 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5046 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5047 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5048
3e6e0aab
GT		 5049 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5050 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5051
5f0269f5
ME		 5052 update_cr8_intercept(vcpu);
5053
9c3e4aab 5054 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5055 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5056 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5057 !is_protmode(vcpu))
9c3e4aab
MT		 5058 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5059
b6c7a5dc
HB		 5060 vcpu_put(vcpu);
5061
5062 return 0;
5063}
5064
d0bfb940
JK		 5065int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5066 struct kvm_guest_debug *dbg)
b6c7a5dc 5067{
355be0b9 5068 unsigned long rflags;
ae675ef0 5069 int i, r;
b6c7a5dc
HB		 5070
5071 vcpu_load(vcpu);
5072
4f926bf2
JK		 5073 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5074 r = -EBUSY;
5075 if (vcpu->arch.exception.pending)
5076 goto unlock_out;
5077 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5078 kvm_queue_exception(vcpu, DB_VECTOR);
5079 else
5080 kvm_queue_exception(vcpu, BP_VECTOR);
5081 }
5082
91586a3b
JK		 5083 /*
5084 * Read rflags as long as potentially injected trace flags are still
5085 * filtered out.
5086 */
5087 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5088
5089 vcpu->guest_debug = dbg->control;
5090 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5091 vcpu->guest_debug = 0;
5092
5093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5094 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5095 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5096 vcpu->arch.switch_db_regs =
5097 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5098 } else {
5099 for (i = 0; i < KVM_NR_DB_REGS; i++)
5100 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5101 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5102 }
5103
f92653ee
JK		 5104 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5105 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5106 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5107
91586a3b
JK		 5108 /*
5109 * Trigger an rflags update that will inject or remove the trace
5110 * flags.
5111 */
5112 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5113
355be0b9 5114 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5115
4f926bf2 5116 r = 0;
d0bfb940 5117
4f926bf2 5118unlock_out:
b6c7a5dc
HB		 5119 vcpu_put(vcpu);
5120
5121 return r;
5122}
5123
d0752060
HB		 5124/*
5125 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5126 * we have asm/x86/processor.h
5127 */
5128struct fxsave {
5129 u16 cwd;
5130 u16 swd;
5131 u16 twd;
5132 u16 fop;
5133 u64 rip;
5134 u64 rdp;
5135 u32 mxcsr;
5136 u32 mxcsr_mask;
5137 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5138#ifdef CONFIG_X86_64
5139 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5140#else
5141 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5142#endif
5143};
5144
8b006791
ZX		 5145/*
5146 * Translate a guest virtual address to a guest physical address.
5147 */
5148int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5149 struct kvm_translation *tr)
5150{
5151 unsigned long vaddr = tr->linear_address;
5152 gpa_t gpa;
f656ce01 5153 int idx;
8b006791
ZX		 5154
5155 vcpu_load(vcpu);
f656ce01 5156 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5157 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5158 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5159 tr->physical_address = gpa;
5160 tr->valid = gpa != UNMAPPED_GVA;
5161 tr->writeable = 1;
5162 tr->usermode = 0;
8b006791
ZX		 5163 vcpu_put(vcpu);
5164
5165 return 0;
5166}
5167
d0752060
HB		 5168int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5169{
ad312c7c 5170 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5171
5172 vcpu_load(vcpu);
5173
5174 memcpy(fpu->fpr, fxsave->st_space, 128);
5175 fpu->fcw = fxsave->cwd;
5176 fpu->fsw = fxsave->swd;
5177 fpu->ftwx = fxsave->twd;
5178 fpu->last_opcode = fxsave->fop;
5179 fpu->last_ip = fxsave->rip;
5180 fpu->last_dp = fxsave->rdp;
5181 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5182
5183 vcpu_put(vcpu);
5184
5185 return 0;
5186}
5187
5188int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5189{
ad312c7c 5190 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5191
5192 vcpu_load(vcpu);
5193
5194 memcpy(fxsave->st_space, fpu->fpr, 128);
5195 fxsave->cwd = fpu->fcw;
5196 fxsave->swd = fpu->fsw;
5197 fxsave->twd = fpu->ftwx;
5198 fxsave->fop = fpu->last_opcode;
5199 fxsave->rip = fpu->last_ip;
5200 fxsave->rdp = fpu->last_dp;
5201 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5202
5203 vcpu_put(vcpu);
5204
5205 return 0;
5206}
5207
5208void fx_init(struct kvm_vcpu *vcpu)
5209{
5210 unsigned after_mxcsr_mask;
5211
bc1a34f1
AA		 5212 /*
5213 * Touch the fpu the first time in non atomic context as if
5214 * this is the first fpu instruction the exception handler
5215 * will fire before the instruction returns and it'll have to
5216 * allocate ram with GFP_KERNEL.
5217 */
5218 if (!used_math())
d6e88aec 5219 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5220
d0752060
HB		 5221 /* Initialize guest FPU by resetting ours and saving into guest's */
5222 preempt_disable();
d6e88aec
AK		 5223 kvm_fx_save(&vcpu->arch.host_fx_image);
5224 kvm_fx_finit();
5225 kvm_fx_save(&vcpu->arch.guest_fx_image);
5226 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5227 preempt_enable();
5228
ad312c7c 5229 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5230 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5231 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5232 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5233 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5234}
5235EXPORT_SYMBOL_GPL(fx_init);
5236
5237void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5238{
2608d7a1 5239 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5240 return;
5241
5242 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5243 kvm_fx_save(&vcpu->arch.host_fx_image);
5244 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5245 trace_kvm_fpu(1);
d0752060 5246}
d0752060
HB		 5247
5248void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5249{
5250 if (!vcpu->guest_fpu_loaded)
5251 return;
5252
5253 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5254 kvm_fx_save(&vcpu->arch.guest_fx_image);
5255 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5256 ++vcpu->stat.fpu_reload;
02daab21 5257 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5258 trace_kvm_fpu(0);
d0752060 5259}
e9b11c17
ZX		 5260
5261void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5262{
7f1ea208
JR		 5263 if (vcpu->arch.time_page) {
5264 kvm_release_page_dirty(vcpu->arch.time_page);
5265 vcpu->arch.time_page = NULL;
5266 }
5267
e9b11c17
ZX		 5268 kvm_x86_ops->vcpu_free(vcpu);
5269}
5270
5271struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5272 unsigned int id)
5273{
26e5215f
AK		 5274 return kvm_x86_ops->vcpu_create(kvm, id);
5275}
e9b11c17 5276
26e5215f
AK		 5277int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5278{
5279 int r;
e9b11c17
ZX		 5280
5281 /* We do fxsave: this must be aligned. */
ad312c7c 5282 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5283
0bed3b56 5284 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5285 vcpu_load(vcpu);
5286 r = kvm_arch_vcpu_reset(vcpu);
5287 if (r == 0)
5288 r = kvm_mmu_setup(vcpu);
5289 vcpu_put(vcpu);
5290 if (r < 0)
5291 goto free_vcpu;
5292
26e5215f 5293 return 0;
e9b11c17
ZX		 5294free_vcpu:
5295 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5296 return r;
e9b11c17
ZX		 5297}
5298
d40ccc62 5299void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5300{
5301 vcpu_load(vcpu);
5302 kvm_mmu_unload(vcpu);
5303 vcpu_put(vcpu);
5304
5305 kvm_x86_ops->vcpu_free(vcpu);
5306}
5307
5308int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5309{
448fa4a9
JK		 5310 vcpu->arch.nmi_pending = false;
5311 vcpu->arch.nmi_injected = false;
5312
42dbaa5a
JK		 5313 vcpu->arch.switch_db_regs = 0;
5314 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5315 vcpu->arch.dr6 = DR6_FIXED_1;
5316 vcpu->arch.dr7 = DR7_FIXED_1;
5317
e9b11c17
ZX		 5318 return kvm_x86_ops->vcpu_reset(vcpu);
5319}
5320
10474ae8 5321int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5322{
0cca7907
ZA		 5323 /*
5324 * Since this may be called from a hotplug notifcation,
5325 * we can't get the CPU frequency directly.
5326 */
5327 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5328 int cpu = raw_smp_processor_id();
5329 per_cpu(cpu_tsc_khz, cpu) = 0;
5330 }
18863bdd
AK		 5331
5332 kvm_shared_msr_cpu_online();
5333
10474ae8 5334 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5335}
5336
5337void kvm_arch_hardware_disable(void *garbage)
5338{
5339 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5340 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5341}
5342
5343int kvm_arch_hardware_setup(void)
5344{
5345 return kvm_x86_ops->hardware_setup();
5346}
5347
5348void kvm_arch_hardware_unsetup(void)
5349{
5350 kvm_x86_ops->hardware_unsetup();
5351}
5352
5353void kvm_arch_check_processor_compat(void *rtn)
5354{
5355 kvm_x86_ops->check_processor_compatibility(rtn);
5356}
5357
5358int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5359{
5360 struct page *page;
5361 struct kvm *kvm;
5362 int r;
5363
5364 BUG_ON(vcpu->kvm == NULL);
5365 kvm = vcpu->kvm;
5366
ad312c7c 5367 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5368 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5369 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5370 else
a4535290 5371 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5372
5373 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5374 if (!page) {
5375 r = -ENOMEM;
5376 goto fail;
5377 }
ad312c7c 5378 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5379
5380 r = kvm_mmu_create(vcpu);
5381 if (r < 0)
5382 goto fail_free_pio_data;
5383
5384 if (irqchip_in_kernel(kvm)) {
5385 r = kvm_create_lapic(vcpu);
5386 if (r < 0)
5387 goto fail_mmu_destroy;
5388 }
5389
890ca9ae
HY		 5390 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5391 GFP_KERNEL);
5392 if (!vcpu->arch.mce_banks) {
5393 r = -ENOMEM;
443c39bc 5394 goto fail_free_lapic;
890ca9ae
HY		 5395 }
5396 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5397
e9b11c17 5398 return 0;
443c39bc
WY		 5399fail_free_lapic:
5400 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5401fail_mmu_destroy:
5402 kvm_mmu_destroy(vcpu);
5403fail_free_pio_data:
ad312c7c 5404 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5405fail:
5406 return r;
5407}
5408
5409void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5410{
f656ce01
MT		 5411 int idx;
5412
36cb93fd 5413 kfree(vcpu->arch.mce_banks);
e9b11c17 5414 kvm_free_lapic(vcpu);
f656ce01 5415 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5416 kvm_mmu_destroy(vcpu);
f656ce01 5417 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5418 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5419}
d19a9cd2
ZX		 5420
5421struct kvm *kvm_arch_create_vm(void)
5422{
5423 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5424
5425 if (!kvm)
5426 return ERR_PTR(-ENOMEM);
5427
fef9cce0
MT		 5428 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5429 if (!kvm->arch.aliases) {
5430 kfree(kvm);
5431 return ERR_PTR(-ENOMEM);
5432 }
5433
f05e70ac 5434 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5435 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5436
5550af4d
SY		 5437 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5438 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5439
53f658b3
MT		 5440 rdtscll(kvm->arch.vm_init_tsc);
5441
d19a9cd2
ZX		 5442 return kvm;
5443}
5444
5445static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5446{
5447 vcpu_load(vcpu);
5448 kvm_mmu_unload(vcpu);
5449 vcpu_put(vcpu);
5450}
5451
5452static void kvm_free_vcpus(struct kvm *kvm)
5453{
5454 unsigned int i;
988a2cae 5455 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5456
5457 /*
5458 * Unpin any mmu pages first.
5459 */
988a2cae
GN		 5460 kvm_for_each_vcpu(i, vcpu, kvm)
5461 kvm_unload_vcpu_mmu(vcpu);
5462 kvm_for_each_vcpu(i, vcpu, kvm)
5463 kvm_arch_vcpu_free(vcpu);
5464
5465 mutex_lock(&kvm->lock);
5466 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5467 kvm->vcpus[i] = NULL;
d19a9cd2 5468
988a2cae
GN		 5469 atomic_set(&kvm->online_vcpus, 0);
5470 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5471}
5472
ad8ba2cd
SY		 5473void kvm_arch_sync_events(struct kvm *kvm)
5474{
ba4cef31 5475 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5476}
5477
d19a9cd2
ZX		 5478void kvm_arch_destroy_vm(struct kvm *kvm)
5479{
6eb55818 5480 kvm_iommu_unmap_guest(kvm);
7837699f 5481 kvm_free_pit(kvm);
d7deeeb0
ZX		 5482 kfree(kvm->arch.vpic);
5483 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5484 kvm_free_vcpus(kvm);
5485 kvm_free_physmem(kvm);
3d45830c
AK		 5486 if (kvm->arch.apic_access_page)
5487 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5488 if (kvm->arch.ept_identity_pagetable)
5489 put_page(kvm->arch.ept_identity_pagetable);
64749204 5490 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5491 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5492 kfree(kvm);
5493}
0de10343 5494
f7784b8e
MT		 5495int kvm_arch_prepare_memory_region(struct kvm *kvm,
5496 struct kvm_memory_slot *memslot,
0de10343 5497 struct kvm_memory_slot old,
f7784b8e 5498 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5499 int user_alloc)
5500{
f7784b8e 5501 int npages = memslot->npages;
0de10343
ZX		 5502
5503 /*To keep backward compatibility with older userspace,
5504 *x86 needs to hanlde !user_alloc case.
5505 */
5506 if (!user_alloc) {
5507 if (npages && !old.rmap) {
604b38ac
AA		 5508 unsigned long userspace_addr;
5509
72dc67a6 5510 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5511 userspace_addr = do_mmap(NULL, 0,
5512 npages * PAGE_SIZE,
5513 PROT_READ | PROT_WRITE,
acee3c04 5514 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5515 0);
72dc67a6 5516 up_write(&current->mm->mmap_sem);
0de10343 5517
604b38ac
AA		 5518 if (IS_ERR((void *)userspace_addr))
5519 return PTR_ERR((void *)userspace_addr);
5520
604b38ac 5521 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5522 }
5523 }
5524
f7784b8e
MT		 5525
5526 return 0;
5527}
5528
5529void kvm_arch_commit_memory_region(struct kvm *kvm,
5530 struct kvm_userspace_memory_region *mem,
5531 struct kvm_memory_slot old,
5532 int user_alloc)
5533{
5534
5535 int npages = mem->memory_size >> PAGE_SHIFT;
5536
5537 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5538 int ret;
5539
5540 down_write(&current->mm->mmap_sem);
5541 ret = do_munmap(current->mm, old.userspace_addr,
5542 old.npages * PAGE_SIZE);
5543 up_write(&current->mm->mmap_sem);
5544 if (ret < 0)
5545 printk(KERN_WARNING
5546 "kvm_vm_ioctl_set_memory_region: "
5547 "failed to munmap memory\n");
5548 }
5549
7c8a83b7 5550 spin_lock(&kvm->mmu_lock);
f05e70ac 5551 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5552 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5553 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5554 }
5555
5556 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5557 spin_unlock(&kvm->mmu_lock);
0de10343 5558}
1d737c8a 5559
34d4cb8f
MT		 5560void kvm_arch_flush_shadow(struct kvm *kvm)
5561{
5562 kvm_mmu_zap_all(kvm);
8986ecc0 5563 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5564}
5565
1d737c8a
ZX		 5566int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5567{
a4535290 5568 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5569 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5570 || vcpu->arch.nmi_pending ||
5571 (kvm_arch_interrupt_allowed(vcpu) &&
5572 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5573}
5736199a 5574
5736199a
ZX		 5575void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5576{
32f88400
MT		 5577 int me;
5578 int cpu = vcpu->cpu;
5736199a
ZX		 5579
5580 if (waitqueue_active(&vcpu->wq)) {
5581 wake_up_interruptible(&vcpu->wq);
5582 ++vcpu->stat.halt_wakeup;
5583 }
32f88400
MT		 5584
5585 me = get_cpu();
5586 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5587 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5588 smp_send_reschedule(cpu);
e9571ed5 5589 put_cpu();
5736199a 5590}
78646121
GN		 5591
5592int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5593{
5594 return kvm_x86_ops->interrupt_allowed(vcpu);
5595}
229456fc 5596
f92653ee
JK		 5597bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5598{
5599 unsigned long current_rip = kvm_rip_read(vcpu) +
5600 get_segment_base(vcpu, VCPU_SREG_CS);
5601
5602 return current_rip == linear_rip;
5603}
5604EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5605
94fe45da
JK		 5606unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5607{
5608 unsigned long rflags;
5609
5610 rflags = kvm_x86_ops->get_rflags(vcpu);
5611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5612 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5613 return rflags;
5614}
5615EXPORT_SYMBOL_GPL(kvm_get_rflags);
5616
5617void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5618{
5619 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5620 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5621 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5622 kvm_x86_ops->set_rflags(vcpu, rflags);
5623}
5624EXPORT_SYMBOL_GPL(kvm_set_rflags);
5625
229456fc
MT		 5626EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5627EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5628EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5629EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5630EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5631EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5632EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5633EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5634EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5635EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5636EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5637EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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