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[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
d91cab78 676 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 677 return 1;
d91cab78 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
d91cab78 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
d91cab78
DH		 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 692 return 1;
693
d91cab78
DH		 694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 696 return 1;
d91cab78 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 698 return 1;
699 }
42bdf991 700 kvm_put_guest_xcr0(vcpu);
2acf923e 701 vcpu->arch.xcr0 = xcr0;
56c103ec 702
d91cab78 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 704 kvm_update_cpuid(vcpu);
2acf923e
DC		 705 return 0;
706}
707
708int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709{
764bcbc5
Z		 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 712 kvm_inject_gp(vcpu, 0);
713 return 1;
714 }
715 return 0;
716}
717EXPORT_SYMBOL_GPL(kvm_set_xcr);
718
a83b29c6 719int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 720{
fc78f519 721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
724
0f12244f
GN		 725 if (cr4 & CR4_RESERVED_BITS)
726 return 1;
a03490ed 727
2acf923e
DC		 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 return 1;
730
c68b734f
YW		 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 return 1;
733
97ec8c06
FW		 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 return 1;
736
afcbf13f 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 738 return 1;
739
a03490ed 740 if (is_long_mode(vcpu)) {
0f12244f
GN		 741 if (!(cr4 & X86_CR4_PAE))
742 return 1;
a2edf57f
AK		 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 kvm_read_cr3(vcpu)))
0f12244f
GN		 747 return 1;
748
ad756a16
MJ		 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
751 return 1;
752
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 return 1;
756 }
757
5e1746d6 758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 759 return 1;
a03490ed 760
ad756a16
MJ		 761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 763 kvm_mmu_reset_context(vcpu);
0f12244f 764
2acf923e 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 766 kvm_update_cpuid(vcpu);
2acf923e 767
0f12244f
GN		 768 return 0;
769}
2d3ad1f4 770EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 771
2390218b 772int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 773{
ac146235 774#ifdef CONFIG_X86_64
9d88fca7 775 cr3 &= ~CR3_PCID_INVD;
ac146235 776#endif
9d88fca7 777
9f8fe504 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 779 kvm_mmu_sync_roots(vcpu);
77c3913b 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 781 return 0;
d835dfec
AK		 782 }
783
a03490ed 784 if (is_long_mode(vcpu)) {
d9f89b88
JK		 785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 return 1;
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 789 return 1;
a03490ed 790
0f12244f 791 vcpu->arch.cr3 = cr3;
aff48baa 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 793 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 797
eea1cff9 798int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 799{
0f12244f
GN		 800 if (cr8 & CR8_RESERVED_BITS)
801 return 1;
35754c98 802 if (lapic_in_kernel(vcpu))
a03490ed
CO		 803 kvm_lapic_set_tpr(vcpu, cr8);
804 else
ad312c7c 805 vcpu->arch.cr8 = cr8;
0f12244f
GN		 806 return 0;
807}
2d3ad1f4 808EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 809
2d3ad1f4 810unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 811{
35754c98 812 if (lapic_in_kernel(vcpu))
a03490ed
CO		 813 return kvm_lapic_get_cr8(vcpu);
814 else
ad312c7c 815 return vcpu->arch.cr8;
a03490ed 816}
2d3ad1f4 817EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 818
ae561ede
NA		 819static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820{
821 int i;
822
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 }
828}
829
73aaf249
JK		 830static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831{
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834}
835
c8639010
JK		 836static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837{
838 unsigned long dr7;
839
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
842 else
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 848}
849
6f43ed01
NA		 850static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851{
852 u64 fixed = DR6_FIXED_1;
853
854 if (!guest_cpuid_has_rtm(vcpu))
855 fixed |= DR6_RTM;
856 return fixed;
857}
858
338dbc97 859static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 860{
861 switch (dr) {
862 case 0 ... 3:
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
866 break;
867 case 4:
020df079
GN		 868 /* fall through */
869 case 6:
338dbc97
GN		 870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
6f43ed01 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 873 kvm_update_dr6(vcpu);
020df079
GN		 874 break;
875 case 5:
020df079
GN		 876 /* fall through */
877 default: /* 7 */
338dbc97
GN		 878 if (val & 0xffffffff00000000ULL)
879 return -1; /* #GP */
020df079 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 881 kvm_update_dr7(vcpu);
020df079
GN		 882 break;
883 }
884
885 return 0;
886}
338dbc97
GN		 887
888int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889{
16f8a6f9 890 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 891 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 892 return 1;
893 }
894 return 0;
338dbc97 895}
020df079
GN		 896EXPORT_SYMBOL_GPL(kvm_set_dr);
897
16f8a6f9 898int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 899{
900 switch (dr) {
901 case 0 ... 3:
902 *val = vcpu->arch.db[dr];
903 break;
904 case 4:
020df079
GN		 905 /* fall through */
906 case 6:
73aaf249
JK		 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
909 else
910 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 911 break;
912 case 5:
020df079
GN		 913 /* fall through */
914 default: /* 7 */
915 *val = vcpu->arch.dr7;
916 break;
917 }
338dbc97
GN		 918 return 0;
919}
020df079
GN		 920EXPORT_SYMBOL_GPL(kvm_get_dr);
921
022cd0e8
AK		 922bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923{
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 u64 data;
926 int err;
927
c6702c9d 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 929 if (err)
930 return err;
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 return err;
934}
935EXPORT_SYMBOL_GPL(kvm_rdpmc);
936
043405e1
CO		 937/*
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940 *
941 * This list is modified at module load time to reflect the
e3267cbb 942 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
043405e1 945 */
e3267cbb 946
043405e1
CO		 947static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 949 MSR_STAR,
043405e1
CO		 950#ifdef CONFIG_X86_64
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952#endif
b3897a49 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 955};
956
957static unsigned num_msrs_to_save;
958
62ef68bb
PB		 959static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 966 HV_X64_MSR_RESET,
11c4b1ca 967 HV_X64_MSR_VP_INDEX,
9eec50b8 968 HV_X64_MSR_VP_RUNTIME,
5c919412 969 HV_X64_MSR_SCONTROL,
1f4b34f8 970 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 971 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
972 MSR_KVM_PV_EOI_EN,
973
ba904635 974 MSR_IA32_TSC_ADJUST,
a3e06bbe 975 MSR_IA32_TSCDEADLINE,
043405e1 976 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 977 MSR_IA32_MCG_STATUS,
978 MSR_IA32_MCG_CTL,
64d60670 979 MSR_IA32_SMBASE,
043405e1
CO		 980};
981
62ef68bb
PB		 982static unsigned num_emulated_msrs;
983
384bb783 984bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 985{
b69e8cae 986 if (efer & efer_reserved_bits)
384bb783 987 return false;
15c4a640 988
1b2fd70c
AG		 989 if (efer & EFER_FFXSR) {
990 struct kvm_cpuid_entry2 *feat;
991
992 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 993 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 994 return false;
1b2fd70c
AG		 995 }
996
d8017474
AG		 997 if (efer & EFER_SVME) {
998 struct kvm_cpuid_entry2 *feat;
999
1000 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1001 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1002 return false;
d8017474
AG		 1003 }
1004
384bb783
JK		 1005 return true;
1006}
1007EXPORT_SYMBOL_GPL(kvm_valid_efer);
1008
1009static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1010{
1011 u64 old_efer = vcpu->arch.efer;
1012
1013 if (!kvm_valid_efer(vcpu, efer))
1014 return 1;
1015
1016 if (is_paging(vcpu)
1017 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1018 return 1;
1019
15c4a640 1020 efer &= ~EFER_LMA;
f6801dff 1021 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1022
a3d204e2
SY		 1023 kvm_x86_ops->set_efer(vcpu, efer);
1024
aad82703
SY		 1025 /* Update reserved bits */
1026 if ((efer ^ old_efer) & EFER_NX)
1027 kvm_mmu_reset_context(vcpu);
1028
b69e8cae 1029 return 0;
15c4a640
CO		 1030}
1031
f2b4b7dd
JR		 1032void kvm_enable_efer_bits(u64 mask)
1033{
1034 efer_reserved_bits &= ~mask;
1035}
1036EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1037
15c4a640
CO		 1038/*
1039 * Writes msr value into into the appropriate "register".
1040 * Returns 0 on success, non-0 otherwise.
1041 * Assumes vcpu_load() was already called.
1042 */
8fe8ab46 1043int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1044{
854e8bb1
NA		 1045 switch (msr->index) {
1046 case MSR_FS_BASE:
1047 case MSR_GS_BASE:
1048 case MSR_KERNEL_GS_BASE:
1049 case MSR_CSTAR:
1050 case MSR_LSTAR:
1051 if (is_noncanonical_address(msr->data))
1052 return 1;
1053 break;
1054 case MSR_IA32_SYSENTER_EIP:
1055 case MSR_IA32_SYSENTER_ESP:
1056 /*
1057 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1058 * non-canonical address is written on Intel but not on
1059 * AMD (which ignores the top 32-bits, because it does
1060 * not implement 64-bit SYSENTER).
1061 *
1062 * 64-bit code should hence be able to write a non-canonical
1063 * value on AMD. Making the address canonical ensures that
1064 * vmentry does not fail on Intel after writing a non-canonical
1065 * value, and that something deterministic happens if the guest
1066 * invokes 64-bit SYSENTER.
1067 */
1068 msr->data = get_canonical(msr->data);
1069 }
8fe8ab46 1070 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1071}
854e8bb1 1072EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1073
313a3dc7
CO		 1074/*
1075 * Adapt set_msr() to msr_io()'s calling convention
1076 */
609e36d3
PB		 1077static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1078{
1079 struct msr_data msr;
1080 int r;
1081
1082 msr.index = index;
1083 msr.host_initiated = true;
1084 r = kvm_get_msr(vcpu, &msr);
1085 if (r)
1086 return r;
1087
1088 *data = msr.data;
1089 return 0;
1090}
1091
313a3dc7
CO		 1092static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1093{
8fe8ab46
WA		 1094 struct msr_data msr;
1095
1096 msr.data = *data;
1097 msr.index = index;
1098 msr.host_initiated = true;
1099 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1100}
1101
16e8d74d
MT		 1102#ifdef CONFIG_X86_64
1103struct pvclock_gtod_data {
1104 seqcount_t seq;
1105
1106 struct { /* extract of a clocksource struct */
1107 int vclock_mode;
1108 cycle_t cycle_last;
1109 cycle_t mask;
1110 u32 mult;
1111 u32 shift;
1112 } clock;
1113
cbcf2dd3
TG		 1114 u64 boot_ns;
1115 u64 nsec_base;
16e8d74d
MT		 1116};
1117
1118static struct pvclock_gtod_data pvclock_gtod_data;
1119
1120static void update_pvclock_gtod(struct timekeeper *tk)
1121{
1122 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1123 u64 boot_ns;
1124
876e7881 1125 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1126
1127 write_seqcount_begin(&vdata->seq);
1128
1129 /* copy pvclock gtod data */
876e7881
PZ		 1130 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1131 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1132 vdata->clock.mask = tk->tkr_mono.mask;
1133 vdata->clock.mult = tk->tkr_mono.mult;
1134 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1135
cbcf2dd3 1136 vdata->boot_ns = boot_ns;
876e7881 1137 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1138
1139 write_seqcount_end(&vdata->seq);
1140}
1141#endif
1142
bab5bb39
NK		 1143void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1144{
1145 /*
1146 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1147 * vcpu_enter_guest. This function is only called from
1148 * the physical CPU that is running vcpu.
1149 */
1150 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1151}
16e8d74d 1152
18068523
GOC		 1153static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1154{
9ed3c444
AK		 1155 int version;
1156 int r;
50d0a0f9 1157 struct pvclock_wall_clock wc;
923de3cf 1158 struct timespec boot;
18068523
GOC		 1159
1160 if (!wall_clock)
1161 return;
1162
9ed3c444
AK		 1163 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1164 if (r)
1165 return;
1166
1167 if (version & 1)
1168 ++version; /* first time write, random junk */
1169
1170 ++version;
18068523 1171
1dab1345
NK		 1172 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1173 return;
18068523 1174
50d0a0f9
GH		 1175 /*
1176 * The guest calculates current wall clock time by adding
34c238a1 1177 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1178 * wall clock specified here. guest system time equals host
1179 * system time for us, thus we must fill in host boot time here.
1180 */
923de3cf 1181 getboottime(&boot);
50d0a0f9 1182
4b648665
BR		 1183 if (kvm->arch.kvmclock_offset) {
1184 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1185 boot = timespec_sub(boot, ts);
1186 }
50d0a0f9
GH		 1187 wc.sec = boot.tv_sec;
1188 wc.nsec = boot.tv_nsec;
1189 wc.version = version;
18068523
GOC		 1190
1191 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1192
1193 version++;
1194 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1195}
1196
50d0a0f9
GH		 1197static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1198{
1199 uint32_t quotient, remainder;
1200
1201 /* Don't try to replace with do_div(), this one calculates
1202 * "(dividend << 32) / divisor" */
1203 __asm__ ( "divl %4"
1204 : "=a" (quotient), "=d" (remainder)
1205 : "0" (0), "1" (dividend), "r" (divisor) );
1206 return quotient;
1207}
1208
5f4e3f88
ZA		 1209static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1210 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1211{
5f4e3f88 1212 uint64_t scaled64;
50d0a0f9
GH		 1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
5f4e3f88
ZA		 1217 tps64 = base_khz * 1000LL;
1218 scaled64 = scaled_khz * 1000LL;
50933623 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
50933623
JK		 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
50d0a0f9
GH		 1230 shift++;
1231 }
1232
5f4e3f88
ZA		 1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1235
5f4e3f88
ZA		 1236 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1237 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1238}
1239
d828199e 1240#ifdef CONFIG_X86_64
16e8d74d 1241static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1242#endif
16e8d74d 1243
c8076604 1244static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1245static unsigned long max_tsc_khz;
c8076604 1246
cc578287 1247static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1248{
cc578287
ZA		 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1251}
1252
cc578287 1253static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1254{
cc578287
ZA		 1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1e993611
JR		 1258}
1259
381d585c
HZ		 1260static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261{
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294}
1295
1296static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1297{
cc578287
ZA		 1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
217fc9cf 1300
03ba32ca 1301 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1302 if (this_tsc_khz == 0) {
1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1305 return -1;
ad721883 1306 }
03ba32ca 1307
c285545f
ZA		 1308 /* Compute a scale to convert nanoseconds in TSC cycles */
1309 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
1312 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1322 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1324 use_scaling = 1;
1325 }
381d585c 1326 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1327}
1328
1329static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330{
e26101b1 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
e26101b1 1334 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1335 return tsc;
1336}
1337
69b0049a 1338static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1339{
1340#ifdef CONFIG_X86_64
1341 bool vcpus_matched;
b48aa97e
MT		 1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
7f187922
MT		 1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363#endif
1364}
1365
ba904635
WA		 1366static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367{
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370}
1371
35181e86
HZ		 1372/*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383{
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385}
1386
1387u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388{
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396}
1397EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
07c1419a
HZ		 1399static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400{
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406}
1407
4ba76538
HZ		 1408u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409{
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411}
1412EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
8fe8ab46 1414void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1415{
1416 struct kvm *kvm = vcpu->kvm;
f38e098f 1417 u64 offset, ns, elapsed;
99e3e30a 1418 unsigned long flags;
02626b6a 1419 s64 usdiff;
b48aa97e 1420 bool matched;
0d3da0d2 1421 bool already_matched;
8fe8ab46 1422 u64 data = msr->data;
99e3e30a 1423
038f8c11 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1425 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1426 ns = get_kernel_ns();
f38e098f 1427 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1428
03ba32ca 1429 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1430 int faulted = 0;
1431
03ba32ca
MT		 1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1434#ifdef CONFIG_X86_64
03ba32ca 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1436#else
03ba32ca 1437 /* do_div() only does unsigned */
8915aa27
MT		 1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
5d3cb0f6 1452#endif
03ba32ca
MT		 1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
8915aa27
MT		 1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1463
1464 /*
5d3cb0f6
ZA		 1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
02626b6a 1474 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1476 if (!check_tsc_unstable()) {
e26101b1 1477 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
857e4099 1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1481 data += delta;
07c1419a 1482 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1484 }
b48aa97e 1485 matched = true;
0d3da0d2 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
4a969980 1493 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1501 matched = false;
0d3da0d2 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1503 kvm->arch.cur_tsc_generation, data);
f38e098f 1504 }
e26101b1
ZA		 1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
f38e098f
ZA		 1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
5d3cb0f6 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1513
b183aa58 1514 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
ba904635
WA		 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1527 if (!matched) {
b48aa97e 1528 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
b48aa97e
MT		 1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1535}
e26101b1 1536
99e3e30a
ZA		 1537EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
58ea6767
HZ		 1539static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541{
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543}
1544
1545static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546{
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
d828199e
MT		 1553#ifdef CONFIG_X86_64
1554
1555static cycle_t read_tsc(void)
1556{
03b9730b
AL		 1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a funciton of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573}
1574
1575static inline u64 vgettsc(cycle_t *cycle_now)
1576{
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584}
1585
cbcf2dd3 1586static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1587{
cbcf2dd3 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1589 unsigned long seq;
d828199e 1590 int mode;
cbcf2dd3 1591 u64 ns;
d828199e 1592
d828199e
MT		 1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
cbcf2dd3 1596 ns = gtod->nsec_base;
d828199e
MT		 1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
cbcf2dd3 1599 ns += gtod->boot_ns;
d828199e 1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1601 *t = ns;
d828199e
MT		 1602
1603 return mode;
1604}
1605
1606/* returns true if host is using tsc clocksource */
1607static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608{
d828199e
MT		 1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
cbcf2dd3 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1614}
1615#endif
1616
1617/*
1618 *
b48aa97e
MT		 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
d828199e
MT		 1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
b48aa97e 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1655 *
1656 */
1657
1658static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659{
1660#ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
b48aa97e
MT		 1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
b48aa97e 1672 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
16a96021 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1679
d828199e
MT		 1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
d828199e
MT		 1686#endif
1687}
1688
2860c4b1
PB		 1689void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690{
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692}
1693
2e762ff7
MT		 1694static void kvm_gen_update_masterclock(struct kvm *kvm)
1695{
1696#ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714#endif
1715}
1716
34c238a1 1717static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1718{
27cca94e 1719 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1720 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1721 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1722 s64 kernel_ns;
d828199e 1723 u64 tsc_timestamp, host_tsc;
0b79459b 1724 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1725 u8 pvclock_flags;
d828199e
MT		 1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
18068523 1730
d828199e
MT		 1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
89cbc767 1745 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1746 if (unlikely(this_tsc_khz == 0)) {
1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
d828199e 1751 if (!use_master_clock) {
4ea1636b 1752 host_tsc = rdtsc();
d828199e
MT		 1753 kernel_ns = get_kernel_ns();
1754 }
1755
4ba76538 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1757
c285545f
ZA		 1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
f1e2b260 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1772 tsc_timestamp = tsc;
1773 }
50d0a0f9
GH		 1774 }
1775
18068523
GOC		 1776 local_irq_restore(flags);
1777
0b79459b 1778 if (!vcpu->pv_time_enabled)
c285545f 1779 return 0;
18068523 1780
e48672fa 1781 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1782 tgt_tsc_khz = kvm_has_tsc_control ?
1783 vcpu->virtual_tsc_khz : this_tsc_khz;
1784 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1785 &vcpu->hv_clock.tsc_shift,
1786 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1787 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1788 }
1789
1790 /* With all the info we got, fill in the values */
1d5f066e 1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1793 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1794
09a0c3f1
OH		 1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1796 &guest_hv_clock, sizeof(guest_hv_clock))))
1797 return 0;
1798
5dca0d91
RK		 1799 /* This VCPU is paused, but it's legal for a guest to read another
1800 * VCPU's kvmclock, so we really have to follow the specification where
1801 * it says that version is odd if data is being modified, and even after
1802 * it is consistent.
1803 *
1804 * Version field updates must be kept separate. This is because
1805 * kvm_write_guest_cached might use a "rep movs" instruction, and
1806 * writes within a string instruction are weakly ordered. So there
1807 * are three writes overall.
1808 *
1809 * As a small optimization, only write the version field in the first
1810 * and third write. The vcpu->pv_time cache is still valid, because the
1811 * version field is the first in the struct.
18068523 1812 */
5dca0d91
RK		 1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1814
1815 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1817 &vcpu->hv_clock,
1818 sizeof(vcpu->hv_clock.version));
1819
1820 smp_wmb();
78c0337a
MT		 1821
1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1824
1825 if (vcpu->pvclock_set_guest_stopped_request) {
1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1827 vcpu->pvclock_set_guest_stopped_request = false;
1828 }
1829
d828199e
MT		 1830 /* If the host uses TSC clocksource, then it is stable */
1831 if (use_master_clock)
1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1833
78c0337a
MT		 1834 vcpu->hv_clock.flags = pvclock_flags;
1835
ce1a5e60
DM		 1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837
0b79459b
AH		 1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 &vcpu->hv_clock,
1840 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1841
1842 smp_wmb();
1843
1844 vcpu->hv_clock.version++;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock.version));
8cfdc000 1848 return 0;
c8076604
GH		 1849}
1850
0061d53d
MT		 1851/*
1852 * kvmclock updates which are isolated to a given vcpu, such as
1853 * vcpu->cpu migration, should not allow system_timestamp from
1854 * the rest of the vcpus to remain static. Otherwise ntp frequency
1855 * correction applies to one vcpu's system_timestamp but not
1856 * the others.
1857 *
1858 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1859 * We need to rate-limit these requests though, as they can
1860 * considerably slow guests that have a large number of vcpus.
1861 * The time for a remote vcpu to update its kvmclock is bound
1862 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1863 */
1864
7e44e449
AJ		 1865#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1866
1867static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1868{
1869 int i;
7e44e449
AJ		 1870 struct delayed_work *dwork = to_delayed_work(work);
1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1872 kvmclock_update_work);
1873 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1874 struct kvm_vcpu *vcpu;
1875
1876 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1878 kvm_vcpu_kick(vcpu);
1879 }
1880}
1881
7e44e449
AJ		 1882static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1883{
1884 struct kvm *kvm = v->kvm;
1885
105b21bb 1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1888 KVMCLOCK_UPDATE_DELAY);
1889}
1890
332967a3
AJ		 1891#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1892
1893static void kvmclock_sync_fn(struct work_struct *work)
1894{
1895 struct delayed_work *dwork = to_delayed_work(work);
1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1897 kvmclock_sync_work);
1898 struct kvm *kvm = container_of(ka, struct kvm, arch);
1899
630994b3
MT		 1900 if (!kvmclock_periodic_sync)
1901 return;
1902
332967a3
AJ		 1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1905 KVMCLOCK_SYNC_PERIOD);
1906}
1907
890ca9ae 1908static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1909{
890ca9ae
HY		 1910 u64 mcg_cap = vcpu->arch.mcg_cap;
1911 unsigned bank_num = mcg_cap & 0xff;
1912
15c4a640 1913 switch (msr) {
15c4a640 1914 case MSR_IA32_MCG_STATUS:
890ca9ae 1915 vcpu->arch.mcg_status = data;
15c4a640 1916 break;
c7ac679c 1917 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1918 if (!(mcg_cap & MCG_CTL_P))
1919 return 1;
1920 if (data != 0 && data != ~(u64)0)
1921 return -1;
1922 vcpu->arch.mcg_ctl = data;
1923 break;
1924 default:
1925 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1926 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1927 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1928 /* only 0 or all 1s can be written to IA32_MCi_CTL
1929 * some Linux kernels though clear bit 10 in bank 4 to
1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1931 * this to avoid an uncatched #GP in the guest
1932 */
890ca9ae 1933 if ((offset & 0x3) == 0 &&
114be429 1934 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1935 return -1;
1936 vcpu->arch.mce_banks[offset] = data;
1937 break;
1938 }
1939 return 1;
1940 }
1941 return 0;
1942}
1943
ffde22ac
ES		 1944static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1945{
1946 struct kvm *kvm = vcpu->kvm;
1947 int lm = is_long_mode(vcpu);
1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1951 : kvm->arch.xen_hvm_config.blob_size_32;
1952 u32 page_num = data & ~PAGE_MASK;
1953 u64 page_addr = data & PAGE_MASK;
1954 u8 *page;
1955 int r;
1956
1957 r = -E2BIG;
1958 if (page_num >= blob_size)
1959 goto out;
1960 r = -ENOMEM;
ff5c2c03
SL		 1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1962 if (IS_ERR(page)) {
1963 r = PTR_ERR(page);
ffde22ac 1964 goto out;
ff5c2c03 1965 }
54bf36aa 1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1967 goto out_free;
1968 r = 0;
1969out_free:
1970 kfree(page);
1971out:
1972 return r;
1973}
1974
344d9588
GN		 1975static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1976{
1977 gpa_t gpa = data & ~0x3f;
1978
4a969980 1979 /* Bits 2:5 are reserved, Should be zero */
6adba527 1980 if (data & 0x3c)
344d9588
GN		 1981 return 1;
1982
1983 vcpu->arch.apf.msr_val = data;
1984
1985 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1986 kvm_clear_async_pf_completion_queue(vcpu);
1987 kvm_async_pf_hash_reset(vcpu);
1988 return 0;
1989 }
1990
8f964525
AH		 1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1992 sizeof(u32)))
344d9588
GN		 1993 return 1;
1994
6adba527 1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1996 kvm_async_pf_wakeup_all(vcpu);
1997 return 0;
1998}
1999
12f9a48f
GC		 2000static void kvmclock_reset(struct kvm_vcpu *vcpu)
2001{
0b79459b 2002 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2003}
2004
c9aaa895
GC		 2005static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2006{
2007 u64 delta;
2008
2009 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2010 return;
2011
2012 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2013 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2014 vcpu->arch.st.accum_steal = delta;
2015}
2016
2017static void record_steal_time(struct kvm_vcpu *vcpu)
2018{
7cae2bed
MT		 2019 accumulate_steal_time(vcpu);
2020
c9aaa895
GC		 2021 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2022 return;
2023
2024 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2026 return;
2027
2028 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2029 vcpu->arch.st.steal.version += 2;
2030 vcpu->arch.st.accum_steal = 0;
2031
2032 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2033 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2034}
2035
8fe8ab46 2036int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2037{
5753785f 2038 bool pr = false;
8fe8ab46
WA		 2039 u32 msr = msr_info->index;
2040 u64 data = msr_info->data;
5753785f 2041
15c4a640 2042 switch (msr) {
2e32b719
BP		 2043 case MSR_AMD64_NB_CFG:
2044 case MSR_IA32_UCODE_REV:
2045 case MSR_IA32_UCODE_WRITE:
2046 case MSR_VM_HSAVE_PA:
2047 case MSR_AMD64_PATCH_LOADER:
2048 case MSR_AMD64_BU_CFG2:
2049 break;
2050
15c4a640 2051 case MSR_EFER:
b69e8cae 2052 return set_efer(vcpu, data);
8f1589d9
AP		 2053 case MSR_K7_HWCR:
2054 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2055 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2056 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2057 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2058 if (data != 0) {
a737f256
CD		 2059 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2060 data);
8f1589d9
AP		 2061 return 1;
2062 }
15c4a640 2063 break;
f7c6d140
AP		 2064 case MSR_FAM10H_MMIO_CONF_BASE:
2065 if (data != 0) {
a737f256
CD		 2066 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2067 "0x%llx\n", data);
f7c6d140
AP		 2068 return 1;
2069 }
15c4a640 2070 break;
b5e2fec0
AG		 2071 case MSR_IA32_DEBUGCTLMSR:
2072 if (!data) {
2073 /* We support the non-activated case already */
2074 break;
2075 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2076 /* Values other than LBR and BTF are vendor-specific,
2077 thus reserved and should throw a #GP */
2078 return 1;
2079 }
a737f256
CD		 2080 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2081 __func__, data);
b5e2fec0 2082 break;
9ba075a6 2083 case 0x200 ... 0x2ff:
ff53604b 2084 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2085 case MSR_IA32_APICBASE:
58cb628d 2086 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2087 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2088 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2089 case MSR_IA32_TSCDEADLINE:
2090 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2091 break;
ba904635
WA		 2092 case MSR_IA32_TSC_ADJUST:
2093 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2094 if (!msr_info->host_initiated) {
d913b904 2095 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2096 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2097 }
2098 vcpu->arch.ia32_tsc_adjust_msr = data;
2099 }
2100 break;
15c4a640 2101 case MSR_IA32_MISC_ENABLE:
ad312c7c 2102 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2103 break;
64d60670
PB		 2104 case MSR_IA32_SMBASE:
2105 if (!msr_info->host_initiated)
2106 return 1;
2107 vcpu->arch.smbase = data;
2108 break;
11c6bffa 2109 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2110 case MSR_KVM_WALL_CLOCK:
2111 vcpu->kvm->arch.wall_clock = data;
2112 kvm_write_wall_clock(vcpu->kvm, data);
2113 break;
11c6bffa 2114 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2115 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2116 u64 gpa_offset;
54750f2c
MT		 2117 struct kvm_arch *ka = &vcpu->kvm->arch;
2118
12f9a48f 2119 kvmclock_reset(vcpu);
18068523 2120
54750f2c
MT		 2121 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2122 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2123
2124 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2125 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2126 &vcpu->requests);
2127
2128 ka->boot_vcpu_runs_old_kvmclock = tmp;
2129 }
2130
18068523 2131 vcpu->arch.time = data;
0061d53d 2132 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2133
2134 /* we verify if the enable bit is set... */
2135 if (!(data & 1))
2136 break;
2137
0b79459b 2138 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2139
0b79459b 2140 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2141 &vcpu->arch.pv_time, data & ~1ULL,
2142 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2143 vcpu->arch.pv_time_enabled = false;
2144 else
2145 vcpu->arch.pv_time_enabled = true;
32cad84f 2146
18068523
GOC		 2147 break;
2148 }
344d9588
GN		 2149 case MSR_KVM_ASYNC_PF_EN:
2150 if (kvm_pv_enable_async_pf(vcpu, data))
2151 return 1;
2152 break;
c9aaa895
GC		 2153 case MSR_KVM_STEAL_TIME:
2154
2155 if (unlikely(!sched_info_on()))
2156 return 1;
2157
2158 if (data & KVM_STEAL_RESERVED_MASK)
2159 return 1;
2160
2161 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2162 data & KVM_STEAL_VALID_BITS,
2163 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2164 return 1;
2165
2166 vcpu->arch.st.msr_val = data;
2167
2168 if (!(data & KVM_MSR_ENABLED))
2169 break;
2170
c9aaa895
GC		 2171 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2172
2173 break;
ae7a2a3f
MT		 2174 case MSR_KVM_PV_EOI_EN:
2175 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2176 return 1;
2177 break;
c9aaa895 2178
890ca9ae
HY		 2179 case MSR_IA32_MCG_CTL:
2180 case MSR_IA32_MCG_STATUS:
81760dcc 2181 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2182 return set_msr_mce(vcpu, msr, data);
71db6023 2183
6912ac32
WH		 2184 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2185 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2186 pr = true; /* fall through */
2187 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2188 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2189 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2190 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2191
2192 if (pr || data != 0)
a737f256
CD		 2193 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2194 "0x%x data 0x%llx\n", msr, data);
5753785f 2195 break;
84e0cefa
JS		 2196 case MSR_K7_CLK_CTL:
2197 /*
2198 * Ignore all writes to this no longer documented MSR.
2199 * Writes are only relevant for old K7 processors,
2200 * all pre-dating SVM, but a recommended workaround from
4a969980 2201 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2202 * affected processor models on the command line, hence
2203 * the need to ignore the workaround.
2204 */
2205 break;
55cd8e5a 2206 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2207 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2208 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2209 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2210 return kvm_hv_set_msr_common(vcpu, msr, data,
2211 msr_info->host_initiated);
91c9c3ed 2212 case MSR_IA32_BBL_CR_CTL3:
2213 /* Drop writes to this legacy MSR -- see rdmsr
2214 * counterpart for further detail.
2215 */
a737f256 2216 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2217 break;
2b036c6b
BO		 2218 case MSR_AMD64_OSVW_ID_LENGTH:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.length = data;
2222 break;
2223 case MSR_AMD64_OSVW_STATUS:
2224 if (!guest_cpuid_has_osvw(vcpu))
2225 return 1;
2226 vcpu->arch.osvw.status = data;
2227 break;
15c4a640 2228 default:
ffde22ac
ES		 2229 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2230 return xen_hvm_config(vcpu, data);
c6702c9d 2231 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2232 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2233 if (!ignore_msrs) {
a737f256
CD		 2234 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2235 msr, data);
ed85c068
AP		 2236 return 1;
2237 } else {
a737f256
CD		 2238 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2239 msr, data);
ed85c068
AP		 2240 break;
2241 }
15c4a640
CO		 2242 }
2243 return 0;
2244}
2245EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2246
2247
2248/*
2249 * Reads an msr value (of 'msr_index') into 'pdata'.
2250 * Returns 0 on success, non-0 otherwise.
2251 * Assumes vcpu_load() was already called.
2252 */
609e36d3 2253int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2254{
609e36d3 2255 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2256}
ff651cb6 2257EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2258
890ca9ae 2259static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2260{
2261 u64 data;
890ca9ae
HY		 2262 u64 mcg_cap = vcpu->arch.mcg_cap;
2263 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2264
2265 switch (msr) {
15c4a640
CO		 2266 case MSR_IA32_P5_MC_ADDR:
2267 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2268 data = 0;
2269 break;
15c4a640 2270 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2271 data = vcpu->arch.mcg_cap;
2272 break;
c7ac679c 2273 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2274 if (!(mcg_cap & MCG_CTL_P))
2275 return 1;
2276 data = vcpu->arch.mcg_ctl;
2277 break;
2278 case MSR_IA32_MCG_STATUS:
2279 data = vcpu->arch.mcg_status;
2280 break;
2281 default:
2282 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2283 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2284 u32 offset = msr - MSR_IA32_MC0_CTL;
2285 data = vcpu->arch.mce_banks[offset];
2286 break;
2287 }
2288 return 1;
2289 }
2290 *pdata = data;
2291 return 0;
2292}
2293
609e36d3 2294int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2295{
609e36d3 2296 switch (msr_info->index) {
890ca9ae 2297 case MSR_IA32_PLATFORM_ID:
15c4a640 2298 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2299 case MSR_IA32_DEBUGCTLMSR:
2300 case MSR_IA32_LASTBRANCHFROMIP:
2301 case MSR_IA32_LASTBRANCHTOIP:
2302 case MSR_IA32_LASTINTFROMIP:
2303 case MSR_IA32_LASTINTTOIP:
60af2ecd 2304 case MSR_K8_SYSCFG:
3afb1121
PB		 2305 case MSR_K8_TSEG_ADDR:
2306 case MSR_K8_TSEG_MASK:
60af2ecd 2307 case MSR_K7_HWCR:
61a6bd67 2308 case MSR_VM_HSAVE_PA:
1fdbd48c 2309 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2310 case MSR_AMD64_NB_CFG:
f7c6d140 2311 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2312 case MSR_AMD64_BU_CFG2:
609e36d3 2313 msr_info->data = 0;
15c4a640 2314 break;
6912ac32
WH		 2315 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2316 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2317 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2318 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2319 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2320 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2321 msr_info->data = 0;
5753785f 2322 break;
742bc670 2323 case MSR_IA32_UCODE_REV:
609e36d3 2324 msr_info->data = 0x100000000ULL;
742bc670 2325 break;
9ba075a6 2326 case MSR_MTRRcap:
9ba075a6 2327 case 0x200 ... 0x2ff:
ff53604b 2328 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2329 case 0xcd: /* fsb frequency */
609e36d3 2330 msr_info->data = 3;
15c4a640 2331 break;
7b914098
JS		 2332 /*
2333 * MSR_EBC_FREQUENCY_ID
2334 * Conservative value valid for even the basic CPU models.
2335 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2336 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2337 * and 266MHz for model 3, or 4. Set Core Clock
2338 * Frequency to System Bus Frequency Ratio to 1 (bits
2339 * 31:24) even though these are only valid for CPU
2340 * models > 2, however guests may end up dividing or
2341 * multiplying by zero otherwise.
2342 */
2343 case MSR_EBC_FREQUENCY_ID:
609e36d3 2344 msr_info->data = 1 << 24;
7b914098 2345 break;
15c4a640 2346 case MSR_IA32_APICBASE:
609e36d3 2347 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2348 break;
0105d1a5 2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2350 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2351 break;
a3e06bbe 2352 case MSR_IA32_TSCDEADLINE:
609e36d3 2353 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2354 break;
ba904635 2355 case MSR_IA32_TSC_ADJUST:
609e36d3 2356 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2357 break;
15c4a640 2358 case MSR_IA32_MISC_ENABLE:
609e36d3 2359 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2360 break;
64d60670
PB		 2361 case MSR_IA32_SMBASE:
2362 if (!msr_info->host_initiated)
2363 return 1;
2364 msr_info->data = vcpu->arch.smbase;
15c4a640 2365 break;
847f0ad8
AG		 2366 case MSR_IA32_PERF_STATUS:
2367 /* TSC increment by tick */
609e36d3 2368 msr_info->data = 1000ULL;
847f0ad8 2369 /* CPU multiplier */
b0996ae4 2370 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2371 break;
15c4a640 2372 case MSR_EFER:
609e36d3 2373 msr_info->data = vcpu->arch.efer;
15c4a640 2374 break;
18068523 2375 case MSR_KVM_WALL_CLOCK:
11c6bffa 2376 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2377 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2378 break;
2379 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2380 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2381 msr_info->data = vcpu->arch.time;
18068523 2382 break;
344d9588 2383 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2384 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2385 break;
c9aaa895 2386 case MSR_KVM_STEAL_TIME:
609e36d3 2387 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2388 break;
1d92128f 2389 case MSR_KVM_PV_EOI_EN:
609e36d3 2390 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2391 break;
890ca9ae
HY		 2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
2394 case MSR_IA32_MCG_CAP:
2395 case MSR_IA32_MCG_CTL:
2396 case MSR_IA32_MCG_STATUS:
81760dcc 2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2398 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2399 case MSR_K7_CLK_CTL:
2400 /*
2401 * Provide expected ramp-up count for K7. All other
2402 * are set to zero, indicating minimum divisors for
2403 * every field.
2404 *
2405 * This prevents guest kernels on AMD host with CPU
2406 * type 6, model 8 and higher from exploding due to
2407 * the rdmsr failing.
2408 */
609e36d3 2409 msr_info->data = 0x20000000;
84e0cefa 2410 break;
55cd8e5a 2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2412 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2413 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2414 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2415 return kvm_hv_get_msr_common(vcpu,
2416 msr_info->index, &msr_info->data);
55cd8e5a 2417 break;
91c9c3ed 2418 case MSR_IA32_BBL_CR_CTL3:
2419 /* This legacy MSR exists but isn't fully documented in current
2420 * silicon. It is however accessed by winxp in very narrow
2421 * scenarios where it sets bit #19, itself documented as
2422 * a "reserved" bit. Best effort attempt to source coherent
2423 * read data here should the balance of the register be
2424 * interpreted by the guest:
2425 *
2426 * L2 cache control register 3: 64GB range, 256KB size,
2427 * enabled, latency 0x1, configured
2428 */
609e36d3 2429 msr_info->data = 0xbe702111;
91c9c3ed 2430 break;
2b036c6b
BO		 2431 case MSR_AMD64_OSVW_ID_LENGTH:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
609e36d3 2434 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2435 break;
2436 case MSR_AMD64_OSVW_STATUS:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
609e36d3 2439 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2440 break;
15c4a640 2441 default:
c6702c9d 2442 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2443 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2444 if (!ignore_msrs) {
609e36d3 2445 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2446 return 1;
2447 } else {
609e36d3
PB		 2448 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2449 msr_info->data = 0;
ed85c068
AP		 2450 }
2451 break;
15c4a640 2452 }
15c4a640
CO		 2453 return 0;
2454}
2455EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2456
313a3dc7
CO		 2457/*
2458 * Read or write a bunch of msrs. All parameters are kernel addresses.
2459 *
2460 * @return number of msrs set successfully.
2461 */
2462static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2463 struct kvm_msr_entry *entries,
2464 int (*do_msr)(struct kvm_vcpu *vcpu,
2465 unsigned index, u64 *data))
2466{
f656ce01 2467 int i, idx;
313a3dc7 2468
f656ce01 2469 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2470 for (i = 0; i < msrs->nmsrs; ++i)
2471 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2472 break;
f656ce01 2473 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2474
313a3dc7
CO		 2475 return i;
2476}
2477
2478/*
2479 * Read or write a bunch of msrs. Parameters are user addresses.
2480 *
2481 * @return number of msrs set successfully.
2482 */
2483static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2484 int (*do_msr)(struct kvm_vcpu *vcpu,
2485 unsigned index, u64 *data),
2486 int writeback)
2487{
2488 struct kvm_msrs msrs;
2489 struct kvm_msr_entry *entries;
2490 int r, n;
2491 unsigned size;
2492
2493 r = -EFAULT;
2494 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2495 goto out;
2496
2497 r = -E2BIG;
2498 if (msrs.nmsrs >= MAX_IO_MSRS)
2499 goto out;
2500
313a3dc7 2501 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2502 entries = memdup_user(user_msrs->entries, size);
2503 if (IS_ERR(entries)) {
2504 r = PTR_ERR(entries);
313a3dc7 2505 goto out;
ff5c2c03 2506 }
313a3dc7
CO		 2507
2508 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2509 if (r < 0)
2510 goto out_free;
2511
2512 r = -EFAULT;
2513 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2514 goto out_free;
2515
2516 r = n;
2517
2518out_free:
7a73c028 2519 kfree(entries);
313a3dc7
CO		 2520out:
2521 return r;
2522}
2523
784aa3d7 2524int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2525{
2526 int r;
2527
2528 switch (ext) {
2529 case KVM_CAP_IRQCHIP:
2530 case KVM_CAP_HLT:
2531 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2532 case KVM_CAP_SET_TSS_ADDR:
07716717 2533 case KVM_CAP_EXT_CPUID:
9c15bb1d 2534 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2535 case KVM_CAP_CLOCKSOURCE:
7837699f 2536 case KVM_CAP_PIT:
a28e4f5a 2537 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2538 case KVM_CAP_MP_STATE:
ed848624 2539 case KVM_CAP_SYNC_MMU:
a355c85c 2540 case KVM_CAP_USER_NMI:
52d939a0 2541 case KVM_CAP_REINJECT_CONTROL:
4925663a 2542 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2543 case KVM_CAP_IOEVENTFD:
f848a5a8 2544 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2545 case KVM_CAP_PIT2:
e9f42757 2546 case KVM_CAP_PIT_STATE2:
b927a3ce 2547 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2548 case KVM_CAP_XEN_HVM:
afbcf7ab 2549 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2550 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2551 case KVM_CAP_HYPERV:
10388a07 2552 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2553 case KVM_CAP_HYPERV_SPIN:
5c919412 2554 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2555 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2556 case KVM_CAP_DEBUGREGS:
d2be1651 2557 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2558 case KVM_CAP_XSAVE:
344d9588 2559 case KVM_CAP_ASYNC_PF:
92a1f12d 2560 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2561 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2562 case KVM_CAP_READONLY_MEM:
5f66b620 2563 case KVM_CAP_HYPERV_TIME:
100943c5 2564 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2565 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2566 case KVM_CAP_ENABLE_CAP_VM:
2567 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2568 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2569 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2570#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2571 case KVM_CAP_ASSIGN_DEV_IRQ:
2572 case KVM_CAP_PCI_2_3:
2573#endif
018d00d2
ZX		 2574 r = 1;
2575 break;
6d396b55
PB		 2576 case KVM_CAP_X86_SMM:
2577 /* SMBASE is usually relocated above 1M on modern chipsets,
2578 * and SMM handlers might indeed rely on 4G segment limits,
2579 * so do not report SMM to be available if real mode is
2580 * emulated via vm86 mode. Still, do not go to great lengths
2581 * to avoid userspace's usage of the feature, because it is a
2582 * fringe case that is not enabled except via specific settings
2583 * of the module parameters.
2584 */
2585 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2586 break;
542472b5
LV		 2587 case KVM_CAP_COALESCED_MMIO:
2588 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2589 break;
774ead3a
AK		 2590 case KVM_CAP_VAPIC:
2591 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2592 break;
f725230a 2593 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2594 r = KVM_SOFT_MAX_VCPUS;
2595 break;
2596 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2597 r = KVM_MAX_VCPUS;
2598 break;
a988b910 2599 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2600 r = KVM_USER_MEM_SLOTS;
a988b910 2601 break;
a68a6a72
MT		 2602 case KVM_CAP_PV_MMU: /* obsolete */
2603 r = 0;
2f333bcb 2604 break;
4cee4b72 2605#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2606 case KVM_CAP_IOMMU:
a1b60c1c 2607 r = iommu_present(&pci_bus_type);
62c476c7 2608 break;
4cee4b72 2609#endif
890ca9ae
HY		 2610 case KVM_CAP_MCE:
2611 r = KVM_MAX_MCE_BANKS;
2612 break;
2d5b5a66
SY		 2613 case KVM_CAP_XCRS:
2614 r = cpu_has_xsave;
2615 break;
92a1f12d
JR		 2616 case KVM_CAP_TSC_CONTROL:
2617 r = kvm_has_tsc_control;
2618 break;
018d00d2
ZX		 2619 default:
2620 r = 0;
2621 break;
2622 }
2623 return r;
2624
2625}
2626
043405e1
CO		 2627long kvm_arch_dev_ioctl(struct file *filp,
2628 unsigned int ioctl, unsigned long arg)
2629{
2630 void __user *argp = (void __user *)arg;
2631 long r;
2632
2633 switch (ioctl) {
2634 case KVM_GET_MSR_INDEX_LIST: {
2635 struct kvm_msr_list __user *user_msr_list = argp;
2636 struct kvm_msr_list msr_list;
2637 unsigned n;
2638
2639 r = -EFAULT;
2640 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2641 goto out;
2642 n = msr_list.nmsrs;
62ef68bb 2643 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2644 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2645 goto out;
2646 r = -E2BIG;
e125e7b6 2647 if (n < msr_list.nmsrs)
043405e1
CO		 2648 goto out;
2649 r = -EFAULT;
2650 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2651 num_msrs_to_save * sizeof(u32)))
2652 goto out;
e125e7b6 2653 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2654 &emulated_msrs,
62ef68bb 2655 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2656 goto out;
2657 r = 0;
2658 break;
2659 }
9c15bb1d
BP		 2660 case KVM_GET_SUPPORTED_CPUID:
2661 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2662 struct kvm_cpuid2 __user *cpuid_arg = argp;
2663 struct kvm_cpuid2 cpuid;
2664
2665 r = -EFAULT;
2666 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2667 goto out;
9c15bb1d
BP		 2668
2669 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2670 ioctl);
674eea0f
AK		 2671 if (r)
2672 goto out;
2673
2674 r = -EFAULT;
2675 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2676 goto out;
2677 r = 0;
2678 break;
2679 }
890ca9ae
HY		 2680 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2681 u64 mce_cap;
2682
2683 mce_cap = KVM_MCE_CAP_SUPPORTED;
2684 r = -EFAULT;
2685 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2686 goto out;
2687 r = 0;
2688 break;
2689 }
043405e1
CO		 2690 default:
2691 r = -EINVAL;
2692 }
2693out:
2694 return r;
2695}
2696
f5f48ee1
SY		 2697static void wbinvd_ipi(void *garbage)
2698{
2699 wbinvd();
2700}
2701
2702static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2703{
e0f0bbc5 2704 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2705}
2706
2860c4b1
PB		 2707static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2708{
2709 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2710}
2711
313a3dc7
CO		 2712void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2713{
f5f48ee1
SY		 2714 /* Address WBINVD may be executed by guest */
2715 if (need_emulate_wbinvd(vcpu)) {
2716 if (kvm_x86_ops->has_wbinvd_exit())
2717 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2718 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2719 smp_call_function_single(vcpu->cpu,
2720 wbinvd_ipi, NULL, 1);
2721 }
2722
313a3dc7 2723 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2724
0dd6a6ed
ZA		 2725 /* Apply any externally detected TSC adjustments (due to suspend) */
2726 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2727 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2728 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2730 }
8f6055cb 2731
48434c20 2732 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2733 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2734 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2735 if (tsc_delta < 0)
2736 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2737 if (check_tsc_unstable()) {
07c1419a 2738 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2739 vcpu->arch.last_guest_tsc);
2740 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2741 vcpu->arch.tsc_catchup = 1;
c285545f 2742 }
d98d07ca
MT		 2743 /*
2744 * On a host with synchronized TSC, there is no need to update
2745 * kvmclock on vcpu->cpu migration
2746 */
2747 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2748 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2749 if (vcpu->cpu != cpu)
2750 kvm_migrate_timers(vcpu);
e48672fa 2751 vcpu->cpu = cpu;
6b7d7e76 2752 }
c9aaa895 2753
c9aaa895 2754 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2755}
2756
2757void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2758{
02daab21 2759 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2760 kvm_put_guest_fpu(vcpu);
4ea1636b 2761 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2762}
2763
313a3dc7
CO		 2764static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2765 struct kvm_lapic_state *s)
2766{
d62caabb
AS		 2767 if (vcpu->arch.apicv_active)
2768 kvm_x86_ops->sync_pir_to_irr(vcpu);
2769
ad312c7c 2770 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2771
2772 return 0;
2773}
2774
2775static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2776 struct kvm_lapic_state *s)
2777{
64eb0620 2778 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2779 update_cr8_intercept(vcpu);
313a3dc7
CO		 2780
2781 return 0;
2782}
2783
127a457a
MG		 2784static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2785{
2786 return (!lapic_in_kernel(vcpu) ||
2787 kvm_apic_accept_pic_intr(vcpu));
2788}
2789
782d422b
MG		 2790/*
2791 * if userspace requested an interrupt window, check that the
2792 * interrupt window is open.
2793 *
2794 * No need to exit to userspace if we already have an interrupt queued.
2795 */
2796static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2797{
2798 return kvm_arch_interrupt_allowed(vcpu) &&
2799 !kvm_cpu_has_interrupt(vcpu) &&
2800 !kvm_event_needs_reinjection(vcpu) &&
2801 kvm_cpu_accept_dm_intr(vcpu);
2802}
2803
f77bc6a4
ZX		 2804static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2805 struct kvm_interrupt *irq)
2806{
02cdb50f 2807 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2808 return -EINVAL;
1c1a9ce9
SR		 2809
2810 if (!irqchip_in_kernel(vcpu->kvm)) {
2811 kvm_queue_interrupt(vcpu, irq->irq, false);
2812 kvm_make_request(KVM_REQ_EVENT, vcpu);
2813 return 0;
2814 }
2815
2816 /*
2817 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2818 * fail for in-kernel 8259.
2819 */
2820 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2821 return -ENXIO;
f77bc6a4 2822
1c1a9ce9
SR		 2823 if (vcpu->arch.pending_external_vector != -1)
2824 return -EEXIST;
f77bc6a4 2825
1c1a9ce9 2826 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2827 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2828 return 0;
2829}
2830
c4abb7c9
JK		 2831static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2832{
c4abb7c9 2833 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2834
2835 return 0;
2836}
2837
f077825a
PB		 2838static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2839{
64d60670
PB		 2840 kvm_make_request(KVM_REQ_SMI, vcpu);
2841
f077825a
PB		 2842 return 0;
2843}
2844
b209749f
AK		 2845static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2846 struct kvm_tpr_access_ctl *tac)
2847{
2848 if (tac->flags)
2849 return -EINVAL;
2850 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2851 return 0;
2852}
2853
890ca9ae
HY		 2854static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2855 u64 mcg_cap)
2856{
2857 int r;
2858 unsigned bank_num = mcg_cap & 0xff, bank;
2859
2860 r = -EINVAL;
a9e38c3e 2861 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2862 goto out;
2863 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2864 goto out;
2865 r = 0;
2866 vcpu->arch.mcg_cap = mcg_cap;
2867 /* Init IA32_MCG_CTL to all 1s */
2868 if (mcg_cap & MCG_CTL_P)
2869 vcpu->arch.mcg_ctl = ~(u64)0;
2870 /* Init IA32_MCi_CTL to all 1s */
2871 for (bank = 0; bank < bank_num; bank++)
2872 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2873out:
2874 return r;
2875}
2876
2877static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2878 struct kvm_x86_mce *mce)
2879{
2880 u64 mcg_cap = vcpu->arch.mcg_cap;
2881 unsigned bank_num = mcg_cap & 0xff;
2882 u64 *banks = vcpu->arch.mce_banks;
2883
2884 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2885 return -EINVAL;
2886 /*
2887 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2888 * reporting is disabled
2889 */
2890 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2891 vcpu->arch.mcg_ctl != ~(u64)0)
2892 return 0;
2893 banks += 4 * mce->bank;
2894 /*
2895 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2896 * reporting is disabled for the bank
2897 */
2898 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2899 return 0;
2900 if (mce->status & MCI_STATUS_UC) {
2901 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2902 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2903 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2904 return 0;
2905 }
2906 if (banks[1] & MCI_STATUS_VAL)
2907 mce->status |= MCI_STATUS_OVER;
2908 banks[2] = mce->addr;
2909 banks[3] = mce->misc;
2910 vcpu->arch.mcg_status = mce->mcg_status;
2911 banks[1] = mce->status;
2912 kvm_queue_exception(vcpu, MC_VECTOR);
2913 } else if (!(banks[1] & MCI_STATUS_VAL)
2914 || !(banks[1] & MCI_STATUS_UC)) {
2915 if (banks[1] & MCI_STATUS_VAL)
2916 mce->status |= MCI_STATUS_OVER;
2917 banks[2] = mce->addr;
2918 banks[3] = mce->misc;
2919 banks[1] = mce->status;
2920 } else
2921 banks[1] |= MCI_STATUS_OVER;
2922 return 0;
2923}
2924
3cfc3092
JK		 2925static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2927{
7460fb4a 2928 process_nmi(vcpu);
03b82a30
JK		 2929 events->exception.injected =
2930 vcpu->arch.exception.pending &&
2931 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2932 events->exception.nr = vcpu->arch.exception.nr;
2933 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2934 events->exception.pad = 0;
3cfc3092
JK		 2935 events->exception.error_code = vcpu->arch.exception.error_code;
2936
03b82a30
JK		 2937 events->interrupt.injected =
2938 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2939 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2940 events->interrupt.soft = 0;
37ccdcbe 2941 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2942
2943 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2944 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2945 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2946 events->nmi.pad = 0;
3cfc3092 2947
66450a21 2948 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2949
f077825a
PB		 2950 events->smi.smm = is_smm(vcpu);
2951 events->smi.pending = vcpu->arch.smi_pending;
2952 events->smi.smm_inside_nmi =
2953 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2954 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2955
dab4b911 2956 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2957 | KVM_VCPUEVENT_VALID_SHADOW
2958 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2959 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2960}
2961
2962static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2963 struct kvm_vcpu_events *events)
2964{
dab4b911 2965 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2966 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2967 | KVM_VCPUEVENT_VALID_SHADOW
2968 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2969 return -EINVAL;
2970
7460fb4a 2971 process_nmi(vcpu);
3cfc3092
JK		 2972 vcpu->arch.exception.pending = events->exception.injected;
2973 vcpu->arch.exception.nr = events->exception.nr;
2974 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2975 vcpu->arch.exception.error_code = events->exception.error_code;
2976
2977 vcpu->arch.interrupt.pending = events->interrupt.injected;
2978 vcpu->arch.interrupt.nr = events->interrupt.nr;
2979 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2980 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2981 kvm_x86_ops->set_interrupt_shadow(vcpu,
2982 events->interrupt.shadow);
3cfc3092
JK		 2983
2984 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2985 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2986 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2987 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2988
66450a21
JK		 2989 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2990 kvm_vcpu_has_lapic(vcpu))
2991 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2992
f077825a
PB		 2993 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2994 if (events->smi.smm)
2995 vcpu->arch.hflags |= HF_SMM_MASK;
2996 else
2997 vcpu->arch.hflags &= ~HF_SMM_MASK;
2998 vcpu->arch.smi_pending = events->smi.pending;
2999 if (events->smi.smm_inside_nmi)
3000 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3001 else
3002 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3003 if (kvm_vcpu_has_lapic(vcpu)) {
3004 if (events->smi.latched_init)
3005 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3006 else
3007 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3008 }
3009 }
3010
3842d135
AK		 3011 kvm_make_request(KVM_REQ_EVENT, vcpu);
3012
3cfc3092
JK		 3013 return 0;
3014}
3015
a1efbe77
JK		 3016static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3017 struct kvm_debugregs *dbgregs)
3018{
73aaf249
JK		 3019 unsigned long val;
3020
a1efbe77 3021 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3022 kvm_get_dr(vcpu, 6, &val);
73aaf249 3023 dbgregs->dr6 = val;
a1efbe77
JK		 3024 dbgregs->dr7 = vcpu->arch.dr7;
3025 dbgregs->flags = 0;
97e69aa6 3026 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3027}
3028
3029static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3030 struct kvm_debugregs *dbgregs)
3031{
3032 if (dbgregs->flags)
3033 return -EINVAL;
3034
a1efbe77 3035 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3036 kvm_update_dr0123(vcpu);
a1efbe77 3037 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3038 kvm_update_dr6(vcpu);
a1efbe77 3039 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3040 kvm_update_dr7(vcpu);
a1efbe77 3041
a1efbe77
JK		 3042 return 0;
3043}
3044
df1daba7
PB		 3045#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3046
3047static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3048{
c47ada30 3049 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3050 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3051 u64 valid;
3052
3053 /*
3054 * Copy legacy XSAVE area, to avoid complications with CPUID
3055 * leaves 0 and 1 in the loop below.
3056 */
3057 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3058
3059 /* Set XSTATE_BV */
3060 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3061
3062 /*
3063 * Copy each region from the possibly compacted offset to the
3064 * non-compacted offset.
3065 */
d91cab78 3066 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3067 while (valid) {
3068 u64 feature = valid & -valid;
3069 int index = fls64(feature) - 1;
3070 void *src = get_xsave_addr(xsave, feature);
3071
3072 if (src) {
3073 u32 size, offset, ecx, edx;
3074 cpuid_count(XSTATE_CPUID, index,
3075 &size, &offset, &ecx, &edx);
3076 memcpy(dest + offset, src, size);
3077 }
3078
3079 valid -= feature;
3080 }
3081}
3082
3083static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3084{
c47ada30 3085 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3086 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3087 u64 valid;
3088
3089 /*
3090 * Copy legacy XSAVE area, to avoid complications with CPUID
3091 * leaves 0 and 1 in the loop below.
3092 */
3093 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3094
3095 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3096 xsave->header.xfeatures = xstate_bv;
df1daba7 3097 if (cpu_has_xsaves)
3a54450b 3098 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3099
3100 /*
3101 * Copy each region from the non-compacted offset to the
3102 * possibly compacted offset.
3103 */
d91cab78 3104 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3105 while (valid) {
3106 u64 feature = valid & -valid;
3107 int index = fls64(feature) - 1;
3108 void *dest = get_xsave_addr(xsave, feature);
3109
3110 if (dest) {
3111 u32 size, offset, ecx, edx;
3112 cpuid_count(XSTATE_CPUID, index,
3113 &size, &offset, &ecx, &edx);
3114 memcpy(dest, src + offset, size);
ee4100da 3115 }
df1daba7
PB		 3116
3117 valid -= feature;
3118 }
3119}
3120
2d5b5a66
SY		 3121static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3122 struct kvm_xsave *guest_xsave)
3123{
4344ee98 3124 if (cpu_has_xsave) {
df1daba7
PB		 3125 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3126 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3127 } else {
2d5b5a66 3128 memcpy(guest_xsave->region,
7366ed77 3129 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3130 sizeof(struct fxregs_state));
2d5b5a66 3131 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3132 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3133 }
3134}
3135
3136static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3137 struct kvm_xsave *guest_xsave)
3138{
3139 u64 xstate_bv =
3140 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3141
d7876f1b
PB		 3142 if (cpu_has_xsave) {
3143 /*
3144 * Here we allow setting states that are not present in
3145 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3146 * with old userspace.
3147 */
4ff41732 3148 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3149 return -EINVAL;
df1daba7 3150 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3151 } else {
d91cab78 3152 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3153 return -EINVAL;
7366ed77 3154 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3155 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3156 }
3157 return 0;
3158}
3159
3160static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3161 struct kvm_xcrs *guest_xcrs)
3162{
3163 if (!cpu_has_xsave) {
3164 guest_xcrs->nr_xcrs = 0;
3165 return;
3166 }
3167
3168 guest_xcrs->nr_xcrs = 1;
3169 guest_xcrs->flags = 0;
3170 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3171 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3172}
3173
3174static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3175 struct kvm_xcrs *guest_xcrs)
3176{
3177 int i, r = 0;
3178
3179 if (!cpu_has_xsave)
3180 return -EINVAL;
3181
3182 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3183 return -EINVAL;
3184
3185 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3186 /* Only support XCR0 currently */
c67a04cb 3187 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3188 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3189 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3190 break;
3191 }
3192 if (r)
3193 r = -EINVAL;
3194 return r;
3195}
3196
1c0b28c2
EM		 3197/*
3198 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3199 * stopped by the hypervisor. This function will be called from the host only.
3200 * EINVAL is returned when the host attempts to set the flag for a guest that
3201 * does not support pv clocks.
3202 */
3203static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3204{
0b79459b 3205 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3206 return -EINVAL;
51d59c6b 3207 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3208 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3209 return 0;
3210}
3211
5c919412
AS		 3212static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3213 struct kvm_enable_cap *cap)
3214{
3215 if (cap->flags)
3216 return -EINVAL;
3217
3218 switch (cap->cap) {
3219 case KVM_CAP_HYPERV_SYNIC:
3220 return kvm_hv_activate_synic(vcpu);
3221 default:
3222 return -EINVAL;
3223 }
3224}
3225
313a3dc7
CO		 3226long kvm_arch_vcpu_ioctl(struct file *filp,
3227 unsigned int ioctl, unsigned long arg)
3228{
3229 struct kvm_vcpu *vcpu = filp->private_data;
3230 void __user *argp = (void __user *)arg;
3231 int r;
d1ac91d8
AK		 3232 union {
3233 struct kvm_lapic_state *lapic;
3234 struct kvm_xsave *xsave;
3235 struct kvm_xcrs *xcrs;
3236 void *buffer;
3237 } u;
3238
3239 u.buffer = NULL;
313a3dc7
CO		 3240 switch (ioctl) {
3241 case KVM_GET_LAPIC: {
2204ae3c
MT		 3242 r = -EINVAL;
3243 if (!vcpu->arch.apic)
3244 goto out;
d1ac91d8 3245 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3246
b772ff36 3247 r = -ENOMEM;
d1ac91d8 3248 if (!u.lapic)
b772ff36 3249 goto out;
d1ac91d8 3250 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3251 if (r)
3252 goto out;
3253 r = -EFAULT;
d1ac91d8 3254 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3255 goto out;
3256 r = 0;
3257 break;
3258 }
3259 case KVM_SET_LAPIC: {
2204ae3c
MT		 3260 r = -EINVAL;
3261 if (!vcpu->arch.apic)
3262 goto out;
ff5c2c03 3263 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3264 if (IS_ERR(u.lapic))
3265 return PTR_ERR(u.lapic);
ff5c2c03 3266
d1ac91d8 3267 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3268 break;
3269 }
f77bc6a4
ZX		 3270 case KVM_INTERRUPT: {
3271 struct kvm_interrupt irq;
3272
3273 r = -EFAULT;
3274 if (copy_from_user(&irq, argp, sizeof irq))
3275 goto out;
3276 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3277 break;
3278 }
c4abb7c9
JK		 3279 case KVM_NMI: {
3280 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3281 break;
3282 }
f077825a
PB		 3283 case KVM_SMI: {
3284 r = kvm_vcpu_ioctl_smi(vcpu);
3285 break;
3286 }
313a3dc7
CO		 3287 case KVM_SET_CPUID: {
3288 struct kvm_cpuid __user *cpuid_arg = argp;
3289 struct kvm_cpuid cpuid;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3293 goto out;
3294 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3295 break;
3296 }
07716717
DK		 3297 case KVM_SET_CPUID2: {
3298 struct kvm_cpuid2 __user *cpuid_arg = argp;
3299 struct kvm_cpuid2 cpuid;
3300
3301 r = -EFAULT;
3302 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3303 goto out;
3304 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3305 cpuid_arg->entries);
07716717
DK		 3306 break;
3307 }
3308 case KVM_GET_CPUID2: {
3309 struct kvm_cpuid2 __user *cpuid_arg = argp;
3310 struct kvm_cpuid2 cpuid;
3311
3312 r = -EFAULT;
3313 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3314 goto out;
3315 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3316 cpuid_arg->entries);
07716717
DK		 3317 if (r)
3318 goto out;
3319 r = -EFAULT;
3320 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3321 goto out;
3322 r = 0;
3323 break;
3324 }
313a3dc7 3325 case KVM_GET_MSRS:
609e36d3 3326 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3327 break;
3328 case KVM_SET_MSRS:
3329 r = msr_io(vcpu, argp, do_set_msr, 0);
3330 break;
b209749f
AK		 3331 case KVM_TPR_ACCESS_REPORTING: {
3332 struct kvm_tpr_access_ctl tac;
3333
3334 r = -EFAULT;
3335 if (copy_from_user(&tac, argp, sizeof tac))
3336 goto out;
3337 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3338 if (r)
3339 goto out;
3340 r = -EFAULT;
3341 if (copy_to_user(argp, &tac, sizeof tac))
3342 goto out;
3343 r = 0;
3344 break;
3345 };
b93463aa
AK		 3346 case KVM_SET_VAPIC_ADDR: {
3347 struct kvm_vapic_addr va;
3348
3349 r = -EINVAL;
35754c98 3350 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3351 goto out;
3352 r = -EFAULT;
3353 if (copy_from_user(&va, argp, sizeof va))
3354 goto out;
fda4e2e8 3355 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3356 break;
3357 }
890ca9ae
HY		 3358 case KVM_X86_SETUP_MCE: {
3359 u64 mcg_cap;
3360
3361 r = -EFAULT;
3362 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3363 goto out;
3364 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3365 break;
3366 }
3367 case KVM_X86_SET_MCE: {
3368 struct kvm_x86_mce mce;
3369
3370 r = -EFAULT;
3371 if (copy_from_user(&mce, argp, sizeof mce))
3372 goto out;
3373 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3374 break;
3375 }
3cfc3092
JK		 3376 case KVM_GET_VCPU_EVENTS: {
3377 struct kvm_vcpu_events events;
3378
3379 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3380
3381 r = -EFAULT;
3382 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3383 break;
3384 r = 0;
3385 break;
3386 }
3387 case KVM_SET_VCPU_EVENTS: {
3388 struct kvm_vcpu_events events;
3389
3390 r = -EFAULT;
3391 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3392 break;
3393
3394 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3395 break;
3396 }
a1efbe77
JK		 3397 case KVM_GET_DEBUGREGS: {
3398 struct kvm_debugregs dbgregs;
3399
3400 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3401
3402 r = -EFAULT;
3403 if (copy_to_user(argp, &dbgregs,
3404 sizeof(struct kvm_debugregs)))
3405 break;
3406 r = 0;
3407 break;
3408 }
3409 case KVM_SET_DEBUGREGS: {
3410 struct kvm_debugregs dbgregs;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&dbgregs, argp,
3414 sizeof(struct kvm_debugregs)))
3415 break;
3416
3417 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3418 break;
3419 }
2d5b5a66 3420 case KVM_GET_XSAVE: {
d1ac91d8 3421 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3422 r = -ENOMEM;
d1ac91d8 3423 if (!u.xsave)
2d5b5a66
SY		 3424 break;
3425
d1ac91d8 3426 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3427
3428 r = -EFAULT;
d1ac91d8 3429 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3430 break;
3431 r = 0;
3432 break;
3433 }
3434 case KVM_SET_XSAVE: {
ff5c2c03 3435 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3436 if (IS_ERR(u.xsave))
3437 return PTR_ERR(u.xsave);
2d5b5a66 3438
d1ac91d8 3439 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3440 break;
3441 }
3442 case KVM_GET_XCRS: {
d1ac91d8 3443 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3444 r = -ENOMEM;
d1ac91d8 3445 if (!u.xcrs)
2d5b5a66
SY		 3446 break;
3447
d1ac91d8 3448 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3449
3450 r = -EFAULT;
d1ac91d8 3451 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3452 sizeof(struct kvm_xcrs)))
3453 break;
3454 r = 0;
3455 break;
3456 }
3457 case KVM_SET_XCRS: {
ff5c2c03 3458 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3459 if (IS_ERR(u.xcrs))
3460 return PTR_ERR(u.xcrs);
2d5b5a66 3461
d1ac91d8 3462 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3463 break;
3464 }
92a1f12d
JR		 3465 case KVM_SET_TSC_KHZ: {
3466 u32 user_tsc_khz;
3467
3468 r = -EINVAL;
92a1f12d
JR		 3469 user_tsc_khz = (u32)arg;
3470
3471 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3472 goto out;
3473
cc578287
ZA		 3474 if (user_tsc_khz == 0)
3475 user_tsc_khz = tsc_khz;
3476
381d585c
HZ		 3477 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3478 r = 0;
92a1f12d 3479
92a1f12d
JR		 3480 goto out;
3481 }
3482 case KVM_GET_TSC_KHZ: {
cc578287 3483 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3484 goto out;
3485 }
1c0b28c2
EM		 3486 case KVM_KVMCLOCK_CTRL: {
3487 r = kvm_set_guest_paused(vcpu);
3488 goto out;
3489 }
5c919412
AS		 3490 case KVM_ENABLE_CAP: {
3491 struct kvm_enable_cap cap;
3492
3493 r = -EFAULT;
3494 if (copy_from_user(&cap, argp, sizeof(cap)))
3495 goto out;
3496 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3497 break;
3498 }
313a3dc7
CO		 3499 default:
3500 r = -EINVAL;
3501 }
3502out:
d1ac91d8 3503 kfree(u.buffer);
313a3dc7
CO		 3504 return r;
3505}
3506
5b1c1493
CO		 3507int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3508{
3509 return VM_FAULT_SIGBUS;
3510}
3511
1fe779f8
CO		 3512static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3513{
3514 int ret;
3515
3516 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3517 return -EINVAL;
1fe779f8
CO		 3518 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3519 return ret;
3520}
3521
b927a3ce
SY		 3522static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3523 u64 ident_addr)
3524{
3525 kvm->arch.ept_identity_map_addr = ident_addr;
3526 return 0;
3527}
3528
1fe779f8
CO		 3529static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3530 u32 kvm_nr_mmu_pages)
3531{
3532 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3533 return -EINVAL;
3534
79fac95e 3535 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3536
3537 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3538 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3539
79fac95e 3540 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3541 return 0;
3542}
3543
3544static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3545{
39de71ec 3546 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3547}
3548
1fe779f8
CO		 3549static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3550{
3551 int r;
3552
3553 r = 0;
3554 switch (chip->chip_id) {
3555 case KVM_IRQCHIP_PIC_MASTER:
3556 memcpy(&chip->chip.pic,
3557 &pic_irqchip(kvm)->pics[0],
3558 sizeof(struct kvm_pic_state));
3559 break;
3560 case KVM_IRQCHIP_PIC_SLAVE:
3561 memcpy(&chip->chip.pic,
3562 &pic_irqchip(kvm)->pics[1],
3563 sizeof(struct kvm_pic_state));
3564 break;
3565 case KVM_IRQCHIP_IOAPIC:
eba0226b 3566 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3567 break;
3568 default:
3569 r = -EINVAL;
3570 break;
3571 }
3572 return r;
3573}
3574
3575static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3576{
3577 int r;
3578
3579 r = 0;
3580 switch (chip->chip_id) {
3581 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3582 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3583 memcpy(&pic_irqchip(kvm)->pics[0],
3584 &chip->chip.pic,
3585 sizeof(struct kvm_pic_state));
f4f51050 3586 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3587 break;
3588 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3589 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3590 memcpy(&pic_irqchip(kvm)->pics[1],
3591 &chip->chip.pic,
3592 sizeof(struct kvm_pic_state));
f4f51050 3593 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3594 break;
3595 case KVM_IRQCHIP_IOAPIC:
eba0226b 3596 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3597 break;
3598 default:
3599 r = -EINVAL;
3600 break;
3601 }
3602 kvm_pic_update_irq(pic_irqchip(kvm));
3603 return r;
3604}
3605
e0f63cb9
SY		 3606static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3607{
894a9c55 3608 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3609 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3610 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3611 return 0;
e0f63cb9
SY		 3612}
3613
3614static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3615{
0185604c 3616 int i;
894a9c55 3617 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3618 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
0185604c
AH		 3619 for (i = 0; i < 3; i++)
3620 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
e9f42757 3621 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3622 return 0;
e9f42757
BK		 3623}
3624
3625static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3626{
e9f42757
BK		 3627 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3628 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3629 sizeof(ps->channels));
3630 ps->flags = kvm->arch.vpit->pit_state.flags;
3631 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3632 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3633 return 0;
e9f42757
BK		 3634}
3635
3636static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3637{
2da29bcc 3638 int start = 0;
0185604c 3639 int i;
e9f42757
BK		 3640 u32 prev_legacy, cur_legacy;
3641 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3642 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3643 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3644 if (!prev_legacy && cur_legacy)
3645 start = 1;
3646 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3647 sizeof(kvm->arch.vpit->pit_state.channels));
3648 kvm->arch.vpit->pit_state.flags = ps->flags;
0185604c 3649 for (i = 0; i < 3; i++)
e5e57e7a
PB		 3650 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count,
3651 start && i == 0);
894a9c55 3652 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3653 return 0;
e0f63cb9
SY		 3654}
3655
52d939a0
MT		 3656static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3657 struct kvm_reinject_control *control)
3658{
3659 if (!kvm->arch.vpit)
3660 return -ENXIO;
894a9c55 3661 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3662 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3663 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3664 return 0;
3665}
3666
95d4c16c 3667/**
60c34612
TY		 3668 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3669 * @kvm: kvm instance
3670 * @log: slot id and address to which we copy the log
95d4c16c 3671 *
e108ff2f
PB		 3672 * Steps 1-4 below provide general overview of dirty page logging. See
3673 * kvm_get_dirty_log_protect() function description for additional details.
3674 *
3675 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3676 * always flush the TLB (step 4) even if previous step failed and the dirty
3677 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3678 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3679 * writes will be marked dirty for next log read.
95d4c16c 3680 *
60c34612
TY		 3681 * 1. Take a snapshot of the bit and clear it if needed.
3682 * 2. Write protect the corresponding page.
e108ff2f
PB		 3683 * 3. Copy the snapshot to the userspace.
3684 * 4. Flush TLB's if needed.
5bb064dc 3685 */
60c34612 3686int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3687{
60c34612 3688 bool is_dirty = false;
e108ff2f 3689 int r;
5bb064dc 3690
79fac95e 3691 mutex_lock(&kvm->slots_lock);
5bb064dc 3692
88178fd4
KH		 3693 /*
3694 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3695 */
3696 if (kvm_x86_ops->flush_log_dirty)
3697 kvm_x86_ops->flush_log_dirty(kvm);
3698
e108ff2f 3699 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3700
3701 /*
3702 * All the TLBs can be flushed out of mmu lock, see the comments in
3703 * kvm_mmu_slot_remove_write_access().
3704 */
e108ff2f 3705 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3706 if (is_dirty)
3707 kvm_flush_remote_tlbs(kvm);
3708
79fac95e 3709 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3710 return r;
3711}
3712
aa2fbe6d
YZ		 3713int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3714 bool line_status)
23d43cf9
CD		 3715{
3716 if (!irqchip_in_kernel(kvm))
3717 return -ENXIO;
3718
3719 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3720 irq_event->irq, irq_event->level,
3721 line_status);
23d43cf9
CD		 3722 return 0;
3723}
3724
90de4a18
NA		 3725static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3726 struct kvm_enable_cap *cap)
3727{
3728 int r;
3729
3730 if (cap->flags)
3731 return -EINVAL;
3732
3733 switch (cap->cap) {
3734 case KVM_CAP_DISABLE_QUIRKS:
3735 kvm->arch.disabled_quirks = cap->args[0];
3736 r = 0;
3737 break;
49df6397
SR		 3738 case KVM_CAP_SPLIT_IRQCHIP: {
3739 mutex_lock(&kvm->lock);
b053b2ae
SR		 3740 r = -EINVAL;
3741 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3742 goto split_irqchip_unlock;
49df6397
SR		 3743 r = -EEXIST;
3744 if (irqchip_in_kernel(kvm))
3745 goto split_irqchip_unlock;
3746 if (atomic_read(&kvm->online_vcpus))
3747 goto split_irqchip_unlock;
3748 r = kvm_setup_empty_irq_routing(kvm);
3749 if (r)
3750 goto split_irqchip_unlock;
3751 /* Pairs with irqchip_in_kernel. */
3752 smp_wmb();
3753 kvm->arch.irqchip_split = true;
b053b2ae 3754 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3755 r = 0;
3756split_irqchip_unlock:
3757 mutex_unlock(&kvm->lock);
3758 break;
3759 }
90de4a18
NA		 3760 default:
3761 r = -EINVAL;
3762 break;
3763 }
3764 return r;
3765}
3766
1fe779f8
CO		 3767long kvm_arch_vm_ioctl(struct file *filp,
3768 unsigned int ioctl, unsigned long arg)
3769{
3770 struct kvm *kvm = filp->private_data;
3771 void __user *argp = (void __user *)arg;
367e1319 3772 int r = -ENOTTY;
f0d66275
DH		 3773 /*
3774 * This union makes it completely explicit to gcc-3.x
3775 * that these two variables' stack usage should be
3776 * combined, not added together.
3777 */
3778 union {
3779 struct kvm_pit_state ps;
e9f42757 3780 struct kvm_pit_state2 ps2;
c5ff41ce 3781 struct kvm_pit_config pit_config;
f0d66275 3782 } u;
1fe779f8
CO		 3783
3784 switch (ioctl) {
3785 case KVM_SET_TSS_ADDR:
3786 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3787 break;
b927a3ce
SY		 3788 case KVM_SET_IDENTITY_MAP_ADDR: {
3789 u64 ident_addr;
3790
3791 r = -EFAULT;
3792 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3793 goto out;
3794 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3795 break;
3796 }
1fe779f8
CO		 3797 case KVM_SET_NR_MMU_PAGES:
3798 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3799 break;
3800 case KVM_GET_NR_MMU_PAGES:
3801 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3802 break;
3ddea128
MT		 3803 case KVM_CREATE_IRQCHIP: {
3804 struct kvm_pic *vpic;
3805
3806 mutex_lock(&kvm->lock);
3807 r = -EEXIST;
3808 if (kvm->arch.vpic)
3809 goto create_irqchip_unlock;
3e515705
AK		 3810 r = -EINVAL;
3811 if (atomic_read(&kvm->online_vcpus))
3812 goto create_irqchip_unlock;
1fe779f8 3813 r = -ENOMEM;
3ddea128
MT		 3814 vpic = kvm_create_pic(kvm);
3815 if (vpic) {
1fe779f8
CO		 3816 r = kvm_ioapic_init(kvm);
3817 if (r) {
175504cd 3818 mutex_lock(&kvm->slots_lock);
71ba994c 3819 kvm_destroy_pic(vpic);
175504cd 3820 mutex_unlock(&kvm->slots_lock);
3ddea128 3821 goto create_irqchip_unlock;
1fe779f8
CO		 3822 }
3823 } else
3ddea128 3824 goto create_irqchip_unlock;
399ec807
AK		 3825 r = kvm_setup_default_irq_routing(kvm);
3826 if (r) {
175504cd 3827 mutex_lock(&kvm->slots_lock);
3ddea128 3828 mutex_lock(&kvm->irq_lock);
72bb2fcd 3829 kvm_ioapic_destroy(kvm);
71ba994c 3830 kvm_destroy_pic(vpic);
3ddea128 3831 mutex_unlock(&kvm->irq_lock);
175504cd 3832 mutex_unlock(&kvm->slots_lock);
71ba994c 3833 goto create_irqchip_unlock;
399ec807 3834 }
71ba994c
PB		 3835 /* Write kvm->irq_routing before kvm->arch.vpic. */
3836 smp_wmb();
3837 kvm->arch.vpic = vpic;
3ddea128
MT		 3838 create_irqchip_unlock:
3839 mutex_unlock(&kvm->lock);
1fe779f8 3840 break;
3ddea128 3841 }
7837699f 3842 case KVM_CREATE_PIT:
c5ff41ce
JK		 3843 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3844 goto create_pit;
3845 case KVM_CREATE_PIT2:
3846 r = -EFAULT;
3847 if (copy_from_user(&u.pit_config, argp,
3848 sizeof(struct kvm_pit_config)))
3849 goto out;
3850 create_pit:
79fac95e 3851 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3852 r = -EEXIST;
3853 if (kvm->arch.vpit)
3854 goto create_pit_unlock;
7837699f 3855 r = -ENOMEM;
c5ff41ce 3856 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3857 if (kvm->arch.vpit)
3858 r = 0;
269e05e4 3859 create_pit_unlock:
79fac95e 3860 mutex_unlock(&kvm->slots_lock);
7837699f 3861 break;
1fe779f8
CO		 3862 case KVM_GET_IRQCHIP: {
3863 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3864 struct kvm_irqchip *chip;
1fe779f8 3865
ff5c2c03
SL		 3866 chip = memdup_user(argp, sizeof(*chip));
3867 if (IS_ERR(chip)) {
3868 r = PTR_ERR(chip);
1fe779f8 3869 goto out;
ff5c2c03
SL		 3870 }
3871
1fe779f8 3872 r = -ENXIO;
49df6397 3873 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3874 goto get_irqchip_out;
3875 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3876 if (r)
f0d66275 3877 goto get_irqchip_out;
1fe779f8 3878 r = -EFAULT;
f0d66275
DH		 3879 if (copy_to_user(argp, chip, sizeof *chip))
3880 goto get_irqchip_out;
1fe779f8 3881 r = 0;
f0d66275
DH		 3882 get_irqchip_out:
3883 kfree(chip);
1fe779f8
CO		 3884 break;
3885 }
3886 case KVM_SET_IRQCHIP: {
3887 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3888 struct kvm_irqchip *chip;
1fe779f8 3889
ff5c2c03
SL		 3890 chip = memdup_user(argp, sizeof(*chip));
3891 if (IS_ERR(chip)) {
3892 r = PTR_ERR(chip);
1fe779f8 3893 goto out;
ff5c2c03
SL		 3894 }
3895
1fe779f8 3896 r = -ENXIO;
49df6397 3897 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3898 goto set_irqchip_out;
3899 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3900 if (r)
f0d66275 3901 goto set_irqchip_out;
1fe779f8 3902 r = 0;
f0d66275
DH		 3903 set_irqchip_out:
3904 kfree(chip);
1fe779f8
CO		 3905 break;
3906 }
e0f63cb9 3907 case KVM_GET_PIT: {
e0f63cb9 3908 r = -EFAULT;
f0d66275 3909 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3910 goto out;
3911 r = -ENXIO;
3912 if (!kvm->arch.vpit)
3913 goto out;
f0d66275 3914 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3915 if (r)
3916 goto out;
3917 r = -EFAULT;
f0d66275 3918 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3919 goto out;
3920 r = 0;
3921 break;
3922 }
3923 case KVM_SET_PIT: {
e0f63cb9 3924 r = -EFAULT;
f0d66275 3925 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3926 goto out;
3927 r = -ENXIO;
3928 if (!kvm->arch.vpit)
3929 goto out;
f0d66275 3930 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3931 break;
3932 }
e9f42757
BK		 3933 case KVM_GET_PIT2: {
3934 r = -ENXIO;
3935 if (!kvm->arch.vpit)
3936 goto out;
3937 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3938 if (r)
3939 goto out;
3940 r = -EFAULT;
3941 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3942 goto out;
3943 r = 0;
3944 break;
3945 }
3946 case KVM_SET_PIT2: {
3947 r = -EFAULT;
3948 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3949 goto out;
3950 r = -ENXIO;
3951 if (!kvm->arch.vpit)
3952 goto out;
3953 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3954 break;
3955 }
52d939a0
MT		 3956 case KVM_REINJECT_CONTROL: {
3957 struct kvm_reinject_control control;
3958 r = -EFAULT;
3959 if (copy_from_user(&control, argp, sizeof(control)))
3960 goto out;
3961 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3962 break;
3963 }
d71ba788
PB		 3964 case KVM_SET_BOOT_CPU_ID:
3965 r = 0;
3966 mutex_lock(&kvm->lock);
3967 if (atomic_read(&kvm->online_vcpus) != 0)
3968 r = -EBUSY;
3969 else
3970 kvm->arch.bsp_vcpu_id = arg;
3971 mutex_unlock(&kvm->lock);
3972 break;
ffde22ac
ES		 3973 case KVM_XEN_HVM_CONFIG: {
3974 r = -EFAULT;
3975 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3976 sizeof(struct kvm_xen_hvm_config)))
3977 goto out;
3978 r = -EINVAL;
3979 if (kvm->arch.xen_hvm_config.flags)
3980 goto out;
3981 r = 0;
3982 break;
3983 }
afbcf7ab 3984 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3985 struct kvm_clock_data user_ns;
3986 u64 now_ns;
3987 s64 delta;
3988
3989 r = -EFAULT;
3990 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3991 goto out;
3992
3993 r = -EINVAL;
3994 if (user_ns.flags)
3995 goto out;
3996
3997 r = 0;
395c6b0a 3998 local_irq_disable();
759379dd 3999 now_ns = get_kernel_ns();
afbcf7ab 4000 delta = user_ns.clock - now_ns;
395c6b0a 4001 local_irq_enable();
afbcf7ab 4002 kvm->arch.kvmclock_offset = delta;
2e762ff7 4003 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4004 break;
4005 }
4006 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4007 struct kvm_clock_data user_ns;
4008 u64 now_ns;
4009
395c6b0a 4010 local_irq_disable();
759379dd 4011 now_ns = get_kernel_ns();
afbcf7ab 4012 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4013 local_irq_enable();
afbcf7ab 4014 user_ns.flags = 0;
97e69aa6 4015 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4016
4017 r = -EFAULT;
4018 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4019 goto out;
4020 r = 0;
4021 break;
4022 }
90de4a18
NA		 4023 case KVM_ENABLE_CAP: {
4024 struct kvm_enable_cap cap;
afbcf7ab 4025
90de4a18
NA		 4026 r = -EFAULT;
4027 if (copy_from_user(&cap, argp, sizeof(cap)))
4028 goto out;
4029 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4030 break;
4031 }
1fe779f8 4032 default:
c274e03a 4033 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4034 }
4035out:
4036 return r;
4037}
4038
a16b043c 4039static void kvm_init_msr_list(void)
043405e1
CO		 4040{
4041 u32 dummy[2];
4042 unsigned i, j;
4043
62ef68bb 4044 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4045 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4046 continue;
93c4adc7
PB		 4047
4048 /*
4049 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4050 * to the guests in some cases.
93c4adc7
PB		 4051 */
4052 switch (msrs_to_save[i]) {
4053 case MSR_IA32_BNDCFGS:
4054 if (!kvm_x86_ops->mpx_supported())
4055 continue;
4056 break;
9dbe6cf9
PB		 4057 case MSR_TSC_AUX:
4058 if (!kvm_x86_ops->rdtscp_supported())
4059 continue;
4060 break;
93c4adc7
PB		 4061 default:
4062 break;
4063 }
4064
043405e1
CO		 4065 if (j < i)
4066 msrs_to_save[j] = msrs_to_save[i];
4067 j++;
4068 }
4069 num_msrs_to_save = j;
62ef68bb
PB		 4070
4071 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4072 switch (emulated_msrs[i]) {
6d396b55
PB		 4073 case MSR_IA32_SMBASE:
4074 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4075 continue;
4076 break;
62ef68bb
PB		 4077 default:
4078 break;
4079 }
4080
4081 if (j < i)
4082 emulated_msrs[j] = emulated_msrs[i];
4083 j++;
4084 }
4085 num_emulated_msrs = j;
043405e1
CO		 4086}
4087
bda9020e
MT		 4088static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4089 const void *v)
bbd9b64e 4090{
70252a10
AK		 4091 int handled = 0;
4092 int n;
4093
4094 do {
4095 n = min(len, 8);
4096 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4097 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4098 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4099 break;
4100 handled += n;
4101 addr += n;
4102 len -= n;
4103 v += n;
4104 } while (len);
bbd9b64e 4105
70252a10 4106 return handled;
bbd9b64e
CO		 4107}
4108
bda9020e 4109static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4110{
70252a10
AK		 4111 int handled = 0;
4112 int n;
4113
4114 do {
4115 n = min(len, 8);
4116 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4117 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4118 addr, n, v))
4119 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4120 break;
4121 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4122 handled += n;
4123 addr += n;
4124 len -= n;
4125 v += n;
4126 } while (len);
bbd9b64e 4127
70252a10 4128 return handled;
bbd9b64e
CO		 4129}
4130
2dafc6c2
GN		 4131static void kvm_set_segment(struct kvm_vcpu *vcpu,
4132 struct kvm_segment *var, int seg)
4133{
4134 kvm_x86_ops->set_segment(vcpu, var, seg);
4135}
4136
4137void kvm_get_segment(struct kvm_vcpu *vcpu,
4138 struct kvm_segment *var, int seg)
4139{
4140 kvm_x86_ops->get_segment(vcpu, var, seg);
4141}
4142
54987b7a
PB		 4143gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4144 struct x86_exception *exception)
02f59dc9
JR		 4145{
4146 gpa_t t_gpa;
02f59dc9
JR		 4147
4148 BUG_ON(!mmu_is_nested(vcpu));
4149
4150 /* NPT walks are always user-walks */
4151 access |= PFERR_USER_MASK;
54987b7a 4152 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4153
4154 return t_gpa;
4155}
4156
ab9ae313
AK		 4157gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4158 struct x86_exception *exception)
1871c602
GN		 4159{
4160 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4161 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4162}
4163
ab9ae313
AK		 4164 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4165 struct x86_exception *exception)
1871c602
GN		 4166{
4167 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4168 access |= PFERR_FETCH_MASK;
ab9ae313 4169 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4170}
4171
ab9ae313
AK		 4172gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4173 struct x86_exception *exception)
1871c602
GN		 4174{
4175 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4176 access |= PFERR_WRITE_MASK;
ab9ae313 4177 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4178}
4179
4180/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4181gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4182 struct x86_exception *exception)
1871c602 4183{
ab9ae313 4184 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4185}
4186
4187static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4188 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4189 struct x86_exception *exception)
bbd9b64e
CO		 4190{
4191 void *data = val;
10589a46 4192 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4193
4194 while (bytes) {
14dfe855 4195 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4196 exception);
bbd9b64e 4197 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4198 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4199 int ret;
4200
bcc55cba 4201 if (gpa == UNMAPPED_GVA)
ab9ae313 4202 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4203 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4204 offset, toread);
10589a46 4205 if (ret < 0) {
c3cd7ffa 4206 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4207 goto out;
4208 }
bbd9b64e 4209
77c2002e
IE		 4210 bytes -= toread;
4211 data += toread;
4212 addr += toread;
bbd9b64e 4213 }
10589a46 4214out:
10589a46 4215 return r;
bbd9b64e 4216}
77c2002e 4217
1871c602 4218/* used for instruction fetching */
0f65dd70
AK		 4219static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4220 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4221 struct x86_exception *exception)
1871c602 4222{
0f65dd70 4223 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4224 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4225 unsigned offset;
4226 int ret;
0f65dd70 4227
44583cba
PB		 4228 /* Inline kvm_read_guest_virt_helper for speed. */
4229 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4230 exception);
4231 if (unlikely(gpa == UNMAPPED_GVA))
4232 return X86EMUL_PROPAGATE_FAULT;
4233
4234 offset = addr & (PAGE_SIZE-1);
4235 if (WARN_ON(offset + bytes > PAGE_SIZE))
4236 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4237 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4238 offset, bytes);
44583cba
PB		 4239 if (unlikely(ret < 0))
4240 return X86EMUL_IO_NEEDED;
4241
4242 return X86EMUL_CONTINUE;
1871c602
GN		 4243}
4244
064aea77 4245int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4246 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4247 struct x86_exception *exception)
1871c602 4248{
0f65dd70 4249 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4250 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4251
1871c602 4252 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4253 exception);
1871c602 4254}
064aea77 4255EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4256
0f65dd70
AK		 4257static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4258 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4259 struct x86_exception *exception)
1871c602 4260{
0f65dd70 4261 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4262 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4263}
4264
7a036a6f
RK		 4265static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4266 unsigned long addr, void *val, unsigned int bytes)
4267{
4268 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4269 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4270
4271 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4272}
4273
6a4d7550 4274int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4275 gva_t addr, void *val,
2dafc6c2 4276 unsigned int bytes,
bcc55cba 4277 struct x86_exception *exception)
77c2002e 4278{
0f65dd70 4279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4280 void *data = val;
4281 int r = X86EMUL_CONTINUE;
4282
4283 while (bytes) {
14dfe855
JR		 4284 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4285 PFERR_WRITE_MASK,
ab9ae313 4286 exception);
77c2002e
IE		 4287 unsigned offset = addr & (PAGE_SIZE-1);
4288 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4289 int ret;
4290
bcc55cba 4291 if (gpa == UNMAPPED_GVA)
ab9ae313 4292 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4293 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4294 if (ret < 0) {
c3cd7ffa 4295 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4296 goto out;
4297 }
4298
4299 bytes -= towrite;
4300 data += towrite;
4301 addr += towrite;
4302 }
4303out:
4304 return r;
4305}
6a4d7550 4306EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4307
af7cc7d1
XG		 4308static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4309 gpa_t *gpa, struct x86_exception *exception,
4310 bool write)
4311{
97d64b78
AK		 4312 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4313 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4314
97d64b78 4315 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4316 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4317 vcpu->arch.access, access)) {
bebb106a
XG		 4318 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4319 (gva & (PAGE_SIZE - 1));
4f022648 4320 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4321 return 1;
4322 }
4323
af7cc7d1
XG		 4324 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4325
4326 if (*gpa == UNMAPPED_GVA)
4327 return -1;
4328
4329 /* For APIC access vmexit */
4330 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4331 return 1;
4332
4f022648
XG		 4333 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4334 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4335 return 1;
4f022648 4336 }
bebb106a 4337
af7cc7d1
XG		 4338 return 0;
4339}
4340
3200f405 4341int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4342 const void *val, int bytes)
bbd9b64e
CO		 4343{
4344 int ret;
4345
54bf36aa 4346 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4347 if (ret < 0)
bbd9b64e 4348 return 0;
f57f2ef5 4349 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4350 return 1;
4351}
4352
77d197b2
XG		 4353struct read_write_emulator_ops {
4354 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4355 int bytes);
4356 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4357 void *val, int bytes);
4358 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4359 int bytes, void *val);
4360 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4361 void *val, int bytes);
4362 bool write;
4363};
4364
4365static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4366{
4367 if (vcpu->mmio_read_completed) {
77d197b2 4368 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4369 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4370 vcpu->mmio_read_completed = 0;
4371 return 1;
4372 }
4373
4374 return 0;
4375}
4376
4377static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4378 void *val, int bytes)
4379{
54bf36aa 4380 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4381}
4382
4383static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4384 void *val, int bytes)
4385{
4386 return emulator_write_phys(vcpu, gpa, val, bytes);
4387}
4388
4389static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4390{
4391 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4392 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4393}
4394
4395static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4396 void *val, int bytes)
4397{
4398 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4399 return X86EMUL_IO_NEEDED;
4400}
4401
4402static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4403 void *val, int bytes)
4404{
f78146b0
AK		 4405 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4406
87da7e66 4407 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4408 return X86EMUL_CONTINUE;
4409}
4410
0fbe9b0b 4411static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4412 .read_write_prepare = read_prepare,
4413 .read_write_emulate = read_emulate,
4414 .read_write_mmio = vcpu_mmio_read,
4415 .read_write_exit_mmio = read_exit_mmio,
4416};
4417
0fbe9b0b 4418static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4419 .read_write_emulate = write_emulate,
4420 .read_write_mmio = write_mmio,
4421 .read_write_exit_mmio = write_exit_mmio,
4422 .write = true,
4423};
4424
22388a3c
XG		 4425static int emulator_read_write_onepage(unsigned long addr, void *val,
4426 unsigned int bytes,
4427 struct x86_exception *exception,
4428 struct kvm_vcpu *vcpu,
0fbe9b0b 4429 const struct read_write_emulator_ops *ops)
bbd9b64e 4430{
af7cc7d1
XG		 4431 gpa_t gpa;
4432 int handled, ret;
22388a3c 4433 bool write = ops->write;
f78146b0 4434 struct kvm_mmio_fragment *frag;
10589a46 4435
22388a3c 4436 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4437
af7cc7d1 4438 if (ret < 0)
bbd9b64e 4439 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4440
4441 /* For APIC access vmexit */
af7cc7d1 4442 if (ret)
bbd9b64e
CO		 4443 goto mmio;
4444
22388a3c 4445 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4446 return X86EMUL_CONTINUE;
4447
4448mmio:
4449 /*
4450 * Is this MMIO handled locally?
4451 */
22388a3c 4452 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4453 if (handled == bytes)
bbd9b64e 4454 return X86EMUL_CONTINUE;
bbd9b64e 4455
70252a10
AK		 4456 gpa += handled;
4457 bytes -= handled;
4458 val += handled;
4459
87da7e66
XG		 4460 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4461 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4462 frag->gpa = gpa;
4463 frag->data = val;
4464 frag->len = bytes;
f78146b0 4465 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4466}
4467
52eb5a6d
XL		 4468static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4469 unsigned long addr,
22388a3c
XG		 4470 void *val, unsigned int bytes,
4471 struct x86_exception *exception,
0fbe9b0b 4472 const struct read_write_emulator_ops *ops)
bbd9b64e 4473{
0f65dd70 4474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4475 gpa_t gpa;
4476 int rc;
4477
4478 if (ops->read_write_prepare &&
4479 ops->read_write_prepare(vcpu, val, bytes))
4480 return X86EMUL_CONTINUE;
4481
4482 vcpu->mmio_nr_fragments = 0;
0f65dd70 4483
bbd9b64e
CO		 4484 /* Crossing a page boundary? */
4485 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4486 int now;
bbd9b64e
CO		 4487
4488 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4489 rc = emulator_read_write_onepage(addr, val, now, exception,
4490 vcpu, ops);
4491
bbd9b64e
CO		 4492 if (rc != X86EMUL_CONTINUE)
4493 return rc;
4494 addr += now;
bac15531
NA		 4495 if (ctxt->mode != X86EMUL_MODE_PROT64)
4496 addr = (u32)addr;
bbd9b64e
CO		 4497 val += now;
4498 bytes -= now;
4499 }
22388a3c 4500
f78146b0
AK		 4501 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4502 vcpu, ops);
4503 if (rc != X86EMUL_CONTINUE)
4504 return rc;
4505
4506 if (!vcpu->mmio_nr_fragments)
4507 return rc;
4508
4509 gpa = vcpu->mmio_fragments[0].gpa;
4510
4511 vcpu->mmio_needed = 1;
4512 vcpu->mmio_cur_fragment = 0;
4513
87da7e66 4514 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4515 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4516 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4517 vcpu->run->mmio.phys_addr = gpa;
4518
4519 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4520}
4521
4522static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4523 unsigned long addr,
4524 void *val,
4525 unsigned int bytes,
4526 struct x86_exception *exception)
4527{
4528 return emulator_read_write(ctxt, addr, val, bytes,
4529 exception, &read_emultor);
4530}
4531
52eb5a6d 4532static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4533 unsigned long addr,
4534 const void *val,
4535 unsigned int bytes,
4536 struct x86_exception *exception)
4537{
4538 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4539 exception, &write_emultor);
bbd9b64e 4540}
bbd9b64e 4541
daea3e73
AK		 4542#define CMPXCHG_TYPE(t, ptr, old, new) \
4543 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4544
4545#ifdef CONFIG_X86_64
4546# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4547#else
4548# define CMPXCHG64(ptr, old, new) \
9749a6c0 4549 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4550#endif
4551
0f65dd70
AK		 4552static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4553 unsigned long addr,
bbd9b64e
CO		 4554 const void *old,
4555 const void *new,
4556 unsigned int bytes,
0f65dd70 4557 struct x86_exception *exception)
bbd9b64e 4558{
0f65dd70 4559 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4560 gpa_t gpa;
4561 struct page *page;
4562 char *kaddr;
4563 bool exchanged;
2bacc55c 4564
daea3e73
AK		 4565 /* guests cmpxchg8b have to be emulated atomically */
4566 if (bytes > 8 || (bytes & (bytes - 1)))
4567 goto emul_write;
10589a46 4568
daea3e73 4569 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4570
daea3e73
AK		 4571 if (gpa == UNMAPPED_GVA ||
4572 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4573 goto emul_write;
2bacc55c 4574
daea3e73
AK		 4575 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4576 goto emul_write;
72dc67a6 4577
54bf36aa 4578 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4579 if (is_error_page(page))
c19b8bd6 4580 goto emul_write;
72dc67a6 4581
8fd75e12 4582 kaddr = kmap_atomic(page);
daea3e73
AK		 4583 kaddr += offset_in_page(gpa);
4584 switch (bytes) {
4585 case 1:
4586 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4587 break;
4588 case 2:
4589 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4590 break;
4591 case 4:
4592 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4593 break;
4594 case 8:
4595 exchanged = CMPXCHG64(kaddr, old, new);
4596 break;
4597 default:
4598 BUG();
2bacc55c 4599 }
8fd75e12 4600 kunmap_atomic(kaddr);
daea3e73
AK		 4601 kvm_release_page_dirty(page);
4602
4603 if (!exchanged)
4604 return X86EMUL_CMPXCHG_FAILED;
4605
54bf36aa 4606 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4607 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4608
4609 return X86EMUL_CONTINUE;
4a5f48f6 4610
3200f405 4611emul_write:
daea3e73 4612 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4613
0f65dd70 4614 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4615}
4616
cf8f70bf
GN		 4617static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4618{
4619 /* TODO: String I/O for in kernel device */
4620 int r;
4621
4622 if (vcpu->arch.pio.in)
e32edf4f 4623 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4624 vcpu->arch.pio.size, pd);
4625 else
e32edf4f 4626 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4627 vcpu->arch.pio.port, vcpu->arch.pio.size,
4628 pd);
4629 return r;
4630}
4631
6f6fbe98
XG		 4632static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4633 unsigned short port, void *val,
4634 unsigned int count, bool in)
cf8f70bf 4635{
cf8f70bf 4636 vcpu->arch.pio.port = port;
6f6fbe98 4637 vcpu->arch.pio.in = in;
7972995b 4638 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4639 vcpu->arch.pio.size = size;
4640
4641 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4642 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4643 return 1;
4644 }
4645
4646 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4647 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4648 vcpu->run->io.size = size;
4649 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4650 vcpu->run->io.count = count;
4651 vcpu->run->io.port = port;
4652
4653 return 0;
4654}
4655
6f6fbe98
XG		 4656static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4657 int size, unsigned short port, void *val,
4658 unsigned int count)
cf8f70bf 4659{
ca1d4a9e 4660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4661 int ret;
ca1d4a9e 4662
6f6fbe98
XG		 4663 if (vcpu->arch.pio.count)
4664 goto data_avail;
cf8f70bf 4665
6f6fbe98
XG		 4666 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4667 if (ret) {
4668data_avail:
4669 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4670 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4671 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4672 return 1;
4673 }
4674
cf8f70bf
GN		 4675 return 0;
4676}
4677
6f6fbe98
XG		 4678static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4679 int size, unsigned short port,
4680 const void *val, unsigned int count)
4681{
4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4683
4684 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4685 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4686 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4687}
4688
bbd9b64e
CO		 4689static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4690{
4691 return kvm_x86_ops->get_segment_base(vcpu, seg);
4692}
4693
3cb16fe7 4694static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4695{
3cb16fe7 4696 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4697}
4698
5cb56059 4699int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4700{
4701 if (!need_emulate_wbinvd(vcpu))
4702 return X86EMUL_CONTINUE;
4703
4704 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4705 int cpu = get_cpu();
4706
4707 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4708 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4709 wbinvd_ipi, NULL, 1);
2eec7343 4710 put_cpu();
f5f48ee1 4711 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4712 } else
4713 wbinvd();
f5f48ee1
SY		 4714 return X86EMUL_CONTINUE;
4715}
5cb56059
JS		 4716
4717int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4718{
4719 kvm_x86_ops->skip_emulated_instruction(vcpu);
4720 return kvm_emulate_wbinvd_noskip(vcpu);
4721}
f5f48ee1
SY		 4722EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4723
5cb56059
JS		 4724
4725
bcaf5cc5
AK		 4726static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4727{
5cb56059 4728 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4729}
4730
52eb5a6d
XL		 4731static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4732 unsigned long *dest)
bbd9b64e 4733{
16f8a6f9 4734 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4735}
4736
52eb5a6d
XL		 4737static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4738 unsigned long value)
bbd9b64e 4739{
338dbc97 4740
717746e3 4741 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4742}
4743
52a46617 4744static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4745{
52a46617 4746 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4747}
4748
717746e3 4749static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4750{
717746e3 4751 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4752 unsigned long value;
4753
4754 switch (cr) {
4755 case 0:
4756 value = kvm_read_cr0(vcpu);
4757 break;
4758 case 2:
4759 value = vcpu->arch.cr2;
4760 break;
4761 case 3:
9f8fe504 4762 value = kvm_read_cr3(vcpu);
52a46617
GN		 4763 break;
4764 case 4:
4765 value = kvm_read_cr4(vcpu);
4766 break;
4767 case 8:
4768 value = kvm_get_cr8(vcpu);
4769 break;
4770 default:
a737f256 4771 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4772 return 0;
4773 }
4774
4775 return value;
4776}
4777
717746e3 4778static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4779{
717746e3 4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4781 int res = 0;
4782
52a46617
GN		 4783 switch (cr) {
4784 case 0:
49a9b07e 4785 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4786 break;
4787 case 2:
4788 vcpu->arch.cr2 = val;
4789 break;
4790 case 3:
2390218b 4791 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4792 break;
4793 case 4:
a83b29c6 4794 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4795 break;
4796 case 8:
eea1cff9 4797 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4798 break;
4799 default:
a737f256 4800 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4801 res = -1;
52a46617 4802 }
0f12244f
GN		 4803
4804 return res;
52a46617
GN		 4805}
4806
717746e3 4807static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4808{
717746e3 4809 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4810}
4811
4bff1e86 4812static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4813{
4bff1e86 4814 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4815}
4816
4bff1e86 4817static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4818{
4bff1e86 4819 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4820}
4821
1ac9d0cf
AK		 4822static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4823{
4824 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4825}
4826
4827static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4828{
4829 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4830}
4831
4bff1e86
AK		 4832static unsigned long emulator_get_cached_segment_base(
4833 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4834{
4bff1e86 4835 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4836}
4837
1aa36616
AK		 4838static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4839 struct desc_struct *desc, u32 *base3,
4840 int seg)
2dafc6c2
GN		 4841{
4842 struct kvm_segment var;
4843
4bff1e86 4844 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4845 *selector = var.selector;
2dafc6c2 4846
378a8b09
GN		 4847 if (var.unusable) {
4848 memset(desc, 0, sizeof(*desc));
2dafc6c2 4849 return false;
378a8b09 4850 }
2dafc6c2
GN		 4851
4852 if (var.g)
4853 var.limit >>= 12;
4854 set_desc_limit(desc, var.limit);
4855 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4856#ifdef CONFIG_X86_64
4857 if (base3)
4858 *base3 = var.base >> 32;
4859#endif
2dafc6c2
GN		 4860 desc->type = var.type;
4861 desc->s = var.s;
4862 desc->dpl = var.dpl;
4863 desc->p = var.present;
4864 desc->avl = var.avl;
4865 desc->l = var.l;
4866 desc->d = var.db;
4867 desc->g = var.g;
4868
4869 return true;
4870}
4871
1aa36616
AK		 4872static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4873 struct desc_struct *desc, u32 base3,
4874 int seg)
2dafc6c2 4875{
4bff1e86 4876 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4877 struct kvm_segment var;
4878
1aa36616 4879 var.selector = selector;
2dafc6c2 4880 var.base = get_desc_base(desc);
5601d05b
GN		 4881#ifdef CONFIG_X86_64
4882 var.base |= ((u64)base3) << 32;
4883#endif
2dafc6c2
GN		 4884 var.limit = get_desc_limit(desc);
4885 if (desc->g)
4886 var.limit = (var.limit << 12) | 0xfff;
4887 var.type = desc->type;
2dafc6c2
GN		 4888 var.dpl = desc->dpl;
4889 var.db = desc->d;
4890 var.s = desc->s;
4891 var.l = desc->l;
4892 var.g = desc->g;
4893 var.avl = desc->avl;
4894 var.present = desc->p;
4895 var.unusable = !var.present;
4896 var.padding = 0;
4897
4898 kvm_set_segment(vcpu, &var, seg);
4899 return;
4900}
4901
717746e3
AK		 4902static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4903 u32 msr_index, u64 *pdata)
4904{
609e36d3
PB		 4905 struct msr_data msr;
4906 int r;
4907
4908 msr.index = msr_index;
4909 msr.host_initiated = false;
4910 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4911 if (r)
4912 return r;
4913
4914 *pdata = msr.data;
4915 return 0;
717746e3
AK		 4916}
4917
4918static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4919 u32 msr_index, u64 data)
4920{
8fe8ab46
WA		 4921 struct msr_data msr;
4922
4923 msr.data = data;
4924 msr.index = msr_index;
4925 msr.host_initiated = false;
4926 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4927}
4928
64d60670
PB		 4929static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4930{
4931 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4932
4933 return vcpu->arch.smbase;
4934}
4935
4936static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4937{
4938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4939
4940 vcpu->arch.smbase = smbase;
4941}
4942
67f4d428
NA		 4943static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4944 u32 pmc)
4945{
c6702c9d 4946 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4947}
4948
222d21aa
AK		 4949static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4950 u32 pmc, u64 *pdata)
4951{
c6702c9d 4952 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4953}
4954
6c3287f7
AK		 4955static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4956{
4957 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4958}
4959
5037f6f3
AK		 4960static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4961{
4962 preempt_disable();
5197b808 4963 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4964 /*
4965 * CR0.TS may reference the host fpu state, not the guest fpu state,
4966 * so it may be clear at this point.
4967 */
4968 clts();
4969}
4970
4971static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4972{
4973 preempt_enable();
4974}
4975
2953538e 4976static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4977 struct x86_instruction_info *info,
c4f035c6
AK		 4978 enum x86_intercept_stage stage)
4979{
2953538e 4980 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4981}
4982
0017f93a 4983static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4984 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4985{
0017f93a 4986 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4987}
4988
dd856efa
AK		 4989static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4990{
4991 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4992}
4993
4994static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4995{
4996 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4997}
4998
801806d9
NA		 4999static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5000{
5001 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5002}
5003
0225fb50 5004static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5005 .read_gpr = emulator_read_gpr,
5006 .write_gpr = emulator_write_gpr,
1871c602 5007 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5008 .write_std = kvm_write_guest_virt_system,
7a036a6f 5009 .read_phys = kvm_read_guest_phys_system,
1871c602 5010 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5011 .read_emulated = emulator_read_emulated,
5012 .write_emulated = emulator_write_emulated,
5013 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5014 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5015 .pio_in_emulated = emulator_pio_in_emulated,
5016 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5017 .get_segment = emulator_get_segment,
5018 .set_segment = emulator_set_segment,
5951c442 5019 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5020 .get_gdt = emulator_get_gdt,
160ce1f1 5021 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5022 .set_gdt = emulator_set_gdt,
5023 .set_idt = emulator_set_idt,
52a46617
GN		 5024 .get_cr = emulator_get_cr,
5025 .set_cr = emulator_set_cr,
9c537244 5026 .cpl = emulator_get_cpl,
35aa5375
GN		 5027 .get_dr = emulator_get_dr,
5028 .set_dr = emulator_set_dr,
64d60670
PB		 5029 .get_smbase = emulator_get_smbase,
5030 .set_smbase = emulator_set_smbase,
717746e3
AK		 5031 .set_msr = emulator_set_msr,
5032 .get_msr = emulator_get_msr,
67f4d428 5033 .check_pmc = emulator_check_pmc,
222d21aa 5034 .read_pmc = emulator_read_pmc,
6c3287f7 5035 .halt = emulator_halt,
bcaf5cc5 5036 .wbinvd = emulator_wbinvd,
d6aa1000 5037 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5038 .get_fpu = emulator_get_fpu,
5039 .put_fpu = emulator_put_fpu,
c4f035c6 5040 .intercept = emulator_intercept,
bdb42f5a 5041 .get_cpuid = emulator_get_cpuid,
801806d9 5042 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5043};
5044
95cb2295
GN		 5045static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5046{
37ccdcbe 5047 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5048 /*
5049 * an sti; sti; sequence only disable interrupts for the first
5050 * instruction. So, if the last instruction, be it emulated or
5051 * not, left the system with the INT_STI flag enabled, it
5052 * means that the last instruction is an sti. We should not
5053 * leave the flag on in this case. The same goes for mov ss
5054 */
37ccdcbe
PB		 5055 if (int_shadow & mask)
5056 mask = 0;
6addfc42 5057 if (unlikely(int_shadow || mask)) {
95cb2295 5058 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5059 if (!mask)
5060 kvm_make_request(KVM_REQ_EVENT, vcpu);
5061 }
95cb2295
GN		 5062}
5063
ef54bcfe 5064static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5065{
5066 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5067 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5068 return kvm_propagate_fault(vcpu, &ctxt->exception);
5069
5070 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5071 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5072 ctxt->exception.error_code);
54b8486f 5073 else
da9cb575 5074 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5075 return false;
54b8486f
GN		 5076}
5077
8ec4722d
MG		 5078static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5079{
adf52235 5080 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5081 int cs_db, cs_l;
5082
8ec4722d
MG		 5083 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5084
adf52235
TY		 5085 ctxt->eflags = kvm_get_rflags(vcpu);
5086 ctxt->eip = kvm_rip_read(vcpu);
5087 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5088 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5089 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5090 cs_db ? X86EMUL_MODE_PROT32 :
5091 X86EMUL_MODE_PROT16;
a584539b 5092 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5093 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5094 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5095 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5096
dd856efa 5097 init_decode_cache(ctxt);
7ae441ea 5098 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5099}
5100
71f9833b 5101int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5102{
9d74191a 5103 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5104 int ret;
5105
5106 init_emulate_ctxt(vcpu);
5107
9dac77fa
AK		 5108 ctxt->op_bytes = 2;
5109 ctxt->ad_bytes = 2;
5110 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5111 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5112
5113 if (ret != X86EMUL_CONTINUE)
5114 return EMULATE_FAIL;
5115
9dac77fa 5116 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5117 kvm_rip_write(vcpu, ctxt->eip);
5118 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5119
5120 if (irq == NMI_VECTOR)
7460fb4a 5121 vcpu->arch.nmi_pending = 0;
63995653
MG		 5122 else
5123 vcpu->arch.interrupt.pending = false;
5124
5125 return EMULATE_DONE;
5126}
5127EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5128
6d77dbfc
GN		 5129static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5130{
fc3a9157
JR		 5131 int r = EMULATE_DONE;
5132
6d77dbfc
GN		 5133 ++vcpu->stat.insn_emulation_fail;
5134 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5135 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5136 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5137 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5138 vcpu->run->internal.ndata = 0;
5139 r = EMULATE_FAIL;
5140 }
6d77dbfc 5141 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5142
5143 return r;
6d77dbfc
GN		 5144}
5145
93c05d3e 5146static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5147 bool write_fault_to_shadow_pgtable,
5148 int emulation_type)
a6f177ef 5149{
95b3cf69 5150 gpa_t gpa = cr2;
8e3d9d06 5151 pfn_t pfn;
a6f177ef 5152
991eebf9
GN		 5153 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5154 return false;
5155
95b3cf69
XG		 5156 if (!vcpu->arch.mmu.direct_map) {
5157 /*
5158 * Write permission should be allowed since only
5159 * write access need to be emulated.
5160 */
5161 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5162
95b3cf69
XG		 5163 /*
5164 * If the mapping is invalid in guest, let cpu retry
5165 * it to generate fault.
5166 */
5167 if (gpa == UNMAPPED_GVA)
5168 return true;
5169 }
a6f177ef 5170
8e3d9d06
XG		 5171 /*
5172 * Do not retry the unhandleable instruction if it faults on the
5173 * readonly host memory, otherwise it will goto a infinite loop:
5174 * retry instruction -> write #PF -> emulation fail -> retry
5175 * instruction -> ...
5176 */
5177 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5178
5179 /*
5180 * If the instruction failed on the error pfn, it can not be fixed,
5181 * report the error to userspace.
5182 */
5183 if (is_error_noslot_pfn(pfn))
5184 return false;
5185
5186 kvm_release_pfn_clean(pfn);
5187
5188 /* The instructions are well-emulated on direct mmu. */
5189 if (vcpu->arch.mmu.direct_map) {
5190 unsigned int indirect_shadow_pages;
5191
5192 spin_lock(&vcpu->kvm->mmu_lock);
5193 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5194 spin_unlock(&vcpu->kvm->mmu_lock);
5195
5196 if (indirect_shadow_pages)
5197 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5198
a6f177ef 5199 return true;
8e3d9d06 5200 }
a6f177ef 5201
95b3cf69
XG		 5202 /*
5203 * if emulation was due to access to shadowed page table
5204 * and it failed try to unshadow page and re-enter the
5205 * guest to let CPU execute the instruction.
5206 */
5207 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5208
5209 /*
5210 * If the access faults on its page table, it can not
5211 * be fixed by unprotecting shadow page and it should
5212 * be reported to userspace.
5213 */
5214 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5215}
5216
1cb3f3ae
XG		 5217static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5218 unsigned long cr2, int emulation_type)
5219{
5220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5221 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5222
5223 last_retry_eip = vcpu->arch.last_retry_eip;
5224 last_retry_addr = vcpu->arch.last_retry_addr;
5225
5226 /*
5227 * If the emulation is caused by #PF and it is non-page_table
5228 * writing instruction, it means the VM-EXIT is caused by shadow
5229 * page protected, we can zap the shadow page and retry this
5230 * instruction directly.
5231 *
5232 * Note: if the guest uses a non-page-table modifying instruction
5233 * on the PDE that points to the instruction, then we will unmap
5234 * the instruction and go to an infinite loop. So, we cache the
5235 * last retried eip and the last fault address, if we meet the eip
5236 * and the address again, we can break out of the potential infinite
5237 * loop.
5238 */
5239 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5240
5241 if (!(emulation_type & EMULTYPE_RETRY))
5242 return false;
5243
5244 if (x86_page_table_writing_insn(ctxt))
5245 return false;
5246
5247 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5248 return false;
5249
5250 vcpu->arch.last_retry_eip = ctxt->eip;
5251 vcpu->arch.last_retry_addr = cr2;
5252
5253 if (!vcpu->arch.mmu.direct_map)
5254 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5255
22368028 5256 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5257
5258 return true;
5259}
5260
716d51ab
GN		 5261static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5262static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5263
64d60670 5264static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5265{
64d60670 5266 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5267 /* This is a good place to trace that we are exiting SMM. */
5268 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5269
64d60670
PB		 5270 if (unlikely(vcpu->arch.smi_pending)) {
5271 kvm_make_request(KVM_REQ_SMI, vcpu);
5272 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5273 } else {
5274 /* Process a latched INIT, if any. */
5275 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5276 }
5277 }
699023e2
PB		 5278
5279 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5280}
5281
5282static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5283{
5284 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5285
a584539b 5286 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5287
5288 if (changed & HF_SMM_MASK)
5289 kvm_smm_changed(vcpu);
a584539b
PB		 5290}
5291
4a1e10d5
PB		 5292static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5293 unsigned long *db)
5294{
5295 u32 dr6 = 0;
5296 int i;
5297 u32 enable, rwlen;
5298
5299 enable = dr7;
5300 rwlen = dr7 >> 16;
5301 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5302 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5303 dr6 |= (1 << i);
5304 return dr6;
5305}
5306
6addfc42 5307static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5308{
5309 struct kvm_run *kvm_run = vcpu->run;
5310
5311 /*
6addfc42
PB		 5312 * rflags is the old, "raw" value of the flags. The new value has
5313 * not been saved yet.
663f4c61
PB		 5314 *
5315 * This is correct even for TF set by the guest, because "the
5316 * processor will not generate this exception after the instruction
5317 * that sets the TF flag".
5318 */
663f4c61
PB		 5319 if (unlikely(rflags & X86_EFLAGS_TF)) {
5320 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5321 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5322 DR6_RTM;
663f4c61
PB		 5323 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5324 kvm_run->debug.arch.exception = DB_VECTOR;
5325 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5326 *r = EMULATE_USER_EXIT;
5327 } else {
5328 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5329 /*
5330 * "Certain debug exceptions may clear bit 0-3. The
5331 * remaining contents of the DR6 register are never
5332 * cleared by the processor".
5333 */
5334 vcpu->arch.dr6 &= ~15;
6f43ed01 5335 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5336 kvm_queue_exception(vcpu, DB_VECTOR);
5337 }
5338 }
5339}
5340
4a1e10d5
PB		 5341static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5342{
4a1e10d5
PB		 5343 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5344 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5345 struct kvm_run *kvm_run = vcpu->run;
5346 unsigned long eip = kvm_get_linear_rip(vcpu);
5347 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5348 vcpu->arch.guest_debug_dr7,
5349 vcpu->arch.eff_db);
5350
5351 if (dr6 != 0) {
6f43ed01 5352 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5353 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5354 kvm_run->debug.arch.exception = DB_VECTOR;
5355 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5356 *r = EMULATE_USER_EXIT;
5357 return true;
5358 }
5359 }
5360
4161a569
NA		 5361 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5362 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5363 unsigned long eip = kvm_get_linear_rip(vcpu);
5364 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5365 vcpu->arch.dr7,
5366 vcpu->arch.db);
5367
5368 if (dr6 != 0) {
5369 vcpu->arch.dr6 &= ~15;
6f43ed01 5370 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5371 kvm_queue_exception(vcpu, DB_VECTOR);
5372 *r = EMULATE_DONE;
5373 return true;
5374 }
5375 }
5376
5377 return false;
5378}
5379
51d8b661
AP		 5380int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5381 unsigned long cr2,
dc25e89e
AP		 5382 int emulation_type,
5383 void *insn,
5384 int insn_len)
bbd9b64e 5385{
95cb2295 5386 int r;
9d74191a 5387 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5388 bool writeback = true;
93c05d3e 5389 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5390
93c05d3e
XG		 5391 /*
5392 * Clear write_fault_to_shadow_pgtable here to ensure it is
5393 * never reused.
5394 */
5395 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5396 kvm_clear_exception_queue(vcpu);
8d7d8102 5397
571008da 5398 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5399 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5400
5401 /*
5402 * We will reenter on the same instruction since
5403 * we do not set complete_userspace_io. This does not
5404 * handle watchpoints yet, those would be handled in
5405 * the emulate_ops.
5406 */
5407 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5408 return r;
5409
9d74191a
TY		 5410 ctxt->interruptibility = 0;
5411 ctxt->have_exception = false;
e0ad0b47 5412 ctxt->exception.vector = -1;
9d74191a 5413 ctxt->perm_ok = false;
bbd9b64e 5414
b51e974f 5415 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5416
9d74191a 5417 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5418
e46479f8 5419 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5420 ++vcpu->stat.insn_emulation;
1d2887e2 5421 if (r != EMULATION_OK) {
4005996e
AK		 5422 if (emulation_type & EMULTYPE_TRAP_UD)
5423 return EMULATE_FAIL;
991eebf9
GN		 5424 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5425 emulation_type))
bbd9b64e 5426 return EMULATE_DONE;
6d77dbfc
GN		 5427 if (emulation_type & EMULTYPE_SKIP)
5428 return EMULATE_FAIL;
5429 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5430 }
5431 }
5432
ba8afb6b 5433 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5434 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5435 if (ctxt->eflags & X86_EFLAGS_RF)
5436 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5437 return EMULATE_DONE;
5438 }
5439
1cb3f3ae
XG		 5440 if (retry_instruction(ctxt, cr2, emulation_type))
5441 return EMULATE_DONE;
5442
7ae441ea 5443 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5444 changes registers values during IO operation */
7ae441ea
GN		 5445 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5446 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5447 emulator_invalidate_register_cache(ctxt);
7ae441ea 5448 }
4d2179e1 5449
5cd21917 5450restart:
9d74191a 5451 r = x86_emulate_insn(ctxt);
bbd9b64e 5452
775fde86
JR		 5453 if (r == EMULATION_INTERCEPTED)
5454 return EMULATE_DONE;
5455
d2ddd1c4 5456 if (r == EMULATION_FAILED) {
991eebf9
GN		 5457 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5458 emulation_type))
c3cd7ffa
GN		 5459 return EMULATE_DONE;
5460
6d77dbfc 5461 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5462 }
5463
9d74191a 5464 if (ctxt->have_exception) {
d2ddd1c4 5465 r = EMULATE_DONE;
ef54bcfe
PB		 5466 if (inject_emulated_exception(vcpu))
5467 return r;
d2ddd1c4 5468 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5469 if (!vcpu->arch.pio.in) {
5470 /* FIXME: return into emulator if single-stepping. */
3457e419 5471 vcpu->arch.pio.count = 0;
0912c977 5472 } else {
7ae441ea 5473 writeback = false;
716d51ab
GN		 5474 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5475 }
ac0a48c3 5476 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5477 } else if (vcpu->mmio_needed) {
5478 if (!vcpu->mmio_is_write)
5479 writeback = false;
ac0a48c3 5480 r = EMULATE_USER_EXIT;
716d51ab 5481 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5482 } else if (r == EMULATION_RESTART)
5cd21917 5483 goto restart;
d2ddd1c4
GN		 5484 else
5485 r = EMULATE_DONE;
f850e2e6 5486
7ae441ea 5487 if (writeback) {
6addfc42 5488 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5489 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5490 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5491 if (vcpu->arch.hflags != ctxt->emul_flags)
5492 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5493 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5494 if (r == EMULATE_DONE)
6addfc42 5495 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5496 if (!ctxt->have_exception ||
5497 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5498 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5499
5500 /*
5501 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5502 * do nothing, and it will be requested again as soon as
5503 * the shadow expires. But we still need to check here,
5504 * because POPF has no interrupt shadow.
5505 */
5506 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5507 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5508 } else
5509 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5510
5511 return r;
de7d789a 5512}
51d8b661 5513EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5514
cf8f70bf 5515int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5516{
cf8f70bf 5517 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5518 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5519 size, port, &val, 1);
cf8f70bf 5520 /* do not return to emulator after return from userspace */
7972995b 5521 vcpu->arch.pio.count = 0;
de7d789a
CO		 5522 return ret;
5523}
cf8f70bf 5524EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5525
8cfdc000
ZA		 5526static void tsc_bad(void *info)
5527{
0a3aee0d 5528 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5529}
5530
5531static void tsc_khz_changed(void *data)
c8076604 5532{
8cfdc000
ZA		 5533 struct cpufreq_freqs *freq = data;
5534 unsigned long khz = 0;
5535
5536 if (data)
5537 khz = freq->new;
5538 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5539 khz = cpufreq_quick_get(raw_smp_processor_id());
5540 if (!khz)
5541 khz = tsc_khz;
0a3aee0d 5542 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5543}
5544
c8076604
GH		 5545static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5546 void *data)
5547{
5548 struct cpufreq_freqs *freq = data;
5549 struct kvm *kvm;
5550 struct kvm_vcpu *vcpu;
5551 int i, send_ipi = 0;
5552
8cfdc000
ZA		 5553 /*
5554 * We allow guests to temporarily run on slowing clocks,
5555 * provided we notify them after, or to run on accelerating
5556 * clocks, provided we notify them before. Thus time never
5557 * goes backwards.
5558 *
5559 * However, we have a problem. We can't atomically update
5560 * the frequency of a given CPU from this function; it is
5561 * merely a notifier, which can be called from any CPU.
5562 * Changing the TSC frequency at arbitrary points in time
5563 * requires a recomputation of local variables related to
5564 * the TSC for each VCPU. We must flag these local variables
5565 * to be updated and be sure the update takes place with the
5566 * new frequency before any guests proceed.
5567 *
5568 * Unfortunately, the combination of hotplug CPU and frequency
5569 * change creates an intractable locking scenario; the order
5570 * of when these callouts happen is undefined with respect to
5571 * CPU hotplug, and they can race with each other. As such,
5572 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5573 * undefined; you can actually have a CPU frequency change take
5574 * place in between the computation of X and the setting of the
5575 * variable. To protect against this problem, all updates of
5576 * the per_cpu tsc_khz variable are done in an interrupt
5577 * protected IPI, and all callers wishing to update the value
5578 * must wait for a synchronous IPI to complete (which is trivial
5579 * if the caller is on the CPU already). This establishes the
5580 * necessary total order on variable updates.
5581 *
5582 * Note that because a guest time update may take place
5583 * anytime after the setting of the VCPU's request bit, the
5584 * correct TSC value must be set before the request. However,
5585 * to ensure the update actually makes it to any guest which
5586 * starts running in hardware virtualization between the set
5587 * and the acquisition of the spinlock, we must also ping the
5588 * CPU after setting the request bit.
5589 *
5590 */
5591
c8076604
GH		 5592 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5593 return 0;
5594 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5595 return 0;
8cfdc000
ZA		 5596
5597 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5598
2f303b74 5599 spin_lock(&kvm_lock);
c8076604 5600 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5601 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5602 if (vcpu->cpu != freq->cpu)
5603 continue;
c285545f 5604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5605 if (vcpu->cpu != smp_processor_id())
8cfdc000 5606 send_ipi = 1;
c8076604
GH		 5607 }
5608 }
2f303b74 5609 spin_unlock(&kvm_lock);
c8076604
GH		 5610
5611 if (freq->old < freq->new && send_ipi) {
5612 /*
5613 * We upscale the frequency. Must make the guest
5614 * doesn't see old kvmclock values while running with
5615 * the new frequency, otherwise we risk the guest sees
5616 * time go backwards.
5617 *
5618 * In case we update the frequency for another cpu
5619 * (which might be in guest context) send an interrupt
5620 * to kick the cpu out of guest context. Next time
5621 * guest context is entered kvmclock will be updated,
5622 * so the guest will not see stale values.
5623 */
8cfdc000 5624 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5625 }
5626 return 0;
5627}
5628
5629static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5630 .notifier_call = kvmclock_cpufreq_notifier
5631};
5632
5633static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5634 unsigned long action, void *hcpu)
5635{
5636 unsigned int cpu = (unsigned long)hcpu;
5637
5638 switch (action) {
5639 case CPU_ONLINE:
5640 case CPU_DOWN_FAILED:
5641 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5642 break;
5643 case CPU_DOWN_PREPARE:
5644 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5645 break;
5646 }
5647 return NOTIFY_OK;
5648}
5649
5650static struct notifier_block kvmclock_cpu_notifier_block = {
5651 .notifier_call = kvmclock_cpu_notifier,
5652 .priority = -INT_MAX
c8076604
GH		 5653};
5654
b820cc0c
ZA		 5655static void kvm_timer_init(void)
5656{
5657 int cpu;
5658
c285545f 5659 max_tsc_khz = tsc_khz;
460dd42e
SB		 5660
5661 cpu_notifier_register_begin();
b820cc0c 5662 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5663#ifdef CONFIG_CPU_FREQ
5664 struct cpufreq_policy policy;
5665 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5666 cpu = get_cpu();
5667 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5668 if (policy.cpuinfo.max_freq)
5669 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5670 put_cpu();
c285545f 5671#endif
b820cc0c
ZA		 5672 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5673 CPUFREQ_TRANSITION_NOTIFIER);
5674 }
c285545f 5675 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5676 for_each_online_cpu(cpu)
5677 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5678
5679 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5680 cpu_notifier_register_done();
5681
b820cc0c
ZA		 5682}
5683
ff9d07a0
ZY		 5684static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5685
f5132b01 5686int kvm_is_in_guest(void)
ff9d07a0 5687{
086c9855 5688 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5689}
5690
5691static int kvm_is_user_mode(void)
5692{
5693 int user_mode = 3;
dcf46b94 5694
086c9855
AS		 5695 if (__this_cpu_read(current_vcpu))
5696 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5697
ff9d07a0
ZY		 5698 return user_mode != 0;
5699}
5700
5701static unsigned long kvm_get_guest_ip(void)
5702{
5703 unsigned long ip = 0;
dcf46b94 5704
086c9855
AS		 5705 if (__this_cpu_read(current_vcpu))
5706 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5707
ff9d07a0
ZY		 5708 return ip;
5709}
5710
5711static struct perf_guest_info_callbacks kvm_guest_cbs = {
5712 .is_in_guest = kvm_is_in_guest,
5713 .is_user_mode = kvm_is_user_mode,
5714 .get_guest_ip = kvm_get_guest_ip,
5715};
5716
5717void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5718{
086c9855 5719 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5720}
5721EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5722
5723void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5724{
086c9855 5725 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5726}
5727EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5728
ce88decf
XG		 5729static void kvm_set_mmio_spte_mask(void)
5730{
5731 u64 mask;
5732 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5733
5734 /*
5735 * Set the reserved bits and the present bit of an paging-structure
5736 * entry to generate page fault with PFER.RSV = 1.
5737 */
885032b9 5738 /* Mask the reserved physical address bits. */
d1431483 5739 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5740
5741 /* Bit 62 is always reserved for 32bit host. */
5742 mask |= 0x3ull << 62;
5743
5744 /* Set the present bit. */
ce88decf
XG		 5745 mask |= 1ull;
5746
5747#ifdef CONFIG_X86_64
5748 /*
5749 * If reserved bit is not supported, clear the present bit to disable
5750 * mmio page fault.
5751 */
5752 if (maxphyaddr == 52)
5753 mask &= ~1ull;
5754#endif
5755
5756 kvm_mmu_set_mmio_spte_mask(mask);
5757}
5758
16e8d74d
MT		 5759#ifdef CONFIG_X86_64
5760static void pvclock_gtod_update_fn(struct work_struct *work)
5761{
d828199e
MT		 5762 struct kvm *kvm;
5763
5764 struct kvm_vcpu *vcpu;
5765 int i;
5766
2f303b74 5767 spin_lock(&kvm_lock);
d828199e
MT		 5768 list_for_each_entry(kvm, &vm_list, vm_list)
5769 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5770 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5771 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5772 spin_unlock(&kvm_lock);
16e8d74d
MT		 5773}
5774
5775static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5776
5777/*
5778 * Notification about pvclock gtod data update.
5779 */
5780static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5781 void *priv)
5782{
5783 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5784 struct timekeeper *tk = priv;
5785
5786 update_pvclock_gtod(tk);
5787
5788 /* disable master clock if host does not trust, or does not
5789 * use, TSC clocksource
5790 */
5791 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5792 atomic_read(&kvm_guest_has_master_clock) != 0)
5793 queue_work(system_long_wq, &pvclock_gtod_work);
5794
5795 return 0;
5796}
5797
5798static struct notifier_block pvclock_gtod_notifier = {
5799 .notifier_call = pvclock_gtod_notify,
5800};
5801#endif
5802
f8c16bba 5803int kvm_arch_init(void *opaque)
043405e1 5804{
b820cc0c 5805 int r;
6b61edf7 5806 struct kvm_x86_ops *ops = opaque;
f8c16bba 5807
f8c16bba
ZX		 5808 if (kvm_x86_ops) {
5809 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5810 r = -EEXIST;
5811 goto out;
f8c16bba
ZX		 5812 }
5813
5814 if (!ops->cpu_has_kvm_support()) {
5815 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5816 r = -EOPNOTSUPP;
5817 goto out;
f8c16bba
ZX		 5818 }
5819 if (ops->disabled_by_bios()) {
5820 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5821 r = -EOPNOTSUPP;
5822 goto out;
f8c16bba
ZX		 5823 }
5824
013f6a5d
MT		 5825 r = -ENOMEM;
5826 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5827 if (!shared_msrs) {
5828 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5829 goto out;
5830 }
5831
97db56ce
AK		 5832 r = kvm_mmu_module_init();
5833 if (r)
013f6a5d 5834 goto out_free_percpu;
97db56ce 5835
ce88decf 5836 kvm_set_mmio_spte_mask();
97db56ce 5837
f8c16bba 5838 kvm_x86_ops = ops;
920c8377 5839
7b52345e 5840 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5841 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5842
b820cc0c 5843 kvm_timer_init();
c8076604 5844
ff9d07a0
ZY		 5845 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5846
2acf923e
DC		 5847 if (cpu_has_xsave)
5848 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5849
c5cc421b 5850 kvm_lapic_init();
16e8d74d
MT		 5851#ifdef CONFIG_X86_64
5852 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5853#endif
5854
f8c16bba 5855 return 0;
56c6d28a 5856
013f6a5d
MT		 5857out_free_percpu:
5858 free_percpu(shared_msrs);
56c6d28a 5859out:
56c6d28a 5860 return r;
043405e1 5861}
8776e519 5862
f8c16bba
ZX		 5863void kvm_arch_exit(void)
5864{
ff9d07a0
ZY		 5865 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5866
888d256e
JK		 5867 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5868 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5869 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5870 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5871#ifdef CONFIG_X86_64
5872 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5873#endif
f8c16bba 5874 kvm_x86_ops = NULL;
56c6d28a 5875 kvm_mmu_module_exit();
013f6a5d 5876 free_percpu(shared_msrs);
56c6d28a 5877}
f8c16bba 5878
5cb56059 5879int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5880{
5881 ++vcpu->stat.halt_exits;
35754c98 5882 if (lapic_in_kernel(vcpu)) {
a4535290 5883 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5884 return 1;
5885 } else {
5886 vcpu->run->exit_reason = KVM_EXIT_HLT;
5887 return 0;
5888 }
5889}
5cb56059
JS		 5890EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5891
5892int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5893{
5894 kvm_x86_ops->skip_emulated_instruction(vcpu);
5895 return kvm_vcpu_halt(vcpu);
5896}
8776e519
HB		 5897EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5898
6aef266c
SV		 5899/*
5900 * kvm_pv_kick_cpu_op: Kick a vcpu.
5901 *
5902 * @apicid - apicid of vcpu to be kicked.
5903 */
5904static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5905{
24d2166b 5906 struct kvm_lapic_irq lapic_irq;
6aef266c 5907
24d2166b
R		 5908 lapic_irq.shorthand = 0;
5909 lapic_irq.dest_mode = 0;
5910 lapic_irq.dest_id = apicid;
93bbf0b8 5911 lapic_irq.msi_redir_hint = false;
6aef266c 5912
24d2166b 5913 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5914 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5915}
5916
d62caabb
AS		 5917void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5918{
5919 vcpu->arch.apicv_active = false;
5920 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5921}
5922
8776e519
HB		 5923int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5924{
5925 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5926 int op_64_bit, r = 1;
8776e519 5927
5cb56059
JS		 5928 kvm_x86_ops->skip_emulated_instruction(vcpu);
5929
55cd8e5a
GN		 5930 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5931 return kvm_hv_hypercall(vcpu);
5932
5fdbf976
MT		 5933 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5934 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5935 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5936 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5937 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5938
229456fc 5939 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5940
a449c7aa
NA		 5941 op_64_bit = is_64_bit_mode(vcpu);
5942 if (!op_64_bit) {
8776e519
HB		 5943 nr &= 0xFFFFFFFF;
5944 a0 &= 0xFFFFFFFF;
5945 a1 &= 0xFFFFFFFF;
5946 a2 &= 0xFFFFFFFF;
5947 a3 &= 0xFFFFFFFF;
5948 }
5949
07708c4a
JK		 5950 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5951 ret = -KVM_EPERM;
5952 goto out;
5953 }
5954
8776e519 5955 switch (nr) {
b93463aa
AK		 5956 case KVM_HC_VAPIC_POLL_IRQ:
5957 ret = 0;
5958 break;
6aef266c
SV		 5959 case KVM_HC_KICK_CPU:
5960 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5961 ret = 0;
5962 break;
8776e519
HB		 5963 default:
5964 ret = -KVM_ENOSYS;
5965 break;
5966 }
07708c4a 5967out:
a449c7aa
NA		 5968 if (!op_64_bit)
5969 ret = (u32)ret;
5fdbf976 5970 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5971 ++vcpu->stat.hypercalls;
2f333bcb 5972 return r;
8776e519
HB		 5973}
5974EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5975
b6785def 5976static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5977{
d6aa1000 5978 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5979 char instruction[3];
5fdbf976 5980 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5981
8776e519 5982 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5983
9d74191a 5984 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5985}
5986
851ba692 5987static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5988{
782d422b
MG		 5989 return vcpu->run->request_interrupt_window &&
5990 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 5991}
5992
851ba692 5993static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5994{
851ba692
AK		 5995 struct kvm_run *kvm_run = vcpu->run;
5996
91586a3b 5997 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5998 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5999 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6000 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6001 kvm_run->ready_for_interrupt_injection =
6002 pic_in_kernel(vcpu->kvm) ||
782d422b 6003 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6004}
6005
95ba8273
GN		 6006static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6007{
6008 int max_irr, tpr;
6009
6010 if (!kvm_x86_ops->update_cr8_intercept)
6011 return;
6012
88c808fd
AK		 6013 if (!vcpu->arch.apic)
6014 return;
6015
d62caabb
AS		 6016 if (vcpu->arch.apicv_active)
6017 return;
6018
8db3baa2
GN		 6019 if (!vcpu->arch.apic->vapic_addr)
6020 max_irr = kvm_lapic_find_highest_irr(vcpu);
6021 else
6022 max_irr = -1;
95ba8273
GN		 6023
6024 if (max_irr != -1)
6025 max_irr >>= 4;
6026
6027 tpr = kvm_lapic_get_cr8(vcpu);
6028
6029 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6030}
6031
b6b8a145 6032static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6033{
b6b8a145
JK		 6034 int r;
6035
95ba8273 6036 /* try to reinject previous events if any */
b59bb7bd 6037 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6038 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6039 vcpu->arch.exception.has_error_code,
6040 vcpu->arch.exception.error_code);
d6e8c854
NA		 6041
6042 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6043 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6044 X86_EFLAGS_RF);
6045
6bdf0662
NA		 6046 if (vcpu->arch.exception.nr == DB_VECTOR &&
6047 (vcpu->arch.dr7 & DR7_GD)) {
6048 vcpu->arch.dr7 &= ~DR7_GD;
6049 kvm_update_dr7(vcpu);
6050 }
6051
b59bb7bd
GN		 6052 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6053 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6054 vcpu->arch.exception.error_code,
6055 vcpu->arch.exception.reinject);
b6b8a145 6056 return 0;
b59bb7bd
GN		 6057 }
6058
95ba8273
GN		 6059 if (vcpu->arch.nmi_injected) {
6060 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6061 return 0;
95ba8273
GN		 6062 }
6063
6064 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6065 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6066 return 0;
6067 }
6068
6069 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6070 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6071 if (r != 0)
6072 return r;
95ba8273
GN		 6073 }
6074
6075 /* try to inject new event if pending */
6076 if (vcpu->arch.nmi_pending) {
6077 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6078 --vcpu->arch.nmi_pending;
95ba8273
GN		 6079 vcpu->arch.nmi_injected = true;
6080 kvm_x86_ops->set_nmi(vcpu);
6081 }
c7c9c56c 6082 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6083 /*
6084 * Because interrupts can be injected asynchronously, we are
6085 * calling check_nested_events again here to avoid a race condition.
6086 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6087 * proposal and current concerns. Perhaps we should be setting
6088 * KVM_REQ_EVENT only on certain events and not unconditionally?
6089 */
6090 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6091 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6092 if (r != 0)
6093 return r;
6094 }
95ba8273 6095 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6096 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6097 false);
6098 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6099 }
6100 }
b6b8a145 6101 return 0;
95ba8273
GN		 6102}
6103
7460fb4a
AK		 6104static void process_nmi(struct kvm_vcpu *vcpu)
6105{
6106 unsigned limit = 2;
6107
6108 /*
6109 * x86 is limited to one NMI running, and one NMI pending after it.
6110 * If an NMI is already in progress, limit further NMIs to just one.
6111 * Otherwise, allow two (and we'll inject the first one immediately).
6112 */
6113 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6114 limit = 1;
6115
6116 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6117 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6118 kvm_make_request(KVM_REQ_EVENT, vcpu);
6119}
6120
660a5d51
PB		 6121#define put_smstate(type, buf, offset, val) \
6122 *(type *)((buf) + (offset) - 0x7e00) = val
6123
6124static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6125{
6126 u32 flags = 0;
6127 flags |= seg->g << 23;
6128 flags |= seg->db << 22;
6129 flags |= seg->l << 21;
6130 flags |= seg->avl << 20;
6131 flags |= seg->present << 15;
6132 flags |= seg->dpl << 13;
6133 flags |= seg->s << 12;
6134 flags |= seg->type << 8;
6135 return flags;
6136}
6137
6138static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6139{
6140 struct kvm_segment seg;
6141 int offset;
6142
6143 kvm_get_segment(vcpu, &seg, n);
6144 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6145
6146 if (n < 3)
6147 offset = 0x7f84 + n * 12;
6148 else
6149 offset = 0x7f2c + (n - 3) * 12;
6150
6151 put_smstate(u32, buf, offset + 8, seg.base);
6152 put_smstate(u32, buf, offset + 4, seg.limit);
6153 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6154}
6155
efbb288a 6156#ifdef CONFIG_X86_64
660a5d51
PB		 6157static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6158{
6159 struct kvm_segment seg;
6160 int offset;
6161 u16 flags;
6162
6163 kvm_get_segment(vcpu, &seg, n);
6164 offset = 0x7e00 + n * 16;
6165
6166 flags = process_smi_get_segment_flags(&seg) >> 8;
6167 put_smstate(u16, buf, offset, seg.selector);
6168 put_smstate(u16, buf, offset + 2, flags);
6169 put_smstate(u32, buf, offset + 4, seg.limit);
6170 put_smstate(u64, buf, offset + 8, seg.base);
6171}
efbb288a 6172#endif
660a5d51
PB		 6173
6174static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6175{
6176 struct desc_ptr dt;
6177 struct kvm_segment seg;
6178 unsigned long val;
6179 int i;
6180
6181 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6182 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6183 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6184 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6185
6186 for (i = 0; i < 8; i++)
6187 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6188
6189 kvm_get_dr(vcpu, 6, &val);
6190 put_smstate(u32, buf, 0x7fcc, (u32)val);
6191 kvm_get_dr(vcpu, 7, &val);
6192 put_smstate(u32, buf, 0x7fc8, (u32)val);
6193
6194 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6195 put_smstate(u32, buf, 0x7fc4, seg.selector);
6196 put_smstate(u32, buf, 0x7f64, seg.base);
6197 put_smstate(u32, buf, 0x7f60, seg.limit);
6198 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6199
6200 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6201 put_smstate(u32, buf, 0x7fc0, seg.selector);
6202 put_smstate(u32, buf, 0x7f80, seg.base);
6203 put_smstate(u32, buf, 0x7f7c, seg.limit);
6204 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6205
6206 kvm_x86_ops->get_gdt(vcpu, &dt);
6207 put_smstate(u32, buf, 0x7f74, dt.address);
6208 put_smstate(u32, buf, 0x7f70, dt.size);
6209
6210 kvm_x86_ops->get_idt(vcpu, &dt);
6211 put_smstate(u32, buf, 0x7f58, dt.address);
6212 put_smstate(u32, buf, 0x7f54, dt.size);
6213
6214 for (i = 0; i < 6; i++)
6215 process_smi_save_seg_32(vcpu, buf, i);
6216
6217 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6218
6219 /* revision id */
6220 put_smstate(u32, buf, 0x7efc, 0x00020000);
6221 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6222}
6223
6224static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6225{
6226#ifdef CONFIG_X86_64
6227 struct desc_ptr dt;
6228 struct kvm_segment seg;
6229 unsigned long val;
6230 int i;
6231
6232 for (i = 0; i < 16; i++)
6233 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6234
6235 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6236 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6237
6238 kvm_get_dr(vcpu, 6, &val);
6239 put_smstate(u64, buf, 0x7f68, val);
6240 kvm_get_dr(vcpu, 7, &val);
6241 put_smstate(u64, buf, 0x7f60, val);
6242
6243 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6244 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6245 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6246
6247 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6248
6249 /* revision id */
6250 put_smstate(u32, buf, 0x7efc, 0x00020064);
6251
6252 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6253
6254 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6255 put_smstate(u16, buf, 0x7e90, seg.selector);
6256 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6257 put_smstate(u32, buf, 0x7e94, seg.limit);
6258 put_smstate(u64, buf, 0x7e98, seg.base);
6259
6260 kvm_x86_ops->get_idt(vcpu, &dt);
6261 put_smstate(u32, buf, 0x7e84, dt.size);
6262 put_smstate(u64, buf, 0x7e88, dt.address);
6263
6264 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6265 put_smstate(u16, buf, 0x7e70, seg.selector);
6266 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6267 put_smstate(u32, buf, 0x7e74, seg.limit);
6268 put_smstate(u64, buf, 0x7e78, seg.base);
6269
6270 kvm_x86_ops->get_gdt(vcpu, &dt);
6271 put_smstate(u32, buf, 0x7e64, dt.size);
6272 put_smstate(u64, buf, 0x7e68, dt.address);
6273
6274 for (i = 0; i < 6; i++)
6275 process_smi_save_seg_64(vcpu, buf, i);
6276#else
6277 WARN_ON_ONCE(1);
6278#endif
6279}
6280
64d60670
PB		 6281static void process_smi(struct kvm_vcpu *vcpu)
6282{
660a5d51 6283 struct kvm_segment cs, ds;
18c3626e 6284 struct desc_ptr dt;
660a5d51
PB		 6285 char buf[512];
6286 u32 cr0;
6287
64d60670
PB		 6288 if (is_smm(vcpu)) {
6289 vcpu->arch.smi_pending = true;
6290 return;
6291 }
6292
660a5d51
PB		 6293 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6294 vcpu->arch.hflags |= HF_SMM_MASK;
6295 memset(buf, 0, 512);
6296 if (guest_cpuid_has_longmode(vcpu))
6297 process_smi_save_state_64(vcpu, buf);
6298 else
6299 process_smi_save_state_32(vcpu, buf);
6300
54bf36aa 6301 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6302
6303 if (kvm_x86_ops->get_nmi_mask(vcpu))
6304 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6305 else
6306 kvm_x86_ops->set_nmi_mask(vcpu, true);
6307
6308 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6309 kvm_rip_write(vcpu, 0x8000);
6310
6311 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6312 kvm_x86_ops->set_cr0(vcpu, cr0);
6313 vcpu->arch.cr0 = cr0;
6314
6315 kvm_x86_ops->set_cr4(vcpu, 0);
6316
18c3626e
PB		 6317 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6318 dt.address = dt.size = 0;
6319 kvm_x86_ops->set_idt(vcpu, &dt);
6320
660a5d51
PB		 6321 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6322
6323 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6324 cs.base = vcpu->arch.smbase;
6325
6326 ds.selector = 0;
6327 ds.base = 0;
6328
6329 cs.limit = ds.limit = 0xffffffff;
6330 cs.type = ds.type = 0x3;
6331 cs.dpl = ds.dpl = 0;
6332 cs.db = ds.db = 0;
6333 cs.s = ds.s = 1;
6334 cs.l = ds.l = 0;
6335 cs.g = ds.g = 1;
6336 cs.avl = ds.avl = 0;
6337 cs.present = ds.present = 1;
6338 cs.unusable = ds.unusable = 0;
6339 cs.padding = ds.padding = 0;
6340
6341 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6342 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6343 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6344 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6345 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6346 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6347
6348 if (guest_cpuid_has_longmode(vcpu))
6349 kvm_x86_ops->set_efer(vcpu, 0);
6350
6351 kvm_update_cpuid(vcpu);
6352 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6353}
6354
2860c4b1
PB		 6355void kvm_make_scan_ioapic_request(struct kvm *kvm)
6356{
6357 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6358}
6359
3d81bc7e 6360static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6361{
5c919412
AS		 6362 u64 eoi_exit_bitmap[4];
6363
3d81bc7e
YZ		 6364 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6365 return;
c7c9c56c 6366
6308630b 6367 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6368
b053b2ae 6369 if (irqchip_split(vcpu->kvm))
6308630b 6370 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6371 else {
d62caabb
AS		 6372 if (vcpu->arch.apicv_active)
6373 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6374 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6375 }
5c919412
AS		 6376 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6377 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6378 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6379}
6380
a70656b6
RK		 6381static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6382{
6383 ++vcpu->stat.tlb_flush;
6384 kvm_x86_ops->tlb_flush(vcpu);
6385}
6386
4256f43f
TC		 6387void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6388{
c24ae0dc
TC		 6389 struct page *page = NULL;
6390
35754c98 6391 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6392 return;
6393
4256f43f
TC		 6394 if (!kvm_x86_ops->set_apic_access_page_addr)
6395 return;
6396
c24ae0dc 6397 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6398 if (is_error_page(page))
6399 return;
c24ae0dc
TC		 6400 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6401
6402 /*
6403 * Do not pin apic access page in memory, the MMU notifier
6404 * will call us again if it is migrated or swapped out.
6405 */
6406 put_page(page);
4256f43f
TC		 6407}
6408EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6409
fe71557a
TC		 6410void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6411 unsigned long address)
6412{
c24ae0dc
TC		 6413 /*
6414 * The physical address of apic access page is stored in the VMCS.
6415 * Update it when it becomes invalid.
6416 */
6417 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6418 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6419}
6420
9357d939 6421/*
362c698f 6422 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6423 * exiting to the userspace. Otherwise, the value will be returned to the
6424 * userspace.
6425 */
851ba692 6426static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6427{
6428 int r;
62a193ed
MG		 6429 bool req_int_win =
6430 dm_request_for_irq_injection(vcpu) &&
6431 kvm_cpu_accept_dm_intr(vcpu);
6432
730dca42 6433 bool req_immediate_exit = false;
b6c7a5dc 6434
3e007509 6435 if (vcpu->requests) {
a8eeb04a 6436 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6437 kvm_mmu_unload(vcpu);
a8eeb04a 6438 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6439 __kvm_migrate_timers(vcpu);
d828199e
MT		 6440 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6441 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6442 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6443 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6444 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6445 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6446 if (unlikely(r))
6447 goto out;
6448 }
a8eeb04a 6449 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6450 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6451 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6452 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6453 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6454 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6455 r = 0;
6456 goto out;
6457 }
a8eeb04a 6458 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6459 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6460 r = 0;
6461 goto out;
6462 }
a8eeb04a 6463 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6464 vcpu->fpu_active = 0;
6465 kvm_x86_ops->fpu_deactivate(vcpu);
6466 }
af585b92
GN		 6467 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6468 /* Page is swapped out. Do synthetic halt */
6469 vcpu->arch.apf.halted = true;
6470 r = 1;
6471 goto out;
6472 }
c9aaa895
GC		 6473 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6474 record_steal_time(vcpu);
64d60670
PB		 6475 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6476 process_smi(vcpu);
7460fb4a
AK		 6477 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6478 process_nmi(vcpu);
f5132b01 6479 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6480 kvm_pmu_handle_event(vcpu);
f5132b01 6481 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6482 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6483 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6484 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6485 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6486 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6487 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6488 vcpu->run->eoi.vector =
6489 vcpu->arch.pending_ioapic_eoi;
6490 r = 0;
6491 goto out;
6492 }
6493 }
3d81bc7e
YZ		 6494 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6495 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6496 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6497 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6498 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6499 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6500 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6501 r = 0;
6502 goto out;
6503 }
e516cebb
AS		 6504 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6505 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6506 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6507 r = 0;
6508 goto out;
6509 }
db397571
AS		 6510 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6511 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6512 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6513 r = 0;
6514 goto out;
6515 }
f3b138c5
AS		 6516
6517 /*
6518 * KVM_REQ_HV_STIMER has to be processed after
6519 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6520 * depend on the guest clock being up-to-date
6521 */
1f4b34f8
AS		 6522 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6523 kvm_hv_process_stimers(vcpu);
2f52d58c 6524 }
b93463aa 6525
bf9f6ac8
FW		 6526 /*
6527 * KVM_REQ_EVENT is not set when posted interrupts are set by
6528 * VT-d hardware, so we have to update RVI unconditionally.
6529 */
6530 if (kvm_lapic_enabled(vcpu)) {
6531 /*
6532 * Update architecture specific hints for APIC
6533 * virtual interrupt delivery.
6534 */
d62caabb 6535 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6536 kvm_x86_ops->hwapic_irr_update(vcpu,
6537 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6538 }
b93463aa 6539
b463a6f7 6540 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6541 kvm_apic_accept_events(vcpu);
6542 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6543 r = 1;
6544 goto out;
6545 }
6546
b6b8a145
JK		 6547 if (inject_pending_event(vcpu, req_int_win) != 0)
6548 req_immediate_exit = true;
b463a6f7 6549 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6550 else if (vcpu->arch.nmi_pending)
c9a7953f 6551 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6552 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6553 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6554
6555 if (kvm_lapic_enabled(vcpu)) {
6556 update_cr8_intercept(vcpu);
6557 kvm_lapic_sync_to_vapic(vcpu);
6558 }
6559 }
6560
d8368af8
AK		 6561 r = kvm_mmu_reload(vcpu);
6562 if (unlikely(r)) {
d905c069 6563 goto cancel_injection;
d8368af8
AK		 6564 }
6565
b6c7a5dc
HB		 6566 preempt_disable();
6567
6568 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6569 if (vcpu->fpu_active)
6570 kvm_load_guest_fpu(vcpu);
2acf923e 6571 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6572
6b7e2d09
XG		 6573 vcpu->mode = IN_GUEST_MODE;
6574
01b71917
MT		 6575 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6576
6b7e2d09
XG		 6577 /* We should set ->mode before check ->requests,
6578 * see the comment in make_all_cpus_request.
6579 */
01b71917 6580 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6581
d94e1dc9 6582 local_irq_disable();
32f88400 6583
6b7e2d09 6584 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6585 || need_resched() || signal_pending(current)) {
6b7e2d09 6586 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6587 smp_wmb();
6c142801
AK		 6588 local_irq_enable();
6589 preempt_enable();
01b71917 6590 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6591 r = 1;
d905c069 6592 goto cancel_injection;
6c142801
AK		 6593 }
6594
d6185f20
NHE		 6595 if (req_immediate_exit)
6596 smp_send_reschedule(vcpu->cpu);
6597
8b89fe1f
PB		 6598 trace_kvm_entry(vcpu->vcpu_id);
6599 wait_lapic_expire(vcpu);
ccf73aaf 6600 __kvm_guest_enter();
b6c7a5dc 6601
42dbaa5a 6602 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6603 set_debugreg(0, 7);
6604 set_debugreg(vcpu->arch.eff_db[0], 0);
6605 set_debugreg(vcpu->arch.eff_db[1], 1);
6606 set_debugreg(vcpu->arch.eff_db[2], 2);
6607 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6608 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6609 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6610 }
b6c7a5dc 6611
851ba692 6612 kvm_x86_ops->run(vcpu);
b6c7a5dc 6613
c77fb5fe
PB		 6614 /*
6615 * Do this here before restoring debug registers on the host. And
6616 * since we do this before handling the vmexit, a DR access vmexit
6617 * can (a) read the correct value of the debug registers, (b) set
6618 * KVM_DEBUGREG_WONT_EXIT again.
6619 */
6620 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6621 int i;
6622
6623 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6624 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6625 for (i = 0; i < KVM_NR_DB_REGS; i++)
6626 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6627 }
6628
24f1e32c
FW		 6629 /*
6630 * If the guest has used debug registers, at least dr7
6631 * will be disabled while returning to the host.
6632 * If we don't have active breakpoints in the host, we don't
6633 * care about the messed up debug address registers. But if
6634 * we have some of them active, restore the old state.
6635 */
59d8eb53 6636 if (hw_breakpoint_active())
24f1e32c 6637 hw_breakpoint_restore();
42dbaa5a 6638
4ba76538 6639 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6640
6b7e2d09 6641 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6642 smp_wmb();
a547c6db
YZ		 6643
6644 /* Interrupt is enabled by handle_external_intr() */
6645 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6646
6647 ++vcpu->stat.exits;
6648
6649 /*
6650 * We must have an instruction between local_irq_enable() and
6651 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6652 * the interrupt shadow. The stat.exits increment will do nicely.
6653 * But we need to prevent reordering, hence this barrier():
6654 */
6655 barrier();
6656
6657 kvm_guest_exit();
6658
6659 preempt_enable();
6660
f656ce01 6661 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6662
b6c7a5dc
HB		 6663 /*
6664 * Profile KVM exit RIPs:
6665 */
6666 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6667 unsigned long rip = kvm_rip_read(vcpu);
6668 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6669 }
6670
cc578287
ZA		 6671 if (unlikely(vcpu->arch.tsc_always_catchup))
6672 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6673
5cfb1d5a
MT		 6674 if (vcpu->arch.apic_attention)
6675 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6676
851ba692 6677 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6678 return r;
6679
6680cancel_injection:
6681 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6682 if (unlikely(vcpu->arch.apic_attention))
6683 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6684out:
6685 return r;
6686}
b6c7a5dc 6687
362c698f
PB		 6688static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6689{
bf9f6ac8
FW		 6690 if (!kvm_arch_vcpu_runnable(vcpu) &&
6691 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6692 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6693 kvm_vcpu_block(vcpu);
6694 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6695
6696 if (kvm_x86_ops->post_block)
6697 kvm_x86_ops->post_block(vcpu);
6698
9c8fd1ba
PB		 6699 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6700 return 1;
6701 }
362c698f
PB		 6702
6703 kvm_apic_accept_events(vcpu);
6704 switch(vcpu->arch.mp_state) {
6705 case KVM_MP_STATE_HALTED:
6706 vcpu->arch.pv.pv_unhalted = false;
6707 vcpu->arch.mp_state =
6708 KVM_MP_STATE_RUNNABLE;
6709 case KVM_MP_STATE_RUNNABLE:
6710 vcpu->arch.apf.halted = false;
6711 break;
6712 case KVM_MP_STATE_INIT_RECEIVED:
6713 break;
6714 default:
6715 return -EINTR;
6716 break;
6717 }
6718 return 1;
6719}
09cec754 6720
5d9bc648
PB		 6721static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6722{
6723 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6724 !vcpu->arch.apf.halted);
6725}
6726
362c698f 6727static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6728{
6729 int r;
f656ce01 6730 struct kvm *kvm = vcpu->kvm;
d7690175 6731
f656ce01 6732 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6733
362c698f 6734 for (;;) {
58f800d5 6735 if (kvm_vcpu_running(vcpu)) {
851ba692 6736 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6737 } else {
362c698f 6738 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6739 }
6740
09cec754
GN		 6741 if (r <= 0)
6742 break;
6743
6744 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6745 if (kvm_cpu_has_pending_timer(vcpu))
6746 kvm_inject_pending_timer_irqs(vcpu);
6747
782d422b
MG		 6748 if (dm_request_for_irq_injection(vcpu) &&
6749 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6750 r = 0;
6751 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6752 ++vcpu->stat.request_irq_exits;
362c698f 6753 break;
09cec754 6754 }
af585b92
GN		 6755
6756 kvm_check_async_pf_completion(vcpu);
6757
09cec754
GN		 6758 if (signal_pending(current)) {
6759 r = -EINTR;
851ba692 6760 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6761 ++vcpu->stat.signal_exits;
362c698f 6762 break;
09cec754
GN		 6763 }
6764 if (need_resched()) {
f656ce01 6765 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6766 cond_resched();
f656ce01 6767 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6768 }
b6c7a5dc
HB		 6769 }
6770
f656ce01 6771 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6772
6773 return r;
6774}
6775
716d51ab
GN		 6776static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6777{
6778 int r;
6779 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6780 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6781 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6782 if (r != EMULATE_DONE)
6783 return 0;
6784 return 1;
6785}
6786
6787static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6788{
6789 BUG_ON(!vcpu->arch.pio.count);
6790
6791 return complete_emulated_io(vcpu);
6792}
6793
f78146b0
AK		 6794/*
6795 * Implements the following, as a state machine:
6796 *
6797 * read:
6798 * for each fragment
87da7e66
XG		 6799 * for each mmio piece in the fragment
6800 * write gpa, len
6801 * exit
6802 * copy data
f78146b0
AK		 6803 * execute insn
6804 *
6805 * write:
6806 * for each fragment
87da7e66
XG		 6807 * for each mmio piece in the fragment
6808 * write gpa, len
6809 * copy data
6810 * exit
f78146b0 6811 */
716d51ab 6812static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6813{
6814 struct kvm_run *run = vcpu->run;
f78146b0 6815 struct kvm_mmio_fragment *frag;
87da7e66 6816 unsigned len;
5287f194 6817
716d51ab 6818 BUG_ON(!vcpu->mmio_needed);
5287f194 6819
716d51ab 6820 /* Complete previous fragment */
87da7e66
XG		 6821 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6822 len = min(8u, frag->len);
716d51ab 6823 if (!vcpu->mmio_is_write)
87da7e66
XG		 6824 memcpy(frag->data, run->mmio.data, len);
6825
6826 if (frag->len <= 8) {
6827 /* Switch to the next fragment. */
6828 frag++;
6829 vcpu->mmio_cur_fragment++;
6830 } else {
6831 /* Go forward to the next mmio piece. */
6832 frag->data += len;
6833 frag->gpa += len;
6834 frag->len -= len;
6835 }
6836
a08d3b3b 6837 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6838 vcpu->mmio_needed = 0;
0912c977
PB		 6839
6840 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6841 if (vcpu->mmio_is_write)
716d51ab
GN		 6842 return 1;
6843 vcpu->mmio_read_completed = 1;
6844 return complete_emulated_io(vcpu);
6845 }
87da7e66 6846
716d51ab
GN		 6847 run->exit_reason = KVM_EXIT_MMIO;
6848 run->mmio.phys_addr = frag->gpa;
6849 if (vcpu->mmio_is_write)
87da7e66
XG		 6850 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6851 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6852 run->mmio.is_write = vcpu->mmio_is_write;
6853 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6854 return 0;
5287f194
AK		 6855}
6856
716d51ab 6857
b6c7a5dc
HB		 6858int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6859{
c5bedc68 6860 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6861 int r;
6862 sigset_t sigsaved;
6863
c4d72e2d 6864 fpu__activate_curr(fpu);
e5c30142 6865
ac9f6dc0
AK		 6866 if (vcpu->sigset_active)
6867 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6868
a4535290 6869 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6870 kvm_vcpu_block(vcpu);
66450a21 6871 kvm_apic_accept_events(vcpu);
d7690175 6872 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6873 r = -EAGAIN;
6874 goto out;
b6c7a5dc
HB		 6875 }
6876
b6c7a5dc 6877 /* re-sync apic's tpr */
35754c98 6878 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6879 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6880 r = -EINVAL;
6881 goto out;
6882 }
6883 }
b6c7a5dc 6884
716d51ab
GN		 6885 if (unlikely(vcpu->arch.complete_userspace_io)) {
6886 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6887 vcpu->arch.complete_userspace_io = NULL;
6888 r = cui(vcpu);
6889 if (r <= 0)
6890 goto out;
6891 } else
6892 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6893
362c698f 6894 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6895
6896out:
f1d86e46 6897 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6898 if (vcpu->sigset_active)
6899 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6900
b6c7a5dc
HB		 6901 return r;
6902}
6903
6904int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6905{
7ae441ea
GN		 6906 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6907 /*
6908 * We are here if userspace calls get_regs() in the middle of
6909 * instruction emulation. Registers state needs to be copied
4a969980 6910 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6911 * that usually, but some bad designed PV devices (vmware
6912 * backdoor interface) need this to work
6913 */
dd856efa 6914 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6915 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6916 }
5fdbf976
MT		 6917 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6918 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6919 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6920 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6921 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6922 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6923 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6924 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6925#ifdef CONFIG_X86_64
5fdbf976
MT		 6926 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6927 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6928 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6929 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6930 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6931 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6932 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6933 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6934#endif
6935
5fdbf976 6936 regs->rip = kvm_rip_read(vcpu);
91586a3b 6937 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6938
b6c7a5dc
HB		 6939 return 0;
6940}
6941
6942int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6943{
7ae441ea
GN		 6944 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6945 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6946
5fdbf976
MT		 6947 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6948 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6949 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6950 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6951 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6952 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6953 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6954 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6955#ifdef CONFIG_X86_64
5fdbf976
MT		 6956 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6957 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6958 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6959 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6960 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6961 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6962 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6963 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6964#endif
6965
5fdbf976 6966 kvm_rip_write(vcpu, regs->rip);
91586a3b 6967 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6968
b4f14abd
JK		 6969 vcpu->arch.exception.pending = false;
6970
3842d135
AK		 6971 kvm_make_request(KVM_REQ_EVENT, vcpu);
6972
b6c7a5dc
HB		 6973 return 0;
6974}
6975
b6c7a5dc
HB		 6976void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6977{
6978 struct kvm_segment cs;
6979
3e6e0aab 6980 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6981 *db = cs.db;
6982 *l = cs.l;
6983}
6984EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6985
6986int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6987 struct kvm_sregs *sregs)
6988{
89a27f4d 6989 struct desc_ptr dt;
b6c7a5dc 6990
3e6e0aab
GT		 6991 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6992 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6993 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6994 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6995 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6996 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6997
3e6e0aab
GT		 6998 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6999 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7000
7001 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7002 sregs->idt.limit = dt.size;
7003 sregs->idt.base = dt.address;
b6c7a5dc 7004 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7005 sregs->gdt.limit = dt.size;
7006 sregs->gdt.base = dt.address;
b6c7a5dc 7007
4d4ec087 7008 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7009 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7010 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7011 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7012 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7013 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7014 sregs->apic_base = kvm_get_apic_base(vcpu);
7015
923c61bb 7016 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7017
36752c9b 7018 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7019 set_bit(vcpu->arch.interrupt.nr,
7020 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7021
b6c7a5dc
HB		 7022 return 0;
7023}
7024
62d9f0db
MT		 7025int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7026 struct kvm_mp_state *mp_state)
7027{
66450a21 7028 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7029 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7030 vcpu->arch.pv.pv_unhalted)
7031 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7032 else
7033 mp_state->mp_state = vcpu->arch.mp_state;
7034
62d9f0db
MT		 7035 return 0;
7036}
7037
7038int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7039 struct kvm_mp_state *mp_state)
7040{
66450a21
JK		 7041 if (!kvm_vcpu_has_lapic(vcpu) &&
7042 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7043 return -EINVAL;
7044
7045 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7046 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7047 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7048 } else
7049 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7050 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7051 return 0;
7052}
7053
7f3d35fd
KW		 7054int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7055 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7056{
9d74191a 7057 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7058 int ret;
e01c2426 7059
8ec4722d 7060 init_emulate_ctxt(vcpu);
c697518a 7061
7f3d35fd 7062 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7063 has_error_code, error_code);
c697518a 7064
c697518a 7065 if (ret)
19d04437 7066 return EMULATE_FAIL;
37817f29 7067
9d74191a
TY		 7068 kvm_rip_write(vcpu, ctxt->eip);
7069 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7070 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7071 return EMULATE_DONE;
37817f29
IE		 7072}
7073EXPORT_SYMBOL_GPL(kvm_task_switch);
7074
b6c7a5dc
HB		 7075int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7076 struct kvm_sregs *sregs)
7077{
58cb628d 7078 struct msr_data apic_base_msr;
b6c7a5dc 7079 int mmu_reset_needed = 0;
63f42e02 7080 int pending_vec, max_bits, idx;
89a27f4d 7081 struct desc_ptr dt;
b6c7a5dc 7082
6d1068b3
PM		 7083 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7084 return -EINVAL;
7085
89a27f4d
GN		 7086 dt.size = sregs->idt.limit;
7087 dt.address = sregs->idt.base;
b6c7a5dc 7088 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7089 dt.size = sregs->gdt.limit;
7090 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7091 kvm_x86_ops->set_gdt(vcpu, &dt);
7092
ad312c7c 7093 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7094 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7095 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7096 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7097
2d3ad1f4 7098 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7099
f6801dff 7100 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7101 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7102 apic_base_msr.data = sregs->apic_base;
7103 apic_base_msr.host_initiated = true;
7104 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7105
4d4ec087 7106 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7107 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7108 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7109
fc78f519 7110 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7111 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7112 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7113 kvm_update_cpuid(vcpu);
63f42e02
XG		 7114
7115 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7116 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7117 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7118 mmu_reset_needed = 1;
7119 }
63f42e02 7120 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7121
7122 if (mmu_reset_needed)
7123 kvm_mmu_reset_context(vcpu);
7124
a50abc3b 7125 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7126 pending_vec = find_first_bit(
7127 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7128 if (pending_vec < max_bits) {
66fd3f7f 7129 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7130 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7131 }
7132
3e6e0aab
GT		 7133 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7134 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7135 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7136 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7137 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7138 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7139
3e6e0aab
GT		 7140 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7141 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7142
5f0269f5
ME		 7143 update_cr8_intercept(vcpu);
7144
9c3e4aab 7145 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7146 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7147 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7148 !is_protmode(vcpu))
9c3e4aab
MT		 7149 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7150
3842d135
AK		 7151 kvm_make_request(KVM_REQ_EVENT, vcpu);
7152
b6c7a5dc
HB		 7153 return 0;
7154}
7155
d0bfb940
JK		 7156int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7157 struct kvm_guest_debug *dbg)
b6c7a5dc 7158{
355be0b9 7159 unsigned long rflags;
ae675ef0 7160 int i, r;
b6c7a5dc 7161
4f926bf2
JK		 7162 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7163 r = -EBUSY;
7164 if (vcpu->arch.exception.pending)
2122ff5e 7165 goto out;
4f926bf2
JK		 7166 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7167 kvm_queue_exception(vcpu, DB_VECTOR);
7168 else
7169 kvm_queue_exception(vcpu, BP_VECTOR);
7170 }
7171
91586a3b
JK		 7172 /*
7173 * Read rflags as long as potentially injected trace flags are still
7174 * filtered out.
7175 */
7176 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7177
7178 vcpu->guest_debug = dbg->control;
7179 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7180 vcpu->guest_debug = 0;
7181
7182 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7183 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7184 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7185 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7186 } else {
7187 for (i = 0; i < KVM_NR_DB_REGS; i++)
7188 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7189 }
c8639010 7190 kvm_update_dr7(vcpu);
ae675ef0 7191
f92653ee
JK		 7192 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7193 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7194 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7195
91586a3b
JK		 7196 /*
7197 * Trigger an rflags update that will inject or remove the trace
7198 * flags.
7199 */
7200 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7201
a96036b8 7202 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7203
4f926bf2 7204 r = 0;
d0bfb940 7205
2122ff5e 7206out:
b6c7a5dc
HB		 7207
7208 return r;
7209}
7210
8b006791
ZX		 7211/*
7212 * Translate a guest virtual address to a guest physical address.
7213 */
7214int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7215 struct kvm_translation *tr)
7216{
7217 unsigned long vaddr = tr->linear_address;
7218 gpa_t gpa;
f656ce01 7219 int idx;
8b006791 7220
f656ce01 7221 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7222 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7223 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7224 tr->physical_address = gpa;
7225 tr->valid = gpa != UNMAPPED_GVA;
7226 tr->writeable = 1;
7227 tr->usermode = 0;
8b006791
ZX		 7228
7229 return 0;
7230}
7231
d0752060
HB		 7232int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7233{
c47ada30 7234 struct fxregs_state *fxsave =
7366ed77 7235 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7236
d0752060
HB		 7237 memcpy(fpu->fpr, fxsave->st_space, 128);
7238 fpu->fcw = fxsave->cwd;
7239 fpu->fsw = fxsave->swd;
7240 fpu->ftwx = fxsave->twd;
7241 fpu->last_opcode = fxsave->fop;
7242 fpu->last_ip = fxsave->rip;
7243 fpu->last_dp = fxsave->rdp;
7244 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7245
d0752060
HB		 7246 return 0;
7247}
7248
7249int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7250{
c47ada30 7251 struct fxregs_state *fxsave =
7366ed77 7252 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7253
d0752060
HB		 7254 memcpy(fxsave->st_space, fpu->fpr, 128);
7255 fxsave->cwd = fpu->fcw;
7256 fxsave->swd = fpu->fsw;
7257 fxsave->twd = fpu->ftwx;
7258 fxsave->fop = fpu->last_opcode;
7259 fxsave->rip = fpu->last_ip;
7260 fxsave->rdp = fpu->last_dp;
7261 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7262
d0752060
HB		 7263 return 0;
7264}
7265
0ee6a517 7266static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7267{
bf935b0b 7268 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7269 if (cpu_has_xsaves)
7366ed77 7270 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7271 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7272
2acf923e
DC		 7273 /*
7274 * Ensure guest xcr0 is valid for loading
7275 */
d91cab78 7276 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7277
ad312c7c 7278 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7279}
d0752060
HB		 7280
7281void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7282{
2608d7a1 7283 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7284 return;
7285
2acf923e
DC		 7286 /*
7287 * Restore all possible states in the guest,
7288 * and assume host would use all available bits.
7289 * Guest xcr0 would be loaded later.
7290 */
7291 kvm_put_guest_xcr0(vcpu);
d0752060 7292 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7293 __kernel_fpu_begin();
003e2e8b 7294 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7295 trace_kvm_fpu(1);
d0752060 7296}
d0752060
HB		 7297
7298void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7299{
2acf923e
DC		 7300 kvm_put_guest_xcr0(vcpu);
7301
653f52c3
RR		 7302 if (!vcpu->guest_fpu_loaded) {
7303 vcpu->fpu_counter = 0;
d0752060 7304 return;
653f52c3 7305 }
d0752060
HB		 7306
7307 vcpu->guest_fpu_loaded = 0;
4f836347 7308 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7309 __kernel_fpu_end();
f096ed85 7310 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7311 /*
7312 * If using eager FPU mode, or if the guest is a frequent user
7313 * of the FPU, just leave the FPU active for next time.
7314 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7315 * the FPU in bursts will revert to loading it on demand.
7316 */
a9b4fb7e 7317 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7318 if (++vcpu->fpu_counter < 5)
7319 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7320 }
0c04851c 7321 trace_kvm_fpu(0);
d0752060 7322}
e9b11c17
ZX		 7323
7324void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7325{
12f9a48f 7326 kvmclock_reset(vcpu);
7f1ea208 7327
f5f48ee1 7328 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7329 kvm_x86_ops->vcpu_free(vcpu);
7330}
7331
7332struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7333 unsigned int id)
7334{
c447e76b
LL		 7335 struct kvm_vcpu *vcpu;
7336
6755bae8
ZA		 7337 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7338 printk_once(KERN_WARNING
7339 "kvm: SMP vm created on host with unstable TSC; "
7340 "guest TSC will not be reliable\n");
c447e76b
LL		 7341
7342 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7343
c447e76b 7344 return vcpu;
26e5215f 7345}
e9b11c17 7346
26e5215f
AK		 7347int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7348{
7349 int r;
e9b11c17 7350
19efffa2 7351 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7352 r = vcpu_load(vcpu);
7353 if (r)
7354 return r;
d28bc9dd 7355 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7356 kvm_mmu_setup(vcpu);
e9b11c17 7357 vcpu_put(vcpu);
26e5215f 7358 return r;
e9b11c17
ZX		 7359}
7360
31928aa5 7361void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7362{
8fe8ab46 7363 struct msr_data msr;
332967a3 7364 struct kvm *kvm = vcpu->kvm;
42897d86 7365
31928aa5
DD		 7366 if (vcpu_load(vcpu))
7367 return;
8fe8ab46
WA		 7368 msr.data = 0x0;
7369 msr.index = MSR_IA32_TSC;
7370 msr.host_initiated = true;
7371 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7372 vcpu_put(vcpu);
7373
630994b3
MT		 7374 if (!kvmclock_periodic_sync)
7375 return;
7376
332967a3
AJ		 7377 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7378 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7379}
7380
d40ccc62 7381void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7382{
9fc77441 7383 int r;
344d9588
GN		 7384 vcpu->arch.apf.msr_val = 0;
7385
9fc77441
MT		 7386 r = vcpu_load(vcpu);
7387 BUG_ON(r);
e9b11c17
ZX		 7388 kvm_mmu_unload(vcpu);
7389 vcpu_put(vcpu);
7390
7391 kvm_x86_ops->vcpu_free(vcpu);
7392}
7393
d28bc9dd 7394void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7395{
e69fab5d
PB		 7396 vcpu->arch.hflags = 0;
7397
7460fb4a
AK		 7398 atomic_set(&vcpu->arch.nmi_queued, 0);
7399 vcpu->arch.nmi_pending = 0;
448fa4a9 7400 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7401 kvm_clear_interrupt_queue(vcpu);
7402 kvm_clear_exception_queue(vcpu);
448fa4a9 7403
42dbaa5a 7404 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7405 kvm_update_dr0123(vcpu);
6f43ed01 7406 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7407 kvm_update_dr6(vcpu);
42dbaa5a 7408 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7409 kvm_update_dr7(vcpu);
42dbaa5a 7410
1119022c
NA		 7411 vcpu->arch.cr2 = 0;
7412
3842d135 7413 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7414 vcpu->arch.apf.msr_val = 0;
c9aaa895 7415 vcpu->arch.st.msr_val = 0;
3842d135 7416
12f9a48f
GC		 7417 kvmclock_reset(vcpu);
7418
af585b92
GN		 7419 kvm_clear_async_pf_completion_queue(vcpu);
7420 kvm_async_pf_hash_reset(vcpu);
7421 vcpu->arch.apf.halted = false;
3842d135 7422
64d60670 7423 if (!init_event) {
d28bc9dd 7424 kvm_pmu_reset(vcpu);
64d60670
PB		 7425 vcpu->arch.smbase = 0x30000;
7426 }
f5132b01 7427
66f7b72e
JS		 7428 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7429 vcpu->arch.regs_avail = ~0;
7430 vcpu->arch.regs_dirty = ~0;
7431
d28bc9dd 7432 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7433}
7434
2b4a273b 7435void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7436{
7437 struct kvm_segment cs;
7438
7439 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7440 cs.selector = vector << 8;
7441 cs.base = vector << 12;
7442 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7443 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7444}
7445
13a34e06 7446int kvm_arch_hardware_enable(void)
e9b11c17 7447{
ca84d1a2
ZA		 7448 struct kvm *kvm;
7449 struct kvm_vcpu *vcpu;
7450 int i;
0dd6a6ed
ZA		 7451 int ret;
7452 u64 local_tsc;
7453 u64 max_tsc = 0;
7454 bool stable, backwards_tsc = false;
18863bdd
AK		 7455
7456 kvm_shared_msr_cpu_online();
13a34e06 7457 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7458 if (ret != 0)
7459 return ret;
7460
4ea1636b 7461 local_tsc = rdtsc();
0dd6a6ed
ZA		 7462 stable = !check_tsc_unstable();
7463 list_for_each_entry(kvm, &vm_list, vm_list) {
7464 kvm_for_each_vcpu(i, vcpu, kvm) {
7465 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7466 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7467 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7468 backwards_tsc = true;
7469 if (vcpu->arch.last_host_tsc > max_tsc)
7470 max_tsc = vcpu->arch.last_host_tsc;
7471 }
7472 }
7473 }
7474
7475 /*
7476 * Sometimes, even reliable TSCs go backwards. This happens on
7477 * platforms that reset TSC during suspend or hibernate actions, but
7478 * maintain synchronization. We must compensate. Fortunately, we can
7479 * detect that condition here, which happens early in CPU bringup,
7480 * before any KVM threads can be running. Unfortunately, we can't
7481 * bring the TSCs fully up to date with real time, as we aren't yet far
7482 * enough into CPU bringup that we know how much real time has actually
7483 * elapsed; our helper function, get_kernel_ns() will be using boot
7484 * variables that haven't been updated yet.
7485 *
7486 * So we simply find the maximum observed TSC above, then record the
7487 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7488 * the adjustment will be applied. Note that we accumulate
7489 * adjustments, in case multiple suspend cycles happen before some VCPU
7490 * gets a chance to run again. In the event that no KVM threads get a
7491 * chance to run, we will miss the entire elapsed period, as we'll have
7492 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7493 * loose cycle time. This isn't too big a deal, since the loss will be
7494 * uniform across all VCPUs (not to mention the scenario is extremely
7495 * unlikely). It is possible that a second hibernate recovery happens
7496 * much faster than a first, causing the observed TSC here to be
7497 * smaller; this would require additional padding adjustment, which is
7498 * why we set last_host_tsc to the local tsc observed here.
7499 *
7500 * N.B. - this code below runs only on platforms with reliable TSC,
7501 * as that is the only way backwards_tsc is set above. Also note
7502 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7503 * have the same delta_cyc adjustment applied if backwards_tsc
7504 * is detected. Note further, this adjustment is only done once,
7505 * as we reset last_host_tsc on all VCPUs to stop this from being
7506 * called multiple times (one for each physical CPU bringup).
7507 *
4a969980 7508 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7509 * will be compensated by the logic in vcpu_load, which sets the TSC to
7510 * catchup mode. This will catchup all VCPUs to real time, but cannot
7511 * guarantee that they stay in perfect synchronization.
7512 */
7513 if (backwards_tsc) {
7514 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7515 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7516 list_for_each_entry(kvm, &vm_list, vm_list) {
7517 kvm_for_each_vcpu(i, vcpu, kvm) {
7518 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7519 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7520 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7521 }
7522
7523 /*
7524 * We have to disable TSC offset matching.. if you were
7525 * booting a VM while issuing an S4 host suspend....
7526 * you may have some problem. Solving this issue is
7527 * left as an exercise to the reader.
7528 */
7529 kvm->arch.last_tsc_nsec = 0;
7530 kvm->arch.last_tsc_write = 0;
7531 }
7532
7533 }
7534 return 0;
e9b11c17
ZX		 7535}
7536
13a34e06 7537void kvm_arch_hardware_disable(void)
e9b11c17 7538{
13a34e06
RK		 7539 kvm_x86_ops->hardware_disable();
7540 drop_user_return_notifiers();
e9b11c17
ZX		 7541}
7542
7543int kvm_arch_hardware_setup(void)
7544{
9e9c3fe4
NA		 7545 int r;
7546
7547 r = kvm_x86_ops->hardware_setup();
7548 if (r != 0)
7549 return r;
7550
35181e86
HZ		 7551 if (kvm_has_tsc_control) {
7552 /*
7553 * Make sure the user can only configure tsc_khz values that
7554 * fit into a signed integer.
7555 * A min value is not calculated needed because it will always
7556 * be 1 on all machines.
7557 */
7558 u64 max = min(0x7fffffffULL,
7559 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7560 kvm_max_guest_tsc_khz = max;
7561
ad721883 7562 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7563 }
ad721883 7564
9e9c3fe4
NA		 7565 kvm_init_msr_list();
7566 return 0;
e9b11c17
ZX		 7567}
7568
7569void kvm_arch_hardware_unsetup(void)
7570{
7571 kvm_x86_ops->hardware_unsetup();
7572}
7573
7574void kvm_arch_check_processor_compat(void *rtn)
7575{
7576 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7577}
7578
7579bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7580{
7581 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7582}
7583EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7584
7585bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7586{
7587 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7588}
7589
3e515705
AK		 7590bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7591{
35754c98 7592 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7593}
7594
54e9818f
GN		 7595struct static_key kvm_no_apic_vcpu __read_mostly;
7596
e9b11c17
ZX		 7597int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7598{
7599 struct page *page;
7600 struct kvm *kvm;
7601 int r;
7602
7603 BUG_ON(vcpu->kvm == NULL);
7604 kvm = vcpu->kvm;
7605
d62caabb 7606 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7607 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7608 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7609 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7610 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7611 else
a4535290 7612 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7613
7614 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7615 if (!page) {
7616 r = -ENOMEM;
7617 goto fail;
7618 }
ad312c7c 7619 vcpu->arch.pio_data = page_address(page);
e9b11c17 7620
cc578287 7621 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7622
e9b11c17
ZX		 7623 r = kvm_mmu_create(vcpu);
7624 if (r < 0)
7625 goto fail_free_pio_data;
7626
7627 if (irqchip_in_kernel(kvm)) {
7628 r = kvm_create_lapic(vcpu);
7629 if (r < 0)
7630 goto fail_mmu_destroy;
54e9818f
GN		 7631 } else
7632 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7633
890ca9ae
HY		 7634 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7635 GFP_KERNEL);
7636 if (!vcpu->arch.mce_banks) {
7637 r = -ENOMEM;
443c39bc 7638 goto fail_free_lapic;
890ca9ae
HY		 7639 }
7640 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7641
f1797359
WY		 7642 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7643 r = -ENOMEM;
f5f48ee1 7644 goto fail_free_mce_banks;
f1797359 7645 }
f5f48ee1 7646
0ee6a517 7647 fx_init(vcpu);
66f7b72e 7648
ba904635 7649 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7650 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7651
7652 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7653 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7654
5a4f55cd
EK		 7655 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7656
74545705
RK		 7657 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7658
af585b92 7659 kvm_async_pf_hash_reset(vcpu);
f5132b01 7660 kvm_pmu_init(vcpu);
af585b92 7661
1c1a9ce9
SR		 7662 vcpu->arch.pending_external_vector = -1;
7663
5c919412
AS		 7664 kvm_hv_vcpu_init(vcpu);
7665
e9b11c17 7666 return 0;
0ee6a517 7667
f5f48ee1
SY		 7668fail_free_mce_banks:
7669 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7670fail_free_lapic:
7671 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7672fail_mmu_destroy:
7673 kvm_mmu_destroy(vcpu);
7674fail_free_pio_data:
ad312c7c 7675 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7676fail:
7677 return r;
7678}
7679
7680void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7681{
f656ce01
MT		 7682 int idx;
7683
1f4b34f8 7684 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7685 kvm_pmu_destroy(vcpu);
36cb93fd 7686 kfree(vcpu->arch.mce_banks);
e9b11c17 7687 kvm_free_lapic(vcpu);
f656ce01 7688 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7689 kvm_mmu_destroy(vcpu);
f656ce01 7690 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7691 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7692 if (!lapic_in_kernel(vcpu))
54e9818f 7693 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7694}
d19a9cd2 7695
e790d9ef
RK		 7696void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7697{
ae97a3b8 7698 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7699}
7700
e08b9637 7701int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7702{
e08b9637
CO		 7703 if (type)
7704 return -EINVAL;
7705
6ef768fa 7706 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7707 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7708 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7709 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7710 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7711
5550af4d
SY		 7712 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7713 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7714 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7715 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7716 &kvm->arch.irq_sources_bitmap);
5550af4d 7717
038f8c11 7718 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7719 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7720 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7721
7722 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7723
7e44e449 7724 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7725 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7726
d89f5eff 7727 return 0;
d19a9cd2
ZX		 7728}
7729
7730static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7731{
9fc77441
MT		 7732 int r;
7733 r = vcpu_load(vcpu);
7734 BUG_ON(r);
d19a9cd2
ZX		 7735 kvm_mmu_unload(vcpu);
7736 vcpu_put(vcpu);
7737}
7738
7739static void kvm_free_vcpus(struct kvm *kvm)
7740{
7741 unsigned int i;
988a2cae 7742 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7743
7744 /*
7745 * Unpin any mmu pages first.
7746 */
af585b92
GN		 7747 kvm_for_each_vcpu(i, vcpu, kvm) {
7748 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7749 kvm_unload_vcpu_mmu(vcpu);
af585b92 7750 }
988a2cae
GN		 7751 kvm_for_each_vcpu(i, vcpu, kvm)
7752 kvm_arch_vcpu_free(vcpu);
7753
7754 mutex_lock(&kvm->lock);
7755 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7756 kvm->vcpus[i] = NULL;
d19a9cd2 7757
988a2cae
GN		 7758 atomic_set(&kvm->online_vcpus, 0);
7759 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7760}
7761
ad8ba2cd
SY		 7762void kvm_arch_sync_events(struct kvm *kvm)
7763{
332967a3 7764 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7765 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7766 kvm_free_all_assigned_devices(kvm);
aea924f6 7767 kvm_free_pit(kvm);
ad8ba2cd
SY		 7768}
7769
1d8007bd 7770int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7771{
7772 int i, r;
25188b99 7773 unsigned long hva;
f0d648bd
PB		 7774 struct kvm_memslots *slots = kvm_memslots(kvm);
7775 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7776
7777 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7778 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7779 return -EINVAL;
9da0e4d5 7780
f0d648bd
PB		 7781 slot = id_to_memslot(slots, id);
7782 if (size) {
7783 if (WARN_ON(slot->npages))
7784 return -EEXIST;
7785
7786 /*
7787 * MAP_SHARED to prevent internal slot pages from being moved
7788 * by fork()/COW.
7789 */
7790 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7791 MAP_SHARED | MAP_ANONYMOUS, 0);
7792 if (IS_ERR((void *)hva))
7793 return PTR_ERR((void *)hva);
7794 } else {
7795 if (!slot->npages)
7796 return 0;
7797
7798 hva = 0;
7799 }
7800
7801 old = *slot;
9da0e4d5 7802 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7803 struct kvm_userspace_memory_region m;
9da0e4d5 7804
1d8007bd
PB		 7805 m.slot = id | (i << 16);
7806 m.flags = 0;
7807 m.guest_phys_addr = gpa;
f0d648bd 7808 m.userspace_addr = hva;
1d8007bd 7809 m.memory_size = size;
9da0e4d5
PB		 7810 r = __kvm_set_memory_region(kvm, &m);
7811 if (r < 0)
7812 return r;
7813 }
7814
f0d648bd
PB		 7815 if (!size) {
7816 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7817 WARN_ON(r < 0);
7818 }
7819
9da0e4d5
PB		 7820 return 0;
7821}
7822EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7823
1d8007bd 7824int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7825{
7826 int r;
7827
7828 mutex_lock(&kvm->slots_lock);
1d8007bd 7829 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7830 mutex_unlock(&kvm->slots_lock);
7831
7832 return r;
7833}
7834EXPORT_SYMBOL_GPL(x86_set_memory_region);
7835
d19a9cd2
ZX		 7836void kvm_arch_destroy_vm(struct kvm *kvm)
7837{
27469d29
AH		 7838 if (current->mm == kvm->mm) {
7839 /*
7840 * Free memory regions allocated on behalf of userspace,
7841 * unless the the memory map has changed due to process exit
7842 * or fd copying.
7843 */
1d8007bd
PB		 7844 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7845 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7846 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7847 }
6eb55818 7848 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7849 kfree(kvm->arch.vpic);
7850 kfree(kvm->arch.vioapic);
d19a9cd2 7851 kvm_free_vcpus(kvm);
1e08ec4a 7852 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7853}
0de10343 7854
5587027c 7855void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7856 struct kvm_memory_slot *dont)
7857{
7858 int i;
7859
d89cc617
TY		 7860 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7861 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7862 kvfree(free->arch.rmap[i]);
d89cc617 7863 free->arch.rmap[i] = NULL;
77d11309 7864 }
d89cc617
TY		 7865 if (i == 0)
7866 continue;
7867
7868 if (!dont || free->arch.lpage_info[i - 1] !=
7869 dont->arch.lpage_info[i - 1]) {
548ef284 7870 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7871 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7872 }
7873 }
7874}
7875
5587027c
AK		 7876int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7877 unsigned long npages)
db3fe4eb
TY		 7878{
7879 int i;
7880
d89cc617 7881 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7882 unsigned long ugfn;
7883 int lpages;
d89cc617 7884 int level = i + 1;
db3fe4eb
TY		 7885
7886 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7887 slot->base_gfn, level) + 1;
7888
d89cc617
TY		 7889 slot->arch.rmap[i] =
7890 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7891 if (!slot->arch.rmap[i])
77d11309 7892 goto out_free;
d89cc617
TY		 7893 if (i == 0)
7894 continue;
77d11309 7895
d89cc617
TY		 7896 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7897 sizeof(*slot->arch.lpage_info[i - 1]));
7898 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7899 goto out_free;
7900
7901 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7902 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7903 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7904 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7905 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7906 /*
7907 * If the gfn and userspace address are not aligned wrt each
7908 * other, or if explicitly asked to, disable large page
7909 * support for this slot
7910 */
7911 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7912 !kvm_largepages_enabled()) {
7913 unsigned long j;
7914
7915 for (j = 0; j < lpages; ++j)
d89cc617 7916 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7917 }
7918 }
7919
7920 return 0;
7921
7922out_free:
d89cc617 7923 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7924 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7925 slot->arch.rmap[i] = NULL;
7926 if (i == 0)
7927 continue;
7928
548ef284 7929 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7930 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7931 }
7932 return -ENOMEM;
7933}
7934
15f46015 7935void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7936{
e6dff7d1
TY		 7937 /*
7938 * memslots->generation has been incremented.
7939 * mmio generation may have reached its maximum value.
7940 */
54bf36aa 7941 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7942}
7943
f7784b8e
MT		 7944int kvm_arch_prepare_memory_region(struct kvm *kvm,
7945 struct kvm_memory_slot *memslot,
09170a49 7946 const struct kvm_userspace_memory_region *mem,
7b6195a9 7947 enum kvm_mr_change change)
0de10343 7948{
f7784b8e
MT		 7949 return 0;
7950}
7951
88178fd4
KH		 7952static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7953 struct kvm_memory_slot *new)
7954{
7955 /* Still write protect RO slot */
7956 if (new->flags & KVM_MEM_READONLY) {
7957 kvm_mmu_slot_remove_write_access(kvm, new);
7958 return;
7959 }
7960
7961 /*
7962 * Call kvm_x86_ops dirty logging hooks when they are valid.
7963 *
7964 * kvm_x86_ops->slot_disable_log_dirty is called when:
7965 *
7966 * - KVM_MR_CREATE with dirty logging is disabled
7967 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7968 *
7969 * The reason is, in case of PML, we need to set D-bit for any slots
7970 * with dirty logging disabled in order to eliminate unnecessary GPA
7971 * logging in PML buffer (and potential PML buffer full VMEXT). This
7972 * guarantees leaving PML enabled during guest's lifetime won't have
7973 * any additonal overhead from PML when guest is running with dirty
7974 * logging disabled for memory slots.
7975 *
7976 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7977 * to dirty logging mode.
7978 *
7979 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7980 *
7981 * In case of write protect:
7982 *
7983 * Write protect all pages for dirty logging.
7984 *
7985 * All the sptes including the large sptes which point to this
7986 * slot are set to readonly. We can not create any new large
7987 * spte on this slot until the end of the logging.
7988 *
7989 * See the comments in fast_page_fault().
7990 */
7991 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7992 if (kvm_x86_ops->slot_enable_log_dirty)
7993 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7994 else
7995 kvm_mmu_slot_remove_write_access(kvm, new);
7996 } else {
7997 if (kvm_x86_ops->slot_disable_log_dirty)
7998 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7999 }
8000}
8001
f7784b8e 8002void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8003 const struct kvm_userspace_memory_region *mem,
8482644a 8004 const struct kvm_memory_slot *old,
f36f3f28 8005 const struct kvm_memory_slot *new,
8482644a 8006 enum kvm_mr_change change)
f7784b8e 8007{
8482644a 8008 int nr_mmu_pages = 0;
f7784b8e 8009
48c0e4e9
XG		 8010 if (!kvm->arch.n_requested_mmu_pages)
8011 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8012
48c0e4e9 8013 if (nr_mmu_pages)
0de10343 8014 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8015
3ea3b7fa
WL		 8016 /*
8017 * Dirty logging tracks sptes in 4k granularity, meaning that large
8018 * sptes have to be split. If live migration is successful, the guest
8019 * in the source machine will be destroyed and large sptes will be
8020 * created in the destination. However, if the guest continues to run
8021 * in the source machine (for example if live migration fails), small
8022 * sptes will remain around and cause bad performance.
8023 *
8024 * Scan sptes if dirty logging has been stopped, dropping those
8025 * which can be collapsed into a single large-page spte. Later
8026 * page faults will create the large-page sptes.
8027 */
8028 if ((change != KVM_MR_DELETE) &&
8029 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8030 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8031 kvm_mmu_zap_collapsible_sptes(kvm, new);
8032
c972f3b1 8033 /*
88178fd4 8034 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8035 *
88178fd4
KH		 8036 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8037 * been zapped so no dirty logging staff is needed for old slot. For
8038 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8039 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8040 *
8041 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8042 */
88178fd4 8043 if (change != KVM_MR_DELETE)
f36f3f28 8044 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8045}
1d737c8a 8046
2df72e9b 8047void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8048{
6ca18b69 8049 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8050}
8051
2df72e9b
MT		 8052void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8053 struct kvm_memory_slot *slot)
8054{
6ca18b69 8055 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8056}
8057
5d9bc648
PB		 8058static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8059{
8060 if (!list_empty_careful(&vcpu->async_pf.done))
8061 return true;
8062
8063 if (kvm_apic_has_events(vcpu))
8064 return true;
8065
8066 if (vcpu->arch.pv.pv_unhalted)
8067 return true;
8068
8069 if (atomic_read(&vcpu->arch.nmi_queued))
8070 return true;
8071
73917739
PB		 8072 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8073 return true;
8074
5d9bc648
PB		 8075 if (kvm_arch_interrupt_allowed(vcpu) &&
8076 kvm_cpu_has_interrupt(vcpu))
8077 return true;
8078
1f4b34f8
AS		 8079 if (kvm_hv_has_stimer_pending(vcpu))
8080 return true;
8081
5d9bc648
PB		 8082 return false;
8083}
8084
1d737c8a
ZX		 8085int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8086{
b6b8a145
JK		 8087 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8088 kvm_x86_ops->check_nested_events(vcpu, false);
8089
5d9bc648 8090 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8091}
5736199a 8092
b6d33834 8093int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8094{
b6d33834 8095 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8096}
78646121
GN		 8097
8098int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8099{
8100 return kvm_x86_ops->interrupt_allowed(vcpu);
8101}
229456fc 8102
82b32774 8103unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8104{
82b32774
NA		 8105 if (is_64_bit_mode(vcpu))
8106 return kvm_rip_read(vcpu);
8107 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8108 kvm_rip_read(vcpu));
8109}
8110EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8111
82b32774
NA		 8112bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8113{
8114 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8115}
8116EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8117
94fe45da
JK		 8118unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8119{
8120 unsigned long rflags;
8121
8122 rflags = kvm_x86_ops->get_rflags(vcpu);
8123 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8124 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8125 return rflags;
8126}
8127EXPORT_SYMBOL_GPL(kvm_get_rflags);
8128
6addfc42 8129static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8130{
8131 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8132 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8133 rflags |= X86_EFLAGS_TF;
94fe45da 8134 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8135}
8136
8137void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8138{
8139 __kvm_set_rflags(vcpu, rflags);
3842d135 8140 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8141}
8142EXPORT_SYMBOL_GPL(kvm_set_rflags);
8143
56028d08
GN		 8144void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8145{
8146 int r;
8147
fb67e14f 8148 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8149 work->wakeup_all)
56028d08
GN		 8150 return;
8151
8152 r = kvm_mmu_reload(vcpu);
8153 if (unlikely(r))
8154 return;
8155
fb67e14f
XG		 8156 if (!vcpu->arch.mmu.direct_map &&
8157 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8158 return;
8159
56028d08
GN		 8160 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8161}
8162
af585b92
GN		 8163static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8164{
8165 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8166}
8167
8168static inline u32 kvm_async_pf_next_probe(u32 key)
8169{
8170 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8171}
8172
8173static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8174{
8175 u32 key = kvm_async_pf_hash_fn(gfn);
8176
8177 while (vcpu->arch.apf.gfns[key] != ~0)
8178 key = kvm_async_pf_next_probe(key);
8179
8180 vcpu->arch.apf.gfns[key] = gfn;
8181}
8182
8183static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8184{
8185 int i;
8186 u32 key = kvm_async_pf_hash_fn(gfn);
8187
8188 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8189 (vcpu->arch.apf.gfns[key] != gfn &&
8190 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8191 key = kvm_async_pf_next_probe(key);
8192
8193 return key;
8194}
8195
8196bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8197{
8198 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8199}
8200
8201static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8202{
8203 u32 i, j, k;
8204
8205 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8206 while (true) {
8207 vcpu->arch.apf.gfns[i] = ~0;
8208 do {
8209 j = kvm_async_pf_next_probe(j);
8210 if (vcpu->arch.apf.gfns[j] == ~0)
8211 return;
8212 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8213 /*
8214 * k lies cyclically in ]i,j]
8215 * | i.k.j |
8216 * |....j i.k.| or |.k..j i...|
8217 */
8218 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8219 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8220 i = j;
8221 }
8222}
8223
7c90705b
GN		 8224static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8225{
8226
8227 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8228 sizeof(val));
8229}
8230
af585b92
GN		 8231void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8232 struct kvm_async_pf *work)
8233{
6389ee94
AK		 8234 struct x86_exception fault;
8235
7c90705b 8236 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8237 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8238
8239 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8240 (vcpu->arch.apf.send_user_only &&
8241 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8242 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8243 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8244 fault.vector = PF_VECTOR;
8245 fault.error_code_valid = true;
8246 fault.error_code = 0;
8247 fault.nested_page_fault = false;
8248 fault.address = work->arch.token;
8249 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8250 }
af585b92
GN		 8251}
8252
8253void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8254 struct kvm_async_pf *work)
8255{
6389ee94
AK		 8256 struct x86_exception fault;
8257
7c90705b 8258 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8259 if (work->wakeup_all)
7c90705b
GN		 8260 work->arch.token = ~0; /* broadcast wakeup */
8261 else
8262 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8263
8264 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8265 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8266 fault.vector = PF_VECTOR;
8267 fault.error_code_valid = true;
8268 fault.error_code = 0;
8269 fault.nested_page_fault = false;
8270 fault.address = work->arch.token;
8271 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8272 }
e6d53e3b 8273 vcpu->arch.apf.halted = false;
a4fa1635 8274 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8275}
8276
8277bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8278{
8279 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8280 return true;
8281 else
8282 return !kvm_event_needs_reinjection(vcpu) &&
8283 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8284}
8285
5544eb9b
PB		 8286void kvm_arch_start_assignment(struct kvm *kvm)
8287{
8288 atomic_inc(&kvm->arch.assigned_device_count);
8289}
8290EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8291
8292void kvm_arch_end_assignment(struct kvm *kvm)
8293{
8294 atomic_dec(&kvm->arch.assigned_device_count);
8295}
8296EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8297
8298bool kvm_arch_has_assigned_device(struct kvm *kvm)
8299{
8300 return atomic_read(&kvm->arch.assigned_device_count);
8301}
8302EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8303
e0f0bbc5
AW		 8304void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8305{
8306 atomic_inc(&kvm->arch.noncoherent_dma_count);
8307}
8308EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8309
8310void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8311{
8312 atomic_dec(&kvm->arch.noncoherent_dma_count);
8313}
8314EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8315
8316bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8317{
8318 return atomic_read(&kvm->arch.noncoherent_dma_count);
8319}
8320EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8321
87276880
FW		 8322int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8323 struct irq_bypass_producer *prod)
8324{
8325 struct kvm_kernel_irqfd *irqfd =
8326 container_of(cons, struct kvm_kernel_irqfd, consumer);
8327
8328 if (kvm_x86_ops->update_pi_irte) {
8329 irqfd->producer = prod;
8330 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8331 prod->irq, irqfd->gsi, 1);
8332 }
8333
8334 return -EINVAL;
8335}
8336
8337void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8338 struct irq_bypass_producer *prod)
8339{
8340 int ret;
8341 struct kvm_kernel_irqfd *irqfd =
8342 container_of(cons, struct kvm_kernel_irqfd, consumer);
8343
8344 if (!kvm_x86_ops->update_pi_irte) {
8345 WARN_ON(irqfd->producer != NULL);
8346 return;
8347 }
8348
8349 WARN_ON(irqfd->producer != prod);
8350 irqfd->producer = NULL;
8351
8352 /*
8353 * When producer of consumer is unregistered, we change back to
8354 * remapped mode, so we can re-use the current implementation
8355 * when the irq is masked/disabed or the consumer side (KVM
8356 * int this case doesn't want to receive the interrupts.
8357 */
8358 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8359 if (ret)
8360 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8361 " fails: %d\n", irqfd->consumer.token, ret);
8362}
8363
8364int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8365 uint32_t guest_irq, bool set)
8366{
8367 if (!kvm_x86_ops->update_pi_irte)
8368 return -EINVAL;
8369
8370 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8371}
8372
229456fc 8373EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8374EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8375EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8376EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8377EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8378EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8379EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8380EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8381EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8382EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8383EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8384EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8385EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8386EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8387EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8388EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8389EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux kernel - Deliverables
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