Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
313a3dc7 | 29 | |
18068523 | 30 | #include <linux/clocksource.h> |
4d5c5d0f | 31 | #include <linux/interrupt.h> |
313a3dc7 CO |
32 | #include <linux/kvm.h> |
33 | #include <linux/fs.h> | |
34 | #include <linux/vmalloc.h> | |
5fb76f9b | 35 | #include <linux/module.h> |
0de10343 | 36 | #include <linux/mman.h> |
2bacc55c | 37 | #include <linux/highmem.h> |
19de40a8 | 38 | #include <linux/iommu.h> |
62c476c7 | 39 | #include <linux/intel-iommu.h> |
c8076604 | 40 | #include <linux/cpufreq.h> |
18863bdd | 41 | #include <linux/user-return-notifier.h> |
a983fb23 | 42 | #include <linux/srcu.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
ff9d07a0 | 44 | #include <linux/perf_event.h> |
7bee342a | 45 | #include <linux/uaccess.h> |
af585b92 | 46 | #include <linux/hash.h> |
aec51dc4 | 47 | #include <trace/events/kvm.h> |
2ed152af | 48 | |
229456fc MT |
49 | #define CREATE_TRACE_POINTS |
50 | #include "trace.h" | |
043405e1 | 51 | |
24f1e32c | 52 | #include <asm/debugreg.h> |
d825ed0a | 53 | #include <asm/msr.h> |
a5f61300 | 54 | #include <asm/desc.h> |
0bed3b56 | 55 | #include <asm/mtrr.h> |
890ca9ae | 56 | #include <asm/mce.h> |
7cf30855 | 57 | #include <asm/i387.h> |
98918833 | 58 | #include <asm/xcr.h> |
1d5f066e | 59 | #include <asm/pvclock.h> |
217fc9cf | 60 | #include <asm/div64.h> |
043405e1 | 61 | |
313a3dc7 | 62 | #define MAX_IO_MSRS 256 |
a03490ed CO |
63 | #define CR0_RESERVED_BITS \ |
64 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
65 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
66 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
67 | #define CR4_RESERVED_BITS \ | |
68 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
69 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
70 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
2acf923e | 71 | | X86_CR4_OSXSAVE \ |
a03490ed CO |
72 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
73 | ||
74 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
75 | |
76 | #define KVM_MAX_MCE_BANKS 32 | |
5854dbca | 77 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 78 | |
50a37eb4 JR |
79 | /* EFER defaults: |
80 | * - enable syscall per default because its emulated by KVM | |
81 | * - enable LME and LMA per default on 64 bit KVM | |
82 | */ | |
83 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
84 | static |
85 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 86 | #else |
1260edbe | 87 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 88 | #endif |
313a3dc7 | 89 | |
ba1389b7 AK |
90 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
91 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 92 | |
cb142eb7 | 93 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
94 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
95 | struct kvm_cpuid_entry2 __user *entries); | |
96 | ||
97896d04 | 97 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 98 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 99 | |
ed85c068 AP |
100 | int ignore_msrs = 0; |
101 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
102 | ||
18863bdd AK |
103 | #define KVM_NR_SHARED_MSRS 16 |
104 | ||
105 | struct kvm_shared_msrs_global { | |
106 | int nr; | |
2bf78fa7 | 107 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
108 | }; |
109 | ||
110 | struct kvm_shared_msrs { | |
111 | struct user_return_notifier urn; | |
112 | bool registered; | |
2bf78fa7 SY |
113 | struct kvm_shared_msr_values { |
114 | u64 host; | |
115 | u64 curr; | |
116 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
117 | }; |
118 | ||
119 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
120 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
121 | ||
417bc304 | 122 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
123 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
124 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
125 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
126 | { "invlpg", VCPU_STAT(invlpg) }, | |
127 | { "exits", VCPU_STAT(exits) }, | |
128 | { "io_exits", VCPU_STAT(io_exits) }, | |
129 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
130 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
131 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 132 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
133 | { "halt_exits", VCPU_STAT(halt_exits) }, |
134 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 135 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
136 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
137 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
138 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
139 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
140 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
141 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
142 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 143 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 144 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
145 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
146 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
147 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
148 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
149 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
150 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 151 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 152 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 153 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 154 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
155 | { NULL } |
156 | }; | |
157 | ||
2acf923e DC |
158 | u64 __read_mostly host_xcr0; |
159 | ||
af585b92 GN |
160 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
161 | { | |
162 | int i; | |
163 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
164 | vcpu->arch.apf.gfns[i] = ~0; | |
165 | } | |
166 | ||
18863bdd AK |
167 | static void kvm_on_user_return(struct user_return_notifier *urn) |
168 | { | |
169 | unsigned slot; | |
18863bdd AK |
170 | struct kvm_shared_msrs *locals |
171 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 172 | struct kvm_shared_msr_values *values; |
18863bdd AK |
173 | |
174 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
175 | values = &locals->values[slot]; |
176 | if (values->host != values->curr) { | |
177 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
178 | values->curr = values->host; | |
18863bdd AK |
179 | } |
180 | } | |
181 | locals->registered = false; | |
182 | user_return_notifier_unregister(urn); | |
183 | } | |
184 | ||
2bf78fa7 | 185 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 186 | { |
2bf78fa7 | 187 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
188 | u64 value; |
189 | ||
2bf78fa7 SY |
190 | smsr = &__get_cpu_var(shared_msrs); |
191 | /* only read, and nobody should modify it at this time, | |
192 | * so don't need lock */ | |
193 | if (slot >= shared_msrs_global.nr) { | |
194 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
195 | return; | |
196 | } | |
197 | rdmsrl_safe(msr, &value); | |
198 | smsr->values[slot].host = value; | |
199 | smsr->values[slot].curr = value; | |
200 | } | |
201 | ||
202 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
203 | { | |
18863bdd AK |
204 | if (slot >= shared_msrs_global.nr) |
205 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
206 | shared_msrs_global.msrs[slot] = msr; |
207 | /* we need ensured the shared_msr_global have been updated */ | |
208 | smp_wmb(); | |
18863bdd AK |
209 | } |
210 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
211 | ||
212 | static void kvm_shared_msr_cpu_online(void) | |
213 | { | |
214 | unsigned i; | |
18863bdd AK |
215 | |
216 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 217 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
218 | } |
219 | ||
d5696725 | 220 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
221 | { |
222 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
223 | ||
2bf78fa7 | 224 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 225 | return; |
2bf78fa7 SY |
226 | smsr->values[slot].curr = value; |
227 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
228 | if (!smsr->registered) { |
229 | smsr->urn.on_user_return = kvm_on_user_return; | |
230 | user_return_notifier_register(&smsr->urn); | |
231 | smsr->registered = true; | |
232 | } | |
233 | } | |
234 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
235 | ||
3548bab5 AK |
236 | static void drop_user_return_notifiers(void *ignore) |
237 | { | |
238 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
239 | ||
240 | if (smsr->registered) | |
241 | kvm_on_user_return(&smsr->urn); | |
242 | } | |
243 | ||
6866b83e CO |
244 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
245 | { | |
246 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 247 | return vcpu->arch.apic_base; |
6866b83e | 248 | else |
ad312c7c | 249 | return vcpu->arch.apic_base; |
6866b83e CO |
250 | } |
251 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
252 | ||
253 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
254 | { | |
255 | /* TODO: reserve bits check */ | |
256 | if (irqchip_in_kernel(vcpu->kvm)) | |
257 | kvm_lapic_set_base(vcpu, data); | |
258 | else | |
ad312c7c | 259 | vcpu->arch.apic_base = data; |
6866b83e CO |
260 | } |
261 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
262 | ||
3fd28fce ED |
263 | #define EXCPT_BENIGN 0 |
264 | #define EXCPT_CONTRIBUTORY 1 | |
265 | #define EXCPT_PF 2 | |
266 | ||
267 | static int exception_class(int vector) | |
268 | { | |
269 | switch (vector) { | |
270 | case PF_VECTOR: | |
271 | return EXCPT_PF; | |
272 | case DE_VECTOR: | |
273 | case TS_VECTOR: | |
274 | case NP_VECTOR: | |
275 | case SS_VECTOR: | |
276 | case GP_VECTOR: | |
277 | return EXCPT_CONTRIBUTORY; | |
278 | default: | |
279 | break; | |
280 | } | |
281 | return EXCPT_BENIGN; | |
282 | } | |
283 | ||
284 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
285 | unsigned nr, bool has_error, u32 error_code, |
286 | bool reinject) | |
3fd28fce ED |
287 | { |
288 | u32 prev_nr; | |
289 | int class1, class2; | |
290 | ||
3842d135 AK |
291 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
292 | ||
3fd28fce ED |
293 | if (!vcpu->arch.exception.pending) { |
294 | queue: | |
295 | vcpu->arch.exception.pending = true; | |
296 | vcpu->arch.exception.has_error_code = has_error; | |
297 | vcpu->arch.exception.nr = nr; | |
298 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 299 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
300 | return; |
301 | } | |
302 | ||
303 | /* to check exception */ | |
304 | prev_nr = vcpu->arch.exception.nr; | |
305 | if (prev_nr == DF_VECTOR) { | |
306 | /* triple fault -> shutdown */ | |
a8eeb04a | 307 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
308 | return; |
309 | } | |
310 | class1 = exception_class(prev_nr); | |
311 | class2 = exception_class(nr); | |
312 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
313 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
314 | /* generate double fault per SDM Table 5-5 */ | |
315 | vcpu->arch.exception.pending = true; | |
316 | vcpu->arch.exception.has_error_code = true; | |
317 | vcpu->arch.exception.nr = DF_VECTOR; | |
318 | vcpu->arch.exception.error_code = 0; | |
319 | } else | |
320 | /* replace previous exception with a new one in a hope | |
321 | that instruction re-execution will regenerate lost | |
322 | exception */ | |
323 | goto queue; | |
324 | } | |
325 | ||
298101da AK |
326 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
327 | { | |
ce7ddec4 | 328 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
329 | } |
330 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
331 | ||
ce7ddec4 JR |
332 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
333 | { | |
334 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
335 | } | |
336 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
337 | ||
db8fcefa | 338 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 339 | { |
db8fcefa AP |
340 | if (err) |
341 | kvm_inject_gp(vcpu, 0); | |
342 | else | |
343 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
344 | } | |
345 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 346 | |
6389ee94 | 347 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
348 | { |
349 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
350 | vcpu->arch.cr2 = fault->address; |
351 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee AK |
352 | } |
353 | ||
6389ee94 | 354 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 355 | { |
6389ee94 AK |
356 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
357 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 358 | else |
6389ee94 | 359 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
d4f8cf66 JR |
360 | } |
361 | ||
3419ffc8 SY |
362 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
363 | { | |
3842d135 | 364 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c761e586 | 365 | vcpu->arch.nmi_pending = 1; |
3419ffc8 SY |
366 | } |
367 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
368 | ||
298101da AK |
369 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
370 | { | |
ce7ddec4 | 371 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
372 | } |
373 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
374 | ||
ce7ddec4 JR |
375 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
376 | { | |
377 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
378 | } | |
379 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
380 | ||
0a79b009 AK |
381 | /* |
382 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
383 | * a #GP and return false. | |
384 | */ | |
385 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 386 | { |
0a79b009 AK |
387 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
388 | return true; | |
389 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
390 | return false; | |
298101da | 391 | } |
0a79b009 | 392 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 393 | |
ec92fe44 JR |
394 | /* |
395 | * This function will be used to read from the physical memory of the currently | |
396 | * running guest. The difference to kvm_read_guest_page is that this function | |
397 | * can read from guest physical or from the guest's guest physical memory. | |
398 | */ | |
399 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
400 | gfn_t ngfn, void *data, int offset, int len, | |
401 | u32 access) | |
402 | { | |
403 | gfn_t real_gfn; | |
404 | gpa_t ngpa; | |
405 | ||
406 | ngpa = gfn_to_gpa(ngfn); | |
407 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access); | |
408 | if (real_gfn == UNMAPPED_GVA) | |
409 | return -EFAULT; | |
410 | ||
411 | real_gfn = gpa_to_gfn(real_gfn); | |
412 | ||
413 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
414 | } | |
415 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
416 | ||
3d06b8bf JR |
417 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
418 | void *data, int offset, int len, u32 access) | |
419 | { | |
420 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
421 | data, offset, len, access); | |
422 | } | |
423 | ||
a03490ed CO |
424 | /* |
425 | * Load the pae pdptrs. Return true is they are all valid. | |
426 | */ | |
ff03a073 | 427 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
428 | { |
429 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
430 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
431 | int i; | |
432 | int ret; | |
ff03a073 | 433 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 434 | |
ff03a073 JR |
435 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
436 | offset * sizeof(u64), sizeof(pdpte), | |
437 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
438 | if (ret < 0) { |
439 | ret = 0; | |
440 | goto out; | |
441 | } | |
442 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 443 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 444 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
445 | ret = 0; |
446 | goto out; | |
447 | } | |
448 | } | |
449 | ret = 1; | |
450 | ||
ff03a073 | 451 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
452 | __set_bit(VCPU_EXREG_PDPTR, |
453 | (unsigned long *)&vcpu->arch.regs_avail); | |
454 | __set_bit(VCPU_EXREG_PDPTR, | |
455 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 456 | out: |
a03490ed CO |
457 | |
458 | return ret; | |
459 | } | |
cc4b6871 | 460 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 461 | |
d835dfec AK |
462 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
463 | { | |
ff03a073 | 464 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 465 | bool changed = true; |
3d06b8bf JR |
466 | int offset; |
467 | gfn_t gfn; | |
d835dfec AK |
468 | int r; |
469 | ||
470 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
471 | return false; | |
472 | ||
6de4f3ad AK |
473 | if (!test_bit(VCPU_EXREG_PDPTR, |
474 | (unsigned long *)&vcpu->arch.regs_avail)) | |
475 | return true; | |
476 | ||
9f8fe504 AK |
477 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
478 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
479 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
480 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
481 | if (r < 0) |
482 | goto out; | |
ff03a073 | 483 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 484 | out: |
d835dfec AK |
485 | |
486 | return changed; | |
487 | } | |
488 | ||
49a9b07e | 489 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 490 | { |
aad82703 SY |
491 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
492 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
493 | X86_CR0_CD | X86_CR0_NW; | |
494 | ||
f9a48e6a AK |
495 | cr0 |= X86_CR0_ET; |
496 | ||
ab344828 | 497 | #ifdef CONFIG_X86_64 |
0f12244f GN |
498 | if (cr0 & 0xffffffff00000000UL) |
499 | return 1; | |
ab344828 GN |
500 | #endif |
501 | ||
502 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 503 | |
0f12244f GN |
504 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
505 | return 1; | |
a03490ed | 506 | |
0f12244f GN |
507 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
508 | return 1; | |
a03490ed CO |
509 | |
510 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
511 | #ifdef CONFIG_X86_64 | |
f6801dff | 512 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
513 | int cs_db, cs_l; |
514 | ||
0f12244f GN |
515 | if (!is_pae(vcpu)) |
516 | return 1; | |
a03490ed | 517 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
518 | if (cs_l) |
519 | return 1; | |
a03490ed CO |
520 | } else |
521 | #endif | |
ff03a073 | 522 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 523 | kvm_read_cr3(vcpu))) |
0f12244f | 524 | return 1; |
a03490ed CO |
525 | } |
526 | ||
527 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
a03490ed | 528 | |
d170c419 | 529 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 530 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
531 | kvm_async_pf_hash_reset(vcpu); |
532 | } | |
e5f3f027 | 533 | |
aad82703 SY |
534 | if ((cr0 ^ old_cr0) & update_bits) |
535 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
536 | return 0; |
537 | } | |
2d3ad1f4 | 538 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 539 | |
2d3ad1f4 | 540 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 541 | { |
49a9b07e | 542 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 543 | } |
2d3ad1f4 | 544 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 545 | |
2acf923e DC |
546 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
547 | { | |
548 | u64 xcr0; | |
549 | ||
550 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
551 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
552 | return 1; | |
553 | xcr0 = xcr; | |
554 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
555 | return 1; | |
556 | if (!(xcr0 & XSTATE_FP)) | |
557 | return 1; | |
558 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
559 | return 1; | |
560 | if (xcr0 & ~host_xcr0) | |
561 | return 1; | |
562 | vcpu->arch.xcr0 = xcr0; | |
563 | vcpu->guest_xcr0_loaded = 0; | |
564 | return 0; | |
565 | } | |
566 | ||
567 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
568 | { | |
569 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
570 | kvm_inject_gp(vcpu, 0); | |
571 | return 1; | |
572 | } | |
573 | return 0; | |
574 | } | |
575 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
576 | ||
577 | static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu) | |
578 | { | |
579 | struct kvm_cpuid_entry2 *best; | |
580 | ||
581 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
582 | return best && (best->ecx & bit(X86_FEATURE_XSAVE)); | |
583 | } | |
584 | ||
585 | static void update_cpuid(struct kvm_vcpu *vcpu) | |
586 | { | |
587 | struct kvm_cpuid_entry2 *best; | |
588 | ||
589 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
590 | if (!best) | |
591 | return; | |
592 | ||
593 | /* Update OSXSAVE bit */ | |
594 | if (cpu_has_xsave && best->function == 0x1) { | |
595 | best->ecx &= ~(bit(X86_FEATURE_OSXSAVE)); | |
596 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) | |
597 | best->ecx |= bit(X86_FEATURE_OSXSAVE); | |
598 | } | |
599 | } | |
600 | ||
a83b29c6 | 601 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 602 | { |
fc78f519 | 603 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
a2edf57f AK |
604 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; |
605 | ||
0f12244f GN |
606 | if (cr4 & CR4_RESERVED_BITS) |
607 | return 1; | |
a03490ed | 608 | |
2acf923e DC |
609 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
610 | return 1; | |
611 | ||
a03490ed | 612 | if (is_long_mode(vcpu)) { |
0f12244f GN |
613 | if (!(cr4 & X86_CR4_PAE)) |
614 | return 1; | |
a2edf57f AK |
615 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
616 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
617 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
618 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
619 | return 1; |
620 | ||
621 | if (cr4 & X86_CR4_VMXE) | |
622 | return 1; | |
a03490ed | 623 | |
a03490ed | 624 | kvm_x86_ops->set_cr4(vcpu, cr4); |
62ad0755 | 625 | |
aad82703 SY |
626 | if ((cr4 ^ old_cr4) & pdptr_bits) |
627 | kvm_mmu_reset_context(vcpu); | |
0f12244f | 628 | |
2acf923e DC |
629 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
630 | update_cpuid(vcpu); | |
631 | ||
0f12244f GN |
632 | return 0; |
633 | } | |
2d3ad1f4 | 634 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 635 | |
2390218b | 636 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 637 | { |
9f8fe504 | 638 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 639 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 640 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 641 | return 0; |
d835dfec AK |
642 | } |
643 | ||
a03490ed | 644 | if (is_long_mode(vcpu)) { |
0f12244f GN |
645 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
646 | return 1; | |
a03490ed CO |
647 | } else { |
648 | if (is_pae(vcpu)) { | |
0f12244f GN |
649 | if (cr3 & CR3_PAE_RESERVED_BITS) |
650 | return 1; | |
ff03a073 JR |
651 | if (is_paging(vcpu) && |
652 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
0f12244f | 653 | return 1; |
a03490ed CO |
654 | } |
655 | /* | |
656 | * We don't check reserved bits in nonpae mode, because | |
657 | * this isn't enforced, and VMware depends on this. | |
658 | */ | |
659 | } | |
660 | ||
a03490ed CO |
661 | /* |
662 | * Does the new cr3 value map to physical memory? (Note, we | |
663 | * catch an invalid cr3 even in real-mode, because it would | |
664 | * cause trouble later on when we turn on paging anyway.) | |
665 | * | |
666 | * A real CPU would silently accept an invalid cr3 and would | |
667 | * attempt to use it - with largely undefined (and often hard | |
668 | * to debug) behavior on the guest side. | |
669 | */ | |
670 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
671 | return 1; |
672 | vcpu->arch.cr3 = cr3; | |
aff48baa | 673 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
0f12244f GN |
674 | vcpu->arch.mmu.new_cr3(vcpu); |
675 | return 0; | |
676 | } | |
2d3ad1f4 | 677 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 678 | |
eea1cff9 | 679 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 680 | { |
0f12244f GN |
681 | if (cr8 & CR8_RESERVED_BITS) |
682 | return 1; | |
a03490ed CO |
683 | if (irqchip_in_kernel(vcpu->kvm)) |
684 | kvm_lapic_set_tpr(vcpu, cr8); | |
685 | else | |
ad312c7c | 686 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
687 | return 0; |
688 | } | |
2d3ad1f4 | 689 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 690 | |
2d3ad1f4 | 691 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
692 | { |
693 | if (irqchip_in_kernel(vcpu->kvm)) | |
694 | return kvm_lapic_get_cr8(vcpu); | |
695 | else | |
ad312c7c | 696 | return vcpu->arch.cr8; |
a03490ed | 697 | } |
2d3ad1f4 | 698 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 699 | |
338dbc97 | 700 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
701 | { |
702 | switch (dr) { | |
703 | case 0 ... 3: | |
704 | vcpu->arch.db[dr] = val; | |
705 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
706 | vcpu->arch.eff_db[dr] = val; | |
707 | break; | |
708 | case 4: | |
338dbc97 GN |
709 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
710 | return 1; /* #UD */ | |
020df079 GN |
711 | /* fall through */ |
712 | case 6: | |
338dbc97 GN |
713 | if (val & 0xffffffff00000000ULL) |
714 | return -1; /* #GP */ | |
020df079 GN |
715 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
716 | break; | |
717 | case 5: | |
338dbc97 GN |
718 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
719 | return 1; /* #UD */ | |
020df079 GN |
720 | /* fall through */ |
721 | default: /* 7 */ | |
338dbc97 GN |
722 | if (val & 0xffffffff00000000ULL) |
723 | return -1; /* #GP */ | |
020df079 GN |
724 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
725 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
726 | kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7); | |
727 | vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK); | |
728 | } | |
729 | break; | |
730 | } | |
731 | ||
732 | return 0; | |
733 | } | |
338dbc97 GN |
734 | |
735 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
736 | { | |
737 | int res; | |
738 | ||
739 | res = __kvm_set_dr(vcpu, dr, val); | |
740 | if (res > 0) | |
741 | kvm_queue_exception(vcpu, UD_VECTOR); | |
742 | else if (res < 0) | |
743 | kvm_inject_gp(vcpu, 0); | |
744 | ||
745 | return res; | |
746 | } | |
020df079 GN |
747 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
748 | ||
338dbc97 | 749 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
750 | { |
751 | switch (dr) { | |
752 | case 0 ... 3: | |
753 | *val = vcpu->arch.db[dr]; | |
754 | break; | |
755 | case 4: | |
338dbc97 | 756 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 757 | return 1; |
020df079 GN |
758 | /* fall through */ |
759 | case 6: | |
760 | *val = vcpu->arch.dr6; | |
761 | break; | |
762 | case 5: | |
338dbc97 | 763 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 764 | return 1; |
020df079 GN |
765 | /* fall through */ |
766 | default: /* 7 */ | |
767 | *val = vcpu->arch.dr7; | |
768 | break; | |
769 | } | |
770 | ||
771 | return 0; | |
772 | } | |
338dbc97 GN |
773 | |
774 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
775 | { | |
776 | if (_kvm_get_dr(vcpu, dr, val)) { | |
777 | kvm_queue_exception(vcpu, UD_VECTOR); | |
778 | return 1; | |
779 | } | |
780 | return 0; | |
781 | } | |
020df079 GN |
782 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
783 | ||
043405e1 CO |
784 | /* |
785 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
786 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
787 | * | |
788 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
789 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
790 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 791 | */ |
e3267cbb | 792 | |
344d9588 | 793 | #define KVM_SAVE_MSRS_BEGIN 8 |
043405e1 | 794 | static u32 msrs_to_save[] = { |
e3267cbb | 795 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 796 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 797 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
344d9588 | 798 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, |
043405e1 | 799 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 800 | MSR_STAR, |
043405e1 CO |
801 | #ifdef CONFIG_X86_64 |
802 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
803 | #endif | |
e90aa41e | 804 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
805 | }; |
806 | ||
807 | static unsigned num_msrs_to_save; | |
808 | ||
809 | static u32 emulated_msrs[] = { | |
810 | MSR_IA32_MISC_ENABLE, | |
908e75f3 AK |
811 | MSR_IA32_MCG_STATUS, |
812 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
813 | }; |
814 | ||
b69e8cae | 815 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 816 | { |
aad82703 SY |
817 | u64 old_efer = vcpu->arch.efer; |
818 | ||
b69e8cae RJ |
819 | if (efer & efer_reserved_bits) |
820 | return 1; | |
15c4a640 CO |
821 | |
822 | if (is_paging(vcpu) | |
b69e8cae RJ |
823 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) |
824 | return 1; | |
15c4a640 | 825 | |
1b2fd70c AG |
826 | if (efer & EFER_FFXSR) { |
827 | struct kvm_cpuid_entry2 *feat; | |
828 | ||
829 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
830 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
831 | return 1; | |
1b2fd70c AG |
832 | } |
833 | ||
d8017474 AG |
834 | if (efer & EFER_SVME) { |
835 | struct kvm_cpuid_entry2 *feat; | |
836 | ||
837 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
838 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
839 | return 1; | |
d8017474 AG |
840 | } |
841 | ||
15c4a640 | 842 | efer &= ~EFER_LMA; |
f6801dff | 843 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 844 | |
a3d204e2 SY |
845 | kvm_x86_ops->set_efer(vcpu, efer); |
846 | ||
9645bb56 | 847 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; |
b69e8cae | 848 | |
aad82703 SY |
849 | /* Update reserved bits */ |
850 | if ((efer ^ old_efer) & EFER_NX) | |
851 | kvm_mmu_reset_context(vcpu); | |
852 | ||
b69e8cae | 853 | return 0; |
15c4a640 CO |
854 | } |
855 | ||
f2b4b7dd JR |
856 | void kvm_enable_efer_bits(u64 mask) |
857 | { | |
858 | efer_reserved_bits &= ~mask; | |
859 | } | |
860 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
861 | ||
862 | ||
15c4a640 CO |
863 | /* |
864 | * Writes msr value into into the appropriate "register". | |
865 | * Returns 0 on success, non-0 otherwise. | |
866 | * Assumes vcpu_load() was already called. | |
867 | */ | |
868 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
869 | { | |
870 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
871 | } | |
872 | ||
313a3dc7 CO |
873 | /* |
874 | * Adapt set_msr() to msr_io()'s calling convention | |
875 | */ | |
876 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
877 | { | |
878 | return kvm_set_msr(vcpu, index, *data); | |
879 | } | |
880 | ||
18068523 GOC |
881 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
882 | { | |
9ed3c444 AK |
883 | int version; |
884 | int r; | |
50d0a0f9 | 885 | struct pvclock_wall_clock wc; |
923de3cf | 886 | struct timespec boot; |
18068523 GOC |
887 | |
888 | if (!wall_clock) | |
889 | return; | |
890 | ||
9ed3c444 AK |
891 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
892 | if (r) | |
893 | return; | |
894 | ||
895 | if (version & 1) | |
896 | ++version; /* first time write, random junk */ | |
897 | ||
898 | ++version; | |
18068523 | 899 | |
18068523 GOC |
900 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
901 | ||
50d0a0f9 GH |
902 | /* |
903 | * The guest calculates current wall clock time by adding | |
34c238a1 | 904 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
905 | * wall clock specified here. guest system time equals host |
906 | * system time for us, thus we must fill in host boot time here. | |
907 | */ | |
923de3cf | 908 | getboottime(&boot); |
50d0a0f9 GH |
909 | |
910 | wc.sec = boot.tv_sec; | |
911 | wc.nsec = boot.tv_nsec; | |
912 | wc.version = version; | |
18068523 GOC |
913 | |
914 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
915 | ||
916 | version++; | |
917 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
918 | } |
919 | ||
50d0a0f9 GH |
920 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
921 | { | |
922 | uint32_t quotient, remainder; | |
923 | ||
924 | /* Don't try to replace with do_div(), this one calculates | |
925 | * "(dividend << 32) / divisor" */ | |
926 | __asm__ ( "divl %4" | |
927 | : "=a" (quotient), "=d" (remainder) | |
928 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
929 | return quotient; | |
930 | } | |
931 | ||
5f4e3f88 ZA |
932 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
933 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 934 | { |
5f4e3f88 | 935 | uint64_t scaled64; |
50d0a0f9 GH |
936 | int32_t shift = 0; |
937 | uint64_t tps64; | |
938 | uint32_t tps32; | |
939 | ||
5f4e3f88 ZA |
940 | tps64 = base_khz * 1000LL; |
941 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 942 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
943 | tps64 >>= 1; |
944 | shift--; | |
945 | } | |
946 | ||
947 | tps32 = (uint32_t)tps64; | |
50933623 JK |
948 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
949 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
950 | scaled64 >>= 1; |
951 | else | |
952 | tps32 <<= 1; | |
50d0a0f9 GH |
953 | shift++; |
954 | } | |
955 | ||
5f4e3f88 ZA |
956 | *pshift = shift; |
957 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 958 | |
5f4e3f88 ZA |
959 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
960 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
961 | } |
962 | ||
759379dd ZA |
963 | static inline u64 get_kernel_ns(void) |
964 | { | |
965 | struct timespec ts; | |
966 | ||
967 | WARN_ON(preemptible()); | |
968 | ktime_get_ts(&ts); | |
969 | monotonic_to_bootbased(&ts); | |
970 | return timespec_to_ns(&ts); | |
50d0a0f9 GH |
971 | } |
972 | ||
c8076604 | 973 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
c285545f | 974 | unsigned long max_tsc_khz; |
c8076604 | 975 | |
8cfdc000 ZA |
976 | static inline int kvm_tsc_changes_freq(void) |
977 | { | |
978 | int cpu = get_cpu(); | |
979 | int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && | |
980 | cpufreq_quick_get(cpu) != 0; | |
981 | put_cpu(); | |
982 | return ret; | |
983 | } | |
984 | ||
759379dd ZA |
985 | static inline u64 nsec_to_cycles(u64 nsec) |
986 | { | |
217fc9cf AK |
987 | u64 ret; |
988 | ||
759379dd ZA |
989 | WARN_ON(preemptible()); |
990 | if (kvm_tsc_changes_freq()) | |
991 | printk_once(KERN_WARNING | |
992 | "kvm: unreliable cycle conversion on adjustable rate TSC\n"); | |
0a3aee0d | 993 | ret = nsec * __this_cpu_read(cpu_tsc_khz); |
217fc9cf AK |
994 | do_div(ret, USEC_PER_SEC); |
995 | return ret; | |
759379dd ZA |
996 | } |
997 | ||
c285545f ZA |
998 | static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz) |
999 | { | |
1000 | /* Compute a scale to convert nanoseconds in TSC cycles */ | |
1001 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
1002 | &kvm->arch.virtual_tsc_shift, | |
1003 | &kvm->arch.virtual_tsc_mult); | |
1004 | kvm->arch.virtual_tsc_khz = this_tsc_khz; | |
1005 | } | |
1006 | ||
1007 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1008 | { | |
1009 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec, | |
1010 | vcpu->kvm->arch.virtual_tsc_mult, | |
1011 | vcpu->kvm->arch.virtual_tsc_shift); | |
1012 | tsc += vcpu->arch.last_tsc_write; | |
1013 | return tsc; | |
1014 | } | |
1015 | ||
99e3e30a ZA |
1016 | void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data) |
1017 | { | |
1018 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1019 | u64 offset, ns, elapsed; |
99e3e30a | 1020 | unsigned long flags; |
46543ba4 | 1021 | s64 sdiff; |
99e3e30a | 1022 | |
038f8c11 | 1023 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
99e3e30a | 1024 | offset = data - native_read_tsc(); |
759379dd | 1025 | ns = get_kernel_ns(); |
f38e098f | 1026 | elapsed = ns - kvm->arch.last_tsc_nsec; |
46543ba4 ZA |
1027 | sdiff = data - kvm->arch.last_tsc_write; |
1028 | if (sdiff < 0) | |
1029 | sdiff = -sdiff; | |
f38e098f ZA |
1030 | |
1031 | /* | |
46543ba4 | 1032 | * Special case: close write to TSC within 5 seconds of |
f38e098f | 1033 | * another CPU is interpreted as an attempt to synchronize |
0d2eb44f | 1034 | * The 5 seconds is to accommodate host load / swapping as |
46543ba4 | 1035 | * well as any reset of TSC during the boot process. |
f38e098f ZA |
1036 | * |
1037 | * In that case, for a reliable TSC, we can match TSC offsets, | |
46543ba4 | 1038 | * or make a best guest using elapsed value. |
f38e098f | 1039 | */ |
46543ba4 ZA |
1040 | if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) && |
1041 | elapsed < 5ULL * NSEC_PER_SEC) { | |
f38e098f ZA |
1042 | if (!check_tsc_unstable()) { |
1043 | offset = kvm->arch.last_tsc_offset; | |
1044 | pr_debug("kvm: matched tsc offset for %llu\n", data); | |
1045 | } else { | |
759379dd ZA |
1046 | u64 delta = nsec_to_cycles(elapsed); |
1047 | offset += delta; | |
1048 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); | |
f38e098f ZA |
1049 | } |
1050 | ns = kvm->arch.last_tsc_nsec; | |
1051 | } | |
1052 | kvm->arch.last_tsc_nsec = ns; | |
1053 | kvm->arch.last_tsc_write = data; | |
1054 | kvm->arch.last_tsc_offset = offset; | |
99e3e30a | 1055 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
038f8c11 | 1056 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
99e3e30a ZA |
1057 | |
1058 | /* Reset of TSC must disable overshoot protection below */ | |
1059 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
c285545f ZA |
1060 | vcpu->arch.last_tsc_write = data; |
1061 | vcpu->arch.last_tsc_nsec = ns; | |
99e3e30a ZA |
1062 | } |
1063 | EXPORT_SYMBOL_GPL(kvm_write_tsc); | |
1064 | ||
34c238a1 | 1065 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1066 | { |
18068523 GOC |
1067 | unsigned long flags; |
1068 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1069 | void *shared_kaddr; | |
463656c0 | 1070 | unsigned long this_tsc_khz; |
1d5f066e ZA |
1071 | s64 kernel_ns, max_kernel_ns; |
1072 | u64 tsc_timestamp; | |
18068523 | 1073 | |
18068523 GOC |
1074 | /* Keep irq disabled to prevent changes to the clock */ |
1075 | local_irq_save(flags); | |
1d5f066e | 1076 | kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp); |
759379dd | 1077 | kernel_ns = get_kernel_ns(); |
0a3aee0d | 1078 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
18068523 | 1079 | |
8cfdc000 | 1080 | if (unlikely(this_tsc_khz == 0)) { |
c285545f | 1081 | local_irq_restore(flags); |
34c238a1 | 1082 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
8cfdc000 ZA |
1083 | return 1; |
1084 | } | |
18068523 | 1085 | |
c285545f ZA |
1086 | /* |
1087 | * We may have to catch up the TSC to match elapsed wall clock | |
1088 | * time for two reasons, even if kvmclock is used. | |
1089 | * 1) CPU could have been running below the maximum TSC rate | |
1090 | * 2) Broken TSC compensation resets the base at each VCPU | |
1091 | * entry to avoid unknown leaps of TSC even when running | |
1092 | * again on the same CPU. This may cause apparent elapsed | |
1093 | * time to disappear, and the guest to stand still or run | |
1094 | * very slowly. | |
1095 | */ | |
1096 | if (vcpu->tsc_catchup) { | |
1097 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1098 | if (tsc > tsc_timestamp) { | |
1099 | kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp); | |
1100 | tsc_timestamp = tsc; | |
1101 | } | |
50d0a0f9 GH |
1102 | } |
1103 | ||
18068523 GOC |
1104 | local_irq_restore(flags); |
1105 | ||
c285545f ZA |
1106 | if (!vcpu->time_page) |
1107 | return 0; | |
18068523 | 1108 | |
1d5f066e ZA |
1109 | /* |
1110 | * Time as measured by the TSC may go backwards when resetting the base | |
1111 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1112 | * higher than the resolution of the other clock scales. Thus, many | |
1113 | * possible measurments of the TSC correspond to one measurement of any | |
1114 | * other clock, and so a spread of values is possible. This is not a | |
1115 | * problem for the computation of the nanosecond clock; with TSC rates | |
1116 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1117 | * nanosecond value, and any path through this code will inevitably | |
1118 | * take longer than that. However, with the kernel_ns value itself, | |
1119 | * the precision may be much lower, down to HZ granularity. If the | |
1120 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1121 | * range, and the second in the high end of the range, we can get: | |
1122 | * | |
1123 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1124 | * | |
1125 | * As the sampling errors potentially range in the thousands of cycles, | |
1126 | * it is possible such a time value has already been observed by the | |
1127 | * guest. To protect against this, we must compute the system time as | |
1128 | * observed by the guest and ensure the new system time is greater. | |
1129 | */ | |
1130 | max_kernel_ns = 0; | |
1131 | if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) { | |
1132 | max_kernel_ns = vcpu->last_guest_tsc - | |
1133 | vcpu->hv_clock.tsc_timestamp; | |
1134 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1135 | vcpu->hv_clock.tsc_to_system_mul, | |
1136 | vcpu->hv_clock.tsc_shift); | |
1137 | max_kernel_ns += vcpu->last_kernel_ns; | |
1138 | } | |
afbcf7ab | 1139 | |
e48672fa | 1140 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1141 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1142 | &vcpu->hv_clock.tsc_shift, | |
1143 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1144 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1145 | } |
1146 | ||
1d5f066e ZA |
1147 | if (max_kernel_ns > kernel_ns) |
1148 | kernel_ns = max_kernel_ns; | |
1149 | ||
8cfdc000 | 1150 | /* With all the info we got, fill in the values */ |
1d5f066e | 1151 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1152 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
1d5f066e | 1153 | vcpu->last_kernel_ns = kernel_ns; |
28e4639a | 1154 | vcpu->last_guest_tsc = tsc_timestamp; |
371bcf64 GC |
1155 | vcpu->hv_clock.flags = 0; |
1156 | ||
18068523 GOC |
1157 | /* |
1158 | * The interface expects us to write an even number signaling that the | |
1159 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1160 | * state, we just increase by 2 at the end. |
18068523 | 1161 | */ |
50d0a0f9 | 1162 | vcpu->hv_clock.version += 2; |
18068523 GOC |
1163 | |
1164 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
1165 | ||
1166 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 1167 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
1168 | |
1169 | kunmap_atomic(shared_kaddr, KM_USER0); | |
1170 | ||
1171 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
8cfdc000 | 1172 | return 0; |
c8076604 GH |
1173 | } |
1174 | ||
9ba075a6 AK |
1175 | static bool msr_mtrr_valid(unsigned msr) |
1176 | { | |
1177 | switch (msr) { | |
1178 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1179 | case MSR_MTRRfix64K_00000: | |
1180 | case MSR_MTRRfix16K_80000: | |
1181 | case MSR_MTRRfix16K_A0000: | |
1182 | case MSR_MTRRfix4K_C0000: | |
1183 | case MSR_MTRRfix4K_C8000: | |
1184 | case MSR_MTRRfix4K_D0000: | |
1185 | case MSR_MTRRfix4K_D8000: | |
1186 | case MSR_MTRRfix4K_E0000: | |
1187 | case MSR_MTRRfix4K_E8000: | |
1188 | case MSR_MTRRfix4K_F0000: | |
1189 | case MSR_MTRRfix4K_F8000: | |
1190 | case MSR_MTRRdefType: | |
1191 | case MSR_IA32_CR_PAT: | |
1192 | return true; | |
1193 | case 0x2f8: | |
1194 | return true; | |
1195 | } | |
1196 | return false; | |
1197 | } | |
1198 | ||
d6289b93 MT |
1199 | static bool valid_pat_type(unsigned t) |
1200 | { | |
1201 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1202 | } | |
1203 | ||
1204 | static bool valid_mtrr_type(unsigned t) | |
1205 | { | |
1206 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1207 | } | |
1208 | ||
1209 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1210 | { | |
1211 | int i; | |
1212 | ||
1213 | if (!msr_mtrr_valid(msr)) | |
1214 | return false; | |
1215 | ||
1216 | if (msr == MSR_IA32_CR_PAT) { | |
1217 | for (i = 0; i < 8; i++) | |
1218 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1219 | return false; | |
1220 | return true; | |
1221 | } else if (msr == MSR_MTRRdefType) { | |
1222 | if (data & ~0xcff) | |
1223 | return false; | |
1224 | return valid_mtrr_type(data & 0xff); | |
1225 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1226 | for (i = 0; i < 8 ; i++) | |
1227 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1228 | return false; | |
1229 | return true; | |
1230 | } | |
1231 | ||
1232 | /* variable MTRRs */ | |
1233 | return valid_mtrr_type(data & 0xff); | |
1234 | } | |
1235 | ||
9ba075a6 AK |
1236 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1237 | { | |
0bed3b56 SY |
1238 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1239 | ||
d6289b93 | 1240 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1241 | return 1; |
1242 | ||
0bed3b56 SY |
1243 | if (msr == MSR_MTRRdefType) { |
1244 | vcpu->arch.mtrr_state.def_type = data; | |
1245 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1246 | } else if (msr == MSR_MTRRfix64K_00000) | |
1247 | p[0] = data; | |
1248 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1249 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1250 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1251 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1252 | else if (msr == MSR_IA32_CR_PAT) | |
1253 | vcpu->arch.pat = data; | |
1254 | else { /* Variable MTRRs */ | |
1255 | int idx, is_mtrr_mask; | |
1256 | u64 *pt; | |
1257 | ||
1258 | idx = (msr - 0x200) / 2; | |
1259 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1260 | if (!is_mtrr_mask) | |
1261 | pt = | |
1262 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1263 | else | |
1264 | pt = | |
1265 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1266 | *pt = data; | |
1267 | } | |
1268 | ||
1269 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1270 | return 0; |
1271 | } | |
15c4a640 | 1272 | |
890ca9ae | 1273 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1274 | { |
890ca9ae HY |
1275 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1276 | unsigned bank_num = mcg_cap & 0xff; | |
1277 | ||
15c4a640 | 1278 | switch (msr) { |
15c4a640 | 1279 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1280 | vcpu->arch.mcg_status = data; |
15c4a640 | 1281 | break; |
c7ac679c | 1282 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1283 | if (!(mcg_cap & MCG_CTL_P)) |
1284 | return 1; | |
1285 | if (data != 0 && data != ~(u64)0) | |
1286 | return -1; | |
1287 | vcpu->arch.mcg_ctl = data; | |
1288 | break; | |
1289 | default: | |
1290 | if (msr >= MSR_IA32_MC0_CTL && | |
1291 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1292 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1293 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1294 | * some Linux kernels though clear bit 10 in bank 4 to | |
1295 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1296 | * this to avoid an uncatched #GP in the guest | |
1297 | */ | |
890ca9ae | 1298 | if ((offset & 0x3) == 0 && |
114be429 | 1299 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1300 | return -1; |
1301 | vcpu->arch.mce_banks[offset] = data; | |
1302 | break; | |
1303 | } | |
1304 | return 1; | |
1305 | } | |
1306 | return 0; | |
1307 | } | |
1308 | ||
ffde22ac ES |
1309 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1310 | { | |
1311 | struct kvm *kvm = vcpu->kvm; | |
1312 | int lm = is_long_mode(vcpu); | |
1313 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1314 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1315 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1316 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1317 | u32 page_num = data & ~PAGE_MASK; | |
1318 | u64 page_addr = data & PAGE_MASK; | |
1319 | u8 *page; | |
1320 | int r; | |
1321 | ||
1322 | r = -E2BIG; | |
1323 | if (page_num >= blob_size) | |
1324 | goto out; | |
1325 | r = -ENOMEM; | |
1326 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
1327 | if (!page) | |
1328 | goto out; | |
1329 | r = -EFAULT; | |
1330 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
1331 | goto out_free; | |
1332 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
1333 | goto out_free; | |
1334 | r = 0; | |
1335 | out_free: | |
1336 | kfree(page); | |
1337 | out: | |
1338 | return r; | |
1339 | } | |
1340 | ||
55cd8e5a GN |
1341 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1342 | { | |
1343 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1344 | } | |
1345 | ||
1346 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1347 | { | |
1348 | bool r = false; | |
1349 | switch (msr) { | |
1350 | case HV_X64_MSR_GUEST_OS_ID: | |
1351 | case HV_X64_MSR_HYPERCALL: | |
1352 | r = true; | |
1353 | break; | |
1354 | } | |
1355 | ||
1356 | return r; | |
1357 | } | |
1358 | ||
1359 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1360 | { | |
1361 | struct kvm *kvm = vcpu->kvm; | |
1362 | ||
1363 | switch (msr) { | |
1364 | case HV_X64_MSR_GUEST_OS_ID: | |
1365 | kvm->arch.hv_guest_os_id = data; | |
1366 | /* setting guest os id to zero disables hypercall page */ | |
1367 | if (!kvm->arch.hv_guest_os_id) | |
1368 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1369 | break; | |
1370 | case HV_X64_MSR_HYPERCALL: { | |
1371 | u64 gfn; | |
1372 | unsigned long addr; | |
1373 | u8 instructions[4]; | |
1374 | ||
1375 | /* if guest os id is not set hypercall should remain disabled */ | |
1376 | if (!kvm->arch.hv_guest_os_id) | |
1377 | break; | |
1378 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1379 | kvm->arch.hv_hypercall = data; | |
1380 | break; | |
1381 | } | |
1382 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1383 | addr = gfn_to_hva(kvm, gfn); | |
1384 | if (kvm_is_error_hva(addr)) | |
1385 | return 1; | |
1386 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1387 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1388 | if (copy_to_user((void __user *)addr, instructions, 4)) | |
1389 | return 1; | |
1390 | kvm->arch.hv_hypercall = data; | |
1391 | break; | |
1392 | } | |
1393 | default: | |
1394 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1395 | "data 0x%llx\n", msr, data); | |
1396 | return 1; | |
1397 | } | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1402 | { | |
10388a07 GN |
1403 | switch (msr) { |
1404 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1405 | unsigned long addr; | |
55cd8e5a | 1406 | |
10388a07 GN |
1407 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1408 | vcpu->arch.hv_vapic = data; | |
1409 | break; | |
1410 | } | |
1411 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1412 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1413 | if (kvm_is_error_hva(addr)) | |
1414 | return 1; | |
1415 | if (clear_user((void __user *)addr, PAGE_SIZE)) | |
1416 | return 1; | |
1417 | vcpu->arch.hv_vapic = data; | |
1418 | break; | |
1419 | } | |
1420 | case HV_X64_MSR_EOI: | |
1421 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1422 | case HV_X64_MSR_ICR: | |
1423 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1424 | case HV_X64_MSR_TPR: | |
1425 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1426 | default: | |
1427 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1428 | "data 0x%llx\n", msr, data); | |
1429 | return 1; | |
1430 | } | |
1431 | ||
1432 | return 0; | |
55cd8e5a GN |
1433 | } |
1434 | ||
344d9588 GN |
1435 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1436 | { | |
1437 | gpa_t gpa = data & ~0x3f; | |
1438 | ||
6adba527 GN |
1439 | /* Bits 2:5 are resrved, Should be zero */ |
1440 | if (data & 0x3c) | |
344d9588 GN |
1441 | return 1; |
1442 | ||
1443 | vcpu->arch.apf.msr_val = data; | |
1444 | ||
1445 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1446 | kvm_clear_async_pf_completion_queue(vcpu); | |
1447 | kvm_async_pf_hash_reset(vcpu); | |
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa)) | |
1452 | return 1; | |
1453 | ||
6adba527 | 1454 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1455 | kvm_async_pf_wakeup_all(vcpu); |
1456 | return 0; | |
1457 | } | |
1458 | ||
12f9a48f GC |
1459 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
1460 | { | |
1461 | if (vcpu->arch.time_page) { | |
1462 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1463 | vcpu->arch.time_page = NULL; | |
1464 | } | |
1465 | } | |
1466 | ||
15c4a640 CO |
1467 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1468 | { | |
1469 | switch (msr) { | |
15c4a640 | 1470 | case MSR_EFER: |
b69e8cae | 1471 | return set_efer(vcpu, data); |
8f1589d9 AP |
1472 | case MSR_K7_HWCR: |
1473 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1474 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
8f1589d9 AP |
1475 | if (data != 0) { |
1476 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1477 | data); | |
1478 | return 1; | |
1479 | } | |
15c4a640 | 1480 | break; |
f7c6d140 AP |
1481 | case MSR_FAM10H_MMIO_CONF_BASE: |
1482 | if (data != 0) { | |
1483 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
1484 | "0x%llx\n", data); | |
1485 | return 1; | |
1486 | } | |
15c4a640 | 1487 | break; |
c323c0e5 | 1488 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1489 | break; |
b5e2fec0 AG |
1490 | case MSR_IA32_DEBUGCTLMSR: |
1491 | if (!data) { | |
1492 | /* We support the non-activated case already */ | |
1493 | break; | |
1494 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1495 | /* Values other than LBR and BTF are vendor-specific, | |
1496 | thus reserved and should throw a #GP */ | |
1497 | return 1; | |
1498 | } | |
1499 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1500 | __func__, data); | |
1501 | break; | |
15c4a640 CO |
1502 | case MSR_IA32_UCODE_REV: |
1503 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1504 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1505 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1506 | break; |
9ba075a6 AK |
1507 | case 0x200 ... 0x2ff: |
1508 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1509 | case MSR_IA32_APICBASE: |
1510 | kvm_set_apic_base(vcpu, data); | |
1511 | break; | |
0105d1a5 GN |
1512 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1513 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 1514 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1515 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1516 | break; |
11c6bffa | 1517 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1518 | case MSR_KVM_WALL_CLOCK: |
1519 | vcpu->kvm->arch.wall_clock = data; | |
1520 | kvm_write_wall_clock(vcpu->kvm, data); | |
1521 | break; | |
11c6bffa | 1522 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 1523 | case MSR_KVM_SYSTEM_TIME: { |
12f9a48f | 1524 | kvmclock_reset(vcpu); |
18068523 GOC |
1525 | |
1526 | vcpu->arch.time = data; | |
c285545f | 1527 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
18068523 GOC |
1528 | |
1529 | /* we verify if the enable bit is set... */ | |
1530 | if (!(data & 1)) | |
1531 | break; | |
1532 | ||
1533 | /* ...but clean it before doing the actual write */ | |
1534 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1535 | ||
18068523 GOC |
1536 | vcpu->arch.time_page = |
1537 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1538 | |
1539 | if (is_error_page(vcpu->arch.time_page)) { | |
1540 | kvm_release_page_clean(vcpu->arch.time_page); | |
1541 | vcpu->arch.time_page = NULL; | |
1542 | } | |
18068523 GOC |
1543 | break; |
1544 | } | |
344d9588 GN |
1545 | case MSR_KVM_ASYNC_PF_EN: |
1546 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
1547 | return 1; | |
1548 | break; | |
890ca9ae HY |
1549 | case MSR_IA32_MCG_CTL: |
1550 | case MSR_IA32_MCG_STATUS: | |
1551 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1552 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1553 | |
1554 | /* Performance counters are not protected by a CPUID bit, | |
1555 | * so we should check all of them in the generic path for the sake of | |
1556 | * cross vendor migration. | |
1557 | * Writing a zero into the event select MSRs disables them, | |
1558 | * which we perfectly emulate ;-). Any other value should be at least | |
1559 | * reported, some guests depend on them. | |
1560 | */ | |
1561 | case MSR_P6_EVNTSEL0: | |
1562 | case MSR_P6_EVNTSEL1: | |
1563 | case MSR_K7_EVNTSEL0: | |
1564 | case MSR_K7_EVNTSEL1: | |
1565 | case MSR_K7_EVNTSEL2: | |
1566 | case MSR_K7_EVNTSEL3: | |
1567 | if (data != 0) | |
1568 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1569 | "0x%x data 0x%llx\n", msr, data); | |
1570 | break; | |
1571 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1572 | * so we ignore writes to make it happy. | |
1573 | */ | |
1574 | case MSR_P6_PERFCTR0: | |
1575 | case MSR_P6_PERFCTR1: | |
1576 | case MSR_K7_PERFCTR0: | |
1577 | case MSR_K7_PERFCTR1: | |
1578 | case MSR_K7_PERFCTR2: | |
1579 | case MSR_K7_PERFCTR3: | |
1580 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1581 | "0x%x data 0x%llx\n", msr, data); | |
1582 | break; | |
84e0cefa JS |
1583 | case MSR_K7_CLK_CTL: |
1584 | /* | |
1585 | * Ignore all writes to this no longer documented MSR. | |
1586 | * Writes are only relevant for old K7 processors, | |
1587 | * all pre-dating SVM, but a recommended workaround from | |
1588 | * AMD for these chips. It is possible to speicify the | |
1589 | * affected processor models on the command line, hence | |
1590 | * the need to ignore the workaround. | |
1591 | */ | |
1592 | break; | |
55cd8e5a GN |
1593 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1594 | if (kvm_hv_msr_partition_wide(msr)) { | |
1595 | int r; | |
1596 | mutex_lock(&vcpu->kvm->lock); | |
1597 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1598 | mutex_unlock(&vcpu->kvm->lock); | |
1599 | return r; | |
1600 | } else | |
1601 | return set_msr_hyperv(vcpu, msr, data); | |
1602 | break; | |
91c9c3ed | 1603 | case MSR_IA32_BBL_CR_CTL3: |
1604 | /* Drop writes to this legacy MSR -- see rdmsr | |
1605 | * counterpart for further detail. | |
1606 | */ | |
1607 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); | |
1608 | break; | |
15c4a640 | 1609 | default: |
ffde22ac ES |
1610 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1611 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1612 | if (!ignore_msrs) { |
1613 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1614 | msr, data); | |
1615 | return 1; | |
1616 | } else { | |
1617 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1618 | msr, data); | |
1619 | break; | |
1620 | } | |
15c4a640 CO |
1621 | } |
1622 | return 0; | |
1623 | } | |
1624 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1625 | ||
1626 | ||
1627 | /* | |
1628 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1629 | * Returns 0 on success, non-0 otherwise. | |
1630 | * Assumes vcpu_load() was already called. | |
1631 | */ | |
1632 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1633 | { | |
1634 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1635 | } | |
1636 | ||
9ba075a6 AK |
1637 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1638 | { | |
0bed3b56 SY |
1639 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1640 | ||
9ba075a6 AK |
1641 | if (!msr_mtrr_valid(msr)) |
1642 | return 1; | |
1643 | ||
0bed3b56 SY |
1644 | if (msr == MSR_MTRRdefType) |
1645 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1646 | (vcpu->arch.mtrr_state.enabled << 10); | |
1647 | else if (msr == MSR_MTRRfix64K_00000) | |
1648 | *pdata = p[0]; | |
1649 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1650 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1651 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1652 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1653 | else if (msr == MSR_IA32_CR_PAT) | |
1654 | *pdata = vcpu->arch.pat; | |
1655 | else { /* Variable MTRRs */ | |
1656 | int idx, is_mtrr_mask; | |
1657 | u64 *pt; | |
1658 | ||
1659 | idx = (msr - 0x200) / 2; | |
1660 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1661 | if (!is_mtrr_mask) | |
1662 | pt = | |
1663 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1664 | else | |
1665 | pt = | |
1666 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1667 | *pdata = *pt; | |
1668 | } | |
1669 | ||
9ba075a6 AK |
1670 | return 0; |
1671 | } | |
1672 | ||
890ca9ae | 1673 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1674 | { |
1675 | u64 data; | |
890ca9ae HY |
1676 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1677 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1678 | |
1679 | switch (msr) { | |
15c4a640 CO |
1680 | case MSR_IA32_P5_MC_ADDR: |
1681 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1682 | data = 0; |
1683 | break; | |
15c4a640 | 1684 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1685 | data = vcpu->arch.mcg_cap; |
1686 | break; | |
c7ac679c | 1687 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1688 | if (!(mcg_cap & MCG_CTL_P)) |
1689 | return 1; | |
1690 | data = vcpu->arch.mcg_ctl; | |
1691 | break; | |
1692 | case MSR_IA32_MCG_STATUS: | |
1693 | data = vcpu->arch.mcg_status; | |
1694 | break; | |
1695 | default: | |
1696 | if (msr >= MSR_IA32_MC0_CTL && | |
1697 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1698 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1699 | data = vcpu->arch.mce_banks[offset]; | |
1700 | break; | |
1701 | } | |
1702 | return 1; | |
1703 | } | |
1704 | *pdata = data; | |
1705 | return 0; | |
1706 | } | |
1707 | ||
55cd8e5a GN |
1708 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1709 | { | |
1710 | u64 data = 0; | |
1711 | struct kvm *kvm = vcpu->kvm; | |
1712 | ||
1713 | switch (msr) { | |
1714 | case HV_X64_MSR_GUEST_OS_ID: | |
1715 | data = kvm->arch.hv_guest_os_id; | |
1716 | break; | |
1717 | case HV_X64_MSR_HYPERCALL: | |
1718 | data = kvm->arch.hv_hypercall; | |
1719 | break; | |
1720 | default: | |
1721 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1722 | return 1; | |
1723 | } | |
1724 | ||
1725 | *pdata = data; | |
1726 | return 0; | |
1727 | } | |
1728 | ||
1729 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1730 | { | |
1731 | u64 data = 0; | |
1732 | ||
1733 | switch (msr) { | |
1734 | case HV_X64_MSR_VP_INDEX: { | |
1735 | int r; | |
1736 | struct kvm_vcpu *v; | |
1737 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1738 | if (v == vcpu) | |
1739 | data = r; | |
1740 | break; | |
1741 | } | |
10388a07 GN |
1742 | case HV_X64_MSR_EOI: |
1743 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1744 | case HV_X64_MSR_ICR: | |
1745 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1746 | case HV_X64_MSR_TPR: | |
1747 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
55cd8e5a GN |
1748 | default: |
1749 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1750 | return 1; | |
1751 | } | |
1752 | *pdata = data; | |
1753 | return 0; | |
1754 | } | |
1755 | ||
890ca9ae HY |
1756 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1757 | { | |
1758 | u64 data; | |
1759 | ||
1760 | switch (msr) { | |
890ca9ae | 1761 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1762 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1763 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1764 | case MSR_IA32_DEBUGCTLMSR: |
1765 | case MSR_IA32_LASTBRANCHFROMIP: | |
1766 | case MSR_IA32_LASTBRANCHTOIP: | |
1767 | case MSR_IA32_LASTINTFROMIP: | |
1768 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1769 | case MSR_K8_SYSCFG: |
1770 | case MSR_K7_HWCR: | |
61a6bd67 | 1771 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1772 | case MSR_P6_PERFCTR0: |
1773 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1774 | case MSR_P6_EVNTSEL0: |
1775 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1776 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1777 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1778 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1779 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1780 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1781 | data = 0; |
1782 | break; | |
9ba075a6 AK |
1783 | case MSR_MTRRcap: |
1784 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1785 | break; | |
1786 | case 0x200 ... 0x2ff: | |
1787 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1788 | case 0xcd: /* fsb frequency */ |
1789 | data = 3; | |
1790 | break; | |
7b914098 JS |
1791 | /* |
1792 | * MSR_EBC_FREQUENCY_ID | |
1793 | * Conservative value valid for even the basic CPU models. | |
1794 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
1795 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
1796 | * and 266MHz for model 3, or 4. Set Core Clock | |
1797 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
1798 | * 31:24) even though these are only valid for CPU | |
1799 | * models > 2, however guests may end up dividing or | |
1800 | * multiplying by zero otherwise. | |
1801 | */ | |
1802 | case MSR_EBC_FREQUENCY_ID: | |
1803 | data = 1 << 24; | |
1804 | break; | |
15c4a640 CO |
1805 | case MSR_IA32_APICBASE: |
1806 | data = kvm_get_apic_base(vcpu); | |
1807 | break; | |
0105d1a5 GN |
1808 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1809 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1810 | break; | |
15c4a640 | 1811 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1812 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1813 | break; |
847f0ad8 AG |
1814 | case MSR_IA32_PERF_STATUS: |
1815 | /* TSC increment by tick */ | |
1816 | data = 1000ULL; | |
1817 | /* CPU multiplier */ | |
1818 | data |= (((uint64_t)4ULL) << 40); | |
1819 | break; | |
15c4a640 | 1820 | case MSR_EFER: |
f6801dff | 1821 | data = vcpu->arch.efer; |
15c4a640 | 1822 | break; |
18068523 | 1823 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 1824 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1825 | data = vcpu->kvm->arch.wall_clock; |
1826 | break; | |
1827 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 1828 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1829 | data = vcpu->arch.time; |
1830 | break; | |
344d9588 GN |
1831 | case MSR_KVM_ASYNC_PF_EN: |
1832 | data = vcpu->arch.apf.msr_val; | |
1833 | break; | |
890ca9ae HY |
1834 | case MSR_IA32_P5_MC_ADDR: |
1835 | case MSR_IA32_P5_MC_TYPE: | |
1836 | case MSR_IA32_MCG_CAP: | |
1837 | case MSR_IA32_MCG_CTL: | |
1838 | case MSR_IA32_MCG_STATUS: | |
1839 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1840 | return get_msr_mce(vcpu, msr, pdata); | |
84e0cefa JS |
1841 | case MSR_K7_CLK_CTL: |
1842 | /* | |
1843 | * Provide expected ramp-up count for K7. All other | |
1844 | * are set to zero, indicating minimum divisors for | |
1845 | * every field. | |
1846 | * | |
1847 | * This prevents guest kernels on AMD host with CPU | |
1848 | * type 6, model 8 and higher from exploding due to | |
1849 | * the rdmsr failing. | |
1850 | */ | |
1851 | data = 0x20000000; | |
1852 | break; | |
55cd8e5a GN |
1853 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1854 | if (kvm_hv_msr_partition_wide(msr)) { | |
1855 | int r; | |
1856 | mutex_lock(&vcpu->kvm->lock); | |
1857 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
1858 | mutex_unlock(&vcpu->kvm->lock); | |
1859 | return r; | |
1860 | } else | |
1861 | return get_msr_hyperv(vcpu, msr, pdata); | |
1862 | break; | |
91c9c3ed | 1863 | case MSR_IA32_BBL_CR_CTL3: |
1864 | /* This legacy MSR exists but isn't fully documented in current | |
1865 | * silicon. It is however accessed by winxp in very narrow | |
1866 | * scenarios where it sets bit #19, itself documented as | |
1867 | * a "reserved" bit. Best effort attempt to source coherent | |
1868 | * read data here should the balance of the register be | |
1869 | * interpreted by the guest: | |
1870 | * | |
1871 | * L2 cache control register 3: 64GB range, 256KB size, | |
1872 | * enabled, latency 0x1, configured | |
1873 | */ | |
1874 | data = 0xbe702111; | |
1875 | break; | |
15c4a640 | 1876 | default: |
ed85c068 AP |
1877 | if (!ignore_msrs) { |
1878 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1879 | return 1; | |
1880 | } else { | |
1881 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1882 | data = 0; | |
1883 | } | |
1884 | break; | |
15c4a640 CO |
1885 | } |
1886 | *pdata = data; | |
1887 | return 0; | |
1888 | } | |
1889 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1890 | ||
313a3dc7 CO |
1891 | /* |
1892 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1893 | * | |
1894 | * @return number of msrs set successfully. | |
1895 | */ | |
1896 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1897 | struct kvm_msr_entry *entries, | |
1898 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1899 | unsigned index, u64 *data)) | |
1900 | { | |
f656ce01 | 1901 | int i, idx; |
313a3dc7 | 1902 | |
f656ce01 | 1903 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
1904 | for (i = 0; i < msrs->nmsrs; ++i) |
1905 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1906 | break; | |
f656ce01 | 1907 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 1908 | |
313a3dc7 CO |
1909 | return i; |
1910 | } | |
1911 | ||
1912 | /* | |
1913 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1914 | * | |
1915 | * @return number of msrs set successfully. | |
1916 | */ | |
1917 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1918 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1919 | unsigned index, u64 *data), | |
1920 | int writeback) | |
1921 | { | |
1922 | struct kvm_msrs msrs; | |
1923 | struct kvm_msr_entry *entries; | |
1924 | int r, n; | |
1925 | unsigned size; | |
1926 | ||
1927 | r = -EFAULT; | |
1928 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1929 | goto out; | |
1930 | ||
1931 | r = -E2BIG; | |
1932 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1933 | goto out; | |
1934 | ||
1935 | r = -ENOMEM; | |
1936 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
7a73c028 | 1937 | entries = kmalloc(size, GFP_KERNEL); |
313a3dc7 CO |
1938 | if (!entries) |
1939 | goto out; | |
1940 | ||
1941 | r = -EFAULT; | |
1942 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1943 | goto out_free; | |
1944 | ||
1945 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1946 | if (r < 0) | |
1947 | goto out_free; | |
1948 | ||
1949 | r = -EFAULT; | |
1950 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1951 | goto out_free; | |
1952 | ||
1953 | r = n; | |
1954 | ||
1955 | out_free: | |
7a73c028 | 1956 | kfree(entries); |
313a3dc7 CO |
1957 | out: |
1958 | return r; | |
1959 | } | |
1960 | ||
018d00d2 ZX |
1961 | int kvm_dev_ioctl_check_extension(long ext) |
1962 | { | |
1963 | int r; | |
1964 | ||
1965 | switch (ext) { | |
1966 | case KVM_CAP_IRQCHIP: | |
1967 | case KVM_CAP_HLT: | |
1968 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1969 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1970 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1971 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1972 | case KVM_CAP_PIT: |
a28e4f5a | 1973 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1974 | case KVM_CAP_MP_STATE: |
ed848624 | 1975 | case KVM_CAP_SYNC_MMU: |
a355c85c | 1976 | case KVM_CAP_USER_NMI: |
52d939a0 | 1977 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1978 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1979 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1980 | case KVM_CAP_IRQFD: |
d34e6b17 | 1981 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1982 | case KVM_CAP_PIT2: |
e9f42757 | 1983 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1984 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1985 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1986 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1987 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 1988 | case KVM_CAP_HYPERV: |
10388a07 | 1989 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 1990 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 1991 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 1992 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 1993 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 1994 | case KVM_CAP_XSAVE: |
344d9588 | 1995 | case KVM_CAP_ASYNC_PF: |
018d00d2 ZX |
1996 | r = 1; |
1997 | break; | |
542472b5 LV |
1998 | case KVM_CAP_COALESCED_MMIO: |
1999 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2000 | break; | |
774ead3a AK |
2001 | case KVM_CAP_VAPIC: |
2002 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2003 | break; | |
f725230a AK |
2004 | case KVM_CAP_NR_VCPUS: |
2005 | r = KVM_MAX_VCPUS; | |
2006 | break; | |
a988b910 AK |
2007 | case KVM_CAP_NR_MEMSLOTS: |
2008 | r = KVM_MEMORY_SLOTS; | |
2009 | break; | |
a68a6a72 MT |
2010 | case KVM_CAP_PV_MMU: /* obsolete */ |
2011 | r = 0; | |
2f333bcb | 2012 | break; |
62c476c7 | 2013 | case KVM_CAP_IOMMU: |
19de40a8 | 2014 | r = iommu_found(); |
62c476c7 | 2015 | break; |
890ca9ae HY |
2016 | case KVM_CAP_MCE: |
2017 | r = KVM_MAX_MCE_BANKS; | |
2018 | break; | |
2d5b5a66 SY |
2019 | case KVM_CAP_XCRS: |
2020 | r = cpu_has_xsave; | |
2021 | break; | |
018d00d2 ZX |
2022 | default: |
2023 | r = 0; | |
2024 | break; | |
2025 | } | |
2026 | return r; | |
2027 | ||
2028 | } | |
2029 | ||
043405e1 CO |
2030 | long kvm_arch_dev_ioctl(struct file *filp, |
2031 | unsigned int ioctl, unsigned long arg) | |
2032 | { | |
2033 | void __user *argp = (void __user *)arg; | |
2034 | long r; | |
2035 | ||
2036 | switch (ioctl) { | |
2037 | case KVM_GET_MSR_INDEX_LIST: { | |
2038 | struct kvm_msr_list __user *user_msr_list = argp; | |
2039 | struct kvm_msr_list msr_list; | |
2040 | unsigned n; | |
2041 | ||
2042 | r = -EFAULT; | |
2043 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2044 | goto out; | |
2045 | n = msr_list.nmsrs; | |
2046 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2047 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2048 | goto out; | |
2049 | r = -E2BIG; | |
e125e7b6 | 2050 | if (n < msr_list.nmsrs) |
043405e1 CO |
2051 | goto out; |
2052 | r = -EFAULT; | |
2053 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2054 | num_msrs_to_save * sizeof(u32))) | |
2055 | goto out; | |
e125e7b6 | 2056 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2057 | &emulated_msrs, |
2058 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2059 | goto out; | |
2060 | r = 0; | |
2061 | break; | |
2062 | } | |
674eea0f AK |
2063 | case KVM_GET_SUPPORTED_CPUID: { |
2064 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2065 | struct kvm_cpuid2 cpuid; | |
2066 | ||
2067 | r = -EFAULT; | |
2068 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2069 | goto out; | |
2070 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 2071 | cpuid_arg->entries); |
674eea0f AK |
2072 | if (r) |
2073 | goto out; | |
2074 | ||
2075 | r = -EFAULT; | |
2076 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2077 | goto out; | |
2078 | r = 0; | |
2079 | break; | |
2080 | } | |
890ca9ae HY |
2081 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2082 | u64 mce_cap; | |
2083 | ||
2084 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2085 | r = -EFAULT; | |
2086 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2087 | goto out; | |
2088 | r = 0; | |
2089 | break; | |
2090 | } | |
043405e1 CO |
2091 | default: |
2092 | r = -EINVAL; | |
2093 | } | |
2094 | out: | |
2095 | return r; | |
2096 | } | |
2097 | ||
f5f48ee1 SY |
2098 | static void wbinvd_ipi(void *garbage) |
2099 | { | |
2100 | wbinvd(); | |
2101 | } | |
2102 | ||
2103 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2104 | { | |
2105 | return vcpu->kvm->arch.iommu_domain && | |
2106 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
2107 | } | |
2108 | ||
313a3dc7 CO |
2109 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2110 | { | |
f5f48ee1 SY |
2111 | /* Address WBINVD may be executed by guest */ |
2112 | if (need_emulate_wbinvd(vcpu)) { | |
2113 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2114 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2115 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2116 | smp_call_function_single(vcpu->cpu, | |
2117 | wbinvd_ipi, NULL, 1); | |
2118 | } | |
2119 | ||
313a3dc7 | 2120 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
48434c20 | 2121 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
e48672fa ZA |
2122 | /* Make sure TSC doesn't go backwards */ |
2123 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : | |
2124 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
2125 | if (tsc_delta < 0) | |
2126 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2127 | if (check_tsc_unstable()) { |
e48672fa | 2128 | kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta); |
c285545f | 2129 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2130 | } |
1aa8ceef | 2131 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2132 | if (vcpu->cpu != cpu) |
2133 | kvm_migrate_timers(vcpu); | |
e48672fa | 2134 | vcpu->cpu = cpu; |
6b7d7e76 | 2135 | } |
313a3dc7 CO |
2136 | } |
2137 | ||
2138 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2139 | { | |
02daab21 | 2140 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2141 | kvm_put_guest_fpu(vcpu); |
e48672fa | 2142 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2143 | } |
2144 | ||
07716717 | 2145 | static int is_efer_nx(void) |
313a3dc7 | 2146 | { |
e286e86e | 2147 | unsigned long long efer = 0; |
313a3dc7 | 2148 | |
e286e86e | 2149 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
2150 | return efer & EFER_NX; |
2151 | } | |
2152 | ||
2153 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
2154 | { | |
2155 | int i; | |
2156 | struct kvm_cpuid_entry2 *e, *entry; | |
2157 | ||
313a3dc7 | 2158 | entry = NULL; |
ad312c7c ZX |
2159 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
2160 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
2161 | if (e->function == 0x80000001) { |
2162 | entry = e; | |
2163 | break; | |
2164 | } | |
2165 | } | |
07716717 | 2166 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
2167 | entry->edx &= ~(1 << 20); |
2168 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
2169 | } | |
2170 | } | |
2171 | ||
07716717 | 2172 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
2173 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
2174 | struct kvm_cpuid *cpuid, | |
2175 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
2176 | { |
2177 | int r, i; | |
2178 | struct kvm_cpuid_entry *cpuid_entries; | |
2179 | ||
2180 | r = -E2BIG; | |
2181 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2182 | goto out; | |
2183 | r = -ENOMEM; | |
2184 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
2185 | if (!cpuid_entries) | |
2186 | goto out; | |
2187 | r = -EFAULT; | |
2188 | if (copy_from_user(cpuid_entries, entries, | |
2189 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
2190 | goto out_free; | |
2191 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
2192 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
2193 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
2194 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
2195 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
2196 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
2197 | vcpu->arch.cpuid_entries[i].index = 0; | |
2198 | vcpu->arch.cpuid_entries[i].flags = 0; | |
2199 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
2200 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
2201 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
2202 | } | |
2203 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
2204 | cpuid_fix_nx_cap(vcpu); |
2205 | r = 0; | |
fc61b800 | 2206 | kvm_apic_set_version(vcpu); |
0e851880 | 2207 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2208 | update_cpuid(vcpu); |
07716717 DK |
2209 | |
2210 | out_free: | |
2211 | vfree(cpuid_entries); | |
2212 | out: | |
2213 | return r; | |
2214 | } | |
2215 | ||
2216 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
2217 | struct kvm_cpuid2 *cpuid, |
2218 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
2219 | { |
2220 | int r; | |
2221 | ||
2222 | r = -E2BIG; | |
2223 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2224 | goto out; | |
2225 | r = -EFAULT; | |
ad312c7c | 2226 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 2227 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 2228 | goto out; |
ad312c7c | 2229 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 2230 | kvm_apic_set_version(vcpu); |
0e851880 | 2231 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2232 | update_cpuid(vcpu); |
313a3dc7 CO |
2233 | return 0; |
2234 | ||
2235 | out: | |
2236 | return r; | |
2237 | } | |
2238 | ||
07716717 | 2239 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
2240 | struct kvm_cpuid2 *cpuid, |
2241 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
2242 | { |
2243 | int r; | |
2244 | ||
2245 | r = -E2BIG; | |
ad312c7c | 2246 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
2247 | goto out; |
2248 | r = -EFAULT; | |
ad312c7c | 2249 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 2250 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2251 | goto out; |
2252 | return 0; | |
2253 | ||
2254 | out: | |
ad312c7c | 2255 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
2256 | return r; |
2257 | } | |
2258 | ||
945ee35e AK |
2259 | static void cpuid_mask(u32 *word, int wordnum) |
2260 | { | |
2261 | *word &= boot_cpu_data.x86_capability[wordnum]; | |
2262 | } | |
2263 | ||
07716717 | 2264 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 2265 | u32 index) |
07716717 DK |
2266 | { |
2267 | entry->function = function; | |
2268 | entry->index = index; | |
2269 | cpuid_count(entry->function, entry->index, | |
19355475 | 2270 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
2271 | entry->flags = 0; |
2272 | } | |
2273 | ||
7faa4ee1 AK |
2274 | #define F(x) bit(X86_FEATURE_##x) |
2275 | ||
07716717 DK |
2276 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
2277 | u32 index, int *nent, int maxnent) | |
2278 | { | |
7faa4ee1 | 2279 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 2280 | #ifdef CONFIG_X86_64 |
17cc3935 SY |
2281 | unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL) |
2282 | ? F(GBPAGES) : 0; | |
7faa4ee1 AK |
2283 | unsigned f_lm = F(LM); |
2284 | #else | |
17cc3935 | 2285 | unsigned f_gbpages = 0; |
7faa4ee1 | 2286 | unsigned f_lm = 0; |
07716717 | 2287 | #endif |
4e47c7a6 | 2288 | unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0; |
7faa4ee1 AK |
2289 | |
2290 | /* cpuid 1.edx */ | |
2291 | const u32 kvm_supported_word0_x86_features = | |
2292 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2293 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2294 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
2295 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2296 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
2297 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
2298 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
2299 | 0 /* HTT, TM, Reserved, PBE */; | |
2300 | /* cpuid 0x80000001.edx */ | |
2301 | const u32 kvm_supported_word1_x86_features = | |
2302 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2303 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2304 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
2305 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2306 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
2307 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
4e47c7a6 | 2308 | F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp | |
7faa4ee1 AK |
2309 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
2310 | /* cpuid 1.ecx */ | |
2311 | const u32 kvm_supported_word4_x86_features = | |
6c3f6041 | 2312 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | |
d149c731 AK |
2313 | 0 /* DS-CPL, VMX, SMX, EST */ | |
2314 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
2315 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
2316 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 2317 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
6d886fd0 AP |
2318 | 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | |
2319 | F(F16C); | |
7faa4ee1 | 2320 | /* cpuid 0x80000001.ecx */ |
07716717 | 2321 | const u32 kvm_supported_word6_x86_features = |
4c62a2dc | 2322 | F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | |
7faa4ee1 | 2323 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | |
7ef8aa72 | 2324 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) | |
6d886fd0 | 2325 | 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM); |
07716717 | 2326 | |
19355475 | 2327 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
2328 | get_cpu(); |
2329 | do_cpuid_1_ent(entry, function, index); | |
2330 | ++*nent; | |
2331 | ||
2332 | switch (function) { | |
2333 | case 0: | |
2acf923e | 2334 | entry->eax = min(entry->eax, (u32)0xd); |
07716717 DK |
2335 | break; |
2336 | case 1: | |
2337 | entry->edx &= kvm_supported_word0_x86_features; | |
945ee35e | 2338 | cpuid_mask(&entry->edx, 0); |
7faa4ee1 | 2339 | entry->ecx &= kvm_supported_word4_x86_features; |
945ee35e | 2340 | cpuid_mask(&entry->ecx, 4); |
0d1de2d9 GN |
2341 | /* we support x2apic emulation even if host does not support |
2342 | * it since we emulate x2apic in software */ | |
2343 | entry->ecx |= F(X2APIC); | |
07716717 DK |
2344 | break; |
2345 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
2346 | * may return different values. This forces us to get_cpu() before | |
2347 | * issuing the first command, and also to emulate this annoying behavior | |
2348 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
2349 | case 2: { | |
2350 | int t, times = entry->eax & 0xff; | |
2351 | ||
2352 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 2353 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
2354 | for (t = 1; t < times && *nent < maxnent; ++t) { |
2355 | do_cpuid_1_ent(&entry[t], function, 0); | |
2356 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
2357 | ++*nent; | |
2358 | } | |
2359 | break; | |
2360 | } | |
2361 | /* function 4 and 0xb have additional index. */ | |
2362 | case 4: { | |
14af3f3c | 2363 | int i, cache_type; |
07716717 DK |
2364 | |
2365 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2366 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
2367 | for (i = 1; *nent < maxnent; ++i) { |
2368 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
2369 | if (!cache_type) |
2370 | break; | |
14af3f3c HH |
2371 | do_cpuid_1_ent(&entry[i], function, i); |
2372 | entry[i].flags |= | |
07716717 DK |
2373 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2374 | ++*nent; | |
2375 | } | |
2376 | break; | |
2377 | } | |
2378 | case 0xb: { | |
14af3f3c | 2379 | int i, level_type; |
07716717 DK |
2380 | |
2381 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2382 | /* read more entries until level_type is zero */ | |
14af3f3c | 2383 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 2384 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
2385 | if (!level_type) |
2386 | break; | |
14af3f3c HH |
2387 | do_cpuid_1_ent(&entry[i], function, i); |
2388 | entry[i].flags |= | |
07716717 DK |
2389 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2390 | ++*nent; | |
2391 | } | |
2392 | break; | |
2393 | } | |
2acf923e DC |
2394 | case 0xd: { |
2395 | int i; | |
2396 | ||
2397 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
20800bc9 AP |
2398 | for (i = 1; *nent < maxnent && i < 64; ++i) { |
2399 | if (entry[i].eax == 0) | |
2400 | continue; | |
2acf923e DC |
2401 | do_cpuid_1_ent(&entry[i], function, i); |
2402 | entry[i].flags |= | |
2403 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2404 | ++*nent; | |
2405 | } | |
2406 | break; | |
2407 | } | |
84478c82 GC |
2408 | case KVM_CPUID_SIGNATURE: { |
2409 | char signature[12] = "KVMKVMKVM\0\0"; | |
2410 | u32 *sigptr = (u32 *)signature; | |
2411 | entry->eax = 0; | |
2412 | entry->ebx = sigptr[0]; | |
2413 | entry->ecx = sigptr[1]; | |
2414 | entry->edx = sigptr[2]; | |
2415 | break; | |
2416 | } | |
2417 | case KVM_CPUID_FEATURES: | |
2418 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
2419 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
371bcf64 | 2420 | (1 << KVM_FEATURE_CLOCKSOURCE2) | |
32918924 | 2421 | (1 << KVM_FEATURE_ASYNC_PF) | |
371bcf64 | 2422 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); |
84478c82 GC |
2423 | entry->ebx = 0; |
2424 | entry->ecx = 0; | |
2425 | entry->edx = 0; | |
2426 | break; | |
07716717 DK |
2427 | case 0x80000000: |
2428 | entry->eax = min(entry->eax, 0x8000001a); | |
2429 | break; | |
2430 | case 0x80000001: | |
2431 | entry->edx &= kvm_supported_word1_x86_features; | |
945ee35e | 2432 | cpuid_mask(&entry->edx, 1); |
07716717 | 2433 | entry->ecx &= kvm_supported_word6_x86_features; |
945ee35e | 2434 | cpuid_mask(&entry->ecx, 6); |
07716717 DK |
2435 | break; |
2436 | } | |
d4330ef2 JR |
2437 | |
2438 | kvm_x86_ops->set_supported_cpuid(function, entry); | |
2439 | ||
07716717 DK |
2440 | put_cpu(); |
2441 | } | |
2442 | ||
7faa4ee1 AK |
2443 | #undef F |
2444 | ||
674eea0f | 2445 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 2446 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
2447 | { |
2448 | struct kvm_cpuid_entry2 *cpuid_entries; | |
2449 | int limit, nent = 0, r = -E2BIG; | |
2450 | u32 func; | |
2451 | ||
2452 | if (cpuid->nent < 1) | |
2453 | goto out; | |
6a544355 AK |
2454 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
2455 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
2456 | r = -ENOMEM; |
2457 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
2458 | if (!cpuid_entries) | |
2459 | goto out; | |
2460 | ||
2461 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
2462 | limit = cpuid_entries[0].eax; | |
2463 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
2464 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2465 | &nent, cpuid->nent); |
07716717 DK |
2466 | r = -E2BIG; |
2467 | if (nent >= cpuid->nent) | |
2468 | goto out_free; | |
2469 | ||
2470 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
2471 | limit = cpuid_entries[nent - 1].eax; | |
2472 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
2473 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2474 | &nent, cpuid->nent); |
84478c82 GC |
2475 | |
2476 | ||
2477 | ||
2478 | r = -E2BIG; | |
2479 | if (nent >= cpuid->nent) | |
2480 | goto out_free; | |
2481 | ||
2482 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent, | |
2483 | cpuid->nent); | |
2484 | ||
2485 | r = -E2BIG; | |
2486 | if (nent >= cpuid->nent) | |
2487 | goto out_free; | |
2488 | ||
2489 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent, | |
2490 | cpuid->nent); | |
2491 | ||
cb007648 MM |
2492 | r = -E2BIG; |
2493 | if (nent >= cpuid->nent) | |
2494 | goto out_free; | |
2495 | ||
07716717 DK |
2496 | r = -EFAULT; |
2497 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 2498 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2499 | goto out_free; |
2500 | cpuid->nent = nent; | |
2501 | r = 0; | |
2502 | ||
2503 | out_free: | |
2504 | vfree(cpuid_entries); | |
2505 | out: | |
2506 | return r; | |
2507 | } | |
2508 | ||
313a3dc7 CO |
2509 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2510 | struct kvm_lapic_state *s) | |
2511 | { | |
ad312c7c | 2512 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2513 | |
2514 | return 0; | |
2515 | } | |
2516 | ||
2517 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2518 | struct kvm_lapic_state *s) | |
2519 | { | |
ad312c7c | 2520 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 2521 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 2522 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2523 | |
2524 | return 0; | |
2525 | } | |
2526 | ||
f77bc6a4 ZX |
2527 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2528 | struct kvm_interrupt *irq) | |
2529 | { | |
2530 | if (irq->irq < 0 || irq->irq >= 256) | |
2531 | return -EINVAL; | |
2532 | if (irqchip_in_kernel(vcpu->kvm)) | |
2533 | return -ENXIO; | |
f77bc6a4 | 2534 | |
66fd3f7f | 2535 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2536 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2537 | |
f77bc6a4 ZX |
2538 | return 0; |
2539 | } | |
2540 | ||
c4abb7c9 JK |
2541 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2542 | { | |
c4abb7c9 | 2543 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2544 | |
2545 | return 0; | |
2546 | } | |
2547 | ||
b209749f AK |
2548 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2549 | struct kvm_tpr_access_ctl *tac) | |
2550 | { | |
2551 | if (tac->flags) | |
2552 | return -EINVAL; | |
2553 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2554 | return 0; | |
2555 | } | |
2556 | ||
890ca9ae HY |
2557 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2558 | u64 mcg_cap) | |
2559 | { | |
2560 | int r; | |
2561 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2562 | ||
2563 | r = -EINVAL; | |
a9e38c3e | 2564 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2565 | goto out; |
2566 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2567 | goto out; | |
2568 | r = 0; | |
2569 | vcpu->arch.mcg_cap = mcg_cap; | |
2570 | /* Init IA32_MCG_CTL to all 1s */ | |
2571 | if (mcg_cap & MCG_CTL_P) | |
2572 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2573 | /* Init IA32_MCi_CTL to all 1s */ | |
2574 | for (bank = 0; bank < bank_num; bank++) | |
2575 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2576 | out: | |
2577 | return r; | |
2578 | } | |
2579 | ||
2580 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2581 | struct kvm_x86_mce *mce) | |
2582 | { | |
2583 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2584 | unsigned bank_num = mcg_cap & 0xff; | |
2585 | u64 *banks = vcpu->arch.mce_banks; | |
2586 | ||
2587 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2588 | return -EINVAL; | |
2589 | /* | |
2590 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2591 | * reporting is disabled | |
2592 | */ | |
2593 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2594 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2595 | return 0; | |
2596 | banks += 4 * mce->bank; | |
2597 | /* | |
2598 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2599 | * reporting is disabled for the bank | |
2600 | */ | |
2601 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2602 | return 0; | |
2603 | if (mce->status & MCI_STATUS_UC) { | |
2604 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2605 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2606 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2607 | return 0; |
2608 | } | |
2609 | if (banks[1] & MCI_STATUS_VAL) | |
2610 | mce->status |= MCI_STATUS_OVER; | |
2611 | banks[2] = mce->addr; | |
2612 | banks[3] = mce->misc; | |
2613 | vcpu->arch.mcg_status = mce->mcg_status; | |
2614 | banks[1] = mce->status; | |
2615 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2616 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2617 | || !(banks[1] & MCI_STATUS_UC)) { | |
2618 | if (banks[1] & MCI_STATUS_VAL) | |
2619 | mce->status |= MCI_STATUS_OVER; | |
2620 | banks[2] = mce->addr; | |
2621 | banks[3] = mce->misc; | |
2622 | banks[1] = mce->status; | |
2623 | } else | |
2624 | banks[1] |= MCI_STATUS_OVER; | |
2625 | return 0; | |
2626 | } | |
2627 | ||
3cfc3092 JK |
2628 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2629 | struct kvm_vcpu_events *events) | |
2630 | { | |
03b82a30 JK |
2631 | events->exception.injected = |
2632 | vcpu->arch.exception.pending && | |
2633 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2634 | events->exception.nr = vcpu->arch.exception.nr; |
2635 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2636 | events->exception.pad = 0; |
3cfc3092 JK |
2637 | events->exception.error_code = vcpu->arch.exception.error_code; |
2638 | ||
03b82a30 JK |
2639 | events->interrupt.injected = |
2640 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2641 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2642 | events->interrupt.soft = 0; |
48005f64 JK |
2643 | events->interrupt.shadow = |
2644 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2645 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2646 | |
2647 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2648 | events->nmi.pending = vcpu->arch.nmi_pending; | |
2649 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
97e69aa6 | 2650 | events->nmi.pad = 0; |
3cfc3092 JK |
2651 | |
2652 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2653 | ||
dab4b911 | 2654 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2655 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2656 | | KVM_VCPUEVENT_VALID_SHADOW); | |
97e69aa6 | 2657 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2658 | } |
2659 | ||
2660 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2661 | struct kvm_vcpu_events *events) | |
2662 | { | |
dab4b911 | 2663 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2664 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2665 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2666 | return -EINVAL; |
2667 | ||
3cfc3092 JK |
2668 | vcpu->arch.exception.pending = events->exception.injected; |
2669 | vcpu->arch.exception.nr = events->exception.nr; | |
2670 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2671 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2672 | ||
2673 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2674 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2675 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
2676 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2677 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2678 | events->interrupt.shadow); | |
3cfc3092 JK |
2679 | |
2680 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2681 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2682 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2683 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2684 | ||
dab4b911 JK |
2685 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2686 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 | 2687 | |
3842d135 AK |
2688 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2689 | ||
3cfc3092 JK |
2690 | return 0; |
2691 | } | |
2692 | ||
a1efbe77 JK |
2693 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2694 | struct kvm_debugregs *dbgregs) | |
2695 | { | |
a1efbe77 JK |
2696 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2697 | dbgregs->dr6 = vcpu->arch.dr6; | |
2698 | dbgregs->dr7 = vcpu->arch.dr7; | |
2699 | dbgregs->flags = 0; | |
97e69aa6 | 2700 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
2701 | } |
2702 | ||
2703 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2704 | struct kvm_debugregs *dbgregs) | |
2705 | { | |
2706 | if (dbgregs->flags) | |
2707 | return -EINVAL; | |
2708 | ||
a1efbe77 JK |
2709 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2710 | vcpu->arch.dr6 = dbgregs->dr6; | |
2711 | vcpu->arch.dr7 = dbgregs->dr7; | |
2712 | ||
a1efbe77 JK |
2713 | return 0; |
2714 | } | |
2715 | ||
2d5b5a66 SY |
2716 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2717 | struct kvm_xsave *guest_xsave) | |
2718 | { | |
2719 | if (cpu_has_xsave) | |
2720 | memcpy(guest_xsave->region, | |
2721 | &vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2722 | xstate_size); |
2d5b5a66 SY |
2723 | else { |
2724 | memcpy(guest_xsave->region, | |
2725 | &vcpu->arch.guest_fpu.state->fxsave, | |
2726 | sizeof(struct i387_fxsave_struct)); | |
2727 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2728 | XSTATE_FPSSE; | |
2729 | } | |
2730 | } | |
2731 | ||
2732 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2733 | struct kvm_xsave *guest_xsave) | |
2734 | { | |
2735 | u64 xstate_bv = | |
2736 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2737 | ||
2738 | if (cpu_has_xsave) | |
2739 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2740 | guest_xsave->region, xstate_size); |
2d5b5a66 SY |
2741 | else { |
2742 | if (xstate_bv & ~XSTATE_FPSSE) | |
2743 | return -EINVAL; | |
2744 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2745 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2746 | } | |
2747 | return 0; | |
2748 | } | |
2749 | ||
2750 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2751 | struct kvm_xcrs *guest_xcrs) | |
2752 | { | |
2753 | if (!cpu_has_xsave) { | |
2754 | guest_xcrs->nr_xcrs = 0; | |
2755 | return; | |
2756 | } | |
2757 | ||
2758 | guest_xcrs->nr_xcrs = 1; | |
2759 | guest_xcrs->flags = 0; | |
2760 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2761 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2762 | } | |
2763 | ||
2764 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2765 | struct kvm_xcrs *guest_xcrs) | |
2766 | { | |
2767 | int i, r = 0; | |
2768 | ||
2769 | if (!cpu_has_xsave) | |
2770 | return -EINVAL; | |
2771 | ||
2772 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2773 | return -EINVAL; | |
2774 | ||
2775 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2776 | /* Only support XCR0 currently */ | |
2777 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2778 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2779 | guest_xcrs->xcrs[0].value); | |
2780 | break; | |
2781 | } | |
2782 | if (r) | |
2783 | r = -EINVAL; | |
2784 | return r; | |
2785 | } | |
2786 | ||
313a3dc7 CO |
2787 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2788 | unsigned int ioctl, unsigned long arg) | |
2789 | { | |
2790 | struct kvm_vcpu *vcpu = filp->private_data; | |
2791 | void __user *argp = (void __user *)arg; | |
2792 | int r; | |
d1ac91d8 AK |
2793 | union { |
2794 | struct kvm_lapic_state *lapic; | |
2795 | struct kvm_xsave *xsave; | |
2796 | struct kvm_xcrs *xcrs; | |
2797 | void *buffer; | |
2798 | } u; | |
2799 | ||
2800 | u.buffer = NULL; | |
313a3dc7 CO |
2801 | switch (ioctl) { |
2802 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2803 | r = -EINVAL; |
2804 | if (!vcpu->arch.apic) | |
2805 | goto out; | |
d1ac91d8 | 2806 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2807 | |
b772ff36 | 2808 | r = -ENOMEM; |
d1ac91d8 | 2809 | if (!u.lapic) |
b772ff36 | 2810 | goto out; |
d1ac91d8 | 2811 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2812 | if (r) |
2813 | goto out; | |
2814 | r = -EFAULT; | |
d1ac91d8 | 2815 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2816 | goto out; |
2817 | r = 0; | |
2818 | break; | |
2819 | } | |
2820 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2821 | r = -EINVAL; |
2822 | if (!vcpu->arch.apic) | |
2823 | goto out; | |
d1ac91d8 | 2824 | u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
b772ff36 | 2825 | r = -ENOMEM; |
d1ac91d8 | 2826 | if (!u.lapic) |
b772ff36 | 2827 | goto out; |
313a3dc7 | 2828 | r = -EFAULT; |
d1ac91d8 | 2829 | if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 2830 | goto out; |
d1ac91d8 | 2831 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2832 | if (r) |
2833 | goto out; | |
2834 | r = 0; | |
2835 | break; | |
2836 | } | |
f77bc6a4 ZX |
2837 | case KVM_INTERRUPT: { |
2838 | struct kvm_interrupt irq; | |
2839 | ||
2840 | r = -EFAULT; | |
2841 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2842 | goto out; | |
2843 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2844 | if (r) | |
2845 | goto out; | |
2846 | r = 0; | |
2847 | break; | |
2848 | } | |
c4abb7c9 JK |
2849 | case KVM_NMI: { |
2850 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2851 | if (r) | |
2852 | goto out; | |
2853 | r = 0; | |
2854 | break; | |
2855 | } | |
313a3dc7 CO |
2856 | case KVM_SET_CPUID: { |
2857 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2858 | struct kvm_cpuid cpuid; | |
2859 | ||
2860 | r = -EFAULT; | |
2861 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2862 | goto out; | |
2863 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2864 | if (r) | |
2865 | goto out; | |
2866 | break; | |
2867 | } | |
07716717 DK |
2868 | case KVM_SET_CPUID2: { |
2869 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2870 | struct kvm_cpuid2 cpuid; | |
2871 | ||
2872 | r = -EFAULT; | |
2873 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2874 | goto out; | |
2875 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2876 | cpuid_arg->entries); |
07716717 DK |
2877 | if (r) |
2878 | goto out; | |
2879 | break; | |
2880 | } | |
2881 | case KVM_GET_CPUID2: { | |
2882 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2883 | struct kvm_cpuid2 cpuid; | |
2884 | ||
2885 | r = -EFAULT; | |
2886 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2887 | goto out; | |
2888 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2889 | cpuid_arg->entries); |
07716717 DK |
2890 | if (r) |
2891 | goto out; | |
2892 | r = -EFAULT; | |
2893 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2894 | goto out; | |
2895 | r = 0; | |
2896 | break; | |
2897 | } | |
313a3dc7 CO |
2898 | case KVM_GET_MSRS: |
2899 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2900 | break; | |
2901 | case KVM_SET_MSRS: | |
2902 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2903 | break; | |
b209749f AK |
2904 | case KVM_TPR_ACCESS_REPORTING: { |
2905 | struct kvm_tpr_access_ctl tac; | |
2906 | ||
2907 | r = -EFAULT; | |
2908 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2909 | goto out; | |
2910 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2911 | if (r) | |
2912 | goto out; | |
2913 | r = -EFAULT; | |
2914 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2915 | goto out; | |
2916 | r = 0; | |
2917 | break; | |
2918 | }; | |
b93463aa AK |
2919 | case KVM_SET_VAPIC_ADDR: { |
2920 | struct kvm_vapic_addr va; | |
2921 | ||
2922 | r = -EINVAL; | |
2923 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2924 | goto out; | |
2925 | r = -EFAULT; | |
2926 | if (copy_from_user(&va, argp, sizeof va)) | |
2927 | goto out; | |
2928 | r = 0; | |
2929 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2930 | break; | |
2931 | } | |
890ca9ae HY |
2932 | case KVM_X86_SETUP_MCE: { |
2933 | u64 mcg_cap; | |
2934 | ||
2935 | r = -EFAULT; | |
2936 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2937 | goto out; | |
2938 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2939 | break; | |
2940 | } | |
2941 | case KVM_X86_SET_MCE: { | |
2942 | struct kvm_x86_mce mce; | |
2943 | ||
2944 | r = -EFAULT; | |
2945 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2946 | goto out; | |
2947 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2948 | break; | |
2949 | } | |
3cfc3092 JK |
2950 | case KVM_GET_VCPU_EVENTS: { |
2951 | struct kvm_vcpu_events events; | |
2952 | ||
2953 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2954 | ||
2955 | r = -EFAULT; | |
2956 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2957 | break; | |
2958 | r = 0; | |
2959 | break; | |
2960 | } | |
2961 | case KVM_SET_VCPU_EVENTS: { | |
2962 | struct kvm_vcpu_events events; | |
2963 | ||
2964 | r = -EFAULT; | |
2965 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2966 | break; | |
2967 | ||
2968 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2969 | break; | |
2970 | } | |
a1efbe77 JK |
2971 | case KVM_GET_DEBUGREGS: { |
2972 | struct kvm_debugregs dbgregs; | |
2973 | ||
2974 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2975 | ||
2976 | r = -EFAULT; | |
2977 | if (copy_to_user(argp, &dbgregs, | |
2978 | sizeof(struct kvm_debugregs))) | |
2979 | break; | |
2980 | r = 0; | |
2981 | break; | |
2982 | } | |
2983 | case KVM_SET_DEBUGREGS: { | |
2984 | struct kvm_debugregs dbgregs; | |
2985 | ||
2986 | r = -EFAULT; | |
2987 | if (copy_from_user(&dbgregs, argp, | |
2988 | sizeof(struct kvm_debugregs))) | |
2989 | break; | |
2990 | ||
2991 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2992 | break; | |
2993 | } | |
2d5b5a66 | 2994 | case KVM_GET_XSAVE: { |
d1ac91d8 | 2995 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2996 | r = -ENOMEM; |
d1ac91d8 | 2997 | if (!u.xsave) |
2d5b5a66 SY |
2998 | break; |
2999 | ||
d1ac91d8 | 3000 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3001 | |
3002 | r = -EFAULT; | |
d1ac91d8 | 3003 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3004 | break; |
3005 | r = 0; | |
3006 | break; | |
3007 | } | |
3008 | case KVM_SET_XSAVE: { | |
d1ac91d8 | 3009 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3010 | r = -ENOMEM; |
d1ac91d8 | 3011 | if (!u.xsave) |
2d5b5a66 SY |
3012 | break; |
3013 | ||
3014 | r = -EFAULT; | |
d1ac91d8 | 3015 | if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3016 | break; |
3017 | ||
d1ac91d8 | 3018 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3019 | break; |
3020 | } | |
3021 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3022 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3023 | r = -ENOMEM; |
d1ac91d8 | 3024 | if (!u.xcrs) |
2d5b5a66 SY |
3025 | break; |
3026 | ||
d1ac91d8 | 3027 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3028 | |
3029 | r = -EFAULT; | |
d1ac91d8 | 3030 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3031 | sizeof(struct kvm_xcrs))) |
3032 | break; | |
3033 | r = 0; | |
3034 | break; | |
3035 | } | |
3036 | case KVM_SET_XCRS: { | |
d1ac91d8 | 3037 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3038 | r = -ENOMEM; |
d1ac91d8 | 3039 | if (!u.xcrs) |
2d5b5a66 SY |
3040 | break; |
3041 | ||
3042 | r = -EFAULT; | |
d1ac91d8 | 3043 | if (copy_from_user(u.xcrs, argp, |
2d5b5a66 SY |
3044 | sizeof(struct kvm_xcrs))) |
3045 | break; | |
3046 | ||
d1ac91d8 | 3047 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3048 | break; |
3049 | } | |
313a3dc7 CO |
3050 | default: |
3051 | r = -EINVAL; | |
3052 | } | |
3053 | out: | |
d1ac91d8 | 3054 | kfree(u.buffer); |
313a3dc7 CO |
3055 | return r; |
3056 | } | |
3057 | ||
1fe779f8 CO |
3058 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3059 | { | |
3060 | int ret; | |
3061 | ||
3062 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
3063 | return -1; | |
3064 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
3065 | return ret; | |
3066 | } | |
3067 | ||
b927a3ce SY |
3068 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3069 | u64 ident_addr) | |
3070 | { | |
3071 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3072 | return 0; | |
3073 | } | |
3074 | ||
1fe779f8 CO |
3075 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3076 | u32 kvm_nr_mmu_pages) | |
3077 | { | |
3078 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3079 | return -EINVAL; | |
3080 | ||
79fac95e | 3081 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 3082 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
3083 | |
3084 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3085 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3086 | |
7c8a83b7 | 3087 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 3088 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3089 | return 0; |
3090 | } | |
3091 | ||
3092 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3093 | { | |
39de71ec | 3094 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3095 | } |
3096 | ||
1fe779f8 CO |
3097 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3098 | { | |
3099 | int r; | |
3100 | ||
3101 | r = 0; | |
3102 | switch (chip->chip_id) { | |
3103 | case KVM_IRQCHIP_PIC_MASTER: | |
3104 | memcpy(&chip->chip.pic, | |
3105 | &pic_irqchip(kvm)->pics[0], | |
3106 | sizeof(struct kvm_pic_state)); | |
3107 | break; | |
3108 | case KVM_IRQCHIP_PIC_SLAVE: | |
3109 | memcpy(&chip->chip.pic, | |
3110 | &pic_irqchip(kvm)->pics[1], | |
3111 | sizeof(struct kvm_pic_state)); | |
3112 | break; | |
3113 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3114 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3115 | break; |
3116 | default: | |
3117 | r = -EINVAL; | |
3118 | break; | |
3119 | } | |
3120 | return r; | |
3121 | } | |
3122 | ||
3123 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3124 | { | |
3125 | int r; | |
3126 | ||
3127 | r = 0; | |
3128 | switch (chip->chip_id) { | |
3129 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3130 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3131 | memcpy(&pic_irqchip(kvm)->pics[0], |
3132 | &chip->chip.pic, | |
3133 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3134 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3135 | break; |
3136 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3137 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3138 | memcpy(&pic_irqchip(kvm)->pics[1], |
3139 | &chip->chip.pic, | |
3140 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3141 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3142 | break; |
3143 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3144 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3145 | break; |
3146 | default: | |
3147 | r = -EINVAL; | |
3148 | break; | |
3149 | } | |
3150 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3151 | return r; | |
3152 | } | |
3153 | ||
e0f63cb9 SY |
3154 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3155 | { | |
3156 | int r = 0; | |
3157 | ||
894a9c55 | 3158 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3159 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3160 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3161 | return r; |
3162 | } | |
3163 | ||
3164 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3165 | { | |
3166 | int r = 0; | |
3167 | ||
894a9c55 | 3168 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3169 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3170 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3171 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3172 | return r; | |
3173 | } | |
3174 | ||
3175 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3176 | { | |
3177 | int r = 0; | |
3178 | ||
3179 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3180 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3181 | sizeof(ps->channels)); | |
3182 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3183 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3184 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3185 | return r; |
3186 | } | |
3187 | ||
3188 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3189 | { | |
3190 | int r = 0, start = 0; | |
3191 | u32 prev_legacy, cur_legacy; | |
3192 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3193 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3194 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3195 | if (!prev_legacy && cur_legacy) | |
3196 | start = 1; | |
3197 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3198 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3199 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3200 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3201 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3202 | return r; |
3203 | } | |
3204 | ||
52d939a0 MT |
3205 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3206 | struct kvm_reinject_control *control) | |
3207 | { | |
3208 | if (!kvm->arch.vpit) | |
3209 | return -ENXIO; | |
894a9c55 | 3210 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 3211 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 3212 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3213 | return 0; |
3214 | } | |
3215 | ||
5bb064dc ZX |
3216 | /* |
3217 | * Get (and clear) the dirty memory log for a memory slot. | |
3218 | */ | |
3219 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
3220 | struct kvm_dirty_log *log) | |
3221 | { | |
87bf6e7d | 3222 | int r, i; |
5bb064dc | 3223 | struct kvm_memory_slot *memslot; |
87bf6e7d | 3224 | unsigned long n; |
b050b015 | 3225 | unsigned long is_dirty = 0; |
5bb064dc | 3226 | |
79fac95e | 3227 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3228 | |
b050b015 MT |
3229 | r = -EINVAL; |
3230 | if (log->slot >= KVM_MEMORY_SLOTS) | |
3231 | goto out; | |
3232 | ||
3233 | memslot = &kvm->memslots->memslots[log->slot]; | |
3234 | r = -ENOENT; | |
3235 | if (!memslot->dirty_bitmap) | |
3236 | goto out; | |
3237 | ||
87bf6e7d | 3238 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3239 | |
b050b015 MT |
3240 | for (i = 0; !is_dirty && i < n/sizeof(long); i++) |
3241 | is_dirty = memslot->dirty_bitmap[i]; | |
5bb064dc ZX |
3242 | |
3243 | /* If nothing is dirty, don't bother messing with page tables. */ | |
3244 | if (is_dirty) { | |
b050b015 | 3245 | struct kvm_memslots *slots, *old_slots; |
914ebccd | 3246 | unsigned long *dirty_bitmap; |
b050b015 | 3247 | |
515a0127 TY |
3248 | dirty_bitmap = memslot->dirty_bitmap_head; |
3249 | if (memslot->dirty_bitmap == dirty_bitmap) | |
3250 | dirty_bitmap += n / sizeof(long); | |
914ebccd | 3251 | memset(dirty_bitmap, 0, n); |
b050b015 | 3252 | |
914ebccd TY |
3253 | r = -ENOMEM; |
3254 | slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL); | |
515a0127 | 3255 | if (!slots) |
914ebccd | 3256 | goto out; |
b050b015 MT |
3257 | memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots)); |
3258 | slots->memslots[log->slot].dirty_bitmap = dirty_bitmap; | |
49c7754c | 3259 | slots->generation++; |
b050b015 MT |
3260 | |
3261 | old_slots = kvm->memslots; | |
3262 | rcu_assign_pointer(kvm->memslots, slots); | |
3263 | synchronize_srcu_expedited(&kvm->srcu); | |
3264 | dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap; | |
3265 | kfree(old_slots); | |
914ebccd | 3266 | |
edde99ce MT |
3267 | spin_lock(&kvm->mmu_lock); |
3268 | kvm_mmu_slot_remove_write_access(kvm, log->slot); | |
3269 | spin_unlock(&kvm->mmu_lock); | |
3270 | ||
914ebccd | 3271 | r = -EFAULT; |
515a0127 | 3272 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) |
914ebccd | 3273 | goto out; |
914ebccd TY |
3274 | } else { |
3275 | r = -EFAULT; | |
3276 | if (clear_user(log->dirty_bitmap, n)) | |
3277 | goto out; | |
5bb064dc | 3278 | } |
b050b015 | 3279 | |
5bb064dc ZX |
3280 | r = 0; |
3281 | out: | |
79fac95e | 3282 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3283 | return r; |
3284 | } | |
3285 | ||
1fe779f8 CO |
3286 | long kvm_arch_vm_ioctl(struct file *filp, |
3287 | unsigned int ioctl, unsigned long arg) | |
3288 | { | |
3289 | struct kvm *kvm = filp->private_data; | |
3290 | void __user *argp = (void __user *)arg; | |
367e1319 | 3291 | int r = -ENOTTY; |
f0d66275 DH |
3292 | /* |
3293 | * This union makes it completely explicit to gcc-3.x | |
3294 | * that these two variables' stack usage should be | |
3295 | * combined, not added together. | |
3296 | */ | |
3297 | union { | |
3298 | struct kvm_pit_state ps; | |
e9f42757 | 3299 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3300 | struct kvm_pit_config pit_config; |
f0d66275 | 3301 | } u; |
1fe779f8 CO |
3302 | |
3303 | switch (ioctl) { | |
3304 | case KVM_SET_TSS_ADDR: | |
3305 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
3306 | if (r < 0) | |
3307 | goto out; | |
3308 | break; | |
b927a3ce SY |
3309 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3310 | u64 ident_addr; | |
3311 | ||
3312 | r = -EFAULT; | |
3313 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3314 | goto out; | |
3315 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
3316 | if (r < 0) | |
3317 | goto out; | |
3318 | break; | |
3319 | } | |
1fe779f8 CO |
3320 | case KVM_SET_NR_MMU_PAGES: |
3321 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
3322 | if (r) | |
3323 | goto out; | |
3324 | break; | |
3325 | case KVM_GET_NR_MMU_PAGES: | |
3326 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3327 | break; | |
3ddea128 MT |
3328 | case KVM_CREATE_IRQCHIP: { |
3329 | struct kvm_pic *vpic; | |
3330 | ||
3331 | mutex_lock(&kvm->lock); | |
3332 | r = -EEXIST; | |
3333 | if (kvm->arch.vpic) | |
3334 | goto create_irqchip_unlock; | |
1fe779f8 | 3335 | r = -ENOMEM; |
3ddea128 MT |
3336 | vpic = kvm_create_pic(kvm); |
3337 | if (vpic) { | |
1fe779f8 CO |
3338 | r = kvm_ioapic_init(kvm); |
3339 | if (r) { | |
175504cd | 3340 | mutex_lock(&kvm->slots_lock); |
72bb2fcd WY |
3341 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
3342 | &vpic->dev); | |
175504cd | 3343 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3344 | kfree(vpic); |
3345 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3346 | } |
3347 | } else | |
3ddea128 MT |
3348 | goto create_irqchip_unlock; |
3349 | smp_wmb(); | |
3350 | kvm->arch.vpic = vpic; | |
3351 | smp_wmb(); | |
399ec807 AK |
3352 | r = kvm_setup_default_irq_routing(kvm); |
3353 | if (r) { | |
175504cd | 3354 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3355 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3356 | kvm_ioapic_destroy(kvm); |
3357 | kvm_destroy_pic(kvm); | |
3ddea128 | 3358 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3359 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3360 | } |
3ddea128 MT |
3361 | create_irqchip_unlock: |
3362 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3363 | break; |
3ddea128 | 3364 | } |
7837699f | 3365 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3366 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3367 | goto create_pit; | |
3368 | case KVM_CREATE_PIT2: | |
3369 | r = -EFAULT; | |
3370 | if (copy_from_user(&u.pit_config, argp, | |
3371 | sizeof(struct kvm_pit_config))) | |
3372 | goto out; | |
3373 | create_pit: | |
79fac95e | 3374 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3375 | r = -EEXIST; |
3376 | if (kvm->arch.vpit) | |
3377 | goto create_pit_unlock; | |
7837699f | 3378 | r = -ENOMEM; |
c5ff41ce | 3379 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3380 | if (kvm->arch.vpit) |
3381 | r = 0; | |
269e05e4 | 3382 | create_pit_unlock: |
79fac95e | 3383 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3384 | break; |
4925663a | 3385 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
3386 | case KVM_IRQ_LINE: { |
3387 | struct kvm_irq_level irq_event; | |
3388 | ||
3389 | r = -EFAULT; | |
3390 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
3391 | goto out; | |
160d2f6c | 3392 | r = -ENXIO; |
1fe779f8 | 3393 | if (irqchip_in_kernel(kvm)) { |
4925663a | 3394 | __s32 status; |
4925663a GN |
3395 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
3396 | irq_event.irq, irq_event.level); | |
4925663a | 3397 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
160d2f6c | 3398 | r = -EFAULT; |
4925663a GN |
3399 | irq_event.status = status; |
3400 | if (copy_to_user(argp, &irq_event, | |
3401 | sizeof irq_event)) | |
3402 | goto out; | |
3403 | } | |
1fe779f8 CO |
3404 | r = 0; |
3405 | } | |
3406 | break; | |
3407 | } | |
3408 | case KVM_GET_IRQCHIP: { | |
3409 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3410 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3411 | |
f0d66275 DH |
3412 | r = -ENOMEM; |
3413 | if (!chip) | |
1fe779f8 | 3414 | goto out; |
f0d66275 DH |
3415 | r = -EFAULT; |
3416 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3417 | goto get_irqchip_out; | |
1fe779f8 CO |
3418 | r = -ENXIO; |
3419 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3420 | goto get_irqchip_out; |
3421 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3422 | if (r) |
f0d66275 | 3423 | goto get_irqchip_out; |
1fe779f8 | 3424 | r = -EFAULT; |
f0d66275 DH |
3425 | if (copy_to_user(argp, chip, sizeof *chip)) |
3426 | goto get_irqchip_out; | |
1fe779f8 | 3427 | r = 0; |
f0d66275 DH |
3428 | get_irqchip_out: |
3429 | kfree(chip); | |
3430 | if (r) | |
3431 | goto out; | |
1fe779f8 CO |
3432 | break; |
3433 | } | |
3434 | case KVM_SET_IRQCHIP: { | |
3435 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3436 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3437 | |
f0d66275 DH |
3438 | r = -ENOMEM; |
3439 | if (!chip) | |
1fe779f8 | 3440 | goto out; |
f0d66275 DH |
3441 | r = -EFAULT; |
3442 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3443 | goto set_irqchip_out; | |
1fe779f8 CO |
3444 | r = -ENXIO; |
3445 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3446 | goto set_irqchip_out; |
3447 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3448 | if (r) |
f0d66275 | 3449 | goto set_irqchip_out; |
1fe779f8 | 3450 | r = 0; |
f0d66275 DH |
3451 | set_irqchip_out: |
3452 | kfree(chip); | |
3453 | if (r) | |
3454 | goto out; | |
1fe779f8 CO |
3455 | break; |
3456 | } | |
e0f63cb9 | 3457 | case KVM_GET_PIT: { |
e0f63cb9 | 3458 | r = -EFAULT; |
f0d66275 | 3459 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3460 | goto out; |
3461 | r = -ENXIO; | |
3462 | if (!kvm->arch.vpit) | |
3463 | goto out; | |
f0d66275 | 3464 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3465 | if (r) |
3466 | goto out; | |
3467 | r = -EFAULT; | |
f0d66275 | 3468 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3469 | goto out; |
3470 | r = 0; | |
3471 | break; | |
3472 | } | |
3473 | case KVM_SET_PIT: { | |
e0f63cb9 | 3474 | r = -EFAULT; |
f0d66275 | 3475 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3476 | goto out; |
3477 | r = -ENXIO; | |
3478 | if (!kvm->arch.vpit) | |
3479 | goto out; | |
f0d66275 | 3480 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3481 | if (r) |
3482 | goto out; | |
3483 | r = 0; | |
3484 | break; | |
3485 | } | |
e9f42757 BK |
3486 | case KVM_GET_PIT2: { |
3487 | r = -ENXIO; | |
3488 | if (!kvm->arch.vpit) | |
3489 | goto out; | |
3490 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3491 | if (r) | |
3492 | goto out; | |
3493 | r = -EFAULT; | |
3494 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3495 | goto out; | |
3496 | r = 0; | |
3497 | break; | |
3498 | } | |
3499 | case KVM_SET_PIT2: { | |
3500 | r = -EFAULT; | |
3501 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3502 | goto out; | |
3503 | r = -ENXIO; | |
3504 | if (!kvm->arch.vpit) | |
3505 | goto out; | |
3506 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3507 | if (r) | |
3508 | goto out; | |
3509 | r = 0; | |
3510 | break; | |
3511 | } | |
52d939a0 MT |
3512 | case KVM_REINJECT_CONTROL: { |
3513 | struct kvm_reinject_control control; | |
3514 | r = -EFAULT; | |
3515 | if (copy_from_user(&control, argp, sizeof(control))) | |
3516 | goto out; | |
3517 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3518 | if (r) | |
3519 | goto out; | |
3520 | r = 0; | |
3521 | break; | |
3522 | } | |
ffde22ac ES |
3523 | case KVM_XEN_HVM_CONFIG: { |
3524 | r = -EFAULT; | |
3525 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3526 | sizeof(struct kvm_xen_hvm_config))) | |
3527 | goto out; | |
3528 | r = -EINVAL; | |
3529 | if (kvm->arch.xen_hvm_config.flags) | |
3530 | goto out; | |
3531 | r = 0; | |
3532 | break; | |
3533 | } | |
afbcf7ab | 3534 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3535 | struct kvm_clock_data user_ns; |
3536 | u64 now_ns; | |
3537 | s64 delta; | |
3538 | ||
3539 | r = -EFAULT; | |
3540 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3541 | goto out; | |
3542 | ||
3543 | r = -EINVAL; | |
3544 | if (user_ns.flags) | |
3545 | goto out; | |
3546 | ||
3547 | r = 0; | |
395c6b0a | 3548 | local_irq_disable(); |
759379dd | 3549 | now_ns = get_kernel_ns(); |
afbcf7ab | 3550 | delta = user_ns.clock - now_ns; |
395c6b0a | 3551 | local_irq_enable(); |
afbcf7ab GC |
3552 | kvm->arch.kvmclock_offset = delta; |
3553 | break; | |
3554 | } | |
3555 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3556 | struct kvm_clock_data user_ns; |
3557 | u64 now_ns; | |
3558 | ||
395c6b0a | 3559 | local_irq_disable(); |
759379dd | 3560 | now_ns = get_kernel_ns(); |
afbcf7ab | 3561 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3562 | local_irq_enable(); |
afbcf7ab | 3563 | user_ns.flags = 0; |
97e69aa6 | 3564 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
3565 | |
3566 | r = -EFAULT; | |
3567 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3568 | goto out; | |
3569 | r = 0; | |
3570 | break; | |
3571 | } | |
3572 | ||
1fe779f8 CO |
3573 | default: |
3574 | ; | |
3575 | } | |
3576 | out: | |
3577 | return r; | |
3578 | } | |
3579 | ||
a16b043c | 3580 | static void kvm_init_msr_list(void) |
043405e1 CO |
3581 | { |
3582 | u32 dummy[2]; | |
3583 | unsigned i, j; | |
3584 | ||
e3267cbb GC |
3585 | /* skip the first msrs in the list. KVM-specific */ |
3586 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3587 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3588 | continue; | |
3589 | if (j < i) | |
3590 | msrs_to_save[j] = msrs_to_save[i]; | |
3591 | j++; | |
3592 | } | |
3593 | num_msrs_to_save = j; | |
3594 | } | |
3595 | ||
bda9020e MT |
3596 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3597 | const void *v) | |
bbd9b64e | 3598 | { |
70252a10 AK |
3599 | int handled = 0; |
3600 | int n; | |
3601 | ||
3602 | do { | |
3603 | n = min(len, 8); | |
3604 | if (!(vcpu->arch.apic && | |
3605 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) | |
3606 | && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3607 | break; | |
3608 | handled += n; | |
3609 | addr += n; | |
3610 | len -= n; | |
3611 | v += n; | |
3612 | } while (len); | |
bbd9b64e | 3613 | |
70252a10 | 3614 | return handled; |
bbd9b64e CO |
3615 | } |
3616 | ||
bda9020e | 3617 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3618 | { |
70252a10 AK |
3619 | int handled = 0; |
3620 | int n; | |
3621 | ||
3622 | do { | |
3623 | n = min(len, 8); | |
3624 | if (!(vcpu->arch.apic && | |
3625 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) | |
3626 | && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3627 | break; | |
3628 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
3629 | handled += n; | |
3630 | addr += n; | |
3631 | len -= n; | |
3632 | v += n; | |
3633 | } while (len); | |
bbd9b64e | 3634 | |
70252a10 | 3635 | return handled; |
bbd9b64e CO |
3636 | } |
3637 | ||
2dafc6c2 GN |
3638 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3639 | struct kvm_segment *var, int seg) | |
3640 | { | |
3641 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3642 | } | |
3643 | ||
3644 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3645 | struct kvm_segment *var, int seg) | |
3646 | { | |
3647 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3648 | } | |
3649 | ||
c30a358d JR |
3650 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
3651 | { | |
3652 | return gpa; | |
3653 | } | |
3654 | ||
02f59dc9 JR |
3655 | static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
3656 | { | |
3657 | gpa_t t_gpa; | |
ab9ae313 | 3658 | struct x86_exception exception; |
02f59dc9 JR |
3659 | |
3660 | BUG_ON(!mmu_is_nested(vcpu)); | |
3661 | ||
3662 | /* NPT walks are always user-walks */ | |
3663 | access |= PFERR_USER_MASK; | |
ab9ae313 | 3664 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); |
02f59dc9 JR |
3665 | |
3666 | return t_gpa; | |
3667 | } | |
3668 | ||
ab9ae313 AK |
3669 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
3670 | struct x86_exception *exception) | |
1871c602 GN |
3671 | { |
3672 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 3673 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3674 | } |
3675 | ||
ab9ae313 AK |
3676 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
3677 | struct x86_exception *exception) | |
1871c602 GN |
3678 | { |
3679 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3680 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 3681 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3682 | } |
3683 | ||
ab9ae313 AK |
3684 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
3685 | struct x86_exception *exception) | |
1871c602 GN |
3686 | { |
3687 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3688 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 3689 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3690 | } |
3691 | ||
3692 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
3693 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
3694 | struct x86_exception *exception) | |
1871c602 | 3695 | { |
ab9ae313 | 3696 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
3697 | } |
3698 | ||
3699 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3700 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 3701 | struct x86_exception *exception) |
bbd9b64e CO |
3702 | { |
3703 | void *data = val; | |
10589a46 | 3704 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3705 | |
3706 | while (bytes) { | |
14dfe855 | 3707 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 3708 | exception); |
bbd9b64e | 3709 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3710 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3711 | int ret; |
3712 | ||
bcc55cba | 3713 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3714 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e | 3715 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3716 | if (ret < 0) { |
c3cd7ffa | 3717 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3718 | goto out; |
3719 | } | |
bbd9b64e | 3720 | |
77c2002e IE |
3721 | bytes -= toread; |
3722 | data += toread; | |
3723 | addr += toread; | |
bbd9b64e | 3724 | } |
10589a46 | 3725 | out: |
10589a46 | 3726 | return r; |
bbd9b64e | 3727 | } |
77c2002e | 3728 | |
1871c602 GN |
3729 | /* used for instruction fetching */ |
3730 | static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
bcc55cba AK |
3731 | struct kvm_vcpu *vcpu, |
3732 | struct x86_exception *exception) | |
1871c602 GN |
3733 | { |
3734 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3735 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, | |
bcc55cba AK |
3736 | access | PFERR_FETCH_MASK, |
3737 | exception); | |
1871c602 GN |
3738 | } |
3739 | ||
3740 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
bcc55cba AK |
3741 | struct kvm_vcpu *vcpu, |
3742 | struct x86_exception *exception) | |
1871c602 GN |
3743 | { |
3744 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3745 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, | |
bcc55cba | 3746 | exception); |
1871c602 GN |
3747 | } |
3748 | ||
3749 | static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes, | |
bcc55cba AK |
3750 | struct kvm_vcpu *vcpu, |
3751 | struct x86_exception *exception) | |
1871c602 | 3752 | { |
bcc55cba | 3753 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
3754 | } |
3755 | ||
7972995b | 3756 | static int kvm_write_guest_virt_system(gva_t addr, void *val, |
2dafc6c2 | 3757 | unsigned int bytes, |
7972995b | 3758 | struct kvm_vcpu *vcpu, |
bcc55cba | 3759 | struct x86_exception *exception) |
77c2002e IE |
3760 | { |
3761 | void *data = val; | |
3762 | int r = X86EMUL_CONTINUE; | |
3763 | ||
3764 | while (bytes) { | |
14dfe855 JR |
3765 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
3766 | PFERR_WRITE_MASK, | |
ab9ae313 | 3767 | exception); |
77c2002e IE |
3768 | unsigned offset = addr & (PAGE_SIZE-1); |
3769 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3770 | int ret; | |
3771 | ||
bcc55cba | 3772 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3773 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
3774 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
3775 | if (ret < 0) { | |
c3cd7ffa | 3776 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3777 | goto out; |
3778 | } | |
3779 | ||
3780 | bytes -= towrite; | |
3781 | data += towrite; | |
3782 | addr += towrite; | |
3783 | } | |
3784 | out: | |
3785 | return r; | |
3786 | } | |
3787 | ||
bbd9b64e CO |
3788 | static int emulator_read_emulated(unsigned long addr, |
3789 | void *val, | |
3790 | unsigned int bytes, | |
bcc55cba | 3791 | struct x86_exception *exception, |
bbd9b64e CO |
3792 | struct kvm_vcpu *vcpu) |
3793 | { | |
bbd9b64e | 3794 | gpa_t gpa; |
70252a10 | 3795 | int handled; |
bbd9b64e CO |
3796 | |
3797 | if (vcpu->mmio_read_completed) { | |
3798 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
3799 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
3800 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
3801 | vcpu->mmio_read_completed = 0; |
3802 | return X86EMUL_CONTINUE; | |
3803 | } | |
3804 | ||
ab9ae313 | 3805 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception); |
1871c602 | 3806 | |
8fe681e9 | 3807 | if (gpa == UNMAPPED_GVA) |
1871c602 | 3808 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3809 | |
3810 | /* For APIC access vmexit */ | |
3811 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3812 | goto mmio; | |
3813 | ||
bcc55cba AK |
3814 | if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception) |
3815 | == X86EMUL_CONTINUE) | |
bbd9b64e | 3816 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3817 | |
3818 | mmio: | |
3819 | /* | |
3820 | * Is this MMIO handled locally? | |
3821 | */ | |
70252a10 AK |
3822 | handled = vcpu_mmio_read(vcpu, gpa, bytes, val); |
3823 | ||
3824 | if (handled == bytes) | |
bbd9b64e | 3825 | return X86EMUL_CONTINUE; |
70252a10 AK |
3826 | |
3827 | gpa += handled; | |
3828 | bytes -= handled; | |
3829 | val += handled; | |
aec51dc4 AK |
3830 | |
3831 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
3832 | |
3833 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3834 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3835 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
cef4dea0 AK |
3836 | vcpu->mmio_size = bytes; |
3837 | vcpu->run->mmio.len = min(vcpu->mmio_size, 8); | |
411c35b7 | 3838 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0; |
cef4dea0 | 3839 | vcpu->mmio_index = 0; |
bbd9b64e | 3840 | |
c3cd7ffa | 3841 | return X86EMUL_IO_NEEDED; |
bbd9b64e CO |
3842 | } |
3843 | ||
3200f405 | 3844 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 3845 | const void *val, int bytes) |
bbd9b64e CO |
3846 | { |
3847 | int ret; | |
3848 | ||
3849 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3850 | if (ret < 0) |
bbd9b64e | 3851 | return 0; |
ad218f85 | 3852 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
3853 | return 1; |
3854 | } | |
3855 | ||
3856 | static int emulator_write_emulated_onepage(unsigned long addr, | |
3857 | const void *val, | |
3858 | unsigned int bytes, | |
bcc55cba | 3859 | struct x86_exception *exception, |
bbd9b64e CO |
3860 | struct kvm_vcpu *vcpu) |
3861 | { | |
10589a46 | 3862 | gpa_t gpa; |
70252a10 | 3863 | int handled; |
10589a46 | 3864 | |
ab9ae313 | 3865 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception); |
bbd9b64e | 3866 | |
8fe681e9 | 3867 | if (gpa == UNMAPPED_GVA) |
bbd9b64e | 3868 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3869 | |
3870 | /* For APIC access vmexit */ | |
3871 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3872 | goto mmio; | |
3873 | ||
3874 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
3875 | return X86EMUL_CONTINUE; | |
3876 | ||
3877 | mmio: | |
aec51dc4 | 3878 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
3879 | /* |
3880 | * Is this MMIO handled locally? | |
3881 | */ | |
70252a10 AK |
3882 | handled = vcpu_mmio_write(vcpu, gpa, bytes, val); |
3883 | if (handled == bytes) | |
bbd9b64e | 3884 | return X86EMUL_CONTINUE; |
bbd9b64e | 3885 | |
70252a10 AK |
3886 | gpa += handled; |
3887 | bytes -= handled; | |
3888 | val += handled; | |
3889 | ||
bbd9b64e | 3890 | vcpu->mmio_needed = 1; |
cef4dea0 | 3891 | memcpy(vcpu->mmio_data, val, bytes); |
411c35b7 GN |
3892 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3893 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
cef4dea0 AK |
3894 | vcpu->mmio_size = bytes; |
3895 | vcpu->run->mmio.len = min(vcpu->mmio_size, 8); | |
411c35b7 | 3896 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1; |
cef4dea0 AK |
3897 | memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8); |
3898 | vcpu->mmio_index = 0; | |
bbd9b64e CO |
3899 | |
3900 | return X86EMUL_CONTINUE; | |
3901 | } | |
3902 | ||
3903 | int emulator_write_emulated(unsigned long addr, | |
8f6abd06 GN |
3904 | const void *val, |
3905 | unsigned int bytes, | |
bcc55cba | 3906 | struct x86_exception *exception, |
8f6abd06 | 3907 | struct kvm_vcpu *vcpu) |
bbd9b64e CO |
3908 | { |
3909 | /* Crossing a page boundary? */ | |
3910 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
3911 | int rc, now; | |
3912 | ||
3913 | now = -addr & ~PAGE_MASK; | |
bcc55cba | 3914 | rc = emulator_write_emulated_onepage(addr, val, now, exception, |
8fe681e9 | 3915 | vcpu); |
bbd9b64e CO |
3916 | if (rc != X86EMUL_CONTINUE) |
3917 | return rc; | |
3918 | addr += now; | |
3919 | val += now; | |
3920 | bytes -= now; | |
3921 | } | |
bcc55cba | 3922 | return emulator_write_emulated_onepage(addr, val, bytes, exception, |
8fe681e9 | 3923 | vcpu); |
bbd9b64e | 3924 | } |
bbd9b64e | 3925 | |
daea3e73 AK |
3926 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3927 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3928 | ||
3929 | #ifdef CONFIG_X86_64 | |
3930 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3931 | #else | |
3932 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 3933 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
3934 | #endif |
3935 | ||
bbd9b64e CO |
3936 | static int emulator_cmpxchg_emulated(unsigned long addr, |
3937 | const void *old, | |
3938 | const void *new, | |
3939 | unsigned int bytes, | |
bcc55cba | 3940 | struct x86_exception *exception, |
bbd9b64e CO |
3941 | struct kvm_vcpu *vcpu) |
3942 | { | |
daea3e73 AK |
3943 | gpa_t gpa; |
3944 | struct page *page; | |
3945 | char *kaddr; | |
3946 | bool exchanged; | |
2bacc55c | 3947 | |
daea3e73 AK |
3948 | /* guests cmpxchg8b have to be emulated atomically */ |
3949 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3950 | goto emul_write; | |
10589a46 | 3951 | |
daea3e73 | 3952 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3953 | |
daea3e73 AK |
3954 | if (gpa == UNMAPPED_GVA || |
3955 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3956 | goto emul_write; | |
2bacc55c | 3957 | |
daea3e73 AK |
3958 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3959 | goto emul_write; | |
72dc67a6 | 3960 | |
daea3e73 | 3961 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
c19b8bd6 WY |
3962 | if (is_error_page(page)) { |
3963 | kvm_release_page_clean(page); | |
3964 | goto emul_write; | |
3965 | } | |
72dc67a6 | 3966 | |
daea3e73 AK |
3967 | kaddr = kmap_atomic(page, KM_USER0); |
3968 | kaddr += offset_in_page(gpa); | |
3969 | switch (bytes) { | |
3970 | case 1: | |
3971 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3972 | break; | |
3973 | case 2: | |
3974 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3975 | break; | |
3976 | case 4: | |
3977 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3978 | break; | |
3979 | case 8: | |
3980 | exchanged = CMPXCHG64(kaddr, old, new); | |
3981 | break; | |
3982 | default: | |
3983 | BUG(); | |
2bacc55c | 3984 | } |
daea3e73 AK |
3985 | kunmap_atomic(kaddr, KM_USER0); |
3986 | kvm_release_page_dirty(page); | |
3987 | ||
3988 | if (!exchanged) | |
3989 | return X86EMUL_CMPXCHG_FAILED; | |
3990 | ||
8f6abd06 GN |
3991 | kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1); |
3992 | ||
3993 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 3994 | |
3200f405 | 3995 | emul_write: |
daea3e73 | 3996 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3997 | |
bcc55cba | 3998 | return emulator_write_emulated(addr, new, bytes, exception, vcpu); |
bbd9b64e CO |
3999 | } |
4000 | ||
cf8f70bf GN |
4001 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4002 | { | |
4003 | /* TODO: String I/O for in kernel device */ | |
4004 | int r; | |
4005 | ||
4006 | if (vcpu->arch.pio.in) | |
4007 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
4008 | vcpu->arch.pio.size, pd); | |
4009 | else | |
4010 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
4011 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
4012 | pd); | |
4013 | return r; | |
4014 | } | |
4015 | ||
4016 | ||
4017 | static int emulator_pio_in_emulated(int size, unsigned short port, void *val, | |
4018 | unsigned int count, struct kvm_vcpu *vcpu) | |
4019 | { | |
7972995b | 4020 | if (vcpu->arch.pio.count) |
cf8f70bf GN |
4021 | goto data_avail; |
4022 | ||
61cfab2e | 4023 | trace_kvm_pio(0, port, size, count); |
cf8f70bf GN |
4024 | |
4025 | vcpu->arch.pio.port = port; | |
4026 | vcpu->arch.pio.in = 1; | |
7972995b | 4027 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4028 | vcpu->arch.pio.size = size; |
4029 | ||
4030 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
4031 | data_avail: | |
4032 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 4033 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4034 | return 1; |
4035 | } | |
4036 | ||
4037 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
4038 | vcpu->run->io.direction = KVM_EXIT_IO_IN; | |
4039 | vcpu->run->io.size = size; | |
4040 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4041 | vcpu->run->io.count = count; | |
4042 | vcpu->run->io.port = port; | |
4043 | ||
4044 | return 0; | |
4045 | } | |
4046 | ||
4047 | static int emulator_pio_out_emulated(int size, unsigned short port, | |
4048 | const void *val, unsigned int count, | |
4049 | struct kvm_vcpu *vcpu) | |
4050 | { | |
61cfab2e | 4051 | trace_kvm_pio(1, port, size, count); |
cf8f70bf GN |
4052 | |
4053 | vcpu->arch.pio.port = port; | |
4054 | vcpu->arch.pio.in = 0; | |
7972995b | 4055 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4056 | vcpu->arch.pio.size = size; |
4057 | ||
4058 | memcpy(vcpu->arch.pio_data, val, size * count); | |
4059 | ||
4060 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4061 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4062 | return 1; |
4063 | } | |
4064 | ||
4065 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
4066 | vcpu->run->io.direction = KVM_EXIT_IO_OUT; | |
4067 | vcpu->run->io.size = size; | |
4068 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4069 | vcpu->run->io.count = count; | |
4070 | vcpu->run->io.port = port; | |
4071 | ||
4072 | return 0; | |
4073 | } | |
4074 | ||
bbd9b64e CO |
4075 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4076 | { | |
4077 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4078 | } | |
4079 | ||
4080 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
4081 | { | |
a7052897 | 4082 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
4083 | return X86EMUL_CONTINUE; |
4084 | } | |
4085 | ||
f5f48ee1 SY |
4086 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
4087 | { | |
4088 | if (!need_emulate_wbinvd(vcpu)) | |
4089 | return X86EMUL_CONTINUE; | |
4090 | ||
4091 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4092 | int cpu = get_cpu(); |
4093 | ||
4094 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4095 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4096 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4097 | put_cpu(); |
f5f48ee1 | 4098 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4099 | } else |
4100 | wbinvd(); | |
f5f48ee1 SY |
4101 | return X86EMUL_CONTINUE; |
4102 | } | |
4103 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4104 | ||
bbd9b64e CO |
4105 | int emulate_clts(struct kvm_vcpu *vcpu) |
4106 | { | |
4d4ec087 | 4107 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
6b52d186 | 4108 | kvm_x86_ops->fpu_activate(vcpu); |
bbd9b64e CO |
4109 | return X86EMUL_CONTINUE; |
4110 | } | |
4111 | ||
35aa5375 | 4112 | int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu) |
bbd9b64e | 4113 | { |
338dbc97 | 4114 | return _kvm_get_dr(vcpu, dr, dest); |
bbd9b64e CO |
4115 | } |
4116 | ||
35aa5375 | 4117 | int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu) |
bbd9b64e | 4118 | { |
338dbc97 GN |
4119 | |
4120 | return __kvm_set_dr(vcpu, dr, value); | |
bbd9b64e CO |
4121 | } |
4122 | ||
52a46617 | 4123 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4124 | { |
52a46617 | 4125 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4126 | } |
4127 | ||
52a46617 | 4128 | static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu) |
bbd9b64e | 4129 | { |
52a46617 GN |
4130 | unsigned long value; |
4131 | ||
4132 | switch (cr) { | |
4133 | case 0: | |
4134 | value = kvm_read_cr0(vcpu); | |
4135 | break; | |
4136 | case 2: | |
4137 | value = vcpu->arch.cr2; | |
4138 | break; | |
4139 | case 3: | |
9f8fe504 | 4140 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4141 | break; |
4142 | case 4: | |
4143 | value = kvm_read_cr4(vcpu); | |
4144 | break; | |
4145 | case 8: | |
4146 | value = kvm_get_cr8(vcpu); | |
4147 | break; | |
4148 | default: | |
4149 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
4150 | return 0; | |
4151 | } | |
4152 | ||
4153 | return value; | |
4154 | } | |
4155 | ||
0f12244f | 4156 | static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu) |
52a46617 | 4157 | { |
0f12244f GN |
4158 | int res = 0; |
4159 | ||
52a46617 GN |
4160 | switch (cr) { |
4161 | case 0: | |
49a9b07e | 4162 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4163 | break; |
4164 | case 2: | |
4165 | vcpu->arch.cr2 = val; | |
4166 | break; | |
4167 | case 3: | |
2390218b | 4168 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4169 | break; |
4170 | case 4: | |
a83b29c6 | 4171 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4172 | break; |
4173 | case 8: | |
eea1cff9 | 4174 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4175 | break; |
4176 | default: | |
4177 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
0f12244f | 4178 | res = -1; |
52a46617 | 4179 | } |
0f12244f GN |
4180 | |
4181 | return res; | |
52a46617 GN |
4182 | } |
4183 | ||
9c537244 GN |
4184 | static int emulator_get_cpl(struct kvm_vcpu *vcpu) |
4185 | { | |
4186 | return kvm_x86_ops->get_cpl(vcpu); | |
4187 | } | |
4188 | ||
2dafc6c2 GN |
4189 | static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
4190 | { | |
4191 | kvm_x86_ops->get_gdt(vcpu, dt); | |
4192 | } | |
4193 | ||
160ce1f1 MG |
4194 | static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
4195 | { | |
4196 | kvm_x86_ops->get_idt(vcpu, dt); | |
4197 | } | |
4198 | ||
5951c442 GN |
4199 | static unsigned long emulator_get_cached_segment_base(int seg, |
4200 | struct kvm_vcpu *vcpu) | |
4201 | { | |
4202 | return get_segment_base(vcpu, seg); | |
4203 | } | |
4204 | ||
5601d05b GN |
4205 | static bool emulator_get_cached_descriptor(struct desc_struct *desc, u32 *base3, |
4206 | int seg, struct kvm_vcpu *vcpu) | |
2dafc6c2 GN |
4207 | { |
4208 | struct kvm_segment var; | |
4209 | ||
4210 | kvm_get_segment(vcpu, &var, seg); | |
4211 | ||
4212 | if (var.unusable) | |
4213 | return false; | |
4214 | ||
4215 | if (var.g) | |
4216 | var.limit >>= 12; | |
4217 | set_desc_limit(desc, var.limit); | |
4218 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4219 | #ifdef CONFIG_X86_64 |
4220 | if (base3) | |
4221 | *base3 = var.base >> 32; | |
4222 | #endif | |
2dafc6c2 GN |
4223 | desc->type = var.type; |
4224 | desc->s = var.s; | |
4225 | desc->dpl = var.dpl; | |
4226 | desc->p = var.present; | |
4227 | desc->avl = var.avl; | |
4228 | desc->l = var.l; | |
4229 | desc->d = var.db; | |
4230 | desc->g = var.g; | |
4231 | ||
4232 | return true; | |
4233 | } | |
4234 | ||
5601d05b GN |
4235 | static void emulator_set_cached_descriptor(struct desc_struct *desc, u32 base3, |
4236 | int seg, struct kvm_vcpu *vcpu) | |
2dafc6c2 GN |
4237 | { |
4238 | struct kvm_segment var; | |
4239 | ||
4240 | /* needed to preserve selector */ | |
4241 | kvm_get_segment(vcpu, &var, seg); | |
4242 | ||
4243 | var.base = get_desc_base(desc); | |
5601d05b GN |
4244 | #ifdef CONFIG_X86_64 |
4245 | var.base |= ((u64)base3) << 32; | |
4246 | #endif | |
2dafc6c2 GN |
4247 | var.limit = get_desc_limit(desc); |
4248 | if (desc->g) | |
4249 | var.limit = (var.limit << 12) | 0xfff; | |
4250 | var.type = desc->type; | |
4251 | var.present = desc->p; | |
4252 | var.dpl = desc->dpl; | |
4253 | var.db = desc->d; | |
4254 | var.s = desc->s; | |
4255 | var.l = desc->l; | |
4256 | var.g = desc->g; | |
4257 | var.avl = desc->avl; | |
4258 | var.present = desc->p; | |
4259 | var.unusable = !var.present; | |
4260 | var.padding = 0; | |
4261 | ||
4262 | kvm_set_segment(vcpu, &var, seg); | |
4263 | return; | |
4264 | } | |
4265 | ||
4266 | static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu) | |
4267 | { | |
4268 | struct kvm_segment kvm_seg; | |
4269 | ||
4270 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4271 | return kvm_seg.selector; | |
4272 | } | |
4273 | ||
4274 | static void emulator_set_segment_selector(u16 sel, int seg, | |
4275 | struct kvm_vcpu *vcpu) | |
4276 | { | |
4277 | struct kvm_segment kvm_seg; | |
4278 | ||
4279 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4280 | kvm_seg.selector = sel; | |
4281 | kvm_set_segment(vcpu, &kvm_seg, seg); | |
4282 | } | |
4283 | ||
14af3f3c | 4284 | static struct x86_emulate_ops emulate_ops = { |
1871c602 | 4285 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4286 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4287 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4288 | .read_emulated = emulator_read_emulated, |
4289 | .write_emulated = emulator_write_emulated, | |
4290 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
cf8f70bf GN |
4291 | .pio_in_emulated = emulator_pio_in_emulated, |
4292 | .pio_out_emulated = emulator_pio_out_emulated, | |
2dafc6c2 GN |
4293 | .get_cached_descriptor = emulator_get_cached_descriptor, |
4294 | .set_cached_descriptor = emulator_set_cached_descriptor, | |
4295 | .get_segment_selector = emulator_get_segment_selector, | |
4296 | .set_segment_selector = emulator_set_segment_selector, | |
5951c442 | 4297 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4298 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4299 | .get_idt = emulator_get_idt, |
52a46617 GN |
4300 | .get_cr = emulator_get_cr, |
4301 | .set_cr = emulator_set_cr, | |
9c537244 | 4302 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4303 | .get_dr = emulator_get_dr, |
4304 | .set_dr = emulator_set_dr, | |
3fb1b5db GN |
4305 | .set_msr = kvm_set_msr, |
4306 | .get_msr = kvm_get_msr, | |
bbd9b64e CO |
4307 | }; |
4308 | ||
5fdbf976 MT |
4309 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
4310 | { | |
4311 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4312 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4313 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
4314 | vcpu->arch.regs_dirty = ~0; | |
4315 | } | |
4316 | ||
95cb2295 GN |
4317 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4318 | { | |
4319 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4320 | /* | |
4321 | * an sti; sti; sequence only disable interrupts for the first | |
4322 | * instruction. So, if the last instruction, be it emulated or | |
4323 | * not, left the system with the INT_STI flag enabled, it | |
4324 | * means that the last instruction is an sti. We should not | |
4325 | * leave the flag on in this case. The same goes for mov ss | |
4326 | */ | |
4327 | if (!(int_shadow & mask)) | |
4328 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4329 | } | |
4330 | ||
54b8486f GN |
4331 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
4332 | { | |
4333 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 4334 | if (ctxt->exception.vector == PF_VECTOR) |
6389ee94 | 4335 | kvm_propagate_fault(vcpu, &ctxt->exception); |
da9cb575 AK |
4336 | else if (ctxt->exception.error_code_valid) |
4337 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, | |
4338 | ctxt->exception.error_code); | |
54b8486f | 4339 | else |
da9cb575 | 4340 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
54b8486f GN |
4341 | } |
4342 | ||
8ec4722d MG |
4343 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4344 | { | |
4345 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; | |
4346 | int cs_db, cs_l; | |
4347 | ||
4348 | cache_all_regs(vcpu); | |
4349 | ||
4350 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4351 | ||
4352 | vcpu->arch.emulate_ctxt.vcpu = vcpu; | |
f6e78475 | 4353 | vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu); |
8ec4722d MG |
4354 | vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); |
4355 | vcpu->arch.emulate_ctxt.mode = | |
4356 | (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4357 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
4358 | ? X86EMUL_MODE_VM86 : cs_l | |
4359 | ? X86EMUL_MODE_PROT64 : cs_db | |
4360 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
4361 | memset(c, 0, sizeof(struct decode_cache)); | |
4362 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4363 | } | |
4364 | ||
63995653 MG |
4365 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq) |
4366 | { | |
4367 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; | |
4368 | int ret; | |
4369 | ||
4370 | init_emulate_ctxt(vcpu); | |
4371 | ||
4372 | vcpu->arch.emulate_ctxt.decode.op_bytes = 2; | |
4373 | vcpu->arch.emulate_ctxt.decode.ad_bytes = 2; | |
4374 | vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip; | |
4375 | ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq); | |
4376 | ||
4377 | if (ret != X86EMUL_CONTINUE) | |
4378 | return EMULATE_FAIL; | |
4379 | ||
4380 | vcpu->arch.emulate_ctxt.eip = c->eip; | |
4381 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); | |
4382 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); | |
f6e78475 | 4383 | kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
63995653 MG |
4384 | |
4385 | if (irq == NMI_VECTOR) | |
4386 | vcpu->arch.nmi_pending = false; | |
4387 | else | |
4388 | vcpu->arch.interrupt.pending = false; | |
4389 | ||
4390 | return EMULATE_DONE; | |
4391 | } | |
4392 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
4393 | ||
6d77dbfc GN |
4394 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
4395 | { | |
fc3a9157 JR |
4396 | int r = EMULATE_DONE; |
4397 | ||
6d77dbfc GN |
4398 | ++vcpu->stat.insn_emulation_fail; |
4399 | trace_kvm_emulate_insn_failed(vcpu); | |
fc3a9157 JR |
4400 | if (!is_guest_mode(vcpu)) { |
4401 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4402 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4403 | vcpu->run->internal.ndata = 0; | |
4404 | r = EMULATE_FAIL; | |
4405 | } | |
6d77dbfc | 4406 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
4407 | |
4408 | return r; | |
6d77dbfc GN |
4409 | } |
4410 | ||
a6f177ef GN |
4411 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva) |
4412 | { | |
4413 | gpa_t gpa; | |
4414 | ||
68be0803 GN |
4415 | if (tdp_enabled) |
4416 | return false; | |
4417 | ||
a6f177ef GN |
4418 | /* |
4419 | * if emulation was due to access to shadowed page table | |
4420 | * and it failed try to unshadow page and re-entetr the | |
4421 | * guest to let CPU execute the instruction. | |
4422 | */ | |
4423 | if (kvm_mmu_unprotect_page_virt(vcpu, gva)) | |
4424 | return true; | |
4425 | ||
4426 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL); | |
4427 | ||
4428 | if (gpa == UNMAPPED_GVA) | |
4429 | return true; /* let cpu generate fault */ | |
4430 | ||
4431 | if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT))) | |
4432 | return true; | |
4433 | ||
4434 | return false; | |
4435 | } | |
4436 | ||
51d8b661 AP |
4437 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
4438 | unsigned long cr2, | |
dc25e89e AP |
4439 | int emulation_type, |
4440 | void *insn, | |
4441 | int insn_len) | |
bbd9b64e | 4442 | { |
95cb2295 | 4443 | int r; |
4d2179e1 | 4444 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
bbd9b64e | 4445 | |
26eef70c | 4446 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 4447 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 4448 | /* |
56e82318 | 4449 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
4450 | * instead of direct ->regs accesses, can save hundred cycles |
4451 | * on Intel for instructions that don't read/change RSP, for | |
4452 | * for example. | |
4453 | */ | |
4454 | cache_all_regs(vcpu); | |
bbd9b64e | 4455 | |
571008da | 4456 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 4457 | init_emulate_ctxt(vcpu); |
95cb2295 | 4458 | vcpu->arch.emulate_ctxt.interruptibility = 0; |
da9cb575 | 4459 | vcpu->arch.emulate_ctxt.have_exception = false; |
4fc40f07 | 4460 | vcpu->arch.emulate_ctxt.perm_ok = false; |
bbd9b64e | 4461 | |
4005996e AK |
4462 | vcpu->arch.emulate_ctxt.only_vendor_specific_insn |
4463 | = emulation_type & EMULTYPE_TRAP_UD; | |
4464 | ||
dc25e89e | 4465 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len); |
bbd9b64e | 4466 | |
e46479f8 | 4467 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 4468 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 4469 | if (r) { |
4005996e AK |
4470 | if (emulation_type & EMULTYPE_TRAP_UD) |
4471 | return EMULATE_FAIL; | |
a6f177ef | 4472 | if (reexecute_instruction(vcpu, cr2)) |
bbd9b64e | 4473 | return EMULATE_DONE; |
6d77dbfc GN |
4474 | if (emulation_type & EMULTYPE_SKIP) |
4475 | return EMULATE_FAIL; | |
4476 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4477 | } |
4478 | } | |
4479 | ||
ba8afb6b GN |
4480 | if (emulation_type & EMULTYPE_SKIP) { |
4481 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
4482 | return EMULATE_DONE; | |
4483 | } | |
4484 | ||
4d2179e1 GN |
4485 | /* this is needed for vmware backdor interface to work since it |
4486 | changes registers values during IO operation */ | |
4487 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4488 | ||
5cd21917 | 4489 | restart: |
9aabc88f | 4490 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt); |
bbd9b64e | 4491 | |
d2ddd1c4 | 4492 | if (r == EMULATION_FAILED) { |
a6f177ef | 4493 | if (reexecute_instruction(vcpu, cr2)) |
c3cd7ffa GN |
4494 | return EMULATE_DONE; |
4495 | ||
6d77dbfc | 4496 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4497 | } |
4498 | ||
da9cb575 | 4499 | if (vcpu->arch.emulate_ctxt.have_exception) { |
54b8486f | 4500 | inject_emulated_exception(vcpu); |
d2ddd1c4 GN |
4501 | r = EMULATE_DONE; |
4502 | } else if (vcpu->arch.pio.count) { | |
3457e419 GN |
4503 | if (!vcpu->arch.pio.in) |
4504 | vcpu->arch.pio.count = 0; | |
e85d28f8 | 4505 | r = EMULATE_DO_MMIO; |
cef4dea0 | 4506 | } else if (vcpu->mmio_needed) |
e85d28f8 | 4507 | r = EMULATE_DO_MMIO; |
cef4dea0 | 4508 | else if (r == EMULATION_RESTART) |
5cd21917 | 4509 | goto restart; |
d2ddd1c4 GN |
4510 | else |
4511 | r = EMULATE_DONE; | |
f850e2e6 | 4512 | |
e85d28f8 | 4513 | toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility); |
f6e78475 | 4514 | kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
3842d135 | 4515 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e85d28f8 GN |
4516 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
4517 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); | |
4518 | ||
4519 | return r; | |
de7d789a | 4520 | } |
51d8b661 | 4521 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 4522 | |
cf8f70bf | 4523 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 4524 | { |
cf8f70bf GN |
4525 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4526 | int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu); | |
4527 | /* do not return to emulator after return from userspace */ | |
7972995b | 4528 | vcpu->arch.pio.count = 0; |
de7d789a CO |
4529 | return ret; |
4530 | } | |
cf8f70bf | 4531 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 4532 | |
8cfdc000 ZA |
4533 | static void tsc_bad(void *info) |
4534 | { | |
0a3aee0d | 4535 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
4536 | } |
4537 | ||
4538 | static void tsc_khz_changed(void *data) | |
c8076604 | 4539 | { |
8cfdc000 ZA |
4540 | struct cpufreq_freqs *freq = data; |
4541 | unsigned long khz = 0; | |
4542 | ||
4543 | if (data) | |
4544 | khz = freq->new; | |
4545 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
4546 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
4547 | if (!khz) | |
4548 | khz = tsc_khz; | |
0a3aee0d | 4549 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
4550 | } |
4551 | ||
c8076604 GH |
4552 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
4553 | void *data) | |
4554 | { | |
4555 | struct cpufreq_freqs *freq = data; | |
4556 | struct kvm *kvm; | |
4557 | struct kvm_vcpu *vcpu; | |
4558 | int i, send_ipi = 0; | |
4559 | ||
8cfdc000 ZA |
4560 | /* |
4561 | * We allow guests to temporarily run on slowing clocks, | |
4562 | * provided we notify them after, or to run on accelerating | |
4563 | * clocks, provided we notify them before. Thus time never | |
4564 | * goes backwards. | |
4565 | * | |
4566 | * However, we have a problem. We can't atomically update | |
4567 | * the frequency of a given CPU from this function; it is | |
4568 | * merely a notifier, which can be called from any CPU. | |
4569 | * Changing the TSC frequency at arbitrary points in time | |
4570 | * requires a recomputation of local variables related to | |
4571 | * the TSC for each VCPU. We must flag these local variables | |
4572 | * to be updated and be sure the update takes place with the | |
4573 | * new frequency before any guests proceed. | |
4574 | * | |
4575 | * Unfortunately, the combination of hotplug CPU and frequency | |
4576 | * change creates an intractable locking scenario; the order | |
4577 | * of when these callouts happen is undefined with respect to | |
4578 | * CPU hotplug, and they can race with each other. As such, | |
4579 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
4580 | * undefined; you can actually have a CPU frequency change take | |
4581 | * place in between the computation of X and the setting of the | |
4582 | * variable. To protect against this problem, all updates of | |
4583 | * the per_cpu tsc_khz variable are done in an interrupt | |
4584 | * protected IPI, and all callers wishing to update the value | |
4585 | * must wait for a synchronous IPI to complete (which is trivial | |
4586 | * if the caller is on the CPU already). This establishes the | |
4587 | * necessary total order on variable updates. | |
4588 | * | |
4589 | * Note that because a guest time update may take place | |
4590 | * anytime after the setting of the VCPU's request bit, the | |
4591 | * correct TSC value must be set before the request. However, | |
4592 | * to ensure the update actually makes it to any guest which | |
4593 | * starts running in hardware virtualization between the set | |
4594 | * and the acquisition of the spinlock, we must also ping the | |
4595 | * CPU after setting the request bit. | |
4596 | * | |
4597 | */ | |
4598 | ||
c8076604 GH |
4599 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
4600 | return 0; | |
4601 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
4602 | return 0; | |
8cfdc000 ZA |
4603 | |
4604 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 4605 | |
e935b837 | 4606 | raw_spin_lock(&kvm_lock); |
c8076604 | 4607 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 4608 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
4609 | if (vcpu->cpu != freq->cpu) |
4610 | continue; | |
c285545f | 4611 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 4612 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 4613 | send_ipi = 1; |
c8076604 GH |
4614 | } |
4615 | } | |
e935b837 | 4616 | raw_spin_unlock(&kvm_lock); |
c8076604 GH |
4617 | |
4618 | if (freq->old < freq->new && send_ipi) { | |
4619 | /* | |
4620 | * We upscale the frequency. Must make the guest | |
4621 | * doesn't see old kvmclock values while running with | |
4622 | * the new frequency, otherwise we risk the guest sees | |
4623 | * time go backwards. | |
4624 | * | |
4625 | * In case we update the frequency for another cpu | |
4626 | * (which might be in guest context) send an interrupt | |
4627 | * to kick the cpu out of guest context. Next time | |
4628 | * guest context is entered kvmclock will be updated, | |
4629 | * so the guest will not see stale values. | |
4630 | */ | |
8cfdc000 | 4631 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
4632 | } |
4633 | return 0; | |
4634 | } | |
4635 | ||
4636 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
4637 | .notifier_call = kvmclock_cpufreq_notifier |
4638 | }; | |
4639 | ||
4640 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
4641 | unsigned long action, void *hcpu) | |
4642 | { | |
4643 | unsigned int cpu = (unsigned long)hcpu; | |
4644 | ||
4645 | switch (action) { | |
4646 | case CPU_ONLINE: | |
4647 | case CPU_DOWN_FAILED: | |
4648 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
4649 | break; | |
4650 | case CPU_DOWN_PREPARE: | |
4651 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
4652 | break; | |
4653 | } | |
4654 | return NOTIFY_OK; | |
4655 | } | |
4656 | ||
4657 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
4658 | .notifier_call = kvmclock_cpu_notifier, | |
4659 | .priority = -INT_MAX | |
c8076604 GH |
4660 | }; |
4661 | ||
b820cc0c ZA |
4662 | static void kvm_timer_init(void) |
4663 | { | |
4664 | int cpu; | |
4665 | ||
c285545f | 4666 | max_tsc_khz = tsc_khz; |
8cfdc000 | 4667 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
b820cc0c | 4668 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
4669 | #ifdef CONFIG_CPU_FREQ |
4670 | struct cpufreq_policy policy; | |
4671 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
4672 | cpu = get_cpu(); |
4673 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
4674 | if (policy.cpuinfo.max_freq) |
4675 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 4676 | put_cpu(); |
c285545f | 4677 | #endif |
b820cc0c ZA |
4678 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
4679 | CPUFREQ_TRANSITION_NOTIFIER); | |
4680 | } | |
c285545f | 4681 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
4682 | for_each_online_cpu(cpu) |
4683 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
b820cc0c ZA |
4684 | } |
4685 | ||
ff9d07a0 ZY |
4686 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
4687 | ||
4688 | static int kvm_is_in_guest(void) | |
4689 | { | |
4690 | return percpu_read(current_vcpu) != NULL; | |
4691 | } | |
4692 | ||
4693 | static int kvm_is_user_mode(void) | |
4694 | { | |
4695 | int user_mode = 3; | |
dcf46b94 | 4696 | |
ff9d07a0 ZY |
4697 | if (percpu_read(current_vcpu)) |
4698 | user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu)); | |
dcf46b94 | 4699 | |
ff9d07a0 ZY |
4700 | return user_mode != 0; |
4701 | } | |
4702 | ||
4703 | static unsigned long kvm_get_guest_ip(void) | |
4704 | { | |
4705 | unsigned long ip = 0; | |
dcf46b94 | 4706 | |
ff9d07a0 ZY |
4707 | if (percpu_read(current_vcpu)) |
4708 | ip = kvm_rip_read(percpu_read(current_vcpu)); | |
dcf46b94 | 4709 | |
ff9d07a0 ZY |
4710 | return ip; |
4711 | } | |
4712 | ||
4713 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
4714 | .is_in_guest = kvm_is_in_guest, | |
4715 | .is_user_mode = kvm_is_user_mode, | |
4716 | .get_guest_ip = kvm_get_guest_ip, | |
4717 | }; | |
4718 | ||
4719 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
4720 | { | |
4721 | percpu_write(current_vcpu, vcpu); | |
4722 | } | |
4723 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
4724 | ||
4725 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
4726 | { | |
4727 | percpu_write(current_vcpu, NULL); | |
4728 | } | |
4729 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
4730 | ||
f8c16bba | 4731 | int kvm_arch_init(void *opaque) |
043405e1 | 4732 | { |
b820cc0c | 4733 | int r; |
f8c16bba ZX |
4734 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
4735 | ||
f8c16bba ZX |
4736 | if (kvm_x86_ops) { |
4737 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
4738 | r = -EEXIST; |
4739 | goto out; | |
f8c16bba ZX |
4740 | } |
4741 | ||
4742 | if (!ops->cpu_has_kvm_support()) { | |
4743 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
4744 | r = -EOPNOTSUPP; |
4745 | goto out; | |
f8c16bba ZX |
4746 | } |
4747 | if (ops->disabled_by_bios()) { | |
4748 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
4749 | r = -EOPNOTSUPP; |
4750 | goto out; | |
f8c16bba ZX |
4751 | } |
4752 | ||
97db56ce AK |
4753 | r = kvm_mmu_module_init(); |
4754 | if (r) | |
4755 | goto out; | |
4756 | ||
4757 | kvm_init_msr_list(); | |
4758 | ||
f8c16bba | 4759 | kvm_x86_ops = ops; |
56c6d28a | 4760 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e | 4761 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 4762 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 4763 | |
b820cc0c | 4764 | kvm_timer_init(); |
c8076604 | 4765 | |
ff9d07a0 ZY |
4766 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
4767 | ||
2acf923e DC |
4768 | if (cpu_has_xsave) |
4769 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
4770 | ||
f8c16bba | 4771 | return 0; |
56c6d28a ZX |
4772 | |
4773 | out: | |
56c6d28a | 4774 | return r; |
043405e1 | 4775 | } |
8776e519 | 4776 | |
f8c16bba ZX |
4777 | void kvm_arch_exit(void) |
4778 | { | |
ff9d07a0 ZY |
4779 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
4780 | ||
888d256e JK |
4781 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
4782 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
4783 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 4784 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
f8c16bba | 4785 | kvm_x86_ops = NULL; |
56c6d28a ZX |
4786 | kvm_mmu_module_exit(); |
4787 | } | |
f8c16bba | 4788 | |
8776e519 HB |
4789 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
4790 | { | |
4791 | ++vcpu->stat.halt_exits; | |
4792 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 4793 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
4794 | return 1; |
4795 | } else { | |
4796 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
4797 | return 0; | |
4798 | } | |
4799 | } | |
4800 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
4801 | ||
2f333bcb MT |
4802 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
4803 | unsigned long a1) | |
4804 | { | |
4805 | if (is_long_mode(vcpu)) | |
4806 | return a0; | |
4807 | else | |
4808 | return a0 | ((gpa_t)a1 << 32); | |
4809 | } | |
4810 | ||
55cd8e5a GN |
4811 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
4812 | { | |
4813 | u64 param, ingpa, outgpa, ret; | |
4814 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
4815 | bool fast, longmode; | |
4816 | int cs_db, cs_l; | |
4817 | ||
4818 | /* | |
4819 | * hypercall generates UD from non zero cpl and real mode | |
4820 | * per HYPER-V spec | |
4821 | */ | |
3eeb3288 | 4822 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
4823 | kvm_queue_exception(vcpu, UD_VECTOR); |
4824 | return 0; | |
4825 | } | |
4826 | ||
4827 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4828 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
4829 | ||
4830 | if (!longmode) { | |
ccd46936 GN |
4831 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
4832 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
4833 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
4834 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
4835 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
4836 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
4837 | } |
4838 | #ifdef CONFIG_X86_64 | |
4839 | else { | |
4840 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4841 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4842 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
4843 | } | |
4844 | #endif | |
4845 | ||
4846 | code = param & 0xffff; | |
4847 | fast = (param >> 16) & 0x1; | |
4848 | rep_cnt = (param >> 32) & 0xfff; | |
4849 | rep_idx = (param >> 48) & 0xfff; | |
4850 | ||
4851 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
4852 | ||
c25bc163 GN |
4853 | switch (code) { |
4854 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
4855 | kvm_vcpu_on_spin(vcpu); | |
4856 | break; | |
4857 | default: | |
4858 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
4859 | break; | |
4860 | } | |
55cd8e5a GN |
4861 | |
4862 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
4863 | if (longmode) { | |
4864 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
4865 | } else { | |
4866 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
4867 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
4868 | } | |
4869 | ||
4870 | return 1; | |
4871 | } | |
4872 | ||
8776e519 HB |
4873 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
4874 | { | |
4875 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 4876 | int r = 1; |
8776e519 | 4877 | |
55cd8e5a GN |
4878 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
4879 | return kvm_hv_hypercall(vcpu); | |
4880 | ||
5fdbf976 MT |
4881 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4882 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4883 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4884 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4885 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 4886 | |
229456fc | 4887 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 4888 | |
8776e519 HB |
4889 | if (!is_long_mode(vcpu)) { |
4890 | nr &= 0xFFFFFFFF; | |
4891 | a0 &= 0xFFFFFFFF; | |
4892 | a1 &= 0xFFFFFFFF; | |
4893 | a2 &= 0xFFFFFFFF; | |
4894 | a3 &= 0xFFFFFFFF; | |
4895 | } | |
4896 | ||
07708c4a JK |
4897 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
4898 | ret = -KVM_EPERM; | |
4899 | goto out; | |
4900 | } | |
4901 | ||
8776e519 | 4902 | switch (nr) { |
b93463aa AK |
4903 | case KVM_HC_VAPIC_POLL_IRQ: |
4904 | ret = 0; | |
4905 | break; | |
2f333bcb MT |
4906 | case KVM_HC_MMU_OP: |
4907 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
4908 | break; | |
8776e519 HB |
4909 | default: |
4910 | ret = -KVM_ENOSYS; | |
4911 | break; | |
4912 | } | |
07708c4a | 4913 | out: |
5fdbf976 | 4914 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 4915 | ++vcpu->stat.hypercalls; |
2f333bcb | 4916 | return r; |
8776e519 HB |
4917 | } |
4918 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
4919 | ||
4920 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
4921 | { | |
4922 | char instruction[3]; | |
5fdbf976 | 4923 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 4924 | |
8776e519 HB |
4925 | /* |
4926 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
4927 | * to ensure that the updated hypercall appears atomically across all | |
4928 | * VCPUs. | |
4929 | */ | |
4930 | kvm_mmu_zap_all(vcpu->kvm); | |
4931 | ||
8776e519 | 4932 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 4933 | |
8fe681e9 | 4934 | return emulator_write_emulated(rip, instruction, 3, NULL, vcpu); |
8776e519 HB |
4935 | } |
4936 | ||
8776e519 HB |
4937 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) |
4938 | { | |
89a27f4d | 4939 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4940 | |
4941 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4942 | } | |
4943 | ||
4944 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
4945 | { | |
89a27f4d | 4946 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4947 | |
4948 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4949 | } | |
4950 | ||
07716717 DK |
4951 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
4952 | { | |
ad312c7c ZX |
4953 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
4954 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
4955 | |
4956 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4957 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 4958 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 4959 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
4960 | if (ej->function == e->function) { |
4961 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4962 | return j; | |
4963 | } | |
4964 | } | |
4965 | return 0; /* silence gcc, even though control never reaches here */ | |
4966 | } | |
4967 | ||
4968 | /* find an entry with matching function, matching index (if needed), and that | |
4969 | * should be read next (if it's stateful) */ | |
4970 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
4971 | u32 function, u32 index) | |
4972 | { | |
4973 | if (e->function != function) | |
4974 | return 0; | |
4975 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
4976 | return 0; | |
4977 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 4978 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
4979 | return 0; |
4980 | return 1; | |
4981 | } | |
4982 | ||
d8017474 AG |
4983 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
4984 | u32 function, u32 index) | |
8776e519 HB |
4985 | { |
4986 | int i; | |
d8017474 | 4987 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 4988 | |
ad312c7c | 4989 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
4990 | struct kvm_cpuid_entry2 *e; |
4991 | ||
ad312c7c | 4992 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
4993 | if (is_matching_cpuid_entry(e, function, index)) { |
4994 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
4995 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
4996 | best = e; |
4997 | break; | |
4998 | } | |
8776e519 | 4999 | } |
d8017474 AG |
5000 | return best; |
5001 | } | |
0e851880 | 5002 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
d8017474 | 5003 | |
82725b20 DE |
5004 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
5005 | { | |
5006 | struct kvm_cpuid_entry2 *best; | |
5007 | ||
f7a71197 AK |
5008 | best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); |
5009 | if (!best || best->eax < 0x80000008) | |
5010 | goto not_found; | |
82725b20 DE |
5011 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); |
5012 | if (best) | |
5013 | return best->eax & 0xff; | |
f7a71197 | 5014 | not_found: |
82725b20 DE |
5015 | return 36; |
5016 | } | |
5017 | ||
bd22f5cf AP |
5018 | /* |
5019 | * If no match is found, check whether we exceed the vCPU's limit | |
5020 | * and return the content of the highest valid _standard_ leaf instead. | |
5021 | * This is to satisfy the CPUID specification. | |
5022 | */ | |
5023 | static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu, | |
5024 | u32 function, u32 index) | |
5025 | { | |
5026 | struct kvm_cpuid_entry2 *maxlevel; | |
5027 | ||
5028 | maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); | |
5029 | if (!maxlevel || maxlevel->eax >= function) | |
5030 | return NULL; | |
5031 | if (function & 0x80000000) { | |
5032 | maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0); | |
5033 | if (!maxlevel) | |
5034 | return NULL; | |
5035 | } | |
5036 | return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index); | |
5037 | } | |
5038 | ||
d8017474 AG |
5039 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
5040 | { | |
5041 | u32 function, index; | |
5042 | struct kvm_cpuid_entry2 *best; | |
5043 | ||
5044 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
5045 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5046 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
5047 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
5048 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
5049 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
5050 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
bd22f5cf AP |
5051 | |
5052 | if (!best) | |
5053 | best = check_cpuid_limit(vcpu, function, index); | |
5054 | ||
8776e519 | 5055 | if (best) { |
5fdbf976 MT |
5056 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
5057 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
5058 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
5059 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 5060 | } |
8776e519 | 5061 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
5062 | trace_kvm_cpuid(function, |
5063 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
5064 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
5065 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
5066 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
5067 | } |
5068 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 5069 | |
b6c7a5dc HB |
5070 | /* |
5071 | * Check if userspace requested an interrupt window, and that the | |
5072 | * interrupt window is open. | |
5073 | * | |
5074 | * No need to exit to userspace if we already have an interrupt queued. | |
5075 | */ | |
851ba692 | 5076 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5077 | { |
8061823a | 5078 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 5079 | vcpu->run->request_interrupt_window && |
5df56646 | 5080 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
5081 | } |
5082 | ||
851ba692 | 5083 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5084 | { |
851ba692 AK |
5085 | struct kvm_run *kvm_run = vcpu->run; |
5086 | ||
91586a3b | 5087 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 5088 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5089 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 5090 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 5091 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 5092 | else |
b6c7a5dc | 5093 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
5094 | kvm_arch_interrupt_allowed(vcpu) && |
5095 | !kvm_cpu_has_interrupt(vcpu) && | |
5096 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
5097 | } |
5098 | ||
b93463aa AK |
5099 | static void vapic_enter(struct kvm_vcpu *vcpu) |
5100 | { | |
5101 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5102 | struct page *page; | |
5103 | ||
5104 | if (!apic || !apic->vapic_addr) | |
5105 | return; | |
5106 | ||
5107 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
5108 | |
5109 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
5110 | } |
5111 | ||
5112 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
5113 | { | |
5114 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 5115 | int idx; |
b93463aa AK |
5116 | |
5117 | if (!apic || !apic->vapic_addr) | |
5118 | return; | |
5119 | ||
f656ce01 | 5120 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
5121 | kvm_release_page_dirty(apic->vapic_page); |
5122 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 5123 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5124 | } |
5125 | ||
95ba8273 GN |
5126 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5127 | { | |
5128 | int max_irr, tpr; | |
5129 | ||
5130 | if (!kvm_x86_ops->update_cr8_intercept) | |
5131 | return; | |
5132 | ||
88c808fd AK |
5133 | if (!vcpu->arch.apic) |
5134 | return; | |
5135 | ||
8db3baa2 GN |
5136 | if (!vcpu->arch.apic->vapic_addr) |
5137 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5138 | else | |
5139 | max_irr = -1; | |
95ba8273 GN |
5140 | |
5141 | if (max_irr != -1) | |
5142 | max_irr >>= 4; | |
5143 | ||
5144 | tpr = kvm_lapic_get_cr8(vcpu); | |
5145 | ||
5146 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5147 | } | |
5148 | ||
851ba692 | 5149 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
5150 | { |
5151 | /* try to reinject previous events if any */ | |
b59bb7bd | 5152 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
5153 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
5154 | vcpu->arch.exception.has_error_code, | |
5155 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
5156 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
5157 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
5158 | vcpu->arch.exception.error_code, |
5159 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
5160 | return; |
5161 | } | |
5162 | ||
95ba8273 GN |
5163 | if (vcpu->arch.nmi_injected) { |
5164 | kvm_x86_ops->set_nmi(vcpu); | |
5165 | return; | |
5166 | } | |
5167 | ||
5168 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 5169 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
5170 | return; |
5171 | } | |
5172 | ||
5173 | /* try to inject new event if pending */ | |
5174 | if (vcpu->arch.nmi_pending) { | |
5175 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
5176 | vcpu->arch.nmi_pending = false; | |
5177 | vcpu->arch.nmi_injected = true; | |
5178 | kvm_x86_ops->set_nmi(vcpu); | |
5179 | } | |
5180 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
5181 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
5182 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
5183 | false); | |
5184 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
5185 | } |
5186 | } | |
5187 | } | |
5188 | ||
2acf923e DC |
5189 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
5190 | { | |
5191 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
5192 | !vcpu->guest_xcr0_loaded) { | |
5193 | /* kvm_set_xcr() also depends on this */ | |
5194 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
5195 | vcpu->guest_xcr0_loaded = 1; | |
5196 | } | |
5197 | } | |
5198 | ||
5199 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
5200 | { | |
5201 | if (vcpu->guest_xcr0_loaded) { | |
5202 | if (vcpu->arch.xcr0 != host_xcr0) | |
5203 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
5204 | vcpu->guest_xcr0_loaded = 0; | |
5205 | } | |
5206 | } | |
5207 | ||
851ba692 | 5208 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
5209 | { |
5210 | int r; | |
1499e54a | 5211 | bool nmi_pending; |
6a8b1d13 | 5212 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 5213 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 5214 | |
3e007509 | 5215 | if (vcpu->requests) { |
a8eeb04a | 5216 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 5217 | kvm_mmu_unload(vcpu); |
a8eeb04a | 5218 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 5219 | __kvm_migrate_timers(vcpu); |
34c238a1 ZA |
5220 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
5221 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
5222 | if (unlikely(r)) |
5223 | goto out; | |
5224 | } | |
a8eeb04a | 5225 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 5226 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 5227 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 5228 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 5229 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 5230 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
5231 | r = 0; |
5232 | goto out; | |
5233 | } | |
a8eeb04a | 5234 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 5235 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
5236 | r = 0; |
5237 | goto out; | |
5238 | } | |
a8eeb04a | 5239 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
5240 | vcpu->fpu_active = 0; |
5241 | kvm_x86_ops->fpu_deactivate(vcpu); | |
5242 | } | |
af585b92 GN |
5243 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
5244 | /* Page is swapped out. Do synthetic halt */ | |
5245 | vcpu->arch.apf.halted = true; | |
5246 | r = 1; | |
5247 | goto out; | |
5248 | } | |
2f52d58c | 5249 | } |
b93463aa | 5250 | |
3e007509 AK |
5251 | r = kvm_mmu_reload(vcpu); |
5252 | if (unlikely(r)) | |
5253 | goto out; | |
5254 | ||
1499e54a GN |
5255 | /* |
5256 | * An NMI can be injected between local nmi_pending read and | |
5257 | * vcpu->arch.nmi_pending read inside inject_pending_event(). | |
5258 | * But in that case, KVM_REQ_EVENT will be set, which makes | |
5259 | * the race described above benign. | |
5260 | */ | |
5261 | nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending); | |
5262 | ||
b463a6f7 AK |
5263 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
5264 | inject_pending_event(vcpu); | |
5265 | ||
5266 | /* enable NMI/IRQ window open exits if needed */ | |
1499e54a | 5267 | if (nmi_pending) |
b463a6f7 AK |
5268 | kvm_x86_ops->enable_nmi_window(vcpu); |
5269 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
5270 | kvm_x86_ops->enable_irq_window(vcpu); | |
5271 | ||
5272 | if (kvm_lapic_enabled(vcpu)) { | |
5273 | update_cr8_intercept(vcpu); | |
5274 | kvm_lapic_sync_to_vapic(vcpu); | |
5275 | } | |
5276 | } | |
5277 | ||
b6c7a5dc HB |
5278 | preempt_disable(); |
5279 | ||
5280 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
5281 | if (vcpu->fpu_active) |
5282 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 5283 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 5284 | |
6b7e2d09 XG |
5285 | vcpu->mode = IN_GUEST_MODE; |
5286 | ||
5287 | /* We should set ->mode before check ->requests, | |
5288 | * see the comment in make_all_cpus_request. | |
5289 | */ | |
5290 | smp_mb(); | |
b6c7a5dc | 5291 | |
d94e1dc9 | 5292 | local_irq_disable(); |
32f88400 | 5293 | |
6b7e2d09 | 5294 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 5295 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 5296 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5297 | smp_wmb(); |
6c142801 AK |
5298 | local_irq_enable(); |
5299 | preempt_enable(); | |
b463a6f7 | 5300 | kvm_x86_ops->cancel_injection(vcpu); |
6c142801 AK |
5301 | r = 1; |
5302 | goto out; | |
5303 | } | |
5304 | ||
f656ce01 | 5305 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 5306 | |
b6c7a5dc HB |
5307 | kvm_guest_enter(); |
5308 | ||
42dbaa5a | 5309 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
5310 | set_debugreg(0, 7); |
5311 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5312 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5313 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5314 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
5315 | } | |
b6c7a5dc | 5316 | |
229456fc | 5317 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 5318 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 5319 | |
24f1e32c FW |
5320 | /* |
5321 | * If the guest has used debug registers, at least dr7 | |
5322 | * will be disabled while returning to the host. | |
5323 | * If we don't have active breakpoints in the host, we don't | |
5324 | * care about the messed up debug address registers. But if | |
5325 | * we have some of them active, restore the old state. | |
5326 | */ | |
59d8eb53 | 5327 | if (hw_breakpoint_active()) |
24f1e32c | 5328 | hw_breakpoint_restore(); |
42dbaa5a | 5329 | |
1d5f066e ZA |
5330 | kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc); |
5331 | ||
6b7e2d09 | 5332 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5333 | smp_wmb(); |
b6c7a5dc HB |
5334 | local_irq_enable(); |
5335 | ||
5336 | ++vcpu->stat.exits; | |
5337 | ||
5338 | /* | |
5339 | * We must have an instruction between local_irq_enable() and | |
5340 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
5341 | * the interrupt shadow. The stat.exits increment will do nicely. | |
5342 | * But we need to prevent reordering, hence this barrier(): | |
5343 | */ | |
5344 | barrier(); | |
5345 | ||
5346 | kvm_guest_exit(); | |
5347 | ||
5348 | preempt_enable(); | |
5349 | ||
f656ce01 | 5350 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 5351 | |
b6c7a5dc HB |
5352 | /* |
5353 | * Profile KVM exit RIPs: | |
5354 | */ | |
5355 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
5356 | unsigned long rip = kvm_rip_read(vcpu); |
5357 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
5358 | } |
5359 | ||
298101da | 5360 | |
b93463aa AK |
5361 | kvm_lapic_sync_from_vapic(vcpu); |
5362 | ||
851ba692 | 5363 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
5364 | out: |
5365 | return r; | |
5366 | } | |
b6c7a5dc | 5367 | |
09cec754 | 5368 | |
851ba692 | 5369 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
5370 | { |
5371 | int r; | |
f656ce01 | 5372 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
5373 | |
5374 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
5375 | pr_debug("vcpu %d received sipi with vector # %x\n", |
5376 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 5377 | kvm_lapic_reset(vcpu); |
5f179287 | 5378 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
5379 | if (r) |
5380 | return r; | |
5381 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
5382 | } |
5383 | ||
f656ce01 | 5384 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
5385 | vapic_enter(vcpu); |
5386 | ||
5387 | r = 1; | |
5388 | while (r > 0) { | |
af585b92 GN |
5389 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
5390 | !vcpu->arch.apf.halted) | |
851ba692 | 5391 | r = vcpu_enter_guest(vcpu); |
d7690175 | 5392 | else { |
f656ce01 | 5393 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 5394 | kvm_vcpu_block(vcpu); |
f656ce01 | 5395 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
a8eeb04a | 5396 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
09cec754 GN |
5397 | { |
5398 | switch(vcpu->arch.mp_state) { | |
5399 | case KVM_MP_STATE_HALTED: | |
d7690175 | 5400 | vcpu->arch.mp_state = |
09cec754 GN |
5401 | KVM_MP_STATE_RUNNABLE; |
5402 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 5403 | vcpu->arch.apf.halted = false; |
09cec754 GN |
5404 | break; |
5405 | case KVM_MP_STATE_SIPI_RECEIVED: | |
5406 | default: | |
5407 | r = -EINTR; | |
5408 | break; | |
5409 | } | |
5410 | } | |
d7690175 MT |
5411 | } |
5412 | ||
09cec754 GN |
5413 | if (r <= 0) |
5414 | break; | |
5415 | ||
5416 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
5417 | if (kvm_cpu_has_pending_timer(vcpu)) | |
5418 | kvm_inject_pending_timer_irqs(vcpu); | |
5419 | ||
851ba692 | 5420 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 5421 | r = -EINTR; |
851ba692 | 5422 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5423 | ++vcpu->stat.request_irq_exits; |
5424 | } | |
af585b92 GN |
5425 | |
5426 | kvm_check_async_pf_completion(vcpu); | |
5427 | ||
09cec754 GN |
5428 | if (signal_pending(current)) { |
5429 | r = -EINTR; | |
851ba692 | 5430 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5431 | ++vcpu->stat.signal_exits; |
5432 | } | |
5433 | if (need_resched()) { | |
f656ce01 | 5434 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 5435 | kvm_resched(vcpu); |
f656ce01 | 5436 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 5437 | } |
b6c7a5dc HB |
5438 | } |
5439 | ||
f656ce01 | 5440 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 5441 | |
b93463aa AK |
5442 | vapic_exit(vcpu); |
5443 | ||
b6c7a5dc HB |
5444 | return r; |
5445 | } | |
5446 | ||
5287f194 AK |
5447 | static int complete_mmio(struct kvm_vcpu *vcpu) |
5448 | { | |
5449 | struct kvm_run *run = vcpu->run; | |
5450 | int r; | |
5451 | ||
5452 | if (!(vcpu->arch.pio.count || vcpu->mmio_needed)) | |
5453 | return 1; | |
5454 | ||
5455 | if (vcpu->mmio_needed) { | |
5287f194 | 5456 | vcpu->mmio_needed = 0; |
cef4dea0 AK |
5457 | if (!vcpu->mmio_is_write) |
5458 | memcpy(vcpu->mmio_data, run->mmio.data, 8); | |
5459 | vcpu->mmio_index += 8; | |
5460 | if (vcpu->mmio_index < vcpu->mmio_size) { | |
5461 | run->exit_reason = KVM_EXIT_MMIO; | |
5462 | run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index; | |
5463 | memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8); | |
5464 | run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8); | |
5465 | run->mmio.is_write = vcpu->mmio_is_write; | |
5466 | vcpu->mmio_needed = 1; | |
5467 | return 0; | |
5468 | } | |
5469 | if (vcpu->mmio_is_write) | |
5470 | return 1; | |
5471 | vcpu->mmio_read_completed = 1; | |
5287f194 AK |
5472 | } |
5473 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
5474 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
5475 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
5476 | if (r != EMULATE_DONE) | |
5477 | return 0; | |
5478 | return 1; | |
5479 | } | |
5480 | ||
b6c7a5dc HB |
5481 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
5482 | { | |
5483 | int r; | |
5484 | sigset_t sigsaved; | |
5485 | ||
e5c30142 AK |
5486 | if (!tsk_used_math(current) && init_fpu(current)) |
5487 | return -ENOMEM; | |
5488 | ||
ac9f6dc0 AK |
5489 | if (vcpu->sigset_active) |
5490 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
5491 | ||
a4535290 | 5492 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 5493 | kvm_vcpu_block(vcpu); |
d7690175 | 5494 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
5495 | r = -EAGAIN; |
5496 | goto out; | |
b6c7a5dc HB |
5497 | } |
5498 | ||
b6c7a5dc | 5499 | /* re-sync apic's tpr */ |
eea1cff9 AP |
5500 | if (!irqchip_in_kernel(vcpu->kvm)) { |
5501 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
5502 | r = -EINVAL; | |
5503 | goto out; | |
5504 | } | |
5505 | } | |
b6c7a5dc | 5506 | |
5287f194 AK |
5507 | r = complete_mmio(vcpu); |
5508 | if (r <= 0) | |
5509 | goto out; | |
5510 | ||
5fdbf976 MT |
5511 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
5512 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
5513 | kvm_run->hypercall.ret); | |
b6c7a5dc | 5514 | |
851ba692 | 5515 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
5516 | |
5517 | out: | |
f1d86e46 | 5518 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
5519 | if (vcpu->sigset_active) |
5520 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
5521 | ||
b6c7a5dc HB |
5522 | return r; |
5523 | } | |
5524 | ||
5525 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5526 | { | |
5fdbf976 MT |
5527 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5528 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5529 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5530 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5531 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5532 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
5533 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
5534 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 5535 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5536 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
5537 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
5538 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
5539 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
5540 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
5541 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
5542 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
5543 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
5544 | #endif |
5545 | ||
5fdbf976 | 5546 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 5547 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 5548 | |
b6c7a5dc HB |
5549 | return 0; |
5550 | } | |
5551 | ||
5552 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5553 | { | |
5fdbf976 MT |
5554 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
5555 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
5556 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
5557 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
5558 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
5559 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
5560 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
5561 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 5562 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5563 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
5564 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
5565 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
5566 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
5567 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
5568 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
5569 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
5570 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
5571 | #endif |
5572 | ||
5fdbf976 | 5573 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 5574 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 5575 | |
b4f14abd JK |
5576 | vcpu->arch.exception.pending = false; |
5577 | ||
3842d135 AK |
5578 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5579 | ||
b6c7a5dc HB |
5580 | return 0; |
5581 | } | |
5582 | ||
b6c7a5dc HB |
5583 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
5584 | { | |
5585 | struct kvm_segment cs; | |
5586 | ||
3e6e0aab | 5587 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
5588 | *db = cs.db; |
5589 | *l = cs.l; | |
5590 | } | |
5591 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
5592 | ||
5593 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
5594 | struct kvm_sregs *sregs) | |
5595 | { | |
89a27f4d | 5596 | struct desc_ptr dt; |
b6c7a5dc | 5597 | |
3e6e0aab GT |
5598 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5599 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5600 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5601 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5602 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5603 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5604 | |
3e6e0aab GT |
5605 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5606 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
5607 | |
5608 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
5609 | sregs->idt.limit = dt.size; |
5610 | sregs->idt.base = dt.address; | |
b6c7a5dc | 5611 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
5612 | sregs->gdt.limit = dt.size; |
5613 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 5614 | |
4d4ec087 | 5615 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 5616 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 5617 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 5618 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 5619 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 5620 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
5621 | sregs->apic_base = kvm_get_apic_base(vcpu); |
5622 | ||
923c61bb | 5623 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 5624 | |
36752c9b | 5625 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
5626 | set_bit(vcpu->arch.interrupt.nr, |
5627 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 5628 | |
b6c7a5dc HB |
5629 | return 0; |
5630 | } | |
5631 | ||
62d9f0db MT |
5632 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
5633 | struct kvm_mp_state *mp_state) | |
5634 | { | |
62d9f0db | 5635 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
5636 | return 0; |
5637 | } | |
5638 | ||
5639 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
5640 | struct kvm_mp_state *mp_state) | |
5641 | { | |
62d9f0db | 5642 | vcpu->arch.mp_state = mp_state->mp_state; |
3842d135 | 5643 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
5644 | return 0; |
5645 | } | |
5646 | ||
e269fb21 JK |
5647 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason, |
5648 | bool has_error_code, u32 error_code) | |
b6c7a5dc | 5649 | { |
4d2179e1 | 5650 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
8ec4722d | 5651 | int ret; |
e01c2426 | 5652 | |
8ec4722d | 5653 | init_emulate_ctxt(vcpu); |
c697518a | 5654 | |
9aabc88f | 5655 | ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, |
e269fb21 JK |
5656 | tss_selector, reason, has_error_code, |
5657 | error_code); | |
c697518a | 5658 | |
c697518a | 5659 | if (ret) |
19d04437 | 5660 | return EMULATE_FAIL; |
37817f29 | 5661 | |
4d2179e1 | 5662 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
95c55886 | 5663 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); |
f6e78475 | 5664 | kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
3842d135 | 5665 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 5666 | return EMULATE_DONE; |
37817f29 IE |
5667 | } |
5668 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5669 | ||
b6c7a5dc HB |
5670 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5671 | struct kvm_sregs *sregs) | |
5672 | { | |
5673 | int mmu_reset_needed = 0; | |
63f42e02 | 5674 | int pending_vec, max_bits, idx; |
89a27f4d | 5675 | struct desc_ptr dt; |
b6c7a5dc | 5676 | |
89a27f4d GN |
5677 | dt.size = sregs->idt.limit; |
5678 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5679 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5680 | dt.size = sregs->gdt.limit; |
5681 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5682 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5683 | ||
ad312c7c | 5684 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 5685 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 5686 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 5687 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 5688 | |
2d3ad1f4 | 5689 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5690 | |
f6801dff | 5691 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5692 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5693 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5694 | ||
4d4ec087 | 5695 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5696 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5697 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5698 | |
fc78f519 | 5699 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5700 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c SY |
5701 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
5702 | update_cpuid(vcpu); | |
63f42e02 XG |
5703 | |
5704 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 5705 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 5706 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
5707 | mmu_reset_needed = 1; |
5708 | } | |
63f42e02 | 5709 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
5710 | |
5711 | if (mmu_reset_needed) | |
5712 | kvm_mmu_reset_context(vcpu); | |
5713 | ||
923c61bb GN |
5714 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5715 | pending_vec = find_first_bit( | |
5716 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5717 | if (pending_vec < max_bits) { | |
66fd3f7f | 5718 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 5719 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
5720 | } |
5721 | ||
3e6e0aab GT |
5722 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5723 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5724 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5725 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5726 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5727 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5728 | |
3e6e0aab GT |
5729 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5730 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5731 | |
5f0269f5 ME |
5732 | update_cr8_intercept(vcpu); |
5733 | ||
9c3e4aab | 5734 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5735 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5736 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5737 | !is_protmode(vcpu)) |
9c3e4aab MT |
5738 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5739 | ||
3842d135 AK |
5740 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5741 | ||
b6c7a5dc HB |
5742 | return 0; |
5743 | } | |
5744 | ||
d0bfb940 JK |
5745 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5746 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5747 | { |
355be0b9 | 5748 | unsigned long rflags; |
ae675ef0 | 5749 | int i, r; |
b6c7a5dc | 5750 | |
4f926bf2 JK |
5751 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5752 | r = -EBUSY; | |
5753 | if (vcpu->arch.exception.pending) | |
2122ff5e | 5754 | goto out; |
4f926bf2 JK |
5755 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
5756 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5757 | else | |
5758 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5759 | } | |
5760 | ||
91586a3b JK |
5761 | /* |
5762 | * Read rflags as long as potentially injected trace flags are still | |
5763 | * filtered out. | |
5764 | */ | |
5765 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5766 | |
5767 | vcpu->guest_debug = dbg->control; | |
5768 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5769 | vcpu->guest_debug = 0; | |
5770 | ||
5771 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5772 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5773 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5774 | vcpu->arch.switch_db_regs = | |
5775 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5776 | } else { | |
5777 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5778 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5779 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5780 | } | |
5781 | ||
f92653ee JK |
5782 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5783 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5784 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5785 | |
91586a3b JK |
5786 | /* |
5787 | * Trigger an rflags update that will inject or remove the trace | |
5788 | * flags. | |
5789 | */ | |
5790 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5791 | |
355be0b9 | 5792 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5793 | |
4f926bf2 | 5794 | r = 0; |
d0bfb940 | 5795 | |
2122ff5e | 5796 | out: |
b6c7a5dc HB |
5797 | |
5798 | return r; | |
5799 | } | |
5800 | ||
8b006791 ZX |
5801 | /* |
5802 | * Translate a guest virtual address to a guest physical address. | |
5803 | */ | |
5804 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5805 | struct kvm_translation *tr) | |
5806 | { | |
5807 | unsigned long vaddr = tr->linear_address; | |
5808 | gpa_t gpa; | |
f656ce01 | 5809 | int idx; |
8b006791 | 5810 | |
f656ce01 | 5811 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5812 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5813 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5814 | tr->physical_address = gpa; |
5815 | tr->valid = gpa != UNMAPPED_GVA; | |
5816 | tr->writeable = 1; | |
5817 | tr->usermode = 0; | |
8b006791 ZX |
5818 | |
5819 | return 0; | |
5820 | } | |
5821 | ||
d0752060 HB |
5822 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5823 | { | |
98918833 SY |
5824 | struct i387_fxsave_struct *fxsave = |
5825 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5826 | |
d0752060 HB |
5827 | memcpy(fpu->fpr, fxsave->st_space, 128); |
5828 | fpu->fcw = fxsave->cwd; | |
5829 | fpu->fsw = fxsave->swd; | |
5830 | fpu->ftwx = fxsave->twd; | |
5831 | fpu->last_opcode = fxsave->fop; | |
5832 | fpu->last_ip = fxsave->rip; | |
5833 | fpu->last_dp = fxsave->rdp; | |
5834 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5835 | ||
d0752060 HB |
5836 | return 0; |
5837 | } | |
5838 | ||
5839 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5840 | { | |
98918833 SY |
5841 | struct i387_fxsave_struct *fxsave = |
5842 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5843 | |
d0752060 HB |
5844 | memcpy(fxsave->st_space, fpu->fpr, 128); |
5845 | fxsave->cwd = fpu->fcw; | |
5846 | fxsave->swd = fpu->fsw; | |
5847 | fxsave->twd = fpu->ftwx; | |
5848 | fxsave->fop = fpu->last_opcode; | |
5849 | fxsave->rip = fpu->last_ip; | |
5850 | fxsave->rdp = fpu->last_dp; | |
5851 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5852 | ||
d0752060 HB |
5853 | return 0; |
5854 | } | |
5855 | ||
10ab25cd | 5856 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 5857 | { |
10ab25cd JK |
5858 | int err; |
5859 | ||
5860 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
5861 | if (err) | |
5862 | return err; | |
5863 | ||
98918833 | 5864 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 5865 | |
2acf923e DC |
5866 | /* |
5867 | * Ensure guest xcr0 is valid for loading | |
5868 | */ | |
5869 | vcpu->arch.xcr0 = XSTATE_FP; | |
5870 | ||
ad312c7c | 5871 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
5872 | |
5873 | return 0; | |
d0752060 HB |
5874 | } |
5875 | EXPORT_SYMBOL_GPL(fx_init); | |
5876 | ||
98918833 SY |
5877 | static void fx_free(struct kvm_vcpu *vcpu) |
5878 | { | |
5879 | fpu_free(&vcpu->arch.guest_fpu); | |
5880 | } | |
5881 | ||
d0752060 HB |
5882 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
5883 | { | |
2608d7a1 | 5884 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5885 | return; |
5886 | ||
2acf923e DC |
5887 | /* |
5888 | * Restore all possible states in the guest, | |
5889 | * and assume host would use all available bits. | |
5890 | * Guest xcr0 would be loaded later. | |
5891 | */ | |
5892 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 5893 | vcpu->guest_fpu_loaded = 1; |
7cf30855 | 5894 | unlazy_fpu(current); |
98918833 | 5895 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 5896 | trace_kvm_fpu(1); |
d0752060 | 5897 | } |
d0752060 HB |
5898 | |
5899 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5900 | { | |
2acf923e DC |
5901 | kvm_put_guest_xcr0(vcpu); |
5902 | ||
d0752060 HB |
5903 | if (!vcpu->guest_fpu_loaded) |
5904 | return; | |
5905 | ||
5906 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 5907 | fpu_save_init(&vcpu->arch.guest_fpu); |
f096ed85 | 5908 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 5909 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 5910 | trace_kvm_fpu(0); |
d0752060 | 5911 | } |
e9b11c17 ZX |
5912 | |
5913 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5914 | { | |
12f9a48f | 5915 | kvmclock_reset(vcpu); |
7f1ea208 | 5916 | |
f5f48ee1 | 5917 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 5918 | fx_free(vcpu); |
e9b11c17 ZX |
5919 | kvm_x86_ops->vcpu_free(vcpu); |
5920 | } | |
5921 | ||
5922 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5923 | unsigned int id) | |
5924 | { | |
6755bae8 ZA |
5925 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
5926 | printk_once(KERN_WARNING | |
5927 | "kvm: SMP vm created on host with unstable TSC; " | |
5928 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
5929 | return kvm_x86_ops->vcpu_create(kvm, id); |
5930 | } | |
e9b11c17 | 5931 | |
26e5215f AK |
5932 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5933 | { | |
5934 | int r; | |
e9b11c17 | 5935 | |
0bed3b56 | 5936 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5937 | vcpu_load(vcpu); |
5938 | r = kvm_arch_vcpu_reset(vcpu); | |
5939 | if (r == 0) | |
5940 | r = kvm_mmu_setup(vcpu); | |
5941 | vcpu_put(vcpu); | |
5942 | if (r < 0) | |
5943 | goto free_vcpu; | |
5944 | ||
26e5215f | 5945 | return 0; |
e9b11c17 ZX |
5946 | free_vcpu: |
5947 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 5948 | return r; |
e9b11c17 ZX |
5949 | } |
5950 | ||
d40ccc62 | 5951 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 5952 | { |
344d9588 GN |
5953 | vcpu->arch.apf.msr_val = 0; |
5954 | ||
e9b11c17 ZX |
5955 | vcpu_load(vcpu); |
5956 | kvm_mmu_unload(vcpu); | |
5957 | vcpu_put(vcpu); | |
5958 | ||
98918833 | 5959 | fx_free(vcpu); |
e9b11c17 ZX |
5960 | kvm_x86_ops->vcpu_free(vcpu); |
5961 | } | |
5962 | ||
5963 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
5964 | { | |
448fa4a9 JK |
5965 | vcpu->arch.nmi_pending = false; |
5966 | vcpu->arch.nmi_injected = false; | |
5967 | ||
42dbaa5a JK |
5968 | vcpu->arch.switch_db_regs = 0; |
5969 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
5970 | vcpu->arch.dr6 = DR6_FIXED_1; | |
5971 | vcpu->arch.dr7 = DR7_FIXED_1; | |
5972 | ||
3842d135 | 5973 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 5974 | vcpu->arch.apf.msr_val = 0; |
3842d135 | 5975 | |
12f9a48f GC |
5976 | kvmclock_reset(vcpu); |
5977 | ||
af585b92 GN |
5978 | kvm_clear_async_pf_completion_queue(vcpu); |
5979 | kvm_async_pf_hash_reset(vcpu); | |
5980 | vcpu->arch.apf.halted = false; | |
3842d135 | 5981 | |
e9b11c17 ZX |
5982 | return kvm_x86_ops->vcpu_reset(vcpu); |
5983 | } | |
5984 | ||
10474ae8 | 5985 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 5986 | { |
ca84d1a2 ZA |
5987 | struct kvm *kvm; |
5988 | struct kvm_vcpu *vcpu; | |
5989 | int i; | |
18863bdd AK |
5990 | |
5991 | kvm_shared_msr_cpu_online(); | |
ca84d1a2 ZA |
5992 | list_for_each_entry(kvm, &vm_list, vm_list) |
5993 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5994 | if (vcpu->cpu == smp_processor_id()) | |
c285545f | 5995 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
10474ae8 | 5996 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5997 | } |
5998 | ||
5999 | void kvm_arch_hardware_disable(void *garbage) | |
6000 | { | |
6001 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 6002 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
6003 | } |
6004 | ||
6005 | int kvm_arch_hardware_setup(void) | |
6006 | { | |
6007 | return kvm_x86_ops->hardware_setup(); | |
6008 | } | |
6009 | ||
6010 | void kvm_arch_hardware_unsetup(void) | |
6011 | { | |
6012 | kvm_x86_ops->hardware_unsetup(); | |
6013 | } | |
6014 | ||
6015 | void kvm_arch_check_processor_compat(void *rtn) | |
6016 | { | |
6017 | kvm_x86_ops->check_processor_compatibility(rtn); | |
6018 | } | |
6019 | ||
6020 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
6021 | { | |
6022 | struct page *page; | |
6023 | struct kvm *kvm; | |
6024 | int r; | |
6025 | ||
6026 | BUG_ON(vcpu->kvm == NULL); | |
6027 | kvm = vcpu->kvm; | |
6028 | ||
9aabc88f | 6029 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
14dfe855 | 6030 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
ad312c7c | 6031 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c30a358d | 6032 | vcpu->arch.mmu.translate_gpa = translate_gpa; |
02f59dc9 | 6033 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
c5af89b6 | 6034 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 6035 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 6036 | else |
a4535290 | 6037 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
6038 | |
6039 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
6040 | if (!page) { | |
6041 | r = -ENOMEM; | |
6042 | goto fail; | |
6043 | } | |
ad312c7c | 6044 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 6045 | |
c285545f ZA |
6046 | if (!kvm->arch.virtual_tsc_khz) |
6047 | kvm_arch_set_tsc_khz(kvm, max_tsc_khz); | |
6048 | ||
e9b11c17 ZX |
6049 | r = kvm_mmu_create(vcpu); |
6050 | if (r < 0) | |
6051 | goto fail_free_pio_data; | |
6052 | ||
6053 | if (irqchip_in_kernel(kvm)) { | |
6054 | r = kvm_create_lapic(vcpu); | |
6055 | if (r < 0) | |
6056 | goto fail_mmu_destroy; | |
6057 | } | |
6058 | ||
890ca9ae HY |
6059 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
6060 | GFP_KERNEL); | |
6061 | if (!vcpu->arch.mce_banks) { | |
6062 | r = -ENOMEM; | |
443c39bc | 6063 | goto fail_free_lapic; |
890ca9ae HY |
6064 | } |
6065 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
6066 | ||
f5f48ee1 SY |
6067 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) |
6068 | goto fail_free_mce_banks; | |
6069 | ||
af585b92 GN |
6070 | kvm_async_pf_hash_reset(vcpu); |
6071 | ||
e9b11c17 | 6072 | return 0; |
f5f48ee1 SY |
6073 | fail_free_mce_banks: |
6074 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
6075 | fail_free_lapic: |
6076 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
6077 | fail_mmu_destroy: |
6078 | kvm_mmu_destroy(vcpu); | |
6079 | fail_free_pio_data: | |
ad312c7c | 6080 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
6081 | fail: |
6082 | return r; | |
6083 | } | |
6084 | ||
6085 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
6086 | { | |
f656ce01 MT |
6087 | int idx; |
6088 | ||
36cb93fd | 6089 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 6090 | kvm_free_lapic(vcpu); |
f656ce01 | 6091 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 6092 | kvm_mmu_destroy(vcpu); |
f656ce01 | 6093 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 6094 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 6095 | } |
d19a9cd2 | 6096 | |
d89f5eff | 6097 | int kvm_arch_init_vm(struct kvm *kvm) |
d19a9cd2 | 6098 | { |
f05e70ac | 6099 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 6100 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 6101 | |
5550af4d SY |
6102 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
6103 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
6104 | ||
038f8c11 | 6105 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
53f658b3 | 6106 | |
d89f5eff | 6107 | return 0; |
d19a9cd2 ZX |
6108 | } |
6109 | ||
6110 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
6111 | { | |
6112 | vcpu_load(vcpu); | |
6113 | kvm_mmu_unload(vcpu); | |
6114 | vcpu_put(vcpu); | |
6115 | } | |
6116 | ||
6117 | static void kvm_free_vcpus(struct kvm *kvm) | |
6118 | { | |
6119 | unsigned int i; | |
988a2cae | 6120 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
6121 | |
6122 | /* | |
6123 | * Unpin any mmu pages first. | |
6124 | */ | |
af585b92 GN |
6125 | kvm_for_each_vcpu(i, vcpu, kvm) { |
6126 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 6127 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 6128 | } |
988a2cae GN |
6129 | kvm_for_each_vcpu(i, vcpu, kvm) |
6130 | kvm_arch_vcpu_free(vcpu); | |
6131 | ||
6132 | mutex_lock(&kvm->lock); | |
6133 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
6134 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 6135 | |
988a2cae GN |
6136 | atomic_set(&kvm->online_vcpus, 0); |
6137 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
6138 | } |
6139 | ||
ad8ba2cd SY |
6140 | void kvm_arch_sync_events(struct kvm *kvm) |
6141 | { | |
ba4cef31 | 6142 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 6143 | kvm_free_pit(kvm); |
ad8ba2cd SY |
6144 | } |
6145 | ||
d19a9cd2 ZX |
6146 | void kvm_arch_destroy_vm(struct kvm *kvm) |
6147 | { | |
6eb55818 | 6148 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
6149 | kfree(kvm->arch.vpic); |
6150 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 6151 | kvm_free_vcpus(kvm); |
3d45830c AK |
6152 | if (kvm->arch.apic_access_page) |
6153 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
6154 | if (kvm->arch.ept_identity_pagetable) |
6155 | put_page(kvm->arch.ept_identity_pagetable); | |
d19a9cd2 | 6156 | } |
0de10343 | 6157 | |
f7784b8e MT |
6158 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
6159 | struct kvm_memory_slot *memslot, | |
0de10343 | 6160 | struct kvm_memory_slot old, |
f7784b8e | 6161 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
6162 | int user_alloc) |
6163 | { | |
f7784b8e | 6164 | int npages = memslot->npages; |
7ac77099 AK |
6165 | int map_flags = MAP_PRIVATE | MAP_ANONYMOUS; |
6166 | ||
6167 | /* Prevent internal slot pages from being moved by fork()/COW. */ | |
6168 | if (memslot->id >= KVM_MEMORY_SLOTS) | |
6169 | map_flags = MAP_SHARED | MAP_ANONYMOUS; | |
0de10343 ZX |
6170 | |
6171 | /*To keep backward compatibility with older userspace, | |
6172 | *x86 needs to hanlde !user_alloc case. | |
6173 | */ | |
6174 | if (!user_alloc) { | |
6175 | if (npages && !old.rmap) { | |
604b38ac AA |
6176 | unsigned long userspace_addr; |
6177 | ||
72dc67a6 | 6178 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
6179 | userspace_addr = do_mmap(NULL, 0, |
6180 | npages * PAGE_SIZE, | |
6181 | PROT_READ | PROT_WRITE, | |
7ac77099 | 6182 | map_flags, |
604b38ac | 6183 | 0); |
72dc67a6 | 6184 | up_write(¤t->mm->mmap_sem); |
0de10343 | 6185 | |
604b38ac AA |
6186 | if (IS_ERR((void *)userspace_addr)) |
6187 | return PTR_ERR((void *)userspace_addr); | |
6188 | ||
604b38ac | 6189 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
6190 | } |
6191 | } | |
6192 | ||
f7784b8e MT |
6193 | |
6194 | return 0; | |
6195 | } | |
6196 | ||
6197 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
6198 | struct kvm_userspace_memory_region *mem, | |
6199 | struct kvm_memory_slot old, | |
6200 | int user_alloc) | |
6201 | { | |
6202 | ||
48c0e4e9 | 6203 | int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT; |
f7784b8e MT |
6204 | |
6205 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
6206 | int ret; | |
6207 | ||
6208 | down_write(¤t->mm->mmap_sem); | |
6209 | ret = do_munmap(current->mm, old.userspace_addr, | |
6210 | old.npages * PAGE_SIZE); | |
6211 | up_write(¤t->mm->mmap_sem); | |
6212 | if (ret < 0) | |
6213 | printk(KERN_WARNING | |
6214 | "kvm_vm_ioctl_set_memory_region: " | |
6215 | "failed to munmap memory\n"); | |
6216 | } | |
6217 | ||
48c0e4e9 XG |
6218 | if (!kvm->arch.n_requested_mmu_pages) |
6219 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
6220 | ||
7c8a83b7 | 6221 | spin_lock(&kvm->mmu_lock); |
48c0e4e9 | 6222 | if (nr_mmu_pages) |
0de10343 | 6223 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
0de10343 | 6224 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); |
7c8a83b7 | 6225 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 6226 | } |
1d737c8a | 6227 | |
34d4cb8f MT |
6228 | void kvm_arch_flush_shadow(struct kvm *kvm) |
6229 | { | |
6230 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 6231 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
6232 | } |
6233 | ||
1d737c8a ZX |
6234 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
6235 | { | |
af585b92 GN |
6236 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6237 | !vcpu->arch.apf.halted) | |
6238 | || !list_empty_careful(&vcpu->async_pf.done) | |
a1b37100 GN |
6239 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
6240 | || vcpu->arch.nmi_pending || | |
6241 | (kvm_arch_interrupt_allowed(vcpu) && | |
6242 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 6243 | } |
5736199a | 6244 | |
5736199a ZX |
6245 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
6246 | { | |
32f88400 MT |
6247 | int me; |
6248 | int cpu = vcpu->cpu; | |
5736199a ZX |
6249 | |
6250 | if (waitqueue_active(&vcpu->wq)) { | |
6251 | wake_up_interruptible(&vcpu->wq); | |
6252 | ++vcpu->stat.halt_wakeup; | |
6253 | } | |
32f88400 MT |
6254 | |
6255 | me = get_cpu(); | |
6256 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
6b7e2d09 | 6257 | if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE) |
32f88400 | 6258 | smp_send_reschedule(cpu); |
e9571ed5 | 6259 | put_cpu(); |
5736199a | 6260 | } |
78646121 GN |
6261 | |
6262 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
6263 | { | |
6264 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
6265 | } | |
229456fc | 6266 | |
f92653ee JK |
6267 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
6268 | { | |
6269 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
6270 | get_segment_base(vcpu, VCPU_SREG_CS); | |
6271 | ||
6272 | return current_rip == linear_rip; | |
6273 | } | |
6274 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
6275 | ||
94fe45da JK |
6276 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
6277 | { | |
6278 | unsigned long rflags; | |
6279 | ||
6280 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
6281 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 6282 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
6283 | return rflags; |
6284 | } | |
6285 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
6286 | ||
6287 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
6288 | { | |
6289 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 6290 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 6291 | rflags |= X86_EFLAGS_TF; |
94fe45da | 6292 | kvm_x86_ops->set_rflags(vcpu, rflags); |
3842d135 | 6293 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
6294 | } |
6295 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
6296 | ||
56028d08 GN |
6297 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
6298 | { | |
6299 | int r; | |
6300 | ||
fb67e14f | 6301 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
c4806acd | 6302 | is_error_page(work->page)) |
56028d08 GN |
6303 | return; |
6304 | ||
6305 | r = kvm_mmu_reload(vcpu); | |
6306 | if (unlikely(r)) | |
6307 | return; | |
6308 | ||
fb67e14f XG |
6309 | if (!vcpu->arch.mmu.direct_map && |
6310 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
6311 | return; | |
6312 | ||
56028d08 GN |
6313 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
6314 | } | |
6315 | ||
af585b92 GN |
6316 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
6317 | { | |
6318 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
6319 | } | |
6320 | ||
6321 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
6322 | { | |
6323 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
6324 | } | |
6325 | ||
6326 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6327 | { | |
6328 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6329 | ||
6330 | while (vcpu->arch.apf.gfns[key] != ~0) | |
6331 | key = kvm_async_pf_next_probe(key); | |
6332 | ||
6333 | vcpu->arch.apf.gfns[key] = gfn; | |
6334 | } | |
6335 | ||
6336 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6337 | { | |
6338 | int i; | |
6339 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6340 | ||
6341 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
6342 | (vcpu->arch.apf.gfns[key] != gfn && |
6343 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
6344 | key = kvm_async_pf_next_probe(key); |
6345 | ||
6346 | return key; | |
6347 | } | |
6348 | ||
6349 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6350 | { | |
6351 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
6352 | } | |
6353 | ||
6354 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6355 | { | |
6356 | u32 i, j, k; | |
6357 | ||
6358 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
6359 | while (true) { | |
6360 | vcpu->arch.apf.gfns[i] = ~0; | |
6361 | do { | |
6362 | j = kvm_async_pf_next_probe(j); | |
6363 | if (vcpu->arch.apf.gfns[j] == ~0) | |
6364 | return; | |
6365 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
6366 | /* | |
6367 | * k lies cyclically in ]i,j] | |
6368 | * | i.k.j | | |
6369 | * |....j i.k.| or |.k..j i...| | |
6370 | */ | |
6371 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
6372 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
6373 | i = j; | |
6374 | } | |
6375 | } | |
6376 | ||
7c90705b GN |
6377 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
6378 | { | |
6379 | ||
6380 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
6381 | sizeof(val)); | |
6382 | } | |
6383 | ||
af585b92 GN |
6384 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
6385 | struct kvm_async_pf *work) | |
6386 | { | |
6389ee94 AK |
6387 | struct x86_exception fault; |
6388 | ||
7c90705b | 6389 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 6390 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
6391 | |
6392 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
6393 | (vcpu->arch.apf.send_user_only && |
6394 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
6395 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
6396 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
6397 | fault.vector = PF_VECTOR; |
6398 | fault.error_code_valid = true; | |
6399 | fault.error_code = 0; | |
6400 | fault.nested_page_fault = false; | |
6401 | fault.address = work->arch.token; | |
6402 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6403 | } |
af585b92 GN |
6404 | } |
6405 | ||
6406 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
6407 | struct kvm_async_pf *work) | |
6408 | { | |
6389ee94 AK |
6409 | struct x86_exception fault; |
6410 | ||
7c90705b GN |
6411 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
6412 | if (is_error_page(work->page)) | |
6413 | work->arch.token = ~0; /* broadcast wakeup */ | |
6414 | else | |
6415 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
6416 | ||
6417 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
6418 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
6419 | fault.vector = PF_VECTOR; |
6420 | fault.error_code_valid = true; | |
6421 | fault.error_code = 0; | |
6422 | fault.nested_page_fault = false; | |
6423 | fault.address = work->arch.token; | |
6424 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6425 | } |
e6d53e3b | 6426 | vcpu->arch.apf.halted = false; |
7c90705b GN |
6427 | } |
6428 | ||
6429 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
6430 | { | |
6431 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
6432 | return true; | |
6433 | else | |
6434 | return !kvm_event_needs_reinjection(vcpu) && | |
6435 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
6436 | } |
6437 | ||
229456fc MT |
6438 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
6439 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
6440 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
6441 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
6442 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 6443 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 6444 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 6445 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 6446 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 6447 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 6448 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 6449 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |