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KVM: X86: Let kvm-clock report the right tsc frequency
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
50a37eb4
JR		 66/* EFER defaults:
67 * - enable syscall per default because its emulated by KVM
68 * - enable LME and LMA per default on 64 bit KVM
69 */
70#ifdef CONFIG_X86_64
1260edbe
LJ		 71static
72u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 73#else
1260edbe 74static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
cb142eb7 80static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 81static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
82 struct kvm_cpuid_entry2 __user *entries);
83
97896d04 84struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 85EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 86
ed85c068
AP		 87int ignore_msrs = 0;
88module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
89
18863bdd
AK		 90#define KVM_NR_SHARED_MSRS 16
91
92struct kvm_shared_msrs_global {
93 int nr;
2bf78fa7 94 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 95};
96
97struct kvm_shared_msrs {
98 struct user_return_notifier urn;
99 bool registered;
2bf78fa7
SY		 100 struct kvm_shared_msr_values {
101 u64 host;
102 u64 curr;
103 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
107static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
108
417bc304 109struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 110 { "pf_fixed", VCPU_STAT(pf_fixed) },
111 { "pf_guest", VCPU_STAT(pf_guest) },
112 { "tlb_flush", VCPU_STAT(tlb_flush) },
113 { "invlpg", VCPU_STAT(invlpg) },
114 { "exits", VCPU_STAT(exits) },
115 { "io_exits", VCPU_STAT(io_exits) },
116 { "mmio_exits", VCPU_STAT(mmio_exits) },
117 { "signal_exits", VCPU_STAT(signal_exits) },
118 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 119 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 120 { "halt_exits", VCPU_STAT(halt_exits) },
121 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 122 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 123 { "request_irq", VCPU_STAT(request_irq_exits) },
124 { "irq_exits", VCPU_STAT(irq_exits) },
125 { "host_state_reload", VCPU_STAT(host_state_reload) },
126 { "efer_reload", VCPU_STAT(efer_reload) },
127 { "fpu_reload", VCPU_STAT(fpu_reload) },
128 { "insn_emulation", VCPU_STAT(insn_emulation) },
129 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 130 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 131 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 132 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
133 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
134 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
135 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
136 { "mmu_flooded", VM_STAT(mmu_flooded) },
137 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 138 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 139 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 140 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 141 { "largepages", VM_STAT(lpages) },
417bc304
HB		 142 { NULL }
143};
144
2acf923e
DC		 145u64 __read_mostly host_xcr0;
146
af585b92
GN		 147static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
148{
149 int i;
150 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
151 vcpu->arch.apf.gfns[i] = ~0;
152}
153
18863bdd
AK		 154static void kvm_on_user_return(struct user_return_notifier *urn)
155{
156 unsigned slot;
18863bdd
AK		 157 struct kvm_shared_msrs *locals
158 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 159 struct kvm_shared_msr_values *values;
18863bdd
AK		 160
161 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 162 values = &locals->values[slot];
163 if (values->host != values->curr) {
164 wrmsrl(shared_msrs_global.msrs[slot], values->host);
165 values->curr = values->host;
18863bdd
AK		 166 }
167 }
168 locals->registered = false;
169 user_return_notifier_unregister(urn);
170}
171
2bf78fa7 172static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 173{
2bf78fa7 174 struct kvm_shared_msrs *smsr;
18863bdd
AK		 175 u64 value;
176
2bf78fa7
SY		 177 smsr = &__get_cpu_var(shared_msrs);
178 /* only read, and nobody should modify it at this time,
179 * so don't need lock */
180 if (slot >= shared_msrs_global.nr) {
181 printk(KERN_ERR "kvm: invalid MSR slot!");
182 return;
183 }
184 rdmsrl_safe(msr, &value);
185 smsr->values[slot].host = value;
186 smsr->values[slot].curr = value;
187}
188
189void kvm_define_shared_msr(unsigned slot, u32 msr)
190{
18863bdd
AK		 191 if (slot >= shared_msrs_global.nr)
192 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 193 shared_msrs_global.msrs[slot] = msr;
194 /* we need ensured the shared_msr_global have been updated */
195 smp_wmb();
18863bdd
AK		 196}
197EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
198
199static void kvm_shared_msr_cpu_online(void)
200{
201 unsigned i;
18863bdd
AK		 202
203 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 204 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 205}
206
d5696725 207void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 208{
209 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
210
2bf78fa7 211 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 212 return;
2bf78fa7
SY		 213 smsr->values[slot].curr = value;
214 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 215 if (!smsr->registered) {
216 smsr->urn.on_user_return = kvm_on_user_return;
217 user_return_notifier_register(&smsr->urn);
218 smsr->registered = true;
219 }
220}
221EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
222
3548bab5
AK		 223static void drop_user_return_notifiers(void *ignore)
224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227 if (smsr->registered)
228 kvm_on_user_return(&smsr->urn);
229}
230
6866b83e
CO		 231u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
232{
233 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 234 return vcpu->arch.apic_base;
6866b83e 235 else
ad312c7c 236 return vcpu->arch.apic_base;
6866b83e
CO		 237}
238EXPORT_SYMBOL_GPL(kvm_get_apic_base);
239
240void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
241{
242 /* TODO: reserve bits check */
243 if (irqchip_in_kernel(vcpu->kvm))
244 kvm_lapic_set_base(vcpu, data);
245 else
ad312c7c 246 vcpu->arch.apic_base = data;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_set_apic_base);
249
3fd28fce
ED		 250#define EXCPT_BENIGN 0
251#define EXCPT_CONTRIBUTORY 1
252#define EXCPT_PF 2
253
254static int exception_class(int vector)
255{
256 switch (vector) {
257 case PF_VECTOR:
258 return EXCPT_PF;
259 case DE_VECTOR:
260 case TS_VECTOR:
261 case NP_VECTOR:
262 case SS_VECTOR:
263 case GP_VECTOR:
264 return EXCPT_CONTRIBUTORY;
265 default:
266 break;
267 }
268 return EXCPT_BENIGN;
269}
270
271static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 272 unsigned nr, bool has_error, u32 error_code,
273 bool reinject)
3fd28fce
ED		 274{
275 u32 prev_nr;
276 int class1, class2;
277
3842d135
AK		 278 kvm_make_request(KVM_REQ_EVENT, vcpu);
279
3fd28fce
ED		 280 if (!vcpu->arch.exception.pending) {
281 queue:
282 vcpu->arch.exception.pending = true;
283 vcpu->arch.exception.has_error_code = has_error;
284 vcpu->arch.exception.nr = nr;
285 vcpu->arch.exception.error_code = error_code;
3f0fd292 286 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 287 return;
288 }
289
290 /* to check exception */
291 prev_nr = vcpu->arch.exception.nr;
292 if (prev_nr == DF_VECTOR) {
293 /* triple fault -> shutdown */
a8eeb04a 294 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 295 return;
296 }
297 class1 = exception_class(prev_nr);
298 class2 = exception_class(nr);
299 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
300 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
301 /* generate double fault per SDM Table 5-5 */
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = true;
304 vcpu->arch.exception.nr = DF_VECTOR;
305 vcpu->arch.exception.error_code = 0;
306 } else
307 /* replace previous exception with a new one in a hope
308 that instruction re-execution will regenerate lost
309 exception */
310 goto queue;
311}
312
298101da
AK		 313void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
ce7ddec4 315 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 316}
317EXPORT_SYMBOL_GPL(kvm_queue_exception);
318
ce7ddec4
JR		 319void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
320{
321 kvm_multiple_exception(vcpu, nr, false, 0, true);
322}
323EXPORT_SYMBOL_GPL(kvm_requeue_exception);
324
db8fcefa 325void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 326{
db8fcefa
AP		 327 if (err)
328 kvm_inject_gp(vcpu, 0);
329 else
330 kvm_x86_ops->skip_emulated_instruction(vcpu);
331}
332EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 333
6389ee94 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 335{
336 ++vcpu->stat.pf_guest;
6389ee94
AK		 337 vcpu->arch.cr2 = fault->address;
338 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 339}
340
6389ee94 341void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 342{
6389ee94
AK		 343 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
344 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 345 else
6389ee94 346 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 347}
348
3419ffc8
SY		 349void kvm_inject_nmi(struct kvm_vcpu *vcpu)
350{
3842d135 351 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 352 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 353}
354EXPORT_SYMBOL_GPL(kvm_inject_nmi);
355
298101da
AK		 356void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
357{
ce7ddec4 358 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 359}
360EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
361
ce7ddec4
JR		 362void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
363{
364 kvm_multiple_exception(vcpu, nr, true, error_code, true);
365}
366EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
367
0a79b009
AK		 368/*
369 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
370 * a #GP and return false.
371 */
372bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 373{
0a79b009
AK		 374 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
375 return true;
376 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
377 return false;
298101da 378}
0a79b009 379EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 380
ec92fe44
JR		 381/*
382 * This function will be used to read from the physical memory of the currently
383 * running guest. The difference to kvm_read_guest_page is that this function
384 * can read from guest physical or from the guest's guest physical memory.
385 */
386int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
387 gfn_t ngfn, void *data, int offset, int len,
388 u32 access)
389{
390 gfn_t real_gfn;
391 gpa_t ngpa;
392
393 ngpa = gfn_to_gpa(ngfn);
394 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
395 if (real_gfn == UNMAPPED_GVA)
396 return -EFAULT;
397
398 real_gfn = gpa_to_gfn(real_gfn);
399
400 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
401}
402EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
403
3d06b8bf
JR		 404int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
405 void *data, int offset, int len, u32 access)
406{
407 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
408 data, offset, len, access);
409}
410
a03490ed
CO		 411/*
412 * Load the pae pdptrs. Return true is they are all valid.
413 */
ff03a073 414int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 415{
416 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
417 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
418 int i;
419 int ret;
ff03a073 420 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 421
ff03a073
JR		 422 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
423 offset * sizeof(u64), sizeof(pdpte),
424 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 425 if (ret < 0) {
426 ret = 0;
427 goto out;
428 }
429 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 430 if (is_present_gpte(pdpte[i]) &&
20c466b5 431 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 432 ret = 0;
433 goto out;
434 }
435 }
436 ret = 1;
437
ff03a073 438 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 439 __set_bit(VCPU_EXREG_PDPTR,
440 (unsigned long *)&vcpu->arch.regs_avail);
441 __set_bit(VCPU_EXREG_PDPTR,
442 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 443out:
a03490ed
CO		 444
445 return ret;
446}
cc4b6871 447EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 448
d835dfec
AK		 449static bool pdptrs_changed(struct kvm_vcpu *vcpu)
450{
ff03a073 451 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 452 bool changed = true;
3d06b8bf
JR		 453 int offset;
454 gfn_t gfn;
d835dfec
AK		 455 int r;
456
457 if (is_long_mode(vcpu) || !is_pae(vcpu))
458 return false;
459
6de4f3ad
AK		 460 if (!test_bit(VCPU_EXREG_PDPTR,
461 (unsigned long *)&vcpu->arch.regs_avail))
462 return true;
463
9f8fe504
AK		 464 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
465 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 466 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
467 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 468 if (r < 0)
469 goto out;
ff03a073 470 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 471out:
d835dfec
AK		 472
473 return changed;
474}
475
49a9b07e 476int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 477{
aad82703
SY		 478 unsigned long old_cr0 = kvm_read_cr0(vcpu);
479 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
480 X86_CR0_CD | X86_CR0_NW;
481
f9a48e6a
AK		 482 cr0 |= X86_CR0_ET;
483
ab344828 484#ifdef CONFIG_X86_64
0f12244f
GN		 485 if (cr0 & 0xffffffff00000000UL)
486 return 1;
ab344828
GN		 487#endif
488
489 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 490
0f12244f
GN		 491 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
492 return 1;
a03490ed 493
0f12244f
GN		 494 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
495 return 1;
a03490ed
CO		 496
497 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
498#ifdef CONFIG_X86_64
f6801dff 499 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 500 int cs_db, cs_l;
501
0f12244f
GN		 502 if (!is_pae(vcpu))
503 return 1;
a03490ed 504 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 505 if (cs_l)
506 return 1;
a03490ed
CO		 507 } else
508#endif
ff03a073 509 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 510 kvm_read_cr3(vcpu)))
0f12244f 511 return 1;
a03490ed
CO		 512 }
513
514 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 515
d170c419 516 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 517 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 518 kvm_async_pf_hash_reset(vcpu);
519 }
e5f3f027 520
aad82703
SY		 521 if ((cr0 ^ old_cr0) & update_bits)
522 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 523 return 0;
524}
2d3ad1f4 525EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 526
2d3ad1f4 527void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 528{
49a9b07e 529 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 530}
2d3ad1f4 531EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 532
2acf923e
DC		 533int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
534{
535 u64 xcr0;
536
537 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
538 if (index != XCR_XFEATURE_ENABLED_MASK)
539 return 1;
540 xcr0 = xcr;
541 if (kvm_x86_ops->get_cpl(vcpu) != 0)
542 return 1;
543 if (!(xcr0 & XSTATE_FP))
544 return 1;
545 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
546 return 1;
547 if (xcr0 & ~host_xcr0)
548 return 1;
549 vcpu->arch.xcr0 = xcr0;
550 vcpu->guest_xcr0_loaded = 0;
551 return 0;
552}
553
554int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
555{
556 if (__kvm_set_xcr(vcpu, index, xcr)) {
557 kvm_inject_gp(vcpu, 0);
558 return 1;
559 }
560 return 0;
561}
562EXPORT_SYMBOL_GPL(kvm_set_xcr);
563
564static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
565{
566 struct kvm_cpuid_entry2 *best;
567
568 best = kvm_find_cpuid_entry(vcpu, 1, 0);
569 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
570}
571
572static void update_cpuid(struct kvm_vcpu *vcpu)
573{
574 struct kvm_cpuid_entry2 *best;
575
576 best = kvm_find_cpuid_entry(vcpu, 1, 0);
577 if (!best)
578 return;
579
580 /* Update OSXSAVE bit */
581 if (cpu_has_xsave && best->function == 0x1) {
582 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
583 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
584 best->ecx |= bit(X86_FEATURE_OSXSAVE);
585 }
586}
587
a83b29c6 588int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 589{
fc78f519 590 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 591 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
592
0f12244f
GN		 593 if (cr4 & CR4_RESERVED_BITS)
594 return 1;
a03490ed 595
2acf923e
DC		 596 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
597 return 1;
598
a03490ed 599 if (is_long_mode(vcpu)) {
0f12244f
GN		 600 if (!(cr4 & X86_CR4_PAE))
601 return 1;
a2edf57f
AK		 602 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
603 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 604 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
605 kvm_read_cr3(vcpu)))
0f12244f
GN		 606 return 1;
607
608 if (cr4 & X86_CR4_VMXE)
609 return 1;
a03490ed 610
a03490ed 611 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 612
aad82703
SY		 613 if ((cr4 ^ old_cr4) & pdptr_bits)
614 kvm_mmu_reset_context(vcpu);
0f12244f 615
2acf923e
DC		 616 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
617 update_cpuid(vcpu);
618
0f12244f
GN		 619 return 0;
620}
2d3ad1f4 621EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 622
2390218b 623int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 624{
9f8fe504 625 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 626 kvm_mmu_sync_roots(vcpu);
d835dfec 627 kvm_mmu_flush_tlb(vcpu);
0f12244f 628 return 0;
d835dfec
AK		 629 }
630
a03490ed 631 if (is_long_mode(vcpu)) {
0f12244f
GN		 632 if (cr3 & CR3_L_MODE_RESERVED_BITS)
633 return 1;
a03490ed
CO		 634 } else {
635 if (is_pae(vcpu)) {
0f12244f
GN		 636 if (cr3 & CR3_PAE_RESERVED_BITS)
637 return 1;
ff03a073
JR		 638 if (is_paging(vcpu) &&
639 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 640 return 1;
a03490ed
CO		 641 }
642 /*
643 * We don't check reserved bits in nonpae mode, because
644 * this isn't enforced, and VMware depends on this.
645 */
646 }
647
a03490ed
CO		 648 /*
649 * Does the new cr3 value map to physical memory? (Note, we
650 * catch an invalid cr3 even in real-mode, because it would
651 * cause trouble later on when we turn on paging anyway.)
652 *
653 * A real CPU would silently accept an invalid cr3 and would
654 * attempt to use it - with largely undefined (and often hard
655 * to debug) behavior on the guest side.
656 */
657 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 658 return 1;
659 vcpu->arch.cr3 = cr3;
aff48baa 660 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 661 vcpu->arch.mmu.new_cr3(vcpu);
662 return 0;
663}
2d3ad1f4 664EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 665
eea1cff9 666int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 667{
0f12244f
GN		 668 if (cr8 & CR8_RESERVED_BITS)
669 return 1;
a03490ed
CO		 670 if (irqchip_in_kernel(vcpu->kvm))
671 kvm_lapic_set_tpr(vcpu, cr8);
672 else
ad312c7c 673 vcpu->arch.cr8 = cr8;
0f12244f
GN		 674 return 0;
675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 677
2d3ad1f4 678unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 679{
680 if (irqchip_in_kernel(vcpu->kvm))
681 return kvm_lapic_get_cr8(vcpu);
682 else
ad312c7c 683 return vcpu->arch.cr8;
a03490ed 684}
2d3ad1f4 685EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 686
338dbc97 687static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 688{
689 switch (dr) {
690 case 0 ... 3:
691 vcpu->arch.db[dr] = val;
692 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
693 vcpu->arch.eff_db[dr] = val;
694 break;
695 case 4:
338dbc97
GN		 696 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
697 return 1; /* #UD */
020df079
GN		 698 /* fall through */
699 case 6:
338dbc97
GN		 700 if (val & 0xffffffff00000000ULL)
701 return -1; /* #GP */
020df079
GN		 702 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
703 break;
704 case 5:
338dbc97
GN		 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
706 return 1; /* #UD */
020df079
GN		 707 /* fall through */
708 default: /* 7 */
338dbc97
GN		 709 if (val & 0xffffffff00000000ULL)
710 return -1; /* #GP */
020df079
GN		 711 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
712 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
713 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
714 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
715 }
716 break;
717 }
718
719 return 0;
720}
338dbc97
GN		 721
722int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
723{
724 int res;
725
726 res = __kvm_set_dr(vcpu, dr, val);
727 if (res > 0)
728 kvm_queue_exception(vcpu, UD_VECTOR);
729 else if (res < 0)
730 kvm_inject_gp(vcpu, 0);
731
732 return res;
733}
020df079
GN		 734EXPORT_SYMBOL_GPL(kvm_set_dr);
735
338dbc97 736static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 737{
738 switch (dr) {
739 case 0 ... 3:
740 *val = vcpu->arch.db[dr];
741 break;
742 case 4:
338dbc97 743 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 744 return 1;
020df079
GN		 745 /* fall through */
746 case 6:
747 *val = vcpu->arch.dr6;
748 break;
749 case 5:
338dbc97 750 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 751 return 1;
020df079
GN		 752 /* fall through */
753 default: /* 7 */
754 *val = vcpu->arch.dr7;
755 break;
756 }
757
758 return 0;
759}
338dbc97
GN		 760
761int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
762{
763 if (_kvm_get_dr(vcpu, dr, val)) {
764 kvm_queue_exception(vcpu, UD_VECTOR);
765 return 1;
766 }
767 return 0;
768}
020df079
GN		 769EXPORT_SYMBOL_GPL(kvm_get_dr);
770
043405e1
CO		 771/*
772 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
773 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
774 *
775 * This list is modified at module load time to reflect the
e3267cbb
GC		 776 * capabilities of the host cpu. This capabilities test skips MSRs that are
777 * kvm-specific. Those are put in the beginning of the list.
043405e1 778 */
e3267cbb 779
344d9588 780#define KVM_SAVE_MSRS_BEGIN 8
043405e1 781static u32 msrs_to_save[] = {
e3267cbb 782 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 783 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 784 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 785 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 786 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 787 MSR_STAR,
043405e1
CO		 788#ifdef CONFIG_X86_64
789 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
790#endif
e90aa41e 791 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 792};
793
794static unsigned num_msrs_to_save;
795
796static u32 emulated_msrs[] = {
797 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 798 MSR_IA32_MCG_STATUS,
799 MSR_IA32_MCG_CTL,
043405e1
CO		 800};
801
b69e8cae 802static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 803{
aad82703
SY		 804 u64 old_efer = vcpu->arch.efer;
805
b69e8cae
RJ		 806 if (efer & efer_reserved_bits)
807 return 1;
15c4a640
CO		 808
809 if (is_paging(vcpu)
b69e8cae
RJ		 810 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
811 return 1;
15c4a640 812
1b2fd70c
AG		 813 if (efer & EFER_FFXSR) {
814 struct kvm_cpuid_entry2 *feat;
815
816 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 817 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
818 return 1;
1b2fd70c
AG		 819 }
820
d8017474
AG		 821 if (efer & EFER_SVME) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
826 return 1;
d8017474
AG		 827 }
828
15c4a640 829 efer &= ~EFER_LMA;
f6801dff 830 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 831
a3d204e2
SY		 832 kvm_x86_ops->set_efer(vcpu, efer);
833
9645bb56 834 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 835
aad82703
SY		 836 /* Update reserved bits */
837 if ((efer ^ old_efer) & EFER_NX)
838 kvm_mmu_reset_context(vcpu);
839
b69e8cae 840 return 0;
15c4a640
CO		 841}
842
f2b4b7dd
JR		 843void kvm_enable_efer_bits(u64 mask)
844{
845 efer_reserved_bits &= ~mask;
846}
847EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
848
849
15c4a640
CO		 850/*
851 * Writes msr value into into the appropriate "register".
852 * Returns 0 on success, non-0 otherwise.
853 * Assumes vcpu_load() was already called.
854 */
855int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
856{
857 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
858}
859
313a3dc7
CO		 860/*
861 * Adapt set_msr() to msr_io()'s calling convention
862 */
863static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
864{
865 return kvm_set_msr(vcpu, index, *data);
866}
867
18068523
GOC		 868static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
869{
9ed3c444
AK		 870 int version;
871 int r;
50d0a0f9 872 struct pvclock_wall_clock wc;
923de3cf 873 struct timespec boot;
18068523
GOC		 874
875 if (!wall_clock)
876 return;
877
9ed3c444
AK		 878 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
879 if (r)
880 return;
881
882 if (version & 1)
883 ++version; /* first time write, random junk */
884
885 ++version;
18068523 886
18068523
GOC		 887 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
888
50d0a0f9
GH		 889 /*
890 * The guest calculates current wall clock time by adding
34c238a1 891 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 892 * wall clock specified here. guest system time equals host
893 * system time for us, thus we must fill in host boot time here.
894 */
923de3cf 895 getboottime(&boot);
50d0a0f9
GH		 896
897 wc.sec = boot.tv_sec;
898 wc.nsec = boot.tv_nsec;
899 wc.version = version;
18068523
GOC		 900
901 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
902
903 version++;
904 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 905}
906
50d0a0f9
GH		 907static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
908{
909 uint32_t quotient, remainder;
910
911 /* Don't try to replace with do_div(), this one calculates
912 * "(dividend << 32) / divisor" */
913 __asm__ ( "divl %4"
914 : "=a" (quotient), "=d" (remainder)
915 : "0" (0), "1" (dividend), "r" (divisor) );
916 return quotient;
917}
918
5f4e3f88
ZA		 919static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
920 s8 *pshift, u32 *pmultiplier)
50d0a0f9 921{
5f4e3f88 922 uint64_t scaled64;
50d0a0f9
GH		 923 int32_t shift = 0;
924 uint64_t tps64;
925 uint32_t tps32;
926
5f4e3f88
ZA		 927 tps64 = base_khz * 1000LL;
928 scaled64 = scaled_khz * 1000LL;
50933623 929 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 930 tps64 >>= 1;
931 shift--;
932 }
933
934 tps32 = (uint32_t)tps64;
50933623
JK		 935 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
936 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 937 scaled64 >>= 1;
938 else
939 tps32 <<= 1;
50d0a0f9
GH		 940 shift++;
941 }
942
5f4e3f88
ZA		 943 *pshift = shift;
944 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 945
5f4e3f88
ZA		 946 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
947 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 948}
949
759379dd
ZA		 950static inline u64 get_kernel_ns(void)
951{
952 struct timespec ts;
953
954 WARN_ON(preemptible());
955 ktime_get_ts(&ts);
956 monotonic_to_bootbased(&ts);
957 return timespec_to_ns(&ts);
50d0a0f9
GH		 958}
959
c8076604 960static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 961unsigned long max_tsc_khz;
c8076604 962
8cfdc000
ZA		 963static inline int kvm_tsc_changes_freq(void)
964{
965 int cpu = get_cpu();
966 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
967 cpufreq_quick_get(cpu) != 0;
968 put_cpu();
969 return ret;
970}
971
1e993611
JR		 972static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
973{
974 if (vcpu->arch.virtual_tsc_khz)
975 return vcpu->arch.virtual_tsc_khz;
976 else
977 return __this_cpu_read(cpu_tsc_khz);
978}
979
759379dd
ZA		 980static inline u64 nsec_to_cycles(u64 nsec)
981{
217fc9cf
AK		 982 u64 ret;
983
759379dd
ZA		 984 WARN_ON(preemptible());
985 if (kvm_tsc_changes_freq())
986 printk_once(KERN_WARNING
987 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
0a3aee0d 988 ret = nsec * __this_cpu_read(cpu_tsc_khz);
217fc9cf
AK		 989 do_div(ret, USEC_PER_SEC);
990 return ret;
759379dd
ZA		 991}
992
1e993611 993static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 994{
995 /* Compute a scale to convert nanoseconds in TSC cycles */
996 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 997 &vcpu->arch.tsc_catchup_shift,
998 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 999}
1000
1001static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1002{
1003 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1004 vcpu->arch.tsc_catchup_mult,
1005 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1006 tsc += vcpu->arch.last_tsc_write;
1007 return tsc;
1008}
1009
99e3e30a
ZA		 1010void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1011{
1012 struct kvm *kvm = vcpu->kvm;
f38e098f 1013 u64 offset, ns, elapsed;
99e3e30a 1014 unsigned long flags;
46543ba4 1015 s64 sdiff;
99e3e30a 1016
038f8c11 1017 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1018 offset = data - native_read_tsc();
759379dd 1019 ns = get_kernel_ns();
f38e098f 1020 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1021 sdiff = data - kvm->arch.last_tsc_write;
1022 if (sdiff < 0)
1023 sdiff = -sdiff;
f38e098f
ZA		 1024
1025 /*
46543ba4 1026 * Special case: close write to TSC within 5 seconds of
f38e098f 1027 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1028 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1029 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1030 *
1031 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1032 * or make a best guest using elapsed value.
f38e098f 1033 */
46543ba4
ZA		 1034 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1035 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1036 if (!check_tsc_unstable()) {
1037 offset = kvm->arch.last_tsc_offset;
1038 pr_debug("kvm: matched tsc offset for %llu\n", data);
1039 } else {
759379dd
ZA		 1040 u64 delta = nsec_to_cycles(elapsed);
1041 offset += delta;
1042 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1043 }
1044 ns = kvm->arch.last_tsc_nsec;
1045 }
1046 kvm->arch.last_tsc_nsec = ns;
1047 kvm->arch.last_tsc_write = data;
1048 kvm->arch.last_tsc_offset = offset;
99e3e30a 1049 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1050 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1051
1052 /* Reset of TSC must disable overshoot protection below */
1053 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1054 vcpu->arch.last_tsc_write = data;
1055 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1056}
1057EXPORT_SYMBOL_GPL(kvm_write_tsc);
1058
34c238a1 1059static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1060{
18068523
GOC		 1061 unsigned long flags;
1062 struct kvm_vcpu_arch *vcpu = &v->arch;
1063 void *shared_kaddr;
463656c0 1064 unsigned long this_tsc_khz;
1d5f066e
ZA		 1065 s64 kernel_ns, max_kernel_ns;
1066 u64 tsc_timestamp;
18068523 1067
18068523
GOC		 1068 /* Keep irq disabled to prevent changes to the clock */
1069 local_irq_save(flags);
1d5f066e 1070 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1071 kernel_ns = get_kernel_ns();
1e993611 1072 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1073 if (unlikely(this_tsc_khz == 0)) {
c285545f 1074 local_irq_restore(flags);
34c238a1 1075 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1076 return 1;
1077 }
18068523 1078
c285545f
ZA		 1079 /*
1080 * We may have to catch up the TSC to match elapsed wall clock
1081 * time for two reasons, even if kvmclock is used.
1082 * 1) CPU could have been running below the maximum TSC rate
1083 * 2) Broken TSC compensation resets the base at each VCPU
1084 * entry to avoid unknown leaps of TSC even when running
1085 * again on the same CPU. This may cause apparent elapsed
1086 * time to disappear, and the guest to stand still or run
1087 * very slowly.
1088 */
1089 if (vcpu->tsc_catchup) {
1090 u64 tsc = compute_guest_tsc(v, kernel_ns);
1091 if (tsc > tsc_timestamp) {
1092 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1093 tsc_timestamp = tsc;
1094 }
50d0a0f9
GH		 1095 }
1096
18068523
GOC		 1097 local_irq_restore(flags);
1098
c285545f
ZA		 1099 if (!vcpu->time_page)
1100 return 0;
18068523 1101
1d5f066e
ZA		 1102 /*
1103 * Time as measured by the TSC may go backwards when resetting the base
1104 * tsc_timestamp. The reason for this is that the TSC resolution is
1105 * higher than the resolution of the other clock scales. Thus, many
1106 * possible measurments of the TSC correspond to one measurement of any
1107 * other clock, and so a spread of values is possible. This is not a
1108 * problem for the computation of the nanosecond clock; with TSC rates
1109 * around 1GHZ, there can only be a few cycles which correspond to one
1110 * nanosecond value, and any path through this code will inevitably
1111 * take longer than that. However, with the kernel_ns value itself,
1112 * the precision may be much lower, down to HZ granularity. If the
1113 * first sampling of TSC against kernel_ns ends in the low part of the
1114 * range, and the second in the high end of the range, we can get:
1115 *
1116 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1117 *
1118 * As the sampling errors potentially range in the thousands of cycles,
1119 * it is possible such a time value has already been observed by the
1120 * guest. To protect against this, we must compute the system time as
1121 * observed by the guest and ensure the new system time is greater.
1122 */
1123 max_kernel_ns = 0;
1124 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1125 max_kernel_ns = vcpu->last_guest_tsc -
1126 vcpu->hv_clock.tsc_timestamp;
1127 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1128 vcpu->hv_clock.tsc_to_system_mul,
1129 vcpu->hv_clock.tsc_shift);
1130 max_kernel_ns += vcpu->last_kernel_ns;
1131 }
afbcf7ab 1132
e48672fa 1133 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1134 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1135 &vcpu->hv_clock.tsc_shift,
1136 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1137 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1138 }
1139
1d5f066e
ZA		 1140 if (max_kernel_ns > kernel_ns)
1141 kernel_ns = max_kernel_ns;
1142
8cfdc000 1143 /* With all the info we got, fill in the values */
1d5f066e 1144 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1145 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1146 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1147 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1148 vcpu->hv_clock.flags = 0;
1149
18068523
GOC		 1150 /*
1151 * The interface expects us to write an even number signaling that the
1152 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1153 * state, we just increase by 2 at the end.
18068523 1154 */
50d0a0f9 1155 vcpu->hv_clock.version += 2;
18068523
GOC		 1156
1157 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1158
1159 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1160 sizeof(vcpu->hv_clock));
18068523
GOC		 1161
1162 kunmap_atomic(shared_kaddr, KM_USER0);
1163
1164 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1165 return 0;
c8076604
GH		 1166}
1167
9ba075a6
AK		 1168static bool msr_mtrr_valid(unsigned msr)
1169{
1170 switch (msr) {
1171 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1172 case MSR_MTRRfix64K_00000:
1173 case MSR_MTRRfix16K_80000:
1174 case MSR_MTRRfix16K_A0000:
1175 case MSR_MTRRfix4K_C0000:
1176 case MSR_MTRRfix4K_C8000:
1177 case MSR_MTRRfix4K_D0000:
1178 case MSR_MTRRfix4K_D8000:
1179 case MSR_MTRRfix4K_E0000:
1180 case MSR_MTRRfix4K_E8000:
1181 case MSR_MTRRfix4K_F0000:
1182 case MSR_MTRRfix4K_F8000:
1183 case MSR_MTRRdefType:
1184 case MSR_IA32_CR_PAT:
1185 return true;
1186 case 0x2f8:
1187 return true;
1188 }
1189 return false;
1190}
1191
d6289b93
MT		 1192static bool valid_pat_type(unsigned t)
1193{
1194 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1195}
1196
1197static bool valid_mtrr_type(unsigned t)
1198{
1199 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1200}
1201
1202static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1203{
1204 int i;
1205
1206 if (!msr_mtrr_valid(msr))
1207 return false;
1208
1209 if (msr == MSR_IA32_CR_PAT) {
1210 for (i = 0; i < 8; i++)
1211 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1212 return false;
1213 return true;
1214 } else if (msr == MSR_MTRRdefType) {
1215 if (data & ~0xcff)
1216 return false;
1217 return valid_mtrr_type(data & 0xff);
1218 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1219 for (i = 0; i < 8 ; i++)
1220 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1221 return false;
1222 return true;
1223 }
1224
1225 /* variable MTRRs */
1226 return valid_mtrr_type(data & 0xff);
1227}
1228
9ba075a6
AK		 1229static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1230{
0bed3b56
SY		 1231 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1232
d6289b93 1233 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1234 return 1;
1235
0bed3b56
SY		 1236 if (msr == MSR_MTRRdefType) {
1237 vcpu->arch.mtrr_state.def_type = data;
1238 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1239 } else if (msr == MSR_MTRRfix64K_00000)
1240 p[0] = data;
1241 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1242 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1243 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1244 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1245 else if (msr == MSR_IA32_CR_PAT)
1246 vcpu->arch.pat = data;
1247 else { /* Variable MTRRs */
1248 int idx, is_mtrr_mask;
1249 u64 *pt;
1250
1251 idx = (msr - 0x200) / 2;
1252 is_mtrr_mask = msr - 0x200 - 2 * idx;
1253 if (!is_mtrr_mask)
1254 pt =
1255 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1256 else
1257 pt =
1258 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1259 *pt = data;
1260 }
1261
1262 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1263 return 0;
1264}
15c4a640 1265
890ca9ae 1266static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1267{
890ca9ae
HY		 1268 u64 mcg_cap = vcpu->arch.mcg_cap;
1269 unsigned bank_num = mcg_cap & 0xff;
1270
15c4a640 1271 switch (msr) {
15c4a640 1272 case MSR_IA32_MCG_STATUS:
890ca9ae 1273 vcpu->arch.mcg_status = data;
15c4a640 1274 break;
c7ac679c 1275 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1276 if (!(mcg_cap & MCG_CTL_P))
1277 return 1;
1278 if (data != 0 && data != ~(u64)0)
1279 return -1;
1280 vcpu->arch.mcg_ctl = data;
1281 break;
1282 default:
1283 if (msr >= MSR_IA32_MC0_CTL &&
1284 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1285 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1286 /* only 0 or all 1s can be written to IA32_MCi_CTL
1287 * some Linux kernels though clear bit 10 in bank 4 to
1288 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1289 * this to avoid an uncatched #GP in the guest
1290 */
890ca9ae 1291 if ((offset & 0x3) == 0 &&
114be429 1292 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1293 return -1;
1294 vcpu->arch.mce_banks[offset] = data;
1295 break;
1296 }
1297 return 1;
1298 }
1299 return 0;
1300}
1301
ffde22ac
ES		 1302static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1303{
1304 struct kvm *kvm = vcpu->kvm;
1305 int lm = is_long_mode(vcpu);
1306 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1307 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1308 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1309 : kvm->arch.xen_hvm_config.blob_size_32;
1310 u32 page_num = data & ~PAGE_MASK;
1311 u64 page_addr = data & PAGE_MASK;
1312 u8 *page;
1313 int r;
1314
1315 r = -E2BIG;
1316 if (page_num >= blob_size)
1317 goto out;
1318 r = -ENOMEM;
1319 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1320 if (!page)
1321 goto out;
1322 r = -EFAULT;
1323 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1324 goto out_free;
1325 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1326 goto out_free;
1327 r = 0;
1328out_free:
1329 kfree(page);
1330out:
1331 return r;
1332}
1333
55cd8e5a
GN		 1334static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1335{
1336 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1337}
1338
1339static bool kvm_hv_msr_partition_wide(u32 msr)
1340{
1341 bool r = false;
1342 switch (msr) {
1343 case HV_X64_MSR_GUEST_OS_ID:
1344 case HV_X64_MSR_HYPERCALL:
1345 r = true;
1346 break;
1347 }
1348
1349 return r;
1350}
1351
1352static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1353{
1354 struct kvm *kvm = vcpu->kvm;
1355
1356 switch (msr) {
1357 case HV_X64_MSR_GUEST_OS_ID:
1358 kvm->arch.hv_guest_os_id = data;
1359 /* setting guest os id to zero disables hypercall page */
1360 if (!kvm->arch.hv_guest_os_id)
1361 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1362 break;
1363 case HV_X64_MSR_HYPERCALL: {
1364 u64 gfn;
1365 unsigned long addr;
1366 u8 instructions[4];
1367
1368 /* if guest os id is not set hypercall should remain disabled */
1369 if (!kvm->arch.hv_guest_os_id)
1370 break;
1371 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1372 kvm->arch.hv_hypercall = data;
1373 break;
1374 }
1375 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1376 addr = gfn_to_hva(kvm, gfn);
1377 if (kvm_is_error_hva(addr))
1378 return 1;
1379 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1380 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1381 if (copy_to_user((void __user *)addr, instructions, 4))
1382 return 1;
1383 kvm->arch.hv_hypercall = data;
1384 break;
1385 }
1386 default:
1387 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1388 "data 0x%llx\n", msr, data);
1389 return 1;
1390 }
1391 return 0;
1392}
1393
1394static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1395{
10388a07
GN		 1396 switch (msr) {
1397 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1398 unsigned long addr;
55cd8e5a 1399
10388a07
GN		 1400 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1401 vcpu->arch.hv_vapic = data;
1402 break;
1403 }
1404 addr = gfn_to_hva(vcpu->kvm, data >>
1405 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1406 if (kvm_is_error_hva(addr))
1407 return 1;
1408 if (clear_user((void __user *)addr, PAGE_SIZE))
1409 return 1;
1410 vcpu->arch.hv_vapic = data;
1411 break;
1412 }
1413 case HV_X64_MSR_EOI:
1414 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1415 case HV_X64_MSR_ICR:
1416 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1417 case HV_X64_MSR_TPR:
1418 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1419 default:
1420 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1421 "data 0x%llx\n", msr, data);
1422 return 1;
1423 }
1424
1425 return 0;
55cd8e5a
GN		 1426}
1427
344d9588
GN		 1428static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1429{
1430 gpa_t gpa = data & ~0x3f;
1431
6adba527
GN		 1432 /* Bits 2:5 are resrved, Should be zero */
1433 if (data & 0x3c)
344d9588
GN		 1434 return 1;
1435
1436 vcpu->arch.apf.msr_val = data;
1437
1438 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1439 kvm_clear_async_pf_completion_queue(vcpu);
1440 kvm_async_pf_hash_reset(vcpu);
1441 return 0;
1442 }
1443
1444 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1445 return 1;
1446
6adba527 1447 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1448 kvm_async_pf_wakeup_all(vcpu);
1449 return 0;
1450}
1451
12f9a48f
GC		 1452static void kvmclock_reset(struct kvm_vcpu *vcpu)
1453{
1454 if (vcpu->arch.time_page) {
1455 kvm_release_page_dirty(vcpu->arch.time_page);
1456 vcpu->arch.time_page = NULL;
1457 }
1458}
1459
15c4a640
CO		 1460int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1461{
1462 switch (msr) {
15c4a640 1463 case MSR_EFER:
b69e8cae 1464 return set_efer(vcpu, data);
8f1589d9
AP		 1465 case MSR_K7_HWCR:
1466 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1467 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1468 if (data != 0) {
1469 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1470 data);
1471 return 1;
1472 }
15c4a640 1473 break;
f7c6d140
AP		 1474 case MSR_FAM10H_MMIO_CONF_BASE:
1475 if (data != 0) {
1476 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1477 "0x%llx\n", data);
1478 return 1;
1479 }
15c4a640 1480 break;
c323c0e5 1481 case MSR_AMD64_NB_CFG:
c7ac679c 1482 break;
b5e2fec0
AG		 1483 case MSR_IA32_DEBUGCTLMSR:
1484 if (!data) {
1485 /* We support the non-activated case already */
1486 break;
1487 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1488 /* Values other than LBR and BTF are vendor-specific,
1489 thus reserved and should throw a #GP */
1490 return 1;
1491 }
1492 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1493 __func__, data);
1494 break;
15c4a640
CO		 1495 case MSR_IA32_UCODE_REV:
1496 case MSR_IA32_UCODE_WRITE:
61a6bd67 1497 case MSR_VM_HSAVE_PA:
6098ca93 1498 case MSR_AMD64_PATCH_LOADER:
15c4a640 1499 break;
9ba075a6
AK		 1500 case 0x200 ... 0x2ff:
1501 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1502 case MSR_IA32_APICBASE:
1503 kvm_set_apic_base(vcpu, data);
1504 break;
0105d1a5
GN		 1505 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1506 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1507 case MSR_IA32_MISC_ENABLE:
ad312c7c 1508 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1509 break;
11c6bffa 1510 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1511 case MSR_KVM_WALL_CLOCK:
1512 vcpu->kvm->arch.wall_clock = data;
1513 kvm_write_wall_clock(vcpu->kvm, data);
1514 break;
11c6bffa 1515 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1516 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1517 kvmclock_reset(vcpu);
18068523
GOC		 1518
1519 vcpu->arch.time = data;
c285545f 1520 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1521
1522 /* we verify if the enable bit is set... */
1523 if (!(data & 1))
1524 break;
1525
1526 /* ...but clean it before doing the actual write */
1527 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1528
18068523
GOC		 1529 vcpu->arch.time_page =
1530 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1531
1532 if (is_error_page(vcpu->arch.time_page)) {
1533 kvm_release_page_clean(vcpu->arch.time_page);
1534 vcpu->arch.time_page = NULL;
1535 }
18068523
GOC		 1536 break;
1537 }
344d9588
GN		 1538 case MSR_KVM_ASYNC_PF_EN:
1539 if (kvm_pv_enable_async_pf(vcpu, data))
1540 return 1;
1541 break;
890ca9ae
HY		 1542 case MSR_IA32_MCG_CTL:
1543 case MSR_IA32_MCG_STATUS:
1544 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1545 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1546
1547 /* Performance counters are not protected by a CPUID bit,
1548 * so we should check all of them in the generic path for the sake of
1549 * cross vendor migration.
1550 * Writing a zero into the event select MSRs disables them,
1551 * which we perfectly emulate ;-). Any other value should be at least
1552 * reported, some guests depend on them.
1553 */
1554 case MSR_P6_EVNTSEL0:
1555 case MSR_P6_EVNTSEL1:
1556 case MSR_K7_EVNTSEL0:
1557 case MSR_K7_EVNTSEL1:
1558 case MSR_K7_EVNTSEL2:
1559 case MSR_K7_EVNTSEL3:
1560 if (data != 0)
1561 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1562 "0x%x data 0x%llx\n", msr, data);
1563 break;
1564 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1565 * so we ignore writes to make it happy.
1566 */
1567 case MSR_P6_PERFCTR0:
1568 case MSR_P6_PERFCTR1:
1569 case MSR_K7_PERFCTR0:
1570 case MSR_K7_PERFCTR1:
1571 case MSR_K7_PERFCTR2:
1572 case MSR_K7_PERFCTR3:
1573 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1574 "0x%x data 0x%llx\n", msr, data);
1575 break;
84e0cefa
JS		 1576 case MSR_K7_CLK_CTL:
1577 /*
1578 * Ignore all writes to this no longer documented MSR.
1579 * Writes are only relevant for old K7 processors,
1580 * all pre-dating SVM, but a recommended workaround from
1581 * AMD for these chips. It is possible to speicify the
1582 * affected processor models on the command line, hence
1583 * the need to ignore the workaround.
1584 */
1585 break;
55cd8e5a
GN		 1586 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1587 if (kvm_hv_msr_partition_wide(msr)) {
1588 int r;
1589 mutex_lock(&vcpu->kvm->lock);
1590 r = set_msr_hyperv_pw(vcpu, msr, data);
1591 mutex_unlock(&vcpu->kvm->lock);
1592 return r;
1593 } else
1594 return set_msr_hyperv(vcpu, msr, data);
1595 break;
91c9c3ed 1596 case MSR_IA32_BBL_CR_CTL3:
1597 /* Drop writes to this legacy MSR -- see rdmsr
1598 * counterpart for further detail.
1599 */
1600 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1601 break;
15c4a640 1602 default:
ffde22ac
ES		 1603 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1604 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1605 if (!ignore_msrs) {
1606 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1607 msr, data);
1608 return 1;
1609 } else {
1610 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1611 msr, data);
1612 break;
1613 }
15c4a640
CO		 1614 }
1615 return 0;
1616}
1617EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1618
1619
1620/*
1621 * Reads an msr value (of 'msr_index') into 'pdata'.
1622 * Returns 0 on success, non-0 otherwise.
1623 * Assumes vcpu_load() was already called.
1624 */
1625int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1626{
1627 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1628}
1629
9ba075a6
AK		 1630static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1631{
0bed3b56
SY		 1632 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1633
9ba075a6
AK		 1634 if (!msr_mtrr_valid(msr))
1635 return 1;
1636
0bed3b56
SY		 1637 if (msr == MSR_MTRRdefType)
1638 *pdata = vcpu->arch.mtrr_state.def_type +
1639 (vcpu->arch.mtrr_state.enabled << 10);
1640 else if (msr == MSR_MTRRfix64K_00000)
1641 *pdata = p[0];
1642 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1643 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1644 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1645 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1646 else if (msr == MSR_IA32_CR_PAT)
1647 *pdata = vcpu->arch.pat;
1648 else { /* Variable MTRRs */
1649 int idx, is_mtrr_mask;
1650 u64 *pt;
1651
1652 idx = (msr - 0x200) / 2;
1653 is_mtrr_mask = msr - 0x200 - 2 * idx;
1654 if (!is_mtrr_mask)
1655 pt =
1656 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1657 else
1658 pt =
1659 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1660 *pdata = *pt;
1661 }
1662
9ba075a6
AK		 1663 return 0;
1664}
1665
890ca9ae 1666static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1667{
1668 u64 data;
890ca9ae
HY		 1669 u64 mcg_cap = vcpu->arch.mcg_cap;
1670 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1671
1672 switch (msr) {
15c4a640
CO		 1673 case MSR_IA32_P5_MC_ADDR:
1674 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1675 data = 0;
1676 break;
15c4a640 1677 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1678 data = vcpu->arch.mcg_cap;
1679 break;
c7ac679c 1680 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1681 if (!(mcg_cap & MCG_CTL_P))
1682 return 1;
1683 data = vcpu->arch.mcg_ctl;
1684 break;
1685 case MSR_IA32_MCG_STATUS:
1686 data = vcpu->arch.mcg_status;
1687 break;
1688 default:
1689 if (msr >= MSR_IA32_MC0_CTL &&
1690 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1691 u32 offset = msr - MSR_IA32_MC0_CTL;
1692 data = vcpu->arch.mce_banks[offset];
1693 break;
1694 }
1695 return 1;
1696 }
1697 *pdata = data;
1698 return 0;
1699}
1700
55cd8e5a
GN		 1701static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1702{
1703 u64 data = 0;
1704 struct kvm *kvm = vcpu->kvm;
1705
1706 switch (msr) {
1707 case HV_X64_MSR_GUEST_OS_ID:
1708 data = kvm->arch.hv_guest_os_id;
1709 break;
1710 case HV_X64_MSR_HYPERCALL:
1711 data = kvm->arch.hv_hypercall;
1712 break;
1713 default:
1714 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1715 return 1;
1716 }
1717
1718 *pdata = data;
1719 return 0;
1720}
1721
1722static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1723{
1724 u64 data = 0;
1725
1726 switch (msr) {
1727 case HV_X64_MSR_VP_INDEX: {
1728 int r;
1729 struct kvm_vcpu *v;
1730 kvm_for_each_vcpu(r, v, vcpu->kvm)
1731 if (v == vcpu)
1732 data = r;
1733 break;
1734 }
10388a07
GN		 1735 case HV_X64_MSR_EOI:
1736 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1737 case HV_X64_MSR_ICR:
1738 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1739 case HV_X64_MSR_TPR:
1740 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1741 default:
1742 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1743 return 1;
1744 }
1745 *pdata = data;
1746 return 0;
1747}
1748
890ca9ae
HY		 1749int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1750{
1751 u64 data;
1752
1753 switch (msr) {
890ca9ae 1754 case MSR_IA32_PLATFORM_ID:
15c4a640 1755 case MSR_IA32_UCODE_REV:
15c4a640 1756 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1757 case MSR_IA32_DEBUGCTLMSR:
1758 case MSR_IA32_LASTBRANCHFROMIP:
1759 case MSR_IA32_LASTBRANCHTOIP:
1760 case MSR_IA32_LASTINTFROMIP:
1761 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1762 case MSR_K8_SYSCFG:
1763 case MSR_K7_HWCR:
61a6bd67 1764 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1765 case MSR_P6_PERFCTR0:
1766 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1767 case MSR_P6_EVNTSEL0:
1768 case MSR_P6_EVNTSEL1:
9e699624 1769 case MSR_K7_EVNTSEL0:
1f3ee616 1770 case MSR_K7_PERFCTR0:
1fdbd48c 1771 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1772 case MSR_AMD64_NB_CFG:
f7c6d140 1773 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1774 data = 0;
1775 break;
9ba075a6
AK		 1776 case MSR_MTRRcap:
1777 data = 0x500 | KVM_NR_VAR_MTRR;
1778 break;
1779 case 0x200 ... 0x2ff:
1780 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1781 case 0xcd: /* fsb frequency */
1782 data = 3;
1783 break;
7b914098
JS		 1784 /*
1785 * MSR_EBC_FREQUENCY_ID
1786 * Conservative value valid for even the basic CPU models.
1787 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1788 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1789 * and 266MHz for model 3, or 4. Set Core Clock
1790 * Frequency to System Bus Frequency Ratio to 1 (bits
1791 * 31:24) even though these are only valid for CPU
1792 * models > 2, however guests may end up dividing or
1793 * multiplying by zero otherwise.
1794 */
1795 case MSR_EBC_FREQUENCY_ID:
1796 data = 1 << 24;
1797 break;
15c4a640
CO		 1798 case MSR_IA32_APICBASE:
1799 data = kvm_get_apic_base(vcpu);
1800 break;
0105d1a5
GN		 1801 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1802 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1803 break;
15c4a640 1804 case MSR_IA32_MISC_ENABLE:
ad312c7c 1805 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1806 break;
847f0ad8
AG		 1807 case MSR_IA32_PERF_STATUS:
1808 /* TSC increment by tick */
1809 data = 1000ULL;
1810 /* CPU multiplier */
1811 data |= (((uint64_t)4ULL) << 40);
1812 break;
15c4a640 1813 case MSR_EFER:
f6801dff 1814 data = vcpu->arch.efer;
15c4a640 1815 break;
18068523 1816 case MSR_KVM_WALL_CLOCK:
11c6bffa 1817 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1818 data = vcpu->kvm->arch.wall_clock;
1819 break;
1820 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1821 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1822 data = vcpu->arch.time;
1823 break;
344d9588
GN		 1824 case MSR_KVM_ASYNC_PF_EN:
1825 data = vcpu->arch.apf.msr_val;
1826 break;
890ca9ae
HY		 1827 case MSR_IA32_P5_MC_ADDR:
1828 case MSR_IA32_P5_MC_TYPE:
1829 case MSR_IA32_MCG_CAP:
1830 case MSR_IA32_MCG_CTL:
1831 case MSR_IA32_MCG_STATUS:
1832 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1833 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1834 case MSR_K7_CLK_CTL:
1835 /*
1836 * Provide expected ramp-up count for K7. All other
1837 * are set to zero, indicating minimum divisors for
1838 * every field.
1839 *
1840 * This prevents guest kernels on AMD host with CPU
1841 * type 6, model 8 and higher from exploding due to
1842 * the rdmsr failing.
1843 */
1844 data = 0x20000000;
1845 break;
55cd8e5a
GN		 1846 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1847 if (kvm_hv_msr_partition_wide(msr)) {
1848 int r;
1849 mutex_lock(&vcpu->kvm->lock);
1850 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1851 mutex_unlock(&vcpu->kvm->lock);
1852 return r;
1853 } else
1854 return get_msr_hyperv(vcpu, msr, pdata);
1855 break;
91c9c3ed 1856 case MSR_IA32_BBL_CR_CTL3:
1857 /* This legacy MSR exists but isn't fully documented in current
1858 * silicon. It is however accessed by winxp in very narrow
1859 * scenarios where it sets bit #19, itself documented as
1860 * a "reserved" bit. Best effort attempt to source coherent
1861 * read data here should the balance of the register be
1862 * interpreted by the guest:
1863 *
1864 * L2 cache control register 3: 64GB range, 256KB size,
1865 * enabled, latency 0x1, configured
1866 */
1867 data = 0xbe702111;
1868 break;
15c4a640 1869 default:
ed85c068
AP		 1870 if (!ignore_msrs) {
1871 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1872 return 1;
1873 } else {
1874 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1875 data = 0;
1876 }
1877 break;
15c4a640
CO		 1878 }
1879 *pdata = data;
1880 return 0;
1881}
1882EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1883
313a3dc7
CO		 1884/*
1885 * Read or write a bunch of msrs. All parameters are kernel addresses.
1886 *
1887 * @return number of msrs set successfully.
1888 */
1889static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1890 struct kvm_msr_entry *entries,
1891 int (*do_msr)(struct kvm_vcpu *vcpu,
1892 unsigned index, u64 *data))
1893{
f656ce01 1894 int i, idx;
313a3dc7 1895
f656ce01 1896 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1897 for (i = 0; i < msrs->nmsrs; ++i)
1898 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1899 break;
f656ce01 1900 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1901
313a3dc7
CO		 1902 return i;
1903}
1904
1905/*
1906 * Read or write a bunch of msrs. Parameters are user addresses.
1907 *
1908 * @return number of msrs set successfully.
1909 */
1910static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1911 int (*do_msr)(struct kvm_vcpu *vcpu,
1912 unsigned index, u64 *data),
1913 int writeback)
1914{
1915 struct kvm_msrs msrs;
1916 struct kvm_msr_entry *entries;
1917 int r, n;
1918 unsigned size;
1919
1920 r = -EFAULT;
1921 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1922 goto out;
1923
1924 r = -E2BIG;
1925 if (msrs.nmsrs >= MAX_IO_MSRS)
1926 goto out;
1927
1928 r = -ENOMEM;
1929 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1930 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1931 if (!entries)
1932 goto out;
1933
1934 r = -EFAULT;
1935 if (copy_from_user(entries, user_msrs->entries, size))
1936 goto out_free;
1937
1938 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1939 if (r < 0)
1940 goto out_free;
1941
1942 r = -EFAULT;
1943 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1944 goto out_free;
1945
1946 r = n;
1947
1948out_free:
7a73c028 1949 kfree(entries);
313a3dc7
CO		 1950out:
1951 return r;
1952}
1953
018d00d2
ZX		 1954int kvm_dev_ioctl_check_extension(long ext)
1955{
1956 int r;
1957
1958 switch (ext) {
1959 case KVM_CAP_IRQCHIP:
1960 case KVM_CAP_HLT:
1961 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1962 case KVM_CAP_SET_TSS_ADDR:
07716717 1963 case KVM_CAP_EXT_CPUID:
c8076604 1964 case KVM_CAP_CLOCKSOURCE:
7837699f 1965 case KVM_CAP_PIT:
a28e4f5a 1966 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1967 case KVM_CAP_MP_STATE:
ed848624 1968 case KVM_CAP_SYNC_MMU:
a355c85c 1969 case KVM_CAP_USER_NMI:
52d939a0 1970 case KVM_CAP_REINJECT_CONTROL:
4925663a 1971 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1972 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1973 case KVM_CAP_IRQFD:
d34e6b17 1974 case KVM_CAP_IOEVENTFD:
c5ff41ce 1975 case KVM_CAP_PIT2:
e9f42757 1976 case KVM_CAP_PIT_STATE2:
b927a3ce 1977 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1978 case KVM_CAP_XEN_HVM:
afbcf7ab 1979 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1980 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1981 case KVM_CAP_HYPERV:
10388a07 1982 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1983 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1984 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1985 case KVM_CAP_DEBUGREGS:
d2be1651 1986 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1987 case KVM_CAP_XSAVE:
344d9588 1988 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1989 r = 1;
1990 break;
542472b5
LV		 1991 case KVM_CAP_COALESCED_MMIO:
1992 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1993 break;
774ead3a
AK		 1994 case KVM_CAP_VAPIC:
1995 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1996 break;
f725230a
AK		 1997 case KVM_CAP_NR_VCPUS:
1998 r = KVM_MAX_VCPUS;
1999 break;
a988b910
AK		 2000 case KVM_CAP_NR_MEMSLOTS:
2001 r = KVM_MEMORY_SLOTS;
2002 break;
a68a6a72
MT		 2003 case KVM_CAP_PV_MMU: /* obsolete */
2004 r = 0;
2f333bcb 2005 break;
62c476c7 2006 case KVM_CAP_IOMMU:
19de40a8 2007 r = iommu_found();
62c476c7 2008 break;
890ca9ae
HY		 2009 case KVM_CAP_MCE:
2010 r = KVM_MAX_MCE_BANKS;
2011 break;
2d5b5a66
SY		 2012 case KVM_CAP_XCRS:
2013 r = cpu_has_xsave;
2014 break;
018d00d2
ZX		 2015 default:
2016 r = 0;
2017 break;
2018 }
2019 return r;
2020
2021}
2022
043405e1
CO		 2023long kvm_arch_dev_ioctl(struct file *filp,
2024 unsigned int ioctl, unsigned long arg)
2025{
2026 void __user *argp = (void __user *)arg;
2027 long r;
2028
2029 switch (ioctl) {
2030 case KVM_GET_MSR_INDEX_LIST: {
2031 struct kvm_msr_list __user *user_msr_list = argp;
2032 struct kvm_msr_list msr_list;
2033 unsigned n;
2034
2035 r = -EFAULT;
2036 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2037 goto out;
2038 n = msr_list.nmsrs;
2039 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2040 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2041 goto out;
2042 r = -E2BIG;
e125e7b6 2043 if (n < msr_list.nmsrs)
043405e1
CO		 2044 goto out;
2045 r = -EFAULT;
2046 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2047 num_msrs_to_save * sizeof(u32)))
2048 goto out;
e125e7b6 2049 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2050 &emulated_msrs,
2051 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2052 goto out;
2053 r = 0;
2054 break;
2055 }
674eea0f
AK		 2056 case KVM_GET_SUPPORTED_CPUID: {
2057 struct kvm_cpuid2 __user *cpuid_arg = argp;
2058 struct kvm_cpuid2 cpuid;
2059
2060 r = -EFAULT;
2061 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2062 goto out;
2063 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2064 cpuid_arg->entries);
674eea0f
AK		 2065 if (r)
2066 goto out;
2067
2068 r = -EFAULT;
2069 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2070 goto out;
2071 r = 0;
2072 break;
2073 }
890ca9ae
HY		 2074 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2075 u64 mce_cap;
2076
2077 mce_cap = KVM_MCE_CAP_SUPPORTED;
2078 r = -EFAULT;
2079 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2080 goto out;
2081 r = 0;
2082 break;
2083 }
043405e1
CO		 2084 default:
2085 r = -EINVAL;
2086 }
2087out:
2088 return r;
2089}
2090
f5f48ee1
SY		 2091static void wbinvd_ipi(void *garbage)
2092{
2093 wbinvd();
2094}
2095
2096static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2097{
2098 return vcpu->kvm->arch.iommu_domain &&
2099 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2100}
2101
313a3dc7
CO		 2102void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2103{
f5f48ee1
SY		 2104 /* Address WBINVD may be executed by guest */
2105 if (need_emulate_wbinvd(vcpu)) {
2106 if (kvm_x86_ops->has_wbinvd_exit())
2107 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2108 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2109 smp_call_function_single(vcpu->cpu,
2110 wbinvd_ipi, NULL, 1);
2111 }
2112
313a3dc7 2113 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2114 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2115 /* Make sure TSC doesn't go backwards */
2116 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2117 native_read_tsc() - vcpu->arch.last_host_tsc;
2118 if (tsc_delta < 0)
2119 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2120 if (check_tsc_unstable()) {
e48672fa 2121 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2122 vcpu->arch.tsc_catchup = 1;
c285545f 2123 }
1aa8ceef 2124 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2125 if (vcpu->cpu != cpu)
2126 kvm_migrate_timers(vcpu);
e48672fa 2127 vcpu->cpu = cpu;
6b7d7e76 2128 }
313a3dc7
CO		 2129}
2130
2131void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2132{
02daab21 2133 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2134 kvm_put_guest_fpu(vcpu);
e48672fa 2135 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2136}
2137
07716717 2138static int is_efer_nx(void)
313a3dc7 2139{
e286e86e 2140 unsigned long long efer = 0;
313a3dc7 2141
e286e86e 2142 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2143 return efer & EFER_NX;
2144}
2145
2146static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2147{
2148 int i;
2149 struct kvm_cpuid_entry2 *e, *entry;
2150
313a3dc7 2151 entry = NULL;
ad312c7c
ZX		 2152 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2153 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2154 if (e->function == 0x80000001) {
2155 entry = e;
2156 break;
2157 }
2158 }
07716717 2159 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2160 entry->edx &= ~(1 << 20);
2161 printk(KERN_INFO "kvm: guest NX capability removed\n");
2162 }
2163}
2164
07716717 2165/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2166static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2167 struct kvm_cpuid *cpuid,
2168 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2169{
2170 int r, i;
2171 struct kvm_cpuid_entry *cpuid_entries;
2172
2173 r = -E2BIG;
2174 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2175 goto out;
2176 r = -ENOMEM;
2177 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2178 if (!cpuid_entries)
2179 goto out;
2180 r = -EFAULT;
2181 if (copy_from_user(cpuid_entries, entries,
2182 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2183 goto out_free;
2184 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2185 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2186 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2187 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2188 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2189 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2190 vcpu->arch.cpuid_entries[i].index = 0;
2191 vcpu->arch.cpuid_entries[i].flags = 0;
2192 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2193 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2194 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2195 }
2196 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2197 cpuid_fix_nx_cap(vcpu);
2198 r = 0;
fc61b800 2199 kvm_apic_set_version(vcpu);
0e851880 2200 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2201 update_cpuid(vcpu);
07716717
DK		 2202
2203out_free:
2204 vfree(cpuid_entries);
2205out:
2206 return r;
2207}
2208
2209static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2210 struct kvm_cpuid2 *cpuid,
2211 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2212{
2213 int r;
2214
2215 r = -E2BIG;
2216 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2217 goto out;
2218 r = -EFAULT;
ad312c7c 2219 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2220 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2221 goto out;
ad312c7c 2222 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2223 kvm_apic_set_version(vcpu);
0e851880 2224 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2225 update_cpuid(vcpu);
313a3dc7
CO		 2226 return 0;
2227
2228out:
2229 return r;
2230}
2231
07716717 2232static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2233 struct kvm_cpuid2 *cpuid,
2234 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2235{
2236 int r;
2237
2238 r = -E2BIG;
ad312c7c 2239 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2240 goto out;
2241 r = -EFAULT;
ad312c7c 2242 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2243 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2244 goto out;
2245 return 0;
2246
2247out:
ad312c7c 2248 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2249 return r;
2250}
2251
945ee35e
AK		 2252static void cpuid_mask(u32 *word, int wordnum)
2253{
2254 *word &= boot_cpu_data.x86_capability[wordnum];
2255}
2256
07716717 2257static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2258 u32 index)
07716717
DK		 2259{
2260 entry->function = function;
2261 entry->index = index;
2262 cpuid_count(entry->function, entry->index,
19355475 2263 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2264 entry->flags = 0;
2265}
2266
7faa4ee1
AK		 2267#define F(x) bit(X86_FEATURE_##x)
2268
07716717
DK		 2269static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2270 u32 index, int *nent, int maxnent)
2271{
7faa4ee1 2272 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2273#ifdef CONFIG_X86_64
17cc3935
SY		 2274 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2275 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2276 unsigned f_lm = F(LM);
2277#else
17cc3935 2278 unsigned f_gbpages = 0;
7faa4ee1 2279 unsigned f_lm = 0;
07716717 2280#endif
4e47c7a6 2281 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2282
2283 /* cpuid 1.edx */
2284 const u32 kvm_supported_word0_x86_features =
2285 F(FPU) | F(VME) | F(DE) | F(PSE) |
2286 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2287 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2288 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2289 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2290 0 /* Reserved, DS, ACPI */ | F(MMX) |
2291 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2292 0 /* HTT, TM, Reserved, PBE */;
2293 /* cpuid 0x80000001.edx */
2294 const u32 kvm_supported_word1_x86_features =
2295 F(FPU) | F(VME) | F(DE) | F(PSE) |
2296 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2297 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2298 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2299 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2300 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2301 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2302 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2303 /* cpuid 1.ecx */
2304 const u32 kvm_supported_word4_x86_features =
6c3f6041 2305 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2306 0 /* DS-CPL, VMX, SMX, EST */ |
2307 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2308 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2309 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2310 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2311 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2312 F(F16C);
7faa4ee1 2313 /* cpuid 0x80000001.ecx */
07716717 2314 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2315 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2316 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2317 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2318 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2319
19355475 2320 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2321 get_cpu();
2322 do_cpuid_1_ent(entry, function, index);
2323 ++*nent;
2324
2325 switch (function) {
2326 case 0:
2acf923e 2327 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2328 break;
2329 case 1:
2330 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2331 cpuid_mask(&entry->edx, 0);
7faa4ee1 2332 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2333 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2334 /* we support x2apic emulation even if host does not support
2335 * it since we emulate x2apic in software */
2336 entry->ecx |= F(X2APIC);
07716717
DK		 2337 break;
2338 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2339 * may return different values. This forces us to get_cpu() before
2340 * issuing the first command, and also to emulate this annoying behavior
2341 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2342 case 2: {
2343 int t, times = entry->eax & 0xff;
2344
2345 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2346 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2347 for (t = 1; t < times && *nent < maxnent; ++t) {
2348 do_cpuid_1_ent(&entry[t], function, 0);
2349 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2350 ++*nent;
2351 }
2352 break;
2353 }
2354 /* function 4 and 0xb have additional index. */
2355 case 4: {
14af3f3c 2356 int i, cache_type;
07716717
DK		 2357
2358 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2359 /* read more entries until cache_type is zero */
14af3f3c
HH		 2360 for (i = 1; *nent < maxnent; ++i) {
2361 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2362 if (!cache_type)
2363 break;
14af3f3c
HH		 2364 do_cpuid_1_ent(&entry[i], function, i);
2365 entry[i].flags |=
07716717
DK		 2366 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2367 ++*nent;
2368 }
2369 break;
2370 }
2371 case 0xb: {
14af3f3c 2372 int i, level_type;
07716717
DK		 2373
2374 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2375 /* read more entries until level_type is zero */
14af3f3c 2376 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2377 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2378 if (!level_type)
2379 break;
14af3f3c
HH		 2380 do_cpuid_1_ent(&entry[i], function, i);
2381 entry[i].flags |=
07716717
DK		 2382 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2383 ++*nent;
2384 }
2385 break;
2386 }
2acf923e
DC		 2387 case 0xd: {
2388 int i;
2389
2390 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9
AP		 2391 for (i = 1; *nent < maxnent && i < 64; ++i) {
2392 if (entry[i].eax == 0)
2393 continue;
2acf923e
DC		 2394 do_cpuid_1_ent(&entry[i], function, i);
2395 entry[i].flags |=
2396 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2397 ++*nent;
2398 }
2399 break;
2400 }
84478c82
GC		 2401 case KVM_CPUID_SIGNATURE: {
2402 char signature[12] = "KVMKVMKVM\0\0";
2403 u32 *sigptr = (u32 *)signature;
2404 entry->eax = 0;
2405 entry->ebx = sigptr[0];
2406 entry->ecx = sigptr[1];
2407 entry->edx = sigptr[2];
2408 break;
2409 }
2410 case KVM_CPUID_FEATURES:
2411 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2412 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2413 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2414 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2415 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2416 entry->ebx = 0;
2417 entry->ecx = 0;
2418 entry->edx = 0;
2419 break;
07716717
DK		 2420 case 0x80000000:
2421 entry->eax = min(entry->eax, 0x8000001a);
2422 break;
2423 case 0x80000001:
2424 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2425 cpuid_mask(&entry->edx, 1);
07716717 2426 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2427 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2428 break;
2429 }
d4330ef2
JR		 2430
2431 kvm_x86_ops->set_supported_cpuid(function, entry);
2432
07716717
DK		 2433 put_cpu();
2434}
2435
7faa4ee1
AK		 2436#undef F
2437
674eea0f 2438static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2439 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2440{
2441 struct kvm_cpuid_entry2 *cpuid_entries;
2442 int limit, nent = 0, r = -E2BIG;
2443 u32 func;
2444
2445 if (cpuid->nent < 1)
2446 goto out;
6a544355
AK		 2447 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2448 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2449 r = -ENOMEM;
2450 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2451 if (!cpuid_entries)
2452 goto out;
2453
2454 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2455 limit = cpuid_entries[0].eax;
2456 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2457 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2458 &nent, cpuid->nent);
07716717
DK		 2459 r = -E2BIG;
2460 if (nent >= cpuid->nent)
2461 goto out_free;
2462
2463 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2464 limit = cpuid_entries[nent - 1].eax;
2465 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2466 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2467 &nent, cpuid->nent);
84478c82
GC		 2468
2469
2470
2471 r = -E2BIG;
2472 if (nent >= cpuid->nent)
2473 goto out_free;
2474
2475 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2476 cpuid->nent);
2477
2478 r = -E2BIG;
2479 if (nent >= cpuid->nent)
2480 goto out_free;
2481
2482 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2483 cpuid->nent);
2484
cb007648
MM		 2485 r = -E2BIG;
2486 if (nent >= cpuid->nent)
2487 goto out_free;
2488
07716717
DK		 2489 r = -EFAULT;
2490 if (copy_to_user(entries, cpuid_entries,
19355475 2491 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2492 goto out_free;
2493 cpuid->nent = nent;
2494 r = 0;
2495
2496out_free:
2497 vfree(cpuid_entries);
2498out:
2499 return r;
2500}
2501
313a3dc7
CO		 2502static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2503 struct kvm_lapic_state *s)
2504{
ad312c7c 2505 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2506
2507 return 0;
2508}
2509
2510static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2511 struct kvm_lapic_state *s)
2512{
ad312c7c 2513 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2514 kvm_apic_post_state_restore(vcpu);
cb142eb7 2515 update_cr8_intercept(vcpu);
313a3dc7
CO		 2516
2517 return 0;
2518}
2519
f77bc6a4
ZX		 2520static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2521 struct kvm_interrupt *irq)
2522{
2523 if (irq->irq < 0 || irq->irq >= 256)
2524 return -EINVAL;
2525 if (irqchip_in_kernel(vcpu->kvm))
2526 return -ENXIO;
f77bc6a4 2527
66fd3f7f 2528 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2529 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2530
f77bc6a4
ZX		 2531 return 0;
2532}
2533
c4abb7c9
JK		 2534static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2535{
c4abb7c9 2536 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2537
2538 return 0;
2539}
2540
b209749f
AK		 2541static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2542 struct kvm_tpr_access_ctl *tac)
2543{
2544 if (tac->flags)
2545 return -EINVAL;
2546 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2547 return 0;
2548}
2549
890ca9ae
HY		 2550static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2551 u64 mcg_cap)
2552{
2553 int r;
2554 unsigned bank_num = mcg_cap & 0xff, bank;
2555
2556 r = -EINVAL;
a9e38c3e 2557 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2558 goto out;
2559 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2560 goto out;
2561 r = 0;
2562 vcpu->arch.mcg_cap = mcg_cap;
2563 /* Init IA32_MCG_CTL to all 1s */
2564 if (mcg_cap & MCG_CTL_P)
2565 vcpu->arch.mcg_ctl = ~(u64)0;
2566 /* Init IA32_MCi_CTL to all 1s */
2567 for (bank = 0; bank < bank_num; bank++)
2568 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2569out:
2570 return r;
2571}
2572
2573static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2574 struct kvm_x86_mce *mce)
2575{
2576 u64 mcg_cap = vcpu->arch.mcg_cap;
2577 unsigned bank_num = mcg_cap & 0xff;
2578 u64 *banks = vcpu->arch.mce_banks;
2579
2580 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2581 return -EINVAL;
2582 /*
2583 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2584 * reporting is disabled
2585 */
2586 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2587 vcpu->arch.mcg_ctl != ~(u64)0)
2588 return 0;
2589 banks += 4 * mce->bank;
2590 /*
2591 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2592 * reporting is disabled for the bank
2593 */
2594 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2595 return 0;
2596 if (mce->status & MCI_STATUS_UC) {
2597 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2598 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2599 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2600 return 0;
2601 }
2602 if (banks[1] & MCI_STATUS_VAL)
2603 mce->status |= MCI_STATUS_OVER;
2604 banks[2] = mce->addr;
2605 banks[3] = mce->misc;
2606 vcpu->arch.mcg_status = mce->mcg_status;
2607 banks[1] = mce->status;
2608 kvm_queue_exception(vcpu, MC_VECTOR);
2609 } else if (!(banks[1] & MCI_STATUS_VAL)
2610 || !(banks[1] & MCI_STATUS_UC)) {
2611 if (banks[1] & MCI_STATUS_VAL)
2612 mce->status |= MCI_STATUS_OVER;
2613 banks[2] = mce->addr;
2614 banks[3] = mce->misc;
2615 banks[1] = mce->status;
2616 } else
2617 banks[1] |= MCI_STATUS_OVER;
2618 return 0;
2619}
2620
3cfc3092
JK		 2621static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2622 struct kvm_vcpu_events *events)
2623{
03b82a30
JK		 2624 events->exception.injected =
2625 vcpu->arch.exception.pending &&
2626 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2627 events->exception.nr = vcpu->arch.exception.nr;
2628 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2629 events->exception.pad = 0;
3cfc3092
JK		 2630 events->exception.error_code = vcpu->arch.exception.error_code;
2631
03b82a30
JK		 2632 events->interrupt.injected =
2633 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2634 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2635 events->interrupt.soft = 0;
48005f64
JK		 2636 events->interrupt.shadow =
2637 kvm_x86_ops->get_interrupt_shadow(vcpu,
2638 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2639
2640 events->nmi.injected = vcpu->arch.nmi_injected;
2641 events->nmi.pending = vcpu->arch.nmi_pending;
2642 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2643 events->nmi.pad = 0;
3cfc3092
JK		 2644
2645 events->sipi_vector = vcpu->arch.sipi_vector;
2646
dab4b911 2647 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2648 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2649 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2650 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2651}
2652
2653static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2654 struct kvm_vcpu_events *events)
2655{
dab4b911 2656 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2657 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2658 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2659 return -EINVAL;
2660
3cfc3092
JK		 2661 vcpu->arch.exception.pending = events->exception.injected;
2662 vcpu->arch.exception.nr = events->exception.nr;
2663 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2664 vcpu->arch.exception.error_code = events->exception.error_code;
2665
2666 vcpu->arch.interrupt.pending = events->interrupt.injected;
2667 vcpu->arch.interrupt.nr = events->interrupt.nr;
2668 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2669 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2670 kvm_x86_ops->set_interrupt_shadow(vcpu,
2671 events->interrupt.shadow);
3cfc3092
JK		 2672
2673 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2674 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2675 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2676 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2677
dab4b911
JK		 2678 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2679 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2680
3842d135
AK		 2681 kvm_make_request(KVM_REQ_EVENT, vcpu);
2682
3cfc3092
JK		 2683 return 0;
2684}
2685
a1efbe77
JK		 2686static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2687 struct kvm_debugregs *dbgregs)
2688{
a1efbe77
JK		 2689 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2690 dbgregs->dr6 = vcpu->arch.dr6;
2691 dbgregs->dr7 = vcpu->arch.dr7;
2692 dbgregs->flags = 0;
97e69aa6 2693 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2694}
2695
2696static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2697 struct kvm_debugregs *dbgregs)
2698{
2699 if (dbgregs->flags)
2700 return -EINVAL;
2701
a1efbe77
JK		 2702 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2703 vcpu->arch.dr6 = dbgregs->dr6;
2704 vcpu->arch.dr7 = dbgregs->dr7;
2705
a1efbe77
JK		 2706 return 0;
2707}
2708
2d5b5a66
SY		 2709static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2710 struct kvm_xsave *guest_xsave)
2711{
2712 if (cpu_has_xsave)
2713 memcpy(guest_xsave->region,
2714 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2715 xstate_size);
2d5b5a66
SY		 2716 else {
2717 memcpy(guest_xsave->region,
2718 &vcpu->arch.guest_fpu.state->fxsave,
2719 sizeof(struct i387_fxsave_struct));
2720 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2721 XSTATE_FPSSE;
2722 }
2723}
2724
2725static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2726 struct kvm_xsave *guest_xsave)
2727{
2728 u64 xstate_bv =
2729 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2730
2731 if (cpu_has_xsave)
2732 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2733 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2734 else {
2735 if (xstate_bv & ~XSTATE_FPSSE)
2736 return -EINVAL;
2737 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2738 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2739 }
2740 return 0;
2741}
2742
2743static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2744 struct kvm_xcrs *guest_xcrs)
2745{
2746 if (!cpu_has_xsave) {
2747 guest_xcrs->nr_xcrs = 0;
2748 return;
2749 }
2750
2751 guest_xcrs->nr_xcrs = 1;
2752 guest_xcrs->flags = 0;
2753 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2754 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2755}
2756
2757static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2758 struct kvm_xcrs *guest_xcrs)
2759{
2760 int i, r = 0;
2761
2762 if (!cpu_has_xsave)
2763 return -EINVAL;
2764
2765 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2766 return -EINVAL;
2767
2768 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2769 /* Only support XCR0 currently */
2770 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2771 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2772 guest_xcrs->xcrs[0].value);
2773 break;
2774 }
2775 if (r)
2776 r = -EINVAL;
2777 return r;
2778}
2779
313a3dc7
CO		 2780long kvm_arch_vcpu_ioctl(struct file *filp,
2781 unsigned int ioctl, unsigned long arg)
2782{
2783 struct kvm_vcpu *vcpu = filp->private_data;
2784 void __user *argp = (void __user *)arg;
2785 int r;
d1ac91d8
AK		 2786 union {
2787 struct kvm_lapic_state *lapic;
2788 struct kvm_xsave *xsave;
2789 struct kvm_xcrs *xcrs;
2790 void *buffer;
2791 } u;
2792
2793 u.buffer = NULL;
313a3dc7
CO		 2794 switch (ioctl) {
2795 case KVM_GET_LAPIC: {
2204ae3c
MT		 2796 r = -EINVAL;
2797 if (!vcpu->arch.apic)
2798 goto out;
d1ac91d8 2799 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2800
b772ff36 2801 r = -ENOMEM;
d1ac91d8 2802 if (!u.lapic)
b772ff36 2803 goto out;
d1ac91d8 2804 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2805 if (r)
2806 goto out;
2807 r = -EFAULT;
d1ac91d8 2808 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2809 goto out;
2810 r = 0;
2811 break;
2812 }
2813 case KVM_SET_LAPIC: {
2204ae3c
MT		 2814 r = -EINVAL;
2815 if (!vcpu->arch.apic)
2816 goto out;
d1ac91d8 2817 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2818 r = -ENOMEM;
d1ac91d8 2819 if (!u.lapic)
b772ff36 2820 goto out;
313a3dc7 2821 r = -EFAULT;
d1ac91d8 2822 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2823 goto out;
d1ac91d8 2824 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2825 if (r)
2826 goto out;
2827 r = 0;
2828 break;
2829 }
f77bc6a4
ZX		 2830 case KVM_INTERRUPT: {
2831 struct kvm_interrupt irq;
2832
2833 r = -EFAULT;
2834 if (copy_from_user(&irq, argp, sizeof irq))
2835 goto out;
2836 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2837 if (r)
2838 goto out;
2839 r = 0;
2840 break;
2841 }
c4abb7c9
JK		 2842 case KVM_NMI: {
2843 r = kvm_vcpu_ioctl_nmi(vcpu);
2844 if (r)
2845 goto out;
2846 r = 0;
2847 break;
2848 }
313a3dc7
CO		 2849 case KVM_SET_CPUID: {
2850 struct kvm_cpuid __user *cpuid_arg = argp;
2851 struct kvm_cpuid cpuid;
2852
2853 r = -EFAULT;
2854 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2855 goto out;
2856 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2857 if (r)
2858 goto out;
2859 break;
2860 }
07716717
DK		 2861 case KVM_SET_CPUID2: {
2862 struct kvm_cpuid2 __user *cpuid_arg = argp;
2863 struct kvm_cpuid2 cpuid;
2864
2865 r = -EFAULT;
2866 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2867 goto out;
2868 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2869 cpuid_arg->entries);
07716717
DK		 2870 if (r)
2871 goto out;
2872 break;
2873 }
2874 case KVM_GET_CPUID2: {
2875 struct kvm_cpuid2 __user *cpuid_arg = argp;
2876 struct kvm_cpuid2 cpuid;
2877
2878 r = -EFAULT;
2879 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2880 goto out;
2881 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2882 cpuid_arg->entries);
07716717
DK		 2883 if (r)
2884 goto out;
2885 r = -EFAULT;
2886 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2887 goto out;
2888 r = 0;
2889 break;
2890 }
313a3dc7
CO		 2891 case KVM_GET_MSRS:
2892 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2893 break;
2894 case KVM_SET_MSRS:
2895 r = msr_io(vcpu, argp, do_set_msr, 0);
2896 break;
b209749f
AK		 2897 case KVM_TPR_ACCESS_REPORTING: {
2898 struct kvm_tpr_access_ctl tac;
2899
2900 r = -EFAULT;
2901 if (copy_from_user(&tac, argp, sizeof tac))
2902 goto out;
2903 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2904 if (r)
2905 goto out;
2906 r = -EFAULT;
2907 if (copy_to_user(argp, &tac, sizeof tac))
2908 goto out;
2909 r = 0;
2910 break;
2911 };
b93463aa
AK		 2912 case KVM_SET_VAPIC_ADDR: {
2913 struct kvm_vapic_addr va;
2914
2915 r = -EINVAL;
2916 if (!irqchip_in_kernel(vcpu->kvm))
2917 goto out;
2918 r = -EFAULT;
2919 if (copy_from_user(&va, argp, sizeof va))
2920 goto out;
2921 r = 0;
2922 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2923 break;
2924 }
890ca9ae
HY		 2925 case KVM_X86_SETUP_MCE: {
2926 u64 mcg_cap;
2927
2928 r = -EFAULT;
2929 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2930 goto out;
2931 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2932 break;
2933 }
2934 case KVM_X86_SET_MCE: {
2935 struct kvm_x86_mce mce;
2936
2937 r = -EFAULT;
2938 if (copy_from_user(&mce, argp, sizeof mce))
2939 goto out;
2940 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2941 break;
2942 }
3cfc3092
JK		 2943 case KVM_GET_VCPU_EVENTS: {
2944 struct kvm_vcpu_events events;
2945
2946 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2947
2948 r = -EFAULT;
2949 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2950 break;
2951 r = 0;
2952 break;
2953 }
2954 case KVM_SET_VCPU_EVENTS: {
2955 struct kvm_vcpu_events events;
2956
2957 r = -EFAULT;
2958 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2959 break;
2960
2961 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2962 break;
2963 }
a1efbe77
JK		 2964 case KVM_GET_DEBUGREGS: {
2965 struct kvm_debugregs dbgregs;
2966
2967 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2968
2969 r = -EFAULT;
2970 if (copy_to_user(argp, &dbgregs,
2971 sizeof(struct kvm_debugregs)))
2972 break;
2973 r = 0;
2974 break;
2975 }
2976 case KVM_SET_DEBUGREGS: {
2977 struct kvm_debugregs dbgregs;
2978
2979 r = -EFAULT;
2980 if (copy_from_user(&dbgregs, argp,
2981 sizeof(struct kvm_debugregs)))
2982 break;
2983
2984 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2985 break;
2986 }
2d5b5a66 2987 case KVM_GET_XSAVE: {
d1ac91d8 2988 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2989 r = -ENOMEM;
d1ac91d8 2990 if (!u.xsave)
2d5b5a66
SY		 2991 break;
2992
d1ac91d8 2993 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2994
2995 r = -EFAULT;
d1ac91d8 2996 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2997 break;
2998 r = 0;
2999 break;
3000 }
3001 case KVM_SET_XSAVE: {
d1ac91d8 3002 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3003 r = -ENOMEM;
d1ac91d8 3004 if (!u.xsave)
2d5b5a66
SY		 3005 break;
3006
3007 r = -EFAULT;
d1ac91d8 3008 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3009 break;
3010
d1ac91d8 3011 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3012 break;
3013 }
3014 case KVM_GET_XCRS: {
d1ac91d8 3015 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3016 r = -ENOMEM;
d1ac91d8 3017 if (!u.xcrs)
2d5b5a66
SY		 3018 break;
3019
d1ac91d8 3020 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3021
3022 r = -EFAULT;
d1ac91d8 3023 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3024 sizeof(struct kvm_xcrs)))
3025 break;
3026 r = 0;
3027 break;
3028 }
3029 case KVM_SET_XCRS: {
d1ac91d8 3030 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3031 r = -ENOMEM;
d1ac91d8 3032 if (!u.xcrs)
2d5b5a66
SY		 3033 break;
3034
3035 r = -EFAULT;
d1ac91d8 3036 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3037 sizeof(struct kvm_xcrs)))
3038 break;
3039
d1ac91d8 3040 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3041 break;
3042 }
313a3dc7
CO		 3043 default:
3044 r = -EINVAL;
3045 }
3046out:
d1ac91d8 3047 kfree(u.buffer);
313a3dc7
CO		 3048 return r;
3049}
3050
1fe779f8
CO		 3051static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3052{
3053 int ret;
3054
3055 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3056 return -1;
3057 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3058 return ret;
3059}
3060
b927a3ce
SY		 3061static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3062 u64 ident_addr)
3063{
3064 kvm->arch.ept_identity_map_addr = ident_addr;
3065 return 0;
3066}
3067
1fe779f8
CO		 3068static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3069 u32 kvm_nr_mmu_pages)
3070{
3071 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3072 return -EINVAL;
3073
79fac95e 3074 mutex_lock(&kvm->slots_lock);
7c8a83b7 3075 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3076
3077 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3078 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3079
7c8a83b7 3080 spin_unlock(&kvm->mmu_lock);
79fac95e 3081 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3082 return 0;
3083}
3084
3085static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3086{
39de71ec 3087 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3088}
3089
1fe779f8
CO		 3090static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3091{
3092 int r;
3093
3094 r = 0;
3095 switch (chip->chip_id) {
3096 case KVM_IRQCHIP_PIC_MASTER:
3097 memcpy(&chip->chip.pic,
3098 &pic_irqchip(kvm)->pics[0],
3099 sizeof(struct kvm_pic_state));
3100 break;
3101 case KVM_IRQCHIP_PIC_SLAVE:
3102 memcpy(&chip->chip.pic,
3103 &pic_irqchip(kvm)->pics[1],
3104 sizeof(struct kvm_pic_state));
3105 break;
3106 case KVM_IRQCHIP_IOAPIC:
eba0226b 3107 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3108 break;
3109 default:
3110 r = -EINVAL;
3111 break;
3112 }
3113 return r;
3114}
3115
3116static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3117{
3118 int r;
3119
3120 r = 0;
3121 switch (chip->chip_id) {
3122 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3123 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3124 memcpy(&pic_irqchip(kvm)->pics[0],
3125 &chip->chip.pic,
3126 sizeof(struct kvm_pic_state));
f4f51050 3127 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3128 break;
3129 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3130 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3131 memcpy(&pic_irqchip(kvm)->pics[1],
3132 &chip->chip.pic,
3133 sizeof(struct kvm_pic_state));
f4f51050 3134 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3135 break;
3136 case KVM_IRQCHIP_IOAPIC:
eba0226b 3137 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3138 break;
3139 default:
3140 r = -EINVAL;
3141 break;
3142 }
3143 kvm_pic_update_irq(pic_irqchip(kvm));
3144 return r;
3145}
3146
e0f63cb9
SY		 3147static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3148{
3149 int r = 0;
3150
894a9c55 3151 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3152 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3153 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3154 return r;
3155}
3156
3157static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3158{
3159 int r = 0;
3160
894a9c55 3161 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3162 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3163 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3164 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3165 return r;
3166}
3167
3168static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3169{
3170 int r = 0;
3171
3172 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3173 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3174 sizeof(ps->channels));
3175 ps->flags = kvm->arch.vpit->pit_state.flags;
3176 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3177 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3178 return r;
3179}
3180
3181static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3182{
3183 int r = 0, start = 0;
3184 u32 prev_legacy, cur_legacy;
3185 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3186 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3187 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3188 if (!prev_legacy && cur_legacy)
3189 start = 1;
3190 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3191 sizeof(kvm->arch.vpit->pit_state.channels));
3192 kvm->arch.vpit->pit_state.flags = ps->flags;
3193 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3194 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3195 return r;
3196}
3197
52d939a0
MT		 3198static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3199 struct kvm_reinject_control *control)
3200{
3201 if (!kvm->arch.vpit)
3202 return -ENXIO;
894a9c55 3203 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3204 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3205 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3206 return 0;
3207}
3208
5bb064dc
ZX		 3209/*
3210 * Get (and clear) the dirty memory log for a memory slot.
3211 */
3212int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3213 struct kvm_dirty_log *log)
3214{
87bf6e7d 3215 int r, i;
5bb064dc 3216 struct kvm_memory_slot *memslot;
87bf6e7d 3217 unsigned long n;
b050b015 3218 unsigned long is_dirty = 0;
5bb064dc 3219
79fac95e 3220 mutex_lock(&kvm->slots_lock);
5bb064dc 3221
b050b015
MT		 3222 r = -EINVAL;
3223 if (log->slot >= KVM_MEMORY_SLOTS)
3224 goto out;
3225
3226 memslot = &kvm->memslots->memslots[log->slot];
3227 r = -ENOENT;
3228 if (!memslot->dirty_bitmap)
3229 goto out;
3230
87bf6e7d 3231 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3232
b050b015
MT		 3233 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3234 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3235
3236 /* If nothing is dirty, don't bother messing with page tables. */
3237 if (is_dirty) {
b050b015 3238 struct kvm_memslots *slots, *old_slots;
914ebccd 3239 unsigned long *dirty_bitmap;
b050b015 3240
515a0127
TY		 3241 dirty_bitmap = memslot->dirty_bitmap_head;
3242 if (memslot->dirty_bitmap == dirty_bitmap)
3243 dirty_bitmap += n / sizeof(long);
914ebccd 3244 memset(dirty_bitmap, 0, n);
b050b015 3245
914ebccd
TY		 3246 r = -ENOMEM;
3247 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3248 if (!slots)
914ebccd 3249 goto out;
b050b015
MT		 3250 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3251 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3252 slots->generation++;
b050b015
MT		 3253
3254 old_slots = kvm->memslots;
3255 rcu_assign_pointer(kvm->memslots, slots);
3256 synchronize_srcu_expedited(&kvm->srcu);
3257 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3258 kfree(old_slots);
914ebccd 3259
edde99ce
MT		 3260 spin_lock(&kvm->mmu_lock);
3261 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3262 spin_unlock(&kvm->mmu_lock);
3263
914ebccd 3264 r = -EFAULT;
515a0127 3265 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3266 goto out;
914ebccd
TY		 3267 } else {
3268 r = -EFAULT;
3269 if (clear_user(log->dirty_bitmap, n))
3270 goto out;
5bb064dc 3271 }
b050b015 3272
5bb064dc
ZX		 3273 r = 0;
3274out:
79fac95e 3275 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3276 return r;
3277}
3278
1fe779f8
CO		 3279long kvm_arch_vm_ioctl(struct file *filp,
3280 unsigned int ioctl, unsigned long arg)
3281{
3282 struct kvm *kvm = filp->private_data;
3283 void __user *argp = (void __user *)arg;
367e1319 3284 int r = -ENOTTY;
f0d66275
DH		 3285 /*
3286 * This union makes it completely explicit to gcc-3.x
3287 * that these two variables' stack usage should be
3288 * combined, not added together.
3289 */
3290 union {
3291 struct kvm_pit_state ps;
e9f42757 3292 struct kvm_pit_state2 ps2;
c5ff41ce 3293 struct kvm_pit_config pit_config;
f0d66275 3294 } u;
1fe779f8
CO		 3295
3296 switch (ioctl) {
3297 case KVM_SET_TSS_ADDR:
3298 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3299 if (r < 0)
3300 goto out;
3301 break;
b927a3ce
SY		 3302 case KVM_SET_IDENTITY_MAP_ADDR: {
3303 u64 ident_addr;
3304
3305 r = -EFAULT;
3306 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3307 goto out;
3308 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3309 if (r < 0)
3310 goto out;
3311 break;
3312 }
1fe779f8
CO		 3313 case KVM_SET_NR_MMU_PAGES:
3314 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3315 if (r)
3316 goto out;
3317 break;
3318 case KVM_GET_NR_MMU_PAGES:
3319 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3320 break;
3ddea128
MT		 3321 case KVM_CREATE_IRQCHIP: {
3322 struct kvm_pic *vpic;
3323
3324 mutex_lock(&kvm->lock);
3325 r = -EEXIST;
3326 if (kvm->arch.vpic)
3327 goto create_irqchip_unlock;
1fe779f8 3328 r = -ENOMEM;
3ddea128
MT		 3329 vpic = kvm_create_pic(kvm);
3330 if (vpic) {
1fe779f8
CO		 3331 r = kvm_ioapic_init(kvm);
3332 if (r) {
175504cd 3333 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3334 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3335 &vpic->dev);
175504cd 3336 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3337 kfree(vpic);
3338 goto create_irqchip_unlock;
1fe779f8
CO		 3339 }
3340 } else
3ddea128
MT		 3341 goto create_irqchip_unlock;
3342 smp_wmb();
3343 kvm->arch.vpic = vpic;
3344 smp_wmb();
399ec807
AK		 3345 r = kvm_setup_default_irq_routing(kvm);
3346 if (r) {
175504cd 3347 mutex_lock(&kvm->slots_lock);
3ddea128 3348 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3349 kvm_ioapic_destroy(kvm);
3350 kvm_destroy_pic(kvm);
3ddea128 3351 mutex_unlock(&kvm->irq_lock);
175504cd 3352 mutex_unlock(&kvm->slots_lock);
399ec807 3353 }
3ddea128
MT		 3354 create_irqchip_unlock:
3355 mutex_unlock(&kvm->lock);
1fe779f8 3356 break;
3ddea128 3357 }
7837699f 3358 case KVM_CREATE_PIT:
c5ff41ce
JK		 3359 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3360 goto create_pit;
3361 case KVM_CREATE_PIT2:
3362 r = -EFAULT;
3363 if (copy_from_user(&u.pit_config, argp,
3364 sizeof(struct kvm_pit_config)))
3365 goto out;
3366 create_pit:
79fac95e 3367 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3368 r = -EEXIST;
3369 if (kvm->arch.vpit)
3370 goto create_pit_unlock;
7837699f 3371 r = -ENOMEM;
c5ff41ce 3372 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3373 if (kvm->arch.vpit)
3374 r = 0;
269e05e4 3375 create_pit_unlock:
79fac95e 3376 mutex_unlock(&kvm->slots_lock);
7837699f 3377 break;
4925663a 3378 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3379 case KVM_IRQ_LINE: {
3380 struct kvm_irq_level irq_event;
3381
3382 r = -EFAULT;
3383 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3384 goto out;
160d2f6c 3385 r = -ENXIO;
1fe779f8 3386 if (irqchip_in_kernel(kvm)) {
4925663a 3387 __s32 status;
4925663a
GN		 3388 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3389 irq_event.irq, irq_event.level);
4925663a 3390 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3391 r = -EFAULT;
4925663a
GN		 3392 irq_event.status = status;
3393 if (copy_to_user(argp, &irq_event,
3394 sizeof irq_event))
3395 goto out;
3396 }
1fe779f8
CO		 3397 r = 0;
3398 }
3399 break;
3400 }
3401 case KVM_GET_IRQCHIP: {
3402 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3403 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3404
f0d66275
DH		 3405 r = -ENOMEM;
3406 if (!chip)
1fe779f8 3407 goto out;
f0d66275
DH		 3408 r = -EFAULT;
3409 if (copy_from_user(chip, argp, sizeof *chip))
3410 goto get_irqchip_out;
1fe779f8
CO		 3411 r = -ENXIO;
3412 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3413 goto get_irqchip_out;
3414 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3415 if (r)
f0d66275 3416 goto get_irqchip_out;
1fe779f8 3417 r = -EFAULT;
f0d66275
DH		 3418 if (copy_to_user(argp, chip, sizeof *chip))
3419 goto get_irqchip_out;
1fe779f8 3420 r = 0;
f0d66275
DH		 3421 get_irqchip_out:
3422 kfree(chip);
3423 if (r)
3424 goto out;
1fe779f8
CO		 3425 break;
3426 }
3427 case KVM_SET_IRQCHIP: {
3428 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3429 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3430
f0d66275
DH		 3431 r = -ENOMEM;
3432 if (!chip)
1fe779f8 3433 goto out;
f0d66275
DH		 3434 r = -EFAULT;
3435 if (copy_from_user(chip, argp, sizeof *chip))
3436 goto set_irqchip_out;
1fe779f8
CO		 3437 r = -ENXIO;
3438 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3439 goto set_irqchip_out;
3440 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3441 if (r)
f0d66275 3442 goto set_irqchip_out;
1fe779f8 3443 r = 0;
f0d66275
DH		 3444 set_irqchip_out:
3445 kfree(chip);
3446 if (r)
3447 goto out;
1fe779f8
CO		 3448 break;
3449 }
e0f63cb9 3450 case KVM_GET_PIT: {
e0f63cb9 3451 r = -EFAULT;
f0d66275 3452 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3453 goto out;
3454 r = -ENXIO;
3455 if (!kvm->arch.vpit)
3456 goto out;
f0d66275 3457 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3458 if (r)
3459 goto out;
3460 r = -EFAULT;
f0d66275 3461 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3462 goto out;
3463 r = 0;
3464 break;
3465 }
3466 case KVM_SET_PIT: {
e0f63cb9 3467 r = -EFAULT;
f0d66275 3468 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3469 goto out;
3470 r = -ENXIO;
3471 if (!kvm->arch.vpit)
3472 goto out;
f0d66275 3473 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3474 if (r)
3475 goto out;
3476 r = 0;
3477 break;
3478 }
e9f42757
BK		 3479 case KVM_GET_PIT2: {
3480 r = -ENXIO;
3481 if (!kvm->arch.vpit)
3482 goto out;
3483 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3484 if (r)
3485 goto out;
3486 r = -EFAULT;
3487 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3488 goto out;
3489 r = 0;
3490 break;
3491 }
3492 case KVM_SET_PIT2: {
3493 r = -EFAULT;
3494 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3495 goto out;
3496 r = -ENXIO;
3497 if (!kvm->arch.vpit)
3498 goto out;
3499 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3500 if (r)
3501 goto out;
3502 r = 0;
3503 break;
3504 }
52d939a0
MT		 3505 case KVM_REINJECT_CONTROL: {
3506 struct kvm_reinject_control control;
3507 r = -EFAULT;
3508 if (copy_from_user(&control, argp, sizeof(control)))
3509 goto out;
3510 r = kvm_vm_ioctl_reinject(kvm, &control);
3511 if (r)
3512 goto out;
3513 r = 0;
3514 break;
3515 }
ffde22ac
ES		 3516 case KVM_XEN_HVM_CONFIG: {
3517 r = -EFAULT;
3518 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3519 sizeof(struct kvm_xen_hvm_config)))
3520 goto out;
3521 r = -EINVAL;
3522 if (kvm->arch.xen_hvm_config.flags)
3523 goto out;
3524 r = 0;
3525 break;
3526 }
afbcf7ab 3527 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3528 struct kvm_clock_data user_ns;
3529 u64 now_ns;
3530 s64 delta;
3531
3532 r = -EFAULT;
3533 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3534 goto out;
3535
3536 r = -EINVAL;
3537 if (user_ns.flags)
3538 goto out;
3539
3540 r = 0;
395c6b0a 3541 local_irq_disable();
759379dd 3542 now_ns = get_kernel_ns();
afbcf7ab 3543 delta = user_ns.clock - now_ns;
395c6b0a 3544 local_irq_enable();
afbcf7ab
GC		 3545 kvm->arch.kvmclock_offset = delta;
3546 break;
3547 }
3548 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3549 struct kvm_clock_data user_ns;
3550 u64 now_ns;
3551
395c6b0a 3552 local_irq_disable();
759379dd 3553 now_ns = get_kernel_ns();
afbcf7ab 3554 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3555 local_irq_enable();
afbcf7ab 3556 user_ns.flags = 0;
97e69aa6 3557 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3558
3559 r = -EFAULT;
3560 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3561 goto out;
3562 r = 0;
3563 break;
3564 }
3565
1fe779f8
CO		 3566 default:
3567 ;
3568 }
3569out:
3570 return r;
3571}
3572
a16b043c 3573static void kvm_init_msr_list(void)
043405e1
CO		 3574{
3575 u32 dummy[2];
3576 unsigned i, j;
3577
e3267cbb
GC		 3578 /* skip the first msrs in the list. KVM-specific */
3579 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3580 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3581 continue;
3582 if (j < i)
3583 msrs_to_save[j] = msrs_to_save[i];
3584 j++;
3585 }
3586 num_msrs_to_save = j;
3587}
3588
bda9020e
MT		 3589static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3590 const void *v)
bbd9b64e 3591{
70252a10
AK		 3592 int handled = 0;
3593 int n;
3594
3595 do {
3596 n = min(len, 8);
3597 if (!(vcpu->arch.apic &&
3598 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3599 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3600 break;
3601 handled += n;
3602 addr += n;
3603 len -= n;
3604 v += n;
3605 } while (len);
bbd9b64e 3606
70252a10 3607 return handled;
bbd9b64e
CO		 3608}
3609
bda9020e 3610static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3611{
70252a10
AK		 3612 int handled = 0;
3613 int n;
3614
3615 do {
3616 n = min(len, 8);
3617 if (!(vcpu->arch.apic &&
3618 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3619 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3620 break;
3621 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3622 handled += n;
3623 addr += n;
3624 len -= n;
3625 v += n;
3626 } while (len);
bbd9b64e 3627
70252a10 3628 return handled;
bbd9b64e
CO		 3629}
3630
2dafc6c2
GN		 3631static void kvm_set_segment(struct kvm_vcpu *vcpu,
3632 struct kvm_segment *var, int seg)
3633{
3634 kvm_x86_ops->set_segment(vcpu, var, seg);
3635}
3636
3637void kvm_get_segment(struct kvm_vcpu *vcpu,
3638 struct kvm_segment *var, int seg)
3639{
3640 kvm_x86_ops->get_segment(vcpu, var, seg);
3641}
3642
c30a358d
JR		 3643static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3644{
3645 return gpa;
3646}
3647
02f59dc9
JR		 3648static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3649{
3650 gpa_t t_gpa;
ab9ae313 3651 struct x86_exception exception;
02f59dc9
JR		 3652
3653 BUG_ON(!mmu_is_nested(vcpu));
3654
3655 /* NPT walks are always user-walks */
3656 access |= PFERR_USER_MASK;
ab9ae313 3657 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3658
3659 return t_gpa;
3660}
3661
ab9ae313
AK		 3662gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3663 struct x86_exception *exception)
1871c602
GN		 3664{
3665 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3666 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3667}
3668
ab9ae313
AK		 3669 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3670 struct x86_exception *exception)
1871c602
GN		 3671{
3672 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3673 access |= PFERR_FETCH_MASK;
ab9ae313 3674 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3675}
3676
ab9ae313
AK		 3677gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3678 struct x86_exception *exception)
1871c602
GN		 3679{
3680 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3681 access |= PFERR_WRITE_MASK;
ab9ae313 3682 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3683}
3684
3685/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3686gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3687 struct x86_exception *exception)
1871c602 3688{
ab9ae313 3689 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3690}
3691
3692static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3693 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3694 struct x86_exception *exception)
bbd9b64e
CO		 3695{
3696 void *data = val;
10589a46 3697 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3698
3699 while (bytes) {
14dfe855 3700 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3701 exception);
bbd9b64e 3702 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3703 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3704 int ret;
3705
bcc55cba 3706 if (gpa == UNMAPPED_GVA)
ab9ae313 3707 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3708 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3709 if (ret < 0) {
c3cd7ffa 3710 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3711 goto out;
3712 }
bbd9b64e 3713
77c2002e
IE		 3714 bytes -= toread;
3715 data += toread;
3716 addr += toread;
bbd9b64e 3717 }
10589a46 3718out:
10589a46 3719 return r;
bbd9b64e 3720}
77c2002e 3721
1871c602
GN		 3722/* used for instruction fetching */
3723static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3724 struct kvm_vcpu *vcpu,
3725 struct x86_exception *exception)
1871c602
GN		 3726{
3727 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3728 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3729 access | PFERR_FETCH_MASK,
3730 exception);
1871c602
GN		 3731}
3732
3733static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3734 struct kvm_vcpu *vcpu,
3735 struct x86_exception *exception)
1871c602
GN		 3736{
3737 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3738 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3739 exception);
1871c602
GN		 3740}
3741
3742static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3743 struct kvm_vcpu *vcpu,
3744 struct x86_exception *exception)
1871c602 3745{
bcc55cba 3746 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3747}
3748
7972995b 3749static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3750 unsigned int bytes,
7972995b 3751 struct kvm_vcpu *vcpu,
bcc55cba 3752 struct x86_exception *exception)
77c2002e
IE		 3753{
3754 void *data = val;
3755 int r = X86EMUL_CONTINUE;
3756
3757 while (bytes) {
14dfe855
JR		 3758 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3759 PFERR_WRITE_MASK,
ab9ae313 3760 exception);
77c2002e
IE		 3761 unsigned offset = addr & (PAGE_SIZE-1);
3762 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3763 int ret;
3764
bcc55cba 3765 if (gpa == UNMAPPED_GVA)
ab9ae313 3766 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3767 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3768 if (ret < 0) {
c3cd7ffa 3769 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3770 goto out;
3771 }
3772
3773 bytes -= towrite;
3774 data += towrite;
3775 addr += towrite;
3776 }
3777out:
3778 return r;
3779}
3780
bbd9b64e
CO		 3781static int emulator_read_emulated(unsigned long addr,
3782 void *val,
3783 unsigned int bytes,
bcc55cba 3784 struct x86_exception *exception,
bbd9b64e
CO		 3785 struct kvm_vcpu *vcpu)
3786{
bbd9b64e 3787 gpa_t gpa;
70252a10 3788 int handled;
bbd9b64e
CO		 3789
3790 if (vcpu->mmio_read_completed) {
3791 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3792 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3793 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3794 vcpu->mmio_read_completed = 0;
3795 return X86EMUL_CONTINUE;
3796 }
3797
ab9ae313 3798 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3799
8fe681e9 3800 if (gpa == UNMAPPED_GVA)
1871c602 3801 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3802
3803 /* For APIC access vmexit */
3804 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3805 goto mmio;
3806
bcc55cba
AK		 3807 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3808 == X86EMUL_CONTINUE)
bbd9b64e 3809 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3810
3811mmio:
3812 /*
3813 * Is this MMIO handled locally?
3814 */
70252a10
AK		 3815 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3816
3817 if (handled == bytes)
bbd9b64e 3818 return X86EMUL_CONTINUE;
70252a10
AK		 3819
3820 gpa += handled;
3821 bytes -= handled;
3822 val += handled;
aec51dc4
AK		 3823
3824 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3825
3826 vcpu->mmio_needed = 1;
411c35b7
GN		 3827 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3828 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3829 vcpu->mmio_size = bytes;
3830 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3831 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3832 vcpu->mmio_index = 0;
bbd9b64e 3833
c3cd7ffa 3834 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3835}
3836
3200f405 3837int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3838 const void *val, int bytes)
bbd9b64e
CO		 3839{
3840 int ret;
3841
3842 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3843 if (ret < 0)
bbd9b64e 3844 return 0;
ad218f85 3845 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3846 return 1;
3847}
3848
3849static int emulator_write_emulated_onepage(unsigned long addr,
3850 const void *val,
3851 unsigned int bytes,
bcc55cba 3852 struct x86_exception *exception,
bbd9b64e
CO		 3853 struct kvm_vcpu *vcpu)
3854{
10589a46 3855 gpa_t gpa;
70252a10 3856 int handled;
10589a46 3857
ab9ae313 3858 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3859
8fe681e9 3860 if (gpa == UNMAPPED_GVA)
bbd9b64e 3861 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3862
3863 /* For APIC access vmexit */
3864 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3865 goto mmio;
3866
3867 if (emulator_write_phys(vcpu, gpa, val, bytes))
3868 return X86EMUL_CONTINUE;
3869
3870mmio:
aec51dc4 3871 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3872 /*
3873 * Is this MMIO handled locally?
3874 */
70252a10
AK		 3875 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
3876 if (handled == bytes)
bbd9b64e 3877 return X86EMUL_CONTINUE;
bbd9b64e 3878
70252a10
AK		 3879 gpa += handled;
3880 bytes -= handled;
3881 val += handled;
3882
bbd9b64e 3883 vcpu->mmio_needed = 1;
cef4dea0 3884 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 3885 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3886 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3887 vcpu->mmio_size = bytes;
3888 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3889 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 3890 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3891 vcpu->mmio_index = 0;
bbd9b64e
CO		 3892
3893 return X86EMUL_CONTINUE;
3894}
3895
3896int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3897 const void *val,
3898 unsigned int bytes,
bcc55cba 3899 struct x86_exception *exception,
8f6abd06 3900 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3901{
3902 /* Crossing a page boundary? */
3903 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3904 int rc, now;
3905
3906 now = -addr & ~PAGE_MASK;
bcc55cba 3907 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3908 vcpu);
bbd9b64e
CO		 3909 if (rc != X86EMUL_CONTINUE)
3910 return rc;
3911 addr += now;
3912 val += now;
3913 bytes -= now;
3914 }
bcc55cba 3915 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3916 vcpu);
bbd9b64e 3917}
bbd9b64e 3918
daea3e73
AK		 3919#define CMPXCHG_TYPE(t, ptr, old, new) \
3920 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3921
3922#ifdef CONFIG_X86_64
3923# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3924#else
3925# define CMPXCHG64(ptr, old, new) \
9749a6c0 3926 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3927#endif
3928
bbd9b64e
CO		 3929static int emulator_cmpxchg_emulated(unsigned long addr,
3930 const void *old,
3931 const void *new,
3932 unsigned int bytes,
bcc55cba 3933 struct x86_exception *exception,
bbd9b64e
CO		 3934 struct kvm_vcpu *vcpu)
3935{
daea3e73
AK		 3936 gpa_t gpa;
3937 struct page *page;
3938 char *kaddr;
3939 bool exchanged;
2bacc55c 3940
daea3e73
AK		 3941 /* guests cmpxchg8b have to be emulated atomically */
3942 if (bytes > 8 || (bytes & (bytes - 1)))
3943 goto emul_write;
10589a46 3944
daea3e73 3945 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3946
daea3e73
AK		 3947 if (gpa == UNMAPPED_GVA ||
3948 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3949 goto emul_write;
2bacc55c 3950
daea3e73
AK		 3951 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3952 goto emul_write;
72dc67a6 3953
daea3e73 3954 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3955 if (is_error_page(page)) {
3956 kvm_release_page_clean(page);
3957 goto emul_write;
3958 }
72dc67a6 3959
daea3e73
AK		 3960 kaddr = kmap_atomic(page, KM_USER0);
3961 kaddr += offset_in_page(gpa);
3962 switch (bytes) {
3963 case 1:
3964 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3965 break;
3966 case 2:
3967 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3968 break;
3969 case 4:
3970 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3971 break;
3972 case 8:
3973 exchanged = CMPXCHG64(kaddr, old, new);
3974 break;
3975 default:
3976 BUG();
2bacc55c 3977 }
daea3e73
AK		 3978 kunmap_atomic(kaddr, KM_USER0);
3979 kvm_release_page_dirty(page);
3980
3981 if (!exchanged)
3982 return X86EMUL_CMPXCHG_FAILED;
3983
8f6abd06
GN		 3984 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3985
3986 return X86EMUL_CONTINUE;
4a5f48f6 3987
3200f405 3988emul_write:
daea3e73 3989 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3990
bcc55cba 3991 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 3992}
3993
cf8f70bf
GN		 3994static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3995{
3996 /* TODO: String I/O for in kernel device */
3997 int r;
3998
3999 if (vcpu->arch.pio.in)
4000 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4001 vcpu->arch.pio.size, pd);
4002 else
4003 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4004 vcpu->arch.pio.port, vcpu->arch.pio.size,
4005 pd);
4006 return r;
4007}
4008
4009
4010static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
4011 unsigned int count, struct kvm_vcpu *vcpu)
4012{
7972995b 4013 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4014 goto data_avail;
4015
61cfab2e 4016 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4017
4018 vcpu->arch.pio.port = port;
4019 vcpu->arch.pio.in = 1;
7972995b 4020 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4021 vcpu->arch.pio.size = size;
4022
4023 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4024 data_avail:
4025 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4026 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4027 return 1;
4028 }
4029
4030 vcpu->run->exit_reason = KVM_EXIT_IO;
4031 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4032 vcpu->run->io.size = size;
4033 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4034 vcpu->run->io.count = count;
4035 vcpu->run->io.port = port;
4036
4037 return 0;
4038}
4039
4040static int emulator_pio_out_emulated(int size, unsigned short port,
4041 const void *val, unsigned int count,
4042 struct kvm_vcpu *vcpu)
4043{
61cfab2e 4044 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4045
4046 vcpu->arch.pio.port = port;
4047 vcpu->arch.pio.in = 0;
7972995b 4048 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4049 vcpu->arch.pio.size = size;
4050
4051 memcpy(vcpu->arch.pio_data, val, size * count);
4052
4053 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4054 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4055 return 1;
4056 }
4057
4058 vcpu->run->exit_reason = KVM_EXIT_IO;
4059 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4060 vcpu->run->io.size = size;
4061 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4062 vcpu->run->io.count = count;
4063 vcpu->run->io.port = port;
4064
4065 return 0;
4066}
4067
bbd9b64e
CO		 4068static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4069{
4070 return kvm_x86_ops->get_segment_base(vcpu, seg);
4071}
4072
4073int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4074{
a7052897 4075 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4076 return X86EMUL_CONTINUE;
4077}
4078
f5f48ee1
SY		 4079int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4080{
4081 if (!need_emulate_wbinvd(vcpu))
4082 return X86EMUL_CONTINUE;
4083
4084 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4085 int cpu = get_cpu();
4086
4087 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4088 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4089 wbinvd_ipi, NULL, 1);
2eec7343 4090 put_cpu();
f5f48ee1 4091 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4092 } else
4093 wbinvd();
f5f48ee1
SY		 4094 return X86EMUL_CONTINUE;
4095}
4096EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4097
bbd9b64e
CO		 4098int emulate_clts(struct kvm_vcpu *vcpu)
4099{
4d4ec087 4100 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4101 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4102 return X86EMUL_CONTINUE;
4103}
4104
35aa5375 4105int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4106{
338dbc97 4107 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4108}
4109
35aa5375 4110int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4111{
338dbc97
GN		 4112
4113 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4114}
4115
52a46617 4116static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4117{
52a46617 4118 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4119}
4120
52a46617 4121static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4122{
52a46617
GN		 4123 unsigned long value;
4124
4125 switch (cr) {
4126 case 0:
4127 value = kvm_read_cr0(vcpu);
4128 break;
4129 case 2:
4130 value = vcpu->arch.cr2;
4131 break;
4132 case 3:
9f8fe504 4133 value = kvm_read_cr3(vcpu);
52a46617
GN		 4134 break;
4135 case 4:
4136 value = kvm_read_cr4(vcpu);
4137 break;
4138 case 8:
4139 value = kvm_get_cr8(vcpu);
4140 break;
4141 default:
4142 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4143 return 0;
4144 }
4145
4146 return value;
4147}
4148
0f12244f 4149static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4150{
0f12244f
GN		 4151 int res = 0;
4152
52a46617
GN		 4153 switch (cr) {
4154 case 0:
49a9b07e 4155 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4156 break;
4157 case 2:
4158 vcpu->arch.cr2 = val;
4159 break;
4160 case 3:
2390218b 4161 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4162 break;
4163 case 4:
a83b29c6 4164 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4165 break;
4166 case 8:
eea1cff9 4167 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4168 break;
4169 default:
4170 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4171 res = -1;
52a46617 4172 }
0f12244f
GN		 4173
4174 return res;
52a46617
GN		 4175}
4176
9c537244
GN		 4177static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4178{
4179 return kvm_x86_ops->get_cpl(vcpu);
4180}
4181
2dafc6c2
GN		 4182static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4183{
4184 kvm_x86_ops->get_gdt(vcpu, dt);
4185}
4186
160ce1f1
MG		 4187static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4188{
4189 kvm_x86_ops->get_idt(vcpu, dt);
4190}
4191
5951c442
GN		 4192static unsigned long emulator_get_cached_segment_base(int seg,
4193 struct kvm_vcpu *vcpu)
4194{
4195 return get_segment_base(vcpu, seg);
4196}
4197
5601d05b
GN		 4198static bool emulator_get_cached_descriptor(struct desc_struct *desc, u32 *base3,
4199 int seg, struct kvm_vcpu *vcpu)
2dafc6c2
GN		 4200{
4201 struct kvm_segment var;
4202
4203 kvm_get_segment(vcpu, &var, seg);
4204
4205 if (var.unusable)
4206 return false;
4207
4208 if (var.g)
4209 var.limit >>= 12;
4210 set_desc_limit(desc, var.limit);
4211 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4212#ifdef CONFIG_X86_64
4213 if (base3)
4214 *base3 = var.base >> 32;
4215#endif
2dafc6c2
GN		 4216 desc->type = var.type;
4217 desc->s = var.s;
4218 desc->dpl = var.dpl;
4219 desc->p = var.present;
4220 desc->avl = var.avl;
4221 desc->l = var.l;
4222 desc->d = var.db;
4223 desc->g = var.g;
4224
4225 return true;
4226}
4227
5601d05b
GN		 4228static void emulator_set_cached_descriptor(struct desc_struct *desc, u32 base3,
4229 int seg, struct kvm_vcpu *vcpu)
2dafc6c2
GN		 4230{
4231 struct kvm_segment var;
4232
4233 /* needed to preserve selector */
4234 kvm_get_segment(vcpu, &var, seg);
4235
4236 var.base = get_desc_base(desc);
5601d05b
GN		 4237#ifdef CONFIG_X86_64
4238 var.base |= ((u64)base3) << 32;
4239#endif
2dafc6c2
GN		 4240 var.limit = get_desc_limit(desc);
4241 if (desc->g)
4242 var.limit = (var.limit << 12) | 0xfff;
4243 var.type = desc->type;
4244 var.present = desc->p;
4245 var.dpl = desc->dpl;
4246 var.db = desc->d;
4247 var.s = desc->s;
4248 var.l = desc->l;
4249 var.g = desc->g;
4250 var.avl = desc->avl;
4251 var.present = desc->p;
4252 var.unusable = !var.present;
4253 var.padding = 0;
4254
4255 kvm_set_segment(vcpu, &var, seg);
4256 return;
4257}
4258
4259static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4260{
4261 struct kvm_segment kvm_seg;
4262
4263 kvm_get_segment(vcpu, &kvm_seg, seg);
4264 return kvm_seg.selector;
4265}
4266
4267static void emulator_set_segment_selector(u16 sel, int seg,
4268 struct kvm_vcpu *vcpu)
4269{
4270 struct kvm_segment kvm_seg;
4271
4272 kvm_get_segment(vcpu, &kvm_seg, seg);
4273 kvm_seg.selector = sel;
4274 kvm_set_segment(vcpu, &kvm_seg, seg);
4275}
4276
5037f6f3
AK		 4277static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4278{
4279 preempt_disable();
4280 kvm_load_guest_fpu(ctxt->vcpu);
4281 /*
4282 * CR0.TS may reference the host fpu state, not the guest fpu state,
4283 * so it may be clear at this point.
4284 */
4285 clts();
4286}
4287
4288static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4289{
4290 preempt_enable();
4291}
4292
8a76d7f2
JR		 4293static int emulator_intercept(struct kvm_vcpu *vcpu,
4294 struct x86_instruction_info *info,
c4f035c6
AK		 4295 enum x86_intercept_stage stage)
4296{
8a76d7f2 4297 return kvm_x86_ops->check_intercept(vcpu, info, stage);
c4f035c6
AK		 4298}
4299
14af3f3c 4300static struct x86_emulate_ops emulate_ops = {
1871c602 4301 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4302 .write_std = kvm_write_guest_virt_system,
1871c602 4303 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4304 .read_emulated = emulator_read_emulated,
4305 .write_emulated = emulator_write_emulated,
4306 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4307 .pio_in_emulated = emulator_pio_in_emulated,
4308 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4309 .get_cached_descriptor = emulator_get_cached_descriptor,
4310 .set_cached_descriptor = emulator_set_cached_descriptor,
4311 .get_segment_selector = emulator_get_segment_selector,
4312 .set_segment_selector = emulator_set_segment_selector,
5951c442 4313 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4314 .get_gdt = emulator_get_gdt,
160ce1f1 4315 .get_idt = emulator_get_idt,
52a46617
GN		 4316 .get_cr = emulator_get_cr,
4317 .set_cr = emulator_set_cr,
9c537244 4318 .cpl = emulator_get_cpl,
35aa5375
GN		 4319 .get_dr = emulator_get_dr,
4320 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4321 .set_msr = kvm_set_msr,
4322 .get_msr = kvm_get_msr,
5037f6f3
AK		 4323 .get_fpu = emulator_get_fpu,
4324 .put_fpu = emulator_put_fpu,
c4f035c6 4325 .intercept = emulator_intercept,
bbd9b64e
CO		 4326};
4327
5fdbf976
MT		 4328static void cache_all_regs(struct kvm_vcpu *vcpu)
4329{
4330 kvm_register_read(vcpu, VCPU_REGS_RAX);
4331 kvm_register_read(vcpu, VCPU_REGS_RSP);
4332 kvm_register_read(vcpu, VCPU_REGS_RIP);
4333 vcpu->arch.regs_dirty = ~0;
4334}
4335
95cb2295
GN		 4336static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4337{
4338 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4339 /*
4340 * an sti; sti; sequence only disable interrupts for the first
4341 * instruction. So, if the last instruction, be it emulated or
4342 * not, left the system with the INT_STI flag enabled, it
4343 * means that the last instruction is an sti. We should not
4344 * leave the flag on in this case. The same goes for mov ss
4345 */
4346 if (!(int_shadow & mask))
4347 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4348}
4349
54b8486f
GN		 4350static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4351{
4352 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4353 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4354 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4355 else if (ctxt->exception.error_code_valid)
4356 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4357 ctxt->exception.error_code);
54b8486f 4358 else
da9cb575 4359 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4360}
4361
8ec4722d
MG		 4362static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4363{
4364 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4365 int cs_db, cs_l;
4366
4367 cache_all_regs(vcpu);
4368
4369 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4370
4371 vcpu->arch.emulate_ctxt.vcpu = vcpu;
f6e78475 4372 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
8ec4722d
MG		 4373 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4374 vcpu->arch.emulate_ctxt.mode =
4375 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4376 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4377 ? X86EMUL_MODE_VM86 : cs_l
4378 ? X86EMUL_MODE_PROT64 : cs_db
4379 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
c4f035c6 4380 vcpu->arch.emulate_ctxt.guest_mode = is_guest_mode(vcpu);
8ec4722d
MG		 4381 memset(c, 0, sizeof(struct decode_cache));
4382 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4383}
4384
63995653
MG		 4385int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4386{
4387 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4388 int ret;
4389
4390 init_emulate_ctxt(vcpu);
4391
4392 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4393 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4394 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4395 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4396
4397 if (ret != X86EMUL_CONTINUE)
4398 return EMULATE_FAIL;
4399
4400 vcpu->arch.emulate_ctxt.eip = c->eip;
4401 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4402 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 4403 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
63995653
MG		 4404
4405 if (irq == NMI_VECTOR)
4406 vcpu->arch.nmi_pending = false;
4407 else
4408 vcpu->arch.interrupt.pending = false;
4409
4410 return EMULATE_DONE;
4411}
4412EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4413
6d77dbfc
GN		 4414static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4415{
fc3a9157
JR		 4416 int r = EMULATE_DONE;
4417
6d77dbfc
GN		 4418 ++vcpu->stat.insn_emulation_fail;
4419 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4420 if (!is_guest_mode(vcpu)) {
4421 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4422 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4423 vcpu->run->internal.ndata = 0;
4424 r = EMULATE_FAIL;
4425 }
6d77dbfc 4426 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4427
4428 return r;
6d77dbfc
GN		 4429}
4430
a6f177ef
GN		 4431static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4432{
4433 gpa_t gpa;
4434
68be0803
GN		 4435 if (tdp_enabled)
4436 return false;
4437
a6f177ef
GN		 4438 /*
4439 * if emulation was due to access to shadowed page table
4440 * and it failed try to unshadow page and re-entetr the
4441 * guest to let CPU execute the instruction.
4442 */
4443 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4444 return true;
4445
4446 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4447
4448 if (gpa == UNMAPPED_GVA)
4449 return true; /* let cpu generate fault */
4450
4451 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4452 return true;
4453
4454 return false;
4455}
4456
51d8b661
AP		 4457int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4458 unsigned long cr2,
dc25e89e
AP		 4459 int emulation_type,
4460 void *insn,
4461 int insn_len)
bbd9b64e 4462{
95cb2295 4463 int r;
4d2179e1 4464 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4465
26eef70c 4466 kvm_clear_exception_queue(vcpu);
ad312c7c 4467 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4468 /*
56e82318 4469 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4470 * instead of direct ->regs accesses, can save hundred cycles
4471 * on Intel for instructions that don't read/change RSP, for
4472 * for example.
4473 */
4474 cache_all_regs(vcpu);
bbd9b64e 4475
571008da 4476 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4477 init_emulate_ctxt(vcpu);
95cb2295 4478 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4479 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4480 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4481
4005996e
AK		 4482 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4483 = emulation_type & EMULTYPE_TRAP_UD;
4484
dc25e89e 4485 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4486
e46479f8 4487 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4488 ++vcpu->stat.insn_emulation;
bbd9b64e 4489 if (r) {
4005996e
AK		 4490 if (emulation_type & EMULTYPE_TRAP_UD)
4491 return EMULATE_FAIL;
a6f177ef 4492 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4493 return EMULATE_DONE;
6d77dbfc
GN		 4494 if (emulation_type & EMULTYPE_SKIP)
4495 return EMULATE_FAIL;
4496 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4497 }
4498 }
4499
ba8afb6b
GN		 4500 if (emulation_type & EMULTYPE_SKIP) {
4501 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4502 return EMULATE_DONE;
4503 }
4504
4d2179e1
GN		 4505 /* this is needed for vmware backdor interface to work since it
4506 changes registers values during IO operation */
4507 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4508
5cd21917 4509restart:
9aabc88f 4510 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4511
775fde86
JR		 4512 if (r == EMULATION_INTERCEPTED)
4513 return EMULATE_DONE;
4514
d2ddd1c4 4515 if (r == EMULATION_FAILED) {
a6f177ef 4516 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4517 return EMULATE_DONE;
4518
6d77dbfc 4519 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4520 }
4521
da9cb575 4522 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4523 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4524 r = EMULATE_DONE;
4525 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4526 if (!vcpu->arch.pio.in)
4527 vcpu->arch.pio.count = 0;
e85d28f8 4528 r = EMULATE_DO_MMIO;
cef4dea0 4529 } else if (vcpu->mmio_needed)
e85d28f8 4530 r = EMULATE_DO_MMIO;
cef4dea0 4531 else if (r == EMULATION_RESTART)
5cd21917 4532 goto restart;
d2ddd1c4
GN		 4533 else
4534 r = EMULATE_DONE;
f850e2e6 4535
e85d28f8 4536 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
f6e78475 4537 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4538 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4539 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4540 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4541
4542 return r;
de7d789a 4543}
51d8b661 4544EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4545
cf8f70bf 4546int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4547{
cf8f70bf
GN		 4548 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4549 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4550 /* do not return to emulator after return from userspace */
7972995b 4551 vcpu->arch.pio.count = 0;
de7d789a
CO		 4552 return ret;
4553}
cf8f70bf 4554EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4555
8cfdc000
ZA		 4556static void tsc_bad(void *info)
4557{
0a3aee0d 4558 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4559}
4560
4561static void tsc_khz_changed(void *data)
c8076604 4562{
8cfdc000
ZA		 4563 struct cpufreq_freqs *freq = data;
4564 unsigned long khz = 0;
4565
4566 if (data)
4567 khz = freq->new;
4568 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4569 khz = cpufreq_quick_get(raw_smp_processor_id());
4570 if (!khz)
4571 khz = tsc_khz;
0a3aee0d 4572 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4573}
4574
c8076604
GH		 4575static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4576 void *data)
4577{
4578 struct cpufreq_freqs *freq = data;
4579 struct kvm *kvm;
4580 struct kvm_vcpu *vcpu;
4581 int i, send_ipi = 0;
4582
8cfdc000
ZA		 4583 /*
4584 * We allow guests to temporarily run on slowing clocks,
4585 * provided we notify them after, or to run on accelerating
4586 * clocks, provided we notify them before. Thus time never
4587 * goes backwards.
4588 *
4589 * However, we have a problem. We can't atomically update
4590 * the frequency of a given CPU from this function; it is
4591 * merely a notifier, which can be called from any CPU.
4592 * Changing the TSC frequency at arbitrary points in time
4593 * requires a recomputation of local variables related to
4594 * the TSC for each VCPU. We must flag these local variables
4595 * to be updated and be sure the update takes place with the
4596 * new frequency before any guests proceed.
4597 *
4598 * Unfortunately, the combination of hotplug CPU and frequency
4599 * change creates an intractable locking scenario; the order
4600 * of when these callouts happen is undefined with respect to
4601 * CPU hotplug, and they can race with each other. As such,
4602 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4603 * undefined; you can actually have a CPU frequency change take
4604 * place in between the computation of X and the setting of the
4605 * variable. To protect against this problem, all updates of
4606 * the per_cpu tsc_khz variable are done in an interrupt
4607 * protected IPI, and all callers wishing to update the value
4608 * must wait for a synchronous IPI to complete (which is trivial
4609 * if the caller is on the CPU already). This establishes the
4610 * necessary total order on variable updates.
4611 *
4612 * Note that because a guest time update may take place
4613 * anytime after the setting of the VCPU's request bit, the
4614 * correct TSC value must be set before the request. However,
4615 * to ensure the update actually makes it to any guest which
4616 * starts running in hardware virtualization between the set
4617 * and the acquisition of the spinlock, we must also ping the
4618 * CPU after setting the request bit.
4619 *
4620 */
4621
c8076604
GH		 4622 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4623 return 0;
4624 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4625 return 0;
8cfdc000
ZA		 4626
4627 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4628
e935b837 4629 raw_spin_lock(&kvm_lock);
c8076604 4630 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4631 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4632 if (vcpu->cpu != freq->cpu)
4633 continue;
c285545f 4634 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4635 if (vcpu->cpu != smp_processor_id())
8cfdc000 4636 send_ipi = 1;
c8076604
GH		 4637 }
4638 }
e935b837 4639 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4640
4641 if (freq->old < freq->new && send_ipi) {
4642 /*
4643 * We upscale the frequency. Must make the guest
4644 * doesn't see old kvmclock values while running with
4645 * the new frequency, otherwise we risk the guest sees
4646 * time go backwards.
4647 *
4648 * In case we update the frequency for another cpu
4649 * (which might be in guest context) send an interrupt
4650 * to kick the cpu out of guest context. Next time
4651 * guest context is entered kvmclock will be updated,
4652 * so the guest will not see stale values.
4653 */
8cfdc000 4654 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4655 }
4656 return 0;
4657}
4658
4659static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4660 .notifier_call = kvmclock_cpufreq_notifier
4661};
4662
4663static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4664 unsigned long action, void *hcpu)
4665{
4666 unsigned int cpu = (unsigned long)hcpu;
4667
4668 switch (action) {
4669 case CPU_ONLINE:
4670 case CPU_DOWN_FAILED:
4671 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4672 break;
4673 case CPU_DOWN_PREPARE:
4674 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4675 break;
4676 }
4677 return NOTIFY_OK;
4678}
4679
4680static struct notifier_block kvmclock_cpu_notifier_block = {
4681 .notifier_call = kvmclock_cpu_notifier,
4682 .priority = -INT_MAX
c8076604
GH		 4683};
4684
b820cc0c
ZA		 4685static void kvm_timer_init(void)
4686{
4687 int cpu;
4688
c285545f 4689 max_tsc_khz = tsc_khz;
8cfdc000 4690 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4691 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4692#ifdef CONFIG_CPU_FREQ
4693 struct cpufreq_policy policy;
4694 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4695 cpu = get_cpu();
4696 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4697 if (policy.cpuinfo.max_freq)
4698 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4699 put_cpu();
c285545f 4700#endif
b820cc0c
ZA		 4701 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4702 CPUFREQ_TRANSITION_NOTIFIER);
4703 }
c285545f 4704 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4705 for_each_online_cpu(cpu)
4706 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4707}
4708
ff9d07a0
ZY		 4709static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4710
4711static int kvm_is_in_guest(void)
4712{
4713 return percpu_read(current_vcpu) != NULL;
4714}
4715
4716static int kvm_is_user_mode(void)
4717{
4718 int user_mode = 3;
dcf46b94 4719
ff9d07a0
ZY		 4720 if (percpu_read(current_vcpu))
4721 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4722
ff9d07a0
ZY		 4723 return user_mode != 0;
4724}
4725
4726static unsigned long kvm_get_guest_ip(void)
4727{
4728 unsigned long ip = 0;
dcf46b94 4729
ff9d07a0
ZY		 4730 if (percpu_read(current_vcpu))
4731 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4732
ff9d07a0
ZY		 4733 return ip;
4734}
4735
4736static struct perf_guest_info_callbacks kvm_guest_cbs = {
4737 .is_in_guest = kvm_is_in_guest,
4738 .is_user_mode = kvm_is_user_mode,
4739 .get_guest_ip = kvm_get_guest_ip,
4740};
4741
4742void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4743{
4744 percpu_write(current_vcpu, vcpu);
4745}
4746EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4747
4748void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4749{
4750 percpu_write(current_vcpu, NULL);
4751}
4752EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4753
f8c16bba 4754int kvm_arch_init(void *opaque)
043405e1 4755{
b820cc0c 4756 int r;
f8c16bba
ZX		 4757 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4758
f8c16bba
ZX		 4759 if (kvm_x86_ops) {
4760 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4761 r = -EEXIST;
4762 goto out;
f8c16bba
ZX		 4763 }
4764
4765 if (!ops->cpu_has_kvm_support()) {
4766 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4767 r = -EOPNOTSUPP;
4768 goto out;
f8c16bba
ZX		 4769 }
4770 if (ops->disabled_by_bios()) {
4771 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4772 r = -EOPNOTSUPP;
4773 goto out;
f8c16bba
ZX		 4774 }
4775
97db56ce
AK		 4776 r = kvm_mmu_module_init();
4777 if (r)
4778 goto out;
4779
4780 kvm_init_msr_list();
4781
f8c16bba 4782 kvm_x86_ops = ops;
56c6d28a 4783 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4784 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4785 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4786
b820cc0c 4787 kvm_timer_init();
c8076604 4788
ff9d07a0
ZY		 4789 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4790
2acf923e
DC		 4791 if (cpu_has_xsave)
4792 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4793
f8c16bba 4794 return 0;
56c6d28a
ZX		 4795
4796out:
56c6d28a 4797 return r;
043405e1 4798}
8776e519 4799
f8c16bba
ZX		 4800void kvm_arch_exit(void)
4801{
ff9d07a0
ZY		 4802 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4803
888d256e
JK		 4804 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4805 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4806 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4807 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4808 kvm_x86_ops = NULL;
56c6d28a
ZX		 4809 kvm_mmu_module_exit();
4810}
f8c16bba 4811
8776e519
HB		 4812int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4813{
4814 ++vcpu->stat.halt_exits;
4815 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4816 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4817 return 1;
4818 } else {
4819 vcpu->run->exit_reason = KVM_EXIT_HLT;
4820 return 0;
4821 }
4822}
4823EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4824
2f333bcb
MT		 4825static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4826 unsigned long a1)
4827{
4828 if (is_long_mode(vcpu))
4829 return a0;
4830 else
4831 return a0 | ((gpa_t)a1 << 32);
4832}
4833
55cd8e5a
GN		 4834int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4835{
4836 u64 param, ingpa, outgpa, ret;
4837 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4838 bool fast, longmode;
4839 int cs_db, cs_l;
4840
4841 /*
4842 * hypercall generates UD from non zero cpl and real mode
4843 * per HYPER-V spec
4844 */
3eeb3288 4845 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4846 kvm_queue_exception(vcpu, UD_VECTOR);
4847 return 0;
4848 }
4849
4850 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4851 longmode = is_long_mode(vcpu) && cs_l == 1;
4852
4853 if (!longmode) {
ccd46936
GN		 4854 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4855 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4856 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4857 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4858 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4859 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4860 }
4861#ifdef CONFIG_X86_64
4862 else {
4863 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4864 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4865 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4866 }
4867#endif
4868
4869 code = param & 0xffff;
4870 fast = (param >> 16) & 0x1;
4871 rep_cnt = (param >> 32) & 0xfff;
4872 rep_idx = (param >> 48) & 0xfff;
4873
4874 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4875
c25bc163
GN		 4876 switch (code) {
4877 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4878 kvm_vcpu_on_spin(vcpu);
4879 break;
4880 default:
4881 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4882 break;
4883 }
55cd8e5a
GN		 4884
4885 ret = res | (((u64)rep_done & 0xfff) << 32);
4886 if (longmode) {
4887 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4888 } else {
4889 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4890 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4891 }
4892
4893 return 1;
4894}
4895
8776e519
HB		 4896int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4897{
4898 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4899 int r = 1;
8776e519 4900
55cd8e5a
GN		 4901 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4902 return kvm_hv_hypercall(vcpu);
4903
5fdbf976
MT		 4904 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4905 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4906 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4907 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4908 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4909
229456fc 4910 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4911
8776e519
HB		 4912 if (!is_long_mode(vcpu)) {
4913 nr &= 0xFFFFFFFF;
4914 a0 &= 0xFFFFFFFF;
4915 a1 &= 0xFFFFFFFF;
4916 a2 &= 0xFFFFFFFF;
4917 a3 &= 0xFFFFFFFF;
4918 }
4919
07708c4a
JK		 4920 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4921 ret = -KVM_EPERM;
4922 goto out;
4923 }
4924
8776e519 4925 switch (nr) {
b93463aa
AK		 4926 case KVM_HC_VAPIC_POLL_IRQ:
4927 ret = 0;
4928 break;
2f333bcb
MT		 4929 case KVM_HC_MMU_OP:
4930 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4931 break;
8776e519
HB		 4932 default:
4933 ret = -KVM_ENOSYS;
4934 break;
4935 }
07708c4a 4936out:
5fdbf976 4937 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4938 ++vcpu->stat.hypercalls;
2f333bcb 4939 return r;
8776e519
HB		 4940}
4941EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4942
4943int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4944{
4945 char instruction[3];
5fdbf976 4946 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4947
8776e519
HB		 4948 /*
4949 * Blow out the MMU to ensure that no other VCPU has an active mapping
4950 * to ensure that the updated hypercall appears atomically across all
4951 * VCPUs.
4952 */
4953 kvm_mmu_zap_all(vcpu->kvm);
4954
8776e519 4955 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4956
8fe681e9 4957 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4958}
4959
8776e519
HB		 4960void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4961{
89a27f4d 4962 struct desc_ptr dt = { limit, base };
8776e519
HB		 4963
4964 kvm_x86_ops->set_gdt(vcpu, &dt);
4965}
4966
4967void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4968{
89a27f4d 4969 struct desc_ptr dt = { limit, base };
8776e519
HB		 4970
4971 kvm_x86_ops->set_idt(vcpu, &dt);
4972}
4973
07716717
DK		 4974static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4975{
ad312c7c
ZX		 4976 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4977 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4978
4979 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4980 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4981 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4982 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4983 if (ej->function == e->function) {
4984 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4985 return j;
4986 }
4987 }
4988 return 0; /* silence gcc, even though control never reaches here */
4989}
4990
4991/* find an entry with matching function, matching index (if needed), and that
4992 * should be read next (if it's stateful) */
4993static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4994 u32 function, u32 index)
4995{
4996 if (e->function != function)
4997 return 0;
4998 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4999 return 0;
5000 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5001 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5002 return 0;
5003 return 1;
5004}
5005
d8017474
AG		 5006struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5007 u32 function, u32 index)
8776e519
HB		 5008{
5009 int i;
d8017474 5010 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5011
ad312c7c 5012 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5013 struct kvm_cpuid_entry2 *e;
5014
ad312c7c 5015 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5016 if (is_matching_cpuid_entry(e, function, index)) {
5017 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5018 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5019 best = e;
5020 break;
5021 }
8776e519 5022 }
d8017474
AG		 5023 return best;
5024}
0e851880 5025EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5026
82725b20
DE		 5027int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5028{
5029 struct kvm_cpuid_entry2 *best;
5030
f7a71197
AK		 5031 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5032 if (!best || best->eax < 0x80000008)
5033 goto not_found;
82725b20
DE		 5034 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5035 if (best)
5036 return best->eax & 0xff;
f7a71197 5037not_found:
82725b20
DE		 5038 return 36;
5039}
5040
bd22f5cf
AP		 5041/*
5042 * If no match is found, check whether we exceed the vCPU's limit
5043 * and return the content of the highest valid _standard_ leaf instead.
5044 * This is to satisfy the CPUID specification.
5045 */
5046static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5047 u32 function, u32 index)
5048{
5049 struct kvm_cpuid_entry2 *maxlevel;
5050
5051 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5052 if (!maxlevel || maxlevel->eax >= function)
5053 return NULL;
5054 if (function & 0x80000000) {
5055 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5056 if (!maxlevel)
5057 return NULL;
5058 }
5059 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5060}
5061
d8017474
AG		 5062void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5063{
5064 u32 function, index;
5065 struct kvm_cpuid_entry2 *best;
5066
5067 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5068 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5069 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5070 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5071 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5072 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5073 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5074
5075 if (!best)
5076 best = check_cpuid_limit(vcpu, function, index);
5077
8776e519 5078 if (best) {
5fdbf976
MT		 5079 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5080 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5081 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5082 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5083 }
8776e519 5084 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5085 trace_kvm_cpuid(function,
5086 kvm_register_read(vcpu, VCPU_REGS_RAX),
5087 kvm_register_read(vcpu, VCPU_REGS_RBX),
5088 kvm_register_read(vcpu, VCPU_REGS_RCX),
5089 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5090}
5091EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5092
b6c7a5dc
HB		 5093/*
5094 * Check if userspace requested an interrupt window, and that the
5095 * interrupt window is open.
5096 *
5097 * No need to exit to userspace if we already have an interrupt queued.
5098 */
851ba692 5099static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5100{
8061823a 5101 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5102 vcpu->run->request_interrupt_window &&
5df56646 5103 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5104}
5105
851ba692 5106static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5107{
851ba692
AK		 5108 struct kvm_run *kvm_run = vcpu->run;
5109
91586a3b 5110 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5111 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5112 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5113 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5114 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5115 else
b6c7a5dc 5116 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5117 kvm_arch_interrupt_allowed(vcpu) &&
5118 !kvm_cpu_has_interrupt(vcpu) &&
5119 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5120}
5121
b93463aa
AK		 5122static void vapic_enter(struct kvm_vcpu *vcpu)
5123{
5124 struct kvm_lapic *apic = vcpu->arch.apic;
5125 struct page *page;
5126
5127 if (!apic || !apic->vapic_addr)
5128 return;
5129
5130 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5131
5132 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5133}
5134
5135static void vapic_exit(struct kvm_vcpu *vcpu)
5136{
5137 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5138 int idx;
b93463aa
AK		 5139
5140 if (!apic || !apic->vapic_addr)
5141 return;
5142
f656ce01 5143 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5144 kvm_release_page_dirty(apic->vapic_page);
5145 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5146 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5147}
5148
95ba8273
GN		 5149static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5150{
5151 int max_irr, tpr;
5152
5153 if (!kvm_x86_ops->update_cr8_intercept)
5154 return;
5155
88c808fd
AK		 5156 if (!vcpu->arch.apic)
5157 return;
5158
8db3baa2
GN		 5159 if (!vcpu->arch.apic->vapic_addr)
5160 max_irr = kvm_lapic_find_highest_irr(vcpu);
5161 else
5162 max_irr = -1;
95ba8273
GN		 5163
5164 if (max_irr != -1)
5165 max_irr >>= 4;
5166
5167 tpr = kvm_lapic_get_cr8(vcpu);
5168
5169 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5170}
5171
851ba692 5172static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5173{
5174 /* try to reinject previous events if any */
b59bb7bd 5175 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5176 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5177 vcpu->arch.exception.has_error_code,
5178 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5179 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5180 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5181 vcpu->arch.exception.error_code,
5182 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5183 return;
5184 }
5185
95ba8273
GN		 5186 if (vcpu->arch.nmi_injected) {
5187 kvm_x86_ops->set_nmi(vcpu);
5188 return;
5189 }
5190
5191 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5192 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5193 return;
5194 }
5195
5196 /* try to inject new event if pending */
5197 if (vcpu->arch.nmi_pending) {
5198 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5199 vcpu->arch.nmi_pending = false;
5200 vcpu->arch.nmi_injected = true;
5201 kvm_x86_ops->set_nmi(vcpu);
5202 }
5203 } else if (kvm_cpu_has_interrupt(vcpu)) {
5204 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5205 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5206 false);
5207 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5208 }
5209 }
5210}
5211
2acf923e
DC		 5212static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5213{
5214 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5215 !vcpu->guest_xcr0_loaded) {
5216 /* kvm_set_xcr() also depends on this */
5217 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5218 vcpu->guest_xcr0_loaded = 1;
5219 }
5220}
5221
5222static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5223{
5224 if (vcpu->guest_xcr0_loaded) {
5225 if (vcpu->arch.xcr0 != host_xcr0)
5226 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5227 vcpu->guest_xcr0_loaded = 0;
5228 }
5229}
5230
851ba692 5231static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5232{
5233 int r;
1499e54a 5234 bool nmi_pending;
6a8b1d13 5235 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5236 vcpu->run->request_interrupt_window;
b6c7a5dc 5237
3e007509 5238 if (vcpu->requests) {
a8eeb04a 5239 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5240 kvm_mmu_unload(vcpu);
a8eeb04a 5241 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5242 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5243 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5244 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5245 if (unlikely(r))
5246 goto out;
5247 }
a8eeb04a 5248 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5249 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5250 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5251 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5252 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5253 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5254 r = 0;
5255 goto out;
5256 }
a8eeb04a 5257 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5258 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5259 r = 0;
5260 goto out;
5261 }
a8eeb04a 5262 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5263 vcpu->fpu_active = 0;
5264 kvm_x86_ops->fpu_deactivate(vcpu);
5265 }
af585b92
GN		 5266 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5267 /* Page is swapped out. Do synthetic halt */
5268 vcpu->arch.apf.halted = true;
5269 r = 1;
5270 goto out;
5271 }
2f52d58c 5272 }
b93463aa 5273
3e007509
AK		 5274 r = kvm_mmu_reload(vcpu);
5275 if (unlikely(r))
5276 goto out;
5277
1499e54a
GN		 5278 /*
5279 * An NMI can be injected between local nmi_pending read and
5280 * vcpu->arch.nmi_pending read inside inject_pending_event().
5281 * But in that case, KVM_REQ_EVENT will be set, which makes
5282 * the race described above benign.
5283 */
5284 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5285
b463a6f7
AK		 5286 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5287 inject_pending_event(vcpu);
5288
5289 /* enable NMI/IRQ window open exits if needed */
1499e54a 5290 if (nmi_pending)
b463a6f7
AK		 5291 kvm_x86_ops->enable_nmi_window(vcpu);
5292 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5293 kvm_x86_ops->enable_irq_window(vcpu);
5294
5295 if (kvm_lapic_enabled(vcpu)) {
5296 update_cr8_intercept(vcpu);
5297 kvm_lapic_sync_to_vapic(vcpu);
5298 }
5299 }
5300
b6c7a5dc
HB		 5301 preempt_disable();
5302
5303 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5304 if (vcpu->fpu_active)
5305 kvm_load_guest_fpu(vcpu);
2acf923e 5306 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5307
6b7e2d09
XG		 5308 vcpu->mode = IN_GUEST_MODE;
5309
5310 /* We should set ->mode before check ->requests,
5311 * see the comment in make_all_cpus_request.
5312 */
5313 smp_mb();
b6c7a5dc 5314
d94e1dc9 5315 local_irq_disable();
32f88400 5316
6b7e2d09 5317 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5318 || need_resched() || signal_pending(current)) {
6b7e2d09 5319 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5320 smp_wmb();
6c142801
AK		 5321 local_irq_enable();
5322 preempt_enable();
b463a6f7 5323 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5324 r = 1;
5325 goto out;
5326 }
5327
f656ce01 5328 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5329
b6c7a5dc
HB		 5330 kvm_guest_enter();
5331
42dbaa5a 5332 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5333 set_debugreg(0, 7);
5334 set_debugreg(vcpu->arch.eff_db[0], 0);
5335 set_debugreg(vcpu->arch.eff_db[1], 1);
5336 set_debugreg(vcpu->arch.eff_db[2], 2);
5337 set_debugreg(vcpu->arch.eff_db[3], 3);
5338 }
b6c7a5dc 5339
229456fc 5340 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5341 kvm_x86_ops->run(vcpu);
b6c7a5dc 5342
24f1e32c
FW		 5343 /*
5344 * If the guest has used debug registers, at least dr7
5345 * will be disabled while returning to the host.
5346 * If we don't have active breakpoints in the host, we don't
5347 * care about the messed up debug address registers. But if
5348 * we have some of them active, restore the old state.
5349 */
59d8eb53 5350 if (hw_breakpoint_active())
24f1e32c 5351 hw_breakpoint_restore();
42dbaa5a 5352
1d5f066e
ZA		 5353 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5354
6b7e2d09 5355 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5356 smp_wmb();
b6c7a5dc
HB		 5357 local_irq_enable();
5358
5359 ++vcpu->stat.exits;
5360
5361 /*
5362 * We must have an instruction between local_irq_enable() and
5363 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5364 * the interrupt shadow. The stat.exits increment will do nicely.
5365 * But we need to prevent reordering, hence this barrier():
5366 */
5367 barrier();
5368
5369 kvm_guest_exit();
5370
5371 preempt_enable();
5372
f656ce01 5373 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5374
b6c7a5dc
HB		 5375 /*
5376 * Profile KVM exit RIPs:
5377 */
5378 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5379 unsigned long rip = kvm_rip_read(vcpu);
5380 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5381 }
5382
298101da 5383
b93463aa
AK		 5384 kvm_lapic_sync_from_vapic(vcpu);
5385
851ba692 5386 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5387out:
5388 return r;
5389}
b6c7a5dc 5390
09cec754 5391
851ba692 5392static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5393{
5394 int r;
f656ce01 5395 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5396
5397 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5398 pr_debug("vcpu %d received sipi with vector # %x\n",
5399 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5400 kvm_lapic_reset(vcpu);
5f179287 5401 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5402 if (r)
5403 return r;
5404 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5405 }
5406
f656ce01 5407 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5408 vapic_enter(vcpu);
5409
5410 r = 1;
5411 while (r > 0) {
af585b92
GN		 5412 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5413 !vcpu->arch.apf.halted)
851ba692 5414 r = vcpu_enter_guest(vcpu);
d7690175 5415 else {
f656ce01 5416 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5417 kvm_vcpu_block(vcpu);
f656ce01 5418 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5419 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5420 {
5421 switch(vcpu->arch.mp_state) {
5422 case KVM_MP_STATE_HALTED:
d7690175 5423 vcpu->arch.mp_state =
09cec754
GN		 5424 KVM_MP_STATE_RUNNABLE;
5425 case KVM_MP_STATE_RUNNABLE:
af585b92 5426 vcpu->arch.apf.halted = false;
09cec754
GN		 5427 break;
5428 case KVM_MP_STATE_SIPI_RECEIVED:
5429 default:
5430 r = -EINTR;
5431 break;
5432 }
5433 }
d7690175
MT		 5434 }
5435
09cec754
GN		 5436 if (r <= 0)
5437 break;
5438
5439 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5440 if (kvm_cpu_has_pending_timer(vcpu))
5441 kvm_inject_pending_timer_irqs(vcpu);
5442
851ba692 5443 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5444 r = -EINTR;
851ba692 5445 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5446 ++vcpu->stat.request_irq_exits;
5447 }
af585b92
GN		 5448
5449 kvm_check_async_pf_completion(vcpu);
5450
09cec754
GN		 5451 if (signal_pending(current)) {
5452 r = -EINTR;
851ba692 5453 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5454 ++vcpu->stat.signal_exits;
5455 }
5456 if (need_resched()) {
f656ce01 5457 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5458 kvm_resched(vcpu);
f656ce01 5459 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5460 }
b6c7a5dc
HB		 5461 }
5462
f656ce01 5463 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5464
b93463aa
AK		 5465 vapic_exit(vcpu);
5466
b6c7a5dc
HB		 5467 return r;
5468}
5469
5287f194
AK		 5470static int complete_mmio(struct kvm_vcpu *vcpu)
5471{
5472 struct kvm_run *run = vcpu->run;
5473 int r;
5474
5475 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5476 return 1;
5477
5478 if (vcpu->mmio_needed) {
5287f194 5479 vcpu->mmio_needed = 0;
cef4dea0
AK		 5480 if (!vcpu->mmio_is_write)
5481 memcpy(vcpu->mmio_data, run->mmio.data, 8);
5482 vcpu->mmio_index += 8;
5483 if (vcpu->mmio_index < vcpu->mmio_size) {
5484 run->exit_reason = KVM_EXIT_MMIO;
5485 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5486 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5487 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5488 run->mmio.is_write = vcpu->mmio_is_write;
5489 vcpu->mmio_needed = 1;
5490 return 0;
5491 }
5492 if (vcpu->mmio_is_write)
5493 return 1;
5494 vcpu->mmio_read_completed = 1;
5287f194
AK		 5495 }
5496 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5497 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5498 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5499 if (r != EMULATE_DONE)
5500 return 0;
5501 return 1;
5502}
5503
b6c7a5dc
HB		 5504int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5505{
5506 int r;
5507 sigset_t sigsaved;
5508
e5c30142
AK		 5509 if (!tsk_used_math(current) && init_fpu(current))
5510 return -ENOMEM;
5511
ac9f6dc0
AK		 5512 if (vcpu->sigset_active)
5513 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5514
a4535290 5515 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5516 kvm_vcpu_block(vcpu);
d7690175 5517 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5518 r = -EAGAIN;
5519 goto out;
b6c7a5dc
HB		 5520 }
5521
b6c7a5dc 5522 /* re-sync apic's tpr */
eea1cff9
AP		 5523 if (!irqchip_in_kernel(vcpu->kvm)) {
5524 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5525 r = -EINVAL;
5526 goto out;
5527 }
5528 }
b6c7a5dc 5529
5287f194
AK		 5530 r = complete_mmio(vcpu);
5531 if (r <= 0)
5532 goto out;
5533
5fdbf976
MT		 5534 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5535 kvm_register_write(vcpu, VCPU_REGS_RAX,
5536 kvm_run->hypercall.ret);
b6c7a5dc 5537
851ba692 5538 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5539
5540out:
f1d86e46 5541 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5542 if (vcpu->sigset_active)
5543 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5544
b6c7a5dc
HB		 5545 return r;
5546}
5547
5548int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5549{
5fdbf976
MT		 5550 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5551 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5552 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5553 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5554 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5555 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5556 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5557 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5558#ifdef CONFIG_X86_64
5fdbf976
MT		 5559 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5560 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5561 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5562 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5563 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5564 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5565 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5566 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5567#endif
5568
5fdbf976 5569 regs->rip = kvm_rip_read(vcpu);
91586a3b 5570 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5571
b6c7a5dc
HB		 5572 return 0;
5573}
5574
5575int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5576{
5fdbf976
MT		 5577 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5578 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5579 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5580 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5581 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5582 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5583 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5584 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5585#ifdef CONFIG_X86_64
5fdbf976
MT		 5586 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5587 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5588 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5589 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5590 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5591 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5592 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5593 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5594#endif
5595
5fdbf976 5596 kvm_rip_write(vcpu, regs->rip);
91586a3b 5597 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5598
b4f14abd
JK		 5599 vcpu->arch.exception.pending = false;
5600
3842d135
AK		 5601 kvm_make_request(KVM_REQ_EVENT, vcpu);
5602
b6c7a5dc
HB		 5603 return 0;
5604}
5605
b6c7a5dc
HB		 5606void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5607{
5608 struct kvm_segment cs;
5609
3e6e0aab 5610 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5611 *db = cs.db;
5612 *l = cs.l;
5613}
5614EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5615
5616int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5617 struct kvm_sregs *sregs)
5618{
89a27f4d 5619 struct desc_ptr dt;
b6c7a5dc 5620
3e6e0aab
GT		 5621 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5622 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5623 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5624 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5625 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5626 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5627
3e6e0aab
GT		 5628 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5629 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5630
5631 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5632 sregs->idt.limit = dt.size;
5633 sregs->idt.base = dt.address;
b6c7a5dc 5634 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5635 sregs->gdt.limit = dt.size;
5636 sregs->gdt.base = dt.address;
b6c7a5dc 5637
4d4ec087 5638 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5639 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5640 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5641 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5642 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5643 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5644 sregs->apic_base = kvm_get_apic_base(vcpu);
5645
923c61bb 5646 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5647
36752c9b 5648 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5649 set_bit(vcpu->arch.interrupt.nr,
5650 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5651
b6c7a5dc
HB		 5652 return 0;
5653}
5654
62d9f0db
MT		 5655int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5656 struct kvm_mp_state *mp_state)
5657{
62d9f0db 5658 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5659 return 0;
5660}
5661
5662int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5663 struct kvm_mp_state *mp_state)
5664{
62d9f0db 5665 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5666 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5667 return 0;
5668}
5669
e269fb21
JK		 5670int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5671 bool has_error_code, u32 error_code)
b6c7a5dc 5672{
4d2179e1 5673 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5674 int ret;
e01c2426 5675
8ec4722d 5676 init_emulate_ctxt(vcpu);
c697518a 5677
9aabc88f 5678 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5679 tss_selector, reason, has_error_code,
5680 error_code);
c697518a 5681
c697518a 5682 if (ret)
19d04437 5683 return EMULATE_FAIL;
37817f29 5684
4d2179e1 5685 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5686 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 5687 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5688 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5689 return EMULATE_DONE;
37817f29
IE		 5690}
5691EXPORT_SYMBOL_GPL(kvm_task_switch);
5692
b6c7a5dc
HB		 5693int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5694 struct kvm_sregs *sregs)
5695{
5696 int mmu_reset_needed = 0;
63f42e02 5697 int pending_vec, max_bits, idx;
89a27f4d 5698 struct desc_ptr dt;
b6c7a5dc 5699
89a27f4d
GN		 5700 dt.size = sregs->idt.limit;
5701 dt.address = sregs->idt.base;
b6c7a5dc 5702 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5703 dt.size = sregs->gdt.limit;
5704 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5705 kvm_x86_ops->set_gdt(vcpu, &dt);
5706
ad312c7c 5707 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5708 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5709 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5710 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5711
2d3ad1f4 5712 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5713
f6801dff 5714 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5715 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5716 kvm_set_apic_base(vcpu, sregs->apic_base);
5717
4d4ec087 5718 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5719 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5720 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5721
fc78f519 5722 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5723 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5724 if (sregs->cr4 & X86_CR4_OSXSAVE)
5725 update_cpuid(vcpu);
63f42e02
XG		 5726
5727 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5728 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5729 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5730 mmu_reset_needed = 1;
5731 }
63f42e02 5732 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5733
5734 if (mmu_reset_needed)
5735 kvm_mmu_reset_context(vcpu);
5736
923c61bb
GN		 5737 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5738 pending_vec = find_first_bit(
5739 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5740 if (pending_vec < max_bits) {
66fd3f7f 5741 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5742 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5743 }
5744
3e6e0aab
GT		 5745 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5746 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5747 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5748 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5749 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5750 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5751
3e6e0aab
GT		 5752 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5753 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5754
5f0269f5
ME		 5755 update_cr8_intercept(vcpu);
5756
9c3e4aab 5757 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5758 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5759 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5760 !is_protmode(vcpu))
9c3e4aab
MT		 5761 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5762
3842d135
AK		 5763 kvm_make_request(KVM_REQ_EVENT, vcpu);
5764
b6c7a5dc
HB		 5765 return 0;
5766}
5767
d0bfb940
JK		 5768int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5769 struct kvm_guest_debug *dbg)
b6c7a5dc 5770{
355be0b9 5771 unsigned long rflags;
ae675ef0 5772 int i, r;
b6c7a5dc 5773
4f926bf2
JK		 5774 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5775 r = -EBUSY;
5776 if (vcpu->arch.exception.pending)
2122ff5e 5777 goto out;
4f926bf2
JK		 5778 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5779 kvm_queue_exception(vcpu, DB_VECTOR);
5780 else
5781 kvm_queue_exception(vcpu, BP_VECTOR);
5782 }
5783
91586a3b
JK		 5784 /*
5785 * Read rflags as long as potentially injected trace flags are still
5786 * filtered out.
5787 */
5788 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5789
5790 vcpu->guest_debug = dbg->control;
5791 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5792 vcpu->guest_debug = 0;
5793
5794 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5795 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5796 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5797 vcpu->arch.switch_db_regs =
5798 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5799 } else {
5800 for (i = 0; i < KVM_NR_DB_REGS; i++)
5801 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5802 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5803 }
5804
f92653ee
JK		 5805 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5806 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5807 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5808
91586a3b
JK		 5809 /*
5810 * Trigger an rflags update that will inject or remove the trace
5811 * flags.
5812 */
5813 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5814
355be0b9 5815 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5816
4f926bf2 5817 r = 0;
d0bfb940 5818
2122ff5e 5819out:
b6c7a5dc
HB		 5820
5821 return r;
5822}
5823
8b006791
ZX		 5824/*
5825 * Translate a guest virtual address to a guest physical address.
5826 */
5827int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5828 struct kvm_translation *tr)
5829{
5830 unsigned long vaddr = tr->linear_address;
5831 gpa_t gpa;
f656ce01 5832 int idx;
8b006791 5833
f656ce01 5834 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5835 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5836 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5837 tr->physical_address = gpa;
5838 tr->valid = gpa != UNMAPPED_GVA;
5839 tr->writeable = 1;
5840 tr->usermode = 0;
8b006791
ZX		 5841
5842 return 0;
5843}
5844
d0752060
HB		 5845int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5846{
98918833
SY		 5847 struct i387_fxsave_struct *fxsave =
5848 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5849
d0752060
HB		 5850 memcpy(fpu->fpr, fxsave->st_space, 128);
5851 fpu->fcw = fxsave->cwd;
5852 fpu->fsw = fxsave->swd;
5853 fpu->ftwx = fxsave->twd;
5854 fpu->last_opcode = fxsave->fop;
5855 fpu->last_ip = fxsave->rip;
5856 fpu->last_dp = fxsave->rdp;
5857 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5858
d0752060
HB		 5859 return 0;
5860}
5861
5862int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5863{
98918833
SY		 5864 struct i387_fxsave_struct *fxsave =
5865 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5866
d0752060
HB		 5867 memcpy(fxsave->st_space, fpu->fpr, 128);
5868 fxsave->cwd = fpu->fcw;
5869 fxsave->swd = fpu->fsw;
5870 fxsave->twd = fpu->ftwx;
5871 fxsave->fop = fpu->last_opcode;
5872 fxsave->rip = fpu->last_ip;
5873 fxsave->rdp = fpu->last_dp;
5874 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5875
d0752060
HB		 5876 return 0;
5877}
5878
10ab25cd 5879int fx_init(struct kvm_vcpu *vcpu)
d0752060 5880{
10ab25cd
JK		 5881 int err;
5882
5883 err = fpu_alloc(&vcpu->arch.guest_fpu);
5884 if (err)
5885 return err;
5886
98918833 5887 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5888
2acf923e
DC		 5889 /*
5890 * Ensure guest xcr0 is valid for loading
5891 */
5892 vcpu->arch.xcr0 = XSTATE_FP;
5893
ad312c7c 5894 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5895
5896 return 0;
d0752060
HB		 5897}
5898EXPORT_SYMBOL_GPL(fx_init);
5899
98918833
SY		 5900static void fx_free(struct kvm_vcpu *vcpu)
5901{
5902 fpu_free(&vcpu->arch.guest_fpu);
5903}
5904
d0752060
HB		 5905void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5906{
2608d7a1 5907 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5908 return;
5909
2acf923e
DC		 5910 /*
5911 * Restore all possible states in the guest,
5912 * and assume host would use all available bits.
5913 * Guest xcr0 would be loaded later.
5914 */
5915 kvm_put_guest_xcr0(vcpu);
d0752060 5916 vcpu->guest_fpu_loaded = 1;
7cf30855 5917 unlazy_fpu(current);
98918833 5918 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5919 trace_kvm_fpu(1);
d0752060 5920}
d0752060
HB		 5921
5922void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5923{
2acf923e
DC		 5924 kvm_put_guest_xcr0(vcpu);
5925
d0752060
HB		 5926 if (!vcpu->guest_fpu_loaded)
5927 return;
5928
5929 vcpu->guest_fpu_loaded = 0;
98918833 5930 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5931 ++vcpu->stat.fpu_reload;
a8eeb04a 5932 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5933 trace_kvm_fpu(0);
d0752060 5934}
e9b11c17
ZX		 5935
5936void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5937{
12f9a48f 5938 kvmclock_reset(vcpu);
7f1ea208 5939
f5f48ee1 5940 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5941 fx_free(vcpu);
e9b11c17
ZX		 5942 kvm_x86_ops->vcpu_free(vcpu);
5943}
5944
5945struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5946 unsigned int id)
5947{
6755bae8
ZA		 5948 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5949 printk_once(KERN_WARNING
5950 "kvm: SMP vm created on host with unstable TSC; "
5951 "guest TSC will not be reliable\n");
26e5215f
AK		 5952 return kvm_x86_ops->vcpu_create(kvm, id);
5953}
e9b11c17 5954
26e5215f
AK		 5955int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5956{
5957 int r;
e9b11c17 5958
0bed3b56 5959 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5960 vcpu_load(vcpu);
5961 r = kvm_arch_vcpu_reset(vcpu);
5962 if (r == 0)
5963 r = kvm_mmu_setup(vcpu);
5964 vcpu_put(vcpu);
5965 if (r < 0)
5966 goto free_vcpu;
5967
26e5215f 5968 return 0;
e9b11c17
ZX		 5969free_vcpu:
5970 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5971 return r;
e9b11c17
ZX		 5972}
5973
d40ccc62 5974void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5975{
344d9588
GN		 5976 vcpu->arch.apf.msr_val = 0;
5977
e9b11c17
ZX		 5978 vcpu_load(vcpu);
5979 kvm_mmu_unload(vcpu);
5980 vcpu_put(vcpu);
5981
98918833 5982 fx_free(vcpu);
e9b11c17
ZX		 5983 kvm_x86_ops->vcpu_free(vcpu);
5984}
5985
5986int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5987{
448fa4a9
JK		 5988 vcpu->arch.nmi_pending = false;
5989 vcpu->arch.nmi_injected = false;
5990
42dbaa5a
JK		 5991 vcpu->arch.switch_db_regs = 0;
5992 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5993 vcpu->arch.dr6 = DR6_FIXED_1;
5994 vcpu->arch.dr7 = DR7_FIXED_1;
5995
3842d135 5996 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5997 vcpu->arch.apf.msr_val = 0;
3842d135 5998
12f9a48f
GC		 5999 kvmclock_reset(vcpu);
6000
af585b92
GN		 6001 kvm_clear_async_pf_completion_queue(vcpu);
6002 kvm_async_pf_hash_reset(vcpu);
6003 vcpu->arch.apf.halted = false;
3842d135 6004
e9b11c17
ZX		 6005 return kvm_x86_ops->vcpu_reset(vcpu);
6006}
6007
10474ae8 6008int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6009{
ca84d1a2
ZA		 6010 struct kvm *kvm;
6011 struct kvm_vcpu *vcpu;
6012 int i;
18863bdd
AK		 6013
6014 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6015 list_for_each_entry(kvm, &vm_list, vm_list)
6016 kvm_for_each_vcpu(i, vcpu, kvm)
6017 if (vcpu->cpu == smp_processor_id())
c285545f 6018 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6019 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6020}
6021
6022void kvm_arch_hardware_disable(void *garbage)
6023{
6024 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6025 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6026}
6027
6028int kvm_arch_hardware_setup(void)
6029{
6030 return kvm_x86_ops->hardware_setup();
6031}
6032
6033void kvm_arch_hardware_unsetup(void)
6034{
6035 kvm_x86_ops->hardware_unsetup();
6036}
6037
6038void kvm_arch_check_processor_compat(void *rtn)
6039{
6040 kvm_x86_ops->check_processor_compatibility(rtn);
6041}
6042
6043int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6044{
6045 struct page *page;
6046 struct kvm *kvm;
6047 int r;
6048
6049 BUG_ON(vcpu->kvm == NULL);
6050 kvm = vcpu->kvm;
6051
9aabc88f 6052 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6053 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6054 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6055 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6056 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6057 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6058 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6059 else
a4535290 6060 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6061
6062 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6063 if (!page) {
6064 r = -ENOMEM;
6065 goto fail;
6066 }
ad312c7c 6067 vcpu->arch.pio_data = page_address(page);
e9b11c17 6068
1e993611 6069 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6070
e9b11c17
ZX		 6071 r = kvm_mmu_create(vcpu);
6072 if (r < 0)
6073 goto fail_free_pio_data;
6074
6075 if (irqchip_in_kernel(kvm)) {
6076 r = kvm_create_lapic(vcpu);
6077 if (r < 0)
6078 goto fail_mmu_destroy;
6079 }
6080
890ca9ae
HY		 6081 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6082 GFP_KERNEL);
6083 if (!vcpu->arch.mce_banks) {
6084 r = -ENOMEM;
443c39bc 6085 goto fail_free_lapic;
890ca9ae
HY		 6086 }
6087 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6088
f5f48ee1
SY		 6089 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6090 goto fail_free_mce_banks;
6091
af585b92
GN		 6092 kvm_async_pf_hash_reset(vcpu);
6093
e9b11c17 6094 return 0;
f5f48ee1
SY		 6095fail_free_mce_banks:
6096 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6097fail_free_lapic:
6098 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6099fail_mmu_destroy:
6100 kvm_mmu_destroy(vcpu);
6101fail_free_pio_data:
ad312c7c 6102 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6103fail:
6104 return r;
6105}
6106
6107void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6108{
f656ce01
MT		 6109 int idx;
6110
36cb93fd 6111 kfree(vcpu->arch.mce_banks);
e9b11c17 6112 kvm_free_lapic(vcpu);
f656ce01 6113 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6114 kvm_mmu_destroy(vcpu);
f656ce01 6115 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6116 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6117}
d19a9cd2 6118
d89f5eff 6119int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6120{
f05e70ac 6121 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6122 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6123
5550af4d
SY		 6124 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6125 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6126
038f8c11 6127 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6128
d89f5eff 6129 return 0;
d19a9cd2
ZX		 6130}
6131
6132static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6133{
6134 vcpu_load(vcpu);
6135 kvm_mmu_unload(vcpu);
6136 vcpu_put(vcpu);
6137}
6138
6139static void kvm_free_vcpus(struct kvm *kvm)
6140{
6141 unsigned int i;
988a2cae 6142 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6143
6144 /*
6145 * Unpin any mmu pages first.
6146 */
af585b92
GN		 6147 kvm_for_each_vcpu(i, vcpu, kvm) {
6148 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6149 kvm_unload_vcpu_mmu(vcpu);
af585b92 6150 }
988a2cae
GN		 6151 kvm_for_each_vcpu(i, vcpu, kvm)
6152 kvm_arch_vcpu_free(vcpu);
6153
6154 mutex_lock(&kvm->lock);
6155 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6156 kvm->vcpus[i] = NULL;
d19a9cd2 6157
988a2cae
GN		 6158 atomic_set(&kvm->online_vcpus, 0);
6159 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6160}
6161
ad8ba2cd
SY		 6162void kvm_arch_sync_events(struct kvm *kvm)
6163{
ba4cef31 6164 kvm_free_all_assigned_devices(kvm);
aea924f6 6165 kvm_free_pit(kvm);
ad8ba2cd
SY		 6166}
6167
d19a9cd2
ZX		 6168void kvm_arch_destroy_vm(struct kvm *kvm)
6169{
6eb55818 6170 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6171 kfree(kvm->arch.vpic);
6172 kfree(kvm->arch.vioapic);
d19a9cd2 6173 kvm_free_vcpus(kvm);
3d45830c
AK		 6174 if (kvm->arch.apic_access_page)
6175 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6176 if (kvm->arch.ept_identity_pagetable)
6177 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6178}
0de10343 6179
f7784b8e
MT		 6180int kvm_arch_prepare_memory_region(struct kvm *kvm,
6181 struct kvm_memory_slot *memslot,
0de10343 6182 struct kvm_memory_slot old,
f7784b8e 6183 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6184 int user_alloc)
6185{
f7784b8e 6186 int npages = memslot->npages;
7ac77099
AK		 6187 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6188
6189 /* Prevent internal slot pages from being moved by fork()/COW. */
6190 if (memslot->id >= KVM_MEMORY_SLOTS)
6191 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6192
6193 /*To keep backward compatibility with older userspace,
6194 *x86 needs to hanlde !user_alloc case.
6195 */
6196 if (!user_alloc) {
6197 if (npages && !old.rmap) {
604b38ac
AA		 6198 unsigned long userspace_addr;
6199
72dc67a6 6200 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6201 userspace_addr = do_mmap(NULL, 0,
6202 npages * PAGE_SIZE,
6203 PROT_READ | PROT_WRITE,
7ac77099 6204 map_flags,
604b38ac 6205 0);
72dc67a6 6206 up_write(&current->mm->mmap_sem);
0de10343 6207
604b38ac
AA		 6208 if (IS_ERR((void *)userspace_addr))
6209 return PTR_ERR((void *)userspace_addr);
6210
604b38ac 6211 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6212 }
6213 }
6214
f7784b8e
MT		 6215
6216 return 0;
6217}
6218
6219void kvm_arch_commit_memory_region(struct kvm *kvm,
6220 struct kvm_userspace_memory_region *mem,
6221 struct kvm_memory_slot old,
6222 int user_alloc)
6223{
6224
48c0e4e9 6225 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6226
6227 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6228 int ret;
6229
6230 down_write(&current->mm->mmap_sem);
6231 ret = do_munmap(current->mm, old.userspace_addr,
6232 old.npages * PAGE_SIZE);
6233 up_write(&current->mm->mmap_sem);
6234 if (ret < 0)
6235 printk(KERN_WARNING
6236 "kvm_vm_ioctl_set_memory_region: "
6237 "failed to munmap memory\n");
6238 }
6239
48c0e4e9
XG		 6240 if (!kvm->arch.n_requested_mmu_pages)
6241 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6242
7c8a83b7 6243 spin_lock(&kvm->mmu_lock);
48c0e4e9 6244 if (nr_mmu_pages)
0de10343 6245 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6246 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6247 spin_unlock(&kvm->mmu_lock);
0de10343 6248}
1d737c8a 6249
34d4cb8f
MT		 6250void kvm_arch_flush_shadow(struct kvm *kvm)
6251{
6252 kvm_mmu_zap_all(kvm);
8986ecc0 6253 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6254}
6255
1d737c8a
ZX		 6256int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6257{
af585b92
GN		 6258 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6259 !vcpu->arch.apf.halted)
6260 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6261 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6262 || vcpu->arch.nmi_pending ||
6263 (kvm_arch_interrupt_allowed(vcpu) &&
6264 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6265}
5736199a 6266
5736199a
ZX		 6267void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6268{
32f88400
MT		 6269 int me;
6270 int cpu = vcpu->cpu;
5736199a
ZX		 6271
6272 if (waitqueue_active(&vcpu->wq)) {
6273 wake_up_interruptible(&vcpu->wq);
6274 ++vcpu->stat.halt_wakeup;
6275 }
32f88400
MT		 6276
6277 me = get_cpu();
6278 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6279 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6280 smp_send_reschedule(cpu);
e9571ed5 6281 put_cpu();
5736199a 6282}
78646121
GN		 6283
6284int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6285{
6286 return kvm_x86_ops->interrupt_allowed(vcpu);
6287}
229456fc 6288
f92653ee
JK		 6289bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6290{
6291 unsigned long current_rip = kvm_rip_read(vcpu) +
6292 get_segment_base(vcpu, VCPU_SREG_CS);
6293
6294 return current_rip == linear_rip;
6295}
6296EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6297
94fe45da
JK		 6298unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6299{
6300 unsigned long rflags;
6301
6302 rflags = kvm_x86_ops->get_rflags(vcpu);
6303 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6304 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6305 return rflags;
6306}
6307EXPORT_SYMBOL_GPL(kvm_get_rflags);
6308
6309void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6310{
6311 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6312 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6313 rflags |= X86_EFLAGS_TF;
94fe45da 6314 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6315 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6316}
6317EXPORT_SYMBOL_GPL(kvm_set_rflags);
6318
56028d08
GN		 6319void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6320{
6321 int r;
6322
fb67e14f 6323 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6324 is_error_page(work->page))
56028d08
GN		 6325 return;
6326
6327 r = kvm_mmu_reload(vcpu);
6328 if (unlikely(r))
6329 return;
6330
fb67e14f
XG		 6331 if (!vcpu->arch.mmu.direct_map &&
6332 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6333 return;
6334
56028d08
GN		 6335 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6336}
6337
af585b92
GN		 6338static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6339{
6340 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6341}
6342
6343static inline u32 kvm_async_pf_next_probe(u32 key)
6344{
6345 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6346}
6347
6348static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6349{
6350 u32 key = kvm_async_pf_hash_fn(gfn);
6351
6352 while (vcpu->arch.apf.gfns[key] != ~0)
6353 key = kvm_async_pf_next_probe(key);
6354
6355 vcpu->arch.apf.gfns[key] = gfn;
6356}
6357
6358static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6359{
6360 int i;
6361 u32 key = kvm_async_pf_hash_fn(gfn);
6362
6363 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6364 (vcpu->arch.apf.gfns[key] != gfn &&
6365 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6366 key = kvm_async_pf_next_probe(key);
6367
6368 return key;
6369}
6370
6371bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6372{
6373 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6374}
6375
6376static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6377{
6378 u32 i, j, k;
6379
6380 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6381 while (true) {
6382 vcpu->arch.apf.gfns[i] = ~0;
6383 do {
6384 j = kvm_async_pf_next_probe(j);
6385 if (vcpu->arch.apf.gfns[j] == ~0)
6386 return;
6387 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6388 /*
6389 * k lies cyclically in ]i,j]
6390 * | i.k.j |
6391 * |....j i.k.| or |.k..j i...|
6392 */
6393 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6394 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6395 i = j;
6396 }
6397}
6398
7c90705b
GN		 6399static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6400{
6401
6402 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6403 sizeof(val));
6404}
6405
af585b92
GN		 6406void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6407 struct kvm_async_pf *work)
6408{
6389ee94
AK		 6409 struct x86_exception fault;
6410
7c90705b 6411 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6412 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6413
6414 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6415 (vcpu->arch.apf.send_user_only &&
6416 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6417 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6418 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6419 fault.vector = PF_VECTOR;
6420 fault.error_code_valid = true;
6421 fault.error_code = 0;
6422 fault.nested_page_fault = false;
6423 fault.address = work->arch.token;
6424 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6425 }
af585b92
GN		 6426}
6427
6428void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6429 struct kvm_async_pf *work)
6430{
6389ee94
AK		 6431 struct x86_exception fault;
6432
7c90705b
GN		 6433 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6434 if (is_error_page(work->page))
6435 work->arch.token = ~0; /* broadcast wakeup */
6436 else
6437 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6438
6439 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6440 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6441 fault.vector = PF_VECTOR;
6442 fault.error_code_valid = true;
6443 fault.error_code = 0;
6444 fault.nested_page_fault = false;
6445 fault.address = work->arch.token;
6446 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6447 }
e6d53e3b 6448 vcpu->arch.apf.halted = false;
7c90705b
GN		 6449}
6450
6451bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6452{
6453 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6454 return true;
6455 else
6456 return !kvm_event_needs_reinjection(vcpu) &&
6457 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6458}
6459
229456fc
MT		 6460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6469EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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