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KVM: SVM: Improve nested interrupt injection
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
043405e1
CO		 40
41#include <asm/uaccess.h>
d825ed0a 42#include <asm/msr.h>
a5f61300 43#include <asm/desc.h>
0bed3b56 44#include <asm/mtrr.h>
890ca9ae 45#include <asm/mce.h>
043405e1 46
313a3dc7 47#define MAX_IO_MSRS 256
a03490ed
CO		 48#define CR0_RESERVED_BITS \
49 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
50 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
51 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
52#define CR4_RESERVED_BITS \
53 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
54 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
55 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
56 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
57
58#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 59
60#define KVM_MAX_MCE_BANKS 32
61#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
62
50a37eb4
JR		 63/* EFER defaults:
64 * - enable syscall per default because its emulated by KVM
65 * - enable LME and LMA per default on 64 bit KVM
66 */
67#ifdef CONFIG_X86_64
68static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
69#else
70static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
71#endif
313a3dc7 72
ba1389b7
AK		 73#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
74#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 75
674eea0f
AK		 76static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
77 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 78struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
79 u32 function, u32 index);
674eea0f 80
97896d04 81struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 82EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 83
417bc304 84struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 85 { "pf_fixed", VCPU_STAT(pf_fixed) },
86 { "pf_guest", VCPU_STAT(pf_guest) },
87 { "tlb_flush", VCPU_STAT(tlb_flush) },
88 { "invlpg", VCPU_STAT(invlpg) },
89 { "exits", VCPU_STAT(exits) },
90 { "io_exits", VCPU_STAT(io_exits) },
91 { "mmio_exits", VCPU_STAT(mmio_exits) },
92 { "signal_exits", VCPU_STAT(signal_exits) },
93 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 94 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 95 { "halt_exits", VCPU_STAT(halt_exits) },
96 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 97 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 98 { "request_irq", VCPU_STAT(request_irq_exits) },
99 { "irq_exits", VCPU_STAT(irq_exits) },
100 { "host_state_reload", VCPU_STAT(host_state_reload) },
101 { "efer_reload", VCPU_STAT(efer_reload) },
102 { "fpu_reload", VCPU_STAT(fpu_reload) },
103 { "insn_emulation", VCPU_STAT(insn_emulation) },
104 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 105 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 106 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 107 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
108 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
109 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
110 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
111 { "mmu_flooded", VM_STAT(mmu_flooded) },
112 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 113 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 114 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 115 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 116 { "largepages", VM_STAT(lpages) },
417bc304
HB		 117 { NULL }
118};
119
5fb76f9b
CO		 120unsigned long segment_base(u16 selector)
121{
122 struct descriptor_table gdt;
a5f61300 123 struct desc_struct *d;
5fb76f9b
CO		 124 unsigned long table_base;
125 unsigned long v;
126
127 if (selector == 0)
128 return 0;
129
130 asm("sgdt %0" : "=m"(gdt));
131 table_base = gdt.base;
132
133 if (selector & 4) { /* from ldt */
134 u16 ldt_selector;
135
136 asm("sldt %0" : "=g"(ldt_selector));
137 table_base = segment_base(ldt_selector);
138 }
a5f61300
AK		 139 d = (struct desc_struct *)(table_base + (selector & ~7));
140 v = d->base0 | ((unsigned long)d->base1 << 16) |
141 ((unsigned long)d->base2 << 24);
5fb76f9b 142#ifdef CONFIG_X86_64
a5f61300
AK		 143 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
144 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 145#endif
146 return v;
147}
148EXPORT_SYMBOL_GPL(segment_base);
149
6866b83e
CO		 150u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
151{
152 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 153 return vcpu->arch.apic_base;
6866b83e 154 else
ad312c7c 155 return vcpu->arch.apic_base;
6866b83e
CO		 156}
157EXPORT_SYMBOL_GPL(kvm_get_apic_base);
158
159void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
160{
161 /* TODO: reserve bits check */
162 if (irqchip_in_kernel(vcpu->kvm))
163 kvm_lapic_set_base(vcpu, data);
164 else
ad312c7c 165 vcpu->arch.apic_base = data;
6866b83e
CO		 166}
167EXPORT_SYMBOL_GPL(kvm_set_apic_base);
168
298101da
AK		 169void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
170{
ad312c7c
ZX		 171 WARN_ON(vcpu->arch.exception.pending);
172 vcpu->arch.exception.pending = true;
173 vcpu->arch.exception.has_error_code = false;
174 vcpu->arch.exception.nr = nr;
298101da
AK		 175}
176EXPORT_SYMBOL_GPL(kvm_queue_exception);
177
c3c91fee
AK		 178void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
179 u32 error_code)
180{
181 ++vcpu->stat.pf_guest;
d8017474 182
71c4dfaf 183 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 184 switch(vcpu->arch.exception.nr) {
185 case DF_VECTOR:
71c4dfaf
JR		 186 /* triple fault -> shutdown */
187 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 188 return;
189 case PF_VECTOR:
190 vcpu->arch.exception.nr = DF_VECTOR;
191 vcpu->arch.exception.error_code = 0;
192 return;
193 default:
194 /* replace previous exception with a new one in a hope
195 that instruction re-execution will regenerate lost
196 exception */
197 vcpu->arch.exception.pending = false;
198 break;
71c4dfaf 199 }
c3c91fee 200 }
ad312c7c 201 vcpu->arch.cr2 = addr;
c3c91fee
AK		 202 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
203}
204
3419ffc8
SY		 205void kvm_inject_nmi(struct kvm_vcpu *vcpu)
206{
207 vcpu->arch.nmi_pending = 1;
208}
209EXPORT_SYMBOL_GPL(kvm_inject_nmi);
210
298101da
AK		 211void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
212{
ad312c7c
ZX		 213 WARN_ON(vcpu->arch.exception.pending);
214 vcpu->arch.exception.pending = true;
215 vcpu->arch.exception.has_error_code = true;
216 vcpu->arch.exception.nr = nr;
217 vcpu->arch.exception.error_code = error_code;
298101da
AK		 218}
219EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
220
221static void __queue_exception(struct kvm_vcpu *vcpu)
222{
ad312c7c
ZX		 223 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
224 vcpu->arch.exception.has_error_code,
225 vcpu->arch.exception.error_code);
298101da
AK		 226}
227
a03490ed
CO		 228/*
229 * Load the pae pdptrs. Return true is they are all valid.
230 */
231int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
232{
233 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
234 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
235 int i;
236 int ret;
ad312c7c 237 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 238
a03490ed
CO		 239 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
240 offset * sizeof(u64), sizeof(pdpte));
241 if (ret < 0) {
242 ret = 0;
243 goto out;
244 }
245 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 246 if (is_present_gpte(pdpte[i]) &&
20c466b5 247 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 248 ret = 0;
249 goto out;
250 }
251 }
252 ret = 1;
253
ad312c7c 254 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 255 __set_bit(VCPU_EXREG_PDPTR,
256 (unsigned long *)&vcpu->arch.regs_avail);
257 __set_bit(VCPU_EXREG_PDPTR,
258 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 259out:
a03490ed
CO		 260
261 return ret;
262}
cc4b6871 263EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 264
d835dfec
AK		 265static bool pdptrs_changed(struct kvm_vcpu *vcpu)
266{
ad312c7c 267 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 268 bool changed = true;
269 int r;
270
271 if (is_long_mode(vcpu) || !is_pae(vcpu))
272 return false;
273
6de4f3ad
AK		 274 if (!test_bit(VCPU_EXREG_PDPTR,
275 (unsigned long *)&vcpu->arch.regs_avail))
276 return true;
277
ad312c7c 278 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 279 if (r < 0)
280 goto out;
ad312c7c 281 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 282out:
d835dfec
AK		 283
284 return changed;
285}
286
2d3ad1f4 287void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 288{
289 if (cr0 & CR0_RESERVED_BITS) {
290 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 291 cr0, vcpu->arch.cr0);
c1a5d4f9 292 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 293 return;
294 }
295
296 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
297 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 298 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 299 return;
300 }
301
302 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
303 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
304 "and a clear PE flag\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307 }
308
309 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
310#ifdef CONFIG_X86_64
ad312c7c 311 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 312 int cs_db, cs_l;
313
314 if (!is_pae(vcpu)) {
315 printk(KERN_DEBUG "set_cr0: #GP, start paging "
316 "in long mode while PAE is disabled\n");
c1a5d4f9 317 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 318 return;
319 }
320 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
321 if (cs_l) {
322 printk(KERN_DEBUG "set_cr0: #GP, start paging "
323 "in long mode while CS.L == 1\n");
c1a5d4f9 324 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 325 return;
326
327 }
328 } else
329#endif
ad312c7c 330 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 331 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
332 "reserved bits\n");
c1a5d4f9 333 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 334 return;
335 }
336
337 }
338
339 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 340 vcpu->arch.cr0 = cr0;
a03490ed 341
a03490ed 342 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 343 return;
344}
2d3ad1f4 345EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 346
2d3ad1f4 347void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 348{
2d3ad1f4 349 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 350 KVMTRACE_1D(LMSW, vcpu,
351 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
352 handler);
a03490ed 353}
2d3ad1f4 354EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 355
2d3ad1f4 356void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 357{
a2edf57f
AK		 358 unsigned long old_cr4 = vcpu->arch.cr4;
359 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
360
a03490ed
CO		 361 if (cr4 & CR4_RESERVED_BITS) {
362 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 363 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 364 return;
365 }
366
367 if (is_long_mode(vcpu)) {
368 if (!(cr4 & X86_CR4_PAE)) {
369 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
370 "in long mode\n");
c1a5d4f9 371 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 372 return;
373 }
a2edf57f
AK		 374 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
375 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 376 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 377 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 378 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 379 return;
380 }
381
382 if (cr4 & X86_CR4_VMXE) {
383 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 384 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 385 return;
386 }
387 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 388 vcpu->arch.cr4 = cr4;
5a41accd 389 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 390 kvm_mmu_reset_context(vcpu);
a03490ed 391}
2d3ad1f4 392EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 393
2d3ad1f4 394void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 395{
ad312c7c 396 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 397 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 398 kvm_mmu_flush_tlb(vcpu);
399 return;
400 }
401
a03490ed
CO		 402 if (is_long_mode(vcpu)) {
403 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
404 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 405 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 406 return;
407 }
408 } else {
409 if (is_pae(vcpu)) {
410 if (cr3 & CR3_PAE_RESERVED_BITS) {
411 printk(KERN_DEBUG
412 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 413 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 414 return;
415 }
416 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
417 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
418 "reserved bits\n");
c1a5d4f9 419 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 420 return;
421 }
422 }
423 /*
424 * We don't check reserved bits in nonpae mode, because
425 * this isn't enforced, and VMware depends on this.
426 */
427 }
428
a03490ed
CO		 429 /*
430 * Does the new cr3 value map to physical memory? (Note, we
431 * catch an invalid cr3 even in real-mode, because it would
432 * cause trouble later on when we turn on paging anyway.)
433 *
434 * A real CPU would silently accept an invalid cr3 and would
435 * attempt to use it - with largely undefined (and often hard
436 * to debug) behavior on the guest side.
437 */
438 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 439 kvm_inject_gp(vcpu, 0);
a03490ed 440 else {
ad312c7c
ZX		 441 vcpu->arch.cr3 = cr3;
442 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 443 }
a03490ed 444}
2d3ad1f4 445EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 446
2d3ad1f4 447void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 448{
449 if (cr8 & CR8_RESERVED_BITS) {
450 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 451 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 452 return;
453 }
454 if (irqchip_in_kernel(vcpu->kvm))
455 kvm_lapic_set_tpr(vcpu, cr8);
456 else
ad312c7c 457 vcpu->arch.cr8 = cr8;
a03490ed 458}
2d3ad1f4 459EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 460
2d3ad1f4 461unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 462{
463 if (irqchip_in_kernel(vcpu->kvm))
464 return kvm_lapic_get_cr8(vcpu);
465 else
ad312c7c 466 return vcpu->arch.cr8;
a03490ed 467}
2d3ad1f4 468EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 469
d8017474
AG		 470static inline u32 bit(int bitno)
471{
472 return 1 << (bitno & 31);
473}
474
043405e1
CO		 475/*
476 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
477 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
478 *
479 * This list is modified at module load time to reflect the
480 * capabilities of the host cpu.
481 */
482static u32 msrs_to_save[] = {
483 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
484 MSR_K6_STAR,
485#ifdef CONFIG_X86_64
486 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
487#endif
af24a4e4 488 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 489 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 490};
491
492static unsigned num_msrs_to_save;
493
494static u32 emulated_msrs[] = {
495 MSR_IA32_MISC_ENABLE,
496};
497
15c4a640
CO		 498static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
499{
f2b4b7dd 500 if (efer & efer_reserved_bits) {
15c4a640
CO		 501 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
502 efer);
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 504 return;
505 }
506
507 if (is_paging(vcpu)
ad312c7c 508 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 509 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 510 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 511 return;
512 }
513
1b2fd70c
AG		 514 if (efer & EFER_FFXSR) {
515 struct kvm_cpuid_entry2 *feat;
516
517 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
518 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
519 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
520 kvm_inject_gp(vcpu, 0);
521 return;
522 }
523 }
524
d8017474
AG		 525 if (efer & EFER_SVME) {
526 struct kvm_cpuid_entry2 *feat;
527
528 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
529 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
530 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
531 kvm_inject_gp(vcpu, 0);
532 return;
533 }
534 }
535
15c4a640
CO		 536 kvm_x86_ops->set_efer(vcpu, efer);
537
538 efer &= ~EFER_LMA;
ad312c7c 539 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 540
ad312c7c 541 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 542
543 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
544 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 545}
546
f2b4b7dd
JR		 547void kvm_enable_efer_bits(u64 mask)
548{
549 efer_reserved_bits &= ~mask;
550}
551EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
552
553
15c4a640
CO		 554/*
555 * Writes msr value into into the appropriate "register".
556 * Returns 0 on success, non-0 otherwise.
557 * Assumes vcpu_load() was already called.
558 */
559int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
560{
561 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
562}
563
313a3dc7
CO		 564/*
565 * Adapt set_msr() to msr_io()'s calling convention
566 */
567static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
568{
569 return kvm_set_msr(vcpu, index, *data);
570}
571
18068523
GOC		 572static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
573{
574 static int version;
50d0a0f9
GH		 575 struct pvclock_wall_clock wc;
576 struct timespec now, sys, boot;
18068523
GOC		 577
578 if (!wall_clock)
579 return;
580
581 version++;
582
18068523
GOC		 583 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
584
50d0a0f9
GH		 585 /*
586 * The guest calculates current wall clock time by adding
587 * system time (updated by kvm_write_guest_time below) to the
588 * wall clock specified here. guest system time equals host
589 * system time for us, thus we must fill in host boot time here.
590 */
591 now = current_kernel_time();
592 ktime_get_ts(&sys);
593 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
594
595 wc.sec = boot.tv_sec;
596 wc.nsec = boot.tv_nsec;
597 wc.version = version;
18068523
GOC		 598
599 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
600
601 version++;
602 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 603}
604
50d0a0f9
GH		 605static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
606{
607 uint32_t quotient, remainder;
608
609 /* Don't try to replace with do_div(), this one calculates
610 * "(dividend << 32) / divisor" */
611 __asm__ ( "divl %4"
612 : "=a" (quotient), "=d" (remainder)
613 : "0" (0), "1" (dividend), "r" (divisor) );
614 return quotient;
615}
616
617static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
618{
619 uint64_t nsecs = 1000000000LL;
620 int32_t shift = 0;
621 uint64_t tps64;
622 uint32_t tps32;
623
624 tps64 = tsc_khz * 1000LL;
625 while (tps64 > nsecs*2) {
626 tps64 >>= 1;
627 shift--;
628 }
629
630 tps32 = (uint32_t)tps64;
631 while (tps32 <= (uint32_t)nsecs) {
632 tps32 <<= 1;
633 shift++;
634 }
635
636 hv_clock->tsc_shift = shift;
637 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
638
639 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 640 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 641 hv_clock->tsc_to_system_mul);
642}
643
c8076604
GH		 644static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
645
18068523
GOC		 646static void kvm_write_guest_time(struct kvm_vcpu *v)
647{
648 struct timespec ts;
649 unsigned long flags;
650 struct kvm_vcpu_arch *vcpu = &v->arch;
651 void *shared_kaddr;
463656c0 652 unsigned long this_tsc_khz;
18068523
GOC		 653
654 if ((!vcpu->time_page))
655 return;
656
463656c0
AK		 657 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
658 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
659 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
660 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 661 }
463656c0 662 put_cpu_var(cpu_tsc_khz);
50d0a0f9 663
18068523
GOC		 664 /* Keep irq disabled to prevent changes to the clock */
665 local_irq_save(flags);
af24a4e4 666 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 667 ktime_get_ts(&ts);
668 local_irq_restore(flags);
669
670 /* With all the info we got, fill in the values */
671
672 vcpu->hv_clock.system_time = ts.tv_nsec +
673 (NSEC_PER_SEC * (u64)ts.tv_sec);
674 /*
675 * The interface expects us to write an even number signaling that the
676 * update is finished. Since the guest won't see the intermediate
50d0a0f9 677 * state, we just increase by 2 at the end.
18068523 678 */
50d0a0f9 679 vcpu->hv_clock.version += 2;
18068523
GOC		 680
681 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
682
683 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 684 sizeof(vcpu->hv_clock));
18068523
GOC		 685
686 kunmap_atomic(shared_kaddr, KM_USER0);
687
688 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
689}
690
c8076604
GH		 691static int kvm_request_guest_time_update(struct kvm_vcpu *v)
692{
693 struct kvm_vcpu_arch *vcpu = &v->arch;
694
695 if (!vcpu->time_page)
696 return 0;
697 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
698 return 1;
699}
700
9ba075a6
AK		 701static bool msr_mtrr_valid(unsigned msr)
702{
703 switch (msr) {
704 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
705 case MSR_MTRRfix64K_00000:
706 case MSR_MTRRfix16K_80000:
707 case MSR_MTRRfix16K_A0000:
708 case MSR_MTRRfix4K_C0000:
709 case MSR_MTRRfix4K_C8000:
710 case MSR_MTRRfix4K_D0000:
711 case MSR_MTRRfix4K_D8000:
712 case MSR_MTRRfix4K_E0000:
713 case MSR_MTRRfix4K_E8000:
714 case MSR_MTRRfix4K_F0000:
715 case MSR_MTRRfix4K_F8000:
716 case MSR_MTRRdefType:
717 case MSR_IA32_CR_PAT:
718 return true;
719 case 0x2f8:
720 return true;
721 }
722 return false;
723}
724
d6289b93
MT		 725static bool valid_pat_type(unsigned t)
726{
727 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
728}
729
730static bool valid_mtrr_type(unsigned t)
731{
732 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
733}
734
735static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
736{
737 int i;
738
739 if (!msr_mtrr_valid(msr))
740 return false;
741
742 if (msr == MSR_IA32_CR_PAT) {
743 for (i = 0; i < 8; i++)
744 if (!valid_pat_type((data >> (i * 8)) & 0xff))
745 return false;
746 return true;
747 } else if (msr == MSR_MTRRdefType) {
748 if (data & ~0xcff)
749 return false;
750 return valid_mtrr_type(data & 0xff);
751 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
752 for (i = 0; i < 8 ; i++)
753 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
754 return false;
755 return true;
756 }
757
758 /* variable MTRRs */
759 return valid_mtrr_type(data & 0xff);
760}
761
9ba075a6
AK		 762static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
763{
0bed3b56
SY		 764 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
765
d6289b93 766 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 767 return 1;
768
0bed3b56
SY		 769 if (msr == MSR_MTRRdefType) {
770 vcpu->arch.mtrr_state.def_type = data;
771 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
772 } else if (msr == MSR_MTRRfix64K_00000)
773 p[0] = data;
774 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
775 p[1 + msr - MSR_MTRRfix16K_80000] = data;
776 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
777 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
778 else if (msr == MSR_IA32_CR_PAT)
779 vcpu->arch.pat = data;
780 else { /* Variable MTRRs */
781 int idx, is_mtrr_mask;
782 u64 *pt;
783
784 idx = (msr - 0x200) / 2;
785 is_mtrr_mask = msr - 0x200 - 2 * idx;
786 if (!is_mtrr_mask)
787 pt =
788 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
789 else
790 pt =
791 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
792 *pt = data;
793 }
794
795 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 796 return 0;
797}
15c4a640 798
890ca9ae 799static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 800{
890ca9ae
HY		 801 u64 mcg_cap = vcpu->arch.mcg_cap;
802 unsigned bank_num = mcg_cap & 0xff;
803
15c4a640 804 switch (msr) {
15c4a640 805 case MSR_IA32_MCG_STATUS:
890ca9ae 806 vcpu->arch.mcg_status = data;
15c4a640 807 break;
c7ac679c 808 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 809 if (!(mcg_cap & MCG_CTL_P))
810 return 1;
811 if (data != 0 && data != ~(u64)0)
812 return -1;
813 vcpu->arch.mcg_ctl = data;
814 break;
815 default:
816 if (msr >= MSR_IA32_MC0_CTL &&
817 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
818 u32 offset = msr - MSR_IA32_MC0_CTL;
819 /* only 0 or all 1s can be written to IA32_MCi_CTL */
820 if ((offset & 0x3) == 0 &&
821 data != 0 && data != ~(u64)0)
822 return -1;
823 vcpu->arch.mce_banks[offset] = data;
824 break;
825 }
826 return 1;
827 }
828 return 0;
829}
830
831int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
832{
833 switch (msr) {
834 case MSR_EFER:
835 set_efer(vcpu, data);
c7ac679c 836 break;
b5e2fec0
AG		 837 case MSR_IA32_DEBUGCTLMSR:
838 if (!data) {
839 /* We support the non-activated case already */
840 break;
841 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
842 /* Values other than LBR and BTF are vendor-specific,
843 thus reserved and should throw a #GP */
844 return 1;
845 }
846 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
847 __func__, data);
848 break;
15c4a640
CO		 849 case MSR_IA32_UCODE_REV:
850 case MSR_IA32_UCODE_WRITE:
61a6bd67 851 case MSR_VM_HSAVE_PA:
15c4a640 852 break;
9ba075a6
AK		 853 case 0x200 ... 0x2ff:
854 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 855 case MSR_IA32_APICBASE:
856 kvm_set_apic_base(vcpu, data);
857 break;
858 case MSR_IA32_MISC_ENABLE:
ad312c7c 859 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 860 break;
18068523
GOC		 861 case MSR_KVM_WALL_CLOCK:
862 vcpu->kvm->arch.wall_clock = data;
863 kvm_write_wall_clock(vcpu->kvm, data);
864 break;
865 case MSR_KVM_SYSTEM_TIME: {
866 if (vcpu->arch.time_page) {
867 kvm_release_page_dirty(vcpu->arch.time_page);
868 vcpu->arch.time_page = NULL;
869 }
870
871 vcpu->arch.time = data;
872
873 /* we verify if the enable bit is set... */
874 if (!(data & 1))
875 break;
876
877 /* ...but clean it before doing the actual write */
878 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
879
18068523
GOC		 880 vcpu->arch.time_page =
881 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 882
883 if (is_error_page(vcpu->arch.time_page)) {
884 kvm_release_page_clean(vcpu->arch.time_page);
885 vcpu->arch.time_page = NULL;
886 }
887
c8076604 888 kvm_request_guest_time_update(vcpu);
18068523
GOC		 889 break;
890 }
890ca9ae
HY		 891 case MSR_IA32_MCG_CTL:
892 case MSR_IA32_MCG_STATUS:
893 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
894 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 895
896 /* Performance counters are not protected by a CPUID bit,
897 * so we should check all of them in the generic path for the sake of
898 * cross vendor migration.
899 * Writing a zero into the event select MSRs disables them,
900 * which we perfectly emulate ;-). Any other value should be at least
901 * reported, some guests depend on them.
902 */
903 case MSR_P6_EVNTSEL0:
904 case MSR_P6_EVNTSEL1:
905 case MSR_K7_EVNTSEL0:
906 case MSR_K7_EVNTSEL1:
907 case MSR_K7_EVNTSEL2:
908 case MSR_K7_EVNTSEL3:
909 if (data != 0)
910 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
911 "0x%x data 0x%llx\n", msr, data);
912 break;
913 /* at least RHEL 4 unconditionally writes to the perfctr registers,
914 * so we ignore writes to make it happy.
915 */
916 case MSR_P6_PERFCTR0:
917 case MSR_P6_PERFCTR1:
918 case MSR_K7_PERFCTR0:
919 case MSR_K7_PERFCTR1:
920 case MSR_K7_PERFCTR2:
921 case MSR_K7_PERFCTR3:
922 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
923 "0x%x data 0x%llx\n", msr, data);
924 break;
15c4a640 925 default:
565f1fbd 926 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 927 return 1;
928 }
929 return 0;
930}
931EXPORT_SYMBOL_GPL(kvm_set_msr_common);
932
933
934/*
935 * Reads an msr value (of 'msr_index') into 'pdata'.
936 * Returns 0 on success, non-0 otherwise.
937 * Assumes vcpu_load() was already called.
938 */
939int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
940{
941 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
942}
943
9ba075a6
AK		 944static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
945{
0bed3b56
SY		 946 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
947
9ba075a6
AK		 948 if (!msr_mtrr_valid(msr))
949 return 1;
950
0bed3b56
SY		 951 if (msr == MSR_MTRRdefType)
952 *pdata = vcpu->arch.mtrr_state.def_type +
953 (vcpu->arch.mtrr_state.enabled << 10);
954 else if (msr == MSR_MTRRfix64K_00000)
955 *pdata = p[0];
956 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
957 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
958 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
959 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
960 else if (msr == MSR_IA32_CR_PAT)
961 *pdata = vcpu->arch.pat;
962 else { /* Variable MTRRs */
963 int idx, is_mtrr_mask;
964 u64 *pt;
965
966 idx = (msr - 0x200) / 2;
967 is_mtrr_mask = msr - 0x200 - 2 * idx;
968 if (!is_mtrr_mask)
969 pt =
970 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
971 else
972 pt =
973 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
974 *pdata = *pt;
975 }
976
9ba075a6
AK		 977 return 0;
978}
979
890ca9ae 980static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 981{
982 u64 data;
890ca9ae
HY		 983 u64 mcg_cap = vcpu->arch.mcg_cap;
984 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 985
986 switch (msr) {
15c4a640
CO		 987 case MSR_IA32_P5_MC_ADDR:
988 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 989 data = 0;
990 break;
15c4a640 991 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 992 data = vcpu->arch.mcg_cap;
993 break;
c7ac679c 994 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 995 if (!(mcg_cap & MCG_CTL_P))
996 return 1;
997 data = vcpu->arch.mcg_ctl;
998 break;
999 case MSR_IA32_MCG_STATUS:
1000 data = vcpu->arch.mcg_status;
1001 break;
1002 default:
1003 if (msr >= MSR_IA32_MC0_CTL &&
1004 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1005 u32 offset = msr - MSR_IA32_MC0_CTL;
1006 data = vcpu->arch.mce_banks[offset];
1007 break;
1008 }
1009 return 1;
1010 }
1011 *pdata = data;
1012 return 0;
1013}
1014
1015int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1016{
1017 u64 data;
1018
1019 switch (msr) {
890ca9ae 1020 case MSR_IA32_PLATFORM_ID:
15c4a640 1021 case MSR_IA32_UCODE_REV:
15c4a640 1022 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1023 case MSR_IA32_DEBUGCTLMSR:
1024 case MSR_IA32_LASTBRANCHFROMIP:
1025 case MSR_IA32_LASTBRANCHTOIP:
1026 case MSR_IA32_LASTINTFROMIP:
1027 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1028 case MSR_K8_SYSCFG:
1029 case MSR_K7_HWCR:
61a6bd67 1030 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1031 case MSR_P6_EVNTSEL0:
1032 case MSR_P6_EVNTSEL1:
9e699624 1033 case MSR_K7_EVNTSEL0:
15c4a640
CO		 1034 data = 0;
1035 break;
9ba075a6
AK		 1036 case MSR_MTRRcap:
1037 data = 0x500 | KVM_NR_VAR_MTRR;
1038 break;
1039 case 0x200 ... 0x2ff:
1040 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1041 case 0xcd: /* fsb frequency */
1042 data = 3;
1043 break;
1044 case MSR_IA32_APICBASE:
1045 data = kvm_get_apic_base(vcpu);
1046 break;
1047 case MSR_IA32_MISC_ENABLE:
ad312c7c 1048 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1049 break;
847f0ad8
AG		 1050 case MSR_IA32_PERF_STATUS:
1051 /* TSC increment by tick */
1052 data = 1000ULL;
1053 /* CPU multiplier */
1054 data |= (((uint64_t)4ULL) << 40);
1055 break;
15c4a640 1056 case MSR_EFER:
ad312c7c 1057 data = vcpu->arch.shadow_efer;
15c4a640 1058 break;
18068523
GOC		 1059 case MSR_KVM_WALL_CLOCK:
1060 data = vcpu->kvm->arch.wall_clock;
1061 break;
1062 case MSR_KVM_SYSTEM_TIME:
1063 data = vcpu->arch.time;
1064 break;
890ca9ae
HY		 1065 case MSR_IA32_P5_MC_ADDR:
1066 case MSR_IA32_P5_MC_TYPE:
1067 case MSR_IA32_MCG_CAP:
1068 case MSR_IA32_MCG_CTL:
1069 case MSR_IA32_MCG_STATUS:
1070 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1071 return get_msr_mce(vcpu, msr, pdata);
15c4a640
CO		 1072 default:
1073 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1074 return 1;
1075 }
1076 *pdata = data;
1077 return 0;
1078}
1079EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1080
313a3dc7
CO		 1081/*
1082 * Read or write a bunch of msrs. All parameters are kernel addresses.
1083 *
1084 * @return number of msrs set successfully.
1085 */
1086static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1087 struct kvm_msr_entry *entries,
1088 int (*do_msr)(struct kvm_vcpu *vcpu,
1089 unsigned index, u64 *data))
1090{
1091 int i;
1092
1093 vcpu_load(vcpu);
1094
3200f405 1095 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1096 for (i = 0; i < msrs->nmsrs; ++i)
1097 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1098 break;
3200f405 1099 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1100
1101 vcpu_put(vcpu);
1102
1103 return i;
1104}
1105
1106/*
1107 * Read or write a bunch of msrs. Parameters are user addresses.
1108 *
1109 * @return number of msrs set successfully.
1110 */
1111static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1112 int (*do_msr)(struct kvm_vcpu *vcpu,
1113 unsigned index, u64 *data),
1114 int writeback)
1115{
1116 struct kvm_msrs msrs;
1117 struct kvm_msr_entry *entries;
1118 int r, n;
1119 unsigned size;
1120
1121 r = -EFAULT;
1122 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1123 goto out;
1124
1125 r = -E2BIG;
1126 if (msrs.nmsrs >= MAX_IO_MSRS)
1127 goto out;
1128
1129 r = -ENOMEM;
1130 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1131 entries = vmalloc(size);
1132 if (!entries)
1133 goto out;
1134
1135 r = -EFAULT;
1136 if (copy_from_user(entries, user_msrs->entries, size))
1137 goto out_free;
1138
1139 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1140 if (r < 0)
1141 goto out_free;
1142
1143 r = -EFAULT;
1144 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1145 goto out_free;
1146
1147 r = n;
1148
1149out_free:
1150 vfree(entries);
1151out:
1152 return r;
1153}
1154
018d00d2
ZX		 1155int kvm_dev_ioctl_check_extension(long ext)
1156{
1157 int r;
1158
1159 switch (ext) {
1160 case KVM_CAP_IRQCHIP:
1161 case KVM_CAP_HLT:
1162 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1163 case KVM_CAP_SET_TSS_ADDR:
07716717 1164 case KVM_CAP_EXT_CPUID:
c8076604 1165 case KVM_CAP_CLOCKSOURCE:
7837699f 1166 case KVM_CAP_PIT:
a28e4f5a 1167 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1168 case KVM_CAP_MP_STATE:
ed848624 1169 case KVM_CAP_SYNC_MMU:
52d939a0 1170 case KVM_CAP_REINJECT_CONTROL:
4925663a 1171 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1172 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1173 case KVM_CAP_IRQFD:
c5ff41ce 1174 case KVM_CAP_PIT2:
018d00d2
ZX		 1175 r = 1;
1176 break;
542472b5
LV		 1177 case KVM_CAP_COALESCED_MMIO:
1178 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1179 break;
774ead3a
AK		 1180 case KVM_CAP_VAPIC:
1181 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1182 break;
f725230a
AK		 1183 case KVM_CAP_NR_VCPUS:
1184 r = KVM_MAX_VCPUS;
1185 break;
a988b910
AK		 1186 case KVM_CAP_NR_MEMSLOTS:
1187 r = KVM_MEMORY_SLOTS;
1188 break;
2f333bcb
MT		 1189 case KVM_CAP_PV_MMU:
1190 r = !tdp_enabled;
1191 break;
62c476c7 1192 case KVM_CAP_IOMMU:
19de40a8 1193 r = iommu_found();
62c476c7 1194 break;
890ca9ae
HY		 1195 case KVM_CAP_MCE:
1196 r = KVM_MAX_MCE_BANKS;
1197 break;
018d00d2
ZX		 1198 default:
1199 r = 0;
1200 break;
1201 }
1202 return r;
1203
1204}
1205
043405e1
CO		 1206long kvm_arch_dev_ioctl(struct file *filp,
1207 unsigned int ioctl, unsigned long arg)
1208{
1209 void __user *argp = (void __user *)arg;
1210 long r;
1211
1212 switch (ioctl) {
1213 case KVM_GET_MSR_INDEX_LIST: {
1214 struct kvm_msr_list __user *user_msr_list = argp;
1215 struct kvm_msr_list msr_list;
1216 unsigned n;
1217
1218 r = -EFAULT;
1219 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1220 goto out;
1221 n = msr_list.nmsrs;
1222 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1223 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1224 goto out;
1225 r = -E2BIG;
e125e7b6 1226 if (n < msr_list.nmsrs)
043405e1
CO		 1227 goto out;
1228 r = -EFAULT;
1229 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1230 num_msrs_to_save * sizeof(u32)))
1231 goto out;
e125e7b6 1232 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1233 &emulated_msrs,
1234 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1235 goto out;
1236 r = 0;
1237 break;
1238 }
674eea0f
AK		 1239 case KVM_GET_SUPPORTED_CPUID: {
1240 struct kvm_cpuid2 __user *cpuid_arg = argp;
1241 struct kvm_cpuid2 cpuid;
1242
1243 r = -EFAULT;
1244 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1245 goto out;
1246 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1247 cpuid_arg->entries);
674eea0f
AK		 1248 if (r)
1249 goto out;
1250
1251 r = -EFAULT;
1252 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1253 goto out;
1254 r = 0;
1255 break;
1256 }
890ca9ae
HY		 1257 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1258 u64 mce_cap;
1259
1260 mce_cap = KVM_MCE_CAP_SUPPORTED;
1261 r = -EFAULT;
1262 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1263 goto out;
1264 r = 0;
1265 break;
1266 }
043405e1
CO		 1267 default:
1268 r = -EINVAL;
1269 }
1270out:
1271 return r;
1272}
1273
313a3dc7
CO		 1274void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1275{
1276 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1277 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1278}
1279
1280void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1281{
1282 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1283 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1284}
1285
07716717 1286static int is_efer_nx(void)
313a3dc7 1287{
e286e86e 1288 unsigned long long efer = 0;
313a3dc7 1289
e286e86e 1290 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1291 return efer & EFER_NX;
1292}
1293
1294static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1295{
1296 int i;
1297 struct kvm_cpuid_entry2 *e, *entry;
1298
313a3dc7 1299 entry = NULL;
ad312c7c
ZX		 1300 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1301 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1302 if (e->function == 0x80000001) {
1303 entry = e;
1304 break;
1305 }
1306 }
07716717 1307 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1308 entry->edx &= ~(1 << 20);
1309 printk(KERN_INFO "kvm: guest NX capability removed\n");
1310 }
1311}
1312
07716717 1313/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1314static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1315 struct kvm_cpuid *cpuid,
1316 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1317{
1318 int r, i;
1319 struct kvm_cpuid_entry *cpuid_entries;
1320
1321 r = -E2BIG;
1322 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1323 goto out;
1324 r = -ENOMEM;
1325 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1326 if (!cpuid_entries)
1327 goto out;
1328 r = -EFAULT;
1329 if (copy_from_user(cpuid_entries, entries,
1330 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1331 goto out_free;
1332 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1333 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1334 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1335 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1336 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1337 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1338 vcpu->arch.cpuid_entries[i].index = 0;
1339 vcpu->arch.cpuid_entries[i].flags = 0;
1340 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1341 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1342 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1343 }
1344 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1345 cpuid_fix_nx_cap(vcpu);
1346 r = 0;
1347
1348out_free:
1349 vfree(cpuid_entries);
1350out:
1351 return r;
1352}
1353
1354static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1355 struct kvm_cpuid2 *cpuid,
1356 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1357{
1358 int r;
1359
1360 r = -E2BIG;
1361 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1362 goto out;
1363 r = -EFAULT;
ad312c7c 1364 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1365 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1366 goto out;
ad312c7c 1367 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1368 return 0;
1369
1370out:
1371 return r;
1372}
1373
07716717 1374static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1375 struct kvm_cpuid2 *cpuid,
1376 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1377{
1378 int r;
1379
1380 r = -E2BIG;
ad312c7c 1381 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1382 goto out;
1383 r = -EFAULT;
ad312c7c 1384 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1385 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1386 goto out;
1387 return 0;
1388
1389out:
ad312c7c 1390 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1391 return r;
1392}
1393
07716717 1394static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1395 u32 index)
07716717
DK		 1396{
1397 entry->function = function;
1398 entry->index = index;
1399 cpuid_count(entry->function, entry->index,
19355475 1400 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1401 entry->flags = 0;
1402}
1403
7faa4ee1
AK		 1404#define F(x) bit(X86_FEATURE_##x)
1405
07716717
DK		 1406static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1407 u32 index, int *nent, int maxnent)
1408{
7faa4ee1 1409 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1410#ifdef CONFIG_X86_64
7faa4ee1
AK		 1411 unsigned f_lm = F(LM);
1412#else
1413 unsigned f_lm = 0;
07716717 1414#endif
7faa4ee1
AK		 1415
1416 /* cpuid 1.edx */
1417 const u32 kvm_supported_word0_x86_features =
1418 F(FPU) | F(VME) | F(DE) | F(PSE) |
1419 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1420 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1421 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1422 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1423 0 /* Reserved, DS, ACPI */ | F(MMX) |
1424 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1425 0 /* HTT, TM, Reserved, PBE */;
1426 /* cpuid 0x80000001.edx */
1427 const u32 kvm_supported_word1_x86_features =
1428 F(FPU) | F(VME) | F(DE) | F(PSE) |
1429 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1430 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1431 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1432 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1433 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1434 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1435 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1436 /* cpuid 1.ecx */
1437 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1438 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1439 0 /* DS-CPL, VMX, SMX, EST */ |
1440 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1441 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1442 0 /* Reserved, DCA */ | F(XMM4_1) |
1443 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1444 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1445 /* cpuid 0x80000001.ecx */
07716717 1446 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1447 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1448 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1449 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1450 0 /* SKINIT */ | 0 /* WDT */;
07716717 1451
19355475 1452 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1453 get_cpu();
1454 do_cpuid_1_ent(entry, function, index);
1455 ++*nent;
1456
1457 switch (function) {
1458 case 0:
1459 entry->eax = min(entry->eax, (u32)0xb);
1460 break;
1461 case 1:
1462 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1463 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1464 break;
1465 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1466 * may return different values. This forces us to get_cpu() before
1467 * issuing the first command, and also to emulate this annoying behavior
1468 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1469 case 2: {
1470 int t, times = entry->eax & 0xff;
1471
1472 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1473 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1474 for (t = 1; t < times && *nent < maxnent; ++t) {
1475 do_cpuid_1_ent(&entry[t], function, 0);
1476 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1477 ++*nent;
1478 }
1479 break;
1480 }
1481 /* function 4 and 0xb have additional index. */
1482 case 4: {
14af3f3c 1483 int i, cache_type;
07716717
DK		 1484
1485 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1486 /* read more entries until cache_type is zero */
14af3f3c
HH		 1487 for (i = 1; *nent < maxnent; ++i) {
1488 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1489 if (!cache_type)
1490 break;
14af3f3c
HH		 1491 do_cpuid_1_ent(&entry[i], function, i);
1492 entry[i].flags |=
07716717
DK		 1493 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1494 ++*nent;
1495 }
1496 break;
1497 }
1498 case 0xb: {
14af3f3c 1499 int i, level_type;
07716717
DK		 1500
1501 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1502 /* read more entries until level_type is zero */
14af3f3c 1503 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1504 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1505 if (!level_type)
1506 break;
14af3f3c
HH		 1507 do_cpuid_1_ent(&entry[i], function, i);
1508 entry[i].flags |=
07716717
DK		 1509 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1510 ++*nent;
1511 }
1512 break;
1513 }
1514 case 0x80000000:
1515 entry->eax = min(entry->eax, 0x8000001a);
1516 break;
1517 case 0x80000001:
1518 entry->edx &= kvm_supported_word1_x86_features;
1519 entry->ecx &= kvm_supported_word6_x86_features;
1520 break;
1521 }
1522 put_cpu();
1523}
1524
7faa4ee1
AK		 1525#undef F
1526
674eea0f 1527static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1528 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1529{
1530 struct kvm_cpuid_entry2 *cpuid_entries;
1531 int limit, nent = 0, r = -E2BIG;
1532 u32 func;
1533
1534 if (cpuid->nent < 1)
1535 goto out;
1536 r = -ENOMEM;
1537 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1538 if (!cpuid_entries)
1539 goto out;
1540
1541 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1542 limit = cpuid_entries[0].eax;
1543 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1544 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1545 &nent, cpuid->nent);
07716717
DK		 1546 r = -E2BIG;
1547 if (nent >= cpuid->nent)
1548 goto out_free;
1549
1550 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1551 limit = cpuid_entries[nent - 1].eax;
1552 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1553 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1554 &nent, cpuid->nent);
cb007648
MM		 1555 r = -E2BIG;
1556 if (nent >= cpuid->nent)
1557 goto out_free;
1558
07716717
DK		 1559 r = -EFAULT;
1560 if (copy_to_user(entries, cpuid_entries,
19355475 1561 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1562 goto out_free;
1563 cpuid->nent = nent;
1564 r = 0;
1565
1566out_free:
1567 vfree(cpuid_entries);
1568out:
1569 return r;
1570}
1571
313a3dc7
CO		 1572static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1573 struct kvm_lapic_state *s)
1574{
1575 vcpu_load(vcpu);
ad312c7c 1576 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1577 vcpu_put(vcpu);
1578
1579 return 0;
1580}
1581
1582static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1583 struct kvm_lapic_state *s)
1584{
1585 vcpu_load(vcpu);
ad312c7c 1586 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1587 kvm_apic_post_state_restore(vcpu);
1588 vcpu_put(vcpu);
1589
1590 return 0;
1591}
1592
f77bc6a4
ZX		 1593static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1594 struct kvm_interrupt *irq)
1595{
1596 if (irq->irq < 0 || irq->irq >= 256)
1597 return -EINVAL;
1598 if (irqchip_in_kernel(vcpu->kvm))
1599 return -ENXIO;
1600 vcpu_load(vcpu);
1601
66fd3f7f 1602 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1603
1604 vcpu_put(vcpu);
1605
1606 return 0;
1607}
1608
c4abb7c9
JK		 1609static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1610{
1611 vcpu_load(vcpu);
1612 kvm_inject_nmi(vcpu);
1613 vcpu_put(vcpu);
1614
1615 return 0;
1616}
1617
b209749f
AK		 1618static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1619 struct kvm_tpr_access_ctl *tac)
1620{
1621 if (tac->flags)
1622 return -EINVAL;
1623 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1624 return 0;
1625}
1626
890ca9ae
HY		 1627static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1628 u64 mcg_cap)
1629{
1630 int r;
1631 unsigned bank_num = mcg_cap & 0xff, bank;
1632
1633 r = -EINVAL;
1634 if (!bank_num)
1635 goto out;
1636 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1637 goto out;
1638 r = 0;
1639 vcpu->arch.mcg_cap = mcg_cap;
1640 /* Init IA32_MCG_CTL to all 1s */
1641 if (mcg_cap & MCG_CTL_P)
1642 vcpu->arch.mcg_ctl = ~(u64)0;
1643 /* Init IA32_MCi_CTL to all 1s */
1644 for (bank = 0; bank < bank_num; bank++)
1645 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1646out:
1647 return r;
1648}
1649
1650static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1651 struct kvm_x86_mce *mce)
1652{
1653 u64 mcg_cap = vcpu->arch.mcg_cap;
1654 unsigned bank_num = mcg_cap & 0xff;
1655 u64 *banks = vcpu->arch.mce_banks;
1656
1657 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1658 return -EINVAL;
1659 /*
1660 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1661 * reporting is disabled
1662 */
1663 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1664 vcpu->arch.mcg_ctl != ~(u64)0)
1665 return 0;
1666 banks += 4 * mce->bank;
1667 /*
1668 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1669 * reporting is disabled for the bank
1670 */
1671 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1672 return 0;
1673 if (mce->status & MCI_STATUS_UC) {
1674 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1675 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1676 printk(KERN_DEBUG "kvm: set_mce: "
1677 "injects mce exception while "
1678 "previous one is in progress!\n");
1679 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1680 return 0;
1681 }
1682 if (banks[1] & MCI_STATUS_VAL)
1683 mce->status |= MCI_STATUS_OVER;
1684 banks[2] = mce->addr;
1685 banks[3] = mce->misc;
1686 vcpu->arch.mcg_status = mce->mcg_status;
1687 banks[1] = mce->status;
1688 kvm_queue_exception(vcpu, MC_VECTOR);
1689 } else if (!(banks[1] & MCI_STATUS_VAL)
1690 || !(banks[1] & MCI_STATUS_UC)) {
1691 if (banks[1] & MCI_STATUS_VAL)
1692 mce->status |= MCI_STATUS_OVER;
1693 banks[2] = mce->addr;
1694 banks[3] = mce->misc;
1695 banks[1] = mce->status;
1696 } else
1697 banks[1] |= MCI_STATUS_OVER;
1698 return 0;
1699}
1700
313a3dc7
CO		 1701long kvm_arch_vcpu_ioctl(struct file *filp,
1702 unsigned int ioctl, unsigned long arg)
1703{
1704 struct kvm_vcpu *vcpu = filp->private_data;
1705 void __user *argp = (void __user *)arg;
1706 int r;
b772ff36 1707 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1708
1709 switch (ioctl) {
1710 case KVM_GET_LAPIC: {
b772ff36 1711 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1712
b772ff36
DH		 1713 r = -ENOMEM;
1714 if (!lapic)
1715 goto out;
1716 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1717 if (r)
1718 goto out;
1719 r = -EFAULT;
b772ff36 1720 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1721 goto out;
1722 r = 0;
1723 break;
1724 }
1725 case KVM_SET_LAPIC: {
b772ff36
DH		 1726 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1727 r = -ENOMEM;
1728 if (!lapic)
1729 goto out;
313a3dc7 1730 r = -EFAULT;
b772ff36 1731 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1732 goto out;
b772ff36 1733 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1734 if (r)
1735 goto out;
1736 r = 0;
1737 break;
1738 }
f77bc6a4
ZX		 1739 case KVM_INTERRUPT: {
1740 struct kvm_interrupt irq;
1741
1742 r = -EFAULT;
1743 if (copy_from_user(&irq, argp, sizeof irq))
1744 goto out;
1745 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1746 if (r)
1747 goto out;
1748 r = 0;
1749 break;
1750 }
c4abb7c9
JK		 1751 case KVM_NMI: {
1752 r = kvm_vcpu_ioctl_nmi(vcpu);
1753 if (r)
1754 goto out;
1755 r = 0;
1756 break;
1757 }
313a3dc7
CO		 1758 case KVM_SET_CPUID: {
1759 struct kvm_cpuid __user *cpuid_arg = argp;
1760 struct kvm_cpuid cpuid;
1761
1762 r = -EFAULT;
1763 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1764 goto out;
1765 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1766 if (r)
1767 goto out;
1768 break;
1769 }
07716717
DK		 1770 case KVM_SET_CPUID2: {
1771 struct kvm_cpuid2 __user *cpuid_arg = argp;
1772 struct kvm_cpuid2 cpuid;
1773
1774 r = -EFAULT;
1775 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1776 goto out;
1777 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1778 cpuid_arg->entries);
07716717
DK		 1779 if (r)
1780 goto out;
1781 break;
1782 }
1783 case KVM_GET_CPUID2: {
1784 struct kvm_cpuid2 __user *cpuid_arg = argp;
1785 struct kvm_cpuid2 cpuid;
1786
1787 r = -EFAULT;
1788 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1789 goto out;
1790 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1791 cpuid_arg->entries);
07716717
DK		 1792 if (r)
1793 goto out;
1794 r = -EFAULT;
1795 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1796 goto out;
1797 r = 0;
1798 break;
1799 }
313a3dc7
CO		 1800 case KVM_GET_MSRS:
1801 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1802 break;
1803 case KVM_SET_MSRS:
1804 r = msr_io(vcpu, argp, do_set_msr, 0);
1805 break;
b209749f
AK		 1806 case KVM_TPR_ACCESS_REPORTING: {
1807 struct kvm_tpr_access_ctl tac;
1808
1809 r = -EFAULT;
1810 if (copy_from_user(&tac, argp, sizeof tac))
1811 goto out;
1812 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1813 if (r)
1814 goto out;
1815 r = -EFAULT;
1816 if (copy_to_user(argp, &tac, sizeof tac))
1817 goto out;
1818 r = 0;
1819 break;
1820 };
b93463aa
AK		 1821 case KVM_SET_VAPIC_ADDR: {
1822 struct kvm_vapic_addr va;
1823
1824 r = -EINVAL;
1825 if (!irqchip_in_kernel(vcpu->kvm))
1826 goto out;
1827 r = -EFAULT;
1828 if (copy_from_user(&va, argp, sizeof va))
1829 goto out;
1830 r = 0;
1831 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1832 break;
1833 }
890ca9ae
HY		 1834 case KVM_X86_SETUP_MCE: {
1835 u64 mcg_cap;
1836
1837 r = -EFAULT;
1838 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1839 goto out;
1840 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1841 break;
1842 }
1843 case KVM_X86_SET_MCE: {
1844 struct kvm_x86_mce mce;
1845
1846 r = -EFAULT;
1847 if (copy_from_user(&mce, argp, sizeof mce))
1848 goto out;
1849 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1850 break;
1851 }
313a3dc7
CO		 1852 default:
1853 r = -EINVAL;
1854 }
1855out:
7a6ce84c 1856 kfree(lapic);
313a3dc7
CO		 1857 return r;
1858}
1859
1fe779f8
CO		 1860static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1861{
1862 int ret;
1863
1864 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1865 return -1;
1866 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1867 return ret;
1868}
1869
1870static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1871 u32 kvm_nr_mmu_pages)
1872{
1873 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1874 return -EINVAL;
1875
72dc67a6 1876 down_write(&kvm->slots_lock);
7c8a83b7 1877 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1878
1879 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1880 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1881
7c8a83b7 1882 spin_unlock(&kvm->mmu_lock);
72dc67a6 1883 up_write(&kvm->slots_lock);
1fe779f8
CO		 1884 return 0;
1885}
1886
1887static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1888{
f05e70ac 1889 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1890}
1891
e9f85cde
ZX		 1892gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1893{
1894 int i;
1895 struct kvm_mem_alias *alias;
1896
d69fb81f
ZX		 1897 for (i = 0; i < kvm->arch.naliases; ++i) {
1898 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1899 if (gfn >= alias->base_gfn
1900 && gfn < alias->base_gfn + alias->npages)
1901 return alias->target_gfn + gfn - alias->base_gfn;
1902 }
1903 return gfn;
1904}
1905
1fe779f8
CO		 1906/*
1907 * Set a new alias region. Aliases map a portion of physical memory into
1908 * another portion. This is useful for memory windows, for example the PC
1909 * VGA region.
1910 */
1911static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1912 struct kvm_memory_alias *alias)
1913{
1914 int r, n;
1915 struct kvm_mem_alias *p;
1916
1917 r = -EINVAL;
1918 /* General sanity checks */
1919 if (alias->memory_size & (PAGE_SIZE - 1))
1920 goto out;
1921 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1922 goto out;
1923 if (alias->slot >= KVM_ALIAS_SLOTS)
1924 goto out;
1925 if (alias->guest_phys_addr + alias->memory_size
1926 < alias->guest_phys_addr)
1927 goto out;
1928 if (alias->target_phys_addr + alias->memory_size
1929 < alias->target_phys_addr)
1930 goto out;
1931
72dc67a6 1932 down_write(&kvm->slots_lock);
a1708ce8 1933 spin_lock(&kvm->mmu_lock);
1fe779f8 1934
d69fb81f 1935 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1936 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1937 p->npages = alias->memory_size >> PAGE_SHIFT;
1938 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1939
1940 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1941 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1942 break;
d69fb81f 1943 kvm->arch.naliases = n;
1fe779f8 1944
a1708ce8 1945 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1946 kvm_mmu_zap_all(kvm);
1947
72dc67a6 1948 up_write(&kvm->slots_lock);
1fe779f8
CO		 1949
1950 return 0;
1951
1952out:
1953 return r;
1954}
1955
1956static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1957{
1958 int r;
1959
1960 r = 0;
1961 switch (chip->chip_id) {
1962 case KVM_IRQCHIP_PIC_MASTER:
1963 memcpy(&chip->chip.pic,
1964 &pic_irqchip(kvm)->pics[0],
1965 sizeof(struct kvm_pic_state));
1966 break;
1967 case KVM_IRQCHIP_PIC_SLAVE:
1968 memcpy(&chip->chip.pic,
1969 &pic_irqchip(kvm)->pics[1],
1970 sizeof(struct kvm_pic_state));
1971 break;
1972 case KVM_IRQCHIP_IOAPIC:
1973 memcpy(&chip->chip.ioapic,
1974 ioapic_irqchip(kvm),
1975 sizeof(struct kvm_ioapic_state));
1976 break;
1977 default:
1978 r = -EINVAL;
1979 break;
1980 }
1981 return r;
1982}
1983
1984static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1985{
1986 int r;
1987
1988 r = 0;
1989 switch (chip->chip_id) {
1990 case KVM_IRQCHIP_PIC_MASTER:
1991 memcpy(&pic_irqchip(kvm)->pics[0],
1992 &chip->chip.pic,
1993 sizeof(struct kvm_pic_state));
1994 break;
1995 case KVM_IRQCHIP_PIC_SLAVE:
1996 memcpy(&pic_irqchip(kvm)->pics[1],
1997 &chip->chip.pic,
1998 sizeof(struct kvm_pic_state));
1999 break;
2000 case KVM_IRQCHIP_IOAPIC:
2001 memcpy(ioapic_irqchip(kvm),
2002 &chip->chip.ioapic,
2003 sizeof(struct kvm_ioapic_state));
2004 break;
2005 default:
2006 r = -EINVAL;
2007 break;
2008 }
2009 kvm_pic_update_irq(pic_irqchip(kvm));
2010 return r;
2011}
2012
e0f63cb9
SY		 2013static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2014{
2015 int r = 0;
2016
2017 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2018 return r;
2019}
2020
2021static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2022{
2023 int r = 0;
2024
2025 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2026 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
2027 return r;
2028}
2029
52d939a0
MT		 2030static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2031 struct kvm_reinject_control *control)
2032{
2033 if (!kvm->arch.vpit)
2034 return -ENXIO;
2035 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2036 return 0;
2037}
2038
5bb064dc
ZX		 2039/*
2040 * Get (and clear) the dirty memory log for a memory slot.
2041 */
2042int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2043 struct kvm_dirty_log *log)
2044{
2045 int r;
2046 int n;
2047 struct kvm_memory_slot *memslot;
2048 int is_dirty = 0;
2049
72dc67a6 2050 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2051
2052 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2053 if (r)
2054 goto out;
2055
2056 /* If nothing is dirty, don't bother messing with page tables. */
2057 if (is_dirty) {
7c8a83b7 2058 spin_lock(&kvm->mmu_lock);
5bb064dc 2059 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2060 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2061 kvm_flush_remote_tlbs(kvm);
2062 memslot = &kvm->memslots[log->slot];
2063 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2064 memset(memslot->dirty_bitmap, 0, n);
2065 }
2066 r = 0;
2067out:
72dc67a6 2068 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2069 return r;
2070}
2071
1fe779f8
CO		 2072long kvm_arch_vm_ioctl(struct file *filp,
2073 unsigned int ioctl, unsigned long arg)
2074{
2075 struct kvm *kvm = filp->private_data;
2076 void __user *argp = (void __user *)arg;
2077 int r = -EINVAL;
f0d66275
DH		 2078 /*
2079 * This union makes it completely explicit to gcc-3.x
2080 * that these two variables' stack usage should be
2081 * combined, not added together.
2082 */
2083 union {
2084 struct kvm_pit_state ps;
2085 struct kvm_memory_alias alias;
c5ff41ce 2086 struct kvm_pit_config pit_config;
f0d66275 2087 } u;
1fe779f8
CO		 2088
2089 switch (ioctl) {
2090 case KVM_SET_TSS_ADDR:
2091 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2092 if (r < 0)
2093 goto out;
2094 break;
2095 case KVM_SET_MEMORY_REGION: {
2096 struct kvm_memory_region kvm_mem;
2097 struct kvm_userspace_memory_region kvm_userspace_mem;
2098
2099 r = -EFAULT;
2100 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2101 goto out;
2102 kvm_userspace_mem.slot = kvm_mem.slot;
2103 kvm_userspace_mem.flags = kvm_mem.flags;
2104 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2105 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2106 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2107 if (r)
2108 goto out;
2109 break;
2110 }
2111 case KVM_SET_NR_MMU_PAGES:
2112 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2113 if (r)
2114 goto out;
2115 break;
2116 case KVM_GET_NR_MMU_PAGES:
2117 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2118 break;
f0d66275 2119 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2120 r = -EFAULT;
f0d66275 2121 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2122 goto out;
f0d66275 2123 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2124 if (r)
2125 goto out;
2126 break;
1fe779f8
CO		 2127 case KVM_CREATE_IRQCHIP:
2128 r = -ENOMEM;
d7deeeb0
ZX		 2129 kvm->arch.vpic = kvm_create_pic(kvm);
2130 if (kvm->arch.vpic) {
1fe779f8
CO		 2131 r = kvm_ioapic_init(kvm);
2132 if (r) {
d7deeeb0
ZX		 2133 kfree(kvm->arch.vpic);
2134 kvm->arch.vpic = NULL;
1fe779f8
CO		 2135 goto out;
2136 }
2137 } else
2138 goto out;
399ec807
AK		 2139 r = kvm_setup_default_irq_routing(kvm);
2140 if (r) {
2141 kfree(kvm->arch.vpic);
2142 kfree(kvm->arch.vioapic);
2143 goto out;
2144 }
1fe779f8 2145 break;
7837699f 2146 case KVM_CREATE_PIT:
c5ff41ce
JK		 2147 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2148 goto create_pit;
2149 case KVM_CREATE_PIT2:
2150 r = -EFAULT;
2151 if (copy_from_user(&u.pit_config, argp,
2152 sizeof(struct kvm_pit_config)))
2153 goto out;
2154 create_pit:
269e05e4
AK		 2155 mutex_lock(&kvm->lock);
2156 r = -EEXIST;
2157 if (kvm->arch.vpit)
2158 goto create_pit_unlock;
7837699f 2159 r = -ENOMEM;
c5ff41ce 2160 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2161 if (kvm->arch.vpit)
2162 r = 0;
269e05e4
AK		 2163 create_pit_unlock:
2164 mutex_unlock(&kvm->lock);
7837699f 2165 break;
4925663a 2166 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2167 case KVM_IRQ_LINE: {
2168 struct kvm_irq_level irq_event;
2169
2170 r = -EFAULT;
2171 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2172 goto out;
2173 if (irqchip_in_kernel(kvm)) {
4925663a 2174 __s32 status;
fa40a821 2175 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2176 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2177 irq_event.irq, irq_event.level);
fa40a821 2178 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2179 if (ioctl == KVM_IRQ_LINE_STATUS) {
2180 irq_event.status = status;
2181 if (copy_to_user(argp, &irq_event,
2182 sizeof irq_event))
2183 goto out;
2184 }
1fe779f8
CO		 2185 r = 0;
2186 }
2187 break;
2188 }
2189 case KVM_GET_IRQCHIP: {
2190 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2191 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2192
f0d66275
DH		 2193 r = -ENOMEM;
2194 if (!chip)
1fe779f8 2195 goto out;
f0d66275
DH		 2196 r = -EFAULT;
2197 if (copy_from_user(chip, argp, sizeof *chip))
2198 goto get_irqchip_out;
1fe779f8
CO		 2199 r = -ENXIO;
2200 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2201 goto get_irqchip_out;
2202 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2203 if (r)
f0d66275 2204 goto get_irqchip_out;
1fe779f8 2205 r = -EFAULT;
f0d66275
DH		 2206 if (copy_to_user(argp, chip, sizeof *chip))
2207 goto get_irqchip_out;
1fe779f8 2208 r = 0;
f0d66275
DH		 2209 get_irqchip_out:
2210 kfree(chip);
2211 if (r)
2212 goto out;
1fe779f8
CO		 2213 break;
2214 }
2215 case KVM_SET_IRQCHIP: {
2216 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2217 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2218
f0d66275
DH		 2219 r = -ENOMEM;
2220 if (!chip)
1fe779f8 2221 goto out;
f0d66275
DH		 2222 r = -EFAULT;
2223 if (copy_from_user(chip, argp, sizeof *chip))
2224 goto set_irqchip_out;
1fe779f8
CO		 2225 r = -ENXIO;
2226 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2227 goto set_irqchip_out;
2228 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2229 if (r)
f0d66275 2230 goto set_irqchip_out;
1fe779f8 2231 r = 0;
f0d66275
DH		 2232 set_irqchip_out:
2233 kfree(chip);
2234 if (r)
2235 goto out;
1fe779f8
CO		 2236 break;
2237 }
e0f63cb9 2238 case KVM_GET_PIT: {
e0f63cb9 2239 r = -EFAULT;
f0d66275 2240 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2241 goto out;
2242 r = -ENXIO;
2243 if (!kvm->arch.vpit)
2244 goto out;
f0d66275 2245 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2246 if (r)
2247 goto out;
2248 r = -EFAULT;
f0d66275 2249 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2250 goto out;
2251 r = 0;
2252 break;
2253 }
2254 case KVM_SET_PIT: {
e0f63cb9 2255 r = -EFAULT;
f0d66275 2256 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2257 goto out;
2258 r = -ENXIO;
2259 if (!kvm->arch.vpit)
2260 goto out;
f0d66275 2261 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2262 if (r)
2263 goto out;
2264 r = 0;
2265 break;
2266 }
52d939a0
MT		 2267 case KVM_REINJECT_CONTROL: {
2268 struct kvm_reinject_control control;
2269 r = -EFAULT;
2270 if (copy_from_user(&control, argp, sizeof(control)))
2271 goto out;
2272 r = kvm_vm_ioctl_reinject(kvm, &control);
2273 if (r)
2274 goto out;
2275 r = 0;
2276 break;
2277 }
1fe779f8
CO		 2278 default:
2279 ;
2280 }
2281out:
2282 return r;
2283}
2284
a16b043c 2285static void kvm_init_msr_list(void)
043405e1
CO		 2286{
2287 u32 dummy[2];
2288 unsigned i, j;
2289
2290 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2291 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2292 continue;
2293 if (j < i)
2294 msrs_to_save[j] = msrs_to_save[i];
2295 j++;
2296 }
2297 num_msrs_to_save = j;
2298}
2299
bbd9b64e
CO		 2300/*
2301 * Only apic need an MMIO device hook, so shortcut now..
2302 */
2303static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2304 gpa_t addr, int len,
2305 int is_write)
bbd9b64e
CO		 2306{
2307 struct kvm_io_device *dev;
2308
ad312c7c
ZX		 2309 if (vcpu->arch.apic) {
2310 dev = &vcpu->arch.apic->dev;
d76685c4 2311 if (kvm_iodevice_in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2312 return dev;
2313 }
2314 return NULL;
2315}
2316
2317
2318static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2319 gpa_t addr, int len,
2320 int is_write)
bbd9b64e
CO		 2321{
2322 struct kvm_io_device *dev;
2323
92760499 2324 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2325 if (dev == NULL)
92760499
LV		 2326 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2327 is_write);
bbd9b64e
CO		 2328 return dev;
2329}
2330
cded19f3
HE		 2331static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2332 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2333{
2334 void *data = val;
10589a46 2335 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2336
2337 while (bytes) {
ad312c7c 2338 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2339 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2340 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2341 int ret;
2342
10589a46
MT		 2343 if (gpa == UNMAPPED_GVA) {
2344 r = X86EMUL_PROPAGATE_FAULT;
2345 goto out;
2346 }
77c2002e 2347 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2348 if (ret < 0) {
2349 r = X86EMUL_UNHANDLEABLE;
2350 goto out;
2351 }
bbd9b64e 2352
77c2002e
IE		 2353 bytes -= toread;
2354 data += toread;
2355 addr += toread;
bbd9b64e 2356 }
10589a46 2357out:
10589a46 2358 return r;
bbd9b64e 2359}
77c2002e 2360
cded19f3
HE		 2361static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2362 struct kvm_vcpu *vcpu)
77c2002e
IE		 2363{
2364 void *data = val;
2365 int r = X86EMUL_CONTINUE;
2366
2367 while (bytes) {
2368 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2369 unsigned offset = addr & (PAGE_SIZE-1);
2370 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2371 int ret;
2372
2373 if (gpa == UNMAPPED_GVA) {
2374 r = X86EMUL_PROPAGATE_FAULT;
2375 goto out;
2376 }
2377 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2378 if (ret < 0) {
2379 r = X86EMUL_UNHANDLEABLE;
2380 goto out;
2381 }
2382
2383 bytes -= towrite;
2384 data += towrite;
2385 addr += towrite;
2386 }
2387out:
2388 return r;
2389}
2390
bbd9b64e 2391
bbd9b64e
CO		 2392static int emulator_read_emulated(unsigned long addr,
2393 void *val,
2394 unsigned int bytes,
2395 struct kvm_vcpu *vcpu)
2396{
2397 struct kvm_io_device *mmio_dev;
2398 gpa_t gpa;
2399
2400 if (vcpu->mmio_read_completed) {
2401 memcpy(val, vcpu->mmio_data, bytes);
2402 vcpu->mmio_read_completed = 0;
2403 return X86EMUL_CONTINUE;
2404 }
2405
ad312c7c 2406 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2407
2408 /* For APIC access vmexit */
2409 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2410 goto mmio;
2411
77c2002e
IE		 2412 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2413 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2414 return X86EMUL_CONTINUE;
2415 if (gpa == UNMAPPED_GVA)
2416 return X86EMUL_PROPAGATE_FAULT;
2417
2418mmio:
2419 /*
2420 * Is this MMIO handled locally?
2421 */
10589a46 2422 mutex_lock(&vcpu->kvm->lock);
92760499 2423 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
fa40a821 2424 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2425 if (mmio_dev) {
2426 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
2427 return X86EMUL_CONTINUE;
2428 }
2429
2430 vcpu->mmio_needed = 1;
2431 vcpu->mmio_phys_addr = gpa;
2432 vcpu->mmio_size = bytes;
2433 vcpu->mmio_is_write = 0;
2434
2435 return X86EMUL_UNHANDLEABLE;
2436}
2437
3200f405 2438int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2439 const void *val, int bytes)
bbd9b64e
CO		 2440{
2441 int ret;
2442
2443 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2444 if (ret < 0)
bbd9b64e 2445 return 0;
ad218f85 2446 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2447 return 1;
2448}
2449
2450static int emulator_write_emulated_onepage(unsigned long addr,
2451 const void *val,
2452 unsigned int bytes,
2453 struct kvm_vcpu *vcpu)
2454{
2455 struct kvm_io_device *mmio_dev;
10589a46
MT		 2456 gpa_t gpa;
2457
10589a46 2458 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2459
2460 if (gpa == UNMAPPED_GVA) {
c3c91fee 2461 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2462 return X86EMUL_PROPAGATE_FAULT;
2463 }
2464
2465 /* For APIC access vmexit */
2466 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2467 goto mmio;
2468
2469 if (emulator_write_phys(vcpu, gpa, val, bytes))
2470 return X86EMUL_CONTINUE;
2471
2472mmio:
2473 /*
2474 * Is this MMIO handled locally?
2475 */
10589a46 2476 mutex_lock(&vcpu->kvm->lock);
92760499 2477 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
fa40a821 2478 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2479 if (mmio_dev) {
2480 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
2481 return X86EMUL_CONTINUE;
2482 }
2483
2484 vcpu->mmio_needed = 1;
2485 vcpu->mmio_phys_addr = gpa;
2486 vcpu->mmio_size = bytes;
2487 vcpu->mmio_is_write = 1;
2488 memcpy(vcpu->mmio_data, val, bytes);
2489
2490 return X86EMUL_CONTINUE;
2491}
2492
2493int emulator_write_emulated(unsigned long addr,
2494 const void *val,
2495 unsigned int bytes,
2496 struct kvm_vcpu *vcpu)
2497{
2498 /* Crossing a page boundary? */
2499 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2500 int rc, now;
2501
2502 now = -addr & ~PAGE_MASK;
2503 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2504 if (rc != X86EMUL_CONTINUE)
2505 return rc;
2506 addr += now;
2507 val += now;
2508 bytes -= now;
2509 }
2510 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2511}
2512EXPORT_SYMBOL_GPL(emulator_write_emulated);
2513
2514static int emulator_cmpxchg_emulated(unsigned long addr,
2515 const void *old,
2516 const void *new,
2517 unsigned int bytes,
2518 struct kvm_vcpu *vcpu)
2519{
2520 static int reported;
2521
2522 if (!reported) {
2523 reported = 1;
2524 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2525 }
2bacc55c
MT		 2526#ifndef CONFIG_X86_64
2527 /* guests cmpxchg8b have to be emulated atomically */
2528 if (bytes == 8) {
10589a46 2529 gpa_t gpa;
2bacc55c 2530 struct page *page;
c0b49b0d 2531 char *kaddr;
2bacc55c
MT		 2532 u64 val;
2533
10589a46
MT		 2534 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2535
2bacc55c
MT		 2536 if (gpa == UNMAPPED_GVA ||
2537 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2538 goto emul_write;
2539
2540 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2541 goto emul_write;
2542
2543 val = *(u64 *)new;
72dc67a6 2544
2bacc55c 2545 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2546
c0b49b0d
AM		 2547 kaddr = kmap_atomic(page, KM_USER0);
2548 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2549 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2550 kvm_release_page_dirty(page);
2551 }
3200f405 2552emul_write:
2bacc55c
MT		 2553#endif
2554
bbd9b64e
CO		 2555 return emulator_write_emulated(addr, new, bytes, vcpu);
2556}
2557
2558static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2559{
2560 return kvm_x86_ops->get_segment_base(vcpu, seg);
2561}
2562
2563int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2564{
a7052897 2565 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2566 return X86EMUL_CONTINUE;
2567}
2568
2569int emulate_clts(struct kvm_vcpu *vcpu)
2570{
54e445ca 2571 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2572 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2573 return X86EMUL_CONTINUE;
2574}
2575
2576int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2577{
2578 struct kvm_vcpu *vcpu = ctxt->vcpu;
2579
2580 switch (dr) {
2581 case 0 ... 3:
2582 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2583 return X86EMUL_CONTINUE;
2584 default:
b8688d51 2585 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2586 return X86EMUL_UNHANDLEABLE;
2587 }
2588}
2589
2590int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2591{
2592 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2593 int exception;
2594
2595 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2596 if (exception) {
2597 /* FIXME: better handling */
2598 return X86EMUL_UNHANDLEABLE;
2599 }
2600 return X86EMUL_CONTINUE;
2601}
2602
2603void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2604{
bbd9b64e 2605 u8 opcodes[4];
5fdbf976 2606 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2607 unsigned long rip_linear;
2608
f76c710d 2609 if (!printk_ratelimit())
bbd9b64e
CO		 2610 return;
2611
25be4608
GC		 2612 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2613
77c2002e 2614 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2615
2616 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2617 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2618}
2619EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2620
14af3f3c 2621static struct x86_emulate_ops emulate_ops = {
77c2002e 2622 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2623 .read_emulated = emulator_read_emulated,
2624 .write_emulated = emulator_write_emulated,
2625 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2626};
2627
5fdbf976
MT		 2628static void cache_all_regs(struct kvm_vcpu *vcpu)
2629{
2630 kvm_register_read(vcpu, VCPU_REGS_RAX);
2631 kvm_register_read(vcpu, VCPU_REGS_RSP);
2632 kvm_register_read(vcpu, VCPU_REGS_RIP);
2633 vcpu->arch.regs_dirty = ~0;
2634}
2635
bbd9b64e
CO		 2636int emulate_instruction(struct kvm_vcpu *vcpu,
2637 struct kvm_run *run,
2638 unsigned long cr2,
2639 u16 error_code,
571008da 2640 int emulation_type)
bbd9b64e 2641{
310b5d30 2642 int r, shadow_mask;
571008da 2643 struct decode_cache *c;
bbd9b64e 2644
26eef70c 2645 kvm_clear_exception_queue(vcpu);
ad312c7c 2646 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2647 /*
2648 * TODO: fix x86_emulate.c to use guest_read/write_register
2649 * instead of direct ->regs accesses, can save hundred cycles
2650 * on Intel for instructions that don't read/change RSP, for
2651 * for example.
2652 */
2653 cache_all_regs(vcpu);
bbd9b64e
CO		 2654
2655 vcpu->mmio_is_write = 0;
ad312c7c 2656 vcpu->arch.pio.string = 0;
bbd9b64e 2657
571008da 2658 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2659 int cs_db, cs_l;
2660 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2661
ad312c7c
ZX		 2662 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2663 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2664 vcpu->arch.emulate_ctxt.mode =
2665 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2666 ? X86EMUL_MODE_REAL : cs_l
2667 ? X86EMUL_MODE_PROT64 : cs_db
2668 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2669
ad312c7c 2670 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2671
2672 /* Reject the instructions other than VMCALL/VMMCALL when
2673 * try to emulate invalid opcode */
2674 c = &vcpu->arch.emulate_ctxt.decode;
2675 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2676 (!(c->twobyte && c->b == 0x01 &&
2677 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2678 c->modrm_mod == 3 && c->modrm_rm == 1)))
2679 return EMULATE_FAIL;
2680
f2b5756b 2681 ++vcpu->stat.insn_emulation;
bbd9b64e 2682 if (r) {
f2b5756b 2683 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2684 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2685 return EMULATE_DONE;
2686 return EMULATE_FAIL;
2687 }
2688 }
2689
ba8afb6b
GN		 2690 if (emulation_type & EMULTYPE_SKIP) {
2691 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2692 return EMULATE_DONE;
2693 }
2694
ad312c7c 2695 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2696 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2697
2698 if (r == 0)
2699 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2700
ad312c7c 2701 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2702 return EMULATE_DO_MMIO;
2703
2704 if ((r || vcpu->mmio_is_write) && run) {
2705 run->exit_reason = KVM_EXIT_MMIO;
2706 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2707 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2708 run->mmio.len = vcpu->mmio_size;
2709 run->mmio.is_write = vcpu->mmio_is_write;
2710 }
2711
2712 if (r) {
2713 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2714 return EMULATE_DONE;
2715 if (!vcpu->mmio_needed) {
2716 kvm_report_emulation_failure(vcpu, "mmio");
2717 return EMULATE_FAIL;
2718 }
2719 return EMULATE_DO_MMIO;
2720 }
2721
ad312c7c 2722 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2723
2724 if (vcpu->mmio_is_write) {
2725 vcpu->mmio_needed = 0;
2726 return EMULATE_DO_MMIO;
2727 }
2728
2729 return EMULATE_DONE;
2730}
2731EXPORT_SYMBOL_GPL(emulate_instruction);
2732
de7d789a
CO		 2733static int pio_copy_data(struct kvm_vcpu *vcpu)
2734{
ad312c7c 2735 void *p = vcpu->arch.pio_data;
0f346074 2736 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2737 unsigned bytes;
0f346074 2738 int ret;
de7d789a 2739
ad312c7c
ZX		 2740 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2741 if (vcpu->arch.pio.in)
0f346074 2742 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2743 else
0f346074
IE		 2744 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2745 return ret;
de7d789a
CO		 2746}
2747
2748int complete_pio(struct kvm_vcpu *vcpu)
2749{
ad312c7c 2750 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2751 long delta;
2752 int r;
5fdbf976 2753 unsigned long val;
de7d789a
CO		 2754
2755 if (!io->string) {
5fdbf976
MT		 2756 if (io->in) {
2757 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2758 memcpy(&val, vcpu->arch.pio_data, io->size);
2759 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2760 }
de7d789a
CO		 2761 } else {
2762 if (io->in) {
2763 r = pio_copy_data(vcpu);
5fdbf976 2764 if (r)
de7d789a 2765 return r;
de7d789a
CO		 2766 }
2767
2768 delta = 1;
2769 if (io->rep) {
2770 delta *= io->cur_count;
2771 /*
2772 * The size of the register should really depend on
2773 * current address size.
2774 */
5fdbf976
MT		 2775 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2776 val -= delta;
2777 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2778 }
2779 if (io->down)
2780 delta = -delta;
2781 delta *= io->size;
5fdbf976
MT		 2782 if (io->in) {
2783 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2784 val += delta;
2785 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2786 } else {
2787 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2788 val += delta;
2789 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2790 }
de7d789a
CO		 2791 }
2792
de7d789a
CO		 2793 io->count -= io->cur_count;
2794 io->cur_count = 0;
2795
2796 return 0;
2797}
2798
2799static void kernel_pio(struct kvm_io_device *pio_dev,
2800 struct kvm_vcpu *vcpu,
2801 void *pd)
2802{
2803 /* TODO: String I/O for in kernel device */
2804
ad312c7c
ZX		 2805 if (vcpu->arch.pio.in)
2806 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2807 vcpu->arch.pio.size,
de7d789a
CO		 2808 pd);
2809 else
ad312c7c
ZX		 2810 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2811 vcpu->arch.pio.size,
de7d789a 2812 pd);
de7d789a
CO		 2813}
2814
2815static void pio_string_write(struct kvm_io_device *pio_dev,
2816 struct kvm_vcpu *vcpu)
2817{
ad312c7c
ZX		 2818 struct kvm_pio_request *io = &vcpu->arch.pio;
2819 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2820 int i;
2821
de7d789a
CO		 2822 for (i = 0; i < io->cur_count; i++) {
2823 kvm_iodevice_write(pio_dev, io->port,
2824 io->size,
2825 pd);
2826 pd += io->size;
2827 }
de7d789a
CO		 2828}
2829
2830static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2831 gpa_t addr, int len,
2832 int is_write)
de7d789a 2833{
92760499 2834 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2835}
2836
2837int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2838 int size, unsigned port)
2839{
2840 struct kvm_io_device *pio_dev;
5fdbf976 2841 unsigned long val;
de7d789a
CO		 2842
2843 vcpu->run->exit_reason = KVM_EXIT_IO;
2844 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2845 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2846 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2847 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2848 vcpu->run->io.port = vcpu->arch.pio.port = port;
2849 vcpu->arch.pio.in = in;
2850 vcpu->arch.pio.string = 0;
2851 vcpu->arch.pio.down = 0;
ad312c7c 2852 vcpu->arch.pio.rep = 0;
de7d789a 2853
2714d1d3
FEL		 2854 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2855 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2856 handler);
2857 else
2858 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2859 handler);
2860
5fdbf976
MT		 2861 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2862 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2863
fa40a821 2864 mutex_lock(&vcpu->kvm->lock);
92760499 2865 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
fa40a821 2866 mutex_unlock(&vcpu->kvm->lock);
de7d789a 2867 if (pio_dev) {
ad312c7c 2868 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2869 complete_pio(vcpu);
2870 return 1;
2871 }
2872 return 0;
2873}
2874EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2875
2876int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2877 int size, unsigned long count, int down,
2878 gva_t address, int rep, unsigned port)
2879{
2880 unsigned now, in_page;
0f346074 2881 int ret = 0;
de7d789a
CO		 2882 struct kvm_io_device *pio_dev;
2883
2884 vcpu->run->exit_reason = KVM_EXIT_IO;
2885 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2886 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2887 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2888 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2889 vcpu->run->io.port = vcpu->arch.pio.port = port;
2890 vcpu->arch.pio.in = in;
2891 vcpu->arch.pio.string = 1;
2892 vcpu->arch.pio.down = down;
ad312c7c 2893 vcpu->arch.pio.rep = rep;
de7d789a 2894
2714d1d3
FEL		 2895 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2896 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2897 handler);
2898 else
2899 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2900 handler);
2901
de7d789a
CO		 2902 if (!count) {
2903 kvm_x86_ops->skip_emulated_instruction(vcpu);
2904 return 1;
2905 }
2906
2907 if (!down)
2908 in_page = PAGE_SIZE - offset_in_page(address);
2909 else
2910 in_page = offset_in_page(address) + size;
2911 now = min(count, (unsigned long)in_page / size);
0f346074 2912 if (!now)
de7d789a 2913 now = 1;
de7d789a
CO		 2914 if (down) {
2915 /*
2916 * String I/O in reverse. Yuck. Kill the guest, fix later.
2917 */
2918 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2919 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2920 return 1;
2921 }
2922 vcpu->run->io.count = now;
ad312c7c 2923 vcpu->arch.pio.cur_count = now;
de7d789a 2924
ad312c7c 2925 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2926 kvm_x86_ops->skip_emulated_instruction(vcpu);
2927
0f346074 2928 vcpu->arch.pio.guest_gva = address;
de7d789a 2929
fa40a821 2930 mutex_lock(&vcpu->kvm->lock);
92760499
LV		 2931 pio_dev = vcpu_find_pio_dev(vcpu, port,
2932 vcpu->arch.pio.cur_count,
2933 !vcpu->arch.pio.in);
fa40a821
MT		 2934 mutex_unlock(&vcpu->kvm->lock);
2935
ad312c7c 2936 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2937 /* string PIO write */
2938 ret = pio_copy_data(vcpu);
0f346074
IE		 2939 if (ret == X86EMUL_PROPAGATE_FAULT) {
2940 kvm_inject_gp(vcpu, 0);
2941 return 1;
2942 }
2943 if (ret == 0 && pio_dev) {
de7d789a
CO		 2944 pio_string_write(pio_dev, vcpu);
2945 complete_pio(vcpu);
ad312c7c 2946 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2947 ret = 1;
2948 }
2949 } else if (pio_dev)
2950 pr_unimpl(vcpu, "no string pio read support yet, "
2951 "port %x size %d count %ld\n",
2952 port, size, count);
2953
2954 return ret;
2955}
2956EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2957
c8076604
GH		 2958static void bounce_off(void *info)
2959{
2960 /* nothing */
2961}
2962
2963static unsigned int ref_freq;
2964static unsigned long tsc_khz_ref;
2965
2966static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2967 void *data)
2968{
2969 struct cpufreq_freqs *freq = data;
2970 struct kvm *kvm;
2971 struct kvm_vcpu *vcpu;
2972 int i, send_ipi = 0;
2973
2974 if (!ref_freq)
2975 ref_freq = freq->old;
2976
2977 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2978 return 0;
2979 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2980 return 0;
2981 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2982
2983 spin_lock(&kvm_lock);
2984 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 2985 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 2986 if (vcpu->cpu != freq->cpu)
2987 continue;
2988 if (!kvm_request_guest_time_update(vcpu))
2989 continue;
2990 if (vcpu->cpu != smp_processor_id())
2991 send_ipi++;
2992 }
2993 }
2994 spin_unlock(&kvm_lock);
2995
2996 if (freq->old < freq->new && send_ipi) {
2997 /*
2998 * We upscale the frequency. Must make the guest
2999 * doesn't see old kvmclock values while running with
3000 * the new frequency, otherwise we risk the guest sees
3001 * time go backwards.
3002 *
3003 * In case we update the frequency for another cpu
3004 * (which might be in guest context) send an interrupt
3005 * to kick the cpu out of guest context. Next time
3006 * guest context is entered kvmclock will be updated,
3007 * so the guest will not see stale values.
3008 */
3009 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3010 }
3011 return 0;
3012}
3013
3014static struct notifier_block kvmclock_cpufreq_notifier_block = {
3015 .notifier_call = kvmclock_cpufreq_notifier
3016};
3017
f8c16bba 3018int kvm_arch_init(void *opaque)
043405e1 3019{
c8076604 3020 int r, cpu;
f8c16bba
ZX		 3021 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3022
f8c16bba
ZX		 3023 if (kvm_x86_ops) {
3024 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3025 r = -EEXIST;
3026 goto out;
f8c16bba
ZX		 3027 }
3028
3029 if (!ops->cpu_has_kvm_support()) {
3030 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3031 r = -EOPNOTSUPP;
3032 goto out;
f8c16bba
ZX		 3033 }
3034 if (ops->disabled_by_bios()) {
3035 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3036 r = -EOPNOTSUPP;
3037 goto out;
f8c16bba
ZX		 3038 }
3039
97db56ce
AK		 3040 r = kvm_mmu_module_init();
3041 if (r)
3042 goto out;
3043
3044 kvm_init_msr_list();
3045
f8c16bba 3046 kvm_x86_ops = ops;
56c6d28a 3047 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3048 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3049 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3050 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3051
3052 for_each_possible_cpu(cpu)
3053 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3054 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3055 tsc_khz_ref = tsc_khz;
3056 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3057 CPUFREQ_TRANSITION_NOTIFIER);
3058 }
3059
f8c16bba 3060 return 0;
56c6d28a
ZX		 3061
3062out:
56c6d28a 3063 return r;
043405e1 3064}
8776e519 3065
f8c16bba
ZX		 3066void kvm_arch_exit(void)
3067{
888d256e
JK		 3068 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3069 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3070 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3071 kvm_x86_ops = NULL;
56c6d28a
ZX		 3072 kvm_mmu_module_exit();
3073}
f8c16bba 3074
8776e519
HB		 3075int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3076{
3077 ++vcpu->stat.halt_exits;
2714d1d3 3078 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 3079 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3080 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3081 return 1;
3082 } else {
3083 vcpu->run->exit_reason = KVM_EXIT_HLT;
3084 return 0;
3085 }
3086}
3087EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3088
2f333bcb
MT		 3089static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3090 unsigned long a1)
3091{
3092 if (is_long_mode(vcpu))
3093 return a0;
3094 else
3095 return a0 | ((gpa_t)a1 << 32);
3096}
3097
8776e519
HB		 3098int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3099{
3100 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3101 int r = 1;
8776e519 3102
5fdbf976
MT		 3103 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3104 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3105 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3106 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3107 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3108
2714d1d3
FEL		 3109 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
3110
8776e519
HB		 3111 if (!is_long_mode(vcpu)) {
3112 nr &= 0xFFFFFFFF;
3113 a0 &= 0xFFFFFFFF;
3114 a1 &= 0xFFFFFFFF;
3115 a2 &= 0xFFFFFFFF;
3116 a3 &= 0xFFFFFFFF;
3117 }
3118
3119 switch (nr) {
b93463aa
AK		 3120 case KVM_HC_VAPIC_POLL_IRQ:
3121 ret = 0;
3122 break;
2f333bcb
MT		 3123 case KVM_HC_MMU_OP:
3124 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3125 break;
8776e519
HB		 3126 default:
3127 ret = -KVM_ENOSYS;
3128 break;
3129 }
5fdbf976 3130 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3131 ++vcpu->stat.hypercalls;
2f333bcb 3132 return r;
8776e519
HB		 3133}
3134EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3135
3136int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3137{
3138 char instruction[3];
3139 int ret = 0;
5fdbf976 3140 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3141
8776e519
HB		 3142
3143 /*
3144 * Blow out the MMU to ensure that no other VCPU has an active mapping
3145 * to ensure that the updated hypercall appears atomically across all
3146 * VCPUs.
3147 */
3148 kvm_mmu_zap_all(vcpu->kvm);
3149
8776e519 3150 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3151 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3152 != X86EMUL_CONTINUE)
3153 ret = -EFAULT;
3154
8776e519
HB		 3155 return ret;
3156}
3157
3158static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3159{
3160 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3161}
3162
3163void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3164{
3165 struct descriptor_table dt = { limit, base };
3166
3167 kvm_x86_ops->set_gdt(vcpu, &dt);
3168}
3169
3170void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3171{
3172 struct descriptor_table dt = { limit, base };
3173
3174 kvm_x86_ops->set_idt(vcpu, &dt);
3175}
3176
3177void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3178 unsigned long *rflags)
3179{
2d3ad1f4 3180 kvm_lmsw(vcpu, msw);
8776e519
HB		 3181 *rflags = kvm_x86_ops->get_rflags(vcpu);
3182}
3183
3184unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3185{
54e445ca
JR		 3186 unsigned long value;
3187
8776e519
HB		 3188 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3189 switch (cr) {
3190 case 0:
54e445ca
JR		 3191 value = vcpu->arch.cr0;
3192 break;
8776e519 3193 case 2:
54e445ca
JR		 3194 value = vcpu->arch.cr2;
3195 break;
8776e519 3196 case 3:
54e445ca
JR		 3197 value = vcpu->arch.cr3;
3198 break;
8776e519 3199 case 4:
54e445ca
JR		 3200 value = vcpu->arch.cr4;
3201 break;
152ff9be 3202 case 8:
54e445ca
JR		 3203 value = kvm_get_cr8(vcpu);
3204 break;
8776e519 3205 default:
b8688d51 3206 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3207 return 0;
3208 }
54e445ca
JR		 3209 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
3210 (u32)((u64)value >> 32), handler);
3211
3212 return value;
8776e519
HB		 3213}
3214
3215void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3216 unsigned long *rflags)
3217{
54e445ca
JR		 3218 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
3219 (u32)((u64)val >> 32), handler);
3220
8776e519
HB		 3221 switch (cr) {
3222 case 0:
2d3ad1f4 3223 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3224 *rflags = kvm_x86_ops->get_rflags(vcpu);
3225 break;
3226 case 2:
ad312c7c 3227 vcpu->arch.cr2 = val;
8776e519
HB		 3228 break;
3229 case 3:
2d3ad1f4 3230 kvm_set_cr3(vcpu, val);
8776e519
HB		 3231 break;
3232 case 4:
2d3ad1f4 3233 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3234 break;
152ff9be 3235 case 8:
2d3ad1f4 3236 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3237 break;
8776e519 3238 default:
b8688d51 3239 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3240 }
3241}
3242
07716717
DK		 3243static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3244{
ad312c7c
ZX		 3245 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3246 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3247
3248 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3249 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3250 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3251 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3252 if (ej->function == e->function) {
3253 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3254 return j;
3255 }
3256 }
3257 return 0; /* silence gcc, even though control never reaches here */
3258}
3259
3260/* find an entry with matching function, matching index (if needed), and that
3261 * should be read next (if it's stateful) */
3262static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3263 u32 function, u32 index)
3264{
3265 if (e->function != function)
3266 return 0;
3267 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3268 return 0;
3269 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3270 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3271 return 0;
3272 return 1;
3273}
3274
d8017474
AG		 3275struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3276 u32 function, u32 index)
8776e519
HB		 3277{
3278 int i;
d8017474 3279 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3280
ad312c7c 3281 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3282 struct kvm_cpuid_entry2 *e;
3283
ad312c7c 3284 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3285 if (is_matching_cpuid_entry(e, function, index)) {
3286 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3287 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3288 best = e;
3289 break;
3290 }
3291 /*
3292 * Both basic or both extended?
3293 */
3294 if (((e->function ^ function) & 0x80000000) == 0)
3295 if (!best || e->function > best->function)
3296 best = e;
3297 }
d8017474
AG		 3298 return best;
3299}
3300
82725b20
DE		 3301int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3302{
3303 struct kvm_cpuid_entry2 *best;
3304
3305 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3306 if (best)
3307 return best->eax & 0xff;
3308 return 36;
3309}
3310
d8017474
AG		 3311void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3312{
3313 u32 function, index;
3314 struct kvm_cpuid_entry2 *best;
3315
3316 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3317 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3318 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3319 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3320 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3321 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3322 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3323 if (best) {
5fdbf976
MT		 3324 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3325 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3326 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3327 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3328 }
8776e519 3329 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3330 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3331 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3332 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3333 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3334 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3335}
3336EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3337
b6c7a5dc
HB		 3338/*
3339 * Check if userspace requested an interrupt window, and that the
3340 * interrupt window is open.
3341 *
3342 * No need to exit to userspace if we already have an interrupt queued.
3343 */
3344static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3345 struct kvm_run *kvm_run)
3346{
8061823a 3347 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3348 kvm_run->request_interrupt_window &&
5df56646 3349 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3350}
3351
3352static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3353 struct kvm_run *kvm_run)
3354{
3355 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3356 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3357 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3358 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3359 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3360 else
b6c7a5dc 3361 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3362 kvm_arch_interrupt_allowed(vcpu) &&
3363 !kvm_cpu_has_interrupt(vcpu) &&
3364 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3365}
3366
b93463aa
AK		 3367static void vapic_enter(struct kvm_vcpu *vcpu)
3368{
3369 struct kvm_lapic *apic = vcpu->arch.apic;
3370 struct page *page;
3371
3372 if (!apic || !apic->vapic_addr)
3373 return;
3374
3375 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3376
3377 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3378}
3379
3380static void vapic_exit(struct kvm_vcpu *vcpu)
3381{
3382 struct kvm_lapic *apic = vcpu->arch.apic;
3383
3384 if (!apic || !apic->vapic_addr)
3385 return;
3386
f8b78fa3 3387 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3388 kvm_release_page_dirty(apic->vapic_page);
3389 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3390 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3391}
3392
95ba8273
GN		 3393static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3394{
3395 int max_irr, tpr;
3396
3397 if (!kvm_x86_ops->update_cr8_intercept)
3398 return;
3399
8db3baa2
GN		 3400 if (!vcpu->arch.apic->vapic_addr)
3401 max_irr = kvm_lapic_find_highest_irr(vcpu);
3402 else
3403 max_irr = -1;
95ba8273
GN		 3404
3405 if (max_irr != -1)
3406 max_irr >>= 4;
3407
3408 tpr = kvm_lapic_get_cr8(vcpu);
3409
3410 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3411}
3412
6a8b1d13 3413static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3414{
3415 /* try to reinject previous events if any */
3416 if (vcpu->arch.nmi_injected) {
3417 kvm_x86_ops->set_nmi(vcpu);
3418 return;
3419 }
3420
3421 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3422 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3423 return;
3424 }
3425
3426 /* try to inject new event if pending */
3427 if (vcpu->arch.nmi_pending) {
3428 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3429 vcpu->arch.nmi_pending = false;
3430 vcpu->arch.nmi_injected = true;
3431 kvm_x86_ops->set_nmi(vcpu);
3432 }
3433 } else if (kvm_cpu_has_interrupt(vcpu)) {
3434 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3435 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3436 false);
3437 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3438 }
3439 }
3440}
3441
d7690175 3442static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3443{
3444 int r;
6a8b1d13
GN		 3445 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3446 kvm_run->request_interrupt_window;
b6c7a5dc 3447
2e53d63a
MT		 3448 if (vcpu->requests)
3449 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3450 kvm_mmu_unload(vcpu);
3451
b6c7a5dc
HB		 3452 r = kvm_mmu_reload(vcpu);
3453 if (unlikely(r))
3454 goto out;
3455
2f52d58c
AK		 3456 if (vcpu->requests) {
3457 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3458 __kvm_migrate_timers(vcpu);
c8076604
GH		 3459 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3460 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3461 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3462 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3463 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3464 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3465 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3466 &vcpu->requests)) {
3467 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3468 r = 0;
3469 goto out;
3470 }
71c4dfaf
JR		 3471 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3472 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3473 r = 0;
3474 goto out;
3475 }
2f52d58c 3476 }
b93463aa 3477
b6c7a5dc
HB		 3478 preempt_disable();
3479
3480 kvm_x86_ops->prepare_guest_switch(vcpu);
3481 kvm_load_guest_fpu(vcpu);
3482
3483 local_irq_disable();
3484
32f88400
MT		 3485 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3486 smp_mb__after_clear_bit();
3487
d7690175 3488 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3489 local_irq_enable();
3490 preempt_enable();
3491 r = 1;
3492 goto out;
3493 }
3494
ad312c7c 3495 if (vcpu->arch.exception.pending)
298101da 3496 __queue_exception(vcpu);
eb9774f0 3497 else
95ba8273 3498 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3499
6a8b1d13
GN		 3500 /* enable NMI/IRQ window open exits if needed */
3501 if (vcpu->arch.nmi_pending)
3502 kvm_x86_ops->enable_nmi_window(vcpu);
3503 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3504 kvm_x86_ops->enable_irq_window(vcpu);
3505
95ba8273 3506 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3507 update_cr8_intercept(vcpu);
3508 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3509 }
b93463aa 3510
3200f405
MT		 3511 up_read(&vcpu->kvm->slots_lock);
3512
b6c7a5dc
HB		 3513 kvm_guest_enter();
3514
42dbaa5a
JK		 3515 get_debugreg(vcpu->arch.host_dr6, 6);
3516 get_debugreg(vcpu->arch.host_dr7, 7);
3517 if (unlikely(vcpu->arch.switch_db_regs)) {
3518 get_debugreg(vcpu->arch.host_db[0], 0);
3519 get_debugreg(vcpu->arch.host_db[1], 1);
3520 get_debugreg(vcpu->arch.host_db[2], 2);
3521 get_debugreg(vcpu->arch.host_db[3], 3);
3522
3523 set_debugreg(0, 7);
3524 set_debugreg(vcpu->arch.eff_db[0], 0);
3525 set_debugreg(vcpu->arch.eff_db[1], 1);
3526 set_debugreg(vcpu->arch.eff_db[2], 2);
3527 set_debugreg(vcpu->arch.eff_db[3], 3);
3528 }
b6c7a5dc 3529
2714d1d3 3530 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3531 kvm_x86_ops->run(vcpu, kvm_run);
3532
42dbaa5a
JK		 3533 if (unlikely(vcpu->arch.switch_db_regs)) {
3534 set_debugreg(0, 7);
3535 set_debugreg(vcpu->arch.host_db[0], 0);
3536 set_debugreg(vcpu->arch.host_db[1], 1);
3537 set_debugreg(vcpu->arch.host_db[2], 2);
3538 set_debugreg(vcpu->arch.host_db[3], 3);
3539 }
3540 set_debugreg(vcpu->arch.host_dr6, 6);
3541 set_debugreg(vcpu->arch.host_dr7, 7);
3542
32f88400 3543 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3544 local_irq_enable();
3545
3546 ++vcpu->stat.exits;
3547
3548 /*
3549 * We must have an instruction between local_irq_enable() and
3550 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3551 * the interrupt shadow. The stat.exits increment will do nicely.
3552 * But we need to prevent reordering, hence this barrier():
3553 */
3554 barrier();
3555
3556 kvm_guest_exit();
3557
3558 preempt_enable();
3559
3200f405
MT		 3560 down_read(&vcpu->kvm->slots_lock);
3561
b6c7a5dc
HB		 3562 /*
3563 * Profile KVM exit RIPs:
3564 */
3565 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3566 unsigned long rip = kvm_rip_read(vcpu);
3567 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3568 }
3569
298101da 3570
b93463aa
AK		 3571 kvm_lapic_sync_from_vapic(vcpu);
3572
b6c7a5dc 3573 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3574out:
3575 return r;
3576}
b6c7a5dc 3577
09cec754 3578
d7690175
MT		 3579static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3580{
3581 int r;
3582
3583 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3584 pr_debug("vcpu %d received sipi with vector # %x\n",
3585 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3586 kvm_lapic_reset(vcpu);
5f179287 3587 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3588 if (r)
3589 return r;
3590 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3591 }
3592
d7690175
MT		 3593 down_read(&vcpu->kvm->slots_lock);
3594 vapic_enter(vcpu);
3595
3596 r = 1;
3597 while (r > 0) {
af2152f5 3598 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3599 r = vcpu_enter_guest(vcpu, kvm_run);
3600 else {
3601 up_read(&vcpu->kvm->slots_lock);
3602 kvm_vcpu_block(vcpu);
3603 down_read(&vcpu->kvm->slots_lock);
3604 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3605 {
3606 switch(vcpu->arch.mp_state) {
3607 case KVM_MP_STATE_HALTED:
d7690175 3608 vcpu->arch.mp_state =
09cec754
GN		 3609 KVM_MP_STATE_RUNNABLE;
3610 case KVM_MP_STATE_RUNNABLE:
3611 break;
3612 case KVM_MP_STATE_SIPI_RECEIVED:
3613 default:
3614 r = -EINTR;
3615 break;
3616 }
3617 }
d7690175
MT		 3618 }
3619
09cec754
GN		 3620 if (r <= 0)
3621 break;
3622
3623 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3624 if (kvm_cpu_has_pending_timer(vcpu))
3625 kvm_inject_pending_timer_irqs(vcpu);
3626
3627 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3628 r = -EINTR;
3629 kvm_run->exit_reason = KVM_EXIT_INTR;
3630 ++vcpu->stat.request_irq_exits;
3631 }
3632 if (signal_pending(current)) {
3633 r = -EINTR;
3634 kvm_run->exit_reason = KVM_EXIT_INTR;
3635 ++vcpu->stat.signal_exits;
3636 }
3637 if (need_resched()) {
3638 up_read(&vcpu->kvm->slots_lock);
3639 kvm_resched(vcpu);
3640 down_read(&vcpu->kvm->slots_lock);
d7690175 3641 }
b6c7a5dc
HB		 3642 }
3643
d7690175 3644 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3645 post_kvm_run_save(vcpu, kvm_run);
3646
b93463aa
AK		 3647 vapic_exit(vcpu);
3648
b6c7a5dc
HB		 3649 return r;
3650}
3651
3652int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3653{
3654 int r;
3655 sigset_t sigsaved;
3656
3657 vcpu_load(vcpu);
3658
ac9f6dc0
AK		 3659 if (vcpu->sigset_active)
3660 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3661
a4535290 3662 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3663 kvm_vcpu_block(vcpu);
d7690175 3664 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3665 r = -EAGAIN;
3666 goto out;
b6c7a5dc
HB		 3667 }
3668
b6c7a5dc
HB		 3669 /* re-sync apic's tpr */
3670 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3671 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3672
ad312c7c 3673 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3674 r = complete_pio(vcpu);
3675 if (r)
3676 goto out;
3677 }
3678#if CONFIG_HAS_IOMEM
3679 if (vcpu->mmio_needed) {
3680 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3681 vcpu->mmio_read_completed = 1;
3682 vcpu->mmio_needed = 0;
3200f405
MT		 3683
3684 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3685 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3686 vcpu->arch.mmio_fault_cr2, 0,
3687 EMULTYPE_NO_DECODE);
3200f405 3688 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3689 if (r == EMULATE_DO_MMIO) {
3690 /*
3691 * Read-modify-write. Back to userspace.
3692 */
3693 r = 0;
3694 goto out;
3695 }
3696 }
3697#endif
5fdbf976
MT		 3698 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3699 kvm_register_write(vcpu, VCPU_REGS_RAX,
3700 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3701
3702 r = __vcpu_run(vcpu, kvm_run);
3703
3704out:
3705 if (vcpu->sigset_active)
3706 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3707
3708 vcpu_put(vcpu);
3709 return r;
3710}
3711
3712int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3713{
3714 vcpu_load(vcpu);
3715
5fdbf976
MT		 3716 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3717 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3718 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3719 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3720 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3721 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3722 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3723 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3724#ifdef CONFIG_X86_64
5fdbf976
MT		 3725 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3726 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3727 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3728 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3729 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3730 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3731 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3732 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3733#endif
3734
5fdbf976 3735 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3736 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3737
3738 /*
3739 * Don't leak debug flags in case they were set for guest debugging
3740 */
d0bfb940 3741 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3742 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3743
3744 vcpu_put(vcpu);
3745
3746 return 0;
3747}
3748
3749int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3750{
3751 vcpu_load(vcpu);
3752
5fdbf976
MT		 3753 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3754 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3755 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3756 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3757 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3758 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3759 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3760 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3761#ifdef CONFIG_X86_64
5fdbf976
MT		 3762 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3763 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3764 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3765 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3766 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3767 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3768 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3769 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3770
b6c7a5dc
HB		 3771#endif
3772
5fdbf976 3773 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3774 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3775
b6c7a5dc 3776
b4f14abd
JK		 3777 vcpu->arch.exception.pending = false;
3778
b6c7a5dc
HB		 3779 vcpu_put(vcpu);
3780
3781 return 0;
3782}
3783
3e6e0aab
GT		 3784void kvm_get_segment(struct kvm_vcpu *vcpu,
3785 struct kvm_segment *var, int seg)
b6c7a5dc 3786{
14af3f3c 3787 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3788}
3789
3790void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3791{
3792 struct kvm_segment cs;
3793
3e6e0aab 3794 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3795 *db = cs.db;
3796 *l = cs.l;
3797}
3798EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3799
3800int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3801 struct kvm_sregs *sregs)
3802{
3803 struct descriptor_table dt;
b6c7a5dc
HB		 3804
3805 vcpu_load(vcpu);
3806
3e6e0aab
GT		 3807 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3808 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3809 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3810 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3811 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3812 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3813
3e6e0aab
GT		 3814 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3815 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3816
3817 kvm_x86_ops->get_idt(vcpu, &dt);
3818 sregs->idt.limit = dt.limit;
3819 sregs->idt.base = dt.base;
3820 kvm_x86_ops->get_gdt(vcpu, &dt);
3821 sregs->gdt.limit = dt.limit;
3822 sregs->gdt.base = dt.base;
3823
3824 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3825 sregs->cr0 = vcpu->arch.cr0;
3826 sregs->cr2 = vcpu->arch.cr2;
3827 sregs->cr3 = vcpu->arch.cr3;
3828 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3829 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3830 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3831 sregs->apic_base = kvm_get_apic_base(vcpu);
3832
923c61bb 3833 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3834
36752c9b 3835 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3836 set_bit(vcpu->arch.interrupt.nr,
3837 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3838
b6c7a5dc
HB		 3839 vcpu_put(vcpu);
3840
3841 return 0;
3842}
3843
62d9f0db
MT		 3844int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3845 struct kvm_mp_state *mp_state)
3846{
3847 vcpu_load(vcpu);
3848 mp_state->mp_state = vcpu->arch.mp_state;
3849 vcpu_put(vcpu);
3850 return 0;
3851}
3852
3853int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3854 struct kvm_mp_state *mp_state)
3855{
3856 vcpu_load(vcpu);
3857 vcpu->arch.mp_state = mp_state->mp_state;
3858 vcpu_put(vcpu);
3859 return 0;
3860}
3861
3e6e0aab 3862static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3863 struct kvm_segment *var, int seg)
3864{
14af3f3c 3865 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3866}
3867
37817f29
IE		 3868static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3869 struct kvm_segment *kvm_desct)
3870{
3871 kvm_desct->base = seg_desc->base0;
3872 kvm_desct->base |= seg_desc->base1 << 16;
3873 kvm_desct->base |= seg_desc->base2 << 24;
3874 kvm_desct->limit = seg_desc->limit0;
3875 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3876 if (seg_desc->g) {
3877 kvm_desct->limit <<= 12;
3878 kvm_desct->limit |= 0xfff;
3879 }
37817f29
IE		 3880 kvm_desct->selector = selector;
3881 kvm_desct->type = seg_desc->type;
3882 kvm_desct->present = seg_desc->p;
3883 kvm_desct->dpl = seg_desc->dpl;
3884 kvm_desct->db = seg_desc->d;
3885 kvm_desct->s = seg_desc->s;
3886 kvm_desct->l = seg_desc->l;
3887 kvm_desct->g = seg_desc->g;
3888 kvm_desct->avl = seg_desc->avl;
3889 if (!selector)
3890 kvm_desct->unusable = 1;
3891 else
3892 kvm_desct->unusable = 0;
3893 kvm_desct->padding = 0;
3894}
3895
b8222ad2
AS		 3896static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3897 u16 selector,
3898 struct descriptor_table *dtable)
37817f29
IE		 3899{
3900 if (selector & 1 << 2) {
3901 struct kvm_segment kvm_seg;
3902
3e6e0aab 3903 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3904
3905 if (kvm_seg.unusable)
3906 dtable->limit = 0;
3907 else
3908 dtable->limit = kvm_seg.limit;
3909 dtable->base = kvm_seg.base;
3910 }
3911 else
3912 kvm_x86_ops->get_gdt(vcpu, dtable);
3913}
3914
3915/* allowed just for 8 bytes segments */
3916static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3917 struct desc_struct *seg_desc)
3918{
98899aa0 3919 gpa_t gpa;
37817f29
IE		 3920 struct descriptor_table dtable;
3921 u16 index = selector >> 3;
3922
b8222ad2 3923 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3924
3925 if (dtable.limit < index * 8 + 7) {
3926 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3927 return 1;
3928 }
98899aa0
MT		 3929 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3930 gpa += index * 8;
3931 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3932}
3933
3934/* allowed just for 8 bytes segments */
3935static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3936 struct desc_struct *seg_desc)
3937{
98899aa0 3938 gpa_t gpa;
37817f29
IE		 3939 struct descriptor_table dtable;
3940 u16 index = selector >> 3;
3941
b8222ad2 3942 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3943
3944 if (dtable.limit < index * 8 + 7)
3945 return 1;
98899aa0
MT		 3946 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3947 gpa += index * 8;
3948 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3949}
3950
3951static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3952 struct desc_struct *seg_desc)
3953{
3954 u32 base_addr;
3955
3956 base_addr = seg_desc->base0;
3957 base_addr |= (seg_desc->base1 << 16);
3958 base_addr |= (seg_desc->base2 << 24);
3959
98899aa0 3960 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3961}
3962
37817f29
IE		 3963static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3964{
3965 struct kvm_segment kvm_seg;
3966
3e6e0aab 3967 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3968 return kvm_seg.selector;
3969}
3970
3971static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3972 u16 selector,
3973 struct kvm_segment *kvm_seg)
3974{
3975 struct desc_struct seg_desc;
3976
3977 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3978 return 1;
3979 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3980 return 0;
3981}
3982
2259e3a7 3983static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3984{
3985 struct kvm_segment segvar = {
3986 .base = selector << 4,
3987 .limit = 0xffff,
3988 .selector = selector,
3989 .type = 3,
3990 .present = 1,
3991 .dpl = 3,
3992 .db = 0,
3993 .s = 1,
3994 .l = 0,
3995 .g = 0,
3996 .avl = 0,
3997 .unusable = 0,
3998 };
3999 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4000 return 0;
4001}
4002
3e6e0aab
GT		 4003int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4004 int type_bits, int seg)
37817f29
IE		 4005{
4006 struct kvm_segment kvm_seg;
4007
f4bbd9aa
AK		 4008 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4009 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4010 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4011 return 1;
4012 kvm_seg.type |= type_bits;
4013
4014 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4015 seg != VCPU_SREG_LDTR)
4016 if (!kvm_seg.s)
4017 kvm_seg.unusable = 1;
4018
3e6e0aab 4019 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4020 return 0;
4021}
4022
4023static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4024 struct tss_segment_32 *tss)
4025{
4026 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4027 tss->eip = kvm_rip_read(vcpu);
37817f29 4028 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4029 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4030 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4031 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4032 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4033 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4034 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4035 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4036 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4037 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4038 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4039 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4040 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4041 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4042 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4043 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4044}
4045
4046static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4047 struct tss_segment_32 *tss)
4048{
4049 kvm_set_cr3(vcpu, tss->cr3);
4050
5fdbf976 4051 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4052 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4053
5fdbf976
MT		 4054 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4055 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4056 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4057 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4058 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4059 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4060 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4061 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4062
3e6e0aab 4063 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4064 return 1;
4065
3e6e0aab 4066 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4067 return 1;
4068
3e6e0aab 4069 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4070 return 1;
4071
3e6e0aab 4072 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4073 return 1;
4074
3e6e0aab 4075 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4076 return 1;
4077
3e6e0aab 4078 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4079 return 1;
4080
3e6e0aab 4081 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4082 return 1;
4083 return 0;
4084}
4085
4086static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4087 struct tss_segment_16 *tss)
4088{
5fdbf976 4089 tss->ip = kvm_rip_read(vcpu);
37817f29 4090 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4091 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4092 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4093 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4094 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4095 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4096 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4097 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4098 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4099
4100 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4101 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4102 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4103 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4104 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4105 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4106}
4107
4108static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4109 struct tss_segment_16 *tss)
4110{
5fdbf976 4111 kvm_rip_write(vcpu, tss->ip);
37817f29 4112 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4113 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4114 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4115 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4116 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4117 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4118 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4119 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4120 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4121
3e6e0aab 4122 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4123 return 1;
4124
3e6e0aab 4125 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4126 return 1;
4127
3e6e0aab 4128 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4129 return 1;
4130
3e6e0aab 4131 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4132 return 1;
4133
3e6e0aab 4134 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4135 return 1;
4136 return 0;
4137}
4138
8b2cf73c 4139static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4140 u16 old_tss_sel, u32 old_tss_base,
4141 struct desc_struct *nseg_desc)
37817f29
IE		 4142{
4143 struct tss_segment_16 tss_segment_16;
4144 int ret = 0;
4145
34198bf8
MT		 4146 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4147 sizeof tss_segment_16))
37817f29
IE		 4148 goto out;
4149
4150 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4151
34198bf8
MT		 4152 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4153 sizeof tss_segment_16))
37817f29 4154 goto out;
34198bf8
MT		 4155
4156 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4157 &tss_segment_16, sizeof tss_segment_16))
4158 goto out;
4159
b237ac37
GN		 4160 if (old_tss_sel != 0xffff) {
4161 tss_segment_16.prev_task_link = old_tss_sel;
4162
4163 if (kvm_write_guest(vcpu->kvm,
4164 get_tss_base_addr(vcpu, nseg_desc),
4165 &tss_segment_16.prev_task_link,
4166 sizeof tss_segment_16.prev_task_link))
4167 goto out;
4168 }
4169
37817f29
IE		 4170 if (load_state_from_tss16(vcpu, &tss_segment_16))
4171 goto out;
4172
4173 ret = 1;
4174out:
4175 return ret;
4176}
4177
8b2cf73c 4178static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4179 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4180 struct desc_struct *nseg_desc)
4181{
4182 struct tss_segment_32 tss_segment_32;
4183 int ret = 0;
4184
34198bf8
MT		 4185 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4186 sizeof tss_segment_32))
37817f29
IE		 4187 goto out;
4188
4189 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4190
34198bf8
MT		 4191 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4192 sizeof tss_segment_32))
4193 goto out;
4194
4195 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4196 &tss_segment_32, sizeof tss_segment_32))
37817f29 4197 goto out;
34198bf8 4198
b237ac37
GN		 4199 if (old_tss_sel != 0xffff) {
4200 tss_segment_32.prev_task_link = old_tss_sel;
4201
4202 if (kvm_write_guest(vcpu->kvm,
4203 get_tss_base_addr(vcpu, nseg_desc),
4204 &tss_segment_32.prev_task_link,
4205 sizeof tss_segment_32.prev_task_link))
4206 goto out;
4207 }
4208
37817f29
IE		 4209 if (load_state_from_tss32(vcpu, &tss_segment_32))
4210 goto out;
4211
4212 ret = 1;
4213out:
4214 return ret;
4215}
4216
4217int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4218{
4219 struct kvm_segment tr_seg;
4220 struct desc_struct cseg_desc;
4221 struct desc_struct nseg_desc;
4222 int ret = 0;
34198bf8
MT		 4223 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4224 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4225
34198bf8 4226 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4227
34198bf8
MT		 4228 /* FIXME: Handle errors. Failure to read either TSS or their
4229 * descriptors should generate a pagefault.
4230 */
37817f29
IE		 4231 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4232 goto out;
4233
34198bf8 4234 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4235 goto out;
4236
37817f29
IE		 4237 if (reason != TASK_SWITCH_IRET) {
4238 int cpl;
4239
4240 cpl = kvm_x86_ops->get_cpl(vcpu);
4241 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4242 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4243 return 1;
4244 }
4245 }
4246
4247 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4248 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4249 return 1;
4250 }
4251
4252 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4253 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4254 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4255 }
4256
4257 if (reason == TASK_SWITCH_IRET) {
4258 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4259 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4260 }
4261
64a7ec06
GN		 4262 /* set back link to prev task only if NT bit is set in eflags
4263 note that old_tss_sel is not used afetr this point */
4264 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4265 old_tss_sel = 0xffff;
37817f29 4266
b237ac37
GN		 4267 /* set back link to prev task only if NT bit is set in eflags
4268 note that old_tss_sel is not used afetr this point */
4269 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4270 old_tss_sel = 0xffff;
4271
37817f29 4272 if (nseg_desc.type & 8)
b237ac37
GN		 4273 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4274 old_tss_base, &nseg_desc);
37817f29 4275 else
b237ac37
GN		 4276 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4277 old_tss_base, &nseg_desc);
37817f29
IE		 4278
4279 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4280 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4281 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4282 }
4283
4284 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4285 nseg_desc.type |= (1 << 1);
37817f29
IE		 4286 save_guest_segment_descriptor(vcpu, tss_selector,
4287 &nseg_desc);
4288 }
4289
4290 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4291 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4292 tr_seg.type = 11;
3e6e0aab 4293 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4294out:
37817f29
IE		 4295 return ret;
4296}
4297EXPORT_SYMBOL_GPL(kvm_task_switch);
4298
b6c7a5dc
HB		 4299int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4300 struct kvm_sregs *sregs)
4301{
4302 int mmu_reset_needed = 0;
923c61bb 4303 int pending_vec, max_bits;
b6c7a5dc
HB		 4304 struct descriptor_table dt;
4305
4306 vcpu_load(vcpu);
4307
4308 dt.limit = sregs->idt.limit;
4309 dt.base = sregs->idt.base;
4310 kvm_x86_ops->set_idt(vcpu, &dt);
4311 dt.limit = sregs->gdt.limit;
4312 dt.base = sregs->gdt.base;
4313 kvm_x86_ops->set_gdt(vcpu, &dt);
4314
ad312c7c
ZX		 4315 vcpu->arch.cr2 = sregs->cr2;
4316 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
59839dff
MT		 4317
4318 down_read(&vcpu->kvm->slots_lock);
4319 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4320 vcpu->arch.cr3 = sregs->cr3;
4321 else
4322 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4323 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc 4324
2d3ad1f4 4325 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4326
ad312c7c 4327 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4328 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4329 kvm_set_apic_base(vcpu, sregs->apic_base);
4330
4331 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4332
ad312c7c 4333 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4334 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4335 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4336
ad312c7c 4337 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4338 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4339 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4340 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4341
4342 if (mmu_reset_needed)
4343 kvm_mmu_reset_context(vcpu);
4344
923c61bb
GN		 4345 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4346 pending_vec = find_first_bit(
4347 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4348 if (pending_vec < max_bits) {
66fd3f7f 4349 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4350 pr_debug("Set back pending irq %d\n", pending_vec);
4351 if (irqchip_in_kernel(vcpu->kvm))
4352 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4353 }
4354
3e6e0aab
GT		 4355 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4356 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4357 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4358 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4359 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4360 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4361
3e6e0aab
GT		 4362 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4363 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4364
9c3e4aab 4365 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4366 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4367 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4368 !(vcpu->arch.cr0 & X86_CR0_PE))
4369 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4370
b6c7a5dc
HB		 4371 vcpu_put(vcpu);
4372
4373 return 0;
4374}
4375
d0bfb940
JK		 4376int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4377 struct kvm_guest_debug *dbg)
b6c7a5dc 4378{
ae675ef0 4379 int i, r;
b6c7a5dc
HB		 4380
4381 vcpu_load(vcpu);
4382
ae675ef0
JK		 4383 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4384 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4385 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4386 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4387 vcpu->arch.switch_db_regs =
4388 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4389 } else {
4390 for (i = 0; i < KVM_NR_DB_REGS; i++)
4391 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4392 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4393 }
4394
b6c7a5dc
HB		 4395 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4396
d0bfb940
JK		 4397 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4398 kvm_queue_exception(vcpu, DB_VECTOR);
4399 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4400 kvm_queue_exception(vcpu, BP_VECTOR);
4401
b6c7a5dc
HB		 4402 vcpu_put(vcpu);
4403
4404 return r;
4405}
4406
d0752060
HB		 4407/*
4408 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4409 * we have asm/x86/processor.h
4410 */
4411struct fxsave {
4412 u16 cwd;
4413 u16 swd;
4414 u16 twd;
4415 u16 fop;
4416 u64 rip;
4417 u64 rdp;
4418 u32 mxcsr;
4419 u32 mxcsr_mask;
4420 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4421#ifdef CONFIG_X86_64
4422 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4423#else
4424 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4425#endif
4426};
4427
8b006791
ZX		 4428/*
4429 * Translate a guest virtual address to a guest physical address.
4430 */
4431int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4432 struct kvm_translation *tr)
4433{
4434 unsigned long vaddr = tr->linear_address;
4435 gpa_t gpa;
4436
4437 vcpu_load(vcpu);
72dc67a6 4438 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4439 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4440 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4441 tr->physical_address = gpa;
4442 tr->valid = gpa != UNMAPPED_GVA;
4443 tr->writeable = 1;
4444 tr->usermode = 0;
8b006791
ZX		 4445 vcpu_put(vcpu);
4446
4447 return 0;
4448}
4449
d0752060
HB		 4450int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4451{
ad312c7c 4452 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4453
4454 vcpu_load(vcpu);
4455
4456 memcpy(fpu->fpr, fxsave->st_space, 128);
4457 fpu->fcw = fxsave->cwd;
4458 fpu->fsw = fxsave->swd;
4459 fpu->ftwx = fxsave->twd;
4460 fpu->last_opcode = fxsave->fop;
4461 fpu->last_ip = fxsave->rip;
4462 fpu->last_dp = fxsave->rdp;
4463 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4464
4465 vcpu_put(vcpu);
4466
4467 return 0;
4468}
4469
4470int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4471{
ad312c7c 4472 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4473
4474 vcpu_load(vcpu);
4475
4476 memcpy(fxsave->st_space, fpu->fpr, 128);
4477 fxsave->cwd = fpu->fcw;
4478 fxsave->swd = fpu->fsw;
4479 fxsave->twd = fpu->ftwx;
4480 fxsave->fop = fpu->last_opcode;
4481 fxsave->rip = fpu->last_ip;
4482 fxsave->rdp = fpu->last_dp;
4483 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4484
4485 vcpu_put(vcpu);
4486
4487 return 0;
4488}
4489
4490void fx_init(struct kvm_vcpu *vcpu)
4491{
4492 unsigned after_mxcsr_mask;
4493
bc1a34f1
AA		 4494 /*
4495 * Touch the fpu the first time in non atomic context as if
4496 * this is the first fpu instruction the exception handler
4497 * will fire before the instruction returns and it'll have to
4498 * allocate ram with GFP_KERNEL.
4499 */
4500 if (!used_math())
d6e88aec 4501 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4502
d0752060
HB		 4503 /* Initialize guest FPU by resetting ours and saving into guest's */
4504 preempt_disable();
d6e88aec
AK		 4505 kvm_fx_save(&vcpu->arch.host_fx_image);
4506 kvm_fx_finit();
4507 kvm_fx_save(&vcpu->arch.guest_fx_image);
4508 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4509 preempt_enable();
4510
ad312c7c 4511 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4512 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4513 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4514 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4515 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4516}
4517EXPORT_SYMBOL_GPL(fx_init);
4518
4519void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4520{
4521 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4522 return;
4523
4524 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4525 kvm_fx_save(&vcpu->arch.host_fx_image);
4526 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4527}
4528EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4529
4530void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4531{
4532 if (!vcpu->guest_fpu_loaded)
4533 return;
4534
4535 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4536 kvm_fx_save(&vcpu->arch.guest_fx_image);
4537 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4538 ++vcpu->stat.fpu_reload;
d0752060
HB		 4539}
4540EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4541
4542void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4543{
7f1ea208
JR		 4544 if (vcpu->arch.time_page) {
4545 kvm_release_page_dirty(vcpu->arch.time_page);
4546 vcpu->arch.time_page = NULL;
4547 }
4548
e9b11c17
ZX		 4549 kvm_x86_ops->vcpu_free(vcpu);
4550}
4551
4552struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4553 unsigned int id)
4554{
26e5215f
AK		 4555 return kvm_x86_ops->vcpu_create(kvm, id);
4556}
e9b11c17 4557
26e5215f
AK		 4558int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4559{
4560 int r;
e9b11c17
ZX		 4561
4562 /* We do fxsave: this must be aligned. */
ad312c7c 4563 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4564
0bed3b56 4565 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4566 vcpu_load(vcpu);
4567 r = kvm_arch_vcpu_reset(vcpu);
4568 if (r == 0)
4569 r = kvm_mmu_setup(vcpu);
4570 vcpu_put(vcpu);
4571 if (r < 0)
4572 goto free_vcpu;
4573
26e5215f 4574 return 0;
e9b11c17
ZX		 4575free_vcpu:
4576 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4577 return r;
e9b11c17
ZX		 4578}
4579
d40ccc62 4580void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4581{
4582 vcpu_load(vcpu);
4583 kvm_mmu_unload(vcpu);
4584 vcpu_put(vcpu);
4585
4586 kvm_x86_ops->vcpu_free(vcpu);
4587}
4588
4589int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4590{
448fa4a9
JK		 4591 vcpu->arch.nmi_pending = false;
4592 vcpu->arch.nmi_injected = false;
4593
42dbaa5a
JK		 4594 vcpu->arch.switch_db_regs = 0;
4595 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4596 vcpu->arch.dr6 = DR6_FIXED_1;
4597 vcpu->arch.dr7 = DR7_FIXED_1;
4598
e9b11c17
ZX		 4599 return kvm_x86_ops->vcpu_reset(vcpu);
4600}
4601
4602void kvm_arch_hardware_enable(void *garbage)
4603{
4604 kvm_x86_ops->hardware_enable(garbage);
4605}
4606
4607void kvm_arch_hardware_disable(void *garbage)
4608{
4609 kvm_x86_ops->hardware_disable(garbage);
4610}
4611
4612int kvm_arch_hardware_setup(void)
4613{
4614 return kvm_x86_ops->hardware_setup();
4615}
4616
4617void kvm_arch_hardware_unsetup(void)
4618{
4619 kvm_x86_ops->hardware_unsetup();
4620}
4621
4622void kvm_arch_check_processor_compat(void *rtn)
4623{
4624 kvm_x86_ops->check_processor_compatibility(rtn);
4625}
4626
4627int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4628{
4629 struct page *page;
4630 struct kvm *kvm;
4631 int r;
4632
4633 BUG_ON(vcpu->kvm == NULL);
4634 kvm = vcpu->kvm;
4635
ad312c7c 4636 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4637 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4638 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4639 else
a4535290 4640 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4641
4642 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4643 if (!page) {
4644 r = -ENOMEM;
4645 goto fail;
4646 }
ad312c7c 4647 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4648
4649 r = kvm_mmu_create(vcpu);
4650 if (r < 0)
4651 goto fail_free_pio_data;
4652
4653 if (irqchip_in_kernel(kvm)) {
4654 r = kvm_create_lapic(vcpu);
4655 if (r < 0)
4656 goto fail_mmu_destroy;
4657 }
4658
890ca9ae
HY		 4659 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4660 GFP_KERNEL);
4661 if (!vcpu->arch.mce_banks) {
4662 r = -ENOMEM;
4663 goto fail_mmu_destroy;
4664 }
4665 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4666
e9b11c17
ZX		 4667 return 0;
4668
4669fail_mmu_destroy:
4670 kvm_mmu_destroy(vcpu);
4671fail_free_pio_data:
ad312c7c 4672 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4673fail:
4674 return r;
4675}
4676
4677void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4678{
4679 kvm_free_lapic(vcpu);
3200f405 4680 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4681 kvm_mmu_destroy(vcpu);
3200f405 4682 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4683 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4684}
d19a9cd2
ZX		 4685
4686struct kvm *kvm_arch_create_vm(void)
4687{
4688 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4689
4690 if (!kvm)
4691 return ERR_PTR(-ENOMEM);
4692
f05e70ac 4693 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4694 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4695
5550af4d
SY		 4696 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4697 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4698
53f658b3
MT		 4699 rdtscll(kvm->arch.vm_init_tsc);
4700
d19a9cd2
ZX		 4701 return kvm;
4702}
4703
4704static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4705{
4706 vcpu_load(vcpu);
4707 kvm_mmu_unload(vcpu);
4708 vcpu_put(vcpu);
4709}
4710
4711static void kvm_free_vcpus(struct kvm *kvm)
4712{
4713 unsigned int i;
988a2cae 4714 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4715
4716 /*
4717 * Unpin any mmu pages first.
4718 */
988a2cae
GN		 4719 kvm_for_each_vcpu(i, vcpu, kvm)
4720 kvm_unload_vcpu_mmu(vcpu);
4721 kvm_for_each_vcpu(i, vcpu, kvm)
4722 kvm_arch_vcpu_free(vcpu);
4723
4724 mutex_lock(&kvm->lock);
4725 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4726 kvm->vcpus[i] = NULL;
d19a9cd2 4727
988a2cae
GN		 4728 atomic_set(&kvm->online_vcpus, 0);
4729 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4730}
4731
ad8ba2cd
SY		 4732void kvm_arch_sync_events(struct kvm *kvm)
4733{
ba4cef31 4734 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4735}
4736
d19a9cd2
ZX		 4737void kvm_arch_destroy_vm(struct kvm *kvm)
4738{
6eb55818 4739 kvm_iommu_unmap_guest(kvm);
7837699f 4740 kvm_free_pit(kvm);
d7deeeb0
ZX		 4741 kfree(kvm->arch.vpic);
4742 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4743 kvm_free_vcpus(kvm);
4744 kvm_free_physmem(kvm);
3d45830c
AK		 4745 if (kvm->arch.apic_access_page)
4746 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4747 if (kvm->arch.ept_identity_pagetable)
4748 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4749 kfree(kvm);
4750}
0de10343
ZX		 4751
4752int kvm_arch_set_memory_region(struct kvm *kvm,
4753 struct kvm_userspace_memory_region *mem,
4754 struct kvm_memory_slot old,
4755 int user_alloc)
4756{
4757 int npages = mem->memory_size >> PAGE_SHIFT;
4758 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4759
4760 /*To keep backward compatibility with older userspace,
4761 *x86 needs to hanlde !user_alloc case.
4762 */
4763 if (!user_alloc) {
4764 if (npages && !old.rmap) {
604b38ac
AA		 4765 unsigned long userspace_addr;
4766
72dc67a6 4767 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4768 userspace_addr = do_mmap(NULL, 0,
4769 npages * PAGE_SIZE,
4770 PROT_READ | PROT_WRITE,
acee3c04 4771 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4772 0);
72dc67a6 4773 up_write(&current->mm->mmap_sem);
0de10343 4774
604b38ac
AA		 4775 if (IS_ERR((void *)userspace_addr))
4776 return PTR_ERR((void *)userspace_addr);
4777
4778 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4779 spin_lock(&kvm->mmu_lock);
4780 memslot->userspace_addr = userspace_addr;
4781 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4782 } else {
4783 if (!old.user_alloc && old.rmap) {
4784 int ret;
4785
72dc67a6 4786 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4787 ret = do_munmap(current->mm, old.userspace_addr,
4788 old.npages * PAGE_SIZE);
72dc67a6 4789 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4790 if (ret < 0)
4791 printk(KERN_WARNING
4792 "kvm_vm_ioctl_set_memory_region: "
4793 "failed to munmap memory\n");
4794 }
4795 }
4796 }
4797
7c8a83b7 4798 spin_lock(&kvm->mmu_lock);
f05e70ac 4799 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4800 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4801 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4802 }
4803
4804 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4805 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4806 kvm_flush_remote_tlbs(kvm);
4807
4808 return 0;
4809}
1d737c8a 4810
34d4cb8f
MT		 4811void kvm_arch_flush_shadow(struct kvm *kvm)
4812{
4813 kvm_mmu_zap_all(kvm);
8986ecc0 4814 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4815}
4816
1d737c8a
ZX		 4817int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4818{
a4535290 4819 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4820 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4821 || vcpu->arch.nmi_pending;
1d737c8a 4822}
5736199a 4823
5736199a
ZX		 4824void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4825{
32f88400
MT		 4826 int me;
4827 int cpu = vcpu->cpu;
5736199a
ZX		 4828
4829 if (waitqueue_active(&vcpu->wq)) {
4830 wake_up_interruptible(&vcpu->wq);
4831 ++vcpu->stat.halt_wakeup;
4832 }
32f88400
MT		 4833
4834 me = get_cpu();
4835 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4836 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4837 smp_send_reschedule(cpu);
e9571ed5 4838 put_cpu();
5736199a 4839}
78646121
GN		 4840
4841int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4842{
4843 return kvm_x86_ops->interrupt_allowed(vcpu);
4844}
Linux kernel - Deliverables
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