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KVM: x86: avoid uninitialized variable warning
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
aec51dc4 54#include <trace/events/kvm.h>
2ed152af 55
229456fc
MT		 56#define CREATE_TRACE_POINTS
57#include "trace.h"
043405e1 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 225 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 226 if (slot >= shared_msrs_global.nr)
227 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 228}
229EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
230
231static void kvm_shared_msr_cpu_online(void)
232{
233 unsigned i;
18863bdd
AK		 234
235 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 236 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 237}
238
8b3c3104 239int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 240{
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 243 int err;
18863bdd 244
2bf78fa7 245 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 246 return 0;
2bf78fa7 247 smsr->values[slot].curr = value;
8b3c3104
AH		 248 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
249 if (err)
250 return 1;
251
18863bdd
AK		 252 if (!smsr->registered) {
253 smsr->urn.on_user_return = kvm_on_user_return;
254 user_return_notifier_register(&smsr->urn);
255 smsr->registered = true;
256 }
8b3c3104 257 return 0;
18863bdd
AK		 258}
259EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
260
13a34e06 261static void drop_user_return_notifiers(void)
3548bab5 262{
013f6a5d
MT		 263 unsigned int cpu = smp_processor_id();
264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 265
266 if (smsr->registered)
267 kvm_on_user_return(&smsr->urn);
268}
269
6866b83e
CO		 270u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
271{
8a5a87d9 272 return vcpu->arch.apic_base;
6866b83e
CO		 273}
274EXPORT_SYMBOL_GPL(kvm_get_apic_base);
275
58cb628d
JK		 276int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
277{
278 u64 old_state = vcpu->arch.apic_base &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 new_state = msr_info->data &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
283 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
284
285 if (!msr_info->host_initiated &&
286 ((msr_info->data & reserved_bits) != 0 ||
287 new_state == X2APIC_ENABLE ||
288 (new_state == MSR_IA32_APICBASE_ENABLE &&
289 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
290 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
291 old_state == 0)))
292 return 1;
293
294 kvm_lapic_set_base(vcpu, msr_info->data);
295 return 0;
6866b83e
CO		 296}
297EXPORT_SYMBOL_GPL(kvm_set_apic_base);
298
2605fc21 299asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 300{
301 /* Fault while not rebooting. We want the trace. */
302 BUG();
303}
304EXPORT_SYMBOL_GPL(kvm_spurious_fault);
305
3fd28fce
ED		 306#define EXCPT_BENIGN 0
307#define EXCPT_CONTRIBUTORY 1
308#define EXCPT_PF 2
309
310static int exception_class(int vector)
311{
312 switch (vector) {
313 case PF_VECTOR:
314 return EXCPT_PF;
315 case DE_VECTOR:
316 case TS_VECTOR:
317 case NP_VECTOR:
318 case SS_VECTOR:
319 case GP_VECTOR:
320 return EXCPT_CONTRIBUTORY;
321 default:
322 break;
323 }
324 return EXCPT_BENIGN;
325}
326
d6e8c854
NA		 327#define EXCPT_FAULT 0
328#define EXCPT_TRAP 1
329#define EXCPT_ABORT 2
330#define EXCPT_INTERRUPT 3
331
332static int exception_type(int vector)
333{
334 unsigned int mask;
335
336 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
337 return EXCPT_INTERRUPT;
338
339 mask = 1 << vector;
340
341 /* #DB is trap, as instruction watchpoints are handled elsewhere */
342 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
343 return EXCPT_TRAP;
344
345 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
346 return EXCPT_ABORT;
347
348 /* Reserved exceptions will result in fault */
349 return EXCPT_FAULT;
350}
351
3fd28fce 352static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 353 unsigned nr, bool has_error, u32 error_code,
354 bool reinject)
3fd28fce
ED		 355{
356 u32 prev_nr;
357 int class1, class2;
358
3842d135
AK		 359 kvm_make_request(KVM_REQ_EVENT, vcpu);
360
3fd28fce
ED		 361 if (!vcpu->arch.exception.pending) {
362 queue:
3ffb2468
NA		 363 if (has_error && !is_protmode(vcpu))
364 has_error = false;
3fd28fce
ED		 365 vcpu->arch.exception.pending = true;
366 vcpu->arch.exception.has_error_code = has_error;
367 vcpu->arch.exception.nr = nr;
368 vcpu->arch.exception.error_code = error_code;
3f0fd292 369 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 370 return;
371 }
372
373 /* to check exception */
374 prev_nr = vcpu->arch.exception.nr;
375 if (prev_nr == DF_VECTOR) {
376 /* triple fault -> shutdown */
a8eeb04a 377 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 378 return;
379 }
380 class1 = exception_class(prev_nr);
381 class2 = exception_class(nr);
382 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
383 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
384 /* generate double fault per SDM Table 5-5 */
385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = true;
387 vcpu->arch.exception.nr = DF_VECTOR;
388 vcpu->arch.exception.error_code = 0;
389 } else
390 /* replace previous exception with a new one in a hope
391 that instruction re-execution will regenerate lost
392 exception */
393 goto queue;
394}
395
298101da
AK		 396void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
397{
ce7ddec4 398 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 399}
400EXPORT_SYMBOL_GPL(kvm_queue_exception);
401
ce7ddec4
JR		 402void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
403{
404 kvm_multiple_exception(vcpu, nr, false, 0, true);
405}
406EXPORT_SYMBOL_GPL(kvm_requeue_exception);
407
db8fcefa 408void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 409{
db8fcefa
AP		 410 if (err)
411 kvm_inject_gp(vcpu, 0);
412 else
413 kvm_x86_ops->skip_emulated_instruction(vcpu);
414}
415EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 416
6389ee94 417void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 418{
419 ++vcpu->stat.pf_guest;
6389ee94
AK		 420 vcpu->arch.cr2 = fault->address;
421 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 422}
27d6c865 423EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 424
ef54bcfe 425static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 426{
6389ee94
AK		 427 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
428 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 429 else
6389ee94 430 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 431
432 return fault->nested_page_fault;
d4f8cf66
JR		 433}
434
3419ffc8
SY		 435void kvm_inject_nmi(struct kvm_vcpu *vcpu)
436{
7460fb4a
AK		 437 atomic_inc(&vcpu->arch.nmi_queued);
438 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 439}
440EXPORT_SYMBOL_GPL(kvm_inject_nmi);
441
298101da
AK		 442void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
443{
ce7ddec4 444 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 445}
446EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
447
ce7ddec4
JR		 448void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
449{
450 kvm_multiple_exception(vcpu, nr, true, error_code, true);
451}
452EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
453
0a79b009
AK		 454/*
455 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
456 * a #GP and return false.
457 */
458bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 459{
0a79b009
AK		 460 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
461 return true;
462 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
463 return false;
298101da 464}
0a79b009 465EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 466
16f8a6f9
NA		 467bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
468{
469 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
470 return true;
471
472 kvm_queue_exception(vcpu, UD_VECTOR);
473 return false;
474}
475EXPORT_SYMBOL_GPL(kvm_require_dr);
476
ec92fe44
JR		 477/*
478 * This function will be used to read from the physical memory of the currently
54bf36aa 479 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 480 * can read from guest physical or from the guest's guest physical memory.
481 */
482int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
483 gfn_t ngfn, void *data, int offset, int len,
484 u32 access)
485{
54987b7a 486 struct x86_exception exception;
ec92fe44
JR		 487 gfn_t real_gfn;
488 gpa_t ngpa;
489
490 ngpa = gfn_to_gpa(ngfn);
54987b7a 491 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 492 if (real_gfn == UNMAPPED_GVA)
493 return -EFAULT;
494
495 real_gfn = gpa_to_gfn(real_gfn);
496
54bf36aa 497 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 498}
499EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
500
69b0049a 501static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 502 void *data, int offset, int len, u32 access)
503{
504 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
505 data, offset, len, access);
506}
507
a03490ed
CO		 508/*
509 * Load the pae pdptrs. Return true is they are all valid.
510 */
ff03a073 511int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 512{
513 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
514 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
515 int i;
516 int ret;
ff03a073 517 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 518
ff03a073
JR		 519 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
520 offset * sizeof(u64), sizeof(pdpte),
521 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 522 if (ret < 0) {
523 ret = 0;
524 goto out;
525 }
526 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 527 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 528 (pdpte[i] &
529 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 530 ret = 0;
531 goto out;
532 }
533 }
534 ret = 1;
535
ff03a073 536 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_avail);
539 __set_bit(VCPU_EXREG_PDPTR,
540 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 541out:
a03490ed
CO		 542
543 return ret;
544}
cc4b6871 545EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 546
d835dfec
AK		 547static bool pdptrs_changed(struct kvm_vcpu *vcpu)
548{
ff03a073 549 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 550 bool changed = true;
3d06b8bf
JR		 551 int offset;
552 gfn_t gfn;
d835dfec
AK		 553 int r;
554
555 if (is_long_mode(vcpu) || !is_pae(vcpu))
556 return false;
557
6de4f3ad
AK		 558 if (!test_bit(VCPU_EXREG_PDPTR,
559 (unsigned long *)&vcpu->arch.regs_avail))
560 return true;
561
9f8fe504
AK		 562 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
563 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 564 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
565 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 566 if (r < 0)
567 goto out;
ff03a073 568 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 569out:
d835dfec
AK		 570
571 return changed;
572}
573
49a9b07e 574int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 575{
aad82703 576 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 577 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 578
f9a48e6a
AK		 579 cr0 |= X86_CR0_ET;
580
ab344828 581#ifdef CONFIG_X86_64
0f12244f
GN		 582 if (cr0 & 0xffffffff00000000UL)
583 return 1;
ab344828
GN		 584#endif
585
586 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 587
0f12244f
GN		 588 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
589 return 1;
a03490ed 590
0f12244f
GN		 591 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
592 return 1;
a03490ed
CO		 593
594 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
595#ifdef CONFIG_X86_64
f6801dff 596 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 597 int cs_db, cs_l;
598
0f12244f
GN		 599 if (!is_pae(vcpu))
600 return 1;
a03490ed 601 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 602 if (cs_l)
603 return 1;
a03490ed
CO		 604 } else
605#endif
ff03a073 606 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 607 kvm_read_cr3(vcpu)))
0f12244f 608 return 1;
a03490ed
CO		 609 }
610
ad756a16
MJ		 611 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
612 return 1;
613
a03490ed 614 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 615
d170c419 616 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 617 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 618 kvm_async_pf_hash_reset(vcpu);
619 }
e5f3f027 620
aad82703
SY		 621 if ((cr0 ^ old_cr0) & update_bits)
622 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 623
624 if ((cr0 ^ old_cr0) & X86_CR0_CD)
625 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 630
2d3ad1f4 631void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 632{
49a9b07e 633 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 634}
2d3ad1f4 635EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 636
42bdf991
MT		 637static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
638{
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
640 !vcpu->guest_xcr0_loaded) {
641 /* kvm_set_xcr() also depends on this */
642 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
643 vcpu->guest_xcr0_loaded = 1;
644 }
645}
646
647static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
648{
649 if (vcpu->guest_xcr0_loaded) {
650 if (vcpu->arch.xcr0 != host_xcr0)
651 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
652 vcpu->guest_xcr0_loaded = 0;
653 }
654}
655
69b0049a 656static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 657{
56c103ec
LJ		 658 u64 xcr0 = xcr;
659 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 660 u64 valid_bits;
2acf923e
DC		 661
662 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
663 if (index != XCR_XFEATURE_ENABLED_MASK)
664 return 1;
2acf923e
DC		 665 if (!(xcr0 & XSTATE_FP))
666 return 1;
667 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
668 return 1;
46c34cb0
PB		 669
670 /*
671 * Do not allow the guest to set bits that we do not support
672 * saving. However, xcr0 bit 0 is always set, even if the
673 * emulated CPU does not support XSAVE (see fx_init).
674 */
675 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
676 if (xcr0 & ~valid_bits)
2acf923e 677 return 1;
46c34cb0 678
390bd528
LJ		 679 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
680 return 1;
681
612263b3
CP		 682 if (xcr0 & XSTATE_AVX512) {
683 if (!(xcr0 & XSTATE_YMM))
684 return 1;
685 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
686 return 1;
687 }
42bdf991 688 kvm_put_guest_xcr0(vcpu);
2acf923e 689 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 690
691 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
692 kvm_update_cpuid(vcpu);
2acf923e
DC		 693 return 0;
694}
695
696int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
697{
764bcbc5
Z		 698 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
699 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 700 kvm_inject_gp(vcpu, 0);
701 return 1;
702 }
703 return 0;
704}
705EXPORT_SYMBOL_GPL(kvm_set_xcr);
706
a83b29c6 707int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 708{
fc78f519 709 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 710 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
711 X86_CR4_SMEP | X86_CR4_SMAP;
712
0f12244f
GN		 713 if (cr4 & CR4_RESERVED_BITS)
714 return 1;
a03490ed 715
2acf923e
DC		 716 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
717 return 1;
718
c68b734f
YW		 719 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
720 return 1;
721
97ec8c06
FW		 722 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
723 return 1;
724
afcbf13f 725 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 726 return 1;
727
a03490ed 728 if (is_long_mode(vcpu)) {
0f12244f
GN		 729 if (!(cr4 & X86_CR4_PAE))
730 return 1;
a2edf57f
AK		 731 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
732 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 733 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
734 kvm_read_cr3(vcpu)))
0f12244f
GN		 735 return 1;
736
ad756a16
MJ		 737 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
738 if (!guest_cpuid_has_pcid(vcpu))
739 return 1;
740
741 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
742 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
743 return 1;
744 }
745
5e1746d6 746 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 747 return 1;
a03490ed 748
ad756a16
MJ		 749 if (((cr4 ^ old_cr4) & pdptr_bits) ||
750 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 751 kvm_mmu_reset_context(vcpu);
0f12244f 752
2acf923e 753 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 754 kvm_update_cpuid(vcpu);
2acf923e 755
0f12244f
GN		 756 return 0;
757}
2d3ad1f4 758EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 759
2390218b 760int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 761{
ac146235 762#ifdef CONFIG_X86_64
9d88fca7 763 cr3 &= ~CR3_PCID_INVD;
ac146235 764#endif
9d88fca7 765
9f8fe504 766 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 767 kvm_mmu_sync_roots(vcpu);
77c3913b 768 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 769 return 0;
d835dfec
AK		 770 }
771
a03490ed 772 if (is_long_mode(vcpu)) {
d9f89b88
JK		 773 if (cr3 & CR3_L_MODE_RESERVED_BITS)
774 return 1;
775 } else if (is_pae(vcpu) && is_paging(vcpu) &&
776 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 777 return 1;
a03490ed 778
0f12244f 779 vcpu->arch.cr3 = cr3;
aff48baa 780 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 781 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 782 return 0;
783}
2d3ad1f4 784EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 785
eea1cff9 786int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 787{
0f12244f
GN		 788 if (cr8 & CR8_RESERVED_BITS)
789 return 1;
a03490ed
CO		 790 if (irqchip_in_kernel(vcpu->kvm))
791 kvm_lapic_set_tpr(vcpu, cr8);
792 else
ad312c7c 793 vcpu->arch.cr8 = cr8;
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 797
2d3ad1f4 798unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 799{
800 if (irqchip_in_kernel(vcpu->kvm))
801 return kvm_lapic_get_cr8(vcpu);
802 else
ad312c7c 803 return vcpu->arch.cr8;
a03490ed 804}
2d3ad1f4 805EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 806
ae561ede
NA		 807static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
808{
809 int i;
810
811 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
812 for (i = 0; i < KVM_NR_DB_REGS; i++)
813 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
814 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
815 }
816}
817
73aaf249
JK		 818static void kvm_update_dr6(struct kvm_vcpu *vcpu)
819{
820 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
821 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
822}
823
c8639010
JK		 824static void kvm_update_dr7(struct kvm_vcpu *vcpu)
825{
826 unsigned long dr7;
827
828 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
829 dr7 = vcpu->arch.guest_debug_dr7;
830 else
831 dr7 = vcpu->arch.dr7;
832 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 833 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
834 if (dr7 & DR7_BP_EN_MASK)
835 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 836}
837
6f43ed01
NA		 838static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
839{
840 u64 fixed = DR6_FIXED_1;
841
842 if (!guest_cpuid_has_rtm(vcpu))
843 fixed |= DR6_RTM;
844 return fixed;
845}
846
338dbc97 847static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 848{
849 switch (dr) {
850 case 0 ... 3:
851 vcpu->arch.db[dr] = val;
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
853 vcpu->arch.eff_db[dr] = val;
854 break;
855 case 4:
020df079
GN		 856 /* fall through */
857 case 6:
338dbc97
GN		 858 if (val & 0xffffffff00000000ULL)
859 return -1; /* #GP */
6f43ed01 860 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 861 kvm_update_dr6(vcpu);
020df079
GN		 862 break;
863 case 5:
020df079
GN		 864 /* fall through */
865 default: /* 7 */
338dbc97
GN		 866 if (val & 0xffffffff00000000ULL)
867 return -1; /* #GP */
020df079 868 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 869 kvm_update_dr7(vcpu);
020df079
GN		 870 break;
871 }
872
873 return 0;
874}
338dbc97
GN		 875
876int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
877{
16f8a6f9 878 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 879 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 880 return 1;
881 }
882 return 0;
338dbc97 883}
020df079
GN		 884EXPORT_SYMBOL_GPL(kvm_set_dr);
885
16f8a6f9 886int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 887{
888 switch (dr) {
889 case 0 ... 3:
890 *val = vcpu->arch.db[dr];
891 break;
892 case 4:
020df079
GN		 893 /* fall through */
894 case 6:
73aaf249
JK		 895 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
896 *val = vcpu->arch.dr6;
897 else
898 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 899 break;
900 case 5:
020df079
GN		 901 /* fall through */
902 default: /* 7 */
903 *val = vcpu->arch.dr7;
904 break;
905 }
338dbc97
GN		 906 return 0;
907}
020df079
GN		 908EXPORT_SYMBOL_GPL(kvm_get_dr);
909
022cd0e8
AK		 910bool kvm_rdpmc(struct kvm_vcpu *vcpu)
911{
912 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
913 u64 data;
914 int err;
915
c6702c9d 916 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 917 if (err)
918 return err;
919 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
920 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
921 return err;
922}
923EXPORT_SYMBOL_GPL(kvm_rdpmc);
924
043405e1
CO		 925/*
926 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
927 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
928 *
929 * This list is modified at module load time to reflect the
e3267cbb 930 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 931 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
932 * may depend on host virtualization features rather than host cpu features.
043405e1 933 */
e3267cbb 934
043405e1
CO		 935static u32 msrs_to_save[] = {
936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 937 MSR_STAR,
043405e1
CO		 938#ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940#endif
b3897a49 941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 943};
944
945static unsigned num_msrs_to_save;
946
62ef68bb
PB		 947static u32 emulated_msrs[] = {
948 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
949 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
950 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
951 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 952 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
953 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
62ef68bb
PB		 954 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
955 MSR_KVM_PV_EOI_EN,
956
ba904635 957 MSR_IA32_TSC_ADJUST,
a3e06bbe 958 MSR_IA32_TSCDEADLINE,
043405e1 959 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 960 MSR_IA32_MCG_STATUS,
961 MSR_IA32_MCG_CTL,
64d60670 962 MSR_IA32_SMBASE,
043405e1
CO		 963};
964
62ef68bb
PB		 965static unsigned num_emulated_msrs;
966
384bb783 967bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 968{
b69e8cae 969 if (efer & efer_reserved_bits)
384bb783 970 return false;
15c4a640 971
1b2fd70c
AG		 972 if (efer & EFER_FFXSR) {
973 struct kvm_cpuid_entry2 *feat;
974
975 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 976 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 977 return false;
1b2fd70c
AG		 978 }
979
d8017474
AG		 980 if (efer & EFER_SVME) {
981 struct kvm_cpuid_entry2 *feat;
982
983 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 984 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 985 return false;
d8017474
AG		 986 }
987
384bb783
JK		 988 return true;
989}
990EXPORT_SYMBOL_GPL(kvm_valid_efer);
991
992static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
993{
994 u64 old_efer = vcpu->arch.efer;
995
996 if (!kvm_valid_efer(vcpu, efer))
997 return 1;
998
999 if (is_paging(vcpu)
1000 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1001 return 1;
1002
15c4a640 1003 efer &= ~EFER_LMA;
f6801dff 1004 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1005
a3d204e2
SY		 1006 kvm_x86_ops->set_efer(vcpu, efer);
1007
aad82703
SY		 1008 /* Update reserved bits */
1009 if ((efer ^ old_efer) & EFER_NX)
1010 kvm_mmu_reset_context(vcpu);
1011
b69e8cae 1012 return 0;
15c4a640
CO		 1013}
1014
f2b4b7dd
JR		 1015void kvm_enable_efer_bits(u64 mask)
1016{
1017 efer_reserved_bits &= ~mask;
1018}
1019EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1020
15c4a640
CO		 1021/*
1022 * Writes msr value into into the appropriate "register".
1023 * Returns 0 on success, non-0 otherwise.
1024 * Assumes vcpu_load() was already called.
1025 */
8fe8ab46 1026int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1027{
854e8bb1
NA		 1028 switch (msr->index) {
1029 case MSR_FS_BASE:
1030 case MSR_GS_BASE:
1031 case MSR_KERNEL_GS_BASE:
1032 case MSR_CSTAR:
1033 case MSR_LSTAR:
1034 if (is_noncanonical_address(msr->data))
1035 return 1;
1036 break;
1037 case MSR_IA32_SYSENTER_EIP:
1038 case MSR_IA32_SYSENTER_ESP:
1039 /*
1040 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1041 * non-canonical address is written on Intel but not on
1042 * AMD (which ignores the top 32-bits, because it does
1043 * not implement 64-bit SYSENTER).
1044 *
1045 * 64-bit code should hence be able to write a non-canonical
1046 * value on AMD. Making the address canonical ensures that
1047 * vmentry does not fail on Intel after writing a non-canonical
1048 * value, and that something deterministic happens if the guest
1049 * invokes 64-bit SYSENTER.
1050 */
1051 msr->data = get_canonical(msr->data);
1052 }
8fe8ab46 1053 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1054}
854e8bb1 1055EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1056
313a3dc7
CO		 1057/*
1058 * Adapt set_msr() to msr_io()'s calling convention
1059 */
609e36d3
PB		 1060static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1061{
1062 struct msr_data msr;
1063 int r;
1064
1065 msr.index = index;
1066 msr.host_initiated = true;
1067 r = kvm_get_msr(vcpu, &msr);
1068 if (r)
1069 return r;
1070
1071 *data = msr.data;
1072 return 0;
1073}
1074
313a3dc7
CO		 1075static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1076{
8fe8ab46
WA		 1077 struct msr_data msr;
1078
1079 msr.data = *data;
1080 msr.index = index;
1081 msr.host_initiated = true;
1082 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1083}
1084
16e8d74d
MT		 1085#ifdef CONFIG_X86_64
1086struct pvclock_gtod_data {
1087 seqcount_t seq;
1088
1089 struct { /* extract of a clocksource struct */
1090 int vclock_mode;
1091 cycle_t cycle_last;
1092 cycle_t mask;
1093 u32 mult;
1094 u32 shift;
1095 } clock;
1096
cbcf2dd3
TG		 1097 u64 boot_ns;
1098 u64 nsec_base;
16e8d74d
MT		 1099};
1100
1101static struct pvclock_gtod_data pvclock_gtod_data;
1102
1103static void update_pvclock_gtod(struct timekeeper *tk)
1104{
1105 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1106 u64 boot_ns;
1107
876e7881 1108 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1109
1110 write_seqcount_begin(&vdata->seq);
1111
1112 /* copy pvclock gtod data */
876e7881
PZ		 1113 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1114 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1115 vdata->clock.mask = tk->tkr_mono.mask;
1116 vdata->clock.mult = tk->tkr_mono.mult;
1117 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1118
cbcf2dd3 1119 vdata->boot_ns = boot_ns;
876e7881 1120 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1121
1122 write_seqcount_end(&vdata->seq);
1123}
1124#endif
1125
bab5bb39
NK		 1126void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1127{
1128 /*
1129 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1130 * vcpu_enter_guest. This function is only called from
1131 * the physical CPU that is running vcpu.
1132 */
1133 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1134}
16e8d74d 1135
18068523
GOC		 1136static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1137{
9ed3c444
AK		 1138 int version;
1139 int r;
50d0a0f9 1140 struct pvclock_wall_clock wc;
923de3cf 1141 struct timespec boot;
18068523
GOC		 1142
1143 if (!wall_clock)
1144 return;
1145
9ed3c444
AK		 1146 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1147 if (r)
1148 return;
1149
1150 if (version & 1)
1151 ++version; /* first time write, random junk */
1152
1153 ++version;
18068523 1154
18068523
GOC		 1155 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1156
50d0a0f9
GH		 1157 /*
1158 * The guest calculates current wall clock time by adding
34c238a1 1159 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1160 * wall clock specified here. guest system time equals host
1161 * system time for us, thus we must fill in host boot time here.
1162 */
923de3cf 1163 getboottime(&boot);
50d0a0f9 1164
4b648665
BR		 1165 if (kvm->arch.kvmclock_offset) {
1166 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1167 boot = timespec_sub(boot, ts);
1168 }
50d0a0f9
GH		 1169 wc.sec = boot.tv_sec;
1170 wc.nsec = boot.tv_nsec;
1171 wc.version = version;
18068523
GOC		 1172
1173 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1174
1175 version++;
1176 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1177}
1178
50d0a0f9
GH		 1179static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1180{
1181 uint32_t quotient, remainder;
1182
1183 /* Don't try to replace with do_div(), this one calculates
1184 * "(dividend << 32) / divisor" */
1185 __asm__ ( "divl %4"
1186 : "=a" (quotient), "=d" (remainder)
1187 : "0" (0), "1" (dividend), "r" (divisor) );
1188 return quotient;
1189}
1190
5f4e3f88
ZA		 1191static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1192 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1193{
5f4e3f88 1194 uint64_t scaled64;
50d0a0f9
GH		 1195 int32_t shift = 0;
1196 uint64_t tps64;
1197 uint32_t tps32;
1198
5f4e3f88
ZA		 1199 tps64 = base_khz * 1000LL;
1200 scaled64 = scaled_khz * 1000LL;
50933623 1201 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1202 tps64 >>= 1;
1203 shift--;
1204 }
1205
1206 tps32 = (uint32_t)tps64;
50933623
JK		 1207 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1208 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1209 scaled64 >>= 1;
1210 else
1211 tps32 <<= 1;
50d0a0f9
GH		 1212 shift++;
1213 }
1214
5f4e3f88
ZA		 1215 *pshift = shift;
1216 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1217
5f4e3f88
ZA		 1218 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1219 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1220}
1221
d828199e 1222#ifdef CONFIG_X86_64
16e8d74d 1223static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1224#endif
16e8d74d 1225
c8076604 1226static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1227static unsigned long max_tsc_khz;
c8076604 1228
cc578287 1229static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1230{
cc578287
ZA		 1231 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1232 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1233}
1234
cc578287 1235static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1236{
cc578287
ZA		 1237 u64 v = (u64)khz * (1000000 + ppm);
1238 do_div(v, 1000000);
1239 return v;
1e993611
JR		 1240}
1241
cc578287 1242static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1243{
cc578287
ZA		 1244 u32 thresh_lo, thresh_hi;
1245 int use_scaling = 0;
217fc9cf 1246
03ba32ca
MT		 1247 /* tsc_khz can be zero if TSC calibration fails */
1248 if (this_tsc_khz == 0)
1249 return;
1250
c285545f
ZA		 1251 /* Compute a scale to convert nanoseconds in TSC cycles */
1252 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1253 &vcpu->arch.virtual_tsc_shift,
1254 &vcpu->arch.virtual_tsc_mult);
1255 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1256
1257 /*
1258 * Compute the variation in TSC rate which is acceptable
1259 * within the range of tolerance and decide if the
1260 * rate being applied is within that bounds of the hardware
1261 * rate. If so, no scaling or compensation need be done.
1262 */
1263 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1264 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1265 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1266 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1267 use_scaling = 1;
1268 }
1269 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1270}
1271
1272static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1273{
e26101b1 1274 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1275 vcpu->arch.virtual_tsc_mult,
1276 vcpu->arch.virtual_tsc_shift);
e26101b1 1277 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1278 return tsc;
1279}
1280
69b0049a 1281static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1282{
1283#ifdef CONFIG_X86_64
1284 bool vcpus_matched;
b48aa97e
MT		 1285 struct kvm_arch *ka = &vcpu->kvm->arch;
1286 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1287
1288 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1289 atomic_read(&vcpu->kvm->online_vcpus));
1290
7f187922
MT		 1291 /*
1292 * Once the masterclock is enabled, always perform request in
1293 * order to update it.
1294 *
1295 * In order to enable masterclock, the host clocksource must be TSC
1296 * and the vcpus need to have matched TSCs. When that happens,
1297 * perform request to enable masterclock.
1298 */
1299 if (ka->use_master_clock ||
1300 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1301 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1302
1303 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1304 atomic_read(&vcpu->kvm->online_vcpus),
1305 ka->use_master_clock, gtod->clock.vclock_mode);
1306#endif
1307}
1308
ba904635
WA		 1309static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1310{
1311 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1312 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1313}
1314
8fe8ab46 1315void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1316{
1317 struct kvm *kvm = vcpu->kvm;
f38e098f 1318 u64 offset, ns, elapsed;
99e3e30a 1319 unsigned long flags;
02626b6a 1320 s64 usdiff;
b48aa97e 1321 bool matched;
0d3da0d2 1322 bool already_matched;
8fe8ab46 1323 u64 data = msr->data;
99e3e30a 1324
038f8c11 1325 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1326 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1327 ns = get_kernel_ns();
f38e098f 1328 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1329
03ba32ca 1330 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1331 int faulted = 0;
1332
03ba32ca
MT		 1333 /* n.b - signed multiplication and division required */
1334 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1335#ifdef CONFIG_X86_64
03ba32ca 1336 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1337#else
03ba32ca 1338 /* do_div() only does unsigned */
8915aa27
MT		 1339 asm("1: idivl %[divisor]\n"
1340 "2: xor %%edx, %%edx\n"
1341 " movl $0, %[faulted]\n"
1342 "3:\n"
1343 ".section .fixup,\"ax\"\n"
1344 "4: movl $1, %[faulted]\n"
1345 " jmp 3b\n"
1346 ".previous\n"
1347
1348 _ASM_EXTABLE(1b, 4b)
1349
1350 : "=A"(usdiff), [faulted] "=r" (faulted)
1351 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1352
5d3cb0f6 1353#endif
03ba32ca
MT		 1354 do_div(elapsed, 1000);
1355 usdiff -= elapsed;
1356 if (usdiff < 0)
1357 usdiff = -usdiff;
8915aa27
MT		 1358
1359 /* idivl overflow => difference is larger than USEC_PER_SEC */
1360 if (faulted)
1361 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1362 } else
1363 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1364
1365 /*
5d3cb0f6
ZA		 1366 * Special case: TSC write with a small delta (1 second) of virtual
1367 * cycle time against real time is interpreted as an attempt to
1368 * synchronize the CPU.
1369 *
1370 * For a reliable TSC, we can match TSC offsets, and for an unstable
1371 * TSC, we add elapsed time in this computation. We could let the
1372 * compensation code attempt to catch up if we fall behind, but
1373 * it's better to try to match offsets from the beginning.
1374 */
02626b6a 1375 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1376 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1377 if (!check_tsc_unstable()) {
e26101b1 1378 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1379 pr_debug("kvm: matched tsc offset for %llu\n", data);
1380 } else {
857e4099 1381 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1382 data += delta;
1383 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1384 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1385 }
b48aa97e 1386 matched = true;
0d3da0d2 1387 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1388 } else {
1389 /*
1390 * We split periods of matched TSC writes into generations.
1391 * For each generation, we track the original measured
1392 * nanosecond time, offset, and write, so if TSCs are in
1393 * sync, we can match exact offset, and if not, we can match
4a969980 1394 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1395 *
1396 * These values are tracked in kvm->arch.cur_xxx variables.
1397 */
1398 kvm->arch.cur_tsc_generation++;
1399 kvm->arch.cur_tsc_nsec = ns;
1400 kvm->arch.cur_tsc_write = data;
1401 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1402 matched = false;
0d3da0d2 1403 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1404 kvm->arch.cur_tsc_generation, data);
f38e098f 1405 }
e26101b1
ZA		 1406
1407 /*
1408 * We also track th most recent recorded KHZ, write and time to
1409 * allow the matching interval to be extended at each write.
1410 */
f38e098f
ZA		 1411 kvm->arch.last_tsc_nsec = ns;
1412 kvm->arch.last_tsc_write = data;
5d3cb0f6 1413 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1414
b183aa58 1415 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1416
1417 /* Keep track of which generation this VCPU has synchronized to */
1418 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1419 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1420 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1421
ba904635
WA		 1422 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1423 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1424 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1425 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1426
1427 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1428 if (!matched) {
b48aa97e 1429 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1430 } else if (!already_matched) {
1431 kvm->arch.nr_vcpus_matched_tsc++;
1432 }
b48aa97e
MT		 1433
1434 kvm_track_tsc_matching(vcpu);
1435 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1436}
e26101b1 1437
99e3e30a
ZA		 1438EXPORT_SYMBOL_GPL(kvm_write_tsc);
1439
d828199e
MT		 1440#ifdef CONFIG_X86_64
1441
1442static cycle_t read_tsc(void)
1443{
1444 cycle_t ret;
1445 u64 last;
1446
1447 /*
1448 * Empirically, a fence (of type that depends on the CPU)
1449 * before rdtsc is enough to ensure that rdtsc is ordered
1450 * with respect to loads. The various CPU manuals are unclear
1451 * as to whether rdtsc can be reordered with later loads,
1452 * but no one has ever seen it happen.
1453 */
1454 rdtsc_barrier();
1455 ret = (cycle_t)vget_cycles();
1456
1457 last = pvclock_gtod_data.clock.cycle_last;
1458
1459 if (likely(ret >= last))
1460 return ret;
1461
1462 /*
1463 * GCC likes to generate cmov here, but this branch is extremely
1464 * predictable (it's just a funciton of time and the likely is
1465 * very likely) and there's a data dependence, so force GCC
1466 * to generate a branch instead. I don't barrier() because
1467 * we don't actually need a barrier, and if this function
1468 * ever gets inlined it will generate worse code.
1469 */
1470 asm volatile ("");
1471 return last;
1472}
1473
1474static inline u64 vgettsc(cycle_t *cycle_now)
1475{
1476 long v;
1477 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1478
1479 *cycle_now = read_tsc();
1480
1481 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1482 return v * gtod->clock.mult;
1483}
1484
cbcf2dd3 1485static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1486{
cbcf2dd3 1487 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1488 unsigned long seq;
d828199e 1489 int mode;
cbcf2dd3 1490 u64 ns;
d828199e 1491
d828199e
MT		 1492 do {
1493 seq = read_seqcount_begin(&gtod->seq);
1494 mode = gtod->clock.vclock_mode;
cbcf2dd3 1495 ns = gtod->nsec_base;
d828199e
MT		 1496 ns += vgettsc(cycle_now);
1497 ns >>= gtod->clock.shift;
cbcf2dd3 1498 ns += gtod->boot_ns;
d828199e 1499 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1500 *t = ns;
d828199e
MT		 1501
1502 return mode;
1503}
1504
1505/* returns true if host is using tsc clocksource */
1506static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1507{
d828199e
MT		 1508 /* checked again under seqlock below */
1509 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1510 return false;
1511
cbcf2dd3 1512 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1513}
1514#endif
1515
1516/*
1517 *
b48aa97e
MT		 1518 * Assuming a stable TSC across physical CPUS, and a stable TSC
1519 * across virtual CPUs, the following condition is possible.
1520 * Each numbered line represents an event visible to both
d828199e
MT		 1521 * CPUs at the next numbered event.
1522 *
1523 * "timespecX" represents host monotonic time. "tscX" represents
1524 * RDTSC value.
1525 *
1526 * VCPU0 on CPU0 | VCPU1 on CPU1
1527 *
1528 * 1. read timespec0,tsc0
1529 * 2. | timespec1 = timespec0 + N
1530 * | tsc1 = tsc0 + M
1531 * 3. transition to guest | transition to guest
1532 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1533 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1534 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1535 *
1536 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1537 *
1538 * - ret0 < ret1
1539 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1540 * ...
1541 * - 0 < N - M => M < N
1542 *
1543 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1544 * always the case (the difference between two distinct xtime instances
1545 * might be smaller then the difference between corresponding TSC reads,
1546 * when updating guest vcpus pvclock areas).
1547 *
1548 * To avoid that problem, do not allow visibility of distinct
1549 * system_timestamp/tsc_timestamp values simultaneously: use a master
1550 * copy of host monotonic time values. Update that master copy
1551 * in lockstep.
1552 *
b48aa97e 1553 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1554 *
1555 */
1556
1557static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1558{
1559#ifdef CONFIG_X86_64
1560 struct kvm_arch *ka = &kvm->arch;
1561 int vclock_mode;
b48aa97e
MT		 1562 bool host_tsc_clocksource, vcpus_matched;
1563
1564 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1565 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1566
1567 /*
1568 * If the host uses TSC clock, then passthrough TSC as stable
1569 * to the guest.
1570 */
b48aa97e 1571 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1572 &ka->master_kernel_ns,
1573 &ka->master_cycle_now);
1574
16a96021 1575 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1576 && !backwards_tsc_observed
1577 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1578
d828199e
MT		 1579 if (ka->use_master_clock)
1580 atomic_set(&kvm_guest_has_master_clock, 1);
1581
1582 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1583 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1584 vcpus_matched);
d828199e
MT		 1585#endif
1586}
1587
2e762ff7
MT		 1588static void kvm_gen_update_masterclock(struct kvm *kvm)
1589{
1590#ifdef CONFIG_X86_64
1591 int i;
1592 struct kvm_vcpu *vcpu;
1593 struct kvm_arch *ka = &kvm->arch;
1594
1595 spin_lock(&ka->pvclock_gtod_sync_lock);
1596 kvm_make_mclock_inprogress_request(kvm);
1597 /* no guest entries from this point */
1598 pvclock_update_vm_gtod_copy(kvm);
1599
1600 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1601 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1602
1603 /* guest entries allowed */
1604 kvm_for_each_vcpu(i, vcpu, kvm)
1605 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1606
1607 spin_unlock(&ka->pvclock_gtod_sync_lock);
1608#endif
1609}
1610
34c238a1 1611static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1612{
d828199e 1613 unsigned long flags, this_tsc_khz;
18068523 1614 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1615 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1616 s64 kernel_ns;
d828199e 1617 u64 tsc_timestamp, host_tsc;
0b79459b 1618 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1619 u8 pvclock_flags;
d828199e
MT		 1620 bool use_master_clock;
1621
1622 kernel_ns = 0;
1623 host_tsc = 0;
18068523 1624
d828199e
MT		 1625 /*
1626 * If the host uses TSC clock, then passthrough TSC as stable
1627 * to the guest.
1628 */
1629 spin_lock(&ka->pvclock_gtod_sync_lock);
1630 use_master_clock = ka->use_master_clock;
1631 if (use_master_clock) {
1632 host_tsc = ka->master_cycle_now;
1633 kernel_ns = ka->master_kernel_ns;
1634 }
1635 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1636
1637 /* Keep irq disabled to prevent changes to the clock */
1638 local_irq_save(flags);
89cbc767 1639 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1640 if (unlikely(this_tsc_khz == 0)) {
1641 local_irq_restore(flags);
1642 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1643 return 1;
1644 }
d828199e
MT		 1645 if (!use_master_clock) {
1646 host_tsc = native_read_tsc();
1647 kernel_ns = get_kernel_ns();
1648 }
1649
1650 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1651
c285545f
ZA		 1652 /*
1653 * We may have to catch up the TSC to match elapsed wall clock
1654 * time for two reasons, even if kvmclock is used.
1655 * 1) CPU could have been running below the maximum TSC rate
1656 * 2) Broken TSC compensation resets the base at each VCPU
1657 * entry to avoid unknown leaps of TSC even when running
1658 * again on the same CPU. This may cause apparent elapsed
1659 * time to disappear, and the guest to stand still or run
1660 * very slowly.
1661 */
1662 if (vcpu->tsc_catchup) {
1663 u64 tsc = compute_guest_tsc(v, kernel_ns);
1664 if (tsc > tsc_timestamp) {
f1e2b260 1665 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1666 tsc_timestamp = tsc;
1667 }
50d0a0f9
GH		 1668 }
1669
18068523
GOC		 1670 local_irq_restore(flags);
1671
0b79459b 1672 if (!vcpu->pv_time_enabled)
c285545f 1673 return 0;
18068523 1674
e48672fa 1675 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1676 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1677 &vcpu->hv_clock.tsc_shift,
1678 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1679 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1680 }
1681
1682 /* With all the info we got, fill in the values */
1d5f066e 1683 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1684 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1685 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1686
09a0c3f1
OH		 1687 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1688 &guest_hv_clock, sizeof(guest_hv_clock))))
1689 return 0;
1690
5dca0d91
RK		 1691 /* This VCPU is paused, but it's legal for a guest to read another
1692 * VCPU's kvmclock, so we really have to follow the specification where
1693 * it says that version is odd if data is being modified, and even after
1694 * it is consistent.
1695 *
1696 * Version field updates must be kept separate. This is because
1697 * kvm_write_guest_cached might use a "rep movs" instruction, and
1698 * writes within a string instruction are weakly ordered. So there
1699 * are three writes overall.
1700 *
1701 * As a small optimization, only write the version field in the first
1702 * and third write. The vcpu->pv_time cache is still valid, because the
1703 * version field is the first in the struct.
18068523 1704 */
5dca0d91
RK		 1705 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1706
1707 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1708 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1709 &vcpu->hv_clock,
1710 sizeof(vcpu->hv_clock.version));
1711
1712 smp_wmb();
78c0337a
MT		 1713
1714 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1715 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1716
1717 if (vcpu->pvclock_set_guest_stopped_request) {
1718 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1719 vcpu->pvclock_set_guest_stopped_request = false;
1720 }
1721
b7e60c5a
MT		 1722 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1723
d828199e
MT		 1724 /* If the host uses TSC clocksource, then it is stable */
1725 if (use_master_clock)
1726 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1727
78c0337a
MT		 1728 vcpu->hv_clock.flags = pvclock_flags;
1729
ce1a5e60
DM		 1730 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1731
0b79459b
AH		 1732 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1733 &vcpu->hv_clock,
1734 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1735
1736 smp_wmb();
1737
1738 vcpu->hv_clock.version++;
1739 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1740 &vcpu->hv_clock,
1741 sizeof(vcpu->hv_clock.version));
8cfdc000 1742 return 0;
c8076604
GH		 1743}
1744
0061d53d
MT		 1745/*
1746 * kvmclock updates which are isolated to a given vcpu, such as
1747 * vcpu->cpu migration, should not allow system_timestamp from
1748 * the rest of the vcpus to remain static. Otherwise ntp frequency
1749 * correction applies to one vcpu's system_timestamp but not
1750 * the others.
1751 *
1752 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1753 * We need to rate-limit these requests though, as they can
1754 * considerably slow guests that have a large number of vcpus.
1755 * The time for a remote vcpu to update its kvmclock is bound
1756 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1757 */
1758
7e44e449
AJ		 1759#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1760
1761static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1762{
1763 int i;
7e44e449
AJ		 1764 struct delayed_work *dwork = to_delayed_work(work);
1765 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1766 kvmclock_update_work);
1767 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1768 struct kvm_vcpu *vcpu;
1769
1770 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1771 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1772 kvm_vcpu_kick(vcpu);
1773 }
1774}
1775
7e44e449
AJ		 1776static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1777{
1778 struct kvm *kvm = v->kvm;
1779
105b21bb 1780 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1781 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1782 KVMCLOCK_UPDATE_DELAY);
1783}
1784
332967a3
AJ		 1785#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1786
1787static void kvmclock_sync_fn(struct work_struct *work)
1788{
1789 struct delayed_work *dwork = to_delayed_work(work);
1790 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1791 kvmclock_sync_work);
1792 struct kvm *kvm = container_of(ka, struct kvm, arch);
1793
630994b3
MT		 1794 if (!kvmclock_periodic_sync)
1795 return;
1796
332967a3
AJ		 1797 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1798 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1799 KVMCLOCK_SYNC_PERIOD);
1800}
1801
890ca9ae 1802static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1803{
890ca9ae
HY		 1804 u64 mcg_cap = vcpu->arch.mcg_cap;
1805 unsigned bank_num = mcg_cap & 0xff;
1806
15c4a640 1807 switch (msr) {
15c4a640 1808 case MSR_IA32_MCG_STATUS:
890ca9ae 1809 vcpu->arch.mcg_status = data;
15c4a640 1810 break;
c7ac679c 1811 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1812 if (!(mcg_cap & MCG_CTL_P))
1813 return 1;
1814 if (data != 0 && data != ~(u64)0)
1815 return -1;
1816 vcpu->arch.mcg_ctl = data;
1817 break;
1818 default:
1819 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1820 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1821 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1822 /* only 0 or all 1s can be written to IA32_MCi_CTL
1823 * some Linux kernels though clear bit 10 in bank 4 to
1824 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1825 * this to avoid an uncatched #GP in the guest
1826 */
890ca9ae 1827 if ((offset & 0x3) == 0 &&
114be429 1828 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1829 return -1;
1830 vcpu->arch.mce_banks[offset] = data;
1831 break;
1832 }
1833 return 1;
1834 }
1835 return 0;
1836}
1837
ffde22ac
ES		 1838static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1839{
1840 struct kvm *kvm = vcpu->kvm;
1841 int lm = is_long_mode(vcpu);
1842 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1843 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1844 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1845 : kvm->arch.xen_hvm_config.blob_size_32;
1846 u32 page_num = data & ~PAGE_MASK;
1847 u64 page_addr = data & PAGE_MASK;
1848 u8 *page;
1849 int r;
1850
1851 r = -E2BIG;
1852 if (page_num >= blob_size)
1853 goto out;
1854 r = -ENOMEM;
ff5c2c03
SL		 1855 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1856 if (IS_ERR(page)) {
1857 r = PTR_ERR(page);
ffde22ac 1858 goto out;
ff5c2c03 1859 }
54bf36aa 1860 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1861 goto out_free;
1862 r = 0;
1863out_free:
1864 kfree(page);
1865out:
1866 return r;
1867}
1868
344d9588
GN		 1869static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1870{
1871 gpa_t gpa = data & ~0x3f;
1872
4a969980 1873 /* Bits 2:5 are reserved, Should be zero */
6adba527 1874 if (data & 0x3c)
344d9588
GN		 1875 return 1;
1876
1877 vcpu->arch.apf.msr_val = data;
1878
1879 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1880 kvm_clear_async_pf_completion_queue(vcpu);
1881 kvm_async_pf_hash_reset(vcpu);
1882 return 0;
1883 }
1884
8f964525
AH		 1885 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1886 sizeof(u32)))
344d9588
GN		 1887 return 1;
1888
6adba527 1889 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1890 kvm_async_pf_wakeup_all(vcpu);
1891 return 0;
1892}
1893
12f9a48f
GC		 1894static void kvmclock_reset(struct kvm_vcpu *vcpu)
1895{
0b79459b 1896 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1897}
1898
c9aaa895
GC		 1899static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1900{
1901 u64 delta;
1902
1903 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1904 return;
1905
1906 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1907 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1908 vcpu->arch.st.accum_steal = delta;
1909}
1910
1911static void record_steal_time(struct kvm_vcpu *vcpu)
1912{
1913 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1914 return;
1915
1916 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1917 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1918 return;
1919
1920 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1921 vcpu->arch.st.steal.version += 2;
1922 vcpu->arch.st.accum_steal = 0;
1923
1924 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1925 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1926}
1927
8fe8ab46 1928int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1929{
5753785f 1930 bool pr = false;
8fe8ab46
WA		 1931 u32 msr = msr_info->index;
1932 u64 data = msr_info->data;
5753785f 1933
15c4a640 1934 switch (msr) {
2e32b719
BP		 1935 case MSR_AMD64_NB_CFG:
1936 case MSR_IA32_UCODE_REV:
1937 case MSR_IA32_UCODE_WRITE:
1938 case MSR_VM_HSAVE_PA:
1939 case MSR_AMD64_PATCH_LOADER:
1940 case MSR_AMD64_BU_CFG2:
1941 break;
1942
15c4a640 1943 case MSR_EFER:
b69e8cae 1944 return set_efer(vcpu, data);
8f1589d9
AP		 1945 case MSR_K7_HWCR:
1946 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1947 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1948 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1949 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1950 if (data != 0) {
a737f256
CD		 1951 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1952 data);
8f1589d9
AP		 1953 return 1;
1954 }
15c4a640 1955 break;
f7c6d140
AP		 1956 case MSR_FAM10H_MMIO_CONF_BASE:
1957 if (data != 0) {
a737f256
CD		 1958 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1959 "0x%llx\n", data);
f7c6d140
AP		 1960 return 1;
1961 }
15c4a640 1962 break;
b5e2fec0
AG		 1963 case MSR_IA32_DEBUGCTLMSR:
1964 if (!data) {
1965 /* We support the non-activated case already */
1966 break;
1967 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1968 /* Values other than LBR and BTF are vendor-specific,
1969 thus reserved and should throw a #GP */
1970 return 1;
1971 }
a737f256
CD		 1972 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1973 __func__, data);
b5e2fec0 1974 break;
9ba075a6 1975 case 0x200 ... 0x2ff:
ff53604b 1976 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1977 case MSR_IA32_APICBASE:
58cb628d 1978 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1979 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1980 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1981 case MSR_IA32_TSCDEADLINE:
1982 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1983 break;
ba904635
WA		 1984 case MSR_IA32_TSC_ADJUST:
1985 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1986 if (!msr_info->host_initiated) {
d913b904 1987 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 1988 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1989 }
1990 vcpu->arch.ia32_tsc_adjust_msr = data;
1991 }
1992 break;
15c4a640 1993 case MSR_IA32_MISC_ENABLE:
ad312c7c 1994 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1995 break;
64d60670
PB		 1996 case MSR_IA32_SMBASE:
1997 if (!msr_info->host_initiated)
1998 return 1;
1999 vcpu->arch.smbase = data;
2000 break;
11c6bffa 2001 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2002 case MSR_KVM_WALL_CLOCK:
2003 vcpu->kvm->arch.wall_clock = data;
2004 kvm_write_wall_clock(vcpu->kvm, data);
2005 break;
11c6bffa 2006 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2007 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2008 u64 gpa_offset;
54750f2c
MT		 2009 struct kvm_arch *ka = &vcpu->kvm->arch;
2010
12f9a48f 2011 kvmclock_reset(vcpu);
18068523 2012
54750f2c
MT		 2013 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2014 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2015
2016 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2017 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2018 &vcpu->requests);
2019
2020 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2021
2022 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2023 }
2024
18068523 2025 vcpu->arch.time = data;
0061d53d 2026 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2027
2028 /* we verify if the enable bit is set... */
2029 if (!(data & 1))
2030 break;
2031
0b79459b 2032 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2033
0b79459b 2034 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2035 &vcpu->arch.pv_time, data & ~1ULL,
2036 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2037 vcpu->arch.pv_time_enabled = false;
2038 else
2039 vcpu->arch.pv_time_enabled = true;
32cad84f 2040
18068523
GOC		 2041 break;
2042 }
344d9588
GN		 2043 case MSR_KVM_ASYNC_PF_EN:
2044 if (kvm_pv_enable_async_pf(vcpu, data))
2045 return 1;
2046 break;
c9aaa895
GC		 2047 case MSR_KVM_STEAL_TIME:
2048
2049 if (unlikely(!sched_info_on()))
2050 return 1;
2051
2052 if (data & KVM_STEAL_RESERVED_MASK)
2053 return 1;
2054
2055 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2056 data & KVM_STEAL_VALID_BITS,
2057 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2058 return 1;
2059
2060 vcpu->arch.st.msr_val = data;
2061
2062 if (!(data & KVM_MSR_ENABLED))
2063 break;
2064
2065 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2066
2067 preempt_disable();
2068 accumulate_steal_time(vcpu);
2069 preempt_enable();
2070
2071 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2072
2073 break;
ae7a2a3f
MT		 2074 case MSR_KVM_PV_EOI_EN:
2075 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2076 return 1;
2077 break;
c9aaa895 2078
890ca9ae
HY		 2079 case MSR_IA32_MCG_CTL:
2080 case MSR_IA32_MCG_STATUS:
81760dcc 2081 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2082 return set_msr_mce(vcpu, msr, data);
71db6023 2083
6912ac32
WH		 2084 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2085 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2086 pr = true; /* fall through */
2087 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2088 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2089 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2090 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2091
2092 if (pr || data != 0)
a737f256
CD		 2093 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2094 "0x%x data 0x%llx\n", msr, data);
5753785f 2095 break;
84e0cefa
JS		 2096 case MSR_K7_CLK_CTL:
2097 /*
2098 * Ignore all writes to this no longer documented MSR.
2099 * Writes are only relevant for old K7 processors,
2100 * all pre-dating SVM, but a recommended workaround from
4a969980 2101 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2102 * affected processor models on the command line, hence
2103 * the need to ignore the workaround.
2104 */
2105 break;
55cd8e5a 2106 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2107 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2108 case HV_X64_MSR_CRASH_CTL:
2109 return kvm_hv_set_msr_common(vcpu, msr, data,
2110 msr_info->host_initiated);
91c9c3ed 2111 case MSR_IA32_BBL_CR_CTL3:
2112 /* Drop writes to this legacy MSR -- see rdmsr
2113 * counterpart for further detail.
2114 */
a737f256 2115 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2116 break;
2b036c6b
BO		 2117 case MSR_AMD64_OSVW_ID_LENGTH:
2118 if (!guest_cpuid_has_osvw(vcpu))
2119 return 1;
2120 vcpu->arch.osvw.length = data;
2121 break;
2122 case MSR_AMD64_OSVW_STATUS:
2123 if (!guest_cpuid_has_osvw(vcpu))
2124 return 1;
2125 vcpu->arch.osvw.status = data;
2126 break;
15c4a640 2127 default:
ffde22ac
ES		 2128 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2129 return xen_hvm_config(vcpu, data);
c6702c9d 2130 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2131 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2132 if (!ignore_msrs) {
a737f256
CD		 2133 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2134 msr, data);
ed85c068
AP		 2135 return 1;
2136 } else {
a737f256
CD		 2137 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2138 msr, data);
ed85c068
AP		 2139 break;
2140 }
15c4a640
CO		 2141 }
2142 return 0;
2143}
2144EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2145
2146
2147/*
2148 * Reads an msr value (of 'msr_index') into 'pdata'.
2149 * Returns 0 on success, non-0 otherwise.
2150 * Assumes vcpu_load() was already called.
2151 */
609e36d3 2152int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2153{
609e36d3 2154 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2155}
ff651cb6 2156EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2157
890ca9ae 2158static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2159{
2160 u64 data;
890ca9ae
HY		 2161 u64 mcg_cap = vcpu->arch.mcg_cap;
2162 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2163
2164 switch (msr) {
15c4a640
CO		 2165 case MSR_IA32_P5_MC_ADDR:
2166 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2167 data = 0;
2168 break;
15c4a640 2169 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2170 data = vcpu->arch.mcg_cap;
2171 break;
c7ac679c 2172 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2173 if (!(mcg_cap & MCG_CTL_P))
2174 return 1;
2175 data = vcpu->arch.mcg_ctl;
2176 break;
2177 case MSR_IA32_MCG_STATUS:
2178 data = vcpu->arch.mcg_status;
2179 break;
2180 default:
2181 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2182 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2183 u32 offset = msr - MSR_IA32_MC0_CTL;
2184 data = vcpu->arch.mce_banks[offset];
2185 break;
2186 }
2187 return 1;
2188 }
2189 *pdata = data;
2190 return 0;
2191}
2192
609e36d3 2193int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2194{
609e36d3 2195 switch (msr_info->index) {
890ca9ae 2196 case MSR_IA32_PLATFORM_ID:
15c4a640 2197 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2198 case MSR_IA32_DEBUGCTLMSR:
2199 case MSR_IA32_LASTBRANCHFROMIP:
2200 case MSR_IA32_LASTBRANCHTOIP:
2201 case MSR_IA32_LASTINTFROMIP:
2202 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2203 case MSR_K8_SYSCFG:
2204 case MSR_K7_HWCR:
61a6bd67 2205 case MSR_VM_HSAVE_PA:
1fdbd48c 2206 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2207 case MSR_AMD64_NB_CFG:
f7c6d140 2208 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2209 case MSR_AMD64_BU_CFG2:
609e36d3 2210 msr_info->data = 0;
15c4a640 2211 break;
6912ac32
WH		 2212 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2213 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2214 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2215 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2216 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2217 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2218 msr_info->data = 0;
5753785f 2219 break;
742bc670 2220 case MSR_IA32_UCODE_REV:
609e36d3 2221 msr_info->data = 0x100000000ULL;
742bc670 2222 break;
9ba075a6 2223 case MSR_MTRRcap:
9ba075a6 2224 case 0x200 ... 0x2ff:
ff53604b 2225 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2226 case 0xcd: /* fsb frequency */
609e36d3 2227 msr_info->data = 3;
15c4a640 2228 break;
7b914098
JS		 2229 /*
2230 * MSR_EBC_FREQUENCY_ID
2231 * Conservative value valid for even the basic CPU models.
2232 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2233 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2234 * and 266MHz for model 3, or 4. Set Core Clock
2235 * Frequency to System Bus Frequency Ratio to 1 (bits
2236 * 31:24) even though these are only valid for CPU
2237 * models > 2, however guests may end up dividing or
2238 * multiplying by zero otherwise.
2239 */
2240 case MSR_EBC_FREQUENCY_ID:
609e36d3 2241 msr_info->data = 1 << 24;
7b914098 2242 break;
15c4a640 2243 case MSR_IA32_APICBASE:
609e36d3 2244 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2245 break;
0105d1a5 2246 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2247 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2248 break;
a3e06bbe 2249 case MSR_IA32_TSCDEADLINE:
609e36d3 2250 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2251 break;
ba904635 2252 case MSR_IA32_TSC_ADJUST:
609e36d3 2253 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2254 break;
15c4a640 2255 case MSR_IA32_MISC_ENABLE:
609e36d3 2256 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2257 break;
64d60670
PB		 2258 case MSR_IA32_SMBASE:
2259 if (!msr_info->host_initiated)
2260 return 1;
2261 msr_info->data = vcpu->arch.smbase;
15c4a640 2262 break;
847f0ad8
AG		 2263 case MSR_IA32_PERF_STATUS:
2264 /* TSC increment by tick */
609e36d3 2265 msr_info->data = 1000ULL;
847f0ad8 2266 /* CPU multiplier */
b0996ae4 2267 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2268 break;
15c4a640 2269 case MSR_EFER:
609e36d3 2270 msr_info->data = vcpu->arch.efer;
15c4a640 2271 break;
18068523 2272 case MSR_KVM_WALL_CLOCK:
11c6bffa 2273 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2274 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2275 break;
2276 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2277 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2278 msr_info->data = vcpu->arch.time;
18068523 2279 break;
344d9588 2280 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2281 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2282 break;
c9aaa895 2283 case MSR_KVM_STEAL_TIME:
609e36d3 2284 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2285 break;
1d92128f 2286 case MSR_KVM_PV_EOI_EN:
609e36d3 2287 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2288 break;
890ca9ae
HY		 2289 case MSR_IA32_P5_MC_ADDR:
2290 case MSR_IA32_P5_MC_TYPE:
2291 case MSR_IA32_MCG_CAP:
2292 case MSR_IA32_MCG_CTL:
2293 case MSR_IA32_MCG_STATUS:
81760dcc 2294 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2295 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2296 case MSR_K7_CLK_CTL:
2297 /*
2298 * Provide expected ramp-up count for K7. All other
2299 * are set to zero, indicating minimum divisors for
2300 * every field.
2301 *
2302 * This prevents guest kernels on AMD host with CPU
2303 * type 6, model 8 and higher from exploding due to
2304 * the rdmsr failing.
2305 */
609e36d3 2306 msr_info->data = 0x20000000;
84e0cefa 2307 break;
55cd8e5a 2308 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2309 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2310 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2311 return kvm_hv_get_msr_common(vcpu,
2312 msr_info->index, &msr_info->data);
55cd8e5a 2313 break;
91c9c3ed 2314 case MSR_IA32_BBL_CR_CTL3:
2315 /* This legacy MSR exists but isn't fully documented in current
2316 * silicon. It is however accessed by winxp in very narrow
2317 * scenarios where it sets bit #19, itself documented as
2318 * a "reserved" bit. Best effort attempt to source coherent
2319 * read data here should the balance of the register be
2320 * interpreted by the guest:
2321 *
2322 * L2 cache control register 3: 64GB range, 256KB size,
2323 * enabled, latency 0x1, configured
2324 */
609e36d3 2325 msr_info->data = 0xbe702111;
91c9c3ed 2326 break;
2b036c6b
BO		 2327 case MSR_AMD64_OSVW_ID_LENGTH:
2328 if (!guest_cpuid_has_osvw(vcpu))
2329 return 1;
609e36d3 2330 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2331 break;
2332 case MSR_AMD64_OSVW_STATUS:
2333 if (!guest_cpuid_has_osvw(vcpu))
2334 return 1;
609e36d3 2335 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2336 break;
15c4a640 2337 default:
c6702c9d 2338 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2339 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2340 if (!ignore_msrs) {
609e36d3 2341 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2342 return 1;
2343 } else {
609e36d3
PB		 2344 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2345 msr_info->data = 0;
ed85c068
AP		 2346 }
2347 break;
15c4a640 2348 }
15c4a640
CO		 2349 return 0;
2350}
2351EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2352
313a3dc7
CO		 2353/*
2354 * Read or write a bunch of msrs. All parameters are kernel addresses.
2355 *
2356 * @return number of msrs set successfully.
2357 */
2358static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2359 struct kvm_msr_entry *entries,
2360 int (*do_msr)(struct kvm_vcpu *vcpu,
2361 unsigned index, u64 *data))
2362{
f656ce01 2363 int i, idx;
313a3dc7 2364
f656ce01 2365 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2366 for (i = 0; i < msrs->nmsrs; ++i)
2367 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2368 break;
f656ce01 2369 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2370
313a3dc7
CO		 2371 return i;
2372}
2373
2374/*
2375 * Read or write a bunch of msrs. Parameters are user addresses.
2376 *
2377 * @return number of msrs set successfully.
2378 */
2379static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2380 int (*do_msr)(struct kvm_vcpu *vcpu,
2381 unsigned index, u64 *data),
2382 int writeback)
2383{
2384 struct kvm_msrs msrs;
2385 struct kvm_msr_entry *entries;
2386 int r, n;
2387 unsigned size;
2388
2389 r = -EFAULT;
2390 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2391 goto out;
2392
2393 r = -E2BIG;
2394 if (msrs.nmsrs >= MAX_IO_MSRS)
2395 goto out;
2396
313a3dc7 2397 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2398 entries = memdup_user(user_msrs->entries, size);
2399 if (IS_ERR(entries)) {
2400 r = PTR_ERR(entries);
313a3dc7 2401 goto out;
ff5c2c03 2402 }
313a3dc7
CO		 2403
2404 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2405 if (r < 0)
2406 goto out_free;
2407
2408 r = -EFAULT;
2409 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2410 goto out_free;
2411
2412 r = n;
2413
2414out_free:
7a73c028 2415 kfree(entries);
313a3dc7
CO		 2416out:
2417 return r;
2418}
2419
784aa3d7 2420int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2421{
2422 int r;
2423
2424 switch (ext) {
2425 case KVM_CAP_IRQCHIP:
2426 case KVM_CAP_HLT:
2427 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2428 case KVM_CAP_SET_TSS_ADDR:
07716717 2429 case KVM_CAP_EXT_CPUID:
9c15bb1d 2430 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2431 case KVM_CAP_CLOCKSOURCE:
7837699f 2432 case KVM_CAP_PIT:
a28e4f5a 2433 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2434 case KVM_CAP_MP_STATE:
ed848624 2435 case KVM_CAP_SYNC_MMU:
a355c85c 2436 case KVM_CAP_USER_NMI:
52d939a0 2437 case KVM_CAP_REINJECT_CONTROL:
4925663a 2438 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2439 case KVM_CAP_IOEVENTFD:
f848a5a8 2440 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2441 case KVM_CAP_PIT2:
e9f42757 2442 case KVM_CAP_PIT_STATE2:
b927a3ce 2443 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2444 case KVM_CAP_XEN_HVM:
afbcf7ab 2445 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2446 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2447 case KVM_CAP_HYPERV:
10388a07 2448 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2449 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2450 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2451 case KVM_CAP_DEBUGREGS:
d2be1651 2452 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2453 case KVM_CAP_XSAVE:
344d9588 2454 case KVM_CAP_ASYNC_PF:
92a1f12d 2455 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2456 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2457 case KVM_CAP_READONLY_MEM:
5f66b620 2458 case KVM_CAP_HYPERV_TIME:
100943c5 2459 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2460 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2461 case KVM_CAP_ENABLE_CAP_VM:
2462 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2463 case KVM_CAP_SET_BOOT_CPU_ID:
2a5bab10
AW		 2464#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2465 case KVM_CAP_ASSIGN_DEV_IRQ:
2466 case KVM_CAP_PCI_2_3:
2467#endif
018d00d2
ZX		 2468 r = 1;
2469 break;
6d396b55
PB		 2470 case KVM_CAP_X86_SMM:
2471 /* SMBASE is usually relocated above 1M on modern chipsets,
2472 * and SMM handlers might indeed rely on 4G segment limits,
2473 * so do not report SMM to be available if real mode is
2474 * emulated via vm86 mode. Still, do not go to great lengths
2475 * to avoid userspace's usage of the feature, because it is a
2476 * fringe case that is not enabled except via specific settings
2477 * of the module parameters.
2478 */
2479 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2480 break;
542472b5
LV		 2481 case KVM_CAP_COALESCED_MMIO:
2482 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2483 break;
774ead3a
AK		 2484 case KVM_CAP_VAPIC:
2485 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2486 break;
f725230a 2487 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2488 r = KVM_SOFT_MAX_VCPUS;
2489 break;
2490 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2491 r = KVM_MAX_VCPUS;
2492 break;
a988b910 2493 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2494 r = KVM_USER_MEM_SLOTS;
a988b910 2495 break;
a68a6a72
MT		 2496 case KVM_CAP_PV_MMU: /* obsolete */
2497 r = 0;
2f333bcb 2498 break;
4cee4b72 2499#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2500 case KVM_CAP_IOMMU:
a1b60c1c 2501 r = iommu_present(&pci_bus_type);
62c476c7 2502 break;
4cee4b72 2503#endif
890ca9ae
HY		 2504 case KVM_CAP_MCE:
2505 r = KVM_MAX_MCE_BANKS;
2506 break;
2d5b5a66
SY		 2507 case KVM_CAP_XCRS:
2508 r = cpu_has_xsave;
2509 break;
92a1f12d
JR		 2510 case KVM_CAP_TSC_CONTROL:
2511 r = kvm_has_tsc_control;
2512 break;
018d00d2
ZX		 2513 default:
2514 r = 0;
2515 break;
2516 }
2517 return r;
2518
2519}
2520
043405e1
CO		 2521long kvm_arch_dev_ioctl(struct file *filp,
2522 unsigned int ioctl, unsigned long arg)
2523{
2524 void __user *argp = (void __user *)arg;
2525 long r;
2526
2527 switch (ioctl) {
2528 case KVM_GET_MSR_INDEX_LIST: {
2529 struct kvm_msr_list __user *user_msr_list = argp;
2530 struct kvm_msr_list msr_list;
2531 unsigned n;
2532
2533 r = -EFAULT;
2534 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2535 goto out;
2536 n = msr_list.nmsrs;
62ef68bb 2537 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2538 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2539 goto out;
2540 r = -E2BIG;
e125e7b6 2541 if (n < msr_list.nmsrs)
043405e1
CO		 2542 goto out;
2543 r = -EFAULT;
2544 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2545 num_msrs_to_save * sizeof(u32)))
2546 goto out;
e125e7b6 2547 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2548 &emulated_msrs,
62ef68bb 2549 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2550 goto out;
2551 r = 0;
2552 break;
2553 }
9c15bb1d
BP		 2554 case KVM_GET_SUPPORTED_CPUID:
2555 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2556 struct kvm_cpuid2 __user *cpuid_arg = argp;
2557 struct kvm_cpuid2 cpuid;
2558
2559 r = -EFAULT;
2560 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2561 goto out;
9c15bb1d
BP		 2562
2563 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2564 ioctl);
674eea0f
AK		 2565 if (r)
2566 goto out;
2567
2568 r = -EFAULT;
2569 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2570 goto out;
2571 r = 0;
2572 break;
2573 }
890ca9ae
HY		 2574 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2575 u64 mce_cap;
2576
2577 mce_cap = KVM_MCE_CAP_SUPPORTED;
2578 r = -EFAULT;
2579 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2580 goto out;
2581 r = 0;
2582 break;
2583 }
043405e1
CO		 2584 default:
2585 r = -EINVAL;
2586 }
2587out:
2588 return r;
2589}
2590
f5f48ee1
SY		 2591static void wbinvd_ipi(void *garbage)
2592{
2593 wbinvd();
2594}
2595
2596static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2597{
e0f0bbc5 2598 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2599}
2600
313a3dc7
CO		 2601void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2602{
f5f48ee1
SY		 2603 /* Address WBINVD may be executed by guest */
2604 if (need_emulate_wbinvd(vcpu)) {
2605 if (kvm_x86_ops->has_wbinvd_exit())
2606 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2607 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2608 smp_call_function_single(vcpu->cpu,
2609 wbinvd_ipi, NULL, 1);
2610 }
2611
313a3dc7 2612 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2613
0dd6a6ed
ZA		 2614 /* Apply any externally detected TSC adjustments (due to suspend) */
2615 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2616 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2617 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2618 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2619 }
8f6055cb 2620
48434c20 2621 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2622 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2623 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2624 if (tsc_delta < 0)
2625 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2626 if (check_tsc_unstable()) {
b183aa58
ZA		 2627 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2628 vcpu->arch.last_guest_tsc);
2629 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2630 vcpu->arch.tsc_catchup = 1;
c285545f 2631 }
d98d07ca
MT		 2632 /*
2633 * On a host with synchronized TSC, there is no need to update
2634 * kvmclock on vcpu->cpu migration
2635 */
2636 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2637 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2638 if (vcpu->cpu != cpu)
2639 kvm_migrate_timers(vcpu);
e48672fa 2640 vcpu->cpu = cpu;
6b7d7e76 2641 }
c9aaa895
GC		 2642
2643 accumulate_steal_time(vcpu);
2644 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2645}
2646
2647void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2648{
02daab21 2649 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2650 kvm_put_guest_fpu(vcpu);
6f526ec5 2651 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2652}
2653
313a3dc7
CO		 2654static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2655 struct kvm_lapic_state *s)
2656{
5a71785d 2657 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2658 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2659
2660 return 0;
2661}
2662
2663static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2664 struct kvm_lapic_state *s)
2665{
64eb0620 2666 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2667 update_cr8_intercept(vcpu);
313a3dc7
CO		 2668
2669 return 0;
2670}
2671
f77bc6a4
ZX		 2672static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2673 struct kvm_interrupt *irq)
2674{
02cdb50f 2675 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2676 return -EINVAL;
2677 if (irqchip_in_kernel(vcpu->kvm))
2678 return -ENXIO;
f77bc6a4 2679
66fd3f7f 2680 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2681 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2682
f77bc6a4
ZX		 2683 return 0;
2684}
2685
c4abb7c9
JK		 2686static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2687{
c4abb7c9 2688 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2689
2690 return 0;
2691}
2692
f077825a
PB		 2693static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2694{
64d60670
PB		 2695 kvm_make_request(KVM_REQ_SMI, vcpu);
2696
f077825a
PB		 2697 return 0;
2698}
2699
b209749f
AK		 2700static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2701 struct kvm_tpr_access_ctl *tac)
2702{
2703 if (tac->flags)
2704 return -EINVAL;
2705 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2706 return 0;
2707}
2708
890ca9ae
HY		 2709static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2710 u64 mcg_cap)
2711{
2712 int r;
2713 unsigned bank_num = mcg_cap & 0xff, bank;
2714
2715 r = -EINVAL;
a9e38c3e 2716 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2717 goto out;
2718 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2719 goto out;
2720 r = 0;
2721 vcpu->arch.mcg_cap = mcg_cap;
2722 /* Init IA32_MCG_CTL to all 1s */
2723 if (mcg_cap & MCG_CTL_P)
2724 vcpu->arch.mcg_ctl = ~(u64)0;
2725 /* Init IA32_MCi_CTL to all 1s */
2726 for (bank = 0; bank < bank_num; bank++)
2727 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2728out:
2729 return r;
2730}
2731
2732static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2733 struct kvm_x86_mce *mce)
2734{
2735 u64 mcg_cap = vcpu->arch.mcg_cap;
2736 unsigned bank_num = mcg_cap & 0xff;
2737 u64 *banks = vcpu->arch.mce_banks;
2738
2739 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2740 return -EINVAL;
2741 /*
2742 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2743 * reporting is disabled
2744 */
2745 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2746 vcpu->arch.mcg_ctl != ~(u64)0)
2747 return 0;
2748 banks += 4 * mce->bank;
2749 /*
2750 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2751 * reporting is disabled for the bank
2752 */
2753 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2754 return 0;
2755 if (mce->status & MCI_STATUS_UC) {
2756 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2757 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2758 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2759 return 0;
2760 }
2761 if (banks[1] & MCI_STATUS_VAL)
2762 mce->status |= MCI_STATUS_OVER;
2763 banks[2] = mce->addr;
2764 banks[3] = mce->misc;
2765 vcpu->arch.mcg_status = mce->mcg_status;
2766 banks[1] = mce->status;
2767 kvm_queue_exception(vcpu, MC_VECTOR);
2768 } else if (!(banks[1] & MCI_STATUS_VAL)
2769 || !(banks[1] & MCI_STATUS_UC)) {
2770 if (banks[1] & MCI_STATUS_VAL)
2771 mce->status |= MCI_STATUS_OVER;
2772 banks[2] = mce->addr;
2773 banks[3] = mce->misc;
2774 banks[1] = mce->status;
2775 } else
2776 banks[1] |= MCI_STATUS_OVER;
2777 return 0;
2778}
2779
3cfc3092
JK		 2780static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2781 struct kvm_vcpu_events *events)
2782{
7460fb4a 2783 process_nmi(vcpu);
03b82a30
JK		 2784 events->exception.injected =
2785 vcpu->arch.exception.pending &&
2786 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2787 events->exception.nr = vcpu->arch.exception.nr;
2788 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2789 events->exception.pad = 0;
3cfc3092
JK		 2790 events->exception.error_code = vcpu->arch.exception.error_code;
2791
03b82a30
JK		 2792 events->interrupt.injected =
2793 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2794 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2795 events->interrupt.soft = 0;
37ccdcbe 2796 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2797
2798 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2799 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2800 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2801 events->nmi.pad = 0;
3cfc3092 2802
66450a21 2803 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2804
f077825a
PB		 2805 events->smi.smm = is_smm(vcpu);
2806 events->smi.pending = vcpu->arch.smi_pending;
2807 events->smi.smm_inside_nmi =
2808 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2809 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2810
dab4b911 2811 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2812 | KVM_VCPUEVENT_VALID_SHADOW
2813 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2814 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2815}
2816
2817static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2818 struct kvm_vcpu_events *events)
2819{
dab4b911 2820 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2821 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2822 | KVM_VCPUEVENT_VALID_SHADOW
2823 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2824 return -EINVAL;
2825
7460fb4a 2826 process_nmi(vcpu);
3cfc3092
JK		 2827 vcpu->arch.exception.pending = events->exception.injected;
2828 vcpu->arch.exception.nr = events->exception.nr;
2829 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2830 vcpu->arch.exception.error_code = events->exception.error_code;
2831
2832 vcpu->arch.interrupt.pending = events->interrupt.injected;
2833 vcpu->arch.interrupt.nr = events->interrupt.nr;
2834 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2835 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2836 kvm_x86_ops->set_interrupt_shadow(vcpu,
2837 events->interrupt.shadow);
3cfc3092
JK		 2838
2839 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2840 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2841 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2842 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2843
66450a21
JK		 2844 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2845 kvm_vcpu_has_lapic(vcpu))
2846 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2847
f077825a
PB		 2848 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2849 if (events->smi.smm)
2850 vcpu->arch.hflags |= HF_SMM_MASK;
2851 else
2852 vcpu->arch.hflags &= ~HF_SMM_MASK;
2853 vcpu->arch.smi_pending = events->smi.pending;
2854 if (events->smi.smm_inside_nmi)
2855 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2856 else
2857 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2858 if (kvm_vcpu_has_lapic(vcpu)) {
2859 if (events->smi.latched_init)
2860 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2861 else
2862 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2863 }
2864 }
2865
3842d135
AK		 2866 kvm_make_request(KVM_REQ_EVENT, vcpu);
2867
3cfc3092
JK		 2868 return 0;
2869}
2870
a1efbe77
JK		 2871static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2872 struct kvm_debugregs *dbgregs)
2873{
73aaf249
JK		 2874 unsigned long val;
2875
a1efbe77 2876 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2877 kvm_get_dr(vcpu, 6, &val);
73aaf249 2878 dbgregs->dr6 = val;
a1efbe77
JK		 2879 dbgregs->dr7 = vcpu->arch.dr7;
2880 dbgregs->flags = 0;
97e69aa6 2881 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2882}
2883
2884static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2885 struct kvm_debugregs *dbgregs)
2886{
2887 if (dbgregs->flags)
2888 return -EINVAL;
2889
a1efbe77 2890 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2891 kvm_update_dr0123(vcpu);
a1efbe77 2892 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2893 kvm_update_dr6(vcpu);
a1efbe77 2894 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2895 kvm_update_dr7(vcpu);
a1efbe77 2896
a1efbe77
JK		 2897 return 0;
2898}
2899
df1daba7
PB		 2900#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2901
2902static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2903{
c47ada30 2904 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2905 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2906 u64 valid;
2907
2908 /*
2909 * Copy legacy XSAVE area, to avoid complications with CPUID
2910 * leaves 0 and 1 in the loop below.
2911 */
2912 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2913
2914 /* Set XSTATE_BV */
2915 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2916
2917 /*
2918 * Copy each region from the possibly compacted offset to the
2919 * non-compacted offset.
2920 */
2921 valid = xstate_bv & ~XSTATE_FPSSE;
2922 while (valid) {
2923 u64 feature = valid & -valid;
2924 int index = fls64(feature) - 1;
2925 void *src = get_xsave_addr(xsave, feature);
2926
2927 if (src) {
2928 u32 size, offset, ecx, edx;
2929 cpuid_count(XSTATE_CPUID, index,
2930 &size, &offset, &ecx, &edx);
2931 memcpy(dest + offset, src, size);
2932 }
2933
2934 valid -= feature;
2935 }
2936}
2937
2938static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2939{
c47ada30 2940 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2941 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2942 u64 valid;
2943
2944 /*
2945 * Copy legacy XSAVE area, to avoid complications with CPUID
2946 * leaves 0 and 1 in the loop below.
2947 */
2948 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2949
2950 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2951 xsave->header.xfeatures = xstate_bv;
df1daba7 2952 if (cpu_has_xsaves)
3a54450b 2953 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2954
2955 /*
2956 * Copy each region from the non-compacted offset to the
2957 * possibly compacted offset.
2958 */
2959 valid = xstate_bv & ~XSTATE_FPSSE;
2960 while (valid) {
2961 u64 feature = valid & -valid;
2962 int index = fls64(feature) - 1;
2963 void *dest = get_xsave_addr(xsave, feature);
2964
2965 if (dest) {
2966 u32 size, offset, ecx, edx;
2967 cpuid_count(XSTATE_CPUID, index,
2968 &size, &offset, &ecx, &edx);
2969 memcpy(dest, src + offset, size);
ee4100da 2970 }
df1daba7
PB		 2971
2972 valid -= feature;
2973 }
2974}
2975
2d5b5a66
SY		 2976static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2977 struct kvm_xsave *guest_xsave)
2978{
4344ee98 2979 if (cpu_has_xsave) {
df1daba7
PB		 2980 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2981 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2982 } else {
2d5b5a66 2983 memcpy(guest_xsave->region,
7366ed77 2984 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2985 sizeof(struct fxregs_state));
2d5b5a66
SY		 2986 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2987 XSTATE_FPSSE;
2988 }
2989}
2990
2991static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2992 struct kvm_xsave *guest_xsave)
2993{
2994 u64 xstate_bv =
2995 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2996
d7876f1b
PB		 2997 if (cpu_has_xsave) {
2998 /*
2999 * Here we allow setting states that are not present in
3000 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3001 * with old userspace.
3002 */
4ff41732 3003 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3004 return -EINVAL;
df1daba7 3005 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3006 } else {
2d5b5a66
SY		 3007 if (xstate_bv & ~XSTATE_FPSSE)
3008 return -EINVAL;
7366ed77 3009 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3010 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3011 }
3012 return 0;
3013}
3014
3015static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3016 struct kvm_xcrs *guest_xcrs)
3017{
3018 if (!cpu_has_xsave) {
3019 guest_xcrs->nr_xcrs = 0;
3020 return;
3021 }
3022
3023 guest_xcrs->nr_xcrs = 1;
3024 guest_xcrs->flags = 0;
3025 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3026 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3027}
3028
3029static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3030 struct kvm_xcrs *guest_xcrs)
3031{
3032 int i, r = 0;
3033
3034 if (!cpu_has_xsave)
3035 return -EINVAL;
3036
3037 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3038 return -EINVAL;
3039
3040 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3041 /* Only support XCR0 currently */
c67a04cb 3042 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3043 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3044 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3045 break;
3046 }
3047 if (r)
3048 r = -EINVAL;
3049 return r;
3050}
3051
1c0b28c2
EM		 3052/*
3053 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3054 * stopped by the hypervisor. This function will be called from the host only.
3055 * EINVAL is returned when the host attempts to set the flag for a guest that
3056 * does not support pv clocks.
3057 */
3058static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3059{
0b79459b 3060 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3061 return -EINVAL;
51d59c6b 3062 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3063 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3064 return 0;
3065}
3066
313a3dc7
CO		 3067long kvm_arch_vcpu_ioctl(struct file *filp,
3068 unsigned int ioctl, unsigned long arg)
3069{
3070 struct kvm_vcpu *vcpu = filp->private_data;
3071 void __user *argp = (void __user *)arg;
3072 int r;
d1ac91d8
AK		 3073 union {
3074 struct kvm_lapic_state *lapic;
3075 struct kvm_xsave *xsave;
3076 struct kvm_xcrs *xcrs;
3077 void *buffer;
3078 } u;
3079
3080 u.buffer = NULL;
313a3dc7
CO		 3081 switch (ioctl) {
3082 case KVM_GET_LAPIC: {
2204ae3c
MT		 3083 r = -EINVAL;
3084 if (!vcpu->arch.apic)
3085 goto out;
d1ac91d8 3086 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3087
b772ff36 3088 r = -ENOMEM;
d1ac91d8 3089 if (!u.lapic)
b772ff36 3090 goto out;
d1ac91d8 3091 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3092 if (r)
3093 goto out;
3094 r = -EFAULT;
d1ac91d8 3095 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3096 goto out;
3097 r = 0;
3098 break;
3099 }
3100 case KVM_SET_LAPIC: {
2204ae3c
MT		 3101 r = -EINVAL;
3102 if (!vcpu->arch.apic)
3103 goto out;
ff5c2c03 3104 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3105 if (IS_ERR(u.lapic))
3106 return PTR_ERR(u.lapic);
ff5c2c03 3107
d1ac91d8 3108 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3109 break;
3110 }
f77bc6a4
ZX		 3111 case KVM_INTERRUPT: {
3112 struct kvm_interrupt irq;
3113
3114 r = -EFAULT;
3115 if (copy_from_user(&irq, argp, sizeof irq))
3116 goto out;
3117 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3118 break;
3119 }
c4abb7c9
JK		 3120 case KVM_NMI: {
3121 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3122 break;
3123 }
f077825a
PB		 3124 case KVM_SMI: {
3125 r = kvm_vcpu_ioctl_smi(vcpu);
3126 break;
3127 }
313a3dc7
CO		 3128 case KVM_SET_CPUID: {
3129 struct kvm_cpuid __user *cpuid_arg = argp;
3130 struct kvm_cpuid cpuid;
3131
3132 r = -EFAULT;
3133 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3134 goto out;
3135 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3136 break;
3137 }
07716717
DK		 3138 case KVM_SET_CPUID2: {
3139 struct kvm_cpuid2 __user *cpuid_arg = argp;
3140 struct kvm_cpuid2 cpuid;
3141
3142 r = -EFAULT;
3143 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3144 goto out;
3145 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3146 cpuid_arg->entries);
07716717
DK		 3147 break;
3148 }
3149 case KVM_GET_CPUID2: {
3150 struct kvm_cpuid2 __user *cpuid_arg = argp;
3151 struct kvm_cpuid2 cpuid;
3152
3153 r = -EFAULT;
3154 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3155 goto out;
3156 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3157 cpuid_arg->entries);
07716717
DK		 3158 if (r)
3159 goto out;
3160 r = -EFAULT;
3161 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3162 goto out;
3163 r = 0;
3164 break;
3165 }
313a3dc7 3166 case KVM_GET_MSRS:
609e36d3 3167 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3168 break;
3169 case KVM_SET_MSRS:
3170 r = msr_io(vcpu, argp, do_set_msr, 0);
3171 break;
b209749f
AK		 3172 case KVM_TPR_ACCESS_REPORTING: {
3173 struct kvm_tpr_access_ctl tac;
3174
3175 r = -EFAULT;
3176 if (copy_from_user(&tac, argp, sizeof tac))
3177 goto out;
3178 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3179 if (r)
3180 goto out;
3181 r = -EFAULT;
3182 if (copy_to_user(argp, &tac, sizeof tac))
3183 goto out;
3184 r = 0;
3185 break;
3186 };
b93463aa
AK		 3187 case KVM_SET_VAPIC_ADDR: {
3188 struct kvm_vapic_addr va;
3189
3190 r = -EINVAL;
3191 if (!irqchip_in_kernel(vcpu->kvm))
3192 goto out;
3193 r = -EFAULT;
3194 if (copy_from_user(&va, argp, sizeof va))
3195 goto out;
fda4e2e8 3196 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3197 break;
3198 }
890ca9ae
HY		 3199 case KVM_X86_SETUP_MCE: {
3200 u64 mcg_cap;
3201
3202 r = -EFAULT;
3203 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3204 goto out;
3205 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3206 break;
3207 }
3208 case KVM_X86_SET_MCE: {
3209 struct kvm_x86_mce mce;
3210
3211 r = -EFAULT;
3212 if (copy_from_user(&mce, argp, sizeof mce))
3213 goto out;
3214 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3215 break;
3216 }
3cfc3092
JK		 3217 case KVM_GET_VCPU_EVENTS: {
3218 struct kvm_vcpu_events events;
3219
3220 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3221
3222 r = -EFAULT;
3223 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3224 break;
3225 r = 0;
3226 break;
3227 }
3228 case KVM_SET_VCPU_EVENTS: {
3229 struct kvm_vcpu_events events;
3230
3231 r = -EFAULT;
3232 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3233 break;
3234
3235 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3236 break;
3237 }
a1efbe77
JK		 3238 case KVM_GET_DEBUGREGS: {
3239 struct kvm_debugregs dbgregs;
3240
3241 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3242
3243 r = -EFAULT;
3244 if (copy_to_user(argp, &dbgregs,
3245 sizeof(struct kvm_debugregs)))
3246 break;
3247 r = 0;
3248 break;
3249 }
3250 case KVM_SET_DEBUGREGS: {
3251 struct kvm_debugregs dbgregs;
3252
3253 r = -EFAULT;
3254 if (copy_from_user(&dbgregs, argp,
3255 sizeof(struct kvm_debugregs)))
3256 break;
3257
3258 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3259 break;
3260 }
2d5b5a66 3261 case KVM_GET_XSAVE: {
d1ac91d8 3262 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3263 r = -ENOMEM;
d1ac91d8 3264 if (!u.xsave)
2d5b5a66
SY		 3265 break;
3266
d1ac91d8 3267 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3268
3269 r = -EFAULT;
d1ac91d8 3270 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3271 break;
3272 r = 0;
3273 break;
3274 }
3275 case KVM_SET_XSAVE: {
ff5c2c03 3276 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3277 if (IS_ERR(u.xsave))
3278 return PTR_ERR(u.xsave);
2d5b5a66 3279
d1ac91d8 3280 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3281 break;
3282 }
3283 case KVM_GET_XCRS: {
d1ac91d8 3284 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3285 r = -ENOMEM;
d1ac91d8 3286 if (!u.xcrs)
2d5b5a66
SY		 3287 break;
3288
d1ac91d8 3289 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3290
3291 r = -EFAULT;
d1ac91d8 3292 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3293 sizeof(struct kvm_xcrs)))
3294 break;
3295 r = 0;
3296 break;
3297 }
3298 case KVM_SET_XCRS: {
ff5c2c03 3299 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3300 if (IS_ERR(u.xcrs))
3301 return PTR_ERR(u.xcrs);
2d5b5a66 3302
d1ac91d8 3303 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3304 break;
3305 }
92a1f12d
JR		 3306 case KVM_SET_TSC_KHZ: {
3307 u32 user_tsc_khz;
3308
3309 r = -EINVAL;
92a1f12d
JR		 3310 user_tsc_khz = (u32)arg;
3311
3312 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3313 goto out;
3314
cc578287
ZA		 3315 if (user_tsc_khz == 0)
3316 user_tsc_khz = tsc_khz;
3317
3318 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3319
3320 r = 0;
3321 goto out;
3322 }
3323 case KVM_GET_TSC_KHZ: {
cc578287 3324 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3325 goto out;
3326 }
1c0b28c2
EM		 3327 case KVM_KVMCLOCK_CTRL: {
3328 r = kvm_set_guest_paused(vcpu);
3329 goto out;
3330 }
313a3dc7
CO		 3331 default:
3332 r = -EINVAL;
3333 }
3334out:
d1ac91d8 3335 kfree(u.buffer);
313a3dc7
CO		 3336 return r;
3337}
3338
5b1c1493
CO		 3339int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3340{
3341 return VM_FAULT_SIGBUS;
3342}
3343
1fe779f8
CO		 3344static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3345{
3346 int ret;
3347
3348 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3349 return -EINVAL;
1fe779f8
CO		 3350 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3351 return ret;
3352}
3353
b927a3ce
SY		 3354static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3355 u64 ident_addr)
3356{
3357 kvm->arch.ept_identity_map_addr = ident_addr;
3358 return 0;
3359}
3360
1fe779f8
CO		 3361static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3362 u32 kvm_nr_mmu_pages)
3363{
3364 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3365 return -EINVAL;
3366
79fac95e 3367 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3368
3369 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3370 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3371
79fac95e 3372 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3373 return 0;
3374}
3375
3376static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3377{
39de71ec 3378 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3379}
3380
1fe779f8
CO		 3381static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3382{
3383 int r;
3384
3385 r = 0;
3386 switch (chip->chip_id) {
3387 case KVM_IRQCHIP_PIC_MASTER:
3388 memcpy(&chip->chip.pic,
3389 &pic_irqchip(kvm)->pics[0],
3390 sizeof(struct kvm_pic_state));
3391 break;
3392 case KVM_IRQCHIP_PIC_SLAVE:
3393 memcpy(&chip->chip.pic,
3394 &pic_irqchip(kvm)->pics[1],
3395 sizeof(struct kvm_pic_state));
3396 break;
3397 case KVM_IRQCHIP_IOAPIC:
eba0226b 3398 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3399 break;
3400 default:
3401 r = -EINVAL;
3402 break;
3403 }
3404 return r;
3405}
3406
3407static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3408{
3409 int r;
3410
3411 r = 0;
3412 switch (chip->chip_id) {
3413 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3414 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3415 memcpy(&pic_irqchip(kvm)->pics[0],
3416 &chip->chip.pic,
3417 sizeof(struct kvm_pic_state));
f4f51050 3418 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3419 break;
3420 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3421 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3422 memcpy(&pic_irqchip(kvm)->pics[1],
3423 &chip->chip.pic,
3424 sizeof(struct kvm_pic_state));
f4f51050 3425 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3426 break;
3427 case KVM_IRQCHIP_IOAPIC:
eba0226b 3428 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3429 break;
3430 default:
3431 r = -EINVAL;
3432 break;
3433 }
3434 kvm_pic_update_irq(pic_irqchip(kvm));
3435 return r;
3436}
3437
e0f63cb9
SY		 3438static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3439{
3440 int r = 0;
3441
894a9c55 3442 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3443 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3444 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3445 return r;
3446}
3447
3448static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3449{
3450 int r = 0;
3451
894a9c55 3452 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3453 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3454 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3456 return r;
3457}
3458
3459static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3460{
3461 int r = 0;
3462
3463 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3464 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3465 sizeof(ps->channels));
3466 ps->flags = kvm->arch.vpit->pit_state.flags;
3467 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3468 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3469 return r;
3470}
3471
3472static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3473{
3474 int r = 0, start = 0;
3475 u32 prev_legacy, cur_legacy;
3476 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3477 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3478 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3479 if (!prev_legacy && cur_legacy)
3480 start = 1;
3481 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3482 sizeof(kvm->arch.vpit->pit_state.channels));
3483 kvm->arch.vpit->pit_state.flags = ps->flags;
3484 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3485 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3486 return r;
3487}
3488
52d939a0
MT		 3489static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3490 struct kvm_reinject_control *control)
3491{
3492 if (!kvm->arch.vpit)
3493 return -ENXIO;
894a9c55 3494 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3495 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3496 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3497 return 0;
3498}
3499
95d4c16c 3500/**
60c34612
TY		 3501 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3502 * @kvm: kvm instance
3503 * @log: slot id and address to which we copy the log
95d4c16c 3504 *
e108ff2f
PB		 3505 * Steps 1-4 below provide general overview of dirty page logging. See
3506 * kvm_get_dirty_log_protect() function description for additional details.
3507 *
3508 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3509 * always flush the TLB (step 4) even if previous step failed and the dirty
3510 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3511 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3512 * writes will be marked dirty for next log read.
95d4c16c 3513 *
60c34612
TY		 3514 * 1. Take a snapshot of the bit and clear it if needed.
3515 * 2. Write protect the corresponding page.
e108ff2f
PB		 3516 * 3. Copy the snapshot to the userspace.
3517 * 4. Flush TLB's if needed.
5bb064dc 3518 */
60c34612 3519int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3520{
60c34612 3521 bool is_dirty = false;
e108ff2f 3522 int r;
5bb064dc 3523
79fac95e 3524 mutex_lock(&kvm->slots_lock);
5bb064dc 3525
88178fd4
KH		 3526 /*
3527 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3528 */
3529 if (kvm_x86_ops->flush_log_dirty)
3530 kvm_x86_ops->flush_log_dirty(kvm);
3531
e108ff2f 3532 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3533
3534 /*
3535 * All the TLBs can be flushed out of mmu lock, see the comments in
3536 * kvm_mmu_slot_remove_write_access().
3537 */
e108ff2f 3538 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3539 if (is_dirty)
3540 kvm_flush_remote_tlbs(kvm);
3541
79fac95e 3542 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3543 return r;
3544}
3545
aa2fbe6d
YZ		 3546int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3547 bool line_status)
23d43cf9
CD		 3548{
3549 if (!irqchip_in_kernel(kvm))
3550 return -ENXIO;
3551
3552 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3553 irq_event->irq, irq_event->level,
3554 line_status);
23d43cf9
CD		 3555 return 0;
3556}
3557
90de4a18
NA		 3558static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3559 struct kvm_enable_cap *cap)
3560{
3561 int r;
3562
3563 if (cap->flags)
3564 return -EINVAL;
3565
3566 switch (cap->cap) {
3567 case KVM_CAP_DISABLE_QUIRKS:
3568 kvm->arch.disabled_quirks = cap->args[0];
3569 r = 0;
3570 break;
3571 default:
3572 r = -EINVAL;
3573 break;
3574 }
3575 return r;
3576}
3577
1fe779f8
CO		 3578long kvm_arch_vm_ioctl(struct file *filp,
3579 unsigned int ioctl, unsigned long arg)
3580{
3581 struct kvm *kvm = filp->private_data;
3582 void __user *argp = (void __user *)arg;
367e1319 3583 int r = -ENOTTY;
f0d66275
DH		 3584 /*
3585 * This union makes it completely explicit to gcc-3.x
3586 * that these two variables' stack usage should be
3587 * combined, not added together.
3588 */
3589 union {
3590 struct kvm_pit_state ps;
e9f42757 3591 struct kvm_pit_state2 ps2;
c5ff41ce 3592 struct kvm_pit_config pit_config;
f0d66275 3593 } u;
1fe779f8
CO		 3594
3595 switch (ioctl) {
3596 case KVM_SET_TSS_ADDR:
3597 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3598 break;
b927a3ce
SY		 3599 case KVM_SET_IDENTITY_MAP_ADDR: {
3600 u64 ident_addr;
3601
3602 r = -EFAULT;
3603 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3604 goto out;
3605 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3606 break;
3607 }
1fe779f8
CO		 3608 case KVM_SET_NR_MMU_PAGES:
3609 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3610 break;
3611 case KVM_GET_NR_MMU_PAGES:
3612 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3613 break;
3ddea128
MT		 3614 case KVM_CREATE_IRQCHIP: {
3615 struct kvm_pic *vpic;
3616
3617 mutex_lock(&kvm->lock);
3618 r = -EEXIST;
3619 if (kvm->arch.vpic)
3620 goto create_irqchip_unlock;
3e515705
AK		 3621 r = -EINVAL;
3622 if (atomic_read(&kvm->online_vcpus))
3623 goto create_irqchip_unlock;
1fe779f8 3624 r = -ENOMEM;
3ddea128
MT		 3625 vpic = kvm_create_pic(kvm);
3626 if (vpic) {
1fe779f8
CO		 3627 r = kvm_ioapic_init(kvm);
3628 if (r) {
175504cd 3629 mutex_lock(&kvm->slots_lock);
71ba994c 3630 kvm_destroy_pic(vpic);
175504cd 3631 mutex_unlock(&kvm->slots_lock);
3ddea128 3632 goto create_irqchip_unlock;
1fe779f8
CO		 3633 }
3634 } else
3ddea128 3635 goto create_irqchip_unlock;
399ec807
AK		 3636 r = kvm_setup_default_irq_routing(kvm);
3637 if (r) {
175504cd 3638 mutex_lock(&kvm->slots_lock);
3ddea128 3639 mutex_lock(&kvm->irq_lock);
72bb2fcd 3640 kvm_ioapic_destroy(kvm);
71ba994c 3641 kvm_destroy_pic(vpic);
3ddea128 3642 mutex_unlock(&kvm->irq_lock);
175504cd 3643 mutex_unlock(&kvm->slots_lock);
71ba994c 3644 goto create_irqchip_unlock;
399ec807 3645 }
71ba994c
PB		 3646 /* Write kvm->irq_routing before kvm->arch.vpic. */
3647 smp_wmb();
3648 kvm->arch.vpic = vpic;
3ddea128
MT		 3649 create_irqchip_unlock:
3650 mutex_unlock(&kvm->lock);
1fe779f8 3651 break;
3ddea128 3652 }
7837699f 3653 case KVM_CREATE_PIT:
c5ff41ce
JK		 3654 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3655 goto create_pit;
3656 case KVM_CREATE_PIT2:
3657 r = -EFAULT;
3658 if (copy_from_user(&u.pit_config, argp,
3659 sizeof(struct kvm_pit_config)))
3660 goto out;
3661 create_pit:
79fac95e 3662 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3663 r = -EEXIST;
3664 if (kvm->arch.vpit)
3665 goto create_pit_unlock;
7837699f 3666 r = -ENOMEM;
c5ff41ce 3667 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3668 if (kvm->arch.vpit)
3669 r = 0;
269e05e4 3670 create_pit_unlock:
79fac95e 3671 mutex_unlock(&kvm->slots_lock);
7837699f 3672 break;
1fe779f8
CO		 3673 case KVM_GET_IRQCHIP: {
3674 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3675 struct kvm_irqchip *chip;
1fe779f8 3676
ff5c2c03
SL		 3677 chip = memdup_user(argp, sizeof(*chip));
3678 if (IS_ERR(chip)) {
3679 r = PTR_ERR(chip);
1fe779f8 3680 goto out;
ff5c2c03
SL		 3681 }
3682
1fe779f8
CO		 3683 r = -ENXIO;
3684 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3685 goto get_irqchip_out;
3686 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3687 if (r)
f0d66275 3688 goto get_irqchip_out;
1fe779f8 3689 r = -EFAULT;
f0d66275
DH		 3690 if (copy_to_user(argp, chip, sizeof *chip))
3691 goto get_irqchip_out;
1fe779f8 3692 r = 0;
f0d66275
DH		 3693 get_irqchip_out:
3694 kfree(chip);
1fe779f8
CO		 3695 break;
3696 }
3697 case KVM_SET_IRQCHIP: {
3698 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3699 struct kvm_irqchip *chip;
1fe779f8 3700
ff5c2c03
SL		 3701 chip = memdup_user(argp, sizeof(*chip));
3702 if (IS_ERR(chip)) {
3703 r = PTR_ERR(chip);
1fe779f8 3704 goto out;
ff5c2c03
SL		 3705 }
3706
1fe779f8
CO		 3707 r = -ENXIO;
3708 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3709 goto set_irqchip_out;
3710 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3711 if (r)
f0d66275 3712 goto set_irqchip_out;
1fe779f8 3713 r = 0;
f0d66275
DH		 3714 set_irqchip_out:
3715 kfree(chip);
1fe779f8
CO		 3716 break;
3717 }
e0f63cb9 3718 case KVM_GET_PIT: {
e0f63cb9 3719 r = -EFAULT;
f0d66275 3720 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3721 goto out;
3722 r = -ENXIO;
3723 if (!kvm->arch.vpit)
3724 goto out;
f0d66275 3725 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3726 if (r)
3727 goto out;
3728 r = -EFAULT;
f0d66275 3729 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3730 goto out;
3731 r = 0;
3732 break;
3733 }
3734 case KVM_SET_PIT: {
e0f63cb9 3735 r = -EFAULT;
f0d66275 3736 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3737 goto out;
3738 r = -ENXIO;
3739 if (!kvm->arch.vpit)
3740 goto out;
f0d66275 3741 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3742 break;
3743 }
e9f42757
BK		 3744 case KVM_GET_PIT2: {
3745 r = -ENXIO;
3746 if (!kvm->arch.vpit)
3747 goto out;
3748 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3749 if (r)
3750 goto out;
3751 r = -EFAULT;
3752 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3753 goto out;
3754 r = 0;
3755 break;
3756 }
3757 case KVM_SET_PIT2: {
3758 r = -EFAULT;
3759 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3760 goto out;
3761 r = -ENXIO;
3762 if (!kvm->arch.vpit)
3763 goto out;
3764 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3765 break;
3766 }
52d939a0
MT		 3767 case KVM_REINJECT_CONTROL: {
3768 struct kvm_reinject_control control;
3769 r = -EFAULT;
3770 if (copy_from_user(&control, argp, sizeof(control)))
3771 goto out;
3772 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3773 break;
3774 }
d71ba788
PB		 3775 case KVM_SET_BOOT_CPU_ID:
3776 r = 0;
3777 mutex_lock(&kvm->lock);
3778 if (atomic_read(&kvm->online_vcpus) != 0)
3779 r = -EBUSY;
3780 else
3781 kvm->arch.bsp_vcpu_id = arg;
3782 mutex_unlock(&kvm->lock);
3783 break;
ffde22ac
ES		 3784 case KVM_XEN_HVM_CONFIG: {
3785 r = -EFAULT;
3786 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3787 sizeof(struct kvm_xen_hvm_config)))
3788 goto out;
3789 r = -EINVAL;
3790 if (kvm->arch.xen_hvm_config.flags)
3791 goto out;
3792 r = 0;
3793 break;
3794 }
afbcf7ab 3795 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3796 struct kvm_clock_data user_ns;
3797 u64 now_ns;
3798 s64 delta;
3799
3800 r = -EFAULT;
3801 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3802 goto out;
3803
3804 r = -EINVAL;
3805 if (user_ns.flags)
3806 goto out;
3807
3808 r = 0;
395c6b0a 3809 local_irq_disable();
759379dd 3810 now_ns = get_kernel_ns();
afbcf7ab 3811 delta = user_ns.clock - now_ns;
395c6b0a 3812 local_irq_enable();
afbcf7ab 3813 kvm->arch.kvmclock_offset = delta;
2e762ff7 3814 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3815 break;
3816 }
3817 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3818 struct kvm_clock_data user_ns;
3819 u64 now_ns;
3820
395c6b0a 3821 local_irq_disable();
759379dd 3822 now_ns = get_kernel_ns();
afbcf7ab 3823 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3824 local_irq_enable();
afbcf7ab 3825 user_ns.flags = 0;
97e69aa6 3826 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3827
3828 r = -EFAULT;
3829 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3830 goto out;
3831 r = 0;
3832 break;
3833 }
90de4a18
NA		 3834 case KVM_ENABLE_CAP: {
3835 struct kvm_enable_cap cap;
afbcf7ab 3836
90de4a18
NA		 3837 r = -EFAULT;
3838 if (copy_from_user(&cap, argp, sizeof(cap)))
3839 goto out;
3840 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3841 break;
3842 }
1fe779f8 3843 default:
c274e03a 3844 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3845 }
3846out:
3847 return r;
3848}
3849
a16b043c 3850static void kvm_init_msr_list(void)
043405e1
CO		 3851{
3852 u32 dummy[2];
3853 unsigned i, j;
3854
62ef68bb 3855 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3856 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3857 continue;
93c4adc7
PB		 3858
3859 /*
3860 * Even MSRs that are valid in the host may not be exposed
3861 * to the guests in some cases. We could work around this
3862 * in VMX with the generic MSR save/load machinery, but it
3863 * is not really worthwhile since it will really only
3864 * happen with nested virtualization.
3865 */
3866 switch (msrs_to_save[i]) {
3867 case MSR_IA32_BNDCFGS:
3868 if (!kvm_x86_ops->mpx_supported())
3869 continue;
3870 break;
3871 default:
3872 break;
3873 }
3874
043405e1
CO		 3875 if (j < i)
3876 msrs_to_save[j] = msrs_to_save[i];
3877 j++;
3878 }
3879 num_msrs_to_save = j;
62ef68bb
PB		 3880
3881 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3882 switch (emulated_msrs[i]) {
6d396b55
PB		 3883 case MSR_IA32_SMBASE:
3884 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3885 continue;
3886 break;
62ef68bb
PB		 3887 default:
3888 break;
3889 }
3890
3891 if (j < i)
3892 emulated_msrs[j] = emulated_msrs[i];
3893 j++;
3894 }
3895 num_emulated_msrs = j;
043405e1
CO		 3896}
3897
bda9020e
MT		 3898static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3899 const void *v)
bbd9b64e 3900{
70252a10
AK		 3901 int handled = 0;
3902 int n;
3903
3904 do {
3905 n = min(len, 8);
3906 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3907 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3908 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3909 break;
3910 handled += n;
3911 addr += n;
3912 len -= n;
3913 v += n;
3914 } while (len);
bbd9b64e 3915
70252a10 3916 return handled;
bbd9b64e
CO		 3917}
3918
bda9020e 3919static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3920{
70252a10
AK		 3921 int handled = 0;
3922 int n;
3923
3924 do {
3925 n = min(len, 8);
3926 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3927 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3928 addr, n, v))
3929 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3930 break;
3931 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3932 handled += n;
3933 addr += n;
3934 len -= n;
3935 v += n;
3936 } while (len);
bbd9b64e 3937
70252a10 3938 return handled;
bbd9b64e
CO		 3939}
3940
2dafc6c2
GN		 3941static void kvm_set_segment(struct kvm_vcpu *vcpu,
3942 struct kvm_segment *var, int seg)
3943{
3944 kvm_x86_ops->set_segment(vcpu, var, seg);
3945}
3946
3947void kvm_get_segment(struct kvm_vcpu *vcpu,
3948 struct kvm_segment *var, int seg)
3949{
3950 kvm_x86_ops->get_segment(vcpu, var, seg);
3951}
3952
54987b7a
PB		 3953gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3954 struct x86_exception *exception)
02f59dc9
JR		 3955{
3956 gpa_t t_gpa;
02f59dc9
JR		 3957
3958 BUG_ON(!mmu_is_nested(vcpu));
3959
3960 /* NPT walks are always user-walks */
3961 access |= PFERR_USER_MASK;
54987b7a 3962 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3963
3964 return t_gpa;
3965}
3966
ab9ae313
AK		 3967gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3968 struct x86_exception *exception)
1871c602
GN		 3969{
3970 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3971 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3972}
3973
ab9ae313
AK		 3974 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3975 struct x86_exception *exception)
1871c602
GN		 3976{
3977 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3978 access |= PFERR_FETCH_MASK;
ab9ae313 3979 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3980}
3981
ab9ae313
AK		 3982gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3983 struct x86_exception *exception)
1871c602
GN		 3984{
3985 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3986 access |= PFERR_WRITE_MASK;
ab9ae313 3987 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3988}
3989
3990/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3991gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3992 struct x86_exception *exception)
1871c602 3993{
ab9ae313 3994 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3995}
3996
3997static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3998 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3999 struct x86_exception *exception)
bbd9b64e
CO		 4000{
4001 void *data = val;
10589a46 4002 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4003
4004 while (bytes) {
14dfe855 4005 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4006 exception);
bbd9b64e 4007 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4008 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4009 int ret;
4010
bcc55cba 4011 if (gpa == UNMAPPED_GVA)
ab9ae313 4012 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4013 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4014 offset, toread);
10589a46 4015 if (ret < 0) {
c3cd7ffa 4016 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4017 goto out;
4018 }
bbd9b64e 4019
77c2002e
IE		 4020 bytes -= toread;
4021 data += toread;
4022 addr += toread;
bbd9b64e 4023 }
10589a46 4024out:
10589a46 4025 return r;
bbd9b64e 4026}
77c2002e 4027
1871c602 4028/* used for instruction fetching */
0f65dd70
AK		 4029static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4030 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4031 struct x86_exception *exception)
1871c602 4032{
0f65dd70 4033 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4034 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4035 unsigned offset;
4036 int ret;
0f65dd70 4037
44583cba
PB		 4038 /* Inline kvm_read_guest_virt_helper for speed. */
4039 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4040 exception);
4041 if (unlikely(gpa == UNMAPPED_GVA))
4042 return X86EMUL_PROPAGATE_FAULT;
4043
4044 offset = addr & (PAGE_SIZE-1);
4045 if (WARN_ON(offset + bytes > PAGE_SIZE))
4046 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4047 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4048 offset, bytes);
44583cba
PB		 4049 if (unlikely(ret < 0))
4050 return X86EMUL_IO_NEEDED;
4051
4052 return X86EMUL_CONTINUE;
1871c602
GN		 4053}
4054
064aea77 4055int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4056 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4057 struct x86_exception *exception)
1871c602 4058{
0f65dd70 4059 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4060 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4061
1871c602 4062 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4063 exception);
1871c602 4064}
064aea77 4065EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4066
0f65dd70
AK		 4067static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4068 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4069 struct x86_exception *exception)
1871c602 4070{
0f65dd70 4071 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4072 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4073}
4074
6a4d7550 4075int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4076 gva_t addr, void *val,
2dafc6c2 4077 unsigned int bytes,
bcc55cba 4078 struct x86_exception *exception)
77c2002e 4079{
0f65dd70 4080 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4081 void *data = val;
4082 int r = X86EMUL_CONTINUE;
4083
4084 while (bytes) {
14dfe855
JR		 4085 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4086 PFERR_WRITE_MASK,
ab9ae313 4087 exception);
77c2002e
IE		 4088 unsigned offset = addr & (PAGE_SIZE-1);
4089 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4090 int ret;
4091
bcc55cba 4092 if (gpa == UNMAPPED_GVA)
ab9ae313 4093 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4094 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4095 if (ret < 0) {
c3cd7ffa 4096 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4097 goto out;
4098 }
4099
4100 bytes -= towrite;
4101 data += towrite;
4102 addr += towrite;
4103 }
4104out:
4105 return r;
4106}
6a4d7550 4107EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4108
af7cc7d1
XG		 4109static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4110 gpa_t *gpa, struct x86_exception *exception,
4111 bool write)
4112{
97d64b78
AK		 4113 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4114 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4115
97d64b78 4116 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4117 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4118 vcpu->arch.access, access)) {
bebb106a
XG		 4119 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4120 (gva & (PAGE_SIZE - 1));
4f022648 4121 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4122 return 1;
4123 }
4124
af7cc7d1
XG		 4125 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4126
4127 if (*gpa == UNMAPPED_GVA)
4128 return -1;
4129
4130 /* For APIC access vmexit */
4131 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4132 return 1;
4133
4f022648
XG		 4134 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4135 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4136 return 1;
4f022648 4137 }
bebb106a 4138
af7cc7d1
XG		 4139 return 0;
4140}
4141
3200f405 4142int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4143 const void *val, int bytes)
bbd9b64e
CO		 4144{
4145 int ret;
4146
54bf36aa 4147 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4148 if (ret < 0)
bbd9b64e 4149 return 0;
f57f2ef5 4150 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4151 return 1;
4152}
4153
77d197b2
XG		 4154struct read_write_emulator_ops {
4155 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4156 int bytes);
4157 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4158 void *val, int bytes);
4159 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4160 int bytes, void *val);
4161 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4162 void *val, int bytes);
4163 bool write;
4164};
4165
4166static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4167{
4168 if (vcpu->mmio_read_completed) {
77d197b2 4169 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4170 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4171 vcpu->mmio_read_completed = 0;
4172 return 1;
4173 }
4174
4175 return 0;
4176}
4177
4178static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4179 void *val, int bytes)
4180{
54bf36aa 4181 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4182}
4183
4184static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4185 void *val, int bytes)
4186{
4187 return emulator_write_phys(vcpu, gpa, val, bytes);
4188}
4189
4190static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4191{
4192 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4193 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4194}
4195
4196static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4197 void *val, int bytes)
4198{
4199 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4200 return X86EMUL_IO_NEEDED;
4201}
4202
4203static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4204 void *val, int bytes)
4205{
f78146b0
AK		 4206 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4207
87da7e66 4208 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4209 return X86EMUL_CONTINUE;
4210}
4211
0fbe9b0b 4212static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4213 .read_write_prepare = read_prepare,
4214 .read_write_emulate = read_emulate,
4215 .read_write_mmio = vcpu_mmio_read,
4216 .read_write_exit_mmio = read_exit_mmio,
4217};
4218
0fbe9b0b 4219static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4220 .read_write_emulate = write_emulate,
4221 .read_write_mmio = write_mmio,
4222 .read_write_exit_mmio = write_exit_mmio,
4223 .write = true,
4224};
4225
22388a3c
XG		 4226static int emulator_read_write_onepage(unsigned long addr, void *val,
4227 unsigned int bytes,
4228 struct x86_exception *exception,
4229 struct kvm_vcpu *vcpu,
0fbe9b0b 4230 const struct read_write_emulator_ops *ops)
bbd9b64e 4231{
af7cc7d1
XG		 4232 gpa_t gpa;
4233 int handled, ret;
22388a3c 4234 bool write = ops->write;
f78146b0 4235 struct kvm_mmio_fragment *frag;
10589a46 4236
22388a3c 4237 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4238
af7cc7d1 4239 if (ret < 0)
bbd9b64e 4240 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4241
4242 /* For APIC access vmexit */
af7cc7d1 4243 if (ret)
bbd9b64e
CO		 4244 goto mmio;
4245
22388a3c 4246 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4247 return X86EMUL_CONTINUE;
4248
4249mmio:
4250 /*
4251 * Is this MMIO handled locally?
4252 */
22388a3c 4253 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4254 if (handled == bytes)
bbd9b64e 4255 return X86EMUL_CONTINUE;
bbd9b64e 4256
70252a10
AK		 4257 gpa += handled;
4258 bytes -= handled;
4259 val += handled;
4260
87da7e66
XG		 4261 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4262 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4263 frag->gpa = gpa;
4264 frag->data = val;
4265 frag->len = bytes;
f78146b0 4266 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4267}
4268
52eb5a6d
XL		 4269static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4270 unsigned long addr,
22388a3c
XG		 4271 void *val, unsigned int bytes,
4272 struct x86_exception *exception,
0fbe9b0b 4273 const struct read_write_emulator_ops *ops)
bbd9b64e 4274{
0f65dd70 4275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4276 gpa_t gpa;
4277 int rc;
4278
4279 if (ops->read_write_prepare &&
4280 ops->read_write_prepare(vcpu, val, bytes))
4281 return X86EMUL_CONTINUE;
4282
4283 vcpu->mmio_nr_fragments = 0;
0f65dd70 4284
bbd9b64e
CO		 4285 /* Crossing a page boundary? */
4286 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4287 int now;
bbd9b64e
CO		 4288
4289 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4290 rc = emulator_read_write_onepage(addr, val, now, exception,
4291 vcpu, ops);
4292
bbd9b64e
CO		 4293 if (rc != X86EMUL_CONTINUE)
4294 return rc;
4295 addr += now;
bac15531
NA		 4296 if (ctxt->mode != X86EMUL_MODE_PROT64)
4297 addr = (u32)addr;
bbd9b64e
CO		 4298 val += now;
4299 bytes -= now;
4300 }
22388a3c 4301
f78146b0
AK		 4302 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4303 vcpu, ops);
4304 if (rc != X86EMUL_CONTINUE)
4305 return rc;
4306
4307 if (!vcpu->mmio_nr_fragments)
4308 return rc;
4309
4310 gpa = vcpu->mmio_fragments[0].gpa;
4311
4312 vcpu->mmio_needed = 1;
4313 vcpu->mmio_cur_fragment = 0;
4314
87da7e66 4315 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4316 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4317 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4318 vcpu->run->mmio.phys_addr = gpa;
4319
4320 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4321}
4322
4323static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4324 unsigned long addr,
4325 void *val,
4326 unsigned int bytes,
4327 struct x86_exception *exception)
4328{
4329 return emulator_read_write(ctxt, addr, val, bytes,
4330 exception, &read_emultor);
4331}
4332
52eb5a6d 4333static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4334 unsigned long addr,
4335 const void *val,
4336 unsigned int bytes,
4337 struct x86_exception *exception)
4338{
4339 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4340 exception, &write_emultor);
bbd9b64e 4341}
bbd9b64e 4342
daea3e73
AK		 4343#define CMPXCHG_TYPE(t, ptr, old, new) \
4344 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4345
4346#ifdef CONFIG_X86_64
4347# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4348#else
4349# define CMPXCHG64(ptr, old, new) \
9749a6c0 4350 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4351#endif
4352
0f65dd70
AK		 4353static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4354 unsigned long addr,
bbd9b64e
CO		 4355 const void *old,
4356 const void *new,
4357 unsigned int bytes,
0f65dd70 4358 struct x86_exception *exception)
bbd9b64e 4359{
0f65dd70 4360 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4361 gpa_t gpa;
4362 struct page *page;
4363 char *kaddr;
4364 bool exchanged;
2bacc55c 4365
daea3e73
AK		 4366 /* guests cmpxchg8b have to be emulated atomically */
4367 if (bytes > 8 || (bytes & (bytes - 1)))
4368 goto emul_write;
10589a46 4369
daea3e73 4370 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4371
daea3e73
AK		 4372 if (gpa == UNMAPPED_GVA ||
4373 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4374 goto emul_write;
2bacc55c 4375
daea3e73
AK		 4376 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4377 goto emul_write;
72dc67a6 4378
54bf36aa 4379 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4380 if (is_error_page(page))
c19b8bd6 4381 goto emul_write;
72dc67a6 4382
8fd75e12 4383 kaddr = kmap_atomic(page);
daea3e73
AK		 4384 kaddr += offset_in_page(gpa);
4385 switch (bytes) {
4386 case 1:
4387 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4388 break;
4389 case 2:
4390 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4391 break;
4392 case 4:
4393 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4394 break;
4395 case 8:
4396 exchanged = CMPXCHG64(kaddr, old, new);
4397 break;
4398 default:
4399 BUG();
2bacc55c 4400 }
8fd75e12 4401 kunmap_atomic(kaddr);
daea3e73
AK		 4402 kvm_release_page_dirty(page);
4403
4404 if (!exchanged)
4405 return X86EMUL_CMPXCHG_FAILED;
4406
54bf36aa 4407 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4408 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4409
4410 return X86EMUL_CONTINUE;
4a5f48f6 4411
3200f405 4412emul_write:
daea3e73 4413 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4414
0f65dd70 4415 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4416}
4417
cf8f70bf
GN		 4418static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4419{
4420 /* TODO: String I/O for in kernel device */
4421 int r;
4422
4423 if (vcpu->arch.pio.in)
e32edf4f 4424 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4425 vcpu->arch.pio.size, pd);
4426 else
e32edf4f 4427 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4428 vcpu->arch.pio.port, vcpu->arch.pio.size,
4429 pd);
4430 return r;
4431}
4432
6f6fbe98
XG		 4433static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4434 unsigned short port, void *val,
4435 unsigned int count, bool in)
cf8f70bf 4436{
cf8f70bf 4437 vcpu->arch.pio.port = port;
6f6fbe98 4438 vcpu->arch.pio.in = in;
7972995b 4439 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4440 vcpu->arch.pio.size = size;
4441
4442 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4443 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4444 return 1;
4445 }
4446
4447 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4448 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4449 vcpu->run->io.size = size;
4450 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4451 vcpu->run->io.count = count;
4452 vcpu->run->io.port = port;
4453
4454 return 0;
4455}
4456
6f6fbe98
XG		 4457static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4458 int size, unsigned short port, void *val,
4459 unsigned int count)
cf8f70bf 4460{
ca1d4a9e 4461 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4462 int ret;
ca1d4a9e 4463
6f6fbe98
XG		 4464 if (vcpu->arch.pio.count)
4465 goto data_avail;
cf8f70bf 4466
6f6fbe98
XG		 4467 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4468 if (ret) {
4469data_avail:
4470 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4471 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4472 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4473 return 1;
4474 }
4475
cf8f70bf
GN		 4476 return 0;
4477}
4478
6f6fbe98
XG		 4479static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4480 int size, unsigned short port,
4481 const void *val, unsigned int count)
4482{
4483 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4484
4485 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4486 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4487 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4488}
4489
bbd9b64e
CO		 4490static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4491{
4492 return kvm_x86_ops->get_segment_base(vcpu, seg);
4493}
4494
3cb16fe7 4495static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4496{
3cb16fe7 4497 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4498}
4499
5cb56059 4500int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4501{
4502 if (!need_emulate_wbinvd(vcpu))
4503 return X86EMUL_CONTINUE;
4504
4505 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4506 int cpu = get_cpu();
4507
4508 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4509 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4510 wbinvd_ipi, NULL, 1);
2eec7343 4511 put_cpu();
f5f48ee1 4512 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4513 } else
4514 wbinvd();
f5f48ee1
SY		 4515 return X86EMUL_CONTINUE;
4516}
5cb56059
JS		 4517
4518int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4519{
4520 kvm_x86_ops->skip_emulated_instruction(vcpu);
4521 return kvm_emulate_wbinvd_noskip(vcpu);
4522}
f5f48ee1
SY		 4523EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4524
5cb56059
JS		 4525
4526
bcaf5cc5
AK		 4527static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4528{
5cb56059 4529 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4530}
4531
52eb5a6d
XL		 4532static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4533 unsigned long *dest)
bbd9b64e 4534{
16f8a6f9 4535 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4536}
4537
52eb5a6d
XL		 4538static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4539 unsigned long value)
bbd9b64e 4540{
338dbc97 4541
717746e3 4542 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4543}
4544
52a46617 4545static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4546{
52a46617 4547 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4548}
4549
717746e3 4550static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4551{
717746e3 4552 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4553 unsigned long value;
4554
4555 switch (cr) {
4556 case 0:
4557 value = kvm_read_cr0(vcpu);
4558 break;
4559 case 2:
4560 value = vcpu->arch.cr2;
4561 break;
4562 case 3:
9f8fe504 4563 value = kvm_read_cr3(vcpu);
52a46617
GN		 4564 break;
4565 case 4:
4566 value = kvm_read_cr4(vcpu);
4567 break;
4568 case 8:
4569 value = kvm_get_cr8(vcpu);
4570 break;
4571 default:
a737f256 4572 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4573 return 0;
4574 }
4575
4576 return value;
4577}
4578
717746e3 4579static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4580{
717746e3 4581 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4582 int res = 0;
4583
52a46617
GN		 4584 switch (cr) {
4585 case 0:
49a9b07e 4586 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4587 break;
4588 case 2:
4589 vcpu->arch.cr2 = val;
4590 break;
4591 case 3:
2390218b 4592 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4593 break;
4594 case 4:
a83b29c6 4595 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4596 break;
4597 case 8:
eea1cff9 4598 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4599 break;
4600 default:
a737f256 4601 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4602 res = -1;
52a46617 4603 }
0f12244f
GN		 4604
4605 return res;
52a46617
GN		 4606}
4607
717746e3 4608static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4609{
717746e3 4610 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4611}
4612
4bff1e86 4613static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4614{
4bff1e86 4615 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4616}
4617
4bff1e86 4618static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4619{
4bff1e86 4620 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4621}
4622
1ac9d0cf
AK		 4623static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4624{
4625 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4626}
4627
4628static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4629{
4630 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4631}
4632
4bff1e86
AK		 4633static unsigned long emulator_get_cached_segment_base(
4634 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4635{
4bff1e86 4636 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4637}
4638
1aa36616
AK		 4639static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4640 struct desc_struct *desc, u32 *base3,
4641 int seg)
2dafc6c2
GN		 4642{
4643 struct kvm_segment var;
4644
4bff1e86 4645 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4646 *selector = var.selector;
2dafc6c2 4647
378a8b09
GN		 4648 if (var.unusable) {
4649 memset(desc, 0, sizeof(*desc));
2dafc6c2 4650 return false;
378a8b09 4651 }
2dafc6c2
GN		 4652
4653 if (var.g)
4654 var.limit >>= 12;
4655 set_desc_limit(desc, var.limit);
4656 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4657#ifdef CONFIG_X86_64
4658 if (base3)
4659 *base3 = var.base >> 32;
4660#endif
2dafc6c2
GN		 4661 desc->type = var.type;
4662 desc->s = var.s;
4663 desc->dpl = var.dpl;
4664 desc->p = var.present;
4665 desc->avl = var.avl;
4666 desc->l = var.l;
4667 desc->d = var.db;
4668 desc->g = var.g;
4669
4670 return true;
4671}
4672
1aa36616
AK		 4673static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4674 struct desc_struct *desc, u32 base3,
4675 int seg)
2dafc6c2 4676{
4bff1e86 4677 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4678 struct kvm_segment var;
4679
1aa36616 4680 var.selector = selector;
2dafc6c2 4681 var.base = get_desc_base(desc);
5601d05b
GN		 4682#ifdef CONFIG_X86_64
4683 var.base |= ((u64)base3) << 32;
4684#endif
2dafc6c2
GN		 4685 var.limit = get_desc_limit(desc);
4686 if (desc->g)
4687 var.limit = (var.limit << 12) | 0xfff;
4688 var.type = desc->type;
2dafc6c2
GN		 4689 var.dpl = desc->dpl;
4690 var.db = desc->d;
4691 var.s = desc->s;
4692 var.l = desc->l;
4693 var.g = desc->g;
4694 var.avl = desc->avl;
4695 var.present = desc->p;
4696 var.unusable = !var.present;
4697 var.padding = 0;
4698
4699 kvm_set_segment(vcpu, &var, seg);
4700 return;
4701}
4702
717746e3
AK		 4703static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4704 u32 msr_index, u64 *pdata)
4705{
609e36d3
PB		 4706 struct msr_data msr;
4707 int r;
4708
4709 msr.index = msr_index;
4710 msr.host_initiated = false;
4711 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4712 if (r)
4713 return r;
4714
4715 *pdata = msr.data;
4716 return 0;
717746e3
AK		 4717}
4718
4719static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4720 u32 msr_index, u64 data)
4721{
8fe8ab46
WA		 4722 struct msr_data msr;
4723
4724 msr.data = data;
4725 msr.index = msr_index;
4726 msr.host_initiated = false;
4727 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4728}
4729
64d60670
PB		 4730static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4731{
4732 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4733
4734 return vcpu->arch.smbase;
4735}
4736
4737static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4738{
4739 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4740
4741 vcpu->arch.smbase = smbase;
4742}
4743
67f4d428
NA		 4744static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4745 u32 pmc)
4746{
c6702c9d 4747 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4748}
4749
222d21aa
AK		 4750static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4751 u32 pmc, u64 *pdata)
4752{
c6702c9d 4753 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4754}
4755
6c3287f7
AK		 4756static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4757{
4758 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4759}
4760
5037f6f3
AK		 4761static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4762{
4763 preempt_disable();
5197b808 4764 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4765 /*
4766 * CR0.TS may reference the host fpu state, not the guest fpu state,
4767 * so it may be clear at this point.
4768 */
4769 clts();
4770}
4771
4772static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4773{
4774 preempt_enable();
4775}
4776
2953538e 4777static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4778 struct x86_instruction_info *info,
c4f035c6
AK		 4779 enum x86_intercept_stage stage)
4780{
2953538e 4781 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4782}
4783
0017f93a 4784static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4785 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4786{
0017f93a 4787 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4788}
4789
dd856efa
AK		 4790static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4791{
4792 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4793}
4794
4795static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4796{
4797 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4798}
4799
801806d9
NA		 4800static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4801{
4802 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4803}
4804
0225fb50 4805static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4806 .read_gpr = emulator_read_gpr,
4807 .write_gpr = emulator_write_gpr,
1871c602 4808 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4809 .write_std = kvm_write_guest_virt_system,
1871c602 4810 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4811 .read_emulated = emulator_read_emulated,
4812 .write_emulated = emulator_write_emulated,
4813 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4814 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4815 .pio_in_emulated = emulator_pio_in_emulated,
4816 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4817 .get_segment = emulator_get_segment,
4818 .set_segment = emulator_set_segment,
5951c442 4819 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4820 .get_gdt = emulator_get_gdt,
160ce1f1 4821 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4822 .set_gdt = emulator_set_gdt,
4823 .set_idt = emulator_set_idt,
52a46617
GN		 4824 .get_cr = emulator_get_cr,
4825 .set_cr = emulator_set_cr,
9c537244 4826 .cpl = emulator_get_cpl,
35aa5375
GN		 4827 .get_dr = emulator_get_dr,
4828 .set_dr = emulator_set_dr,
64d60670
PB		 4829 .get_smbase = emulator_get_smbase,
4830 .set_smbase = emulator_set_smbase,
717746e3
AK		 4831 .set_msr = emulator_set_msr,
4832 .get_msr = emulator_get_msr,
67f4d428 4833 .check_pmc = emulator_check_pmc,
222d21aa 4834 .read_pmc = emulator_read_pmc,
6c3287f7 4835 .halt = emulator_halt,
bcaf5cc5 4836 .wbinvd = emulator_wbinvd,
d6aa1000 4837 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4838 .get_fpu = emulator_get_fpu,
4839 .put_fpu = emulator_put_fpu,
c4f035c6 4840 .intercept = emulator_intercept,
bdb42f5a 4841 .get_cpuid = emulator_get_cpuid,
801806d9 4842 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4843};
4844
95cb2295
GN		 4845static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4846{
37ccdcbe 4847 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4848 /*
4849 * an sti; sti; sequence only disable interrupts for the first
4850 * instruction. So, if the last instruction, be it emulated or
4851 * not, left the system with the INT_STI flag enabled, it
4852 * means that the last instruction is an sti. We should not
4853 * leave the flag on in this case. The same goes for mov ss
4854 */
37ccdcbe
PB		 4855 if (int_shadow & mask)
4856 mask = 0;
6addfc42 4857 if (unlikely(int_shadow || mask)) {
95cb2295 4858 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4859 if (!mask)
4860 kvm_make_request(KVM_REQ_EVENT, vcpu);
4861 }
95cb2295
GN		 4862}
4863
ef54bcfe 4864static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4865{
4866 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4867 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4868 return kvm_propagate_fault(vcpu, &ctxt->exception);
4869
4870 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4871 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4872 ctxt->exception.error_code);
54b8486f 4873 else
da9cb575 4874 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4875 return false;
54b8486f
GN		 4876}
4877
8ec4722d
MG		 4878static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4879{
adf52235 4880 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4881 int cs_db, cs_l;
4882
8ec4722d
MG		 4883 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4884
adf52235
TY		 4885 ctxt->eflags = kvm_get_rflags(vcpu);
4886 ctxt->eip = kvm_rip_read(vcpu);
4887 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4888 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4889 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4890 cs_db ? X86EMUL_MODE_PROT32 :
4891 X86EMUL_MODE_PROT16;
a584539b 4892 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4893 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4894 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4895 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4896
dd856efa 4897 init_decode_cache(ctxt);
7ae441ea 4898 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4899}
4900
71f9833b 4901int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4902{
9d74191a 4903 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4904 int ret;
4905
4906 init_emulate_ctxt(vcpu);
4907
9dac77fa
AK		 4908 ctxt->op_bytes = 2;
4909 ctxt->ad_bytes = 2;
4910 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4911 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4912
4913 if (ret != X86EMUL_CONTINUE)
4914 return EMULATE_FAIL;
4915
9dac77fa 4916 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4917 kvm_rip_write(vcpu, ctxt->eip);
4918 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4919
4920 if (irq == NMI_VECTOR)
7460fb4a 4921 vcpu->arch.nmi_pending = 0;
63995653
MG		 4922 else
4923 vcpu->arch.interrupt.pending = false;
4924
4925 return EMULATE_DONE;
4926}
4927EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4928
6d77dbfc
GN		 4929static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4930{
fc3a9157
JR		 4931 int r = EMULATE_DONE;
4932
6d77dbfc
GN		 4933 ++vcpu->stat.insn_emulation_fail;
4934 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4935 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4936 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4937 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4938 vcpu->run->internal.ndata = 0;
4939 r = EMULATE_FAIL;
4940 }
6d77dbfc 4941 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4942
4943 return r;
6d77dbfc
GN		 4944}
4945
93c05d3e 4946static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4947 bool write_fault_to_shadow_pgtable,
4948 int emulation_type)
a6f177ef 4949{
95b3cf69 4950 gpa_t gpa = cr2;
8e3d9d06 4951 pfn_t pfn;
a6f177ef 4952
991eebf9
GN		 4953 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4954 return false;
4955
95b3cf69
XG		 4956 if (!vcpu->arch.mmu.direct_map) {
4957 /*
4958 * Write permission should be allowed since only
4959 * write access need to be emulated.
4960 */
4961 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4962
95b3cf69
XG		 4963 /*
4964 * If the mapping is invalid in guest, let cpu retry
4965 * it to generate fault.
4966 */
4967 if (gpa == UNMAPPED_GVA)
4968 return true;
4969 }
a6f177ef 4970
8e3d9d06
XG		 4971 /*
4972 * Do not retry the unhandleable instruction if it faults on the
4973 * readonly host memory, otherwise it will goto a infinite loop:
4974 * retry instruction -> write #PF -> emulation fail -> retry
4975 * instruction -> ...
4976 */
4977 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4978
4979 /*
4980 * If the instruction failed on the error pfn, it can not be fixed,
4981 * report the error to userspace.
4982 */
4983 if (is_error_noslot_pfn(pfn))
4984 return false;
4985
4986 kvm_release_pfn_clean(pfn);
4987
4988 /* The instructions are well-emulated on direct mmu. */
4989 if (vcpu->arch.mmu.direct_map) {
4990 unsigned int indirect_shadow_pages;
4991
4992 spin_lock(&vcpu->kvm->mmu_lock);
4993 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4994 spin_unlock(&vcpu->kvm->mmu_lock);
4995
4996 if (indirect_shadow_pages)
4997 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4998
a6f177ef 4999 return true;
8e3d9d06 5000 }
a6f177ef 5001
95b3cf69
XG		 5002 /*
5003 * if emulation was due to access to shadowed page table
5004 * and it failed try to unshadow page and re-enter the
5005 * guest to let CPU execute the instruction.
5006 */
5007 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5008
5009 /*
5010 * If the access faults on its page table, it can not
5011 * be fixed by unprotecting shadow page and it should
5012 * be reported to userspace.
5013 */
5014 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5015}
5016
1cb3f3ae
XG		 5017static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5018 unsigned long cr2, int emulation_type)
5019{
5020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5021 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5022
5023 last_retry_eip = vcpu->arch.last_retry_eip;
5024 last_retry_addr = vcpu->arch.last_retry_addr;
5025
5026 /*
5027 * If the emulation is caused by #PF and it is non-page_table
5028 * writing instruction, it means the VM-EXIT is caused by shadow
5029 * page protected, we can zap the shadow page and retry this
5030 * instruction directly.
5031 *
5032 * Note: if the guest uses a non-page-table modifying instruction
5033 * on the PDE that points to the instruction, then we will unmap
5034 * the instruction and go to an infinite loop. So, we cache the
5035 * last retried eip and the last fault address, if we meet the eip
5036 * and the address again, we can break out of the potential infinite
5037 * loop.
5038 */
5039 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5040
5041 if (!(emulation_type & EMULTYPE_RETRY))
5042 return false;
5043
5044 if (x86_page_table_writing_insn(ctxt))
5045 return false;
5046
5047 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5048 return false;
5049
5050 vcpu->arch.last_retry_eip = ctxt->eip;
5051 vcpu->arch.last_retry_addr = cr2;
5052
5053 if (!vcpu->arch.mmu.direct_map)
5054 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5055
22368028 5056 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5057
5058 return true;
5059}
5060
716d51ab
GN		 5061static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5062static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5063
64d60670 5064static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5065{
64d60670 5066 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5067 /* This is a good place to trace that we are exiting SMM. */
5068 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5069
64d60670
PB		 5070 if (unlikely(vcpu->arch.smi_pending)) {
5071 kvm_make_request(KVM_REQ_SMI, vcpu);
5072 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5073 } else {
5074 /* Process a latched INIT, if any. */
5075 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5076 }
5077 }
699023e2
PB		 5078
5079 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5080}
5081
5082static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5083{
5084 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5085
a584539b 5086 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5087
5088 if (changed & HF_SMM_MASK)
5089 kvm_smm_changed(vcpu);
a584539b
PB		 5090}
5091
4a1e10d5
PB		 5092static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5093 unsigned long *db)
5094{
5095 u32 dr6 = 0;
5096 int i;
5097 u32 enable, rwlen;
5098
5099 enable = dr7;
5100 rwlen = dr7 >> 16;
5101 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5102 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5103 dr6 |= (1 << i);
5104 return dr6;
5105}
5106
6addfc42 5107static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5108{
5109 struct kvm_run *kvm_run = vcpu->run;
5110
5111 /*
6addfc42
PB		 5112 * rflags is the old, "raw" value of the flags. The new value has
5113 * not been saved yet.
663f4c61
PB		 5114 *
5115 * This is correct even for TF set by the guest, because "the
5116 * processor will not generate this exception after the instruction
5117 * that sets the TF flag".
5118 */
663f4c61
PB		 5119 if (unlikely(rflags & X86_EFLAGS_TF)) {
5120 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5121 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5122 DR6_RTM;
663f4c61
PB		 5123 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5124 kvm_run->debug.arch.exception = DB_VECTOR;
5125 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5126 *r = EMULATE_USER_EXIT;
5127 } else {
5128 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5129 /*
5130 * "Certain debug exceptions may clear bit 0-3. The
5131 * remaining contents of the DR6 register are never
5132 * cleared by the processor".
5133 */
5134 vcpu->arch.dr6 &= ~15;
6f43ed01 5135 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5136 kvm_queue_exception(vcpu, DB_VECTOR);
5137 }
5138 }
5139}
5140
4a1e10d5
PB		 5141static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5142{
4a1e10d5
PB		 5143 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5144 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5145 struct kvm_run *kvm_run = vcpu->run;
5146 unsigned long eip = kvm_get_linear_rip(vcpu);
5147 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5148 vcpu->arch.guest_debug_dr7,
5149 vcpu->arch.eff_db);
5150
5151 if (dr6 != 0) {
6f43ed01 5152 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5153 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5154 kvm_run->debug.arch.exception = DB_VECTOR;
5155 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5156 *r = EMULATE_USER_EXIT;
5157 return true;
5158 }
5159 }
5160
4161a569
NA		 5161 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5162 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5163 unsigned long eip = kvm_get_linear_rip(vcpu);
5164 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5165 vcpu->arch.dr7,
5166 vcpu->arch.db);
5167
5168 if (dr6 != 0) {
5169 vcpu->arch.dr6 &= ~15;
6f43ed01 5170 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5171 kvm_queue_exception(vcpu, DB_VECTOR);
5172 *r = EMULATE_DONE;
5173 return true;
5174 }
5175 }
5176
5177 return false;
5178}
5179
51d8b661
AP		 5180int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5181 unsigned long cr2,
dc25e89e
AP		 5182 int emulation_type,
5183 void *insn,
5184 int insn_len)
bbd9b64e 5185{
95cb2295 5186 int r;
9d74191a 5187 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5188 bool writeback = true;
93c05d3e 5189 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5190
93c05d3e
XG		 5191 /*
5192 * Clear write_fault_to_shadow_pgtable here to ensure it is
5193 * never reused.
5194 */
5195 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5196 kvm_clear_exception_queue(vcpu);
8d7d8102 5197
571008da 5198 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5199 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5200
5201 /*
5202 * We will reenter on the same instruction since
5203 * we do not set complete_userspace_io. This does not
5204 * handle watchpoints yet, those would be handled in
5205 * the emulate_ops.
5206 */
5207 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5208 return r;
5209
9d74191a
TY		 5210 ctxt->interruptibility = 0;
5211 ctxt->have_exception = false;
e0ad0b47 5212 ctxt->exception.vector = -1;
9d74191a 5213 ctxt->perm_ok = false;
bbd9b64e 5214
b51e974f 5215 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5216
9d74191a 5217 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5218
e46479f8 5219 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5220 ++vcpu->stat.insn_emulation;
1d2887e2 5221 if (r != EMULATION_OK) {
4005996e
AK		 5222 if (emulation_type & EMULTYPE_TRAP_UD)
5223 return EMULATE_FAIL;
991eebf9
GN		 5224 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5225 emulation_type))
bbd9b64e 5226 return EMULATE_DONE;
6d77dbfc
GN		 5227 if (emulation_type & EMULTYPE_SKIP)
5228 return EMULATE_FAIL;
5229 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5230 }
5231 }
5232
ba8afb6b 5233 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5234 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5235 if (ctxt->eflags & X86_EFLAGS_RF)
5236 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5237 return EMULATE_DONE;
5238 }
5239
1cb3f3ae
XG		 5240 if (retry_instruction(ctxt, cr2, emulation_type))
5241 return EMULATE_DONE;
5242
7ae441ea 5243 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5244 changes registers values during IO operation */
7ae441ea
GN		 5245 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5246 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5247 emulator_invalidate_register_cache(ctxt);
7ae441ea 5248 }
4d2179e1 5249
5cd21917 5250restart:
9d74191a 5251 r = x86_emulate_insn(ctxt);
bbd9b64e 5252
775fde86
JR		 5253 if (r == EMULATION_INTERCEPTED)
5254 return EMULATE_DONE;
5255
d2ddd1c4 5256 if (r == EMULATION_FAILED) {
991eebf9
GN		 5257 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5258 emulation_type))
c3cd7ffa
GN		 5259 return EMULATE_DONE;
5260
6d77dbfc 5261 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5262 }
5263
9d74191a 5264 if (ctxt->have_exception) {
d2ddd1c4 5265 r = EMULATE_DONE;
ef54bcfe
PB		 5266 if (inject_emulated_exception(vcpu))
5267 return r;
d2ddd1c4 5268 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5269 if (!vcpu->arch.pio.in) {
5270 /* FIXME: return into emulator if single-stepping. */
3457e419 5271 vcpu->arch.pio.count = 0;
0912c977 5272 } else {
7ae441ea 5273 writeback = false;
716d51ab
GN		 5274 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5275 }
ac0a48c3 5276 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5277 } else if (vcpu->mmio_needed) {
5278 if (!vcpu->mmio_is_write)
5279 writeback = false;
ac0a48c3 5280 r = EMULATE_USER_EXIT;
716d51ab 5281 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5282 } else if (r == EMULATION_RESTART)
5cd21917 5283 goto restart;
d2ddd1c4
GN		 5284 else
5285 r = EMULATE_DONE;
f850e2e6 5286
7ae441ea 5287 if (writeback) {
6addfc42 5288 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5289 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5290 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5291 if (vcpu->arch.hflags != ctxt->emul_flags)
5292 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5293 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5294 if (r == EMULATE_DONE)
6addfc42 5295 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5296 if (!ctxt->have_exception ||
5297 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5298 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5299
5300 /*
5301 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5302 * do nothing, and it will be requested again as soon as
5303 * the shadow expires. But we still need to check here,
5304 * because POPF has no interrupt shadow.
5305 */
5306 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5307 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5308 } else
5309 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5310
5311 return r;
de7d789a 5312}
51d8b661 5313EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5314
cf8f70bf 5315int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5316{
cf8f70bf 5317 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5318 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5319 size, port, &val, 1);
cf8f70bf 5320 /* do not return to emulator after return from userspace */
7972995b 5321 vcpu->arch.pio.count = 0;
de7d789a
CO		 5322 return ret;
5323}
cf8f70bf 5324EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5325
8cfdc000
ZA		 5326static void tsc_bad(void *info)
5327{
0a3aee0d 5328 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5329}
5330
5331static void tsc_khz_changed(void *data)
c8076604 5332{
8cfdc000
ZA		 5333 struct cpufreq_freqs *freq = data;
5334 unsigned long khz = 0;
5335
5336 if (data)
5337 khz = freq->new;
5338 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5339 khz = cpufreq_quick_get(raw_smp_processor_id());
5340 if (!khz)
5341 khz = tsc_khz;
0a3aee0d 5342 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5343}
5344
c8076604
GH		 5345static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5346 void *data)
5347{
5348 struct cpufreq_freqs *freq = data;
5349 struct kvm *kvm;
5350 struct kvm_vcpu *vcpu;
5351 int i, send_ipi = 0;
5352
8cfdc000
ZA		 5353 /*
5354 * We allow guests to temporarily run on slowing clocks,
5355 * provided we notify them after, or to run on accelerating
5356 * clocks, provided we notify them before. Thus time never
5357 * goes backwards.
5358 *
5359 * However, we have a problem. We can't atomically update
5360 * the frequency of a given CPU from this function; it is
5361 * merely a notifier, which can be called from any CPU.
5362 * Changing the TSC frequency at arbitrary points in time
5363 * requires a recomputation of local variables related to
5364 * the TSC for each VCPU. We must flag these local variables
5365 * to be updated and be sure the update takes place with the
5366 * new frequency before any guests proceed.
5367 *
5368 * Unfortunately, the combination of hotplug CPU and frequency
5369 * change creates an intractable locking scenario; the order
5370 * of when these callouts happen is undefined with respect to
5371 * CPU hotplug, and they can race with each other. As such,
5372 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5373 * undefined; you can actually have a CPU frequency change take
5374 * place in between the computation of X and the setting of the
5375 * variable. To protect against this problem, all updates of
5376 * the per_cpu tsc_khz variable are done in an interrupt
5377 * protected IPI, and all callers wishing to update the value
5378 * must wait for a synchronous IPI to complete (which is trivial
5379 * if the caller is on the CPU already). This establishes the
5380 * necessary total order on variable updates.
5381 *
5382 * Note that because a guest time update may take place
5383 * anytime after the setting of the VCPU's request bit, the
5384 * correct TSC value must be set before the request. However,
5385 * to ensure the update actually makes it to any guest which
5386 * starts running in hardware virtualization between the set
5387 * and the acquisition of the spinlock, we must also ping the
5388 * CPU after setting the request bit.
5389 *
5390 */
5391
c8076604
GH		 5392 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5393 return 0;
5394 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5395 return 0;
8cfdc000
ZA		 5396
5397 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5398
2f303b74 5399 spin_lock(&kvm_lock);
c8076604 5400 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5401 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5402 if (vcpu->cpu != freq->cpu)
5403 continue;
c285545f 5404 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5405 if (vcpu->cpu != smp_processor_id())
8cfdc000 5406 send_ipi = 1;
c8076604
GH		 5407 }
5408 }
2f303b74 5409 spin_unlock(&kvm_lock);
c8076604
GH		 5410
5411 if (freq->old < freq->new && send_ipi) {
5412 /*
5413 * We upscale the frequency. Must make the guest
5414 * doesn't see old kvmclock values while running with
5415 * the new frequency, otherwise we risk the guest sees
5416 * time go backwards.
5417 *
5418 * In case we update the frequency for another cpu
5419 * (which might be in guest context) send an interrupt
5420 * to kick the cpu out of guest context. Next time
5421 * guest context is entered kvmclock will be updated,
5422 * so the guest will not see stale values.
5423 */
8cfdc000 5424 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5425 }
5426 return 0;
5427}
5428
5429static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5430 .notifier_call = kvmclock_cpufreq_notifier
5431};
5432
5433static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5434 unsigned long action, void *hcpu)
5435{
5436 unsigned int cpu = (unsigned long)hcpu;
5437
5438 switch (action) {
5439 case CPU_ONLINE:
5440 case CPU_DOWN_FAILED:
5441 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5442 break;
5443 case CPU_DOWN_PREPARE:
5444 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5445 break;
5446 }
5447 return NOTIFY_OK;
5448}
5449
5450static struct notifier_block kvmclock_cpu_notifier_block = {
5451 .notifier_call = kvmclock_cpu_notifier,
5452 .priority = -INT_MAX
c8076604
GH		 5453};
5454
b820cc0c
ZA		 5455static void kvm_timer_init(void)
5456{
5457 int cpu;
5458
c285545f 5459 max_tsc_khz = tsc_khz;
460dd42e
SB		 5460
5461 cpu_notifier_register_begin();
b820cc0c 5462 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5463#ifdef CONFIG_CPU_FREQ
5464 struct cpufreq_policy policy;
5465 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5466 cpu = get_cpu();
5467 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5468 if (policy.cpuinfo.max_freq)
5469 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5470 put_cpu();
c285545f 5471#endif
b820cc0c
ZA		 5472 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5473 CPUFREQ_TRANSITION_NOTIFIER);
5474 }
c285545f 5475 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5476 for_each_online_cpu(cpu)
5477 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5478
5479 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5480 cpu_notifier_register_done();
5481
b820cc0c
ZA		 5482}
5483
ff9d07a0
ZY		 5484static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5485
f5132b01 5486int kvm_is_in_guest(void)
ff9d07a0 5487{
086c9855 5488 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5489}
5490
5491static int kvm_is_user_mode(void)
5492{
5493 int user_mode = 3;
dcf46b94 5494
086c9855
AS		 5495 if (__this_cpu_read(current_vcpu))
5496 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5497
ff9d07a0
ZY		 5498 return user_mode != 0;
5499}
5500
5501static unsigned long kvm_get_guest_ip(void)
5502{
5503 unsigned long ip = 0;
dcf46b94 5504
086c9855
AS		 5505 if (__this_cpu_read(current_vcpu))
5506 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5507
ff9d07a0
ZY		 5508 return ip;
5509}
5510
5511static struct perf_guest_info_callbacks kvm_guest_cbs = {
5512 .is_in_guest = kvm_is_in_guest,
5513 .is_user_mode = kvm_is_user_mode,
5514 .get_guest_ip = kvm_get_guest_ip,
5515};
5516
5517void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5518{
086c9855 5519 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5520}
5521EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5522
5523void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5524{
086c9855 5525 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5526}
5527EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5528
ce88decf
XG		 5529static void kvm_set_mmio_spte_mask(void)
5530{
5531 u64 mask;
5532 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5533
5534 /*
5535 * Set the reserved bits and the present bit of an paging-structure
5536 * entry to generate page fault with PFER.RSV = 1.
5537 */
885032b9 5538 /* Mask the reserved physical address bits. */
d1431483 5539 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5540
5541 /* Bit 62 is always reserved for 32bit host. */
5542 mask |= 0x3ull << 62;
5543
5544 /* Set the present bit. */
ce88decf
XG		 5545 mask |= 1ull;
5546
5547#ifdef CONFIG_X86_64
5548 /*
5549 * If reserved bit is not supported, clear the present bit to disable
5550 * mmio page fault.
5551 */
5552 if (maxphyaddr == 52)
5553 mask &= ~1ull;
5554#endif
5555
5556 kvm_mmu_set_mmio_spte_mask(mask);
5557}
5558
16e8d74d
MT		 5559#ifdef CONFIG_X86_64
5560static void pvclock_gtod_update_fn(struct work_struct *work)
5561{
d828199e
MT		 5562 struct kvm *kvm;
5563
5564 struct kvm_vcpu *vcpu;
5565 int i;
5566
2f303b74 5567 spin_lock(&kvm_lock);
d828199e
MT		 5568 list_for_each_entry(kvm, &vm_list, vm_list)
5569 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5570 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5571 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5572 spin_unlock(&kvm_lock);
16e8d74d
MT		 5573}
5574
5575static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5576
5577/*
5578 * Notification about pvclock gtod data update.
5579 */
5580static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5581 void *priv)
5582{
5583 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5584 struct timekeeper *tk = priv;
5585
5586 update_pvclock_gtod(tk);
5587
5588 /* disable master clock if host does not trust, or does not
5589 * use, TSC clocksource
5590 */
5591 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5592 atomic_read(&kvm_guest_has_master_clock) != 0)
5593 queue_work(system_long_wq, &pvclock_gtod_work);
5594
5595 return 0;
5596}
5597
5598static struct notifier_block pvclock_gtod_notifier = {
5599 .notifier_call = pvclock_gtod_notify,
5600};
5601#endif
5602
f8c16bba 5603int kvm_arch_init(void *opaque)
043405e1 5604{
b820cc0c 5605 int r;
6b61edf7 5606 struct kvm_x86_ops *ops = opaque;
f8c16bba 5607
f8c16bba
ZX		 5608 if (kvm_x86_ops) {
5609 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5610 r = -EEXIST;
5611 goto out;
f8c16bba
ZX		 5612 }
5613
5614 if (!ops->cpu_has_kvm_support()) {
5615 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5616 r = -EOPNOTSUPP;
5617 goto out;
f8c16bba
ZX		 5618 }
5619 if (ops->disabled_by_bios()) {
5620 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5621 r = -EOPNOTSUPP;
5622 goto out;
f8c16bba
ZX		 5623 }
5624
013f6a5d
MT		 5625 r = -ENOMEM;
5626 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5627 if (!shared_msrs) {
5628 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5629 goto out;
5630 }
5631
97db56ce
AK		 5632 r = kvm_mmu_module_init();
5633 if (r)
013f6a5d 5634 goto out_free_percpu;
97db56ce 5635
ce88decf 5636 kvm_set_mmio_spte_mask();
97db56ce 5637
f8c16bba 5638 kvm_x86_ops = ops;
920c8377 5639
7b52345e 5640 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5641 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5642
b820cc0c 5643 kvm_timer_init();
c8076604 5644
ff9d07a0
ZY		 5645 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5646
2acf923e
DC		 5647 if (cpu_has_xsave)
5648 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5649
c5cc421b 5650 kvm_lapic_init();
16e8d74d
MT		 5651#ifdef CONFIG_X86_64
5652 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5653#endif
5654
f8c16bba 5655 return 0;
56c6d28a 5656
013f6a5d
MT		 5657out_free_percpu:
5658 free_percpu(shared_msrs);
56c6d28a 5659out:
56c6d28a 5660 return r;
043405e1 5661}
8776e519 5662
f8c16bba
ZX		 5663void kvm_arch_exit(void)
5664{
ff9d07a0
ZY		 5665 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5666
888d256e
JK		 5667 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5668 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5669 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5670 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5671#ifdef CONFIG_X86_64
5672 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5673#endif
f8c16bba 5674 kvm_x86_ops = NULL;
56c6d28a 5675 kvm_mmu_module_exit();
013f6a5d 5676 free_percpu(shared_msrs);
56c6d28a 5677}
f8c16bba 5678
5cb56059 5679int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5680{
5681 ++vcpu->stat.halt_exits;
5682 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5683 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5684 return 1;
5685 } else {
5686 vcpu->run->exit_reason = KVM_EXIT_HLT;
5687 return 0;
5688 }
5689}
5cb56059
JS		 5690EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5691
5692int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5693{
5694 kvm_x86_ops->skip_emulated_instruction(vcpu);
5695 return kvm_vcpu_halt(vcpu);
5696}
8776e519
HB		 5697EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5698
6aef266c
SV		 5699/*
5700 * kvm_pv_kick_cpu_op: Kick a vcpu.
5701 *
5702 * @apicid - apicid of vcpu to be kicked.
5703 */
5704static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5705{
24d2166b 5706 struct kvm_lapic_irq lapic_irq;
6aef266c 5707
24d2166b
R		 5708 lapic_irq.shorthand = 0;
5709 lapic_irq.dest_mode = 0;
5710 lapic_irq.dest_id = apicid;
93bbf0b8 5711 lapic_irq.msi_redir_hint = false;
6aef266c 5712
24d2166b 5713 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5714 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5715}
5716
8776e519
HB		 5717int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5718{
5719 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5720 int op_64_bit, r = 1;
8776e519 5721
5cb56059
JS		 5722 kvm_x86_ops->skip_emulated_instruction(vcpu);
5723
55cd8e5a
GN		 5724 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5725 return kvm_hv_hypercall(vcpu);
5726
5fdbf976
MT		 5727 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5728 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5729 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5730 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5731 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5732
229456fc 5733 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5734
a449c7aa
NA		 5735 op_64_bit = is_64_bit_mode(vcpu);
5736 if (!op_64_bit) {
8776e519
HB		 5737 nr &= 0xFFFFFFFF;
5738 a0 &= 0xFFFFFFFF;
5739 a1 &= 0xFFFFFFFF;
5740 a2 &= 0xFFFFFFFF;
5741 a3 &= 0xFFFFFFFF;
5742 }
5743
07708c4a
JK		 5744 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5745 ret = -KVM_EPERM;
5746 goto out;
5747 }
5748
8776e519 5749 switch (nr) {
b93463aa
AK		 5750 case KVM_HC_VAPIC_POLL_IRQ:
5751 ret = 0;
5752 break;
6aef266c
SV		 5753 case KVM_HC_KICK_CPU:
5754 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5755 ret = 0;
5756 break;
8776e519
HB		 5757 default:
5758 ret = -KVM_ENOSYS;
5759 break;
5760 }
07708c4a 5761out:
a449c7aa
NA		 5762 if (!op_64_bit)
5763 ret = (u32)ret;
5fdbf976 5764 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5765 ++vcpu->stat.hypercalls;
2f333bcb 5766 return r;
8776e519
HB		 5767}
5768EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5769
b6785def 5770static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5771{
d6aa1000 5772 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5773 char instruction[3];
5fdbf976 5774 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5775
8776e519 5776 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5777
9d74191a 5778 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5779}
5780
b6c7a5dc
HB		 5781/*
5782 * Check if userspace requested an interrupt window, and that the
5783 * interrupt window is open.
5784 *
5785 * No need to exit to userspace if we already have an interrupt queued.
5786 */
851ba692 5787static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5788{
8061823a 5789 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5790 vcpu->run->request_interrupt_window &&
5df56646 5791 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5792}
5793
851ba692 5794static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5795{
851ba692
AK		 5796 struct kvm_run *kvm_run = vcpu->run;
5797
91586a3b 5798 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5799 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5800 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5801 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5802 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5803 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5804 else
b6c7a5dc 5805 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5806 kvm_arch_interrupt_allowed(vcpu) &&
5807 !kvm_cpu_has_interrupt(vcpu) &&
5808 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5809}
5810
95ba8273
GN		 5811static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5812{
5813 int max_irr, tpr;
5814
5815 if (!kvm_x86_ops->update_cr8_intercept)
5816 return;
5817
88c808fd
AK		 5818 if (!vcpu->arch.apic)
5819 return;
5820
8db3baa2
GN		 5821 if (!vcpu->arch.apic->vapic_addr)
5822 max_irr = kvm_lapic_find_highest_irr(vcpu);
5823 else
5824 max_irr = -1;
95ba8273
GN		 5825
5826 if (max_irr != -1)
5827 max_irr >>= 4;
5828
5829 tpr = kvm_lapic_get_cr8(vcpu);
5830
5831 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5832}
5833
b6b8a145 5834static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5835{
b6b8a145
JK		 5836 int r;
5837
95ba8273 5838 /* try to reinject previous events if any */
b59bb7bd 5839 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5840 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5841 vcpu->arch.exception.has_error_code,
5842 vcpu->arch.exception.error_code);
d6e8c854
NA		 5843
5844 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5845 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5846 X86_EFLAGS_RF);
5847
6bdf0662
NA		 5848 if (vcpu->arch.exception.nr == DB_VECTOR &&
5849 (vcpu->arch.dr7 & DR7_GD)) {
5850 vcpu->arch.dr7 &= ~DR7_GD;
5851 kvm_update_dr7(vcpu);
5852 }
5853
b59bb7bd
GN		 5854 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5855 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5856 vcpu->arch.exception.error_code,
5857 vcpu->arch.exception.reinject);
b6b8a145 5858 return 0;
b59bb7bd
GN		 5859 }
5860
95ba8273
GN		 5861 if (vcpu->arch.nmi_injected) {
5862 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5863 return 0;
95ba8273
GN		 5864 }
5865
5866 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5867 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5868 return 0;
5869 }
5870
5871 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5872 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5873 if (r != 0)
5874 return r;
95ba8273
GN		 5875 }
5876
5877 /* try to inject new event if pending */
5878 if (vcpu->arch.nmi_pending) {
5879 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5880 --vcpu->arch.nmi_pending;
95ba8273
GN		 5881 vcpu->arch.nmi_injected = true;
5882 kvm_x86_ops->set_nmi(vcpu);
5883 }
c7c9c56c 5884 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5885 /*
5886 * Because interrupts can be injected asynchronously, we are
5887 * calling check_nested_events again here to avoid a race condition.
5888 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5889 * proposal and current concerns. Perhaps we should be setting
5890 * KVM_REQ_EVENT only on certain events and not unconditionally?
5891 */
5892 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5893 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5894 if (r != 0)
5895 return r;
5896 }
95ba8273 5897 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5898 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5899 false);
5900 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5901 }
5902 }
b6b8a145 5903 return 0;
95ba8273
GN		 5904}
5905
7460fb4a
AK		 5906static void process_nmi(struct kvm_vcpu *vcpu)
5907{
5908 unsigned limit = 2;
5909
5910 /*
5911 * x86 is limited to one NMI running, and one NMI pending after it.
5912 * If an NMI is already in progress, limit further NMIs to just one.
5913 * Otherwise, allow two (and we'll inject the first one immediately).
5914 */
5915 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5916 limit = 1;
5917
5918 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5919 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5920 kvm_make_request(KVM_REQ_EVENT, vcpu);
5921}
5922
660a5d51
PB		 5923#define put_smstate(type, buf, offset, val) \
5924 *(type *)((buf) + (offset) - 0x7e00) = val
5925
5926static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5927{
5928 u32 flags = 0;
5929 flags |= seg->g << 23;
5930 flags |= seg->db << 22;
5931 flags |= seg->l << 21;
5932 flags |= seg->avl << 20;
5933 flags |= seg->present << 15;
5934 flags |= seg->dpl << 13;
5935 flags |= seg->s << 12;
5936 flags |= seg->type << 8;
5937 return flags;
5938}
5939
5940static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5941{
5942 struct kvm_segment seg;
5943 int offset;
5944
5945 kvm_get_segment(vcpu, &seg, n);
5946 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5947
5948 if (n < 3)
5949 offset = 0x7f84 + n * 12;
5950 else
5951 offset = 0x7f2c + (n - 3) * 12;
5952
5953 put_smstate(u32, buf, offset + 8, seg.base);
5954 put_smstate(u32, buf, offset + 4, seg.limit);
5955 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5956}
5957
5958static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5959{
5960 struct kvm_segment seg;
5961 int offset;
5962 u16 flags;
5963
5964 kvm_get_segment(vcpu, &seg, n);
5965 offset = 0x7e00 + n * 16;
5966
5967 flags = process_smi_get_segment_flags(&seg) >> 8;
5968 put_smstate(u16, buf, offset, seg.selector);
5969 put_smstate(u16, buf, offset + 2, flags);
5970 put_smstate(u32, buf, offset + 4, seg.limit);
5971 put_smstate(u64, buf, offset + 8, seg.base);
5972}
5973
5974static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
5975{
5976 struct desc_ptr dt;
5977 struct kvm_segment seg;
5978 unsigned long val;
5979 int i;
5980
5981 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
5982 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
5983 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
5984 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
5985
5986 for (i = 0; i < 8; i++)
5987 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
5988
5989 kvm_get_dr(vcpu, 6, &val);
5990 put_smstate(u32, buf, 0x7fcc, (u32)val);
5991 kvm_get_dr(vcpu, 7, &val);
5992 put_smstate(u32, buf, 0x7fc8, (u32)val);
5993
5994 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
5995 put_smstate(u32, buf, 0x7fc4, seg.selector);
5996 put_smstate(u32, buf, 0x7f64, seg.base);
5997 put_smstate(u32, buf, 0x7f60, seg.limit);
5998 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
5999
6000 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6001 put_smstate(u32, buf, 0x7fc0, seg.selector);
6002 put_smstate(u32, buf, 0x7f80, seg.base);
6003 put_smstate(u32, buf, 0x7f7c, seg.limit);
6004 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6005
6006 kvm_x86_ops->get_gdt(vcpu, &dt);
6007 put_smstate(u32, buf, 0x7f74, dt.address);
6008 put_smstate(u32, buf, 0x7f70, dt.size);
6009
6010 kvm_x86_ops->get_idt(vcpu, &dt);
6011 put_smstate(u32, buf, 0x7f58, dt.address);
6012 put_smstate(u32, buf, 0x7f54, dt.size);
6013
6014 for (i = 0; i < 6; i++)
6015 process_smi_save_seg_32(vcpu, buf, i);
6016
6017 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6018
6019 /* revision id */
6020 put_smstate(u32, buf, 0x7efc, 0x00020000);
6021 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6022}
6023
6024static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6025{
6026#ifdef CONFIG_X86_64
6027 struct desc_ptr dt;
6028 struct kvm_segment seg;
6029 unsigned long val;
6030 int i;
6031
6032 for (i = 0; i < 16; i++)
6033 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6034
6035 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6036 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6037
6038 kvm_get_dr(vcpu, 6, &val);
6039 put_smstate(u64, buf, 0x7f68, val);
6040 kvm_get_dr(vcpu, 7, &val);
6041 put_smstate(u64, buf, 0x7f60, val);
6042
6043 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6044 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6045 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6046
6047 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6048
6049 /* revision id */
6050 put_smstate(u32, buf, 0x7efc, 0x00020064);
6051
6052 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6053
6054 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6055 put_smstate(u16, buf, 0x7e90, seg.selector);
6056 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6057 put_smstate(u32, buf, 0x7e94, seg.limit);
6058 put_smstate(u64, buf, 0x7e98, seg.base);
6059
6060 kvm_x86_ops->get_idt(vcpu, &dt);
6061 put_smstate(u32, buf, 0x7e84, dt.size);
6062 put_smstate(u64, buf, 0x7e88, dt.address);
6063
6064 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6065 put_smstate(u16, buf, 0x7e70, seg.selector);
6066 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6067 put_smstate(u32, buf, 0x7e74, seg.limit);
6068 put_smstate(u64, buf, 0x7e78, seg.base);
6069
6070 kvm_x86_ops->get_gdt(vcpu, &dt);
6071 put_smstate(u32, buf, 0x7e64, dt.size);
6072 put_smstate(u64, buf, 0x7e68, dt.address);
6073
6074 for (i = 0; i < 6; i++)
6075 process_smi_save_seg_64(vcpu, buf, i);
6076#else
6077 WARN_ON_ONCE(1);
6078#endif
6079}
6080
64d60670
PB		 6081static void process_smi(struct kvm_vcpu *vcpu)
6082{
660a5d51
PB		 6083 struct kvm_segment cs, ds;
6084 char buf[512];
6085 u32 cr0;
6086
64d60670
PB		 6087 if (is_smm(vcpu)) {
6088 vcpu->arch.smi_pending = true;
6089 return;
6090 }
6091
660a5d51
PB		 6092 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6093 vcpu->arch.hflags |= HF_SMM_MASK;
6094 memset(buf, 0, 512);
6095 if (guest_cpuid_has_longmode(vcpu))
6096 process_smi_save_state_64(vcpu, buf);
6097 else
6098 process_smi_save_state_32(vcpu, buf);
6099
54bf36aa 6100 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6101
6102 if (kvm_x86_ops->get_nmi_mask(vcpu))
6103 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6104 else
6105 kvm_x86_ops->set_nmi_mask(vcpu, true);
6106
6107 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6108 kvm_rip_write(vcpu, 0x8000);
6109
6110 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6111 kvm_x86_ops->set_cr0(vcpu, cr0);
6112 vcpu->arch.cr0 = cr0;
6113
6114 kvm_x86_ops->set_cr4(vcpu, 0);
6115
6116 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6117
6118 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6119 cs.base = vcpu->arch.smbase;
6120
6121 ds.selector = 0;
6122 ds.base = 0;
6123
6124 cs.limit = ds.limit = 0xffffffff;
6125 cs.type = ds.type = 0x3;
6126 cs.dpl = ds.dpl = 0;
6127 cs.db = ds.db = 0;
6128 cs.s = ds.s = 1;
6129 cs.l = ds.l = 0;
6130 cs.g = ds.g = 1;
6131 cs.avl = ds.avl = 0;
6132 cs.present = ds.present = 1;
6133 cs.unusable = ds.unusable = 0;
6134 cs.padding = ds.padding = 0;
6135
6136 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6137 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6138 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6139 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6140 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6141 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6142
6143 if (guest_cpuid_has_longmode(vcpu))
6144 kvm_x86_ops->set_efer(vcpu, 0);
6145
6146 kvm_update_cpuid(vcpu);
6147 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6148}
6149
3d81bc7e 6150static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6151{
6152 u64 eoi_exit_bitmap[4];
cf9e65b7 6153 u32 tmr[8];
c7c9c56c 6154
3d81bc7e
YZ		 6155 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6156 return;
c7c9c56c
YZ		 6157
6158 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6159 memset(tmr, 0, 32);
c7c9c56c 6160
cf9e65b7 6161 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6162 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6163 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6164}
6165
a70656b6
RK		 6166static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6167{
6168 ++vcpu->stat.tlb_flush;
6169 kvm_x86_ops->tlb_flush(vcpu);
6170}
6171
4256f43f
TC		 6172void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6173{
c24ae0dc
TC		 6174 struct page *page = NULL;
6175
f439ed27
PB		 6176 if (!irqchip_in_kernel(vcpu->kvm))
6177 return;
6178
4256f43f
TC		 6179 if (!kvm_x86_ops->set_apic_access_page_addr)
6180 return;
6181
c24ae0dc 6182 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6183 if (is_error_page(page))
6184 return;
c24ae0dc
TC		 6185 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6186
6187 /*
6188 * Do not pin apic access page in memory, the MMU notifier
6189 * will call us again if it is migrated or swapped out.
6190 */
6191 put_page(page);
4256f43f
TC		 6192}
6193EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6194
fe71557a
TC		 6195void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6196 unsigned long address)
6197{
c24ae0dc
TC		 6198 /*
6199 * The physical address of apic access page is stored in the VMCS.
6200 * Update it when it becomes invalid.
6201 */
6202 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6203 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6204}
6205
9357d939 6206/*
362c698f 6207 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6208 * exiting to the userspace. Otherwise, the value will be returned to the
6209 * userspace.
6210 */
851ba692 6211static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6212{
6213 int r;
6a8b1d13 6214 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6215 vcpu->run->request_interrupt_window;
730dca42 6216 bool req_immediate_exit = false;
b6c7a5dc 6217
3e007509 6218 if (vcpu->requests) {
a8eeb04a 6219 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6220 kvm_mmu_unload(vcpu);
a8eeb04a 6221 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6222 __kvm_migrate_timers(vcpu);
d828199e
MT		 6223 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6224 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6225 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6226 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6227 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6228 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6229 if (unlikely(r))
6230 goto out;
6231 }
a8eeb04a 6232 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6233 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6234 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6235 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6236 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6237 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6238 r = 0;
6239 goto out;
6240 }
a8eeb04a 6241 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6242 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6243 r = 0;
6244 goto out;
6245 }
a8eeb04a 6246 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6247 vcpu->fpu_active = 0;
6248 kvm_x86_ops->fpu_deactivate(vcpu);
6249 }
af585b92
GN		 6250 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6251 /* Page is swapped out. Do synthetic halt */
6252 vcpu->arch.apf.halted = true;
6253 r = 1;
6254 goto out;
6255 }
c9aaa895
GC		 6256 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6257 record_steal_time(vcpu);
64d60670
PB		 6258 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6259 process_smi(vcpu);
7460fb4a
AK		 6260 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6261 process_nmi(vcpu);
f5132b01 6262 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6263 kvm_pmu_handle_event(vcpu);
f5132b01 6264 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6265 kvm_pmu_deliver_pmi(vcpu);
3d81bc7e
YZ		 6266 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6267 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6268 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6269 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6270 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6271 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6272 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6273 r = 0;
6274 goto out;
6275 }
2f52d58c 6276 }
b93463aa 6277
b463a6f7 6278 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6279 kvm_apic_accept_events(vcpu);
6280 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6281 r = 1;
6282 goto out;
6283 }
6284
b6b8a145
JK		 6285 if (inject_pending_event(vcpu, req_int_win) != 0)
6286 req_immediate_exit = true;
b463a6f7 6287 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6288 else if (vcpu->arch.nmi_pending)
c9a7953f 6289 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6290 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6291 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6292
6293 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6294 /*
6295 * Update architecture specific hints for APIC
6296 * virtual interrupt delivery.
6297 */
6298 if (kvm_x86_ops->hwapic_irr_update)
6299 kvm_x86_ops->hwapic_irr_update(vcpu,
6300 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6301 update_cr8_intercept(vcpu);
6302 kvm_lapic_sync_to_vapic(vcpu);
6303 }
6304 }
6305
d8368af8
AK		 6306 r = kvm_mmu_reload(vcpu);
6307 if (unlikely(r)) {
d905c069 6308 goto cancel_injection;
d8368af8
AK		 6309 }
6310
b6c7a5dc
HB		 6311 preempt_disable();
6312
6313 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6314 if (vcpu->fpu_active)
6315 kvm_load_guest_fpu(vcpu);
2acf923e 6316 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6317
6b7e2d09
XG		 6318 vcpu->mode = IN_GUEST_MODE;
6319
01b71917
MT		 6320 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6321
6b7e2d09
XG		 6322 /* We should set ->mode before check ->requests,
6323 * see the comment in make_all_cpus_request.
6324 */
01b71917 6325 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6326
d94e1dc9 6327 local_irq_disable();
32f88400 6328
6b7e2d09 6329 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6330 || need_resched() || signal_pending(current)) {
6b7e2d09 6331 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6332 smp_wmb();
6c142801
AK		 6333 local_irq_enable();
6334 preempt_enable();
01b71917 6335 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6336 r = 1;
d905c069 6337 goto cancel_injection;
6c142801
AK		 6338 }
6339
d6185f20
NHE		 6340 if (req_immediate_exit)
6341 smp_send_reschedule(vcpu->cpu);
6342
ccf73aaf 6343 __kvm_guest_enter();
b6c7a5dc 6344
42dbaa5a 6345 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6346 set_debugreg(0, 7);
6347 set_debugreg(vcpu->arch.eff_db[0], 0);
6348 set_debugreg(vcpu->arch.eff_db[1], 1);
6349 set_debugreg(vcpu->arch.eff_db[2], 2);
6350 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6351 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6352 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6353 }
b6c7a5dc 6354
229456fc 6355 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6356 wait_lapic_expire(vcpu);
851ba692 6357 kvm_x86_ops->run(vcpu);
b6c7a5dc 6358
c77fb5fe
PB		 6359 /*
6360 * Do this here before restoring debug registers on the host. And
6361 * since we do this before handling the vmexit, a DR access vmexit
6362 * can (a) read the correct value of the debug registers, (b) set
6363 * KVM_DEBUGREG_WONT_EXIT again.
6364 */
6365 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6366 int i;
6367
6368 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6369 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6370 for (i = 0; i < KVM_NR_DB_REGS; i++)
6371 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6372 }
6373
24f1e32c
FW		 6374 /*
6375 * If the guest has used debug registers, at least dr7
6376 * will be disabled while returning to the host.
6377 * If we don't have active breakpoints in the host, we don't
6378 * care about the messed up debug address registers. But if
6379 * we have some of them active, restore the old state.
6380 */
59d8eb53 6381 if (hw_breakpoint_active())
24f1e32c 6382 hw_breakpoint_restore();
42dbaa5a 6383
886b470c
MT		 6384 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6385 native_read_tsc());
1d5f066e 6386
6b7e2d09 6387 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6388 smp_wmb();
a547c6db
YZ		 6389
6390 /* Interrupt is enabled by handle_external_intr() */
6391 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6392
6393 ++vcpu->stat.exits;
6394
6395 /*
6396 * We must have an instruction between local_irq_enable() and
6397 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6398 * the interrupt shadow. The stat.exits increment will do nicely.
6399 * But we need to prevent reordering, hence this barrier():
6400 */
6401 barrier();
6402
6403 kvm_guest_exit();
6404
6405 preempt_enable();
6406
f656ce01 6407 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6408
b6c7a5dc
HB		 6409 /*
6410 * Profile KVM exit RIPs:
6411 */
6412 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6413 unsigned long rip = kvm_rip_read(vcpu);
6414 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6415 }
6416
cc578287
ZA		 6417 if (unlikely(vcpu->arch.tsc_always_catchup))
6418 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6419
5cfb1d5a
MT		 6420 if (vcpu->arch.apic_attention)
6421 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6422
851ba692 6423 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6424 return r;
6425
6426cancel_injection:
6427 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6428 if (unlikely(vcpu->arch.apic_attention))
6429 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6430out:
6431 return r;
6432}
b6c7a5dc 6433
362c698f
PB		 6434static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6435{
9c8fd1ba
PB		 6436 if (!kvm_arch_vcpu_runnable(vcpu)) {
6437 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6438 kvm_vcpu_block(vcpu);
6439 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6440 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6441 return 1;
6442 }
362c698f
PB		 6443
6444 kvm_apic_accept_events(vcpu);
6445 switch(vcpu->arch.mp_state) {
6446 case KVM_MP_STATE_HALTED:
6447 vcpu->arch.pv.pv_unhalted = false;
6448 vcpu->arch.mp_state =
6449 KVM_MP_STATE_RUNNABLE;
6450 case KVM_MP_STATE_RUNNABLE:
6451 vcpu->arch.apf.halted = false;
6452 break;
6453 case KVM_MP_STATE_INIT_RECEIVED:
6454 break;
6455 default:
6456 return -EINTR;
6457 break;
6458 }
6459 return 1;
6460}
09cec754 6461
362c698f 6462static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6463{
6464 int r;
f656ce01 6465 struct kvm *kvm = vcpu->kvm;
d7690175 6466
f656ce01 6467 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6468
362c698f 6469 for (;;) {
af585b92
GN		 6470 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6471 !vcpu->arch.apf.halted)
851ba692 6472 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6473 else
6474 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6475 if (r <= 0)
6476 break;
6477
6478 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6479 if (kvm_cpu_has_pending_timer(vcpu))
6480 kvm_inject_pending_timer_irqs(vcpu);
6481
851ba692 6482 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6483 r = -EINTR;
851ba692 6484 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6485 ++vcpu->stat.request_irq_exits;
362c698f 6486 break;
09cec754 6487 }
af585b92
GN		 6488
6489 kvm_check_async_pf_completion(vcpu);
6490
09cec754
GN		 6491 if (signal_pending(current)) {
6492 r = -EINTR;
851ba692 6493 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6494 ++vcpu->stat.signal_exits;
362c698f 6495 break;
09cec754
GN		 6496 }
6497 if (need_resched()) {
f656ce01 6498 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6499 cond_resched();
f656ce01 6500 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6501 }
b6c7a5dc
HB		 6502 }
6503
f656ce01 6504 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6505
6506 return r;
6507}
6508
716d51ab
GN		 6509static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6510{
6511 int r;
6512 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6513 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6514 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6515 if (r != EMULATE_DONE)
6516 return 0;
6517 return 1;
6518}
6519
6520static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6521{
6522 BUG_ON(!vcpu->arch.pio.count);
6523
6524 return complete_emulated_io(vcpu);
6525}
6526
f78146b0
AK		 6527/*
6528 * Implements the following, as a state machine:
6529 *
6530 * read:
6531 * for each fragment
87da7e66
XG		 6532 * for each mmio piece in the fragment
6533 * write gpa, len
6534 * exit
6535 * copy data
f78146b0
AK		 6536 * execute insn
6537 *
6538 * write:
6539 * for each fragment
87da7e66
XG		 6540 * for each mmio piece in the fragment
6541 * write gpa, len
6542 * copy data
6543 * exit
f78146b0 6544 */
716d51ab 6545static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6546{
6547 struct kvm_run *run = vcpu->run;
f78146b0 6548 struct kvm_mmio_fragment *frag;
87da7e66 6549 unsigned len;
5287f194 6550
716d51ab 6551 BUG_ON(!vcpu->mmio_needed);
5287f194 6552
716d51ab 6553 /* Complete previous fragment */
87da7e66
XG		 6554 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6555 len = min(8u, frag->len);
716d51ab 6556 if (!vcpu->mmio_is_write)
87da7e66
XG		 6557 memcpy(frag->data, run->mmio.data, len);
6558
6559 if (frag->len <= 8) {
6560 /* Switch to the next fragment. */
6561 frag++;
6562 vcpu->mmio_cur_fragment++;
6563 } else {
6564 /* Go forward to the next mmio piece. */
6565 frag->data += len;
6566 frag->gpa += len;
6567 frag->len -= len;
6568 }
6569
a08d3b3b 6570 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6571 vcpu->mmio_needed = 0;
0912c977
PB		 6572
6573 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6574 if (vcpu->mmio_is_write)
716d51ab
GN		 6575 return 1;
6576 vcpu->mmio_read_completed = 1;
6577 return complete_emulated_io(vcpu);
6578 }
87da7e66 6579
716d51ab
GN		 6580 run->exit_reason = KVM_EXIT_MMIO;
6581 run->mmio.phys_addr = frag->gpa;
6582 if (vcpu->mmio_is_write)
87da7e66
XG		 6583 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6584 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6585 run->mmio.is_write = vcpu->mmio_is_write;
6586 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6587 return 0;
5287f194
AK		 6588}
6589
716d51ab 6590
b6c7a5dc
HB		 6591int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6592{
c5bedc68 6593 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6594 int r;
6595 sigset_t sigsaved;
6596
c4d72e2d 6597 fpu__activate_curr(fpu);
e5c30142 6598
ac9f6dc0
AK		 6599 if (vcpu->sigset_active)
6600 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6601
a4535290 6602 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6603 kvm_vcpu_block(vcpu);
66450a21 6604 kvm_apic_accept_events(vcpu);
d7690175 6605 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6606 r = -EAGAIN;
6607 goto out;
b6c7a5dc
HB		 6608 }
6609
b6c7a5dc 6610 /* re-sync apic's tpr */
eea1cff9
AP		 6611 if (!irqchip_in_kernel(vcpu->kvm)) {
6612 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6613 r = -EINVAL;
6614 goto out;
6615 }
6616 }
b6c7a5dc 6617
716d51ab
GN		 6618 if (unlikely(vcpu->arch.complete_userspace_io)) {
6619 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6620 vcpu->arch.complete_userspace_io = NULL;
6621 r = cui(vcpu);
6622 if (r <= 0)
6623 goto out;
6624 } else
6625 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6626
362c698f 6627 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6628
6629out:
f1d86e46 6630 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6631 if (vcpu->sigset_active)
6632 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6633
b6c7a5dc
HB		 6634 return r;
6635}
6636
6637int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6638{
7ae441ea
GN		 6639 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6640 /*
6641 * We are here if userspace calls get_regs() in the middle of
6642 * instruction emulation. Registers state needs to be copied
4a969980 6643 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6644 * that usually, but some bad designed PV devices (vmware
6645 * backdoor interface) need this to work
6646 */
dd856efa 6647 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6648 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6649 }
5fdbf976
MT		 6650 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6651 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6652 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6653 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6654 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6655 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6656 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6657 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6658#ifdef CONFIG_X86_64
5fdbf976
MT		 6659 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6660 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6661 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6662 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6663 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6664 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6665 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6666 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6667#endif
6668
5fdbf976 6669 regs->rip = kvm_rip_read(vcpu);
91586a3b 6670 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6671
b6c7a5dc
HB		 6672 return 0;
6673}
6674
6675int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6676{
7ae441ea
GN		 6677 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6678 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6679
5fdbf976
MT		 6680 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6681 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6682 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6683 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6684 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6685 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6686 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6687 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6688#ifdef CONFIG_X86_64
5fdbf976
MT		 6689 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6690 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6691 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6692 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6693 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6694 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6695 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6696 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6697#endif
6698
5fdbf976 6699 kvm_rip_write(vcpu, regs->rip);
91586a3b 6700 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6701
b4f14abd
JK		 6702 vcpu->arch.exception.pending = false;
6703
3842d135
AK		 6704 kvm_make_request(KVM_REQ_EVENT, vcpu);
6705
b6c7a5dc
HB		 6706 return 0;
6707}
6708
b6c7a5dc
HB		 6709void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6710{
6711 struct kvm_segment cs;
6712
3e6e0aab 6713 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6714 *db = cs.db;
6715 *l = cs.l;
6716}
6717EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6718
6719int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6720 struct kvm_sregs *sregs)
6721{
89a27f4d 6722 struct desc_ptr dt;
b6c7a5dc 6723
3e6e0aab
GT		 6724 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6725 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6726 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6727 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6728 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6729 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6730
3e6e0aab
GT		 6731 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6732 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6733
6734 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6735 sregs->idt.limit = dt.size;
6736 sregs->idt.base = dt.address;
b6c7a5dc 6737 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6738 sregs->gdt.limit = dt.size;
6739 sregs->gdt.base = dt.address;
b6c7a5dc 6740
4d4ec087 6741 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6742 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6743 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6744 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6745 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6746 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6747 sregs->apic_base = kvm_get_apic_base(vcpu);
6748
923c61bb 6749 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6750
36752c9b 6751 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6752 set_bit(vcpu->arch.interrupt.nr,
6753 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6754
b6c7a5dc
HB		 6755 return 0;
6756}
6757
62d9f0db
MT		 6758int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6759 struct kvm_mp_state *mp_state)
6760{
66450a21 6761 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6762 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6763 vcpu->arch.pv.pv_unhalted)
6764 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6765 else
6766 mp_state->mp_state = vcpu->arch.mp_state;
6767
62d9f0db
MT		 6768 return 0;
6769}
6770
6771int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6772 struct kvm_mp_state *mp_state)
6773{
66450a21
JK		 6774 if (!kvm_vcpu_has_lapic(vcpu) &&
6775 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6776 return -EINVAL;
6777
6778 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6779 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6780 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6781 } else
6782 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6783 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6784 return 0;
6785}
6786
7f3d35fd
KW		 6787int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6788 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6789{
9d74191a 6790 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6791 int ret;
e01c2426 6792
8ec4722d 6793 init_emulate_ctxt(vcpu);
c697518a 6794
7f3d35fd 6795 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6796 has_error_code, error_code);
c697518a 6797
c697518a 6798 if (ret)
19d04437 6799 return EMULATE_FAIL;
37817f29 6800
9d74191a
TY		 6801 kvm_rip_write(vcpu, ctxt->eip);
6802 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6803 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6804 return EMULATE_DONE;
37817f29
IE		 6805}
6806EXPORT_SYMBOL_GPL(kvm_task_switch);
6807
b6c7a5dc
HB		 6808int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6809 struct kvm_sregs *sregs)
6810{
58cb628d 6811 struct msr_data apic_base_msr;
b6c7a5dc 6812 int mmu_reset_needed = 0;
63f42e02 6813 int pending_vec, max_bits, idx;
89a27f4d 6814 struct desc_ptr dt;
b6c7a5dc 6815
6d1068b3
PM		 6816 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6817 return -EINVAL;
6818
89a27f4d
GN		 6819 dt.size = sregs->idt.limit;
6820 dt.address = sregs->idt.base;
b6c7a5dc 6821 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6822 dt.size = sregs->gdt.limit;
6823 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6824 kvm_x86_ops->set_gdt(vcpu, &dt);
6825
ad312c7c 6826 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6827 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6828 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6829 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6830
2d3ad1f4 6831 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6832
f6801dff 6833 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6834 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6835 apic_base_msr.data = sregs->apic_base;
6836 apic_base_msr.host_initiated = true;
6837 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6838
4d4ec087 6839 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6840 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6841 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6842
fc78f519 6843 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6844 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6845 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6846 kvm_update_cpuid(vcpu);
63f42e02
XG		 6847
6848 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6849 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6850 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6851 mmu_reset_needed = 1;
6852 }
63f42e02 6853 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6854
6855 if (mmu_reset_needed)
6856 kvm_mmu_reset_context(vcpu);
6857
a50abc3b 6858 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6859 pending_vec = find_first_bit(
6860 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6861 if (pending_vec < max_bits) {
66fd3f7f 6862 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6863 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6864 }
6865
3e6e0aab
GT		 6866 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6867 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6868 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6869 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6870 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6871 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6872
3e6e0aab
GT		 6873 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6874 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6875
5f0269f5
ME		 6876 update_cr8_intercept(vcpu);
6877
9c3e4aab 6878 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6879 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6880 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6881 !is_protmode(vcpu))
9c3e4aab
MT		 6882 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6883
3842d135
AK		 6884 kvm_make_request(KVM_REQ_EVENT, vcpu);
6885
b6c7a5dc
HB		 6886 return 0;
6887}
6888
d0bfb940
JK		 6889int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6890 struct kvm_guest_debug *dbg)
b6c7a5dc 6891{
355be0b9 6892 unsigned long rflags;
ae675ef0 6893 int i, r;
b6c7a5dc 6894
4f926bf2
JK		 6895 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6896 r = -EBUSY;
6897 if (vcpu->arch.exception.pending)
2122ff5e 6898 goto out;
4f926bf2
JK		 6899 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6900 kvm_queue_exception(vcpu, DB_VECTOR);
6901 else
6902 kvm_queue_exception(vcpu, BP_VECTOR);
6903 }
6904
91586a3b
JK		 6905 /*
6906 * Read rflags as long as potentially injected trace flags are still
6907 * filtered out.
6908 */
6909 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6910
6911 vcpu->guest_debug = dbg->control;
6912 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6913 vcpu->guest_debug = 0;
6914
6915 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6916 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6917 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6918 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6919 } else {
6920 for (i = 0; i < KVM_NR_DB_REGS; i++)
6921 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6922 }
c8639010 6923 kvm_update_dr7(vcpu);
ae675ef0 6924
f92653ee
JK		 6925 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6926 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6927 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6928
91586a3b
JK		 6929 /*
6930 * Trigger an rflags update that will inject or remove the trace
6931 * flags.
6932 */
6933 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6934
c8639010 6935 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6936
4f926bf2 6937 r = 0;
d0bfb940 6938
2122ff5e 6939out:
b6c7a5dc
HB		 6940
6941 return r;
6942}
6943
8b006791
ZX		 6944/*
6945 * Translate a guest virtual address to a guest physical address.
6946 */
6947int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6948 struct kvm_translation *tr)
6949{
6950 unsigned long vaddr = tr->linear_address;
6951 gpa_t gpa;
f656ce01 6952 int idx;
8b006791 6953
f656ce01 6954 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6955 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6956 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6957 tr->physical_address = gpa;
6958 tr->valid = gpa != UNMAPPED_GVA;
6959 tr->writeable = 1;
6960 tr->usermode = 0;
8b006791
ZX		 6961
6962 return 0;
6963}
6964
d0752060
HB		 6965int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6966{
c47ada30 6967 struct fxregs_state *fxsave =
7366ed77 6968 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6969
d0752060
HB		 6970 memcpy(fpu->fpr, fxsave->st_space, 128);
6971 fpu->fcw = fxsave->cwd;
6972 fpu->fsw = fxsave->swd;
6973 fpu->ftwx = fxsave->twd;
6974 fpu->last_opcode = fxsave->fop;
6975 fpu->last_ip = fxsave->rip;
6976 fpu->last_dp = fxsave->rdp;
6977 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6978
d0752060
HB		 6979 return 0;
6980}
6981
6982int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6983{
c47ada30 6984 struct fxregs_state *fxsave =
7366ed77 6985 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6986
d0752060
HB		 6987 memcpy(fxsave->st_space, fpu->fpr, 128);
6988 fxsave->cwd = fpu->fcw;
6989 fxsave->swd = fpu->fsw;
6990 fxsave->twd = fpu->ftwx;
6991 fxsave->fop = fpu->last_opcode;
6992 fxsave->rip = fpu->last_ip;
6993 fxsave->rdp = fpu->last_dp;
6994 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6995
d0752060
HB		 6996 return 0;
6997}
6998
0ee6a517 6999static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7000{
bf935b0b 7001 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7002 if (cpu_has_xsaves)
7366ed77 7003 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7004 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7005
2acf923e
DC		 7006 /*
7007 * Ensure guest xcr0 is valid for loading
7008 */
7009 vcpu->arch.xcr0 = XSTATE_FP;
7010
ad312c7c 7011 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7012}
d0752060
HB		 7013
7014void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7015{
2608d7a1 7016 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7017 return;
7018
2acf923e
DC		 7019 /*
7020 * Restore all possible states in the guest,
7021 * and assume host would use all available bits.
7022 * Guest xcr0 would be loaded later.
7023 */
7024 kvm_put_guest_xcr0(vcpu);
d0752060 7025 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7026 __kernel_fpu_begin();
003e2e8b 7027 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7028 trace_kvm_fpu(1);
d0752060 7029}
d0752060
HB		 7030
7031void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7032{
2acf923e
DC		 7033 kvm_put_guest_xcr0(vcpu);
7034
653f52c3
RR		 7035 if (!vcpu->guest_fpu_loaded) {
7036 vcpu->fpu_counter = 0;
d0752060 7037 return;
653f52c3 7038 }
d0752060
HB		 7039
7040 vcpu->guest_fpu_loaded = 0;
4f836347 7041 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7042 __kernel_fpu_end();
f096ed85 7043 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7044 /*
7045 * If using eager FPU mode, or if the guest is a frequent user
7046 * of the FPU, just leave the FPU active for next time.
7047 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7048 * the FPU in bursts will revert to loading it on demand.
7049 */
a9b4fb7e 7050 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7051 if (++vcpu->fpu_counter < 5)
7052 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7053 }
0c04851c 7054 trace_kvm_fpu(0);
d0752060 7055}
e9b11c17
ZX		 7056
7057void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7058{
12f9a48f 7059 kvmclock_reset(vcpu);
7f1ea208 7060
f5f48ee1 7061 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7062 kvm_x86_ops->vcpu_free(vcpu);
7063}
7064
7065struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7066 unsigned int id)
7067{
c447e76b
LL		 7068 struct kvm_vcpu *vcpu;
7069
6755bae8
ZA		 7070 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7071 printk_once(KERN_WARNING
7072 "kvm: SMP vm created on host with unstable TSC; "
7073 "guest TSC will not be reliable\n");
c447e76b
LL		 7074
7075 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7076
c447e76b 7077 return vcpu;
26e5215f 7078}
e9b11c17 7079
26e5215f
AK		 7080int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7081{
7082 int r;
e9b11c17 7083
19efffa2 7084 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7085 r = vcpu_load(vcpu);
7086 if (r)
7087 return r;
d28bc9dd 7088 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7089 kvm_mmu_setup(vcpu);
e9b11c17 7090 vcpu_put(vcpu);
26e5215f 7091 return r;
e9b11c17
ZX		 7092}
7093
31928aa5 7094void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7095{
8fe8ab46 7096 struct msr_data msr;
332967a3 7097 struct kvm *kvm = vcpu->kvm;
42897d86 7098
31928aa5
DD		 7099 if (vcpu_load(vcpu))
7100 return;
8fe8ab46
WA		 7101 msr.data = 0x0;
7102 msr.index = MSR_IA32_TSC;
7103 msr.host_initiated = true;
7104 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7105 vcpu_put(vcpu);
7106
630994b3
MT		 7107 if (!kvmclock_periodic_sync)
7108 return;
7109
332967a3
AJ		 7110 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7111 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7112}
7113
d40ccc62 7114void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7115{
9fc77441 7116 int r;
344d9588
GN		 7117 vcpu->arch.apf.msr_val = 0;
7118
9fc77441
MT		 7119 r = vcpu_load(vcpu);
7120 BUG_ON(r);
e9b11c17
ZX		 7121 kvm_mmu_unload(vcpu);
7122 vcpu_put(vcpu);
7123
7124 kvm_x86_ops->vcpu_free(vcpu);
7125}
7126
d28bc9dd 7127void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7128{
e69fab5d
PB		 7129 vcpu->arch.hflags = 0;
7130
7460fb4a
AK		 7131 atomic_set(&vcpu->arch.nmi_queued, 0);
7132 vcpu->arch.nmi_pending = 0;
448fa4a9 7133 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7134 kvm_clear_interrupt_queue(vcpu);
7135 kvm_clear_exception_queue(vcpu);
448fa4a9 7136
42dbaa5a 7137 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7138 kvm_update_dr0123(vcpu);
6f43ed01 7139 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7140 kvm_update_dr6(vcpu);
42dbaa5a 7141 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7142 kvm_update_dr7(vcpu);
42dbaa5a 7143
1119022c
NA		 7144 vcpu->arch.cr2 = 0;
7145
3842d135 7146 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7147 vcpu->arch.apf.msr_val = 0;
c9aaa895 7148 vcpu->arch.st.msr_val = 0;
3842d135 7149
12f9a48f
GC		 7150 kvmclock_reset(vcpu);
7151
af585b92
GN		 7152 kvm_clear_async_pf_completion_queue(vcpu);
7153 kvm_async_pf_hash_reset(vcpu);
7154 vcpu->arch.apf.halted = false;
3842d135 7155
64d60670 7156 if (!init_event) {
d28bc9dd 7157 kvm_pmu_reset(vcpu);
64d60670
PB		 7158 vcpu->arch.smbase = 0x30000;
7159 }
f5132b01 7160
66f7b72e
JS		 7161 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7162 vcpu->arch.regs_avail = ~0;
7163 vcpu->arch.regs_dirty = ~0;
7164
d28bc9dd 7165 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7166}
7167
2b4a273b 7168void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7169{
7170 struct kvm_segment cs;
7171
7172 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7173 cs.selector = vector << 8;
7174 cs.base = vector << 12;
7175 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7176 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7177}
7178
13a34e06 7179int kvm_arch_hardware_enable(void)
e9b11c17 7180{
ca84d1a2
ZA		 7181 struct kvm *kvm;
7182 struct kvm_vcpu *vcpu;
7183 int i;
0dd6a6ed
ZA		 7184 int ret;
7185 u64 local_tsc;
7186 u64 max_tsc = 0;
7187 bool stable, backwards_tsc = false;
18863bdd
AK		 7188
7189 kvm_shared_msr_cpu_online();
13a34e06 7190 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7191 if (ret != 0)
7192 return ret;
7193
7194 local_tsc = native_read_tsc();
7195 stable = !check_tsc_unstable();
7196 list_for_each_entry(kvm, &vm_list, vm_list) {
7197 kvm_for_each_vcpu(i, vcpu, kvm) {
7198 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7199 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7200 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7201 backwards_tsc = true;
7202 if (vcpu->arch.last_host_tsc > max_tsc)
7203 max_tsc = vcpu->arch.last_host_tsc;
7204 }
7205 }
7206 }
7207
7208 /*
7209 * Sometimes, even reliable TSCs go backwards. This happens on
7210 * platforms that reset TSC during suspend or hibernate actions, but
7211 * maintain synchronization. We must compensate. Fortunately, we can
7212 * detect that condition here, which happens early in CPU bringup,
7213 * before any KVM threads can be running. Unfortunately, we can't
7214 * bring the TSCs fully up to date with real time, as we aren't yet far
7215 * enough into CPU bringup that we know how much real time has actually
7216 * elapsed; our helper function, get_kernel_ns() will be using boot
7217 * variables that haven't been updated yet.
7218 *
7219 * So we simply find the maximum observed TSC above, then record the
7220 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7221 * the adjustment will be applied. Note that we accumulate
7222 * adjustments, in case multiple suspend cycles happen before some VCPU
7223 * gets a chance to run again. In the event that no KVM threads get a
7224 * chance to run, we will miss the entire elapsed period, as we'll have
7225 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7226 * loose cycle time. This isn't too big a deal, since the loss will be
7227 * uniform across all VCPUs (not to mention the scenario is extremely
7228 * unlikely). It is possible that a second hibernate recovery happens
7229 * much faster than a first, causing the observed TSC here to be
7230 * smaller; this would require additional padding adjustment, which is
7231 * why we set last_host_tsc to the local tsc observed here.
7232 *
7233 * N.B. - this code below runs only on platforms with reliable TSC,
7234 * as that is the only way backwards_tsc is set above. Also note
7235 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7236 * have the same delta_cyc adjustment applied if backwards_tsc
7237 * is detected. Note further, this adjustment is only done once,
7238 * as we reset last_host_tsc on all VCPUs to stop this from being
7239 * called multiple times (one for each physical CPU bringup).
7240 *
4a969980 7241 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7242 * will be compensated by the logic in vcpu_load, which sets the TSC to
7243 * catchup mode. This will catchup all VCPUs to real time, but cannot
7244 * guarantee that they stay in perfect synchronization.
7245 */
7246 if (backwards_tsc) {
7247 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7248 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7249 list_for_each_entry(kvm, &vm_list, vm_list) {
7250 kvm_for_each_vcpu(i, vcpu, kvm) {
7251 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7252 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7253 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7254 }
7255
7256 /*
7257 * We have to disable TSC offset matching.. if you were
7258 * booting a VM while issuing an S4 host suspend....
7259 * you may have some problem. Solving this issue is
7260 * left as an exercise to the reader.
7261 */
7262 kvm->arch.last_tsc_nsec = 0;
7263 kvm->arch.last_tsc_write = 0;
7264 }
7265
7266 }
7267 return 0;
e9b11c17
ZX		 7268}
7269
13a34e06 7270void kvm_arch_hardware_disable(void)
e9b11c17 7271{
13a34e06
RK		 7272 kvm_x86_ops->hardware_disable();
7273 drop_user_return_notifiers();
e9b11c17
ZX		 7274}
7275
7276int kvm_arch_hardware_setup(void)
7277{
9e9c3fe4
NA		 7278 int r;
7279
7280 r = kvm_x86_ops->hardware_setup();
7281 if (r != 0)
7282 return r;
7283
7284 kvm_init_msr_list();
7285 return 0;
e9b11c17
ZX		 7286}
7287
7288void kvm_arch_hardware_unsetup(void)
7289{
7290 kvm_x86_ops->hardware_unsetup();
7291}
7292
7293void kvm_arch_check_processor_compat(void *rtn)
7294{
7295 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7296}
7297
7298bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7299{
7300 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7301}
7302EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7303
7304bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7305{
7306 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7307}
7308
3e515705
AK		 7309bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7310{
7311 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7312}
7313
54e9818f
GN		 7314struct static_key kvm_no_apic_vcpu __read_mostly;
7315
e9b11c17
ZX		 7316int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7317{
7318 struct page *page;
7319 struct kvm *kvm;
7320 int r;
7321
7322 BUG_ON(vcpu->kvm == NULL);
7323 kvm = vcpu->kvm;
7324
6aef266c 7325 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7326 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7327 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7328 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7329 else
a4535290 7330 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7331
7332 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7333 if (!page) {
7334 r = -ENOMEM;
7335 goto fail;
7336 }
ad312c7c 7337 vcpu->arch.pio_data = page_address(page);
e9b11c17 7338
cc578287 7339 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7340
e9b11c17
ZX		 7341 r = kvm_mmu_create(vcpu);
7342 if (r < 0)
7343 goto fail_free_pio_data;
7344
7345 if (irqchip_in_kernel(kvm)) {
7346 r = kvm_create_lapic(vcpu);
7347 if (r < 0)
7348 goto fail_mmu_destroy;
54e9818f
GN		 7349 } else
7350 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7351
890ca9ae
HY		 7352 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7353 GFP_KERNEL);
7354 if (!vcpu->arch.mce_banks) {
7355 r = -ENOMEM;
443c39bc 7356 goto fail_free_lapic;
890ca9ae
HY		 7357 }
7358 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7359
f1797359
WY		 7360 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7361 r = -ENOMEM;
f5f48ee1 7362 goto fail_free_mce_banks;
f1797359 7363 }
f5f48ee1 7364
0ee6a517 7365 fx_init(vcpu);
66f7b72e 7366
ba904635 7367 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7368 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7369
7370 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7371 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7372
5a4f55cd
EK		 7373 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7374
74545705
RK		 7375 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7376
af585b92 7377 kvm_async_pf_hash_reset(vcpu);
f5132b01 7378 kvm_pmu_init(vcpu);
af585b92 7379
e9b11c17 7380 return 0;
0ee6a517 7381
f5f48ee1
SY		 7382fail_free_mce_banks:
7383 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7384fail_free_lapic:
7385 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7386fail_mmu_destroy:
7387 kvm_mmu_destroy(vcpu);
7388fail_free_pio_data:
ad312c7c 7389 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7390fail:
7391 return r;
7392}
7393
7394void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7395{
f656ce01
MT		 7396 int idx;
7397
f5132b01 7398 kvm_pmu_destroy(vcpu);
36cb93fd 7399 kfree(vcpu->arch.mce_banks);
e9b11c17 7400 kvm_free_lapic(vcpu);
f656ce01 7401 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7402 kvm_mmu_destroy(vcpu);
f656ce01 7403 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7404 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7405 if (!irqchip_in_kernel(vcpu->kvm))
7406 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7407}
d19a9cd2 7408
e790d9ef
RK		 7409void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7410{
ae97a3b8 7411 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7412}
7413
e08b9637 7414int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7415{
e08b9637
CO		 7416 if (type)
7417 return -EINVAL;
7418
6ef768fa 7419 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7420 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7421 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7422 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7423 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7424
5550af4d
SY		 7425 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7426 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7427 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7428 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7429 &kvm->arch.irq_sources_bitmap);
5550af4d 7430
038f8c11 7431 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7432 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7433 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7434
7435 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7436
7e44e449 7437 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7438 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7439
d89f5eff 7440 return 0;
d19a9cd2
ZX		 7441}
7442
7443static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7444{
9fc77441
MT		 7445 int r;
7446 r = vcpu_load(vcpu);
7447 BUG_ON(r);
d19a9cd2
ZX		 7448 kvm_mmu_unload(vcpu);
7449 vcpu_put(vcpu);
7450}
7451
7452static void kvm_free_vcpus(struct kvm *kvm)
7453{
7454 unsigned int i;
988a2cae 7455 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7456
7457 /*
7458 * Unpin any mmu pages first.
7459 */
af585b92
GN		 7460 kvm_for_each_vcpu(i, vcpu, kvm) {
7461 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7462 kvm_unload_vcpu_mmu(vcpu);
af585b92 7463 }
988a2cae
GN		 7464 kvm_for_each_vcpu(i, vcpu, kvm)
7465 kvm_arch_vcpu_free(vcpu);
7466
7467 mutex_lock(&kvm->lock);
7468 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7469 kvm->vcpus[i] = NULL;
d19a9cd2 7470
988a2cae
GN		 7471 atomic_set(&kvm->online_vcpus, 0);
7472 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7473}
7474
ad8ba2cd
SY		 7475void kvm_arch_sync_events(struct kvm *kvm)
7476{
332967a3 7477 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7478 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7479 kvm_free_all_assigned_devices(kvm);
aea924f6 7480 kvm_free_pit(kvm);
ad8ba2cd
SY		 7481}
7482
9da0e4d5
PB		 7483int __x86_set_memory_region(struct kvm *kvm,
7484 const struct kvm_userspace_memory_region *mem)
7485{
7486 int i, r;
7487
7488 /* Called with kvm->slots_lock held. */
7489 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7490
7491 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7492 struct kvm_userspace_memory_region m = *mem;
7493
7494 m.slot |= i << 16;
7495 r = __kvm_set_memory_region(kvm, &m);
7496 if (r < 0)
7497 return r;
7498 }
7499
7500 return 0;
7501}
7502EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7503
7504int x86_set_memory_region(struct kvm *kvm,
7505 const struct kvm_userspace_memory_region *mem)
7506{
7507 int r;
7508
7509 mutex_lock(&kvm->slots_lock);
7510 r = __x86_set_memory_region(kvm, mem);
7511 mutex_unlock(&kvm->slots_lock);
7512
7513 return r;
7514}
7515EXPORT_SYMBOL_GPL(x86_set_memory_region);
7516
d19a9cd2
ZX		 7517void kvm_arch_destroy_vm(struct kvm *kvm)
7518{
27469d29
AH		 7519 if (current->mm == kvm->mm) {
7520 /*
7521 * Free memory regions allocated on behalf of userspace,
7522 * unless the the memory map has changed due to process exit
7523 * or fd copying.
7524 */
7525 struct kvm_userspace_memory_region mem;
7526 memset(&mem, 0, sizeof(mem));
7527 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7528 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7529
7530 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7531 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7532
7533 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7534 x86_set_memory_region(kvm, &mem);
27469d29 7535 }
6eb55818 7536 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7537 kfree(kvm->arch.vpic);
7538 kfree(kvm->arch.vioapic);
d19a9cd2 7539 kvm_free_vcpus(kvm);
1e08ec4a 7540 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7541}
0de10343 7542
5587027c 7543void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7544 struct kvm_memory_slot *dont)
7545{
7546 int i;
7547
d89cc617
TY		 7548 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7549 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7550 kvfree(free->arch.rmap[i]);
d89cc617 7551 free->arch.rmap[i] = NULL;
77d11309 7552 }
d89cc617
TY		 7553 if (i == 0)
7554 continue;
7555
7556 if (!dont || free->arch.lpage_info[i - 1] !=
7557 dont->arch.lpage_info[i - 1]) {
548ef284 7558 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7559 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7560 }
7561 }
7562}
7563
5587027c
AK		 7564int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7565 unsigned long npages)
db3fe4eb
TY		 7566{
7567 int i;
7568
d89cc617 7569 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7570 unsigned long ugfn;
7571 int lpages;
d89cc617 7572 int level = i + 1;
db3fe4eb
TY		 7573
7574 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7575 slot->base_gfn, level) + 1;
7576
d89cc617
TY		 7577 slot->arch.rmap[i] =
7578 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7579 if (!slot->arch.rmap[i])
77d11309 7580 goto out_free;
d89cc617
TY		 7581 if (i == 0)
7582 continue;
77d11309 7583
d89cc617
TY		 7584 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7585 sizeof(*slot->arch.lpage_info[i - 1]));
7586 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7587 goto out_free;
7588
7589 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7590 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7591 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7592 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7593 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7594 /*
7595 * If the gfn and userspace address are not aligned wrt each
7596 * other, or if explicitly asked to, disable large page
7597 * support for this slot
7598 */
7599 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7600 !kvm_largepages_enabled()) {
7601 unsigned long j;
7602
7603 for (j = 0; j < lpages; ++j)
d89cc617 7604 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7605 }
7606 }
7607
7608 return 0;
7609
7610out_free:
d89cc617 7611 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7612 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7613 slot->arch.rmap[i] = NULL;
7614 if (i == 0)
7615 continue;
7616
548ef284 7617 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7618 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7619 }
7620 return -ENOMEM;
7621}
7622
15f46015 7623void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7624{
e6dff7d1
TY		 7625 /*
7626 * memslots->generation has been incremented.
7627 * mmio generation may have reached its maximum value.
7628 */
54bf36aa 7629 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7630}
7631
f7784b8e
MT		 7632int kvm_arch_prepare_memory_region(struct kvm *kvm,
7633 struct kvm_memory_slot *memslot,
09170a49 7634 const struct kvm_userspace_memory_region *mem,
7b6195a9 7635 enum kvm_mr_change change)
0de10343 7636{
7a905b14
TY		 7637 /*
7638 * Only private memory slots need to be mapped here since
7639 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7640 */
7b6195a9 7641 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7642 unsigned long userspace_addr;
604b38ac 7643
7a905b14
TY		 7644 /*
7645 * MAP_SHARED to prevent internal slot pages from being moved
7646 * by fork()/COW.
7647 */
7b6195a9 7648 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7649 PROT_READ | PROT_WRITE,
7650 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7651
7a905b14
TY		 7652 if (IS_ERR((void *)userspace_addr))
7653 return PTR_ERR((void *)userspace_addr);
604b38ac 7654
7a905b14 7655 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7656 }
7657
f7784b8e
MT		 7658 return 0;
7659}
7660
88178fd4
KH		 7661static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7662 struct kvm_memory_slot *new)
7663{
7664 /* Still write protect RO slot */
7665 if (new->flags & KVM_MEM_READONLY) {
7666 kvm_mmu_slot_remove_write_access(kvm, new);
7667 return;
7668 }
7669
7670 /*
7671 * Call kvm_x86_ops dirty logging hooks when they are valid.
7672 *
7673 * kvm_x86_ops->slot_disable_log_dirty is called when:
7674 *
7675 * - KVM_MR_CREATE with dirty logging is disabled
7676 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7677 *
7678 * The reason is, in case of PML, we need to set D-bit for any slots
7679 * with dirty logging disabled in order to eliminate unnecessary GPA
7680 * logging in PML buffer (and potential PML buffer full VMEXT). This
7681 * guarantees leaving PML enabled during guest's lifetime won't have
7682 * any additonal overhead from PML when guest is running with dirty
7683 * logging disabled for memory slots.
7684 *
7685 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7686 * to dirty logging mode.
7687 *
7688 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7689 *
7690 * In case of write protect:
7691 *
7692 * Write protect all pages for dirty logging.
7693 *
7694 * All the sptes including the large sptes which point to this
7695 * slot are set to readonly. We can not create any new large
7696 * spte on this slot until the end of the logging.
7697 *
7698 * See the comments in fast_page_fault().
7699 */
7700 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7701 if (kvm_x86_ops->slot_enable_log_dirty)
7702 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7703 else
7704 kvm_mmu_slot_remove_write_access(kvm, new);
7705 } else {
7706 if (kvm_x86_ops->slot_disable_log_dirty)
7707 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7708 }
7709}
7710
f7784b8e 7711void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7712 const struct kvm_userspace_memory_region *mem,
8482644a 7713 const struct kvm_memory_slot *old,
f36f3f28 7714 const struct kvm_memory_slot *new,
8482644a 7715 enum kvm_mr_change change)
f7784b8e 7716{
8482644a 7717 int nr_mmu_pages = 0;
f7784b8e 7718
f36f3f28 7719 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7720 int ret;
7721
8482644a
TY		 7722 ret = vm_munmap(old->userspace_addr,
7723 old->npages * PAGE_SIZE);
f7784b8e
MT		 7724 if (ret < 0)
7725 printk(KERN_WARNING
7726 "kvm_vm_ioctl_set_memory_region: "
7727 "failed to munmap memory\n");
7728 }
7729
48c0e4e9
XG		 7730 if (!kvm->arch.n_requested_mmu_pages)
7731 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7732
48c0e4e9 7733 if (nr_mmu_pages)
0de10343 7734 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7735
3ea3b7fa
WL		 7736 /*
7737 * Dirty logging tracks sptes in 4k granularity, meaning that large
7738 * sptes have to be split. If live migration is successful, the guest
7739 * in the source machine will be destroyed and large sptes will be
7740 * created in the destination. However, if the guest continues to run
7741 * in the source machine (for example if live migration fails), small
7742 * sptes will remain around and cause bad performance.
7743 *
7744 * Scan sptes if dirty logging has been stopped, dropping those
7745 * which can be collapsed into a single large-page spte. Later
7746 * page faults will create the large-page sptes.
7747 */
7748 if ((change != KVM_MR_DELETE) &&
7749 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7750 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7751 kvm_mmu_zap_collapsible_sptes(kvm, new);
7752
c972f3b1 7753 /*
88178fd4 7754 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7755 *
88178fd4
KH		 7756 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7757 * been zapped so no dirty logging staff is needed for old slot. For
7758 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7759 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7760 *
7761 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7762 */
88178fd4 7763 if (change != KVM_MR_DELETE)
f36f3f28 7764 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7765}
1d737c8a 7766
2df72e9b 7767void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7768{
6ca18b69 7769 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7770}
7771
2df72e9b
MT		 7772void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7773 struct kvm_memory_slot *slot)
7774{
6ca18b69 7775 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7776}
7777
1d737c8a
ZX		 7778int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7779{
b6b8a145
JK		 7780 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7781 kvm_x86_ops->check_nested_events(vcpu, false);
7782
af585b92
GN		 7783 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7784 !vcpu->arch.apf.halted)
7785 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7786 || kvm_apic_has_events(vcpu)
6aef266c 7787 || vcpu->arch.pv.pv_unhalted
7460fb4a 7788 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7789 (kvm_arch_interrupt_allowed(vcpu) &&
7790 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7791}
5736199a 7792
b6d33834 7793int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7794{
b6d33834 7795 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7796}
78646121
GN		 7797
7798int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7799{
7800 return kvm_x86_ops->interrupt_allowed(vcpu);
7801}
229456fc 7802
82b32774 7803unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7804{
82b32774
NA		 7805 if (is_64_bit_mode(vcpu))
7806 return kvm_rip_read(vcpu);
7807 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7808 kvm_rip_read(vcpu));
7809}
7810EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7811
82b32774
NA		 7812bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7813{
7814 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7815}
7816EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7817
94fe45da
JK		 7818unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7819{
7820 unsigned long rflags;
7821
7822 rflags = kvm_x86_ops->get_rflags(vcpu);
7823 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7824 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7825 return rflags;
7826}
7827EXPORT_SYMBOL_GPL(kvm_get_rflags);
7828
6addfc42 7829static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7830{
7831 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7832 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7833 rflags |= X86_EFLAGS_TF;
94fe45da 7834 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7835}
7836
7837void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7838{
7839 __kvm_set_rflags(vcpu, rflags);
3842d135 7840 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7841}
7842EXPORT_SYMBOL_GPL(kvm_set_rflags);
7843
56028d08
GN		 7844void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7845{
7846 int r;
7847
fb67e14f 7848 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7849 work->wakeup_all)
56028d08
GN		 7850 return;
7851
7852 r = kvm_mmu_reload(vcpu);
7853 if (unlikely(r))
7854 return;
7855
fb67e14f
XG		 7856 if (!vcpu->arch.mmu.direct_map &&
7857 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7858 return;
7859
56028d08
GN		 7860 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7861}
7862
af585b92
GN		 7863static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7864{
7865 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7866}
7867
7868static inline u32 kvm_async_pf_next_probe(u32 key)
7869{
7870 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7871}
7872
7873static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7874{
7875 u32 key = kvm_async_pf_hash_fn(gfn);
7876
7877 while (vcpu->arch.apf.gfns[key] != ~0)
7878 key = kvm_async_pf_next_probe(key);
7879
7880 vcpu->arch.apf.gfns[key] = gfn;
7881}
7882
7883static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7884{
7885 int i;
7886 u32 key = kvm_async_pf_hash_fn(gfn);
7887
7888 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7889 (vcpu->arch.apf.gfns[key] != gfn &&
7890 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7891 key = kvm_async_pf_next_probe(key);
7892
7893 return key;
7894}
7895
7896bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7897{
7898 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7899}
7900
7901static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7902{
7903 u32 i, j, k;
7904
7905 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7906 while (true) {
7907 vcpu->arch.apf.gfns[i] = ~0;
7908 do {
7909 j = kvm_async_pf_next_probe(j);
7910 if (vcpu->arch.apf.gfns[j] == ~0)
7911 return;
7912 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7913 /*
7914 * k lies cyclically in ]i,j]
7915 * | i.k.j |
7916 * |....j i.k.| or |.k..j i...|
7917 */
7918 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7919 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7920 i = j;
7921 }
7922}
7923
7c90705b
GN		 7924static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7925{
7926
7927 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7928 sizeof(val));
7929}
7930
af585b92
GN		 7931void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7932 struct kvm_async_pf *work)
7933{
6389ee94
AK		 7934 struct x86_exception fault;
7935
7c90705b 7936 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7937 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7938
7939 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7940 (vcpu->arch.apf.send_user_only &&
7941 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7942 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7943 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7944 fault.vector = PF_VECTOR;
7945 fault.error_code_valid = true;
7946 fault.error_code = 0;
7947 fault.nested_page_fault = false;
7948 fault.address = work->arch.token;
7949 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7950 }
af585b92
GN		 7951}
7952
7953void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7954 struct kvm_async_pf *work)
7955{
6389ee94
AK		 7956 struct x86_exception fault;
7957
7c90705b 7958 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7959 if (work->wakeup_all)
7c90705b
GN		 7960 work->arch.token = ~0; /* broadcast wakeup */
7961 else
7962 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7963
7964 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7965 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7966 fault.vector = PF_VECTOR;
7967 fault.error_code_valid = true;
7968 fault.error_code = 0;
7969 fault.nested_page_fault = false;
7970 fault.address = work->arch.token;
7971 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7972 }
e6d53e3b 7973 vcpu->arch.apf.halted = false;
a4fa1635 7974 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7975}
7976
7977bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7978{
7979 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7980 return true;
7981 else
7982 return !kvm_event_needs_reinjection(vcpu) &&
7983 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7984}
7985
5544eb9b
PB		 7986void kvm_arch_start_assignment(struct kvm *kvm)
7987{
7988 atomic_inc(&kvm->arch.assigned_device_count);
7989}
7990EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
7991
7992void kvm_arch_end_assignment(struct kvm *kvm)
7993{
7994 atomic_dec(&kvm->arch.assigned_device_count);
7995}
7996EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
7997
7998bool kvm_arch_has_assigned_device(struct kvm *kvm)
7999{
8000 return atomic_read(&kvm->arch.assigned_device_count);
8001}
8002EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8003
e0f0bbc5
AW		 8004void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8005{
8006 atomic_inc(&kvm->arch.noncoherent_dma_count);
8007}
8008EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8009
8010void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8011{
8012 atomic_dec(&kvm->arch.noncoherent_dma_count);
8013}
8014EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8015
8016bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8017{
8018 return atomic_read(&kvm->arch.noncoherent_dma_count);
8019}
8020EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8021
229456fc
MT		 8022EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8023EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8024EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8025EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8026EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8027EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8028EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8029EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8030EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8031EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8032EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8033EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8034EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8035EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8036EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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