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KVM: x86: Add a common TSC scaling function
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
2acf923e
DC		 676 if (!(xcr0 & XSTATE_FP))
677 return 1;
678 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
686 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
390bd528
LJ		 690 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
691 return 1;
692
612263b3
CP		 693 if (xcr0 & XSTATE_AVX512) {
694 if (!(xcr0 & XSTATE_YMM))
695 return 1;
696 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
697 return 1;
698 }
42bdf991 699 kvm_put_guest_xcr0(vcpu);
2acf923e 700 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 701
702 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
703 kvm_update_cpuid(vcpu);
2acf923e
DC		 704 return 0;
705}
706
707int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
708{
764bcbc5
Z		 709 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
710 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 711 kvm_inject_gp(vcpu, 0);
712 return 1;
713 }
714 return 0;
715}
716EXPORT_SYMBOL_GPL(kvm_set_xcr);
717
a83b29c6 718int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 719{
fc78f519 720 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 721 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
722 X86_CR4_SMEP | X86_CR4_SMAP;
723
0f12244f
GN		 724 if (cr4 & CR4_RESERVED_BITS)
725 return 1;
a03490ed 726
2acf923e
DC		 727 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
728 return 1;
729
c68b734f
YW		 730 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
731 return 1;
732
97ec8c06
FW		 733 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
734 return 1;
735
afcbf13f 736 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 737 return 1;
738
a03490ed 739 if (is_long_mode(vcpu)) {
0f12244f
GN		 740 if (!(cr4 & X86_CR4_PAE))
741 return 1;
a2edf57f
AK		 742 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
743 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 744 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
745 kvm_read_cr3(vcpu)))
0f12244f
GN		 746 return 1;
747
ad756a16
MJ		 748 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
749 if (!guest_cpuid_has_pcid(vcpu))
750 return 1;
751
752 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
753 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
754 return 1;
755 }
756
5e1746d6 757 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 758 return 1;
a03490ed 759
ad756a16
MJ		 760 if (((cr4 ^ old_cr4) & pdptr_bits) ||
761 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 762 kvm_mmu_reset_context(vcpu);
0f12244f 763
2acf923e 764 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 765 kvm_update_cpuid(vcpu);
2acf923e 766
0f12244f
GN		 767 return 0;
768}
2d3ad1f4 769EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 770
2390218b 771int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 772{
ac146235 773#ifdef CONFIG_X86_64
9d88fca7 774 cr3 &= ~CR3_PCID_INVD;
ac146235 775#endif
9d88fca7 776
9f8fe504 777 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 778 kvm_mmu_sync_roots(vcpu);
77c3913b 779 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 780 return 0;
d835dfec
AK		 781 }
782
a03490ed 783 if (is_long_mode(vcpu)) {
d9f89b88
JK		 784 if (cr3 & CR3_L_MODE_RESERVED_BITS)
785 return 1;
786 } else if (is_pae(vcpu) && is_paging(vcpu) &&
787 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 788 return 1;
a03490ed 789
0f12244f 790 vcpu->arch.cr3 = cr3;
aff48baa 791 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 792 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 796
eea1cff9 797int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 798{
0f12244f
GN		 799 if (cr8 & CR8_RESERVED_BITS)
800 return 1;
35754c98 801 if (lapic_in_kernel(vcpu))
a03490ed
CO		 802 kvm_lapic_set_tpr(vcpu, cr8);
803 else
ad312c7c 804 vcpu->arch.cr8 = cr8;
0f12244f
GN		 805 return 0;
806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 808
2d3ad1f4 809unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 810{
35754c98 811 if (lapic_in_kernel(vcpu))
a03490ed
CO		 812 return kvm_lapic_get_cr8(vcpu);
813 else
ad312c7c 814 return vcpu->arch.cr8;
a03490ed 815}
2d3ad1f4 816EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 817
ae561ede
NA		 818static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
819{
820 int i;
821
822 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
823 for (i = 0; i < KVM_NR_DB_REGS; i++)
824 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
825 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
826 }
827}
828
73aaf249
JK		 829static void kvm_update_dr6(struct kvm_vcpu *vcpu)
830{
831 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
832 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
833}
834
c8639010
JK		 835static void kvm_update_dr7(struct kvm_vcpu *vcpu)
836{
837 unsigned long dr7;
838
839 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
840 dr7 = vcpu->arch.guest_debug_dr7;
841 else
842 dr7 = vcpu->arch.dr7;
843 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 844 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
845 if (dr7 & DR7_BP_EN_MASK)
846 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 847}
848
6f43ed01
NA		 849static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
850{
851 u64 fixed = DR6_FIXED_1;
852
853 if (!guest_cpuid_has_rtm(vcpu))
854 fixed |= DR6_RTM;
855 return fixed;
856}
857
338dbc97 858static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 859{
860 switch (dr) {
861 case 0 ... 3:
862 vcpu->arch.db[dr] = val;
863 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
864 vcpu->arch.eff_db[dr] = val;
865 break;
866 case 4:
020df079
GN		 867 /* fall through */
868 case 6:
338dbc97
GN		 869 if (val & 0xffffffff00000000ULL)
870 return -1; /* #GP */
6f43ed01 871 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 872 kvm_update_dr6(vcpu);
020df079
GN		 873 break;
874 case 5:
020df079
GN		 875 /* fall through */
876 default: /* 7 */
338dbc97
GN		 877 if (val & 0xffffffff00000000ULL)
878 return -1; /* #GP */
020df079 879 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 880 kvm_update_dr7(vcpu);
020df079
GN		 881 break;
882 }
883
884 return 0;
885}
338dbc97
GN		 886
887int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
888{
16f8a6f9 889 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 890 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 891 return 1;
892 }
893 return 0;
338dbc97 894}
020df079
GN		 895EXPORT_SYMBOL_GPL(kvm_set_dr);
896
16f8a6f9 897int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 898{
899 switch (dr) {
900 case 0 ... 3:
901 *val = vcpu->arch.db[dr];
902 break;
903 case 4:
020df079
GN		 904 /* fall through */
905 case 6:
73aaf249
JK		 906 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
907 *val = vcpu->arch.dr6;
908 else
909 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 910 break;
911 case 5:
020df079
GN		 912 /* fall through */
913 default: /* 7 */
914 *val = vcpu->arch.dr7;
915 break;
916 }
338dbc97
GN		 917 return 0;
918}
020df079
GN		 919EXPORT_SYMBOL_GPL(kvm_get_dr);
920
022cd0e8
AK		 921bool kvm_rdpmc(struct kvm_vcpu *vcpu)
922{
923 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
924 u64 data;
925 int err;
926
c6702c9d 927 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 928 if (err)
929 return err;
930 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
931 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
932 return err;
933}
934EXPORT_SYMBOL_GPL(kvm_rdpmc);
935
043405e1
CO		 936/*
937 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
938 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
939 *
940 * This list is modified at module load time to reflect the
e3267cbb 941 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 942 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
943 * may depend on host virtualization features rather than host cpu features.
043405e1 944 */
e3267cbb 945
043405e1
CO		 946static u32 msrs_to_save[] = {
947 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 948 MSR_STAR,
043405e1
CO		 949#ifdef CONFIG_X86_64
950 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
951#endif
b3897a49 952 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 953 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 954};
955
956static unsigned num_msrs_to_save;
957
62ef68bb
PB		 958static u32 emulated_msrs[] = {
959 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
960 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
961 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
962 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 963 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
964 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 965 HV_X64_MSR_RESET,
11c4b1ca 966 HV_X64_MSR_VP_INDEX,
9eec50b8 967 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 968 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
969 MSR_KVM_PV_EOI_EN,
970
ba904635 971 MSR_IA32_TSC_ADJUST,
a3e06bbe 972 MSR_IA32_TSCDEADLINE,
043405e1 973 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 974 MSR_IA32_MCG_STATUS,
975 MSR_IA32_MCG_CTL,
64d60670 976 MSR_IA32_SMBASE,
043405e1
CO		 977};
978
62ef68bb
PB		 979static unsigned num_emulated_msrs;
980
384bb783 981bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 982{
b69e8cae 983 if (efer & efer_reserved_bits)
384bb783 984 return false;
15c4a640 985
1b2fd70c
AG		 986 if (efer & EFER_FFXSR) {
987 struct kvm_cpuid_entry2 *feat;
988
989 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 990 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 991 return false;
1b2fd70c
AG		 992 }
993
d8017474
AG		 994 if (efer & EFER_SVME) {
995 struct kvm_cpuid_entry2 *feat;
996
997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 998 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 999 return false;
d8017474
AG		 1000 }
1001
384bb783
JK		 1002 return true;
1003}
1004EXPORT_SYMBOL_GPL(kvm_valid_efer);
1005
1006static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1007{
1008 u64 old_efer = vcpu->arch.efer;
1009
1010 if (!kvm_valid_efer(vcpu, efer))
1011 return 1;
1012
1013 if (is_paging(vcpu)
1014 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1015 return 1;
1016
15c4a640 1017 efer &= ~EFER_LMA;
f6801dff 1018 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1019
a3d204e2
SY		 1020 kvm_x86_ops->set_efer(vcpu, efer);
1021
aad82703
SY		 1022 /* Update reserved bits */
1023 if ((efer ^ old_efer) & EFER_NX)
1024 kvm_mmu_reset_context(vcpu);
1025
b69e8cae 1026 return 0;
15c4a640
CO		 1027}
1028
f2b4b7dd
JR		 1029void kvm_enable_efer_bits(u64 mask)
1030{
1031 efer_reserved_bits &= ~mask;
1032}
1033EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1034
15c4a640
CO		 1035/*
1036 * Writes msr value into into the appropriate "register".
1037 * Returns 0 on success, non-0 otherwise.
1038 * Assumes vcpu_load() was already called.
1039 */
8fe8ab46 1040int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1041{
854e8bb1
NA		 1042 switch (msr->index) {
1043 case MSR_FS_BASE:
1044 case MSR_GS_BASE:
1045 case MSR_KERNEL_GS_BASE:
1046 case MSR_CSTAR:
1047 case MSR_LSTAR:
1048 if (is_noncanonical_address(msr->data))
1049 return 1;
1050 break;
1051 case MSR_IA32_SYSENTER_EIP:
1052 case MSR_IA32_SYSENTER_ESP:
1053 /*
1054 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1055 * non-canonical address is written on Intel but not on
1056 * AMD (which ignores the top 32-bits, because it does
1057 * not implement 64-bit SYSENTER).
1058 *
1059 * 64-bit code should hence be able to write a non-canonical
1060 * value on AMD. Making the address canonical ensures that
1061 * vmentry does not fail on Intel after writing a non-canonical
1062 * value, and that something deterministic happens if the guest
1063 * invokes 64-bit SYSENTER.
1064 */
1065 msr->data = get_canonical(msr->data);
1066 }
8fe8ab46 1067 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1068}
854e8bb1 1069EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1070
313a3dc7
CO		 1071/*
1072 * Adapt set_msr() to msr_io()'s calling convention
1073 */
609e36d3
PB		 1074static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1075{
1076 struct msr_data msr;
1077 int r;
1078
1079 msr.index = index;
1080 msr.host_initiated = true;
1081 r = kvm_get_msr(vcpu, &msr);
1082 if (r)
1083 return r;
1084
1085 *data = msr.data;
1086 return 0;
1087}
1088
313a3dc7
CO		 1089static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1090{
8fe8ab46
WA		 1091 struct msr_data msr;
1092
1093 msr.data = *data;
1094 msr.index = index;
1095 msr.host_initiated = true;
1096 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1097}
1098
16e8d74d
MT		 1099#ifdef CONFIG_X86_64
1100struct pvclock_gtod_data {
1101 seqcount_t seq;
1102
1103 struct { /* extract of a clocksource struct */
1104 int vclock_mode;
1105 cycle_t cycle_last;
1106 cycle_t mask;
1107 u32 mult;
1108 u32 shift;
1109 } clock;
1110
cbcf2dd3
TG		 1111 u64 boot_ns;
1112 u64 nsec_base;
16e8d74d
MT		 1113};
1114
1115static struct pvclock_gtod_data pvclock_gtod_data;
1116
1117static void update_pvclock_gtod(struct timekeeper *tk)
1118{
1119 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1120 u64 boot_ns;
1121
876e7881 1122 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1123
1124 write_seqcount_begin(&vdata->seq);
1125
1126 /* copy pvclock gtod data */
876e7881
PZ		 1127 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1128 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1129 vdata->clock.mask = tk->tkr_mono.mask;
1130 vdata->clock.mult = tk->tkr_mono.mult;
1131 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1132
cbcf2dd3 1133 vdata->boot_ns = boot_ns;
876e7881 1134 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1135
1136 write_seqcount_end(&vdata->seq);
1137}
1138#endif
1139
bab5bb39
NK		 1140void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1141{
1142 /*
1143 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1144 * vcpu_enter_guest. This function is only called from
1145 * the physical CPU that is running vcpu.
1146 */
1147 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1148}
16e8d74d 1149
18068523
GOC		 1150static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1151{
9ed3c444
AK		 1152 int version;
1153 int r;
50d0a0f9 1154 struct pvclock_wall_clock wc;
923de3cf 1155 struct timespec boot;
18068523
GOC		 1156
1157 if (!wall_clock)
1158 return;
1159
9ed3c444
AK		 1160 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1161 if (r)
1162 return;
1163
1164 if (version & 1)
1165 ++version; /* first time write, random junk */
1166
1167 ++version;
18068523 1168
18068523
GOC		 1169 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1170
50d0a0f9
GH		 1171 /*
1172 * The guest calculates current wall clock time by adding
34c238a1 1173 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1174 * wall clock specified here. guest system time equals host
1175 * system time for us, thus we must fill in host boot time here.
1176 */
923de3cf 1177 getboottime(&boot);
50d0a0f9 1178
4b648665
BR		 1179 if (kvm->arch.kvmclock_offset) {
1180 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1181 boot = timespec_sub(boot, ts);
1182 }
50d0a0f9
GH		 1183 wc.sec = boot.tv_sec;
1184 wc.nsec = boot.tv_nsec;
1185 wc.version = version;
18068523
GOC		 1186
1187 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1188
1189 version++;
1190 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1191}
1192
50d0a0f9
GH		 1193static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1194{
1195 uint32_t quotient, remainder;
1196
1197 /* Don't try to replace with do_div(), this one calculates
1198 * "(dividend << 32) / divisor" */
1199 __asm__ ( "divl %4"
1200 : "=a" (quotient), "=d" (remainder)
1201 : "0" (0), "1" (dividend), "r" (divisor) );
1202 return quotient;
1203}
1204
5f4e3f88
ZA		 1205static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1206 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1207{
5f4e3f88 1208 uint64_t scaled64;
50d0a0f9
GH		 1209 int32_t shift = 0;
1210 uint64_t tps64;
1211 uint32_t tps32;
1212
5f4e3f88
ZA		 1213 tps64 = base_khz * 1000LL;
1214 scaled64 = scaled_khz * 1000LL;
50933623 1215 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1216 tps64 >>= 1;
1217 shift--;
1218 }
1219
1220 tps32 = (uint32_t)tps64;
50933623
JK		 1221 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1222 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1223 scaled64 >>= 1;
1224 else
1225 tps32 <<= 1;
50d0a0f9
GH		 1226 shift++;
1227 }
1228
5f4e3f88
ZA		 1229 *pshift = shift;
1230 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1231
5f4e3f88
ZA		 1232 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1233 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1234}
1235
d828199e 1236#ifdef CONFIG_X86_64
16e8d74d 1237static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1238#endif
16e8d74d 1239
c8076604 1240static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1241static unsigned long max_tsc_khz;
c8076604 1242
cc578287 1243static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1244{
cc578287
ZA		 1245 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1246 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1247}
1248
cc578287 1249static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1250{
cc578287
ZA		 1251 u64 v = (u64)khz * (1000000 + ppm);
1252 do_div(v, 1000000);
1253 return v;
1e993611
JR		 1254}
1255
cc578287 1256static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1257{
cc578287
ZA		 1258 u32 thresh_lo, thresh_hi;
1259 int use_scaling = 0;
217fc9cf 1260
03ba32ca 1261 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1262 if (this_tsc_khz == 0) {
1263 /* set tsc_scaling_ratio to a safe value */
1264 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
03ba32ca 1265 return;
ad721883 1266 }
03ba32ca 1267
c285545f
ZA		 1268 /* Compute a scale to convert nanoseconds in TSC cycles */
1269 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1270 &vcpu->arch.virtual_tsc_shift,
1271 &vcpu->arch.virtual_tsc_mult);
1272 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1273
1274 /*
1275 * Compute the variation in TSC rate which is acceptable
1276 * within the range of tolerance and decide if the
1277 * rate being applied is within that bounds of the hardware
1278 * rate. If so, no scaling or compensation need be done.
1279 */
1280 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1281 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1282 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1283 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1284 use_scaling = 1;
1285 }
1286 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1287}
1288
1289static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1290{
e26101b1 1291 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1292 vcpu->arch.virtual_tsc_mult,
1293 vcpu->arch.virtual_tsc_shift);
e26101b1 1294 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1295 return tsc;
1296}
1297
69b0049a 1298static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1299{
1300#ifdef CONFIG_X86_64
1301 bool vcpus_matched;
b48aa97e
MT		 1302 struct kvm_arch *ka = &vcpu->kvm->arch;
1303 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1304
1305 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1306 atomic_read(&vcpu->kvm->online_vcpus));
1307
7f187922
MT		 1308 /*
1309 * Once the masterclock is enabled, always perform request in
1310 * order to update it.
1311 *
1312 * In order to enable masterclock, the host clocksource must be TSC
1313 * and the vcpus need to have matched TSCs. When that happens,
1314 * perform request to enable masterclock.
1315 */
1316 if (ka->use_master_clock ||
1317 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1318 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1319
1320 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1321 atomic_read(&vcpu->kvm->online_vcpus),
1322 ka->use_master_clock, gtod->clock.vclock_mode);
1323#endif
1324}
1325
ba904635
WA		 1326static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1327{
1328 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1329 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1330}
1331
35181e86
HZ		 1332/*
1333 * Multiply tsc by a fixed point number represented by ratio.
1334 *
1335 * The most significant 64-N bits (mult) of ratio represent the
1336 * integral part of the fixed point number; the remaining N bits
1337 * (frac) represent the fractional part, ie. ratio represents a fixed
1338 * point number (mult + frac * 2^(-N)).
1339 *
1340 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1341 */
1342static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1343{
1344 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1345}
1346
1347u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1348{
1349 u64 _tsc = tsc;
1350 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1351
1352 if (ratio != kvm_default_tsc_scaling_ratio)
1353 _tsc = __scale_tsc(ratio, tsc);
1354
1355 return _tsc;
1356}
1357EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1358
8fe8ab46 1359void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1360{
1361 struct kvm *kvm = vcpu->kvm;
f38e098f 1362 u64 offset, ns, elapsed;
99e3e30a 1363 unsigned long flags;
02626b6a 1364 s64 usdiff;
b48aa97e 1365 bool matched;
0d3da0d2 1366 bool already_matched;
8fe8ab46 1367 u64 data = msr->data;
99e3e30a 1368
038f8c11 1369 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1370 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1371 ns = get_kernel_ns();
f38e098f 1372 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1373
03ba32ca 1374 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1375 int faulted = 0;
1376
03ba32ca
MT		 1377 /* n.b - signed multiplication and division required */
1378 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1379#ifdef CONFIG_X86_64
03ba32ca 1380 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1381#else
03ba32ca 1382 /* do_div() only does unsigned */
8915aa27
MT		 1383 asm("1: idivl %[divisor]\n"
1384 "2: xor %%edx, %%edx\n"
1385 " movl $0, %[faulted]\n"
1386 "3:\n"
1387 ".section .fixup,\"ax\"\n"
1388 "4: movl $1, %[faulted]\n"
1389 " jmp 3b\n"
1390 ".previous\n"
1391
1392 _ASM_EXTABLE(1b, 4b)
1393
1394 : "=A"(usdiff), [faulted] "=r" (faulted)
1395 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1396
5d3cb0f6 1397#endif
03ba32ca
MT		 1398 do_div(elapsed, 1000);
1399 usdiff -= elapsed;
1400 if (usdiff < 0)
1401 usdiff = -usdiff;
8915aa27
MT		 1402
1403 /* idivl overflow => difference is larger than USEC_PER_SEC */
1404 if (faulted)
1405 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1406 } else
1407 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1408
1409 /*
5d3cb0f6
ZA		 1410 * Special case: TSC write with a small delta (1 second) of virtual
1411 * cycle time against real time is interpreted as an attempt to
1412 * synchronize the CPU.
1413 *
1414 * For a reliable TSC, we can match TSC offsets, and for an unstable
1415 * TSC, we add elapsed time in this computation. We could let the
1416 * compensation code attempt to catch up if we fall behind, but
1417 * it's better to try to match offsets from the beginning.
1418 */
02626b6a 1419 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1420 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1421 if (!check_tsc_unstable()) {
e26101b1 1422 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1423 pr_debug("kvm: matched tsc offset for %llu\n", data);
1424 } else {
857e4099 1425 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1426 data += delta;
1427 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1428 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1429 }
b48aa97e 1430 matched = true;
0d3da0d2 1431 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1432 } else {
1433 /*
1434 * We split periods of matched TSC writes into generations.
1435 * For each generation, we track the original measured
1436 * nanosecond time, offset, and write, so if TSCs are in
1437 * sync, we can match exact offset, and if not, we can match
4a969980 1438 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1439 *
1440 * These values are tracked in kvm->arch.cur_xxx variables.
1441 */
1442 kvm->arch.cur_tsc_generation++;
1443 kvm->arch.cur_tsc_nsec = ns;
1444 kvm->arch.cur_tsc_write = data;
1445 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1446 matched = false;
0d3da0d2 1447 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1448 kvm->arch.cur_tsc_generation, data);
f38e098f 1449 }
e26101b1
ZA		 1450
1451 /*
1452 * We also track th most recent recorded KHZ, write and time to
1453 * allow the matching interval to be extended at each write.
1454 */
f38e098f
ZA		 1455 kvm->arch.last_tsc_nsec = ns;
1456 kvm->arch.last_tsc_write = data;
5d3cb0f6 1457 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1458
b183aa58 1459 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1460
1461 /* Keep track of which generation this VCPU has synchronized to */
1462 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1463 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1464 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1465
ba904635
WA		 1466 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1467 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1468 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1469 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1470
1471 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1472 if (!matched) {
b48aa97e 1473 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1474 } else if (!already_matched) {
1475 kvm->arch.nr_vcpus_matched_tsc++;
1476 }
b48aa97e
MT		 1477
1478 kvm_track_tsc_matching(vcpu);
1479 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1480}
e26101b1 1481
99e3e30a
ZA		 1482EXPORT_SYMBOL_GPL(kvm_write_tsc);
1483
d828199e
MT		 1484#ifdef CONFIG_X86_64
1485
1486static cycle_t read_tsc(void)
1487{
03b9730b
AL		 1488 cycle_t ret = (cycle_t)rdtsc_ordered();
1489 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1490
1491 if (likely(ret >= last))
1492 return ret;
1493
1494 /*
1495 * GCC likes to generate cmov here, but this branch is extremely
1496 * predictable (it's just a funciton of time and the likely is
1497 * very likely) and there's a data dependence, so force GCC
1498 * to generate a branch instead. I don't barrier() because
1499 * we don't actually need a barrier, and if this function
1500 * ever gets inlined it will generate worse code.
1501 */
1502 asm volatile ("");
1503 return last;
1504}
1505
1506static inline u64 vgettsc(cycle_t *cycle_now)
1507{
1508 long v;
1509 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1510
1511 *cycle_now = read_tsc();
1512
1513 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1514 return v * gtod->clock.mult;
1515}
1516
cbcf2dd3 1517static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1518{
cbcf2dd3 1519 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1520 unsigned long seq;
d828199e 1521 int mode;
cbcf2dd3 1522 u64 ns;
d828199e 1523
d828199e
MT		 1524 do {
1525 seq = read_seqcount_begin(&gtod->seq);
1526 mode = gtod->clock.vclock_mode;
cbcf2dd3 1527 ns = gtod->nsec_base;
d828199e
MT		 1528 ns += vgettsc(cycle_now);
1529 ns >>= gtod->clock.shift;
cbcf2dd3 1530 ns += gtod->boot_ns;
d828199e 1531 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1532 *t = ns;
d828199e
MT		 1533
1534 return mode;
1535}
1536
1537/* returns true if host is using tsc clocksource */
1538static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1539{
d828199e
MT		 1540 /* checked again under seqlock below */
1541 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1542 return false;
1543
cbcf2dd3 1544 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1545}
1546#endif
1547
1548/*
1549 *
b48aa97e
MT		 1550 * Assuming a stable TSC across physical CPUS, and a stable TSC
1551 * across virtual CPUs, the following condition is possible.
1552 * Each numbered line represents an event visible to both
d828199e
MT		 1553 * CPUs at the next numbered event.
1554 *
1555 * "timespecX" represents host monotonic time. "tscX" represents
1556 * RDTSC value.
1557 *
1558 * VCPU0 on CPU0 | VCPU1 on CPU1
1559 *
1560 * 1. read timespec0,tsc0
1561 * 2. | timespec1 = timespec0 + N
1562 * | tsc1 = tsc0 + M
1563 * 3. transition to guest | transition to guest
1564 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1565 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1566 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1567 *
1568 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1569 *
1570 * - ret0 < ret1
1571 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1572 * ...
1573 * - 0 < N - M => M < N
1574 *
1575 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1576 * always the case (the difference between two distinct xtime instances
1577 * might be smaller then the difference between corresponding TSC reads,
1578 * when updating guest vcpus pvclock areas).
1579 *
1580 * To avoid that problem, do not allow visibility of distinct
1581 * system_timestamp/tsc_timestamp values simultaneously: use a master
1582 * copy of host monotonic time values. Update that master copy
1583 * in lockstep.
1584 *
b48aa97e 1585 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1586 *
1587 */
1588
1589static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1590{
1591#ifdef CONFIG_X86_64
1592 struct kvm_arch *ka = &kvm->arch;
1593 int vclock_mode;
b48aa97e
MT		 1594 bool host_tsc_clocksource, vcpus_matched;
1595
1596 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1597 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1598
1599 /*
1600 * If the host uses TSC clock, then passthrough TSC as stable
1601 * to the guest.
1602 */
b48aa97e 1603 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1604 &ka->master_kernel_ns,
1605 &ka->master_cycle_now);
1606
16a96021 1607 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1608 && !backwards_tsc_observed
1609 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1610
d828199e
MT		 1611 if (ka->use_master_clock)
1612 atomic_set(&kvm_guest_has_master_clock, 1);
1613
1614 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1615 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1616 vcpus_matched);
d828199e
MT		 1617#endif
1618}
1619
2e762ff7
MT		 1620static void kvm_gen_update_masterclock(struct kvm *kvm)
1621{
1622#ifdef CONFIG_X86_64
1623 int i;
1624 struct kvm_vcpu *vcpu;
1625 struct kvm_arch *ka = &kvm->arch;
1626
1627 spin_lock(&ka->pvclock_gtod_sync_lock);
1628 kvm_make_mclock_inprogress_request(kvm);
1629 /* no guest entries from this point */
1630 pvclock_update_vm_gtod_copy(kvm);
1631
1632 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1633 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1634
1635 /* guest entries allowed */
1636 kvm_for_each_vcpu(i, vcpu, kvm)
1637 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1638
1639 spin_unlock(&ka->pvclock_gtod_sync_lock);
1640#endif
1641}
1642
34c238a1 1643static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1644{
d828199e 1645 unsigned long flags, this_tsc_khz;
18068523 1646 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1647 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1648 s64 kernel_ns;
d828199e 1649 u64 tsc_timestamp, host_tsc;
0b79459b 1650 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1651 u8 pvclock_flags;
d828199e
MT		 1652 bool use_master_clock;
1653
1654 kernel_ns = 0;
1655 host_tsc = 0;
18068523 1656
d828199e
MT		 1657 /*
1658 * If the host uses TSC clock, then passthrough TSC as stable
1659 * to the guest.
1660 */
1661 spin_lock(&ka->pvclock_gtod_sync_lock);
1662 use_master_clock = ka->use_master_clock;
1663 if (use_master_clock) {
1664 host_tsc = ka->master_cycle_now;
1665 kernel_ns = ka->master_kernel_ns;
1666 }
1667 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1668
1669 /* Keep irq disabled to prevent changes to the clock */
1670 local_irq_save(flags);
89cbc767 1671 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1672 if (unlikely(this_tsc_khz == 0)) {
1673 local_irq_restore(flags);
1674 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1675 return 1;
1676 }
d828199e 1677 if (!use_master_clock) {
4ea1636b 1678 host_tsc = rdtsc();
d828199e
MT		 1679 kernel_ns = get_kernel_ns();
1680 }
1681
1682 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1683
c285545f
ZA		 1684 /*
1685 * We may have to catch up the TSC to match elapsed wall clock
1686 * time for two reasons, even if kvmclock is used.
1687 * 1) CPU could have been running below the maximum TSC rate
1688 * 2) Broken TSC compensation resets the base at each VCPU
1689 * entry to avoid unknown leaps of TSC even when running
1690 * again on the same CPU. This may cause apparent elapsed
1691 * time to disappear, and the guest to stand still or run
1692 * very slowly.
1693 */
1694 if (vcpu->tsc_catchup) {
1695 u64 tsc = compute_guest_tsc(v, kernel_ns);
1696 if (tsc > tsc_timestamp) {
f1e2b260 1697 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1698 tsc_timestamp = tsc;
1699 }
50d0a0f9
GH		 1700 }
1701
18068523
GOC		 1702 local_irq_restore(flags);
1703
0b79459b 1704 if (!vcpu->pv_time_enabled)
c285545f 1705 return 0;
18068523 1706
e48672fa 1707 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1708 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1709 &vcpu->hv_clock.tsc_shift,
1710 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1711 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1712 }
1713
1714 /* With all the info we got, fill in the values */
1d5f066e 1715 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1716 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1717 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1718
09a0c3f1
OH		 1719 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1720 &guest_hv_clock, sizeof(guest_hv_clock))))
1721 return 0;
1722
5dca0d91
RK		 1723 /* This VCPU is paused, but it's legal for a guest to read another
1724 * VCPU's kvmclock, so we really have to follow the specification where
1725 * it says that version is odd if data is being modified, and even after
1726 * it is consistent.
1727 *
1728 * Version field updates must be kept separate. This is because
1729 * kvm_write_guest_cached might use a "rep movs" instruction, and
1730 * writes within a string instruction are weakly ordered. So there
1731 * are three writes overall.
1732 *
1733 * As a small optimization, only write the version field in the first
1734 * and third write. The vcpu->pv_time cache is still valid, because the
1735 * version field is the first in the struct.
18068523 1736 */
5dca0d91
RK		 1737 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1738
1739 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1740 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1741 &vcpu->hv_clock,
1742 sizeof(vcpu->hv_clock.version));
1743
1744 smp_wmb();
78c0337a
MT		 1745
1746 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1747 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1748
1749 if (vcpu->pvclock_set_guest_stopped_request) {
1750 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1751 vcpu->pvclock_set_guest_stopped_request = false;
1752 }
1753
d828199e
MT		 1754 /* If the host uses TSC clocksource, then it is stable */
1755 if (use_master_clock)
1756 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1757
78c0337a
MT		 1758 vcpu->hv_clock.flags = pvclock_flags;
1759
ce1a5e60
DM		 1760 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1761
0b79459b
AH		 1762 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1763 &vcpu->hv_clock,
1764 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1765
1766 smp_wmb();
1767
1768 vcpu->hv_clock.version++;
1769 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1770 &vcpu->hv_clock,
1771 sizeof(vcpu->hv_clock.version));
8cfdc000 1772 return 0;
c8076604
GH		 1773}
1774
0061d53d
MT		 1775/*
1776 * kvmclock updates which are isolated to a given vcpu, such as
1777 * vcpu->cpu migration, should not allow system_timestamp from
1778 * the rest of the vcpus to remain static. Otherwise ntp frequency
1779 * correction applies to one vcpu's system_timestamp but not
1780 * the others.
1781 *
1782 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1783 * We need to rate-limit these requests though, as they can
1784 * considerably slow guests that have a large number of vcpus.
1785 * The time for a remote vcpu to update its kvmclock is bound
1786 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1787 */
1788
7e44e449
AJ		 1789#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1790
1791static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1792{
1793 int i;
7e44e449
AJ		 1794 struct delayed_work *dwork = to_delayed_work(work);
1795 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1796 kvmclock_update_work);
1797 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1798 struct kvm_vcpu *vcpu;
1799
1800 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1801 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1802 kvm_vcpu_kick(vcpu);
1803 }
1804}
1805
7e44e449
AJ		 1806static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1807{
1808 struct kvm *kvm = v->kvm;
1809
105b21bb 1810 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1811 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1812 KVMCLOCK_UPDATE_DELAY);
1813}
1814
332967a3
AJ		 1815#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1816
1817static void kvmclock_sync_fn(struct work_struct *work)
1818{
1819 struct delayed_work *dwork = to_delayed_work(work);
1820 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1821 kvmclock_sync_work);
1822 struct kvm *kvm = container_of(ka, struct kvm, arch);
1823
630994b3
MT		 1824 if (!kvmclock_periodic_sync)
1825 return;
1826
332967a3
AJ		 1827 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1828 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1829 KVMCLOCK_SYNC_PERIOD);
1830}
1831
890ca9ae 1832static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1833{
890ca9ae
HY		 1834 u64 mcg_cap = vcpu->arch.mcg_cap;
1835 unsigned bank_num = mcg_cap & 0xff;
1836
15c4a640 1837 switch (msr) {
15c4a640 1838 case MSR_IA32_MCG_STATUS:
890ca9ae 1839 vcpu->arch.mcg_status = data;
15c4a640 1840 break;
c7ac679c 1841 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1842 if (!(mcg_cap & MCG_CTL_P))
1843 return 1;
1844 if (data != 0 && data != ~(u64)0)
1845 return -1;
1846 vcpu->arch.mcg_ctl = data;
1847 break;
1848 default:
1849 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1850 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1851 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1852 /* only 0 or all 1s can be written to IA32_MCi_CTL
1853 * some Linux kernels though clear bit 10 in bank 4 to
1854 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1855 * this to avoid an uncatched #GP in the guest
1856 */
890ca9ae 1857 if ((offset & 0x3) == 0 &&
114be429 1858 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1859 return -1;
1860 vcpu->arch.mce_banks[offset] = data;
1861 break;
1862 }
1863 return 1;
1864 }
1865 return 0;
1866}
1867
ffde22ac
ES		 1868static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1869{
1870 struct kvm *kvm = vcpu->kvm;
1871 int lm = is_long_mode(vcpu);
1872 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1873 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1874 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1875 : kvm->arch.xen_hvm_config.blob_size_32;
1876 u32 page_num = data & ~PAGE_MASK;
1877 u64 page_addr = data & PAGE_MASK;
1878 u8 *page;
1879 int r;
1880
1881 r = -E2BIG;
1882 if (page_num >= blob_size)
1883 goto out;
1884 r = -ENOMEM;
ff5c2c03
SL		 1885 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1886 if (IS_ERR(page)) {
1887 r = PTR_ERR(page);
ffde22ac 1888 goto out;
ff5c2c03 1889 }
54bf36aa 1890 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1891 goto out_free;
1892 r = 0;
1893out_free:
1894 kfree(page);
1895out:
1896 return r;
1897}
1898
344d9588
GN		 1899static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1900{
1901 gpa_t gpa = data & ~0x3f;
1902
4a969980 1903 /* Bits 2:5 are reserved, Should be zero */
6adba527 1904 if (data & 0x3c)
344d9588
GN		 1905 return 1;
1906
1907 vcpu->arch.apf.msr_val = data;
1908
1909 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1910 kvm_clear_async_pf_completion_queue(vcpu);
1911 kvm_async_pf_hash_reset(vcpu);
1912 return 0;
1913 }
1914
8f964525
AH		 1915 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1916 sizeof(u32)))
344d9588
GN		 1917 return 1;
1918
6adba527 1919 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1920 kvm_async_pf_wakeup_all(vcpu);
1921 return 0;
1922}
1923
12f9a48f
GC		 1924static void kvmclock_reset(struct kvm_vcpu *vcpu)
1925{
0b79459b 1926 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1927}
1928
c9aaa895
GC		 1929static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1930{
1931 u64 delta;
1932
1933 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1934 return;
1935
1936 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1937 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1938 vcpu->arch.st.accum_steal = delta;
1939}
1940
1941static void record_steal_time(struct kvm_vcpu *vcpu)
1942{
7cae2bed
MT		 1943 accumulate_steal_time(vcpu);
1944
c9aaa895
GC		 1945 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1946 return;
1947
1948 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1949 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1950 return;
1951
1952 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1953 vcpu->arch.st.steal.version += 2;
1954 vcpu->arch.st.accum_steal = 0;
1955
1956 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1957 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1958}
1959
8fe8ab46 1960int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1961{
5753785f 1962 bool pr = false;
8fe8ab46
WA		 1963 u32 msr = msr_info->index;
1964 u64 data = msr_info->data;
5753785f 1965
15c4a640 1966 switch (msr) {
2e32b719
BP		 1967 case MSR_AMD64_NB_CFG:
1968 case MSR_IA32_UCODE_REV:
1969 case MSR_IA32_UCODE_WRITE:
1970 case MSR_VM_HSAVE_PA:
1971 case MSR_AMD64_PATCH_LOADER:
1972 case MSR_AMD64_BU_CFG2:
1973 break;
1974
15c4a640 1975 case MSR_EFER:
b69e8cae 1976 return set_efer(vcpu, data);
8f1589d9
AP		 1977 case MSR_K7_HWCR:
1978 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1979 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1980 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1981 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1982 if (data != 0) {
a737f256
CD		 1983 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1984 data);
8f1589d9
AP		 1985 return 1;
1986 }
15c4a640 1987 break;
f7c6d140
AP		 1988 case MSR_FAM10H_MMIO_CONF_BASE:
1989 if (data != 0) {
a737f256
CD		 1990 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1991 "0x%llx\n", data);
f7c6d140
AP		 1992 return 1;
1993 }
15c4a640 1994 break;
b5e2fec0
AG		 1995 case MSR_IA32_DEBUGCTLMSR:
1996 if (!data) {
1997 /* We support the non-activated case already */
1998 break;
1999 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2000 /* Values other than LBR and BTF are vendor-specific,
2001 thus reserved and should throw a #GP */
2002 return 1;
2003 }
a737f256
CD		 2004 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2005 __func__, data);
b5e2fec0 2006 break;
9ba075a6 2007 case 0x200 ... 0x2ff:
ff53604b 2008 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2009 case MSR_IA32_APICBASE:
58cb628d 2010 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2011 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2012 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2013 case MSR_IA32_TSCDEADLINE:
2014 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2015 break;
ba904635
WA		 2016 case MSR_IA32_TSC_ADJUST:
2017 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2018 if (!msr_info->host_initiated) {
d913b904 2019 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2020 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2021 }
2022 vcpu->arch.ia32_tsc_adjust_msr = data;
2023 }
2024 break;
15c4a640 2025 case MSR_IA32_MISC_ENABLE:
ad312c7c 2026 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2027 break;
64d60670
PB		 2028 case MSR_IA32_SMBASE:
2029 if (!msr_info->host_initiated)
2030 return 1;
2031 vcpu->arch.smbase = data;
2032 break;
11c6bffa 2033 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2034 case MSR_KVM_WALL_CLOCK:
2035 vcpu->kvm->arch.wall_clock = data;
2036 kvm_write_wall_clock(vcpu->kvm, data);
2037 break;
11c6bffa 2038 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2039 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2040 u64 gpa_offset;
54750f2c
MT		 2041 struct kvm_arch *ka = &vcpu->kvm->arch;
2042
12f9a48f 2043 kvmclock_reset(vcpu);
18068523 2044
54750f2c
MT		 2045 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2046 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2047
2048 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2049 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2050 &vcpu->requests);
2051
2052 ka->boot_vcpu_runs_old_kvmclock = tmp;
2053 }
2054
18068523 2055 vcpu->arch.time = data;
0061d53d 2056 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2057
2058 /* we verify if the enable bit is set... */
2059 if (!(data & 1))
2060 break;
2061
0b79459b 2062 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2063
0b79459b 2064 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2065 &vcpu->arch.pv_time, data & ~1ULL,
2066 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2067 vcpu->arch.pv_time_enabled = false;
2068 else
2069 vcpu->arch.pv_time_enabled = true;
32cad84f 2070
18068523
GOC		 2071 break;
2072 }
344d9588
GN		 2073 case MSR_KVM_ASYNC_PF_EN:
2074 if (kvm_pv_enable_async_pf(vcpu, data))
2075 return 1;
2076 break;
c9aaa895
GC		 2077 case MSR_KVM_STEAL_TIME:
2078
2079 if (unlikely(!sched_info_on()))
2080 return 1;
2081
2082 if (data & KVM_STEAL_RESERVED_MASK)
2083 return 1;
2084
2085 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2086 data & KVM_STEAL_VALID_BITS,
2087 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2088 return 1;
2089
2090 vcpu->arch.st.msr_val = data;
2091
2092 if (!(data & KVM_MSR_ENABLED))
2093 break;
2094
c9aaa895
GC		 2095 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2096
2097 break;
ae7a2a3f
MT		 2098 case MSR_KVM_PV_EOI_EN:
2099 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2100 return 1;
2101 break;
c9aaa895 2102
890ca9ae
HY		 2103 case MSR_IA32_MCG_CTL:
2104 case MSR_IA32_MCG_STATUS:
81760dcc 2105 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2106 return set_msr_mce(vcpu, msr, data);
71db6023 2107
6912ac32
WH		 2108 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2109 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2110 pr = true; /* fall through */
2111 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2112 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2113 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2114 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2115
2116 if (pr || data != 0)
a737f256
CD		 2117 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2118 "0x%x data 0x%llx\n", msr, data);
5753785f 2119 break;
84e0cefa
JS		 2120 case MSR_K7_CLK_CTL:
2121 /*
2122 * Ignore all writes to this no longer documented MSR.
2123 * Writes are only relevant for old K7 processors,
2124 * all pre-dating SVM, but a recommended workaround from
4a969980 2125 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2126 * affected processor models on the command line, hence
2127 * the need to ignore the workaround.
2128 */
2129 break;
55cd8e5a 2130 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2131 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2132 case HV_X64_MSR_CRASH_CTL:
2133 return kvm_hv_set_msr_common(vcpu, msr, data,
2134 msr_info->host_initiated);
91c9c3ed 2135 case MSR_IA32_BBL_CR_CTL3:
2136 /* Drop writes to this legacy MSR -- see rdmsr
2137 * counterpart for further detail.
2138 */
a737f256 2139 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2140 break;
2b036c6b
BO		 2141 case MSR_AMD64_OSVW_ID_LENGTH:
2142 if (!guest_cpuid_has_osvw(vcpu))
2143 return 1;
2144 vcpu->arch.osvw.length = data;
2145 break;
2146 case MSR_AMD64_OSVW_STATUS:
2147 if (!guest_cpuid_has_osvw(vcpu))
2148 return 1;
2149 vcpu->arch.osvw.status = data;
2150 break;
15c4a640 2151 default:
ffde22ac
ES		 2152 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2153 return xen_hvm_config(vcpu, data);
c6702c9d 2154 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2155 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2156 if (!ignore_msrs) {
a737f256
CD		 2157 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2158 msr, data);
ed85c068
AP		 2159 return 1;
2160 } else {
a737f256
CD		 2161 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2162 msr, data);
ed85c068
AP		 2163 break;
2164 }
15c4a640
CO		 2165 }
2166 return 0;
2167}
2168EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2169
2170
2171/*
2172 * Reads an msr value (of 'msr_index') into 'pdata'.
2173 * Returns 0 on success, non-0 otherwise.
2174 * Assumes vcpu_load() was already called.
2175 */
609e36d3 2176int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2177{
609e36d3 2178 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2179}
ff651cb6 2180EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2181
890ca9ae 2182static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2183{
2184 u64 data;
890ca9ae
HY		 2185 u64 mcg_cap = vcpu->arch.mcg_cap;
2186 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2187
2188 switch (msr) {
15c4a640
CO		 2189 case MSR_IA32_P5_MC_ADDR:
2190 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2191 data = 0;
2192 break;
15c4a640 2193 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2194 data = vcpu->arch.mcg_cap;
2195 break;
c7ac679c 2196 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2197 if (!(mcg_cap & MCG_CTL_P))
2198 return 1;
2199 data = vcpu->arch.mcg_ctl;
2200 break;
2201 case MSR_IA32_MCG_STATUS:
2202 data = vcpu->arch.mcg_status;
2203 break;
2204 default:
2205 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2206 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2207 u32 offset = msr - MSR_IA32_MC0_CTL;
2208 data = vcpu->arch.mce_banks[offset];
2209 break;
2210 }
2211 return 1;
2212 }
2213 *pdata = data;
2214 return 0;
2215}
2216
609e36d3 2217int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2218{
609e36d3 2219 switch (msr_info->index) {
890ca9ae 2220 case MSR_IA32_PLATFORM_ID:
15c4a640 2221 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2222 case MSR_IA32_DEBUGCTLMSR:
2223 case MSR_IA32_LASTBRANCHFROMIP:
2224 case MSR_IA32_LASTBRANCHTOIP:
2225 case MSR_IA32_LASTINTFROMIP:
2226 case MSR_IA32_LASTINTTOIP:
60af2ecd 2227 case MSR_K8_SYSCFG:
3afb1121
PB		 2228 case MSR_K8_TSEG_ADDR:
2229 case MSR_K8_TSEG_MASK:
60af2ecd 2230 case MSR_K7_HWCR:
61a6bd67 2231 case MSR_VM_HSAVE_PA:
1fdbd48c 2232 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2233 case MSR_AMD64_NB_CFG:
f7c6d140 2234 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2235 case MSR_AMD64_BU_CFG2:
609e36d3 2236 msr_info->data = 0;
15c4a640 2237 break;
6912ac32
WH		 2238 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2239 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2240 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2241 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2242 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2243 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2244 msr_info->data = 0;
5753785f 2245 break;
742bc670 2246 case MSR_IA32_UCODE_REV:
609e36d3 2247 msr_info->data = 0x100000000ULL;
742bc670 2248 break;
9ba075a6 2249 case MSR_MTRRcap:
9ba075a6 2250 case 0x200 ... 0x2ff:
ff53604b 2251 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2252 case 0xcd: /* fsb frequency */
609e36d3 2253 msr_info->data = 3;
15c4a640 2254 break;
7b914098
JS		 2255 /*
2256 * MSR_EBC_FREQUENCY_ID
2257 * Conservative value valid for even the basic CPU models.
2258 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2259 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2260 * and 266MHz for model 3, or 4. Set Core Clock
2261 * Frequency to System Bus Frequency Ratio to 1 (bits
2262 * 31:24) even though these are only valid for CPU
2263 * models > 2, however guests may end up dividing or
2264 * multiplying by zero otherwise.
2265 */
2266 case MSR_EBC_FREQUENCY_ID:
609e36d3 2267 msr_info->data = 1 << 24;
7b914098 2268 break;
15c4a640 2269 case MSR_IA32_APICBASE:
609e36d3 2270 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2271 break;
0105d1a5 2272 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2273 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2274 break;
a3e06bbe 2275 case MSR_IA32_TSCDEADLINE:
609e36d3 2276 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2277 break;
ba904635 2278 case MSR_IA32_TSC_ADJUST:
609e36d3 2279 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2280 break;
15c4a640 2281 case MSR_IA32_MISC_ENABLE:
609e36d3 2282 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2283 break;
64d60670
PB		 2284 case MSR_IA32_SMBASE:
2285 if (!msr_info->host_initiated)
2286 return 1;
2287 msr_info->data = vcpu->arch.smbase;
15c4a640 2288 break;
847f0ad8
AG		 2289 case MSR_IA32_PERF_STATUS:
2290 /* TSC increment by tick */
609e36d3 2291 msr_info->data = 1000ULL;
847f0ad8 2292 /* CPU multiplier */
b0996ae4 2293 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2294 break;
15c4a640 2295 case MSR_EFER:
609e36d3 2296 msr_info->data = vcpu->arch.efer;
15c4a640 2297 break;
18068523 2298 case MSR_KVM_WALL_CLOCK:
11c6bffa 2299 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2300 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2301 break;
2302 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2303 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2304 msr_info->data = vcpu->arch.time;
18068523 2305 break;
344d9588 2306 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2307 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2308 break;
c9aaa895 2309 case MSR_KVM_STEAL_TIME:
609e36d3 2310 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2311 break;
1d92128f 2312 case MSR_KVM_PV_EOI_EN:
609e36d3 2313 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2314 break;
890ca9ae
HY		 2315 case MSR_IA32_P5_MC_ADDR:
2316 case MSR_IA32_P5_MC_TYPE:
2317 case MSR_IA32_MCG_CAP:
2318 case MSR_IA32_MCG_CTL:
2319 case MSR_IA32_MCG_STATUS:
81760dcc 2320 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2321 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2322 case MSR_K7_CLK_CTL:
2323 /*
2324 * Provide expected ramp-up count for K7. All other
2325 * are set to zero, indicating minimum divisors for
2326 * every field.
2327 *
2328 * This prevents guest kernels on AMD host with CPU
2329 * type 6, model 8 and higher from exploding due to
2330 * the rdmsr failing.
2331 */
609e36d3 2332 msr_info->data = 0x20000000;
84e0cefa 2333 break;
55cd8e5a 2334 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2335 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2336 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2337 return kvm_hv_get_msr_common(vcpu,
2338 msr_info->index, &msr_info->data);
55cd8e5a 2339 break;
91c9c3ed 2340 case MSR_IA32_BBL_CR_CTL3:
2341 /* This legacy MSR exists but isn't fully documented in current
2342 * silicon. It is however accessed by winxp in very narrow
2343 * scenarios where it sets bit #19, itself documented as
2344 * a "reserved" bit. Best effort attempt to source coherent
2345 * read data here should the balance of the register be
2346 * interpreted by the guest:
2347 *
2348 * L2 cache control register 3: 64GB range, 256KB size,
2349 * enabled, latency 0x1, configured
2350 */
609e36d3 2351 msr_info->data = 0xbe702111;
91c9c3ed 2352 break;
2b036c6b
BO		 2353 case MSR_AMD64_OSVW_ID_LENGTH:
2354 if (!guest_cpuid_has_osvw(vcpu))
2355 return 1;
609e36d3 2356 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2357 break;
2358 case MSR_AMD64_OSVW_STATUS:
2359 if (!guest_cpuid_has_osvw(vcpu))
2360 return 1;
609e36d3 2361 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2362 break;
15c4a640 2363 default:
c6702c9d 2364 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2365 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2366 if (!ignore_msrs) {
609e36d3 2367 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2368 return 1;
2369 } else {
609e36d3
PB		 2370 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2371 msr_info->data = 0;
ed85c068
AP		 2372 }
2373 break;
15c4a640 2374 }
15c4a640
CO		 2375 return 0;
2376}
2377EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2378
313a3dc7
CO		 2379/*
2380 * Read or write a bunch of msrs. All parameters are kernel addresses.
2381 *
2382 * @return number of msrs set successfully.
2383 */
2384static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2385 struct kvm_msr_entry *entries,
2386 int (*do_msr)(struct kvm_vcpu *vcpu,
2387 unsigned index, u64 *data))
2388{
f656ce01 2389 int i, idx;
313a3dc7 2390
f656ce01 2391 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2392 for (i = 0; i < msrs->nmsrs; ++i)
2393 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2394 break;
f656ce01 2395 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2396
313a3dc7
CO		 2397 return i;
2398}
2399
2400/*
2401 * Read or write a bunch of msrs. Parameters are user addresses.
2402 *
2403 * @return number of msrs set successfully.
2404 */
2405static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2406 int (*do_msr)(struct kvm_vcpu *vcpu,
2407 unsigned index, u64 *data),
2408 int writeback)
2409{
2410 struct kvm_msrs msrs;
2411 struct kvm_msr_entry *entries;
2412 int r, n;
2413 unsigned size;
2414
2415 r = -EFAULT;
2416 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2417 goto out;
2418
2419 r = -E2BIG;
2420 if (msrs.nmsrs >= MAX_IO_MSRS)
2421 goto out;
2422
313a3dc7 2423 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2424 entries = memdup_user(user_msrs->entries, size);
2425 if (IS_ERR(entries)) {
2426 r = PTR_ERR(entries);
313a3dc7 2427 goto out;
ff5c2c03 2428 }
313a3dc7
CO		 2429
2430 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2431 if (r < 0)
2432 goto out_free;
2433
2434 r = -EFAULT;
2435 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2436 goto out_free;
2437
2438 r = n;
2439
2440out_free:
7a73c028 2441 kfree(entries);
313a3dc7
CO		 2442out:
2443 return r;
2444}
2445
784aa3d7 2446int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2447{
2448 int r;
2449
2450 switch (ext) {
2451 case KVM_CAP_IRQCHIP:
2452 case KVM_CAP_HLT:
2453 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2454 case KVM_CAP_SET_TSS_ADDR:
07716717 2455 case KVM_CAP_EXT_CPUID:
9c15bb1d 2456 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2457 case KVM_CAP_CLOCKSOURCE:
7837699f 2458 case KVM_CAP_PIT:
a28e4f5a 2459 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2460 case KVM_CAP_MP_STATE:
ed848624 2461 case KVM_CAP_SYNC_MMU:
a355c85c 2462 case KVM_CAP_USER_NMI:
52d939a0 2463 case KVM_CAP_REINJECT_CONTROL:
4925663a 2464 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2465 case KVM_CAP_IOEVENTFD:
f848a5a8 2466 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2467 case KVM_CAP_PIT2:
e9f42757 2468 case KVM_CAP_PIT_STATE2:
b927a3ce 2469 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2470 case KVM_CAP_XEN_HVM:
afbcf7ab 2471 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2472 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2473 case KVM_CAP_HYPERV:
10388a07 2474 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2475 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2476 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2477 case KVM_CAP_DEBUGREGS:
d2be1651 2478 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2479 case KVM_CAP_XSAVE:
344d9588 2480 case KVM_CAP_ASYNC_PF:
92a1f12d 2481 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2482 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2483 case KVM_CAP_READONLY_MEM:
5f66b620 2484 case KVM_CAP_HYPERV_TIME:
100943c5 2485 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2486 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2487 case KVM_CAP_ENABLE_CAP_VM:
2488 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2489 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2490 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2491#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2492 case KVM_CAP_ASSIGN_DEV_IRQ:
2493 case KVM_CAP_PCI_2_3:
2494#endif
018d00d2
ZX		 2495 r = 1;
2496 break;
6d396b55
PB		 2497 case KVM_CAP_X86_SMM:
2498 /* SMBASE is usually relocated above 1M on modern chipsets,
2499 * and SMM handlers might indeed rely on 4G segment limits,
2500 * so do not report SMM to be available if real mode is
2501 * emulated via vm86 mode. Still, do not go to great lengths
2502 * to avoid userspace's usage of the feature, because it is a
2503 * fringe case that is not enabled except via specific settings
2504 * of the module parameters.
2505 */
2506 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2507 break;
542472b5
LV		 2508 case KVM_CAP_COALESCED_MMIO:
2509 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2510 break;
774ead3a
AK		 2511 case KVM_CAP_VAPIC:
2512 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2513 break;
f725230a 2514 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2515 r = KVM_SOFT_MAX_VCPUS;
2516 break;
2517 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2518 r = KVM_MAX_VCPUS;
2519 break;
a988b910 2520 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2521 r = KVM_USER_MEM_SLOTS;
a988b910 2522 break;
a68a6a72
MT		 2523 case KVM_CAP_PV_MMU: /* obsolete */
2524 r = 0;
2f333bcb 2525 break;
4cee4b72 2526#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2527 case KVM_CAP_IOMMU:
a1b60c1c 2528 r = iommu_present(&pci_bus_type);
62c476c7 2529 break;
4cee4b72 2530#endif
890ca9ae
HY		 2531 case KVM_CAP_MCE:
2532 r = KVM_MAX_MCE_BANKS;
2533 break;
2d5b5a66
SY		 2534 case KVM_CAP_XCRS:
2535 r = cpu_has_xsave;
2536 break;
92a1f12d
JR		 2537 case KVM_CAP_TSC_CONTROL:
2538 r = kvm_has_tsc_control;
2539 break;
018d00d2
ZX		 2540 default:
2541 r = 0;
2542 break;
2543 }
2544 return r;
2545
2546}
2547
043405e1
CO		 2548long kvm_arch_dev_ioctl(struct file *filp,
2549 unsigned int ioctl, unsigned long arg)
2550{
2551 void __user *argp = (void __user *)arg;
2552 long r;
2553
2554 switch (ioctl) {
2555 case KVM_GET_MSR_INDEX_LIST: {
2556 struct kvm_msr_list __user *user_msr_list = argp;
2557 struct kvm_msr_list msr_list;
2558 unsigned n;
2559
2560 r = -EFAULT;
2561 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2562 goto out;
2563 n = msr_list.nmsrs;
62ef68bb 2564 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2565 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2566 goto out;
2567 r = -E2BIG;
e125e7b6 2568 if (n < msr_list.nmsrs)
043405e1
CO		 2569 goto out;
2570 r = -EFAULT;
2571 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2572 num_msrs_to_save * sizeof(u32)))
2573 goto out;
e125e7b6 2574 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2575 &emulated_msrs,
62ef68bb 2576 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2577 goto out;
2578 r = 0;
2579 break;
2580 }
9c15bb1d
BP		 2581 case KVM_GET_SUPPORTED_CPUID:
2582 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2583 struct kvm_cpuid2 __user *cpuid_arg = argp;
2584 struct kvm_cpuid2 cpuid;
2585
2586 r = -EFAULT;
2587 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2588 goto out;
9c15bb1d
BP		 2589
2590 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2591 ioctl);
674eea0f
AK		 2592 if (r)
2593 goto out;
2594
2595 r = -EFAULT;
2596 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2597 goto out;
2598 r = 0;
2599 break;
2600 }
890ca9ae
HY		 2601 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2602 u64 mce_cap;
2603
2604 mce_cap = KVM_MCE_CAP_SUPPORTED;
2605 r = -EFAULT;
2606 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2607 goto out;
2608 r = 0;
2609 break;
2610 }
043405e1
CO		 2611 default:
2612 r = -EINVAL;
2613 }
2614out:
2615 return r;
2616}
2617
f5f48ee1
SY		 2618static void wbinvd_ipi(void *garbage)
2619{
2620 wbinvd();
2621}
2622
2623static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2624{
e0f0bbc5 2625 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2626}
2627
313a3dc7
CO		 2628void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2629{
f5f48ee1
SY		 2630 /* Address WBINVD may be executed by guest */
2631 if (need_emulate_wbinvd(vcpu)) {
2632 if (kvm_x86_ops->has_wbinvd_exit())
2633 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2634 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2635 smp_call_function_single(vcpu->cpu,
2636 wbinvd_ipi, NULL, 1);
2637 }
2638
313a3dc7 2639 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2640
0dd6a6ed
ZA		 2641 /* Apply any externally detected TSC adjustments (due to suspend) */
2642 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2643 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2644 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2645 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2646 }
8f6055cb 2647
48434c20 2648 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2649 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2650 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2651 if (tsc_delta < 0)
2652 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2653 if (check_tsc_unstable()) {
b183aa58
ZA		 2654 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2655 vcpu->arch.last_guest_tsc);
2656 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2657 vcpu->arch.tsc_catchup = 1;
c285545f 2658 }
d98d07ca
MT		 2659 /*
2660 * On a host with synchronized TSC, there is no need to update
2661 * kvmclock on vcpu->cpu migration
2662 */
2663 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2664 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2665 if (vcpu->cpu != cpu)
2666 kvm_migrate_timers(vcpu);
e48672fa 2667 vcpu->cpu = cpu;
6b7d7e76 2668 }
c9aaa895 2669
c9aaa895 2670 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2671}
2672
2673void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2674{
02daab21 2675 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2676 kvm_put_guest_fpu(vcpu);
4ea1636b 2677 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2678}
2679
313a3dc7
CO		 2680static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2681 struct kvm_lapic_state *s)
2682{
5a71785d 2683 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2684 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2685
2686 return 0;
2687}
2688
2689static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2690 struct kvm_lapic_state *s)
2691{
64eb0620 2692 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2693 update_cr8_intercept(vcpu);
313a3dc7
CO		 2694
2695 return 0;
2696}
2697
f77bc6a4
ZX		 2698static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2699 struct kvm_interrupt *irq)
2700{
02cdb50f 2701 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2702 return -EINVAL;
1c1a9ce9
SR		 2703
2704 if (!irqchip_in_kernel(vcpu->kvm)) {
2705 kvm_queue_interrupt(vcpu, irq->irq, false);
2706 kvm_make_request(KVM_REQ_EVENT, vcpu);
2707 return 0;
2708 }
2709
2710 /*
2711 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2712 * fail for in-kernel 8259.
2713 */
2714 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2715 return -ENXIO;
f77bc6a4 2716
1c1a9ce9
SR		 2717 if (vcpu->arch.pending_external_vector != -1)
2718 return -EEXIST;
f77bc6a4 2719
1c1a9ce9 2720 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2721 return 0;
2722}
2723
c4abb7c9
JK		 2724static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2725{
c4abb7c9 2726 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2727
2728 return 0;
2729}
2730
f077825a
PB		 2731static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2732{
64d60670
PB		 2733 kvm_make_request(KVM_REQ_SMI, vcpu);
2734
f077825a
PB		 2735 return 0;
2736}
2737
b209749f
AK		 2738static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2739 struct kvm_tpr_access_ctl *tac)
2740{
2741 if (tac->flags)
2742 return -EINVAL;
2743 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2744 return 0;
2745}
2746
890ca9ae
HY		 2747static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2748 u64 mcg_cap)
2749{
2750 int r;
2751 unsigned bank_num = mcg_cap & 0xff, bank;
2752
2753 r = -EINVAL;
a9e38c3e 2754 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2755 goto out;
2756 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2757 goto out;
2758 r = 0;
2759 vcpu->arch.mcg_cap = mcg_cap;
2760 /* Init IA32_MCG_CTL to all 1s */
2761 if (mcg_cap & MCG_CTL_P)
2762 vcpu->arch.mcg_ctl = ~(u64)0;
2763 /* Init IA32_MCi_CTL to all 1s */
2764 for (bank = 0; bank < bank_num; bank++)
2765 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2766out:
2767 return r;
2768}
2769
2770static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2771 struct kvm_x86_mce *mce)
2772{
2773 u64 mcg_cap = vcpu->arch.mcg_cap;
2774 unsigned bank_num = mcg_cap & 0xff;
2775 u64 *banks = vcpu->arch.mce_banks;
2776
2777 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2778 return -EINVAL;
2779 /*
2780 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2781 * reporting is disabled
2782 */
2783 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2784 vcpu->arch.mcg_ctl != ~(u64)0)
2785 return 0;
2786 banks += 4 * mce->bank;
2787 /*
2788 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2789 * reporting is disabled for the bank
2790 */
2791 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2792 return 0;
2793 if (mce->status & MCI_STATUS_UC) {
2794 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2795 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2796 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2797 return 0;
2798 }
2799 if (banks[1] & MCI_STATUS_VAL)
2800 mce->status |= MCI_STATUS_OVER;
2801 banks[2] = mce->addr;
2802 banks[3] = mce->misc;
2803 vcpu->arch.mcg_status = mce->mcg_status;
2804 banks[1] = mce->status;
2805 kvm_queue_exception(vcpu, MC_VECTOR);
2806 } else if (!(banks[1] & MCI_STATUS_VAL)
2807 || !(banks[1] & MCI_STATUS_UC)) {
2808 if (banks[1] & MCI_STATUS_VAL)
2809 mce->status |= MCI_STATUS_OVER;
2810 banks[2] = mce->addr;
2811 banks[3] = mce->misc;
2812 banks[1] = mce->status;
2813 } else
2814 banks[1] |= MCI_STATUS_OVER;
2815 return 0;
2816}
2817
3cfc3092
JK		 2818static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2819 struct kvm_vcpu_events *events)
2820{
7460fb4a 2821 process_nmi(vcpu);
03b82a30
JK		 2822 events->exception.injected =
2823 vcpu->arch.exception.pending &&
2824 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2825 events->exception.nr = vcpu->arch.exception.nr;
2826 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2827 events->exception.pad = 0;
3cfc3092
JK		 2828 events->exception.error_code = vcpu->arch.exception.error_code;
2829
03b82a30
JK		 2830 events->interrupt.injected =
2831 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2832 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2833 events->interrupt.soft = 0;
37ccdcbe 2834 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2835
2836 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2837 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2838 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2839 events->nmi.pad = 0;
3cfc3092 2840
66450a21 2841 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2842
f077825a
PB		 2843 events->smi.smm = is_smm(vcpu);
2844 events->smi.pending = vcpu->arch.smi_pending;
2845 events->smi.smm_inside_nmi =
2846 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2847 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2848
dab4b911 2849 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2850 | KVM_VCPUEVENT_VALID_SHADOW
2851 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2852 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2853}
2854
2855static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2856 struct kvm_vcpu_events *events)
2857{
dab4b911 2858 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2859 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2860 | KVM_VCPUEVENT_VALID_SHADOW
2861 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2862 return -EINVAL;
2863
7460fb4a 2864 process_nmi(vcpu);
3cfc3092
JK		 2865 vcpu->arch.exception.pending = events->exception.injected;
2866 vcpu->arch.exception.nr = events->exception.nr;
2867 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2868 vcpu->arch.exception.error_code = events->exception.error_code;
2869
2870 vcpu->arch.interrupt.pending = events->interrupt.injected;
2871 vcpu->arch.interrupt.nr = events->interrupt.nr;
2872 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2873 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2874 kvm_x86_ops->set_interrupt_shadow(vcpu,
2875 events->interrupt.shadow);
3cfc3092
JK		 2876
2877 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2878 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2879 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2880 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2881
66450a21
JK		 2882 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2883 kvm_vcpu_has_lapic(vcpu))
2884 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2885
f077825a
PB		 2886 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2887 if (events->smi.smm)
2888 vcpu->arch.hflags |= HF_SMM_MASK;
2889 else
2890 vcpu->arch.hflags &= ~HF_SMM_MASK;
2891 vcpu->arch.smi_pending = events->smi.pending;
2892 if (events->smi.smm_inside_nmi)
2893 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2894 else
2895 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2896 if (kvm_vcpu_has_lapic(vcpu)) {
2897 if (events->smi.latched_init)
2898 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2899 else
2900 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2901 }
2902 }
2903
3842d135
AK		 2904 kvm_make_request(KVM_REQ_EVENT, vcpu);
2905
3cfc3092
JK		 2906 return 0;
2907}
2908
a1efbe77
JK		 2909static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2910 struct kvm_debugregs *dbgregs)
2911{
73aaf249
JK		 2912 unsigned long val;
2913
a1efbe77 2914 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2915 kvm_get_dr(vcpu, 6, &val);
73aaf249 2916 dbgregs->dr6 = val;
a1efbe77
JK		 2917 dbgregs->dr7 = vcpu->arch.dr7;
2918 dbgregs->flags = 0;
97e69aa6 2919 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2920}
2921
2922static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2923 struct kvm_debugregs *dbgregs)
2924{
2925 if (dbgregs->flags)
2926 return -EINVAL;
2927
a1efbe77 2928 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2929 kvm_update_dr0123(vcpu);
a1efbe77 2930 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2931 kvm_update_dr6(vcpu);
a1efbe77 2932 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2933 kvm_update_dr7(vcpu);
a1efbe77 2934
a1efbe77
JK		 2935 return 0;
2936}
2937
df1daba7
PB		 2938#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2939
2940static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2941{
c47ada30 2942 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2943 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2944 u64 valid;
2945
2946 /*
2947 * Copy legacy XSAVE area, to avoid complications with CPUID
2948 * leaves 0 and 1 in the loop below.
2949 */
2950 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2951
2952 /* Set XSTATE_BV */
2953 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2954
2955 /*
2956 * Copy each region from the possibly compacted offset to the
2957 * non-compacted offset.
2958 */
2959 valid = xstate_bv & ~XSTATE_FPSSE;
2960 while (valid) {
2961 u64 feature = valid & -valid;
2962 int index = fls64(feature) - 1;
2963 void *src = get_xsave_addr(xsave, feature);
2964
2965 if (src) {
2966 u32 size, offset, ecx, edx;
2967 cpuid_count(XSTATE_CPUID, index,
2968 &size, &offset, &ecx, &edx);
2969 memcpy(dest + offset, src, size);
2970 }
2971
2972 valid -= feature;
2973 }
2974}
2975
2976static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2977{
c47ada30 2978 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2979 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2980 u64 valid;
2981
2982 /*
2983 * Copy legacy XSAVE area, to avoid complications with CPUID
2984 * leaves 0 and 1 in the loop below.
2985 */
2986 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2987
2988 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2989 xsave->header.xfeatures = xstate_bv;
df1daba7 2990 if (cpu_has_xsaves)
3a54450b 2991 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2992
2993 /*
2994 * Copy each region from the non-compacted offset to the
2995 * possibly compacted offset.
2996 */
2997 valid = xstate_bv & ~XSTATE_FPSSE;
2998 while (valid) {
2999 u64 feature = valid & -valid;
3000 int index = fls64(feature) - 1;
3001 void *dest = get_xsave_addr(xsave, feature);
3002
3003 if (dest) {
3004 u32 size, offset, ecx, edx;
3005 cpuid_count(XSTATE_CPUID, index,
3006 &size, &offset, &ecx, &edx);
3007 memcpy(dest, src + offset, size);
ee4100da 3008 }
df1daba7
PB		 3009
3010 valid -= feature;
3011 }
3012}
3013
2d5b5a66
SY		 3014static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3015 struct kvm_xsave *guest_xsave)
3016{
4344ee98 3017 if (cpu_has_xsave) {
df1daba7
PB		 3018 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3019 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3020 } else {
2d5b5a66 3021 memcpy(guest_xsave->region,
7366ed77 3022 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3023 sizeof(struct fxregs_state));
2d5b5a66
SY		 3024 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3025 XSTATE_FPSSE;
3026 }
3027}
3028
3029static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3030 struct kvm_xsave *guest_xsave)
3031{
3032 u64 xstate_bv =
3033 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3034
d7876f1b
PB		 3035 if (cpu_has_xsave) {
3036 /*
3037 * Here we allow setting states that are not present in
3038 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3039 * with old userspace.
3040 */
4ff41732 3041 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3042 return -EINVAL;
df1daba7 3043 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3044 } else {
2d5b5a66
SY		 3045 if (xstate_bv & ~XSTATE_FPSSE)
3046 return -EINVAL;
7366ed77 3047 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3048 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3049 }
3050 return 0;
3051}
3052
3053static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3054 struct kvm_xcrs *guest_xcrs)
3055{
3056 if (!cpu_has_xsave) {
3057 guest_xcrs->nr_xcrs = 0;
3058 return;
3059 }
3060
3061 guest_xcrs->nr_xcrs = 1;
3062 guest_xcrs->flags = 0;
3063 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3064 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3065}
3066
3067static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3068 struct kvm_xcrs *guest_xcrs)
3069{
3070 int i, r = 0;
3071
3072 if (!cpu_has_xsave)
3073 return -EINVAL;
3074
3075 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3076 return -EINVAL;
3077
3078 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3079 /* Only support XCR0 currently */
c67a04cb 3080 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3081 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3082 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3083 break;
3084 }
3085 if (r)
3086 r = -EINVAL;
3087 return r;
3088}
3089
1c0b28c2
EM		 3090/*
3091 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3092 * stopped by the hypervisor. This function will be called from the host only.
3093 * EINVAL is returned when the host attempts to set the flag for a guest that
3094 * does not support pv clocks.
3095 */
3096static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3097{
0b79459b 3098 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3099 return -EINVAL;
51d59c6b 3100 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3101 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3102 return 0;
3103}
3104
313a3dc7
CO		 3105long kvm_arch_vcpu_ioctl(struct file *filp,
3106 unsigned int ioctl, unsigned long arg)
3107{
3108 struct kvm_vcpu *vcpu = filp->private_data;
3109 void __user *argp = (void __user *)arg;
3110 int r;
d1ac91d8
AK		 3111 union {
3112 struct kvm_lapic_state *lapic;
3113 struct kvm_xsave *xsave;
3114 struct kvm_xcrs *xcrs;
3115 void *buffer;
3116 } u;
3117
3118 u.buffer = NULL;
313a3dc7
CO		 3119 switch (ioctl) {
3120 case KVM_GET_LAPIC: {
2204ae3c
MT		 3121 r = -EINVAL;
3122 if (!vcpu->arch.apic)
3123 goto out;
d1ac91d8 3124 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3125
b772ff36 3126 r = -ENOMEM;
d1ac91d8 3127 if (!u.lapic)
b772ff36 3128 goto out;
d1ac91d8 3129 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3130 if (r)
3131 goto out;
3132 r = -EFAULT;
d1ac91d8 3133 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3134 goto out;
3135 r = 0;
3136 break;
3137 }
3138 case KVM_SET_LAPIC: {
2204ae3c
MT		 3139 r = -EINVAL;
3140 if (!vcpu->arch.apic)
3141 goto out;
ff5c2c03 3142 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3143 if (IS_ERR(u.lapic))
3144 return PTR_ERR(u.lapic);
ff5c2c03 3145
d1ac91d8 3146 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3147 break;
3148 }
f77bc6a4
ZX		 3149 case KVM_INTERRUPT: {
3150 struct kvm_interrupt irq;
3151
3152 r = -EFAULT;
3153 if (copy_from_user(&irq, argp, sizeof irq))
3154 goto out;
3155 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3156 break;
3157 }
c4abb7c9
JK		 3158 case KVM_NMI: {
3159 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3160 break;
3161 }
f077825a
PB		 3162 case KVM_SMI: {
3163 r = kvm_vcpu_ioctl_smi(vcpu);
3164 break;
3165 }
313a3dc7
CO		 3166 case KVM_SET_CPUID: {
3167 struct kvm_cpuid __user *cpuid_arg = argp;
3168 struct kvm_cpuid cpuid;
3169
3170 r = -EFAULT;
3171 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3172 goto out;
3173 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3174 break;
3175 }
07716717
DK		 3176 case KVM_SET_CPUID2: {
3177 struct kvm_cpuid2 __user *cpuid_arg = argp;
3178 struct kvm_cpuid2 cpuid;
3179
3180 r = -EFAULT;
3181 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3182 goto out;
3183 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3184 cpuid_arg->entries);
07716717
DK		 3185 break;
3186 }
3187 case KVM_GET_CPUID2: {
3188 struct kvm_cpuid2 __user *cpuid_arg = argp;
3189 struct kvm_cpuid2 cpuid;
3190
3191 r = -EFAULT;
3192 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3193 goto out;
3194 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3195 cpuid_arg->entries);
07716717
DK		 3196 if (r)
3197 goto out;
3198 r = -EFAULT;
3199 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3200 goto out;
3201 r = 0;
3202 break;
3203 }
313a3dc7 3204 case KVM_GET_MSRS:
609e36d3 3205 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3206 break;
3207 case KVM_SET_MSRS:
3208 r = msr_io(vcpu, argp, do_set_msr, 0);
3209 break;
b209749f
AK		 3210 case KVM_TPR_ACCESS_REPORTING: {
3211 struct kvm_tpr_access_ctl tac;
3212
3213 r = -EFAULT;
3214 if (copy_from_user(&tac, argp, sizeof tac))
3215 goto out;
3216 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3217 if (r)
3218 goto out;
3219 r = -EFAULT;
3220 if (copy_to_user(argp, &tac, sizeof tac))
3221 goto out;
3222 r = 0;
3223 break;
3224 };
b93463aa
AK		 3225 case KVM_SET_VAPIC_ADDR: {
3226 struct kvm_vapic_addr va;
3227
3228 r = -EINVAL;
35754c98 3229 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3230 goto out;
3231 r = -EFAULT;
3232 if (copy_from_user(&va, argp, sizeof va))
3233 goto out;
fda4e2e8 3234 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3235 break;
3236 }
890ca9ae
HY		 3237 case KVM_X86_SETUP_MCE: {
3238 u64 mcg_cap;
3239
3240 r = -EFAULT;
3241 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3242 goto out;
3243 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3244 break;
3245 }
3246 case KVM_X86_SET_MCE: {
3247 struct kvm_x86_mce mce;
3248
3249 r = -EFAULT;
3250 if (copy_from_user(&mce, argp, sizeof mce))
3251 goto out;
3252 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3253 break;
3254 }
3cfc3092
JK		 3255 case KVM_GET_VCPU_EVENTS: {
3256 struct kvm_vcpu_events events;
3257
3258 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3259
3260 r = -EFAULT;
3261 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3262 break;
3263 r = 0;
3264 break;
3265 }
3266 case KVM_SET_VCPU_EVENTS: {
3267 struct kvm_vcpu_events events;
3268
3269 r = -EFAULT;
3270 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3271 break;
3272
3273 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3274 break;
3275 }
a1efbe77
JK		 3276 case KVM_GET_DEBUGREGS: {
3277 struct kvm_debugregs dbgregs;
3278
3279 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3280
3281 r = -EFAULT;
3282 if (copy_to_user(argp, &dbgregs,
3283 sizeof(struct kvm_debugregs)))
3284 break;
3285 r = 0;
3286 break;
3287 }
3288 case KVM_SET_DEBUGREGS: {
3289 struct kvm_debugregs dbgregs;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&dbgregs, argp,
3293 sizeof(struct kvm_debugregs)))
3294 break;
3295
3296 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3297 break;
3298 }
2d5b5a66 3299 case KVM_GET_XSAVE: {
d1ac91d8 3300 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3301 r = -ENOMEM;
d1ac91d8 3302 if (!u.xsave)
2d5b5a66
SY		 3303 break;
3304
d1ac91d8 3305 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3306
3307 r = -EFAULT;
d1ac91d8 3308 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3309 break;
3310 r = 0;
3311 break;
3312 }
3313 case KVM_SET_XSAVE: {
ff5c2c03 3314 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3315 if (IS_ERR(u.xsave))
3316 return PTR_ERR(u.xsave);
2d5b5a66 3317
d1ac91d8 3318 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3319 break;
3320 }
3321 case KVM_GET_XCRS: {
d1ac91d8 3322 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3323 r = -ENOMEM;
d1ac91d8 3324 if (!u.xcrs)
2d5b5a66
SY		 3325 break;
3326
d1ac91d8 3327 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3328
3329 r = -EFAULT;
d1ac91d8 3330 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3331 sizeof(struct kvm_xcrs)))
3332 break;
3333 r = 0;
3334 break;
3335 }
3336 case KVM_SET_XCRS: {
ff5c2c03 3337 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3338 if (IS_ERR(u.xcrs))
3339 return PTR_ERR(u.xcrs);
2d5b5a66 3340
d1ac91d8 3341 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3342 break;
3343 }
92a1f12d
JR		 3344 case KVM_SET_TSC_KHZ: {
3345 u32 user_tsc_khz;
3346
3347 r = -EINVAL;
92a1f12d
JR		 3348 user_tsc_khz = (u32)arg;
3349
3350 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3351 goto out;
3352
cc578287
ZA		 3353 if (user_tsc_khz == 0)
3354 user_tsc_khz = tsc_khz;
3355
3356 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3357
3358 r = 0;
3359 goto out;
3360 }
3361 case KVM_GET_TSC_KHZ: {
cc578287 3362 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3363 goto out;
3364 }
1c0b28c2
EM		 3365 case KVM_KVMCLOCK_CTRL: {
3366 r = kvm_set_guest_paused(vcpu);
3367 goto out;
3368 }
313a3dc7
CO		 3369 default:
3370 r = -EINVAL;
3371 }
3372out:
d1ac91d8 3373 kfree(u.buffer);
313a3dc7
CO		 3374 return r;
3375}
3376
5b1c1493
CO		 3377int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3378{
3379 return VM_FAULT_SIGBUS;
3380}
3381
1fe779f8
CO		 3382static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3383{
3384 int ret;
3385
3386 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3387 return -EINVAL;
1fe779f8
CO		 3388 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3389 return ret;
3390}
3391
b927a3ce
SY		 3392static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3393 u64 ident_addr)
3394{
3395 kvm->arch.ept_identity_map_addr = ident_addr;
3396 return 0;
3397}
3398
1fe779f8
CO		 3399static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3400 u32 kvm_nr_mmu_pages)
3401{
3402 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3403 return -EINVAL;
3404
79fac95e 3405 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3406
3407 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3408 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3409
79fac95e 3410 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3411 return 0;
3412}
3413
3414static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3415{
39de71ec 3416 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3417}
3418
1fe779f8
CO		 3419static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3420{
3421 int r;
3422
3423 r = 0;
3424 switch (chip->chip_id) {
3425 case KVM_IRQCHIP_PIC_MASTER:
3426 memcpy(&chip->chip.pic,
3427 &pic_irqchip(kvm)->pics[0],
3428 sizeof(struct kvm_pic_state));
3429 break;
3430 case KVM_IRQCHIP_PIC_SLAVE:
3431 memcpy(&chip->chip.pic,
3432 &pic_irqchip(kvm)->pics[1],
3433 sizeof(struct kvm_pic_state));
3434 break;
3435 case KVM_IRQCHIP_IOAPIC:
eba0226b 3436 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3437 break;
3438 default:
3439 r = -EINVAL;
3440 break;
3441 }
3442 return r;
3443}
3444
3445static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3446{
3447 int r;
3448
3449 r = 0;
3450 switch (chip->chip_id) {
3451 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3452 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3453 memcpy(&pic_irqchip(kvm)->pics[0],
3454 &chip->chip.pic,
3455 sizeof(struct kvm_pic_state));
f4f51050 3456 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3457 break;
3458 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3459 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3460 memcpy(&pic_irqchip(kvm)->pics[1],
3461 &chip->chip.pic,
3462 sizeof(struct kvm_pic_state));
f4f51050 3463 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3464 break;
3465 case KVM_IRQCHIP_IOAPIC:
eba0226b 3466 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3467 break;
3468 default:
3469 r = -EINVAL;
3470 break;
3471 }
3472 kvm_pic_update_irq(pic_irqchip(kvm));
3473 return r;
3474}
3475
e0f63cb9
SY		 3476static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3477{
894a9c55 3478 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3479 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3480 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3481 return 0;
e0f63cb9
SY		 3482}
3483
3484static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3485{
894a9c55 3486 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3487 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3488 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3489 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3490 return 0;
e9f42757
BK		 3491}
3492
3493static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3494{
e9f42757
BK		 3495 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3496 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3497 sizeof(ps->channels));
3498 ps->flags = kvm->arch.vpit->pit_state.flags;
3499 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3500 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3501 return 0;
e9f42757
BK		 3502}
3503
3504static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3505{
2da29bcc 3506 int start = 0;
e9f42757
BK		 3507 u32 prev_legacy, cur_legacy;
3508 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3509 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3510 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3511 if (!prev_legacy && cur_legacy)
3512 start = 1;
3513 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3514 sizeof(kvm->arch.vpit->pit_state.channels));
3515 kvm->arch.vpit->pit_state.flags = ps->flags;
3516 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3517 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3518 return 0;
e0f63cb9
SY		 3519}
3520
52d939a0
MT		 3521static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3522 struct kvm_reinject_control *control)
3523{
3524 if (!kvm->arch.vpit)
3525 return -ENXIO;
894a9c55 3526 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3527 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3528 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3529 return 0;
3530}
3531
95d4c16c 3532/**
60c34612
TY		 3533 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3534 * @kvm: kvm instance
3535 * @log: slot id and address to which we copy the log
95d4c16c 3536 *
e108ff2f
PB		 3537 * Steps 1-4 below provide general overview of dirty page logging. See
3538 * kvm_get_dirty_log_protect() function description for additional details.
3539 *
3540 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3541 * always flush the TLB (step 4) even if previous step failed and the dirty
3542 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3543 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3544 * writes will be marked dirty for next log read.
95d4c16c 3545 *
60c34612
TY		 3546 * 1. Take a snapshot of the bit and clear it if needed.
3547 * 2. Write protect the corresponding page.
e108ff2f
PB		 3548 * 3. Copy the snapshot to the userspace.
3549 * 4. Flush TLB's if needed.
5bb064dc 3550 */
60c34612 3551int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3552{
60c34612 3553 bool is_dirty = false;
e108ff2f 3554 int r;
5bb064dc 3555
79fac95e 3556 mutex_lock(&kvm->slots_lock);
5bb064dc 3557
88178fd4
KH		 3558 /*
3559 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3560 */
3561 if (kvm_x86_ops->flush_log_dirty)
3562 kvm_x86_ops->flush_log_dirty(kvm);
3563
e108ff2f 3564 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3565
3566 /*
3567 * All the TLBs can be flushed out of mmu lock, see the comments in
3568 * kvm_mmu_slot_remove_write_access().
3569 */
e108ff2f 3570 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3571 if (is_dirty)
3572 kvm_flush_remote_tlbs(kvm);
3573
79fac95e 3574 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3575 return r;
3576}
3577
aa2fbe6d
YZ		 3578int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3579 bool line_status)
23d43cf9
CD		 3580{
3581 if (!irqchip_in_kernel(kvm))
3582 return -ENXIO;
3583
3584 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3585 irq_event->irq, irq_event->level,
3586 line_status);
23d43cf9
CD		 3587 return 0;
3588}
3589
90de4a18
NA		 3590static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3591 struct kvm_enable_cap *cap)
3592{
3593 int r;
3594
3595 if (cap->flags)
3596 return -EINVAL;
3597
3598 switch (cap->cap) {
3599 case KVM_CAP_DISABLE_QUIRKS:
3600 kvm->arch.disabled_quirks = cap->args[0];
3601 r = 0;
3602 break;
49df6397
SR		 3603 case KVM_CAP_SPLIT_IRQCHIP: {
3604 mutex_lock(&kvm->lock);
b053b2ae
SR		 3605 r = -EINVAL;
3606 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3607 goto split_irqchip_unlock;
49df6397
SR		 3608 r = -EEXIST;
3609 if (irqchip_in_kernel(kvm))
3610 goto split_irqchip_unlock;
3611 if (atomic_read(&kvm->online_vcpus))
3612 goto split_irqchip_unlock;
3613 r = kvm_setup_empty_irq_routing(kvm);
3614 if (r)
3615 goto split_irqchip_unlock;
3616 /* Pairs with irqchip_in_kernel. */
3617 smp_wmb();
3618 kvm->arch.irqchip_split = true;
b053b2ae 3619 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3620 r = 0;
3621split_irqchip_unlock:
3622 mutex_unlock(&kvm->lock);
3623 break;
3624 }
90de4a18
NA		 3625 default:
3626 r = -EINVAL;
3627 break;
3628 }
3629 return r;
3630}
3631
1fe779f8
CO		 3632long kvm_arch_vm_ioctl(struct file *filp,
3633 unsigned int ioctl, unsigned long arg)
3634{
3635 struct kvm *kvm = filp->private_data;
3636 void __user *argp = (void __user *)arg;
367e1319 3637 int r = -ENOTTY;
f0d66275
DH		 3638 /*
3639 * This union makes it completely explicit to gcc-3.x
3640 * that these two variables' stack usage should be
3641 * combined, not added together.
3642 */
3643 union {
3644 struct kvm_pit_state ps;
e9f42757 3645 struct kvm_pit_state2 ps2;
c5ff41ce 3646 struct kvm_pit_config pit_config;
f0d66275 3647 } u;
1fe779f8
CO		 3648
3649 switch (ioctl) {
3650 case KVM_SET_TSS_ADDR:
3651 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3652 break;
b927a3ce
SY		 3653 case KVM_SET_IDENTITY_MAP_ADDR: {
3654 u64 ident_addr;
3655
3656 r = -EFAULT;
3657 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3658 goto out;
3659 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3660 break;
3661 }
1fe779f8
CO		 3662 case KVM_SET_NR_MMU_PAGES:
3663 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3664 break;
3665 case KVM_GET_NR_MMU_PAGES:
3666 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3667 break;
3ddea128
MT		 3668 case KVM_CREATE_IRQCHIP: {
3669 struct kvm_pic *vpic;
3670
3671 mutex_lock(&kvm->lock);
3672 r = -EEXIST;
3673 if (kvm->arch.vpic)
3674 goto create_irqchip_unlock;
3e515705
AK		 3675 r = -EINVAL;
3676 if (atomic_read(&kvm->online_vcpus))
3677 goto create_irqchip_unlock;
1fe779f8 3678 r = -ENOMEM;
3ddea128
MT		 3679 vpic = kvm_create_pic(kvm);
3680 if (vpic) {
1fe779f8
CO		 3681 r = kvm_ioapic_init(kvm);
3682 if (r) {
175504cd 3683 mutex_lock(&kvm->slots_lock);
71ba994c 3684 kvm_destroy_pic(vpic);
175504cd 3685 mutex_unlock(&kvm->slots_lock);
3ddea128 3686 goto create_irqchip_unlock;
1fe779f8
CO		 3687 }
3688 } else
3ddea128 3689 goto create_irqchip_unlock;
399ec807
AK		 3690 r = kvm_setup_default_irq_routing(kvm);
3691 if (r) {
175504cd 3692 mutex_lock(&kvm->slots_lock);
3ddea128 3693 mutex_lock(&kvm->irq_lock);
72bb2fcd 3694 kvm_ioapic_destroy(kvm);
71ba994c 3695 kvm_destroy_pic(vpic);
3ddea128 3696 mutex_unlock(&kvm->irq_lock);
175504cd 3697 mutex_unlock(&kvm->slots_lock);
71ba994c 3698 goto create_irqchip_unlock;
399ec807 3699 }
71ba994c
PB		 3700 /* Write kvm->irq_routing before kvm->arch.vpic. */
3701 smp_wmb();
3702 kvm->arch.vpic = vpic;
3ddea128
MT		 3703 create_irqchip_unlock:
3704 mutex_unlock(&kvm->lock);
1fe779f8 3705 break;
3ddea128 3706 }
7837699f 3707 case KVM_CREATE_PIT:
c5ff41ce
JK		 3708 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3709 goto create_pit;
3710 case KVM_CREATE_PIT2:
3711 r = -EFAULT;
3712 if (copy_from_user(&u.pit_config, argp,
3713 sizeof(struct kvm_pit_config)))
3714 goto out;
3715 create_pit:
79fac95e 3716 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3717 r = -EEXIST;
3718 if (kvm->arch.vpit)
3719 goto create_pit_unlock;
7837699f 3720 r = -ENOMEM;
c5ff41ce 3721 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3722 if (kvm->arch.vpit)
3723 r = 0;
269e05e4 3724 create_pit_unlock:
79fac95e 3725 mutex_unlock(&kvm->slots_lock);
7837699f 3726 break;
1fe779f8
CO		 3727 case KVM_GET_IRQCHIP: {
3728 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3729 struct kvm_irqchip *chip;
1fe779f8 3730
ff5c2c03
SL		 3731 chip = memdup_user(argp, sizeof(*chip));
3732 if (IS_ERR(chip)) {
3733 r = PTR_ERR(chip);
1fe779f8 3734 goto out;
ff5c2c03
SL		 3735 }
3736
1fe779f8 3737 r = -ENXIO;
49df6397 3738 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3739 goto get_irqchip_out;
3740 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3741 if (r)
f0d66275 3742 goto get_irqchip_out;
1fe779f8 3743 r = -EFAULT;
f0d66275
DH		 3744 if (copy_to_user(argp, chip, sizeof *chip))
3745 goto get_irqchip_out;
1fe779f8 3746 r = 0;
f0d66275
DH		 3747 get_irqchip_out:
3748 kfree(chip);
1fe779f8
CO		 3749 break;
3750 }
3751 case KVM_SET_IRQCHIP: {
3752 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3753 struct kvm_irqchip *chip;
1fe779f8 3754
ff5c2c03
SL		 3755 chip = memdup_user(argp, sizeof(*chip));
3756 if (IS_ERR(chip)) {
3757 r = PTR_ERR(chip);
1fe779f8 3758 goto out;
ff5c2c03
SL		 3759 }
3760
1fe779f8 3761 r = -ENXIO;
49df6397 3762 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3763 goto set_irqchip_out;
3764 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3765 if (r)
f0d66275 3766 goto set_irqchip_out;
1fe779f8 3767 r = 0;
f0d66275
DH		 3768 set_irqchip_out:
3769 kfree(chip);
1fe779f8
CO		 3770 break;
3771 }
e0f63cb9 3772 case KVM_GET_PIT: {
e0f63cb9 3773 r = -EFAULT;
f0d66275 3774 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3775 goto out;
3776 r = -ENXIO;
3777 if (!kvm->arch.vpit)
3778 goto out;
f0d66275 3779 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3780 if (r)
3781 goto out;
3782 r = -EFAULT;
f0d66275 3783 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3784 goto out;
3785 r = 0;
3786 break;
3787 }
3788 case KVM_SET_PIT: {
e0f63cb9 3789 r = -EFAULT;
f0d66275 3790 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3791 goto out;
3792 r = -ENXIO;
3793 if (!kvm->arch.vpit)
3794 goto out;
f0d66275 3795 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3796 break;
3797 }
e9f42757
BK		 3798 case KVM_GET_PIT2: {
3799 r = -ENXIO;
3800 if (!kvm->arch.vpit)
3801 goto out;
3802 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3803 if (r)
3804 goto out;
3805 r = -EFAULT;
3806 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3807 goto out;
3808 r = 0;
3809 break;
3810 }
3811 case KVM_SET_PIT2: {
3812 r = -EFAULT;
3813 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3814 goto out;
3815 r = -ENXIO;
3816 if (!kvm->arch.vpit)
3817 goto out;
3818 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3819 break;
3820 }
52d939a0
MT		 3821 case KVM_REINJECT_CONTROL: {
3822 struct kvm_reinject_control control;
3823 r = -EFAULT;
3824 if (copy_from_user(&control, argp, sizeof(control)))
3825 goto out;
3826 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3827 break;
3828 }
d71ba788
PB		 3829 case KVM_SET_BOOT_CPU_ID:
3830 r = 0;
3831 mutex_lock(&kvm->lock);
3832 if (atomic_read(&kvm->online_vcpus) != 0)
3833 r = -EBUSY;
3834 else
3835 kvm->arch.bsp_vcpu_id = arg;
3836 mutex_unlock(&kvm->lock);
3837 break;
ffde22ac
ES		 3838 case KVM_XEN_HVM_CONFIG: {
3839 r = -EFAULT;
3840 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3841 sizeof(struct kvm_xen_hvm_config)))
3842 goto out;
3843 r = -EINVAL;
3844 if (kvm->arch.xen_hvm_config.flags)
3845 goto out;
3846 r = 0;
3847 break;
3848 }
afbcf7ab 3849 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3850 struct kvm_clock_data user_ns;
3851 u64 now_ns;
3852 s64 delta;
3853
3854 r = -EFAULT;
3855 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3856 goto out;
3857
3858 r = -EINVAL;
3859 if (user_ns.flags)
3860 goto out;
3861
3862 r = 0;
395c6b0a 3863 local_irq_disable();
759379dd 3864 now_ns = get_kernel_ns();
afbcf7ab 3865 delta = user_ns.clock - now_ns;
395c6b0a 3866 local_irq_enable();
afbcf7ab 3867 kvm->arch.kvmclock_offset = delta;
2e762ff7 3868 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3869 break;
3870 }
3871 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3872 struct kvm_clock_data user_ns;
3873 u64 now_ns;
3874
395c6b0a 3875 local_irq_disable();
759379dd 3876 now_ns = get_kernel_ns();
afbcf7ab 3877 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3878 local_irq_enable();
afbcf7ab 3879 user_ns.flags = 0;
97e69aa6 3880 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3881
3882 r = -EFAULT;
3883 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3884 goto out;
3885 r = 0;
3886 break;
3887 }
90de4a18
NA		 3888 case KVM_ENABLE_CAP: {
3889 struct kvm_enable_cap cap;
afbcf7ab 3890
90de4a18
NA		 3891 r = -EFAULT;
3892 if (copy_from_user(&cap, argp, sizeof(cap)))
3893 goto out;
3894 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3895 break;
3896 }
1fe779f8 3897 default:
c274e03a 3898 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3899 }
3900out:
3901 return r;
3902}
3903
a16b043c 3904static void kvm_init_msr_list(void)
043405e1
CO		 3905{
3906 u32 dummy[2];
3907 unsigned i, j;
3908
62ef68bb 3909 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3910 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3911 continue;
93c4adc7
PB		 3912
3913 /*
3914 * Even MSRs that are valid in the host may not be exposed
3915 * to the guests in some cases. We could work around this
3916 * in VMX with the generic MSR save/load machinery, but it
3917 * is not really worthwhile since it will really only
3918 * happen with nested virtualization.
3919 */
3920 switch (msrs_to_save[i]) {
3921 case MSR_IA32_BNDCFGS:
3922 if (!kvm_x86_ops->mpx_supported())
3923 continue;
3924 break;
3925 default:
3926 break;
3927 }
3928
043405e1
CO		 3929 if (j < i)
3930 msrs_to_save[j] = msrs_to_save[i];
3931 j++;
3932 }
3933 num_msrs_to_save = j;
62ef68bb
PB		 3934
3935 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3936 switch (emulated_msrs[i]) {
6d396b55
PB		 3937 case MSR_IA32_SMBASE:
3938 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3939 continue;
3940 break;
62ef68bb
PB		 3941 default:
3942 break;
3943 }
3944
3945 if (j < i)
3946 emulated_msrs[j] = emulated_msrs[i];
3947 j++;
3948 }
3949 num_emulated_msrs = j;
043405e1
CO		 3950}
3951
bda9020e
MT		 3952static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3953 const void *v)
bbd9b64e 3954{
70252a10
AK		 3955 int handled = 0;
3956 int n;
3957
3958 do {
3959 n = min(len, 8);
3960 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3961 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3962 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3963 break;
3964 handled += n;
3965 addr += n;
3966 len -= n;
3967 v += n;
3968 } while (len);
bbd9b64e 3969
70252a10 3970 return handled;
bbd9b64e
CO		 3971}
3972
bda9020e 3973static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3974{
70252a10
AK		 3975 int handled = 0;
3976 int n;
3977
3978 do {
3979 n = min(len, 8);
3980 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3981 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3982 addr, n, v))
3983 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3984 break;
3985 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3986 handled += n;
3987 addr += n;
3988 len -= n;
3989 v += n;
3990 } while (len);
bbd9b64e 3991
70252a10 3992 return handled;
bbd9b64e
CO		 3993}
3994
2dafc6c2
GN		 3995static void kvm_set_segment(struct kvm_vcpu *vcpu,
3996 struct kvm_segment *var, int seg)
3997{
3998 kvm_x86_ops->set_segment(vcpu, var, seg);
3999}
4000
4001void kvm_get_segment(struct kvm_vcpu *vcpu,
4002 struct kvm_segment *var, int seg)
4003{
4004 kvm_x86_ops->get_segment(vcpu, var, seg);
4005}
4006
54987b7a
PB		 4007gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4008 struct x86_exception *exception)
02f59dc9
JR		 4009{
4010 gpa_t t_gpa;
02f59dc9
JR		 4011
4012 BUG_ON(!mmu_is_nested(vcpu));
4013
4014 /* NPT walks are always user-walks */
4015 access |= PFERR_USER_MASK;
54987b7a 4016 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4017
4018 return t_gpa;
4019}
4020
ab9ae313
AK		 4021gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4022 struct x86_exception *exception)
1871c602
GN		 4023{
4024 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4025 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4026}
4027
ab9ae313
AK		 4028 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4029 struct x86_exception *exception)
1871c602
GN		 4030{
4031 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4032 access |= PFERR_FETCH_MASK;
ab9ae313 4033 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4034}
4035
ab9ae313
AK		 4036gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4037 struct x86_exception *exception)
1871c602
GN		 4038{
4039 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4040 access |= PFERR_WRITE_MASK;
ab9ae313 4041 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4042}
4043
4044/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4045gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4046 struct x86_exception *exception)
1871c602 4047{
ab9ae313 4048 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4049}
4050
4051static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4052 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4053 struct x86_exception *exception)
bbd9b64e
CO		 4054{
4055 void *data = val;
10589a46 4056 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4057
4058 while (bytes) {
14dfe855 4059 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4060 exception);
bbd9b64e 4061 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4062 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4063 int ret;
4064
bcc55cba 4065 if (gpa == UNMAPPED_GVA)
ab9ae313 4066 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4067 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4068 offset, toread);
10589a46 4069 if (ret < 0) {
c3cd7ffa 4070 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4071 goto out;
4072 }
bbd9b64e 4073
77c2002e
IE		 4074 bytes -= toread;
4075 data += toread;
4076 addr += toread;
bbd9b64e 4077 }
10589a46 4078out:
10589a46 4079 return r;
bbd9b64e 4080}
77c2002e 4081
1871c602 4082/* used for instruction fetching */
0f65dd70
AK		 4083static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4084 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4085 struct x86_exception *exception)
1871c602 4086{
0f65dd70 4087 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4088 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4089 unsigned offset;
4090 int ret;
0f65dd70 4091
44583cba
PB		 4092 /* Inline kvm_read_guest_virt_helper for speed. */
4093 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4094 exception);
4095 if (unlikely(gpa == UNMAPPED_GVA))
4096 return X86EMUL_PROPAGATE_FAULT;
4097
4098 offset = addr & (PAGE_SIZE-1);
4099 if (WARN_ON(offset + bytes > PAGE_SIZE))
4100 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4101 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4102 offset, bytes);
44583cba
PB		 4103 if (unlikely(ret < 0))
4104 return X86EMUL_IO_NEEDED;
4105
4106 return X86EMUL_CONTINUE;
1871c602
GN		 4107}
4108
064aea77 4109int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4110 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4111 struct x86_exception *exception)
1871c602 4112{
0f65dd70 4113 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4114 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4115
1871c602 4116 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4117 exception);
1871c602 4118}
064aea77 4119EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4120
0f65dd70
AK		 4121static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4122 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4123 struct x86_exception *exception)
1871c602 4124{
0f65dd70 4125 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4126 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4127}
4128
7a036a6f
RK		 4129static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4130 unsigned long addr, void *val, unsigned int bytes)
4131{
4132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4133 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4134
4135 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4136}
4137
6a4d7550 4138int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4139 gva_t addr, void *val,
2dafc6c2 4140 unsigned int bytes,
bcc55cba 4141 struct x86_exception *exception)
77c2002e 4142{
0f65dd70 4143 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4144 void *data = val;
4145 int r = X86EMUL_CONTINUE;
4146
4147 while (bytes) {
14dfe855
JR		 4148 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4149 PFERR_WRITE_MASK,
ab9ae313 4150 exception);
77c2002e
IE		 4151 unsigned offset = addr & (PAGE_SIZE-1);
4152 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4153 int ret;
4154
bcc55cba 4155 if (gpa == UNMAPPED_GVA)
ab9ae313 4156 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4157 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4158 if (ret < 0) {
c3cd7ffa 4159 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4160 goto out;
4161 }
4162
4163 bytes -= towrite;
4164 data += towrite;
4165 addr += towrite;
4166 }
4167out:
4168 return r;
4169}
6a4d7550 4170EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4171
af7cc7d1
XG		 4172static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4173 gpa_t *gpa, struct x86_exception *exception,
4174 bool write)
4175{
97d64b78
AK		 4176 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4177 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4178
97d64b78 4179 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4180 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4181 vcpu->arch.access, access)) {
bebb106a
XG		 4182 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4183 (gva & (PAGE_SIZE - 1));
4f022648 4184 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4185 return 1;
4186 }
4187
af7cc7d1
XG		 4188 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4189
4190 if (*gpa == UNMAPPED_GVA)
4191 return -1;
4192
4193 /* For APIC access vmexit */
4194 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4195 return 1;
4196
4f022648
XG		 4197 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4198 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4199 return 1;
4f022648 4200 }
bebb106a 4201
af7cc7d1
XG		 4202 return 0;
4203}
4204
3200f405 4205int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4206 const void *val, int bytes)
bbd9b64e
CO		 4207{
4208 int ret;
4209
54bf36aa 4210 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4211 if (ret < 0)
bbd9b64e 4212 return 0;
f57f2ef5 4213 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4214 return 1;
4215}
4216
77d197b2
XG		 4217struct read_write_emulator_ops {
4218 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4219 int bytes);
4220 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4221 void *val, int bytes);
4222 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4223 int bytes, void *val);
4224 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4225 void *val, int bytes);
4226 bool write;
4227};
4228
4229static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4230{
4231 if (vcpu->mmio_read_completed) {
77d197b2 4232 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4233 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4234 vcpu->mmio_read_completed = 0;
4235 return 1;
4236 }
4237
4238 return 0;
4239}
4240
4241static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4242 void *val, int bytes)
4243{
54bf36aa 4244 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4245}
4246
4247static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4248 void *val, int bytes)
4249{
4250 return emulator_write_phys(vcpu, gpa, val, bytes);
4251}
4252
4253static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4254{
4255 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4256 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4257}
4258
4259static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4260 void *val, int bytes)
4261{
4262 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4263 return X86EMUL_IO_NEEDED;
4264}
4265
4266static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4267 void *val, int bytes)
4268{
f78146b0
AK		 4269 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4270
87da7e66 4271 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4272 return X86EMUL_CONTINUE;
4273}
4274
0fbe9b0b 4275static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4276 .read_write_prepare = read_prepare,
4277 .read_write_emulate = read_emulate,
4278 .read_write_mmio = vcpu_mmio_read,
4279 .read_write_exit_mmio = read_exit_mmio,
4280};
4281
0fbe9b0b 4282static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4283 .read_write_emulate = write_emulate,
4284 .read_write_mmio = write_mmio,
4285 .read_write_exit_mmio = write_exit_mmio,
4286 .write = true,
4287};
4288
22388a3c
XG		 4289static int emulator_read_write_onepage(unsigned long addr, void *val,
4290 unsigned int bytes,
4291 struct x86_exception *exception,
4292 struct kvm_vcpu *vcpu,
0fbe9b0b 4293 const struct read_write_emulator_ops *ops)
bbd9b64e 4294{
af7cc7d1
XG		 4295 gpa_t gpa;
4296 int handled, ret;
22388a3c 4297 bool write = ops->write;
f78146b0 4298 struct kvm_mmio_fragment *frag;
10589a46 4299
22388a3c 4300 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4301
af7cc7d1 4302 if (ret < 0)
bbd9b64e 4303 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4304
4305 /* For APIC access vmexit */
af7cc7d1 4306 if (ret)
bbd9b64e
CO		 4307 goto mmio;
4308
22388a3c 4309 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4310 return X86EMUL_CONTINUE;
4311
4312mmio:
4313 /*
4314 * Is this MMIO handled locally?
4315 */
22388a3c 4316 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4317 if (handled == bytes)
bbd9b64e 4318 return X86EMUL_CONTINUE;
bbd9b64e 4319
70252a10
AK		 4320 gpa += handled;
4321 bytes -= handled;
4322 val += handled;
4323
87da7e66
XG		 4324 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4325 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4326 frag->gpa = gpa;
4327 frag->data = val;
4328 frag->len = bytes;
f78146b0 4329 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4330}
4331
52eb5a6d
XL		 4332static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4333 unsigned long addr,
22388a3c
XG		 4334 void *val, unsigned int bytes,
4335 struct x86_exception *exception,
0fbe9b0b 4336 const struct read_write_emulator_ops *ops)
bbd9b64e 4337{
0f65dd70 4338 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4339 gpa_t gpa;
4340 int rc;
4341
4342 if (ops->read_write_prepare &&
4343 ops->read_write_prepare(vcpu, val, bytes))
4344 return X86EMUL_CONTINUE;
4345
4346 vcpu->mmio_nr_fragments = 0;
0f65dd70 4347
bbd9b64e
CO		 4348 /* Crossing a page boundary? */
4349 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4350 int now;
bbd9b64e
CO		 4351
4352 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4353 rc = emulator_read_write_onepage(addr, val, now, exception,
4354 vcpu, ops);
4355
bbd9b64e
CO		 4356 if (rc != X86EMUL_CONTINUE)
4357 return rc;
4358 addr += now;
bac15531
NA		 4359 if (ctxt->mode != X86EMUL_MODE_PROT64)
4360 addr = (u32)addr;
bbd9b64e
CO		 4361 val += now;
4362 bytes -= now;
4363 }
22388a3c 4364
f78146b0
AK		 4365 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4366 vcpu, ops);
4367 if (rc != X86EMUL_CONTINUE)
4368 return rc;
4369
4370 if (!vcpu->mmio_nr_fragments)
4371 return rc;
4372
4373 gpa = vcpu->mmio_fragments[0].gpa;
4374
4375 vcpu->mmio_needed = 1;
4376 vcpu->mmio_cur_fragment = 0;
4377
87da7e66 4378 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4379 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4380 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4381 vcpu->run->mmio.phys_addr = gpa;
4382
4383 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4384}
4385
4386static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4387 unsigned long addr,
4388 void *val,
4389 unsigned int bytes,
4390 struct x86_exception *exception)
4391{
4392 return emulator_read_write(ctxt, addr, val, bytes,
4393 exception, &read_emultor);
4394}
4395
52eb5a6d 4396static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4397 unsigned long addr,
4398 const void *val,
4399 unsigned int bytes,
4400 struct x86_exception *exception)
4401{
4402 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4403 exception, &write_emultor);
bbd9b64e 4404}
bbd9b64e 4405
daea3e73
AK		 4406#define CMPXCHG_TYPE(t, ptr, old, new) \
4407 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4408
4409#ifdef CONFIG_X86_64
4410# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4411#else
4412# define CMPXCHG64(ptr, old, new) \
9749a6c0 4413 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4414#endif
4415
0f65dd70
AK		 4416static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4417 unsigned long addr,
bbd9b64e
CO		 4418 const void *old,
4419 const void *new,
4420 unsigned int bytes,
0f65dd70 4421 struct x86_exception *exception)
bbd9b64e 4422{
0f65dd70 4423 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4424 gpa_t gpa;
4425 struct page *page;
4426 char *kaddr;
4427 bool exchanged;
2bacc55c 4428
daea3e73
AK		 4429 /* guests cmpxchg8b have to be emulated atomically */
4430 if (bytes > 8 || (bytes & (bytes - 1)))
4431 goto emul_write;
10589a46 4432
daea3e73 4433 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4434
daea3e73
AK		 4435 if (gpa == UNMAPPED_GVA ||
4436 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4437 goto emul_write;
2bacc55c 4438
daea3e73
AK		 4439 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4440 goto emul_write;
72dc67a6 4441
54bf36aa 4442 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4443 if (is_error_page(page))
c19b8bd6 4444 goto emul_write;
72dc67a6 4445
8fd75e12 4446 kaddr = kmap_atomic(page);
daea3e73
AK		 4447 kaddr += offset_in_page(gpa);
4448 switch (bytes) {
4449 case 1:
4450 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4451 break;
4452 case 2:
4453 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4454 break;
4455 case 4:
4456 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4457 break;
4458 case 8:
4459 exchanged = CMPXCHG64(kaddr, old, new);
4460 break;
4461 default:
4462 BUG();
2bacc55c 4463 }
8fd75e12 4464 kunmap_atomic(kaddr);
daea3e73
AK		 4465 kvm_release_page_dirty(page);
4466
4467 if (!exchanged)
4468 return X86EMUL_CMPXCHG_FAILED;
4469
54bf36aa 4470 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4471 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4472
4473 return X86EMUL_CONTINUE;
4a5f48f6 4474
3200f405 4475emul_write:
daea3e73 4476 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4477
0f65dd70 4478 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4479}
4480
cf8f70bf
GN		 4481static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4482{
4483 /* TODO: String I/O for in kernel device */
4484 int r;
4485
4486 if (vcpu->arch.pio.in)
e32edf4f 4487 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4488 vcpu->arch.pio.size, pd);
4489 else
e32edf4f 4490 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4491 vcpu->arch.pio.port, vcpu->arch.pio.size,
4492 pd);
4493 return r;
4494}
4495
6f6fbe98
XG		 4496static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4497 unsigned short port, void *val,
4498 unsigned int count, bool in)
cf8f70bf 4499{
cf8f70bf 4500 vcpu->arch.pio.port = port;
6f6fbe98 4501 vcpu->arch.pio.in = in;
7972995b 4502 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4503 vcpu->arch.pio.size = size;
4504
4505 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4506 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4507 return 1;
4508 }
4509
4510 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4511 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4512 vcpu->run->io.size = size;
4513 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4514 vcpu->run->io.count = count;
4515 vcpu->run->io.port = port;
4516
4517 return 0;
4518}
4519
6f6fbe98
XG		 4520static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4521 int size, unsigned short port, void *val,
4522 unsigned int count)
cf8f70bf 4523{
ca1d4a9e 4524 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4525 int ret;
ca1d4a9e 4526
6f6fbe98
XG		 4527 if (vcpu->arch.pio.count)
4528 goto data_avail;
cf8f70bf 4529
6f6fbe98
XG		 4530 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4531 if (ret) {
4532data_avail:
4533 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4534 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4535 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4536 return 1;
4537 }
4538
cf8f70bf
GN		 4539 return 0;
4540}
4541
6f6fbe98
XG		 4542static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4543 int size, unsigned short port,
4544 const void *val, unsigned int count)
4545{
4546 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4547
4548 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4549 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4550 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4551}
4552
bbd9b64e
CO		 4553static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4554{
4555 return kvm_x86_ops->get_segment_base(vcpu, seg);
4556}
4557
3cb16fe7 4558static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4559{
3cb16fe7 4560 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4561}
4562
5cb56059 4563int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4564{
4565 if (!need_emulate_wbinvd(vcpu))
4566 return X86EMUL_CONTINUE;
4567
4568 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4569 int cpu = get_cpu();
4570
4571 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4572 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4573 wbinvd_ipi, NULL, 1);
2eec7343 4574 put_cpu();
f5f48ee1 4575 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4576 } else
4577 wbinvd();
f5f48ee1
SY		 4578 return X86EMUL_CONTINUE;
4579}
5cb56059
JS		 4580
4581int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4582{
4583 kvm_x86_ops->skip_emulated_instruction(vcpu);
4584 return kvm_emulate_wbinvd_noskip(vcpu);
4585}
f5f48ee1
SY		 4586EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4587
5cb56059
JS		 4588
4589
bcaf5cc5
AK		 4590static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4591{
5cb56059 4592 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4593}
4594
52eb5a6d
XL		 4595static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4596 unsigned long *dest)
bbd9b64e 4597{
16f8a6f9 4598 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4599}
4600
52eb5a6d
XL		 4601static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4602 unsigned long value)
bbd9b64e 4603{
338dbc97 4604
717746e3 4605 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4606}
4607
52a46617 4608static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4609{
52a46617 4610 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4611}
4612
717746e3 4613static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4614{
717746e3 4615 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4616 unsigned long value;
4617
4618 switch (cr) {
4619 case 0:
4620 value = kvm_read_cr0(vcpu);
4621 break;
4622 case 2:
4623 value = vcpu->arch.cr2;
4624 break;
4625 case 3:
9f8fe504 4626 value = kvm_read_cr3(vcpu);
52a46617
GN		 4627 break;
4628 case 4:
4629 value = kvm_read_cr4(vcpu);
4630 break;
4631 case 8:
4632 value = kvm_get_cr8(vcpu);
4633 break;
4634 default:
a737f256 4635 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4636 return 0;
4637 }
4638
4639 return value;
4640}
4641
717746e3 4642static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4643{
717746e3 4644 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4645 int res = 0;
4646
52a46617
GN		 4647 switch (cr) {
4648 case 0:
49a9b07e 4649 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4650 break;
4651 case 2:
4652 vcpu->arch.cr2 = val;
4653 break;
4654 case 3:
2390218b 4655 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4656 break;
4657 case 4:
a83b29c6 4658 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4659 break;
4660 case 8:
eea1cff9 4661 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4662 break;
4663 default:
a737f256 4664 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4665 res = -1;
52a46617 4666 }
0f12244f
GN		 4667
4668 return res;
52a46617
GN		 4669}
4670
717746e3 4671static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4672{
717746e3 4673 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4674}
4675
4bff1e86 4676static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4677{
4bff1e86 4678 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4679}
4680
4bff1e86 4681static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4682{
4bff1e86 4683 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4684}
4685
1ac9d0cf
AK		 4686static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4687{
4688 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4689}
4690
4691static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4692{
4693 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4694}
4695
4bff1e86
AK		 4696static unsigned long emulator_get_cached_segment_base(
4697 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4698{
4bff1e86 4699 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4700}
4701
1aa36616
AK		 4702static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4703 struct desc_struct *desc, u32 *base3,
4704 int seg)
2dafc6c2
GN		 4705{
4706 struct kvm_segment var;
4707
4bff1e86 4708 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4709 *selector = var.selector;
2dafc6c2 4710
378a8b09
GN		 4711 if (var.unusable) {
4712 memset(desc, 0, sizeof(*desc));
2dafc6c2 4713 return false;
378a8b09 4714 }
2dafc6c2
GN		 4715
4716 if (var.g)
4717 var.limit >>= 12;
4718 set_desc_limit(desc, var.limit);
4719 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4720#ifdef CONFIG_X86_64
4721 if (base3)
4722 *base3 = var.base >> 32;
4723#endif
2dafc6c2
GN		 4724 desc->type = var.type;
4725 desc->s = var.s;
4726 desc->dpl = var.dpl;
4727 desc->p = var.present;
4728 desc->avl = var.avl;
4729 desc->l = var.l;
4730 desc->d = var.db;
4731 desc->g = var.g;
4732
4733 return true;
4734}
4735
1aa36616
AK		 4736static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4737 struct desc_struct *desc, u32 base3,
4738 int seg)
2dafc6c2 4739{
4bff1e86 4740 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4741 struct kvm_segment var;
4742
1aa36616 4743 var.selector = selector;
2dafc6c2 4744 var.base = get_desc_base(desc);
5601d05b
GN		 4745#ifdef CONFIG_X86_64
4746 var.base |= ((u64)base3) << 32;
4747#endif
2dafc6c2
GN		 4748 var.limit = get_desc_limit(desc);
4749 if (desc->g)
4750 var.limit = (var.limit << 12) | 0xfff;
4751 var.type = desc->type;
2dafc6c2
GN		 4752 var.dpl = desc->dpl;
4753 var.db = desc->d;
4754 var.s = desc->s;
4755 var.l = desc->l;
4756 var.g = desc->g;
4757 var.avl = desc->avl;
4758 var.present = desc->p;
4759 var.unusable = !var.present;
4760 var.padding = 0;
4761
4762 kvm_set_segment(vcpu, &var, seg);
4763 return;
4764}
4765
717746e3
AK		 4766static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4767 u32 msr_index, u64 *pdata)
4768{
609e36d3
PB		 4769 struct msr_data msr;
4770 int r;
4771
4772 msr.index = msr_index;
4773 msr.host_initiated = false;
4774 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4775 if (r)
4776 return r;
4777
4778 *pdata = msr.data;
4779 return 0;
717746e3
AK		 4780}
4781
4782static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4783 u32 msr_index, u64 data)
4784{
8fe8ab46
WA		 4785 struct msr_data msr;
4786
4787 msr.data = data;
4788 msr.index = msr_index;
4789 msr.host_initiated = false;
4790 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4791}
4792
64d60670
PB		 4793static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4794{
4795 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4796
4797 return vcpu->arch.smbase;
4798}
4799
4800static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4801{
4802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4803
4804 vcpu->arch.smbase = smbase;
4805}
4806
67f4d428
NA		 4807static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4808 u32 pmc)
4809{
c6702c9d 4810 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4811}
4812
222d21aa
AK		 4813static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4814 u32 pmc, u64 *pdata)
4815{
c6702c9d 4816 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4817}
4818
6c3287f7
AK		 4819static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4820{
4821 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4822}
4823
5037f6f3
AK		 4824static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4825{
4826 preempt_disable();
5197b808 4827 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4828 /*
4829 * CR0.TS may reference the host fpu state, not the guest fpu state,
4830 * so it may be clear at this point.
4831 */
4832 clts();
4833}
4834
4835static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4836{
4837 preempt_enable();
4838}
4839
2953538e 4840static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4841 struct x86_instruction_info *info,
c4f035c6
AK		 4842 enum x86_intercept_stage stage)
4843{
2953538e 4844 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4845}
4846
0017f93a 4847static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4848 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4849{
0017f93a 4850 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4851}
4852
dd856efa
AK		 4853static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4854{
4855 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4856}
4857
4858static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4859{
4860 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4861}
4862
801806d9
NA		 4863static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4864{
4865 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4866}
4867
0225fb50 4868static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4869 .read_gpr = emulator_read_gpr,
4870 .write_gpr = emulator_write_gpr,
1871c602 4871 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4872 .write_std = kvm_write_guest_virt_system,
7a036a6f 4873 .read_phys = kvm_read_guest_phys_system,
1871c602 4874 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4875 .read_emulated = emulator_read_emulated,
4876 .write_emulated = emulator_write_emulated,
4877 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4878 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4879 .pio_in_emulated = emulator_pio_in_emulated,
4880 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4881 .get_segment = emulator_get_segment,
4882 .set_segment = emulator_set_segment,
5951c442 4883 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4884 .get_gdt = emulator_get_gdt,
160ce1f1 4885 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4886 .set_gdt = emulator_set_gdt,
4887 .set_idt = emulator_set_idt,
52a46617
GN		 4888 .get_cr = emulator_get_cr,
4889 .set_cr = emulator_set_cr,
9c537244 4890 .cpl = emulator_get_cpl,
35aa5375
GN		 4891 .get_dr = emulator_get_dr,
4892 .set_dr = emulator_set_dr,
64d60670
PB		 4893 .get_smbase = emulator_get_smbase,
4894 .set_smbase = emulator_set_smbase,
717746e3
AK		 4895 .set_msr = emulator_set_msr,
4896 .get_msr = emulator_get_msr,
67f4d428 4897 .check_pmc = emulator_check_pmc,
222d21aa 4898 .read_pmc = emulator_read_pmc,
6c3287f7 4899 .halt = emulator_halt,
bcaf5cc5 4900 .wbinvd = emulator_wbinvd,
d6aa1000 4901 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4902 .get_fpu = emulator_get_fpu,
4903 .put_fpu = emulator_put_fpu,
c4f035c6 4904 .intercept = emulator_intercept,
bdb42f5a 4905 .get_cpuid = emulator_get_cpuid,
801806d9 4906 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4907};
4908
95cb2295
GN		 4909static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4910{
37ccdcbe 4911 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4912 /*
4913 * an sti; sti; sequence only disable interrupts for the first
4914 * instruction. So, if the last instruction, be it emulated or
4915 * not, left the system with the INT_STI flag enabled, it
4916 * means that the last instruction is an sti. We should not
4917 * leave the flag on in this case. The same goes for mov ss
4918 */
37ccdcbe
PB		 4919 if (int_shadow & mask)
4920 mask = 0;
6addfc42 4921 if (unlikely(int_shadow || mask)) {
95cb2295 4922 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4923 if (!mask)
4924 kvm_make_request(KVM_REQ_EVENT, vcpu);
4925 }
95cb2295
GN		 4926}
4927
ef54bcfe 4928static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4929{
4930 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4931 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4932 return kvm_propagate_fault(vcpu, &ctxt->exception);
4933
4934 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4935 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4936 ctxt->exception.error_code);
54b8486f 4937 else
da9cb575 4938 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4939 return false;
54b8486f
GN		 4940}
4941
8ec4722d
MG		 4942static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4943{
adf52235 4944 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4945 int cs_db, cs_l;
4946
8ec4722d
MG		 4947 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4948
adf52235
TY		 4949 ctxt->eflags = kvm_get_rflags(vcpu);
4950 ctxt->eip = kvm_rip_read(vcpu);
4951 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4952 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4953 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4954 cs_db ? X86EMUL_MODE_PROT32 :
4955 X86EMUL_MODE_PROT16;
a584539b 4956 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4957 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4958 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4959 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4960
dd856efa 4961 init_decode_cache(ctxt);
7ae441ea 4962 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4963}
4964
71f9833b 4965int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4966{
9d74191a 4967 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4968 int ret;
4969
4970 init_emulate_ctxt(vcpu);
4971
9dac77fa
AK		 4972 ctxt->op_bytes = 2;
4973 ctxt->ad_bytes = 2;
4974 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4975 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4976
4977 if (ret != X86EMUL_CONTINUE)
4978 return EMULATE_FAIL;
4979
9dac77fa 4980 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4981 kvm_rip_write(vcpu, ctxt->eip);
4982 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4983
4984 if (irq == NMI_VECTOR)
7460fb4a 4985 vcpu->arch.nmi_pending = 0;
63995653
MG		 4986 else
4987 vcpu->arch.interrupt.pending = false;
4988
4989 return EMULATE_DONE;
4990}
4991EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4992
6d77dbfc
GN		 4993static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4994{
fc3a9157
JR		 4995 int r = EMULATE_DONE;
4996
6d77dbfc
GN		 4997 ++vcpu->stat.insn_emulation_fail;
4998 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4999 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5000 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5001 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5002 vcpu->run->internal.ndata = 0;
5003 r = EMULATE_FAIL;
5004 }
6d77dbfc 5005 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5006
5007 return r;
6d77dbfc
GN		 5008}
5009
93c05d3e 5010static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5011 bool write_fault_to_shadow_pgtable,
5012 int emulation_type)
a6f177ef 5013{
95b3cf69 5014 gpa_t gpa = cr2;
8e3d9d06 5015 pfn_t pfn;
a6f177ef 5016
991eebf9
GN		 5017 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5018 return false;
5019
95b3cf69
XG		 5020 if (!vcpu->arch.mmu.direct_map) {
5021 /*
5022 * Write permission should be allowed since only
5023 * write access need to be emulated.
5024 */
5025 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5026
95b3cf69
XG		 5027 /*
5028 * If the mapping is invalid in guest, let cpu retry
5029 * it to generate fault.
5030 */
5031 if (gpa == UNMAPPED_GVA)
5032 return true;
5033 }
a6f177ef 5034
8e3d9d06
XG		 5035 /*
5036 * Do not retry the unhandleable instruction if it faults on the
5037 * readonly host memory, otherwise it will goto a infinite loop:
5038 * retry instruction -> write #PF -> emulation fail -> retry
5039 * instruction -> ...
5040 */
5041 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5042
5043 /*
5044 * If the instruction failed on the error pfn, it can not be fixed,
5045 * report the error to userspace.
5046 */
5047 if (is_error_noslot_pfn(pfn))
5048 return false;
5049
5050 kvm_release_pfn_clean(pfn);
5051
5052 /* The instructions are well-emulated on direct mmu. */
5053 if (vcpu->arch.mmu.direct_map) {
5054 unsigned int indirect_shadow_pages;
5055
5056 spin_lock(&vcpu->kvm->mmu_lock);
5057 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5058 spin_unlock(&vcpu->kvm->mmu_lock);
5059
5060 if (indirect_shadow_pages)
5061 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5062
a6f177ef 5063 return true;
8e3d9d06 5064 }
a6f177ef 5065
95b3cf69
XG		 5066 /*
5067 * if emulation was due to access to shadowed page table
5068 * and it failed try to unshadow page and re-enter the
5069 * guest to let CPU execute the instruction.
5070 */
5071 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5072
5073 /*
5074 * If the access faults on its page table, it can not
5075 * be fixed by unprotecting shadow page and it should
5076 * be reported to userspace.
5077 */
5078 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5079}
5080
1cb3f3ae
XG		 5081static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5082 unsigned long cr2, int emulation_type)
5083{
5084 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5085 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5086
5087 last_retry_eip = vcpu->arch.last_retry_eip;
5088 last_retry_addr = vcpu->arch.last_retry_addr;
5089
5090 /*
5091 * If the emulation is caused by #PF and it is non-page_table
5092 * writing instruction, it means the VM-EXIT is caused by shadow
5093 * page protected, we can zap the shadow page and retry this
5094 * instruction directly.
5095 *
5096 * Note: if the guest uses a non-page-table modifying instruction
5097 * on the PDE that points to the instruction, then we will unmap
5098 * the instruction and go to an infinite loop. So, we cache the
5099 * last retried eip and the last fault address, if we meet the eip
5100 * and the address again, we can break out of the potential infinite
5101 * loop.
5102 */
5103 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5104
5105 if (!(emulation_type & EMULTYPE_RETRY))
5106 return false;
5107
5108 if (x86_page_table_writing_insn(ctxt))
5109 return false;
5110
5111 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5112 return false;
5113
5114 vcpu->arch.last_retry_eip = ctxt->eip;
5115 vcpu->arch.last_retry_addr = cr2;
5116
5117 if (!vcpu->arch.mmu.direct_map)
5118 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5119
22368028 5120 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5121
5122 return true;
5123}
5124
716d51ab
GN		 5125static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5126static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5127
64d60670 5128static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5129{
64d60670 5130 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5131 /* This is a good place to trace that we are exiting SMM. */
5132 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5133
64d60670
PB		 5134 if (unlikely(vcpu->arch.smi_pending)) {
5135 kvm_make_request(KVM_REQ_SMI, vcpu);
5136 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5137 } else {
5138 /* Process a latched INIT, if any. */
5139 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5140 }
5141 }
699023e2
PB		 5142
5143 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5144}
5145
5146static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5147{
5148 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5149
a584539b 5150 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5151
5152 if (changed & HF_SMM_MASK)
5153 kvm_smm_changed(vcpu);
a584539b
PB		 5154}
5155
4a1e10d5
PB		 5156static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5157 unsigned long *db)
5158{
5159 u32 dr6 = 0;
5160 int i;
5161 u32 enable, rwlen;
5162
5163 enable = dr7;
5164 rwlen = dr7 >> 16;
5165 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5166 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5167 dr6 |= (1 << i);
5168 return dr6;
5169}
5170
6addfc42 5171static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5172{
5173 struct kvm_run *kvm_run = vcpu->run;
5174
5175 /*
6addfc42
PB		 5176 * rflags is the old, "raw" value of the flags. The new value has
5177 * not been saved yet.
663f4c61
PB		 5178 *
5179 * This is correct even for TF set by the guest, because "the
5180 * processor will not generate this exception after the instruction
5181 * that sets the TF flag".
5182 */
663f4c61
PB		 5183 if (unlikely(rflags & X86_EFLAGS_TF)) {
5184 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5185 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5186 DR6_RTM;
663f4c61
PB		 5187 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5188 kvm_run->debug.arch.exception = DB_VECTOR;
5189 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5190 *r = EMULATE_USER_EXIT;
5191 } else {
5192 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5193 /*
5194 * "Certain debug exceptions may clear bit 0-3. The
5195 * remaining contents of the DR6 register are never
5196 * cleared by the processor".
5197 */
5198 vcpu->arch.dr6 &= ~15;
6f43ed01 5199 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5200 kvm_queue_exception(vcpu, DB_VECTOR);
5201 }
5202 }
5203}
5204
4a1e10d5
PB		 5205static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5206{
4a1e10d5
PB		 5207 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5208 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5209 struct kvm_run *kvm_run = vcpu->run;
5210 unsigned long eip = kvm_get_linear_rip(vcpu);
5211 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5212 vcpu->arch.guest_debug_dr7,
5213 vcpu->arch.eff_db);
5214
5215 if (dr6 != 0) {
6f43ed01 5216 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5217 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5218 kvm_run->debug.arch.exception = DB_VECTOR;
5219 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5220 *r = EMULATE_USER_EXIT;
5221 return true;
5222 }
5223 }
5224
4161a569
NA		 5225 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5226 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5227 unsigned long eip = kvm_get_linear_rip(vcpu);
5228 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5229 vcpu->arch.dr7,
5230 vcpu->arch.db);
5231
5232 if (dr6 != 0) {
5233 vcpu->arch.dr6 &= ~15;
6f43ed01 5234 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5235 kvm_queue_exception(vcpu, DB_VECTOR);
5236 *r = EMULATE_DONE;
5237 return true;
5238 }
5239 }
5240
5241 return false;
5242}
5243
51d8b661
AP		 5244int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5245 unsigned long cr2,
dc25e89e
AP		 5246 int emulation_type,
5247 void *insn,
5248 int insn_len)
bbd9b64e 5249{
95cb2295 5250 int r;
9d74191a 5251 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5252 bool writeback = true;
93c05d3e 5253 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5254
93c05d3e
XG		 5255 /*
5256 * Clear write_fault_to_shadow_pgtable here to ensure it is
5257 * never reused.
5258 */
5259 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5260 kvm_clear_exception_queue(vcpu);
8d7d8102 5261
571008da 5262 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5263 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5264
5265 /*
5266 * We will reenter on the same instruction since
5267 * we do not set complete_userspace_io. This does not
5268 * handle watchpoints yet, those would be handled in
5269 * the emulate_ops.
5270 */
5271 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5272 return r;
5273
9d74191a
TY		 5274 ctxt->interruptibility = 0;
5275 ctxt->have_exception = false;
e0ad0b47 5276 ctxt->exception.vector = -1;
9d74191a 5277 ctxt->perm_ok = false;
bbd9b64e 5278
b51e974f 5279 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5280
9d74191a 5281 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5282
e46479f8 5283 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5284 ++vcpu->stat.insn_emulation;
1d2887e2 5285 if (r != EMULATION_OK) {
4005996e
AK		 5286 if (emulation_type & EMULTYPE_TRAP_UD)
5287 return EMULATE_FAIL;
991eebf9
GN		 5288 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5289 emulation_type))
bbd9b64e 5290 return EMULATE_DONE;
6d77dbfc
GN		 5291 if (emulation_type & EMULTYPE_SKIP)
5292 return EMULATE_FAIL;
5293 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5294 }
5295 }
5296
ba8afb6b 5297 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5298 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5299 if (ctxt->eflags & X86_EFLAGS_RF)
5300 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5301 return EMULATE_DONE;
5302 }
5303
1cb3f3ae
XG		 5304 if (retry_instruction(ctxt, cr2, emulation_type))
5305 return EMULATE_DONE;
5306
7ae441ea 5307 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5308 changes registers values during IO operation */
7ae441ea
GN		 5309 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5310 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5311 emulator_invalidate_register_cache(ctxt);
7ae441ea 5312 }
4d2179e1 5313
5cd21917 5314restart:
9d74191a 5315 r = x86_emulate_insn(ctxt);
bbd9b64e 5316
775fde86
JR		 5317 if (r == EMULATION_INTERCEPTED)
5318 return EMULATE_DONE;
5319
d2ddd1c4 5320 if (r == EMULATION_FAILED) {
991eebf9
GN		 5321 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5322 emulation_type))
c3cd7ffa
GN		 5323 return EMULATE_DONE;
5324
6d77dbfc 5325 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5326 }
5327
9d74191a 5328 if (ctxt->have_exception) {
d2ddd1c4 5329 r = EMULATE_DONE;
ef54bcfe
PB		 5330 if (inject_emulated_exception(vcpu))
5331 return r;
d2ddd1c4 5332 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5333 if (!vcpu->arch.pio.in) {
5334 /* FIXME: return into emulator if single-stepping. */
3457e419 5335 vcpu->arch.pio.count = 0;
0912c977 5336 } else {
7ae441ea 5337 writeback = false;
716d51ab
GN		 5338 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5339 }
ac0a48c3 5340 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5341 } else if (vcpu->mmio_needed) {
5342 if (!vcpu->mmio_is_write)
5343 writeback = false;
ac0a48c3 5344 r = EMULATE_USER_EXIT;
716d51ab 5345 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5346 } else if (r == EMULATION_RESTART)
5cd21917 5347 goto restart;
d2ddd1c4
GN		 5348 else
5349 r = EMULATE_DONE;
f850e2e6 5350
7ae441ea 5351 if (writeback) {
6addfc42 5352 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5353 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5354 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5355 if (vcpu->arch.hflags != ctxt->emul_flags)
5356 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5357 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5358 if (r == EMULATE_DONE)
6addfc42 5359 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5360 if (!ctxt->have_exception ||
5361 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5362 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5363
5364 /*
5365 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5366 * do nothing, and it will be requested again as soon as
5367 * the shadow expires. But we still need to check here,
5368 * because POPF has no interrupt shadow.
5369 */
5370 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5371 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5372 } else
5373 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5374
5375 return r;
de7d789a 5376}
51d8b661 5377EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5378
cf8f70bf 5379int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5380{
cf8f70bf 5381 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5382 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5383 size, port, &val, 1);
cf8f70bf 5384 /* do not return to emulator after return from userspace */
7972995b 5385 vcpu->arch.pio.count = 0;
de7d789a
CO		 5386 return ret;
5387}
cf8f70bf 5388EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5389
8cfdc000
ZA		 5390static void tsc_bad(void *info)
5391{
0a3aee0d 5392 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5393}
5394
5395static void tsc_khz_changed(void *data)
c8076604 5396{
8cfdc000
ZA		 5397 struct cpufreq_freqs *freq = data;
5398 unsigned long khz = 0;
5399
5400 if (data)
5401 khz = freq->new;
5402 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5403 khz = cpufreq_quick_get(raw_smp_processor_id());
5404 if (!khz)
5405 khz = tsc_khz;
0a3aee0d 5406 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5407}
5408
c8076604
GH		 5409static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5410 void *data)
5411{
5412 struct cpufreq_freqs *freq = data;
5413 struct kvm *kvm;
5414 struct kvm_vcpu *vcpu;
5415 int i, send_ipi = 0;
5416
8cfdc000
ZA		 5417 /*
5418 * We allow guests to temporarily run on slowing clocks,
5419 * provided we notify them after, or to run on accelerating
5420 * clocks, provided we notify them before. Thus time never
5421 * goes backwards.
5422 *
5423 * However, we have a problem. We can't atomically update
5424 * the frequency of a given CPU from this function; it is
5425 * merely a notifier, which can be called from any CPU.
5426 * Changing the TSC frequency at arbitrary points in time
5427 * requires a recomputation of local variables related to
5428 * the TSC for each VCPU. We must flag these local variables
5429 * to be updated and be sure the update takes place with the
5430 * new frequency before any guests proceed.
5431 *
5432 * Unfortunately, the combination of hotplug CPU and frequency
5433 * change creates an intractable locking scenario; the order
5434 * of when these callouts happen is undefined with respect to
5435 * CPU hotplug, and they can race with each other. As such,
5436 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5437 * undefined; you can actually have a CPU frequency change take
5438 * place in between the computation of X and the setting of the
5439 * variable. To protect against this problem, all updates of
5440 * the per_cpu tsc_khz variable are done in an interrupt
5441 * protected IPI, and all callers wishing to update the value
5442 * must wait for a synchronous IPI to complete (which is trivial
5443 * if the caller is on the CPU already). This establishes the
5444 * necessary total order on variable updates.
5445 *
5446 * Note that because a guest time update may take place
5447 * anytime after the setting of the VCPU's request bit, the
5448 * correct TSC value must be set before the request. However,
5449 * to ensure the update actually makes it to any guest which
5450 * starts running in hardware virtualization between the set
5451 * and the acquisition of the spinlock, we must also ping the
5452 * CPU after setting the request bit.
5453 *
5454 */
5455
c8076604
GH		 5456 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5457 return 0;
5458 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5459 return 0;
8cfdc000
ZA		 5460
5461 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5462
2f303b74 5463 spin_lock(&kvm_lock);
c8076604 5464 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5465 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5466 if (vcpu->cpu != freq->cpu)
5467 continue;
c285545f 5468 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5469 if (vcpu->cpu != smp_processor_id())
8cfdc000 5470 send_ipi = 1;
c8076604
GH		 5471 }
5472 }
2f303b74 5473 spin_unlock(&kvm_lock);
c8076604
GH		 5474
5475 if (freq->old < freq->new && send_ipi) {
5476 /*
5477 * We upscale the frequency. Must make the guest
5478 * doesn't see old kvmclock values while running with
5479 * the new frequency, otherwise we risk the guest sees
5480 * time go backwards.
5481 *
5482 * In case we update the frequency for another cpu
5483 * (which might be in guest context) send an interrupt
5484 * to kick the cpu out of guest context. Next time
5485 * guest context is entered kvmclock will be updated,
5486 * so the guest will not see stale values.
5487 */
8cfdc000 5488 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5489 }
5490 return 0;
5491}
5492
5493static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5494 .notifier_call = kvmclock_cpufreq_notifier
5495};
5496
5497static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5498 unsigned long action, void *hcpu)
5499{
5500 unsigned int cpu = (unsigned long)hcpu;
5501
5502 switch (action) {
5503 case CPU_ONLINE:
5504 case CPU_DOWN_FAILED:
5505 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5506 break;
5507 case CPU_DOWN_PREPARE:
5508 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5509 break;
5510 }
5511 return NOTIFY_OK;
5512}
5513
5514static struct notifier_block kvmclock_cpu_notifier_block = {
5515 .notifier_call = kvmclock_cpu_notifier,
5516 .priority = -INT_MAX
c8076604
GH		 5517};
5518
b820cc0c
ZA		 5519static void kvm_timer_init(void)
5520{
5521 int cpu;
5522
c285545f 5523 max_tsc_khz = tsc_khz;
460dd42e
SB		 5524
5525 cpu_notifier_register_begin();
b820cc0c 5526 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5527#ifdef CONFIG_CPU_FREQ
5528 struct cpufreq_policy policy;
5529 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5530 cpu = get_cpu();
5531 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5532 if (policy.cpuinfo.max_freq)
5533 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5534 put_cpu();
c285545f 5535#endif
b820cc0c
ZA		 5536 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5537 CPUFREQ_TRANSITION_NOTIFIER);
5538 }
c285545f 5539 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5540 for_each_online_cpu(cpu)
5541 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5542
5543 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5544 cpu_notifier_register_done();
5545
b820cc0c
ZA		 5546}
5547
ff9d07a0
ZY		 5548static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5549
f5132b01 5550int kvm_is_in_guest(void)
ff9d07a0 5551{
086c9855 5552 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5553}
5554
5555static int kvm_is_user_mode(void)
5556{
5557 int user_mode = 3;
dcf46b94 5558
086c9855
AS		 5559 if (__this_cpu_read(current_vcpu))
5560 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5561
ff9d07a0
ZY		 5562 return user_mode != 0;
5563}
5564
5565static unsigned long kvm_get_guest_ip(void)
5566{
5567 unsigned long ip = 0;
dcf46b94 5568
086c9855
AS		 5569 if (__this_cpu_read(current_vcpu))
5570 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5571
ff9d07a0
ZY		 5572 return ip;
5573}
5574
5575static struct perf_guest_info_callbacks kvm_guest_cbs = {
5576 .is_in_guest = kvm_is_in_guest,
5577 .is_user_mode = kvm_is_user_mode,
5578 .get_guest_ip = kvm_get_guest_ip,
5579};
5580
5581void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5582{
086c9855 5583 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5584}
5585EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5586
5587void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5588{
086c9855 5589 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5590}
5591EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5592
ce88decf
XG		 5593static void kvm_set_mmio_spte_mask(void)
5594{
5595 u64 mask;
5596 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5597
5598 /*
5599 * Set the reserved bits and the present bit of an paging-structure
5600 * entry to generate page fault with PFER.RSV = 1.
5601 */
885032b9 5602 /* Mask the reserved physical address bits. */
d1431483 5603 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5604
5605 /* Bit 62 is always reserved for 32bit host. */
5606 mask |= 0x3ull << 62;
5607
5608 /* Set the present bit. */
ce88decf
XG		 5609 mask |= 1ull;
5610
5611#ifdef CONFIG_X86_64
5612 /*
5613 * If reserved bit is not supported, clear the present bit to disable
5614 * mmio page fault.
5615 */
5616 if (maxphyaddr == 52)
5617 mask &= ~1ull;
5618#endif
5619
5620 kvm_mmu_set_mmio_spte_mask(mask);
5621}
5622
16e8d74d
MT		 5623#ifdef CONFIG_X86_64
5624static void pvclock_gtod_update_fn(struct work_struct *work)
5625{
d828199e
MT		 5626 struct kvm *kvm;
5627
5628 struct kvm_vcpu *vcpu;
5629 int i;
5630
2f303b74 5631 spin_lock(&kvm_lock);
d828199e
MT		 5632 list_for_each_entry(kvm, &vm_list, vm_list)
5633 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5634 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5635 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5636 spin_unlock(&kvm_lock);
16e8d74d
MT		 5637}
5638
5639static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5640
5641/*
5642 * Notification about pvclock gtod data update.
5643 */
5644static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5645 void *priv)
5646{
5647 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5648 struct timekeeper *tk = priv;
5649
5650 update_pvclock_gtod(tk);
5651
5652 /* disable master clock if host does not trust, or does not
5653 * use, TSC clocksource
5654 */
5655 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5656 atomic_read(&kvm_guest_has_master_clock) != 0)
5657 queue_work(system_long_wq, &pvclock_gtod_work);
5658
5659 return 0;
5660}
5661
5662static struct notifier_block pvclock_gtod_notifier = {
5663 .notifier_call = pvclock_gtod_notify,
5664};
5665#endif
5666
f8c16bba 5667int kvm_arch_init(void *opaque)
043405e1 5668{
b820cc0c 5669 int r;
6b61edf7 5670 struct kvm_x86_ops *ops = opaque;
f8c16bba 5671
f8c16bba
ZX		 5672 if (kvm_x86_ops) {
5673 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5674 r = -EEXIST;
5675 goto out;
f8c16bba
ZX		 5676 }
5677
5678 if (!ops->cpu_has_kvm_support()) {
5679 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5680 r = -EOPNOTSUPP;
5681 goto out;
f8c16bba
ZX		 5682 }
5683 if (ops->disabled_by_bios()) {
5684 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5685 r = -EOPNOTSUPP;
5686 goto out;
f8c16bba
ZX		 5687 }
5688
013f6a5d
MT		 5689 r = -ENOMEM;
5690 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5691 if (!shared_msrs) {
5692 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5693 goto out;
5694 }
5695
97db56ce
AK		 5696 r = kvm_mmu_module_init();
5697 if (r)
013f6a5d 5698 goto out_free_percpu;
97db56ce 5699
ce88decf 5700 kvm_set_mmio_spte_mask();
97db56ce 5701
f8c16bba 5702 kvm_x86_ops = ops;
920c8377 5703
7b52345e 5704 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5705 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5706
b820cc0c 5707 kvm_timer_init();
c8076604 5708
ff9d07a0
ZY		 5709 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5710
2acf923e
DC		 5711 if (cpu_has_xsave)
5712 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5713
c5cc421b 5714 kvm_lapic_init();
16e8d74d
MT		 5715#ifdef CONFIG_X86_64
5716 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5717#endif
5718
f8c16bba 5719 return 0;
56c6d28a 5720
013f6a5d
MT		 5721out_free_percpu:
5722 free_percpu(shared_msrs);
56c6d28a 5723out:
56c6d28a 5724 return r;
043405e1 5725}
8776e519 5726
f8c16bba
ZX		 5727void kvm_arch_exit(void)
5728{
ff9d07a0
ZY		 5729 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5730
888d256e
JK		 5731 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5732 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5733 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5734 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5735#ifdef CONFIG_X86_64
5736 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5737#endif
f8c16bba 5738 kvm_x86_ops = NULL;
56c6d28a 5739 kvm_mmu_module_exit();
013f6a5d 5740 free_percpu(shared_msrs);
56c6d28a 5741}
f8c16bba 5742
5cb56059 5743int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5744{
5745 ++vcpu->stat.halt_exits;
35754c98 5746 if (lapic_in_kernel(vcpu)) {
a4535290 5747 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5748 return 1;
5749 } else {
5750 vcpu->run->exit_reason = KVM_EXIT_HLT;
5751 return 0;
5752 }
5753}
5cb56059
JS		 5754EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5755
5756int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5757{
5758 kvm_x86_ops->skip_emulated_instruction(vcpu);
5759 return kvm_vcpu_halt(vcpu);
5760}
8776e519
HB		 5761EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5762
6aef266c
SV		 5763/*
5764 * kvm_pv_kick_cpu_op: Kick a vcpu.
5765 *
5766 * @apicid - apicid of vcpu to be kicked.
5767 */
5768static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5769{
24d2166b 5770 struct kvm_lapic_irq lapic_irq;
6aef266c 5771
24d2166b
R		 5772 lapic_irq.shorthand = 0;
5773 lapic_irq.dest_mode = 0;
5774 lapic_irq.dest_id = apicid;
93bbf0b8 5775 lapic_irq.msi_redir_hint = false;
6aef266c 5776
24d2166b 5777 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5778 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5779}
5780
8776e519
HB		 5781int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5782{
5783 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5784 int op_64_bit, r = 1;
8776e519 5785
5cb56059
JS		 5786 kvm_x86_ops->skip_emulated_instruction(vcpu);
5787
55cd8e5a
GN		 5788 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5789 return kvm_hv_hypercall(vcpu);
5790
5fdbf976
MT		 5791 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5792 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5793 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5794 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5795 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5796
229456fc 5797 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5798
a449c7aa
NA		 5799 op_64_bit = is_64_bit_mode(vcpu);
5800 if (!op_64_bit) {
8776e519
HB		 5801 nr &= 0xFFFFFFFF;
5802 a0 &= 0xFFFFFFFF;
5803 a1 &= 0xFFFFFFFF;
5804 a2 &= 0xFFFFFFFF;
5805 a3 &= 0xFFFFFFFF;
5806 }
5807
07708c4a
JK		 5808 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5809 ret = -KVM_EPERM;
5810 goto out;
5811 }
5812
8776e519 5813 switch (nr) {
b93463aa
AK		 5814 case KVM_HC_VAPIC_POLL_IRQ:
5815 ret = 0;
5816 break;
6aef266c
SV		 5817 case KVM_HC_KICK_CPU:
5818 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5819 ret = 0;
5820 break;
8776e519
HB		 5821 default:
5822 ret = -KVM_ENOSYS;
5823 break;
5824 }
07708c4a 5825out:
a449c7aa
NA		 5826 if (!op_64_bit)
5827 ret = (u32)ret;
5fdbf976 5828 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5829 ++vcpu->stat.hypercalls;
2f333bcb 5830 return r;
8776e519
HB		 5831}
5832EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5833
b6785def 5834static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5835{
d6aa1000 5836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5837 char instruction[3];
5fdbf976 5838 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5839
8776e519 5840 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5841
9d74191a 5842 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5843}
5844
b6c7a5dc
HB		 5845/*
5846 * Check if userspace requested an interrupt window, and that the
5847 * interrupt window is open.
5848 *
5849 * No need to exit to userspace if we already have an interrupt queued.
5850 */
851ba692 5851static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5852{
1c1a9ce9
SR		 5853 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5854 return false;
5855
5856 if (kvm_cpu_has_interrupt(vcpu))
5857 return false;
5858
5859 return (irqchip_split(vcpu->kvm)
5860 ? kvm_apic_accept_pic_intr(vcpu)
5861 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5862}
5863
851ba692 5864static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5865{
851ba692
AK		 5866 struct kvm_run *kvm_run = vcpu->run;
5867
91586a3b 5868 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5869 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5870 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5871 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5872 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5873 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5874 kvm_arch_interrupt_allowed(vcpu) &&
5875 !kvm_cpu_has_interrupt(vcpu) &&
5876 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5877 else if (!pic_in_kernel(vcpu->kvm))
5878 kvm_run->ready_for_interrupt_injection =
5879 kvm_apic_accept_pic_intr(vcpu) &&
5880 !kvm_cpu_has_interrupt(vcpu);
5881 else
5882 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5883}
5884
95ba8273
GN		 5885static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5886{
5887 int max_irr, tpr;
5888
5889 if (!kvm_x86_ops->update_cr8_intercept)
5890 return;
5891
88c808fd
AK		 5892 if (!vcpu->arch.apic)
5893 return;
5894
8db3baa2
GN		 5895 if (!vcpu->arch.apic->vapic_addr)
5896 max_irr = kvm_lapic_find_highest_irr(vcpu);
5897 else
5898 max_irr = -1;
95ba8273
GN		 5899
5900 if (max_irr != -1)
5901 max_irr >>= 4;
5902
5903 tpr = kvm_lapic_get_cr8(vcpu);
5904
5905 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5906}
5907
b6b8a145 5908static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5909{
b6b8a145
JK		 5910 int r;
5911
95ba8273 5912 /* try to reinject previous events if any */
b59bb7bd 5913 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5914 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5915 vcpu->arch.exception.has_error_code,
5916 vcpu->arch.exception.error_code);
d6e8c854
NA		 5917
5918 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5919 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5920 X86_EFLAGS_RF);
5921
6bdf0662
NA		 5922 if (vcpu->arch.exception.nr == DB_VECTOR &&
5923 (vcpu->arch.dr7 & DR7_GD)) {
5924 vcpu->arch.dr7 &= ~DR7_GD;
5925 kvm_update_dr7(vcpu);
5926 }
5927
b59bb7bd
GN		 5928 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5929 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5930 vcpu->arch.exception.error_code,
5931 vcpu->arch.exception.reinject);
b6b8a145 5932 return 0;
b59bb7bd
GN		 5933 }
5934
95ba8273
GN		 5935 if (vcpu->arch.nmi_injected) {
5936 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5937 return 0;
95ba8273
GN		 5938 }
5939
5940 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5941 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5942 return 0;
5943 }
5944
5945 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5946 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5947 if (r != 0)
5948 return r;
95ba8273
GN		 5949 }
5950
5951 /* try to inject new event if pending */
5952 if (vcpu->arch.nmi_pending) {
5953 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5954 --vcpu->arch.nmi_pending;
95ba8273
GN		 5955 vcpu->arch.nmi_injected = true;
5956 kvm_x86_ops->set_nmi(vcpu);
5957 }
c7c9c56c 5958 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5959 /*
5960 * Because interrupts can be injected asynchronously, we are
5961 * calling check_nested_events again here to avoid a race condition.
5962 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5963 * proposal and current concerns. Perhaps we should be setting
5964 * KVM_REQ_EVENT only on certain events and not unconditionally?
5965 */
5966 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5967 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5968 if (r != 0)
5969 return r;
5970 }
95ba8273 5971 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5972 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5973 false);
5974 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5975 }
5976 }
b6b8a145 5977 return 0;
95ba8273
GN		 5978}
5979
7460fb4a
AK		 5980static void process_nmi(struct kvm_vcpu *vcpu)
5981{
5982 unsigned limit = 2;
5983
5984 /*
5985 * x86 is limited to one NMI running, and one NMI pending after it.
5986 * If an NMI is already in progress, limit further NMIs to just one.
5987 * Otherwise, allow two (and we'll inject the first one immediately).
5988 */
5989 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5990 limit = 1;
5991
5992 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5993 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5994 kvm_make_request(KVM_REQ_EVENT, vcpu);
5995}
5996
660a5d51
PB		 5997#define put_smstate(type, buf, offset, val) \
5998 *(type *)((buf) + (offset) - 0x7e00) = val
5999
6000static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6001{
6002 u32 flags = 0;
6003 flags |= seg->g << 23;
6004 flags |= seg->db << 22;
6005 flags |= seg->l << 21;
6006 flags |= seg->avl << 20;
6007 flags |= seg->present << 15;
6008 flags |= seg->dpl << 13;
6009 flags |= seg->s << 12;
6010 flags |= seg->type << 8;
6011 return flags;
6012}
6013
6014static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6015{
6016 struct kvm_segment seg;
6017 int offset;
6018
6019 kvm_get_segment(vcpu, &seg, n);
6020 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6021
6022 if (n < 3)
6023 offset = 0x7f84 + n * 12;
6024 else
6025 offset = 0x7f2c + (n - 3) * 12;
6026
6027 put_smstate(u32, buf, offset + 8, seg.base);
6028 put_smstate(u32, buf, offset + 4, seg.limit);
6029 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6030}
6031
efbb288a 6032#ifdef CONFIG_X86_64
660a5d51
PB		 6033static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6034{
6035 struct kvm_segment seg;
6036 int offset;
6037 u16 flags;
6038
6039 kvm_get_segment(vcpu, &seg, n);
6040 offset = 0x7e00 + n * 16;
6041
6042 flags = process_smi_get_segment_flags(&seg) >> 8;
6043 put_smstate(u16, buf, offset, seg.selector);
6044 put_smstate(u16, buf, offset + 2, flags);
6045 put_smstate(u32, buf, offset + 4, seg.limit);
6046 put_smstate(u64, buf, offset + 8, seg.base);
6047}
efbb288a 6048#endif
660a5d51
PB		 6049
6050static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6051{
6052 struct desc_ptr dt;
6053 struct kvm_segment seg;
6054 unsigned long val;
6055 int i;
6056
6057 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6058 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6059 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6060 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6061
6062 for (i = 0; i < 8; i++)
6063 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6064
6065 kvm_get_dr(vcpu, 6, &val);
6066 put_smstate(u32, buf, 0x7fcc, (u32)val);
6067 kvm_get_dr(vcpu, 7, &val);
6068 put_smstate(u32, buf, 0x7fc8, (u32)val);
6069
6070 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6071 put_smstate(u32, buf, 0x7fc4, seg.selector);
6072 put_smstate(u32, buf, 0x7f64, seg.base);
6073 put_smstate(u32, buf, 0x7f60, seg.limit);
6074 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6075
6076 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6077 put_smstate(u32, buf, 0x7fc0, seg.selector);
6078 put_smstate(u32, buf, 0x7f80, seg.base);
6079 put_smstate(u32, buf, 0x7f7c, seg.limit);
6080 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6081
6082 kvm_x86_ops->get_gdt(vcpu, &dt);
6083 put_smstate(u32, buf, 0x7f74, dt.address);
6084 put_smstate(u32, buf, 0x7f70, dt.size);
6085
6086 kvm_x86_ops->get_idt(vcpu, &dt);
6087 put_smstate(u32, buf, 0x7f58, dt.address);
6088 put_smstate(u32, buf, 0x7f54, dt.size);
6089
6090 for (i = 0; i < 6; i++)
6091 process_smi_save_seg_32(vcpu, buf, i);
6092
6093 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6094
6095 /* revision id */
6096 put_smstate(u32, buf, 0x7efc, 0x00020000);
6097 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6098}
6099
6100static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6101{
6102#ifdef CONFIG_X86_64
6103 struct desc_ptr dt;
6104 struct kvm_segment seg;
6105 unsigned long val;
6106 int i;
6107
6108 for (i = 0; i < 16; i++)
6109 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6110
6111 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6112 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6113
6114 kvm_get_dr(vcpu, 6, &val);
6115 put_smstate(u64, buf, 0x7f68, val);
6116 kvm_get_dr(vcpu, 7, &val);
6117 put_smstate(u64, buf, 0x7f60, val);
6118
6119 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6120 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6121 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6122
6123 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6124
6125 /* revision id */
6126 put_smstate(u32, buf, 0x7efc, 0x00020064);
6127
6128 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6129
6130 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6131 put_smstate(u16, buf, 0x7e90, seg.selector);
6132 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6133 put_smstate(u32, buf, 0x7e94, seg.limit);
6134 put_smstate(u64, buf, 0x7e98, seg.base);
6135
6136 kvm_x86_ops->get_idt(vcpu, &dt);
6137 put_smstate(u32, buf, 0x7e84, dt.size);
6138 put_smstate(u64, buf, 0x7e88, dt.address);
6139
6140 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6141 put_smstate(u16, buf, 0x7e70, seg.selector);
6142 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6143 put_smstate(u32, buf, 0x7e74, seg.limit);
6144 put_smstate(u64, buf, 0x7e78, seg.base);
6145
6146 kvm_x86_ops->get_gdt(vcpu, &dt);
6147 put_smstate(u32, buf, 0x7e64, dt.size);
6148 put_smstate(u64, buf, 0x7e68, dt.address);
6149
6150 for (i = 0; i < 6; i++)
6151 process_smi_save_seg_64(vcpu, buf, i);
6152#else
6153 WARN_ON_ONCE(1);
6154#endif
6155}
6156
64d60670
PB		 6157static void process_smi(struct kvm_vcpu *vcpu)
6158{
660a5d51 6159 struct kvm_segment cs, ds;
18c3626e 6160 struct desc_ptr dt;
660a5d51
PB		 6161 char buf[512];
6162 u32 cr0;
6163
64d60670
PB		 6164 if (is_smm(vcpu)) {
6165 vcpu->arch.smi_pending = true;
6166 return;
6167 }
6168
660a5d51
PB		 6169 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6170 vcpu->arch.hflags |= HF_SMM_MASK;
6171 memset(buf, 0, 512);
6172 if (guest_cpuid_has_longmode(vcpu))
6173 process_smi_save_state_64(vcpu, buf);
6174 else
6175 process_smi_save_state_32(vcpu, buf);
6176
54bf36aa 6177 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6178
6179 if (kvm_x86_ops->get_nmi_mask(vcpu))
6180 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6181 else
6182 kvm_x86_ops->set_nmi_mask(vcpu, true);
6183
6184 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6185 kvm_rip_write(vcpu, 0x8000);
6186
6187 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6188 kvm_x86_ops->set_cr0(vcpu, cr0);
6189 vcpu->arch.cr0 = cr0;
6190
6191 kvm_x86_ops->set_cr4(vcpu, 0);
6192
18c3626e
PB		 6193 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6194 dt.address = dt.size = 0;
6195 kvm_x86_ops->set_idt(vcpu, &dt);
6196
660a5d51
PB		 6197 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6198
6199 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6200 cs.base = vcpu->arch.smbase;
6201
6202 ds.selector = 0;
6203 ds.base = 0;
6204
6205 cs.limit = ds.limit = 0xffffffff;
6206 cs.type = ds.type = 0x3;
6207 cs.dpl = ds.dpl = 0;
6208 cs.db = ds.db = 0;
6209 cs.s = ds.s = 1;
6210 cs.l = ds.l = 0;
6211 cs.g = ds.g = 1;
6212 cs.avl = ds.avl = 0;
6213 cs.present = ds.present = 1;
6214 cs.unusable = ds.unusable = 0;
6215 cs.padding = ds.padding = 0;
6216
6217 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6218 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6219 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6220 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6221 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6222 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6223
6224 if (guest_cpuid_has_longmode(vcpu))
6225 kvm_x86_ops->set_efer(vcpu, 0);
6226
6227 kvm_update_cpuid(vcpu);
6228 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6229}
6230
3d81bc7e 6231static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6232{
3d81bc7e
YZ		 6233 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6234 return;
c7c9c56c 6235
3bb345f3 6236 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6237
b053b2ae
SR		 6238 if (irqchip_split(vcpu->kvm))
6239 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb
RK		 6240 else {
6241 kvm_x86_ops->sync_pir_to_irr(vcpu);
b053b2ae 6242 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb 6243 }
3bb345f3 6244 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6245}
6246
a70656b6
RK		 6247static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6248{
6249 ++vcpu->stat.tlb_flush;
6250 kvm_x86_ops->tlb_flush(vcpu);
6251}
6252
4256f43f
TC		 6253void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6254{
c24ae0dc
TC		 6255 struct page *page = NULL;
6256
35754c98 6257 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6258 return;
6259
4256f43f
TC		 6260 if (!kvm_x86_ops->set_apic_access_page_addr)
6261 return;
6262
c24ae0dc 6263 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6264 if (is_error_page(page))
6265 return;
c24ae0dc
TC		 6266 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6267
6268 /*
6269 * Do not pin apic access page in memory, the MMU notifier
6270 * will call us again if it is migrated or swapped out.
6271 */
6272 put_page(page);
4256f43f
TC		 6273}
6274EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6275
fe71557a
TC		 6276void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6277 unsigned long address)
6278{
c24ae0dc
TC		 6279 /*
6280 * The physical address of apic access page is stored in the VMCS.
6281 * Update it when it becomes invalid.
6282 */
6283 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6284 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6285}
6286
9357d939 6287/*
362c698f 6288 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6289 * exiting to the userspace. Otherwise, the value will be returned to the
6290 * userspace.
6291 */
851ba692 6292static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6293{
6294 int r;
35754c98 6295 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6296 vcpu->run->request_interrupt_window;
730dca42 6297 bool req_immediate_exit = false;
b6c7a5dc 6298
3e007509 6299 if (vcpu->requests) {
a8eeb04a 6300 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6301 kvm_mmu_unload(vcpu);
a8eeb04a 6302 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6303 __kvm_migrate_timers(vcpu);
d828199e
MT		 6304 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6305 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6306 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6307 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6308 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6309 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6310 if (unlikely(r))
6311 goto out;
6312 }
a8eeb04a 6313 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6314 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6315 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6316 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6317 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6318 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6319 r = 0;
6320 goto out;
6321 }
a8eeb04a 6322 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6323 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6324 r = 0;
6325 goto out;
6326 }
a8eeb04a 6327 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6328 vcpu->fpu_active = 0;
6329 kvm_x86_ops->fpu_deactivate(vcpu);
6330 }
af585b92
GN		 6331 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6332 /* Page is swapped out. Do synthetic halt */
6333 vcpu->arch.apf.halted = true;
6334 r = 1;
6335 goto out;
6336 }
c9aaa895
GC		 6337 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6338 record_steal_time(vcpu);
64d60670
PB		 6339 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6340 process_smi(vcpu);
7460fb4a
AK		 6341 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6342 process_nmi(vcpu);
f5132b01 6343 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6344 kvm_pmu_handle_event(vcpu);
f5132b01 6345 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6346 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6347 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6348 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6349 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6350 (void *) vcpu->arch.eoi_exit_bitmap)) {
6351 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6352 vcpu->run->eoi.vector =
6353 vcpu->arch.pending_ioapic_eoi;
6354 r = 0;
6355 goto out;
6356 }
6357 }
3d81bc7e
YZ		 6358 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6359 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6360 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6361 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6362 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6363 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6364 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6365 r = 0;
6366 goto out;
6367 }
e516cebb
AS		 6368 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6369 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6370 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6371 r = 0;
6372 goto out;
6373 }
2f52d58c 6374 }
b93463aa 6375
bf9f6ac8
FW		 6376 /*
6377 * KVM_REQ_EVENT is not set when posted interrupts are set by
6378 * VT-d hardware, so we have to update RVI unconditionally.
6379 */
6380 if (kvm_lapic_enabled(vcpu)) {
6381 /*
6382 * Update architecture specific hints for APIC
6383 * virtual interrupt delivery.
6384 */
6385 if (kvm_x86_ops->hwapic_irr_update)
6386 kvm_x86_ops->hwapic_irr_update(vcpu,
6387 kvm_lapic_find_highest_irr(vcpu));
6388 }
6389
b463a6f7 6390 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6391 kvm_apic_accept_events(vcpu);
6392 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6393 r = 1;
6394 goto out;
6395 }
6396
b6b8a145
JK		 6397 if (inject_pending_event(vcpu, req_int_win) != 0)
6398 req_immediate_exit = true;
b463a6f7 6399 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6400 else if (vcpu->arch.nmi_pending)
c9a7953f 6401 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6402 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6403 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6404
6405 if (kvm_lapic_enabled(vcpu)) {
6406 update_cr8_intercept(vcpu);
6407 kvm_lapic_sync_to_vapic(vcpu);
6408 }
6409 }
6410
d8368af8
AK		 6411 r = kvm_mmu_reload(vcpu);
6412 if (unlikely(r)) {
d905c069 6413 goto cancel_injection;
d8368af8
AK		 6414 }
6415
b6c7a5dc
HB		 6416 preempt_disable();
6417
6418 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6419 if (vcpu->fpu_active)
6420 kvm_load_guest_fpu(vcpu);
2acf923e 6421 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6422
6b7e2d09
XG		 6423 vcpu->mode = IN_GUEST_MODE;
6424
01b71917
MT		 6425 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6426
6b7e2d09
XG		 6427 /* We should set ->mode before check ->requests,
6428 * see the comment in make_all_cpus_request.
6429 */
01b71917 6430 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6431
d94e1dc9 6432 local_irq_disable();
32f88400 6433
6b7e2d09 6434 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6435 || need_resched() || signal_pending(current)) {
6b7e2d09 6436 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6437 smp_wmb();
6c142801
AK		 6438 local_irq_enable();
6439 preempt_enable();
01b71917 6440 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6441 r = 1;
d905c069 6442 goto cancel_injection;
6c142801
AK		 6443 }
6444
d6185f20
NHE		 6445 if (req_immediate_exit)
6446 smp_send_reschedule(vcpu->cpu);
6447
ccf73aaf 6448 __kvm_guest_enter();
b6c7a5dc 6449
42dbaa5a 6450 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6451 set_debugreg(0, 7);
6452 set_debugreg(vcpu->arch.eff_db[0], 0);
6453 set_debugreg(vcpu->arch.eff_db[1], 1);
6454 set_debugreg(vcpu->arch.eff_db[2], 2);
6455 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6456 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6457 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6458 }
b6c7a5dc 6459
229456fc 6460 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6461 wait_lapic_expire(vcpu);
851ba692 6462 kvm_x86_ops->run(vcpu);
b6c7a5dc 6463
c77fb5fe
PB		 6464 /*
6465 * Do this here before restoring debug registers on the host. And
6466 * since we do this before handling the vmexit, a DR access vmexit
6467 * can (a) read the correct value of the debug registers, (b) set
6468 * KVM_DEBUGREG_WONT_EXIT again.
6469 */
6470 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6471 int i;
6472
6473 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6474 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6475 for (i = 0; i < KVM_NR_DB_REGS; i++)
6476 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6477 }
6478
24f1e32c
FW		 6479 /*
6480 * If the guest has used debug registers, at least dr7
6481 * will be disabled while returning to the host.
6482 * If we don't have active breakpoints in the host, we don't
6483 * care about the messed up debug address registers. But if
6484 * we have some of them active, restore the old state.
6485 */
59d8eb53 6486 if (hw_breakpoint_active())
24f1e32c 6487 hw_breakpoint_restore();
42dbaa5a 6488
886b470c 6489 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
4ea1636b 6490 rdtsc());
1d5f066e 6491
6b7e2d09 6492 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6493 smp_wmb();
a547c6db
YZ		 6494
6495 /* Interrupt is enabled by handle_external_intr() */
6496 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6497
6498 ++vcpu->stat.exits;
6499
6500 /*
6501 * We must have an instruction between local_irq_enable() and
6502 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6503 * the interrupt shadow. The stat.exits increment will do nicely.
6504 * But we need to prevent reordering, hence this barrier():
6505 */
6506 barrier();
6507
6508 kvm_guest_exit();
6509
6510 preempt_enable();
6511
f656ce01 6512 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6513
b6c7a5dc
HB		 6514 /*
6515 * Profile KVM exit RIPs:
6516 */
6517 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6518 unsigned long rip = kvm_rip_read(vcpu);
6519 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6520 }
6521
cc578287
ZA		 6522 if (unlikely(vcpu->arch.tsc_always_catchup))
6523 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6524
5cfb1d5a
MT		 6525 if (vcpu->arch.apic_attention)
6526 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6527
851ba692 6528 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6529 return r;
6530
6531cancel_injection:
6532 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6533 if (unlikely(vcpu->arch.apic_attention))
6534 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6535out:
6536 return r;
6537}
b6c7a5dc 6538
362c698f
PB		 6539static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6540{
bf9f6ac8
FW		 6541 if (!kvm_arch_vcpu_runnable(vcpu) &&
6542 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6543 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6544 kvm_vcpu_block(vcpu);
6545 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6546
6547 if (kvm_x86_ops->post_block)
6548 kvm_x86_ops->post_block(vcpu);
6549
9c8fd1ba
PB		 6550 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6551 return 1;
6552 }
362c698f
PB		 6553
6554 kvm_apic_accept_events(vcpu);
6555 switch(vcpu->arch.mp_state) {
6556 case KVM_MP_STATE_HALTED:
6557 vcpu->arch.pv.pv_unhalted = false;
6558 vcpu->arch.mp_state =
6559 KVM_MP_STATE_RUNNABLE;
6560 case KVM_MP_STATE_RUNNABLE:
6561 vcpu->arch.apf.halted = false;
6562 break;
6563 case KVM_MP_STATE_INIT_RECEIVED:
6564 break;
6565 default:
6566 return -EINTR;
6567 break;
6568 }
6569 return 1;
6570}
09cec754 6571
5d9bc648
PB		 6572static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6573{
6574 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6575 !vcpu->arch.apf.halted);
6576}
6577
362c698f 6578static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6579{
6580 int r;
f656ce01 6581 struct kvm *kvm = vcpu->kvm;
d7690175 6582
f656ce01 6583 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6584
362c698f 6585 for (;;) {
58f800d5 6586 if (kvm_vcpu_running(vcpu)) {
851ba692 6587 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6588 } else {
362c698f 6589 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6590 }
6591
09cec754
GN		 6592 if (r <= 0)
6593 break;
6594
6595 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6596 if (kvm_cpu_has_pending_timer(vcpu))
6597 kvm_inject_pending_timer_irqs(vcpu);
6598
851ba692 6599 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6600 r = 0;
6601 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6602 ++vcpu->stat.request_irq_exits;
362c698f 6603 break;
09cec754 6604 }
af585b92
GN		 6605
6606 kvm_check_async_pf_completion(vcpu);
6607
09cec754
GN		 6608 if (signal_pending(current)) {
6609 r = -EINTR;
851ba692 6610 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6611 ++vcpu->stat.signal_exits;
362c698f 6612 break;
09cec754
GN		 6613 }
6614 if (need_resched()) {
f656ce01 6615 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6616 cond_resched();
f656ce01 6617 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6618 }
b6c7a5dc
HB		 6619 }
6620
f656ce01 6621 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6622
6623 return r;
6624}
6625
716d51ab
GN		 6626static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6627{
6628 int r;
6629 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6630 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6631 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6632 if (r != EMULATE_DONE)
6633 return 0;
6634 return 1;
6635}
6636
6637static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6638{
6639 BUG_ON(!vcpu->arch.pio.count);
6640
6641 return complete_emulated_io(vcpu);
6642}
6643
f78146b0
AK		 6644/*
6645 * Implements the following, as a state machine:
6646 *
6647 * read:
6648 * for each fragment
87da7e66
XG		 6649 * for each mmio piece in the fragment
6650 * write gpa, len
6651 * exit
6652 * copy data
f78146b0
AK		 6653 * execute insn
6654 *
6655 * write:
6656 * for each fragment
87da7e66
XG		 6657 * for each mmio piece in the fragment
6658 * write gpa, len
6659 * copy data
6660 * exit
f78146b0 6661 */
716d51ab 6662static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6663{
6664 struct kvm_run *run = vcpu->run;
f78146b0 6665 struct kvm_mmio_fragment *frag;
87da7e66 6666 unsigned len;
5287f194 6667
716d51ab 6668 BUG_ON(!vcpu->mmio_needed);
5287f194 6669
716d51ab 6670 /* Complete previous fragment */
87da7e66
XG		 6671 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6672 len = min(8u, frag->len);
716d51ab 6673 if (!vcpu->mmio_is_write)
87da7e66
XG		 6674 memcpy(frag->data, run->mmio.data, len);
6675
6676 if (frag->len <= 8) {
6677 /* Switch to the next fragment. */
6678 frag++;
6679 vcpu->mmio_cur_fragment++;
6680 } else {
6681 /* Go forward to the next mmio piece. */
6682 frag->data += len;
6683 frag->gpa += len;
6684 frag->len -= len;
6685 }
6686
a08d3b3b 6687 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6688 vcpu->mmio_needed = 0;
0912c977
PB		 6689
6690 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6691 if (vcpu->mmio_is_write)
716d51ab
GN		 6692 return 1;
6693 vcpu->mmio_read_completed = 1;
6694 return complete_emulated_io(vcpu);
6695 }
87da7e66 6696
716d51ab
GN		 6697 run->exit_reason = KVM_EXIT_MMIO;
6698 run->mmio.phys_addr = frag->gpa;
6699 if (vcpu->mmio_is_write)
87da7e66
XG		 6700 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6701 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6702 run->mmio.is_write = vcpu->mmio_is_write;
6703 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6704 return 0;
5287f194
AK		 6705}
6706
716d51ab 6707
b6c7a5dc
HB		 6708int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6709{
c5bedc68 6710 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6711 int r;
6712 sigset_t sigsaved;
6713
c4d72e2d 6714 fpu__activate_curr(fpu);
e5c30142 6715
ac9f6dc0
AK		 6716 if (vcpu->sigset_active)
6717 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6718
a4535290 6719 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6720 kvm_vcpu_block(vcpu);
66450a21 6721 kvm_apic_accept_events(vcpu);
d7690175 6722 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6723 r = -EAGAIN;
6724 goto out;
b6c7a5dc
HB		 6725 }
6726
b6c7a5dc 6727 /* re-sync apic's tpr */
35754c98 6728 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6729 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6730 r = -EINVAL;
6731 goto out;
6732 }
6733 }
b6c7a5dc 6734
716d51ab
GN		 6735 if (unlikely(vcpu->arch.complete_userspace_io)) {
6736 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6737 vcpu->arch.complete_userspace_io = NULL;
6738 r = cui(vcpu);
6739 if (r <= 0)
6740 goto out;
6741 } else
6742 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6743
362c698f 6744 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6745
6746out:
f1d86e46 6747 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6748 if (vcpu->sigset_active)
6749 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6750
b6c7a5dc
HB		 6751 return r;
6752}
6753
6754int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6755{
7ae441ea
GN		 6756 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6757 /*
6758 * We are here if userspace calls get_regs() in the middle of
6759 * instruction emulation. Registers state needs to be copied
4a969980 6760 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6761 * that usually, but some bad designed PV devices (vmware
6762 * backdoor interface) need this to work
6763 */
dd856efa 6764 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6765 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6766 }
5fdbf976
MT		 6767 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6768 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6769 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6770 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6771 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6772 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6773 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6774 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6775#ifdef CONFIG_X86_64
5fdbf976
MT		 6776 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6777 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6778 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6779 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6780 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6781 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6782 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6783 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6784#endif
6785
5fdbf976 6786 regs->rip = kvm_rip_read(vcpu);
91586a3b 6787 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6788
b6c7a5dc
HB		 6789 return 0;
6790}
6791
6792int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6793{
7ae441ea
GN		 6794 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6795 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6796
5fdbf976
MT		 6797 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6798 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6799 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6800 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6801 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6802 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6803 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6804 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6805#ifdef CONFIG_X86_64
5fdbf976
MT		 6806 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6807 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6808 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6809 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6810 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6811 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6812 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6813 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6814#endif
6815
5fdbf976 6816 kvm_rip_write(vcpu, regs->rip);
91586a3b 6817 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6818
b4f14abd
JK		 6819 vcpu->arch.exception.pending = false;
6820
3842d135
AK		 6821 kvm_make_request(KVM_REQ_EVENT, vcpu);
6822
b6c7a5dc
HB		 6823 return 0;
6824}
6825
b6c7a5dc
HB		 6826void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6827{
6828 struct kvm_segment cs;
6829
3e6e0aab 6830 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6831 *db = cs.db;
6832 *l = cs.l;
6833}
6834EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6835
6836int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6837 struct kvm_sregs *sregs)
6838{
89a27f4d 6839 struct desc_ptr dt;
b6c7a5dc 6840
3e6e0aab
GT		 6841 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6842 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6843 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6844 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6845 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6846 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6847
3e6e0aab
GT		 6848 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6849 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6850
6851 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6852 sregs->idt.limit = dt.size;
6853 sregs->idt.base = dt.address;
b6c7a5dc 6854 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6855 sregs->gdt.limit = dt.size;
6856 sregs->gdt.base = dt.address;
b6c7a5dc 6857
4d4ec087 6858 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6859 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6860 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6861 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6862 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6863 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6864 sregs->apic_base = kvm_get_apic_base(vcpu);
6865
923c61bb 6866 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6867
36752c9b 6868 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6869 set_bit(vcpu->arch.interrupt.nr,
6870 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6871
b6c7a5dc
HB		 6872 return 0;
6873}
6874
62d9f0db
MT		 6875int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6876 struct kvm_mp_state *mp_state)
6877{
66450a21 6878 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6879 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6880 vcpu->arch.pv.pv_unhalted)
6881 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6882 else
6883 mp_state->mp_state = vcpu->arch.mp_state;
6884
62d9f0db
MT		 6885 return 0;
6886}
6887
6888int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6889 struct kvm_mp_state *mp_state)
6890{
66450a21
JK		 6891 if (!kvm_vcpu_has_lapic(vcpu) &&
6892 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6893 return -EINVAL;
6894
6895 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6896 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6897 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6898 } else
6899 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6900 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6901 return 0;
6902}
6903
7f3d35fd
KW		 6904int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6905 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6906{
9d74191a 6907 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6908 int ret;
e01c2426 6909
8ec4722d 6910 init_emulate_ctxt(vcpu);
c697518a 6911
7f3d35fd 6912 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6913 has_error_code, error_code);
c697518a 6914
c697518a 6915 if (ret)
19d04437 6916 return EMULATE_FAIL;
37817f29 6917
9d74191a
TY		 6918 kvm_rip_write(vcpu, ctxt->eip);
6919 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6920 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6921 return EMULATE_DONE;
37817f29
IE		 6922}
6923EXPORT_SYMBOL_GPL(kvm_task_switch);
6924
b6c7a5dc
HB		 6925int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6926 struct kvm_sregs *sregs)
6927{
58cb628d 6928 struct msr_data apic_base_msr;
b6c7a5dc 6929 int mmu_reset_needed = 0;
63f42e02 6930 int pending_vec, max_bits, idx;
89a27f4d 6931 struct desc_ptr dt;
b6c7a5dc 6932
6d1068b3
PM		 6933 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6934 return -EINVAL;
6935
89a27f4d
GN		 6936 dt.size = sregs->idt.limit;
6937 dt.address = sregs->idt.base;
b6c7a5dc 6938 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6939 dt.size = sregs->gdt.limit;
6940 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6941 kvm_x86_ops->set_gdt(vcpu, &dt);
6942
ad312c7c 6943 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6944 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6945 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6946 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6947
2d3ad1f4 6948 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6949
f6801dff 6950 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6951 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6952 apic_base_msr.data = sregs->apic_base;
6953 apic_base_msr.host_initiated = true;
6954 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6955
4d4ec087 6956 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6957 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6958 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6959
fc78f519 6960 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6961 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6962 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6963 kvm_update_cpuid(vcpu);
63f42e02
XG		 6964
6965 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6966 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6967 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6968 mmu_reset_needed = 1;
6969 }
63f42e02 6970 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6971
6972 if (mmu_reset_needed)
6973 kvm_mmu_reset_context(vcpu);
6974
a50abc3b 6975 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6976 pending_vec = find_first_bit(
6977 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6978 if (pending_vec < max_bits) {
66fd3f7f 6979 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6980 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6981 }
6982
3e6e0aab
GT		 6983 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6984 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6985 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6986 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6987 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6988 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6989
3e6e0aab
GT		 6990 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6991 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6992
5f0269f5
ME		 6993 update_cr8_intercept(vcpu);
6994
9c3e4aab 6995 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6996 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6997 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6998 !is_protmode(vcpu))
9c3e4aab
MT		 6999 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7000
3842d135
AK		 7001 kvm_make_request(KVM_REQ_EVENT, vcpu);
7002
b6c7a5dc
HB		 7003 return 0;
7004}
7005
d0bfb940
JK		 7006int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7007 struct kvm_guest_debug *dbg)
b6c7a5dc 7008{
355be0b9 7009 unsigned long rflags;
ae675ef0 7010 int i, r;
b6c7a5dc 7011
4f926bf2
JK		 7012 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7013 r = -EBUSY;
7014 if (vcpu->arch.exception.pending)
2122ff5e 7015 goto out;
4f926bf2
JK		 7016 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7017 kvm_queue_exception(vcpu, DB_VECTOR);
7018 else
7019 kvm_queue_exception(vcpu, BP_VECTOR);
7020 }
7021
91586a3b
JK		 7022 /*
7023 * Read rflags as long as potentially injected trace flags are still
7024 * filtered out.
7025 */
7026 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7027
7028 vcpu->guest_debug = dbg->control;
7029 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7030 vcpu->guest_debug = 0;
7031
7032 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7033 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7034 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7035 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7036 } else {
7037 for (i = 0; i < KVM_NR_DB_REGS; i++)
7038 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7039 }
c8639010 7040 kvm_update_dr7(vcpu);
ae675ef0 7041
f92653ee
JK		 7042 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7043 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7044 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7045
91586a3b
JK		 7046 /*
7047 * Trigger an rflags update that will inject or remove the trace
7048 * flags.
7049 */
7050 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7051
c8639010 7052 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7053
4f926bf2 7054 r = 0;
d0bfb940 7055
2122ff5e 7056out:
b6c7a5dc
HB		 7057
7058 return r;
7059}
7060
8b006791
ZX		 7061/*
7062 * Translate a guest virtual address to a guest physical address.
7063 */
7064int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7065 struct kvm_translation *tr)
7066{
7067 unsigned long vaddr = tr->linear_address;
7068 gpa_t gpa;
f656ce01 7069 int idx;
8b006791 7070
f656ce01 7071 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7072 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7073 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7074 tr->physical_address = gpa;
7075 tr->valid = gpa != UNMAPPED_GVA;
7076 tr->writeable = 1;
7077 tr->usermode = 0;
8b006791
ZX		 7078
7079 return 0;
7080}
7081
d0752060
HB		 7082int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7083{
c47ada30 7084 struct fxregs_state *fxsave =
7366ed77 7085 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7086
d0752060
HB		 7087 memcpy(fpu->fpr, fxsave->st_space, 128);
7088 fpu->fcw = fxsave->cwd;
7089 fpu->fsw = fxsave->swd;
7090 fpu->ftwx = fxsave->twd;
7091 fpu->last_opcode = fxsave->fop;
7092 fpu->last_ip = fxsave->rip;
7093 fpu->last_dp = fxsave->rdp;
7094 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7095
d0752060
HB		 7096 return 0;
7097}
7098
7099int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7100{
c47ada30 7101 struct fxregs_state *fxsave =
7366ed77 7102 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7103
d0752060
HB		 7104 memcpy(fxsave->st_space, fpu->fpr, 128);
7105 fxsave->cwd = fpu->fcw;
7106 fxsave->swd = fpu->fsw;
7107 fxsave->twd = fpu->ftwx;
7108 fxsave->fop = fpu->last_opcode;
7109 fxsave->rip = fpu->last_ip;
7110 fxsave->rdp = fpu->last_dp;
7111 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7112
d0752060
HB		 7113 return 0;
7114}
7115
0ee6a517 7116static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7117{
bf935b0b 7118 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7119 if (cpu_has_xsaves)
7366ed77 7120 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7121 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7122
2acf923e
DC		 7123 /*
7124 * Ensure guest xcr0 is valid for loading
7125 */
7126 vcpu->arch.xcr0 = XSTATE_FP;
7127
ad312c7c 7128 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7129}
d0752060
HB		 7130
7131void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7132{
2608d7a1 7133 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7134 return;
7135
2acf923e
DC		 7136 /*
7137 * Restore all possible states in the guest,
7138 * and assume host would use all available bits.
7139 * Guest xcr0 would be loaded later.
7140 */
7141 kvm_put_guest_xcr0(vcpu);
d0752060 7142 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7143 __kernel_fpu_begin();
003e2e8b 7144 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7145 trace_kvm_fpu(1);
d0752060 7146}
d0752060
HB		 7147
7148void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7149{
2acf923e
DC		 7150 kvm_put_guest_xcr0(vcpu);
7151
653f52c3
RR		 7152 if (!vcpu->guest_fpu_loaded) {
7153 vcpu->fpu_counter = 0;
d0752060 7154 return;
653f52c3 7155 }
d0752060
HB		 7156
7157 vcpu->guest_fpu_loaded = 0;
4f836347 7158 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7159 __kernel_fpu_end();
f096ed85 7160 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7161 /*
7162 * If using eager FPU mode, or if the guest is a frequent user
7163 * of the FPU, just leave the FPU active for next time.
7164 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7165 * the FPU in bursts will revert to loading it on demand.
7166 */
a9b4fb7e 7167 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7168 if (++vcpu->fpu_counter < 5)
7169 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7170 }
0c04851c 7171 trace_kvm_fpu(0);
d0752060 7172}
e9b11c17
ZX		 7173
7174void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7175{
12f9a48f 7176 kvmclock_reset(vcpu);
7f1ea208 7177
f5f48ee1 7178 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7179 kvm_x86_ops->vcpu_free(vcpu);
7180}
7181
7182struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7183 unsigned int id)
7184{
c447e76b
LL		 7185 struct kvm_vcpu *vcpu;
7186
6755bae8
ZA		 7187 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7188 printk_once(KERN_WARNING
7189 "kvm: SMP vm created on host with unstable TSC; "
7190 "guest TSC will not be reliable\n");
c447e76b
LL		 7191
7192 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7193
c447e76b 7194 return vcpu;
26e5215f 7195}
e9b11c17 7196
26e5215f
AK		 7197int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7198{
7199 int r;
e9b11c17 7200
19efffa2 7201 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7202 r = vcpu_load(vcpu);
7203 if (r)
7204 return r;
d28bc9dd 7205 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7206 kvm_mmu_setup(vcpu);
e9b11c17 7207 vcpu_put(vcpu);
26e5215f 7208 return r;
e9b11c17
ZX		 7209}
7210
31928aa5 7211void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7212{
8fe8ab46 7213 struct msr_data msr;
332967a3 7214 struct kvm *kvm = vcpu->kvm;
42897d86 7215
31928aa5
DD		 7216 if (vcpu_load(vcpu))
7217 return;
8fe8ab46
WA		 7218 msr.data = 0x0;
7219 msr.index = MSR_IA32_TSC;
7220 msr.host_initiated = true;
7221 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7222 vcpu_put(vcpu);
7223
630994b3
MT		 7224 if (!kvmclock_periodic_sync)
7225 return;
7226
332967a3
AJ		 7227 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7228 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7229}
7230
d40ccc62 7231void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7232{
9fc77441 7233 int r;
344d9588
GN		 7234 vcpu->arch.apf.msr_val = 0;
7235
9fc77441
MT		 7236 r = vcpu_load(vcpu);
7237 BUG_ON(r);
e9b11c17
ZX		 7238 kvm_mmu_unload(vcpu);
7239 vcpu_put(vcpu);
7240
7241 kvm_x86_ops->vcpu_free(vcpu);
7242}
7243
d28bc9dd 7244void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7245{
e69fab5d
PB		 7246 vcpu->arch.hflags = 0;
7247
7460fb4a
AK		 7248 atomic_set(&vcpu->arch.nmi_queued, 0);
7249 vcpu->arch.nmi_pending = 0;
448fa4a9 7250 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7251 kvm_clear_interrupt_queue(vcpu);
7252 kvm_clear_exception_queue(vcpu);
448fa4a9 7253
42dbaa5a 7254 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7255 kvm_update_dr0123(vcpu);
6f43ed01 7256 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7257 kvm_update_dr6(vcpu);
42dbaa5a 7258 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7259 kvm_update_dr7(vcpu);
42dbaa5a 7260
1119022c
NA		 7261 vcpu->arch.cr2 = 0;
7262
3842d135 7263 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7264 vcpu->arch.apf.msr_val = 0;
c9aaa895 7265 vcpu->arch.st.msr_val = 0;
3842d135 7266
12f9a48f
GC		 7267 kvmclock_reset(vcpu);
7268
af585b92
GN		 7269 kvm_clear_async_pf_completion_queue(vcpu);
7270 kvm_async_pf_hash_reset(vcpu);
7271 vcpu->arch.apf.halted = false;
3842d135 7272
64d60670 7273 if (!init_event) {
d28bc9dd 7274 kvm_pmu_reset(vcpu);
64d60670
PB		 7275 vcpu->arch.smbase = 0x30000;
7276 }
f5132b01 7277
66f7b72e
JS		 7278 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7279 vcpu->arch.regs_avail = ~0;
7280 vcpu->arch.regs_dirty = ~0;
7281
d28bc9dd 7282 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7283}
7284
2b4a273b 7285void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7286{
7287 struct kvm_segment cs;
7288
7289 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7290 cs.selector = vector << 8;
7291 cs.base = vector << 12;
7292 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7293 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7294}
7295
13a34e06 7296int kvm_arch_hardware_enable(void)
e9b11c17 7297{
ca84d1a2
ZA		 7298 struct kvm *kvm;
7299 struct kvm_vcpu *vcpu;
7300 int i;
0dd6a6ed
ZA		 7301 int ret;
7302 u64 local_tsc;
7303 u64 max_tsc = 0;
7304 bool stable, backwards_tsc = false;
18863bdd
AK		 7305
7306 kvm_shared_msr_cpu_online();
13a34e06 7307 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7308 if (ret != 0)
7309 return ret;
7310
4ea1636b 7311 local_tsc = rdtsc();
0dd6a6ed
ZA		 7312 stable = !check_tsc_unstable();
7313 list_for_each_entry(kvm, &vm_list, vm_list) {
7314 kvm_for_each_vcpu(i, vcpu, kvm) {
7315 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7316 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7317 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7318 backwards_tsc = true;
7319 if (vcpu->arch.last_host_tsc > max_tsc)
7320 max_tsc = vcpu->arch.last_host_tsc;
7321 }
7322 }
7323 }
7324
7325 /*
7326 * Sometimes, even reliable TSCs go backwards. This happens on
7327 * platforms that reset TSC during suspend or hibernate actions, but
7328 * maintain synchronization. We must compensate. Fortunately, we can
7329 * detect that condition here, which happens early in CPU bringup,
7330 * before any KVM threads can be running. Unfortunately, we can't
7331 * bring the TSCs fully up to date with real time, as we aren't yet far
7332 * enough into CPU bringup that we know how much real time has actually
7333 * elapsed; our helper function, get_kernel_ns() will be using boot
7334 * variables that haven't been updated yet.
7335 *
7336 * So we simply find the maximum observed TSC above, then record the
7337 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7338 * the adjustment will be applied. Note that we accumulate
7339 * adjustments, in case multiple suspend cycles happen before some VCPU
7340 * gets a chance to run again. In the event that no KVM threads get a
7341 * chance to run, we will miss the entire elapsed period, as we'll have
7342 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7343 * loose cycle time. This isn't too big a deal, since the loss will be
7344 * uniform across all VCPUs (not to mention the scenario is extremely
7345 * unlikely). It is possible that a second hibernate recovery happens
7346 * much faster than a first, causing the observed TSC here to be
7347 * smaller; this would require additional padding adjustment, which is
7348 * why we set last_host_tsc to the local tsc observed here.
7349 *
7350 * N.B. - this code below runs only on platforms with reliable TSC,
7351 * as that is the only way backwards_tsc is set above. Also note
7352 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7353 * have the same delta_cyc adjustment applied if backwards_tsc
7354 * is detected. Note further, this adjustment is only done once,
7355 * as we reset last_host_tsc on all VCPUs to stop this from being
7356 * called multiple times (one for each physical CPU bringup).
7357 *
4a969980 7358 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7359 * will be compensated by the logic in vcpu_load, which sets the TSC to
7360 * catchup mode. This will catchup all VCPUs to real time, but cannot
7361 * guarantee that they stay in perfect synchronization.
7362 */
7363 if (backwards_tsc) {
7364 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7365 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7366 list_for_each_entry(kvm, &vm_list, vm_list) {
7367 kvm_for_each_vcpu(i, vcpu, kvm) {
7368 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7369 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7370 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7371 }
7372
7373 /*
7374 * We have to disable TSC offset matching.. if you were
7375 * booting a VM while issuing an S4 host suspend....
7376 * you may have some problem. Solving this issue is
7377 * left as an exercise to the reader.
7378 */
7379 kvm->arch.last_tsc_nsec = 0;
7380 kvm->arch.last_tsc_write = 0;
7381 }
7382
7383 }
7384 return 0;
e9b11c17
ZX		 7385}
7386
13a34e06 7387void kvm_arch_hardware_disable(void)
e9b11c17 7388{
13a34e06
RK		 7389 kvm_x86_ops->hardware_disable();
7390 drop_user_return_notifiers();
e9b11c17
ZX		 7391}
7392
7393int kvm_arch_hardware_setup(void)
7394{
9e9c3fe4
NA		 7395 int r;
7396
7397 r = kvm_x86_ops->hardware_setup();
7398 if (r != 0)
7399 return r;
7400
35181e86
HZ		 7401 if (kvm_has_tsc_control) {
7402 /*
7403 * Make sure the user can only configure tsc_khz values that
7404 * fit into a signed integer.
7405 * A min value is not calculated needed because it will always
7406 * be 1 on all machines.
7407 */
7408 u64 max = min(0x7fffffffULL,
7409 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7410 kvm_max_guest_tsc_khz = max;
7411
ad721883 7412 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7413 }
ad721883 7414
9e9c3fe4
NA		 7415 kvm_init_msr_list();
7416 return 0;
e9b11c17
ZX		 7417}
7418
7419void kvm_arch_hardware_unsetup(void)
7420{
7421 kvm_x86_ops->hardware_unsetup();
7422}
7423
7424void kvm_arch_check_processor_compat(void *rtn)
7425{
7426 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7427}
7428
7429bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7430{
7431 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7432}
7433EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7434
7435bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7436{
7437 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7438}
7439
3e515705
AK		 7440bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7441{
35754c98 7442 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7443}
7444
54e9818f
GN		 7445struct static_key kvm_no_apic_vcpu __read_mostly;
7446
e9b11c17
ZX		 7447int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7448{
7449 struct page *page;
7450 struct kvm *kvm;
7451 int r;
7452
7453 BUG_ON(vcpu->kvm == NULL);
7454 kvm = vcpu->kvm;
7455
6aef266c 7456 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7457 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7458 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7459 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7460 else
a4535290 7461 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7462
7463 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7464 if (!page) {
7465 r = -ENOMEM;
7466 goto fail;
7467 }
ad312c7c 7468 vcpu->arch.pio_data = page_address(page);
e9b11c17 7469
cc578287 7470 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7471
e9b11c17
ZX		 7472 r = kvm_mmu_create(vcpu);
7473 if (r < 0)
7474 goto fail_free_pio_data;
7475
7476 if (irqchip_in_kernel(kvm)) {
7477 r = kvm_create_lapic(vcpu);
7478 if (r < 0)
7479 goto fail_mmu_destroy;
54e9818f
GN		 7480 } else
7481 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7482
890ca9ae
HY		 7483 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7484 GFP_KERNEL);
7485 if (!vcpu->arch.mce_banks) {
7486 r = -ENOMEM;
443c39bc 7487 goto fail_free_lapic;
890ca9ae
HY		 7488 }
7489 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7490
f1797359
WY		 7491 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7492 r = -ENOMEM;
f5f48ee1 7493 goto fail_free_mce_banks;
f1797359 7494 }
f5f48ee1 7495
0ee6a517 7496 fx_init(vcpu);
66f7b72e 7497
ba904635 7498 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7499 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7500
7501 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7502 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7503
5a4f55cd
EK		 7504 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7505
74545705
RK		 7506 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7507
af585b92 7508 kvm_async_pf_hash_reset(vcpu);
f5132b01 7509 kvm_pmu_init(vcpu);
af585b92 7510
1c1a9ce9
SR		 7511 vcpu->arch.pending_external_vector = -1;
7512
e9b11c17 7513 return 0;
0ee6a517 7514
f5f48ee1
SY		 7515fail_free_mce_banks:
7516 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7517fail_free_lapic:
7518 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7519fail_mmu_destroy:
7520 kvm_mmu_destroy(vcpu);
7521fail_free_pio_data:
ad312c7c 7522 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7523fail:
7524 return r;
7525}
7526
7527void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7528{
f656ce01
MT		 7529 int idx;
7530
f5132b01 7531 kvm_pmu_destroy(vcpu);
36cb93fd 7532 kfree(vcpu->arch.mce_banks);
e9b11c17 7533 kvm_free_lapic(vcpu);
f656ce01 7534 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7535 kvm_mmu_destroy(vcpu);
f656ce01 7536 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7537 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7538 if (!lapic_in_kernel(vcpu))
54e9818f 7539 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7540}
d19a9cd2 7541
e790d9ef
RK		 7542void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7543{
ae97a3b8 7544 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7545}
7546
e08b9637 7547int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7548{
e08b9637
CO		 7549 if (type)
7550 return -EINVAL;
7551
6ef768fa 7552 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7553 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7554 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7555 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7556 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7557
5550af4d
SY		 7558 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7559 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7560 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7561 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7562 &kvm->arch.irq_sources_bitmap);
5550af4d 7563
038f8c11 7564 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7565 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7566 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7567
7568 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7569
7e44e449 7570 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7571 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7572
d89f5eff 7573 return 0;
d19a9cd2
ZX		 7574}
7575
7576static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7577{
9fc77441
MT		 7578 int r;
7579 r = vcpu_load(vcpu);
7580 BUG_ON(r);
d19a9cd2
ZX		 7581 kvm_mmu_unload(vcpu);
7582 vcpu_put(vcpu);
7583}
7584
7585static void kvm_free_vcpus(struct kvm *kvm)
7586{
7587 unsigned int i;
988a2cae 7588 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7589
7590 /*
7591 * Unpin any mmu pages first.
7592 */
af585b92
GN		 7593 kvm_for_each_vcpu(i, vcpu, kvm) {
7594 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7595 kvm_unload_vcpu_mmu(vcpu);
af585b92 7596 }
988a2cae
GN		 7597 kvm_for_each_vcpu(i, vcpu, kvm)
7598 kvm_arch_vcpu_free(vcpu);
7599
7600 mutex_lock(&kvm->lock);
7601 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7602 kvm->vcpus[i] = NULL;
d19a9cd2 7603
988a2cae
GN		 7604 atomic_set(&kvm->online_vcpus, 0);
7605 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7606}
7607
ad8ba2cd
SY		 7608void kvm_arch_sync_events(struct kvm *kvm)
7609{
332967a3 7610 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7611 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7612 kvm_free_all_assigned_devices(kvm);
aea924f6 7613 kvm_free_pit(kvm);
ad8ba2cd
SY		 7614}
7615
1d8007bd 7616int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7617{
7618 int i, r;
25188b99 7619 unsigned long hva;
f0d648bd
PB		 7620 struct kvm_memslots *slots = kvm_memslots(kvm);
7621 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7622
7623 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7624 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7625 return -EINVAL;
9da0e4d5 7626
f0d648bd
PB		 7627 slot = id_to_memslot(slots, id);
7628 if (size) {
7629 if (WARN_ON(slot->npages))
7630 return -EEXIST;
7631
7632 /*
7633 * MAP_SHARED to prevent internal slot pages from being moved
7634 * by fork()/COW.
7635 */
7636 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7637 MAP_SHARED | MAP_ANONYMOUS, 0);
7638 if (IS_ERR((void *)hva))
7639 return PTR_ERR((void *)hva);
7640 } else {
7641 if (!slot->npages)
7642 return 0;
9da0e4d5 7643
f0d648bd
PB		 7644 hva = 0;
7645 }
7646
7647 old = *slot;
9da0e4d5 7648 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7649 struct kvm_userspace_memory_region m;
9da0e4d5 7650
1d8007bd
PB		 7651 m.slot = id | (i << 16);
7652 m.flags = 0;
7653 m.guest_phys_addr = gpa;
f0d648bd 7654 m.userspace_addr = hva;
1d8007bd 7655 m.memory_size = size;
9da0e4d5
PB		 7656 r = __kvm_set_memory_region(kvm, &m);
7657 if (r < 0)
7658 return r;
7659 }
7660
f0d648bd
PB		 7661 if (!size) {
7662 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7663 WARN_ON(r < 0);
7664 }
7665
9da0e4d5
PB		 7666 return 0;
7667}
7668EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7669
1d8007bd 7670int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7671{
7672 int r;
7673
7674 mutex_lock(&kvm->slots_lock);
1d8007bd 7675 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7676 mutex_unlock(&kvm->slots_lock);
7677
7678 return r;
7679}
7680EXPORT_SYMBOL_GPL(x86_set_memory_region);
7681
d19a9cd2
ZX		 7682void kvm_arch_destroy_vm(struct kvm *kvm)
7683{
27469d29
AH		 7684 if (current->mm == kvm->mm) {
7685 /*
7686 * Free memory regions allocated on behalf of userspace,
7687 * unless the the memory map has changed due to process exit
7688 * or fd copying.
7689 */
1d8007bd
PB		 7690 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7691 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7692 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7693 }
6eb55818 7694 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7695 kfree(kvm->arch.vpic);
7696 kfree(kvm->arch.vioapic);
d19a9cd2 7697 kvm_free_vcpus(kvm);
1e08ec4a 7698 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7699}
0de10343 7700
5587027c 7701void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7702 struct kvm_memory_slot *dont)
7703{
7704 int i;
7705
d89cc617
TY		 7706 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7707 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7708 kvfree(free->arch.rmap[i]);
d89cc617 7709 free->arch.rmap[i] = NULL;
77d11309 7710 }
d89cc617
TY		 7711 if (i == 0)
7712 continue;
7713
7714 if (!dont || free->arch.lpage_info[i - 1] !=
7715 dont->arch.lpage_info[i - 1]) {
548ef284 7716 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7717 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7718 }
7719 }
7720}
7721
5587027c
AK		 7722int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7723 unsigned long npages)
db3fe4eb
TY		 7724{
7725 int i;
7726
d89cc617 7727 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7728 unsigned long ugfn;
7729 int lpages;
d89cc617 7730 int level = i + 1;
db3fe4eb
TY		 7731
7732 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7733 slot->base_gfn, level) + 1;
7734
d89cc617
TY		 7735 slot->arch.rmap[i] =
7736 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7737 if (!slot->arch.rmap[i])
77d11309 7738 goto out_free;
d89cc617
TY		 7739 if (i == 0)
7740 continue;
77d11309 7741
d89cc617
TY		 7742 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7743 sizeof(*slot->arch.lpage_info[i - 1]));
7744 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7745 goto out_free;
7746
7747 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7748 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7749 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7750 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7751 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7752 /*
7753 * If the gfn and userspace address are not aligned wrt each
7754 * other, or if explicitly asked to, disable large page
7755 * support for this slot
7756 */
7757 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7758 !kvm_largepages_enabled()) {
7759 unsigned long j;
7760
7761 for (j = 0; j < lpages; ++j)
d89cc617 7762 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7763 }
7764 }
7765
7766 return 0;
7767
7768out_free:
d89cc617 7769 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7770 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7771 slot->arch.rmap[i] = NULL;
7772 if (i == 0)
7773 continue;
7774
548ef284 7775 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7776 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7777 }
7778 return -ENOMEM;
7779}
7780
15f46015 7781void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7782{
e6dff7d1
TY		 7783 /*
7784 * memslots->generation has been incremented.
7785 * mmio generation may have reached its maximum value.
7786 */
54bf36aa 7787 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7788}
7789
f7784b8e
MT		 7790int kvm_arch_prepare_memory_region(struct kvm *kvm,
7791 struct kvm_memory_slot *memslot,
09170a49 7792 const struct kvm_userspace_memory_region *mem,
7b6195a9 7793 enum kvm_mr_change change)
0de10343 7794{
f7784b8e
MT		 7795 return 0;
7796}
7797
88178fd4
KH		 7798static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7799 struct kvm_memory_slot *new)
7800{
7801 /* Still write protect RO slot */
7802 if (new->flags & KVM_MEM_READONLY) {
7803 kvm_mmu_slot_remove_write_access(kvm, new);
7804 return;
7805 }
7806
7807 /*
7808 * Call kvm_x86_ops dirty logging hooks when they are valid.
7809 *
7810 * kvm_x86_ops->slot_disable_log_dirty is called when:
7811 *
7812 * - KVM_MR_CREATE with dirty logging is disabled
7813 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7814 *
7815 * The reason is, in case of PML, we need to set D-bit for any slots
7816 * with dirty logging disabled in order to eliminate unnecessary GPA
7817 * logging in PML buffer (and potential PML buffer full VMEXT). This
7818 * guarantees leaving PML enabled during guest's lifetime won't have
7819 * any additonal overhead from PML when guest is running with dirty
7820 * logging disabled for memory slots.
7821 *
7822 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7823 * to dirty logging mode.
7824 *
7825 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7826 *
7827 * In case of write protect:
7828 *
7829 * Write protect all pages for dirty logging.
7830 *
7831 * All the sptes including the large sptes which point to this
7832 * slot are set to readonly. We can not create any new large
7833 * spte on this slot until the end of the logging.
7834 *
7835 * See the comments in fast_page_fault().
7836 */
7837 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7838 if (kvm_x86_ops->slot_enable_log_dirty)
7839 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7840 else
7841 kvm_mmu_slot_remove_write_access(kvm, new);
7842 } else {
7843 if (kvm_x86_ops->slot_disable_log_dirty)
7844 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7845 }
7846}
7847
f7784b8e 7848void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7849 const struct kvm_userspace_memory_region *mem,
8482644a 7850 const struct kvm_memory_slot *old,
f36f3f28 7851 const struct kvm_memory_slot *new,
8482644a 7852 enum kvm_mr_change change)
f7784b8e 7853{
8482644a 7854 int nr_mmu_pages = 0;
f7784b8e 7855
48c0e4e9
XG		 7856 if (!kvm->arch.n_requested_mmu_pages)
7857 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7858
48c0e4e9 7859 if (nr_mmu_pages)
0de10343 7860 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7861
3ea3b7fa
WL		 7862 /*
7863 * Dirty logging tracks sptes in 4k granularity, meaning that large
7864 * sptes have to be split. If live migration is successful, the guest
7865 * in the source machine will be destroyed and large sptes will be
7866 * created in the destination. However, if the guest continues to run
7867 * in the source machine (for example if live migration fails), small
7868 * sptes will remain around and cause bad performance.
7869 *
7870 * Scan sptes if dirty logging has been stopped, dropping those
7871 * which can be collapsed into a single large-page spte. Later
7872 * page faults will create the large-page sptes.
7873 */
7874 if ((change != KVM_MR_DELETE) &&
7875 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7876 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7877 kvm_mmu_zap_collapsible_sptes(kvm, new);
7878
c972f3b1 7879 /*
88178fd4 7880 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7881 *
88178fd4
KH		 7882 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7883 * been zapped so no dirty logging staff is needed for old slot. For
7884 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7885 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7886 *
7887 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7888 */
88178fd4 7889 if (change != KVM_MR_DELETE)
f36f3f28 7890 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7891}
1d737c8a 7892
2df72e9b 7893void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7894{
6ca18b69 7895 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7896}
7897
2df72e9b
MT		 7898void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7899 struct kvm_memory_slot *slot)
7900{
6ca18b69 7901 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7902}
7903
5d9bc648
PB		 7904static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7905{
7906 if (!list_empty_careful(&vcpu->async_pf.done))
7907 return true;
7908
7909 if (kvm_apic_has_events(vcpu))
7910 return true;
7911
7912 if (vcpu->arch.pv.pv_unhalted)
7913 return true;
7914
7915 if (atomic_read(&vcpu->arch.nmi_queued))
7916 return true;
7917
73917739
PB		 7918 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7919 return true;
7920
5d9bc648
PB		 7921 if (kvm_arch_interrupt_allowed(vcpu) &&
7922 kvm_cpu_has_interrupt(vcpu))
7923 return true;
7924
7925 return false;
7926}
7927
1d737c8a
ZX		 7928int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7929{
b6b8a145
JK		 7930 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7931 kvm_x86_ops->check_nested_events(vcpu, false);
7932
5d9bc648 7933 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 7934}
5736199a 7935
b6d33834 7936int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7937{
b6d33834 7938 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7939}
78646121
GN		 7940
7941int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7942{
7943 return kvm_x86_ops->interrupt_allowed(vcpu);
7944}
229456fc 7945
82b32774 7946unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7947{
82b32774
NA		 7948 if (is_64_bit_mode(vcpu))
7949 return kvm_rip_read(vcpu);
7950 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7951 kvm_rip_read(vcpu));
7952}
7953EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7954
82b32774
NA		 7955bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7956{
7957 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7958}
7959EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7960
94fe45da
JK		 7961unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7962{
7963 unsigned long rflags;
7964
7965 rflags = kvm_x86_ops->get_rflags(vcpu);
7966 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7967 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7968 return rflags;
7969}
7970EXPORT_SYMBOL_GPL(kvm_get_rflags);
7971
6addfc42 7972static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7973{
7974 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7975 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7976 rflags |= X86_EFLAGS_TF;
94fe45da 7977 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7978}
7979
7980void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7981{
7982 __kvm_set_rflags(vcpu, rflags);
3842d135 7983 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7984}
7985EXPORT_SYMBOL_GPL(kvm_set_rflags);
7986
56028d08
GN		 7987void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7988{
7989 int r;
7990
fb67e14f 7991 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7992 work->wakeup_all)
56028d08
GN		 7993 return;
7994
7995 r = kvm_mmu_reload(vcpu);
7996 if (unlikely(r))
7997 return;
7998
fb67e14f
XG		 7999 if (!vcpu->arch.mmu.direct_map &&
8000 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8001 return;
8002
56028d08
GN		 8003 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8004}
8005
af585b92
GN		 8006static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8007{
8008 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8009}
8010
8011static inline u32 kvm_async_pf_next_probe(u32 key)
8012{
8013 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8014}
8015
8016static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8017{
8018 u32 key = kvm_async_pf_hash_fn(gfn);
8019
8020 while (vcpu->arch.apf.gfns[key] != ~0)
8021 key = kvm_async_pf_next_probe(key);
8022
8023 vcpu->arch.apf.gfns[key] = gfn;
8024}
8025
8026static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8027{
8028 int i;
8029 u32 key = kvm_async_pf_hash_fn(gfn);
8030
8031 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8032 (vcpu->arch.apf.gfns[key] != gfn &&
8033 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8034 key = kvm_async_pf_next_probe(key);
8035
8036 return key;
8037}
8038
8039bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8040{
8041 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8042}
8043
8044static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8045{
8046 u32 i, j, k;
8047
8048 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8049 while (true) {
8050 vcpu->arch.apf.gfns[i] = ~0;
8051 do {
8052 j = kvm_async_pf_next_probe(j);
8053 if (vcpu->arch.apf.gfns[j] == ~0)
8054 return;
8055 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8056 /*
8057 * k lies cyclically in ]i,j]
8058 * | i.k.j |
8059 * |....j i.k.| or |.k..j i...|
8060 */
8061 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8062 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8063 i = j;
8064 }
8065}
8066
7c90705b
GN		 8067static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8068{
8069
8070 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8071 sizeof(val));
8072}
8073
af585b92
GN		 8074void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8075 struct kvm_async_pf *work)
8076{
6389ee94
AK		 8077 struct x86_exception fault;
8078
7c90705b 8079 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8080 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8081
8082 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8083 (vcpu->arch.apf.send_user_only &&
8084 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8085 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8086 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8087 fault.vector = PF_VECTOR;
8088 fault.error_code_valid = true;
8089 fault.error_code = 0;
8090 fault.nested_page_fault = false;
8091 fault.address = work->arch.token;
8092 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8093 }
af585b92
GN		 8094}
8095
8096void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8097 struct kvm_async_pf *work)
8098{
6389ee94
AK		 8099 struct x86_exception fault;
8100
7c90705b 8101 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8102 if (work->wakeup_all)
7c90705b
GN		 8103 work->arch.token = ~0; /* broadcast wakeup */
8104 else
8105 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8106
8107 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8108 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8109 fault.vector = PF_VECTOR;
8110 fault.error_code_valid = true;
8111 fault.error_code = 0;
8112 fault.nested_page_fault = false;
8113 fault.address = work->arch.token;
8114 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8115 }
e6d53e3b 8116 vcpu->arch.apf.halted = false;
a4fa1635 8117 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8118}
8119
8120bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8121{
8122 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8123 return true;
8124 else
8125 return !kvm_event_needs_reinjection(vcpu) &&
8126 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8127}
8128
5544eb9b
PB		 8129void kvm_arch_start_assignment(struct kvm *kvm)
8130{
8131 atomic_inc(&kvm->arch.assigned_device_count);
8132}
8133EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8134
8135void kvm_arch_end_assignment(struct kvm *kvm)
8136{
8137 atomic_dec(&kvm->arch.assigned_device_count);
8138}
8139EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8140
8141bool kvm_arch_has_assigned_device(struct kvm *kvm)
8142{
8143 return atomic_read(&kvm->arch.assigned_device_count);
8144}
8145EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8146
e0f0bbc5
AW		 8147void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8148{
8149 atomic_inc(&kvm->arch.noncoherent_dma_count);
8150}
8151EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8152
8153void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8154{
8155 atomic_dec(&kvm->arch.noncoherent_dma_count);
8156}
8157EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8158
8159bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8160{
8161 return atomic_read(&kvm->arch.noncoherent_dma_count);
8162}
8163EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8164
87276880
FW		 8165int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8166 struct irq_bypass_producer *prod)
8167{
8168 struct kvm_kernel_irqfd *irqfd =
8169 container_of(cons, struct kvm_kernel_irqfd, consumer);
8170
8171 if (kvm_x86_ops->update_pi_irte) {
8172 irqfd->producer = prod;
8173 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8174 prod->irq, irqfd->gsi, 1);
8175 }
8176
8177 return -EINVAL;
8178}
8179
8180void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8181 struct irq_bypass_producer *prod)
8182{
8183 int ret;
8184 struct kvm_kernel_irqfd *irqfd =
8185 container_of(cons, struct kvm_kernel_irqfd, consumer);
8186
8187 if (!kvm_x86_ops->update_pi_irte) {
8188 WARN_ON(irqfd->producer != NULL);
8189 return;
8190 }
8191
8192 WARN_ON(irqfd->producer != prod);
8193 irqfd->producer = NULL;
8194
8195 /*
8196 * When producer of consumer is unregistered, we change back to
8197 * remapped mode, so we can re-use the current implementation
8198 * when the irq is masked/disabed or the consumer side (KVM
8199 * int this case doesn't want to receive the interrupts.
8200 */
8201 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8202 if (ret)
8203 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8204 " fails: %d\n", irqfd->consumer.token, ret);
8205}
8206
8207int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8208 uint32_t guest_irq, bool set)
8209{
8210 if (!kvm_x86_ops->update_pi_irte)
8211 return -EINVAL;
8212
8213 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8214}
8215
229456fc 8216EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8217EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8218EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8219EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8220EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8221EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8222EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8223EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8224EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8225EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8226EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8227EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8228EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8229EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8230EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8231EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8232EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux kernel - Deliverables
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