Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
313a3dc7 | 30 | |
18068523 | 31 | #include <linux/clocksource.h> |
4d5c5d0f | 32 | #include <linux/interrupt.h> |
313a3dc7 CO |
33 | #include <linux/kvm.h> |
34 | #include <linux/fs.h> | |
35 | #include <linux/vmalloc.h> | |
5fb76f9b | 36 | #include <linux/module.h> |
0de10343 | 37 | #include <linux/mman.h> |
2bacc55c | 38 | #include <linux/highmem.h> |
19de40a8 | 39 | #include <linux/iommu.h> |
62c476c7 | 40 | #include <linux/intel-iommu.h> |
c8076604 | 41 | #include <linux/cpufreq.h> |
18863bdd | 42 | #include <linux/user-return-notifier.h> |
a983fb23 | 43 | #include <linux/srcu.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
ff9d07a0 | 45 | #include <linux/perf_event.h> |
7bee342a | 46 | #include <linux/uaccess.h> |
af585b92 | 47 | #include <linux/hash.h> |
a1b60c1c | 48 | #include <linux/pci.h> |
aec51dc4 | 49 | #include <trace/events/kvm.h> |
2ed152af | 50 | |
229456fc MT |
51 | #define CREATE_TRACE_POINTS |
52 | #include "trace.h" | |
043405e1 | 53 | |
24f1e32c | 54 | #include <asm/debugreg.h> |
d825ed0a | 55 | #include <asm/msr.h> |
a5f61300 | 56 | #include <asm/desc.h> |
0bed3b56 | 57 | #include <asm/mtrr.h> |
890ca9ae | 58 | #include <asm/mce.h> |
7cf30855 | 59 | #include <asm/i387.h> |
1361b83a | 60 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 61 | #include <asm/xcr.h> |
1d5f066e | 62 | #include <asm/pvclock.h> |
217fc9cf | 63 | #include <asm/div64.h> |
043405e1 | 64 | |
313a3dc7 | 65 | #define MAX_IO_MSRS 256 |
890ca9ae | 66 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 67 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 68 | |
0f65dd70 AK |
69 | #define emul_to_vcpu(ctxt) \ |
70 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
71 | ||
50a37eb4 JR |
72 | /* EFER defaults: |
73 | * - enable syscall per default because its emulated by KVM | |
74 | * - enable LME and LMA per default on 64 bit KVM | |
75 | */ | |
76 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
77 | static |
78 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 79 | #else |
1260edbe | 80 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 81 | #endif |
313a3dc7 | 82 | |
ba1389b7 AK |
83 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
84 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 85 | |
cb142eb7 | 86 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 87 | static void process_nmi(struct kvm_vcpu *vcpu); |
674eea0f | 88 | |
97896d04 | 89 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 90 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 91 | |
476bc001 RR |
92 | static bool ignore_msrs = 0; |
93 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 94 | |
92a1f12d JR |
95 | bool kvm_has_tsc_control; |
96 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
97 | u32 kvm_max_guest_tsc_khz; | |
98 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
99 | ||
cc578287 ZA |
100 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
101 | static u32 tsc_tolerance_ppm = 250; | |
102 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
103 | ||
18863bdd AK |
104 | #define KVM_NR_SHARED_MSRS 16 |
105 | ||
106 | struct kvm_shared_msrs_global { | |
107 | int nr; | |
2bf78fa7 | 108 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
109 | }; |
110 | ||
111 | struct kvm_shared_msrs { | |
112 | struct user_return_notifier urn; | |
113 | bool registered; | |
2bf78fa7 SY |
114 | struct kvm_shared_msr_values { |
115 | u64 host; | |
116 | u64 curr; | |
117 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
118 | }; |
119 | ||
120 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
121 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
122 | ||
417bc304 | 123 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
124 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
125 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
126 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
127 | { "invlpg", VCPU_STAT(invlpg) }, | |
128 | { "exits", VCPU_STAT(exits) }, | |
129 | { "io_exits", VCPU_STAT(io_exits) }, | |
130 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
131 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
132 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 133 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
134 | { "halt_exits", VCPU_STAT(halt_exits) }, |
135 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 136 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
137 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
138 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
139 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
140 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
141 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
142 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
143 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 144 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 145 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
146 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
147 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
148 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
149 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
150 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
151 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 152 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 153 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 154 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 155 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
156 | { NULL } |
157 | }; | |
158 | ||
2acf923e DC |
159 | u64 __read_mostly host_xcr0; |
160 | ||
d6aa1000 AK |
161 | int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
162 | ||
af585b92 GN |
163 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
164 | { | |
165 | int i; | |
166 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
167 | vcpu->arch.apf.gfns[i] = ~0; | |
168 | } | |
169 | ||
18863bdd AK |
170 | static void kvm_on_user_return(struct user_return_notifier *urn) |
171 | { | |
172 | unsigned slot; | |
18863bdd AK |
173 | struct kvm_shared_msrs *locals |
174 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 175 | struct kvm_shared_msr_values *values; |
18863bdd AK |
176 | |
177 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
178 | values = &locals->values[slot]; |
179 | if (values->host != values->curr) { | |
180 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
181 | values->curr = values->host; | |
18863bdd AK |
182 | } |
183 | } | |
184 | locals->registered = false; | |
185 | user_return_notifier_unregister(urn); | |
186 | } | |
187 | ||
2bf78fa7 | 188 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 189 | { |
2bf78fa7 | 190 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
191 | u64 value; |
192 | ||
2bf78fa7 SY |
193 | smsr = &__get_cpu_var(shared_msrs); |
194 | /* only read, and nobody should modify it at this time, | |
195 | * so don't need lock */ | |
196 | if (slot >= shared_msrs_global.nr) { | |
197 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
198 | return; | |
199 | } | |
200 | rdmsrl_safe(msr, &value); | |
201 | smsr->values[slot].host = value; | |
202 | smsr->values[slot].curr = value; | |
203 | } | |
204 | ||
205 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
206 | { | |
18863bdd AK |
207 | if (slot >= shared_msrs_global.nr) |
208 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
209 | shared_msrs_global.msrs[slot] = msr; |
210 | /* we need ensured the shared_msr_global have been updated */ | |
211 | smp_wmb(); | |
18863bdd AK |
212 | } |
213 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
214 | ||
215 | static void kvm_shared_msr_cpu_online(void) | |
216 | { | |
217 | unsigned i; | |
18863bdd AK |
218 | |
219 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 220 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
221 | } |
222 | ||
d5696725 | 223 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
224 | { |
225 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
226 | ||
2bf78fa7 | 227 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 228 | return; |
2bf78fa7 SY |
229 | smsr->values[slot].curr = value; |
230 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
231 | if (!smsr->registered) { |
232 | smsr->urn.on_user_return = kvm_on_user_return; | |
233 | user_return_notifier_register(&smsr->urn); | |
234 | smsr->registered = true; | |
235 | } | |
236 | } | |
237 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
238 | ||
3548bab5 AK |
239 | static void drop_user_return_notifiers(void *ignore) |
240 | { | |
241 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
242 | ||
243 | if (smsr->registered) | |
244 | kvm_on_user_return(&smsr->urn); | |
245 | } | |
246 | ||
6866b83e CO |
247 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
248 | { | |
8a5a87d9 | 249 | return vcpu->arch.apic_base; |
6866b83e CO |
250 | } |
251 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
252 | ||
253 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
254 | { | |
255 | /* TODO: reserve bits check */ | |
8a5a87d9 | 256 | kvm_lapic_set_base(vcpu, data); |
6866b83e CO |
257 | } |
258 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
259 | ||
3fd28fce ED |
260 | #define EXCPT_BENIGN 0 |
261 | #define EXCPT_CONTRIBUTORY 1 | |
262 | #define EXCPT_PF 2 | |
263 | ||
264 | static int exception_class(int vector) | |
265 | { | |
266 | switch (vector) { | |
267 | case PF_VECTOR: | |
268 | return EXCPT_PF; | |
269 | case DE_VECTOR: | |
270 | case TS_VECTOR: | |
271 | case NP_VECTOR: | |
272 | case SS_VECTOR: | |
273 | case GP_VECTOR: | |
274 | return EXCPT_CONTRIBUTORY; | |
275 | default: | |
276 | break; | |
277 | } | |
278 | return EXCPT_BENIGN; | |
279 | } | |
280 | ||
281 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
282 | unsigned nr, bool has_error, u32 error_code, |
283 | bool reinject) | |
3fd28fce ED |
284 | { |
285 | u32 prev_nr; | |
286 | int class1, class2; | |
287 | ||
3842d135 AK |
288 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
289 | ||
3fd28fce ED |
290 | if (!vcpu->arch.exception.pending) { |
291 | queue: | |
292 | vcpu->arch.exception.pending = true; | |
293 | vcpu->arch.exception.has_error_code = has_error; | |
294 | vcpu->arch.exception.nr = nr; | |
295 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 296 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
297 | return; |
298 | } | |
299 | ||
300 | /* to check exception */ | |
301 | prev_nr = vcpu->arch.exception.nr; | |
302 | if (prev_nr == DF_VECTOR) { | |
303 | /* triple fault -> shutdown */ | |
a8eeb04a | 304 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
305 | return; |
306 | } | |
307 | class1 = exception_class(prev_nr); | |
308 | class2 = exception_class(nr); | |
309 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
310 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
311 | /* generate double fault per SDM Table 5-5 */ | |
312 | vcpu->arch.exception.pending = true; | |
313 | vcpu->arch.exception.has_error_code = true; | |
314 | vcpu->arch.exception.nr = DF_VECTOR; | |
315 | vcpu->arch.exception.error_code = 0; | |
316 | } else | |
317 | /* replace previous exception with a new one in a hope | |
318 | that instruction re-execution will regenerate lost | |
319 | exception */ | |
320 | goto queue; | |
321 | } | |
322 | ||
298101da AK |
323 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
324 | { | |
ce7ddec4 | 325 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
326 | } |
327 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
328 | ||
ce7ddec4 JR |
329 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
330 | { | |
331 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
332 | } | |
333 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
334 | ||
db8fcefa | 335 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 336 | { |
db8fcefa AP |
337 | if (err) |
338 | kvm_inject_gp(vcpu, 0); | |
339 | else | |
340 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
341 | } | |
342 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 343 | |
6389ee94 | 344 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
345 | { |
346 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
347 | vcpu->arch.cr2 = fault->address; |
348 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 349 | } |
27d6c865 | 350 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 351 | |
6389ee94 | 352 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 353 | { |
6389ee94 AK |
354 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
355 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 356 | else |
6389ee94 | 357 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
d4f8cf66 JR |
358 | } |
359 | ||
3419ffc8 SY |
360 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
361 | { | |
7460fb4a AK |
362 | atomic_inc(&vcpu->arch.nmi_queued); |
363 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
364 | } |
365 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
366 | ||
298101da AK |
367 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
368 | { | |
ce7ddec4 | 369 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
370 | } |
371 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
372 | ||
ce7ddec4 JR |
373 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
374 | { | |
375 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
376 | } | |
377 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
378 | ||
0a79b009 AK |
379 | /* |
380 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
381 | * a #GP and return false. | |
382 | */ | |
383 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 384 | { |
0a79b009 AK |
385 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
386 | return true; | |
387 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
388 | return false; | |
298101da | 389 | } |
0a79b009 | 390 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 391 | |
ec92fe44 JR |
392 | /* |
393 | * This function will be used to read from the physical memory of the currently | |
394 | * running guest. The difference to kvm_read_guest_page is that this function | |
395 | * can read from guest physical or from the guest's guest physical memory. | |
396 | */ | |
397 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
398 | gfn_t ngfn, void *data, int offset, int len, | |
399 | u32 access) | |
400 | { | |
401 | gfn_t real_gfn; | |
402 | gpa_t ngpa; | |
403 | ||
404 | ngpa = gfn_to_gpa(ngfn); | |
405 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access); | |
406 | if (real_gfn == UNMAPPED_GVA) | |
407 | return -EFAULT; | |
408 | ||
409 | real_gfn = gpa_to_gfn(real_gfn); | |
410 | ||
411 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
412 | } | |
413 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
414 | ||
3d06b8bf JR |
415 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
416 | void *data, int offset, int len, u32 access) | |
417 | { | |
418 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
419 | data, offset, len, access); | |
420 | } | |
421 | ||
a03490ed CO |
422 | /* |
423 | * Load the pae pdptrs. Return true is they are all valid. | |
424 | */ | |
ff03a073 | 425 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
426 | { |
427 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
428 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
429 | int i; | |
430 | int ret; | |
ff03a073 | 431 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 432 | |
ff03a073 JR |
433 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
434 | offset * sizeof(u64), sizeof(pdpte), | |
435 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
436 | if (ret < 0) { |
437 | ret = 0; | |
438 | goto out; | |
439 | } | |
440 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 441 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 442 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
443 | ret = 0; |
444 | goto out; | |
445 | } | |
446 | } | |
447 | ret = 1; | |
448 | ||
ff03a073 | 449 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
450 | __set_bit(VCPU_EXREG_PDPTR, |
451 | (unsigned long *)&vcpu->arch.regs_avail); | |
452 | __set_bit(VCPU_EXREG_PDPTR, | |
453 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 454 | out: |
a03490ed CO |
455 | |
456 | return ret; | |
457 | } | |
cc4b6871 | 458 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 459 | |
d835dfec AK |
460 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
461 | { | |
ff03a073 | 462 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 463 | bool changed = true; |
3d06b8bf JR |
464 | int offset; |
465 | gfn_t gfn; | |
d835dfec AK |
466 | int r; |
467 | ||
468 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
469 | return false; | |
470 | ||
6de4f3ad AK |
471 | if (!test_bit(VCPU_EXREG_PDPTR, |
472 | (unsigned long *)&vcpu->arch.regs_avail)) | |
473 | return true; | |
474 | ||
9f8fe504 AK |
475 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
476 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
477 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
478 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
479 | if (r < 0) |
480 | goto out; | |
ff03a073 | 481 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 482 | out: |
d835dfec AK |
483 | |
484 | return changed; | |
485 | } | |
486 | ||
49a9b07e | 487 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 488 | { |
aad82703 SY |
489 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
490 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
491 | X86_CR0_CD | X86_CR0_NW; | |
492 | ||
f9a48e6a AK |
493 | cr0 |= X86_CR0_ET; |
494 | ||
ab344828 | 495 | #ifdef CONFIG_X86_64 |
0f12244f GN |
496 | if (cr0 & 0xffffffff00000000UL) |
497 | return 1; | |
ab344828 GN |
498 | #endif |
499 | ||
500 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 501 | |
0f12244f GN |
502 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
503 | return 1; | |
a03490ed | 504 | |
0f12244f GN |
505 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
506 | return 1; | |
a03490ed CO |
507 | |
508 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
509 | #ifdef CONFIG_X86_64 | |
f6801dff | 510 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
511 | int cs_db, cs_l; |
512 | ||
0f12244f GN |
513 | if (!is_pae(vcpu)) |
514 | return 1; | |
a03490ed | 515 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
516 | if (cs_l) |
517 | return 1; | |
a03490ed CO |
518 | } else |
519 | #endif | |
ff03a073 | 520 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 521 | kvm_read_cr3(vcpu))) |
0f12244f | 522 | return 1; |
a03490ed CO |
523 | } |
524 | ||
ad756a16 MJ |
525 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
526 | return 1; | |
527 | ||
a03490ed | 528 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 529 | |
d170c419 | 530 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 531 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
532 | kvm_async_pf_hash_reset(vcpu); |
533 | } | |
e5f3f027 | 534 | |
aad82703 SY |
535 | if ((cr0 ^ old_cr0) & update_bits) |
536 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
537 | return 0; |
538 | } | |
2d3ad1f4 | 539 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 540 | |
2d3ad1f4 | 541 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 542 | { |
49a9b07e | 543 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 544 | } |
2d3ad1f4 | 545 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 546 | |
2acf923e DC |
547 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
548 | { | |
549 | u64 xcr0; | |
550 | ||
551 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
552 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
553 | return 1; | |
554 | xcr0 = xcr; | |
555 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
556 | return 1; | |
557 | if (!(xcr0 & XSTATE_FP)) | |
558 | return 1; | |
559 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
560 | return 1; | |
561 | if (xcr0 & ~host_xcr0) | |
562 | return 1; | |
563 | vcpu->arch.xcr0 = xcr0; | |
564 | vcpu->guest_xcr0_loaded = 0; | |
565 | return 0; | |
566 | } | |
567 | ||
568 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
569 | { | |
570 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
571 | kvm_inject_gp(vcpu, 0); | |
572 | return 1; | |
573 | } | |
574 | return 0; | |
575 | } | |
576 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
577 | ||
a83b29c6 | 578 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 579 | { |
fc78f519 | 580 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
c68b734f YW |
581 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | |
582 | X86_CR4_PAE | X86_CR4_SMEP; | |
0f12244f GN |
583 | if (cr4 & CR4_RESERVED_BITS) |
584 | return 1; | |
a03490ed | 585 | |
2acf923e DC |
586 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
587 | return 1; | |
588 | ||
c68b734f YW |
589 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
590 | return 1; | |
591 | ||
74dc2b4f YW |
592 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS)) |
593 | return 1; | |
594 | ||
a03490ed | 595 | if (is_long_mode(vcpu)) { |
0f12244f GN |
596 | if (!(cr4 & X86_CR4_PAE)) |
597 | return 1; | |
a2edf57f AK |
598 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
599 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
600 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
601 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
602 | return 1; |
603 | ||
ad756a16 MJ |
604 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
605 | if (!guest_cpuid_has_pcid(vcpu)) | |
606 | return 1; | |
607 | ||
608 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
609 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
610 | return 1; | |
611 | } | |
612 | ||
5e1746d6 | 613 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 614 | return 1; |
a03490ed | 615 | |
ad756a16 MJ |
616 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
617 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 618 | kvm_mmu_reset_context(vcpu); |
0f12244f | 619 | |
2acf923e | 620 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 621 | kvm_update_cpuid(vcpu); |
2acf923e | 622 | |
0f12244f GN |
623 | return 0; |
624 | } | |
2d3ad1f4 | 625 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 626 | |
2390218b | 627 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 628 | { |
9f8fe504 | 629 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 630 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 631 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 632 | return 0; |
d835dfec AK |
633 | } |
634 | ||
a03490ed | 635 | if (is_long_mode(vcpu)) { |
ad756a16 MJ |
636 | if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) { |
637 | if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS) | |
638 | return 1; | |
639 | } else | |
640 | if (cr3 & CR3_L_MODE_RESERVED_BITS) | |
641 | return 1; | |
a03490ed CO |
642 | } else { |
643 | if (is_pae(vcpu)) { | |
0f12244f GN |
644 | if (cr3 & CR3_PAE_RESERVED_BITS) |
645 | return 1; | |
ff03a073 JR |
646 | if (is_paging(vcpu) && |
647 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
0f12244f | 648 | return 1; |
a03490ed CO |
649 | } |
650 | /* | |
651 | * We don't check reserved bits in nonpae mode, because | |
652 | * this isn't enforced, and VMware depends on this. | |
653 | */ | |
654 | } | |
655 | ||
a03490ed CO |
656 | /* |
657 | * Does the new cr3 value map to physical memory? (Note, we | |
658 | * catch an invalid cr3 even in real-mode, because it would | |
659 | * cause trouble later on when we turn on paging anyway.) | |
660 | * | |
661 | * A real CPU would silently accept an invalid cr3 and would | |
662 | * attempt to use it - with largely undefined (and often hard | |
663 | * to debug) behavior on the guest side. | |
664 | */ | |
665 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
666 | return 1; |
667 | vcpu->arch.cr3 = cr3; | |
aff48baa | 668 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
0f12244f GN |
669 | vcpu->arch.mmu.new_cr3(vcpu); |
670 | return 0; | |
671 | } | |
2d3ad1f4 | 672 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 673 | |
eea1cff9 | 674 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 675 | { |
0f12244f GN |
676 | if (cr8 & CR8_RESERVED_BITS) |
677 | return 1; | |
a03490ed CO |
678 | if (irqchip_in_kernel(vcpu->kvm)) |
679 | kvm_lapic_set_tpr(vcpu, cr8); | |
680 | else | |
ad312c7c | 681 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
682 | return 0; |
683 | } | |
2d3ad1f4 | 684 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 685 | |
2d3ad1f4 | 686 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
687 | { |
688 | if (irqchip_in_kernel(vcpu->kvm)) | |
689 | return kvm_lapic_get_cr8(vcpu); | |
690 | else | |
ad312c7c | 691 | return vcpu->arch.cr8; |
a03490ed | 692 | } |
2d3ad1f4 | 693 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 694 | |
c8639010 JK |
695 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
696 | { | |
697 | unsigned long dr7; | |
698 | ||
699 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
700 | dr7 = vcpu->arch.guest_debug_dr7; | |
701 | else | |
702 | dr7 = vcpu->arch.dr7; | |
703 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
704 | vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK); | |
705 | } | |
706 | ||
338dbc97 | 707 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
708 | { |
709 | switch (dr) { | |
710 | case 0 ... 3: | |
711 | vcpu->arch.db[dr] = val; | |
712 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
713 | vcpu->arch.eff_db[dr] = val; | |
714 | break; | |
715 | case 4: | |
338dbc97 GN |
716 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
717 | return 1; /* #UD */ | |
020df079 GN |
718 | /* fall through */ |
719 | case 6: | |
338dbc97 GN |
720 | if (val & 0xffffffff00000000ULL) |
721 | return -1; /* #GP */ | |
020df079 GN |
722 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
723 | break; | |
724 | case 5: | |
338dbc97 GN |
725 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
726 | return 1; /* #UD */ | |
020df079 GN |
727 | /* fall through */ |
728 | default: /* 7 */ | |
338dbc97 GN |
729 | if (val & 0xffffffff00000000ULL) |
730 | return -1; /* #GP */ | |
020df079 | 731 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 732 | kvm_update_dr7(vcpu); |
020df079 GN |
733 | break; |
734 | } | |
735 | ||
736 | return 0; | |
737 | } | |
338dbc97 GN |
738 | |
739 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
740 | { | |
741 | int res; | |
742 | ||
743 | res = __kvm_set_dr(vcpu, dr, val); | |
744 | if (res > 0) | |
745 | kvm_queue_exception(vcpu, UD_VECTOR); | |
746 | else if (res < 0) | |
747 | kvm_inject_gp(vcpu, 0); | |
748 | ||
749 | return res; | |
750 | } | |
020df079 GN |
751 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
752 | ||
338dbc97 | 753 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
754 | { |
755 | switch (dr) { | |
756 | case 0 ... 3: | |
757 | *val = vcpu->arch.db[dr]; | |
758 | break; | |
759 | case 4: | |
338dbc97 | 760 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 761 | return 1; |
020df079 GN |
762 | /* fall through */ |
763 | case 6: | |
764 | *val = vcpu->arch.dr6; | |
765 | break; | |
766 | case 5: | |
338dbc97 | 767 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 768 | return 1; |
020df079 GN |
769 | /* fall through */ |
770 | default: /* 7 */ | |
771 | *val = vcpu->arch.dr7; | |
772 | break; | |
773 | } | |
774 | ||
775 | return 0; | |
776 | } | |
338dbc97 GN |
777 | |
778 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
779 | { | |
780 | if (_kvm_get_dr(vcpu, dr, val)) { | |
781 | kvm_queue_exception(vcpu, UD_VECTOR); | |
782 | return 1; | |
783 | } | |
784 | return 0; | |
785 | } | |
020df079 GN |
786 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
787 | ||
022cd0e8 AK |
788 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
789 | { | |
790 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
791 | u64 data; | |
792 | int err; | |
793 | ||
794 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
795 | if (err) | |
796 | return err; | |
797 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
798 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
799 | return err; | |
800 | } | |
801 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
802 | ||
043405e1 CO |
803 | /* |
804 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
805 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
806 | * | |
807 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
808 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
809 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 810 | */ |
e3267cbb | 811 | |
439793d4 | 812 | #define KVM_SAVE_MSRS_BEGIN 10 |
043405e1 | 813 | static u32 msrs_to_save[] = { |
e3267cbb | 814 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 815 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 816 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
c9aaa895 | 817 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
ae7a2a3f | 818 | MSR_KVM_PV_EOI_EN, |
043405e1 | 819 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 820 | MSR_STAR, |
043405e1 CO |
821 | #ifdef CONFIG_X86_64 |
822 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
823 | #endif | |
e90aa41e | 824 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
825 | }; |
826 | ||
827 | static unsigned num_msrs_to_save; | |
828 | ||
f1d24831 | 829 | static const u32 emulated_msrs[] = { |
a3e06bbe | 830 | MSR_IA32_TSCDEADLINE, |
043405e1 | 831 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
832 | MSR_IA32_MCG_STATUS, |
833 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
834 | }; |
835 | ||
b69e8cae | 836 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 837 | { |
aad82703 SY |
838 | u64 old_efer = vcpu->arch.efer; |
839 | ||
b69e8cae RJ |
840 | if (efer & efer_reserved_bits) |
841 | return 1; | |
15c4a640 CO |
842 | |
843 | if (is_paging(vcpu) | |
b69e8cae RJ |
844 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) |
845 | return 1; | |
15c4a640 | 846 | |
1b2fd70c AG |
847 | if (efer & EFER_FFXSR) { |
848 | struct kvm_cpuid_entry2 *feat; | |
849 | ||
850 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
851 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
852 | return 1; | |
1b2fd70c AG |
853 | } |
854 | ||
d8017474 AG |
855 | if (efer & EFER_SVME) { |
856 | struct kvm_cpuid_entry2 *feat; | |
857 | ||
858 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
859 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
860 | return 1; | |
d8017474 AG |
861 | } |
862 | ||
15c4a640 | 863 | efer &= ~EFER_LMA; |
f6801dff | 864 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 865 | |
a3d204e2 SY |
866 | kvm_x86_ops->set_efer(vcpu, efer); |
867 | ||
9645bb56 | 868 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; |
b69e8cae | 869 | |
aad82703 SY |
870 | /* Update reserved bits */ |
871 | if ((efer ^ old_efer) & EFER_NX) | |
872 | kvm_mmu_reset_context(vcpu); | |
873 | ||
b69e8cae | 874 | return 0; |
15c4a640 CO |
875 | } |
876 | ||
f2b4b7dd JR |
877 | void kvm_enable_efer_bits(u64 mask) |
878 | { | |
879 | efer_reserved_bits &= ~mask; | |
880 | } | |
881 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
882 | ||
883 | ||
15c4a640 CO |
884 | /* |
885 | * Writes msr value into into the appropriate "register". | |
886 | * Returns 0 on success, non-0 otherwise. | |
887 | * Assumes vcpu_load() was already called. | |
888 | */ | |
889 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
890 | { | |
891 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
892 | } | |
893 | ||
313a3dc7 CO |
894 | /* |
895 | * Adapt set_msr() to msr_io()'s calling convention | |
896 | */ | |
897 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
898 | { | |
899 | return kvm_set_msr(vcpu, index, *data); | |
900 | } | |
901 | ||
18068523 GOC |
902 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
903 | { | |
9ed3c444 AK |
904 | int version; |
905 | int r; | |
50d0a0f9 | 906 | struct pvclock_wall_clock wc; |
923de3cf | 907 | struct timespec boot; |
18068523 GOC |
908 | |
909 | if (!wall_clock) | |
910 | return; | |
911 | ||
9ed3c444 AK |
912 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
913 | if (r) | |
914 | return; | |
915 | ||
916 | if (version & 1) | |
917 | ++version; /* first time write, random junk */ | |
918 | ||
919 | ++version; | |
18068523 | 920 | |
18068523 GOC |
921 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
922 | ||
50d0a0f9 GH |
923 | /* |
924 | * The guest calculates current wall clock time by adding | |
34c238a1 | 925 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
926 | * wall clock specified here. guest system time equals host |
927 | * system time for us, thus we must fill in host boot time here. | |
928 | */ | |
923de3cf | 929 | getboottime(&boot); |
50d0a0f9 | 930 | |
4b648665 BR |
931 | if (kvm->arch.kvmclock_offset) { |
932 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
933 | boot = timespec_sub(boot, ts); | |
934 | } | |
50d0a0f9 GH |
935 | wc.sec = boot.tv_sec; |
936 | wc.nsec = boot.tv_nsec; | |
937 | wc.version = version; | |
18068523 GOC |
938 | |
939 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
940 | ||
941 | version++; | |
942 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
943 | } |
944 | ||
50d0a0f9 GH |
945 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
946 | { | |
947 | uint32_t quotient, remainder; | |
948 | ||
949 | /* Don't try to replace with do_div(), this one calculates | |
950 | * "(dividend << 32) / divisor" */ | |
951 | __asm__ ( "divl %4" | |
952 | : "=a" (quotient), "=d" (remainder) | |
953 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
954 | return quotient; | |
955 | } | |
956 | ||
5f4e3f88 ZA |
957 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
958 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 959 | { |
5f4e3f88 | 960 | uint64_t scaled64; |
50d0a0f9 GH |
961 | int32_t shift = 0; |
962 | uint64_t tps64; | |
963 | uint32_t tps32; | |
964 | ||
5f4e3f88 ZA |
965 | tps64 = base_khz * 1000LL; |
966 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 967 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
968 | tps64 >>= 1; |
969 | shift--; | |
970 | } | |
971 | ||
972 | tps32 = (uint32_t)tps64; | |
50933623 JK |
973 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
974 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
975 | scaled64 >>= 1; |
976 | else | |
977 | tps32 <<= 1; | |
50d0a0f9 GH |
978 | shift++; |
979 | } | |
980 | ||
5f4e3f88 ZA |
981 | *pshift = shift; |
982 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 983 | |
5f4e3f88 ZA |
984 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
985 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
986 | } |
987 | ||
759379dd ZA |
988 | static inline u64 get_kernel_ns(void) |
989 | { | |
990 | struct timespec ts; | |
991 | ||
992 | WARN_ON(preemptible()); | |
993 | ktime_get_ts(&ts); | |
994 | monotonic_to_bootbased(&ts); | |
995 | return timespec_to_ns(&ts); | |
50d0a0f9 GH |
996 | } |
997 | ||
c8076604 | 998 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
c285545f | 999 | unsigned long max_tsc_khz; |
c8076604 | 1000 | |
cc578287 | 1001 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1002 | { |
cc578287 ZA |
1003 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1004 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1005 | } |
1006 | ||
cc578287 | 1007 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1008 | { |
cc578287 ZA |
1009 | u64 v = (u64)khz * (1000000 + ppm); |
1010 | do_div(v, 1000000); | |
1011 | return v; | |
1e993611 JR |
1012 | } |
1013 | ||
cc578287 | 1014 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 1015 | { |
cc578287 ZA |
1016 | u32 thresh_lo, thresh_hi; |
1017 | int use_scaling = 0; | |
217fc9cf | 1018 | |
c285545f ZA |
1019 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1020 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1021 | &vcpu->arch.virtual_tsc_shift, |
1022 | &vcpu->arch.virtual_tsc_mult); | |
1023 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1024 | ||
1025 | /* | |
1026 | * Compute the variation in TSC rate which is acceptable | |
1027 | * within the range of tolerance and decide if the | |
1028 | * rate being applied is within that bounds of the hardware | |
1029 | * rate. If so, no scaling or compensation need be done. | |
1030 | */ | |
1031 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1032 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1033 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1034 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1035 | use_scaling = 1; | |
1036 | } | |
1037 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1038 | } |
1039 | ||
1040 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1041 | { | |
e26101b1 | 1042 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1043 | vcpu->arch.virtual_tsc_mult, |
1044 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1045 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1046 | return tsc; |
1047 | } | |
1048 | ||
99e3e30a ZA |
1049 | void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data) |
1050 | { | |
1051 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1052 | u64 offset, ns, elapsed; |
99e3e30a | 1053 | unsigned long flags; |
02626b6a | 1054 | s64 usdiff; |
99e3e30a | 1055 | |
038f8c11 | 1056 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1057 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1058 | ns = get_kernel_ns(); |
f38e098f | 1059 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 ZA |
1060 | |
1061 | /* n.b - signed multiplication and division required */ | |
02626b6a | 1062 | usdiff = data - kvm->arch.last_tsc_write; |
5d3cb0f6 | 1063 | #ifdef CONFIG_X86_64 |
02626b6a | 1064 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 ZA |
1065 | #else |
1066 | /* do_div() only does unsigned */ | |
1067 | asm("idivl %2; xor %%edx, %%edx" | |
02626b6a MT |
1068 | : "=A"(usdiff) |
1069 | : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz)); | |
5d3cb0f6 | 1070 | #endif |
02626b6a MT |
1071 | do_div(elapsed, 1000); |
1072 | usdiff -= elapsed; | |
1073 | if (usdiff < 0) | |
1074 | usdiff = -usdiff; | |
f38e098f ZA |
1075 | |
1076 | /* | |
5d3cb0f6 ZA |
1077 | * Special case: TSC write with a small delta (1 second) of virtual |
1078 | * cycle time against real time is interpreted as an attempt to | |
1079 | * synchronize the CPU. | |
1080 | * | |
1081 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1082 | * TSC, we add elapsed time in this computation. We could let the | |
1083 | * compensation code attempt to catch up if we fall behind, but | |
1084 | * it's better to try to match offsets from the beginning. | |
1085 | */ | |
02626b6a | 1086 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1087 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1088 | if (!check_tsc_unstable()) { |
e26101b1 | 1089 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1090 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1091 | } else { | |
857e4099 | 1092 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1093 | data += delta; |
1094 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1095 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1096 | } |
e26101b1 ZA |
1097 | } else { |
1098 | /* | |
1099 | * We split periods of matched TSC writes into generations. | |
1100 | * For each generation, we track the original measured | |
1101 | * nanosecond time, offset, and write, so if TSCs are in | |
1102 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1103 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1104 | * |
1105 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1106 | */ | |
1107 | kvm->arch.cur_tsc_generation++; | |
1108 | kvm->arch.cur_tsc_nsec = ns; | |
1109 | kvm->arch.cur_tsc_write = data; | |
1110 | kvm->arch.cur_tsc_offset = offset; | |
1111 | pr_debug("kvm: new tsc generation %u, clock %llu\n", | |
1112 | kvm->arch.cur_tsc_generation, data); | |
f38e098f | 1113 | } |
e26101b1 ZA |
1114 | |
1115 | /* | |
1116 | * We also track th most recent recorded KHZ, write and time to | |
1117 | * allow the matching interval to be extended at each write. | |
1118 | */ | |
f38e098f ZA |
1119 | kvm->arch.last_tsc_nsec = ns; |
1120 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1121 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a ZA |
1122 | |
1123 | /* Reset of TSC must disable overshoot protection below */ | |
1124 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
b183aa58 | 1125 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1126 | |
1127 | /* Keep track of which generation this VCPU has synchronized to */ | |
1128 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1129 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1130 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1131 | ||
1132 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
1133 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
99e3e30a | 1134 | } |
e26101b1 | 1135 | |
99e3e30a ZA |
1136 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1137 | ||
34c238a1 | 1138 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1139 | { |
18068523 GOC |
1140 | unsigned long flags; |
1141 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1142 | void *shared_kaddr; | |
463656c0 | 1143 | unsigned long this_tsc_khz; |
1d5f066e ZA |
1144 | s64 kernel_ns, max_kernel_ns; |
1145 | u64 tsc_timestamp; | |
51d59c6b | 1146 | u8 pvclock_flags; |
18068523 | 1147 | |
18068523 GOC |
1148 | /* Keep irq disabled to prevent changes to the clock */ |
1149 | local_irq_save(flags); | |
d5c1785d | 1150 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v); |
759379dd | 1151 | kernel_ns = get_kernel_ns(); |
cc578287 | 1152 | this_tsc_khz = __get_cpu_var(cpu_tsc_khz); |
8cfdc000 | 1153 | if (unlikely(this_tsc_khz == 0)) { |
c285545f | 1154 | local_irq_restore(flags); |
34c238a1 | 1155 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
8cfdc000 ZA |
1156 | return 1; |
1157 | } | |
18068523 | 1158 | |
c285545f ZA |
1159 | /* |
1160 | * We may have to catch up the TSC to match elapsed wall clock | |
1161 | * time for two reasons, even if kvmclock is used. | |
1162 | * 1) CPU could have been running below the maximum TSC rate | |
1163 | * 2) Broken TSC compensation resets the base at each VCPU | |
1164 | * entry to avoid unknown leaps of TSC even when running | |
1165 | * again on the same CPU. This may cause apparent elapsed | |
1166 | * time to disappear, and the guest to stand still or run | |
1167 | * very slowly. | |
1168 | */ | |
1169 | if (vcpu->tsc_catchup) { | |
1170 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1171 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1172 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1173 | tsc_timestamp = tsc; |
1174 | } | |
50d0a0f9 GH |
1175 | } |
1176 | ||
18068523 GOC |
1177 | local_irq_restore(flags); |
1178 | ||
c285545f ZA |
1179 | if (!vcpu->time_page) |
1180 | return 0; | |
18068523 | 1181 | |
1d5f066e ZA |
1182 | /* |
1183 | * Time as measured by the TSC may go backwards when resetting the base | |
1184 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1185 | * higher than the resolution of the other clock scales. Thus, many | |
1186 | * possible measurments of the TSC correspond to one measurement of any | |
1187 | * other clock, and so a spread of values is possible. This is not a | |
1188 | * problem for the computation of the nanosecond clock; with TSC rates | |
1189 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1190 | * nanosecond value, and any path through this code will inevitably | |
1191 | * take longer than that. However, with the kernel_ns value itself, | |
1192 | * the precision may be much lower, down to HZ granularity. If the | |
1193 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1194 | * range, and the second in the high end of the range, we can get: | |
1195 | * | |
1196 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1197 | * | |
1198 | * As the sampling errors potentially range in the thousands of cycles, | |
1199 | * it is possible such a time value has already been observed by the | |
1200 | * guest. To protect against this, we must compute the system time as | |
1201 | * observed by the guest and ensure the new system time is greater. | |
1202 | */ | |
1203 | max_kernel_ns = 0; | |
b183aa58 | 1204 | if (vcpu->hv_clock.tsc_timestamp) { |
1d5f066e ZA |
1205 | max_kernel_ns = vcpu->last_guest_tsc - |
1206 | vcpu->hv_clock.tsc_timestamp; | |
1207 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1208 | vcpu->hv_clock.tsc_to_system_mul, | |
1209 | vcpu->hv_clock.tsc_shift); | |
1210 | max_kernel_ns += vcpu->last_kernel_ns; | |
1211 | } | |
afbcf7ab | 1212 | |
e48672fa | 1213 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1214 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1215 | &vcpu->hv_clock.tsc_shift, | |
1216 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1217 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1218 | } |
1219 | ||
1d5f066e ZA |
1220 | if (max_kernel_ns > kernel_ns) |
1221 | kernel_ns = max_kernel_ns; | |
1222 | ||
8cfdc000 | 1223 | /* With all the info we got, fill in the values */ |
1d5f066e | 1224 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1225 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
1d5f066e | 1226 | vcpu->last_kernel_ns = kernel_ns; |
28e4639a | 1227 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b MT |
1228 | |
1229 | pvclock_flags = 0; | |
1230 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1231 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1232 | vcpu->pvclock_set_guest_stopped_request = false; | |
1233 | } | |
1234 | ||
1235 | vcpu->hv_clock.flags = pvclock_flags; | |
371bcf64 | 1236 | |
18068523 GOC |
1237 | /* |
1238 | * The interface expects us to write an even number signaling that the | |
1239 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1240 | * state, we just increase by 2 at the end. |
18068523 | 1241 | */ |
50d0a0f9 | 1242 | vcpu->hv_clock.version += 2; |
18068523 | 1243 | |
8fd75e12 | 1244 | shared_kaddr = kmap_atomic(vcpu->time_page); |
18068523 GOC |
1245 | |
1246 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 1247 | sizeof(vcpu->hv_clock)); |
18068523 | 1248 | |
8fd75e12 | 1249 | kunmap_atomic(shared_kaddr); |
18068523 GOC |
1250 | |
1251 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
8cfdc000 | 1252 | return 0; |
c8076604 GH |
1253 | } |
1254 | ||
9ba075a6 AK |
1255 | static bool msr_mtrr_valid(unsigned msr) |
1256 | { | |
1257 | switch (msr) { | |
1258 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1259 | case MSR_MTRRfix64K_00000: | |
1260 | case MSR_MTRRfix16K_80000: | |
1261 | case MSR_MTRRfix16K_A0000: | |
1262 | case MSR_MTRRfix4K_C0000: | |
1263 | case MSR_MTRRfix4K_C8000: | |
1264 | case MSR_MTRRfix4K_D0000: | |
1265 | case MSR_MTRRfix4K_D8000: | |
1266 | case MSR_MTRRfix4K_E0000: | |
1267 | case MSR_MTRRfix4K_E8000: | |
1268 | case MSR_MTRRfix4K_F0000: | |
1269 | case MSR_MTRRfix4K_F8000: | |
1270 | case MSR_MTRRdefType: | |
1271 | case MSR_IA32_CR_PAT: | |
1272 | return true; | |
1273 | case 0x2f8: | |
1274 | return true; | |
1275 | } | |
1276 | return false; | |
1277 | } | |
1278 | ||
d6289b93 MT |
1279 | static bool valid_pat_type(unsigned t) |
1280 | { | |
1281 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1282 | } | |
1283 | ||
1284 | static bool valid_mtrr_type(unsigned t) | |
1285 | { | |
1286 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1287 | } | |
1288 | ||
1289 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1290 | { | |
1291 | int i; | |
1292 | ||
1293 | if (!msr_mtrr_valid(msr)) | |
1294 | return false; | |
1295 | ||
1296 | if (msr == MSR_IA32_CR_PAT) { | |
1297 | for (i = 0; i < 8; i++) | |
1298 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1299 | return false; | |
1300 | return true; | |
1301 | } else if (msr == MSR_MTRRdefType) { | |
1302 | if (data & ~0xcff) | |
1303 | return false; | |
1304 | return valid_mtrr_type(data & 0xff); | |
1305 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1306 | for (i = 0; i < 8 ; i++) | |
1307 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1308 | return false; | |
1309 | return true; | |
1310 | } | |
1311 | ||
1312 | /* variable MTRRs */ | |
1313 | return valid_mtrr_type(data & 0xff); | |
1314 | } | |
1315 | ||
9ba075a6 AK |
1316 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1317 | { | |
0bed3b56 SY |
1318 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1319 | ||
d6289b93 | 1320 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1321 | return 1; |
1322 | ||
0bed3b56 SY |
1323 | if (msr == MSR_MTRRdefType) { |
1324 | vcpu->arch.mtrr_state.def_type = data; | |
1325 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1326 | } else if (msr == MSR_MTRRfix64K_00000) | |
1327 | p[0] = data; | |
1328 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1329 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1330 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1331 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1332 | else if (msr == MSR_IA32_CR_PAT) | |
1333 | vcpu->arch.pat = data; | |
1334 | else { /* Variable MTRRs */ | |
1335 | int idx, is_mtrr_mask; | |
1336 | u64 *pt; | |
1337 | ||
1338 | idx = (msr - 0x200) / 2; | |
1339 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1340 | if (!is_mtrr_mask) | |
1341 | pt = | |
1342 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1343 | else | |
1344 | pt = | |
1345 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1346 | *pt = data; | |
1347 | } | |
1348 | ||
1349 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1350 | return 0; |
1351 | } | |
15c4a640 | 1352 | |
890ca9ae | 1353 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1354 | { |
890ca9ae HY |
1355 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1356 | unsigned bank_num = mcg_cap & 0xff; | |
1357 | ||
15c4a640 | 1358 | switch (msr) { |
15c4a640 | 1359 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1360 | vcpu->arch.mcg_status = data; |
15c4a640 | 1361 | break; |
c7ac679c | 1362 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1363 | if (!(mcg_cap & MCG_CTL_P)) |
1364 | return 1; | |
1365 | if (data != 0 && data != ~(u64)0) | |
1366 | return -1; | |
1367 | vcpu->arch.mcg_ctl = data; | |
1368 | break; | |
1369 | default: | |
1370 | if (msr >= MSR_IA32_MC0_CTL && | |
1371 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1372 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1373 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1374 | * some Linux kernels though clear bit 10 in bank 4 to | |
1375 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1376 | * this to avoid an uncatched #GP in the guest | |
1377 | */ | |
890ca9ae | 1378 | if ((offset & 0x3) == 0 && |
114be429 | 1379 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1380 | return -1; |
1381 | vcpu->arch.mce_banks[offset] = data; | |
1382 | break; | |
1383 | } | |
1384 | return 1; | |
1385 | } | |
1386 | return 0; | |
1387 | } | |
1388 | ||
ffde22ac ES |
1389 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1390 | { | |
1391 | struct kvm *kvm = vcpu->kvm; | |
1392 | int lm = is_long_mode(vcpu); | |
1393 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1394 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1395 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1396 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1397 | u32 page_num = data & ~PAGE_MASK; | |
1398 | u64 page_addr = data & PAGE_MASK; | |
1399 | u8 *page; | |
1400 | int r; | |
1401 | ||
1402 | r = -E2BIG; | |
1403 | if (page_num >= blob_size) | |
1404 | goto out; | |
1405 | r = -ENOMEM; | |
ff5c2c03 SL |
1406 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1407 | if (IS_ERR(page)) { | |
1408 | r = PTR_ERR(page); | |
ffde22ac | 1409 | goto out; |
ff5c2c03 | 1410 | } |
ffde22ac ES |
1411 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) |
1412 | goto out_free; | |
1413 | r = 0; | |
1414 | out_free: | |
1415 | kfree(page); | |
1416 | out: | |
1417 | return r; | |
1418 | } | |
1419 | ||
55cd8e5a GN |
1420 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1421 | { | |
1422 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1423 | } | |
1424 | ||
1425 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1426 | { | |
1427 | bool r = false; | |
1428 | switch (msr) { | |
1429 | case HV_X64_MSR_GUEST_OS_ID: | |
1430 | case HV_X64_MSR_HYPERCALL: | |
1431 | r = true; | |
1432 | break; | |
1433 | } | |
1434 | ||
1435 | return r; | |
1436 | } | |
1437 | ||
1438 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1439 | { | |
1440 | struct kvm *kvm = vcpu->kvm; | |
1441 | ||
1442 | switch (msr) { | |
1443 | case HV_X64_MSR_GUEST_OS_ID: | |
1444 | kvm->arch.hv_guest_os_id = data; | |
1445 | /* setting guest os id to zero disables hypercall page */ | |
1446 | if (!kvm->arch.hv_guest_os_id) | |
1447 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1448 | break; | |
1449 | case HV_X64_MSR_HYPERCALL: { | |
1450 | u64 gfn; | |
1451 | unsigned long addr; | |
1452 | u8 instructions[4]; | |
1453 | ||
1454 | /* if guest os id is not set hypercall should remain disabled */ | |
1455 | if (!kvm->arch.hv_guest_os_id) | |
1456 | break; | |
1457 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1458 | kvm->arch.hv_hypercall = data; | |
1459 | break; | |
1460 | } | |
1461 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1462 | addr = gfn_to_hva(kvm, gfn); | |
1463 | if (kvm_is_error_hva(addr)) | |
1464 | return 1; | |
1465 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1466 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 1467 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
1468 | return 1; |
1469 | kvm->arch.hv_hypercall = data; | |
1470 | break; | |
1471 | } | |
1472 | default: | |
a737f256 CD |
1473 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1474 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
1475 | return 1; |
1476 | } | |
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1481 | { | |
10388a07 GN |
1482 | switch (msr) { |
1483 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1484 | unsigned long addr; | |
55cd8e5a | 1485 | |
10388a07 GN |
1486 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1487 | vcpu->arch.hv_vapic = data; | |
1488 | break; | |
1489 | } | |
1490 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1491 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1492 | if (kvm_is_error_hva(addr)) | |
1493 | return 1; | |
8b0cedff | 1494 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
1495 | return 1; |
1496 | vcpu->arch.hv_vapic = data; | |
1497 | break; | |
1498 | } | |
1499 | case HV_X64_MSR_EOI: | |
1500 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1501 | case HV_X64_MSR_ICR: | |
1502 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1503 | case HV_X64_MSR_TPR: | |
1504 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1505 | default: | |
a737f256 CD |
1506 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1507 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
1508 | return 1; |
1509 | } | |
1510 | ||
1511 | return 0; | |
55cd8e5a GN |
1512 | } |
1513 | ||
344d9588 GN |
1514 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1515 | { | |
1516 | gpa_t gpa = data & ~0x3f; | |
1517 | ||
4a969980 | 1518 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 1519 | if (data & 0x3c) |
344d9588 GN |
1520 | return 1; |
1521 | ||
1522 | vcpu->arch.apf.msr_val = data; | |
1523 | ||
1524 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1525 | kvm_clear_async_pf_completion_queue(vcpu); | |
1526 | kvm_async_pf_hash_reset(vcpu); | |
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa)) | |
1531 | return 1; | |
1532 | ||
6adba527 | 1533 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1534 | kvm_async_pf_wakeup_all(vcpu); |
1535 | return 0; | |
1536 | } | |
1537 | ||
12f9a48f GC |
1538 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
1539 | { | |
1540 | if (vcpu->arch.time_page) { | |
1541 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1542 | vcpu->arch.time_page = NULL; | |
1543 | } | |
1544 | } | |
1545 | ||
c9aaa895 GC |
1546 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
1547 | { | |
1548 | u64 delta; | |
1549 | ||
1550 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1551 | return; | |
1552 | ||
1553 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
1554 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
1555 | vcpu->arch.st.accum_steal = delta; | |
1556 | } | |
1557 | ||
1558 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
1559 | { | |
1560 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1561 | return; | |
1562 | ||
1563 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1564 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
1565 | return; | |
1566 | ||
1567 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
1568 | vcpu->arch.st.steal.version += 2; | |
1569 | vcpu->arch.st.accum_steal = 0; | |
1570 | ||
1571 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1572 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
1573 | } | |
1574 | ||
15c4a640 CO |
1575 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1576 | { | |
5753785f GN |
1577 | bool pr = false; |
1578 | ||
15c4a640 | 1579 | switch (msr) { |
15c4a640 | 1580 | case MSR_EFER: |
b69e8cae | 1581 | return set_efer(vcpu, data); |
8f1589d9 AP |
1582 | case MSR_K7_HWCR: |
1583 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1584 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 1585 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
8f1589d9 | 1586 | if (data != 0) { |
a737f256 CD |
1587 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
1588 | data); | |
8f1589d9 AP |
1589 | return 1; |
1590 | } | |
15c4a640 | 1591 | break; |
f7c6d140 AP |
1592 | case MSR_FAM10H_MMIO_CONF_BASE: |
1593 | if (data != 0) { | |
a737f256 CD |
1594 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
1595 | "0x%llx\n", data); | |
f7c6d140 AP |
1596 | return 1; |
1597 | } | |
15c4a640 | 1598 | break; |
c323c0e5 | 1599 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1600 | break; |
b5e2fec0 AG |
1601 | case MSR_IA32_DEBUGCTLMSR: |
1602 | if (!data) { | |
1603 | /* We support the non-activated case already */ | |
1604 | break; | |
1605 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1606 | /* Values other than LBR and BTF are vendor-specific, | |
1607 | thus reserved and should throw a #GP */ | |
1608 | return 1; | |
1609 | } | |
a737f256 CD |
1610 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
1611 | __func__, data); | |
b5e2fec0 | 1612 | break; |
15c4a640 CO |
1613 | case MSR_IA32_UCODE_REV: |
1614 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1615 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1616 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1617 | break; |
9ba075a6 AK |
1618 | case 0x200 ... 0x2ff: |
1619 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1620 | case MSR_IA32_APICBASE: |
1621 | kvm_set_apic_base(vcpu, data); | |
1622 | break; | |
0105d1a5 GN |
1623 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1624 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
1625 | case MSR_IA32_TSCDEADLINE: |
1626 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1627 | break; | |
15c4a640 | 1628 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1629 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1630 | break; |
11c6bffa | 1631 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1632 | case MSR_KVM_WALL_CLOCK: |
1633 | vcpu->kvm->arch.wall_clock = data; | |
1634 | kvm_write_wall_clock(vcpu->kvm, data); | |
1635 | break; | |
11c6bffa | 1636 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 1637 | case MSR_KVM_SYSTEM_TIME: { |
12f9a48f | 1638 | kvmclock_reset(vcpu); |
18068523 GOC |
1639 | |
1640 | vcpu->arch.time = data; | |
c285545f | 1641 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
18068523 GOC |
1642 | |
1643 | /* we verify if the enable bit is set... */ | |
1644 | if (!(data & 1)) | |
1645 | break; | |
1646 | ||
1647 | /* ...but clean it before doing the actual write */ | |
1648 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1649 | ||
18068523 GOC |
1650 | vcpu->arch.time_page = |
1651 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 | 1652 | |
32cad84f | 1653 | if (is_error_page(vcpu->arch.time_page)) |
18068523 | 1654 | vcpu->arch.time_page = NULL; |
32cad84f | 1655 | |
18068523 GOC |
1656 | break; |
1657 | } | |
344d9588 GN |
1658 | case MSR_KVM_ASYNC_PF_EN: |
1659 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
1660 | return 1; | |
1661 | break; | |
c9aaa895 GC |
1662 | case MSR_KVM_STEAL_TIME: |
1663 | ||
1664 | if (unlikely(!sched_info_on())) | |
1665 | return 1; | |
1666 | ||
1667 | if (data & KVM_STEAL_RESERVED_MASK) | |
1668 | return 1; | |
1669 | ||
1670 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
1671 | data & KVM_STEAL_VALID_BITS)) | |
1672 | return 1; | |
1673 | ||
1674 | vcpu->arch.st.msr_val = data; | |
1675 | ||
1676 | if (!(data & KVM_MSR_ENABLED)) | |
1677 | break; | |
1678 | ||
1679 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
1680 | ||
1681 | preempt_disable(); | |
1682 | accumulate_steal_time(vcpu); | |
1683 | preempt_enable(); | |
1684 | ||
1685 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
1686 | ||
1687 | break; | |
ae7a2a3f MT |
1688 | case MSR_KVM_PV_EOI_EN: |
1689 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
1690 | return 1; | |
1691 | break; | |
c9aaa895 | 1692 | |
890ca9ae HY |
1693 | case MSR_IA32_MCG_CTL: |
1694 | case MSR_IA32_MCG_STATUS: | |
1695 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1696 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1697 | |
1698 | /* Performance counters are not protected by a CPUID bit, | |
1699 | * so we should check all of them in the generic path for the sake of | |
1700 | * cross vendor migration. | |
1701 | * Writing a zero into the event select MSRs disables them, | |
1702 | * which we perfectly emulate ;-). Any other value should be at least | |
1703 | * reported, some guests depend on them. | |
1704 | */ | |
71db6023 AP |
1705 | case MSR_K7_EVNTSEL0: |
1706 | case MSR_K7_EVNTSEL1: | |
1707 | case MSR_K7_EVNTSEL2: | |
1708 | case MSR_K7_EVNTSEL3: | |
1709 | if (data != 0) | |
a737f256 CD |
1710 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
1711 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
1712 | break; |
1713 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1714 | * so we ignore writes to make it happy. | |
1715 | */ | |
71db6023 AP |
1716 | case MSR_K7_PERFCTR0: |
1717 | case MSR_K7_PERFCTR1: | |
1718 | case MSR_K7_PERFCTR2: | |
1719 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
1720 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
1721 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 1722 | break; |
5753785f GN |
1723 | case MSR_P6_PERFCTR0: |
1724 | case MSR_P6_PERFCTR1: | |
1725 | pr = true; | |
1726 | case MSR_P6_EVNTSEL0: | |
1727 | case MSR_P6_EVNTSEL1: | |
1728 | if (kvm_pmu_msr(vcpu, msr)) | |
1729 | return kvm_pmu_set_msr(vcpu, msr, data); | |
1730 | ||
1731 | if (pr || data != 0) | |
a737f256 CD |
1732 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
1733 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 1734 | break; |
84e0cefa JS |
1735 | case MSR_K7_CLK_CTL: |
1736 | /* | |
1737 | * Ignore all writes to this no longer documented MSR. | |
1738 | * Writes are only relevant for old K7 processors, | |
1739 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 1740 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
1741 | * affected processor models on the command line, hence |
1742 | * the need to ignore the workaround. | |
1743 | */ | |
1744 | break; | |
55cd8e5a GN |
1745 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1746 | if (kvm_hv_msr_partition_wide(msr)) { | |
1747 | int r; | |
1748 | mutex_lock(&vcpu->kvm->lock); | |
1749 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1750 | mutex_unlock(&vcpu->kvm->lock); | |
1751 | return r; | |
1752 | } else | |
1753 | return set_msr_hyperv(vcpu, msr, data); | |
1754 | break; | |
91c9c3ed | 1755 | case MSR_IA32_BBL_CR_CTL3: |
1756 | /* Drop writes to this legacy MSR -- see rdmsr | |
1757 | * counterpart for further detail. | |
1758 | */ | |
a737f256 | 1759 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 1760 | break; |
2b036c6b BO |
1761 | case MSR_AMD64_OSVW_ID_LENGTH: |
1762 | if (!guest_cpuid_has_osvw(vcpu)) | |
1763 | return 1; | |
1764 | vcpu->arch.osvw.length = data; | |
1765 | break; | |
1766 | case MSR_AMD64_OSVW_STATUS: | |
1767 | if (!guest_cpuid_has_osvw(vcpu)) | |
1768 | return 1; | |
1769 | vcpu->arch.osvw.status = data; | |
1770 | break; | |
15c4a640 | 1771 | default: |
ffde22ac ES |
1772 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1773 | return xen_hvm_config(vcpu, data); | |
f5132b01 GN |
1774 | if (kvm_pmu_msr(vcpu, msr)) |
1775 | return kvm_pmu_set_msr(vcpu, msr, data); | |
ed85c068 | 1776 | if (!ignore_msrs) { |
a737f256 CD |
1777 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
1778 | msr, data); | |
ed85c068 AP |
1779 | return 1; |
1780 | } else { | |
a737f256 CD |
1781 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
1782 | msr, data); | |
ed85c068 AP |
1783 | break; |
1784 | } | |
15c4a640 CO |
1785 | } |
1786 | return 0; | |
1787 | } | |
1788 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1789 | ||
1790 | ||
1791 | /* | |
1792 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1793 | * Returns 0 on success, non-0 otherwise. | |
1794 | * Assumes vcpu_load() was already called. | |
1795 | */ | |
1796 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1797 | { | |
1798 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1799 | } | |
1800 | ||
9ba075a6 AK |
1801 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1802 | { | |
0bed3b56 SY |
1803 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1804 | ||
9ba075a6 AK |
1805 | if (!msr_mtrr_valid(msr)) |
1806 | return 1; | |
1807 | ||
0bed3b56 SY |
1808 | if (msr == MSR_MTRRdefType) |
1809 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1810 | (vcpu->arch.mtrr_state.enabled << 10); | |
1811 | else if (msr == MSR_MTRRfix64K_00000) | |
1812 | *pdata = p[0]; | |
1813 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1814 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1815 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1816 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1817 | else if (msr == MSR_IA32_CR_PAT) | |
1818 | *pdata = vcpu->arch.pat; | |
1819 | else { /* Variable MTRRs */ | |
1820 | int idx, is_mtrr_mask; | |
1821 | u64 *pt; | |
1822 | ||
1823 | idx = (msr - 0x200) / 2; | |
1824 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1825 | if (!is_mtrr_mask) | |
1826 | pt = | |
1827 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1828 | else | |
1829 | pt = | |
1830 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1831 | *pdata = *pt; | |
1832 | } | |
1833 | ||
9ba075a6 AK |
1834 | return 0; |
1835 | } | |
1836 | ||
890ca9ae | 1837 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1838 | { |
1839 | u64 data; | |
890ca9ae HY |
1840 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1841 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1842 | |
1843 | switch (msr) { | |
15c4a640 CO |
1844 | case MSR_IA32_P5_MC_ADDR: |
1845 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1846 | data = 0; |
1847 | break; | |
15c4a640 | 1848 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1849 | data = vcpu->arch.mcg_cap; |
1850 | break; | |
c7ac679c | 1851 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1852 | if (!(mcg_cap & MCG_CTL_P)) |
1853 | return 1; | |
1854 | data = vcpu->arch.mcg_ctl; | |
1855 | break; | |
1856 | case MSR_IA32_MCG_STATUS: | |
1857 | data = vcpu->arch.mcg_status; | |
1858 | break; | |
1859 | default: | |
1860 | if (msr >= MSR_IA32_MC0_CTL && | |
1861 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1862 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1863 | data = vcpu->arch.mce_banks[offset]; | |
1864 | break; | |
1865 | } | |
1866 | return 1; | |
1867 | } | |
1868 | *pdata = data; | |
1869 | return 0; | |
1870 | } | |
1871 | ||
55cd8e5a GN |
1872 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1873 | { | |
1874 | u64 data = 0; | |
1875 | struct kvm *kvm = vcpu->kvm; | |
1876 | ||
1877 | switch (msr) { | |
1878 | case HV_X64_MSR_GUEST_OS_ID: | |
1879 | data = kvm->arch.hv_guest_os_id; | |
1880 | break; | |
1881 | case HV_X64_MSR_HYPERCALL: | |
1882 | data = kvm->arch.hv_hypercall; | |
1883 | break; | |
1884 | default: | |
a737f256 | 1885 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
1886 | return 1; |
1887 | } | |
1888 | ||
1889 | *pdata = data; | |
1890 | return 0; | |
1891 | } | |
1892 | ||
1893 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1894 | { | |
1895 | u64 data = 0; | |
1896 | ||
1897 | switch (msr) { | |
1898 | case HV_X64_MSR_VP_INDEX: { | |
1899 | int r; | |
1900 | struct kvm_vcpu *v; | |
1901 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1902 | if (v == vcpu) | |
1903 | data = r; | |
1904 | break; | |
1905 | } | |
10388a07 GN |
1906 | case HV_X64_MSR_EOI: |
1907 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1908 | case HV_X64_MSR_ICR: | |
1909 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1910 | case HV_X64_MSR_TPR: | |
1911 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 1912 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
1913 | data = vcpu->arch.hv_vapic; |
1914 | break; | |
55cd8e5a | 1915 | default: |
a737f256 | 1916 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
1917 | return 1; |
1918 | } | |
1919 | *pdata = data; | |
1920 | return 0; | |
1921 | } | |
1922 | ||
890ca9ae HY |
1923 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1924 | { | |
1925 | u64 data; | |
1926 | ||
1927 | switch (msr) { | |
890ca9ae | 1928 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1929 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1930 | case MSR_IA32_DEBUGCTLMSR: |
1931 | case MSR_IA32_LASTBRANCHFROMIP: | |
1932 | case MSR_IA32_LASTBRANCHTOIP: | |
1933 | case MSR_IA32_LASTINTFROMIP: | |
1934 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1935 | case MSR_K8_SYSCFG: |
1936 | case MSR_K7_HWCR: | |
61a6bd67 | 1937 | case MSR_VM_HSAVE_PA: |
9e699624 | 1938 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1939 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1940 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1941 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1942 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1943 | data = 0; |
1944 | break; | |
5753785f GN |
1945 | case MSR_P6_PERFCTR0: |
1946 | case MSR_P6_PERFCTR1: | |
1947 | case MSR_P6_EVNTSEL0: | |
1948 | case MSR_P6_EVNTSEL1: | |
1949 | if (kvm_pmu_msr(vcpu, msr)) | |
1950 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
1951 | data = 0; | |
1952 | break; | |
742bc670 MT |
1953 | case MSR_IA32_UCODE_REV: |
1954 | data = 0x100000000ULL; | |
1955 | break; | |
9ba075a6 AK |
1956 | case MSR_MTRRcap: |
1957 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1958 | break; | |
1959 | case 0x200 ... 0x2ff: | |
1960 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1961 | case 0xcd: /* fsb frequency */ |
1962 | data = 3; | |
1963 | break; | |
7b914098 JS |
1964 | /* |
1965 | * MSR_EBC_FREQUENCY_ID | |
1966 | * Conservative value valid for even the basic CPU models. | |
1967 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
1968 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
1969 | * and 266MHz for model 3, or 4. Set Core Clock | |
1970 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
1971 | * 31:24) even though these are only valid for CPU | |
1972 | * models > 2, however guests may end up dividing or | |
1973 | * multiplying by zero otherwise. | |
1974 | */ | |
1975 | case MSR_EBC_FREQUENCY_ID: | |
1976 | data = 1 << 24; | |
1977 | break; | |
15c4a640 CO |
1978 | case MSR_IA32_APICBASE: |
1979 | data = kvm_get_apic_base(vcpu); | |
1980 | break; | |
0105d1a5 GN |
1981 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1982 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1983 | break; | |
a3e06bbe LJ |
1984 | case MSR_IA32_TSCDEADLINE: |
1985 | data = kvm_get_lapic_tscdeadline_msr(vcpu); | |
1986 | break; | |
15c4a640 | 1987 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1988 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1989 | break; |
847f0ad8 AG |
1990 | case MSR_IA32_PERF_STATUS: |
1991 | /* TSC increment by tick */ | |
1992 | data = 1000ULL; | |
1993 | /* CPU multiplier */ | |
1994 | data |= (((uint64_t)4ULL) << 40); | |
1995 | break; | |
15c4a640 | 1996 | case MSR_EFER: |
f6801dff | 1997 | data = vcpu->arch.efer; |
15c4a640 | 1998 | break; |
18068523 | 1999 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2000 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2001 | data = vcpu->kvm->arch.wall_clock; |
2002 | break; | |
2003 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2004 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
2005 | data = vcpu->arch.time; |
2006 | break; | |
344d9588 GN |
2007 | case MSR_KVM_ASYNC_PF_EN: |
2008 | data = vcpu->arch.apf.msr_val; | |
2009 | break; | |
c9aaa895 GC |
2010 | case MSR_KVM_STEAL_TIME: |
2011 | data = vcpu->arch.st.msr_val; | |
2012 | break; | |
1d92128f MT |
2013 | case MSR_KVM_PV_EOI_EN: |
2014 | data = vcpu->arch.pv_eoi.msr_val; | |
2015 | break; | |
890ca9ae HY |
2016 | case MSR_IA32_P5_MC_ADDR: |
2017 | case MSR_IA32_P5_MC_TYPE: | |
2018 | case MSR_IA32_MCG_CAP: | |
2019 | case MSR_IA32_MCG_CTL: | |
2020 | case MSR_IA32_MCG_STATUS: | |
2021 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
2022 | return get_msr_mce(vcpu, msr, pdata); | |
84e0cefa JS |
2023 | case MSR_K7_CLK_CTL: |
2024 | /* | |
2025 | * Provide expected ramp-up count for K7. All other | |
2026 | * are set to zero, indicating minimum divisors for | |
2027 | * every field. | |
2028 | * | |
2029 | * This prevents guest kernels on AMD host with CPU | |
2030 | * type 6, model 8 and higher from exploding due to | |
2031 | * the rdmsr failing. | |
2032 | */ | |
2033 | data = 0x20000000; | |
2034 | break; | |
55cd8e5a GN |
2035 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2036 | if (kvm_hv_msr_partition_wide(msr)) { | |
2037 | int r; | |
2038 | mutex_lock(&vcpu->kvm->lock); | |
2039 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
2040 | mutex_unlock(&vcpu->kvm->lock); | |
2041 | return r; | |
2042 | } else | |
2043 | return get_msr_hyperv(vcpu, msr, pdata); | |
2044 | break; | |
91c9c3ed | 2045 | case MSR_IA32_BBL_CR_CTL3: |
2046 | /* This legacy MSR exists but isn't fully documented in current | |
2047 | * silicon. It is however accessed by winxp in very narrow | |
2048 | * scenarios where it sets bit #19, itself documented as | |
2049 | * a "reserved" bit. Best effort attempt to source coherent | |
2050 | * read data here should the balance of the register be | |
2051 | * interpreted by the guest: | |
2052 | * | |
2053 | * L2 cache control register 3: 64GB range, 256KB size, | |
2054 | * enabled, latency 0x1, configured | |
2055 | */ | |
2056 | data = 0xbe702111; | |
2057 | break; | |
2b036c6b BO |
2058 | case MSR_AMD64_OSVW_ID_LENGTH: |
2059 | if (!guest_cpuid_has_osvw(vcpu)) | |
2060 | return 1; | |
2061 | data = vcpu->arch.osvw.length; | |
2062 | break; | |
2063 | case MSR_AMD64_OSVW_STATUS: | |
2064 | if (!guest_cpuid_has_osvw(vcpu)) | |
2065 | return 1; | |
2066 | data = vcpu->arch.osvw.status; | |
2067 | break; | |
15c4a640 | 2068 | default: |
f5132b01 GN |
2069 | if (kvm_pmu_msr(vcpu, msr)) |
2070 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
ed85c068 | 2071 | if (!ignore_msrs) { |
a737f256 | 2072 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2073 | return 1; |
2074 | } else { | |
a737f256 | 2075 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2076 | data = 0; |
2077 | } | |
2078 | break; | |
15c4a640 CO |
2079 | } |
2080 | *pdata = data; | |
2081 | return 0; | |
2082 | } | |
2083 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2084 | ||
313a3dc7 CO |
2085 | /* |
2086 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2087 | * | |
2088 | * @return number of msrs set successfully. | |
2089 | */ | |
2090 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2091 | struct kvm_msr_entry *entries, | |
2092 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2093 | unsigned index, u64 *data)) | |
2094 | { | |
f656ce01 | 2095 | int i, idx; |
313a3dc7 | 2096 | |
f656ce01 | 2097 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2098 | for (i = 0; i < msrs->nmsrs; ++i) |
2099 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2100 | break; | |
f656ce01 | 2101 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2102 | |
313a3dc7 CO |
2103 | return i; |
2104 | } | |
2105 | ||
2106 | /* | |
2107 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2108 | * | |
2109 | * @return number of msrs set successfully. | |
2110 | */ | |
2111 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2112 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2113 | unsigned index, u64 *data), | |
2114 | int writeback) | |
2115 | { | |
2116 | struct kvm_msrs msrs; | |
2117 | struct kvm_msr_entry *entries; | |
2118 | int r, n; | |
2119 | unsigned size; | |
2120 | ||
2121 | r = -EFAULT; | |
2122 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2123 | goto out; | |
2124 | ||
2125 | r = -E2BIG; | |
2126 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2127 | goto out; | |
2128 | ||
313a3dc7 | 2129 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2130 | entries = memdup_user(user_msrs->entries, size); |
2131 | if (IS_ERR(entries)) { | |
2132 | r = PTR_ERR(entries); | |
313a3dc7 | 2133 | goto out; |
ff5c2c03 | 2134 | } |
313a3dc7 CO |
2135 | |
2136 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2137 | if (r < 0) | |
2138 | goto out_free; | |
2139 | ||
2140 | r = -EFAULT; | |
2141 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2142 | goto out_free; | |
2143 | ||
2144 | r = n; | |
2145 | ||
2146 | out_free: | |
7a73c028 | 2147 | kfree(entries); |
313a3dc7 CO |
2148 | out: |
2149 | return r; | |
2150 | } | |
2151 | ||
018d00d2 ZX |
2152 | int kvm_dev_ioctl_check_extension(long ext) |
2153 | { | |
2154 | int r; | |
2155 | ||
2156 | switch (ext) { | |
2157 | case KVM_CAP_IRQCHIP: | |
2158 | case KVM_CAP_HLT: | |
2159 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2160 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2161 | case KVM_CAP_EXT_CPUID: |
c8076604 | 2162 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2163 | case KVM_CAP_PIT: |
a28e4f5a | 2164 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2165 | case KVM_CAP_MP_STATE: |
ed848624 | 2166 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2167 | case KVM_CAP_USER_NMI: |
52d939a0 | 2168 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2169 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 2170 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 2171 | case KVM_CAP_IRQFD: |
d34e6b17 | 2172 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 2173 | case KVM_CAP_PIT2: |
e9f42757 | 2174 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2175 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2176 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2177 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2178 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2179 | case KVM_CAP_HYPERV: |
10388a07 | 2180 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2181 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2182 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2183 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2184 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2185 | case KVM_CAP_XSAVE: |
344d9588 | 2186 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2187 | case KVM_CAP_GET_TSC_KHZ: |
07700a94 | 2188 | case KVM_CAP_PCI_2_3: |
1c0b28c2 | 2189 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2190 | case KVM_CAP_READONLY_MEM: |
7a84428a | 2191 | case KVM_CAP_IRQFD_RESAMPLE: |
018d00d2 ZX |
2192 | r = 1; |
2193 | break; | |
542472b5 LV |
2194 | case KVM_CAP_COALESCED_MMIO: |
2195 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2196 | break; | |
774ead3a AK |
2197 | case KVM_CAP_VAPIC: |
2198 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2199 | break; | |
f725230a | 2200 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2201 | r = KVM_SOFT_MAX_VCPUS; |
2202 | break; | |
2203 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2204 | r = KVM_MAX_VCPUS; |
2205 | break; | |
a988b910 AK |
2206 | case KVM_CAP_NR_MEMSLOTS: |
2207 | r = KVM_MEMORY_SLOTS; | |
2208 | break; | |
a68a6a72 MT |
2209 | case KVM_CAP_PV_MMU: /* obsolete */ |
2210 | r = 0; | |
2f333bcb | 2211 | break; |
62c476c7 | 2212 | case KVM_CAP_IOMMU: |
a1b60c1c | 2213 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2214 | break; |
890ca9ae HY |
2215 | case KVM_CAP_MCE: |
2216 | r = KVM_MAX_MCE_BANKS; | |
2217 | break; | |
2d5b5a66 SY |
2218 | case KVM_CAP_XCRS: |
2219 | r = cpu_has_xsave; | |
2220 | break; | |
92a1f12d JR |
2221 | case KVM_CAP_TSC_CONTROL: |
2222 | r = kvm_has_tsc_control; | |
2223 | break; | |
4d25a066 JK |
2224 | case KVM_CAP_TSC_DEADLINE_TIMER: |
2225 | r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER); | |
2226 | break; | |
018d00d2 ZX |
2227 | default: |
2228 | r = 0; | |
2229 | break; | |
2230 | } | |
2231 | return r; | |
2232 | ||
2233 | } | |
2234 | ||
043405e1 CO |
2235 | long kvm_arch_dev_ioctl(struct file *filp, |
2236 | unsigned int ioctl, unsigned long arg) | |
2237 | { | |
2238 | void __user *argp = (void __user *)arg; | |
2239 | long r; | |
2240 | ||
2241 | switch (ioctl) { | |
2242 | case KVM_GET_MSR_INDEX_LIST: { | |
2243 | struct kvm_msr_list __user *user_msr_list = argp; | |
2244 | struct kvm_msr_list msr_list; | |
2245 | unsigned n; | |
2246 | ||
2247 | r = -EFAULT; | |
2248 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2249 | goto out; | |
2250 | n = msr_list.nmsrs; | |
2251 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2252 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2253 | goto out; | |
2254 | r = -E2BIG; | |
e125e7b6 | 2255 | if (n < msr_list.nmsrs) |
043405e1 CO |
2256 | goto out; |
2257 | r = -EFAULT; | |
2258 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2259 | num_msrs_to_save * sizeof(u32))) | |
2260 | goto out; | |
e125e7b6 | 2261 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2262 | &emulated_msrs, |
2263 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2264 | goto out; | |
2265 | r = 0; | |
2266 | break; | |
2267 | } | |
674eea0f AK |
2268 | case KVM_GET_SUPPORTED_CPUID: { |
2269 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2270 | struct kvm_cpuid2 cpuid; | |
2271 | ||
2272 | r = -EFAULT; | |
2273 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2274 | goto out; | |
2275 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 2276 | cpuid_arg->entries); |
674eea0f AK |
2277 | if (r) |
2278 | goto out; | |
2279 | ||
2280 | r = -EFAULT; | |
2281 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2282 | goto out; | |
2283 | r = 0; | |
2284 | break; | |
2285 | } | |
890ca9ae HY |
2286 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2287 | u64 mce_cap; | |
2288 | ||
2289 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2290 | r = -EFAULT; | |
2291 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2292 | goto out; | |
2293 | r = 0; | |
2294 | break; | |
2295 | } | |
043405e1 CO |
2296 | default: |
2297 | r = -EINVAL; | |
2298 | } | |
2299 | out: | |
2300 | return r; | |
2301 | } | |
2302 | ||
f5f48ee1 SY |
2303 | static void wbinvd_ipi(void *garbage) |
2304 | { | |
2305 | wbinvd(); | |
2306 | } | |
2307 | ||
2308 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2309 | { | |
2310 | return vcpu->kvm->arch.iommu_domain && | |
2311 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
2312 | } | |
2313 | ||
313a3dc7 CO |
2314 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2315 | { | |
f5f48ee1 SY |
2316 | /* Address WBINVD may be executed by guest */ |
2317 | if (need_emulate_wbinvd(vcpu)) { | |
2318 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2319 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2320 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2321 | smp_call_function_single(vcpu->cpu, | |
2322 | wbinvd_ipi, NULL, 1); | |
2323 | } | |
2324 | ||
313a3dc7 | 2325 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2326 | |
0dd6a6ed ZA |
2327 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2328 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2329 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2330 | vcpu->arch.tsc_offset_adjustment = 0; | |
2331 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
2332 | } | |
8f6055cb | 2333 | |
48434c20 | 2334 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
2335 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
2336 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
2337 | if (tsc_delta < 0) |
2338 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2339 | if (check_tsc_unstable()) { |
b183aa58 ZA |
2340 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
2341 | vcpu->arch.last_guest_tsc); | |
2342 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2343 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2344 | } |
1aa8ceef | 2345 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2346 | if (vcpu->cpu != cpu) |
2347 | kvm_migrate_timers(vcpu); | |
e48672fa | 2348 | vcpu->cpu = cpu; |
6b7d7e76 | 2349 | } |
c9aaa895 GC |
2350 | |
2351 | accumulate_steal_time(vcpu); | |
2352 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
2353 | } |
2354 | ||
2355 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2356 | { | |
02daab21 | 2357 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2358 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 2359 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2360 | } |
2361 | ||
313a3dc7 CO |
2362 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2363 | struct kvm_lapic_state *s) | |
2364 | { | |
ad312c7c | 2365 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2366 | |
2367 | return 0; | |
2368 | } | |
2369 | ||
2370 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2371 | struct kvm_lapic_state *s) | |
2372 | { | |
64eb0620 | 2373 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2374 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2375 | |
2376 | return 0; | |
2377 | } | |
2378 | ||
f77bc6a4 ZX |
2379 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2380 | struct kvm_interrupt *irq) | |
2381 | { | |
a50abc3b | 2382 | if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 ZX |
2383 | return -EINVAL; |
2384 | if (irqchip_in_kernel(vcpu->kvm)) | |
2385 | return -ENXIO; | |
f77bc6a4 | 2386 | |
66fd3f7f | 2387 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2388 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2389 | |
f77bc6a4 ZX |
2390 | return 0; |
2391 | } | |
2392 | ||
c4abb7c9 JK |
2393 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2394 | { | |
c4abb7c9 | 2395 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2396 | |
2397 | return 0; | |
2398 | } | |
2399 | ||
b209749f AK |
2400 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2401 | struct kvm_tpr_access_ctl *tac) | |
2402 | { | |
2403 | if (tac->flags) | |
2404 | return -EINVAL; | |
2405 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2406 | return 0; | |
2407 | } | |
2408 | ||
890ca9ae HY |
2409 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2410 | u64 mcg_cap) | |
2411 | { | |
2412 | int r; | |
2413 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2414 | ||
2415 | r = -EINVAL; | |
a9e38c3e | 2416 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2417 | goto out; |
2418 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2419 | goto out; | |
2420 | r = 0; | |
2421 | vcpu->arch.mcg_cap = mcg_cap; | |
2422 | /* Init IA32_MCG_CTL to all 1s */ | |
2423 | if (mcg_cap & MCG_CTL_P) | |
2424 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2425 | /* Init IA32_MCi_CTL to all 1s */ | |
2426 | for (bank = 0; bank < bank_num; bank++) | |
2427 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2428 | out: | |
2429 | return r; | |
2430 | } | |
2431 | ||
2432 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2433 | struct kvm_x86_mce *mce) | |
2434 | { | |
2435 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2436 | unsigned bank_num = mcg_cap & 0xff; | |
2437 | u64 *banks = vcpu->arch.mce_banks; | |
2438 | ||
2439 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2440 | return -EINVAL; | |
2441 | /* | |
2442 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2443 | * reporting is disabled | |
2444 | */ | |
2445 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2446 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2447 | return 0; | |
2448 | banks += 4 * mce->bank; | |
2449 | /* | |
2450 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2451 | * reporting is disabled for the bank | |
2452 | */ | |
2453 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2454 | return 0; | |
2455 | if (mce->status & MCI_STATUS_UC) { | |
2456 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2457 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2458 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2459 | return 0; |
2460 | } | |
2461 | if (banks[1] & MCI_STATUS_VAL) | |
2462 | mce->status |= MCI_STATUS_OVER; | |
2463 | banks[2] = mce->addr; | |
2464 | banks[3] = mce->misc; | |
2465 | vcpu->arch.mcg_status = mce->mcg_status; | |
2466 | banks[1] = mce->status; | |
2467 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2468 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2469 | || !(banks[1] & MCI_STATUS_UC)) { | |
2470 | if (banks[1] & MCI_STATUS_VAL) | |
2471 | mce->status |= MCI_STATUS_OVER; | |
2472 | banks[2] = mce->addr; | |
2473 | banks[3] = mce->misc; | |
2474 | banks[1] = mce->status; | |
2475 | } else | |
2476 | banks[1] |= MCI_STATUS_OVER; | |
2477 | return 0; | |
2478 | } | |
2479 | ||
3cfc3092 JK |
2480 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2481 | struct kvm_vcpu_events *events) | |
2482 | { | |
7460fb4a | 2483 | process_nmi(vcpu); |
03b82a30 JK |
2484 | events->exception.injected = |
2485 | vcpu->arch.exception.pending && | |
2486 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2487 | events->exception.nr = vcpu->arch.exception.nr; |
2488 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2489 | events->exception.pad = 0; |
3cfc3092 JK |
2490 | events->exception.error_code = vcpu->arch.exception.error_code; |
2491 | ||
03b82a30 JK |
2492 | events->interrupt.injected = |
2493 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2494 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2495 | events->interrupt.soft = 0; |
48005f64 JK |
2496 | events->interrupt.shadow = |
2497 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2498 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2499 | |
2500 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 2501 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 2502 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 2503 | events->nmi.pad = 0; |
3cfc3092 JK |
2504 | |
2505 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2506 | ||
dab4b911 | 2507 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2508 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2509 | | KVM_VCPUEVENT_VALID_SHADOW); | |
97e69aa6 | 2510 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2511 | } |
2512 | ||
2513 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2514 | struct kvm_vcpu_events *events) | |
2515 | { | |
dab4b911 | 2516 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2517 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2518 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2519 | return -EINVAL; |
2520 | ||
7460fb4a | 2521 | process_nmi(vcpu); |
3cfc3092 JK |
2522 | vcpu->arch.exception.pending = events->exception.injected; |
2523 | vcpu->arch.exception.nr = events->exception.nr; | |
2524 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2525 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2526 | ||
2527 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2528 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2529 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
2530 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2531 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2532 | events->interrupt.shadow); | |
3cfc3092 JK |
2533 | |
2534 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2535 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2536 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2537 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2538 | ||
dab4b911 JK |
2539 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2540 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 | 2541 | |
3842d135 AK |
2542 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2543 | ||
3cfc3092 JK |
2544 | return 0; |
2545 | } | |
2546 | ||
a1efbe77 JK |
2547 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2548 | struct kvm_debugregs *dbgregs) | |
2549 | { | |
a1efbe77 JK |
2550 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2551 | dbgregs->dr6 = vcpu->arch.dr6; | |
2552 | dbgregs->dr7 = vcpu->arch.dr7; | |
2553 | dbgregs->flags = 0; | |
97e69aa6 | 2554 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
2555 | } |
2556 | ||
2557 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2558 | struct kvm_debugregs *dbgregs) | |
2559 | { | |
2560 | if (dbgregs->flags) | |
2561 | return -EINVAL; | |
2562 | ||
a1efbe77 JK |
2563 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2564 | vcpu->arch.dr6 = dbgregs->dr6; | |
2565 | vcpu->arch.dr7 = dbgregs->dr7; | |
2566 | ||
a1efbe77 JK |
2567 | return 0; |
2568 | } | |
2569 | ||
2d5b5a66 SY |
2570 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2571 | struct kvm_xsave *guest_xsave) | |
2572 | { | |
2573 | if (cpu_has_xsave) | |
2574 | memcpy(guest_xsave->region, | |
2575 | &vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2576 | xstate_size); |
2d5b5a66 SY |
2577 | else { |
2578 | memcpy(guest_xsave->region, | |
2579 | &vcpu->arch.guest_fpu.state->fxsave, | |
2580 | sizeof(struct i387_fxsave_struct)); | |
2581 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2582 | XSTATE_FPSSE; | |
2583 | } | |
2584 | } | |
2585 | ||
2586 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2587 | struct kvm_xsave *guest_xsave) | |
2588 | { | |
2589 | u64 xstate_bv = | |
2590 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2591 | ||
2592 | if (cpu_has_xsave) | |
2593 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2594 | guest_xsave->region, xstate_size); |
2d5b5a66 SY |
2595 | else { |
2596 | if (xstate_bv & ~XSTATE_FPSSE) | |
2597 | return -EINVAL; | |
2598 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2599 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2600 | } | |
2601 | return 0; | |
2602 | } | |
2603 | ||
2604 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2605 | struct kvm_xcrs *guest_xcrs) | |
2606 | { | |
2607 | if (!cpu_has_xsave) { | |
2608 | guest_xcrs->nr_xcrs = 0; | |
2609 | return; | |
2610 | } | |
2611 | ||
2612 | guest_xcrs->nr_xcrs = 1; | |
2613 | guest_xcrs->flags = 0; | |
2614 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2615 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2616 | } | |
2617 | ||
2618 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2619 | struct kvm_xcrs *guest_xcrs) | |
2620 | { | |
2621 | int i, r = 0; | |
2622 | ||
2623 | if (!cpu_has_xsave) | |
2624 | return -EINVAL; | |
2625 | ||
2626 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2627 | return -EINVAL; | |
2628 | ||
2629 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2630 | /* Only support XCR0 currently */ | |
2631 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2632 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2633 | guest_xcrs->xcrs[0].value); | |
2634 | break; | |
2635 | } | |
2636 | if (r) | |
2637 | r = -EINVAL; | |
2638 | return r; | |
2639 | } | |
2640 | ||
1c0b28c2 EM |
2641 | /* |
2642 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
2643 | * stopped by the hypervisor. This function will be called from the host only. | |
2644 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
2645 | * does not support pv clocks. | |
2646 | */ | |
2647 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
2648 | { | |
1c0b28c2 EM |
2649 | if (!vcpu->arch.time_page) |
2650 | return -EINVAL; | |
51d59c6b | 2651 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
2652 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2653 | return 0; | |
2654 | } | |
2655 | ||
313a3dc7 CO |
2656 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2657 | unsigned int ioctl, unsigned long arg) | |
2658 | { | |
2659 | struct kvm_vcpu *vcpu = filp->private_data; | |
2660 | void __user *argp = (void __user *)arg; | |
2661 | int r; | |
d1ac91d8 AK |
2662 | union { |
2663 | struct kvm_lapic_state *lapic; | |
2664 | struct kvm_xsave *xsave; | |
2665 | struct kvm_xcrs *xcrs; | |
2666 | void *buffer; | |
2667 | } u; | |
2668 | ||
2669 | u.buffer = NULL; | |
313a3dc7 CO |
2670 | switch (ioctl) { |
2671 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2672 | r = -EINVAL; |
2673 | if (!vcpu->arch.apic) | |
2674 | goto out; | |
d1ac91d8 | 2675 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2676 | |
b772ff36 | 2677 | r = -ENOMEM; |
d1ac91d8 | 2678 | if (!u.lapic) |
b772ff36 | 2679 | goto out; |
d1ac91d8 | 2680 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2681 | if (r) |
2682 | goto out; | |
2683 | r = -EFAULT; | |
d1ac91d8 | 2684 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2685 | goto out; |
2686 | r = 0; | |
2687 | break; | |
2688 | } | |
2689 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2690 | r = -EINVAL; |
2691 | if (!vcpu->arch.apic) | |
2692 | goto out; | |
ff5c2c03 SL |
2693 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
2694 | if (IS_ERR(u.lapic)) { | |
2695 | r = PTR_ERR(u.lapic); | |
313a3dc7 | 2696 | goto out; |
ff5c2c03 SL |
2697 | } |
2698 | ||
d1ac91d8 | 2699 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2700 | if (r) |
2701 | goto out; | |
2702 | r = 0; | |
2703 | break; | |
2704 | } | |
f77bc6a4 ZX |
2705 | case KVM_INTERRUPT: { |
2706 | struct kvm_interrupt irq; | |
2707 | ||
2708 | r = -EFAULT; | |
2709 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2710 | goto out; | |
2711 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2712 | if (r) | |
2713 | goto out; | |
2714 | r = 0; | |
2715 | break; | |
2716 | } | |
c4abb7c9 JK |
2717 | case KVM_NMI: { |
2718 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2719 | if (r) | |
2720 | goto out; | |
2721 | r = 0; | |
2722 | break; | |
2723 | } | |
313a3dc7 CO |
2724 | case KVM_SET_CPUID: { |
2725 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2726 | struct kvm_cpuid cpuid; | |
2727 | ||
2728 | r = -EFAULT; | |
2729 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2730 | goto out; | |
2731 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2732 | if (r) | |
2733 | goto out; | |
2734 | break; | |
2735 | } | |
07716717 DK |
2736 | case KVM_SET_CPUID2: { |
2737 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2738 | struct kvm_cpuid2 cpuid; | |
2739 | ||
2740 | r = -EFAULT; | |
2741 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2742 | goto out; | |
2743 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2744 | cpuid_arg->entries); |
07716717 DK |
2745 | if (r) |
2746 | goto out; | |
2747 | break; | |
2748 | } | |
2749 | case KVM_GET_CPUID2: { | |
2750 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2751 | struct kvm_cpuid2 cpuid; | |
2752 | ||
2753 | r = -EFAULT; | |
2754 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2755 | goto out; | |
2756 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2757 | cpuid_arg->entries); |
07716717 DK |
2758 | if (r) |
2759 | goto out; | |
2760 | r = -EFAULT; | |
2761 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2762 | goto out; | |
2763 | r = 0; | |
2764 | break; | |
2765 | } | |
313a3dc7 CO |
2766 | case KVM_GET_MSRS: |
2767 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2768 | break; | |
2769 | case KVM_SET_MSRS: | |
2770 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2771 | break; | |
b209749f AK |
2772 | case KVM_TPR_ACCESS_REPORTING: { |
2773 | struct kvm_tpr_access_ctl tac; | |
2774 | ||
2775 | r = -EFAULT; | |
2776 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2777 | goto out; | |
2778 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2779 | if (r) | |
2780 | goto out; | |
2781 | r = -EFAULT; | |
2782 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2783 | goto out; | |
2784 | r = 0; | |
2785 | break; | |
2786 | }; | |
b93463aa AK |
2787 | case KVM_SET_VAPIC_ADDR: { |
2788 | struct kvm_vapic_addr va; | |
2789 | ||
2790 | r = -EINVAL; | |
2791 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2792 | goto out; | |
2793 | r = -EFAULT; | |
2794 | if (copy_from_user(&va, argp, sizeof va)) | |
2795 | goto out; | |
2796 | r = 0; | |
2797 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2798 | break; | |
2799 | } | |
890ca9ae HY |
2800 | case KVM_X86_SETUP_MCE: { |
2801 | u64 mcg_cap; | |
2802 | ||
2803 | r = -EFAULT; | |
2804 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2805 | goto out; | |
2806 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2807 | break; | |
2808 | } | |
2809 | case KVM_X86_SET_MCE: { | |
2810 | struct kvm_x86_mce mce; | |
2811 | ||
2812 | r = -EFAULT; | |
2813 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2814 | goto out; | |
2815 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2816 | break; | |
2817 | } | |
3cfc3092 JK |
2818 | case KVM_GET_VCPU_EVENTS: { |
2819 | struct kvm_vcpu_events events; | |
2820 | ||
2821 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2822 | ||
2823 | r = -EFAULT; | |
2824 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2825 | break; | |
2826 | r = 0; | |
2827 | break; | |
2828 | } | |
2829 | case KVM_SET_VCPU_EVENTS: { | |
2830 | struct kvm_vcpu_events events; | |
2831 | ||
2832 | r = -EFAULT; | |
2833 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2834 | break; | |
2835 | ||
2836 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2837 | break; | |
2838 | } | |
a1efbe77 JK |
2839 | case KVM_GET_DEBUGREGS: { |
2840 | struct kvm_debugregs dbgregs; | |
2841 | ||
2842 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2843 | ||
2844 | r = -EFAULT; | |
2845 | if (copy_to_user(argp, &dbgregs, | |
2846 | sizeof(struct kvm_debugregs))) | |
2847 | break; | |
2848 | r = 0; | |
2849 | break; | |
2850 | } | |
2851 | case KVM_SET_DEBUGREGS: { | |
2852 | struct kvm_debugregs dbgregs; | |
2853 | ||
2854 | r = -EFAULT; | |
2855 | if (copy_from_user(&dbgregs, argp, | |
2856 | sizeof(struct kvm_debugregs))) | |
2857 | break; | |
2858 | ||
2859 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2860 | break; | |
2861 | } | |
2d5b5a66 | 2862 | case KVM_GET_XSAVE: { |
d1ac91d8 | 2863 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2864 | r = -ENOMEM; |
d1ac91d8 | 2865 | if (!u.xsave) |
2d5b5a66 SY |
2866 | break; |
2867 | ||
d1ac91d8 | 2868 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2869 | |
2870 | r = -EFAULT; | |
d1ac91d8 | 2871 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2872 | break; |
2873 | r = 0; | |
2874 | break; | |
2875 | } | |
2876 | case KVM_SET_XSAVE: { | |
ff5c2c03 SL |
2877 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
2878 | if (IS_ERR(u.xsave)) { | |
2879 | r = PTR_ERR(u.xsave); | |
2880 | goto out; | |
2881 | } | |
2d5b5a66 | 2882 | |
d1ac91d8 | 2883 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2884 | break; |
2885 | } | |
2886 | case KVM_GET_XCRS: { | |
d1ac91d8 | 2887 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 2888 | r = -ENOMEM; |
d1ac91d8 | 2889 | if (!u.xcrs) |
2d5b5a66 SY |
2890 | break; |
2891 | ||
d1ac91d8 | 2892 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2893 | |
2894 | r = -EFAULT; | |
d1ac91d8 | 2895 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
2896 | sizeof(struct kvm_xcrs))) |
2897 | break; | |
2898 | r = 0; | |
2899 | break; | |
2900 | } | |
2901 | case KVM_SET_XCRS: { | |
ff5c2c03 SL |
2902 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
2903 | if (IS_ERR(u.xcrs)) { | |
2904 | r = PTR_ERR(u.xcrs); | |
2905 | goto out; | |
2906 | } | |
2d5b5a66 | 2907 | |
d1ac91d8 | 2908 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2909 | break; |
2910 | } | |
92a1f12d JR |
2911 | case KVM_SET_TSC_KHZ: { |
2912 | u32 user_tsc_khz; | |
2913 | ||
2914 | r = -EINVAL; | |
92a1f12d JR |
2915 | user_tsc_khz = (u32)arg; |
2916 | ||
2917 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
2918 | goto out; | |
2919 | ||
cc578287 ZA |
2920 | if (user_tsc_khz == 0) |
2921 | user_tsc_khz = tsc_khz; | |
2922 | ||
2923 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
2924 | |
2925 | r = 0; | |
2926 | goto out; | |
2927 | } | |
2928 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 2929 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
2930 | goto out; |
2931 | } | |
1c0b28c2 EM |
2932 | case KVM_KVMCLOCK_CTRL: { |
2933 | r = kvm_set_guest_paused(vcpu); | |
2934 | goto out; | |
2935 | } | |
313a3dc7 CO |
2936 | default: |
2937 | r = -EINVAL; | |
2938 | } | |
2939 | out: | |
d1ac91d8 | 2940 | kfree(u.buffer); |
313a3dc7 CO |
2941 | return r; |
2942 | } | |
2943 | ||
5b1c1493 CO |
2944 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
2945 | { | |
2946 | return VM_FAULT_SIGBUS; | |
2947 | } | |
2948 | ||
1fe779f8 CO |
2949 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
2950 | { | |
2951 | int ret; | |
2952 | ||
2953 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
2954 | return -1; | |
2955 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
2956 | return ret; | |
2957 | } | |
2958 | ||
b927a3ce SY |
2959 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
2960 | u64 ident_addr) | |
2961 | { | |
2962 | kvm->arch.ept_identity_map_addr = ident_addr; | |
2963 | return 0; | |
2964 | } | |
2965 | ||
1fe779f8 CO |
2966 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
2967 | u32 kvm_nr_mmu_pages) | |
2968 | { | |
2969 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
2970 | return -EINVAL; | |
2971 | ||
79fac95e | 2972 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 2973 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
2974 | |
2975 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 2976 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 2977 | |
7c8a83b7 | 2978 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 2979 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2980 | return 0; |
2981 | } | |
2982 | ||
2983 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
2984 | { | |
39de71ec | 2985 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
2986 | } |
2987 | ||
1fe779f8 CO |
2988 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
2989 | { | |
2990 | int r; | |
2991 | ||
2992 | r = 0; | |
2993 | switch (chip->chip_id) { | |
2994 | case KVM_IRQCHIP_PIC_MASTER: | |
2995 | memcpy(&chip->chip.pic, | |
2996 | &pic_irqchip(kvm)->pics[0], | |
2997 | sizeof(struct kvm_pic_state)); | |
2998 | break; | |
2999 | case KVM_IRQCHIP_PIC_SLAVE: | |
3000 | memcpy(&chip->chip.pic, | |
3001 | &pic_irqchip(kvm)->pics[1], | |
3002 | sizeof(struct kvm_pic_state)); | |
3003 | break; | |
3004 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3005 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3006 | break; |
3007 | default: | |
3008 | r = -EINVAL; | |
3009 | break; | |
3010 | } | |
3011 | return r; | |
3012 | } | |
3013 | ||
3014 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3015 | { | |
3016 | int r; | |
3017 | ||
3018 | r = 0; | |
3019 | switch (chip->chip_id) { | |
3020 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3021 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3022 | memcpy(&pic_irqchip(kvm)->pics[0], |
3023 | &chip->chip.pic, | |
3024 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3025 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3026 | break; |
3027 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3028 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3029 | memcpy(&pic_irqchip(kvm)->pics[1], |
3030 | &chip->chip.pic, | |
3031 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3032 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3033 | break; |
3034 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3035 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3036 | break; |
3037 | default: | |
3038 | r = -EINVAL; | |
3039 | break; | |
3040 | } | |
3041 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3042 | return r; | |
3043 | } | |
3044 | ||
e0f63cb9 SY |
3045 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3046 | { | |
3047 | int r = 0; | |
3048 | ||
894a9c55 | 3049 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3050 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3051 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3052 | return r; |
3053 | } | |
3054 | ||
3055 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3056 | { | |
3057 | int r = 0; | |
3058 | ||
894a9c55 | 3059 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3060 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3061 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3062 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3063 | return r; | |
3064 | } | |
3065 | ||
3066 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3067 | { | |
3068 | int r = 0; | |
3069 | ||
3070 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3071 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3072 | sizeof(ps->channels)); | |
3073 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3074 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3075 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3076 | return r; |
3077 | } | |
3078 | ||
3079 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3080 | { | |
3081 | int r = 0, start = 0; | |
3082 | u32 prev_legacy, cur_legacy; | |
3083 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3084 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3085 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3086 | if (!prev_legacy && cur_legacy) | |
3087 | start = 1; | |
3088 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3089 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3090 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3091 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3092 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3093 | return r; |
3094 | } | |
3095 | ||
52d939a0 MT |
3096 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3097 | struct kvm_reinject_control *control) | |
3098 | { | |
3099 | if (!kvm->arch.vpit) | |
3100 | return -ENXIO; | |
894a9c55 | 3101 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3102 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3103 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3104 | return 0; |
3105 | } | |
3106 | ||
95d4c16c | 3107 | /** |
60c34612 TY |
3108 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3109 | * @kvm: kvm instance | |
3110 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3111 | * |
60c34612 TY |
3112 | * We need to keep it in mind that VCPU threads can write to the bitmap |
3113 | * concurrently. So, to avoid losing data, we keep the following order for | |
3114 | * each bit: | |
95d4c16c | 3115 | * |
60c34612 TY |
3116 | * 1. Take a snapshot of the bit and clear it if needed. |
3117 | * 2. Write protect the corresponding page. | |
3118 | * 3. Flush TLB's if needed. | |
3119 | * 4. Copy the snapshot to the userspace. | |
95d4c16c | 3120 | * |
60c34612 TY |
3121 | * Between 2 and 3, the guest may write to the page using the remaining TLB |
3122 | * entry. This is not a problem because the page will be reported dirty at | |
3123 | * step 4 using the snapshot taken before and step 3 ensures that successive | |
3124 | * writes will be logged for the next call. | |
5bb064dc | 3125 | */ |
60c34612 | 3126 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3127 | { |
7850ac54 | 3128 | int r; |
5bb064dc | 3129 | struct kvm_memory_slot *memslot; |
60c34612 TY |
3130 | unsigned long n, i; |
3131 | unsigned long *dirty_bitmap; | |
3132 | unsigned long *dirty_bitmap_buffer; | |
3133 | bool is_dirty = false; | |
5bb064dc | 3134 | |
79fac95e | 3135 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3136 | |
b050b015 MT |
3137 | r = -EINVAL; |
3138 | if (log->slot >= KVM_MEMORY_SLOTS) | |
3139 | goto out; | |
3140 | ||
28a37544 | 3141 | memslot = id_to_memslot(kvm->memslots, log->slot); |
60c34612 TY |
3142 | |
3143 | dirty_bitmap = memslot->dirty_bitmap; | |
b050b015 | 3144 | r = -ENOENT; |
60c34612 | 3145 | if (!dirty_bitmap) |
b050b015 MT |
3146 | goto out; |
3147 | ||
87bf6e7d | 3148 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3149 | |
60c34612 TY |
3150 | dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long); |
3151 | memset(dirty_bitmap_buffer, 0, n); | |
b050b015 | 3152 | |
60c34612 | 3153 | spin_lock(&kvm->mmu_lock); |
b050b015 | 3154 | |
60c34612 TY |
3155 | for (i = 0; i < n / sizeof(long); i++) { |
3156 | unsigned long mask; | |
3157 | gfn_t offset; | |
cdfca7b3 | 3158 | |
60c34612 TY |
3159 | if (!dirty_bitmap[i]) |
3160 | continue; | |
b050b015 | 3161 | |
60c34612 | 3162 | is_dirty = true; |
914ebccd | 3163 | |
60c34612 TY |
3164 | mask = xchg(&dirty_bitmap[i], 0); |
3165 | dirty_bitmap_buffer[i] = mask; | |
edde99ce | 3166 | |
60c34612 TY |
3167 | offset = i * BITS_PER_LONG; |
3168 | kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); | |
5bb064dc | 3169 | } |
60c34612 TY |
3170 | if (is_dirty) |
3171 | kvm_flush_remote_tlbs(kvm); | |
3172 | ||
3173 | spin_unlock(&kvm->mmu_lock); | |
3174 | ||
3175 | r = -EFAULT; | |
3176 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) | |
3177 | goto out; | |
b050b015 | 3178 | |
5bb064dc ZX |
3179 | r = 0; |
3180 | out: | |
79fac95e | 3181 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3182 | return r; |
3183 | } | |
3184 | ||
23d43cf9 CD |
3185 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event) |
3186 | { | |
3187 | if (!irqchip_in_kernel(kvm)) | |
3188 | return -ENXIO; | |
3189 | ||
3190 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
3191 | irq_event->irq, irq_event->level); | |
3192 | return 0; | |
3193 | } | |
3194 | ||
1fe779f8 CO |
3195 | long kvm_arch_vm_ioctl(struct file *filp, |
3196 | unsigned int ioctl, unsigned long arg) | |
3197 | { | |
3198 | struct kvm *kvm = filp->private_data; | |
3199 | void __user *argp = (void __user *)arg; | |
367e1319 | 3200 | int r = -ENOTTY; |
f0d66275 DH |
3201 | /* |
3202 | * This union makes it completely explicit to gcc-3.x | |
3203 | * that these two variables' stack usage should be | |
3204 | * combined, not added together. | |
3205 | */ | |
3206 | union { | |
3207 | struct kvm_pit_state ps; | |
e9f42757 | 3208 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3209 | struct kvm_pit_config pit_config; |
f0d66275 | 3210 | } u; |
1fe779f8 CO |
3211 | |
3212 | switch (ioctl) { | |
3213 | case KVM_SET_TSS_ADDR: | |
3214 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
3215 | if (r < 0) | |
3216 | goto out; | |
3217 | break; | |
b927a3ce SY |
3218 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3219 | u64 ident_addr; | |
3220 | ||
3221 | r = -EFAULT; | |
3222 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3223 | goto out; | |
3224 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
3225 | if (r < 0) | |
3226 | goto out; | |
3227 | break; | |
3228 | } | |
1fe779f8 CO |
3229 | case KVM_SET_NR_MMU_PAGES: |
3230 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
3231 | if (r) | |
3232 | goto out; | |
3233 | break; | |
3234 | case KVM_GET_NR_MMU_PAGES: | |
3235 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3236 | break; | |
3ddea128 MT |
3237 | case KVM_CREATE_IRQCHIP: { |
3238 | struct kvm_pic *vpic; | |
3239 | ||
3240 | mutex_lock(&kvm->lock); | |
3241 | r = -EEXIST; | |
3242 | if (kvm->arch.vpic) | |
3243 | goto create_irqchip_unlock; | |
3e515705 AK |
3244 | r = -EINVAL; |
3245 | if (atomic_read(&kvm->online_vcpus)) | |
3246 | goto create_irqchip_unlock; | |
1fe779f8 | 3247 | r = -ENOMEM; |
3ddea128 MT |
3248 | vpic = kvm_create_pic(kvm); |
3249 | if (vpic) { | |
1fe779f8 CO |
3250 | r = kvm_ioapic_init(kvm); |
3251 | if (r) { | |
175504cd | 3252 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 3253 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
3254 | &vpic->dev_master); |
3255 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3256 | &vpic->dev_slave); | |
3257 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3258 | &vpic->dev_eclr); | |
175504cd | 3259 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3260 | kfree(vpic); |
3261 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3262 | } |
3263 | } else | |
3ddea128 MT |
3264 | goto create_irqchip_unlock; |
3265 | smp_wmb(); | |
3266 | kvm->arch.vpic = vpic; | |
3267 | smp_wmb(); | |
399ec807 AK |
3268 | r = kvm_setup_default_irq_routing(kvm); |
3269 | if (r) { | |
175504cd | 3270 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3271 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3272 | kvm_ioapic_destroy(kvm); |
3273 | kvm_destroy_pic(kvm); | |
3ddea128 | 3274 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3275 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3276 | } |
3ddea128 MT |
3277 | create_irqchip_unlock: |
3278 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3279 | break; |
3ddea128 | 3280 | } |
7837699f | 3281 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3282 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3283 | goto create_pit; | |
3284 | case KVM_CREATE_PIT2: | |
3285 | r = -EFAULT; | |
3286 | if (copy_from_user(&u.pit_config, argp, | |
3287 | sizeof(struct kvm_pit_config))) | |
3288 | goto out; | |
3289 | create_pit: | |
79fac95e | 3290 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3291 | r = -EEXIST; |
3292 | if (kvm->arch.vpit) | |
3293 | goto create_pit_unlock; | |
7837699f | 3294 | r = -ENOMEM; |
c5ff41ce | 3295 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3296 | if (kvm->arch.vpit) |
3297 | r = 0; | |
269e05e4 | 3298 | create_pit_unlock: |
79fac95e | 3299 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3300 | break; |
1fe779f8 CO |
3301 | case KVM_GET_IRQCHIP: { |
3302 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3303 | struct kvm_irqchip *chip; |
1fe779f8 | 3304 | |
ff5c2c03 SL |
3305 | chip = memdup_user(argp, sizeof(*chip)); |
3306 | if (IS_ERR(chip)) { | |
3307 | r = PTR_ERR(chip); | |
1fe779f8 | 3308 | goto out; |
ff5c2c03 SL |
3309 | } |
3310 | ||
1fe779f8 CO |
3311 | r = -ENXIO; |
3312 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3313 | goto get_irqchip_out; |
3314 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3315 | if (r) |
f0d66275 | 3316 | goto get_irqchip_out; |
1fe779f8 | 3317 | r = -EFAULT; |
f0d66275 DH |
3318 | if (copy_to_user(argp, chip, sizeof *chip)) |
3319 | goto get_irqchip_out; | |
1fe779f8 | 3320 | r = 0; |
f0d66275 DH |
3321 | get_irqchip_out: |
3322 | kfree(chip); | |
3323 | if (r) | |
3324 | goto out; | |
1fe779f8 CO |
3325 | break; |
3326 | } | |
3327 | case KVM_SET_IRQCHIP: { | |
3328 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3329 | struct kvm_irqchip *chip; |
1fe779f8 | 3330 | |
ff5c2c03 SL |
3331 | chip = memdup_user(argp, sizeof(*chip)); |
3332 | if (IS_ERR(chip)) { | |
3333 | r = PTR_ERR(chip); | |
1fe779f8 | 3334 | goto out; |
ff5c2c03 SL |
3335 | } |
3336 | ||
1fe779f8 CO |
3337 | r = -ENXIO; |
3338 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3339 | goto set_irqchip_out; |
3340 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3341 | if (r) |
f0d66275 | 3342 | goto set_irqchip_out; |
1fe779f8 | 3343 | r = 0; |
f0d66275 DH |
3344 | set_irqchip_out: |
3345 | kfree(chip); | |
3346 | if (r) | |
3347 | goto out; | |
1fe779f8 CO |
3348 | break; |
3349 | } | |
e0f63cb9 | 3350 | case KVM_GET_PIT: { |
e0f63cb9 | 3351 | r = -EFAULT; |
f0d66275 | 3352 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3353 | goto out; |
3354 | r = -ENXIO; | |
3355 | if (!kvm->arch.vpit) | |
3356 | goto out; | |
f0d66275 | 3357 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3358 | if (r) |
3359 | goto out; | |
3360 | r = -EFAULT; | |
f0d66275 | 3361 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3362 | goto out; |
3363 | r = 0; | |
3364 | break; | |
3365 | } | |
3366 | case KVM_SET_PIT: { | |
e0f63cb9 | 3367 | r = -EFAULT; |
f0d66275 | 3368 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3369 | goto out; |
3370 | r = -ENXIO; | |
3371 | if (!kvm->arch.vpit) | |
3372 | goto out; | |
f0d66275 | 3373 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3374 | if (r) |
3375 | goto out; | |
3376 | r = 0; | |
3377 | break; | |
3378 | } | |
e9f42757 BK |
3379 | case KVM_GET_PIT2: { |
3380 | r = -ENXIO; | |
3381 | if (!kvm->arch.vpit) | |
3382 | goto out; | |
3383 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3384 | if (r) | |
3385 | goto out; | |
3386 | r = -EFAULT; | |
3387 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3388 | goto out; | |
3389 | r = 0; | |
3390 | break; | |
3391 | } | |
3392 | case KVM_SET_PIT2: { | |
3393 | r = -EFAULT; | |
3394 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3395 | goto out; | |
3396 | r = -ENXIO; | |
3397 | if (!kvm->arch.vpit) | |
3398 | goto out; | |
3399 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3400 | if (r) | |
3401 | goto out; | |
3402 | r = 0; | |
3403 | break; | |
3404 | } | |
52d939a0 MT |
3405 | case KVM_REINJECT_CONTROL: { |
3406 | struct kvm_reinject_control control; | |
3407 | r = -EFAULT; | |
3408 | if (copy_from_user(&control, argp, sizeof(control))) | |
3409 | goto out; | |
3410 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3411 | if (r) | |
3412 | goto out; | |
3413 | r = 0; | |
3414 | break; | |
3415 | } | |
ffde22ac ES |
3416 | case KVM_XEN_HVM_CONFIG: { |
3417 | r = -EFAULT; | |
3418 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3419 | sizeof(struct kvm_xen_hvm_config))) | |
3420 | goto out; | |
3421 | r = -EINVAL; | |
3422 | if (kvm->arch.xen_hvm_config.flags) | |
3423 | goto out; | |
3424 | r = 0; | |
3425 | break; | |
3426 | } | |
afbcf7ab | 3427 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3428 | struct kvm_clock_data user_ns; |
3429 | u64 now_ns; | |
3430 | s64 delta; | |
3431 | ||
3432 | r = -EFAULT; | |
3433 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3434 | goto out; | |
3435 | ||
3436 | r = -EINVAL; | |
3437 | if (user_ns.flags) | |
3438 | goto out; | |
3439 | ||
3440 | r = 0; | |
395c6b0a | 3441 | local_irq_disable(); |
759379dd | 3442 | now_ns = get_kernel_ns(); |
afbcf7ab | 3443 | delta = user_ns.clock - now_ns; |
395c6b0a | 3444 | local_irq_enable(); |
afbcf7ab GC |
3445 | kvm->arch.kvmclock_offset = delta; |
3446 | break; | |
3447 | } | |
3448 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3449 | struct kvm_clock_data user_ns; |
3450 | u64 now_ns; | |
3451 | ||
395c6b0a | 3452 | local_irq_disable(); |
759379dd | 3453 | now_ns = get_kernel_ns(); |
afbcf7ab | 3454 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3455 | local_irq_enable(); |
afbcf7ab | 3456 | user_ns.flags = 0; |
97e69aa6 | 3457 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
3458 | |
3459 | r = -EFAULT; | |
3460 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3461 | goto out; | |
3462 | r = 0; | |
3463 | break; | |
3464 | } | |
3465 | ||
1fe779f8 CO |
3466 | default: |
3467 | ; | |
3468 | } | |
3469 | out: | |
3470 | return r; | |
3471 | } | |
3472 | ||
a16b043c | 3473 | static void kvm_init_msr_list(void) |
043405e1 CO |
3474 | { |
3475 | u32 dummy[2]; | |
3476 | unsigned i, j; | |
3477 | ||
e3267cbb GC |
3478 | /* skip the first msrs in the list. KVM-specific */ |
3479 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3480 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3481 | continue; | |
3482 | if (j < i) | |
3483 | msrs_to_save[j] = msrs_to_save[i]; | |
3484 | j++; | |
3485 | } | |
3486 | num_msrs_to_save = j; | |
3487 | } | |
3488 | ||
bda9020e MT |
3489 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3490 | const void *v) | |
bbd9b64e | 3491 | { |
70252a10 AK |
3492 | int handled = 0; |
3493 | int n; | |
3494 | ||
3495 | do { | |
3496 | n = min(len, 8); | |
3497 | if (!(vcpu->arch.apic && | |
3498 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) | |
3499 | && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3500 | break; | |
3501 | handled += n; | |
3502 | addr += n; | |
3503 | len -= n; | |
3504 | v += n; | |
3505 | } while (len); | |
bbd9b64e | 3506 | |
70252a10 | 3507 | return handled; |
bbd9b64e CO |
3508 | } |
3509 | ||
bda9020e | 3510 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3511 | { |
70252a10 AK |
3512 | int handled = 0; |
3513 | int n; | |
3514 | ||
3515 | do { | |
3516 | n = min(len, 8); | |
3517 | if (!(vcpu->arch.apic && | |
3518 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) | |
3519 | && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3520 | break; | |
3521 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
3522 | handled += n; | |
3523 | addr += n; | |
3524 | len -= n; | |
3525 | v += n; | |
3526 | } while (len); | |
bbd9b64e | 3527 | |
70252a10 | 3528 | return handled; |
bbd9b64e CO |
3529 | } |
3530 | ||
2dafc6c2 GN |
3531 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3532 | struct kvm_segment *var, int seg) | |
3533 | { | |
3534 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3535 | } | |
3536 | ||
3537 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3538 | struct kvm_segment *var, int seg) | |
3539 | { | |
3540 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3541 | } | |
3542 | ||
e459e322 | 3543 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
02f59dc9 JR |
3544 | { |
3545 | gpa_t t_gpa; | |
ab9ae313 | 3546 | struct x86_exception exception; |
02f59dc9 JR |
3547 | |
3548 | BUG_ON(!mmu_is_nested(vcpu)); | |
3549 | ||
3550 | /* NPT walks are always user-walks */ | |
3551 | access |= PFERR_USER_MASK; | |
ab9ae313 | 3552 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); |
02f59dc9 JR |
3553 | |
3554 | return t_gpa; | |
3555 | } | |
3556 | ||
ab9ae313 AK |
3557 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
3558 | struct x86_exception *exception) | |
1871c602 GN |
3559 | { |
3560 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 3561 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3562 | } |
3563 | ||
ab9ae313 AK |
3564 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
3565 | struct x86_exception *exception) | |
1871c602 GN |
3566 | { |
3567 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3568 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 3569 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3570 | } |
3571 | ||
ab9ae313 AK |
3572 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
3573 | struct x86_exception *exception) | |
1871c602 GN |
3574 | { |
3575 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3576 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 3577 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
3578 | } |
3579 | ||
3580 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
3581 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
3582 | struct x86_exception *exception) | |
1871c602 | 3583 | { |
ab9ae313 | 3584 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
3585 | } |
3586 | ||
3587 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3588 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 3589 | struct x86_exception *exception) |
bbd9b64e CO |
3590 | { |
3591 | void *data = val; | |
10589a46 | 3592 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3593 | |
3594 | while (bytes) { | |
14dfe855 | 3595 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 3596 | exception); |
bbd9b64e | 3597 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3598 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3599 | int ret; |
3600 | ||
bcc55cba | 3601 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3602 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e | 3603 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3604 | if (ret < 0) { |
c3cd7ffa | 3605 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3606 | goto out; |
3607 | } | |
bbd9b64e | 3608 | |
77c2002e IE |
3609 | bytes -= toread; |
3610 | data += toread; | |
3611 | addr += toread; | |
bbd9b64e | 3612 | } |
10589a46 | 3613 | out: |
10589a46 | 3614 | return r; |
bbd9b64e | 3615 | } |
77c2002e | 3616 | |
1871c602 | 3617 | /* used for instruction fetching */ |
0f65dd70 AK |
3618 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
3619 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 3620 | struct x86_exception *exception) |
1871c602 | 3621 | { |
0f65dd70 | 3622 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 3623 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 3624 | |
1871c602 | 3625 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, |
bcc55cba AK |
3626 | access | PFERR_FETCH_MASK, |
3627 | exception); | |
1871c602 GN |
3628 | } |
3629 | ||
064aea77 | 3630 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 3631 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 3632 | struct x86_exception *exception) |
1871c602 | 3633 | { |
0f65dd70 | 3634 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 3635 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 3636 | |
1871c602 | 3637 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 3638 | exception); |
1871c602 | 3639 | } |
064aea77 | 3640 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 3641 | |
0f65dd70 AK |
3642 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
3643 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 3644 | struct x86_exception *exception) |
1871c602 | 3645 | { |
0f65dd70 | 3646 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 3647 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
3648 | } |
3649 | ||
6a4d7550 | 3650 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 3651 | gva_t addr, void *val, |
2dafc6c2 | 3652 | unsigned int bytes, |
bcc55cba | 3653 | struct x86_exception *exception) |
77c2002e | 3654 | { |
0f65dd70 | 3655 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
3656 | void *data = val; |
3657 | int r = X86EMUL_CONTINUE; | |
3658 | ||
3659 | while (bytes) { | |
14dfe855 JR |
3660 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
3661 | PFERR_WRITE_MASK, | |
ab9ae313 | 3662 | exception); |
77c2002e IE |
3663 | unsigned offset = addr & (PAGE_SIZE-1); |
3664 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3665 | int ret; | |
3666 | ||
bcc55cba | 3667 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 3668 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
3669 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
3670 | if (ret < 0) { | |
c3cd7ffa | 3671 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3672 | goto out; |
3673 | } | |
3674 | ||
3675 | bytes -= towrite; | |
3676 | data += towrite; | |
3677 | addr += towrite; | |
3678 | } | |
3679 | out: | |
3680 | return r; | |
3681 | } | |
6a4d7550 | 3682 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 3683 | |
af7cc7d1 XG |
3684 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
3685 | gpa_t *gpa, struct x86_exception *exception, | |
3686 | bool write) | |
3687 | { | |
97d64b78 AK |
3688 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
3689 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 3690 | |
97d64b78 AK |
3691 | if (vcpu_match_mmio_gva(vcpu, gva) |
3692 | && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) { | |
bebb106a XG |
3693 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
3694 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 3695 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
3696 | return 1; |
3697 | } | |
3698 | ||
af7cc7d1 XG |
3699 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
3700 | ||
3701 | if (*gpa == UNMAPPED_GVA) | |
3702 | return -1; | |
3703 | ||
3704 | /* For APIC access vmexit */ | |
3705 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3706 | return 1; | |
3707 | ||
4f022648 XG |
3708 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
3709 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 3710 | return 1; |
4f022648 | 3711 | } |
bebb106a | 3712 | |
af7cc7d1 XG |
3713 | return 0; |
3714 | } | |
3715 | ||
3200f405 | 3716 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 3717 | const void *val, int bytes) |
bbd9b64e CO |
3718 | { |
3719 | int ret; | |
3720 | ||
3721 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3722 | if (ret < 0) |
bbd9b64e | 3723 | return 0; |
f57f2ef5 | 3724 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
3725 | return 1; |
3726 | } | |
3727 | ||
77d197b2 XG |
3728 | struct read_write_emulator_ops { |
3729 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
3730 | int bytes); | |
3731 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3732 | void *val, int bytes); | |
3733 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3734 | int bytes, void *val); | |
3735 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3736 | void *val, int bytes); | |
3737 | bool write; | |
3738 | }; | |
3739 | ||
3740 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
3741 | { | |
3742 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 3743 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 3744 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
3745 | vcpu->mmio_read_completed = 0; |
3746 | return 1; | |
3747 | } | |
3748 | ||
3749 | return 0; | |
3750 | } | |
3751 | ||
3752 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3753 | void *val, int bytes) | |
3754 | { | |
3755 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
3756 | } | |
3757 | ||
3758 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3759 | void *val, int bytes) | |
3760 | { | |
3761 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
3762 | } | |
3763 | ||
3764 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
3765 | { | |
3766 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
3767 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
3768 | } | |
3769 | ||
3770 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3771 | void *val, int bytes) | |
3772 | { | |
3773 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
3774 | return X86EMUL_IO_NEEDED; | |
3775 | } | |
3776 | ||
3777 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3778 | void *val, int bytes) | |
3779 | { | |
f78146b0 AK |
3780 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
3781 | ||
3782 | memcpy(vcpu->run->mmio.data, frag->data, frag->len); | |
77d197b2 XG |
3783 | return X86EMUL_CONTINUE; |
3784 | } | |
3785 | ||
0fbe9b0b | 3786 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
3787 | .read_write_prepare = read_prepare, |
3788 | .read_write_emulate = read_emulate, | |
3789 | .read_write_mmio = vcpu_mmio_read, | |
3790 | .read_write_exit_mmio = read_exit_mmio, | |
3791 | }; | |
3792 | ||
0fbe9b0b | 3793 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
3794 | .read_write_emulate = write_emulate, |
3795 | .read_write_mmio = write_mmio, | |
3796 | .read_write_exit_mmio = write_exit_mmio, | |
3797 | .write = true, | |
3798 | }; | |
3799 | ||
22388a3c XG |
3800 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
3801 | unsigned int bytes, | |
3802 | struct x86_exception *exception, | |
3803 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 3804 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 3805 | { |
af7cc7d1 XG |
3806 | gpa_t gpa; |
3807 | int handled, ret; | |
22388a3c | 3808 | bool write = ops->write; |
f78146b0 | 3809 | struct kvm_mmio_fragment *frag; |
10589a46 | 3810 | |
22388a3c | 3811 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 3812 | |
af7cc7d1 | 3813 | if (ret < 0) |
bbd9b64e | 3814 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3815 | |
3816 | /* For APIC access vmexit */ | |
af7cc7d1 | 3817 | if (ret) |
bbd9b64e CO |
3818 | goto mmio; |
3819 | ||
22388a3c | 3820 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
3821 | return X86EMUL_CONTINUE; |
3822 | ||
3823 | mmio: | |
3824 | /* | |
3825 | * Is this MMIO handled locally? | |
3826 | */ | |
22388a3c | 3827 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 3828 | if (handled == bytes) |
bbd9b64e | 3829 | return X86EMUL_CONTINUE; |
bbd9b64e | 3830 | |
70252a10 AK |
3831 | gpa += handled; |
3832 | bytes -= handled; | |
3833 | val += handled; | |
3834 | ||
f78146b0 AK |
3835 | while (bytes) { |
3836 | unsigned now = min(bytes, 8U); | |
bbd9b64e | 3837 | |
f78146b0 AK |
3838 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; |
3839 | frag->gpa = gpa; | |
3840 | frag->data = val; | |
3841 | frag->len = now; | |
3842 | ||
3843 | gpa += now; | |
3844 | val += now; | |
3845 | bytes -= now; | |
3846 | } | |
3847 | return X86EMUL_CONTINUE; | |
bbd9b64e CO |
3848 | } |
3849 | ||
22388a3c XG |
3850 | int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, |
3851 | void *val, unsigned int bytes, | |
3852 | struct x86_exception *exception, | |
0fbe9b0b | 3853 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 3854 | { |
0f65dd70 | 3855 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
3856 | gpa_t gpa; |
3857 | int rc; | |
3858 | ||
3859 | if (ops->read_write_prepare && | |
3860 | ops->read_write_prepare(vcpu, val, bytes)) | |
3861 | return X86EMUL_CONTINUE; | |
3862 | ||
3863 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 3864 | |
bbd9b64e CO |
3865 | /* Crossing a page boundary? */ |
3866 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 3867 | int now; |
bbd9b64e CO |
3868 | |
3869 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
3870 | rc = emulator_read_write_onepage(addr, val, now, exception, |
3871 | vcpu, ops); | |
3872 | ||
bbd9b64e CO |
3873 | if (rc != X86EMUL_CONTINUE) |
3874 | return rc; | |
3875 | addr += now; | |
3876 | val += now; | |
3877 | bytes -= now; | |
3878 | } | |
22388a3c | 3879 | |
f78146b0 AK |
3880 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
3881 | vcpu, ops); | |
3882 | if (rc != X86EMUL_CONTINUE) | |
3883 | return rc; | |
3884 | ||
3885 | if (!vcpu->mmio_nr_fragments) | |
3886 | return rc; | |
3887 | ||
3888 | gpa = vcpu->mmio_fragments[0].gpa; | |
3889 | ||
3890 | vcpu->mmio_needed = 1; | |
3891 | vcpu->mmio_cur_fragment = 0; | |
3892 | ||
3893 | vcpu->run->mmio.len = vcpu->mmio_fragments[0].len; | |
3894 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; | |
3895 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
3896 | vcpu->run->mmio.phys_addr = gpa; | |
3897 | ||
3898 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
3899 | } |
3900 | ||
3901 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
3902 | unsigned long addr, | |
3903 | void *val, | |
3904 | unsigned int bytes, | |
3905 | struct x86_exception *exception) | |
3906 | { | |
3907 | return emulator_read_write(ctxt, addr, val, bytes, | |
3908 | exception, &read_emultor); | |
3909 | } | |
3910 | ||
3911 | int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, | |
3912 | unsigned long addr, | |
3913 | const void *val, | |
3914 | unsigned int bytes, | |
3915 | struct x86_exception *exception) | |
3916 | { | |
3917 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
3918 | exception, &write_emultor); | |
bbd9b64e | 3919 | } |
bbd9b64e | 3920 | |
daea3e73 AK |
3921 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3922 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3923 | ||
3924 | #ifdef CONFIG_X86_64 | |
3925 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3926 | #else | |
3927 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 3928 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
3929 | #endif |
3930 | ||
0f65dd70 AK |
3931 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
3932 | unsigned long addr, | |
bbd9b64e CO |
3933 | const void *old, |
3934 | const void *new, | |
3935 | unsigned int bytes, | |
0f65dd70 | 3936 | struct x86_exception *exception) |
bbd9b64e | 3937 | { |
0f65dd70 | 3938 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
3939 | gpa_t gpa; |
3940 | struct page *page; | |
3941 | char *kaddr; | |
3942 | bool exchanged; | |
2bacc55c | 3943 | |
daea3e73 AK |
3944 | /* guests cmpxchg8b have to be emulated atomically */ |
3945 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3946 | goto emul_write; | |
10589a46 | 3947 | |
daea3e73 | 3948 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3949 | |
daea3e73 AK |
3950 | if (gpa == UNMAPPED_GVA || |
3951 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3952 | goto emul_write; | |
2bacc55c | 3953 | |
daea3e73 AK |
3954 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3955 | goto emul_write; | |
72dc67a6 | 3956 | |
daea3e73 | 3957 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
32cad84f | 3958 | if (is_error_page(page)) |
c19b8bd6 | 3959 | goto emul_write; |
72dc67a6 | 3960 | |
8fd75e12 | 3961 | kaddr = kmap_atomic(page); |
daea3e73 AK |
3962 | kaddr += offset_in_page(gpa); |
3963 | switch (bytes) { | |
3964 | case 1: | |
3965 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3966 | break; | |
3967 | case 2: | |
3968 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3969 | break; | |
3970 | case 4: | |
3971 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3972 | break; | |
3973 | case 8: | |
3974 | exchanged = CMPXCHG64(kaddr, old, new); | |
3975 | break; | |
3976 | default: | |
3977 | BUG(); | |
2bacc55c | 3978 | } |
8fd75e12 | 3979 | kunmap_atomic(kaddr); |
daea3e73 AK |
3980 | kvm_release_page_dirty(page); |
3981 | ||
3982 | if (!exchanged) | |
3983 | return X86EMUL_CMPXCHG_FAILED; | |
3984 | ||
f57f2ef5 | 3985 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
3986 | |
3987 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 3988 | |
3200f405 | 3989 | emul_write: |
daea3e73 | 3990 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3991 | |
0f65dd70 | 3992 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
3993 | } |
3994 | ||
cf8f70bf GN |
3995 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
3996 | { | |
3997 | /* TODO: String I/O for in kernel device */ | |
3998 | int r; | |
3999 | ||
4000 | if (vcpu->arch.pio.in) | |
4001 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
4002 | vcpu->arch.pio.size, pd); | |
4003 | else | |
4004 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
4005 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
4006 | pd); | |
4007 | return r; | |
4008 | } | |
4009 | ||
6f6fbe98 XG |
4010 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4011 | unsigned short port, void *val, | |
4012 | unsigned int count, bool in) | |
cf8f70bf | 4013 | { |
6f6fbe98 | 4014 | trace_kvm_pio(!in, port, size, count); |
cf8f70bf GN |
4015 | |
4016 | vcpu->arch.pio.port = port; | |
6f6fbe98 | 4017 | vcpu->arch.pio.in = in; |
7972995b | 4018 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4019 | vcpu->arch.pio.size = size; |
4020 | ||
4021 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4022 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4023 | return 1; |
4024 | } | |
4025 | ||
4026 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4027 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4028 | vcpu->run->io.size = size; |
4029 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4030 | vcpu->run->io.count = count; | |
4031 | vcpu->run->io.port = port; | |
4032 | ||
4033 | return 0; | |
4034 | } | |
4035 | ||
6f6fbe98 XG |
4036 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4037 | int size, unsigned short port, void *val, | |
4038 | unsigned int count) | |
cf8f70bf | 4039 | { |
ca1d4a9e | 4040 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4041 | int ret; |
ca1d4a9e | 4042 | |
6f6fbe98 XG |
4043 | if (vcpu->arch.pio.count) |
4044 | goto data_avail; | |
cf8f70bf | 4045 | |
6f6fbe98 XG |
4046 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4047 | if (ret) { | |
4048 | data_avail: | |
4049 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 4050 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4051 | return 1; |
4052 | } | |
4053 | ||
cf8f70bf GN |
4054 | return 0; |
4055 | } | |
4056 | ||
6f6fbe98 XG |
4057 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4058 | int size, unsigned short port, | |
4059 | const void *val, unsigned int count) | |
4060 | { | |
4061 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4062 | ||
4063 | memcpy(vcpu->arch.pio_data, val, size * count); | |
4064 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); | |
4065 | } | |
4066 | ||
bbd9b64e CO |
4067 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4068 | { | |
4069 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4070 | } | |
4071 | ||
3cb16fe7 | 4072 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4073 | { |
3cb16fe7 | 4074 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4075 | } |
4076 | ||
f5f48ee1 SY |
4077 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
4078 | { | |
4079 | if (!need_emulate_wbinvd(vcpu)) | |
4080 | return X86EMUL_CONTINUE; | |
4081 | ||
4082 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4083 | int cpu = get_cpu(); |
4084 | ||
4085 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4086 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4087 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4088 | put_cpu(); |
f5f48ee1 | 4089 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4090 | } else |
4091 | wbinvd(); | |
f5f48ee1 SY |
4092 | return X86EMUL_CONTINUE; |
4093 | } | |
4094 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4095 | ||
bcaf5cc5 AK |
4096 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4097 | { | |
4098 | kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); | |
4099 | } | |
4100 | ||
717746e3 | 4101 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) |
bbd9b64e | 4102 | { |
717746e3 | 4103 | return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4104 | } |
4105 | ||
717746e3 | 4106 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) |
bbd9b64e | 4107 | { |
338dbc97 | 4108 | |
717746e3 | 4109 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4110 | } |
4111 | ||
52a46617 | 4112 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4113 | { |
52a46617 | 4114 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4115 | } |
4116 | ||
717746e3 | 4117 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4118 | { |
717746e3 | 4119 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4120 | unsigned long value; |
4121 | ||
4122 | switch (cr) { | |
4123 | case 0: | |
4124 | value = kvm_read_cr0(vcpu); | |
4125 | break; | |
4126 | case 2: | |
4127 | value = vcpu->arch.cr2; | |
4128 | break; | |
4129 | case 3: | |
9f8fe504 | 4130 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4131 | break; |
4132 | case 4: | |
4133 | value = kvm_read_cr4(vcpu); | |
4134 | break; | |
4135 | case 8: | |
4136 | value = kvm_get_cr8(vcpu); | |
4137 | break; | |
4138 | default: | |
a737f256 | 4139 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4140 | return 0; |
4141 | } | |
4142 | ||
4143 | return value; | |
4144 | } | |
4145 | ||
717746e3 | 4146 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4147 | { |
717746e3 | 4148 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4149 | int res = 0; |
4150 | ||
52a46617 GN |
4151 | switch (cr) { |
4152 | case 0: | |
49a9b07e | 4153 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4154 | break; |
4155 | case 2: | |
4156 | vcpu->arch.cr2 = val; | |
4157 | break; | |
4158 | case 3: | |
2390218b | 4159 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4160 | break; |
4161 | case 4: | |
a83b29c6 | 4162 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4163 | break; |
4164 | case 8: | |
eea1cff9 | 4165 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4166 | break; |
4167 | default: | |
a737f256 | 4168 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4169 | res = -1; |
52a46617 | 4170 | } |
0f12244f GN |
4171 | |
4172 | return res; | |
52a46617 GN |
4173 | } |
4174 | ||
4cee4798 KW |
4175 | static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val) |
4176 | { | |
4177 | kvm_set_rflags(emul_to_vcpu(ctxt), val); | |
4178 | } | |
4179 | ||
717746e3 | 4180 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4181 | { |
717746e3 | 4182 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4183 | } |
4184 | ||
4bff1e86 | 4185 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4186 | { |
4bff1e86 | 4187 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4188 | } |
4189 | ||
4bff1e86 | 4190 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4191 | { |
4bff1e86 | 4192 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4193 | } |
4194 | ||
1ac9d0cf AK |
4195 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4196 | { | |
4197 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4198 | } | |
4199 | ||
4200 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4201 | { | |
4202 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4203 | } | |
4204 | ||
4bff1e86 AK |
4205 | static unsigned long emulator_get_cached_segment_base( |
4206 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4207 | { |
4bff1e86 | 4208 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4209 | } |
4210 | ||
1aa36616 AK |
4211 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4212 | struct desc_struct *desc, u32 *base3, | |
4213 | int seg) | |
2dafc6c2 GN |
4214 | { |
4215 | struct kvm_segment var; | |
4216 | ||
4bff1e86 | 4217 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4218 | *selector = var.selector; |
2dafc6c2 GN |
4219 | |
4220 | if (var.unusable) | |
4221 | return false; | |
4222 | ||
4223 | if (var.g) | |
4224 | var.limit >>= 12; | |
4225 | set_desc_limit(desc, var.limit); | |
4226 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4227 | #ifdef CONFIG_X86_64 |
4228 | if (base3) | |
4229 | *base3 = var.base >> 32; | |
4230 | #endif | |
2dafc6c2 GN |
4231 | desc->type = var.type; |
4232 | desc->s = var.s; | |
4233 | desc->dpl = var.dpl; | |
4234 | desc->p = var.present; | |
4235 | desc->avl = var.avl; | |
4236 | desc->l = var.l; | |
4237 | desc->d = var.db; | |
4238 | desc->g = var.g; | |
4239 | ||
4240 | return true; | |
4241 | } | |
4242 | ||
1aa36616 AK |
4243 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4244 | struct desc_struct *desc, u32 base3, | |
4245 | int seg) | |
2dafc6c2 | 4246 | { |
4bff1e86 | 4247 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4248 | struct kvm_segment var; |
4249 | ||
1aa36616 | 4250 | var.selector = selector; |
2dafc6c2 | 4251 | var.base = get_desc_base(desc); |
5601d05b GN |
4252 | #ifdef CONFIG_X86_64 |
4253 | var.base |= ((u64)base3) << 32; | |
4254 | #endif | |
2dafc6c2 GN |
4255 | var.limit = get_desc_limit(desc); |
4256 | if (desc->g) | |
4257 | var.limit = (var.limit << 12) | 0xfff; | |
4258 | var.type = desc->type; | |
4259 | var.present = desc->p; | |
4260 | var.dpl = desc->dpl; | |
4261 | var.db = desc->d; | |
4262 | var.s = desc->s; | |
4263 | var.l = desc->l; | |
4264 | var.g = desc->g; | |
4265 | var.avl = desc->avl; | |
4266 | var.present = desc->p; | |
4267 | var.unusable = !var.present; | |
4268 | var.padding = 0; | |
4269 | ||
4270 | kvm_set_segment(vcpu, &var, seg); | |
4271 | return; | |
4272 | } | |
4273 | ||
717746e3 AK |
4274 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4275 | u32 msr_index, u64 *pdata) | |
4276 | { | |
4277 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
4278 | } | |
4279 | ||
4280 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4281 | u32 msr_index, u64 data) | |
4282 | { | |
4283 | return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); | |
4284 | } | |
4285 | ||
222d21aa AK |
4286 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4287 | u32 pmc, u64 *pdata) | |
4288 | { | |
4289 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4290 | } | |
4291 | ||
6c3287f7 AK |
4292 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4293 | { | |
4294 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4295 | } | |
4296 | ||
5037f6f3 AK |
4297 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4298 | { | |
4299 | preempt_disable(); | |
5197b808 | 4300 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4301 | /* |
4302 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4303 | * so it may be clear at this point. | |
4304 | */ | |
4305 | clts(); | |
4306 | } | |
4307 | ||
4308 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4309 | { | |
4310 | preempt_enable(); | |
4311 | } | |
4312 | ||
2953538e | 4313 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 4314 | struct x86_instruction_info *info, |
c4f035c6 AK |
4315 | enum x86_intercept_stage stage) |
4316 | { | |
2953538e | 4317 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
4318 | } |
4319 | ||
0017f93a | 4320 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
4321 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
4322 | { | |
0017f93a | 4323 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
4324 | } |
4325 | ||
dd856efa AK |
4326 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
4327 | { | |
4328 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
4329 | } | |
4330 | ||
4331 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
4332 | { | |
4333 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
4334 | } | |
4335 | ||
0225fb50 | 4336 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
4337 | .read_gpr = emulator_read_gpr, |
4338 | .write_gpr = emulator_write_gpr, | |
1871c602 | 4339 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4340 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4341 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4342 | .read_emulated = emulator_read_emulated, |
4343 | .write_emulated = emulator_write_emulated, | |
4344 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 4345 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
4346 | .pio_in_emulated = emulator_pio_in_emulated, |
4347 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
4348 | .get_segment = emulator_get_segment, |
4349 | .set_segment = emulator_set_segment, | |
5951c442 | 4350 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4351 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4352 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
4353 | .set_gdt = emulator_set_gdt, |
4354 | .set_idt = emulator_set_idt, | |
52a46617 GN |
4355 | .get_cr = emulator_get_cr, |
4356 | .set_cr = emulator_set_cr, | |
4cee4798 | 4357 | .set_rflags = emulator_set_rflags, |
9c537244 | 4358 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4359 | .get_dr = emulator_get_dr, |
4360 | .set_dr = emulator_set_dr, | |
717746e3 AK |
4361 | .set_msr = emulator_set_msr, |
4362 | .get_msr = emulator_get_msr, | |
222d21aa | 4363 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 4364 | .halt = emulator_halt, |
bcaf5cc5 | 4365 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 4366 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
4367 | .get_fpu = emulator_get_fpu, |
4368 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 4369 | .intercept = emulator_intercept, |
bdb42f5a | 4370 | .get_cpuid = emulator_get_cpuid, |
bbd9b64e CO |
4371 | }; |
4372 | ||
95cb2295 GN |
4373 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4374 | { | |
4375 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4376 | /* | |
4377 | * an sti; sti; sequence only disable interrupts for the first | |
4378 | * instruction. So, if the last instruction, be it emulated or | |
4379 | * not, left the system with the INT_STI flag enabled, it | |
4380 | * means that the last instruction is an sti. We should not | |
4381 | * leave the flag on in this case. The same goes for mov ss | |
4382 | */ | |
4383 | if (!(int_shadow & mask)) | |
4384 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4385 | } | |
4386 | ||
54b8486f GN |
4387 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
4388 | { | |
4389 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 4390 | if (ctxt->exception.vector == PF_VECTOR) |
6389ee94 | 4391 | kvm_propagate_fault(vcpu, &ctxt->exception); |
da9cb575 AK |
4392 | else if (ctxt->exception.error_code_valid) |
4393 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, | |
4394 | ctxt->exception.error_code); | |
54b8486f | 4395 | else |
da9cb575 | 4396 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
54b8486f GN |
4397 | } |
4398 | ||
dd856efa | 4399 | static void init_decode_cache(struct x86_emulate_ctxt *ctxt) |
b5c9ff73 | 4400 | { |
9dac77fa | 4401 | memset(&ctxt->twobyte, 0, |
dd856efa | 4402 | (void *)&ctxt->_regs - (void *)&ctxt->twobyte); |
b5c9ff73 | 4403 | |
9dac77fa AK |
4404 | ctxt->fetch.start = 0; |
4405 | ctxt->fetch.end = 0; | |
4406 | ctxt->io_read.pos = 0; | |
4407 | ctxt->io_read.end = 0; | |
4408 | ctxt->mem_read.pos = 0; | |
4409 | ctxt->mem_read.end = 0; | |
b5c9ff73 TY |
4410 | } |
4411 | ||
8ec4722d MG |
4412 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4413 | { | |
adf52235 | 4414 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
4415 | int cs_db, cs_l; |
4416 | ||
8ec4722d MG |
4417 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
4418 | ||
adf52235 TY |
4419 | ctxt->eflags = kvm_get_rflags(vcpu); |
4420 | ctxt->eip = kvm_rip_read(vcpu); | |
4421 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4422 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
4423 | cs_l ? X86EMUL_MODE_PROT64 : | |
4424 | cs_db ? X86EMUL_MODE_PROT32 : | |
4425 | X86EMUL_MODE_PROT16; | |
4426 | ctxt->guest_mode = is_guest_mode(vcpu); | |
4427 | ||
dd856efa | 4428 | init_decode_cache(ctxt); |
7ae441ea | 4429 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
4430 | } |
4431 | ||
71f9833b | 4432 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 4433 | { |
9d74191a | 4434 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
4435 | int ret; |
4436 | ||
4437 | init_emulate_ctxt(vcpu); | |
4438 | ||
9dac77fa AK |
4439 | ctxt->op_bytes = 2; |
4440 | ctxt->ad_bytes = 2; | |
4441 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 4442 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
4443 | |
4444 | if (ret != X86EMUL_CONTINUE) | |
4445 | return EMULATE_FAIL; | |
4446 | ||
9dac77fa | 4447 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
4448 | kvm_rip_write(vcpu, ctxt->eip); |
4449 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
4450 | |
4451 | if (irq == NMI_VECTOR) | |
7460fb4a | 4452 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
4453 | else |
4454 | vcpu->arch.interrupt.pending = false; | |
4455 | ||
4456 | return EMULATE_DONE; | |
4457 | } | |
4458 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
4459 | ||
6d77dbfc GN |
4460 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
4461 | { | |
fc3a9157 JR |
4462 | int r = EMULATE_DONE; |
4463 | ||
6d77dbfc GN |
4464 | ++vcpu->stat.insn_emulation_fail; |
4465 | trace_kvm_emulate_insn_failed(vcpu); | |
fc3a9157 JR |
4466 | if (!is_guest_mode(vcpu)) { |
4467 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4468 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4469 | vcpu->run->internal.ndata = 0; | |
4470 | r = EMULATE_FAIL; | |
4471 | } | |
6d77dbfc | 4472 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
4473 | |
4474 | return r; | |
6d77dbfc GN |
4475 | } |
4476 | ||
a6f177ef GN |
4477 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva) |
4478 | { | |
4479 | gpa_t gpa; | |
8e3d9d06 | 4480 | pfn_t pfn; |
a6f177ef | 4481 | |
68be0803 GN |
4482 | if (tdp_enabled) |
4483 | return false; | |
4484 | ||
a6f177ef GN |
4485 | /* |
4486 | * if emulation was due to access to shadowed page table | |
4a969980 | 4487 | * and it failed try to unshadow page and re-enter the |
a6f177ef GN |
4488 | * guest to let CPU execute the instruction. |
4489 | */ | |
4490 | if (kvm_mmu_unprotect_page_virt(vcpu, gva)) | |
4491 | return true; | |
4492 | ||
4493 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL); | |
4494 | ||
4495 | if (gpa == UNMAPPED_GVA) | |
4496 | return true; /* let cpu generate fault */ | |
4497 | ||
8e3d9d06 XG |
4498 | /* |
4499 | * Do not retry the unhandleable instruction if it faults on the | |
4500 | * readonly host memory, otherwise it will goto a infinite loop: | |
4501 | * retry instruction -> write #PF -> emulation fail -> retry | |
4502 | * instruction -> ... | |
4503 | */ | |
4504 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
4505 | if (!is_error_pfn(pfn)) { | |
4506 | kvm_release_pfn_clean(pfn); | |
a6f177ef | 4507 | return true; |
8e3d9d06 | 4508 | } |
a6f177ef GN |
4509 | |
4510 | return false; | |
4511 | } | |
4512 | ||
1cb3f3ae XG |
4513 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
4514 | unsigned long cr2, int emulation_type) | |
4515 | { | |
4516 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4517 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
4518 | ||
4519 | last_retry_eip = vcpu->arch.last_retry_eip; | |
4520 | last_retry_addr = vcpu->arch.last_retry_addr; | |
4521 | ||
4522 | /* | |
4523 | * If the emulation is caused by #PF and it is non-page_table | |
4524 | * writing instruction, it means the VM-EXIT is caused by shadow | |
4525 | * page protected, we can zap the shadow page and retry this | |
4526 | * instruction directly. | |
4527 | * | |
4528 | * Note: if the guest uses a non-page-table modifying instruction | |
4529 | * on the PDE that points to the instruction, then we will unmap | |
4530 | * the instruction and go to an infinite loop. So, we cache the | |
4531 | * last retried eip and the last fault address, if we meet the eip | |
4532 | * and the address again, we can break out of the potential infinite | |
4533 | * loop. | |
4534 | */ | |
4535 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
4536 | ||
4537 | if (!(emulation_type & EMULTYPE_RETRY)) | |
4538 | return false; | |
4539 | ||
4540 | if (x86_page_table_writing_insn(ctxt)) | |
4541 | return false; | |
4542 | ||
4543 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
4544 | return false; | |
4545 | ||
4546 | vcpu->arch.last_retry_eip = ctxt->eip; | |
4547 | vcpu->arch.last_retry_addr = cr2; | |
4548 | ||
4549 | if (!vcpu->arch.mmu.direct_map) | |
4550 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
4551 | ||
4552 | kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
4553 | ||
4554 | return true; | |
4555 | } | |
4556 | ||
716d51ab GN |
4557 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
4558 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
4559 | ||
51d8b661 AP |
4560 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
4561 | unsigned long cr2, | |
dc25e89e AP |
4562 | int emulation_type, |
4563 | void *insn, | |
4564 | int insn_len) | |
bbd9b64e | 4565 | { |
95cb2295 | 4566 | int r; |
9d74191a | 4567 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 4568 | bool writeback = true; |
bbd9b64e | 4569 | |
26eef70c | 4570 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 4571 | |
571008da | 4572 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 4573 | init_emulate_ctxt(vcpu); |
9d74191a TY |
4574 | ctxt->interruptibility = 0; |
4575 | ctxt->have_exception = false; | |
4576 | ctxt->perm_ok = false; | |
bbd9b64e | 4577 | |
9d74191a | 4578 | ctxt->only_vendor_specific_insn |
4005996e AK |
4579 | = emulation_type & EMULTYPE_TRAP_UD; |
4580 | ||
9d74191a | 4581 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 4582 | |
e46479f8 | 4583 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 4584 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 4585 | if (r != EMULATION_OK) { |
4005996e AK |
4586 | if (emulation_type & EMULTYPE_TRAP_UD) |
4587 | return EMULATE_FAIL; | |
a6f177ef | 4588 | if (reexecute_instruction(vcpu, cr2)) |
bbd9b64e | 4589 | return EMULATE_DONE; |
6d77dbfc GN |
4590 | if (emulation_type & EMULTYPE_SKIP) |
4591 | return EMULATE_FAIL; | |
4592 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4593 | } |
4594 | } | |
4595 | ||
ba8afb6b | 4596 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 4597 | kvm_rip_write(vcpu, ctxt->_eip); |
ba8afb6b GN |
4598 | return EMULATE_DONE; |
4599 | } | |
4600 | ||
1cb3f3ae XG |
4601 | if (retry_instruction(ctxt, cr2, emulation_type)) |
4602 | return EMULATE_DONE; | |
4603 | ||
7ae441ea | 4604 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 4605 | changes registers values during IO operation */ |
7ae441ea GN |
4606 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
4607 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 4608 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 4609 | } |
4d2179e1 | 4610 | |
5cd21917 | 4611 | restart: |
9d74191a | 4612 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 4613 | |
775fde86 JR |
4614 | if (r == EMULATION_INTERCEPTED) |
4615 | return EMULATE_DONE; | |
4616 | ||
d2ddd1c4 | 4617 | if (r == EMULATION_FAILED) { |
a6f177ef | 4618 | if (reexecute_instruction(vcpu, cr2)) |
c3cd7ffa GN |
4619 | return EMULATE_DONE; |
4620 | ||
6d77dbfc | 4621 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4622 | } |
4623 | ||
9d74191a | 4624 | if (ctxt->have_exception) { |
54b8486f | 4625 | inject_emulated_exception(vcpu); |
d2ddd1c4 GN |
4626 | r = EMULATE_DONE; |
4627 | } else if (vcpu->arch.pio.count) { | |
3457e419 GN |
4628 | if (!vcpu->arch.pio.in) |
4629 | vcpu->arch.pio.count = 0; | |
716d51ab | 4630 | else { |
7ae441ea | 4631 | writeback = false; |
716d51ab GN |
4632 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
4633 | } | |
e85d28f8 | 4634 | r = EMULATE_DO_MMIO; |
7ae441ea GN |
4635 | } else if (vcpu->mmio_needed) { |
4636 | if (!vcpu->mmio_is_write) | |
4637 | writeback = false; | |
e85d28f8 | 4638 | r = EMULATE_DO_MMIO; |
716d51ab | 4639 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 4640 | } else if (r == EMULATION_RESTART) |
5cd21917 | 4641 | goto restart; |
d2ddd1c4 GN |
4642 | else |
4643 | r = EMULATE_DONE; | |
f850e2e6 | 4644 | |
7ae441ea | 4645 | if (writeback) { |
9d74191a TY |
4646 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
4647 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7ae441ea | 4648 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
7ae441ea | 4649 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9d74191a | 4650 | kvm_rip_write(vcpu, ctxt->eip); |
7ae441ea GN |
4651 | } else |
4652 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
4653 | |
4654 | return r; | |
de7d789a | 4655 | } |
51d8b661 | 4656 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 4657 | |
cf8f70bf | 4658 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 4659 | { |
cf8f70bf | 4660 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
4661 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
4662 | size, port, &val, 1); | |
cf8f70bf | 4663 | /* do not return to emulator after return from userspace */ |
7972995b | 4664 | vcpu->arch.pio.count = 0; |
de7d789a CO |
4665 | return ret; |
4666 | } | |
cf8f70bf | 4667 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 4668 | |
8cfdc000 ZA |
4669 | static void tsc_bad(void *info) |
4670 | { | |
0a3aee0d | 4671 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
4672 | } |
4673 | ||
4674 | static void tsc_khz_changed(void *data) | |
c8076604 | 4675 | { |
8cfdc000 ZA |
4676 | struct cpufreq_freqs *freq = data; |
4677 | unsigned long khz = 0; | |
4678 | ||
4679 | if (data) | |
4680 | khz = freq->new; | |
4681 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
4682 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
4683 | if (!khz) | |
4684 | khz = tsc_khz; | |
0a3aee0d | 4685 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
4686 | } |
4687 | ||
c8076604 GH |
4688 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
4689 | void *data) | |
4690 | { | |
4691 | struct cpufreq_freqs *freq = data; | |
4692 | struct kvm *kvm; | |
4693 | struct kvm_vcpu *vcpu; | |
4694 | int i, send_ipi = 0; | |
4695 | ||
8cfdc000 ZA |
4696 | /* |
4697 | * We allow guests to temporarily run on slowing clocks, | |
4698 | * provided we notify them after, or to run on accelerating | |
4699 | * clocks, provided we notify them before. Thus time never | |
4700 | * goes backwards. | |
4701 | * | |
4702 | * However, we have a problem. We can't atomically update | |
4703 | * the frequency of a given CPU from this function; it is | |
4704 | * merely a notifier, which can be called from any CPU. | |
4705 | * Changing the TSC frequency at arbitrary points in time | |
4706 | * requires a recomputation of local variables related to | |
4707 | * the TSC for each VCPU. We must flag these local variables | |
4708 | * to be updated and be sure the update takes place with the | |
4709 | * new frequency before any guests proceed. | |
4710 | * | |
4711 | * Unfortunately, the combination of hotplug CPU and frequency | |
4712 | * change creates an intractable locking scenario; the order | |
4713 | * of when these callouts happen is undefined with respect to | |
4714 | * CPU hotplug, and they can race with each other. As such, | |
4715 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
4716 | * undefined; you can actually have a CPU frequency change take | |
4717 | * place in between the computation of X and the setting of the | |
4718 | * variable. To protect against this problem, all updates of | |
4719 | * the per_cpu tsc_khz variable are done in an interrupt | |
4720 | * protected IPI, and all callers wishing to update the value | |
4721 | * must wait for a synchronous IPI to complete (which is trivial | |
4722 | * if the caller is on the CPU already). This establishes the | |
4723 | * necessary total order on variable updates. | |
4724 | * | |
4725 | * Note that because a guest time update may take place | |
4726 | * anytime after the setting of the VCPU's request bit, the | |
4727 | * correct TSC value must be set before the request. However, | |
4728 | * to ensure the update actually makes it to any guest which | |
4729 | * starts running in hardware virtualization between the set | |
4730 | * and the acquisition of the spinlock, we must also ping the | |
4731 | * CPU after setting the request bit. | |
4732 | * | |
4733 | */ | |
4734 | ||
c8076604 GH |
4735 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
4736 | return 0; | |
4737 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
4738 | return 0; | |
8cfdc000 ZA |
4739 | |
4740 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 4741 | |
e935b837 | 4742 | raw_spin_lock(&kvm_lock); |
c8076604 | 4743 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 4744 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
4745 | if (vcpu->cpu != freq->cpu) |
4746 | continue; | |
c285545f | 4747 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 4748 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 4749 | send_ipi = 1; |
c8076604 GH |
4750 | } |
4751 | } | |
e935b837 | 4752 | raw_spin_unlock(&kvm_lock); |
c8076604 GH |
4753 | |
4754 | if (freq->old < freq->new && send_ipi) { | |
4755 | /* | |
4756 | * We upscale the frequency. Must make the guest | |
4757 | * doesn't see old kvmclock values while running with | |
4758 | * the new frequency, otherwise we risk the guest sees | |
4759 | * time go backwards. | |
4760 | * | |
4761 | * In case we update the frequency for another cpu | |
4762 | * (which might be in guest context) send an interrupt | |
4763 | * to kick the cpu out of guest context. Next time | |
4764 | * guest context is entered kvmclock will be updated, | |
4765 | * so the guest will not see stale values. | |
4766 | */ | |
8cfdc000 | 4767 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
4768 | } |
4769 | return 0; | |
4770 | } | |
4771 | ||
4772 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
4773 | .notifier_call = kvmclock_cpufreq_notifier |
4774 | }; | |
4775 | ||
4776 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
4777 | unsigned long action, void *hcpu) | |
4778 | { | |
4779 | unsigned int cpu = (unsigned long)hcpu; | |
4780 | ||
4781 | switch (action) { | |
4782 | case CPU_ONLINE: | |
4783 | case CPU_DOWN_FAILED: | |
4784 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
4785 | break; | |
4786 | case CPU_DOWN_PREPARE: | |
4787 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
4788 | break; | |
4789 | } | |
4790 | return NOTIFY_OK; | |
4791 | } | |
4792 | ||
4793 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
4794 | .notifier_call = kvmclock_cpu_notifier, | |
4795 | .priority = -INT_MAX | |
c8076604 GH |
4796 | }; |
4797 | ||
b820cc0c ZA |
4798 | static void kvm_timer_init(void) |
4799 | { | |
4800 | int cpu; | |
4801 | ||
c285545f | 4802 | max_tsc_khz = tsc_khz; |
8cfdc000 | 4803 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
b820cc0c | 4804 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
4805 | #ifdef CONFIG_CPU_FREQ |
4806 | struct cpufreq_policy policy; | |
4807 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
4808 | cpu = get_cpu(); |
4809 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
4810 | if (policy.cpuinfo.max_freq) |
4811 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 4812 | put_cpu(); |
c285545f | 4813 | #endif |
b820cc0c ZA |
4814 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
4815 | CPUFREQ_TRANSITION_NOTIFIER); | |
4816 | } | |
c285545f | 4817 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
4818 | for_each_online_cpu(cpu) |
4819 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
b820cc0c ZA |
4820 | } |
4821 | ||
ff9d07a0 ZY |
4822 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
4823 | ||
f5132b01 | 4824 | int kvm_is_in_guest(void) |
ff9d07a0 | 4825 | { |
086c9855 | 4826 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
4827 | } |
4828 | ||
4829 | static int kvm_is_user_mode(void) | |
4830 | { | |
4831 | int user_mode = 3; | |
dcf46b94 | 4832 | |
086c9855 AS |
4833 | if (__this_cpu_read(current_vcpu)) |
4834 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 4835 | |
ff9d07a0 ZY |
4836 | return user_mode != 0; |
4837 | } | |
4838 | ||
4839 | static unsigned long kvm_get_guest_ip(void) | |
4840 | { | |
4841 | unsigned long ip = 0; | |
dcf46b94 | 4842 | |
086c9855 AS |
4843 | if (__this_cpu_read(current_vcpu)) |
4844 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 4845 | |
ff9d07a0 ZY |
4846 | return ip; |
4847 | } | |
4848 | ||
4849 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
4850 | .is_in_guest = kvm_is_in_guest, | |
4851 | .is_user_mode = kvm_is_user_mode, | |
4852 | .get_guest_ip = kvm_get_guest_ip, | |
4853 | }; | |
4854 | ||
4855 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
4856 | { | |
086c9855 | 4857 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
4858 | } |
4859 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
4860 | ||
4861 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
4862 | { | |
086c9855 | 4863 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
4864 | } |
4865 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
4866 | ||
ce88decf XG |
4867 | static void kvm_set_mmio_spte_mask(void) |
4868 | { | |
4869 | u64 mask; | |
4870 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
4871 | ||
4872 | /* | |
4873 | * Set the reserved bits and the present bit of an paging-structure | |
4874 | * entry to generate page fault with PFER.RSV = 1. | |
4875 | */ | |
4876 | mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr; | |
4877 | mask |= 1ull; | |
4878 | ||
4879 | #ifdef CONFIG_X86_64 | |
4880 | /* | |
4881 | * If reserved bit is not supported, clear the present bit to disable | |
4882 | * mmio page fault. | |
4883 | */ | |
4884 | if (maxphyaddr == 52) | |
4885 | mask &= ~1ull; | |
4886 | #endif | |
4887 | ||
4888 | kvm_mmu_set_mmio_spte_mask(mask); | |
4889 | } | |
4890 | ||
f8c16bba | 4891 | int kvm_arch_init(void *opaque) |
043405e1 | 4892 | { |
b820cc0c | 4893 | int r; |
f8c16bba ZX |
4894 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
4895 | ||
f8c16bba ZX |
4896 | if (kvm_x86_ops) { |
4897 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
4898 | r = -EEXIST; |
4899 | goto out; | |
f8c16bba ZX |
4900 | } |
4901 | ||
4902 | if (!ops->cpu_has_kvm_support()) { | |
4903 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
4904 | r = -EOPNOTSUPP; |
4905 | goto out; | |
f8c16bba ZX |
4906 | } |
4907 | if (ops->disabled_by_bios()) { | |
4908 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
4909 | r = -EOPNOTSUPP; |
4910 | goto out; | |
f8c16bba ZX |
4911 | } |
4912 | ||
97db56ce AK |
4913 | r = kvm_mmu_module_init(); |
4914 | if (r) | |
4915 | goto out; | |
4916 | ||
ce88decf | 4917 | kvm_set_mmio_spte_mask(); |
97db56ce AK |
4918 | kvm_init_msr_list(); |
4919 | ||
f8c16bba | 4920 | kvm_x86_ops = ops; |
7b52345e | 4921 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 4922 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 4923 | |
b820cc0c | 4924 | kvm_timer_init(); |
c8076604 | 4925 | |
ff9d07a0 ZY |
4926 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
4927 | ||
2acf923e DC |
4928 | if (cpu_has_xsave) |
4929 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
4930 | ||
c5cc421b | 4931 | kvm_lapic_init(); |
f8c16bba | 4932 | return 0; |
56c6d28a ZX |
4933 | |
4934 | out: | |
56c6d28a | 4935 | return r; |
043405e1 | 4936 | } |
8776e519 | 4937 | |
f8c16bba ZX |
4938 | void kvm_arch_exit(void) |
4939 | { | |
ff9d07a0 ZY |
4940 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
4941 | ||
888d256e JK |
4942 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
4943 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
4944 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 4945 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
f8c16bba | 4946 | kvm_x86_ops = NULL; |
56c6d28a ZX |
4947 | kvm_mmu_module_exit(); |
4948 | } | |
f8c16bba | 4949 | |
8776e519 HB |
4950 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
4951 | { | |
4952 | ++vcpu->stat.halt_exits; | |
4953 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 4954 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
4955 | return 1; |
4956 | } else { | |
4957 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
4958 | return 0; | |
4959 | } | |
4960 | } | |
4961 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
4962 | ||
55cd8e5a GN |
4963 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
4964 | { | |
4965 | u64 param, ingpa, outgpa, ret; | |
4966 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
4967 | bool fast, longmode; | |
4968 | int cs_db, cs_l; | |
4969 | ||
4970 | /* | |
4971 | * hypercall generates UD from non zero cpl and real mode | |
4972 | * per HYPER-V spec | |
4973 | */ | |
3eeb3288 | 4974 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
4975 | kvm_queue_exception(vcpu, UD_VECTOR); |
4976 | return 0; | |
4977 | } | |
4978 | ||
4979 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4980 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
4981 | ||
4982 | if (!longmode) { | |
ccd46936 GN |
4983 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
4984 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
4985 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
4986 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
4987 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
4988 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
4989 | } |
4990 | #ifdef CONFIG_X86_64 | |
4991 | else { | |
4992 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4993 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4994 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
4995 | } | |
4996 | #endif | |
4997 | ||
4998 | code = param & 0xffff; | |
4999 | fast = (param >> 16) & 0x1; | |
5000 | rep_cnt = (param >> 32) & 0xfff; | |
5001 | rep_idx = (param >> 48) & 0xfff; | |
5002 | ||
5003 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
5004 | ||
c25bc163 GN |
5005 | switch (code) { |
5006 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
5007 | kvm_vcpu_on_spin(vcpu); | |
5008 | break; | |
5009 | default: | |
5010 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
5011 | break; | |
5012 | } | |
55cd8e5a GN |
5013 | |
5014 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
5015 | if (longmode) { | |
5016 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5017 | } else { | |
5018 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
5019 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
5020 | } | |
5021 | ||
5022 | return 1; | |
5023 | } | |
5024 | ||
8776e519 HB |
5025 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5026 | { | |
5027 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 5028 | int r = 1; |
8776e519 | 5029 | |
55cd8e5a GN |
5030 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5031 | return kvm_hv_hypercall(vcpu); | |
5032 | ||
5fdbf976 MT |
5033 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5034 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5035 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5036 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5037 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5038 | |
229456fc | 5039 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5040 | |
8776e519 HB |
5041 | if (!is_long_mode(vcpu)) { |
5042 | nr &= 0xFFFFFFFF; | |
5043 | a0 &= 0xFFFFFFFF; | |
5044 | a1 &= 0xFFFFFFFF; | |
5045 | a2 &= 0xFFFFFFFF; | |
5046 | a3 &= 0xFFFFFFFF; | |
5047 | } | |
5048 | ||
07708c4a JK |
5049 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5050 | ret = -KVM_EPERM; | |
5051 | goto out; | |
5052 | } | |
5053 | ||
8776e519 | 5054 | switch (nr) { |
b93463aa AK |
5055 | case KVM_HC_VAPIC_POLL_IRQ: |
5056 | ret = 0; | |
5057 | break; | |
8776e519 HB |
5058 | default: |
5059 | ret = -KVM_ENOSYS; | |
5060 | break; | |
5061 | } | |
07708c4a | 5062 | out: |
5fdbf976 | 5063 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 5064 | ++vcpu->stat.hypercalls; |
2f333bcb | 5065 | return r; |
8776e519 HB |
5066 | } |
5067 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
5068 | ||
d6aa1000 | 5069 | int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 5070 | { |
d6aa1000 | 5071 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 5072 | char instruction[3]; |
5fdbf976 | 5073 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 5074 | |
8776e519 HB |
5075 | /* |
5076 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
5077 | * to ensure that the updated hypercall appears atomically across all | |
5078 | * VCPUs. | |
5079 | */ | |
5080 | kvm_mmu_zap_all(vcpu->kvm); | |
5081 | ||
8776e519 | 5082 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 5083 | |
9d74191a | 5084 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
5085 | } |
5086 | ||
b6c7a5dc HB |
5087 | /* |
5088 | * Check if userspace requested an interrupt window, and that the | |
5089 | * interrupt window is open. | |
5090 | * | |
5091 | * No need to exit to userspace if we already have an interrupt queued. | |
5092 | */ | |
851ba692 | 5093 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5094 | { |
8061823a | 5095 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 5096 | vcpu->run->request_interrupt_window && |
5df56646 | 5097 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
5098 | } |
5099 | ||
851ba692 | 5100 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5101 | { |
851ba692 AK |
5102 | struct kvm_run *kvm_run = vcpu->run; |
5103 | ||
91586a3b | 5104 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 5105 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5106 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 5107 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 5108 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 5109 | else |
b6c7a5dc | 5110 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
5111 | kvm_arch_interrupt_allowed(vcpu) && |
5112 | !kvm_cpu_has_interrupt(vcpu) && | |
5113 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
5114 | } |
5115 | ||
4484141a | 5116 | static int vapic_enter(struct kvm_vcpu *vcpu) |
b93463aa AK |
5117 | { |
5118 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5119 | struct page *page; | |
5120 | ||
5121 | if (!apic || !apic->vapic_addr) | |
4484141a | 5122 | return 0; |
b93463aa AK |
5123 | |
5124 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
4484141a XG |
5125 | if (is_error_page(page)) |
5126 | return -EFAULT; | |
72dc67a6 IE |
5127 | |
5128 | vcpu->arch.apic->vapic_page = page; | |
4484141a | 5129 | return 0; |
b93463aa AK |
5130 | } |
5131 | ||
5132 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
5133 | { | |
5134 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 5135 | int idx; |
b93463aa AK |
5136 | |
5137 | if (!apic || !apic->vapic_addr) | |
5138 | return; | |
5139 | ||
f656ce01 | 5140 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
5141 | kvm_release_page_dirty(apic->vapic_page); |
5142 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 5143 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5144 | } |
5145 | ||
95ba8273 GN |
5146 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5147 | { | |
5148 | int max_irr, tpr; | |
5149 | ||
5150 | if (!kvm_x86_ops->update_cr8_intercept) | |
5151 | return; | |
5152 | ||
88c808fd AK |
5153 | if (!vcpu->arch.apic) |
5154 | return; | |
5155 | ||
8db3baa2 GN |
5156 | if (!vcpu->arch.apic->vapic_addr) |
5157 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5158 | else | |
5159 | max_irr = -1; | |
95ba8273 GN |
5160 | |
5161 | if (max_irr != -1) | |
5162 | max_irr >>= 4; | |
5163 | ||
5164 | tpr = kvm_lapic_get_cr8(vcpu); | |
5165 | ||
5166 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5167 | } | |
5168 | ||
851ba692 | 5169 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
5170 | { |
5171 | /* try to reinject previous events if any */ | |
b59bb7bd | 5172 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
5173 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
5174 | vcpu->arch.exception.has_error_code, | |
5175 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
5176 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
5177 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
5178 | vcpu->arch.exception.error_code, |
5179 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
5180 | return; |
5181 | } | |
5182 | ||
95ba8273 GN |
5183 | if (vcpu->arch.nmi_injected) { |
5184 | kvm_x86_ops->set_nmi(vcpu); | |
5185 | return; | |
5186 | } | |
5187 | ||
5188 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 5189 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
5190 | return; |
5191 | } | |
5192 | ||
5193 | /* try to inject new event if pending */ | |
5194 | if (vcpu->arch.nmi_pending) { | |
5195 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 5196 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
5197 | vcpu->arch.nmi_injected = true; |
5198 | kvm_x86_ops->set_nmi(vcpu); | |
5199 | } | |
5200 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
5201 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
5202 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
5203 | false); | |
5204 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
5205 | } |
5206 | } | |
5207 | } | |
5208 | ||
2acf923e DC |
5209 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
5210 | { | |
5211 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
5212 | !vcpu->guest_xcr0_loaded) { | |
5213 | /* kvm_set_xcr() also depends on this */ | |
5214 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
5215 | vcpu->guest_xcr0_loaded = 1; | |
5216 | } | |
5217 | } | |
5218 | ||
5219 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
5220 | { | |
5221 | if (vcpu->guest_xcr0_loaded) { | |
5222 | if (vcpu->arch.xcr0 != host_xcr0) | |
5223 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
5224 | vcpu->guest_xcr0_loaded = 0; | |
5225 | } | |
5226 | } | |
5227 | ||
7460fb4a AK |
5228 | static void process_nmi(struct kvm_vcpu *vcpu) |
5229 | { | |
5230 | unsigned limit = 2; | |
5231 | ||
5232 | /* | |
5233 | * x86 is limited to one NMI running, and one NMI pending after it. | |
5234 | * If an NMI is already in progress, limit further NMIs to just one. | |
5235 | * Otherwise, allow two (and we'll inject the first one immediately). | |
5236 | */ | |
5237 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
5238 | limit = 1; | |
5239 | ||
5240 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
5241 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
5242 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5243 | } | |
5244 | ||
851ba692 | 5245 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
5246 | { |
5247 | int r; | |
6a8b1d13 | 5248 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 5249 | vcpu->run->request_interrupt_window; |
d6185f20 | 5250 | bool req_immediate_exit = 0; |
b6c7a5dc | 5251 | |
3e007509 | 5252 | if (vcpu->requests) { |
a8eeb04a | 5253 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 5254 | kvm_mmu_unload(vcpu); |
a8eeb04a | 5255 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 5256 | __kvm_migrate_timers(vcpu); |
34c238a1 ZA |
5257 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
5258 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
5259 | if (unlikely(r)) |
5260 | goto out; | |
5261 | } | |
a8eeb04a | 5262 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 5263 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 5264 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 5265 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 5266 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 5267 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
5268 | r = 0; |
5269 | goto out; | |
5270 | } | |
a8eeb04a | 5271 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 5272 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
5273 | r = 0; |
5274 | goto out; | |
5275 | } | |
a8eeb04a | 5276 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
5277 | vcpu->fpu_active = 0; |
5278 | kvm_x86_ops->fpu_deactivate(vcpu); | |
5279 | } | |
af585b92 GN |
5280 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
5281 | /* Page is swapped out. Do synthetic halt */ | |
5282 | vcpu->arch.apf.halted = true; | |
5283 | r = 1; | |
5284 | goto out; | |
5285 | } | |
c9aaa895 GC |
5286 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
5287 | record_steal_time(vcpu); | |
7460fb4a AK |
5288 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
5289 | process_nmi(vcpu); | |
d6185f20 NHE |
5290 | req_immediate_exit = |
5291 | kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu); | |
f5132b01 GN |
5292 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
5293 | kvm_handle_pmu_event(vcpu); | |
5294 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
5295 | kvm_deliver_pmi(vcpu); | |
2f52d58c | 5296 | } |
b93463aa | 5297 | |
b463a6f7 AK |
5298 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
5299 | inject_pending_event(vcpu); | |
5300 | ||
5301 | /* enable NMI/IRQ window open exits if needed */ | |
7460fb4a | 5302 | if (vcpu->arch.nmi_pending) |
b463a6f7 AK |
5303 | kvm_x86_ops->enable_nmi_window(vcpu); |
5304 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
5305 | kvm_x86_ops->enable_irq_window(vcpu); | |
5306 | ||
5307 | if (kvm_lapic_enabled(vcpu)) { | |
5308 | update_cr8_intercept(vcpu); | |
5309 | kvm_lapic_sync_to_vapic(vcpu); | |
5310 | } | |
5311 | } | |
5312 | ||
d8368af8 AK |
5313 | r = kvm_mmu_reload(vcpu); |
5314 | if (unlikely(r)) { | |
d905c069 | 5315 | goto cancel_injection; |
d8368af8 AK |
5316 | } |
5317 | ||
b6c7a5dc HB |
5318 | preempt_disable(); |
5319 | ||
5320 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
5321 | if (vcpu->fpu_active) |
5322 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 5323 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 5324 | |
6b7e2d09 XG |
5325 | vcpu->mode = IN_GUEST_MODE; |
5326 | ||
5327 | /* We should set ->mode before check ->requests, | |
5328 | * see the comment in make_all_cpus_request. | |
5329 | */ | |
5330 | smp_mb(); | |
b6c7a5dc | 5331 | |
d94e1dc9 | 5332 | local_irq_disable(); |
32f88400 | 5333 | |
6b7e2d09 | 5334 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 5335 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 5336 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5337 | smp_wmb(); |
6c142801 AK |
5338 | local_irq_enable(); |
5339 | preempt_enable(); | |
5340 | r = 1; | |
d905c069 | 5341 | goto cancel_injection; |
6c142801 AK |
5342 | } |
5343 | ||
f656ce01 | 5344 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 5345 | |
d6185f20 NHE |
5346 | if (req_immediate_exit) |
5347 | smp_send_reschedule(vcpu->cpu); | |
5348 | ||
b6c7a5dc HB |
5349 | kvm_guest_enter(); |
5350 | ||
42dbaa5a | 5351 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
5352 | set_debugreg(0, 7); |
5353 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5354 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5355 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5356 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
5357 | } | |
b6c7a5dc | 5358 | |
229456fc | 5359 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 5360 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 5361 | |
24f1e32c FW |
5362 | /* |
5363 | * If the guest has used debug registers, at least dr7 | |
5364 | * will be disabled while returning to the host. | |
5365 | * If we don't have active breakpoints in the host, we don't | |
5366 | * care about the messed up debug address registers. But if | |
5367 | * we have some of them active, restore the old state. | |
5368 | */ | |
59d8eb53 | 5369 | if (hw_breakpoint_active()) |
24f1e32c | 5370 | hw_breakpoint_restore(); |
42dbaa5a | 5371 | |
d5c1785d | 5372 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu); |
1d5f066e | 5373 | |
6b7e2d09 | 5374 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 5375 | smp_wmb(); |
b6c7a5dc HB |
5376 | local_irq_enable(); |
5377 | ||
5378 | ++vcpu->stat.exits; | |
5379 | ||
5380 | /* | |
5381 | * We must have an instruction between local_irq_enable() and | |
5382 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
5383 | * the interrupt shadow. The stat.exits increment will do nicely. | |
5384 | * But we need to prevent reordering, hence this barrier(): | |
5385 | */ | |
5386 | barrier(); | |
5387 | ||
5388 | kvm_guest_exit(); | |
5389 | ||
5390 | preempt_enable(); | |
5391 | ||
f656ce01 | 5392 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 5393 | |
b6c7a5dc HB |
5394 | /* |
5395 | * Profile KVM exit RIPs: | |
5396 | */ | |
5397 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
5398 | unsigned long rip = kvm_rip_read(vcpu); |
5399 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
5400 | } |
5401 | ||
cc578287 ZA |
5402 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
5403 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 5404 | |
5cfb1d5a MT |
5405 | if (vcpu->arch.apic_attention) |
5406 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 5407 | |
851ba692 | 5408 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
5409 | return r; |
5410 | ||
5411 | cancel_injection: | |
5412 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
5413 | if (unlikely(vcpu->arch.apic_attention)) |
5414 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
5415 | out: |
5416 | return r; | |
5417 | } | |
b6c7a5dc | 5418 | |
09cec754 | 5419 | |
851ba692 | 5420 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
5421 | { |
5422 | int r; | |
f656ce01 | 5423 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
5424 | |
5425 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
5426 | pr_debug("vcpu %d received sipi with vector # %x\n", |
5427 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 5428 | kvm_lapic_reset(vcpu); |
5f179287 | 5429 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
5430 | if (r) |
5431 | return r; | |
5432 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
5433 | } |
5434 | ||
f656ce01 | 5435 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
4484141a XG |
5436 | r = vapic_enter(vcpu); |
5437 | if (r) { | |
5438 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
5439 | return r; | |
5440 | } | |
d7690175 MT |
5441 | |
5442 | r = 1; | |
5443 | while (r > 0) { | |
af585b92 GN |
5444 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
5445 | !vcpu->arch.apf.halted) | |
851ba692 | 5446 | r = vcpu_enter_guest(vcpu); |
d7690175 | 5447 | else { |
f656ce01 | 5448 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 5449 | kvm_vcpu_block(vcpu); |
f656ce01 | 5450 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
a8eeb04a | 5451 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
09cec754 GN |
5452 | { |
5453 | switch(vcpu->arch.mp_state) { | |
5454 | case KVM_MP_STATE_HALTED: | |
d7690175 | 5455 | vcpu->arch.mp_state = |
09cec754 GN |
5456 | KVM_MP_STATE_RUNNABLE; |
5457 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 5458 | vcpu->arch.apf.halted = false; |
09cec754 GN |
5459 | break; |
5460 | case KVM_MP_STATE_SIPI_RECEIVED: | |
5461 | default: | |
5462 | r = -EINTR; | |
5463 | break; | |
5464 | } | |
5465 | } | |
d7690175 MT |
5466 | } |
5467 | ||
09cec754 GN |
5468 | if (r <= 0) |
5469 | break; | |
5470 | ||
5471 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
5472 | if (kvm_cpu_has_pending_timer(vcpu)) | |
5473 | kvm_inject_pending_timer_irqs(vcpu); | |
5474 | ||
851ba692 | 5475 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 5476 | r = -EINTR; |
851ba692 | 5477 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5478 | ++vcpu->stat.request_irq_exits; |
5479 | } | |
af585b92 GN |
5480 | |
5481 | kvm_check_async_pf_completion(vcpu); | |
5482 | ||
09cec754 GN |
5483 | if (signal_pending(current)) { |
5484 | r = -EINTR; | |
851ba692 | 5485 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5486 | ++vcpu->stat.signal_exits; |
5487 | } | |
5488 | if (need_resched()) { | |
f656ce01 | 5489 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 5490 | kvm_resched(vcpu); |
f656ce01 | 5491 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 5492 | } |
b6c7a5dc HB |
5493 | } |
5494 | ||
f656ce01 | 5495 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 5496 | |
b93463aa AK |
5497 | vapic_exit(vcpu); |
5498 | ||
b6c7a5dc HB |
5499 | return r; |
5500 | } | |
5501 | ||
716d51ab GN |
5502 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
5503 | { | |
5504 | int r; | |
5505 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
5506 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
5507 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
5508 | if (r != EMULATE_DONE) | |
5509 | return 0; | |
5510 | return 1; | |
5511 | } | |
5512 | ||
5513 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
5514 | { | |
5515 | BUG_ON(!vcpu->arch.pio.count); | |
5516 | ||
5517 | return complete_emulated_io(vcpu); | |
5518 | } | |
5519 | ||
f78146b0 AK |
5520 | /* |
5521 | * Implements the following, as a state machine: | |
5522 | * | |
5523 | * read: | |
5524 | * for each fragment | |
5525 | * write gpa, len | |
5526 | * exit | |
5527 | * copy data | |
5528 | * execute insn | |
5529 | * | |
5530 | * write: | |
5531 | * for each fragment | |
5532 | * write gpa, len | |
5533 | * copy data | |
5534 | * exit | |
5535 | */ | |
716d51ab | 5536 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
5537 | { |
5538 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 5539 | struct kvm_mmio_fragment *frag; |
5287f194 | 5540 | |
716d51ab | 5541 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 5542 | |
716d51ab GN |
5543 | /* Complete previous fragment */ |
5544 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++]; | |
5545 | if (!vcpu->mmio_is_write) | |
5546 | memcpy(frag->data, run->mmio.data, frag->len); | |
5547 | if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) { | |
5548 | vcpu->mmio_needed = 0; | |
cef4dea0 | 5549 | if (vcpu->mmio_is_write) |
716d51ab GN |
5550 | return 1; |
5551 | vcpu->mmio_read_completed = 1; | |
5552 | return complete_emulated_io(vcpu); | |
5553 | } | |
5554 | /* Initiate next fragment */ | |
5555 | ++frag; | |
5556 | run->exit_reason = KVM_EXIT_MMIO; | |
5557 | run->mmio.phys_addr = frag->gpa; | |
5558 | if (vcpu->mmio_is_write) | |
5559 | memcpy(run->mmio.data, frag->data, frag->len); | |
5560 | run->mmio.len = frag->len; | |
5561 | run->mmio.is_write = vcpu->mmio_is_write; | |
5562 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
5563 | return 0; | |
5287f194 AK |
5564 | } |
5565 | ||
716d51ab | 5566 | |
b6c7a5dc HB |
5567 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
5568 | { | |
5569 | int r; | |
5570 | sigset_t sigsaved; | |
5571 | ||
e5c30142 AK |
5572 | if (!tsk_used_math(current) && init_fpu(current)) |
5573 | return -ENOMEM; | |
5574 | ||
ac9f6dc0 AK |
5575 | if (vcpu->sigset_active) |
5576 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
5577 | ||
a4535290 | 5578 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 5579 | kvm_vcpu_block(vcpu); |
d7690175 | 5580 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
5581 | r = -EAGAIN; |
5582 | goto out; | |
b6c7a5dc HB |
5583 | } |
5584 | ||
b6c7a5dc | 5585 | /* re-sync apic's tpr */ |
eea1cff9 AP |
5586 | if (!irqchip_in_kernel(vcpu->kvm)) { |
5587 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
5588 | r = -EINVAL; | |
5589 | goto out; | |
5590 | } | |
5591 | } | |
b6c7a5dc | 5592 | |
716d51ab GN |
5593 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
5594 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
5595 | vcpu->arch.complete_userspace_io = NULL; | |
5596 | r = cui(vcpu); | |
5597 | if (r <= 0) | |
5598 | goto out; | |
5599 | } else | |
5600 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 5601 | |
851ba692 | 5602 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
5603 | |
5604 | out: | |
f1d86e46 | 5605 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
5606 | if (vcpu->sigset_active) |
5607 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
5608 | ||
b6c7a5dc HB |
5609 | return r; |
5610 | } | |
5611 | ||
5612 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5613 | { | |
7ae441ea GN |
5614 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
5615 | /* | |
5616 | * We are here if userspace calls get_regs() in the middle of | |
5617 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 5618 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
5619 | * that usually, but some bad designed PV devices (vmware |
5620 | * backdoor interface) need this to work | |
5621 | */ | |
dd856efa | 5622 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
5623 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
5624 | } | |
5fdbf976 MT |
5625 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5626 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5627 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5628 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5629 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5630 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
5631 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
5632 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 5633 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5634 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
5635 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
5636 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
5637 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
5638 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
5639 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
5640 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
5641 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
5642 | #endif |
5643 | ||
5fdbf976 | 5644 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 5645 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 5646 | |
b6c7a5dc HB |
5647 | return 0; |
5648 | } | |
5649 | ||
5650 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5651 | { | |
7ae441ea GN |
5652 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
5653 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
5654 | ||
5fdbf976 MT |
5655 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
5656 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
5657 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
5658 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
5659 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
5660 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
5661 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
5662 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 5663 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5664 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
5665 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
5666 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
5667 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
5668 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
5669 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
5670 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
5671 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
5672 | #endif |
5673 | ||
5fdbf976 | 5674 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 5675 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 5676 | |
b4f14abd JK |
5677 | vcpu->arch.exception.pending = false; |
5678 | ||
3842d135 AK |
5679 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5680 | ||
b6c7a5dc HB |
5681 | return 0; |
5682 | } | |
5683 | ||
b6c7a5dc HB |
5684 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
5685 | { | |
5686 | struct kvm_segment cs; | |
5687 | ||
3e6e0aab | 5688 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
5689 | *db = cs.db; |
5690 | *l = cs.l; | |
5691 | } | |
5692 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
5693 | ||
5694 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
5695 | struct kvm_sregs *sregs) | |
5696 | { | |
89a27f4d | 5697 | struct desc_ptr dt; |
b6c7a5dc | 5698 | |
3e6e0aab GT |
5699 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5700 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5701 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5702 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5703 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5704 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5705 | |
3e6e0aab GT |
5706 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5707 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
5708 | |
5709 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
5710 | sregs->idt.limit = dt.size; |
5711 | sregs->idt.base = dt.address; | |
b6c7a5dc | 5712 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
5713 | sregs->gdt.limit = dt.size; |
5714 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 5715 | |
4d4ec087 | 5716 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 5717 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 5718 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 5719 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 5720 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 5721 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
5722 | sregs->apic_base = kvm_get_apic_base(vcpu); |
5723 | ||
923c61bb | 5724 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 5725 | |
36752c9b | 5726 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
5727 | set_bit(vcpu->arch.interrupt.nr, |
5728 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 5729 | |
b6c7a5dc HB |
5730 | return 0; |
5731 | } | |
5732 | ||
62d9f0db MT |
5733 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
5734 | struct kvm_mp_state *mp_state) | |
5735 | { | |
62d9f0db | 5736 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
5737 | return 0; |
5738 | } | |
5739 | ||
5740 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
5741 | struct kvm_mp_state *mp_state) | |
5742 | { | |
62d9f0db | 5743 | vcpu->arch.mp_state = mp_state->mp_state; |
3842d135 | 5744 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
5745 | return 0; |
5746 | } | |
5747 | ||
7f3d35fd KW |
5748 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
5749 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 5750 | { |
9d74191a | 5751 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 5752 | int ret; |
e01c2426 | 5753 | |
8ec4722d | 5754 | init_emulate_ctxt(vcpu); |
c697518a | 5755 | |
7f3d35fd | 5756 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 5757 | has_error_code, error_code); |
c697518a | 5758 | |
c697518a | 5759 | if (ret) |
19d04437 | 5760 | return EMULATE_FAIL; |
37817f29 | 5761 | |
9d74191a TY |
5762 | kvm_rip_write(vcpu, ctxt->eip); |
5763 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 5764 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 5765 | return EMULATE_DONE; |
37817f29 IE |
5766 | } |
5767 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5768 | ||
b6c7a5dc HB |
5769 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5770 | struct kvm_sregs *sregs) | |
5771 | { | |
5772 | int mmu_reset_needed = 0; | |
63f42e02 | 5773 | int pending_vec, max_bits, idx; |
89a27f4d | 5774 | struct desc_ptr dt; |
b6c7a5dc | 5775 | |
89a27f4d GN |
5776 | dt.size = sregs->idt.limit; |
5777 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5778 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5779 | dt.size = sregs->gdt.limit; |
5780 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5781 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5782 | ||
ad312c7c | 5783 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 5784 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 5785 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 5786 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 5787 | |
2d3ad1f4 | 5788 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5789 | |
f6801dff | 5790 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5791 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5792 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5793 | ||
4d4ec087 | 5794 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5795 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5796 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5797 | |
fc78f519 | 5798 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5799 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 5800 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 5801 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
5802 | |
5803 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 5804 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 5805 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
5806 | mmu_reset_needed = 1; |
5807 | } | |
63f42e02 | 5808 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
5809 | |
5810 | if (mmu_reset_needed) | |
5811 | kvm_mmu_reset_context(vcpu); | |
5812 | ||
a50abc3b | 5813 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
5814 | pending_vec = find_first_bit( |
5815 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5816 | if (pending_vec < max_bits) { | |
66fd3f7f | 5817 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 5818 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
5819 | } |
5820 | ||
3e6e0aab GT |
5821 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5822 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5823 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5824 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5825 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5826 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5827 | |
3e6e0aab GT |
5828 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5829 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5830 | |
5f0269f5 ME |
5831 | update_cr8_intercept(vcpu); |
5832 | ||
9c3e4aab | 5833 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5834 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5835 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5836 | !is_protmode(vcpu)) |
9c3e4aab MT |
5837 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5838 | ||
3842d135 AK |
5839 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5840 | ||
b6c7a5dc HB |
5841 | return 0; |
5842 | } | |
5843 | ||
d0bfb940 JK |
5844 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5845 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5846 | { |
355be0b9 | 5847 | unsigned long rflags; |
ae675ef0 | 5848 | int i, r; |
b6c7a5dc | 5849 | |
4f926bf2 JK |
5850 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5851 | r = -EBUSY; | |
5852 | if (vcpu->arch.exception.pending) | |
2122ff5e | 5853 | goto out; |
4f926bf2 JK |
5854 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
5855 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5856 | else | |
5857 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5858 | } | |
5859 | ||
91586a3b JK |
5860 | /* |
5861 | * Read rflags as long as potentially injected trace flags are still | |
5862 | * filtered out. | |
5863 | */ | |
5864 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5865 | |
5866 | vcpu->guest_debug = dbg->control; | |
5867 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5868 | vcpu->guest_debug = 0; | |
5869 | ||
5870 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5871 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5872 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 5873 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
5874 | } else { |
5875 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5876 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 5877 | } |
c8639010 | 5878 | kvm_update_dr7(vcpu); |
ae675ef0 | 5879 | |
f92653ee JK |
5880 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5881 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5882 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5883 | |
91586a3b JK |
5884 | /* |
5885 | * Trigger an rflags update that will inject or remove the trace | |
5886 | * flags. | |
5887 | */ | |
5888 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5889 | |
c8639010 | 5890 | kvm_x86_ops->update_db_bp_intercept(vcpu); |
b6c7a5dc | 5891 | |
4f926bf2 | 5892 | r = 0; |
d0bfb940 | 5893 | |
2122ff5e | 5894 | out: |
b6c7a5dc HB |
5895 | |
5896 | return r; | |
5897 | } | |
5898 | ||
8b006791 ZX |
5899 | /* |
5900 | * Translate a guest virtual address to a guest physical address. | |
5901 | */ | |
5902 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5903 | struct kvm_translation *tr) | |
5904 | { | |
5905 | unsigned long vaddr = tr->linear_address; | |
5906 | gpa_t gpa; | |
f656ce01 | 5907 | int idx; |
8b006791 | 5908 | |
f656ce01 | 5909 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5910 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5911 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5912 | tr->physical_address = gpa; |
5913 | tr->valid = gpa != UNMAPPED_GVA; | |
5914 | tr->writeable = 1; | |
5915 | tr->usermode = 0; | |
8b006791 ZX |
5916 | |
5917 | return 0; | |
5918 | } | |
5919 | ||
d0752060 HB |
5920 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5921 | { | |
98918833 SY |
5922 | struct i387_fxsave_struct *fxsave = |
5923 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5924 | |
d0752060 HB |
5925 | memcpy(fpu->fpr, fxsave->st_space, 128); |
5926 | fpu->fcw = fxsave->cwd; | |
5927 | fpu->fsw = fxsave->swd; | |
5928 | fpu->ftwx = fxsave->twd; | |
5929 | fpu->last_opcode = fxsave->fop; | |
5930 | fpu->last_ip = fxsave->rip; | |
5931 | fpu->last_dp = fxsave->rdp; | |
5932 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5933 | ||
d0752060 HB |
5934 | return 0; |
5935 | } | |
5936 | ||
5937 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5938 | { | |
98918833 SY |
5939 | struct i387_fxsave_struct *fxsave = |
5940 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5941 | |
d0752060 HB |
5942 | memcpy(fxsave->st_space, fpu->fpr, 128); |
5943 | fxsave->cwd = fpu->fcw; | |
5944 | fxsave->swd = fpu->fsw; | |
5945 | fxsave->twd = fpu->ftwx; | |
5946 | fxsave->fop = fpu->last_opcode; | |
5947 | fxsave->rip = fpu->last_ip; | |
5948 | fxsave->rdp = fpu->last_dp; | |
5949 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5950 | ||
d0752060 HB |
5951 | return 0; |
5952 | } | |
5953 | ||
10ab25cd | 5954 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 5955 | { |
10ab25cd JK |
5956 | int err; |
5957 | ||
5958 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
5959 | if (err) | |
5960 | return err; | |
5961 | ||
98918833 | 5962 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 5963 | |
2acf923e DC |
5964 | /* |
5965 | * Ensure guest xcr0 is valid for loading | |
5966 | */ | |
5967 | vcpu->arch.xcr0 = XSTATE_FP; | |
5968 | ||
ad312c7c | 5969 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
5970 | |
5971 | return 0; | |
d0752060 HB |
5972 | } |
5973 | EXPORT_SYMBOL_GPL(fx_init); | |
5974 | ||
98918833 SY |
5975 | static void fx_free(struct kvm_vcpu *vcpu) |
5976 | { | |
5977 | fpu_free(&vcpu->arch.guest_fpu); | |
5978 | } | |
5979 | ||
d0752060 HB |
5980 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
5981 | { | |
2608d7a1 | 5982 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5983 | return; |
5984 | ||
2acf923e DC |
5985 | /* |
5986 | * Restore all possible states in the guest, | |
5987 | * and assume host would use all available bits. | |
5988 | * Guest xcr0 would be loaded later. | |
5989 | */ | |
5990 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 5991 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 5992 | __kernel_fpu_begin(); |
98918833 | 5993 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 5994 | trace_kvm_fpu(1); |
d0752060 | 5995 | } |
d0752060 HB |
5996 | |
5997 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5998 | { | |
2acf923e DC |
5999 | kvm_put_guest_xcr0(vcpu); |
6000 | ||
d0752060 HB |
6001 | if (!vcpu->guest_fpu_loaded) |
6002 | return; | |
6003 | ||
6004 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 6005 | fpu_save_init(&vcpu->arch.guest_fpu); |
b1a74bf8 | 6006 | __kernel_fpu_end(); |
f096ed85 | 6007 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 6008 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 6009 | trace_kvm_fpu(0); |
d0752060 | 6010 | } |
e9b11c17 ZX |
6011 | |
6012 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
6013 | { | |
12f9a48f | 6014 | kvmclock_reset(vcpu); |
7f1ea208 | 6015 | |
f5f48ee1 | 6016 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 6017 | fx_free(vcpu); |
e9b11c17 ZX |
6018 | kvm_x86_ops->vcpu_free(vcpu); |
6019 | } | |
6020 | ||
6021 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
6022 | unsigned int id) | |
6023 | { | |
6755bae8 ZA |
6024 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
6025 | printk_once(KERN_WARNING | |
6026 | "kvm: SMP vm created on host with unstable TSC; " | |
6027 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
6028 | return kvm_x86_ops->vcpu_create(kvm, id); |
6029 | } | |
e9b11c17 | 6030 | |
26e5215f AK |
6031 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
6032 | { | |
6033 | int r; | |
e9b11c17 | 6034 | |
0bed3b56 | 6035 | vcpu->arch.mtrr_state.have_fixed = 1; |
9fc77441 MT |
6036 | r = vcpu_load(vcpu); |
6037 | if (r) | |
6038 | return r; | |
e9b11c17 ZX |
6039 | r = kvm_arch_vcpu_reset(vcpu); |
6040 | if (r == 0) | |
6041 | r = kvm_mmu_setup(vcpu); | |
6042 | vcpu_put(vcpu); | |
e9b11c17 | 6043 | |
26e5215f | 6044 | return r; |
e9b11c17 ZX |
6045 | } |
6046 | ||
d40ccc62 | 6047 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 6048 | { |
9fc77441 | 6049 | int r; |
344d9588 GN |
6050 | vcpu->arch.apf.msr_val = 0; |
6051 | ||
9fc77441 MT |
6052 | r = vcpu_load(vcpu); |
6053 | BUG_ON(r); | |
e9b11c17 ZX |
6054 | kvm_mmu_unload(vcpu); |
6055 | vcpu_put(vcpu); | |
6056 | ||
98918833 | 6057 | fx_free(vcpu); |
e9b11c17 ZX |
6058 | kvm_x86_ops->vcpu_free(vcpu); |
6059 | } | |
6060 | ||
6061 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
6062 | { | |
7460fb4a AK |
6063 | atomic_set(&vcpu->arch.nmi_queued, 0); |
6064 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 JK |
6065 | vcpu->arch.nmi_injected = false; |
6066 | ||
42dbaa5a JK |
6067 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
6068 | vcpu->arch.dr6 = DR6_FIXED_1; | |
6069 | vcpu->arch.dr7 = DR7_FIXED_1; | |
c8639010 | 6070 | kvm_update_dr7(vcpu); |
42dbaa5a | 6071 | |
3842d135 | 6072 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 6073 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 6074 | vcpu->arch.st.msr_val = 0; |
3842d135 | 6075 | |
12f9a48f GC |
6076 | kvmclock_reset(vcpu); |
6077 | ||
af585b92 GN |
6078 | kvm_clear_async_pf_completion_queue(vcpu); |
6079 | kvm_async_pf_hash_reset(vcpu); | |
6080 | vcpu->arch.apf.halted = false; | |
3842d135 | 6081 | |
f5132b01 GN |
6082 | kvm_pmu_reset(vcpu); |
6083 | ||
e9b11c17 ZX |
6084 | return kvm_x86_ops->vcpu_reset(vcpu); |
6085 | } | |
6086 | ||
10474ae8 | 6087 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 6088 | { |
ca84d1a2 ZA |
6089 | struct kvm *kvm; |
6090 | struct kvm_vcpu *vcpu; | |
6091 | int i; | |
0dd6a6ed ZA |
6092 | int ret; |
6093 | u64 local_tsc; | |
6094 | u64 max_tsc = 0; | |
6095 | bool stable, backwards_tsc = false; | |
18863bdd AK |
6096 | |
6097 | kvm_shared_msr_cpu_online(); | |
0dd6a6ed ZA |
6098 | ret = kvm_x86_ops->hardware_enable(garbage); |
6099 | if (ret != 0) | |
6100 | return ret; | |
6101 | ||
6102 | local_tsc = native_read_tsc(); | |
6103 | stable = !check_tsc_unstable(); | |
6104 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6105 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6106 | if (!stable && vcpu->cpu == smp_processor_id()) | |
6107 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
6108 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { | |
6109 | backwards_tsc = true; | |
6110 | if (vcpu->arch.last_host_tsc > max_tsc) | |
6111 | max_tsc = vcpu->arch.last_host_tsc; | |
6112 | } | |
6113 | } | |
6114 | } | |
6115 | ||
6116 | /* | |
6117 | * Sometimes, even reliable TSCs go backwards. This happens on | |
6118 | * platforms that reset TSC during suspend or hibernate actions, but | |
6119 | * maintain synchronization. We must compensate. Fortunately, we can | |
6120 | * detect that condition here, which happens early in CPU bringup, | |
6121 | * before any KVM threads can be running. Unfortunately, we can't | |
6122 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
6123 | * enough into CPU bringup that we know how much real time has actually | |
6124 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
6125 | * variables that haven't been updated yet. | |
6126 | * | |
6127 | * So we simply find the maximum observed TSC above, then record the | |
6128 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
6129 | * the adjustment will be applied. Note that we accumulate | |
6130 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
6131 | * gets a chance to run again. In the event that no KVM threads get a | |
6132 | * chance to run, we will miss the entire elapsed period, as we'll have | |
6133 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
6134 | * loose cycle time. This isn't too big a deal, since the loss will be | |
6135 | * uniform across all VCPUs (not to mention the scenario is extremely | |
6136 | * unlikely). It is possible that a second hibernate recovery happens | |
6137 | * much faster than a first, causing the observed TSC here to be | |
6138 | * smaller; this would require additional padding adjustment, which is | |
6139 | * why we set last_host_tsc to the local tsc observed here. | |
6140 | * | |
6141 | * N.B. - this code below runs only on platforms with reliable TSC, | |
6142 | * as that is the only way backwards_tsc is set above. Also note | |
6143 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
6144 | * have the same delta_cyc adjustment applied if backwards_tsc | |
6145 | * is detected. Note further, this adjustment is only done once, | |
6146 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
6147 | * called multiple times (one for each physical CPU bringup). | |
6148 | * | |
4a969980 | 6149 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
6150 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
6151 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
6152 | * guarantee that they stay in perfect synchronization. | |
6153 | */ | |
6154 | if (backwards_tsc) { | |
6155 | u64 delta_cyc = max_tsc - local_tsc; | |
6156 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6157 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6158 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
6159 | vcpu->arch.last_host_tsc = local_tsc; | |
6160 | } | |
6161 | ||
6162 | /* | |
6163 | * We have to disable TSC offset matching.. if you were | |
6164 | * booting a VM while issuing an S4 host suspend.... | |
6165 | * you may have some problem. Solving this issue is | |
6166 | * left as an exercise to the reader. | |
6167 | */ | |
6168 | kvm->arch.last_tsc_nsec = 0; | |
6169 | kvm->arch.last_tsc_write = 0; | |
6170 | } | |
6171 | ||
6172 | } | |
6173 | return 0; | |
e9b11c17 ZX |
6174 | } |
6175 | ||
6176 | void kvm_arch_hardware_disable(void *garbage) | |
6177 | { | |
6178 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 6179 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
6180 | } |
6181 | ||
6182 | int kvm_arch_hardware_setup(void) | |
6183 | { | |
6184 | return kvm_x86_ops->hardware_setup(); | |
6185 | } | |
6186 | ||
6187 | void kvm_arch_hardware_unsetup(void) | |
6188 | { | |
6189 | kvm_x86_ops->hardware_unsetup(); | |
6190 | } | |
6191 | ||
6192 | void kvm_arch_check_processor_compat(void *rtn) | |
6193 | { | |
6194 | kvm_x86_ops->check_processor_compatibility(rtn); | |
6195 | } | |
6196 | ||
3e515705 AK |
6197 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
6198 | { | |
6199 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
6200 | } | |
6201 | ||
54e9818f GN |
6202 | struct static_key kvm_no_apic_vcpu __read_mostly; |
6203 | ||
e9b11c17 ZX |
6204 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
6205 | { | |
6206 | struct page *page; | |
6207 | struct kvm *kvm; | |
6208 | int r; | |
6209 | ||
6210 | BUG_ON(vcpu->kvm == NULL); | |
6211 | kvm = vcpu->kvm; | |
6212 | ||
9aabc88f | 6213 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
c5af89b6 | 6214 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 6215 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 6216 | else |
a4535290 | 6217 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
6218 | |
6219 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
6220 | if (!page) { | |
6221 | r = -ENOMEM; | |
6222 | goto fail; | |
6223 | } | |
ad312c7c | 6224 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 6225 | |
cc578287 | 6226 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 6227 | |
e9b11c17 ZX |
6228 | r = kvm_mmu_create(vcpu); |
6229 | if (r < 0) | |
6230 | goto fail_free_pio_data; | |
6231 | ||
6232 | if (irqchip_in_kernel(kvm)) { | |
6233 | r = kvm_create_lapic(vcpu); | |
6234 | if (r < 0) | |
6235 | goto fail_mmu_destroy; | |
54e9818f GN |
6236 | } else |
6237 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 6238 | |
890ca9ae HY |
6239 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
6240 | GFP_KERNEL); | |
6241 | if (!vcpu->arch.mce_banks) { | |
6242 | r = -ENOMEM; | |
443c39bc | 6243 | goto fail_free_lapic; |
890ca9ae HY |
6244 | } |
6245 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
6246 | ||
f5f48ee1 SY |
6247 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) |
6248 | goto fail_free_mce_banks; | |
6249 | ||
af585b92 | 6250 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 6251 | kvm_pmu_init(vcpu); |
af585b92 | 6252 | |
e9b11c17 | 6253 | return 0; |
f5f48ee1 SY |
6254 | fail_free_mce_banks: |
6255 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
6256 | fail_free_lapic: |
6257 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
6258 | fail_mmu_destroy: |
6259 | kvm_mmu_destroy(vcpu); | |
6260 | fail_free_pio_data: | |
ad312c7c | 6261 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
6262 | fail: |
6263 | return r; | |
6264 | } | |
6265 | ||
6266 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
6267 | { | |
f656ce01 MT |
6268 | int idx; |
6269 | ||
f5132b01 | 6270 | kvm_pmu_destroy(vcpu); |
36cb93fd | 6271 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 6272 | kvm_free_lapic(vcpu); |
f656ce01 | 6273 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 6274 | kvm_mmu_destroy(vcpu); |
f656ce01 | 6275 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 6276 | free_page((unsigned long)vcpu->arch.pio_data); |
54e9818f GN |
6277 | if (!irqchip_in_kernel(vcpu->kvm)) |
6278 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 | 6279 | } |
d19a9cd2 | 6280 | |
e08b9637 | 6281 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 6282 | { |
e08b9637 CO |
6283 | if (type) |
6284 | return -EINVAL; | |
6285 | ||
f05e70ac | 6286 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 6287 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 6288 | |
5550af4d SY |
6289 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
6290 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
6291 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
6292 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
6293 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 6294 | |
038f8c11 | 6295 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 6296 | mutex_init(&kvm->arch.apic_map_lock); |
53f658b3 | 6297 | |
d89f5eff | 6298 | return 0; |
d19a9cd2 ZX |
6299 | } |
6300 | ||
6301 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
6302 | { | |
9fc77441 MT |
6303 | int r; |
6304 | r = vcpu_load(vcpu); | |
6305 | BUG_ON(r); | |
d19a9cd2 ZX |
6306 | kvm_mmu_unload(vcpu); |
6307 | vcpu_put(vcpu); | |
6308 | } | |
6309 | ||
6310 | static void kvm_free_vcpus(struct kvm *kvm) | |
6311 | { | |
6312 | unsigned int i; | |
988a2cae | 6313 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
6314 | |
6315 | /* | |
6316 | * Unpin any mmu pages first. | |
6317 | */ | |
af585b92 GN |
6318 | kvm_for_each_vcpu(i, vcpu, kvm) { |
6319 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 6320 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 6321 | } |
988a2cae GN |
6322 | kvm_for_each_vcpu(i, vcpu, kvm) |
6323 | kvm_arch_vcpu_free(vcpu); | |
6324 | ||
6325 | mutex_lock(&kvm->lock); | |
6326 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
6327 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 6328 | |
988a2cae GN |
6329 | atomic_set(&kvm->online_vcpus, 0); |
6330 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
6331 | } |
6332 | ||
ad8ba2cd SY |
6333 | void kvm_arch_sync_events(struct kvm *kvm) |
6334 | { | |
ba4cef31 | 6335 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 6336 | kvm_free_pit(kvm); |
ad8ba2cd SY |
6337 | } |
6338 | ||
d19a9cd2 ZX |
6339 | void kvm_arch_destroy_vm(struct kvm *kvm) |
6340 | { | |
6eb55818 | 6341 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
6342 | kfree(kvm->arch.vpic); |
6343 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 6344 | kvm_free_vcpus(kvm); |
3d45830c AK |
6345 | if (kvm->arch.apic_access_page) |
6346 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
6347 | if (kvm->arch.ept_identity_pagetable) |
6348 | put_page(kvm->arch.ept_identity_pagetable); | |
1e08ec4a | 6349 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 6350 | } |
0de10343 | 6351 | |
db3fe4eb TY |
6352 | void kvm_arch_free_memslot(struct kvm_memory_slot *free, |
6353 | struct kvm_memory_slot *dont) | |
6354 | { | |
6355 | int i; | |
6356 | ||
d89cc617 TY |
6357 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
6358 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
6359 | kvm_kvfree(free->arch.rmap[i]); | |
6360 | free->arch.rmap[i] = NULL; | |
77d11309 | 6361 | } |
d89cc617 TY |
6362 | if (i == 0) |
6363 | continue; | |
6364 | ||
6365 | if (!dont || free->arch.lpage_info[i - 1] != | |
6366 | dont->arch.lpage_info[i - 1]) { | |
6367 | kvm_kvfree(free->arch.lpage_info[i - 1]); | |
6368 | free->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb TY |
6369 | } |
6370 | } | |
6371 | } | |
6372 | ||
6373 | int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages) | |
6374 | { | |
6375 | int i; | |
6376 | ||
d89cc617 | 6377 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
6378 | unsigned long ugfn; |
6379 | int lpages; | |
d89cc617 | 6380 | int level = i + 1; |
db3fe4eb TY |
6381 | |
6382 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
6383 | slot->base_gfn, level) + 1; | |
6384 | ||
d89cc617 TY |
6385 | slot->arch.rmap[i] = |
6386 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
6387 | if (!slot->arch.rmap[i]) | |
77d11309 | 6388 | goto out_free; |
d89cc617 TY |
6389 | if (i == 0) |
6390 | continue; | |
77d11309 | 6391 | |
d89cc617 TY |
6392 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
6393 | sizeof(*slot->arch.lpage_info[i - 1])); | |
6394 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
6395 | goto out_free; |
6396 | ||
6397 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 6398 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 6399 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 6400 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
6401 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
6402 | /* | |
6403 | * If the gfn and userspace address are not aligned wrt each | |
6404 | * other, or if explicitly asked to, disable large page | |
6405 | * support for this slot | |
6406 | */ | |
6407 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
6408 | !kvm_largepages_enabled()) { | |
6409 | unsigned long j; | |
6410 | ||
6411 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 6412 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
6413 | } |
6414 | } | |
6415 | ||
6416 | return 0; | |
6417 | ||
6418 | out_free: | |
d89cc617 TY |
6419 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
6420 | kvm_kvfree(slot->arch.rmap[i]); | |
6421 | slot->arch.rmap[i] = NULL; | |
6422 | if (i == 0) | |
6423 | continue; | |
6424 | ||
6425 | kvm_kvfree(slot->arch.lpage_info[i - 1]); | |
6426 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb TY |
6427 | } |
6428 | return -ENOMEM; | |
6429 | } | |
6430 | ||
f7784b8e MT |
6431 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
6432 | struct kvm_memory_slot *memslot, | |
0de10343 | 6433 | struct kvm_memory_slot old, |
f7784b8e | 6434 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
6435 | int user_alloc) |
6436 | { | |
f7784b8e | 6437 | int npages = memslot->npages; |
7ac77099 AK |
6438 | int map_flags = MAP_PRIVATE | MAP_ANONYMOUS; |
6439 | ||
6440 | /* Prevent internal slot pages from being moved by fork()/COW. */ | |
6441 | if (memslot->id >= KVM_MEMORY_SLOTS) | |
6442 | map_flags = MAP_SHARED | MAP_ANONYMOUS; | |
0de10343 ZX |
6443 | |
6444 | /*To keep backward compatibility with older userspace, | |
4a969980 | 6445 | *x86 needs to handle !user_alloc case. |
0de10343 ZX |
6446 | */ |
6447 | if (!user_alloc) { | |
aab2eb7a | 6448 | if (npages && !old.npages) { |
604b38ac AA |
6449 | unsigned long userspace_addr; |
6450 | ||
6be5ceb0 | 6451 | userspace_addr = vm_mmap(NULL, 0, |
604b38ac AA |
6452 | npages * PAGE_SIZE, |
6453 | PROT_READ | PROT_WRITE, | |
7ac77099 | 6454 | map_flags, |
604b38ac | 6455 | 0); |
0de10343 | 6456 | |
604b38ac AA |
6457 | if (IS_ERR((void *)userspace_addr)) |
6458 | return PTR_ERR((void *)userspace_addr); | |
6459 | ||
604b38ac | 6460 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
6461 | } |
6462 | } | |
6463 | ||
f7784b8e MT |
6464 | |
6465 | return 0; | |
6466 | } | |
6467 | ||
6468 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
6469 | struct kvm_userspace_memory_region *mem, | |
6470 | struct kvm_memory_slot old, | |
6471 | int user_alloc) | |
6472 | { | |
6473 | ||
48c0e4e9 | 6474 | int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT; |
f7784b8e | 6475 | |
aab2eb7a | 6476 | if (!user_alloc && !old.user_alloc && old.npages && !npages) { |
f7784b8e MT |
6477 | int ret; |
6478 | ||
bfce281c | 6479 | ret = vm_munmap(old.userspace_addr, |
f7784b8e | 6480 | old.npages * PAGE_SIZE); |
f7784b8e MT |
6481 | if (ret < 0) |
6482 | printk(KERN_WARNING | |
6483 | "kvm_vm_ioctl_set_memory_region: " | |
6484 | "failed to munmap memory\n"); | |
6485 | } | |
6486 | ||
48c0e4e9 XG |
6487 | if (!kvm->arch.n_requested_mmu_pages) |
6488 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
6489 | ||
7c8a83b7 | 6490 | spin_lock(&kvm->mmu_lock); |
48c0e4e9 | 6491 | if (nr_mmu_pages) |
0de10343 | 6492 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
0de10343 | 6493 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); |
7c8a83b7 | 6494 | spin_unlock(&kvm->mmu_lock); |
3b4dc3a0 MT |
6495 | /* |
6496 | * If memory slot is created, or moved, we need to clear all | |
6497 | * mmio sptes. | |
6498 | */ | |
6499 | if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) { | |
6500 | kvm_mmu_zap_all(kvm); | |
6501 | kvm_reload_remote_mmus(kvm); | |
6502 | } | |
0de10343 | 6503 | } |
1d737c8a | 6504 | |
2df72e9b | 6505 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f MT |
6506 | { |
6507 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 6508 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
6509 | } |
6510 | ||
2df72e9b MT |
6511 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
6512 | struct kvm_memory_slot *slot) | |
6513 | { | |
6514 | kvm_arch_flush_shadow_all(kvm); | |
6515 | } | |
6516 | ||
1d737c8a ZX |
6517 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
6518 | { | |
af585b92 GN |
6519 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6520 | !vcpu->arch.apf.halted) | |
6521 | || !list_empty_careful(&vcpu->async_pf.done) | |
a1b37100 | 6522 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
7460fb4a | 6523 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
6524 | (kvm_arch_interrupt_allowed(vcpu) && |
6525 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 6526 | } |
5736199a | 6527 | |
b6d33834 | 6528 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 6529 | { |
b6d33834 | 6530 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 6531 | } |
78646121 GN |
6532 | |
6533 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
6534 | { | |
6535 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
6536 | } | |
229456fc | 6537 | |
f92653ee JK |
6538 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
6539 | { | |
6540 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
6541 | get_segment_base(vcpu, VCPU_SREG_CS); | |
6542 | ||
6543 | return current_rip == linear_rip; | |
6544 | } | |
6545 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
6546 | ||
94fe45da JK |
6547 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
6548 | { | |
6549 | unsigned long rflags; | |
6550 | ||
6551 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
6552 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 6553 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
6554 | return rflags; |
6555 | } | |
6556 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
6557 | ||
6558 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
6559 | { | |
6560 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 6561 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 6562 | rflags |= X86_EFLAGS_TF; |
94fe45da | 6563 | kvm_x86_ops->set_rflags(vcpu, rflags); |
3842d135 | 6564 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
6565 | } |
6566 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
6567 | ||
56028d08 GN |
6568 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
6569 | { | |
6570 | int r; | |
6571 | ||
fb67e14f | 6572 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
c4806acd | 6573 | is_error_page(work->page)) |
56028d08 GN |
6574 | return; |
6575 | ||
6576 | r = kvm_mmu_reload(vcpu); | |
6577 | if (unlikely(r)) | |
6578 | return; | |
6579 | ||
fb67e14f XG |
6580 | if (!vcpu->arch.mmu.direct_map && |
6581 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
6582 | return; | |
6583 | ||
56028d08 GN |
6584 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
6585 | } | |
6586 | ||
af585b92 GN |
6587 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
6588 | { | |
6589 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
6590 | } | |
6591 | ||
6592 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
6593 | { | |
6594 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
6595 | } | |
6596 | ||
6597 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6598 | { | |
6599 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6600 | ||
6601 | while (vcpu->arch.apf.gfns[key] != ~0) | |
6602 | key = kvm_async_pf_next_probe(key); | |
6603 | ||
6604 | vcpu->arch.apf.gfns[key] = gfn; | |
6605 | } | |
6606 | ||
6607 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6608 | { | |
6609 | int i; | |
6610 | u32 key = kvm_async_pf_hash_fn(gfn); | |
6611 | ||
6612 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
6613 | (vcpu->arch.apf.gfns[key] != gfn && |
6614 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
6615 | key = kvm_async_pf_next_probe(key); |
6616 | ||
6617 | return key; | |
6618 | } | |
6619 | ||
6620 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6621 | { | |
6622 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
6623 | } | |
6624 | ||
6625 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
6626 | { | |
6627 | u32 i, j, k; | |
6628 | ||
6629 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
6630 | while (true) { | |
6631 | vcpu->arch.apf.gfns[i] = ~0; | |
6632 | do { | |
6633 | j = kvm_async_pf_next_probe(j); | |
6634 | if (vcpu->arch.apf.gfns[j] == ~0) | |
6635 | return; | |
6636 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
6637 | /* | |
6638 | * k lies cyclically in ]i,j] | |
6639 | * | i.k.j | | |
6640 | * |....j i.k.| or |.k..j i...| | |
6641 | */ | |
6642 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
6643 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
6644 | i = j; | |
6645 | } | |
6646 | } | |
6647 | ||
7c90705b GN |
6648 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
6649 | { | |
6650 | ||
6651 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
6652 | sizeof(val)); | |
6653 | } | |
6654 | ||
af585b92 GN |
6655 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
6656 | struct kvm_async_pf *work) | |
6657 | { | |
6389ee94 AK |
6658 | struct x86_exception fault; |
6659 | ||
7c90705b | 6660 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 6661 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
6662 | |
6663 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
6664 | (vcpu->arch.apf.send_user_only && |
6665 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
6666 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
6667 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
6668 | fault.vector = PF_VECTOR; |
6669 | fault.error_code_valid = true; | |
6670 | fault.error_code = 0; | |
6671 | fault.nested_page_fault = false; | |
6672 | fault.address = work->arch.token; | |
6673 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6674 | } |
af585b92 GN |
6675 | } |
6676 | ||
6677 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
6678 | struct kvm_async_pf *work) | |
6679 | { | |
6389ee94 AK |
6680 | struct x86_exception fault; |
6681 | ||
7c90705b GN |
6682 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
6683 | if (is_error_page(work->page)) | |
6684 | work->arch.token = ~0; /* broadcast wakeup */ | |
6685 | else | |
6686 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
6687 | ||
6688 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
6689 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
6690 | fault.vector = PF_VECTOR; |
6691 | fault.error_code_valid = true; | |
6692 | fault.error_code = 0; | |
6693 | fault.nested_page_fault = false; | |
6694 | fault.address = work->arch.token; | |
6695 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 6696 | } |
e6d53e3b | 6697 | vcpu->arch.apf.halted = false; |
a4fa1635 | 6698 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
6699 | } |
6700 | ||
6701 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
6702 | { | |
6703 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
6704 | return true; | |
6705 | else | |
6706 | return !kvm_event_needs_reinjection(vcpu) && | |
6707 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
6708 | } |
6709 | ||
229456fc MT |
6710 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
6711 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
6712 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
6713 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
6714 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 6715 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 6716 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 6717 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 6718 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 6719 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 6720 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 6721 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |