Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
c9eab58f | 30 | #include "assigned-dev.h" |
313a3dc7 | 31 | |
18068523 | 32 | #include <linux/clocksource.h> |
4d5c5d0f | 33 | #include <linux/interrupt.h> |
313a3dc7 CO |
34 | #include <linux/kvm.h> |
35 | #include <linux/fs.h> | |
36 | #include <linux/vmalloc.h> | |
5fb76f9b | 37 | #include <linux/module.h> |
0de10343 | 38 | #include <linux/mman.h> |
2bacc55c | 39 | #include <linux/highmem.h> |
19de40a8 | 40 | #include <linux/iommu.h> |
62c476c7 | 41 | #include <linux/intel-iommu.h> |
c8076604 | 42 | #include <linux/cpufreq.h> |
18863bdd | 43 | #include <linux/user-return-notifier.h> |
a983fb23 | 44 | #include <linux/srcu.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
ff9d07a0 | 46 | #include <linux/perf_event.h> |
7bee342a | 47 | #include <linux/uaccess.h> |
af585b92 | 48 | #include <linux/hash.h> |
a1b60c1c | 49 | #include <linux/pci.h> |
16e8d74d MT |
50 | #include <linux/timekeeper_internal.h> |
51 | #include <linux/pvclock_gtod.h> | |
aec51dc4 | 52 | #include <trace/events/kvm.h> |
2ed152af | 53 | |
229456fc MT |
54 | #define CREATE_TRACE_POINTS |
55 | #include "trace.h" | |
043405e1 | 56 | |
24f1e32c | 57 | #include <asm/debugreg.h> |
d825ed0a | 58 | #include <asm/msr.h> |
a5f61300 | 59 | #include <asm/desc.h> |
0bed3b56 | 60 | #include <asm/mtrr.h> |
890ca9ae | 61 | #include <asm/mce.h> |
7cf30855 | 62 | #include <asm/i387.h> |
1361b83a | 63 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 64 | #include <asm/xcr.h> |
1d5f066e | 65 | #include <asm/pvclock.h> |
217fc9cf | 66 | #include <asm/div64.h> |
043405e1 | 67 | |
313a3dc7 | 68 | #define MAX_IO_MSRS 256 |
890ca9ae | 69 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 70 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 71 | |
0f65dd70 AK |
72 | #define emul_to_vcpu(ctxt) \ |
73 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
74 | ||
50a37eb4 JR |
75 | /* EFER defaults: |
76 | * - enable syscall per default because its emulated by KVM | |
77 | * - enable LME and LMA per default on 64 bit KVM | |
78 | */ | |
79 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
80 | static |
81 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 82 | #else |
1260edbe | 83 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 84 | #endif |
313a3dc7 | 85 | |
ba1389b7 AK |
86 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
87 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 88 | |
cb142eb7 | 89 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 90 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 91 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
674eea0f | 92 | |
97896d04 | 93 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 94 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 95 | |
476bc001 RR |
96 | static bool ignore_msrs = 0; |
97 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 98 | |
9ed96e87 MT |
99 | unsigned int min_timer_period_us = 500; |
100 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
101 | ||
92a1f12d JR |
102 | bool kvm_has_tsc_control; |
103 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
104 | u32 kvm_max_guest_tsc_khz; | |
105 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
106 | ||
cc578287 ZA |
107 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
108 | static u32 tsc_tolerance_ppm = 250; | |
109 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
110 | ||
d0659d94 MT |
111 | /* lapic timer advance (tscdeadline mode only) in nanoseconds */ |
112 | unsigned int lapic_timer_advance_ns = 0; | |
113 | module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); | |
114 | ||
16a96021 MT |
115 | static bool backwards_tsc_observed = false; |
116 | ||
18863bdd AK |
117 | #define KVM_NR_SHARED_MSRS 16 |
118 | ||
119 | struct kvm_shared_msrs_global { | |
120 | int nr; | |
2bf78fa7 | 121 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
122 | }; |
123 | ||
124 | struct kvm_shared_msrs { | |
125 | struct user_return_notifier urn; | |
126 | bool registered; | |
2bf78fa7 SY |
127 | struct kvm_shared_msr_values { |
128 | u64 host; | |
129 | u64 curr; | |
130 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
131 | }; |
132 | ||
133 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 134 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 135 | |
417bc304 | 136 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
137 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
138 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
139 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
140 | { "invlpg", VCPU_STAT(invlpg) }, | |
141 | { "exits", VCPU_STAT(exits) }, | |
142 | { "io_exits", VCPU_STAT(io_exits) }, | |
143 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
144 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
145 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 146 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 147 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 148 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
ba1389b7 | 149 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 150 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
151 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
152 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
153 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
154 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
155 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
156 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
157 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 158 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 159 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
160 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
161 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
162 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
163 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
164 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
165 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 166 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 167 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 168 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 169 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
170 | { NULL } |
171 | }; | |
172 | ||
2acf923e DC |
173 | u64 __read_mostly host_xcr0; |
174 | ||
b6785def | 175 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 176 | |
af585b92 GN |
177 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
178 | { | |
179 | int i; | |
180 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
181 | vcpu->arch.apf.gfns[i] = ~0; | |
182 | } | |
183 | ||
18863bdd AK |
184 | static void kvm_on_user_return(struct user_return_notifier *urn) |
185 | { | |
186 | unsigned slot; | |
18863bdd AK |
187 | struct kvm_shared_msrs *locals |
188 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 189 | struct kvm_shared_msr_values *values; |
18863bdd AK |
190 | |
191 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
192 | values = &locals->values[slot]; |
193 | if (values->host != values->curr) { | |
194 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
195 | values->curr = values->host; | |
18863bdd AK |
196 | } |
197 | } | |
198 | locals->registered = false; | |
199 | user_return_notifier_unregister(urn); | |
200 | } | |
201 | ||
2bf78fa7 | 202 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 203 | { |
18863bdd | 204 | u64 value; |
013f6a5d MT |
205 | unsigned int cpu = smp_processor_id(); |
206 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 207 | |
2bf78fa7 SY |
208 | /* only read, and nobody should modify it at this time, |
209 | * so don't need lock */ | |
210 | if (slot >= shared_msrs_global.nr) { | |
211 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
212 | return; | |
213 | } | |
214 | rdmsrl_safe(msr, &value); | |
215 | smsr->values[slot].host = value; | |
216 | smsr->values[slot].curr = value; | |
217 | } | |
218 | ||
219 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
220 | { | |
0123be42 | 221 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
18863bdd AK |
222 | if (slot >= shared_msrs_global.nr) |
223 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
224 | shared_msrs_global.msrs[slot] = msr; |
225 | /* we need ensured the shared_msr_global have been updated */ | |
226 | smp_wmb(); | |
18863bdd AK |
227 | } |
228 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
229 | ||
230 | static void kvm_shared_msr_cpu_online(void) | |
231 | { | |
232 | unsigned i; | |
18863bdd AK |
233 | |
234 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 235 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
236 | } |
237 | ||
8b3c3104 | 238 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 239 | { |
013f6a5d MT |
240 | unsigned int cpu = smp_processor_id(); |
241 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 242 | int err; |
18863bdd | 243 | |
2bf78fa7 | 244 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 245 | return 0; |
2bf78fa7 | 246 | smsr->values[slot].curr = value; |
8b3c3104 AH |
247 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
248 | if (err) | |
249 | return 1; | |
250 | ||
18863bdd AK |
251 | if (!smsr->registered) { |
252 | smsr->urn.on_user_return = kvm_on_user_return; | |
253 | user_return_notifier_register(&smsr->urn); | |
254 | smsr->registered = true; | |
255 | } | |
8b3c3104 | 256 | return 0; |
18863bdd AK |
257 | } |
258 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
259 | ||
13a34e06 | 260 | static void drop_user_return_notifiers(void) |
3548bab5 | 261 | { |
013f6a5d MT |
262 | unsigned int cpu = smp_processor_id(); |
263 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
264 | |
265 | if (smsr->registered) | |
266 | kvm_on_user_return(&smsr->urn); | |
267 | } | |
268 | ||
6866b83e CO |
269 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
270 | { | |
8a5a87d9 | 271 | return vcpu->arch.apic_base; |
6866b83e CO |
272 | } |
273 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
274 | ||
58cb628d JK |
275 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
276 | { | |
277 | u64 old_state = vcpu->arch.apic_base & | |
278 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
279 | u64 new_state = msr_info->data & | |
280 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
281 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | | |
282 | 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); | |
283 | ||
284 | if (!msr_info->host_initiated && | |
285 | ((msr_info->data & reserved_bits) != 0 || | |
286 | new_state == X2APIC_ENABLE || | |
287 | (new_state == MSR_IA32_APICBASE_ENABLE && | |
288 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || | |
289 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
290 | old_state == 0))) | |
291 | return 1; | |
292 | ||
293 | kvm_lapic_set_base(vcpu, msr_info->data); | |
294 | return 0; | |
6866b83e CO |
295 | } |
296 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
297 | ||
2605fc21 | 298 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
299 | { |
300 | /* Fault while not rebooting. We want the trace. */ | |
301 | BUG(); | |
302 | } | |
303 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
304 | ||
3fd28fce ED |
305 | #define EXCPT_BENIGN 0 |
306 | #define EXCPT_CONTRIBUTORY 1 | |
307 | #define EXCPT_PF 2 | |
308 | ||
309 | static int exception_class(int vector) | |
310 | { | |
311 | switch (vector) { | |
312 | case PF_VECTOR: | |
313 | return EXCPT_PF; | |
314 | case DE_VECTOR: | |
315 | case TS_VECTOR: | |
316 | case NP_VECTOR: | |
317 | case SS_VECTOR: | |
318 | case GP_VECTOR: | |
319 | return EXCPT_CONTRIBUTORY; | |
320 | default: | |
321 | break; | |
322 | } | |
323 | return EXCPT_BENIGN; | |
324 | } | |
325 | ||
d6e8c854 NA |
326 | #define EXCPT_FAULT 0 |
327 | #define EXCPT_TRAP 1 | |
328 | #define EXCPT_ABORT 2 | |
329 | #define EXCPT_INTERRUPT 3 | |
330 | ||
331 | static int exception_type(int vector) | |
332 | { | |
333 | unsigned int mask; | |
334 | ||
335 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
336 | return EXCPT_INTERRUPT; | |
337 | ||
338 | mask = 1 << vector; | |
339 | ||
340 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
341 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
342 | return EXCPT_TRAP; | |
343 | ||
344 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
345 | return EXCPT_ABORT; | |
346 | ||
347 | /* Reserved exceptions will result in fault */ | |
348 | return EXCPT_FAULT; | |
349 | } | |
350 | ||
3fd28fce | 351 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
352 | unsigned nr, bool has_error, u32 error_code, |
353 | bool reinject) | |
3fd28fce ED |
354 | { |
355 | u32 prev_nr; | |
356 | int class1, class2; | |
357 | ||
3842d135 AK |
358 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
359 | ||
3fd28fce ED |
360 | if (!vcpu->arch.exception.pending) { |
361 | queue: | |
3ffb2468 NA |
362 | if (has_error && !is_protmode(vcpu)) |
363 | has_error = false; | |
3fd28fce ED |
364 | vcpu->arch.exception.pending = true; |
365 | vcpu->arch.exception.has_error_code = has_error; | |
366 | vcpu->arch.exception.nr = nr; | |
367 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 368 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
369 | return; |
370 | } | |
371 | ||
372 | /* to check exception */ | |
373 | prev_nr = vcpu->arch.exception.nr; | |
374 | if (prev_nr == DF_VECTOR) { | |
375 | /* triple fault -> shutdown */ | |
a8eeb04a | 376 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
377 | return; |
378 | } | |
379 | class1 = exception_class(prev_nr); | |
380 | class2 = exception_class(nr); | |
381 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
382 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
383 | /* generate double fault per SDM Table 5-5 */ | |
384 | vcpu->arch.exception.pending = true; | |
385 | vcpu->arch.exception.has_error_code = true; | |
386 | vcpu->arch.exception.nr = DF_VECTOR; | |
387 | vcpu->arch.exception.error_code = 0; | |
388 | } else | |
389 | /* replace previous exception with a new one in a hope | |
390 | that instruction re-execution will regenerate lost | |
391 | exception */ | |
392 | goto queue; | |
393 | } | |
394 | ||
298101da AK |
395 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
396 | { | |
ce7ddec4 | 397 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
398 | } |
399 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
400 | ||
ce7ddec4 JR |
401 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
402 | { | |
403 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
406 | ||
db8fcefa | 407 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 408 | { |
db8fcefa AP |
409 | if (err) |
410 | kvm_inject_gp(vcpu, 0); | |
411 | else | |
412 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 415 | |
6389ee94 | 416 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
417 | { |
418 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
419 | vcpu->arch.cr2 = fault->address; |
420 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 421 | } |
27d6c865 | 422 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 423 | |
ef54bcfe | 424 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 425 | { |
6389ee94 AK |
426 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
427 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 428 | else |
6389ee94 | 429 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
430 | |
431 | return fault->nested_page_fault; | |
d4f8cf66 JR |
432 | } |
433 | ||
3419ffc8 SY |
434 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
435 | { | |
7460fb4a AK |
436 | atomic_inc(&vcpu->arch.nmi_queued); |
437 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
438 | } |
439 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
440 | ||
298101da AK |
441 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
442 | { | |
ce7ddec4 | 443 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
444 | } |
445 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
446 | ||
ce7ddec4 JR |
447 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
448 | { | |
449 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
450 | } | |
451 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
452 | ||
0a79b009 AK |
453 | /* |
454 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
455 | * a #GP and return false. | |
456 | */ | |
457 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 458 | { |
0a79b009 AK |
459 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
460 | return true; | |
461 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
462 | return false; | |
298101da | 463 | } |
0a79b009 | 464 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 465 | |
16f8a6f9 NA |
466 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
467 | { | |
468 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
469 | return true; | |
470 | ||
471 | kvm_queue_exception(vcpu, UD_VECTOR); | |
472 | return false; | |
473 | } | |
474 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
475 | ||
ec92fe44 JR |
476 | /* |
477 | * This function will be used to read from the physical memory of the currently | |
478 | * running guest. The difference to kvm_read_guest_page is that this function | |
479 | * can read from guest physical or from the guest's guest physical memory. | |
480 | */ | |
481 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
482 | gfn_t ngfn, void *data, int offset, int len, | |
483 | u32 access) | |
484 | { | |
54987b7a | 485 | struct x86_exception exception; |
ec92fe44 JR |
486 | gfn_t real_gfn; |
487 | gpa_t ngpa; | |
488 | ||
489 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 490 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
491 | if (real_gfn == UNMAPPED_GVA) |
492 | return -EFAULT; | |
493 | ||
494 | real_gfn = gpa_to_gfn(real_gfn); | |
495 | ||
496 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
497 | } | |
498 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
499 | ||
69b0049a | 500 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
501 | void *data, int offset, int len, u32 access) |
502 | { | |
503 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
504 | data, offset, len, access); | |
505 | } | |
506 | ||
a03490ed CO |
507 | /* |
508 | * Load the pae pdptrs. Return true is they are all valid. | |
509 | */ | |
ff03a073 | 510 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
511 | { |
512 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
513 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
514 | int i; | |
515 | int ret; | |
ff03a073 | 516 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 517 | |
ff03a073 JR |
518 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
519 | offset * sizeof(u64), sizeof(pdpte), | |
520 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
521 | if (ret < 0) { |
522 | ret = 0; | |
523 | goto out; | |
524 | } | |
525 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 526 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 527 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
528 | ret = 0; |
529 | goto out; | |
530 | } | |
531 | } | |
532 | ret = 1; | |
533 | ||
ff03a073 | 534 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
535 | __set_bit(VCPU_EXREG_PDPTR, |
536 | (unsigned long *)&vcpu->arch.regs_avail); | |
537 | __set_bit(VCPU_EXREG_PDPTR, | |
538 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 539 | out: |
a03490ed CO |
540 | |
541 | return ret; | |
542 | } | |
cc4b6871 | 543 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 544 | |
d835dfec AK |
545 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
546 | { | |
ff03a073 | 547 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 548 | bool changed = true; |
3d06b8bf JR |
549 | int offset; |
550 | gfn_t gfn; | |
d835dfec AK |
551 | int r; |
552 | ||
553 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
554 | return false; | |
555 | ||
6de4f3ad AK |
556 | if (!test_bit(VCPU_EXREG_PDPTR, |
557 | (unsigned long *)&vcpu->arch.regs_avail)) | |
558 | return true; | |
559 | ||
9f8fe504 AK |
560 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
561 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
562 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
563 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
564 | if (r < 0) |
565 | goto out; | |
ff03a073 | 566 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 567 | out: |
d835dfec AK |
568 | |
569 | return changed; | |
570 | } | |
571 | ||
49a9b07e | 572 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 573 | { |
aad82703 SY |
574 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
575 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
576 | X86_CR0_CD | X86_CR0_NW; | |
577 | ||
f9a48e6a AK |
578 | cr0 |= X86_CR0_ET; |
579 | ||
ab344828 | 580 | #ifdef CONFIG_X86_64 |
0f12244f GN |
581 | if (cr0 & 0xffffffff00000000UL) |
582 | return 1; | |
ab344828 GN |
583 | #endif |
584 | ||
585 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 586 | |
0f12244f GN |
587 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
588 | return 1; | |
a03490ed | 589 | |
0f12244f GN |
590 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
591 | return 1; | |
a03490ed CO |
592 | |
593 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
594 | #ifdef CONFIG_X86_64 | |
f6801dff | 595 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
596 | int cs_db, cs_l; |
597 | ||
0f12244f GN |
598 | if (!is_pae(vcpu)) |
599 | return 1; | |
a03490ed | 600 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
601 | if (cs_l) |
602 | return 1; | |
a03490ed CO |
603 | } else |
604 | #endif | |
ff03a073 | 605 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 606 | kvm_read_cr3(vcpu))) |
0f12244f | 607 | return 1; |
a03490ed CO |
608 | } |
609 | ||
ad756a16 MJ |
610 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
611 | return 1; | |
612 | ||
a03490ed | 613 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 614 | |
d170c419 | 615 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 616 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
617 | kvm_async_pf_hash_reset(vcpu); |
618 | } | |
e5f3f027 | 619 | |
aad82703 SY |
620 | if ((cr0 ^ old_cr0) & update_bits) |
621 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
622 | return 0; |
623 | } | |
2d3ad1f4 | 624 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 625 | |
2d3ad1f4 | 626 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 627 | { |
49a9b07e | 628 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 629 | } |
2d3ad1f4 | 630 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 631 | |
42bdf991 MT |
632 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
633 | { | |
634 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
635 | !vcpu->guest_xcr0_loaded) { | |
636 | /* kvm_set_xcr() also depends on this */ | |
637 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
638 | vcpu->guest_xcr0_loaded = 1; | |
639 | } | |
640 | } | |
641 | ||
642 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
643 | { | |
644 | if (vcpu->guest_xcr0_loaded) { | |
645 | if (vcpu->arch.xcr0 != host_xcr0) | |
646 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
647 | vcpu->guest_xcr0_loaded = 0; | |
648 | } | |
649 | } | |
650 | ||
69b0049a | 651 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 652 | { |
56c103ec LJ |
653 | u64 xcr0 = xcr; |
654 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 655 | u64 valid_bits; |
2acf923e DC |
656 | |
657 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
658 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
659 | return 1; | |
2acf923e DC |
660 | if (!(xcr0 & XSTATE_FP)) |
661 | return 1; | |
662 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
663 | return 1; | |
46c34cb0 PB |
664 | |
665 | /* | |
666 | * Do not allow the guest to set bits that we do not support | |
667 | * saving. However, xcr0 bit 0 is always set, even if the | |
668 | * emulated CPU does not support XSAVE (see fx_init). | |
669 | */ | |
670 | valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; | |
671 | if (xcr0 & ~valid_bits) | |
2acf923e | 672 | return 1; |
46c34cb0 | 673 | |
390bd528 LJ |
674 | if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) |
675 | return 1; | |
676 | ||
612263b3 CP |
677 | if (xcr0 & XSTATE_AVX512) { |
678 | if (!(xcr0 & XSTATE_YMM)) | |
679 | return 1; | |
680 | if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) | |
681 | return 1; | |
682 | } | |
42bdf991 | 683 | kvm_put_guest_xcr0(vcpu); |
2acf923e | 684 | vcpu->arch.xcr0 = xcr0; |
56c103ec LJ |
685 | |
686 | if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) | |
687 | kvm_update_cpuid(vcpu); | |
2acf923e DC |
688 | return 0; |
689 | } | |
690 | ||
691 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
692 | { | |
764bcbc5 Z |
693 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
694 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
695 | kvm_inject_gp(vcpu, 0); |
696 | return 1; | |
697 | } | |
698 | return 0; | |
699 | } | |
700 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
701 | ||
a83b29c6 | 702 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 703 | { |
fc78f519 | 704 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
c68b734f YW |
705 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | |
706 | X86_CR4_PAE | X86_CR4_SMEP; | |
0f12244f GN |
707 | if (cr4 & CR4_RESERVED_BITS) |
708 | return 1; | |
a03490ed | 709 | |
2acf923e DC |
710 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
711 | return 1; | |
712 | ||
c68b734f YW |
713 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
714 | return 1; | |
715 | ||
97ec8c06 FW |
716 | if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) |
717 | return 1; | |
718 | ||
afcbf13f | 719 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) |
74dc2b4f YW |
720 | return 1; |
721 | ||
a03490ed | 722 | if (is_long_mode(vcpu)) { |
0f12244f GN |
723 | if (!(cr4 & X86_CR4_PAE)) |
724 | return 1; | |
a2edf57f AK |
725 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
726 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
727 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
728 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
729 | return 1; |
730 | ||
ad756a16 MJ |
731 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
732 | if (!guest_cpuid_has_pcid(vcpu)) | |
733 | return 1; | |
734 | ||
735 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
736 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
737 | return 1; | |
738 | } | |
739 | ||
5e1746d6 | 740 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 741 | return 1; |
a03490ed | 742 | |
ad756a16 MJ |
743 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
744 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 745 | kvm_mmu_reset_context(vcpu); |
0f12244f | 746 | |
97ec8c06 FW |
747 | if ((cr4 ^ old_cr4) & X86_CR4_SMAP) |
748 | update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); | |
749 | ||
2acf923e | 750 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 751 | kvm_update_cpuid(vcpu); |
2acf923e | 752 | |
0f12244f GN |
753 | return 0; |
754 | } | |
2d3ad1f4 | 755 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 756 | |
2390218b | 757 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 758 | { |
ac146235 | 759 | #ifdef CONFIG_X86_64 |
9d88fca7 | 760 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 761 | #endif |
9d88fca7 | 762 | |
9f8fe504 | 763 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 764 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 765 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 766 | return 0; |
d835dfec AK |
767 | } |
768 | ||
a03490ed | 769 | if (is_long_mode(vcpu)) { |
d9f89b88 JK |
770 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
771 | return 1; | |
772 | } else if (is_pae(vcpu) && is_paging(vcpu) && | |
773 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 774 | return 1; |
a03490ed | 775 | |
0f12244f | 776 | vcpu->arch.cr3 = cr3; |
aff48baa | 777 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 778 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
779 | return 0; |
780 | } | |
2d3ad1f4 | 781 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 782 | |
eea1cff9 | 783 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 784 | { |
0f12244f GN |
785 | if (cr8 & CR8_RESERVED_BITS) |
786 | return 1; | |
a03490ed CO |
787 | if (irqchip_in_kernel(vcpu->kvm)) |
788 | kvm_lapic_set_tpr(vcpu, cr8); | |
789 | else | |
ad312c7c | 790 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
791 | return 0; |
792 | } | |
2d3ad1f4 | 793 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 794 | |
2d3ad1f4 | 795 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
796 | { |
797 | if (irqchip_in_kernel(vcpu->kvm)) | |
798 | return kvm_lapic_get_cr8(vcpu); | |
799 | else | |
ad312c7c | 800 | return vcpu->arch.cr8; |
a03490ed | 801 | } |
2d3ad1f4 | 802 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 803 | |
73aaf249 JK |
804 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
805 | { | |
806 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
807 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
808 | } | |
809 | ||
c8639010 JK |
810 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
811 | { | |
812 | unsigned long dr7; | |
813 | ||
814 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
815 | dr7 = vcpu->arch.guest_debug_dr7; | |
816 | else | |
817 | dr7 = vcpu->arch.dr7; | |
818 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
819 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
820 | if (dr7 & DR7_BP_EN_MASK) | |
821 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
822 | } |
823 | ||
6f43ed01 NA |
824 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
825 | { | |
826 | u64 fixed = DR6_FIXED_1; | |
827 | ||
828 | if (!guest_cpuid_has_rtm(vcpu)) | |
829 | fixed |= DR6_RTM; | |
830 | return fixed; | |
831 | } | |
832 | ||
338dbc97 | 833 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
834 | { |
835 | switch (dr) { | |
836 | case 0 ... 3: | |
837 | vcpu->arch.db[dr] = val; | |
838 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
839 | vcpu->arch.eff_db[dr] = val; | |
840 | break; | |
841 | case 4: | |
020df079 GN |
842 | /* fall through */ |
843 | case 6: | |
338dbc97 GN |
844 | if (val & 0xffffffff00000000ULL) |
845 | return -1; /* #GP */ | |
6f43ed01 | 846 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 847 | kvm_update_dr6(vcpu); |
020df079 GN |
848 | break; |
849 | case 5: | |
020df079 GN |
850 | /* fall through */ |
851 | default: /* 7 */ | |
338dbc97 GN |
852 | if (val & 0xffffffff00000000ULL) |
853 | return -1; /* #GP */ | |
020df079 | 854 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 855 | kvm_update_dr7(vcpu); |
020df079 GN |
856 | break; |
857 | } | |
858 | ||
859 | return 0; | |
860 | } | |
338dbc97 GN |
861 | |
862 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
863 | { | |
16f8a6f9 | 864 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 865 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
866 | return 1; |
867 | } | |
868 | return 0; | |
338dbc97 | 869 | } |
020df079 GN |
870 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
871 | ||
16f8a6f9 | 872 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
873 | { |
874 | switch (dr) { | |
875 | case 0 ... 3: | |
876 | *val = vcpu->arch.db[dr]; | |
877 | break; | |
878 | case 4: | |
020df079 GN |
879 | /* fall through */ |
880 | case 6: | |
73aaf249 JK |
881 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
882 | *val = vcpu->arch.dr6; | |
883 | else | |
884 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
885 | break; |
886 | case 5: | |
020df079 GN |
887 | /* fall through */ |
888 | default: /* 7 */ | |
889 | *val = vcpu->arch.dr7; | |
890 | break; | |
891 | } | |
338dbc97 GN |
892 | return 0; |
893 | } | |
020df079 GN |
894 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
895 | ||
022cd0e8 AK |
896 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
897 | { | |
898 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
899 | u64 data; | |
900 | int err; | |
901 | ||
902 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
903 | if (err) | |
904 | return err; | |
905 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
906 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
907 | return err; | |
908 | } | |
909 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
910 | ||
043405e1 CO |
911 | /* |
912 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
913 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
914 | * | |
915 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
916 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
917 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 918 | */ |
e3267cbb | 919 | |
e984097b | 920 | #define KVM_SAVE_MSRS_BEGIN 12 |
043405e1 | 921 | static u32 msrs_to_save[] = { |
e3267cbb | 922 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 923 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 924 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
e984097b | 925 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, |
c9aaa895 | 926 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
ae7a2a3f | 927 | MSR_KVM_PV_EOI_EN, |
043405e1 | 928 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 929 | MSR_STAR, |
043405e1 CO |
930 | #ifdef CONFIG_X86_64 |
931 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
932 | #endif | |
b3897a49 | 933 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
0dd376e7 | 934 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS |
043405e1 CO |
935 | }; |
936 | ||
937 | static unsigned num_msrs_to_save; | |
938 | ||
f1d24831 | 939 | static const u32 emulated_msrs[] = { |
ba904635 | 940 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 941 | MSR_IA32_TSCDEADLINE, |
043405e1 | 942 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
943 | MSR_IA32_MCG_STATUS, |
944 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
945 | }; |
946 | ||
384bb783 | 947 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 948 | { |
b69e8cae | 949 | if (efer & efer_reserved_bits) |
384bb783 | 950 | return false; |
15c4a640 | 951 | |
1b2fd70c AG |
952 | if (efer & EFER_FFXSR) { |
953 | struct kvm_cpuid_entry2 *feat; | |
954 | ||
955 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 956 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 957 | return false; |
1b2fd70c AG |
958 | } |
959 | ||
d8017474 AG |
960 | if (efer & EFER_SVME) { |
961 | struct kvm_cpuid_entry2 *feat; | |
962 | ||
963 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 964 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 965 | return false; |
d8017474 AG |
966 | } |
967 | ||
384bb783 JK |
968 | return true; |
969 | } | |
970 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
971 | ||
972 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
973 | { | |
974 | u64 old_efer = vcpu->arch.efer; | |
975 | ||
976 | if (!kvm_valid_efer(vcpu, efer)) | |
977 | return 1; | |
978 | ||
979 | if (is_paging(vcpu) | |
980 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
981 | return 1; | |
982 | ||
15c4a640 | 983 | efer &= ~EFER_LMA; |
f6801dff | 984 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 985 | |
a3d204e2 SY |
986 | kvm_x86_ops->set_efer(vcpu, efer); |
987 | ||
aad82703 SY |
988 | /* Update reserved bits */ |
989 | if ((efer ^ old_efer) & EFER_NX) | |
990 | kvm_mmu_reset_context(vcpu); | |
991 | ||
b69e8cae | 992 | return 0; |
15c4a640 CO |
993 | } |
994 | ||
f2b4b7dd JR |
995 | void kvm_enable_efer_bits(u64 mask) |
996 | { | |
997 | efer_reserved_bits &= ~mask; | |
998 | } | |
999 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1000 | ||
15c4a640 CO |
1001 | /* |
1002 | * Writes msr value into into the appropriate "register". | |
1003 | * Returns 0 on success, non-0 otherwise. | |
1004 | * Assumes vcpu_load() was already called. | |
1005 | */ | |
8fe8ab46 | 1006 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1007 | { |
854e8bb1 NA |
1008 | switch (msr->index) { |
1009 | case MSR_FS_BASE: | |
1010 | case MSR_GS_BASE: | |
1011 | case MSR_KERNEL_GS_BASE: | |
1012 | case MSR_CSTAR: | |
1013 | case MSR_LSTAR: | |
1014 | if (is_noncanonical_address(msr->data)) | |
1015 | return 1; | |
1016 | break; | |
1017 | case MSR_IA32_SYSENTER_EIP: | |
1018 | case MSR_IA32_SYSENTER_ESP: | |
1019 | /* | |
1020 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1021 | * non-canonical address is written on Intel but not on | |
1022 | * AMD (which ignores the top 32-bits, because it does | |
1023 | * not implement 64-bit SYSENTER). | |
1024 | * | |
1025 | * 64-bit code should hence be able to write a non-canonical | |
1026 | * value on AMD. Making the address canonical ensures that | |
1027 | * vmentry does not fail on Intel after writing a non-canonical | |
1028 | * value, and that something deterministic happens if the guest | |
1029 | * invokes 64-bit SYSENTER. | |
1030 | */ | |
1031 | msr->data = get_canonical(msr->data); | |
1032 | } | |
8fe8ab46 | 1033 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1034 | } |
854e8bb1 | 1035 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1036 | |
313a3dc7 CO |
1037 | /* |
1038 | * Adapt set_msr() to msr_io()'s calling convention | |
1039 | */ | |
1040 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1041 | { | |
8fe8ab46 WA |
1042 | struct msr_data msr; |
1043 | ||
1044 | msr.data = *data; | |
1045 | msr.index = index; | |
1046 | msr.host_initiated = true; | |
1047 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1048 | } |
1049 | ||
16e8d74d MT |
1050 | #ifdef CONFIG_X86_64 |
1051 | struct pvclock_gtod_data { | |
1052 | seqcount_t seq; | |
1053 | ||
1054 | struct { /* extract of a clocksource struct */ | |
1055 | int vclock_mode; | |
1056 | cycle_t cycle_last; | |
1057 | cycle_t mask; | |
1058 | u32 mult; | |
1059 | u32 shift; | |
1060 | } clock; | |
1061 | ||
cbcf2dd3 TG |
1062 | u64 boot_ns; |
1063 | u64 nsec_base; | |
16e8d74d MT |
1064 | }; |
1065 | ||
1066 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1067 | ||
1068 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1069 | { | |
1070 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1071 | u64 boot_ns; |
1072 | ||
d28ede83 | 1073 | boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot)); |
16e8d74d MT |
1074 | |
1075 | write_seqcount_begin(&vdata->seq); | |
1076 | ||
1077 | /* copy pvclock gtod data */ | |
d28ede83 TG |
1078 | vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode; |
1079 | vdata->clock.cycle_last = tk->tkr.cycle_last; | |
1080 | vdata->clock.mask = tk->tkr.mask; | |
1081 | vdata->clock.mult = tk->tkr.mult; | |
1082 | vdata->clock.shift = tk->tkr.shift; | |
16e8d74d | 1083 | |
cbcf2dd3 | 1084 | vdata->boot_ns = boot_ns; |
d28ede83 | 1085 | vdata->nsec_base = tk->tkr.xtime_nsec; |
16e8d74d MT |
1086 | |
1087 | write_seqcount_end(&vdata->seq); | |
1088 | } | |
1089 | #endif | |
1090 | ||
bab5bb39 NK |
1091 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1092 | { | |
1093 | /* | |
1094 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1095 | * vcpu_enter_guest. This function is only called from | |
1096 | * the physical CPU that is running vcpu. | |
1097 | */ | |
1098 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1099 | } | |
16e8d74d | 1100 | |
18068523 GOC |
1101 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1102 | { | |
9ed3c444 AK |
1103 | int version; |
1104 | int r; | |
50d0a0f9 | 1105 | struct pvclock_wall_clock wc; |
923de3cf | 1106 | struct timespec boot; |
18068523 GOC |
1107 | |
1108 | if (!wall_clock) | |
1109 | return; | |
1110 | ||
9ed3c444 AK |
1111 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1112 | if (r) | |
1113 | return; | |
1114 | ||
1115 | if (version & 1) | |
1116 | ++version; /* first time write, random junk */ | |
1117 | ||
1118 | ++version; | |
18068523 | 1119 | |
18068523 GOC |
1120 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
1121 | ||
50d0a0f9 GH |
1122 | /* |
1123 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1124 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1125 | * wall clock specified here. guest system time equals host |
1126 | * system time for us, thus we must fill in host boot time here. | |
1127 | */ | |
923de3cf | 1128 | getboottime(&boot); |
50d0a0f9 | 1129 | |
4b648665 BR |
1130 | if (kvm->arch.kvmclock_offset) { |
1131 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1132 | boot = timespec_sub(boot, ts); | |
1133 | } | |
50d0a0f9 GH |
1134 | wc.sec = boot.tv_sec; |
1135 | wc.nsec = boot.tv_nsec; | |
1136 | wc.version = version; | |
18068523 GOC |
1137 | |
1138 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1139 | ||
1140 | version++; | |
1141 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1142 | } |
1143 | ||
50d0a0f9 GH |
1144 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1145 | { | |
1146 | uint32_t quotient, remainder; | |
1147 | ||
1148 | /* Don't try to replace with do_div(), this one calculates | |
1149 | * "(dividend << 32) / divisor" */ | |
1150 | __asm__ ( "divl %4" | |
1151 | : "=a" (quotient), "=d" (remainder) | |
1152 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1153 | return quotient; | |
1154 | } | |
1155 | ||
5f4e3f88 ZA |
1156 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
1157 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 1158 | { |
5f4e3f88 | 1159 | uint64_t scaled64; |
50d0a0f9 GH |
1160 | int32_t shift = 0; |
1161 | uint64_t tps64; | |
1162 | uint32_t tps32; | |
1163 | ||
5f4e3f88 ZA |
1164 | tps64 = base_khz * 1000LL; |
1165 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 1166 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1167 | tps64 >>= 1; |
1168 | shift--; | |
1169 | } | |
1170 | ||
1171 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1172 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1173 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1174 | scaled64 >>= 1; |
1175 | else | |
1176 | tps32 <<= 1; | |
50d0a0f9 GH |
1177 | shift++; |
1178 | } | |
1179 | ||
5f4e3f88 ZA |
1180 | *pshift = shift; |
1181 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1182 | |
5f4e3f88 ZA |
1183 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
1184 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
1185 | } |
1186 | ||
759379dd ZA |
1187 | static inline u64 get_kernel_ns(void) |
1188 | { | |
bb0b5812 | 1189 | return ktime_get_boot_ns(); |
50d0a0f9 GH |
1190 | } |
1191 | ||
d828199e | 1192 | #ifdef CONFIG_X86_64 |
16e8d74d | 1193 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1194 | #endif |
16e8d74d | 1195 | |
c8076604 | 1196 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1197 | static unsigned long max_tsc_khz; |
c8076604 | 1198 | |
cc578287 | 1199 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1200 | { |
cc578287 ZA |
1201 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1202 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1203 | } |
1204 | ||
cc578287 | 1205 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1206 | { |
cc578287 ZA |
1207 | u64 v = (u64)khz * (1000000 + ppm); |
1208 | do_div(v, 1000000); | |
1209 | return v; | |
1e993611 JR |
1210 | } |
1211 | ||
cc578287 | 1212 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 1213 | { |
cc578287 ZA |
1214 | u32 thresh_lo, thresh_hi; |
1215 | int use_scaling = 0; | |
217fc9cf | 1216 | |
03ba32ca MT |
1217 | /* tsc_khz can be zero if TSC calibration fails */ |
1218 | if (this_tsc_khz == 0) | |
1219 | return; | |
1220 | ||
c285545f ZA |
1221 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1222 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1223 | &vcpu->arch.virtual_tsc_shift, |
1224 | &vcpu->arch.virtual_tsc_mult); | |
1225 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1226 | ||
1227 | /* | |
1228 | * Compute the variation in TSC rate which is acceptable | |
1229 | * within the range of tolerance and decide if the | |
1230 | * rate being applied is within that bounds of the hardware | |
1231 | * rate. If so, no scaling or compensation need be done. | |
1232 | */ | |
1233 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1234 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1235 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1236 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1237 | use_scaling = 1; | |
1238 | } | |
1239 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1240 | } |
1241 | ||
1242 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1243 | { | |
e26101b1 | 1244 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1245 | vcpu->arch.virtual_tsc_mult, |
1246 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1247 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1248 | return tsc; |
1249 | } | |
1250 | ||
69b0049a | 1251 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1252 | { |
1253 | #ifdef CONFIG_X86_64 | |
1254 | bool vcpus_matched; | |
b48aa97e MT |
1255 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1256 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1257 | ||
1258 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1259 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1260 | ||
7f187922 MT |
1261 | /* |
1262 | * Once the masterclock is enabled, always perform request in | |
1263 | * order to update it. | |
1264 | * | |
1265 | * In order to enable masterclock, the host clocksource must be TSC | |
1266 | * and the vcpus need to have matched TSCs. When that happens, | |
1267 | * perform request to enable masterclock. | |
1268 | */ | |
1269 | if (ka->use_master_clock || | |
1270 | (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) | |
b48aa97e MT |
1271 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1272 | ||
1273 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1274 | atomic_read(&vcpu->kvm->online_vcpus), | |
1275 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1276 | #endif | |
1277 | } | |
1278 | ||
ba904635 WA |
1279 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1280 | { | |
1281 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1282 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1283 | } | |
1284 | ||
8fe8ab46 | 1285 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1286 | { |
1287 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1288 | u64 offset, ns, elapsed; |
99e3e30a | 1289 | unsigned long flags; |
02626b6a | 1290 | s64 usdiff; |
b48aa97e | 1291 | bool matched; |
0d3da0d2 | 1292 | bool already_matched; |
8fe8ab46 | 1293 | u64 data = msr->data; |
99e3e30a | 1294 | |
038f8c11 | 1295 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1296 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1297 | ns = get_kernel_ns(); |
f38e098f | 1298 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1299 | |
03ba32ca | 1300 | if (vcpu->arch.virtual_tsc_khz) { |
8915aa27 MT |
1301 | int faulted = 0; |
1302 | ||
03ba32ca MT |
1303 | /* n.b - signed multiplication and division required */ |
1304 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1305 | #ifdef CONFIG_X86_64 |
03ba32ca | 1306 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1307 | #else |
03ba32ca | 1308 | /* do_div() only does unsigned */ |
8915aa27 MT |
1309 | asm("1: idivl %[divisor]\n" |
1310 | "2: xor %%edx, %%edx\n" | |
1311 | " movl $0, %[faulted]\n" | |
1312 | "3:\n" | |
1313 | ".section .fixup,\"ax\"\n" | |
1314 | "4: movl $1, %[faulted]\n" | |
1315 | " jmp 3b\n" | |
1316 | ".previous\n" | |
1317 | ||
1318 | _ASM_EXTABLE(1b, 4b) | |
1319 | ||
1320 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1321 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1322 | ||
5d3cb0f6 | 1323 | #endif |
03ba32ca MT |
1324 | do_div(elapsed, 1000); |
1325 | usdiff -= elapsed; | |
1326 | if (usdiff < 0) | |
1327 | usdiff = -usdiff; | |
8915aa27 MT |
1328 | |
1329 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1330 | if (faulted) | |
1331 | usdiff = USEC_PER_SEC; | |
03ba32ca MT |
1332 | } else |
1333 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1334 | |
1335 | /* | |
5d3cb0f6 ZA |
1336 | * Special case: TSC write with a small delta (1 second) of virtual |
1337 | * cycle time against real time is interpreted as an attempt to | |
1338 | * synchronize the CPU. | |
1339 | * | |
1340 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1341 | * TSC, we add elapsed time in this computation. We could let the | |
1342 | * compensation code attempt to catch up if we fall behind, but | |
1343 | * it's better to try to match offsets from the beginning. | |
1344 | */ | |
02626b6a | 1345 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1346 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1347 | if (!check_tsc_unstable()) { |
e26101b1 | 1348 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1349 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1350 | } else { | |
857e4099 | 1351 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1352 | data += delta; |
1353 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1354 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1355 | } |
b48aa97e | 1356 | matched = true; |
0d3da0d2 | 1357 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1358 | } else { |
1359 | /* | |
1360 | * We split periods of matched TSC writes into generations. | |
1361 | * For each generation, we track the original measured | |
1362 | * nanosecond time, offset, and write, so if TSCs are in | |
1363 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1364 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1365 | * |
1366 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1367 | */ | |
1368 | kvm->arch.cur_tsc_generation++; | |
1369 | kvm->arch.cur_tsc_nsec = ns; | |
1370 | kvm->arch.cur_tsc_write = data; | |
1371 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1372 | matched = false; |
0d3da0d2 | 1373 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1374 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1375 | } |
e26101b1 ZA |
1376 | |
1377 | /* | |
1378 | * We also track th most recent recorded KHZ, write and time to | |
1379 | * allow the matching interval to be extended at each write. | |
1380 | */ | |
f38e098f ZA |
1381 | kvm->arch.last_tsc_nsec = ns; |
1382 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1383 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1384 | |
b183aa58 | 1385 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1386 | |
1387 | /* Keep track of which generation this VCPU has synchronized to */ | |
1388 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1389 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1390 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1391 | ||
ba904635 WA |
1392 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1393 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1394 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1395 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1396 | |
1397 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1398 | if (!matched) { |
b48aa97e | 1399 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1400 | } else if (!already_matched) { |
1401 | kvm->arch.nr_vcpus_matched_tsc++; | |
1402 | } | |
b48aa97e MT |
1403 | |
1404 | kvm_track_tsc_matching(vcpu); | |
1405 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1406 | } |
e26101b1 | 1407 | |
99e3e30a ZA |
1408 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1409 | ||
d828199e MT |
1410 | #ifdef CONFIG_X86_64 |
1411 | ||
1412 | static cycle_t read_tsc(void) | |
1413 | { | |
1414 | cycle_t ret; | |
1415 | u64 last; | |
1416 | ||
1417 | /* | |
1418 | * Empirically, a fence (of type that depends on the CPU) | |
1419 | * before rdtsc is enough to ensure that rdtsc is ordered | |
1420 | * with respect to loads. The various CPU manuals are unclear | |
1421 | * as to whether rdtsc can be reordered with later loads, | |
1422 | * but no one has ever seen it happen. | |
1423 | */ | |
1424 | rdtsc_barrier(); | |
1425 | ret = (cycle_t)vget_cycles(); | |
1426 | ||
1427 | last = pvclock_gtod_data.clock.cycle_last; | |
1428 | ||
1429 | if (likely(ret >= last)) | |
1430 | return ret; | |
1431 | ||
1432 | /* | |
1433 | * GCC likes to generate cmov here, but this branch is extremely | |
1434 | * predictable (it's just a funciton of time and the likely is | |
1435 | * very likely) and there's a data dependence, so force GCC | |
1436 | * to generate a branch instead. I don't barrier() because | |
1437 | * we don't actually need a barrier, and if this function | |
1438 | * ever gets inlined it will generate worse code. | |
1439 | */ | |
1440 | asm volatile (""); | |
1441 | return last; | |
1442 | } | |
1443 | ||
1444 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1445 | { | |
1446 | long v; | |
1447 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1448 | ||
1449 | *cycle_now = read_tsc(); | |
1450 | ||
1451 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1452 | return v * gtod->clock.mult; | |
1453 | } | |
1454 | ||
cbcf2dd3 | 1455 | static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) |
d828199e | 1456 | { |
cbcf2dd3 | 1457 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1458 | unsigned long seq; |
d828199e | 1459 | int mode; |
cbcf2dd3 | 1460 | u64 ns; |
d828199e | 1461 | |
d828199e MT |
1462 | do { |
1463 | seq = read_seqcount_begin(>od->seq); | |
1464 | mode = gtod->clock.vclock_mode; | |
cbcf2dd3 | 1465 | ns = gtod->nsec_base; |
d828199e MT |
1466 | ns += vgettsc(cycle_now); |
1467 | ns >>= gtod->clock.shift; | |
cbcf2dd3 | 1468 | ns += gtod->boot_ns; |
d828199e | 1469 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1470 | *t = ns; |
d828199e MT |
1471 | |
1472 | return mode; | |
1473 | } | |
1474 | ||
1475 | /* returns true if host is using tsc clocksource */ | |
1476 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1477 | { | |
d828199e MT |
1478 | /* checked again under seqlock below */ |
1479 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1480 | return false; | |
1481 | ||
cbcf2dd3 | 1482 | return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; |
d828199e MT |
1483 | } |
1484 | #endif | |
1485 | ||
1486 | /* | |
1487 | * | |
b48aa97e MT |
1488 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1489 | * across virtual CPUs, the following condition is possible. | |
1490 | * Each numbered line represents an event visible to both | |
d828199e MT |
1491 | * CPUs at the next numbered event. |
1492 | * | |
1493 | * "timespecX" represents host monotonic time. "tscX" represents | |
1494 | * RDTSC value. | |
1495 | * | |
1496 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1497 | * | |
1498 | * 1. read timespec0,tsc0 | |
1499 | * 2. | timespec1 = timespec0 + N | |
1500 | * | tsc1 = tsc0 + M | |
1501 | * 3. transition to guest | transition to guest | |
1502 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1503 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1504 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1505 | * | |
1506 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1507 | * | |
1508 | * - ret0 < ret1 | |
1509 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1510 | * ... | |
1511 | * - 0 < N - M => M < N | |
1512 | * | |
1513 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1514 | * always the case (the difference between two distinct xtime instances | |
1515 | * might be smaller then the difference between corresponding TSC reads, | |
1516 | * when updating guest vcpus pvclock areas). | |
1517 | * | |
1518 | * To avoid that problem, do not allow visibility of distinct | |
1519 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1520 | * copy of host monotonic time values. Update that master copy | |
1521 | * in lockstep. | |
1522 | * | |
b48aa97e | 1523 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1524 | * |
1525 | */ | |
1526 | ||
1527 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1528 | { | |
1529 | #ifdef CONFIG_X86_64 | |
1530 | struct kvm_arch *ka = &kvm->arch; | |
1531 | int vclock_mode; | |
b48aa97e MT |
1532 | bool host_tsc_clocksource, vcpus_matched; |
1533 | ||
1534 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1535 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1536 | |
1537 | /* | |
1538 | * If the host uses TSC clock, then passthrough TSC as stable | |
1539 | * to the guest. | |
1540 | */ | |
b48aa97e | 1541 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1542 | &ka->master_kernel_ns, |
1543 | &ka->master_cycle_now); | |
1544 | ||
16a96021 | 1545 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
54750f2c MT |
1546 | && !backwards_tsc_observed |
1547 | && !ka->boot_vcpu_runs_old_kvmclock; | |
b48aa97e | 1548 | |
d828199e MT |
1549 | if (ka->use_master_clock) |
1550 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1551 | ||
1552 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1553 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1554 | vcpus_matched); | |
d828199e MT |
1555 | #endif |
1556 | } | |
1557 | ||
2e762ff7 MT |
1558 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1559 | { | |
1560 | #ifdef CONFIG_X86_64 | |
1561 | int i; | |
1562 | struct kvm_vcpu *vcpu; | |
1563 | struct kvm_arch *ka = &kvm->arch; | |
1564 | ||
1565 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1566 | kvm_make_mclock_inprogress_request(kvm); | |
1567 | /* no guest entries from this point */ | |
1568 | pvclock_update_vm_gtod_copy(kvm); | |
1569 | ||
1570 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1571 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1572 | |
1573 | /* guest entries allowed */ | |
1574 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1575 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1576 | ||
1577 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1578 | #endif | |
1579 | } | |
1580 | ||
34c238a1 | 1581 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1582 | { |
d828199e | 1583 | unsigned long flags, this_tsc_khz; |
18068523 | 1584 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1585 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1586 | s64 kernel_ns; |
d828199e | 1587 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1588 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1589 | u8 pvclock_flags; |
d828199e MT |
1590 | bool use_master_clock; |
1591 | ||
1592 | kernel_ns = 0; | |
1593 | host_tsc = 0; | |
18068523 | 1594 | |
d828199e MT |
1595 | /* |
1596 | * If the host uses TSC clock, then passthrough TSC as stable | |
1597 | * to the guest. | |
1598 | */ | |
1599 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1600 | use_master_clock = ka->use_master_clock; | |
1601 | if (use_master_clock) { | |
1602 | host_tsc = ka->master_cycle_now; | |
1603 | kernel_ns = ka->master_kernel_ns; | |
1604 | } | |
1605 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1606 | |
1607 | /* Keep irq disabled to prevent changes to the clock */ | |
1608 | local_irq_save(flags); | |
89cbc767 | 1609 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
c09664bb MT |
1610 | if (unlikely(this_tsc_khz == 0)) { |
1611 | local_irq_restore(flags); | |
1612 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1613 | return 1; | |
1614 | } | |
d828199e MT |
1615 | if (!use_master_clock) { |
1616 | host_tsc = native_read_tsc(); | |
1617 | kernel_ns = get_kernel_ns(); | |
1618 | } | |
1619 | ||
1620 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); | |
1621 | ||
c285545f ZA |
1622 | /* |
1623 | * We may have to catch up the TSC to match elapsed wall clock | |
1624 | * time for two reasons, even if kvmclock is used. | |
1625 | * 1) CPU could have been running below the maximum TSC rate | |
1626 | * 2) Broken TSC compensation resets the base at each VCPU | |
1627 | * entry to avoid unknown leaps of TSC even when running | |
1628 | * again on the same CPU. This may cause apparent elapsed | |
1629 | * time to disappear, and the guest to stand still or run | |
1630 | * very slowly. | |
1631 | */ | |
1632 | if (vcpu->tsc_catchup) { | |
1633 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1634 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1635 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1636 | tsc_timestamp = tsc; |
1637 | } | |
50d0a0f9 GH |
1638 | } |
1639 | ||
18068523 GOC |
1640 | local_irq_restore(flags); |
1641 | ||
0b79459b | 1642 | if (!vcpu->pv_time_enabled) |
c285545f | 1643 | return 0; |
18068523 | 1644 | |
e48672fa | 1645 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1646 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1647 | &vcpu->hv_clock.tsc_shift, | |
1648 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1649 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1650 | } |
1651 | ||
1652 | /* With all the info we got, fill in the values */ | |
1d5f066e | 1653 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1654 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 1655 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1656 | |
09a0c3f1 OH |
1657 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1658 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1659 | return 0; | |
1660 | ||
18068523 GOC |
1661 | /* |
1662 | * The interface expects us to write an even number signaling that the | |
1663 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1664 | * state, we just increase by 2 at the end. |
18068523 | 1665 | */ |
09a0c3f1 | 1666 | vcpu->hv_clock.version = guest_hv_clock.version + 2; |
78c0337a MT |
1667 | |
1668 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1669 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1670 | |
1671 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1672 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1673 | vcpu->pvclock_set_guest_stopped_request = false; | |
1674 | } | |
1675 | ||
d828199e MT |
1676 | /* If the host uses TSC clocksource, then it is stable */ |
1677 | if (use_master_clock) | |
1678 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1679 | ||
78c0337a MT |
1680 | vcpu->hv_clock.flags = pvclock_flags; |
1681 | ||
ce1a5e60 DM |
1682 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
1683 | ||
0b79459b AH |
1684 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1685 | &vcpu->hv_clock, | |
1686 | sizeof(vcpu->hv_clock)); | |
8cfdc000 | 1687 | return 0; |
c8076604 GH |
1688 | } |
1689 | ||
0061d53d MT |
1690 | /* |
1691 | * kvmclock updates which are isolated to a given vcpu, such as | |
1692 | * vcpu->cpu migration, should not allow system_timestamp from | |
1693 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1694 | * correction applies to one vcpu's system_timestamp but not | |
1695 | * the others. | |
1696 | * | |
1697 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
1698 | * We need to rate-limit these requests though, as they can |
1699 | * considerably slow guests that have a large number of vcpus. | |
1700 | * The time for a remote vcpu to update its kvmclock is bound | |
1701 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
1702 | */ |
1703 | ||
7e44e449 AJ |
1704 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
1705 | ||
1706 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
1707 | { |
1708 | int i; | |
7e44e449 AJ |
1709 | struct delayed_work *dwork = to_delayed_work(work); |
1710 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1711 | kvmclock_update_work); | |
1712 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
1713 | struct kvm_vcpu *vcpu; |
1714 | ||
1715 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 1716 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
1717 | kvm_vcpu_kick(vcpu); |
1718 | } | |
1719 | } | |
1720 | ||
7e44e449 AJ |
1721 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
1722 | { | |
1723 | struct kvm *kvm = v->kvm; | |
1724 | ||
105b21bb | 1725 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
1726 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
1727 | KVMCLOCK_UPDATE_DELAY); | |
1728 | } | |
1729 | ||
332967a3 AJ |
1730 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
1731 | ||
1732 | static void kvmclock_sync_fn(struct work_struct *work) | |
1733 | { | |
1734 | struct delayed_work *dwork = to_delayed_work(work); | |
1735 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1736 | kvmclock_sync_work); | |
1737 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1738 | ||
1739 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); | |
1740 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
1741 | KVMCLOCK_SYNC_PERIOD); | |
1742 | } | |
1743 | ||
9ba075a6 AK |
1744 | static bool msr_mtrr_valid(unsigned msr) |
1745 | { | |
1746 | switch (msr) { | |
1747 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1748 | case MSR_MTRRfix64K_00000: | |
1749 | case MSR_MTRRfix16K_80000: | |
1750 | case MSR_MTRRfix16K_A0000: | |
1751 | case MSR_MTRRfix4K_C0000: | |
1752 | case MSR_MTRRfix4K_C8000: | |
1753 | case MSR_MTRRfix4K_D0000: | |
1754 | case MSR_MTRRfix4K_D8000: | |
1755 | case MSR_MTRRfix4K_E0000: | |
1756 | case MSR_MTRRfix4K_E8000: | |
1757 | case MSR_MTRRfix4K_F0000: | |
1758 | case MSR_MTRRfix4K_F8000: | |
1759 | case MSR_MTRRdefType: | |
1760 | case MSR_IA32_CR_PAT: | |
1761 | return true; | |
1762 | case 0x2f8: | |
1763 | return true; | |
1764 | } | |
1765 | return false; | |
1766 | } | |
1767 | ||
d6289b93 MT |
1768 | static bool valid_pat_type(unsigned t) |
1769 | { | |
1770 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1771 | } | |
1772 | ||
1773 | static bool valid_mtrr_type(unsigned t) | |
1774 | { | |
1775 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1776 | } | |
1777 | ||
4566654b | 1778 | bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
d6289b93 MT |
1779 | { |
1780 | int i; | |
fd275235 | 1781 | u64 mask; |
d6289b93 MT |
1782 | |
1783 | if (!msr_mtrr_valid(msr)) | |
1784 | return false; | |
1785 | ||
1786 | if (msr == MSR_IA32_CR_PAT) { | |
1787 | for (i = 0; i < 8; i++) | |
1788 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1789 | return false; | |
1790 | return true; | |
1791 | } else if (msr == MSR_MTRRdefType) { | |
1792 | if (data & ~0xcff) | |
1793 | return false; | |
1794 | return valid_mtrr_type(data & 0xff); | |
1795 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1796 | for (i = 0; i < 8 ; i++) | |
1797 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1798 | return false; | |
1799 | return true; | |
1800 | } | |
1801 | ||
1802 | /* variable MTRRs */ | |
adfb5d27 WL |
1803 | WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); |
1804 | ||
fd275235 | 1805 | mask = (~0ULL) << cpuid_maxphyaddr(vcpu); |
d7a2a246 | 1806 | if ((msr & 1) == 0) { |
adfb5d27 | 1807 | /* MTRR base */ |
d7a2a246 WL |
1808 | if (!valid_mtrr_type(data & 0xff)) |
1809 | return false; | |
1810 | mask |= 0xf00; | |
1811 | } else | |
1812 | /* MTRR mask */ | |
1813 | mask |= 0x7ff; | |
1814 | if (data & mask) { | |
1815 | kvm_inject_gp(vcpu, 0); | |
1816 | return false; | |
1817 | } | |
1818 | ||
adfb5d27 | 1819 | return true; |
d6289b93 | 1820 | } |
4566654b | 1821 | EXPORT_SYMBOL_GPL(kvm_mtrr_valid); |
d6289b93 | 1822 | |
9ba075a6 AK |
1823 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1824 | { | |
0bed3b56 SY |
1825 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1826 | ||
4566654b | 1827 | if (!kvm_mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1828 | return 1; |
1829 | ||
0bed3b56 SY |
1830 | if (msr == MSR_MTRRdefType) { |
1831 | vcpu->arch.mtrr_state.def_type = data; | |
1832 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1833 | } else if (msr == MSR_MTRRfix64K_00000) | |
1834 | p[0] = data; | |
1835 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1836 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1837 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1838 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1839 | else if (msr == MSR_IA32_CR_PAT) | |
1840 | vcpu->arch.pat = data; | |
1841 | else { /* Variable MTRRs */ | |
1842 | int idx, is_mtrr_mask; | |
1843 | u64 *pt; | |
1844 | ||
1845 | idx = (msr - 0x200) / 2; | |
1846 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1847 | if (!is_mtrr_mask) | |
1848 | pt = | |
1849 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1850 | else | |
1851 | pt = | |
1852 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1853 | *pt = data; | |
1854 | } | |
1855 | ||
1856 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1857 | return 0; |
1858 | } | |
15c4a640 | 1859 | |
890ca9ae | 1860 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1861 | { |
890ca9ae HY |
1862 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1863 | unsigned bank_num = mcg_cap & 0xff; | |
1864 | ||
15c4a640 | 1865 | switch (msr) { |
15c4a640 | 1866 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1867 | vcpu->arch.mcg_status = data; |
15c4a640 | 1868 | break; |
c7ac679c | 1869 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1870 | if (!(mcg_cap & MCG_CTL_P)) |
1871 | return 1; | |
1872 | if (data != 0 && data != ~(u64)0) | |
1873 | return -1; | |
1874 | vcpu->arch.mcg_ctl = data; | |
1875 | break; | |
1876 | default: | |
1877 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 1878 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 1879 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
1880 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1881 | * some Linux kernels though clear bit 10 in bank 4 to | |
1882 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1883 | * this to avoid an uncatched #GP in the guest | |
1884 | */ | |
890ca9ae | 1885 | if ((offset & 0x3) == 0 && |
114be429 | 1886 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1887 | return -1; |
1888 | vcpu->arch.mce_banks[offset] = data; | |
1889 | break; | |
1890 | } | |
1891 | return 1; | |
1892 | } | |
1893 | return 0; | |
1894 | } | |
1895 | ||
ffde22ac ES |
1896 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1897 | { | |
1898 | struct kvm *kvm = vcpu->kvm; | |
1899 | int lm = is_long_mode(vcpu); | |
1900 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1901 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1902 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1903 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1904 | u32 page_num = data & ~PAGE_MASK; | |
1905 | u64 page_addr = data & PAGE_MASK; | |
1906 | u8 *page; | |
1907 | int r; | |
1908 | ||
1909 | r = -E2BIG; | |
1910 | if (page_num >= blob_size) | |
1911 | goto out; | |
1912 | r = -ENOMEM; | |
ff5c2c03 SL |
1913 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1914 | if (IS_ERR(page)) { | |
1915 | r = PTR_ERR(page); | |
ffde22ac | 1916 | goto out; |
ff5c2c03 | 1917 | } |
ffde22ac ES |
1918 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) |
1919 | goto out_free; | |
1920 | r = 0; | |
1921 | out_free: | |
1922 | kfree(page); | |
1923 | out: | |
1924 | return r; | |
1925 | } | |
1926 | ||
55cd8e5a GN |
1927 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1928 | { | |
1929 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1930 | } | |
1931 | ||
1932 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1933 | { | |
1934 | bool r = false; | |
1935 | switch (msr) { | |
1936 | case HV_X64_MSR_GUEST_OS_ID: | |
1937 | case HV_X64_MSR_HYPERCALL: | |
e984097b VR |
1938 | case HV_X64_MSR_REFERENCE_TSC: |
1939 | case HV_X64_MSR_TIME_REF_COUNT: | |
55cd8e5a GN |
1940 | r = true; |
1941 | break; | |
1942 | } | |
1943 | ||
1944 | return r; | |
1945 | } | |
1946 | ||
1947 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1948 | { | |
1949 | struct kvm *kvm = vcpu->kvm; | |
1950 | ||
1951 | switch (msr) { | |
1952 | case HV_X64_MSR_GUEST_OS_ID: | |
1953 | kvm->arch.hv_guest_os_id = data; | |
1954 | /* setting guest os id to zero disables hypercall page */ | |
1955 | if (!kvm->arch.hv_guest_os_id) | |
1956 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1957 | break; | |
1958 | case HV_X64_MSR_HYPERCALL: { | |
1959 | u64 gfn; | |
1960 | unsigned long addr; | |
1961 | u8 instructions[4]; | |
1962 | ||
1963 | /* if guest os id is not set hypercall should remain disabled */ | |
1964 | if (!kvm->arch.hv_guest_os_id) | |
1965 | break; | |
1966 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1967 | kvm->arch.hv_hypercall = data; | |
1968 | break; | |
1969 | } | |
1970 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1971 | addr = gfn_to_hva(kvm, gfn); | |
1972 | if (kvm_is_error_hva(addr)) | |
1973 | return 1; | |
1974 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1975 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 1976 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
1977 | return 1; |
1978 | kvm->arch.hv_hypercall = data; | |
b94b64c9 | 1979 | mark_page_dirty(kvm, gfn); |
55cd8e5a GN |
1980 | break; |
1981 | } | |
e984097b VR |
1982 | case HV_X64_MSR_REFERENCE_TSC: { |
1983 | u64 gfn; | |
1984 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
1985 | memset(&tsc_ref, 0, sizeof(tsc_ref)); | |
1986 | kvm->arch.hv_tsc_page = data; | |
1987 | if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) | |
1988 | break; | |
1989 | gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; | |
e1fa108d | 1990 | if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, |
e984097b VR |
1991 | &tsc_ref, sizeof(tsc_ref))) |
1992 | return 1; | |
1993 | mark_page_dirty(kvm, gfn); | |
1994 | break; | |
1995 | } | |
55cd8e5a | 1996 | default: |
a737f256 CD |
1997 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1998 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
1999 | return 1; |
2000 | } | |
2001 | return 0; | |
2002 | } | |
2003 | ||
2004 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2005 | { | |
10388a07 GN |
2006 | switch (msr) { |
2007 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
b3af1e88 | 2008 | u64 gfn; |
10388a07 | 2009 | unsigned long addr; |
55cd8e5a | 2010 | |
10388a07 GN |
2011 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
2012 | vcpu->arch.hv_vapic = data; | |
b63cf42f MT |
2013 | if (kvm_lapic_enable_pv_eoi(vcpu, 0)) |
2014 | return 1; | |
10388a07 GN |
2015 | break; |
2016 | } | |
b3af1e88 VR |
2017 | gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; |
2018 | addr = gfn_to_hva(vcpu->kvm, gfn); | |
10388a07 GN |
2019 | if (kvm_is_error_hva(addr)) |
2020 | return 1; | |
8b0cedff | 2021 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
2022 | return 1; |
2023 | vcpu->arch.hv_vapic = data; | |
b3af1e88 | 2024 | mark_page_dirty(vcpu->kvm, gfn); |
b63cf42f MT |
2025 | if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) |
2026 | return 1; | |
10388a07 GN |
2027 | break; |
2028 | } | |
2029 | case HV_X64_MSR_EOI: | |
2030 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
2031 | case HV_X64_MSR_ICR: | |
2032 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
2033 | case HV_X64_MSR_TPR: | |
2034 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
2035 | default: | |
a737f256 CD |
2036 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
2037 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
2038 | return 1; |
2039 | } | |
2040 | ||
2041 | return 0; | |
55cd8e5a GN |
2042 | } |
2043 | ||
344d9588 GN |
2044 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2045 | { | |
2046 | gpa_t gpa = data & ~0x3f; | |
2047 | ||
4a969980 | 2048 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 2049 | if (data & 0x3c) |
344d9588 GN |
2050 | return 1; |
2051 | ||
2052 | vcpu->arch.apf.msr_val = data; | |
2053 | ||
2054 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2055 | kvm_clear_async_pf_completion_queue(vcpu); | |
2056 | kvm_async_pf_hash_reset(vcpu); | |
2057 | return 0; | |
2058 | } | |
2059 | ||
8f964525 AH |
2060 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
2061 | sizeof(u32))) | |
344d9588 GN |
2062 | return 1; |
2063 | ||
6adba527 | 2064 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
2065 | kvm_async_pf_wakeup_all(vcpu); |
2066 | return 0; | |
2067 | } | |
2068 | ||
12f9a48f GC |
2069 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2070 | { | |
0b79459b | 2071 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2072 | } |
2073 | ||
c9aaa895 GC |
2074 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
2075 | { | |
2076 | u64 delta; | |
2077 | ||
2078 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2079 | return; | |
2080 | ||
2081 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
2082 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2083 | vcpu->arch.st.accum_steal = delta; | |
2084 | } | |
2085 | ||
2086 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
2087 | { | |
2088 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2089 | return; | |
2090 | ||
2091 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2092 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
2093 | return; | |
2094 | ||
2095 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
2096 | vcpu->arch.st.steal.version += 2; | |
2097 | vcpu->arch.st.accum_steal = 0; | |
2098 | ||
2099 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2100 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2101 | } | |
2102 | ||
8fe8ab46 | 2103 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2104 | { |
5753785f | 2105 | bool pr = false; |
8fe8ab46 WA |
2106 | u32 msr = msr_info->index; |
2107 | u64 data = msr_info->data; | |
5753785f | 2108 | |
15c4a640 | 2109 | switch (msr) { |
2e32b719 BP |
2110 | case MSR_AMD64_NB_CFG: |
2111 | case MSR_IA32_UCODE_REV: | |
2112 | case MSR_IA32_UCODE_WRITE: | |
2113 | case MSR_VM_HSAVE_PA: | |
2114 | case MSR_AMD64_PATCH_LOADER: | |
2115 | case MSR_AMD64_BU_CFG2: | |
2116 | break; | |
2117 | ||
15c4a640 | 2118 | case MSR_EFER: |
b69e8cae | 2119 | return set_efer(vcpu, data); |
8f1589d9 AP |
2120 | case MSR_K7_HWCR: |
2121 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2122 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2123 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2124 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2125 | if (data != 0) { |
a737f256 CD |
2126 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2127 | data); | |
8f1589d9 AP |
2128 | return 1; |
2129 | } | |
15c4a640 | 2130 | break; |
f7c6d140 AP |
2131 | case MSR_FAM10H_MMIO_CONF_BASE: |
2132 | if (data != 0) { | |
a737f256 CD |
2133 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2134 | "0x%llx\n", data); | |
f7c6d140 AP |
2135 | return 1; |
2136 | } | |
15c4a640 | 2137 | break; |
b5e2fec0 AG |
2138 | case MSR_IA32_DEBUGCTLMSR: |
2139 | if (!data) { | |
2140 | /* We support the non-activated case already */ | |
2141 | break; | |
2142 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2143 | /* Values other than LBR and BTF are vendor-specific, | |
2144 | thus reserved and should throw a #GP */ | |
2145 | return 1; | |
2146 | } | |
a737f256 CD |
2147 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2148 | __func__, data); | |
b5e2fec0 | 2149 | break; |
9ba075a6 AK |
2150 | case 0x200 ... 0x2ff: |
2151 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 | 2152 | case MSR_IA32_APICBASE: |
58cb628d | 2153 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2154 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2155 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2156 | case MSR_IA32_TSCDEADLINE: |
2157 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2158 | break; | |
ba904635 WA |
2159 | case MSR_IA32_TSC_ADJUST: |
2160 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2161 | if (!msr_info->host_initiated) { | |
d913b904 | 2162 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 WA |
2163 | kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); |
2164 | } | |
2165 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2166 | } | |
2167 | break; | |
15c4a640 | 2168 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2169 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2170 | break; |
11c6bffa | 2171 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2172 | case MSR_KVM_WALL_CLOCK: |
2173 | vcpu->kvm->arch.wall_clock = data; | |
2174 | kvm_write_wall_clock(vcpu->kvm, data); | |
2175 | break; | |
11c6bffa | 2176 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2177 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 2178 | u64 gpa_offset; |
54750f2c MT |
2179 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2180 | ||
12f9a48f | 2181 | kvmclock_reset(vcpu); |
18068523 | 2182 | |
54750f2c MT |
2183 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2184 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2185 | ||
2186 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
2187 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, | |
2188 | &vcpu->requests); | |
2189 | ||
2190 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2191 | } | |
2192 | ||
18068523 | 2193 | vcpu->arch.time = data; |
0061d53d | 2194 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2195 | |
2196 | /* we verify if the enable bit is set... */ | |
2197 | if (!(data & 1)) | |
2198 | break; | |
2199 | ||
0b79459b | 2200 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 2201 | |
0b79459b | 2202 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2203 | &vcpu->arch.pv_time, data & ~1ULL, |
2204 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2205 | vcpu->arch.pv_time_enabled = false; |
2206 | else | |
2207 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2208 | |
18068523 GOC |
2209 | break; |
2210 | } | |
344d9588 GN |
2211 | case MSR_KVM_ASYNC_PF_EN: |
2212 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2213 | return 1; | |
2214 | break; | |
c9aaa895 GC |
2215 | case MSR_KVM_STEAL_TIME: |
2216 | ||
2217 | if (unlikely(!sched_info_on())) | |
2218 | return 1; | |
2219 | ||
2220 | if (data & KVM_STEAL_RESERVED_MASK) | |
2221 | return 1; | |
2222 | ||
2223 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2224 | data & KVM_STEAL_VALID_BITS, |
2225 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2226 | return 1; |
2227 | ||
2228 | vcpu->arch.st.msr_val = data; | |
2229 | ||
2230 | if (!(data & KVM_MSR_ENABLED)) | |
2231 | break; | |
2232 | ||
2233 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2234 | ||
2235 | preempt_disable(); | |
2236 | accumulate_steal_time(vcpu); | |
2237 | preempt_enable(); | |
2238 | ||
2239 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2240 | ||
2241 | break; | |
ae7a2a3f MT |
2242 | case MSR_KVM_PV_EOI_EN: |
2243 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2244 | return 1; | |
2245 | break; | |
c9aaa895 | 2246 | |
890ca9ae HY |
2247 | case MSR_IA32_MCG_CTL: |
2248 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2249 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2250 | return set_msr_mce(vcpu, msr, data); |
71db6023 AP |
2251 | |
2252 | /* Performance counters are not protected by a CPUID bit, | |
2253 | * so we should check all of them in the generic path for the sake of | |
2254 | * cross vendor migration. | |
2255 | * Writing a zero into the event select MSRs disables them, | |
2256 | * which we perfectly emulate ;-). Any other value should be at least | |
2257 | * reported, some guests depend on them. | |
2258 | */ | |
71db6023 AP |
2259 | case MSR_K7_EVNTSEL0: |
2260 | case MSR_K7_EVNTSEL1: | |
2261 | case MSR_K7_EVNTSEL2: | |
2262 | case MSR_K7_EVNTSEL3: | |
2263 | if (data != 0) | |
a737f256 CD |
2264 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2265 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
2266 | break; |
2267 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
2268 | * so we ignore writes to make it happy. | |
2269 | */ | |
71db6023 AP |
2270 | case MSR_K7_PERFCTR0: |
2271 | case MSR_K7_PERFCTR1: | |
2272 | case MSR_K7_PERFCTR2: | |
2273 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
2274 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2275 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 2276 | break; |
5753785f GN |
2277 | case MSR_P6_PERFCTR0: |
2278 | case MSR_P6_PERFCTR1: | |
2279 | pr = true; | |
2280 | case MSR_P6_EVNTSEL0: | |
2281 | case MSR_P6_EVNTSEL1: | |
2282 | if (kvm_pmu_msr(vcpu, msr)) | |
afd80d85 | 2283 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2284 | |
2285 | if (pr || data != 0) | |
a737f256 CD |
2286 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2287 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2288 | break; |
84e0cefa JS |
2289 | case MSR_K7_CLK_CTL: |
2290 | /* | |
2291 | * Ignore all writes to this no longer documented MSR. | |
2292 | * Writes are only relevant for old K7 processors, | |
2293 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2294 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2295 | * affected processor models on the command line, hence |
2296 | * the need to ignore the workaround. | |
2297 | */ | |
2298 | break; | |
55cd8e5a GN |
2299 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2300 | if (kvm_hv_msr_partition_wide(msr)) { | |
2301 | int r; | |
2302 | mutex_lock(&vcpu->kvm->lock); | |
2303 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
2304 | mutex_unlock(&vcpu->kvm->lock); | |
2305 | return r; | |
2306 | } else | |
2307 | return set_msr_hyperv(vcpu, msr, data); | |
2308 | break; | |
91c9c3ed | 2309 | case MSR_IA32_BBL_CR_CTL3: |
2310 | /* Drop writes to this legacy MSR -- see rdmsr | |
2311 | * counterpart for further detail. | |
2312 | */ | |
a737f256 | 2313 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2314 | break; |
2b036c6b BO |
2315 | case MSR_AMD64_OSVW_ID_LENGTH: |
2316 | if (!guest_cpuid_has_osvw(vcpu)) | |
2317 | return 1; | |
2318 | vcpu->arch.osvw.length = data; | |
2319 | break; | |
2320 | case MSR_AMD64_OSVW_STATUS: | |
2321 | if (!guest_cpuid_has_osvw(vcpu)) | |
2322 | return 1; | |
2323 | vcpu->arch.osvw.status = data; | |
2324 | break; | |
15c4a640 | 2325 | default: |
ffde22ac ES |
2326 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2327 | return xen_hvm_config(vcpu, data); | |
f5132b01 | 2328 | if (kvm_pmu_msr(vcpu, msr)) |
afd80d85 | 2329 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2330 | if (!ignore_msrs) { |
a737f256 CD |
2331 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2332 | msr, data); | |
ed85c068 AP |
2333 | return 1; |
2334 | } else { | |
a737f256 CD |
2335 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2336 | msr, data); | |
ed85c068 AP |
2337 | break; |
2338 | } | |
15c4a640 CO |
2339 | } |
2340 | return 0; | |
2341 | } | |
2342 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2343 | ||
2344 | ||
2345 | /* | |
2346 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2347 | * Returns 0 on success, non-0 otherwise. | |
2348 | * Assumes vcpu_load() was already called. | |
2349 | */ | |
2350 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
2351 | { | |
2352 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
2353 | } | |
ff651cb6 | 2354 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2355 | |
9ba075a6 AK |
2356 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2357 | { | |
0bed3b56 SY |
2358 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
2359 | ||
9ba075a6 AK |
2360 | if (!msr_mtrr_valid(msr)) |
2361 | return 1; | |
2362 | ||
0bed3b56 SY |
2363 | if (msr == MSR_MTRRdefType) |
2364 | *pdata = vcpu->arch.mtrr_state.def_type + | |
2365 | (vcpu->arch.mtrr_state.enabled << 10); | |
2366 | else if (msr == MSR_MTRRfix64K_00000) | |
2367 | *pdata = p[0]; | |
2368 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
2369 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
2370 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
2371 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
2372 | else if (msr == MSR_IA32_CR_PAT) | |
2373 | *pdata = vcpu->arch.pat; | |
2374 | else { /* Variable MTRRs */ | |
2375 | int idx, is_mtrr_mask; | |
2376 | u64 *pt; | |
2377 | ||
2378 | idx = (msr - 0x200) / 2; | |
2379 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
2380 | if (!is_mtrr_mask) | |
2381 | pt = | |
2382 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
2383 | else | |
2384 | pt = | |
2385 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
2386 | *pdata = *pt; | |
2387 | } | |
2388 | ||
9ba075a6 AK |
2389 | return 0; |
2390 | } | |
2391 | ||
890ca9ae | 2392 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2393 | { |
2394 | u64 data; | |
890ca9ae HY |
2395 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2396 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2397 | |
2398 | switch (msr) { | |
15c4a640 CO |
2399 | case MSR_IA32_P5_MC_ADDR: |
2400 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2401 | data = 0; |
2402 | break; | |
15c4a640 | 2403 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2404 | data = vcpu->arch.mcg_cap; |
2405 | break; | |
c7ac679c | 2406 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2407 | if (!(mcg_cap & MCG_CTL_P)) |
2408 | return 1; | |
2409 | data = vcpu->arch.mcg_ctl; | |
2410 | break; | |
2411 | case MSR_IA32_MCG_STATUS: | |
2412 | data = vcpu->arch.mcg_status; | |
2413 | break; | |
2414 | default: | |
2415 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2416 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2417 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2418 | data = vcpu->arch.mce_banks[offset]; | |
2419 | break; | |
2420 | } | |
2421 | return 1; | |
2422 | } | |
2423 | *pdata = data; | |
2424 | return 0; | |
2425 | } | |
2426 | ||
55cd8e5a GN |
2427 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2428 | { | |
2429 | u64 data = 0; | |
2430 | struct kvm *kvm = vcpu->kvm; | |
2431 | ||
2432 | switch (msr) { | |
2433 | case HV_X64_MSR_GUEST_OS_ID: | |
2434 | data = kvm->arch.hv_guest_os_id; | |
2435 | break; | |
2436 | case HV_X64_MSR_HYPERCALL: | |
2437 | data = kvm->arch.hv_hypercall; | |
2438 | break; | |
e984097b VR |
2439 | case HV_X64_MSR_TIME_REF_COUNT: { |
2440 | data = | |
2441 | div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); | |
2442 | break; | |
2443 | } | |
2444 | case HV_X64_MSR_REFERENCE_TSC: | |
2445 | data = kvm->arch.hv_tsc_page; | |
2446 | break; | |
55cd8e5a | 2447 | default: |
a737f256 | 2448 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2449 | return 1; |
2450 | } | |
2451 | ||
2452 | *pdata = data; | |
2453 | return 0; | |
2454 | } | |
2455 | ||
2456 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2457 | { | |
2458 | u64 data = 0; | |
2459 | ||
2460 | switch (msr) { | |
2461 | case HV_X64_MSR_VP_INDEX: { | |
2462 | int r; | |
2463 | struct kvm_vcpu *v; | |
684851a1 TY |
2464 | kvm_for_each_vcpu(r, v, vcpu->kvm) { |
2465 | if (v == vcpu) { | |
55cd8e5a | 2466 | data = r; |
684851a1 TY |
2467 | break; |
2468 | } | |
2469 | } | |
55cd8e5a GN |
2470 | break; |
2471 | } | |
10388a07 GN |
2472 | case HV_X64_MSR_EOI: |
2473 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
2474 | case HV_X64_MSR_ICR: | |
2475 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
2476 | case HV_X64_MSR_TPR: | |
2477 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 2478 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
2479 | data = vcpu->arch.hv_vapic; |
2480 | break; | |
55cd8e5a | 2481 | default: |
a737f256 | 2482 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2483 | return 1; |
2484 | } | |
2485 | *pdata = data; | |
2486 | return 0; | |
2487 | } | |
2488 | ||
890ca9ae HY |
2489 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2490 | { | |
2491 | u64 data; | |
2492 | ||
2493 | switch (msr) { | |
890ca9ae | 2494 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2495 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2496 | case MSR_IA32_DEBUGCTLMSR: |
2497 | case MSR_IA32_LASTBRANCHFROMIP: | |
2498 | case MSR_IA32_LASTBRANCHTOIP: | |
2499 | case MSR_IA32_LASTINTFROMIP: | |
2500 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
2501 | case MSR_K8_SYSCFG: |
2502 | case MSR_K7_HWCR: | |
61a6bd67 | 2503 | case MSR_VM_HSAVE_PA: |
9e699624 | 2504 | case MSR_K7_EVNTSEL0: |
dc9b2d93 WH |
2505 | case MSR_K7_EVNTSEL1: |
2506 | case MSR_K7_EVNTSEL2: | |
2507 | case MSR_K7_EVNTSEL3: | |
1f3ee616 | 2508 | case MSR_K7_PERFCTR0: |
dc9b2d93 WH |
2509 | case MSR_K7_PERFCTR1: |
2510 | case MSR_K7_PERFCTR2: | |
2511 | case MSR_K7_PERFCTR3: | |
1fdbd48c | 2512 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2513 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2514 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2515 | case MSR_AMD64_BU_CFG2: |
15c4a640 CO |
2516 | data = 0; |
2517 | break; | |
5753785f GN |
2518 | case MSR_P6_PERFCTR0: |
2519 | case MSR_P6_PERFCTR1: | |
2520 | case MSR_P6_EVNTSEL0: | |
2521 | case MSR_P6_EVNTSEL1: | |
2522 | if (kvm_pmu_msr(vcpu, msr)) | |
2523 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
2524 | data = 0; | |
2525 | break; | |
742bc670 MT |
2526 | case MSR_IA32_UCODE_REV: |
2527 | data = 0x100000000ULL; | |
2528 | break; | |
9ba075a6 AK |
2529 | case MSR_MTRRcap: |
2530 | data = 0x500 | KVM_NR_VAR_MTRR; | |
2531 | break; | |
2532 | case 0x200 ... 0x2ff: | |
2533 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
2534 | case 0xcd: /* fsb frequency */ |
2535 | data = 3; | |
2536 | break; | |
7b914098 JS |
2537 | /* |
2538 | * MSR_EBC_FREQUENCY_ID | |
2539 | * Conservative value valid for even the basic CPU models. | |
2540 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2541 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2542 | * and 266MHz for model 3, or 4. Set Core Clock | |
2543 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2544 | * 31:24) even though these are only valid for CPU | |
2545 | * models > 2, however guests may end up dividing or | |
2546 | * multiplying by zero otherwise. | |
2547 | */ | |
2548 | case MSR_EBC_FREQUENCY_ID: | |
2549 | data = 1 << 24; | |
2550 | break; | |
15c4a640 CO |
2551 | case MSR_IA32_APICBASE: |
2552 | data = kvm_get_apic_base(vcpu); | |
2553 | break; | |
0105d1a5 GN |
2554 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2555 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
2556 | break; | |
a3e06bbe LJ |
2557 | case MSR_IA32_TSCDEADLINE: |
2558 | data = kvm_get_lapic_tscdeadline_msr(vcpu); | |
2559 | break; | |
ba904635 WA |
2560 | case MSR_IA32_TSC_ADJUST: |
2561 | data = (u64)vcpu->arch.ia32_tsc_adjust_msr; | |
2562 | break; | |
15c4a640 | 2563 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2564 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2565 | break; |
847f0ad8 AG |
2566 | case MSR_IA32_PERF_STATUS: |
2567 | /* TSC increment by tick */ | |
2568 | data = 1000ULL; | |
2569 | /* CPU multiplier */ | |
2570 | data |= (((uint64_t)4ULL) << 40); | |
2571 | break; | |
15c4a640 | 2572 | case MSR_EFER: |
f6801dff | 2573 | data = vcpu->arch.efer; |
15c4a640 | 2574 | break; |
18068523 | 2575 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2576 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2577 | data = vcpu->kvm->arch.wall_clock; |
2578 | break; | |
2579 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2580 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
2581 | data = vcpu->arch.time; |
2582 | break; | |
344d9588 GN |
2583 | case MSR_KVM_ASYNC_PF_EN: |
2584 | data = vcpu->arch.apf.msr_val; | |
2585 | break; | |
c9aaa895 GC |
2586 | case MSR_KVM_STEAL_TIME: |
2587 | data = vcpu->arch.st.msr_val; | |
2588 | break; | |
1d92128f MT |
2589 | case MSR_KVM_PV_EOI_EN: |
2590 | data = vcpu->arch.pv_eoi.msr_val; | |
2591 | break; | |
890ca9ae HY |
2592 | case MSR_IA32_P5_MC_ADDR: |
2593 | case MSR_IA32_P5_MC_TYPE: | |
2594 | case MSR_IA32_MCG_CAP: | |
2595 | case MSR_IA32_MCG_CTL: | |
2596 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2597 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2598 | return get_msr_mce(vcpu, msr, pdata); |
84e0cefa JS |
2599 | case MSR_K7_CLK_CTL: |
2600 | /* | |
2601 | * Provide expected ramp-up count for K7. All other | |
2602 | * are set to zero, indicating minimum divisors for | |
2603 | * every field. | |
2604 | * | |
2605 | * This prevents guest kernels on AMD host with CPU | |
2606 | * type 6, model 8 and higher from exploding due to | |
2607 | * the rdmsr failing. | |
2608 | */ | |
2609 | data = 0x20000000; | |
2610 | break; | |
55cd8e5a GN |
2611 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2612 | if (kvm_hv_msr_partition_wide(msr)) { | |
2613 | int r; | |
2614 | mutex_lock(&vcpu->kvm->lock); | |
2615 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
2616 | mutex_unlock(&vcpu->kvm->lock); | |
2617 | return r; | |
2618 | } else | |
2619 | return get_msr_hyperv(vcpu, msr, pdata); | |
2620 | break; | |
91c9c3ed | 2621 | case MSR_IA32_BBL_CR_CTL3: |
2622 | /* This legacy MSR exists but isn't fully documented in current | |
2623 | * silicon. It is however accessed by winxp in very narrow | |
2624 | * scenarios where it sets bit #19, itself documented as | |
2625 | * a "reserved" bit. Best effort attempt to source coherent | |
2626 | * read data here should the balance of the register be | |
2627 | * interpreted by the guest: | |
2628 | * | |
2629 | * L2 cache control register 3: 64GB range, 256KB size, | |
2630 | * enabled, latency 0x1, configured | |
2631 | */ | |
2632 | data = 0xbe702111; | |
2633 | break; | |
2b036c6b BO |
2634 | case MSR_AMD64_OSVW_ID_LENGTH: |
2635 | if (!guest_cpuid_has_osvw(vcpu)) | |
2636 | return 1; | |
2637 | data = vcpu->arch.osvw.length; | |
2638 | break; | |
2639 | case MSR_AMD64_OSVW_STATUS: | |
2640 | if (!guest_cpuid_has_osvw(vcpu)) | |
2641 | return 1; | |
2642 | data = vcpu->arch.osvw.status; | |
2643 | break; | |
15c4a640 | 2644 | default: |
f5132b01 GN |
2645 | if (kvm_pmu_msr(vcpu, msr)) |
2646 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
ed85c068 | 2647 | if (!ignore_msrs) { |
a737f256 | 2648 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2649 | return 1; |
2650 | } else { | |
a737f256 | 2651 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2652 | data = 0; |
2653 | } | |
2654 | break; | |
15c4a640 CO |
2655 | } |
2656 | *pdata = data; | |
2657 | return 0; | |
2658 | } | |
2659 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2660 | ||
313a3dc7 CO |
2661 | /* |
2662 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2663 | * | |
2664 | * @return number of msrs set successfully. | |
2665 | */ | |
2666 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2667 | struct kvm_msr_entry *entries, | |
2668 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2669 | unsigned index, u64 *data)) | |
2670 | { | |
f656ce01 | 2671 | int i, idx; |
313a3dc7 | 2672 | |
f656ce01 | 2673 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2674 | for (i = 0; i < msrs->nmsrs; ++i) |
2675 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2676 | break; | |
f656ce01 | 2677 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2678 | |
313a3dc7 CO |
2679 | return i; |
2680 | } | |
2681 | ||
2682 | /* | |
2683 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2684 | * | |
2685 | * @return number of msrs set successfully. | |
2686 | */ | |
2687 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2688 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2689 | unsigned index, u64 *data), | |
2690 | int writeback) | |
2691 | { | |
2692 | struct kvm_msrs msrs; | |
2693 | struct kvm_msr_entry *entries; | |
2694 | int r, n; | |
2695 | unsigned size; | |
2696 | ||
2697 | r = -EFAULT; | |
2698 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2699 | goto out; | |
2700 | ||
2701 | r = -E2BIG; | |
2702 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2703 | goto out; | |
2704 | ||
313a3dc7 | 2705 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2706 | entries = memdup_user(user_msrs->entries, size); |
2707 | if (IS_ERR(entries)) { | |
2708 | r = PTR_ERR(entries); | |
313a3dc7 | 2709 | goto out; |
ff5c2c03 | 2710 | } |
313a3dc7 CO |
2711 | |
2712 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2713 | if (r < 0) | |
2714 | goto out_free; | |
2715 | ||
2716 | r = -EFAULT; | |
2717 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2718 | goto out_free; | |
2719 | ||
2720 | r = n; | |
2721 | ||
2722 | out_free: | |
7a73c028 | 2723 | kfree(entries); |
313a3dc7 CO |
2724 | out: |
2725 | return r; | |
2726 | } | |
2727 | ||
784aa3d7 | 2728 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 ZX |
2729 | { |
2730 | int r; | |
2731 | ||
2732 | switch (ext) { | |
2733 | case KVM_CAP_IRQCHIP: | |
2734 | case KVM_CAP_HLT: | |
2735 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2736 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2737 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2738 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2739 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2740 | case KVM_CAP_PIT: |
a28e4f5a | 2741 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2742 | case KVM_CAP_MP_STATE: |
ed848624 | 2743 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2744 | case KVM_CAP_USER_NMI: |
52d939a0 | 2745 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2746 | case KVM_CAP_IRQ_INJECT_STATUS: |
721eecbf | 2747 | case KVM_CAP_IRQFD: |
d34e6b17 | 2748 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2749 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2750 | case KVM_CAP_PIT2: |
e9f42757 | 2751 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2752 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2753 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2754 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2755 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2756 | case KVM_CAP_HYPERV: |
10388a07 | 2757 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2758 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2759 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2760 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2761 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2762 | case KVM_CAP_XSAVE: |
344d9588 | 2763 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2764 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2765 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2766 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2767 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2768 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 2769 | case KVM_CAP_TSC_DEADLINE_TIMER: |
2a5bab10 AW |
2770 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2771 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2772 | case KVM_CAP_PCI_2_3: | |
2773 | #endif | |
018d00d2 ZX |
2774 | r = 1; |
2775 | break; | |
542472b5 LV |
2776 | case KVM_CAP_COALESCED_MMIO: |
2777 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2778 | break; | |
774ead3a AK |
2779 | case KVM_CAP_VAPIC: |
2780 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2781 | break; | |
f725230a | 2782 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2783 | r = KVM_SOFT_MAX_VCPUS; |
2784 | break; | |
2785 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2786 | r = KVM_MAX_VCPUS; |
2787 | break; | |
a988b910 | 2788 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2789 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2790 | break; |
a68a6a72 MT |
2791 | case KVM_CAP_PV_MMU: /* obsolete */ |
2792 | r = 0; | |
2f333bcb | 2793 | break; |
4cee4b72 | 2794 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2795 | case KVM_CAP_IOMMU: |
a1b60c1c | 2796 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2797 | break; |
4cee4b72 | 2798 | #endif |
890ca9ae HY |
2799 | case KVM_CAP_MCE: |
2800 | r = KVM_MAX_MCE_BANKS; | |
2801 | break; | |
2d5b5a66 SY |
2802 | case KVM_CAP_XCRS: |
2803 | r = cpu_has_xsave; | |
2804 | break; | |
92a1f12d JR |
2805 | case KVM_CAP_TSC_CONTROL: |
2806 | r = kvm_has_tsc_control; | |
2807 | break; | |
018d00d2 ZX |
2808 | default: |
2809 | r = 0; | |
2810 | break; | |
2811 | } | |
2812 | return r; | |
2813 | ||
2814 | } | |
2815 | ||
043405e1 CO |
2816 | long kvm_arch_dev_ioctl(struct file *filp, |
2817 | unsigned int ioctl, unsigned long arg) | |
2818 | { | |
2819 | void __user *argp = (void __user *)arg; | |
2820 | long r; | |
2821 | ||
2822 | switch (ioctl) { | |
2823 | case KVM_GET_MSR_INDEX_LIST: { | |
2824 | struct kvm_msr_list __user *user_msr_list = argp; | |
2825 | struct kvm_msr_list msr_list; | |
2826 | unsigned n; | |
2827 | ||
2828 | r = -EFAULT; | |
2829 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2830 | goto out; | |
2831 | n = msr_list.nmsrs; | |
2832 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2833 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2834 | goto out; | |
2835 | r = -E2BIG; | |
e125e7b6 | 2836 | if (n < msr_list.nmsrs) |
043405e1 CO |
2837 | goto out; |
2838 | r = -EFAULT; | |
2839 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2840 | num_msrs_to_save * sizeof(u32))) | |
2841 | goto out; | |
e125e7b6 | 2842 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2843 | &emulated_msrs, |
2844 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2845 | goto out; | |
2846 | r = 0; | |
2847 | break; | |
2848 | } | |
9c15bb1d BP |
2849 | case KVM_GET_SUPPORTED_CPUID: |
2850 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2851 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2852 | struct kvm_cpuid2 cpuid; | |
2853 | ||
2854 | r = -EFAULT; | |
2855 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2856 | goto out; | |
9c15bb1d BP |
2857 | |
2858 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2859 | ioctl); | |
674eea0f AK |
2860 | if (r) |
2861 | goto out; | |
2862 | ||
2863 | r = -EFAULT; | |
2864 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2865 | goto out; | |
2866 | r = 0; | |
2867 | break; | |
2868 | } | |
890ca9ae HY |
2869 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2870 | u64 mce_cap; | |
2871 | ||
2872 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2873 | r = -EFAULT; | |
2874 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2875 | goto out; | |
2876 | r = 0; | |
2877 | break; | |
2878 | } | |
043405e1 CO |
2879 | default: |
2880 | r = -EINVAL; | |
2881 | } | |
2882 | out: | |
2883 | return r; | |
2884 | } | |
2885 | ||
f5f48ee1 SY |
2886 | static void wbinvd_ipi(void *garbage) |
2887 | { | |
2888 | wbinvd(); | |
2889 | } | |
2890 | ||
2891 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2892 | { | |
e0f0bbc5 | 2893 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
2894 | } |
2895 | ||
313a3dc7 CO |
2896 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2897 | { | |
f5f48ee1 SY |
2898 | /* Address WBINVD may be executed by guest */ |
2899 | if (need_emulate_wbinvd(vcpu)) { | |
2900 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2901 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2902 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2903 | smp_call_function_single(vcpu->cpu, | |
2904 | wbinvd_ipi, NULL, 1); | |
2905 | } | |
2906 | ||
313a3dc7 | 2907 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2908 | |
0dd6a6ed ZA |
2909 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2910 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2911 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2912 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 2913 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 2914 | } |
8f6055cb | 2915 | |
48434c20 | 2916 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
2917 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
2918 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
2919 | if (tsc_delta < 0) |
2920 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2921 | if (check_tsc_unstable()) { |
b183aa58 ZA |
2922 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
2923 | vcpu->arch.last_guest_tsc); | |
2924 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2925 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2926 | } |
d98d07ca MT |
2927 | /* |
2928 | * On a host with synchronized TSC, there is no need to update | |
2929 | * kvmclock on vcpu->cpu migration | |
2930 | */ | |
2931 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 2932 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2933 | if (vcpu->cpu != cpu) |
2934 | kvm_migrate_timers(vcpu); | |
e48672fa | 2935 | vcpu->cpu = cpu; |
6b7d7e76 | 2936 | } |
c9aaa895 GC |
2937 | |
2938 | accumulate_steal_time(vcpu); | |
2939 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
2940 | } |
2941 | ||
2942 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2943 | { | |
02daab21 | 2944 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2945 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 2946 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2947 | } |
2948 | ||
313a3dc7 CO |
2949 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2950 | struct kvm_lapic_state *s) | |
2951 | { | |
5a71785d | 2952 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
ad312c7c | 2953 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2954 | |
2955 | return 0; | |
2956 | } | |
2957 | ||
2958 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2959 | struct kvm_lapic_state *s) | |
2960 | { | |
64eb0620 | 2961 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2962 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2963 | |
2964 | return 0; | |
2965 | } | |
2966 | ||
f77bc6a4 ZX |
2967 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2968 | struct kvm_interrupt *irq) | |
2969 | { | |
02cdb50f | 2970 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 ZX |
2971 | return -EINVAL; |
2972 | if (irqchip_in_kernel(vcpu->kvm)) | |
2973 | return -ENXIO; | |
f77bc6a4 | 2974 | |
66fd3f7f | 2975 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2976 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2977 | |
f77bc6a4 ZX |
2978 | return 0; |
2979 | } | |
2980 | ||
c4abb7c9 JK |
2981 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2982 | { | |
c4abb7c9 | 2983 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2984 | |
2985 | return 0; | |
2986 | } | |
2987 | ||
b209749f AK |
2988 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2989 | struct kvm_tpr_access_ctl *tac) | |
2990 | { | |
2991 | if (tac->flags) | |
2992 | return -EINVAL; | |
2993 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2994 | return 0; | |
2995 | } | |
2996 | ||
890ca9ae HY |
2997 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2998 | u64 mcg_cap) | |
2999 | { | |
3000 | int r; | |
3001 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3002 | ||
3003 | r = -EINVAL; | |
a9e38c3e | 3004 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
3005 | goto out; |
3006 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
3007 | goto out; | |
3008 | r = 0; | |
3009 | vcpu->arch.mcg_cap = mcg_cap; | |
3010 | /* Init IA32_MCG_CTL to all 1s */ | |
3011 | if (mcg_cap & MCG_CTL_P) | |
3012 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3013 | /* Init IA32_MCi_CTL to all 1s */ | |
3014 | for (bank = 0; bank < bank_num; bank++) | |
3015 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
3016 | out: | |
3017 | return r; | |
3018 | } | |
3019 | ||
3020 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3021 | struct kvm_x86_mce *mce) | |
3022 | { | |
3023 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3024 | unsigned bank_num = mcg_cap & 0xff; | |
3025 | u64 *banks = vcpu->arch.mce_banks; | |
3026 | ||
3027 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3028 | return -EINVAL; | |
3029 | /* | |
3030 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3031 | * reporting is disabled | |
3032 | */ | |
3033 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3034 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3035 | return 0; | |
3036 | banks += 4 * mce->bank; | |
3037 | /* | |
3038 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3039 | * reporting is disabled for the bank | |
3040 | */ | |
3041 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3042 | return 0; | |
3043 | if (mce->status & MCI_STATUS_UC) { | |
3044 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3045 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3046 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3047 | return 0; |
3048 | } | |
3049 | if (banks[1] & MCI_STATUS_VAL) | |
3050 | mce->status |= MCI_STATUS_OVER; | |
3051 | banks[2] = mce->addr; | |
3052 | banks[3] = mce->misc; | |
3053 | vcpu->arch.mcg_status = mce->mcg_status; | |
3054 | banks[1] = mce->status; | |
3055 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3056 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3057 | || !(banks[1] & MCI_STATUS_UC)) { | |
3058 | if (banks[1] & MCI_STATUS_VAL) | |
3059 | mce->status |= MCI_STATUS_OVER; | |
3060 | banks[2] = mce->addr; | |
3061 | banks[3] = mce->misc; | |
3062 | banks[1] = mce->status; | |
3063 | } else | |
3064 | banks[1] |= MCI_STATUS_OVER; | |
3065 | return 0; | |
3066 | } | |
3067 | ||
3cfc3092 JK |
3068 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3069 | struct kvm_vcpu_events *events) | |
3070 | { | |
7460fb4a | 3071 | process_nmi(vcpu); |
03b82a30 JK |
3072 | events->exception.injected = |
3073 | vcpu->arch.exception.pending && | |
3074 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
3075 | events->exception.nr = vcpu->arch.exception.nr; |
3076 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 3077 | events->exception.pad = 0; |
3cfc3092 JK |
3078 | events->exception.error_code = vcpu->arch.exception.error_code; |
3079 | ||
03b82a30 JK |
3080 | events->interrupt.injected = |
3081 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 3082 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3083 | events->interrupt.soft = 0; |
37ccdcbe | 3084 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3085 | |
3086 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3087 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3088 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3089 | events->nmi.pad = 0; |
3cfc3092 | 3090 | |
66450a21 | 3091 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3092 | |
dab4b911 | 3093 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3094 | | KVM_VCPUEVENT_VALID_SHADOW); |
97e69aa6 | 3095 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3096 | } |
3097 | ||
3098 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
3099 | struct kvm_vcpu_events *events) | |
3100 | { | |
dab4b911 | 3101 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
3102 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
3103 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
3104 | return -EINVAL; |
3105 | ||
7460fb4a | 3106 | process_nmi(vcpu); |
3cfc3092 JK |
3107 | vcpu->arch.exception.pending = events->exception.injected; |
3108 | vcpu->arch.exception.nr = events->exception.nr; | |
3109 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3110 | vcpu->arch.exception.error_code = events->exception.error_code; | |
3111 | ||
3112 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
3113 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
3114 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3115 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3116 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3117 | events->interrupt.shadow); | |
3cfc3092 JK |
3118 | |
3119 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3120 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3121 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3122 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3123 | ||
66450a21 JK |
3124 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
3125 | kvm_vcpu_has_lapic(vcpu)) | |
3126 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
3cfc3092 | 3127 | |
3842d135 AK |
3128 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3129 | ||
3cfc3092 JK |
3130 | return 0; |
3131 | } | |
3132 | ||
a1efbe77 JK |
3133 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3134 | struct kvm_debugregs *dbgregs) | |
3135 | { | |
73aaf249 JK |
3136 | unsigned long val; |
3137 | ||
a1efbe77 | 3138 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3139 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3140 | dbgregs->dr6 = val; |
a1efbe77 JK |
3141 | dbgregs->dr7 = vcpu->arch.dr7; |
3142 | dbgregs->flags = 0; | |
97e69aa6 | 3143 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3144 | } |
3145 | ||
3146 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3147 | struct kvm_debugregs *dbgregs) | |
3148 | { | |
3149 | if (dbgregs->flags) | |
3150 | return -EINVAL; | |
3151 | ||
a1efbe77 JK |
3152 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
3153 | vcpu->arch.dr6 = dbgregs->dr6; | |
73aaf249 | 3154 | kvm_update_dr6(vcpu); |
a1efbe77 | 3155 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3156 | kvm_update_dr7(vcpu); |
a1efbe77 | 3157 | |
a1efbe77 JK |
3158 | return 0; |
3159 | } | |
3160 | ||
df1daba7 PB |
3161 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3162 | ||
3163 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3164 | { | |
3165 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3166 | u64 xstate_bv = xsave->xsave_hdr.xstate_bv; | |
3167 | u64 valid; | |
3168 | ||
3169 | /* | |
3170 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3171 | * leaves 0 and 1 in the loop below. | |
3172 | */ | |
3173 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3174 | ||
3175 | /* Set XSTATE_BV */ | |
3176 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; | |
3177 | ||
3178 | /* | |
3179 | * Copy each region from the possibly compacted offset to the | |
3180 | * non-compacted offset. | |
3181 | */ | |
3182 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3183 | while (valid) { | |
3184 | u64 feature = valid & -valid; | |
3185 | int index = fls64(feature) - 1; | |
3186 | void *src = get_xsave_addr(xsave, feature); | |
3187 | ||
3188 | if (src) { | |
3189 | u32 size, offset, ecx, edx; | |
3190 | cpuid_count(XSTATE_CPUID, index, | |
3191 | &size, &offset, &ecx, &edx); | |
3192 | memcpy(dest + offset, src, size); | |
3193 | } | |
3194 | ||
3195 | valid -= feature; | |
3196 | } | |
3197 | } | |
3198 | ||
3199 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3200 | { | |
3201 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3202 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); | |
3203 | u64 valid; | |
3204 | ||
3205 | /* | |
3206 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3207 | * leaves 0 and 1 in the loop below. | |
3208 | */ | |
3209 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3210 | ||
3211 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
3212 | xsave->xsave_hdr.xstate_bv = xstate_bv; | |
3213 | if (cpu_has_xsaves) | |
3214 | xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
3215 | ||
3216 | /* | |
3217 | * Copy each region from the non-compacted offset to the | |
3218 | * possibly compacted offset. | |
3219 | */ | |
3220 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3221 | while (valid) { | |
3222 | u64 feature = valid & -valid; | |
3223 | int index = fls64(feature) - 1; | |
3224 | void *dest = get_xsave_addr(xsave, feature); | |
3225 | ||
3226 | if (dest) { | |
3227 | u32 size, offset, ecx, edx; | |
3228 | cpuid_count(XSTATE_CPUID, index, | |
3229 | &size, &offset, &ecx, &edx); | |
3230 | memcpy(dest, src + offset, size); | |
3231 | } else | |
3232 | WARN_ON_ONCE(1); | |
3233 | ||
3234 | valid -= feature; | |
3235 | } | |
3236 | } | |
3237 | ||
2d5b5a66 SY |
3238 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3239 | struct kvm_xsave *guest_xsave) | |
3240 | { | |
4344ee98 | 3241 | if (cpu_has_xsave) { |
df1daba7 PB |
3242 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3243 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3244 | } else { |
2d5b5a66 SY |
3245 | memcpy(guest_xsave->region, |
3246 | &vcpu->arch.guest_fpu.state->fxsave, | |
3247 | sizeof(struct i387_fxsave_struct)); | |
3248 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
3249 | XSTATE_FPSSE; | |
3250 | } | |
3251 | } | |
3252 | ||
3253 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3254 | struct kvm_xsave *guest_xsave) | |
3255 | { | |
3256 | u64 xstate_bv = | |
3257 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3258 | ||
d7876f1b PB |
3259 | if (cpu_has_xsave) { |
3260 | /* | |
3261 | * Here we allow setting states that are not present in | |
3262 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3263 | * with old userspace. | |
3264 | */ | |
4ff41732 | 3265 | if (xstate_bv & ~kvm_supported_xcr0()) |
d7876f1b | 3266 | return -EINVAL; |
df1daba7 | 3267 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3268 | } else { |
2d5b5a66 SY |
3269 | if (xstate_bv & ~XSTATE_FPSSE) |
3270 | return -EINVAL; | |
3271 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
3272 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
3273 | } | |
3274 | return 0; | |
3275 | } | |
3276 | ||
3277 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3278 | struct kvm_xcrs *guest_xcrs) | |
3279 | { | |
3280 | if (!cpu_has_xsave) { | |
3281 | guest_xcrs->nr_xcrs = 0; | |
3282 | return; | |
3283 | } | |
3284 | ||
3285 | guest_xcrs->nr_xcrs = 1; | |
3286 | guest_xcrs->flags = 0; | |
3287 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3288 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3289 | } | |
3290 | ||
3291 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3292 | struct kvm_xcrs *guest_xcrs) | |
3293 | { | |
3294 | int i, r = 0; | |
3295 | ||
3296 | if (!cpu_has_xsave) | |
3297 | return -EINVAL; | |
3298 | ||
3299 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3300 | return -EINVAL; | |
3301 | ||
3302 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3303 | /* Only support XCR0 currently */ | |
c67a04cb | 3304 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3305 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3306 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3307 | break; |
3308 | } | |
3309 | if (r) | |
3310 | r = -EINVAL; | |
3311 | return r; | |
3312 | } | |
3313 | ||
1c0b28c2 EM |
3314 | /* |
3315 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3316 | * stopped by the hypervisor. This function will be called from the host only. | |
3317 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3318 | * does not support pv clocks. | |
3319 | */ | |
3320 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3321 | { | |
0b79459b | 3322 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3323 | return -EINVAL; |
51d59c6b | 3324 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3325 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3326 | return 0; | |
3327 | } | |
3328 | ||
313a3dc7 CO |
3329 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3330 | unsigned int ioctl, unsigned long arg) | |
3331 | { | |
3332 | struct kvm_vcpu *vcpu = filp->private_data; | |
3333 | void __user *argp = (void __user *)arg; | |
3334 | int r; | |
d1ac91d8 AK |
3335 | union { |
3336 | struct kvm_lapic_state *lapic; | |
3337 | struct kvm_xsave *xsave; | |
3338 | struct kvm_xcrs *xcrs; | |
3339 | void *buffer; | |
3340 | } u; | |
3341 | ||
3342 | u.buffer = NULL; | |
313a3dc7 CO |
3343 | switch (ioctl) { |
3344 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
3345 | r = -EINVAL; |
3346 | if (!vcpu->arch.apic) | |
3347 | goto out; | |
d1ac91d8 | 3348 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3349 | |
b772ff36 | 3350 | r = -ENOMEM; |
d1ac91d8 | 3351 | if (!u.lapic) |
b772ff36 | 3352 | goto out; |
d1ac91d8 | 3353 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3354 | if (r) |
3355 | goto out; | |
3356 | r = -EFAULT; | |
d1ac91d8 | 3357 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3358 | goto out; |
3359 | r = 0; | |
3360 | break; | |
3361 | } | |
3362 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
3363 | r = -EINVAL; |
3364 | if (!vcpu->arch.apic) | |
3365 | goto out; | |
ff5c2c03 | 3366 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3367 | if (IS_ERR(u.lapic)) |
3368 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3369 | |
d1ac91d8 | 3370 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3371 | break; |
3372 | } | |
f77bc6a4 ZX |
3373 | case KVM_INTERRUPT: { |
3374 | struct kvm_interrupt irq; | |
3375 | ||
3376 | r = -EFAULT; | |
3377 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3378 | goto out; | |
3379 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3380 | break; |
3381 | } | |
c4abb7c9 JK |
3382 | case KVM_NMI: { |
3383 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3384 | break; |
3385 | } | |
313a3dc7 CO |
3386 | case KVM_SET_CPUID: { |
3387 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3388 | struct kvm_cpuid cpuid; | |
3389 | ||
3390 | r = -EFAULT; | |
3391 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3392 | goto out; | |
3393 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3394 | break; |
3395 | } | |
07716717 DK |
3396 | case KVM_SET_CPUID2: { |
3397 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3398 | struct kvm_cpuid2 cpuid; | |
3399 | ||
3400 | r = -EFAULT; | |
3401 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3402 | goto out; | |
3403 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3404 | cpuid_arg->entries); |
07716717 DK |
3405 | break; |
3406 | } | |
3407 | case KVM_GET_CPUID2: { | |
3408 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3409 | struct kvm_cpuid2 cpuid; | |
3410 | ||
3411 | r = -EFAULT; | |
3412 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3413 | goto out; | |
3414 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3415 | cpuid_arg->entries); |
07716717 DK |
3416 | if (r) |
3417 | goto out; | |
3418 | r = -EFAULT; | |
3419 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3420 | goto out; | |
3421 | r = 0; | |
3422 | break; | |
3423 | } | |
313a3dc7 CO |
3424 | case KVM_GET_MSRS: |
3425 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
3426 | break; | |
3427 | case KVM_SET_MSRS: | |
3428 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3429 | break; | |
b209749f AK |
3430 | case KVM_TPR_ACCESS_REPORTING: { |
3431 | struct kvm_tpr_access_ctl tac; | |
3432 | ||
3433 | r = -EFAULT; | |
3434 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3435 | goto out; | |
3436 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3437 | if (r) | |
3438 | goto out; | |
3439 | r = -EFAULT; | |
3440 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3441 | goto out; | |
3442 | r = 0; | |
3443 | break; | |
3444 | }; | |
b93463aa AK |
3445 | case KVM_SET_VAPIC_ADDR: { |
3446 | struct kvm_vapic_addr va; | |
3447 | ||
3448 | r = -EINVAL; | |
3449 | if (!irqchip_in_kernel(vcpu->kvm)) | |
3450 | goto out; | |
3451 | r = -EFAULT; | |
3452 | if (copy_from_user(&va, argp, sizeof va)) | |
3453 | goto out; | |
fda4e2e8 | 3454 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
b93463aa AK |
3455 | break; |
3456 | } | |
890ca9ae HY |
3457 | case KVM_X86_SETUP_MCE: { |
3458 | u64 mcg_cap; | |
3459 | ||
3460 | r = -EFAULT; | |
3461 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3462 | goto out; | |
3463 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3464 | break; | |
3465 | } | |
3466 | case KVM_X86_SET_MCE: { | |
3467 | struct kvm_x86_mce mce; | |
3468 | ||
3469 | r = -EFAULT; | |
3470 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3471 | goto out; | |
3472 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3473 | break; | |
3474 | } | |
3cfc3092 JK |
3475 | case KVM_GET_VCPU_EVENTS: { |
3476 | struct kvm_vcpu_events events; | |
3477 | ||
3478 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3479 | ||
3480 | r = -EFAULT; | |
3481 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3482 | break; | |
3483 | r = 0; | |
3484 | break; | |
3485 | } | |
3486 | case KVM_SET_VCPU_EVENTS: { | |
3487 | struct kvm_vcpu_events events; | |
3488 | ||
3489 | r = -EFAULT; | |
3490 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3491 | break; | |
3492 | ||
3493 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3494 | break; | |
3495 | } | |
a1efbe77 JK |
3496 | case KVM_GET_DEBUGREGS: { |
3497 | struct kvm_debugregs dbgregs; | |
3498 | ||
3499 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3500 | ||
3501 | r = -EFAULT; | |
3502 | if (copy_to_user(argp, &dbgregs, | |
3503 | sizeof(struct kvm_debugregs))) | |
3504 | break; | |
3505 | r = 0; | |
3506 | break; | |
3507 | } | |
3508 | case KVM_SET_DEBUGREGS: { | |
3509 | struct kvm_debugregs dbgregs; | |
3510 | ||
3511 | r = -EFAULT; | |
3512 | if (copy_from_user(&dbgregs, argp, | |
3513 | sizeof(struct kvm_debugregs))) | |
3514 | break; | |
3515 | ||
3516 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3517 | break; | |
3518 | } | |
2d5b5a66 | 3519 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3520 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3521 | r = -ENOMEM; |
d1ac91d8 | 3522 | if (!u.xsave) |
2d5b5a66 SY |
3523 | break; |
3524 | ||
d1ac91d8 | 3525 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3526 | |
3527 | r = -EFAULT; | |
d1ac91d8 | 3528 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3529 | break; |
3530 | r = 0; | |
3531 | break; | |
3532 | } | |
3533 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3534 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3535 | if (IS_ERR(u.xsave)) |
3536 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3537 | |
d1ac91d8 | 3538 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3539 | break; |
3540 | } | |
3541 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3542 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3543 | r = -ENOMEM; |
d1ac91d8 | 3544 | if (!u.xcrs) |
2d5b5a66 SY |
3545 | break; |
3546 | ||
d1ac91d8 | 3547 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3548 | |
3549 | r = -EFAULT; | |
d1ac91d8 | 3550 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3551 | sizeof(struct kvm_xcrs))) |
3552 | break; | |
3553 | r = 0; | |
3554 | break; | |
3555 | } | |
3556 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3557 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3558 | if (IS_ERR(u.xcrs)) |
3559 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3560 | |
d1ac91d8 | 3561 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3562 | break; |
3563 | } | |
92a1f12d JR |
3564 | case KVM_SET_TSC_KHZ: { |
3565 | u32 user_tsc_khz; | |
3566 | ||
3567 | r = -EINVAL; | |
92a1f12d JR |
3568 | user_tsc_khz = (u32)arg; |
3569 | ||
3570 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3571 | goto out; | |
3572 | ||
cc578287 ZA |
3573 | if (user_tsc_khz == 0) |
3574 | user_tsc_khz = tsc_khz; | |
3575 | ||
3576 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
3577 | |
3578 | r = 0; | |
3579 | goto out; | |
3580 | } | |
3581 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3582 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3583 | goto out; |
3584 | } | |
1c0b28c2 EM |
3585 | case KVM_KVMCLOCK_CTRL: { |
3586 | r = kvm_set_guest_paused(vcpu); | |
3587 | goto out; | |
3588 | } | |
313a3dc7 CO |
3589 | default: |
3590 | r = -EINVAL; | |
3591 | } | |
3592 | out: | |
d1ac91d8 | 3593 | kfree(u.buffer); |
313a3dc7 CO |
3594 | return r; |
3595 | } | |
3596 | ||
5b1c1493 CO |
3597 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3598 | { | |
3599 | return VM_FAULT_SIGBUS; | |
3600 | } | |
3601 | ||
1fe779f8 CO |
3602 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3603 | { | |
3604 | int ret; | |
3605 | ||
3606 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3607 | return -EINVAL; |
1fe779f8 CO |
3608 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3609 | return ret; | |
3610 | } | |
3611 | ||
b927a3ce SY |
3612 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3613 | u64 ident_addr) | |
3614 | { | |
3615 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3616 | return 0; | |
3617 | } | |
3618 | ||
1fe779f8 CO |
3619 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3620 | u32 kvm_nr_mmu_pages) | |
3621 | { | |
3622 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3623 | return -EINVAL; | |
3624 | ||
79fac95e | 3625 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3626 | |
3627 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3628 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3629 | |
79fac95e | 3630 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3631 | return 0; |
3632 | } | |
3633 | ||
3634 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3635 | { | |
39de71ec | 3636 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3637 | } |
3638 | ||
1fe779f8 CO |
3639 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3640 | { | |
3641 | int r; | |
3642 | ||
3643 | r = 0; | |
3644 | switch (chip->chip_id) { | |
3645 | case KVM_IRQCHIP_PIC_MASTER: | |
3646 | memcpy(&chip->chip.pic, | |
3647 | &pic_irqchip(kvm)->pics[0], | |
3648 | sizeof(struct kvm_pic_state)); | |
3649 | break; | |
3650 | case KVM_IRQCHIP_PIC_SLAVE: | |
3651 | memcpy(&chip->chip.pic, | |
3652 | &pic_irqchip(kvm)->pics[1], | |
3653 | sizeof(struct kvm_pic_state)); | |
3654 | break; | |
3655 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3656 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3657 | break; |
3658 | default: | |
3659 | r = -EINVAL; | |
3660 | break; | |
3661 | } | |
3662 | return r; | |
3663 | } | |
3664 | ||
3665 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3666 | { | |
3667 | int r; | |
3668 | ||
3669 | r = 0; | |
3670 | switch (chip->chip_id) { | |
3671 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3672 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3673 | memcpy(&pic_irqchip(kvm)->pics[0], |
3674 | &chip->chip.pic, | |
3675 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3676 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3677 | break; |
3678 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3679 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3680 | memcpy(&pic_irqchip(kvm)->pics[1], |
3681 | &chip->chip.pic, | |
3682 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3683 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3684 | break; |
3685 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3686 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3687 | break; |
3688 | default: | |
3689 | r = -EINVAL; | |
3690 | break; | |
3691 | } | |
3692 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3693 | return r; | |
3694 | } | |
3695 | ||
e0f63cb9 SY |
3696 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3697 | { | |
3698 | int r = 0; | |
3699 | ||
894a9c55 | 3700 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3701 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3702 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3703 | return r; |
3704 | } | |
3705 | ||
3706 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3707 | { | |
3708 | int r = 0; | |
3709 | ||
894a9c55 | 3710 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3711 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3712 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3713 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3714 | return r; | |
3715 | } | |
3716 | ||
3717 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3718 | { | |
3719 | int r = 0; | |
3720 | ||
3721 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3722 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3723 | sizeof(ps->channels)); | |
3724 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3725 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3726 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3727 | return r; |
3728 | } | |
3729 | ||
3730 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3731 | { | |
3732 | int r = 0, start = 0; | |
3733 | u32 prev_legacy, cur_legacy; | |
3734 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3735 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3736 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3737 | if (!prev_legacy && cur_legacy) | |
3738 | start = 1; | |
3739 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3740 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3741 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3742 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3743 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3744 | return r; |
3745 | } | |
3746 | ||
52d939a0 MT |
3747 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3748 | struct kvm_reinject_control *control) | |
3749 | { | |
3750 | if (!kvm->arch.vpit) | |
3751 | return -ENXIO; | |
894a9c55 | 3752 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3753 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3754 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3755 | return 0; |
3756 | } | |
3757 | ||
95d4c16c | 3758 | /** |
60c34612 TY |
3759 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3760 | * @kvm: kvm instance | |
3761 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3762 | * |
e108ff2f PB |
3763 | * Steps 1-4 below provide general overview of dirty page logging. See |
3764 | * kvm_get_dirty_log_protect() function description for additional details. | |
3765 | * | |
3766 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
3767 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
3768 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
3769 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
3770 | * writes will be marked dirty for next log read. | |
95d4c16c | 3771 | * |
60c34612 TY |
3772 | * 1. Take a snapshot of the bit and clear it if needed. |
3773 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
3774 | * 3. Copy the snapshot to the userspace. |
3775 | * 4. Flush TLB's if needed. | |
5bb064dc | 3776 | */ |
60c34612 | 3777 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3778 | { |
60c34612 | 3779 | bool is_dirty = false; |
e108ff2f | 3780 | int r; |
5bb064dc | 3781 | |
79fac95e | 3782 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3783 | |
88178fd4 KH |
3784 | /* |
3785 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
3786 | */ | |
3787 | if (kvm_x86_ops->flush_log_dirty) | |
3788 | kvm_x86_ops->flush_log_dirty(kvm); | |
3789 | ||
e108ff2f | 3790 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
198c74f4 XG |
3791 | |
3792 | /* | |
3793 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
3794 | * kvm_mmu_slot_remove_write_access(). | |
3795 | */ | |
e108ff2f | 3796 | lockdep_assert_held(&kvm->slots_lock); |
198c74f4 XG |
3797 | if (is_dirty) |
3798 | kvm_flush_remote_tlbs(kvm); | |
3799 | ||
79fac95e | 3800 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3801 | return r; |
3802 | } | |
3803 | ||
aa2fbe6d YZ |
3804 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3805 | bool line_status) | |
23d43cf9 CD |
3806 | { |
3807 | if (!irqchip_in_kernel(kvm)) | |
3808 | return -ENXIO; | |
3809 | ||
3810 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3811 | irq_event->irq, irq_event->level, |
3812 | line_status); | |
23d43cf9 CD |
3813 | return 0; |
3814 | } | |
3815 | ||
1fe779f8 CO |
3816 | long kvm_arch_vm_ioctl(struct file *filp, |
3817 | unsigned int ioctl, unsigned long arg) | |
3818 | { | |
3819 | struct kvm *kvm = filp->private_data; | |
3820 | void __user *argp = (void __user *)arg; | |
367e1319 | 3821 | int r = -ENOTTY; |
f0d66275 DH |
3822 | /* |
3823 | * This union makes it completely explicit to gcc-3.x | |
3824 | * that these two variables' stack usage should be | |
3825 | * combined, not added together. | |
3826 | */ | |
3827 | union { | |
3828 | struct kvm_pit_state ps; | |
e9f42757 | 3829 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3830 | struct kvm_pit_config pit_config; |
f0d66275 | 3831 | } u; |
1fe779f8 CO |
3832 | |
3833 | switch (ioctl) { | |
3834 | case KVM_SET_TSS_ADDR: | |
3835 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 3836 | break; |
b927a3ce SY |
3837 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3838 | u64 ident_addr; | |
3839 | ||
3840 | r = -EFAULT; | |
3841 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3842 | goto out; | |
3843 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
3844 | break; |
3845 | } | |
1fe779f8 CO |
3846 | case KVM_SET_NR_MMU_PAGES: |
3847 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
3848 | break; |
3849 | case KVM_GET_NR_MMU_PAGES: | |
3850 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3851 | break; | |
3ddea128 MT |
3852 | case KVM_CREATE_IRQCHIP: { |
3853 | struct kvm_pic *vpic; | |
3854 | ||
3855 | mutex_lock(&kvm->lock); | |
3856 | r = -EEXIST; | |
3857 | if (kvm->arch.vpic) | |
3858 | goto create_irqchip_unlock; | |
3e515705 AK |
3859 | r = -EINVAL; |
3860 | if (atomic_read(&kvm->online_vcpus)) | |
3861 | goto create_irqchip_unlock; | |
1fe779f8 | 3862 | r = -ENOMEM; |
3ddea128 MT |
3863 | vpic = kvm_create_pic(kvm); |
3864 | if (vpic) { | |
1fe779f8 CO |
3865 | r = kvm_ioapic_init(kvm); |
3866 | if (r) { | |
175504cd | 3867 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 3868 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
3869 | &vpic->dev_master); |
3870 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3871 | &vpic->dev_slave); | |
3872 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3873 | &vpic->dev_eclr); | |
175504cd | 3874 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3875 | kfree(vpic); |
3876 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3877 | } |
3878 | } else | |
3ddea128 MT |
3879 | goto create_irqchip_unlock; |
3880 | smp_wmb(); | |
3881 | kvm->arch.vpic = vpic; | |
3882 | smp_wmb(); | |
399ec807 AK |
3883 | r = kvm_setup_default_irq_routing(kvm); |
3884 | if (r) { | |
175504cd | 3885 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3886 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3887 | kvm_ioapic_destroy(kvm); |
3888 | kvm_destroy_pic(kvm); | |
3ddea128 | 3889 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3890 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3891 | } |
3ddea128 MT |
3892 | create_irqchip_unlock: |
3893 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3894 | break; |
3ddea128 | 3895 | } |
7837699f | 3896 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3897 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3898 | goto create_pit; | |
3899 | case KVM_CREATE_PIT2: | |
3900 | r = -EFAULT; | |
3901 | if (copy_from_user(&u.pit_config, argp, | |
3902 | sizeof(struct kvm_pit_config))) | |
3903 | goto out; | |
3904 | create_pit: | |
79fac95e | 3905 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3906 | r = -EEXIST; |
3907 | if (kvm->arch.vpit) | |
3908 | goto create_pit_unlock; | |
7837699f | 3909 | r = -ENOMEM; |
c5ff41ce | 3910 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3911 | if (kvm->arch.vpit) |
3912 | r = 0; | |
269e05e4 | 3913 | create_pit_unlock: |
79fac95e | 3914 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3915 | break; |
1fe779f8 CO |
3916 | case KVM_GET_IRQCHIP: { |
3917 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3918 | struct kvm_irqchip *chip; |
1fe779f8 | 3919 | |
ff5c2c03 SL |
3920 | chip = memdup_user(argp, sizeof(*chip)); |
3921 | if (IS_ERR(chip)) { | |
3922 | r = PTR_ERR(chip); | |
1fe779f8 | 3923 | goto out; |
ff5c2c03 SL |
3924 | } |
3925 | ||
1fe779f8 CO |
3926 | r = -ENXIO; |
3927 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3928 | goto get_irqchip_out; |
3929 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3930 | if (r) |
f0d66275 | 3931 | goto get_irqchip_out; |
1fe779f8 | 3932 | r = -EFAULT; |
f0d66275 DH |
3933 | if (copy_to_user(argp, chip, sizeof *chip)) |
3934 | goto get_irqchip_out; | |
1fe779f8 | 3935 | r = 0; |
f0d66275 DH |
3936 | get_irqchip_out: |
3937 | kfree(chip); | |
1fe779f8 CO |
3938 | break; |
3939 | } | |
3940 | case KVM_SET_IRQCHIP: { | |
3941 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3942 | struct kvm_irqchip *chip; |
1fe779f8 | 3943 | |
ff5c2c03 SL |
3944 | chip = memdup_user(argp, sizeof(*chip)); |
3945 | if (IS_ERR(chip)) { | |
3946 | r = PTR_ERR(chip); | |
1fe779f8 | 3947 | goto out; |
ff5c2c03 SL |
3948 | } |
3949 | ||
1fe779f8 CO |
3950 | r = -ENXIO; |
3951 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3952 | goto set_irqchip_out; |
3953 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3954 | if (r) |
f0d66275 | 3955 | goto set_irqchip_out; |
1fe779f8 | 3956 | r = 0; |
f0d66275 DH |
3957 | set_irqchip_out: |
3958 | kfree(chip); | |
1fe779f8 CO |
3959 | break; |
3960 | } | |
e0f63cb9 | 3961 | case KVM_GET_PIT: { |
e0f63cb9 | 3962 | r = -EFAULT; |
f0d66275 | 3963 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3964 | goto out; |
3965 | r = -ENXIO; | |
3966 | if (!kvm->arch.vpit) | |
3967 | goto out; | |
f0d66275 | 3968 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3969 | if (r) |
3970 | goto out; | |
3971 | r = -EFAULT; | |
f0d66275 | 3972 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3973 | goto out; |
3974 | r = 0; | |
3975 | break; | |
3976 | } | |
3977 | case KVM_SET_PIT: { | |
e0f63cb9 | 3978 | r = -EFAULT; |
f0d66275 | 3979 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3980 | goto out; |
3981 | r = -ENXIO; | |
3982 | if (!kvm->arch.vpit) | |
3983 | goto out; | |
f0d66275 | 3984 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3985 | break; |
3986 | } | |
e9f42757 BK |
3987 | case KVM_GET_PIT2: { |
3988 | r = -ENXIO; | |
3989 | if (!kvm->arch.vpit) | |
3990 | goto out; | |
3991 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3992 | if (r) | |
3993 | goto out; | |
3994 | r = -EFAULT; | |
3995 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3996 | goto out; | |
3997 | r = 0; | |
3998 | break; | |
3999 | } | |
4000 | case KVM_SET_PIT2: { | |
4001 | r = -EFAULT; | |
4002 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
4003 | goto out; | |
4004 | r = -ENXIO; | |
4005 | if (!kvm->arch.vpit) | |
4006 | goto out; | |
4007 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
4008 | break; |
4009 | } | |
52d939a0 MT |
4010 | case KVM_REINJECT_CONTROL: { |
4011 | struct kvm_reinject_control control; | |
4012 | r = -EFAULT; | |
4013 | if (copy_from_user(&control, argp, sizeof(control))) | |
4014 | goto out; | |
4015 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
4016 | break; |
4017 | } | |
ffde22ac ES |
4018 | case KVM_XEN_HVM_CONFIG: { |
4019 | r = -EFAULT; | |
4020 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
4021 | sizeof(struct kvm_xen_hvm_config))) | |
4022 | goto out; | |
4023 | r = -EINVAL; | |
4024 | if (kvm->arch.xen_hvm_config.flags) | |
4025 | goto out; | |
4026 | r = 0; | |
4027 | break; | |
4028 | } | |
afbcf7ab | 4029 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4030 | struct kvm_clock_data user_ns; |
4031 | u64 now_ns; | |
4032 | s64 delta; | |
4033 | ||
4034 | r = -EFAULT; | |
4035 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
4036 | goto out; | |
4037 | ||
4038 | r = -EINVAL; | |
4039 | if (user_ns.flags) | |
4040 | goto out; | |
4041 | ||
4042 | r = 0; | |
395c6b0a | 4043 | local_irq_disable(); |
759379dd | 4044 | now_ns = get_kernel_ns(); |
afbcf7ab | 4045 | delta = user_ns.clock - now_ns; |
395c6b0a | 4046 | local_irq_enable(); |
afbcf7ab | 4047 | kvm->arch.kvmclock_offset = delta; |
2e762ff7 | 4048 | kvm_gen_update_masterclock(kvm); |
afbcf7ab GC |
4049 | break; |
4050 | } | |
4051 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
4052 | struct kvm_clock_data user_ns; |
4053 | u64 now_ns; | |
4054 | ||
395c6b0a | 4055 | local_irq_disable(); |
759379dd | 4056 | now_ns = get_kernel_ns(); |
afbcf7ab | 4057 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 4058 | local_irq_enable(); |
afbcf7ab | 4059 | user_ns.flags = 0; |
97e69aa6 | 4060 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4061 | |
4062 | r = -EFAULT; | |
4063 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4064 | goto out; | |
4065 | r = 0; | |
4066 | break; | |
4067 | } | |
4068 | ||
1fe779f8 | 4069 | default: |
c274e03a | 4070 | r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); |
1fe779f8 CO |
4071 | } |
4072 | out: | |
4073 | return r; | |
4074 | } | |
4075 | ||
a16b043c | 4076 | static void kvm_init_msr_list(void) |
043405e1 CO |
4077 | { |
4078 | u32 dummy[2]; | |
4079 | unsigned i, j; | |
4080 | ||
e3267cbb GC |
4081 | /* skip the first msrs in the list. KVM-specific */ |
4082 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
4083 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4084 | continue; | |
93c4adc7 PB |
4085 | |
4086 | /* | |
4087 | * Even MSRs that are valid in the host may not be exposed | |
4088 | * to the guests in some cases. We could work around this | |
4089 | * in VMX with the generic MSR save/load machinery, but it | |
4090 | * is not really worthwhile since it will really only | |
4091 | * happen with nested virtualization. | |
4092 | */ | |
4093 | switch (msrs_to_save[i]) { | |
4094 | case MSR_IA32_BNDCFGS: | |
4095 | if (!kvm_x86_ops->mpx_supported()) | |
4096 | continue; | |
4097 | break; | |
4098 | default: | |
4099 | break; | |
4100 | } | |
4101 | ||
043405e1 CO |
4102 | if (j < i) |
4103 | msrs_to_save[j] = msrs_to_save[i]; | |
4104 | j++; | |
4105 | } | |
4106 | num_msrs_to_save = j; | |
4107 | } | |
4108 | ||
bda9020e MT |
4109 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4110 | const void *v) | |
bbd9b64e | 4111 | { |
70252a10 AK |
4112 | int handled = 0; |
4113 | int n; | |
4114 | ||
4115 | do { | |
4116 | n = min(len, 8); | |
4117 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4118 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
4119 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4120 | break; |
4121 | handled += n; | |
4122 | addr += n; | |
4123 | len -= n; | |
4124 | v += n; | |
4125 | } while (len); | |
bbd9b64e | 4126 | |
70252a10 | 4127 | return handled; |
bbd9b64e CO |
4128 | } |
4129 | ||
bda9020e | 4130 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4131 | { |
70252a10 AK |
4132 | int handled = 0; |
4133 | int n; | |
4134 | ||
4135 | do { | |
4136 | n = min(len, 8); | |
4137 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4138 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
4139 | addr, n, v)) | |
4140 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4141 | break; |
4142 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
4143 | handled += n; | |
4144 | addr += n; | |
4145 | len -= n; | |
4146 | v += n; | |
4147 | } while (len); | |
bbd9b64e | 4148 | |
70252a10 | 4149 | return handled; |
bbd9b64e CO |
4150 | } |
4151 | ||
2dafc6c2 GN |
4152 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4153 | struct kvm_segment *var, int seg) | |
4154 | { | |
4155 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4156 | } | |
4157 | ||
4158 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4159 | struct kvm_segment *var, int seg) | |
4160 | { | |
4161 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4162 | } | |
4163 | ||
54987b7a PB |
4164 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4165 | struct x86_exception *exception) | |
02f59dc9 JR |
4166 | { |
4167 | gpa_t t_gpa; | |
02f59dc9 JR |
4168 | |
4169 | BUG_ON(!mmu_is_nested(vcpu)); | |
4170 | ||
4171 | /* NPT walks are always user-walks */ | |
4172 | access |= PFERR_USER_MASK; | |
54987b7a | 4173 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4174 | |
4175 | return t_gpa; | |
4176 | } | |
4177 | ||
ab9ae313 AK |
4178 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4179 | struct x86_exception *exception) | |
1871c602 GN |
4180 | { |
4181 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4182 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4183 | } |
4184 | ||
ab9ae313 AK |
4185 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4186 | struct x86_exception *exception) | |
1871c602 GN |
4187 | { |
4188 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4189 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4190 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4191 | } |
4192 | ||
ab9ae313 AK |
4193 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4194 | struct x86_exception *exception) | |
1871c602 GN |
4195 | { |
4196 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4197 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4198 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4199 | } |
4200 | ||
4201 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4202 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4203 | struct x86_exception *exception) | |
1871c602 | 4204 | { |
ab9ae313 | 4205 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4206 | } |
4207 | ||
4208 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4209 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4210 | struct x86_exception *exception) |
bbd9b64e CO |
4211 | { |
4212 | void *data = val; | |
10589a46 | 4213 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4214 | |
4215 | while (bytes) { | |
14dfe855 | 4216 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4217 | exception); |
bbd9b64e | 4218 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4219 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4220 | int ret; |
4221 | ||
bcc55cba | 4222 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4223 | return X86EMUL_PROPAGATE_FAULT; |
44583cba PB |
4224 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, |
4225 | offset, toread); | |
10589a46 | 4226 | if (ret < 0) { |
c3cd7ffa | 4227 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4228 | goto out; |
4229 | } | |
bbd9b64e | 4230 | |
77c2002e IE |
4231 | bytes -= toread; |
4232 | data += toread; | |
4233 | addr += toread; | |
bbd9b64e | 4234 | } |
10589a46 | 4235 | out: |
10589a46 | 4236 | return r; |
bbd9b64e | 4237 | } |
77c2002e | 4238 | |
1871c602 | 4239 | /* used for instruction fetching */ |
0f65dd70 AK |
4240 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4241 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4242 | struct x86_exception *exception) |
1871c602 | 4243 | { |
0f65dd70 | 4244 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4245 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4246 | unsigned offset; |
4247 | int ret; | |
0f65dd70 | 4248 | |
44583cba PB |
4249 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4250 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4251 | exception); | |
4252 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4253 | return X86EMUL_PROPAGATE_FAULT; | |
4254 | ||
4255 | offset = addr & (PAGE_SIZE-1); | |
4256 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4257 | bytes = (unsigned)PAGE_SIZE - offset; | |
4258 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, | |
4259 | offset, bytes); | |
4260 | if (unlikely(ret < 0)) | |
4261 | return X86EMUL_IO_NEEDED; | |
4262 | ||
4263 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4264 | } |
4265 | ||
064aea77 | 4266 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4267 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4268 | struct x86_exception *exception) |
1871c602 | 4269 | { |
0f65dd70 | 4270 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4271 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4272 | |
1871c602 | 4273 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4274 | exception); |
1871c602 | 4275 | } |
064aea77 | 4276 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4277 | |
0f65dd70 AK |
4278 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4279 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4280 | struct x86_exception *exception) |
1871c602 | 4281 | { |
0f65dd70 | 4282 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4283 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4284 | } |
4285 | ||
6a4d7550 | 4286 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4287 | gva_t addr, void *val, |
2dafc6c2 | 4288 | unsigned int bytes, |
bcc55cba | 4289 | struct x86_exception *exception) |
77c2002e | 4290 | { |
0f65dd70 | 4291 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4292 | void *data = val; |
4293 | int r = X86EMUL_CONTINUE; | |
4294 | ||
4295 | while (bytes) { | |
14dfe855 JR |
4296 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4297 | PFERR_WRITE_MASK, | |
ab9ae313 | 4298 | exception); |
77c2002e IE |
4299 | unsigned offset = addr & (PAGE_SIZE-1); |
4300 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4301 | int ret; | |
4302 | ||
bcc55cba | 4303 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4304 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
4305 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
4306 | if (ret < 0) { | |
c3cd7ffa | 4307 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4308 | goto out; |
4309 | } | |
4310 | ||
4311 | bytes -= towrite; | |
4312 | data += towrite; | |
4313 | addr += towrite; | |
4314 | } | |
4315 | out: | |
4316 | return r; | |
4317 | } | |
6a4d7550 | 4318 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4319 | |
af7cc7d1 XG |
4320 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4321 | gpa_t *gpa, struct x86_exception *exception, | |
4322 | bool write) | |
4323 | { | |
97d64b78 AK |
4324 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4325 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4326 | |
97d64b78 | 4327 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 FW |
4328 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
4329 | vcpu->arch.access, access)) { | |
bebb106a XG |
4330 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4331 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4332 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4333 | return 1; |
4334 | } | |
4335 | ||
af7cc7d1 XG |
4336 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4337 | ||
4338 | if (*gpa == UNMAPPED_GVA) | |
4339 | return -1; | |
4340 | ||
4341 | /* For APIC access vmexit */ | |
4342 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4343 | return 1; | |
4344 | ||
4f022648 XG |
4345 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4346 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4347 | return 1; |
4f022648 | 4348 | } |
bebb106a | 4349 | |
af7cc7d1 XG |
4350 | return 0; |
4351 | } | |
4352 | ||
3200f405 | 4353 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4354 | const void *val, int bytes) |
bbd9b64e CO |
4355 | { |
4356 | int ret; | |
4357 | ||
4358 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 4359 | if (ret < 0) |
bbd9b64e | 4360 | return 0; |
f57f2ef5 | 4361 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4362 | return 1; |
4363 | } | |
4364 | ||
77d197b2 XG |
4365 | struct read_write_emulator_ops { |
4366 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4367 | int bytes); | |
4368 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4369 | void *val, int bytes); | |
4370 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4371 | int bytes, void *val); | |
4372 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4373 | void *val, int bytes); | |
4374 | bool write; | |
4375 | }; | |
4376 | ||
4377 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4378 | { | |
4379 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4380 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4381 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4382 | vcpu->mmio_read_completed = 0; |
4383 | return 1; | |
4384 | } | |
4385 | ||
4386 | return 0; | |
4387 | } | |
4388 | ||
4389 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4390 | void *val, int bytes) | |
4391 | { | |
4392 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
4393 | } | |
4394 | ||
4395 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4396 | void *val, int bytes) | |
4397 | { | |
4398 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4399 | } | |
4400 | ||
4401 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4402 | { | |
4403 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4404 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4405 | } | |
4406 | ||
4407 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4408 | void *val, int bytes) | |
4409 | { | |
4410 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4411 | return X86EMUL_IO_NEEDED; | |
4412 | } | |
4413 | ||
4414 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4415 | void *val, int bytes) | |
4416 | { | |
f78146b0 AK |
4417 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4418 | ||
87da7e66 | 4419 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4420 | return X86EMUL_CONTINUE; |
4421 | } | |
4422 | ||
0fbe9b0b | 4423 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4424 | .read_write_prepare = read_prepare, |
4425 | .read_write_emulate = read_emulate, | |
4426 | .read_write_mmio = vcpu_mmio_read, | |
4427 | .read_write_exit_mmio = read_exit_mmio, | |
4428 | }; | |
4429 | ||
0fbe9b0b | 4430 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4431 | .read_write_emulate = write_emulate, |
4432 | .read_write_mmio = write_mmio, | |
4433 | .read_write_exit_mmio = write_exit_mmio, | |
4434 | .write = true, | |
4435 | }; | |
4436 | ||
22388a3c XG |
4437 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4438 | unsigned int bytes, | |
4439 | struct x86_exception *exception, | |
4440 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4441 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4442 | { |
af7cc7d1 XG |
4443 | gpa_t gpa; |
4444 | int handled, ret; | |
22388a3c | 4445 | bool write = ops->write; |
f78146b0 | 4446 | struct kvm_mmio_fragment *frag; |
10589a46 | 4447 | |
22388a3c | 4448 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4449 | |
af7cc7d1 | 4450 | if (ret < 0) |
bbd9b64e | 4451 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4452 | |
4453 | /* For APIC access vmexit */ | |
af7cc7d1 | 4454 | if (ret) |
bbd9b64e CO |
4455 | goto mmio; |
4456 | ||
22388a3c | 4457 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4458 | return X86EMUL_CONTINUE; |
4459 | ||
4460 | mmio: | |
4461 | /* | |
4462 | * Is this MMIO handled locally? | |
4463 | */ | |
22388a3c | 4464 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4465 | if (handled == bytes) |
bbd9b64e | 4466 | return X86EMUL_CONTINUE; |
bbd9b64e | 4467 | |
70252a10 AK |
4468 | gpa += handled; |
4469 | bytes -= handled; | |
4470 | val += handled; | |
4471 | ||
87da7e66 XG |
4472 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4473 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4474 | frag->gpa = gpa; | |
4475 | frag->data = val; | |
4476 | frag->len = bytes; | |
f78146b0 | 4477 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4478 | } |
4479 | ||
52eb5a6d XL |
4480 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
4481 | unsigned long addr, | |
22388a3c XG |
4482 | void *val, unsigned int bytes, |
4483 | struct x86_exception *exception, | |
0fbe9b0b | 4484 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4485 | { |
0f65dd70 | 4486 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4487 | gpa_t gpa; |
4488 | int rc; | |
4489 | ||
4490 | if (ops->read_write_prepare && | |
4491 | ops->read_write_prepare(vcpu, val, bytes)) | |
4492 | return X86EMUL_CONTINUE; | |
4493 | ||
4494 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4495 | |
bbd9b64e CO |
4496 | /* Crossing a page boundary? */ |
4497 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4498 | int now; |
bbd9b64e CO |
4499 | |
4500 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4501 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4502 | vcpu, ops); | |
4503 | ||
bbd9b64e CO |
4504 | if (rc != X86EMUL_CONTINUE) |
4505 | return rc; | |
4506 | addr += now; | |
bac15531 NA |
4507 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
4508 | addr = (u32)addr; | |
bbd9b64e CO |
4509 | val += now; |
4510 | bytes -= now; | |
4511 | } | |
22388a3c | 4512 | |
f78146b0 AK |
4513 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4514 | vcpu, ops); | |
4515 | if (rc != X86EMUL_CONTINUE) | |
4516 | return rc; | |
4517 | ||
4518 | if (!vcpu->mmio_nr_fragments) | |
4519 | return rc; | |
4520 | ||
4521 | gpa = vcpu->mmio_fragments[0].gpa; | |
4522 | ||
4523 | vcpu->mmio_needed = 1; | |
4524 | vcpu->mmio_cur_fragment = 0; | |
4525 | ||
87da7e66 | 4526 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4527 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4528 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4529 | vcpu->run->mmio.phys_addr = gpa; | |
4530 | ||
4531 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4532 | } |
4533 | ||
4534 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4535 | unsigned long addr, | |
4536 | void *val, | |
4537 | unsigned int bytes, | |
4538 | struct x86_exception *exception) | |
4539 | { | |
4540 | return emulator_read_write(ctxt, addr, val, bytes, | |
4541 | exception, &read_emultor); | |
4542 | } | |
4543 | ||
52eb5a6d | 4544 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
4545 | unsigned long addr, |
4546 | const void *val, | |
4547 | unsigned int bytes, | |
4548 | struct x86_exception *exception) | |
4549 | { | |
4550 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4551 | exception, &write_emultor); | |
bbd9b64e | 4552 | } |
bbd9b64e | 4553 | |
daea3e73 AK |
4554 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4555 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4556 | ||
4557 | #ifdef CONFIG_X86_64 | |
4558 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4559 | #else | |
4560 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4561 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4562 | #endif |
4563 | ||
0f65dd70 AK |
4564 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4565 | unsigned long addr, | |
bbd9b64e CO |
4566 | const void *old, |
4567 | const void *new, | |
4568 | unsigned int bytes, | |
0f65dd70 | 4569 | struct x86_exception *exception) |
bbd9b64e | 4570 | { |
0f65dd70 | 4571 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4572 | gpa_t gpa; |
4573 | struct page *page; | |
4574 | char *kaddr; | |
4575 | bool exchanged; | |
2bacc55c | 4576 | |
daea3e73 AK |
4577 | /* guests cmpxchg8b have to be emulated atomically */ |
4578 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4579 | goto emul_write; | |
10589a46 | 4580 | |
daea3e73 | 4581 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4582 | |
daea3e73 AK |
4583 | if (gpa == UNMAPPED_GVA || |
4584 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4585 | goto emul_write; | |
2bacc55c | 4586 | |
daea3e73 AK |
4587 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4588 | goto emul_write; | |
72dc67a6 | 4589 | |
daea3e73 | 4590 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
32cad84f | 4591 | if (is_error_page(page)) |
c19b8bd6 | 4592 | goto emul_write; |
72dc67a6 | 4593 | |
8fd75e12 | 4594 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4595 | kaddr += offset_in_page(gpa); |
4596 | switch (bytes) { | |
4597 | case 1: | |
4598 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4599 | break; | |
4600 | case 2: | |
4601 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4602 | break; | |
4603 | case 4: | |
4604 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4605 | break; | |
4606 | case 8: | |
4607 | exchanged = CMPXCHG64(kaddr, old, new); | |
4608 | break; | |
4609 | default: | |
4610 | BUG(); | |
2bacc55c | 4611 | } |
8fd75e12 | 4612 | kunmap_atomic(kaddr); |
daea3e73 AK |
4613 | kvm_release_page_dirty(page); |
4614 | ||
4615 | if (!exchanged) | |
4616 | return X86EMUL_CMPXCHG_FAILED; | |
4617 | ||
d3714010 | 4618 | mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); |
f57f2ef5 | 4619 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4620 | |
4621 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4622 | |
3200f405 | 4623 | emul_write: |
daea3e73 | 4624 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4625 | |
0f65dd70 | 4626 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4627 | } |
4628 | ||
cf8f70bf GN |
4629 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4630 | { | |
4631 | /* TODO: String I/O for in kernel device */ | |
4632 | int r; | |
4633 | ||
4634 | if (vcpu->arch.pio.in) | |
e32edf4f | 4635 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, |
cf8f70bf GN |
4636 | vcpu->arch.pio.size, pd); |
4637 | else | |
e32edf4f | 4638 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, |
cf8f70bf GN |
4639 | vcpu->arch.pio.port, vcpu->arch.pio.size, |
4640 | pd); | |
4641 | return r; | |
4642 | } | |
4643 | ||
6f6fbe98 XG |
4644 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4645 | unsigned short port, void *val, | |
4646 | unsigned int count, bool in) | |
cf8f70bf | 4647 | { |
cf8f70bf | 4648 | vcpu->arch.pio.port = port; |
6f6fbe98 | 4649 | vcpu->arch.pio.in = in; |
7972995b | 4650 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4651 | vcpu->arch.pio.size = size; |
4652 | ||
4653 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4654 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4655 | return 1; |
4656 | } | |
4657 | ||
4658 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4659 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4660 | vcpu->run->io.size = size; |
4661 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4662 | vcpu->run->io.count = count; | |
4663 | vcpu->run->io.port = port; | |
4664 | ||
4665 | return 0; | |
4666 | } | |
4667 | ||
6f6fbe98 XG |
4668 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4669 | int size, unsigned short port, void *val, | |
4670 | unsigned int count) | |
cf8f70bf | 4671 | { |
ca1d4a9e | 4672 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4673 | int ret; |
ca1d4a9e | 4674 | |
6f6fbe98 XG |
4675 | if (vcpu->arch.pio.count) |
4676 | goto data_avail; | |
cf8f70bf | 4677 | |
6f6fbe98 XG |
4678 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4679 | if (ret) { | |
4680 | data_avail: | |
4681 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 4682 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 4683 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4684 | return 1; |
4685 | } | |
4686 | ||
cf8f70bf GN |
4687 | return 0; |
4688 | } | |
4689 | ||
6f6fbe98 XG |
4690 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4691 | int size, unsigned short port, | |
4692 | const void *val, unsigned int count) | |
4693 | { | |
4694 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4695 | ||
4696 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 4697 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
4698 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
4699 | } | |
4700 | ||
bbd9b64e CO |
4701 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4702 | { | |
4703 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4704 | } | |
4705 | ||
3cb16fe7 | 4706 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4707 | { |
3cb16fe7 | 4708 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4709 | } |
4710 | ||
5cb56059 | 4711 | int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
4712 | { |
4713 | if (!need_emulate_wbinvd(vcpu)) | |
4714 | return X86EMUL_CONTINUE; | |
4715 | ||
4716 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4717 | int cpu = get_cpu(); |
4718 | ||
4719 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4720 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4721 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4722 | put_cpu(); |
f5f48ee1 | 4723 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4724 | } else |
4725 | wbinvd(); | |
f5f48ee1 SY |
4726 | return X86EMUL_CONTINUE; |
4727 | } | |
5cb56059 JS |
4728 | |
4729 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4730 | { | |
4731 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
4732 | return kvm_emulate_wbinvd_noskip(vcpu); | |
4733 | } | |
f5f48ee1 SY |
4734 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
4735 | ||
5cb56059 JS |
4736 | |
4737 | ||
bcaf5cc5 AK |
4738 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4739 | { | |
5cb56059 | 4740 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
4741 | } |
4742 | ||
52eb5a6d XL |
4743 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4744 | unsigned long *dest) | |
bbd9b64e | 4745 | { |
16f8a6f9 | 4746 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4747 | } |
4748 | ||
52eb5a6d XL |
4749 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4750 | unsigned long value) | |
bbd9b64e | 4751 | { |
338dbc97 | 4752 | |
717746e3 | 4753 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4754 | } |
4755 | ||
52a46617 | 4756 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4757 | { |
52a46617 | 4758 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4759 | } |
4760 | ||
717746e3 | 4761 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4762 | { |
717746e3 | 4763 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4764 | unsigned long value; |
4765 | ||
4766 | switch (cr) { | |
4767 | case 0: | |
4768 | value = kvm_read_cr0(vcpu); | |
4769 | break; | |
4770 | case 2: | |
4771 | value = vcpu->arch.cr2; | |
4772 | break; | |
4773 | case 3: | |
9f8fe504 | 4774 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4775 | break; |
4776 | case 4: | |
4777 | value = kvm_read_cr4(vcpu); | |
4778 | break; | |
4779 | case 8: | |
4780 | value = kvm_get_cr8(vcpu); | |
4781 | break; | |
4782 | default: | |
a737f256 | 4783 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4784 | return 0; |
4785 | } | |
4786 | ||
4787 | return value; | |
4788 | } | |
4789 | ||
717746e3 | 4790 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4791 | { |
717746e3 | 4792 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4793 | int res = 0; |
4794 | ||
52a46617 GN |
4795 | switch (cr) { |
4796 | case 0: | |
49a9b07e | 4797 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4798 | break; |
4799 | case 2: | |
4800 | vcpu->arch.cr2 = val; | |
4801 | break; | |
4802 | case 3: | |
2390218b | 4803 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4804 | break; |
4805 | case 4: | |
a83b29c6 | 4806 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4807 | break; |
4808 | case 8: | |
eea1cff9 | 4809 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4810 | break; |
4811 | default: | |
a737f256 | 4812 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4813 | res = -1; |
52a46617 | 4814 | } |
0f12244f GN |
4815 | |
4816 | return res; | |
52a46617 GN |
4817 | } |
4818 | ||
717746e3 | 4819 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4820 | { |
717746e3 | 4821 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4822 | } |
4823 | ||
4bff1e86 | 4824 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4825 | { |
4bff1e86 | 4826 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4827 | } |
4828 | ||
4bff1e86 | 4829 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4830 | { |
4bff1e86 | 4831 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4832 | } |
4833 | ||
1ac9d0cf AK |
4834 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4835 | { | |
4836 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4837 | } | |
4838 | ||
4839 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4840 | { | |
4841 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4842 | } | |
4843 | ||
4bff1e86 AK |
4844 | static unsigned long emulator_get_cached_segment_base( |
4845 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4846 | { |
4bff1e86 | 4847 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4848 | } |
4849 | ||
1aa36616 AK |
4850 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4851 | struct desc_struct *desc, u32 *base3, | |
4852 | int seg) | |
2dafc6c2 GN |
4853 | { |
4854 | struct kvm_segment var; | |
4855 | ||
4bff1e86 | 4856 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4857 | *selector = var.selector; |
2dafc6c2 | 4858 | |
378a8b09 GN |
4859 | if (var.unusable) { |
4860 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 4861 | return false; |
378a8b09 | 4862 | } |
2dafc6c2 GN |
4863 | |
4864 | if (var.g) | |
4865 | var.limit >>= 12; | |
4866 | set_desc_limit(desc, var.limit); | |
4867 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4868 | #ifdef CONFIG_X86_64 |
4869 | if (base3) | |
4870 | *base3 = var.base >> 32; | |
4871 | #endif | |
2dafc6c2 GN |
4872 | desc->type = var.type; |
4873 | desc->s = var.s; | |
4874 | desc->dpl = var.dpl; | |
4875 | desc->p = var.present; | |
4876 | desc->avl = var.avl; | |
4877 | desc->l = var.l; | |
4878 | desc->d = var.db; | |
4879 | desc->g = var.g; | |
4880 | ||
4881 | return true; | |
4882 | } | |
4883 | ||
1aa36616 AK |
4884 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4885 | struct desc_struct *desc, u32 base3, | |
4886 | int seg) | |
2dafc6c2 | 4887 | { |
4bff1e86 | 4888 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4889 | struct kvm_segment var; |
4890 | ||
1aa36616 | 4891 | var.selector = selector; |
2dafc6c2 | 4892 | var.base = get_desc_base(desc); |
5601d05b GN |
4893 | #ifdef CONFIG_X86_64 |
4894 | var.base |= ((u64)base3) << 32; | |
4895 | #endif | |
2dafc6c2 GN |
4896 | var.limit = get_desc_limit(desc); |
4897 | if (desc->g) | |
4898 | var.limit = (var.limit << 12) | 0xfff; | |
4899 | var.type = desc->type; | |
2dafc6c2 GN |
4900 | var.dpl = desc->dpl; |
4901 | var.db = desc->d; | |
4902 | var.s = desc->s; | |
4903 | var.l = desc->l; | |
4904 | var.g = desc->g; | |
4905 | var.avl = desc->avl; | |
4906 | var.present = desc->p; | |
4907 | var.unusable = !var.present; | |
4908 | var.padding = 0; | |
4909 | ||
4910 | kvm_set_segment(vcpu, &var, seg); | |
4911 | return; | |
4912 | } | |
4913 | ||
717746e3 AK |
4914 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4915 | u32 msr_index, u64 *pdata) | |
4916 | { | |
4917 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
4918 | } | |
4919 | ||
4920 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4921 | u32 msr_index, u64 data) | |
4922 | { | |
8fe8ab46 WA |
4923 | struct msr_data msr; |
4924 | ||
4925 | msr.data = data; | |
4926 | msr.index = msr_index; | |
4927 | msr.host_initiated = false; | |
4928 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
4929 | } |
4930 | ||
67f4d428 NA |
4931 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
4932 | u32 pmc) | |
4933 | { | |
4934 | return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); | |
4935 | } | |
4936 | ||
222d21aa AK |
4937 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4938 | u32 pmc, u64 *pdata) | |
4939 | { | |
4940 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4941 | } | |
4942 | ||
6c3287f7 AK |
4943 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4944 | { | |
4945 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4946 | } | |
4947 | ||
5037f6f3 AK |
4948 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4949 | { | |
4950 | preempt_disable(); | |
5197b808 | 4951 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4952 | /* |
4953 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4954 | * so it may be clear at this point. | |
4955 | */ | |
4956 | clts(); | |
4957 | } | |
4958 | ||
4959 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4960 | { | |
4961 | preempt_enable(); | |
4962 | } | |
4963 | ||
2953538e | 4964 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 4965 | struct x86_instruction_info *info, |
c4f035c6 AK |
4966 | enum x86_intercept_stage stage) |
4967 | { | |
2953538e | 4968 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
4969 | } |
4970 | ||
0017f93a | 4971 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
4972 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
4973 | { | |
0017f93a | 4974 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
4975 | } |
4976 | ||
dd856efa AK |
4977 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
4978 | { | |
4979 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
4980 | } | |
4981 | ||
4982 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
4983 | { | |
4984 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
4985 | } | |
4986 | ||
801806d9 NA |
4987 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
4988 | { | |
4989 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
4990 | } | |
4991 | ||
0225fb50 | 4992 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
4993 | .read_gpr = emulator_read_gpr, |
4994 | .write_gpr = emulator_write_gpr, | |
1871c602 | 4995 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4996 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4997 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4998 | .read_emulated = emulator_read_emulated, |
4999 | .write_emulated = emulator_write_emulated, | |
5000 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 5001 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
5002 | .pio_in_emulated = emulator_pio_in_emulated, |
5003 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
5004 | .get_segment = emulator_get_segment, |
5005 | .set_segment = emulator_set_segment, | |
5951c442 | 5006 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 5007 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 5008 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
5009 | .set_gdt = emulator_set_gdt, |
5010 | .set_idt = emulator_set_idt, | |
52a46617 GN |
5011 | .get_cr = emulator_get_cr, |
5012 | .set_cr = emulator_set_cr, | |
9c537244 | 5013 | .cpl = emulator_get_cpl, |
35aa5375 GN |
5014 | .get_dr = emulator_get_dr, |
5015 | .set_dr = emulator_set_dr, | |
717746e3 AK |
5016 | .set_msr = emulator_set_msr, |
5017 | .get_msr = emulator_get_msr, | |
67f4d428 | 5018 | .check_pmc = emulator_check_pmc, |
222d21aa | 5019 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 5020 | .halt = emulator_halt, |
bcaf5cc5 | 5021 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 5022 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
5023 | .get_fpu = emulator_get_fpu, |
5024 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 5025 | .intercept = emulator_intercept, |
bdb42f5a | 5026 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 5027 | .set_nmi_mask = emulator_set_nmi_mask, |
bbd9b64e CO |
5028 | }; |
5029 | ||
95cb2295 GN |
5030 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
5031 | { | |
37ccdcbe | 5032 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
5033 | /* |
5034 | * an sti; sti; sequence only disable interrupts for the first | |
5035 | * instruction. So, if the last instruction, be it emulated or | |
5036 | * not, left the system with the INT_STI flag enabled, it | |
5037 | * means that the last instruction is an sti. We should not | |
5038 | * leave the flag on in this case. The same goes for mov ss | |
5039 | */ | |
37ccdcbe PB |
5040 | if (int_shadow & mask) |
5041 | mask = 0; | |
6addfc42 | 5042 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 5043 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
5044 | if (!mask) |
5045 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5046 | } | |
95cb2295 GN |
5047 | } |
5048 | ||
ef54bcfe | 5049 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
5050 | { |
5051 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 5052 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
5053 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
5054 | ||
5055 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
5056 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
5057 | ctxt->exception.error_code); | |
54b8486f | 5058 | else |
da9cb575 | 5059 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 5060 | return false; |
54b8486f GN |
5061 | } |
5062 | ||
8ec4722d MG |
5063 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
5064 | { | |
adf52235 | 5065 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
5066 | int cs_db, cs_l; |
5067 | ||
8ec4722d MG |
5068 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
5069 | ||
adf52235 TY |
5070 | ctxt->eflags = kvm_get_rflags(vcpu); |
5071 | ctxt->eip = kvm_rip_read(vcpu); | |
5072 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5073 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 5074 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
5075 | cs_db ? X86EMUL_MODE_PROT32 : |
5076 | X86EMUL_MODE_PROT16; | |
5077 | ctxt->guest_mode = is_guest_mode(vcpu); | |
5078 | ||
dd856efa | 5079 | init_decode_cache(ctxt); |
7ae441ea | 5080 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5081 | } |
5082 | ||
71f9833b | 5083 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5084 | { |
9d74191a | 5085 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5086 | int ret; |
5087 | ||
5088 | init_emulate_ctxt(vcpu); | |
5089 | ||
9dac77fa AK |
5090 | ctxt->op_bytes = 2; |
5091 | ctxt->ad_bytes = 2; | |
5092 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5093 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5094 | |
5095 | if (ret != X86EMUL_CONTINUE) | |
5096 | return EMULATE_FAIL; | |
5097 | ||
9dac77fa | 5098 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5099 | kvm_rip_write(vcpu, ctxt->eip); |
5100 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
5101 | |
5102 | if (irq == NMI_VECTOR) | |
7460fb4a | 5103 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
5104 | else |
5105 | vcpu->arch.interrupt.pending = false; | |
5106 | ||
5107 | return EMULATE_DONE; | |
5108 | } | |
5109 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5110 | ||
6d77dbfc GN |
5111 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
5112 | { | |
fc3a9157 JR |
5113 | int r = EMULATE_DONE; |
5114 | ||
6d77dbfc GN |
5115 | ++vcpu->stat.insn_emulation_fail; |
5116 | trace_kvm_emulate_insn_failed(vcpu); | |
a2b9e6c1 | 5117 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5118 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5119 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5120 | vcpu->run->internal.ndata = 0; | |
5121 | r = EMULATE_FAIL; | |
5122 | } | |
6d77dbfc | 5123 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5124 | |
5125 | return r; | |
6d77dbfc GN |
5126 | } |
5127 | ||
93c05d3e | 5128 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5129 | bool write_fault_to_shadow_pgtable, |
5130 | int emulation_type) | |
a6f177ef | 5131 | { |
95b3cf69 | 5132 | gpa_t gpa = cr2; |
8e3d9d06 | 5133 | pfn_t pfn; |
a6f177ef | 5134 | |
991eebf9 GN |
5135 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5136 | return false; | |
5137 | ||
95b3cf69 XG |
5138 | if (!vcpu->arch.mmu.direct_map) { |
5139 | /* | |
5140 | * Write permission should be allowed since only | |
5141 | * write access need to be emulated. | |
5142 | */ | |
5143 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5144 | |
95b3cf69 XG |
5145 | /* |
5146 | * If the mapping is invalid in guest, let cpu retry | |
5147 | * it to generate fault. | |
5148 | */ | |
5149 | if (gpa == UNMAPPED_GVA) | |
5150 | return true; | |
5151 | } | |
a6f177ef | 5152 | |
8e3d9d06 XG |
5153 | /* |
5154 | * Do not retry the unhandleable instruction if it faults on the | |
5155 | * readonly host memory, otherwise it will goto a infinite loop: | |
5156 | * retry instruction -> write #PF -> emulation fail -> retry | |
5157 | * instruction -> ... | |
5158 | */ | |
5159 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5160 | |
5161 | /* | |
5162 | * If the instruction failed on the error pfn, it can not be fixed, | |
5163 | * report the error to userspace. | |
5164 | */ | |
5165 | if (is_error_noslot_pfn(pfn)) | |
5166 | return false; | |
5167 | ||
5168 | kvm_release_pfn_clean(pfn); | |
5169 | ||
5170 | /* The instructions are well-emulated on direct mmu. */ | |
5171 | if (vcpu->arch.mmu.direct_map) { | |
5172 | unsigned int indirect_shadow_pages; | |
5173 | ||
5174 | spin_lock(&vcpu->kvm->mmu_lock); | |
5175 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5176 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5177 | ||
5178 | if (indirect_shadow_pages) | |
5179 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5180 | ||
a6f177ef | 5181 | return true; |
8e3d9d06 | 5182 | } |
a6f177ef | 5183 | |
95b3cf69 XG |
5184 | /* |
5185 | * if emulation was due to access to shadowed page table | |
5186 | * and it failed try to unshadow page and re-enter the | |
5187 | * guest to let CPU execute the instruction. | |
5188 | */ | |
5189 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5190 | |
5191 | /* | |
5192 | * If the access faults on its page table, it can not | |
5193 | * be fixed by unprotecting shadow page and it should | |
5194 | * be reported to userspace. | |
5195 | */ | |
5196 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5197 | } |
5198 | ||
1cb3f3ae XG |
5199 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5200 | unsigned long cr2, int emulation_type) | |
5201 | { | |
5202 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5203 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5204 | ||
5205 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5206 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5207 | ||
5208 | /* | |
5209 | * If the emulation is caused by #PF and it is non-page_table | |
5210 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5211 | * page protected, we can zap the shadow page and retry this | |
5212 | * instruction directly. | |
5213 | * | |
5214 | * Note: if the guest uses a non-page-table modifying instruction | |
5215 | * on the PDE that points to the instruction, then we will unmap | |
5216 | * the instruction and go to an infinite loop. So, we cache the | |
5217 | * last retried eip and the last fault address, if we meet the eip | |
5218 | * and the address again, we can break out of the potential infinite | |
5219 | * loop. | |
5220 | */ | |
5221 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5222 | ||
5223 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5224 | return false; | |
5225 | ||
5226 | if (x86_page_table_writing_insn(ctxt)) | |
5227 | return false; | |
5228 | ||
5229 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5230 | return false; | |
5231 | ||
5232 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5233 | vcpu->arch.last_retry_addr = cr2; | |
5234 | ||
5235 | if (!vcpu->arch.mmu.direct_map) | |
5236 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5237 | ||
22368028 | 5238 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5239 | |
5240 | return true; | |
5241 | } | |
5242 | ||
716d51ab GN |
5243 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5244 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5245 | ||
4a1e10d5 PB |
5246 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5247 | unsigned long *db) | |
5248 | { | |
5249 | u32 dr6 = 0; | |
5250 | int i; | |
5251 | u32 enable, rwlen; | |
5252 | ||
5253 | enable = dr7; | |
5254 | rwlen = dr7 >> 16; | |
5255 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5256 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5257 | dr6 |= (1 << i); | |
5258 | return dr6; | |
5259 | } | |
5260 | ||
6addfc42 | 5261 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) |
663f4c61 PB |
5262 | { |
5263 | struct kvm_run *kvm_run = vcpu->run; | |
5264 | ||
5265 | /* | |
6addfc42 PB |
5266 | * rflags is the old, "raw" value of the flags. The new value has |
5267 | * not been saved yet. | |
663f4c61 PB |
5268 | * |
5269 | * This is correct even for TF set by the guest, because "the | |
5270 | * processor will not generate this exception after the instruction | |
5271 | * that sets the TF flag". | |
5272 | */ | |
663f4c61 PB |
5273 | if (unlikely(rflags & X86_EFLAGS_TF)) { |
5274 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
6f43ed01 NA |
5275 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | |
5276 | DR6_RTM; | |
663f4c61 PB |
5277 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; |
5278 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5279 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5280 | *r = EMULATE_USER_EXIT; | |
5281 | } else { | |
5282 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5283 | /* | |
5284 | * "Certain debug exceptions may clear bit 0-3. The | |
5285 | * remaining contents of the DR6 register are never | |
5286 | * cleared by the processor". | |
5287 | */ | |
5288 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5289 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; |
663f4c61 PB |
5290 | kvm_queue_exception(vcpu, DB_VECTOR); |
5291 | } | |
5292 | } | |
5293 | } | |
5294 | ||
4a1e10d5 PB |
5295 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5296 | { | |
4a1e10d5 PB |
5297 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5298 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5299 | struct kvm_run *kvm_run = vcpu->run; |
5300 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5301 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5302 | vcpu->arch.guest_debug_dr7, |
5303 | vcpu->arch.eff_db); | |
5304 | ||
5305 | if (dr6 != 0) { | |
6f43ed01 | 5306 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5307 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5308 | kvm_run->debug.arch.exception = DB_VECTOR; |
5309 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5310 | *r = EMULATE_USER_EXIT; | |
5311 | return true; | |
5312 | } | |
5313 | } | |
5314 | ||
4161a569 NA |
5315 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5316 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5317 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5318 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5319 | vcpu->arch.dr7, |
5320 | vcpu->arch.db); | |
5321 | ||
5322 | if (dr6 != 0) { | |
5323 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5324 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5325 | kvm_queue_exception(vcpu, DB_VECTOR); |
5326 | *r = EMULATE_DONE; | |
5327 | return true; | |
5328 | } | |
5329 | } | |
5330 | ||
5331 | return false; | |
5332 | } | |
5333 | ||
51d8b661 AP |
5334 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5335 | unsigned long cr2, | |
dc25e89e AP |
5336 | int emulation_type, |
5337 | void *insn, | |
5338 | int insn_len) | |
bbd9b64e | 5339 | { |
95cb2295 | 5340 | int r; |
9d74191a | 5341 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5342 | bool writeback = true; |
93c05d3e | 5343 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5344 | |
93c05d3e XG |
5345 | /* |
5346 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5347 | * never reused. | |
5348 | */ | |
5349 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5350 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5351 | |
571008da | 5352 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5353 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5354 | |
5355 | /* | |
5356 | * We will reenter on the same instruction since | |
5357 | * we do not set complete_userspace_io. This does not | |
5358 | * handle watchpoints yet, those would be handled in | |
5359 | * the emulate_ops. | |
5360 | */ | |
5361 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5362 | return r; | |
5363 | ||
9d74191a TY |
5364 | ctxt->interruptibility = 0; |
5365 | ctxt->have_exception = false; | |
e0ad0b47 | 5366 | ctxt->exception.vector = -1; |
9d74191a | 5367 | ctxt->perm_ok = false; |
bbd9b64e | 5368 | |
b51e974f | 5369 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 5370 | |
9d74191a | 5371 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 5372 | |
e46479f8 | 5373 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 5374 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 5375 | if (r != EMULATION_OK) { |
4005996e AK |
5376 | if (emulation_type & EMULTYPE_TRAP_UD) |
5377 | return EMULATE_FAIL; | |
991eebf9 GN |
5378 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5379 | emulation_type)) | |
bbd9b64e | 5380 | return EMULATE_DONE; |
6d77dbfc GN |
5381 | if (emulation_type & EMULTYPE_SKIP) |
5382 | return EMULATE_FAIL; | |
5383 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
5384 | } |
5385 | } | |
5386 | ||
ba8afb6b | 5387 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 5388 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
5389 | if (ctxt->eflags & X86_EFLAGS_RF) |
5390 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
5391 | return EMULATE_DONE; |
5392 | } | |
5393 | ||
1cb3f3ae XG |
5394 | if (retry_instruction(ctxt, cr2, emulation_type)) |
5395 | return EMULATE_DONE; | |
5396 | ||
7ae441ea | 5397 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 5398 | changes registers values during IO operation */ |
7ae441ea GN |
5399 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
5400 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 5401 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 5402 | } |
4d2179e1 | 5403 | |
5cd21917 | 5404 | restart: |
9d74191a | 5405 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 5406 | |
775fde86 JR |
5407 | if (r == EMULATION_INTERCEPTED) |
5408 | return EMULATE_DONE; | |
5409 | ||
d2ddd1c4 | 5410 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
5411 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5412 | emulation_type)) | |
c3cd7ffa GN |
5413 | return EMULATE_DONE; |
5414 | ||
6d77dbfc | 5415 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
5416 | } |
5417 | ||
9d74191a | 5418 | if (ctxt->have_exception) { |
d2ddd1c4 | 5419 | r = EMULATE_DONE; |
ef54bcfe PB |
5420 | if (inject_emulated_exception(vcpu)) |
5421 | return r; | |
d2ddd1c4 | 5422 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
5423 | if (!vcpu->arch.pio.in) { |
5424 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 5425 | vcpu->arch.pio.count = 0; |
0912c977 | 5426 | } else { |
7ae441ea | 5427 | writeback = false; |
716d51ab GN |
5428 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
5429 | } | |
ac0a48c3 | 5430 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
5431 | } else if (vcpu->mmio_needed) { |
5432 | if (!vcpu->mmio_is_write) | |
5433 | writeback = false; | |
ac0a48c3 | 5434 | r = EMULATE_USER_EXIT; |
716d51ab | 5435 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5436 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5437 | goto restart; |
d2ddd1c4 GN |
5438 | else |
5439 | r = EMULATE_DONE; | |
f850e2e6 | 5440 | |
7ae441ea | 5441 | if (writeback) { |
6addfc42 | 5442 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 5443 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 5444 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9d74191a | 5445 | kvm_rip_write(vcpu, ctxt->eip); |
663f4c61 | 5446 | if (r == EMULATE_DONE) |
6addfc42 | 5447 | kvm_vcpu_check_singlestep(vcpu, rflags, &r); |
38827dbd NA |
5448 | if (!ctxt->have_exception || |
5449 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
5450 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
5451 | |
5452 | /* | |
5453 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
5454 | * do nothing, and it will be requested again as soon as | |
5455 | * the shadow expires. But we still need to check here, | |
5456 | * because POPF has no interrupt shadow. | |
5457 | */ | |
5458 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
5459 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
5460 | } else |
5461 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5462 | |
5463 | return r; | |
de7d789a | 5464 | } |
51d8b661 | 5465 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5466 | |
cf8f70bf | 5467 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5468 | { |
cf8f70bf | 5469 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5470 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5471 | size, port, &val, 1); | |
cf8f70bf | 5472 | /* do not return to emulator after return from userspace */ |
7972995b | 5473 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5474 | return ret; |
5475 | } | |
cf8f70bf | 5476 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5477 | |
8cfdc000 ZA |
5478 | static void tsc_bad(void *info) |
5479 | { | |
0a3aee0d | 5480 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5481 | } |
5482 | ||
5483 | static void tsc_khz_changed(void *data) | |
c8076604 | 5484 | { |
8cfdc000 ZA |
5485 | struct cpufreq_freqs *freq = data; |
5486 | unsigned long khz = 0; | |
5487 | ||
5488 | if (data) | |
5489 | khz = freq->new; | |
5490 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5491 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5492 | if (!khz) | |
5493 | khz = tsc_khz; | |
0a3aee0d | 5494 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5495 | } |
5496 | ||
c8076604 GH |
5497 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5498 | void *data) | |
5499 | { | |
5500 | struct cpufreq_freqs *freq = data; | |
5501 | struct kvm *kvm; | |
5502 | struct kvm_vcpu *vcpu; | |
5503 | int i, send_ipi = 0; | |
5504 | ||
8cfdc000 ZA |
5505 | /* |
5506 | * We allow guests to temporarily run on slowing clocks, | |
5507 | * provided we notify them after, or to run on accelerating | |
5508 | * clocks, provided we notify them before. Thus time never | |
5509 | * goes backwards. | |
5510 | * | |
5511 | * However, we have a problem. We can't atomically update | |
5512 | * the frequency of a given CPU from this function; it is | |
5513 | * merely a notifier, which can be called from any CPU. | |
5514 | * Changing the TSC frequency at arbitrary points in time | |
5515 | * requires a recomputation of local variables related to | |
5516 | * the TSC for each VCPU. We must flag these local variables | |
5517 | * to be updated and be sure the update takes place with the | |
5518 | * new frequency before any guests proceed. | |
5519 | * | |
5520 | * Unfortunately, the combination of hotplug CPU and frequency | |
5521 | * change creates an intractable locking scenario; the order | |
5522 | * of when these callouts happen is undefined with respect to | |
5523 | * CPU hotplug, and they can race with each other. As such, | |
5524 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5525 | * undefined; you can actually have a CPU frequency change take | |
5526 | * place in between the computation of X and the setting of the | |
5527 | * variable. To protect against this problem, all updates of | |
5528 | * the per_cpu tsc_khz variable are done in an interrupt | |
5529 | * protected IPI, and all callers wishing to update the value | |
5530 | * must wait for a synchronous IPI to complete (which is trivial | |
5531 | * if the caller is on the CPU already). This establishes the | |
5532 | * necessary total order on variable updates. | |
5533 | * | |
5534 | * Note that because a guest time update may take place | |
5535 | * anytime after the setting of the VCPU's request bit, the | |
5536 | * correct TSC value must be set before the request. However, | |
5537 | * to ensure the update actually makes it to any guest which | |
5538 | * starts running in hardware virtualization between the set | |
5539 | * and the acquisition of the spinlock, we must also ping the | |
5540 | * CPU after setting the request bit. | |
5541 | * | |
5542 | */ | |
5543 | ||
c8076604 GH |
5544 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5545 | return 0; | |
5546 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5547 | return 0; | |
8cfdc000 ZA |
5548 | |
5549 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5550 | |
2f303b74 | 5551 | spin_lock(&kvm_lock); |
c8076604 | 5552 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5553 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5554 | if (vcpu->cpu != freq->cpu) |
5555 | continue; | |
c285545f | 5556 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5557 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5558 | send_ipi = 1; |
c8076604 GH |
5559 | } |
5560 | } | |
2f303b74 | 5561 | spin_unlock(&kvm_lock); |
c8076604 GH |
5562 | |
5563 | if (freq->old < freq->new && send_ipi) { | |
5564 | /* | |
5565 | * We upscale the frequency. Must make the guest | |
5566 | * doesn't see old kvmclock values while running with | |
5567 | * the new frequency, otherwise we risk the guest sees | |
5568 | * time go backwards. | |
5569 | * | |
5570 | * In case we update the frequency for another cpu | |
5571 | * (which might be in guest context) send an interrupt | |
5572 | * to kick the cpu out of guest context. Next time | |
5573 | * guest context is entered kvmclock will be updated, | |
5574 | * so the guest will not see stale values. | |
5575 | */ | |
8cfdc000 | 5576 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5577 | } |
5578 | return 0; | |
5579 | } | |
5580 | ||
5581 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5582 | .notifier_call = kvmclock_cpufreq_notifier |
5583 | }; | |
5584 | ||
5585 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5586 | unsigned long action, void *hcpu) | |
5587 | { | |
5588 | unsigned int cpu = (unsigned long)hcpu; | |
5589 | ||
5590 | switch (action) { | |
5591 | case CPU_ONLINE: | |
5592 | case CPU_DOWN_FAILED: | |
5593 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5594 | break; | |
5595 | case CPU_DOWN_PREPARE: | |
5596 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5597 | break; | |
5598 | } | |
5599 | return NOTIFY_OK; | |
5600 | } | |
5601 | ||
5602 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5603 | .notifier_call = kvmclock_cpu_notifier, | |
5604 | .priority = -INT_MAX | |
c8076604 GH |
5605 | }; |
5606 | ||
b820cc0c ZA |
5607 | static void kvm_timer_init(void) |
5608 | { | |
5609 | int cpu; | |
5610 | ||
c285545f | 5611 | max_tsc_khz = tsc_khz; |
460dd42e SB |
5612 | |
5613 | cpu_notifier_register_begin(); | |
b820cc0c | 5614 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5615 | #ifdef CONFIG_CPU_FREQ |
5616 | struct cpufreq_policy policy; | |
5617 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5618 | cpu = get_cpu(); |
5619 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5620 | if (policy.cpuinfo.max_freq) |
5621 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5622 | put_cpu(); |
c285545f | 5623 | #endif |
b820cc0c ZA |
5624 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5625 | CPUFREQ_TRANSITION_NOTIFIER); | |
5626 | } | |
c285545f | 5627 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5628 | for_each_online_cpu(cpu) |
5629 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
460dd42e SB |
5630 | |
5631 | __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5632 | cpu_notifier_register_done(); | |
5633 | ||
b820cc0c ZA |
5634 | } |
5635 | ||
ff9d07a0 ZY |
5636 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5637 | ||
f5132b01 | 5638 | int kvm_is_in_guest(void) |
ff9d07a0 | 5639 | { |
086c9855 | 5640 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5641 | } |
5642 | ||
5643 | static int kvm_is_user_mode(void) | |
5644 | { | |
5645 | int user_mode = 3; | |
dcf46b94 | 5646 | |
086c9855 AS |
5647 | if (__this_cpu_read(current_vcpu)) |
5648 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5649 | |
ff9d07a0 ZY |
5650 | return user_mode != 0; |
5651 | } | |
5652 | ||
5653 | static unsigned long kvm_get_guest_ip(void) | |
5654 | { | |
5655 | unsigned long ip = 0; | |
dcf46b94 | 5656 | |
086c9855 AS |
5657 | if (__this_cpu_read(current_vcpu)) |
5658 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5659 | |
ff9d07a0 ZY |
5660 | return ip; |
5661 | } | |
5662 | ||
5663 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5664 | .is_in_guest = kvm_is_in_guest, | |
5665 | .is_user_mode = kvm_is_user_mode, | |
5666 | .get_guest_ip = kvm_get_guest_ip, | |
5667 | }; | |
5668 | ||
5669 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5670 | { | |
086c9855 | 5671 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5672 | } |
5673 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5674 | ||
5675 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5676 | { | |
086c9855 | 5677 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5678 | } |
5679 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5680 | ||
ce88decf XG |
5681 | static void kvm_set_mmio_spte_mask(void) |
5682 | { | |
5683 | u64 mask; | |
5684 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5685 | ||
5686 | /* | |
5687 | * Set the reserved bits and the present bit of an paging-structure | |
5688 | * entry to generate page fault with PFER.RSV = 1. | |
5689 | */ | |
885032b9 | 5690 | /* Mask the reserved physical address bits. */ |
d1431483 | 5691 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 XG |
5692 | |
5693 | /* Bit 62 is always reserved for 32bit host. */ | |
5694 | mask |= 0x3ull << 62; | |
5695 | ||
5696 | /* Set the present bit. */ | |
ce88decf XG |
5697 | mask |= 1ull; |
5698 | ||
5699 | #ifdef CONFIG_X86_64 | |
5700 | /* | |
5701 | * If reserved bit is not supported, clear the present bit to disable | |
5702 | * mmio page fault. | |
5703 | */ | |
5704 | if (maxphyaddr == 52) | |
5705 | mask &= ~1ull; | |
5706 | #endif | |
5707 | ||
5708 | kvm_mmu_set_mmio_spte_mask(mask); | |
5709 | } | |
5710 | ||
16e8d74d MT |
5711 | #ifdef CONFIG_X86_64 |
5712 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5713 | { | |
d828199e MT |
5714 | struct kvm *kvm; |
5715 | ||
5716 | struct kvm_vcpu *vcpu; | |
5717 | int i; | |
5718 | ||
2f303b74 | 5719 | spin_lock(&kvm_lock); |
d828199e MT |
5720 | list_for_each_entry(kvm, &vm_list, vm_list) |
5721 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 5722 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 5723 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 5724 | spin_unlock(&kvm_lock); |
16e8d74d MT |
5725 | } |
5726 | ||
5727 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5728 | ||
5729 | /* | |
5730 | * Notification about pvclock gtod data update. | |
5731 | */ | |
5732 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5733 | void *priv) | |
5734 | { | |
5735 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5736 | struct timekeeper *tk = priv; | |
5737 | ||
5738 | update_pvclock_gtod(tk); | |
5739 | ||
5740 | /* disable master clock if host does not trust, or does not | |
5741 | * use, TSC clocksource | |
5742 | */ | |
5743 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5744 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5745 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5746 | ||
5747 | return 0; | |
5748 | } | |
5749 | ||
5750 | static struct notifier_block pvclock_gtod_notifier = { | |
5751 | .notifier_call = pvclock_gtod_notify, | |
5752 | }; | |
5753 | #endif | |
5754 | ||
f8c16bba | 5755 | int kvm_arch_init(void *opaque) |
043405e1 | 5756 | { |
b820cc0c | 5757 | int r; |
6b61edf7 | 5758 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 5759 | |
f8c16bba ZX |
5760 | if (kvm_x86_ops) { |
5761 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
5762 | r = -EEXIST; |
5763 | goto out; | |
f8c16bba ZX |
5764 | } |
5765 | ||
5766 | if (!ops->cpu_has_kvm_support()) { | |
5767 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
5768 | r = -EOPNOTSUPP; |
5769 | goto out; | |
f8c16bba ZX |
5770 | } |
5771 | if (ops->disabled_by_bios()) { | |
5772 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
5773 | r = -EOPNOTSUPP; |
5774 | goto out; | |
f8c16bba ZX |
5775 | } |
5776 | ||
013f6a5d MT |
5777 | r = -ENOMEM; |
5778 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5779 | if (!shared_msrs) { | |
5780 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5781 | goto out; | |
5782 | } | |
5783 | ||
97db56ce AK |
5784 | r = kvm_mmu_module_init(); |
5785 | if (r) | |
013f6a5d | 5786 | goto out_free_percpu; |
97db56ce | 5787 | |
ce88decf | 5788 | kvm_set_mmio_spte_mask(); |
97db56ce | 5789 | |
f8c16bba | 5790 | kvm_x86_ops = ops; |
920c8377 PB |
5791 | kvm_init_msr_list(); |
5792 | ||
7b52345e | 5793 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 5794 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 5795 | |
b820cc0c | 5796 | kvm_timer_init(); |
c8076604 | 5797 | |
ff9d07a0 ZY |
5798 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
5799 | ||
2acf923e DC |
5800 | if (cpu_has_xsave) |
5801 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
5802 | ||
c5cc421b | 5803 | kvm_lapic_init(); |
16e8d74d MT |
5804 | #ifdef CONFIG_X86_64 |
5805 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5806 | #endif | |
5807 | ||
f8c16bba | 5808 | return 0; |
56c6d28a | 5809 | |
013f6a5d MT |
5810 | out_free_percpu: |
5811 | free_percpu(shared_msrs); | |
56c6d28a | 5812 | out: |
56c6d28a | 5813 | return r; |
043405e1 | 5814 | } |
8776e519 | 5815 | |
f8c16bba ZX |
5816 | void kvm_arch_exit(void) |
5817 | { | |
ff9d07a0 ZY |
5818 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
5819 | ||
888d256e JK |
5820 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
5821 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5822 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 5823 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
5824 | #ifdef CONFIG_X86_64 |
5825 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5826 | #endif | |
f8c16bba | 5827 | kvm_x86_ops = NULL; |
56c6d28a | 5828 | kvm_mmu_module_exit(); |
013f6a5d | 5829 | free_percpu(shared_msrs); |
56c6d28a | 5830 | } |
f8c16bba | 5831 | |
5cb56059 | 5832 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
5833 | { |
5834 | ++vcpu->stat.halt_exits; | |
5835 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 5836 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
5837 | return 1; |
5838 | } else { | |
5839 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5840 | return 0; | |
5841 | } | |
5842 | } | |
5cb56059 JS |
5843 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
5844 | ||
5845 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
5846 | { | |
5847 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
5848 | return kvm_vcpu_halt(vcpu); | |
5849 | } | |
8776e519 HB |
5850 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
5851 | ||
55cd8e5a GN |
5852 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
5853 | { | |
5854 | u64 param, ingpa, outgpa, ret; | |
5855 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
5856 | bool fast, longmode; | |
55cd8e5a GN |
5857 | |
5858 | /* | |
5859 | * hypercall generates UD from non zero cpl and real mode | |
5860 | * per HYPER-V spec | |
5861 | */ | |
3eeb3288 | 5862 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
5863 | kvm_queue_exception(vcpu, UD_VECTOR); |
5864 | return 0; | |
5865 | } | |
5866 | ||
a449c7aa | 5867 | longmode = is_64_bit_mode(vcpu); |
55cd8e5a GN |
5868 | |
5869 | if (!longmode) { | |
ccd46936 GN |
5870 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
5871 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
5872 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
5873 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
5874 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
5875 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
5876 | } |
5877 | #ifdef CONFIG_X86_64 | |
5878 | else { | |
5879 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5880 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5881 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
5882 | } | |
5883 | #endif | |
5884 | ||
5885 | code = param & 0xffff; | |
5886 | fast = (param >> 16) & 0x1; | |
5887 | rep_cnt = (param >> 32) & 0xfff; | |
5888 | rep_idx = (param >> 48) & 0xfff; | |
5889 | ||
5890 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
5891 | ||
c25bc163 GN |
5892 | switch (code) { |
5893 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
5894 | kvm_vcpu_on_spin(vcpu); | |
5895 | break; | |
5896 | default: | |
5897 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
5898 | break; | |
5899 | } | |
55cd8e5a GN |
5900 | |
5901 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
5902 | if (longmode) { | |
5903 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5904 | } else { | |
5905 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
5906 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
5907 | } | |
5908 | ||
5909 | return 1; | |
5910 | } | |
5911 | ||
6aef266c SV |
5912 | /* |
5913 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
5914 | * | |
5915 | * @apicid - apicid of vcpu to be kicked. | |
5916 | */ | |
5917 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
5918 | { | |
24d2166b | 5919 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 5920 | |
24d2166b R |
5921 | lapic_irq.shorthand = 0; |
5922 | lapic_irq.dest_mode = 0; | |
5923 | lapic_irq.dest_id = apicid; | |
6aef266c | 5924 | |
24d2166b | 5925 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 5926 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
5927 | } |
5928 | ||
8776e519 HB |
5929 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5930 | { | |
5931 | unsigned long nr, a0, a1, a2, a3, ret; | |
a449c7aa | 5932 | int op_64_bit, r = 1; |
8776e519 | 5933 | |
5cb56059 JS |
5934 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
5935 | ||
55cd8e5a GN |
5936 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5937 | return kvm_hv_hypercall(vcpu); | |
5938 | ||
5fdbf976 MT |
5939 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5940 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5941 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5942 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5943 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5944 | |
229456fc | 5945 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5946 | |
a449c7aa NA |
5947 | op_64_bit = is_64_bit_mode(vcpu); |
5948 | if (!op_64_bit) { | |
8776e519 HB |
5949 | nr &= 0xFFFFFFFF; |
5950 | a0 &= 0xFFFFFFFF; | |
5951 | a1 &= 0xFFFFFFFF; | |
5952 | a2 &= 0xFFFFFFFF; | |
5953 | a3 &= 0xFFFFFFFF; | |
5954 | } | |
5955 | ||
07708c4a JK |
5956 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5957 | ret = -KVM_EPERM; | |
5958 | goto out; | |
5959 | } | |
5960 | ||
8776e519 | 5961 | switch (nr) { |
b93463aa AK |
5962 | case KVM_HC_VAPIC_POLL_IRQ: |
5963 | ret = 0; | |
5964 | break; | |
6aef266c SV |
5965 | case KVM_HC_KICK_CPU: |
5966 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
5967 | ret = 0; | |
5968 | break; | |
8776e519 HB |
5969 | default: |
5970 | ret = -KVM_ENOSYS; | |
5971 | break; | |
5972 | } | |
07708c4a | 5973 | out: |
a449c7aa NA |
5974 | if (!op_64_bit) |
5975 | ret = (u32)ret; | |
5fdbf976 | 5976 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 5977 | ++vcpu->stat.hypercalls; |
2f333bcb | 5978 | return r; |
8776e519 HB |
5979 | } |
5980 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
5981 | ||
b6785def | 5982 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 5983 | { |
d6aa1000 | 5984 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 5985 | char instruction[3]; |
5fdbf976 | 5986 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 5987 | |
8776e519 | 5988 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 5989 | |
9d74191a | 5990 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
5991 | } |
5992 | ||
b6c7a5dc HB |
5993 | /* |
5994 | * Check if userspace requested an interrupt window, and that the | |
5995 | * interrupt window is open. | |
5996 | * | |
5997 | * No need to exit to userspace if we already have an interrupt queued. | |
5998 | */ | |
851ba692 | 5999 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6000 | { |
8061823a | 6001 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 6002 | vcpu->run->request_interrupt_window && |
5df56646 | 6003 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
6004 | } |
6005 | ||
851ba692 | 6006 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6007 | { |
851ba692 AK |
6008 | struct kvm_run *kvm_run = vcpu->run; |
6009 | ||
91586a3b | 6010 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 6011 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 6012 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 6013 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 6014 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 6015 | else |
b6c7a5dc | 6016 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
6017 | kvm_arch_interrupt_allowed(vcpu) && |
6018 | !kvm_cpu_has_interrupt(vcpu) && | |
6019 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
6020 | } |
6021 | ||
95ba8273 GN |
6022 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
6023 | { | |
6024 | int max_irr, tpr; | |
6025 | ||
6026 | if (!kvm_x86_ops->update_cr8_intercept) | |
6027 | return; | |
6028 | ||
88c808fd AK |
6029 | if (!vcpu->arch.apic) |
6030 | return; | |
6031 | ||
8db3baa2 GN |
6032 | if (!vcpu->arch.apic->vapic_addr) |
6033 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
6034 | else | |
6035 | max_irr = -1; | |
95ba8273 GN |
6036 | |
6037 | if (max_irr != -1) | |
6038 | max_irr >>= 4; | |
6039 | ||
6040 | tpr = kvm_lapic_get_cr8(vcpu); | |
6041 | ||
6042 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
6043 | } | |
6044 | ||
b6b8a145 | 6045 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 6046 | { |
b6b8a145 JK |
6047 | int r; |
6048 | ||
95ba8273 | 6049 | /* try to reinject previous events if any */ |
b59bb7bd | 6050 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
6051 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
6052 | vcpu->arch.exception.has_error_code, | |
6053 | vcpu->arch.exception.error_code); | |
d6e8c854 NA |
6054 | |
6055 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) | |
6056 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
6057 | X86_EFLAGS_RF); | |
6058 | ||
6bdf0662 NA |
6059 | if (vcpu->arch.exception.nr == DB_VECTOR && |
6060 | (vcpu->arch.dr7 & DR7_GD)) { | |
6061 | vcpu->arch.dr7 &= ~DR7_GD; | |
6062 | kvm_update_dr7(vcpu); | |
6063 | } | |
6064 | ||
b59bb7bd GN |
6065 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
6066 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
6067 | vcpu->arch.exception.error_code, |
6068 | vcpu->arch.exception.reinject); | |
b6b8a145 | 6069 | return 0; |
b59bb7bd GN |
6070 | } |
6071 | ||
95ba8273 GN |
6072 | if (vcpu->arch.nmi_injected) { |
6073 | kvm_x86_ops->set_nmi(vcpu); | |
b6b8a145 | 6074 | return 0; |
95ba8273 GN |
6075 | } |
6076 | ||
6077 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 6078 | kvm_x86_ops->set_irq(vcpu); |
b6b8a145 JK |
6079 | return 0; |
6080 | } | |
6081 | ||
6082 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6083 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6084 | if (r != 0) | |
6085 | return r; | |
95ba8273 GN |
6086 | } |
6087 | ||
6088 | /* try to inject new event if pending */ | |
6089 | if (vcpu->arch.nmi_pending) { | |
6090 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 6091 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
6092 | vcpu->arch.nmi_injected = true; |
6093 | kvm_x86_ops->set_nmi(vcpu); | |
6094 | } | |
c7c9c56c | 6095 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6096 | /* |
6097 | * Because interrupts can be injected asynchronously, we are | |
6098 | * calling check_nested_events again here to avoid a race condition. | |
6099 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6100 | * proposal and current concerns. Perhaps we should be setting | |
6101 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6102 | */ | |
6103 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6104 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6105 | if (r != 0) | |
6106 | return r; | |
6107 | } | |
95ba8273 | 6108 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6109 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6110 | false); | |
6111 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6112 | } |
6113 | } | |
b6b8a145 | 6114 | return 0; |
95ba8273 GN |
6115 | } |
6116 | ||
7460fb4a AK |
6117 | static void process_nmi(struct kvm_vcpu *vcpu) |
6118 | { | |
6119 | unsigned limit = 2; | |
6120 | ||
6121 | /* | |
6122 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6123 | * If an NMI is already in progress, limit further NMIs to just one. | |
6124 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6125 | */ | |
6126 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6127 | limit = 1; | |
6128 | ||
6129 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6130 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6131 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6132 | } | |
6133 | ||
3d81bc7e | 6134 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c YZ |
6135 | { |
6136 | u64 eoi_exit_bitmap[4]; | |
cf9e65b7 | 6137 | u32 tmr[8]; |
c7c9c56c | 6138 | |
3d81bc7e YZ |
6139 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
6140 | return; | |
c7c9c56c YZ |
6141 | |
6142 | memset(eoi_exit_bitmap, 0, 32); | |
cf9e65b7 | 6143 | memset(tmr, 0, 32); |
c7c9c56c | 6144 | |
cf9e65b7 | 6145 | kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); |
c7c9c56c | 6146 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
cf9e65b7 | 6147 | kvm_apic_update_tmr(vcpu, tmr); |
c7c9c56c YZ |
6148 | } |
6149 | ||
a70656b6 RK |
6150 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) |
6151 | { | |
6152 | ++vcpu->stat.tlb_flush; | |
6153 | kvm_x86_ops->tlb_flush(vcpu); | |
6154 | } | |
6155 | ||
4256f43f TC |
6156 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
6157 | { | |
c24ae0dc TC |
6158 | struct page *page = NULL; |
6159 | ||
f439ed27 PB |
6160 | if (!irqchip_in_kernel(vcpu->kvm)) |
6161 | return; | |
6162 | ||
4256f43f TC |
6163 | if (!kvm_x86_ops->set_apic_access_page_addr) |
6164 | return; | |
6165 | ||
c24ae0dc TC |
6166 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
6167 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); | |
6168 | ||
6169 | /* | |
6170 | * Do not pin apic access page in memory, the MMU notifier | |
6171 | * will call us again if it is migrated or swapped out. | |
6172 | */ | |
6173 | put_page(page); | |
4256f43f TC |
6174 | } |
6175 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
6176 | ||
fe71557a TC |
6177 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
6178 | unsigned long address) | |
6179 | { | |
c24ae0dc TC |
6180 | /* |
6181 | * The physical address of apic access page is stored in the VMCS. | |
6182 | * Update it when it becomes invalid. | |
6183 | */ | |
6184 | if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) | |
6185 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
fe71557a TC |
6186 | } |
6187 | ||
9357d939 TY |
6188 | /* |
6189 | * Returns 1 to let __vcpu_run() continue the guest execution loop without | |
6190 | * exiting to the userspace. Otherwise, the value will be returned to the | |
6191 | * userspace. | |
6192 | */ | |
851ba692 | 6193 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
6194 | { |
6195 | int r; | |
6a8b1d13 | 6196 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 6197 | vcpu->run->request_interrupt_window; |
730dca42 | 6198 | bool req_immediate_exit = false; |
b6c7a5dc | 6199 | |
3e007509 | 6200 | if (vcpu->requests) { |
a8eeb04a | 6201 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 6202 | kvm_mmu_unload(vcpu); |
a8eeb04a | 6203 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 6204 | __kvm_migrate_timers(vcpu); |
d828199e MT |
6205 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6206 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
6207 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
6208 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
6209 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
6210 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
6211 | if (unlikely(r)) |
6212 | goto out; | |
6213 | } | |
a8eeb04a | 6214 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 6215 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 6216 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
a70656b6 | 6217 | kvm_vcpu_flush_tlb(vcpu); |
a8eeb04a | 6218 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 6219 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
6220 | r = 0; |
6221 | goto out; | |
6222 | } | |
a8eeb04a | 6223 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 6224 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
6225 | r = 0; |
6226 | goto out; | |
6227 | } | |
a8eeb04a | 6228 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
6229 | vcpu->fpu_active = 0; |
6230 | kvm_x86_ops->fpu_deactivate(vcpu); | |
6231 | } | |
af585b92 GN |
6232 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
6233 | /* Page is swapped out. Do synthetic halt */ | |
6234 | vcpu->arch.apf.halted = true; | |
6235 | r = 1; | |
6236 | goto out; | |
6237 | } | |
c9aaa895 GC |
6238 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
6239 | record_steal_time(vcpu); | |
7460fb4a AK |
6240 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
6241 | process_nmi(vcpu); | |
f5132b01 GN |
6242 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
6243 | kvm_handle_pmu_event(vcpu); | |
6244 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
6245 | kvm_deliver_pmi(vcpu); | |
3d81bc7e YZ |
6246 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
6247 | vcpu_scan_ioapic(vcpu); | |
4256f43f TC |
6248 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
6249 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2f52d58c | 6250 | } |
b93463aa | 6251 | |
b463a6f7 | 6252 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
6253 | kvm_apic_accept_events(vcpu); |
6254 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
6255 | r = 1; | |
6256 | goto out; | |
6257 | } | |
6258 | ||
b6b8a145 JK |
6259 | if (inject_pending_event(vcpu, req_int_win) != 0) |
6260 | req_immediate_exit = true; | |
b463a6f7 | 6261 | /* enable NMI/IRQ window open exits if needed */ |
b6b8a145 | 6262 | else if (vcpu->arch.nmi_pending) |
c9a7953f | 6263 | kvm_x86_ops->enable_nmi_window(vcpu); |
c7c9c56c | 6264 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) |
c9a7953f | 6265 | kvm_x86_ops->enable_irq_window(vcpu); |
b463a6f7 AK |
6266 | |
6267 | if (kvm_lapic_enabled(vcpu)) { | |
c7c9c56c YZ |
6268 | /* |
6269 | * Update architecture specific hints for APIC | |
6270 | * virtual interrupt delivery. | |
6271 | */ | |
6272 | if (kvm_x86_ops->hwapic_irr_update) | |
6273 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
6274 | kvm_lapic_find_highest_irr(vcpu)); | |
b463a6f7 AK |
6275 | update_cr8_intercept(vcpu); |
6276 | kvm_lapic_sync_to_vapic(vcpu); | |
6277 | } | |
6278 | } | |
6279 | ||
d8368af8 AK |
6280 | r = kvm_mmu_reload(vcpu); |
6281 | if (unlikely(r)) { | |
d905c069 | 6282 | goto cancel_injection; |
d8368af8 AK |
6283 | } |
6284 | ||
b6c7a5dc HB |
6285 | preempt_disable(); |
6286 | ||
6287 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
6288 | if (vcpu->fpu_active) |
6289 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 6290 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 6291 | |
6b7e2d09 XG |
6292 | vcpu->mode = IN_GUEST_MODE; |
6293 | ||
01b71917 MT |
6294 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6295 | ||
6b7e2d09 XG |
6296 | /* We should set ->mode before check ->requests, |
6297 | * see the comment in make_all_cpus_request. | |
6298 | */ | |
01b71917 | 6299 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 6300 | |
d94e1dc9 | 6301 | local_irq_disable(); |
32f88400 | 6302 | |
6b7e2d09 | 6303 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 6304 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 6305 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6306 | smp_wmb(); |
6c142801 AK |
6307 | local_irq_enable(); |
6308 | preempt_enable(); | |
01b71917 | 6309 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 6310 | r = 1; |
d905c069 | 6311 | goto cancel_injection; |
6c142801 AK |
6312 | } |
6313 | ||
d6185f20 NHE |
6314 | if (req_immediate_exit) |
6315 | smp_send_reschedule(vcpu->cpu); | |
6316 | ||
b6c7a5dc HB |
6317 | kvm_guest_enter(); |
6318 | ||
42dbaa5a | 6319 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
6320 | set_debugreg(0, 7); |
6321 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
6322 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
6323 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
6324 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 6325 | set_debugreg(vcpu->arch.dr6, 6); |
42dbaa5a | 6326 | } |
b6c7a5dc | 6327 | |
229456fc | 6328 | trace_kvm_entry(vcpu->vcpu_id); |
d0659d94 | 6329 | wait_lapic_expire(vcpu); |
851ba692 | 6330 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 6331 | |
c77fb5fe PB |
6332 | /* |
6333 | * Do this here before restoring debug registers on the host. And | |
6334 | * since we do this before handling the vmexit, a DR access vmexit | |
6335 | * can (a) read the correct value of the debug registers, (b) set | |
6336 | * KVM_DEBUGREG_WONT_EXIT again. | |
6337 | */ | |
6338 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
6339 | int i; | |
6340 | ||
6341 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); | |
6342 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
6343 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6344 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
6345 | } | |
6346 | ||
24f1e32c FW |
6347 | /* |
6348 | * If the guest has used debug registers, at least dr7 | |
6349 | * will be disabled while returning to the host. | |
6350 | * If we don't have active breakpoints in the host, we don't | |
6351 | * care about the messed up debug address registers. But if | |
6352 | * we have some of them active, restore the old state. | |
6353 | */ | |
59d8eb53 | 6354 | if (hw_breakpoint_active()) |
24f1e32c | 6355 | hw_breakpoint_restore(); |
42dbaa5a | 6356 | |
886b470c MT |
6357 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, |
6358 | native_read_tsc()); | |
1d5f066e | 6359 | |
6b7e2d09 | 6360 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6361 | smp_wmb(); |
a547c6db YZ |
6362 | |
6363 | /* Interrupt is enabled by handle_external_intr() */ | |
6364 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
6365 | |
6366 | ++vcpu->stat.exits; | |
6367 | ||
6368 | /* | |
6369 | * We must have an instruction between local_irq_enable() and | |
6370 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6371 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6372 | * But we need to prevent reordering, hence this barrier(): | |
6373 | */ | |
6374 | barrier(); | |
6375 | ||
6376 | kvm_guest_exit(); | |
6377 | ||
6378 | preempt_enable(); | |
6379 | ||
f656ce01 | 6380 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 6381 | |
b6c7a5dc HB |
6382 | /* |
6383 | * Profile KVM exit RIPs: | |
6384 | */ | |
6385 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
6386 | unsigned long rip = kvm_rip_read(vcpu); |
6387 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
6388 | } |
6389 | ||
cc578287 ZA |
6390 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
6391 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 6392 | |
5cfb1d5a MT |
6393 | if (vcpu->arch.apic_attention) |
6394 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 6395 | |
851ba692 | 6396 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
6397 | return r; |
6398 | ||
6399 | cancel_injection: | |
6400 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
6401 | if (unlikely(vcpu->arch.apic_attention)) |
6402 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
6403 | out: |
6404 | return r; | |
6405 | } | |
b6c7a5dc | 6406 | |
09cec754 | 6407 | |
851ba692 | 6408 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
6409 | { |
6410 | int r; | |
f656ce01 | 6411 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 6412 | |
f656ce01 | 6413 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
6414 | |
6415 | r = 1; | |
6416 | while (r > 0) { | |
af585b92 GN |
6417 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6418 | !vcpu->arch.apf.halted) | |
851ba692 | 6419 | r = vcpu_enter_guest(vcpu); |
d7690175 | 6420 | else { |
f656ce01 | 6421 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 6422 | kvm_vcpu_block(vcpu); |
f656ce01 | 6423 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
66450a21 JK |
6424 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { |
6425 | kvm_apic_accept_events(vcpu); | |
09cec754 GN |
6426 | switch(vcpu->arch.mp_state) { |
6427 | case KVM_MP_STATE_HALTED: | |
6aef266c | 6428 | vcpu->arch.pv.pv_unhalted = false; |
d7690175 | 6429 | vcpu->arch.mp_state = |
09cec754 GN |
6430 | KVM_MP_STATE_RUNNABLE; |
6431 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 6432 | vcpu->arch.apf.halted = false; |
09cec754 | 6433 | break; |
66450a21 JK |
6434 | case KVM_MP_STATE_INIT_RECEIVED: |
6435 | break; | |
09cec754 GN |
6436 | default: |
6437 | r = -EINTR; | |
6438 | break; | |
6439 | } | |
6440 | } | |
d7690175 MT |
6441 | } |
6442 | ||
09cec754 GN |
6443 | if (r <= 0) |
6444 | break; | |
6445 | ||
6446 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6447 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6448 | kvm_inject_pending_timer_irqs(vcpu); | |
6449 | ||
851ba692 | 6450 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 6451 | r = -EINTR; |
851ba692 | 6452 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
6453 | ++vcpu->stat.request_irq_exits; |
6454 | } | |
af585b92 GN |
6455 | |
6456 | kvm_check_async_pf_completion(vcpu); | |
6457 | ||
09cec754 GN |
6458 | if (signal_pending(current)) { |
6459 | r = -EINTR; | |
851ba692 | 6460 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
6461 | ++vcpu->stat.signal_exits; |
6462 | } | |
6463 | if (need_resched()) { | |
f656ce01 | 6464 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 6465 | cond_resched(); |
f656ce01 | 6466 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6467 | } |
b6c7a5dc HB |
6468 | } |
6469 | ||
f656ce01 | 6470 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
6471 | |
6472 | return r; | |
6473 | } | |
6474 | ||
716d51ab GN |
6475 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
6476 | { | |
6477 | int r; | |
6478 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6479 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6480 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6481 | if (r != EMULATE_DONE) | |
6482 | return 0; | |
6483 | return 1; | |
6484 | } | |
6485 | ||
6486 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6487 | { | |
6488 | BUG_ON(!vcpu->arch.pio.count); | |
6489 | ||
6490 | return complete_emulated_io(vcpu); | |
6491 | } | |
6492 | ||
f78146b0 AK |
6493 | /* |
6494 | * Implements the following, as a state machine: | |
6495 | * | |
6496 | * read: | |
6497 | * for each fragment | |
87da7e66 XG |
6498 | * for each mmio piece in the fragment |
6499 | * write gpa, len | |
6500 | * exit | |
6501 | * copy data | |
f78146b0 AK |
6502 | * execute insn |
6503 | * | |
6504 | * write: | |
6505 | * for each fragment | |
87da7e66 XG |
6506 | * for each mmio piece in the fragment |
6507 | * write gpa, len | |
6508 | * copy data | |
6509 | * exit | |
f78146b0 | 6510 | */ |
716d51ab | 6511 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
6512 | { |
6513 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 6514 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6515 | unsigned len; |
5287f194 | 6516 | |
716d51ab | 6517 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6518 | |
716d51ab | 6519 | /* Complete previous fragment */ |
87da7e66 XG |
6520 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6521 | len = min(8u, frag->len); | |
716d51ab | 6522 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6523 | memcpy(frag->data, run->mmio.data, len); |
6524 | ||
6525 | if (frag->len <= 8) { | |
6526 | /* Switch to the next fragment. */ | |
6527 | frag++; | |
6528 | vcpu->mmio_cur_fragment++; | |
6529 | } else { | |
6530 | /* Go forward to the next mmio piece. */ | |
6531 | frag->data += len; | |
6532 | frag->gpa += len; | |
6533 | frag->len -= len; | |
6534 | } | |
6535 | ||
a08d3b3b | 6536 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 6537 | vcpu->mmio_needed = 0; |
0912c977 PB |
6538 | |
6539 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 6540 | if (vcpu->mmio_is_write) |
716d51ab GN |
6541 | return 1; |
6542 | vcpu->mmio_read_completed = 1; | |
6543 | return complete_emulated_io(vcpu); | |
6544 | } | |
87da7e66 | 6545 | |
716d51ab GN |
6546 | run->exit_reason = KVM_EXIT_MMIO; |
6547 | run->mmio.phys_addr = frag->gpa; | |
6548 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6549 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6550 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6551 | run->mmio.is_write = vcpu->mmio_is_write; |
6552 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6553 | return 0; | |
5287f194 AK |
6554 | } |
6555 | ||
716d51ab | 6556 | |
b6c7a5dc HB |
6557 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6558 | { | |
6559 | int r; | |
6560 | sigset_t sigsaved; | |
6561 | ||
e5c30142 AK |
6562 | if (!tsk_used_math(current) && init_fpu(current)) |
6563 | return -ENOMEM; | |
6564 | ||
ac9f6dc0 AK |
6565 | if (vcpu->sigset_active) |
6566 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6567 | ||
a4535290 | 6568 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6569 | kvm_vcpu_block(vcpu); |
66450a21 | 6570 | kvm_apic_accept_events(vcpu); |
d7690175 | 6571 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6572 | r = -EAGAIN; |
6573 | goto out; | |
b6c7a5dc HB |
6574 | } |
6575 | ||
b6c7a5dc | 6576 | /* re-sync apic's tpr */ |
eea1cff9 AP |
6577 | if (!irqchip_in_kernel(vcpu->kvm)) { |
6578 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
6579 | r = -EINVAL; | |
6580 | goto out; | |
6581 | } | |
6582 | } | |
b6c7a5dc | 6583 | |
716d51ab GN |
6584 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6585 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6586 | vcpu->arch.complete_userspace_io = NULL; | |
6587 | r = cui(vcpu); | |
6588 | if (r <= 0) | |
6589 | goto out; | |
6590 | } else | |
6591 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6592 | |
851ba692 | 6593 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
6594 | |
6595 | out: | |
f1d86e46 | 6596 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6597 | if (vcpu->sigset_active) |
6598 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6599 | ||
b6c7a5dc HB |
6600 | return r; |
6601 | } | |
6602 | ||
6603 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6604 | { | |
7ae441ea GN |
6605 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6606 | /* | |
6607 | * We are here if userspace calls get_regs() in the middle of | |
6608 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6609 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6610 | * that usually, but some bad designed PV devices (vmware |
6611 | * backdoor interface) need this to work | |
6612 | */ | |
dd856efa | 6613 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6614 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6615 | } | |
5fdbf976 MT |
6616 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6617 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6618 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6619 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6620 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6621 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6622 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6623 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6624 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6625 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6626 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6627 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6628 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6629 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6630 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6631 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6632 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6633 | #endif |
6634 | ||
5fdbf976 | 6635 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6636 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6637 | |
b6c7a5dc HB |
6638 | return 0; |
6639 | } | |
6640 | ||
6641 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6642 | { | |
7ae441ea GN |
6643 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
6644 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6645 | ||
5fdbf976 MT |
6646 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
6647 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6648 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6649 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6650 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6651 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6652 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6653 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 6654 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6655 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
6656 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6657 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6658 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6659 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6660 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6661 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6662 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
6663 | #endif |
6664 | ||
5fdbf976 | 6665 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 6666 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 6667 | |
b4f14abd JK |
6668 | vcpu->arch.exception.pending = false; |
6669 | ||
3842d135 AK |
6670 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6671 | ||
b6c7a5dc HB |
6672 | return 0; |
6673 | } | |
6674 | ||
b6c7a5dc HB |
6675 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
6676 | { | |
6677 | struct kvm_segment cs; | |
6678 | ||
3e6e0aab | 6679 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
6680 | *db = cs.db; |
6681 | *l = cs.l; | |
6682 | } | |
6683 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6684 | ||
6685 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6686 | struct kvm_sregs *sregs) | |
6687 | { | |
89a27f4d | 6688 | struct desc_ptr dt; |
b6c7a5dc | 6689 | |
3e6e0aab GT |
6690 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6691 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6692 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6693 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6694 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6695 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6696 | |
3e6e0aab GT |
6697 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6698 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
6699 | |
6700 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
6701 | sregs->idt.limit = dt.size; |
6702 | sregs->idt.base = dt.address; | |
b6c7a5dc | 6703 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
6704 | sregs->gdt.limit = dt.size; |
6705 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 6706 | |
4d4ec087 | 6707 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 6708 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 6709 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 6710 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 6711 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 6712 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
6713 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6714 | ||
923c61bb | 6715 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 6716 | |
36752c9b | 6717 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
6718 | set_bit(vcpu->arch.interrupt.nr, |
6719 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 6720 | |
b6c7a5dc HB |
6721 | return 0; |
6722 | } | |
6723 | ||
62d9f0db MT |
6724 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
6725 | struct kvm_mp_state *mp_state) | |
6726 | { | |
66450a21 | 6727 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
6728 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
6729 | vcpu->arch.pv.pv_unhalted) | |
6730 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
6731 | else | |
6732 | mp_state->mp_state = vcpu->arch.mp_state; | |
6733 | ||
62d9f0db MT |
6734 | return 0; |
6735 | } | |
6736 | ||
6737 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
6738 | struct kvm_mp_state *mp_state) | |
6739 | { | |
66450a21 JK |
6740 | if (!kvm_vcpu_has_lapic(vcpu) && |
6741 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
6742 | return -EINVAL; | |
6743 | ||
6744 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
6745 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
6746 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
6747 | } else | |
6748 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 6749 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
6750 | return 0; |
6751 | } | |
6752 | ||
7f3d35fd KW |
6753 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
6754 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 6755 | { |
9d74191a | 6756 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 6757 | int ret; |
e01c2426 | 6758 | |
8ec4722d | 6759 | init_emulate_ctxt(vcpu); |
c697518a | 6760 | |
7f3d35fd | 6761 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 6762 | has_error_code, error_code); |
c697518a | 6763 | |
c697518a | 6764 | if (ret) |
19d04437 | 6765 | return EMULATE_FAIL; |
37817f29 | 6766 | |
9d74191a TY |
6767 | kvm_rip_write(vcpu, ctxt->eip); |
6768 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 6769 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 6770 | return EMULATE_DONE; |
37817f29 IE |
6771 | } |
6772 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
6773 | ||
b6c7a5dc HB |
6774 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
6775 | struct kvm_sregs *sregs) | |
6776 | { | |
58cb628d | 6777 | struct msr_data apic_base_msr; |
b6c7a5dc | 6778 | int mmu_reset_needed = 0; |
63f42e02 | 6779 | int pending_vec, max_bits, idx; |
89a27f4d | 6780 | struct desc_ptr dt; |
b6c7a5dc | 6781 | |
6d1068b3 PM |
6782 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
6783 | return -EINVAL; | |
6784 | ||
89a27f4d GN |
6785 | dt.size = sregs->idt.limit; |
6786 | dt.address = sregs->idt.base; | |
b6c7a5dc | 6787 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
6788 | dt.size = sregs->gdt.limit; |
6789 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
6790 | kvm_x86_ops->set_gdt(vcpu, &dt); |
6791 | ||
ad312c7c | 6792 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 6793 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 6794 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 6795 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 6796 | |
2d3ad1f4 | 6797 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 6798 | |
f6801dff | 6799 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 6800 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
58cb628d JK |
6801 | apic_base_msr.data = sregs->apic_base; |
6802 | apic_base_msr.host_initiated = true; | |
6803 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
b6c7a5dc | 6804 | |
4d4ec087 | 6805 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 6806 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 6807 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 6808 | |
fc78f519 | 6809 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 6810 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 6811 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 6812 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
6813 | |
6814 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 6815 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 6816 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
6817 | mmu_reset_needed = 1; |
6818 | } | |
63f42e02 | 6819 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
6820 | |
6821 | if (mmu_reset_needed) | |
6822 | kvm_mmu_reset_context(vcpu); | |
6823 | ||
a50abc3b | 6824 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
6825 | pending_vec = find_first_bit( |
6826 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6827 | if (pending_vec < max_bits) { | |
66fd3f7f | 6828 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 6829 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
6830 | } |
6831 | ||
3e6e0aab GT |
6832 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6833 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6834 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6835 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6836 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6837 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6838 | |
3e6e0aab GT |
6839 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6840 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 6841 | |
5f0269f5 ME |
6842 | update_cr8_intercept(vcpu); |
6843 | ||
9c3e4aab | 6844 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 6845 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 6846 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 6847 | !is_protmode(vcpu)) |
9c3e4aab MT |
6848 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
6849 | ||
3842d135 AK |
6850 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6851 | ||
b6c7a5dc HB |
6852 | return 0; |
6853 | } | |
6854 | ||
d0bfb940 JK |
6855 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
6856 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 6857 | { |
355be0b9 | 6858 | unsigned long rflags; |
ae675ef0 | 6859 | int i, r; |
b6c7a5dc | 6860 | |
4f926bf2 JK |
6861 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
6862 | r = -EBUSY; | |
6863 | if (vcpu->arch.exception.pending) | |
2122ff5e | 6864 | goto out; |
4f926bf2 JK |
6865 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
6866 | kvm_queue_exception(vcpu, DB_VECTOR); | |
6867 | else | |
6868 | kvm_queue_exception(vcpu, BP_VECTOR); | |
6869 | } | |
6870 | ||
91586a3b JK |
6871 | /* |
6872 | * Read rflags as long as potentially injected trace flags are still | |
6873 | * filtered out. | |
6874 | */ | |
6875 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
6876 | |
6877 | vcpu->guest_debug = dbg->control; | |
6878 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
6879 | vcpu->guest_debug = 0; | |
6880 | ||
6881 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
6882 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
6883 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 6884 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
6885 | } else { |
6886 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6887 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 6888 | } |
c8639010 | 6889 | kvm_update_dr7(vcpu); |
ae675ef0 | 6890 | |
f92653ee JK |
6891 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
6892 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
6893 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 6894 | |
91586a3b JK |
6895 | /* |
6896 | * Trigger an rflags update that will inject or remove the trace | |
6897 | * flags. | |
6898 | */ | |
6899 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 6900 | |
c8639010 | 6901 | kvm_x86_ops->update_db_bp_intercept(vcpu); |
b6c7a5dc | 6902 | |
4f926bf2 | 6903 | r = 0; |
d0bfb940 | 6904 | |
2122ff5e | 6905 | out: |
b6c7a5dc HB |
6906 | |
6907 | return r; | |
6908 | } | |
6909 | ||
8b006791 ZX |
6910 | /* |
6911 | * Translate a guest virtual address to a guest physical address. | |
6912 | */ | |
6913 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
6914 | struct kvm_translation *tr) | |
6915 | { | |
6916 | unsigned long vaddr = tr->linear_address; | |
6917 | gpa_t gpa; | |
f656ce01 | 6918 | int idx; |
8b006791 | 6919 | |
f656ce01 | 6920 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 6921 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 6922 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
6923 | tr->physical_address = gpa; |
6924 | tr->valid = gpa != UNMAPPED_GVA; | |
6925 | tr->writeable = 1; | |
6926 | tr->usermode = 0; | |
8b006791 ZX |
6927 | |
6928 | return 0; | |
6929 | } | |
6930 | ||
d0752060 HB |
6931 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
6932 | { | |
98918833 SY |
6933 | struct i387_fxsave_struct *fxsave = |
6934 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6935 | |
d0752060 HB |
6936 | memcpy(fpu->fpr, fxsave->st_space, 128); |
6937 | fpu->fcw = fxsave->cwd; | |
6938 | fpu->fsw = fxsave->swd; | |
6939 | fpu->ftwx = fxsave->twd; | |
6940 | fpu->last_opcode = fxsave->fop; | |
6941 | fpu->last_ip = fxsave->rip; | |
6942 | fpu->last_dp = fxsave->rdp; | |
6943 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
6944 | ||
d0752060 HB |
6945 | return 0; |
6946 | } | |
6947 | ||
6948 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
6949 | { | |
98918833 SY |
6950 | struct i387_fxsave_struct *fxsave = |
6951 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6952 | |
d0752060 HB |
6953 | memcpy(fxsave->st_space, fpu->fpr, 128); |
6954 | fxsave->cwd = fpu->fcw; | |
6955 | fxsave->swd = fpu->fsw; | |
6956 | fxsave->twd = fpu->ftwx; | |
6957 | fxsave->fop = fpu->last_opcode; | |
6958 | fxsave->rip = fpu->last_ip; | |
6959 | fxsave->rdp = fpu->last_dp; | |
6960 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
6961 | ||
d0752060 HB |
6962 | return 0; |
6963 | } | |
6964 | ||
10ab25cd | 6965 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 6966 | { |
10ab25cd JK |
6967 | int err; |
6968 | ||
6969 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
6970 | if (err) | |
6971 | return err; | |
6972 | ||
98918833 | 6973 | fpu_finit(&vcpu->arch.guest_fpu); |
df1daba7 PB |
6974 | if (cpu_has_xsaves) |
6975 | vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = | |
6976 | host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
d0752060 | 6977 | |
2acf923e DC |
6978 | /* |
6979 | * Ensure guest xcr0 is valid for loading | |
6980 | */ | |
6981 | vcpu->arch.xcr0 = XSTATE_FP; | |
6982 | ||
ad312c7c | 6983 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
6984 | |
6985 | return 0; | |
d0752060 HB |
6986 | } |
6987 | EXPORT_SYMBOL_GPL(fx_init); | |
6988 | ||
98918833 SY |
6989 | static void fx_free(struct kvm_vcpu *vcpu) |
6990 | { | |
6991 | fpu_free(&vcpu->arch.guest_fpu); | |
6992 | } | |
6993 | ||
d0752060 HB |
6994 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
6995 | { | |
2608d7a1 | 6996 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
6997 | return; |
6998 | ||
2acf923e DC |
6999 | /* |
7000 | * Restore all possible states in the guest, | |
7001 | * and assume host would use all available bits. | |
7002 | * Guest xcr0 would be loaded later. | |
7003 | */ | |
7004 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 7005 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 7006 | __kernel_fpu_begin(); |
98918833 | 7007 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 7008 | trace_kvm_fpu(1); |
d0752060 | 7009 | } |
d0752060 HB |
7010 | |
7011 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
7012 | { | |
2acf923e DC |
7013 | kvm_put_guest_xcr0(vcpu); |
7014 | ||
d0752060 HB |
7015 | if (!vcpu->guest_fpu_loaded) |
7016 | return; | |
7017 | ||
7018 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 7019 | fpu_save_init(&vcpu->arch.guest_fpu); |
b1a74bf8 | 7020 | __kernel_fpu_end(); |
f096ed85 | 7021 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 7022 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 7023 | trace_kvm_fpu(0); |
d0752060 | 7024 | } |
e9b11c17 ZX |
7025 | |
7026 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
7027 | { | |
12f9a48f | 7028 | kvmclock_reset(vcpu); |
7f1ea208 | 7029 | |
f5f48ee1 | 7030 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 7031 | fx_free(vcpu); |
e9b11c17 ZX |
7032 | kvm_x86_ops->vcpu_free(vcpu); |
7033 | } | |
7034 | ||
7035 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
7036 | unsigned int id) | |
7037 | { | |
6755bae8 ZA |
7038 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
7039 | printk_once(KERN_WARNING | |
7040 | "kvm: SMP vm created on host with unstable TSC; " | |
7041 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
7042 | return kvm_x86_ops->vcpu_create(kvm, id); |
7043 | } | |
e9b11c17 | 7044 | |
26e5215f AK |
7045 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
7046 | { | |
7047 | int r; | |
e9b11c17 | 7048 | |
0bed3b56 | 7049 | vcpu->arch.mtrr_state.have_fixed = 1; |
9fc77441 MT |
7050 | r = vcpu_load(vcpu); |
7051 | if (r) | |
7052 | return r; | |
57f252f2 | 7053 | kvm_vcpu_reset(vcpu); |
8a3c1a33 | 7054 | kvm_mmu_setup(vcpu); |
e9b11c17 | 7055 | vcpu_put(vcpu); |
e9b11c17 | 7056 | |
26e5215f | 7057 | return r; |
e9b11c17 ZX |
7058 | } |
7059 | ||
31928aa5 | 7060 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 7061 | { |
8fe8ab46 | 7062 | struct msr_data msr; |
332967a3 | 7063 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 7064 | |
31928aa5 DD |
7065 | if (vcpu_load(vcpu)) |
7066 | return; | |
8fe8ab46 WA |
7067 | msr.data = 0x0; |
7068 | msr.index = MSR_IA32_TSC; | |
7069 | msr.host_initiated = true; | |
7070 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
7071 | vcpu_put(vcpu); |
7072 | ||
332967a3 AJ |
7073 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
7074 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
7075 | } |
7076 | ||
d40ccc62 | 7077 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 7078 | { |
9fc77441 | 7079 | int r; |
344d9588 GN |
7080 | vcpu->arch.apf.msr_val = 0; |
7081 | ||
9fc77441 MT |
7082 | r = vcpu_load(vcpu); |
7083 | BUG_ON(r); | |
e9b11c17 ZX |
7084 | kvm_mmu_unload(vcpu); |
7085 | vcpu_put(vcpu); | |
7086 | ||
98918833 | 7087 | fx_free(vcpu); |
e9b11c17 ZX |
7088 | kvm_x86_ops->vcpu_free(vcpu); |
7089 | } | |
7090 | ||
66450a21 | 7091 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu) |
e9b11c17 | 7092 | { |
7460fb4a AK |
7093 | atomic_set(&vcpu->arch.nmi_queued, 0); |
7094 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 7095 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
7096 | kvm_clear_interrupt_queue(vcpu); |
7097 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 7098 | |
42dbaa5a | 7099 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
6f43ed01 | 7100 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 7101 | kvm_update_dr6(vcpu); |
42dbaa5a | 7102 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 7103 | kvm_update_dr7(vcpu); |
42dbaa5a | 7104 | |
3842d135 | 7105 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 7106 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 7107 | vcpu->arch.st.msr_val = 0; |
3842d135 | 7108 | |
12f9a48f GC |
7109 | kvmclock_reset(vcpu); |
7110 | ||
af585b92 GN |
7111 | kvm_clear_async_pf_completion_queue(vcpu); |
7112 | kvm_async_pf_hash_reset(vcpu); | |
7113 | vcpu->arch.apf.halted = false; | |
3842d135 | 7114 | |
f5132b01 GN |
7115 | kvm_pmu_reset(vcpu); |
7116 | ||
66f7b72e JS |
7117 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
7118 | vcpu->arch.regs_avail = ~0; | |
7119 | vcpu->arch.regs_dirty = ~0; | |
7120 | ||
57f252f2 | 7121 | kvm_x86_ops->vcpu_reset(vcpu); |
e9b11c17 ZX |
7122 | } |
7123 | ||
2b4a273b | 7124 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
7125 | { |
7126 | struct kvm_segment cs; | |
7127 | ||
7128 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7129 | cs.selector = vector << 8; | |
7130 | cs.base = vector << 12; | |
7131 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7132 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
7133 | } |
7134 | ||
13a34e06 | 7135 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 7136 | { |
ca84d1a2 ZA |
7137 | struct kvm *kvm; |
7138 | struct kvm_vcpu *vcpu; | |
7139 | int i; | |
0dd6a6ed ZA |
7140 | int ret; |
7141 | u64 local_tsc; | |
7142 | u64 max_tsc = 0; | |
7143 | bool stable, backwards_tsc = false; | |
18863bdd AK |
7144 | |
7145 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 7146 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
7147 | if (ret != 0) |
7148 | return ret; | |
7149 | ||
7150 | local_tsc = native_read_tsc(); | |
7151 | stable = !check_tsc_unstable(); | |
7152 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7153 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7154 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 7155 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7156 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
7157 | backwards_tsc = true; | |
7158 | if (vcpu->arch.last_host_tsc > max_tsc) | |
7159 | max_tsc = vcpu->arch.last_host_tsc; | |
7160 | } | |
7161 | } | |
7162 | } | |
7163 | ||
7164 | /* | |
7165 | * Sometimes, even reliable TSCs go backwards. This happens on | |
7166 | * platforms that reset TSC during suspend or hibernate actions, but | |
7167 | * maintain synchronization. We must compensate. Fortunately, we can | |
7168 | * detect that condition here, which happens early in CPU bringup, | |
7169 | * before any KVM threads can be running. Unfortunately, we can't | |
7170 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
7171 | * enough into CPU bringup that we know how much real time has actually | |
7172 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
7173 | * variables that haven't been updated yet. | |
7174 | * | |
7175 | * So we simply find the maximum observed TSC above, then record the | |
7176 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
7177 | * the adjustment will be applied. Note that we accumulate | |
7178 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
7179 | * gets a chance to run again. In the event that no KVM threads get a | |
7180 | * chance to run, we will miss the entire elapsed period, as we'll have | |
7181 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
7182 | * loose cycle time. This isn't too big a deal, since the loss will be | |
7183 | * uniform across all VCPUs (not to mention the scenario is extremely | |
7184 | * unlikely). It is possible that a second hibernate recovery happens | |
7185 | * much faster than a first, causing the observed TSC here to be | |
7186 | * smaller; this would require additional padding adjustment, which is | |
7187 | * why we set last_host_tsc to the local tsc observed here. | |
7188 | * | |
7189 | * N.B. - this code below runs only on platforms with reliable TSC, | |
7190 | * as that is the only way backwards_tsc is set above. Also note | |
7191 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
7192 | * have the same delta_cyc adjustment applied if backwards_tsc | |
7193 | * is detected. Note further, this adjustment is only done once, | |
7194 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
7195 | * called multiple times (one for each physical CPU bringup). | |
7196 | * | |
4a969980 | 7197 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
7198 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
7199 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
7200 | * guarantee that they stay in perfect synchronization. | |
7201 | */ | |
7202 | if (backwards_tsc) { | |
7203 | u64 delta_cyc = max_tsc - local_tsc; | |
16a96021 | 7204 | backwards_tsc_observed = true; |
0dd6a6ed ZA |
7205 | list_for_each_entry(kvm, &vm_list, vm_list) { |
7206 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7207 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
7208 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 7209 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7210 | } |
7211 | ||
7212 | /* | |
7213 | * We have to disable TSC offset matching.. if you were | |
7214 | * booting a VM while issuing an S4 host suspend.... | |
7215 | * you may have some problem. Solving this issue is | |
7216 | * left as an exercise to the reader. | |
7217 | */ | |
7218 | kvm->arch.last_tsc_nsec = 0; | |
7219 | kvm->arch.last_tsc_write = 0; | |
7220 | } | |
7221 | ||
7222 | } | |
7223 | return 0; | |
e9b11c17 ZX |
7224 | } |
7225 | ||
13a34e06 | 7226 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 7227 | { |
13a34e06 RK |
7228 | kvm_x86_ops->hardware_disable(); |
7229 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
7230 | } |
7231 | ||
7232 | int kvm_arch_hardware_setup(void) | |
7233 | { | |
7234 | return kvm_x86_ops->hardware_setup(); | |
7235 | } | |
7236 | ||
7237 | void kvm_arch_hardware_unsetup(void) | |
7238 | { | |
7239 | kvm_x86_ops->hardware_unsetup(); | |
7240 | } | |
7241 | ||
7242 | void kvm_arch_check_processor_compat(void *rtn) | |
7243 | { | |
7244 | kvm_x86_ops->check_processor_compatibility(rtn); | |
7245 | } | |
7246 | ||
3e515705 AK |
7247 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
7248 | { | |
7249 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
7250 | } | |
7251 | ||
54e9818f GN |
7252 | struct static_key kvm_no_apic_vcpu __read_mostly; |
7253 | ||
e9b11c17 ZX |
7254 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
7255 | { | |
7256 | struct page *page; | |
7257 | struct kvm *kvm; | |
7258 | int r; | |
7259 | ||
7260 | BUG_ON(vcpu->kvm == NULL); | |
7261 | kvm = vcpu->kvm; | |
7262 | ||
6aef266c | 7263 | vcpu->arch.pv.pv_unhalted = false; |
9aabc88f | 7264 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
c5af89b6 | 7265 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 7266 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 7267 | else |
a4535290 | 7268 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
7269 | |
7270 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
7271 | if (!page) { | |
7272 | r = -ENOMEM; | |
7273 | goto fail; | |
7274 | } | |
ad312c7c | 7275 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 7276 | |
cc578287 | 7277 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 7278 | |
e9b11c17 ZX |
7279 | r = kvm_mmu_create(vcpu); |
7280 | if (r < 0) | |
7281 | goto fail_free_pio_data; | |
7282 | ||
7283 | if (irqchip_in_kernel(kvm)) { | |
7284 | r = kvm_create_lapic(vcpu); | |
7285 | if (r < 0) | |
7286 | goto fail_mmu_destroy; | |
54e9818f GN |
7287 | } else |
7288 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 7289 | |
890ca9ae HY |
7290 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
7291 | GFP_KERNEL); | |
7292 | if (!vcpu->arch.mce_banks) { | |
7293 | r = -ENOMEM; | |
443c39bc | 7294 | goto fail_free_lapic; |
890ca9ae HY |
7295 | } |
7296 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
7297 | ||
f1797359 WY |
7298 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
7299 | r = -ENOMEM; | |
f5f48ee1 | 7300 | goto fail_free_mce_banks; |
f1797359 | 7301 | } |
f5f48ee1 | 7302 | |
66f7b72e JS |
7303 | r = fx_init(vcpu); |
7304 | if (r) | |
7305 | goto fail_free_wbinvd_dirty_mask; | |
7306 | ||
ba904635 | 7307 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 7308 | vcpu->arch.pv_time_enabled = false; |
d7876f1b PB |
7309 | |
7310 | vcpu->arch.guest_supported_xcr0 = 0; | |
4344ee98 | 7311 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 7312 | |
af585b92 | 7313 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 7314 | kvm_pmu_init(vcpu); |
af585b92 | 7315 | |
e9b11c17 | 7316 | return 0; |
66f7b72e JS |
7317 | fail_free_wbinvd_dirty_mask: |
7318 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
7319 | fail_free_mce_banks: |
7320 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
7321 | fail_free_lapic: |
7322 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
7323 | fail_mmu_destroy: |
7324 | kvm_mmu_destroy(vcpu); | |
7325 | fail_free_pio_data: | |
ad312c7c | 7326 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
7327 | fail: |
7328 | return r; | |
7329 | } | |
7330 | ||
7331 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
7332 | { | |
f656ce01 MT |
7333 | int idx; |
7334 | ||
f5132b01 | 7335 | kvm_pmu_destroy(vcpu); |
36cb93fd | 7336 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 7337 | kvm_free_lapic(vcpu); |
f656ce01 | 7338 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 7339 | kvm_mmu_destroy(vcpu); |
f656ce01 | 7340 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 7341 | free_page((unsigned long)vcpu->arch.pio_data); |
54e9818f GN |
7342 | if (!irqchip_in_kernel(vcpu->kvm)) |
7343 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 | 7344 | } |
d19a9cd2 | 7345 | |
e790d9ef RK |
7346 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
7347 | { | |
ae97a3b8 | 7348 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
7349 | } |
7350 | ||
e08b9637 | 7351 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 7352 | { |
e08b9637 CO |
7353 | if (type) |
7354 | return -EINVAL; | |
7355 | ||
6ef768fa | 7356 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 7357 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 7358 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 7359 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 7360 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 7361 | |
5550af4d SY |
7362 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
7363 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
7364 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
7365 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7366 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 7367 | |
038f8c11 | 7368 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 7369 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
7370 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
7371 | ||
7372 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 7373 | |
7e44e449 | 7374 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 7375 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 7376 | |
d89f5eff | 7377 | return 0; |
d19a9cd2 ZX |
7378 | } |
7379 | ||
7380 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7381 | { | |
9fc77441 MT |
7382 | int r; |
7383 | r = vcpu_load(vcpu); | |
7384 | BUG_ON(r); | |
d19a9cd2 ZX |
7385 | kvm_mmu_unload(vcpu); |
7386 | vcpu_put(vcpu); | |
7387 | } | |
7388 | ||
7389 | static void kvm_free_vcpus(struct kvm *kvm) | |
7390 | { | |
7391 | unsigned int i; | |
988a2cae | 7392 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
7393 | |
7394 | /* | |
7395 | * Unpin any mmu pages first. | |
7396 | */ | |
af585b92 GN |
7397 | kvm_for_each_vcpu(i, vcpu, kvm) { |
7398 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 7399 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 7400 | } |
988a2cae GN |
7401 | kvm_for_each_vcpu(i, vcpu, kvm) |
7402 | kvm_arch_vcpu_free(vcpu); | |
7403 | ||
7404 | mutex_lock(&kvm->lock); | |
7405 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7406 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 7407 | |
988a2cae GN |
7408 | atomic_set(&kvm->online_vcpus, 0); |
7409 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
7410 | } |
7411 | ||
ad8ba2cd SY |
7412 | void kvm_arch_sync_events(struct kvm *kvm) |
7413 | { | |
332967a3 | 7414 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 7415 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
ba4cef31 | 7416 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 7417 | kvm_free_pit(kvm); |
ad8ba2cd SY |
7418 | } |
7419 | ||
d19a9cd2 ZX |
7420 | void kvm_arch_destroy_vm(struct kvm *kvm) |
7421 | { | |
27469d29 AH |
7422 | if (current->mm == kvm->mm) { |
7423 | /* | |
7424 | * Free memory regions allocated on behalf of userspace, | |
7425 | * unless the the memory map has changed due to process exit | |
7426 | * or fd copying. | |
7427 | */ | |
7428 | struct kvm_userspace_memory_region mem; | |
7429 | memset(&mem, 0, sizeof(mem)); | |
7430 | mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
7431 | kvm_set_memory_region(kvm, &mem); | |
7432 | ||
7433 | mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
7434 | kvm_set_memory_region(kvm, &mem); | |
7435 | ||
7436 | mem.slot = TSS_PRIVATE_MEMSLOT; | |
7437 | kvm_set_memory_region(kvm, &mem); | |
7438 | } | |
6eb55818 | 7439 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
7440 | kfree(kvm->arch.vpic); |
7441 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 7442 | kvm_free_vcpus(kvm); |
1e08ec4a | 7443 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 7444 | } |
0de10343 | 7445 | |
5587027c | 7446 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
7447 | struct kvm_memory_slot *dont) |
7448 | { | |
7449 | int i; | |
7450 | ||
d89cc617 TY |
7451 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7452 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 7453 | kvfree(free->arch.rmap[i]); |
d89cc617 | 7454 | free->arch.rmap[i] = NULL; |
77d11309 | 7455 | } |
d89cc617 TY |
7456 | if (i == 0) |
7457 | continue; | |
7458 | ||
7459 | if (!dont || free->arch.lpage_info[i - 1] != | |
7460 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 7461 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 7462 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7463 | } |
7464 | } | |
7465 | } | |
7466 | ||
5587027c AK |
7467 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
7468 | unsigned long npages) | |
db3fe4eb TY |
7469 | { |
7470 | int i; | |
7471 | ||
d89cc617 | 7472 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
7473 | unsigned long ugfn; |
7474 | int lpages; | |
d89cc617 | 7475 | int level = i + 1; |
db3fe4eb TY |
7476 | |
7477 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7478 | slot->base_gfn, level) + 1; | |
7479 | ||
d89cc617 TY |
7480 | slot->arch.rmap[i] = |
7481 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7482 | if (!slot->arch.rmap[i]) | |
77d11309 | 7483 | goto out_free; |
d89cc617 TY |
7484 | if (i == 0) |
7485 | continue; | |
77d11309 | 7486 | |
d89cc617 TY |
7487 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
7488 | sizeof(*slot->arch.lpage_info[i - 1])); | |
7489 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
7490 | goto out_free; |
7491 | ||
7492 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 7493 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 7494 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 7495 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
7496 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
7497 | /* | |
7498 | * If the gfn and userspace address are not aligned wrt each | |
7499 | * other, or if explicitly asked to, disable large page | |
7500 | * support for this slot | |
7501 | */ | |
7502 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7503 | !kvm_largepages_enabled()) { | |
7504 | unsigned long j; | |
7505 | ||
7506 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 7507 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
7508 | } |
7509 | } | |
7510 | ||
7511 | return 0; | |
7512 | ||
7513 | out_free: | |
d89cc617 | 7514 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 7515 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
7516 | slot->arch.rmap[i] = NULL; |
7517 | if (i == 0) | |
7518 | continue; | |
7519 | ||
548ef284 | 7520 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 7521 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7522 | } |
7523 | return -ENOMEM; | |
7524 | } | |
7525 | ||
e59dbe09 TY |
7526 | void kvm_arch_memslots_updated(struct kvm *kvm) |
7527 | { | |
e6dff7d1 TY |
7528 | /* |
7529 | * memslots->generation has been incremented. | |
7530 | * mmio generation may have reached its maximum value. | |
7531 | */ | |
7532 | kvm_mmu_invalidate_mmio_sptes(kvm); | |
e59dbe09 TY |
7533 | } |
7534 | ||
f7784b8e MT |
7535 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
7536 | struct kvm_memory_slot *memslot, | |
f7784b8e | 7537 | struct kvm_userspace_memory_region *mem, |
7b6195a9 | 7538 | enum kvm_mr_change change) |
0de10343 | 7539 | { |
7a905b14 TY |
7540 | /* |
7541 | * Only private memory slots need to be mapped here since | |
7542 | * KVM_SET_MEMORY_REGION ioctl is no longer supported. | |
0de10343 | 7543 | */ |
7b6195a9 | 7544 | if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { |
7a905b14 | 7545 | unsigned long userspace_addr; |
604b38ac | 7546 | |
7a905b14 TY |
7547 | /* |
7548 | * MAP_SHARED to prevent internal slot pages from being moved | |
7549 | * by fork()/COW. | |
7550 | */ | |
7b6195a9 | 7551 | userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, |
7a905b14 TY |
7552 | PROT_READ | PROT_WRITE, |
7553 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
0de10343 | 7554 | |
7a905b14 TY |
7555 | if (IS_ERR((void *)userspace_addr)) |
7556 | return PTR_ERR((void *)userspace_addr); | |
604b38ac | 7557 | |
7a905b14 | 7558 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
7559 | } |
7560 | ||
f7784b8e MT |
7561 | return 0; |
7562 | } | |
7563 | ||
88178fd4 KH |
7564 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
7565 | struct kvm_memory_slot *new) | |
7566 | { | |
7567 | /* Still write protect RO slot */ | |
7568 | if (new->flags & KVM_MEM_READONLY) { | |
7569 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7570 | return; | |
7571 | } | |
7572 | ||
7573 | /* | |
7574 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
7575 | * | |
7576 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
7577 | * | |
7578 | * - KVM_MR_CREATE with dirty logging is disabled | |
7579 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
7580 | * | |
7581 | * The reason is, in case of PML, we need to set D-bit for any slots | |
7582 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
7583 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
7584 | * guarantees leaving PML enabled during guest's lifetime won't have | |
7585 | * any additonal overhead from PML when guest is running with dirty | |
7586 | * logging disabled for memory slots. | |
7587 | * | |
7588 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
7589 | * to dirty logging mode. | |
7590 | * | |
7591 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
7592 | * | |
7593 | * In case of write protect: | |
7594 | * | |
7595 | * Write protect all pages for dirty logging. | |
7596 | * | |
7597 | * All the sptes including the large sptes which point to this | |
7598 | * slot are set to readonly. We can not create any new large | |
7599 | * spte on this slot until the end of the logging. | |
7600 | * | |
7601 | * See the comments in fast_page_fault(). | |
7602 | */ | |
7603 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
7604 | if (kvm_x86_ops->slot_enable_log_dirty) | |
7605 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
7606 | else | |
7607 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7608 | } else { | |
7609 | if (kvm_x86_ops->slot_disable_log_dirty) | |
7610 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
7611 | } | |
7612 | } | |
7613 | ||
f7784b8e MT |
7614 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
7615 | struct kvm_userspace_memory_region *mem, | |
8482644a TY |
7616 | const struct kvm_memory_slot *old, |
7617 | enum kvm_mr_change change) | |
f7784b8e | 7618 | { |
1c91cad4 | 7619 | struct kvm_memory_slot *new; |
8482644a | 7620 | int nr_mmu_pages = 0; |
f7784b8e | 7621 | |
8482644a | 7622 | if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { |
f7784b8e MT |
7623 | int ret; |
7624 | ||
8482644a TY |
7625 | ret = vm_munmap(old->userspace_addr, |
7626 | old->npages * PAGE_SIZE); | |
f7784b8e MT |
7627 | if (ret < 0) |
7628 | printk(KERN_WARNING | |
7629 | "kvm_vm_ioctl_set_memory_region: " | |
7630 | "failed to munmap memory\n"); | |
7631 | } | |
7632 | ||
48c0e4e9 XG |
7633 | if (!kvm->arch.n_requested_mmu_pages) |
7634 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
7635 | ||
48c0e4e9 | 7636 | if (nr_mmu_pages) |
0de10343 | 7637 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
1c91cad4 KH |
7638 | |
7639 | /* It's OK to get 'new' slot here as it has already been installed */ | |
7640 | new = id_to_memslot(kvm->memslots, mem->slot); | |
7641 | ||
c972f3b1 | 7642 | /* |
88178fd4 | 7643 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 7644 | * |
88178fd4 KH |
7645 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
7646 | * been zapped so no dirty logging staff is needed for old slot. For | |
7647 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
7648 | * new and it's also covered when dealing with the new slot. | |
c972f3b1 | 7649 | */ |
88178fd4 KH |
7650 | if (change != KVM_MR_DELETE) |
7651 | kvm_mmu_slot_apply_flags(kvm, new); | |
0de10343 | 7652 | } |
1d737c8a | 7653 | |
2df72e9b | 7654 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 7655 | { |
6ca18b69 | 7656 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
7657 | } |
7658 | ||
2df72e9b MT |
7659 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
7660 | struct kvm_memory_slot *slot) | |
7661 | { | |
6ca18b69 | 7662 | kvm_mmu_invalidate_zap_all_pages(kvm); |
2df72e9b MT |
7663 | } |
7664 | ||
1d737c8a ZX |
7665 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
7666 | { | |
b6b8a145 JK |
7667 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
7668 | kvm_x86_ops->check_nested_events(vcpu, false); | |
7669 | ||
af585b92 GN |
7670 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
7671 | !vcpu->arch.apf.halted) | |
7672 | || !list_empty_careful(&vcpu->async_pf.done) | |
66450a21 | 7673 | || kvm_apic_has_events(vcpu) |
6aef266c | 7674 | || vcpu->arch.pv.pv_unhalted |
7460fb4a | 7675 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
7676 | (kvm_arch_interrupt_allowed(vcpu) && |
7677 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 7678 | } |
5736199a | 7679 | |
b6d33834 | 7680 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 7681 | { |
b6d33834 | 7682 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 7683 | } |
78646121 GN |
7684 | |
7685 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
7686 | { | |
7687 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
7688 | } | |
229456fc | 7689 | |
82b32774 | 7690 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 7691 | { |
82b32774 NA |
7692 | if (is_64_bit_mode(vcpu)) |
7693 | return kvm_rip_read(vcpu); | |
7694 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
7695 | kvm_rip_read(vcpu)); | |
7696 | } | |
7697 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 7698 | |
82b32774 NA |
7699 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
7700 | { | |
7701 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
7702 | } |
7703 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
7704 | ||
94fe45da JK |
7705 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
7706 | { | |
7707 | unsigned long rflags; | |
7708 | ||
7709 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
7710 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 7711 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
7712 | return rflags; |
7713 | } | |
7714 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
7715 | ||
6addfc42 | 7716 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
7717 | { |
7718 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 7719 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 7720 | rflags |= X86_EFLAGS_TF; |
94fe45da | 7721 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
7722 | } |
7723 | ||
7724 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
7725 | { | |
7726 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 7727 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
7728 | } |
7729 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
7730 | ||
56028d08 GN |
7731 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
7732 | { | |
7733 | int r; | |
7734 | ||
fb67e14f | 7735 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 7736 | work->wakeup_all) |
56028d08 GN |
7737 | return; |
7738 | ||
7739 | r = kvm_mmu_reload(vcpu); | |
7740 | if (unlikely(r)) | |
7741 | return; | |
7742 | ||
fb67e14f XG |
7743 | if (!vcpu->arch.mmu.direct_map && |
7744 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
7745 | return; | |
7746 | ||
56028d08 GN |
7747 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
7748 | } | |
7749 | ||
af585b92 GN |
7750 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
7751 | { | |
7752 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
7753 | } | |
7754 | ||
7755 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
7756 | { | |
7757 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
7758 | } | |
7759 | ||
7760 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7761 | { | |
7762 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7763 | ||
7764 | while (vcpu->arch.apf.gfns[key] != ~0) | |
7765 | key = kvm_async_pf_next_probe(key); | |
7766 | ||
7767 | vcpu->arch.apf.gfns[key] = gfn; | |
7768 | } | |
7769 | ||
7770 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7771 | { | |
7772 | int i; | |
7773 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7774 | ||
7775 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
7776 | (vcpu->arch.apf.gfns[key] != gfn && |
7777 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
7778 | key = kvm_async_pf_next_probe(key); |
7779 | ||
7780 | return key; | |
7781 | } | |
7782 | ||
7783 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7784 | { | |
7785 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
7786 | } | |
7787 | ||
7788 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7789 | { | |
7790 | u32 i, j, k; | |
7791 | ||
7792 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
7793 | while (true) { | |
7794 | vcpu->arch.apf.gfns[i] = ~0; | |
7795 | do { | |
7796 | j = kvm_async_pf_next_probe(j); | |
7797 | if (vcpu->arch.apf.gfns[j] == ~0) | |
7798 | return; | |
7799 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
7800 | /* | |
7801 | * k lies cyclically in ]i,j] | |
7802 | * | i.k.j | | |
7803 | * |....j i.k.| or |.k..j i...| | |
7804 | */ | |
7805 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
7806 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
7807 | i = j; | |
7808 | } | |
7809 | } | |
7810 | ||
7c90705b GN |
7811 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
7812 | { | |
7813 | ||
7814 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
7815 | sizeof(val)); | |
7816 | } | |
7817 | ||
af585b92 GN |
7818 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
7819 | struct kvm_async_pf *work) | |
7820 | { | |
6389ee94 AK |
7821 | struct x86_exception fault; |
7822 | ||
7c90705b | 7823 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 7824 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
7825 | |
7826 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
7827 | (vcpu->arch.apf.send_user_only && |
7828 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
7829 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
7830 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
7831 | fault.vector = PF_VECTOR; |
7832 | fault.error_code_valid = true; | |
7833 | fault.error_code = 0; | |
7834 | fault.nested_page_fault = false; | |
7835 | fault.address = work->arch.token; | |
7836 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7837 | } |
af585b92 GN |
7838 | } |
7839 | ||
7840 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
7841 | struct kvm_async_pf *work) | |
7842 | { | |
6389ee94 AK |
7843 | struct x86_exception fault; |
7844 | ||
7c90705b | 7845 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
f2e10669 | 7846 | if (work->wakeup_all) |
7c90705b GN |
7847 | work->arch.token = ~0; /* broadcast wakeup */ |
7848 | else | |
7849 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
7850 | ||
7851 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
7852 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
7853 | fault.vector = PF_VECTOR; |
7854 | fault.error_code_valid = true; | |
7855 | fault.error_code = 0; | |
7856 | fault.nested_page_fault = false; | |
7857 | fault.address = work->arch.token; | |
7858 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7859 | } |
e6d53e3b | 7860 | vcpu->arch.apf.halted = false; |
a4fa1635 | 7861 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
7862 | } |
7863 | ||
7864 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
7865 | { | |
7866 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
7867 | return true; | |
7868 | else | |
7869 | return !kvm_event_needs_reinjection(vcpu) && | |
7870 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
7871 | } |
7872 | ||
e0f0bbc5 AW |
7873 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
7874 | { | |
7875 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
7876 | } | |
7877 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
7878 | ||
7879 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
7880 | { | |
7881 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
7882 | } | |
7883 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
7884 | ||
7885 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
7886 | { | |
7887 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
7888 | } | |
7889 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
7890 | ||
229456fc MT |
7891 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
7892 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
7893 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
7894 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
7895 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 7896 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 7897 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 7898 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 7899 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 7900 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 7901 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 7902 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 7903 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 7904 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 7905 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |