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KVM: Leave TSC synchronization window open with each new sync
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
98918833 60#include <asm/xcr.h>
1d5f066e 61#include <asm/pvclock.h>
217fc9cf 62#include <asm/div64.h>
043405e1 63
313a3dc7 64#define MAX_IO_MSRS 256
890ca9ae 65#define KVM_MAX_MCE_BANKS 32
5854dbca 66#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 67
0f65dd70
AK		 68#define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
1260edbe
LJ		 76static
77u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 78#else
1260edbe 79static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 86static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
476bc001
RR		 91static bool ignore_msrs = 0;
92module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
cc578287
ZA		 99/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
100static u32 tsc_tolerance_ppm = 250;
101module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
102
18863bdd
AK		 103#define KVM_NR_SHARED_MSRS 16
104
105struct kvm_shared_msrs_global {
106 int nr;
2bf78fa7 107 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110struct kvm_shared_msrs {
111 struct user_return_notifier urn;
112 bool registered;
2bf78fa7
SY		 113 struct kvm_shared_msr_values {
114 u64 host;
115 u64 curr;
116 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
120static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
121
417bc304 122struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 123 { "pf_fixed", VCPU_STAT(pf_fixed) },
124 { "pf_guest", VCPU_STAT(pf_guest) },
125 { "tlb_flush", VCPU_STAT(tlb_flush) },
126 { "invlpg", VCPU_STAT(invlpg) },
127 { "exits", VCPU_STAT(exits) },
128 { "io_exits", VCPU_STAT(io_exits) },
129 { "mmio_exits", VCPU_STAT(mmio_exits) },
130 { "signal_exits", VCPU_STAT(signal_exits) },
131 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 132 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 133 { "halt_exits", VCPU_STAT(halt_exits) },
134 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 135 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 136 { "request_irq", VCPU_STAT(request_irq_exits) },
137 { "irq_exits", VCPU_STAT(irq_exits) },
138 { "host_state_reload", VCPU_STAT(host_state_reload) },
139 { "efer_reload", VCPU_STAT(efer_reload) },
140 { "fpu_reload", VCPU_STAT(fpu_reload) },
141 { "insn_emulation", VCPU_STAT(insn_emulation) },
142 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 143 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 144 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 145 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
146 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
147 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
148 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
149 { "mmu_flooded", VM_STAT(mmu_flooded) },
150 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 151 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 152 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 153 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 154 { "largepages", VM_STAT(lpages) },
417bc304
HB		 155 { NULL }
156};
157
2acf923e
DC		 158u64 __read_mostly host_xcr0;
159
d6aa1000
AK		 160int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
161
af585b92
GN		 162static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
163{
164 int i;
165 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
166 vcpu->arch.apf.gfns[i] = ~0;
167}
168
18863bdd
AK		 169static void kvm_on_user_return(struct user_return_notifier *urn)
170{
171 unsigned slot;
18863bdd
AK		 172 struct kvm_shared_msrs *locals
173 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 174 struct kvm_shared_msr_values *values;
18863bdd
AK		 175
176 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 177 values = &locals->values[slot];
178 if (values->host != values->curr) {
179 wrmsrl(shared_msrs_global.msrs[slot], values->host);
180 values->curr = values->host;
18863bdd
AK		 181 }
182 }
183 locals->registered = false;
184 user_return_notifier_unregister(urn);
185}
186
2bf78fa7 187static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 188{
2bf78fa7 189 struct kvm_shared_msrs *smsr;
18863bdd
AK		 190 u64 value;
191
2bf78fa7
SY		 192 smsr = &__get_cpu_var(shared_msrs);
193 /* only read, and nobody should modify it at this time,
194 * so don't need lock */
195 if (slot >= shared_msrs_global.nr) {
196 printk(KERN_ERR "kvm: invalid MSR slot!");
197 return;
198 }
199 rdmsrl_safe(msr, &value);
200 smsr->values[slot].host = value;
201 smsr->values[slot].curr = value;
202}
203
204void kvm_define_shared_msr(unsigned slot, u32 msr)
205{
18863bdd
AK		 206 if (slot >= shared_msrs_global.nr)
207 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 208 shared_msrs_global.msrs[slot] = msr;
209 /* we need ensured the shared_msr_global have been updated */
210 smp_wmb();
18863bdd
AK		 211}
212EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
213
214static void kvm_shared_msr_cpu_online(void)
215{
216 unsigned i;
18863bdd
AK		 217
218 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 219 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 220}
221
d5696725 222void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 223{
224 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
225
2bf78fa7 226 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 227 return;
2bf78fa7
SY		 228 smsr->values[slot].curr = value;
229 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 230 if (!smsr->registered) {
231 smsr->urn.on_user_return = kvm_on_user_return;
232 user_return_notifier_register(&smsr->urn);
233 smsr->registered = true;
234 }
235}
236EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
237
3548bab5
AK		 238static void drop_user_return_notifiers(void *ignore)
239{
240 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
241
242 if (smsr->registered)
243 kvm_on_user_return(&smsr->urn);
244}
245
6866b83e
CO		 246u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
247{
248 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 249 return vcpu->arch.apic_base;
6866b83e 250 else
ad312c7c 251 return vcpu->arch.apic_base;
6866b83e
CO		 252}
253EXPORT_SYMBOL_GPL(kvm_get_apic_base);
254
255void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
256{
257 /* TODO: reserve bits check */
258 if (irqchip_in_kernel(vcpu->kvm))
259 kvm_lapic_set_base(vcpu, data);
260 else
ad312c7c 261 vcpu->arch.apic_base = data;
6866b83e
CO		 262}
263EXPORT_SYMBOL_GPL(kvm_set_apic_base);
264
3fd28fce
ED		 265#define EXCPT_BENIGN 0
266#define EXCPT_CONTRIBUTORY 1
267#define EXCPT_PF 2
268
269static int exception_class(int vector)
270{
271 switch (vector) {
272 case PF_VECTOR:
273 return EXCPT_PF;
274 case DE_VECTOR:
275 case TS_VECTOR:
276 case NP_VECTOR:
277 case SS_VECTOR:
278 case GP_VECTOR:
279 return EXCPT_CONTRIBUTORY;
280 default:
281 break;
282 }
283 return EXCPT_BENIGN;
284}
285
286static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 287 unsigned nr, bool has_error, u32 error_code,
288 bool reinject)
3fd28fce
ED		 289{
290 u32 prev_nr;
291 int class1, class2;
292
3842d135
AK		 293 kvm_make_request(KVM_REQ_EVENT, vcpu);
294
3fd28fce
ED		 295 if (!vcpu->arch.exception.pending) {
296 queue:
297 vcpu->arch.exception.pending = true;
298 vcpu->arch.exception.has_error_code = has_error;
299 vcpu->arch.exception.nr = nr;
300 vcpu->arch.exception.error_code = error_code;
3f0fd292 301 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 302 return;
303 }
304
305 /* to check exception */
306 prev_nr = vcpu->arch.exception.nr;
307 if (prev_nr == DF_VECTOR) {
308 /* triple fault -> shutdown */
a8eeb04a 309 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 310 return;
311 }
312 class1 = exception_class(prev_nr);
313 class2 = exception_class(nr);
314 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
315 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
316 /* generate double fault per SDM Table 5-5 */
317 vcpu->arch.exception.pending = true;
318 vcpu->arch.exception.has_error_code = true;
319 vcpu->arch.exception.nr = DF_VECTOR;
320 vcpu->arch.exception.error_code = 0;
321 } else
322 /* replace previous exception with a new one in a hope
323 that instruction re-execution will regenerate lost
324 exception */
325 goto queue;
326}
327
298101da
AK		 328void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
ce7ddec4 330 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 331}
332EXPORT_SYMBOL_GPL(kvm_queue_exception);
333
ce7ddec4
JR		 334void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
336 kvm_multiple_exception(vcpu, nr, false, 0, true);
337}
338EXPORT_SYMBOL_GPL(kvm_requeue_exception);
339
db8fcefa 340void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 341{
db8fcefa
AP		 342 if (err)
343 kvm_inject_gp(vcpu, 0);
344 else
345 kvm_x86_ops->skip_emulated_instruction(vcpu);
346}
347EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 348
6389ee94 349void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 350{
351 ++vcpu->stat.pf_guest;
6389ee94
AK		 352 vcpu->arch.cr2 = fault->address;
353 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 354}
27d6c865 355EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 356
6389ee94 357void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 358{
6389ee94
AK		 359 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
360 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 361 else
6389ee94 362 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 363}
364
3419ffc8
SY		 365void kvm_inject_nmi(struct kvm_vcpu *vcpu)
366{
7460fb4a
AK		 367 atomic_inc(&vcpu->arch.nmi_queued);
368 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 369}
370EXPORT_SYMBOL_GPL(kvm_inject_nmi);
371
298101da
AK		 372void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
373{
ce7ddec4 374 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 375}
376EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
377
ce7ddec4
JR		 378void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
380 kvm_multiple_exception(vcpu, nr, true, error_code, true);
381}
382EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
383
0a79b009
AK		 384/*
385 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
386 * a #GP and return false.
387 */
388bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 389{
0a79b009
AK		 390 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
391 return true;
392 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
393 return false;
298101da 394}
0a79b009 395EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 396
ec92fe44
JR		 397/*
398 * This function will be used to read from the physical memory of the currently
399 * running guest. The difference to kvm_read_guest_page is that this function
400 * can read from guest physical or from the guest's guest physical memory.
401 */
402int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
403 gfn_t ngfn, void *data, int offset, int len,
404 u32 access)
405{
406 gfn_t real_gfn;
407 gpa_t ngpa;
408
409 ngpa = gfn_to_gpa(ngfn);
410 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
411 if (real_gfn == UNMAPPED_GVA)
412 return -EFAULT;
413
414 real_gfn = gpa_to_gfn(real_gfn);
415
416 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
417}
418EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
419
3d06b8bf
JR		 420int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
421 void *data, int offset, int len, u32 access)
422{
423 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
424 data, offset, len, access);
425}
426
a03490ed
CO		 427/*
428 * Load the pae pdptrs. Return true is they are all valid.
429 */
ff03a073 430int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 431{
432 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
433 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
434 int i;
435 int ret;
ff03a073 436 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 437
ff03a073
JR		 438 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
439 offset * sizeof(u64), sizeof(pdpte),
440 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 441 if (ret < 0) {
442 ret = 0;
443 goto out;
444 }
445 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 446 if (is_present_gpte(pdpte[i]) &&
20c466b5 447 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 448 ret = 0;
449 goto out;
450 }
451 }
452 ret = 1;
453
ff03a073 454 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 455 __set_bit(VCPU_EXREG_PDPTR,
456 (unsigned long *)&vcpu->arch.regs_avail);
457 __set_bit(VCPU_EXREG_PDPTR,
458 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 459out:
a03490ed
CO		 460
461 return ret;
462}
cc4b6871 463EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 464
d835dfec
AK		 465static bool pdptrs_changed(struct kvm_vcpu *vcpu)
466{
ff03a073 467 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 468 bool changed = true;
3d06b8bf
JR		 469 int offset;
470 gfn_t gfn;
d835dfec
AK		 471 int r;
472
473 if (is_long_mode(vcpu) || !is_pae(vcpu))
474 return false;
475
6de4f3ad
AK		 476 if (!test_bit(VCPU_EXREG_PDPTR,
477 (unsigned long *)&vcpu->arch.regs_avail))
478 return true;
479
9f8fe504
AK		 480 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
481 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 482 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
483 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 484 if (r < 0)
485 goto out;
ff03a073 486 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 487out:
d835dfec
AK		 488
489 return changed;
490}
491
49a9b07e 492int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 493{
aad82703
SY		 494 unsigned long old_cr0 = kvm_read_cr0(vcpu);
495 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
496 X86_CR0_CD | X86_CR0_NW;
497
f9a48e6a
AK		 498 cr0 |= X86_CR0_ET;
499
ab344828 500#ifdef CONFIG_X86_64
0f12244f
GN		 501 if (cr0 & 0xffffffff00000000UL)
502 return 1;
ab344828
GN		 503#endif
504
505 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 506
0f12244f
GN		 507 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
508 return 1;
a03490ed 509
0f12244f
GN		 510 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
511 return 1;
a03490ed
CO		 512
513 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
514#ifdef CONFIG_X86_64
f6801dff 515 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 516 int cs_db, cs_l;
517
0f12244f
GN		 518 if (!is_pae(vcpu))
519 return 1;
a03490ed 520 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 521 if (cs_l)
522 return 1;
a03490ed
CO		 523 } else
524#endif
ff03a073 525 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 526 kvm_read_cr3(vcpu)))
0f12244f 527 return 1;
a03490ed
CO		 528 }
529
530 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 531
d170c419 532 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 533 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 534 kvm_async_pf_hash_reset(vcpu);
535 }
e5f3f027 536
aad82703
SY		 537 if ((cr0 ^ old_cr0) & update_bits)
538 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 539 return 0;
540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 542
2d3ad1f4 543void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 544{
49a9b07e 545 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 546}
2d3ad1f4 547EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 548
2acf923e
DC		 549int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
550{
551 u64 xcr0;
552
553 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
554 if (index != XCR_XFEATURE_ENABLED_MASK)
555 return 1;
556 xcr0 = xcr;
557 if (kvm_x86_ops->get_cpl(vcpu) != 0)
558 return 1;
559 if (!(xcr0 & XSTATE_FP))
560 return 1;
561 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
562 return 1;
563 if (xcr0 & ~host_xcr0)
564 return 1;
565 vcpu->arch.xcr0 = xcr0;
566 vcpu->guest_xcr0_loaded = 0;
567 return 0;
568}
569
570int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
571{
572 if (__kvm_set_xcr(vcpu, index, xcr)) {
573 kvm_inject_gp(vcpu, 0);
574 return 1;
575 }
576 return 0;
577}
578EXPORT_SYMBOL_GPL(kvm_set_xcr);
579
a83b29c6 580int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 581{
fc78f519 582 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 583 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
584 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 585 if (cr4 & CR4_RESERVED_BITS)
586 return 1;
a03490ed 587
2acf923e
DC		 588 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
589 return 1;
590
c68b734f
YW		 591 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
592 return 1;
593
74dc2b4f
YW		 594 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
595 return 1;
596
a03490ed 597 if (is_long_mode(vcpu)) {
0f12244f
GN		 598 if (!(cr4 & X86_CR4_PAE))
599 return 1;
a2edf57f
AK		 600 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
601 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 602 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
603 kvm_read_cr3(vcpu)))
0f12244f
GN		 604 return 1;
605
5e1746d6 606 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 607 return 1;
a03490ed 608
aad82703
SY		 609 if ((cr4 ^ old_cr4) & pdptr_bits)
610 kvm_mmu_reset_context(vcpu);
0f12244f 611
2acf923e 612 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 613 kvm_update_cpuid(vcpu);
2acf923e 614
0f12244f
GN		 615 return 0;
616}
2d3ad1f4 617EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 618
2390218b 619int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 620{
9f8fe504 621 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 622 kvm_mmu_sync_roots(vcpu);
d835dfec 623 kvm_mmu_flush_tlb(vcpu);
0f12244f 624 return 0;
d835dfec
AK		 625 }
626
a03490ed 627 if (is_long_mode(vcpu)) {
0f12244f
GN		 628 if (cr3 & CR3_L_MODE_RESERVED_BITS)
629 return 1;
a03490ed
CO		 630 } else {
631 if (is_pae(vcpu)) {
0f12244f
GN		 632 if (cr3 & CR3_PAE_RESERVED_BITS)
633 return 1;
ff03a073
JR		 634 if (is_paging(vcpu) &&
635 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 636 return 1;
a03490ed
CO		 637 }
638 /*
639 * We don't check reserved bits in nonpae mode, because
640 * this isn't enforced, and VMware depends on this.
641 */
642 }
643
a03490ed
CO		 644 /*
645 * Does the new cr3 value map to physical memory? (Note, we
646 * catch an invalid cr3 even in real-mode, because it would
647 * cause trouble later on when we turn on paging anyway.)
648 *
649 * A real CPU would silently accept an invalid cr3 and would
650 * attempt to use it - with largely undefined (and often hard
651 * to debug) behavior on the guest side.
652 */
653 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 654 return 1;
655 vcpu->arch.cr3 = cr3;
aff48baa 656 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 657 vcpu->arch.mmu.new_cr3(vcpu);
658 return 0;
659}
2d3ad1f4 660EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 661
eea1cff9 662int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 663{
0f12244f
GN		 664 if (cr8 & CR8_RESERVED_BITS)
665 return 1;
a03490ed
CO		 666 if (irqchip_in_kernel(vcpu->kvm))
667 kvm_lapic_set_tpr(vcpu, cr8);
668 else
ad312c7c 669 vcpu->arch.cr8 = cr8;
0f12244f
GN		 670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 673
2d3ad1f4 674unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 675{
676 if (irqchip_in_kernel(vcpu->kvm))
677 return kvm_lapic_get_cr8(vcpu);
678 else
ad312c7c 679 return vcpu->arch.cr8;
a03490ed 680}
2d3ad1f4 681EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 682
338dbc97 683static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 684{
685 switch (dr) {
686 case 0 ... 3:
687 vcpu->arch.db[dr] = val;
688 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
689 vcpu->arch.eff_db[dr] = val;
690 break;
691 case 4:
338dbc97
GN		 692 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
693 return 1; /* #UD */
020df079
GN		 694 /* fall through */
695 case 6:
338dbc97
GN		 696 if (val & 0xffffffff00000000ULL)
697 return -1; /* #GP */
020df079
GN		 698 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
699 break;
700 case 5:
338dbc97
GN		 701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
702 return 1; /* #UD */
020df079
GN		 703 /* fall through */
704 default: /* 7 */
338dbc97
GN		 705 if (val & 0xffffffff00000000ULL)
706 return -1; /* #GP */
020df079
GN		 707 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
708 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
709 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
710 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
711 }
712 break;
713 }
714
715 return 0;
716}
338dbc97
GN		 717
718int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
719{
720 int res;
721
722 res = __kvm_set_dr(vcpu, dr, val);
723 if (res > 0)
724 kvm_queue_exception(vcpu, UD_VECTOR);
725 else if (res < 0)
726 kvm_inject_gp(vcpu, 0);
727
728 return res;
729}
020df079
GN		 730EXPORT_SYMBOL_GPL(kvm_set_dr);
731
338dbc97 732static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 733{
734 switch (dr) {
735 case 0 ... 3:
736 *val = vcpu->arch.db[dr];
737 break;
738 case 4:
338dbc97 739 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 740 return 1;
020df079
GN		 741 /* fall through */
742 case 6:
743 *val = vcpu->arch.dr6;
744 break;
745 case 5:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 default: /* 7 */
750 *val = vcpu->arch.dr7;
751 break;
752 }
753
754 return 0;
755}
338dbc97
GN		 756
757int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
758{
759 if (_kvm_get_dr(vcpu, dr, val)) {
760 kvm_queue_exception(vcpu, UD_VECTOR);
761 return 1;
762 }
763 return 0;
764}
020df079
GN		 765EXPORT_SYMBOL_GPL(kvm_get_dr);
766
022cd0e8
AK		 767bool kvm_rdpmc(struct kvm_vcpu *vcpu)
768{
769 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
770 u64 data;
771 int err;
772
773 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
774 if (err)
775 return err;
776 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
777 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
778 return err;
779}
780EXPORT_SYMBOL_GPL(kvm_rdpmc);
781
043405e1
CO		 782/*
783 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
784 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
785 *
786 * This list is modified at module load time to reflect the
e3267cbb
GC		 787 * capabilities of the host cpu. This capabilities test skips MSRs that are
788 * kvm-specific. Those are put in the beginning of the list.
043405e1 789 */
e3267cbb 790
c9aaa895 791#define KVM_SAVE_MSRS_BEGIN 9
043405e1 792static u32 msrs_to_save[] = {
e3267cbb 793 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 794 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 795 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 796 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 797 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 798 MSR_STAR,
043405e1
CO		 799#ifdef CONFIG_X86_64
800 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
801#endif
e90aa41e 802 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 803};
804
805static unsigned num_msrs_to_save;
806
807static u32 emulated_msrs[] = {
a3e06bbe 808 MSR_IA32_TSCDEADLINE,
043405e1 809 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 810 MSR_IA32_MCG_STATUS,
811 MSR_IA32_MCG_CTL,
043405e1
CO		 812};
813
b69e8cae 814static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 815{
aad82703
SY		 816 u64 old_efer = vcpu->arch.efer;
817
b69e8cae
RJ		 818 if (efer & efer_reserved_bits)
819 return 1;
15c4a640
CO		 820
821 if (is_paging(vcpu)
b69e8cae
RJ		 822 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
823 return 1;
15c4a640 824
1b2fd70c
AG		 825 if (efer & EFER_FFXSR) {
826 struct kvm_cpuid_entry2 *feat;
827
828 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 829 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
830 return 1;
1b2fd70c
AG		 831 }
832
d8017474
AG		 833 if (efer & EFER_SVME) {
834 struct kvm_cpuid_entry2 *feat;
835
836 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 837 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
838 return 1;
d8017474
AG		 839 }
840
15c4a640 841 efer &= ~EFER_LMA;
f6801dff 842 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 843
a3d204e2
SY		 844 kvm_x86_ops->set_efer(vcpu, efer);
845
9645bb56 846 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 847
aad82703
SY		 848 /* Update reserved bits */
849 if ((efer ^ old_efer) & EFER_NX)
850 kvm_mmu_reset_context(vcpu);
851
b69e8cae 852 return 0;
15c4a640
CO		 853}
854
f2b4b7dd
JR		 855void kvm_enable_efer_bits(u64 mask)
856{
857 efer_reserved_bits &= ~mask;
858}
859EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
860
861
15c4a640
CO		 862/*
863 * Writes msr value into into the appropriate "register".
864 * Returns 0 on success, non-0 otherwise.
865 * Assumes vcpu_load() was already called.
866 */
867int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
868{
869 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
870}
871
313a3dc7
CO		 872/*
873 * Adapt set_msr() to msr_io()'s calling convention
874 */
875static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
876{
877 return kvm_set_msr(vcpu, index, *data);
878}
879
18068523
GOC		 880static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
881{
9ed3c444
AK		 882 int version;
883 int r;
50d0a0f9 884 struct pvclock_wall_clock wc;
923de3cf 885 struct timespec boot;
18068523
GOC		 886
887 if (!wall_clock)
888 return;
889
9ed3c444
AK		 890 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
891 if (r)
892 return;
893
894 if (version & 1)
895 ++version; /* first time write, random junk */
896
897 ++version;
18068523 898
18068523
GOC		 899 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
900
50d0a0f9
GH		 901 /*
902 * The guest calculates current wall clock time by adding
34c238a1 903 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 904 * wall clock specified here. guest system time equals host
905 * system time for us, thus we must fill in host boot time here.
906 */
923de3cf 907 getboottime(&boot);
50d0a0f9
GH		 908
909 wc.sec = boot.tv_sec;
910 wc.nsec = boot.tv_nsec;
911 wc.version = version;
18068523
GOC		 912
913 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
914
915 version++;
916 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 917}
918
50d0a0f9
GH		 919static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
920{
921 uint32_t quotient, remainder;
922
923 /* Don't try to replace with do_div(), this one calculates
924 * "(dividend << 32) / divisor" */
925 __asm__ ( "divl %4"
926 : "=a" (quotient), "=d" (remainder)
927 : "0" (0), "1" (dividend), "r" (divisor) );
928 return quotient;
929}
930
5f4e3f88
ZA		 931static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
932 s8 *pshift, u32 *pmultiplier)
50d0a0f9 933{
5f4e3f88 934 uint64_t scaled64;
50d0a0f9
GH		 935 int32_t shift = 0;
936 uint64_t tps64;
937 uint32_t tps32;
938
5f4e3f88
ZA		 939 tps64 = base_khz * 1000LL;
940 scaled64 = scaled_khz * 1000LL;
50933623 941 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 942 tps64 >>= 1;
943 shift--;
944 }
945
946 tps32 = (uint32_t)tps64;
50933623
JK		 947 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
948 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 949 scaled64 >>= 1;
950 else
951 tps32 <<= 1;
50d0a0f9
GH		 952 shift++;
953 }
954
5f4e3f88
ZA		 955 *pshift = shift;
956 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 957
5f4e3f88
ZA		 958 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
959 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 960}
961
759379dd
ZA		 962static inline u64 get_kernel_ns(void)
963{
964 struct timespec ts;
965
966 WARN_ON(preemptible());
967 ktime_get_ts(&ts);
968 monotonic_to_bootbased(&ts);
969 return timespec_to_ns(&ts);
50d0a0f9
GH		 970}
971
c8076604 972static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 973unsigned long max_tsc_khz;
c8076604 974
cc578287 975static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 976{
cc578287
ZA		 977 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
978 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 979}
980
cc578287 981static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 982{
cc578287
ZA		 983 u64 v = (u64)khz * (1000000 + ppm);
984 do_div(v, 1000000);
985 return v;
1e993611
JR		 986}
987
cc578287 988static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 989{
cc578287
ZA		 990 u32 thresh_lo, thresh_hi;
991 int use_scaling = 0;
217fc9cf 992
c285545f
ZA		 993 /* Compute a scale to convert nanoseconds in TSC cycles */
994 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 995 &vcpu->arch.virtual_tsc_shift,
996 &vcpu->arch.virtual_tsc_mult);
997 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
998
999 /*
1000 * Compute the variation in TSC rate which is acceptable
1001 * within the range of tolerance and decide if the
1002 * rate being applied is within that bounds of the hardware
1003 * rate. If so, no scaling or compensation need be done.
1004 */
1005 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1006 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1007 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1008 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1009 use_scaling = 1;
1010 }
1011 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1012}
1013
1014static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1015{
1016 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
cc578287
ZA		 1017 vcpu->arch.virtual_tsc_mult,
1018 vcpu->arch.virtual_tsc_shift);
c285545f
ZA		 1019 tsc += vcpu->arch.last_tsc_write;
1020 return tsc;
1021}
1022
99e3e30a
ZA		 1023void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1024{
1025 struct kvm *kvm = vcpu->kvm;
f38e098f 1026 u64 offset, ns, elapsed;
99e3e30a 1027 unsigned long flags;
5d3cb0f6 1028 s64 nsdiff;
99e3e30a 1029
038f8c11 1030 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1031 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1032 ns = get_kernel_ns();
f38e098f 1033 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1034
1035 /* n.b - signed multiplication and division required */
1036 nsdiff = data - kvm->arch.last_tsc_write;
1037#ifdef CONFIG_X86_64
1038 nsdiff = (nsdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1039#else
1040 /* do_div() only does unsigned */
1041 asm("idivl %2; xor %%edx, %%edx"
1042 : "=A"(nsdiff)
1043 : "A"(nsdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1044#endif
1045 nsdiff -= elapsed;
1046 if (nsdiff < 0)
1047 nsdiff = -nsdiff;
f38e098f
ZA		 1048
1049 /*
5d3cb0f6
ZA		 1050 * Special case: TSC write with a small delta (1 second) of virtual
1051 * cycle time against real time is interpreted as an attempt to
1052 * synchronize the CPU.
1053 *
1054 * For a reliable TSC, we can match TSC offsets, and for an unstable
1055 * TSC, we add elapsed time in this computation. We could let the
1056 * compensation code attempt to catch up if we fall behind, but
1057 * it's better to try to match offsets from the beginning.
1058 */
1059 if (nsdiff < NSEC_PER_SEC &&
1060 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f
ZA		 1061 if (!check_tsc_unstable()) {
1062 offset = kvm->arch.last_tsc_offset;
1063 pr_debug("kvm: matched tsc offset for %llu\n", data);
1064 } else {
857e4099 1065 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1066 data += delta;
1067 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1068 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1069 }
f38e098f
ZA		 1070 }
1071 kvm->arch.last_tsc_nsec = ns;
1072 kvm->arch.last_tsc_write = data;
1073 kvm->arch.last_tsc_offset = offset;
5d3cb0f6 1074 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1075 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1076 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1077
1078 /* Reset of TSC must disable overshoot protection below */
1079 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1080 vcpu->arch.last_tsc_write = data;
1081 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1082}
1083EXPORT_SYMBOL_GPL(kvm_write_tsc);
1084
34c238a1 1085static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1086{
18068523
GOC		 1087 unsigned long flags;
1088 struct kvm_vcpu_arch *vcpu = &v->arch;
1089 void *shared_kaddr;
463656c0 1090 unsigned long this_tsc_khz;
1d5f066e
ZA		 1091 s64 kernel_ns, max_kernel_ns;
1092 u64 tsc_timestamp;
18068523 1093
18068523
GOC		 1094 /* Keep irq disabled to prevent changes to the clock */
1095 local_irq_save(flags);
d5c1785d 1096 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1097 kernel_ns = get_kernel_ns();
cc578287 1098 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1099 if (unlikely(this_tsc_khz == 0)) {
c285545f 1100 local_irq_restore(flags);
34c238a1 1101 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1102 return 1;
1103 }
18068523 1104
c285545f
ZA		 1105 /*
1106 * We may have to catch up the TSC to match elapsed wall clock
1107 * time for two reasons, even if kvmclock is used.
1108 * 1) CPU could have been running below the maximum TSC rate
1109 * 2) Broken TSC compensation resets the base at each VCPU
1110 * entry to avoid unknown leaps of TSC even when running
1111 * again on the same CPU. This may cause apparent elapsed
1112 * time to disappear, and the guest to stand still or run
1113 * very slowly.
1114 */
1115 if (vcpu->tsc_catchup) {
1116 u64 tsc = compute_guest_tsc(v, kernel_ns);
1117 if (tsc > tsc_timestamp) {
1118 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1119 tsc_timestamp = tsc;
1120 }
50d0a0f9
GH		 1121 }
1122
18068523
GOC		 1123 local_irq_restore(flags);
1124
c285545f
ZA		 1125 if (!vcpu->time_page)
1126 return 0;
18068523 1127
1d5f066e
ZA		 1128 /*
1129 * Time as measured by the TSC may go backwards when resetting the base
1130 * tsc_timestamp. The reason for this is that the TSC resolution is
1131 * higher than the resolution of the other clock scales. Thus, many
1132 * possible measurments of the TSC correspond to one measurement of any
1133 * other clock, and so a spread of values is possible. This is not a
1134 * problem for the computation of the nanosecond clock; with TSC rates
1135 * around 1GHZ, there can only be a few cycles which correspond to one
1136 * nanosecond value, and any path through this code will inevitably
1137 * take longer than that. However, with the kernel_ns value itself,
1138 * the precision may be much lower, down to HZ granularity. If the
1139 * first sampling of TSC against kernel_ns ends in the low part of the
1140 * range, and the second in the high end of the range, we can get:
1141 *
1142 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1143 *
1144 * As the sampling errors potentially range in the thousands of cycles,
1145 * it is possible such a time value has already been observed by the
1146 * guest. To protect against this, we must compute the system time as
1147 * observed by the guest and ensure the new system time is greater.
1148 */
1149 max_kernel_ns = 0;
1150 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1151 max_kernel_ns = vcpu->last_guest_tsc -
1152 vcpu->hv_clock.tsc_timestamp;
1153 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1154 vcpu->hv_clock.tsc_to_system_mul,
1155 vcpu->hv_clock.tsc_shift);
1156 max_kernel_ns += vcpu->last_kernel_ns;
1157 }
afbcf7ab 1158
e48672fa 1159 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1160 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1161 &vcpu->hv_clock.tsc_shift,
1162 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1163 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1164 }
1165
1d5f066e
ZA		 1166 if (max_kernel_ns > kernel_ns)
1167 kernel_ns = max_kernel_ns;
1168
8cfdc000 1169 /* With all the info we got, fill in the values */
1d5f066e 1170 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1171 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1172 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1173 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1174 vcpu->hv_clock.flags = 0;
1175
18068523
GOC		 1176 /*
1177 * The interface expects us to write an even number signaling that the
1178 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1179 * state, we just increase by 2 at the end.
18068523 1180 */
50d0a0f9 1181 vcpu->hv_clock.version += 2;
18068523
GOC		 1182
1183 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1184
1185 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1186 sizeof(vcpu->hv_clock));
18068523
GOC		 1187
1188 kunmap_atomic(shared_kaddr, KM_USER0);
1189
1190 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1191 return 0;
c8076604
GH		 1192}
1193
9ba075a6
AK		 1194static bool msr_mtrr_valid(unsigned msr)
1195{
1196 switch (msr) {
1197 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1198 case MSR_MTRRfix64K_00000:
1199 case MSR_MTRRfix16K_80000:
1200 case MSR_MTRRfix16K_A0000:
1201 case MSR_MTRRfix4K_C0000:
1202 case MSR_MTRRfix4K_C8000:
1203 case MSR_MTRRfix4K_D0000:
1204 case MSR_MTRRfix4K_D8000:
1205 case MSR_MTRRfix4K_E0000:
1206 case MSR_MTRRfix4K_E8000:
1207 case MSR_MTRRfix4K_F0000:
1208 case MSR_MTRRfix4K_F8000:
1209 case MSR_MTRRdefType:
1210 case MSR_IA32_CR_PAT:
1211 return true;
1212 case 0x2f8:
1213 return true;
1214 }
1215 return false;
1216}
1217
d6289b93
MT		 1218static bool valid_pat_type(unsigned t)
1219{
1220 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1221}
1222
1223static bool valid_mtrr_type(unsigned t)
1224{
1225 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1226}
1227
1228static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1229{
1230 int i;
1231
1232 if (!msr_mtrr_valid(msr))
1233 return false;
1234
1235 if (msr == MSR_IA32_CR_PAT) {
1236 for (i = 0; i < 8; i++)
1237 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1238 return false;
1239 return true;
1240 } else if (msr == MSR_MTRRdefType) {
1241 if (data & ~0xcff)
1242 return false;
1243 return valid_mtrr_type(data & 0xff);
1244 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1245 for (i = 0; i < 8 ; i++)
1246 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1247 return false;
1248 return true;
1249 }
1250
1251 /* variable MTRRs */
1252 return valid_mtrr_type(data & 0xff);
1253}
1254
9ba075a6
AK		 1255static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1256{
0bed3b56
SY		 1257 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1258
d6289b93 1259 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1260 return 1;
1261
0bed3b56
SY		 1262 if (msr == MSR_MTRRdefType) {
1263 vcpu->arch.mtrr_state.def_type = data;
1264 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1265 } else if (msr == MSR_MTRRfix64K_00000)
1266 p[0] = data;
1267 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1268 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1269 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1270 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1271 else if (msr == MSR_IA32_CR_PAT)
1272 vcpu->arch.pat = data;
1273 else { /* Variable MTRRs */
1274 int idx, is_mtrr_mask;
1275 u64 *pt;
1276
1277 idx = (msr - 0x200) / 2;
1278 is_mtrr_mask = msr - 0x200 - 2 * idx;
1279 if (!is_mtrr_mask)
1280 pt =
1281 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1282 else
1283 pt =
1284 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1285 *pt = data;
1286 }
1287
1288 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1289 return 0;
1290}
15c4a640 1291
890ca9ae 1292static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1293{
890ca9ae
HY		 1294 u64 mcg_cap = vcpu->arch.mcg_cap;
1295 unsigned bank_num = mcg_cap & 0xff;
1296
15c4a640 1297 switch (msr) {
15c4a640 1298 case MSR_IA32_MCG_STATUS:
890ca9ae 1299 vcpu->arch.mcg_status = data;
15c4a640 1300 break;
c7ac679c 1301 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1302 if (!(mcg_cap & MCG_CTL_P))
1303 return 1;
1304 if (data != 0 && data != ~(u64)0)
1305 return -1;
1306 vcpu->arch.mcg_ctl = data;
1307 break;
1308 default:
1309 if (msr >= MSR_IA32_MC0_CTL &&
1310 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1311 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1312 /* only 0 or all 1s can be written to IA32_MCi_CTL
1313 * some Linux kernels though clear bit 10 in bank 4 to
1314 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1315 * this to avoid an uncatched #GP in the guest
1316 */
890ca9ae 1317 if ((offset & 0x3) == 0 &&
114be429 1318 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1319 return -1;
1320 vcpu->arch.mce_banks[offset] = data;
1321 break;
1322 }
1323 return 1;
1324 }
1325 return 0;
1326}
1327
ffde22ac
ES		 1328static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1329{
1330 struct kvm *kvm = vcpu->kvm;
1331 int lm = is_long_mode(vcpu);
1332 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1333 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1334 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1335 : kvm->arch.xen_hvm_config.blob_size_32;
1336 u32 page_num = data & ~PAGE_MASK;
1337 u64 page_addr = data & PAGE_MASK;
1338 u8 *page;
1339 int r;
1340
1341 r = -E2BIG;
1342 if (page_num >= blob_size)
1343 goto out;
1344 r = -ENOMEM;
ff5c2c03
SL		 1345 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1346 if (IS_ERR(page)) {
1347 r = PTR_ERR(page);
ffde22ac 1348 goto out;
ff5c2c03 1349 }
ffde22ac
ES		 1350 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1351 goto out_free;
1352 r = 0;
1353out_free:
1354 kfree(page);
1355out:
1356 return r;
1357}
1358
55cd8e5a
GN		 1359static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1360{
1361 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1362}
1363
1364static bool kvm_hv_msr_partition_wide(u32 msr)
1365{
1366 bool r = false;
1367 switch (msr) {
1368 case HV_X64_MSR_GUEST_OS_ID:
1369 case HV_X64_MSR_HYPERCALL:
1370 r = true;
1371 break;
1372 }
1373
1374 return r;
1375}
1376
1377static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1378{
1379 struct kvm *kvm = vcpu->kvm;
1380
1381 switch (msr) {
1382 case HV_X64_MSR_GUEST_OS_ID:
1383 kvm->arch.hv_guest_os_id = data;
1384 /* setting guest os id to zero disables hypercall page */
1385 if (!kvm->arch.hv_guest_os_id)
1386 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1387 break;
1388 case HV_X64_MSR_HYPERCALL: {
1389 u64 gfn;
1390 unsigned long addr;
1391 u8 instructions[4];
1392
1393 /* if guest os id is not set hypercall should remain disabled */
1394 if (!kvm->arch.hv_guest_os_id)
1395 break;
1396 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1397 kvm->arch.hv_hypercall = data;
1398 break;
1399 }
1400 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1401 addr = gfn_to_hva(kvm, gfn);
1402 if (kvm_is_error_hva(addr))
1403 return 1;
1404 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1405 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1406 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1407 return 1;
1408 kvm->arch.hv_hypercall = data;
1409 break;
1410 }
1411 default:
1412 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1413 "data 0x%llx\n", msr, data);
1414 return 1;
1415 }
1416 return 0;
1417}
1418
1419static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1420{
10388a07
GN		 1421 switch (msr) {
1422 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1423 unsigned long addr;
55cd8e5a 1424
10388a07
GN		 1425 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1426 vcpu->arch.hv_vapic = data;
1427 break;
1428 }
1429 addr = gfn_to_hva(vcpu->kvm, data >>
1430 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1431 if (kvm_is_error_hva(addr))
1432 return 1;
8b0cedff 1433 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1434 return 1;
1435 vcpu->arch.hv_vapic = data;
1436 break;
1437 }
1438 case HV_X64_MSR_EOI:
1439 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1440 case HV_X64_MSR_ICR:
1441 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1442 case HV_X64_MSR_TPR:
1443 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1444 default:
1445 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1446 "data 0x%llx\n", msr, data);
1447 return 1;
1448 }
1449
1450 return 0;
55cd8e5a
GN		 1451}
1452
344d9588
GN		 1453static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1454{
1455 gpa_t gpa = data & ~0x3f;
1456
6adba527
GN		 1457 /* Bits 2:5 are resrved, Should be zero */
1458 if (data & 0x3c)
344d9588
GN		 1459 return 1;
1460
1461 vcpu->arch.apf.msr_val = data;
1462
1463 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1464 kvm_clear_async_pf_completion_queue(vcpu);
1465 kvm_async_pf_hash_reset(vcpu);
1466 return 0;
1467 }
1468
1469 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1470 return 1;
1471
6adba527 1472 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1473 kvm_async_pf_wakeup_all(vcpu);
1474 return 0;
1475}
1476
12f9a48f
GC		 1477static void kvmclock_reset(struct kvm_vcpu *vcpu)
1478{
1479 if (vcpu->arch.time_page) {
1480 kvm_release_page_dirty(vcpu->arch.time_page);
1481 vcpu->arch.time_page = NULL;
1482 }
1483}
1484
c9aaa895
GC		 1485static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1486{
1487 u64 delta;
1488
1489 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1490 return;
1491
1492 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1493 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1494 vcpu->arch.st.accum_steal = delta;
1495}
1496
1497static void record_steal_time(struct kvm_vcpu *vcpu)
1498{
1499 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1500 return;
1501
1502 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1503 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1504 return;
1505
1506 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1507 vcpu->arch.st.steal.version += 2;
1508 vcpu->arch.st.accum_steal = 0;
1509
1510 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1511 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1512}
1513
15c4a640
CO		 1514int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1515{
5753785f
GN		 1516 bool pr = false;
1517
15c4a640 1518 switch (msr) {
15c4a640 1519 case MSR_EFER:
b69e8cae 1520 return set_efer(vcpu, data);
8f1589d9
AP		 1521 case MSR_K7_HWCR:
1522 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1523 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1524 if (data != 0) {
1525 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1526 data);
1527 return 1;
1528 }
15c4a640 1529 break;
f7c6d140
AP		 1530 case MSR_FAM10H_MMIO_CONF_BASE:
1531 if (data != 0) {
1532 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1533 "0x%llx\n", data);
1534 return 1;
1535 }
15c4a640 1536 break;
c323c0e5 1537 case MSR_AMD64_NB_CFG:
c7ac679c 1538 break;
b5e2fec0
AG		 1539 case MSR_IA32_DEBUGCTLMSR:
1540 if (!data) {
1541 /* We support the non-activated case already */
1542 break;
1543 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1544 /* Values other than LBR and BTF are vendor-specific,
1545 thus reserved and should throw a #GP */
1546 return 1;
1547 }
1548 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1549 __func__, data);
1550 break;
15c4a640
CO		 1551 case MSR_IA32_UCODE_REV:
1552 case MSR_IA32_UCODE_WRITE:
61a6bd67 1553 case MSR_VM_HSAVE_PA:
6098ca93 1554 case MSR_AMD64_PATCH_LOADER:
15c4a640 1555 break;
9ba075a6
AK		 1556 case 0x200 ... 0x2ff:
1557 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1558 case MSR_IA32_APICBASE:
1559 kvm_set_apic_base(vcpu, data);
1560 break;
0105d1a5
GN		 1561 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1562 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1563 case MSR_IA32_TSCDEADLINE:
1564 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1565 break;
15c4a640 1566 case MSR_IA32_MISC_ENABLE:
ad312c7c 1567 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1568 break;
11c6bffa 1569 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1570 case MSR_KVM_WALL_CLOCK:
1571 vcpu->kvm->arch.wall_clock = data;
1572 kvm_write_wall_clock(vcpu->kvm, data);
1573 break;
11c6bffa 1574 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1575 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1576 kvmclock_reset(vcpu);
18068523
GOC		 1577
1578 vcpu->arch.time = data;
c285545f 1579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1580
1581 /* we verify if the enable bit is set... */
1582 if (!(data & 1))
1583 break;
1584
1585 /* ...but clean it before doing the actual write */
1586 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1587
18068523
GOC		 1588 vcpu->arch.time_page =
1589 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1590
1591 if (is_error_page(vcpu->arch.time_page)) {
1592 kvm_release_page_clean(vcpu->arch.time_page);
1593 vcpu->arch.time_page = NULL;
1594 }
18068523
GOC		 1595 break;
1596 }
344d9588
GN		 1597 case MSR_KVM_ASYNC_PF_EN:
1598 if (kvm_pv_enable_async_pf(vcpu, data))
1599 return 1;
1600 break;
c9aaa895
GC		 1601 case MSR_KVM_STEAL_TIME:
1602
1603 if (unlikely(!sched_info_on()))
1604 return 1;
1605
1606 if (data & KVM_STEAL_RESERVED_MASK)
1607 return 1;
1608
1609 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1610 data & KVM_STEAL_VALID_BITS))
1611 return 1;
1612
1613 vcpu->arch.st.msr_val = data;
1614
1615 if (!(data & KVM_MSR_ENABLED))
1616 break;
1617
1618 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1619
1620 preempt_disable();
1621 accumulate_steal_time(vcpu);
1622 preempt_enable();
1623
1624 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1625
1626 break;
1627
890ca9ae
HY		 1628 case MSR_IA32_MCG_CTL:
1629 case MSR_IA32_MCG_STATUS:
1630 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1631 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1632
1633 /* Performance counters are not protected by a CPUID bit,
1634 * so we should check all of them in the generic path for the sake of
1635 * cross vendor migration.
1636 * Writing a zero into the event select MSRs disables them,
1637 * which we perfectly emulate ;-). Any other value should be at least
1638 * reported, some guests depend on them.
1639 */
71db6023
AP		 1640 case MSR_K7_EVNTSEL0:
1641 case MSR_K7_EVNTSEL1:
1642 case MSR_K7_EVNTSEL2:
1643 case MSR_K7_EVNTSEL3:
1644 if (data != 0)
1645 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1646 "0x%x data 0x%llx\n", msr, data);
1647 break;
1648 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1649 * so we ignore writes to make it happy.
1650 */
71db6023
AP		 1651 case MSR_K7_PERFCTR0:
1652 case MSR_K7_PERFCTR1:
1653 case MSR_K7_PERFCTR2:
1654 case MSR_K7_PERFCTR3:
1655 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1656 "0x%x data 0x%llx\n", msr, data);
1657 break;
5753785f
GN		 1658 case MSR_P6_PERFCTR0:
1659 case MSR_P6_PERFCTR1:
1660 pr = true;
1661 case MSR_P6_EVNTSEL0:
1662 case MSR_P6_EVNTSEL1:
1663 if (kvm_pmu_msr(vcpu, msr))
1664 return kvm_pmu_set_msr(vcpu, msr, data);
1665
1666 if (pr || data != 0)
1667 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1668 "0x%x data 0x%llx\n", msr, data);
1669 break;
84e0cefa
JS		 1670 case MSR_K7_CLK_CTL:
1671 /*
1672 * Ignore all writes to this no longer documented MSR.
1673 * Writes are only relevant for old K7 processors,
1674 * all pre-dating SVM, but a recommended workaround from
1675 * AMD for these chips. It is possible to speicify the
1676 * affected processor models on the command line, hence
1677 * the need to ignore the workaround.
1678 */
1679 break;
55cd8e5a
GN		 1680 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1681 if (kvm_hv_msr_partition_wide(msr)) {
1682 int r;
1683 mutex_lock(&vcpu->kvm->lock);
1684 r = set_msr_hyperv_pw(vcpu, msr, data);
1685 mutex_unlock(&vcpu->kvm->lock);
1686 return r;
1687 } else
1688 return set_msr_hyperv(vcpu, msr, data);
1689 break;
91c9c3ed 1690 case MSR_IA32_BBL_CR_CTL3:
1691 /* Drop writes to this legacy MSR -- see rdmsr
1692 * counterpart for further detail.
1693 */
1694 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1695 break;
2b036c6b
BO		 1696 case MSR_AMD64_OSVW_ID_LENGTH:
1697 if (!guest_cpuid_has_osvw(vcpu))
1698 return 1;
1699 vcpu->arch.osvw.length = data;
1700 break;
1701 case MSR_AMD64_OSVW_STATUS:
1702 if (!guest_cpuid_has_osvw(vcpu))
1703 return 1;
1704 vcpu->arch.osvw.status = data;
1705 break;
15c4a640 1706 default:
ffde22ac
ES		 1707 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1708 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1709 if (kvm_pmu_msr(vcpu, msr))
1710 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068
AP		 1711 if (!ignore_msrs) {
1712 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1713 msr, data);
1714 return 1;
1715 } else {
1716 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1717 msr, data);
1718 break;
1719 }
15c4a640
CO		 1720 }
1721 return 0;
1722}
1723EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1724
1725
1726/*
1727 * Reads an msr value (of 'msr_index') into 'pdata'.
1728 * Returns 0 on success, non-0 otherwise.
1729 * Assumes vcpu_load() was already called.
1730 */
1731int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1732{
1733 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1734}
1735
9ba075a6
AK		 1736static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1737{
0bed3b56
SY		 1738 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1739
9ba075a6
AK		 1740 if (!msr_mtrr_valid(msr))
1741 return 1;
1742
0bed3b56
SY		 1743 if (msr == MSR_MTRRdefType)
1744 *pdata = vcpu->arch.mtrr_state.def_type +
1745 (vcpu->arch.mtrr_state.enabled << 10);
1746 else if (msr == MSR_MTRRfix64K_00000)
1747 *pdata = p[0];
1748 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1749 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1750 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1751 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1752 else if (msr == MSR_IA32_CR_PAT)
1753 *pdata = vcpu->arch.pat;
1754 else { /* Variable MTRRs */
1755 int idx, is_mtrr_mask;
1756 u64 *pt;
1757
1758 idx = (msr - 0x200) / 2;
1759 is_mtrr_mask = msr - 0x200 - 2 * idx;
1760 if (!is_mtrr_mask)
1761 pt =
1762 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1763 else
1764 pt =
1765 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1766 *pdata = *pt;
1767 }
1768
9ba075a6
AK		 1769 return 0;
1770}
1771
890ca9ae 1772static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1773{
1774 u64 data;
890ca9ae
HY		 1775 u64 mcg_cap = vcpu->arch.mcg_cap;
1776 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1777
1778 switch (msr) {
15c4a640
CO		 1779 case MSR_IA32_P5_MC_ADDR:
1780 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1781 data = 0;
1782 break;
15c4a640 1783 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1784 data = vcpu->arch.mcg_cap;
1785 break;
c7ac679c 1786 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1787 if (!(mcg_cap & MCG_CTL_P))
1788 return 1;
1789 data = vcpu->arch.mcg_ctl;
1790 break;
1791 case MSR_IA32_MCG_STATUS:
1792 data = vcpu->arch.mcg_status;
1793 break;
1794 default:
1795 if (msr >= MSR_IA32_MC0_CTL &&
1796 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1797 u32 offset = msr - MSR_IA32_MC0_CTL;
1798 data = vcpu->arch.mce_banks[offset];
1799 break;
1800 }
1801 return 1;
1802 }
1803 *pdata = data;
1804 return 0;
1805}
1806
55cd8e5a
GN		 1807static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1808{
1809 u64 data = 0;
1810 struct kvm *kvm = vcpu->kvm;
1811
1812 switch (msr) {
1813 case HV_X64_MSR_GUEST_OS_ID:
1814 data = kvm->arch.hv_guest_os_id;
1815 break;
1816 case HV_X64_MSR_HYPERCALL:
1817 data = kvm->arch.hv_hypercall;
1818 break;
1819 default:
1820 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1821 return 1;
1822 }
1823
1824 *pdata = data;
1825 return 0;
1826}
1827
1828static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1829{
1830 u64 data = 0;
1831
1832 switch (msr) {
1833 case HV_X64_MSR_VP_INDEX: {
1834 int r;
1835 struct kvm_vcpu *v;
1836 kvm_for_each_vcpu(r, v, vcpu->kvm)
1837 if (v == vcpu)
1838 data = r;
1839 break;
1840 }
10388a07
GN		 1841 case HV_X64_MSR_EOI:
1842 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1843 case HV_X64_MSR_ICR:
1844 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1845 case HV_X64_MSR_TPR:
1846 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1847 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1848 data = vcpu->arch.hv_vapic;
1849 break;
55cd8e5a
GN		 1850 default:
1851 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1852 return 1;
1853 }
1854 *pdata = data;
1855 return 0;
1856}
1857
890ca9ae
HY		 1858int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1859{
1860 u64 data;
1861
1862 switch (msr) {
890ca9ae 1863 case MSR_IA32_PLATFORM_ID:
15c4a640 1864 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1865 case MSR_IA32_DEBUGCTLMSR:
1866 case MSR_IA32_LASTBRANCHFROMIP:
1867 case MSR_IA32_LASTBRANCHTOIP:
1868 case MSR_IA32_LASTINTFROMIP:
1869 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1870 case MSR_K8_SYSCFG:
1871 case MSR_K7_HWCR:
61a6bd67 1872 case MSR_VM_HSAVE_PA:
9e699624 1873 case MSR_K7_EVNTSEL0:
1f3ee616 1874 case MSR_K7_PERFCTR0:
1fdbd48c 1875 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1876 case MSR_AMD64_NB_CFG:
f7c6d140 1877 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1878 data = 0;
1879 break;
5753785f
GN		 1880 case MSR_P6_PERFCTR0:
1881 case MSR_P6_PERFCTR1:
1882 case MSR_P6_EVNTSEL0:
1883 case MSR_P6_EVNTSEL1:
1884 if (kvm_pmu_msr(vcpu, msr))
1885 return kvm_pmu_get_msr(vcpu, msr, pdata);
1886 data = 0;
1887 break;
742bc670
MT		 1888 case MSR_IA32_UCODE_REV:
1889 data = 0x100000000ULL;
1890 break;
9ba075a6
AK		 1891 case MSR_MTRRcap:
1892 data = 0x500 | KVM_NR_VAR_MTRR;
1893 break;
1894 case 0x200 ... 0x2ff:
1895 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1896 case 0xcd: /* fsb frequency */
1897 data = 3;
1898 break;
7b914098
JS		 1899 /*
1900 * MSR_EBC_FREQUENCY_ID
1901 * Conservative value valid for even the basic CPU models.
1902 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1903 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1904 * and 266MHz for model 3, or 4. Set Core Clock
1905 * Frequency to System Bus Frequency Ratio to 1 (bits
1906 * 31:24) even though these are only valid for CPU
1907 * models > 2, however guests may end up dividing or
1908 * multiplying by zero otherwise.
1909 */
1910 case MSR_EBC_FREQUENCY_ID:
1911 data = 1 << 24;
1912 break;
15c4a640
CO		 1913 case MSR_IA32_APICBASE:
1914 data = kvm_get_apic_base(vcpu);
1915 break;
0105d1a5
GN		 1916 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1917 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1918 break;
a3e06bbe
LJ		 1919 case MSR_IA32_TSCDEADLINE:
1920 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1921 break;
15c4a640 1922 case MSR_IA32_MISC_ENABLE:
ad312c7c 1923 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1924 break;
847f0ad8
AG		 1925 case MSR_IA32_PERF_STATUS:
1926 /* TSC increment by tick */
1927 data = 1000ULL;
1928 /* CPU multiplier */
1929 data |= (((uint64_t)4ULL) << 40);
1930 break;
15c4a640 1931 case MSR_EFER:
f6801dff 1932 data = vcpu->arch.efer;
15c4a640 1933 break;
18068523 1934 case MSR_KVM_WALL_CLOCK:
11c6bffa 1935 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1936 data = vcpu->kvm->arch.wall_clock;
1937 break;
1938 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1939 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1940 data = vcpu->arch.time;
1941 break;
344d9588
GN		 1942 case MSR_KVM_ASYNC_PF_EN:
1943 data = vcpu->arch.apf.msr_val;
1944 break;
c9aaa895
GC		 1945 case MSR_KVM_STEAL_TIME:
1946 data = vcpu->arch.st.msr_val;
1947 break;
890ca9ae
HY		 1948 case MSR_IA32_P5_MC_ADDR:
1949 case MSR_IA32_P5_MC_TYPE:
1950 case MSR_IA32_MCG_CAP:
1951 case MSR_IA32_MCG_CTL:
1952 case MSR_IA32_MCG_STATUS:
1953 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1954 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1955 case MSR_K7_CLK_CTL:
1956 /*
1957 * Provide expected ramp-up count for K7. All other
1958 * are set to zero, indicating minimum divisors for
1959 * every field.
1960 *
1961 * This prevents guest kernels on AMD host with CPU
1962 * type 6, model 8 and higher from exploding due to
1963 * the rdmsr failing.
1964 */
1965 data = 0x20000000;
1966 break;
55cd8e5a
GN		 1967 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1968 if (kvm_hv_msr_partition_wide(msr)) {
1969 int r;
1970 mutex_lock(&vcpu->kvm->lock);
1971 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1972 mutex_unlock(&vcpu->kvm->lock);
1973 return r;
1974 } else
1975 return get_msr_hyperv(vcpu, msr, pdata);
1976 break;
91c9c3ed 1977 case MSR_IA32_BBL_CR_CTL3:
1978 /* This legacy MSR exists but isn't fully documented in current
1979 * silicon. It is however accessed by winxp in very narrow
1980 * scenarios where it sets bit #19, itself documented as
1981 * a "reserved" bit. Best effort attempt to source coherent
1982 * read data here should the balance of the register be
1983 * interpreted by the guest:
1984 *
1985 * L2 cache control register 3: 64GB range, 256KB size,
1986 * enabled, latency 0x1, configured
1987 */
1988 data = 0xbe702111;
1989 break;
2b036c6b
BO		 1990 case MSR_AMD64_OSVW_ID_LENGTH:
1991 if (!guest_cpuid_has_osvw(vcpu))
1992 return 1;
1993 data = vcpu->arch.osvw.length;
1994 break;
1995 case MSR_AMD64_OSVW_STATUS:
1996 if (!guest_cpuid_has_osvw(vcpu))
1997 return 1;
1998 data = vcpu->arch.osvw.status;
1999 break;
15c4a640 2000 default:
f5132b01
GN		 2001 if (kvm_pmu_msr(vcpu, msr))
2002 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068
AP		 2003 if (!ignore_msrs) {
2004 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2005 return 1;
2006 } else {
2007 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2008 data = 0;
2009 }
2010 break;
15c4a640
CO		 2011 }
2012 *pdata = data;
2013 return 0;
2014}
2015EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2016
313a3dc7
CO		 2017/*
2018 * Read or write a bunch of msrs. All parameters are kernel addresses.
2019 *
2020 * @return number of msrs set successfully.
2021 */
2022static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2023 struct kvm_msr_entry *entries,
2024 int (*do_msr)(struct kvm_vcpu *vcpu,
2025 unsigned index, u64 *data))
2026{
f656ce01 2027 int i, idx;
313a3dc7 2028
f656ce01 2029 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2030 for (i = 0; i < msrs->nmsrs; ++i)
2031 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2032 break;
f656ce01 2033 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2034
313a3dc7
CO		 2035 return i;
2036}
2037
2038/*
2039 * Read or write a bunch of msrs. Parameters are user addresses.
2040 *
2041 * @return number of msrs set successfully.
2042 */
2043static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2044 int (*do_msr)(struct kvm_vcpu *vcpu,
2045 unsigned index, u64 *data),
2046 int writeback)
2047{
2048 struct kvm_msrs msrs;
2049 struct kvm_msr_entry *entries;
2050 int r, n;
2051 unsigned size;
2052
2053 r = -EFAULT;
2054 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2055 goto out;
2056
2057 r = -E2BIG;
2058 if (msrs.nmsrs >= MAX_IO_MSRS)
2059 goto out;
2060
313a3dc7 2061 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2062 entries = memdup_user(user_msrs->entries, size);
2063 if (IS_ERR(entries)) {
2064 r = PTR_ERR(entries);
313a3dc7 2065 goto out;
ff5c2c03 2066 }
313a3dc7
CO		 2067
2068 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2069 if (r < 0)
2070 goto out_free;
2071
2072 r = -EFAULT;
2073 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2074 goto out_free;
2075
2076 r = n;
2077
2078out_free:
7a73c028 2079 kfree(entries);
313a3dc7
CO		 2080out:
2081 return r;
2082}
2083
018d00d2
ZX		 2084int kvm_dev_ioctl_check_extension(long ext)
2085{
2086 int r;
2087
2088 switch (ext) {
2089 case KVM_CAP_IRQCHIP:
2090 case KVM_CAP_HLT:
2091 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2092 case KVM_CAP_SET_TSS_ADDR:
07716717 2093 case KVM_CAP_EXT_CPUID:
c8076604 2094 case KVM_CAP_CLOCKSOURCE:
7837699f 2095 case KVM_CAP_PIT:
a28e4f5a 2096 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2097 case KVM_CAP_MP_STATE:
ed848624 2098 case KVM_CAP_SYNC_MMU:
a355c85c 2099 case KVM_CAP_USER_NMI:
52d939a0 2100 case KVM_CAP_REINJECT_CONTROL:
4925663a 2101 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2102 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2103 case KVM_CAP_IRQFD:
d34e6b17 2104 case KVM_CAP_IOEVENTFD:
c5ff41ce 2105 case KVM_CAP_PIT2:
e9f42757 2106 case KVM_CAP_PIT_STATE2:
b927a3ce 2107 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2108 case KVM_CAP_XEN_HVM:
afbcf7ab 2109 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2110 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2111 case KVM_CAP_HYPERV:
10388a07 2112 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2113 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2114 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2115 case KVM_CAP_DEBUGREGS:
d2be1651 2116 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2117 case KVM_CAP_XSAVE:
344d9588 2118 case KVM_CAP_ASYNC_PF:
92a1f12d 2119 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2120 r = 1;
2121 break;
542472b5
LV		 2122 case KVM_CAP_COALESCED_MMIO:
2123 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2124 break;
774ead3a
AK		 2125 case KVM_CAP_VAPIC:
2126 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2127 break;
f725230a 2128 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2129 r = KVM_SOFT_MAX_VCPUS;
2130 break;
2131 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2132 r = KVM_MAX_VCPUS;
2133 break;
a988b910
AK		 2134 case KVM_CAP_NR_MEMSLOTS:
2135 r = KVM_MEMORY_SLOTS;
2136 break;
a68a6a72
MT		 2137 case KVM_CAP_PV_MMU: /* obsolete */
2138 r = 0;
2f333bcb 2139 break;
62c476c7 2140 case KVM_CAP_IOMMU:
a1b60c1c 2141 r = iommu_present(&pci_bus_type);
62c476c7 2142 break;
890ca9ae
HY		 2143 case KVM_CAP_MCE:
2144 r = KVM_MAX_MCE_BANKS;
2145 break;
2d5b5a66
SY		 2146 case KVM_CAP_XCRS:
2147 r = cpu_has_xsave;
2148 break;
92a1f12d
JR		 2149 case KVM_CAP_TSC_CONTROL:
2150 r = kvm_has_tsc_control;
2151 break;
4d25a066
JK		 2152 case KVM_CAP_TSC_DEADLINE_TIMER:
2153 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2154 break;
018d00d2
ZX		 2155 default:
2156 r = 0;
2157 break;
2158 }
2159 return r;
2160
2161}
2162
043405e1
CO		 2163long kvm_arch_dev_ioctl(struct file *filp,
2164 unsigned int ioctl, unsigned long arg)
2165{
2166 void __user *argp = (void __user *)arg;
2167 long r;
2168
2169 switch (ioctl) {
2170 case KVM_GET_MSR_INDEX_LIST: {
2171 struct kvm_msr_list __user *user_msr_list = argp;
2172 struct kvm_msr_list msr_list;
2173 unsigned n;
2174
2175 r = -EFAULT;
2176 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2177 goto out;
2178 n = msr_list.nmsrs;
2179 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2180 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2181 goto out;
2182 r = -E2BIG;
e125e7b6 2183 if (n < msr_list.nmsrs)
043405e1
CO		 2184 goto out;
2185 r = -EFAULT;
2186 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2187 num_msrs_to_save * sizeof(u32)))
2188 goto out;
e125e7b6 2189 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2190 &emulated_msrs,
2191 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2192 goto out;
2193 r = 0;
2194 break;
2195 }
674eea0f
AK		 2196 case KVM_GET_SUPPORTED_CPUID: {
2197 struct kvm_cpuid2 __user *cpuid_arg = argp;
2198 struct kvm_cpuid2 cpuid;
2199
2200 r = -EFAULT;
2201 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2202 goto out;
2203 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2204 cpuid_arg->entries);
674eea0f
AK		 2205 if (r)
2206 goto out;
2207
2208 r = -EFAULT;
2209 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2210 goto out;
2211 r = 0;
2212 break;
2213 }
890ca9ae
HY		 2214 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2215 u64 mce_cap;
2216
2217 mce_cap = KVM_MCE_CAP_SUPPORTED;
2218 r = -EFAULT;
2219 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2220 goto out;
2221 r = 0;
2222 break;
2223 }
043405e1
CO		 2224 default:
2225 r = -EINVAL;
2226 }
2227out:
2228 return r;
2229}
2230
f5f48ee1
SY		 2231static void wbinvd_ipi(void *garbage)
2232{
2233 wbinvd();
2234}
2235
2236static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2237{
2238 return vcpu->kvm->arch.iommu_domain &&
2239 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2240}
2241
313a3dc7
CO		 2242void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2243{
f5f48ee1
SY		 2244 /* Address WBINVD may be executed by guest */
2245 if (need_emulate_wbinvd(vcpu)) {
2246 if (kvm_x86_ops->has_wbinvd_exit())
2247 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2248 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2249 smp_call_function_single(vcpu->cpu,
2250 wbinvd_ipi, NULL, 1);
2251 }
2252
313a3dc7 2253 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2254 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2255 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2256 s64 tsc_delta;
2257 u64 tsc;
2258
d5c1785d 2259 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
8f6055cb
JR		 2260 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2261 tsc - vcpu->arch.last_guest_tsc;
2262
e48672fa
ZA		 2263 if (tsc_delta < 0)
2264 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2265 if (check_tsc_unstable()) {
e48672fa 2266 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2267 vcpu->arch.tsc_catchup = 1;
c285545f 2268 }
1aa8ceef 2269 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2270 if (vcpu->cpu != cpu)
2271 kvm_migrate_timers(vcpu);
e48672fa 2272 vcpu->cpu = cpu;
6b7d7e76 2273 }
c9aaa895
GC		 2274
2275 accumulate_steal_time(vcpu);
2276 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2277}
2278
2279void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2280{
02daab21 2281 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2282 kvm_put_guest_fpu(vcpu);
d5c1785d 2283 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
313a3dc7
CO		 2284}
2285
313a3dc7
CO		 2286static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2287 struct kvm_lapic_state *s)
2288{
ad312c7c 2289 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2290
2291 return 0;
2292}
2293
2294static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2295 struct kvm_lapic_state *s)
2296{
ad312c7c 2297 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2298 kvm_apic_post_state_restore(vcpu);
cb142eb7 2299 update_cr8_intercept(vcpu);
313a3dc7
CO		 2300
2301 return 0;
2302}
2303
f77bc6a4
ZX		 2304static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2305 struct kvm_interrupt *irq)
2306{
2307 if (irq->irq < 0 || irq->irq >= 256)
2308 return -EINVAL;
2309 if (irqchip_in_kernel(vcpu->kvm))
2310 return -ENXIO;
f77bc6a4 2311
66fd3f7f 2312 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2313 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2314
f77bc6a4
ZX		 2315 return 0;
2316}
2317
c4abb7c9
JK		 2318static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2319{
c4abb7c9 2320 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2321
2322 return 0;
2323}
2324
b209749f
AK		 2325static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2326 struct kvm_tpr_access_ctl *tac)
2327{
2328 if (tac->flags)
2329 return -EINVAL;
2330 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2331 return 0;
2332}
2333
890ca9ae
HY		 2334static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2335 u64 mcg_cap)
2336{
2337 int r;
2338 unsigned bank_num = mcg_cap & 0xff, bank;
2339
2340 r = -EINVAL;
a9e38c3e 2341 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2342 goto out;
2343 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2344 goto out;
2345 r = 0;
2346 vcpu->arch.mcg_cap = mcg_cap;
2347 /* Init IA32_MCG_CTL to all 1s */
2348 if (mcg_cap & MCG_CTL_P)
2349 vcpu->arch.mcg_ctl = ~(u64)0;
2350 /* Init IA32_MCi_CTL to all 1s */
2351 for (bank = 0; bank < bank_num; bank++)
2352 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2353out:
2354 return r;
2355}
2356
2357static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2358 struct kvm_x86_mce *mce)
2359{
2360 u64 mcg_cap = vcpu->arch.mcg_cap;
2361 unsigned bank_num = mcg_cap & 0xff;
2362 u64 *banks = vcpu->arch.mce_banks;
2363
2364 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2365 return -EINVAL;
2366 /*
2367 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2368 * reporting is disabled
2369 */
2370 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2371 vcpu->arch.mcg_ctl != ~(u64)0)
2372 return 0;
2373 banks += 4 * mce->bank;
2374 /*
2375 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2376 * reporting is disabled for the bank
2377 */
2378 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2379 return 0;
2380 if (mce->status & MCI_STATUS_UC) {
2381 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2382 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2383 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2384 return 0;
2385 }
2386 if (banks[1] & MCI_STATUS_VAL)
2387 mce->status |= MCI_STATUS_OVER;
2388 banks[2] = mce->addr;
2389 banks[3] = mce->misc;
2390 vcpu->arch.mcg_status = mce->mcg_status;
2391 banks[1] = mce->status;
2392 kvm_queue_exception(vcpu, MC_VECTOR);
2393 } else if (!(banks[1] & MCI_STATUS_VAL)
2394 || !(banks[1] & MCI_STATUS_UC)) {
2395 if (banks[1] & MCI_STATUS_VAL)
2396 mce->status |= MCI_STATUS_OVER;
2397 banks[2] = mce->addr;
2398 banks[3] = mce->misc;
2399 banks[1] = mce->status;
2400 } else
2401 banks[1] |= MCI_STATUS_OVER;
2402 return 0;
2403}
2404
3cfc3092
JK		 2405static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2406 struct kvm_vcpu_events *events)
2407{
7460fb4a 2408 process_nmi(vcpu);
03b82a30
JK		 2409 events->exception.injected =
2410 vcpu->arch.exception.pending &&
2411 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2412 events->exception.nr = vcpu->arch.exception.nr;
2413 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2414 events->exception.pad = 0;
3cfc3092
JK		 2415 events->exception.error_code = vcpu->arch.exception.error_code;
2416
03b82a30
JK		 2417 events->interrupt.injected =
2418 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2419 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2420 events->interrupt.soft = 0;
48005f64
JK		 2421 events->interrupt.shadow =
2422 kvm_x86_ops->get_interrupt_shadow(vcpu,
2423 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2424
2425 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2426 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2427 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2428 events->nmi.pad = 0;
3cfc3092
JK		 2429
2430 events->sipi_vector = vcpu->arch.sipi_vector;
2431
dab4b911 2432 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2433 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2434 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2435 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2436}
2437
2438static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2439 struct kvm_vcpu_events *events)
2440{
dab4b911 2441 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2442 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2443 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2444 return -EINVAL;
2445
7460fb4a 2446 process_nmi(vcpu);
3cfc3092
JK		 2447 vcpu->arch.exception.pending = events->exception.injected;
2448 vcpu->arch.exception.nr = events->exception.nr;
2449 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2450 vcpu->arch.exception.error_code = events->exception.error_code;
2451
2452 vcpu->arch.interrupt.pending = events->interrupt.injected;
2453 vcpu->arch.interrupt.nr = events->interrupt.nr;
2454 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2455 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2456 kvm_x86_ops->set_interrupt_shadow(vcpu,
2457 events->interrupt.shadow);
3cfc3092
JK		 2458
2459 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2460 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2461 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2462 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2463
dab4b911
JK		 2464 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2465 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2466
3842d135
AK		 2467 kvm_make_request(KVM_REQ_EVENT, vcpu);
2468
3cfc3092
JK		 2469 return 0;
2470}
2471
a1efbe77
JK		 2472static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2473 struct kvm_debugregs *dbgregs)
2474{
a1efbe77
JK		 2475 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2476 dbgregs->dr6 = vcpu->arch.dr6;
2477 dbgregs->dr7 = vcpu->arch.dr7;
2478 dbgregs->flags = 0;
97e69aa6 2479 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2480}
2481
2482static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2483 struct kvm_debugregs *dbgregs)
2484{
2485 if (dbgregs->flags)
2486 return -EINVAL;
2487
a1efbe77
JK		 2488 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2489 vcpu->arch.dr6 = dbgregs->dr6;
2490 vcpu->arch.dr7 = dbgregs->dr7;
2491
a1efbe77
JK		 2492 return 0;
2493}
2494
2d5b5a66
SY		 2495static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2496 struct kvm_xsave *guest_xsave)
2497{
2498 if (cpu_has_xsave)
2499 memcpy(guest_xsave->region,
2500 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2501 xstate_size);
2d5b5a66
SY		 2502 else {
2503 memcpy(guest_xsave->region,
2504 &vcpu->arch.guest_fpu.state->fxsave,
2505 sizeof(struct i387_fxsave_struct));
2506 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2507 XSTATE_FPSSE;
2508 }
2509}
2510
2511static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2512 struct kvm_xsave *guest_xsave)
2513{
2514 u64 xstate_bv =
2515 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2516
2517 if (cpu_has_xsave)
2518 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2519 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2520 else {
2521 if (xstate_bv & ~XSTATE_FPSSE)
2522 return -EINVAL;
2523 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2524 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2525 }
2526 return 0;
2527}
2528
2529static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2530 struct kvm_xcrs *guest_xcrs)
2531{
2532 if (!cpu_has_xsave) {
2533 guest_xcrs->nr_xcrs = 0;
2534 return;
2535 }
2536
2537 guest_xcrs->nr_xcrs = 1;
2538 guest_xcrs->flags = 0;
2539 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2540 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2541}
2542
2543static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2544 struct kvm_xcrs *guest_xcrs)
2545{
2546 int i, r = 0;
2547
2548 if (!cpu_has_xsave)
2549 return -EINVAL;
2550
2551 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2552 return -EINVAL;
2553
2554 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2555 /* Only support XCR0 currently */
2556 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2557 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2558 guest_xcrs->xcrs[0].value);
2559 break;
2560 }
2561 if (r)
2562 r = -EINVAL;
2563 return r;
2564}
2565
313a3dc7
CO		 2566long kvm_arch_vcpu_ioctl(struct file *filp,
2567 unsigned int ioctl, unsigned long arg)
2568{
2569 struct kvm_vcpu *vcpu = filp->private_data;
2570 void __user *argp = (void __user *)arg;
2571 int r;
d1ac91d8
AK		 2572 union {
2573 struct kvm_lapic_state *lapic;
2574 struct kvm_xsave *xsave;
2575 struct kvm_xcrs *xcrs;
2576 void *buffer;
2577 } u;
2578
2579 u.buffer = NULL;
313a3dc7
CO		 2580 switch (ioctl) {
2581 case KVM_GET_LAPIC: {
2204ae3c
MT		 2582 r = -EINVAL;
2583 if (!vcpu->arch.apic)
2584 goto out;
d1ac91d8 2585 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2586
b772ff36 2587 r = -ENOMEM;
d1ac91d8 2588 if (!u.lapic)
b772ff36 2589 goto out;
d1ac91d8 2590 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2591 if (r)
2592 goto out;
2593 r = -EFAULT;
d1ac91d8 2594 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2595 goto out;
2596 r = 0;
2597 break;
2598 }
2599 case KVM_SET_LAPIC: {
2204ae3c
MT		 2600 r = -EINVAL;
2601 if (!vcpu->arch.apic)
2602 goto out;
ff5c2c03
SL		 2603 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2604 if (IS_ERR(u.lapic)) {
2605 r = PTR_ERR(u.lapic);
313a3dc7 2606 goto out;
ff5c2c03
SL		 2607 }
2608
d1ac91d8 2609 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2610 if (r)
2611 goto out;
2612 r = 0;
2613 break;
2614 }
f77bc6a4
ZX		 2615 case KVM_INTERRUPT: {
2616 struct kvm_interrupt irq;
2617
2618 r = -EFAULT;
2619 if (copy_from_user(&irq, argp, sizeof irq))
2620 goto out;
2621 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2622 if (r)
2623 goto out;
2624 r = 0;
2625 break;
2626 }
c4abb7c9
JK		 2627 case KVM_NMI: {
2628 r = kvm_vcpu_ioctl_nmi(vcpu);
2629 if (r)
2630 goto out;
2631 r = 0;
2632 break;
2633 }
313a3dc7
CO		 2634 case KVM_SET_CPUID: {
2635 struct kvm_cpuid __user *cpuid_arg = argp;
2636 struct kvm_cpuid cpuid;
2637
2638 r = -EFAULT;
2639 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2640 goto out;
2641 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2642 if (r)
2643 goto out;
2644 break;
2645 }
07716717
DK		 2646 case KVM_SET_CPUID2: {
2647 struct kvm_cpuid2 __user *cpuid_arg = argp;
2648 struct kvm_cpuid2 cpuid;
2649
2650 r = -EFAULT;
2651 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2652 goto out;
2653 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2654 cpuid_arg->entries);
07716717
DK		 2655 if (r)
2656 goto out;
2657 break;
2658 }
2659 case KVM_GET_CPUID2: {
2660 struct kvm_cpuid2 __user *cpuid_arg = argp;
2661 struct kvm_cpuid2 cpuid;
2662
2663 r = -EFAULT;
2664 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2665 goto out;
2666 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2667 cpuid_arg->entries);
07716717
DK		 2668 if (r)
2669 goto out;
2670 r = -EFAULT;
2671 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2672 goto out;
2673 r = 0;
2674 break;
2675 }
313a3dc7
CO		 2676 case KVM_GET_MSRS:
2677 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2678 break;
2679 case KVM_SET_MSRS:
2680 r = msr_io(vcpu, argp, do_set_msr, 0);
2681 break;
b209749f
AK		 2682 case KVM_TPR_ACCESS_REPORTING: {
2683 struct kvm_tpr_access_ctl tac;
2684
2685 r = -EFAULT;
2686 if (copy_from_user(&tac, argp, sizeof tac))
2687 goto out;
2688 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2689 if (r)
2690 goto out;
2691 r = -EFAULT;
2692 if (copy_to_user(argp, &tac, sizeof tac))
2693 goto out;
2694 r = 0;
2695 break;
2696 };
b93463aa
AK		 2697 case KVM_SET_VAPIC_ADDR: {
2698 struct kvm_vapic_addr va;
2699
2700 r = -EINVAL;
2701 if (!irqchip_in_kernel(vcpu->kvm))
2702 goto out;
2703 r = -EFAULT;
2704 if (copy_from_user(&va, argp, sizeof va))
2705 goto out;
2706 r = 0;
2707 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2708 break;
2709 }
890ca9ae
HY		 2710 case KVM_X86_SETUP_MCE: {
2711 u64 mcg_cap;
2712
2713 r = -EFAULT;
2714 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2715 goto out;
2716 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2717 break;
2718 }
2719 case KVM_X86_SET_MCE: {
2720 struct kvm_x86_mce mce;
2721
2722 r = -EFAULT;
2723 if (copy_from_user(&mce, argp, sizeof mce))
2724 goto out;
2725 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2726 break;
2727 }
3cfc3092
JK		 2728 case KVM_GET_VCPU_EVENTS: {
2729 struct kvm_vcpu_events events;
2730
2731 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2732
2733 r = -EFAULT;
2734 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2735 break;
2736 r = 0;
2737 break;
2738 }
2739 case KVM_SET_VCPU_EVENTS: {
2740 struct kvm_vcpu_events events;
2741
2742 r = -EFAULT;
2743 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2744 break;
2745
2746 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2747 break;
2748 }
a1efbe77
JK		 2749 case KVM_GET_DEBUGREGS: {
2750 struct kvm_debugregs dbgregs;
2751
2752 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2753
2754 r = -EFAULT;
2755 if (copy_to_user(argp, &dbgregs,
2756 sizeof(struct kvm_debugregs)))
2757 break;
2758 r = 0;
2759 break;
2760 }
2761 case KVM_SET_DEBUGREGS: {
2762 struct kvm_debugregs dbgregs;
2763
2764 r = -EFAULT;
2765 if (copy_from_user(&dbgregs, argp,
2766 sizeof(struct kvm_debugregs)))
2767 break;
2768
2769 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2770 break;
2771 }
2d5b5a66 2772 case KVM_GET_XSAVE: {
d1ac91d8 2773 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2774 r = -ENOMEM;
d1ac91d8 2775 if (!u.xsave)
2d5b5a66
SY		 2776 break;
2777
d1ac91d8 2778 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2779
2780 r = -EFAULT;
d1ac91d8 2781 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2782 break;
2783 r = 0;
2784 break;
2785 }
2786 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2787 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2788 if (IS_ERR(u.xsave)) {
2789 r = PTR_ERR(u.xsave);
2790 goto out;
2791 }
2d5b5a66 2792
d1ac91d8 2793 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2794 break;
2795 }
2796 case KVM_GET_XCRS: {
d1ac91d8 2797 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2798 r = -ENOMEM;
d1ac91d8 2799 if (!u.xcrs)
2d5b5a66
SY		 2800 break;
2801
d1ac91d8 2802 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2803
2804 r = -EFAULT;
d1ac91d8 2805 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2806 sizeof(struct kvm_xcrs)))
2807 break;
2808 r = 0;
2809 break;
2810 }
2811 case KVM_SET_XCRS: {
ff5c2c03
SL		 2812 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2813 if (IS_ERR(u.xcrs)) {
2814 r = PTR_ERR(u.xcrs);
2815 goto out;
2816 }
2d5b5a66 2817
d1ac91d8 2818 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2819 break;
2820 }
92a1f12d
JR		 2821 case KVM_SET_TSC_KHZ: {
2822 u32 user_tsc_khz;
2823
2824 r = -EINVAL;
92a1f12d
JR		 2825 user_tsc_khz = (u32)arg;
2826
2827 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2828 goto out;
2829
cc578287
ZA		 2830 if (user_tsc_khz == 0)
2831 user_tsc_khz = tsc_khz;
2832
2833 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2834
2835 r = 0;
2836 goto out;
2837 }
2838 case KVM_GET_TSC_KHZ: {
cc578287 2839 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2840 goto out;
2841 }
313a3dc7
CO		 2842 default:
2843 r = -EINVAL;
2844 }
2845out:
d1ac91d8 2846 kfree(u.buffer);
313a3dc7
CO		 2847 return r;
2848}
2849
5b1c1493
CO		 2850int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2851{
2852 return VM_FAULT_SIGBUS;
2853}
2854
1fe779f8
CO		 2855static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2856{
2857 int ret;
2858
2859 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2860 return -1;
2861 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2862 return ret;
2863}
2864
b927a3ce
SY		 2865static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2866 u64 ident_addr)
2867{
2868 kvm->arch.ept_identity_map_addr = ident_addr;
2869 return 0;
2870}
2871
1fe779f8
CO		 2872static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2873 u32 kvm_nr_mmu_pages)
2874{
2875 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2876 return -EINVAL;
2877
79fac95e 2878 mutex_lock(&kvm->slots_lock);
7c8a83b7 2879 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2880
2881 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2882 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2883
7c8a83b7 2884 spin_unlock(&kvm->mmu_lock);
79fac95e 2885 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2886 return 0;
2887}
2888
2889static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2890{
39de71ec 2891 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2892}
2893
1fe779f8
CO		 2894static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2895{
2896 int r;
2897
2898 r = 0;
2899 switch (chip->chip_id) {
2900 case KVM_IRQCHIP_PIC_MASTER:
2901 memcpy(&chip->chip.pic,
2902 &pic_irqchip(kvm)->pics[0],
2903 sizeof(struct kvm_pic_state));
2904 break;
2905 case KVM_IRQCHIP_PIC_SLAVE:
2906 memcpy(&chip->chip.pic,
2907 &pic_irqchip(kvm)->pics[1],
2908 sizeof(struct kvm_pic_state));
2909 break;
2910 case KVM_IRQCHIP_IOAPIC:
eba0226b 2911 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2912 break;
2913 default:
2914 r = -EINVAL;
2915 break;
2916 }
2917 return r;
2918}
2919
2920static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2921{
2922 int r;
2923
2924 r = 0;
2925 switch (chip->chip_id) {
2926 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2927 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2928 memcpy(&pic_irqchip(kvm)->pics[0],
2929 &chip->chip.pic,
2930 sizeof(struct kvm_pic_state));
f4f51050 2931 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2932 break;
2933 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2934 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2935 memcpy(&pic_irqchip(kvm)->pics[1],
2936 &chip->chip.pic,
2937 sizeof(struct kvm_pic_state));
f4f51050 2938 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2939 break;
2940 case KVM_IRQCHIP_IOAPIC:
eba0226b 2941 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2942 break;
2943 default:
2944 r = -EINVAL;
2945 break;
2946 }
2947 kvm_pic_update_irq(pic_irqchip(kvm));
2948 return r;
2949}
2950
e0f63cb9
SY		 2951static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2952{
2953 int r = 0;
2954
894a9c55 2955 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2956 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2957 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2958 return r;
2959}
2960
2961static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2962{
2963 int r = 0;
2964
894a9c55 2965 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2966 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2967 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2968 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2969 return r;
2970}
2971
2972static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2973{
2974 int r = 0;
2975
2976 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2977 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2978 sizeof(ps->channels));
2979 ps->flags = kvm->arch.vpit->pit_state.flags;
2980 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 2981 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 2982 return r;
2983}
2984
2985static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2986{
2987 int r = 0, start = 0;
2988 u32 prev_legacy, cur_legacy;
2989 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2990 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2991 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2992 if (!prev_legacy && cur_legacy)
2993 start = 1;
2994 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2995 sizeof(kvm->arch.vpit->pit_state.channels));
2996 kvm->arch.vpit->pit_state.flags = ps->flags;
2997 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2998 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2999 return r;
3000}
3001
52d939a0
MT		 3002static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3003 struct kvm_reinject_control *control)
3004{
3005 if (!kvm->arch.vpit)
3006 return -ENXIO;
894a9c55 3007 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3008 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3009 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3010 return 0;
3011}
3012
95d4c16c
TY		 3013/**
3014 * write_protect_slot - write protect a slot for dirty logging
3015 * @kvm: the kvm instance
3016 * @memslot: the slot we protect
3017 * @dirty_bitmap: the bitmap indicating which pages are dirty
3018 * @nr_dirty_pages: the number of dirty pages
3019 *
3020 * We have two ways to find all sptes to protect:
3021 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3022 * checks ones that have a spte mapping a page in the slot.
3023 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3024 *
3025 * Generally speaking, if there are not so many dirty pages compared to the
3026 * number of shadow pages, we should use the latter.
3027 *
3028 * Note that letting others write into a page marked dirty in the old bitmap
3029 * by using the remaining tlb entry is not a problem. That page will become
3030 * write protected again when we flush the tlb and then be reported dirty to
3031 * the user space by copying the old bitmap.
3032 */
3033static void write_protect_slot(struct kvm *kvm,
3034 struct kvm_memory_slot *memslot,
3035 unsigned long *dirty_bitmap,
3036 unsigned long nr_dirty_pages)
3037{
3038 /* Not many dirty pages compared to # of shadow pages. */
3039 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3040 unsigned long gfn_offset;
3041
3042 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3043 unsigned long gfn = memslot->base_gfn + gfn_offset;
3044
3045 spin_lock(&kvm->mmu_lock);
3046 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
3047 spin_unlock(&kvm->mmu_lock);
3048 }
3049 kvm_flush_remote_tlbs(kvm);
3050 } else {
3051 spin_lock(&kvm->mmu_lock);
3052 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
3053 spin_unlock(&kvm->mmu_lock);
3054 }
3055}
3056
5bb064dc
ZX		 3057/*
3058 * Get (and clear) the dirty memory log for a memory slot.
3059 */
3060int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3061 struct kvm_dirty_log *log)
3062{
7850ac54 3063 int r;
5bb064dc 3064 struct kvm_memory_slot *memslot;
95d4c16c 3065 unsigned long n, nr_dirty_pages;
5bb064dc 3066
79fac95e 3067 mutex_lock(&kvm->slots_lock);
5bb064dc 3068
b050b015
MT		 3069 r = -EINVAL;
3070 if (log->slot >= KVM_MEMORY_SLOTS)
3071 goto out;
3072
28a37544 3073 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3074 r = -ENOENT;
3075 if (!memslot->dirty_bitmap)
3076 goto out;
3077
87bf6e7d 3078 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3079 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3080
5bb064dc 3081 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3082 if (nr_dirty_pages) {
b050b015 3083 struct kvm_memslots *slots, *old_slots;
28a37544 3084 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3085
28a37544
XG		 3086 dirty_bitmap = memslot->dirty_bitmap;
3087 dirty_bitmap_head = memslot->dirty_bitmap_head;
3088 if (dirty_bitmap == dirty_bitmap_head)
3089 dirty_bitmap_head += n / sizeof(long);
3090 memset(dirty_bitmap_head, 0, n);
b050b015 3091
914ebccd 3092 r = -ENOMEM;
cdfca7b3 3093 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3094 if (!slots)
914ebccd 3095 goto out;
cdfca7b3 3096
28a37544 3097 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3098 memslot->nr_dirty_pages = 0;
28a37544 3099 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3100 update_memslots(slots, NULL);
b050b015
MT		 3101
3102 old_slots = kvm->memslots;
3103 rcu_assign_pointer(kvm->memslots, slots);
3104 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3105 kfree(old_slots);
914ebccd 3106
95d4c16c 3107 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3108
914ebccd 3109 r = -EFAULT;
515a0127 3110 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3111 goto out;
914ebccd
TY		 3112 } else {
3113 r = -EFAULT;
3114 if (clear_user(log->dirty_bitmap, n))
3115 goto out;
5bb064dc 3116 }
b050b015 3117
5bb064dc
ZX		 3118 r = 0;
3119out:
79fac95e 3120 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3121 return r;
3122}
3123
1fe779f8
CO		 3124long kvm_arch_vm_ioctl(struct file *filp,
3125 unsigned int ioctl, unsigned long arg)
3126{
3127 struct kvm *kvm = filp->private_data;
3128 void __user *argp = (void __user *)arg;
367e1319 3129 int r = -ENOTTY;
f0d66275
DH		 3130 /*
3131 * This union makes it completely explicit to gcc-3.x
3132 * that these two variables' stack usage should be
3133 * combined, not added together.
3134 */
3135 union {
3136 struct kvm_pit_state ps;
e9f42757 3137 struct kvm_pit_state2 ps2;
c5ff41ce 3138 struct kvm_pit_config pit_config;
f0d66275 3139 } u;
1fe779f8
CO		 3140
3141 switch (ioctl) {
3142 case KVM_SET_TSS_ADDR:
3143 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3144 if (r < 0)
3145 goto out;
3146 break;
b927a3ce
SY		 3147 case KVM_SET_IDENTITY_MAP_ADDR: {
3148 u64 ident_addr;
3149
3150 r = -EFAULT;
3151 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3152 goto out;
3153 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3154 if (r < 0)
3155 goto out;
3156 break;
3157 }
1fe779f8
CO		 3158 case KVM_SET_NR_MMU_PAGES:
3159 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3160 if (r)
3161 goto out;
3162 break;
3163 case KVM_GET_NR_MMU_PAGES:
3164 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3165 break;
3ddea128
MT		 3166 case KVM_CREATE_IRQCHIP: {
3167 struct kvm_pic *vpic;
3168
3169 mutex_lock(&kvm->lock);
3170 r = -EEXIST;
3171 if (kvm->arch.vpic)
3172 goto create_irqchip_unlock;
1fe779f8 3173 r = -ENOMEM;
3ddea128
MT		 3174 vpic = kvm_create_pic(kvm);
3175 if (vpic) {
1fe779f8
CO		 3176 r = kvm_ioapic_init(kvm);
3177 if (r) {
175504cd 3178 mutex_lock(&kvm->slots_lock);
72bb2fcd 3179 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3180 &vpic->dev_master);
3181 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3182 &vpic->dev_slave);
3183 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3184 &vpic->dev_eclr);
175504cd 3185 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3186 kfree(vpic);
3187 goto create_irqchip_unlock;
1fe779f8
CO		 3188 }
3189 } else
3ddea128
MT		 3190 goto create_irqchip_unlock;
3191 smp_wmb();
3192 kvm->arch.vpic = vpic;
3193 smp_wmb();
399ec807
AK		 3194 r = kvm_setup_default_irq_routing(kvm);
3195 if (r) {
175504cd 3196 mutex_lock(&kvm->slots_lock);
3ddea128 3197 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3198 kvm_ioapic_destroy(kvm);
3199 kvm_destroy_pic(kvm);
3ddea128 3200 mutex_unlock(&kvm->irq_lock);
175504cd 3201 mutex_unlock(&kvm->slots_lock);
399ec807 3202 }
3ddea128
MT		 3203 create_irqchip_unlock:
3204 mutex_unlock(&kvm->lock);
1fe779f8 3205 break;
3ddea128 3206 }
7837699f 3207 case KVM_CREATE_PIT:
c5ff41ce
JK		 3208 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3209 goto create_pit;
3210 case KVM_CREATE_PIT2:
3211 r = -EFAULT;
3212 if (copy_from_user(&u.pit_config, argp,
3213 sizeof(struct kvm_pit_config)))
3214 goto out;
3215 create_pit:
79fac95e 3216 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3217 r = -EEXIST;
3218 if (kvm->arch.vpit)
3219 goto create_pit_unlock;
7837699f 3220 r = -ENOMEM;
c5ff41ce 3221 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3222 if (kvm->arch.vpit)
3223 r = 0;
269e05e4 3224 create_pit_unlock:
79fac95e 3225 mutex_unlock(&kvm->slots_lock);
7837699f 3226 break;
4925663a 3227 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3228 case KVM_IRQ_LINE: {
3229 struct kvm_irq_level irq_event;
3230
3231 r = -EFAULT;
3232 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3233 goto out;
160d2f6c 3234 r = -ENXIO;
1fe779f8 3235 if (irqchip_in_kernel(kvm)) {
4925663a 3236 __s32 status;
4925663a
GN		 3237 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3238 irq_event.irq, irq_event.level);
4925663a 3239 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3240 r = -EFAULT;
4925663a
GN		 3241 irq_event.status = status;
3242 if (copy_to_user(argp, &irq_event,
3243 sizeof irq_event))
3244 goto out;
3245 }
1fe779f8
CO		 3246 r = 0;
3247 }
3248 break;
3249 }
3250 case KVM_GET_IRQCHIP: {
3251 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3252 struct kvm_irqchip *chip;
1fe779f8 3253
ff5c2c03
SL		 3254 chip = memdup_user(argp, sizeof(*chip));
3255 if (IS_ERR(chip)) {
3256 r = PTR_ERR(chip);
1fe779f8 3257 goto out;
ff5c2c03
SL		 3258 }
3259
1fe779f8
CO		 3260 r = -ENXIO;
3261 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3262 goto get_irqchip_out;
3263 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3264 if (r)
f0d66275 3265 goto get_irqchip_out;
1fe779f8 3266 r = -EFAULT;
f0d66275
DH		 3267 if (copy_to_user(argp, chip, sizeof *chip))
3268 goto get_irqchip_out;
1fe779f8 3269 r = 0;
f0d66275
DH		 3270 get_irqchip_out:
3271 kfree(chip);
3272 if (r)
3273 goto out;
1fe779f8
CO		 3274 break;
3275 }
3276 case KVM_SET_IRQCHIP: {
3277 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3278 struct kvm_irqchip *chip;
1fe779f8 3279
ff5c2c03
SL		 3280 chip = memdup_user(argp, sizeof(*chip));
3281 if (IS_ERR(chip)) {
3282 r = PTR_ERR(chip);
1fe779f8 3283 goto out;
ff5c2c03
SL		 3284 }
3285
1fe779f8
CO		 3286 r = -ENXIO;
3287 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3288 goto set_irqchip_out;
3289 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3290 if (r)
f0d66275 3291 goto set_irqchip_out;
1fe779f8 3292 r = 0;
f0d66275
DH		 3293 set_irqchip_out:
3294 kfree(chip);
3295 if (r)
3296 goto out;
1fe779f8
CO		 3297 break;
3298 }
e0f63cb9 3299 case KVM_GET_PIT: {
e0f63cb9 3300 r = -EFAULT;
f0d66275 3301 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3302 goto out;
3303 r = -ENXIO;
3304 if (!kvm->arch.vpit)
3305 goto out;
f0d66275 3306 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3307 if (r)
3308 goto out;
3309 r = -EFAULT;
f0d66275 3310 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3311 goto out;
3312 r = 0;
3313 break;
3314 }
3315 case KVM_SET_PIT: {
e0f63cb9 3316 r = -EFAULT;
f0d66275 3317 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3318 goto out;
3319 r = -ENXIO;
3320 if (!kvm->arch.vpit)
3321 goto out;
f0d66275 3322 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3323 if (r)
3324 goto out;
3325 r = 0;
3326 break;
3327 }
e9f42757
BK		 3328 case KVM_GET_PIT2: {
3329 r = -ENXIO;
3330 if (!kvm->arch.vpit)
3331 goto out;
3332 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3333 if (r)
3334 goto out;
3335 r = -EFAULT;
3336 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3337 goto out;
3338 r = 0;
3339 break;
3340 }
3341 case KVM_SET_PIT2: {
3342 r = -EFAULT;
3343 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3344 goto out;
3345 r = -ENXIO;
3346 if (!kvm->arch.vpit)
3347 goto out;
3348 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3349 if (r)
3350 goto out;
3351 r = 0;
3352 break;
3353 }
52d939a0
MT		 3354 case KVM_REINJECT_CONTROL: {
3355 struct kvm_reinject_control control;
3356 r = -EFAULT;
3357 if (copy_from_user(&control, argp, sizeof(control)))
3358 goto out;
3359 r = kvm_vm_ioctl_reinject(kvm, &control);
3360 if (r)
3361 goto out;
3362 r = 0;
3363 break;
3364 }
ffde22ac
ES		 3365 case KVM_XEN_HVM_CONFIG: {
3366 r = -EFAULT;
3367 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3368 sizeof(struct kvm_xen_hvm_config)))
3369 goto out;
3370 r = -EINVAL;
3371 if (kvm->arch.xen_hvm_config.flags)
3372 goto out;
3373 r = 0;
3374 break;
3375 }
afbcf7ab 3376 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3377 struct kvm_clock_data user_ns;
3378 u64 now_ns;
3379 s64 delta;
3380
3381 r = -EFAULT;
3382 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3383 goto out;
3384
3385 r = -EINVAL;
3386 if (user_ns.flags)
3387 goto out;
3388
3389 r = 0;
395c6b0a 3390 local_irq_disable();
759379dd 3391 now_ns = get_kernel_ns();
afbcf7ab 3392 delta = user_ns.clock - now_ns;
395c6b0a 3393 local_irq_enable();
afbcf7ab
GC		 3394 kvm->arch.kvmclock_offset = delta;
3395 break;
3396 }
3397 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3398 struct kvm_clock_data user_ns;
3399 u64 now_ns;
3400
395c6b0a 3401 local_irq_disable();
759379dd 3402 now_ns = get_kernel_ns();
afbcf7ab 3403 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3404 local_irq_enable();
afbcf7ab 3405 user_ns.flags = 0;
97e69aa6 3406 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3407
3408 r = -EFAULT;
3409 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3410 goto out;
3411 r = 0;
3412 break;
3413 }
3414
1fe779f8
CO		 3415 default:
3416 ;
3417 }
3418out:
3419 return r;
3420}
3421
a16b043c 3422static void kvm_init_msr_list(void)
043405e1
CO		 3423{
3424 u32 dummy[2];
3425 unsigned i, j;
3426
e3267cbb
GC		 3427 /* skip the first msrs in the list. KVM-specific */
3428 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3429 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3430 continue;
3431 if (j < i)
3432 msrs_to_save[j] = msrs_to_save[i];
3433 j++;
3434 }
3435 num_msrs_to_save = j;
3436}
3437
bda9020e
MT		 3438static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3439 const void *v)
bbd9b64e 3440{
70252a10
AK		 3441 int handled = 0;
3442 int n;
3443
3444 do {
3445 n = min(len, 8);
3446 if (!(vcpu->arch.apic &&
3447 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3448 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3449 break;
3450 handled += n;
3451 addr += n;
3452 len -= n;
3453 v += n;
3454 } while (len);
bbd9b64e 3455
70252a10 3456 return handled;
bbd9b64e
CO		 3457}
3458
bda9020e 3459static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3460{
70252a10
AK		 3461 int handled = 0;
3462 int n;
3463
3464 do {
3465 n = min(len, 8);
3466 if (!(vcpu->arch.apic &&
3467 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3468 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3469 break;
3470 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3471 handled += n;
3472 addr += n;
3473 len -= n;
3474 v += n;
3475 } while (len);
bbd9b64e 3476
70252a10 3477 return handled;
bbd9b64e
CO		 3478}
3479
2dafc6c2
GN		 3480static void kvm_set_segment(struct kvm_vcpu *vcpu,
3481 struct kvm_segment *var, int seg)
3482{
3483 kvm_x86_ops->set_segment(vcpu, var, seg);
3484}
3485
3486void kvm_get_segment(struct kvm_vcpu *vcpu,
3487 struct kvm_segment *var, int seg)
3488{
3489 kvm_x86_ops->get_segment(vcpu, var, seg);
3490}
3491
e459e322 3492gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3493{
3494 gpa_t t_gpa;
ab9ae313 3495 struct x86_exception exception;
02f59dc9
JR		 3496
3497 BUG_ON(!mmu_is_nested(vcpu));
3498
3499 /* NPT walks are always user-walks */
3500 access |= PFERR_USER_MASK;
ab9ae313 3501 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3502
3503 return t_gpa;
3504}
3505
ab9ae313
AK		 3506gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3507 struct x86_exception *exception)
1871c602
GN		 3508{
3509 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3510 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3511}
3512
ab9ae313
AK		 3513 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3514 struct x86_exception *exception)
1871c602
GN		 3515{
3516 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3517 access |= PFERR_FETCH_MASK;
ab9ae313 3518 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3519}
3520
ab9ae313
AK		 3521gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3522 struct x86_exception *exception)
1871c602
GN		 3523{
3524 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3525 access |= PFERR_WRITE_MASK;
ab9ae313 3526 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3527}
3528
3529/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3530gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3531 struct x86_exception *exception)
1871c602 3532{
ab9ae313 3533 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3534}
3535
3536static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3537 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3538 struct x86_exception *exception)
bbd9b64e
CO		 3539{
3540 void *data = val;
10589a46 3541 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3542
3543 while (bytes) {
14dfe855 3544 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3545 exception);
bbd9b64e 3546 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3547 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3548 int ret;
3549
bcc55cba 3550 if (gpa == UNMAPPED_GVA)
ab9ae313 3551 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3552 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3553 if (ret < 0) {
c3cd7ffa 3554 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3555 goto out;
3556 }
bbd9b64e 3557
77c2002e
IE		 3558 bytes -= toread;
3559 data += toread;
3560 addr += toread;
bbd9b64e 3561 }
10589a46 3562out:
10589a46 3563 return r;
bbd9b64e 3564}
77c2002e 3565
1871c602 3566/* used for instruction fetching */
0f65dd70
AK		 3567static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3568 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3569 struct x86_exception *exception)
1871c602 3570{
0f65dd70 3571 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3572 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3573
1871c602 3574 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3575 access | PFERR_FETCH_MASK,
3576 exception);
1871c602
GN		 3577}
3578
064aea77 3579int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3580 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3581 struct x86_exception *exception)
1871c602 3582{
0f65dd70 3583 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3584 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3585
1871c602 3586 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3587 exception);
1871c602 3588}
064aea77 3589EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3590
0f65dd70
AK		 3591static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3592 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3593 struct x86_exception *exception)
1871c602 3594{
0f65dd70 3595 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3596 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3597}
3598
6a4d7550 3599int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3600 gva_t addr, void *val,
2dafc6c2 3601 unsigned int bytes,
bcc55cba 3602 struct x86_exception *exception)
77c2002e 3603{
0f65dd70 3604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3605 void *data = val;
3606 int r = X86EMUL_CONTINUE;
3607
3608 while (bytes) {
14dfe855
JR		 3609 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3610 PFERR_WRITE_MASK,
ab9ae313 3611 exception);
77c2002e
IE		 3612 unsigned offset = addr & (PAGE_SIZE-1);
3613 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3614 int ret;
3615
bcc55cba 3616 if (gpa == UNMAPPED_GVA)
ab9ae313 3617 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3618 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3619 if (ret < 0) {
c3cd7ffa 3620 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3621 goto out;
3622 }
3623
3624 bytes -= towrite;
3625 data += towrite;
3626 addr += towrite;
3627 }
3628out:
3629 return r;
3630}
6a4d7550 3631EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3632
af7cc7d1
XG		 3633static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3634 gpa_t *gpa, struct x86_exception *exception,
3635 bool write)
3636{
3637 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3638
bebb106a
XG		 3639 if (vcpu_match_mmio_gva(vcpu, gva) &&
3640 check_write_user_access(vcpu, write, access,
3641 vcpu->arch.access)) {
3642 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3643 (gva & (PAGE_SIZE - 1));
4f022648 3644 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3645 return 1;
3646 }
3647
af7cc7d1
XG		 3648 if (write)
3649 access |= PFERR_WRITE_MASK;
3650
3651 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3652
3653 if (*gpa == UNMAPPED_GVA)
3654 return -1;
3655
3656 /* For APIC access vmexit */
3657 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3658 return 1;
3659
4f022648
XG		 3660 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3661 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3662 return 1;
4f022648 3663 }
bebb106a 3664
af7cc7d1
XG		 3665 return 0;
3666}
3667
3200f405 3668int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3669 const void *val, int bytes)
bbd9b64e
CO		 3670{
3671 int ret;
3672
3673 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3674 if (ret < 0)
bbd9b64e 3675 return 0;
f57f2ef5 3676 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3677 return 1;
3678}
3679
77d197b2
XG		 3680struct read_write_emulator_ops {
3681 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3682 int bytes);
3683 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3684 void *val, int bytes);
3685 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3686 int bytes, void *val);
3687 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3688 void *val, int bytes);
3689 bool write;
3690};
3691
3692static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3693{
3694 if (vcpu->mmio_read_completed) {
3695 memcpy(val, vcpu->mmio_data, bytes);
3696 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3697 vcpu->mmio_phys_addr, *(u64 *)val);
3698 vcpu->mmio_read_completed = 0;
3699 return 1;
3700 }
3701
3702 return 0;
3703}
3704
3705static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3706 void *val, int bytes)
3707{
3708 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3709}
3710
3711static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3712 void *val, int bytes)
3713{
3714 return emulator_write_phys(vcpu, gpa, val, bytes);
3715}
3716
3717static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3718{
3719 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3720 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3721}
3722
3723static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3724 void *val, int bytes)
3725{
3726 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3727 return X86EMUL_IO_NEEDED;
3728}
3729
3730static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3731 void *val, int bytes)
3732{
3733 memcpy(vcpu->mmio_data, val, bytes);
3734 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3735 return X86EMUL_CONTINUE;
3736}
3737
3738static struct read_write_emulator_ops read_emultor = {
3739 .read_write_prepare = read_prepare,
3740 .read_write_emulate = read_emulate,
3741 .read_write_mmio = vcpu_mmio_read,
3742 .read_write_exit_mmio = read_exit_mmio,
3743};
3744
3745static struct read_write_emulator_ops write_emultor = {
3746 .read_write_emulate = write_emulate,
3747 .read_write_mmio = write_mmio,
3748 .read_write_exit_mmio = write_exit_mmio,
3749 .write = true,
3750};
3751
22388a3c
XG		 3752static int emulator_read_write_onepage(unsigned long addr, void *val,
3753 unsigned int bytes,
3754 struct x86_exception *exception,
3755 struct kvm_vcpu *vcpu,
3756 struct read_write_emulator_ops *ops)
bbd9b64e 3757{
af7cc7d1
XG		 3758 gpa_t gpa;
3759 int handled, ret;
22388a3c
XG		 3760 bool write = ops->write;
3761
3762 if (ops->read_write_prepare &&
3763 ops->read_write_prepare(vcpu, val, bytes))
3764 return X86EMUL_CONTINUE;
10589a46 3765
22388a3c 3766 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3767
af7cc7d1 3768 if (ret < 0)
bbd9b64e 3769 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3770
3771 /* For APIC access vmexit */
af7cc7d1 3772 if (ret)
bbd9b64e
CO		 3773 goto mmio;
3774
22388a3c 3775 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3776 return X86EMUL_CONTINUE;
3777
3778mmio:
3779 /*
3780 * Is this MMIO handled locally?
3781 */
22388a3c 3782 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3783 if (handled == bytes)
bbd9b64e 3784 return X86EMUL_CONTINUE;
bbd9b64e 3785
70252a10
AK		 3786 gpa += handled;
3787 bytes -= handled;
3788 val += handled;
3789
bbd9b64e 3790 vcpu->mmio_needed = 1;
411c35b7
GN		 3791 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3792 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3793 vcpu->mmio_size = bytes;
3794 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3795 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3796 vcpu->mmio_index = 0;
bbd9b64e 3797
22388a3c 3798 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3799}
3800
22388a3c
XG		 3801int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3802 void *val, unsigned int bytes,
3803 struct x86_exception *exception,
3804 struct read_write_emulator_ops *ops)
bbd9b64e 3805{
0f65dd70
AK		 3806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3807
bbd9b64e
CO		 3808 /* Crossing a page boundary? */
3809 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3810 int rc, now;
3811
3812 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3813 rc = emulator_read_write_onepage(addr, val, now, exception,
3814 vcpu, ops);
3815
bbd9b64e
CO		 3816 if (rc != X86EMUL_CONTINUE)
3817 return rc;
3818 addr += now;
3819 val += now;
3820 bytes -= now;
3821 }
22388a3c
XG		 3822
3823 return emulator_read_write_onepage(addr, val, bytes, exception,
3824 vcpu, ops);
3825}
3826
3827static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3828 unsigned long addr,
3829 void *val,
3830 unsigned int bytes,
3831 struct x86_exception *exception)
3832{
3833 return emulator_read_write(ctxt, addr, val, bytes,
3834 exception, &read_emultor);
3835}
3836
3837int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3838 unsigned long addr,
3839 const void *val,
3840 unsigned int bytes,
3841 struct x86_exception *exception)
3842{
3843 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3844 exception, &write_emultor);
bbd9b64e 3845}
bbd9b64e 3846
daea3e73
AK		 3847#define CMPXCHG_TYPE(t, ptr, old, new) \
3848 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3849
3850#ifdef CONFIG_X86_64
3851# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3852#else
3853# define CMPXCHG64(ptr, old, new) \
9749a6c0 3854 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3855#endif
3856
0f65dd70
AK		 3857static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3858 unsigned long addr,
bbd9b64e
CO		 3859 const void *old,
3860 const void *new,
3861 unsigned int bytes,
0f65dd70 3862 struct x86_exception *exception)
bbd9b64e 3863{
0f65dd70 3864 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3865 gpa_t gpa;
3866 struct page *page;
3867 char *kaddr;
3868 bool exchanged;
2bacc55c 3869
daea3e73
AK		 3870 /* guests cmpxchg8b have to be emulated atomically */
3871 if (bytes > 8 || (bytes & (bytes - 1)))
3872 goto emul_write;
10589a46 3873
daea3e73 3874 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3875
daea3e73
AK		 3876 if (gpa == UNMAPPED_GVA ||
3877 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3878 goto emul_write;
2bacc55c 3879
daea3e73
AK		 3880 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3881 goto emul_write;
72dc67a6 3882
daea3e73 3883 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3884 if (is_error_page(page)) {
3885 kvm_release_page_clean(page);
3886 goto emul_write;
3887 }
72dc67a6 3888
daea3e73
AK		 3889 kaddr = kmap_atomic(page, KM_USER0);
3890 kaddr += offset_in_page(gpa);
3891 switch (bytes) {
3892 case 1:
3893 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3894 break;
3895 case 2:
3896 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3897 break;
3898 case 4:
3899 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3900 break;
3901 case 8:
3902 exchanged = CMPXCHG64(kaddr, old, new);
3903 break;
3904 default:
3905 BUG();
2bacc55c 3906 }
daea3e73
AK		 3907 kunmap_atomic(kaddr, KM_USER0);
3908 kvm_release_page_dirty(page);
3909
3910 if (!exchanged)
3911 return X86EMUL_CMPXCHG_FAILED;
3912
f57f2ef5 3913 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3914
3915 return X86EMUL_CONTINUE;
4a5f48f6 3916
3200f405 3917emul_write:
daea3e73 3918 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3919
0f65dd70 3920 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3921}
3922
cf8f70bf
GN		 3923static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3924{
3925 /* TODO: String I/O for in kernel device */
3926 int r;
3927
3928 if (vcpu->arch.pio.in)
3929 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3930 vcpu->arch.pio.size, pd);
3931 else
3932 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3933 vcpu->arch.pio.port, vcpu->arch.pio.size,
3934 pd);
3935 return r;
3936}
3937
6f6fbe98
XG		 3938static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3939 unsigned short port, void *val,
3940 unsigned int count, bool in)
cf8f70bf 3941{
6f6fbe98 3942 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3943
3944 vcpu->arch.pio.port = port;
6f6fbe98 3945 vcpu->arch.pio.in = in;
7972995b 3946 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3947 vcpu->arch.pio.size = size;
3948
3949 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3950 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3951 return 1;
3952 }
3953
3954 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3955 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3956 vcpu->run->io.size = size;
3957 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3958 vcpu->run->io.count = count;
3959 vcpu->run->io.port = port;
3960
3961 return 0;
3962}
3963
6f6fbe98
XG		 3964static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3965 int size, unsigned short port, void *val,
3966 unsigned int count)
cf8f70bf 3967{
ca1d4a9e 3968 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 3969 int ret;
ca1d4a9e 3970
6f6fbe98
XG		 3971 if (vcpu->arch.pio.count)
3972 goto data_avail;
cf8f70bf 3973
6f6fbe98
XG		 3974 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
3975 if (ret) {
3976data_avail:
3977 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3978 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3979 return 1;
3980 }
3981
cf8f70bf
GN		 3982 return 0;
3983}
3984
6f6fbe98
XG		 3985static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
3986 int size, unsigned short port,
3987 const void *val, unsigned int count)
3988{
3989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3990
3991 memcpy(vcpu->arch.pio_data, val, size * count);
3992 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
3993}
3994
bbd9b64e
CO		 3995static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3996{
3997 return kvm_x86_ops->get_segment_base(vcpu, seg);
3998}
3999
3cb16fe7 4000static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4001{
3cb16fe7 4002 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4003}
4004
f5f48ee1
SY		 4005int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4006{
4007 if (!need_emulate_wbinvd(vcpu))
4008 return X86EMUL_CONTINUE;
4009
4010 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4011 int cpu = get_cpu();
4012
4013 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4014 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4015 wbinvd_ipi, NULL, 1);
2eec7343 4016 put_cpu();
f5f48ee1 4017 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4018 } else
4019 wbinvd();
f5f48ee1
SY		 4020 return X86EMUL_CONTINUE;
4021}
4022EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4023
bcaf5cc5
AK		 4024static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4025{
4026 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4027}
4028
717746e3 4029int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4030{
717746e3 4031 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4032}
4033
717746e3 4034int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4035{
338dbc97 4036
717746e3 4037 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4038}
4039
52a46617 4040static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4041{
52a46617 4042 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4043}
4044
717746e3 4045static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4046{
717746e3 4047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4048 unsigned long value;
4049
4050 switch (cr) {
4051 case 0:
4052 value = kvm_read_cr0(vcpu);
4053 break;
4054 case 2:
4055 value = vcpu->arch.cr2;
4056 break;
4057 case 3:
9f8fe504 4058 value = kvm_read_cr3(vcpu);
52a46617
GN		 4059 break;
4060 case 4:
4061 value = kvm_read_cr4(vcpu);
4062 break;
4063 case 8:
4064 value = kvm_get_cr8(vcpu);
4065 break;
4066 default:
4067 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4068 return 0;
4069 }
4070
4071 return value;
4072}
4073
717746e3 4074static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4075{
717746e3 4076 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4077 int res = 0;
4078
52a46617
GN		 4079 switch (cr) {
4080 case 0:
49a9b07e 4081 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4082 break;
4083 case 2:
4084 vcpu->arch.cr2 = val;
4085 break;
4086 case 3:
2390218b 4087 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4088 break;
4089 case 4:
a83b29c6 4090 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4091 break;
4092 case 8:
eea1cff9 4093 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4094 break;
4095 default:
4096 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4097 res = -1;
52a46617 4098 }
0f12244f
GN		 4099
4100 return res;
52a46617
GN		 4101}
4102
717746e3 4103static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4104{
717746e3 4105 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4106}
4107
4bff1e86 4108static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4109{
4bff1e86 4110 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4111}
4112
4bff1e86 4113static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4114{
4bff1e86 4115 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4116}
4117
1ac9d0cf
AK		 4118static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4119{
4120 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4121}
4122
4123static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4124{
4125 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4126}
4127
4bff1e86
AK		 4128static unsigned long emulator_get_cached_segment_base(
4129 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4130{
4bff1e86 4131 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4132}
4133
1aa36616
AK		 4134static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4135 struct desc_struct *desc, u32 *base3,
4136 int seg)
2dafc6c2
GN		 4137{
4138 struct kvm_segment var;
4139
4bff1e86 4140 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4141 *selector = var.selector;
2dafc6c2
GN		 4142
4143 if (var.unusable)
4144 return false;
4145
4146 if (var.g)
4147 var.limit >>= 12;
4148 set_desc_limit(desc, var.limit);
4149 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4150#ifdef CONFIG_X86_64
4151 if (base3)
4152 *base3 = var.base >> 32;
4153#endif
2dafc6c2
GN		 4154 desc->type = var.type;
4155 desc->s = var.s;
4156 desc->dpl = var.dpl;
4157 desc->p = var.present;
4158 desc->avl = var.avl;
4159 desc->l = var.l;
4160 desc->d = var.db;
4161 desc->g = var.g;
4162
4163 return true;
4164}
4165
1aa36616
AK		 4166static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4167 struct desc_struct *desc, u32 base3,
4168 int seg)
2dafc6c2 4169{
4bff1e86 4170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4171 struct kvm_segment var;
4172
1aa36616 4173 var.selector = selector;
2dafc6c2 4174 var.base = get_desc_base(desc);
5601d05b
GN		 4175#ifdef CONFIG_X86_64
4176 var.base |= ((u64)base3) << 32;
4177#endif
2dafc6c2
GN		 4178 var.limit = get_desc_limit(desc);
4179 if (desc->g)
4180 var.limit = (var.limit << 12) | 0xfff;
4181 var.type = desc->type;
4182 var.present = desc->p;
4183 var.dpl = desc->dpl;
4184 var.db = desc->d;
4185 var.s = desc->s;
4186 var.l = desc->l;
4187 var.g = desc->g;
4188 var.avl = desc->avl;
4189 var.present = desc->p;
4190 var.unusable = !var.present;
4191 var.padding = 0;
4192
4193 kvm_set_segment(vcpu, &var, seg);
4194 return;
4195}
4196
717746e3
AK		 4197static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4198 u32 msr_index, u64 *pdata)
4199{
4200 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4201}
4202
4203static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4204 u32 msr_index, u64 data)
4205{
4206 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4207}
4208
222d21aa
AK		 4209static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4210 u32 pmc, u64 *pdata)
4211{
4212 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4213}
4214
6c3287f7
AK		 4215static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4216{
4217 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4218}
4219
5037f6f3
AK		 4220static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4221{
4222 preempt_disable();
5197b808 4223 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4224 /*
4225 * CR0.TS may reference the host fpu state, not the guest fpu state,
4226 * so it may be clear at this point.
4227 */
4228 clts();
4229}
4230
4231static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4232{
4233 preempt_enable();
4234}
4235
2953538e 4236static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4237 struct x86_instruction_info *info,
c4f035c6
AK		 4238 enum x86_intercept_stage stage)
4239{
2953538e 4240 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4241}
4242
bdb42f5a
SB		 4243static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4244 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4245{
4246 struct kvm_cpuid_entry2 *cpuid = NULL;
4247
4248 if (eax && ecx)
4249 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4250 *eax, *ecx);
4251
4252 if (cpuid) {
4253 *eax = cpuid->eax;
4254 *ecx = cpuid->ecx;
4255 if (ebx)
4256 *ebx = cpuid->ebx;
4257 if (edx)
4258 *edx = cpuid->edx;
4259 return true;
4260 }
4261
4262 return false;
4263}
4264
14af3f3c 4265static struct x86_emulate_ops emulate_ops = {
1871c602 4266 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4267 .write_std = kvm_write_guest_virt_system,
1871c602 4268 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4269 .read_emulated = emulator_read_emulated,
4270 .write_emulated = emulator_write_emulated,
4271 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4272 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4273 .pio_in_emulated = emulator_pio_in_emulated,
4274 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4275 .get_segment = emulator_get_segment,
4276 .set_segment = emulator_set_segment,
5951c442 4277 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4278 .get_gdt = emulator_get_gdt,
160ce1f1 4279 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4280 .set_gdt = emulator_set_gdt,
4281 .set_idt = emulator_set_idt,
52a46617
GN		 4282 .get_cr = emulator_get_cr,
4283 .set_cr = emulator_set_cr,
9c537244 4284 .cpl = emulator_get_cpl,
35aa5375
GN		 4285 .get_dr = emulator_get_dr,
4286 .set_dr = emulator_set_dr,
717746e3
AK		 4287 .set_msr = emulator_set_msr,
4288 .get_msr = emulator_get_msr,
222d21aa 4289 .read_pmc = emulator_read_pmc,
6c3287f7 4290 .halt = emulator_halt,
bcaf5cc5 4291 .wbinvd = emulator_wbinvd,
d6aa1000 4292 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4293 .get_fpu = emulator_get_fpu,
4294 .put_fpu = emulator_put_fpu,
c4f035c6 4295 .intercept = emulator_intercept,
bdb42f5a 4296 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4297};
4298
5fdbf976
MT		 4299static void cache_all_regs(struct kvm_vcpu *vcpu)
4300{
4301 kvm_register_read(vcpu, VCPU_REGS_RAX);
4302 kvm_register_read(vcpu, VCPU_REGS_RSP);
4303 kvm_register_read(vcpu, VCPU_REGS_RIP);
4304 vcpu->arch.regs_dirty = ~0;
4305}
4306
95cb2295
GN		 4307static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4308{
4309 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4310 /*
4311 * an sti; sti; sequence only disable interrupts for the first
4312 * instruction. So, if the last instruction, be it emulated or
4313 * not, left the system with the INT_STI flag enabled, it
4314 * means that the last instruction is an sti. We should not
4315 * leave the flag on in this case. The same goes for mov ss
4316 */
4317 if (!(int_shadow & mask))
4318 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4319}
4320
54b8486f
GN		 4321static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4322{
4323 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4324 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4325 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4326 else if (ctxt->exception.error_code_valid)
4327 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4328 ctxt->exception.error_code);
54b8486f 4329 else
da9cb575 4330 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4331}
4332
9dac77fa 4333static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4334 const unsigned long *regs)
4335{
9dac77fa
AK		 4336 memset(&ctxt->twobyte, 0,
4337 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4338 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4339
9dac77fa
AK		 4340 ctxt->fetch.start = 0;
4341 ctxt->fetch.end = 0;
4342 ctxt->io_read.pos = 0;
4343 ctxt->io_read.end = 0;
4344 ctxt->mem_read.pos = 0;
4345 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4346}
4347
8ec4722d
MG		 4348static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4349{
adf52235 4350 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4351 int cs_db, cs_l;
4352
2aab2c5b
GN		 4353 /*
4354 * TODO: fix emulate.c to use guest_read/write_register
4355 * instead of direct ->regs accesses, can save hundred cycles
4356 * on Intel for instructions that don't read/change RSP, for
4357 * for example.
4358 */
8ec4722d
MG		 4359 cache_all_regs(vcpu);
4360
4361 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4362
adf52235
TY		 4363 ctxt->eflags = kvm_get_rflags(vcpu);
4364 ctxt->eip = kvm_rip_read(vcpu);
4365 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4366 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4367 cs_l ? X86EMUL_MODE_PROT64 :
4368 cs_db ? X86EMUL_MODE_PROT32 :
4369 X86EMUL_MODE_PROT16;
4370 ctxt->guest_mode = is_guest_mode(vcpu);
4371
9dac77fa 4372 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4373 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4374}
4375
71f9833b 4376int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4377{
9d74191a 4378 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4379 int ret;
4380
4381 init_emulate_ctxt(vcpu);
4382
9dac77fa
AK		 4383 ctxt->op_bytes = 2;
4384 ctxt->ad_bytes = 2;
4385 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4386 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4387
4388 if (ret != X86EMUL_CONTINUE)
4389 return EMULATE_FAIL;
4390
9dac77fa
AK		 4391 ctxt->eip = ctxt->_eip;
4392 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4393 kvm_rip_write(vcpu, ctxt->eip);
4394 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4395
4396 if (irq == NMI_VECTOR)
7460fb4a 4397 vcpu->arch.nmi_pending = 0;
63995653
MG		 4398 else
4399 vcpu->arch.interrupt.pending = false;
4400
4401 return EMULATE_DONE;
4402}
4403EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4404
6d77dbfc
GN		 4405static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4406{
fc3a9157
JR		 4407 int r = EMULATE_DONE;
4408
6d77dbfc
GN		 4409 ++vcpu->stat.insn_emulation_fail;
4410 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4411 if (!is_guest_mode(vcpu)) {
4412 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4413 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4414 vcpu->run->internal.ndata = 0;
4415 r = EMULATE_FAIL;
4416 }
6d77dbfc 4417 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4418
4419 return r;
6d77dbfc
GN		 4420}
4421
a6f177ef
GN		 4422static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4423{
4424 gpa_t gpa;
4425
68be0803
GN		 4426 if (tdp_enabled)
4427 return false;
4428
a6f177ef
GN		 4429 /*
4430 * if emulation was due to access to shadowed page table
4431 * and it failed try to unshadow page and re-entetr the
4432 * guest to let CPU execute the instruction.
4433 */
4434 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4435 return true;
4436
4437 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4438
4439 if (gpa == UNMAPPED_GVA)
4440 return true; /* let cpu generate fault */
4441
4442 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4443 return true;
4444
4445 return false;
4446}
4447
1cb3f3ae
XG		 4448static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4449 unsigned long cr2, int emulation_type)
4450{
4451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4452 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4453
4454 last_retry_eip = vcpu->arch.last_retry_eip;
4455 last_retry_addr = vcpu->arch.last_retry_addr;
4456
4457 /*
4458 * If the emulation is caused by #PF and it is non-page_table
4459 * writing instruction, it means the VM-EXIT is caused by shadow
4460 * page protected, we can zap the shadow page and retry this
4461 * instruction directly.
4462 *
4463 * Note: if the guest uses a non-page-table modifying instruction
4464 * on the PDE that points to the instruction, then we will unmap
4465 * the instruction and go to an infinite loop. So, we cache the
4466 * last retried eip and the last fault address, if we meet the eip
4467 * and the address again, we can break out of the potential infinite
4468 * loop.
4469 */
4470 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4471
4472 if (!(emulation_type & EMULTYPE_RETRY))
4473 return false;
4474
4475 if (x86_page_table_writing_insn(ctxt))
4476 return false;
4477
4478 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4479 return false;
4480
4481 vcpu->arch.last_retry_eip = ctxt->eip;
4482 vcpu->arch.last_retry_addr = cr2;
4483
4484 if (!vcpu->arch.mmu.direct_map)
4485 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4486
4487 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4488
4489 return true;
4490}
4491
51d8b661
AP		 4492int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4493 unsigned long cr2,
dc25e89e
AP		 4494 int emulation_type,
4495 void *insn,
4496 int insn_len)
bbd9b64e 4497{
95cb2295 4498 int r;
9d74191a 4499 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4500 bool writeback = true;
bbd9b64e 4501
26eef70c 4502 kvm_clear_exception_queue(vcpu);
8d7d8102 4503
571008da 4504 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4505 init_emulate_ctxt(vcpu);
9d74191a
TY		 4506 ctxt->interruptibility = 0;
4507 ctxt->have_exception = false;
4508 ctxt->perm_ok = false;
bbd9b64e 4509
9d74191a 4510 ctxt->only_vendor_specific_insn
4005996e
AK		 4511 = emulation_type & EMULTYPE_TRAP_UD;
4512
9d74191a 4513 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4514
e46479f8 4515 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4516 ++vcpu->stat.insn_emulation;
1d2887e2 4517 if (r != EMULATION_OK) {
4005996e
AK		 4518 if (emulation_type & EMULTYPE_TRAP_UD)
4519 return EMULATE_FAIL;
a6f177ef 4520 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4521 return EMULATE_DONE;
6d77dbfc
GN		 4522 if (emulation_type & EMULTYPE_SKIP)
4523 return EMULATE_FAIL;
4524 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4525 }
4526 }
4527
ba8afb6b 4528 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4529 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4530 return EMULATE_DONE;
4531 }
4532
1cb3f3ae
XG		 4533 if (retry_instruction(ctxt, cr2, emulation_type))
4534 return EMULATE_DONE;
4535
7ae441ea 4536 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4537 changes registers values during IO operation */
7ae441ea
GN		 4538 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4539 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4540 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4541 }
4d2179e1 4542
5cd21917 4543restart:
9d74191a 4544 r = x86_emulate_insn(ctxt);
bbd9b64e 4545
775fde86
JR		 4546 if (r == EMULATION_INTERCEPTED)
4547 return EMULATE_DONE;
4548
d2ddd1c4 4549 if (r == EMULATION_FAILED) {
a6f177ef 4550 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4551 return EMULATE_DONE;
4552
6d77dbfc 4553 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4554 }
4555
9d74191a 4556 if (ctxt->have_exception) {
54b8486f 4557 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4558 r = EMULATE_DONE;
4559 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4560 if (!vcpu->arch.pio.in)
4561 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4562 else
4563 writeback = false;
e85d28f8 4564 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4565 } else if (vcpu->mmio_needed) {
4566 if (!vcpu->mmio_is_write)
4567 writeback = false;
e85d28f8 4568 r = EMULATE_DO_MMIO;
7ae441ea 4569 } else if (r == EMULATION_RESTART)
5cd21917 4570 goto restart;
d2ddd1c4
GN		 4571 else
4572 r = EMULATE_DONE;
f850e2e6 4573
7ae441ea 4574 if (writeback) {
9d74191a
TY		 4575 toggle_interruptibility(vcpu, ctxt->interruptibility);
4576 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4577 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4578 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4579 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4580 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4581 } else
4582 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4583
4584 return r;
de7d789a 4585}
51d8b661 4586EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4587
cf8f70bf 4588int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4589{
cf8f70bf 4590 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4591 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4592 size, port, &val, 1);
cf8f70bf 4593 /* do not return to emulator after return from userspace */
7972995b 4594 vcpu->arch.pio.count = 0;
de7d789a
CO		 4595 return ret;
4596}
cf8f70bf 4597EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4598
8cfdc000
ZA		 4599static void tsc_bad(void *info)
4600{
0a3aee0d 4601 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4602}
4603
4604static void tsc_khz_changed(void *data)
c8076604 4605{
8cfdc000
ZA		 4606 struct cpufreq_freqs *freq = data;
4607 unsigned long khz = 0;
4608
4609 if (data)
4610 khz = freq->new;
4611 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4612 khz = cpufreq_quick_get(raw_smp_processor_id());
4613 if (!khz)
4614 khz = tsc_khz;
0a3aee0d 4615 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4616}
4617
c8076604
GH		 4618static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4619 void *data)
4620{
4621 struct cpufreq_freqs *freq = data;
4622 struct kvm *kvm;
4623 struct kvm_vcpu *vcpu;
4624 int i, send_ipi = 0;
4625
8cfdc000
ZA		 4626 /*
4627 * We allow guests to temporarily run on slowing clocks,
4628 * provided we notify them after, or to run on accelerating
4629 * clocks, provided we notify them before. Thus time never
4630 * goes backwards.
4631 *
4632 * However, we have a problem. We can't atomically update
4633 * the frequency of a given CPU from this function; it is
4634 * merely a notifier, which can be called from any CPU.
4635 * Changing the TSC frequency at arbitrary points in time
4636 * requires a recomputation of local variables related to
4637 * the TSC for each VCPU. We must flag these local variables
4638 * to be updated and be sure the update takes place with the
4639 * new frequency before any guests proceed.
4640 *
4641 * Unfortunately, the combination of hotplug CPU and frequency
4642 * change creates an intractable locking scenario; the order
4643 * of when these callouts happen is undefined with respect to
4644 * CPU hotplug, and they can race with each other. As such,
4645 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4646 * undefined; you can actually have a CPU frequency change take
4647 * place in between the computation of X and the setting of the
4648 * variable. To protect against this problem, all updates of
4649 * the per_cpu tsc_khz variable are done in an interrupt
4650 * protected IPI, and all callers wishing to update the value
4651 * must wait for a synchronous IPI to complete (which is trivial
4652 * if the caller is on the CPU already). This establishes the
4653 * necessary total order on variable updates.
4654 *
4655 * Note that because a guest time update may take place
4656 * anytime after the setting of the VCPU's request bit, the
4657 * correct TSC value must be set before the request. However,
4658 * to ensure the update actually makes it to any guest which
4659 * starts running in hardware virtualization between the set
4660 * and the acquisition of the spinlock, we must also ping the
4661 * CPU after setting the request bit.
4662 *
4663 */
4664
c8076604
GH		 4665 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4666 return 0;
4667 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4668 return 0;
8cfdc000
ZA		 4669
4670 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4671
e935b837 4672 raw_spin_lock(&kvm_lock);
c8076604 4673 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4674 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4675 if (vcpu->cpu != freq->cpu)
4676 continue;
c285545f 4677 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4678 if (vcpu->cpu != smp_processor_id())
8cfdc000 4679 send_ipi = 1;
c8076604
GH		 4680 }
4681 }
e935b837 4682 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4683
4684 if (freq->old < freq->new && send_ipi) {
4685 /*
4686 * We upscale the frequency. Must make the guest
4687 * doesn't see old kvmclock values while running with
4688 * the new frequency, otherwise we risk the guest sees
4689 * time go backwards.
4690 *
4691 * In case we update the frequency for another cpu
4692 * (which might be in guest context) send an interrupt
4693 * to kick the cpu out of guest context. Next time
4694 * guest context is entered kvmclock will be updated,
4695 * so the guest will not see stale values.
4696 */
8cfdc000 4697 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4698 }
4699 return 0;
4700}
4701
4702static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4703 .notifier_call = kvmclock_cpufreq_notifier
4704};
4705
4706static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4707 unsigned long action, void *hcpu)
4708{
4709 unsigned int cpu = (unsigned long)hcpu;
4710
4711 switch (action) {
4712 case CPU_ONLINE:
4713 case CPU_DOWN_FAILED:
4714 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4715 break;
4716 case CPU_DOWN_PREPARE:
4717 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4718 break;
4719 }
4720 return NOTIFY_OK;
4721}
4722
4723static struct notifier_block kvmclock_cpu_notifier_block = {
4724 .notifier_call = kvmclock_cpu_notifier,
4725 .priority = -INT_MAX
c8076604
GH		 4726};
4727
b820cc0c
ZA		 4728static void kvm_timer_init(void)
4729{
4730 int cpu;
4731
c285545f 4732 max_tsc_khz = tsc_khz;
8cfdc000 4733 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4734 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4735#ifdef CONFIG_CPU_FREQ
4736 struct cpufreq_policy policy;
4737 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4738 cpu = get_cpu();
4739 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4740 if (policy.cpuinfo.max_freq)
4741 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4742 put_cpu();
c285545f 4743#endif
b820cc0c
ZA		 4744 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4745 CPUFREQ_TRANSITION_NOTIFIER);
4746 }
c285545f 4747 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4748 for_each_online_cpu(cpu)
4749 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4750}
4751
ff9d07a0
ZY		 4752static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4753
f5132b01 4754int kvm_is_in_guest(void)
ff9d07a0 4755{
086c9855 4756 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4757}
4758
4759static int kvm_is_user_mode(void)
4760{
4761 int user_mode = 3;
dcf46b94 4762
086c9855
AS		 4763 if (__this_cpu_read(current_vcpu))
4764 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4765
ff9d07a0
ZY		 4766 return user_mode != 0;
4767}
4768
4769static unsigned long kvm_get_guest_ip(void)
4770{
4771 unsigned long ip = 0;
dcf46b94 4772
086c9855
AS		 4773 if (__this_cpu_read(current_vcpu))
4774 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4775
ff9d07a0
ZY		 4776 return ip;
4777}
4778
4779static struct perf_guest_info_callbacks kvm_guest_cbs = {
4780 .is_in_guest = kvm_is_in_guest,
4781 .is_user_mode = kvm_is_user_mode,
4782 .get_guest_ip = kvm_get_guest_ip,
4783};
4784
4785void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4786{
086c9855 4787 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4788}
4789EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4790
4791void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4792{
086c9855 4793 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4794}
4795EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4796
ce88decf
XG		 4797static void kvm_set_mmio_spte_mask(void)
4798{
4799 u64 mask;
4800 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4801
4802 /*
4803 * Set the reserved bits and the present bit of an paging-structure
4804 * entry to generate page fault with PFER.RSV = 1.
4805 */
4806 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4807 mask |= 1ull;
4808
4809#ifdef CONFIG_X86_64
4810 /*
4811 * If reserved bit is not supported, clear the present bit to disable
4812 * mmio page fault.
4813 */
4814 if (maxphyaddr == 52)
4815 mask &= ~1ull;
4816#endif
4817
4818 kvm_mmu_set_mmio_spte_mask(mask);
4819}
4820
f8c16bba 4821int kvm_arch_init(void *opaque)
043405e1 4822{
b820cc0c 4823 int r;
f8c16bba
ZX		 4824 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4825
f8c16bba
ZX		 4826 if (kvm_x86_ops) {
4827 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4828 r = -EEXIST;
4829 goto out;
f8c16bba
ZX		 4830 }
4831
4832 if (!ops->cpu_has_kvm_support()) {
4833 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4834 r = -EOPNOTSUPP;
4835 goto out;
f8c16bba
ZX		 4836 }
4837 if (ops->disabled_by_bios()) {
4838 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4839 r = -EOPNOTSUPP;
4840 goto out;
f8c16bba
ZX		 4841 }
4842
97db56ce
AK		 4843 r = kvm_mmu_module_init();
4844 if (r)
4845 goto out;
4846
ce88decf 4847 kvm_set_mmio_spte_mask();
97db56ce
AK		 4848 kvm_init_msr_list();
4849
f8c16bba 4850 kvm_x86_ops = ops;
7b52345e 4851 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4852 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4853
b820cc0c 4854 kvm_timer_init();
c8076604 4855
ff9d07a0
ZY		 4856 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4857
2acf923e
DC		 4858 if (cpu_has_xsave)
4859 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4860
f8c16bba 4861 return 0;
56c6d28a
ZX		 4862
4863out:
56c6d28a 4864 return r;
043405e1 4865}
8776e519 4866
f8c16bba
ZX		 4867void kvm_arch_exit(void)
4868{
ff9d07a0
ZY		 4869 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4870
888d256e
JK		 4871 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4872 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4873 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4874 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4875 kvm_x86_ops = NULL;
56c6d28a
ZX		 4876 kvm_mmu_module_exit();
4877}
f8c16bba 4878
8776e519
HB		 4879int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4880{
4881 ++vcpu->stat.halt_exits;
4882 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4883 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4884 return 1;
4885 } else {
4886 vcpu->run->exit_reason = KVM_EXIT_HLT;
4887 return 0;
4888 }
4889}
4890EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4891
55cd8e5a
GN		 4892int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4893{
4894 u64 param, ingpa, outgpa, ret;
4895 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4896 bool fast, longmode;
4897 int cs_db, cs_l;
4898
4899 /*
4900 * hypercall generates UD from non zero cpl and real mode
4901 * per HYPER-V spec
4902 */
3eeb3288 4903 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4904 kvm_queue_exception(vcpu, UD_VECTOR);
4905 return 0;
4906 }
4907
4908 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4909 longmode = is_long_mode(vcpu) && cs_l == 1;
4910
4911 if (!longmode) {
ccd46936
GN		 4912 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4913 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4914 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4915 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4916 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4917 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4918 }
4919#ifdef CONFIG_X86_64
4920 else {
4921 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4922 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4923 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4924 }
4925#endif
4926
4927 code = param & 0xffff;
4928 fast = (param >> 16) & 0x1;
4929 rep_cnt = (param >> 32) & 0xfff;
4930 rep_idx = (param >> 48) & 0xfff;
4931
4932 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4933
c25bc163
GN		 4934 switch (code) {
4935 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4936 kvm_vcpu_on_spin(vcpu);
4937 break;
4938 default:
4939 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4940 break;
4941 }
55cd8e5a
GN		 4942
4943 ret = res | (((u64)rep_done & 0xfff) << 32);
4944 if (longmode) {
4945 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4946 } else {
4947 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4948 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4949 }
4950
4951 return 1;
4952}
4953
8776e519
HB		 4954int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4955{
4956 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4957 int r = 1;
8776e519 4958
55cd8e5a
GN		 4959 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4960 return kvm_hv_hypercall(vcpu);
4961
5fdbf976
MT		 4962 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4963 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4964 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4965 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4966 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4967
229456fc 4968 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4969
8776e519
HB		 4970 if (!is_long_mode(vcpu)) {
4971 nr &= 0xFFFFFFFF;
4972 a0 &= 0xFFFFFFFF;
4973 a1 &= 0xFFFFFFFF;
4974 a2 &= 0xFFFFFFFF;
4975 a3 &= 0xFFFFFFFF;
4976 }
4977
07708c4a
JK		 4978 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4979 ret = -KVM_EPERM;
4980 goto out;
4981 }
4982
8776e519 4983 switch (nr) {
b93463aa
AK		 4984 case KVM_HC_VAPIC_POLL_IRQ:
4985 ret = 0;
4986 break;
8776e519
HB		 4987 default:
4988 ret = -KVM_ENOSYS;
4989 break;
4990 }
07708c4a 4991out:
5fdbf976 4992 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4993 ++vcpu->stat.hypercalls;
2f333bcb 4994 return r;
8776e519
HB		 4995}
4996EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4997
d6aa1000 4998int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 4999{
d6aa1000 5000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5001 char instruction[3];
5fdbf976 5002 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5003
8776e519
HB		 5004 /*
5005 * Blow out the MMU to ensure that no other VCPU has an active mapping
5006 * to ensure that the updated hypercall appears atomically across all
5007 * VCPUs.
5008 */
5009 kvm_mmu_zap_all(vcpu->kvm);
5010
8776e519 5011 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5012
9d74191a 5013 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5014}
5015
b6c7a5dc
HB		 5016/*
5017 * Check if userspace requested an interrupt window, and that the
5018 * interrupt window is open.
5019 *
5020 * No need to exit to userspace if we already have an interrupt queued.
5021 */
851ba692 5022static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5023{
8061823a 5024 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5025 vcpu->run->request_interrupt_window &&
5df56646 5026 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5027}
5028
851ba692 5029static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5030{
851ba692
AK		 5031 struct kvm_run *kvm_run = vcpu->run;
5032
91586a3b 5033 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5034 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5035 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5036 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5037 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5038 else
b6c7a5dc 5039 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5040 kvm_arch_interrupt_allowed(vcpu) &&
5041 !kvm_cpu_has_interrupt(vcpu) &&
5042 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5043}
5044
b93463aa
AK		 5045static void vapic_enter(struct kvm_vcpu *vcpu)
5046{
5047 struct kvm_lapic *apic = vcpu->arch.apic;
5048 struct page *page;
5049
5050 if (!apic || !apic->vapic_addr)
5051 return;
5052
5053 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5054
5055 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5056}
5057
5058static void vapic_exit(struct kvm_vcpu *vcpu)
5059{
5060 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5061 int idx;
b93463aa
AK		 5062
5063 if (!apic || !apic->vapic_addr)
5064 return;
5065
f656ce01 5066 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5067 kvm_release_page_dirty(apic->vapic_page);
5068 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5069 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5070}
5071
95ba8273
GN		 5072static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5073{
5074 int max_irr, tpr;
5075
5076 if (!kvm_x86_ops->update_cr8_intercept)
5077 return;
5078
88c808fd
AK		 5079 if (!vcpu->arch.apic)
5080 return;
5081
8db3baa2
GN		 5082 if (!vcpu->arch.apic->vapic_addr)
5083 max_irr = kvm_lapic_find_highest_irr(vcpu);
5084 else
5085 max_irr = -1;
95ba8273
GN		 5086
5087 if (max_irr != -1)
5088 max_irr >>= 4;
5089
5090 tpr = kvm_lapic_get_cr8(vcpu);
5091
5092 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5093}
5094
851ba692 5095static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5096{
5097 /* try to reinject previous events if any */
b59bb7bd 5098 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5099 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5100 vcpu->arch.exception.has_error_code,
5101 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5102 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5103 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5104 vcpu->arch.exception.error_code,
5105 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5106 return;
5107 }
5108
95ba8273
GN		 5109 if (vcpu->arch.nmi_injected) {
5110 kvm_x86_ops->set_nmi(vcpu);
5111 return;
5112 }
5113
5114 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5115 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5116 return;
5117 }
5118
5119 /* try to inject new event if pending */
5120 if (vcpu->arch.nmi_pending) {
5121 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5122 --vcpu->arch.nmi_pending;
95ba8273
GN		 5123 vcpu->arch.nmi_injected = true;
5124 kvm_x86_ops->set_nmi(vcpu);
5125 }
5126 } else if (kvm_cpu_has_interrupt(vcpu)) {
5127 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5128 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5129 false);
5130 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5131 }
5132 }
5133}
5134
2acf923e
DC		 5135static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5136{
5137 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5138 !vcpu->guest_xcr0_loaded) {
5139 /* kvm_set_xcr() also depends on this */
5140 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5141 vcpu->guest_xcr0_loaded = 1;
5142 }
5143}
5144
5145static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5146{
5147 if (vcpu->guest_xcr0_loaded) {
5148 if (vcpu->arch.xcr0 != host_xcr0)
5149 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5150 vcpu->guest_xcr0_loaded = 0;
5151 }
5152}
5153
7460fb4a
AK		 5154static void process_nmi(struct kvm_vcpu *vcpu)
5155{
5156 unsigned limit = 2;
5157
5158 /*
5159 * x86 is limited to one NMI running, and one NMI pending after it.
5160 * If an NMI is already in progress, limit further NMIs to just one.
5161 * Otherwise, allow two (and we'll inject the first one immediately).
5162 */
5163 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5164 limit = 1;
5165
5166 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5167 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5168 kvm_make_request(KVM_REQ_EVENT, vcpu);
5169}
5170
851ba692 5171static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5172{
5173 int r;
6a8b1d13 5174 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5175 vcpu->run->request_interrupt_window;
d6185f20 5176 bool req_immediate_exit = 0;
b6c7a5dc 5177
3e007509 5178 if (vcpu->requests) {
a8eeb04a 5179 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5180 kvm_mmu_unload(vcpu);
a8eeb04a 5181 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5182 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5183 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5184 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5185 if (unlikely(r))
5186 goto out;
5187 }
a8eeb04a 5188 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5189 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5190 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5191 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5192 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5193 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5194 r = 0;
5195 goto out;
5196 }
a8eeb04a 5197 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5198 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5199 r = 0;
5200 goto out;
5201 }
a8eeb04a 5202 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5203 vcpu->fpu_active = 0;
5204 kvm_x86_ops->fpu_deactivate(vcpu);
5205 }
af585b92
GN		 5206 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5207 /* Page is swapped out. Do synthetic halt */
5208 vcpu->arch.apf.halted = true;
5209 r = 1;
5210 goto out;
5211 }
c9aaa895
GC		 5212 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5213 record_steal_time(vcpu);
7460fb4a
AK		 5214 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5215 process_nmi(vcpu);
d6185f20
NHE		 5216 req_immediate_exit =
5217 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5218 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5219 kvm_handle_pmu_event(vcpu);
5220 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5221 kvm_deliver_pmi(vcpu);
2f52d58c 5222 }
b93463aa 5223
3e007509
AK		 5224 r = kvm_mmu_reload(vcpu);
5225 if (unlikely(r))
5226 goto out;
5227
b463a6f7
AK		 5228 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5229 inject_pending_event(vcpu);
5230
5231 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5232 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5233 kvm_x86_ops->enable_nmi_window(vcpu);
5234 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5235 kvm_x86_ops->enable_irq_window(vcpu);
5236
5237 if (kvm_lapic_enabled(vcpu)) {
5238 update_cr8_intercept(vcpu);
5239 kvm_lapic_sync_to_vapic(vcpu);
5240 }
5241 }
5242
b6c7a5dc
HB		 5243 preempt_disable();
5244
5245 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5246 if (vcpu->fpu_active)
5247 kvm_load_guest_fpu(vcpu);
2acf923e 5248 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5249
6b7e2d09
XG		 5250 vcpu->mode = IN_GUEST_MODE;
5251
5252 /* We should set ->mode before check ->requests,
5253 * see the comment in make_all_cpus_request.
5254 */
5255 smp_mb();
b6c7a5dc 5256
d94e1dc9 5257 local_irq_disable();
32f88400 5258
6b7e2d09 5259 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5260 || need_resched() || signal_pending(current)) {
6b7e2d09 5261 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5262 smp_wmb();
6c142801
AK		 5263 local_irq_enable();
5264 preempt_enable();
b463a6f7 5265 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5266 r = 1;
5267 goto out;
5268 }
5269
f656ce01 5270 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5271
d6185f20
NHE		 5272 if (req_immediate_exit)
5273 smp_send_reschedule(vcpu->cpu);
5274
b6c7a5dc
HB		 5275 kvm_guest_enter();
5276
42dbaa5a 5277 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5278 set_debugreg(0, 7);
5279 set_debugreg(vcpu->arch.eff_db[0], 0);
5280 set_debugreg(vcpu->arch.eff_db[1], 1);
5281 set_debugreg(vcpu->arch.eff_db[2], 2);
5282 set_debugreg(vcpu->arch.eff_db[3], 3);
5283 }
b6c7a5dc 5284
229456fc 5285 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5286 kvm_x86_ops->run(vcpu);
b6c7a5dc 5287
24f1e32c
FW		 5288 /*
5289 * If the guest has used debug registers, at least dr7
5290 * will be disabled while returning to the host.
5291 * If we don't have active breakpoints in the host, we don't
5292 * care about the messed up debug address registers. But if
5293 * we have some of them active, restore the old state.
5294 */
59d8eb53 5295 if (hw_breakpoint_active())
24f1e32c 5296 hw_breakpoint_restore();
42dbaa5a 5297
d5c1785d 5298 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5299
6b7e2d09 5300 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5301 smp_wmb();
b6c7a5dc
HB		 5302 local_irq_enable();
5303
5304 ++vcpu->stat.exits;
5305
5306 /*
5307 * We must have an instruction between local_irq_enable() and
5308 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5309 * the interrupt shadow. The stat.exits increment will do nicely.
5310 * But we need to prevent reordering, hence this barrier():
5311 */
5312 barrier();
5313
5314 kvm_guest_exit();
5315
5316 preempt_enable();
5317
f656ce01 5318 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5319
b6c7a5dc
HB		 5320 /*
5321 * Profile KVM exit RIPs:
5322 */
5323 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5324 unsigned long rip = kvm_rip_read(vcpu);
5325 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5326 }
5327
cc578287
ZA		 5328 if (unlikely(vcpu->arch.tsc_always_catchup))
5329 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5330
b93463aa
AK		 5331 kvm_lapic_sync_from_vapic(vcpu);
5332
851ba692 5333 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5334out:
5335 return r;
5336}
b6c7a5dc 5337
09cec754 5338
851ba692 5339static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5340{
5341 int r;
f656ce01 5342 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5343
5344 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5345 pr_debug("vcpu %d received sipi with vector # %x\n",
5346 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5347 kvm_lapic_reset(vcpu);
5f179287 5348 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5349 if (r)
5350 return r;
5351 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5352 }
5353
f656ce01 5354 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5355 vapic_enter(vcpu);
5356
5357 r = 1;
5358 while (r > 0) {
af585b92
GN		 5359 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5360 !vcpu->arch.apf.halted)
851ba692 5361 r = vcpu_enter_guest(vcpu);
d7690175 5362 else {
f656ce01 5363 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5364 kvm_vcpu_block(vcpu);
f656ce01 5365 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5366 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5367 {
5368 switch(vcpu->arch.mp_state) {
5369 case KVM_MP_STATE_HALTED:
d7690175 5370 vcpu->arch.mp_state =
09cec754
GN		 5371 KVM_MP_STATE_RUNNABLE;
5372 case KVM_MP_STATE_RUNNABLE:
af585b92 5373 vcpu->arch.apf.halted = false;
09cec754
GN		 5374 break;
5375 case KVM_MP_STATE_SIPI_RECEIVED:
5376 default:
5377 r = -EINTR;
5378 break;
5379 }
5380 }
d7690175
MT		 5381 }
5382
09cec754
GN		 5383 if (r <= 0)
5384 break;
5385
5386 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5387 if (kvm_cpu_has_pending_timer(vcpu))
5388 kvm_inject_pending_timer_irqs(vcpu);
5389
851ba692 5390 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5391 r = -EINTR;
851ba692 5392 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5393 ++vcpu->stat.request_irq_exits;
5394 }
af585b92
GN		 5395
5396 kvm_check_async_pf_completion(vcpu);
5397
09cec754
GN		 5398 if (signal_pending(current)) {
5399 r = -EINTR;
851ba692 5400 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5401 ++vcpu->stat.signal_exits;
5402 }
5403 if (need_resched()) {
f656ce01 5404 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5405 kvm_resched(vcpu);
f656ce01 5406 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5407 }
b6c7a5dc
HB		 5408 }
5409
f656ce01 5410 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5411
b93463aa
AK		 5412 vapic_exit(vcpu);
5413
b6c7a5dc
HB		 5414 return r;
5415}
5416
5287f194
AK		 5417static int complete_mmio(struct kvm_vcpu *vcpu)
5418{
5419 struct kvm_run *run = vcpu->run;
5420 int r;
5421
5422 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5423 return 1;
5424
5425 if (vcpu->mmio_needed) {
5287f194 5426 vcpu->mmio_needed = 0;
cef4dea0 5427 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5428 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5429 run->mmio.data, 8);
cef4dea0
AK		 5430 vcpu->mmio_index += 8;
5431 if (vcpu->mmio_index < vcpu->mmio_size) {
5432 run->exit_reason = KVM_EXIT_MMIO;
5433 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5434 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5435 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5436 run->mmio.is_write = vcpu->mmio_is_write;
5437 vcpu->mmio_needed = 1;
5438 return 0;
5439 }
5440 if (vcpu->mmio_is_write)
5441 return 1;
5442 vcpu->mmio_read_completed = 1;
5287f194
AK		 5443 }
5444 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5445 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5446 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5447 if (r != EMULATE_DONE)
5448 return 0;
5449 return 1;
5450}
5451
b6c7a5dc
HB		 5452int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5453{
5454 int r;
5455 sigset_t sigsaved;
5456
e5c30142
AK		 5457 if (!tsk_used_math(current) && init_fpu(current))
5458 return -ENOMEM;
5459
ac9f6dc0
AK		 5460 if (vcpu->sigset_active)
5461 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5462
a4535290 5463 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5464 kvm_vcpu_block(vcpu);
d7690175 5465 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5466 r = -EAGAIN;
5467 goto out;
b6c7a5dc
HB		 5468 }
5469
b6c7a5dc 5470 /* re-sync apic's tpr */
eea1cff9
AP		 5471 if (!irqchip_in_kernel(vcpu->kvm)) {
5472 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5473 r = -EINVAL;
5474 goto out;
5475 }
5476 }
b6c7a5dc 5477
5287f194
AK		 5478 r = complete_mmio(vcpu);
5479 if (r <= 0)
5480 goto out;
5481
851ba692 5482 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5483
5484out:
f1d86e46 5485 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5486 if (vcpu->sigset_active)
5487 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5488
b6c7a5dc
HB		 5489 return r;
5490}
5491
5492int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5493{
7ae441ea
GN		 5494 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5495 /*
5496 * We are here if userspace calls get_regs() in the middle of
5497 * instruction emulation. Registers state needs to be copied
5498 * back from emulation context to vcpu. Usrapace shouldn't do
5499 * that usually, but some bad designed PV devices (vmware
5500 * backdoor interface) need this to work
5501 */
9dac77fa
AK		 5502 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5503 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5504 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5505 }
5fdbf976
MT		 5506 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5507 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5508 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5509 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5510 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5511 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5512 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5513 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5514#ifdef CONFIG_X86_64
5fdbf976
MT		 5515 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5516 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5517 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5518 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5519 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5520 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5521 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5522 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5523#endif
5524
5fdbf976 5525 regs->rip = kvm_rip_read(vcpu);
91586a3b 5526 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5527
b6c7a5dc
HB		 5528 return 0;
5529}
5530
5531int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5532{
7ae441ea
GN		 5533 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5534 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5535
5fdbf976
MT		 5536 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5537 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5538 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5539 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5540 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5541 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5542 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5543 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5544#ifdef CONFIG_X86_64
5fdbf976
MT		 5545 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5546 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5547 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5548 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5549 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5550 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5551 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5552 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5553#endif
5554
5fdbf976 5555 kvm_rip_write(vcpu, regs->rip);
91586a3b 5556 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5557
b4f14abd
JK		 5558 vcpu->arch.exception.pending = false;
5559
3842d135
AK		 5560 kvm_make_request(KVM_REQ_EVENT, vcpu);
5561
b6c7a5dc
HB		 5562 return 0;
5563}
5564
b6c7a5dc
HB		 5565void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5566{
5567 struct kvm_segment cs;
5568
3e6e0aab 5569 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5570 *db = cs.db;
5571 *l = cs.l;
5572}
5573EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5574
5575int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5576 struct kvm_sregs *sregs)
5577{
89a27f4d 5578 struct desc_ptr dt;
b6c7a5dc 5579
3e6e0aab
GT		 5580 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5581 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5582 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5583 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5584 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5585 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5586
3e6e0aab
GT		 5587 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5588 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5589
5590 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5591 sregs->idt.limit = dt.size;
5592 sregs->idt.base = dt.address;
b6c7a5dc 5593 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5594 sregs->gdt.limit = dt.size;
5595 sregs->gdt.base = dt.address;
b6c7a5dc 5596
4d4ec087 5597 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5598 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5599 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5600 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5601 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5602 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5603 sregs->apic_base = kvm_get_apic_base(vcpu);
5604
923c61bb 5605 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5606
36752c9b 5607 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5608 set_bit(vcpu->arch.interrupt.nr,
5609 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5610
b6c7a5dc
HB		 5611 return 0;
5612}
5613
62d9f0db
MT		 5614int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5615 struct kvm_mp_state *mp_state)
5616{
62d9f0db 5617 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5618 return 0;
5619}
5620
5621int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5622 struct kvm_mp_state *mp_state)
5623{
62d9f0db 5624 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5625 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5626 return 0;
5627}
5628
e269fb21
JK		 5629int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5630 bool has_error_code, u32 error_code)
b6c7a5dc 5631{
9d74191a 5632 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5633 int ret;
e01c2426 5634
8ec4722d 5635 init_emulate_ctxt(vcpu);
c697518a 5636
9d74191a
TY		 5637 ret = emulator_task_switch(ctxt, tss_selector, reason,
5638 has_error_code, error_code);
c697518a 5639
c697518a 5640 if (ret)
19d04437 5641 return EMULATE_FAIL;
37817f29 5642
9dac77fa 5643 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5644 kvm_rip_write(vcpu, ctxt->eip);
5645 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5646 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5647 return EMULATE_DONE;
37817f29
IE		 5648}
5649EXPORT_SYMBOL_GPL(kvm_task_switch);
5650
b6c7a5dc
HB		 5651int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5652 struct kvm_sregs *sregs)
5653{
5654 int mmu_reset_needed = 0;
63f42e02 5655 int pending_vec, max_bits, idx;
89a27f4d 5656 struct desc_ptr dt;
b6c7a5dc 5657
89a27f4d
GN		 5658 dt.size = sregs->idt.limit;
5659 dt.address = sregs->idt.base;
b6c7a5dc 5660 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5661 dt.size = sregs->gdt.limit;
5662 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5663 kvm_x86_ops->set_gdt(vcpu, &dt);
5664
ad312c7c 5665 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5666 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5667 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5669
2d3ad1f4 5670 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5671
f6801dff 5672 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5673 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5674 kvm_set_apic_base(vcpu, sregs->apic_base);
5675
4d4ec087 5676 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5677 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5678 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5679
fc78f519 5680 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5681 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5682 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5683 kvm_update_cpuid(vcpu);
63f42e02
XG		 5684
5685 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5686 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5687 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5688 mmu_reset_needed = 1;
5689 }
63f42e02 5690 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5691
5692 if (mmu_reset_needed)
5693 kvm_mmu_reset_context(vcpu);
5694
923c61bb
GN		 5695 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5696 pending_vec = find_first_bit(
5697 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5698 if (pending_vec < max_bits) {
66fd3f7f 5699 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5700 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5701 }
5702
3e6e0aab
GT		 5703 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5704 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5705 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5706 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5707 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5708 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5709
3e6e0aab
GT		 5710 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5711 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5712
5f0269f5
ME		 5713 update_cr8_intercept(vcpu);
5714
9c3e4aab 5715 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5716 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5717 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5718 !is_protmode(vcpu))
9c3e4aab
MT		 5719 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5720
3842d135
AK		 5721 kvm_make_request(KVM_REQ_EVENT, vcpu);
5722
b6c7a5dc
HB		 5723 return 0;
5724}
5725
d0bfb940
JK		 5726int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5727 struct kvm_guest_debug *dbg)
b6c7a5dc 5728{
355be0b9 5729 unsigned long rflags;
ae675ef0 5730 int i, r;
b6c7a5dc 5731
4f926bf2
JK		 5732 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5733 r = -EBUSY;
5734 if (vcpu->arch.exception.pending)
2122ff5e 5735 goto out;
4f926bf2
JK		 5736 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5737 kvm_queue_exception(vcpu, DB_VECTOR);
5738 else
5739 kvm_queue_exception(vcpu, BP_VECTOR);
5740 }
5741
91586a3b
JK		 5742 /*
5743 * Read rflags as long as potentially injected trace flags are still
5744 * filtered out.
5745 */
5746 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5747
5748 vcpu->guest_debug = dbg->control;
5749 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5750 vcpu->guest_debug = 0;
5751
5752 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5753 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5754 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5755 vcpu->arch.switch_db_regs =
5756 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5757 } else {
5758 for (i = 0; i < KVM_NR_DB_REGS; i++)
5759 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5760 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5761 }
5762
f92653ee
JK		 5763 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5764 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5765 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5766
91586a3b
JK		 5767 /*
5768 * Trigger an rflags update that will inject or remove the trace
5769 * flags.
5770 */
5771 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5772
355be0b9 5773 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5774
4f926bf2 5775 r = 0;
d0bfb940 5776
2122ff5e 5777out:
b6c7a5dc
HB		 5778
5779 return r;
5780}
5781
8b006791
ZX		 5782/*
5783 * Translate a guest virtual address to a guest physical address.
5784 */
5785int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5786 struct kvm_translation *tr)
5787{
5788 unsigned long vaddr = tr->linear_address;
5789 gpa_t gpa;
f656ce01 5790 int idx;
8b006791 5791
f656ce01 5792 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5793 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5794 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5795 tr->physical_address = gpa;
5796 tr->valid = gpa != UNMAPPED_GVA;
5797 tr->writeable = 1;
5798 tr->usermode = 0;
8b006791
ZX		 5799
5800 return 0;
5801}
5802
d0752060
HB		 5803int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5804{
98918833
SY		 5805 struct i387_fxsave_struct *fxsave =
5806 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5807
d0752060
HB		 5808 memcpy(fpu->fpr, fxsave->st_space, 128);
5809 fpu->fcw = fxsave->cwd;
5810 fpu->fsw = fxsave->swd;
5811 fpu->ftwx = fxsave->twd;
5812 fpu->last_opcode = fxsave->fop;
5813 fpu->last_ip = fxsave->rip;
5814 fpu->last_dp = fxsave->rdp;
5815 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5816
d0752060
HB		 5817 return 0;
5818}
5819
5820int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5821{
98918833
SY		 5822 struct i387_fxsave_struct *fxsave =
5823 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5824
d0752060
HB		 5825 memcpy(fxsave->st_space, fpu->fpr, 128);
5826 fxsave->cwd = fpu->fcw;
5827 fxsave->swd = fpu->fsw;
5828 fxsave->twd = fpu->ftwx;
5829 fxsave->fop = fpu->last_opcode;
5830 fxsave->rip = fpu->last_ip;
5831 fxsave->rdp = fpu->last_dp;
5832 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5833
d0752060
HB		 5834 return 0;
5835}
5836
10ab25cd 5837int fx_init(struct kvm_vcpu *vcpu)
d0752060 5838{
10ab25cd
JK		 5839 int err;
5840
5841 err = fpu_alloc(&vcpu->arch.guest_fpu);
5842 if (err)
5843 return err;
5844
98918833 5845 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5846
2acf923e
DC		 5847 /*
5848 * Ensure guest xcr0 is valid for loading
5849 */
5850 vcpu->arch.xcr0 = XSTATE_FP;
5851
ad312c7c 5852 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5853
5854 return 0;
d0752060
HB		 5855}
5856EXPORT_SYMBOL_GPL(fx_init);
5857
98918833
SY		 5858static void fx_free(struct kvm_vcpu *vcpu)
5859{
5860 fpu_free(&vcpu->arch.guest_fpu);
5861}
5862
d0752060
HB		 5863void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5864{
2608d7a1 5865 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5866 return;
5867
2acf923e
DC		 5868 /*
5869 * Restore all possible states in the guest,
5870 * and assume host would use all available bits.
5871 * Guest xcr0 would be loaded later.
5872 */
5873 kvm_put_guest_xcr0(vcpu);
d0752060 5874 vcpu->guest_fpu_loaded = 1;
7cf30855 5875 unlazy_fpu(current);
98918833 5876 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5877 trace_kvm_fpu(1);
d0752060 5878}
d0752060
HB		 5879
5880void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5881{
2acf923e
DC		 5882 kvm_put_guest_xcr0(vcpu);
5883
d0752060
HB		 5884 if (!vcpu->guest_fpu_loaded)
5885 return;
5886
5887 vcpu->guest_fpu_loaded = 0;
98918833 5888 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5889 ++vcpu->stat.fpu_reload;
a8eeb04a 5890 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5891 trace_kvm_fpu(0);
d0752060 5892}
e9b11c17
ZX		 5893
5894void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5895{
12f9a48f 5896 kvmclock_reset(vcpu);
7f1ea208 5897
f5f48ee1 5898 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5899 fx_free(vcpu);
e9b11c17
ZX		 5900 kvm_x86_ops->vcpu_free(vcpu);
5901}
5902
5903struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5904 unsigned int id)
5905{
6755bae8
ZA		 5906 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5907 printk_once(KERN_WARNING
5908 "kvm: SMP vm created on host with unstable TSC; "
5909 "guest TSC will not be reliable\n");
26e5215f
AK		 5910 return kvm_x86_ops->vcpu_create(kvm, id);
5911}
e9b11c17 5912
26e5215f
AK		 5913int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5914{
5915 int r;
e9b11c17 5916
0bed3b56 5917 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5918 vcpu_load(vcpu);
5919 r = kvm_arch_vcpu_reset(vcpu);
5920 if (r == 0)
5921 r = kvm_mmu_setup(vcpu);
5922 vcpu_put(vcpu);
e9b11c17 5923
26e5215f 5924 return r;
e9b11c17
ZX		 5925}
5926
d40ccc62 5927void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5928{
344d9588
GN		 5929 vcpu->arch.apf.msr_val = 0;
5930
e9b11c17
ZX		 5931 vcpu_load(vcpu);
5932 kvm_mmu_unload(vcpu);
5933 vcpu_put(vcpu);
5934
98918833 5935 fx_free(vcpu);
e9b11c17
ZX		 5936 kvm_x86_ops->vcpu_free(vcpu);
5937}
5938
5939int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5940{
7460fb4a
AK		 5941 atomic_set(&vcpu->arch.nmi_queued, 0);
5942 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 5943 vcpu->arch.nmi_injected = false;
5944
42dbaa5a
JK		 5945 vcpu->arch.switch_db_regs = 0;
5946 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5947 vcpu->arch.dr6 = DR6_FIXED_1;
5948 vcpu->arch.dr7 = DR7_FIXED_1;
5949
3842d135 5950 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5951 vcpu->arch.apf.msr_val = 0;
c9aaa895 5952 vcpu->arch.st.msr_val = 0;
3842d135 5953
12f9a48f
GC		 5954 kvmclock_reset(vcpu);
5955
af585b92
GN		 5956 kvm_clear_async_pf_completion_queue(vcpu);
5957 kvm_async_pf_hash_reset(vcpu);
5958 vcpu->arch.apf.halted = false;
3842d135 5959
f5132b01
GN		 5960 kvm_pmu_reset(vcpu);
5961
e9b11c17
ZX		 5962 return kvm_x86_ops->vcpu_reset(vcpu);
5963}
5964
10474ae8 5965int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5966{
ca84d1a2
ZA		 5967 struct kvm *kvm;
5968 struct kvm_vcpu *vcpu;
5969 int i;
18863bdd
AK		 5970
5971 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5972 list_for_each_entry(kvm, &vm_list, vm_list)
5973 kvm_for_each_vcpu(i, vcpu, kvm)
5974 if (vcpu->cpu == smp_processor_id())
c285545f 5975 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5976 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5977}
5978
5979void kvm_arch_hardware_disable(void *garbage)
5980{
5981 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5982 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5983}
5984
5985int kvm_arch_hardware_setup(void)
5986{
5987 return kvm_x86_ops->hardware_setup();
5988}
5989
5990void kvm_arch_hardware_unsetup(void)
5991{
5992 kvm_x86_ops->hardware_unsetup();
5993}
5994
5995void kvm_arch_check_processor_compat(void *rtn)
5996{
5997 kvm_x86_ops->check_processor_compatibility(rtn);
5998}
5999
6000int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6001{
6002 struct page *page;
6003 struct kvm *kvm;
6004 int r;
6005
6006 BUG_ON(vcpu->kvm == NULL);
6007 kvm = vcpu->kvm;
6008
9aabc88f 6009 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6010 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6011 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6012 else
a4535290 6013 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6014
6015 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6016 if (!page) {
6017 r = -ENOMEM;
6018 goto fail;
6019 }
ad312c7c 6020 vcpu->arch.pio_data = page_address(page);
e9b11c17 6021
cc578287 6022 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6023
e9b11c17
ZX		 6024 r = kvm_mmu_create(vcpu);
6025 if (r < 0)
6026 goto fail_free_pio_data;
6027
6028 if (irqchip_in_kernel(kvm)) {
6029 r = kvm_create_lapic(vcpu);
6030 if (r < 0)
6031 goto fail_mmu_destroy;
6032 }
6033
890ca9ae
HY		 6034 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6035 GFP_KERNEL);
6036 if (!vcpu->arch.mce_banks) {
6037 r = -ENOMEM;
443c39bc 6038 goto fail_free_lapic;
890ca9ae
HY		 6039 }
6040 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6041
f5f48ee1
SY		 6042 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6043 goto fail_free_mce_banks;
6044
af585b92 6045 kvm_async_pf_hash_reset(vcpu);
f5132b01 6046 kvm_pmu_init(vcpu);
af585b92 6047
e9b11c17 6048 return 0;
f5f48ee1
SY		 6049fail_free_mce_banks:
6050 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6051fail_free_lapic:
6052 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6053fail_mmu_destroy:
6054 kvm_mmu_destroy(vcpu);
6055fail_free_pio_data:
ad312c7c 6056 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6057fail:
6058 return r;
6059}
6060
6061void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6062{
f656ce01
MT		 6063 int idx;
6064
f5132b01 6065 kvm_pmu_destroy(vcpu);
36cb93fd 6066 kfree(vcpu->arch.mce_banks);
e9b11c17 6067 kvm_free_lapic(vcpu);
f656ce01 6068 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6069 kvm_mmu_destroy(vcpu);
f656ce01 6070 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6071 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6072}
d19a9cd2 6073
e08b9637 6074int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6075{
e08b9637
CO		 6076 if (type)
6077 return -EINVAL;
6078
f05e70ac 6079 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6080 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6081
5550af4d
SY		 6082 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6083 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6084
038f8c11 6085 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6086
d89f5eff 6087 return 0;
d19a9cd2
ZX		 6088}
6089
6090static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6091{
6092 vcpu_load(vcpu);
6093 kvm_mmu_unload(vcpu);
6094 vcpu_put(vcpu);
6095}
6096
6097static void kvm_free_vcpus(struct kvm *kvm)
6098{
6099 unsigned int i;
988a2cae 6100 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6101
6102 /*
6103 * Unpin any mmu pages first.
6104 */
af585b92
GN		 6105 kvm_for_each_vcpu(i, vcpu, kvm) {
6106 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6107 kvm_unload_vcpu_mmu(vcpu);
af585b92 6108 }
988a2cae
GN		 6109 kvm_for_each_vcpu(i, vcpu, kvm)
6110 kvm_arch_vcpu_free(vcpu);
6111
6112 mutex_lock(&kvm->lock);
6113 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6114 kvm->vcpus[i] = NULL;
d19a9cd2 6115
988a2cae
GN		 6116 atomic_set(&kvm->online_vcpus, 0);
6117 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6118}
6119
ad8ba2cd
SY		 6120void kvm_arch_sync_events(struct kvm *kvm)
6121{
ba4cef31 6122 kvm_free_all_assigned_devices(kvm);
aea924f6 6123 kvm_free_pit(kvm);
ad8ba2cd
SY		 6124}
6125
d19a9cd2
ZX		 6126void kvm_arch_destroy_vm(struct kvm *kvm)
6127{
6eb55818 6128 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6129 kfree(kvm->arch.vpic);
6130 kfree(kvm->arch.vioapic);
d19a9cd2 6131 kvm_free_vcpus(kvm);
3d45830c
AK		 6132 if (kvm->arch.apic_access_page)
6133 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6134 if (kvm->arch.ept_identity_pagetable)
6135 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6136}
0de10343 6137
f7784b8e
MT		 6138int kvm_arch_prepare_memory_region(struct kvm *kvm,
6139 struct kvm_memory_slot *memslot,
0de10343 6140 struct kvm_memory_slot old,
f7784b8e 6141 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6142 int user_alloc)
6143{
f7784b8e 6144 int npages = memslot->npages;
7ac77099
AK		 6145 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6146
6147 /* Prevent internal slot pages from being moved by fork()/COW. */
6148 if (memslot->id >= KVM_MEMORY_SLOTS)
6149 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6150
6151 /*To keep backward compatibility with older userspace,
6152 *x86 needs to hanlde !user_alloc case.
6153 */
6154 if (!user_alloc) {
6155 if (npages && !old.rmap) {
604b38ac
AA		 6156 unsigned long userspace_addr;
6157
72dc67a6 6158 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6159 userspace_addr = do_mmap(NULL, 0,
6160 npages * PAGE_SIZE,
6161 PROT_READ | PROT_WRITE,
7ac77099 6162 map_flags,
604b38ac 6163 0);
72dc67a6 6164 up_write(&current->mm->mmap_sem);
0de10343 6165
604b38ac
AA		 6166 if (IS_ERR((void *)userspace_addr))
6167 return PTR_ERR((void *)userspace_addr);
6168
604b38ac 6169 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6170 }
6171 }
6172
f7784b8e
MT		 6173
6174 return 0;
6175}
6176
6177void kvm_arch_commit_memory_region(struct kvm *kvm,
6178 struct kvm_userspace_memory_region *mem,
6179 struct kvm_memory_slot old,
6180 int user_alloc)
6181{
6182
48c0e4e9 6183 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6184
6185 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6186 int ret;
6187
6188 down_write(&current->mm->mmap_sem);
6189 ret = do_munmap(current->mm, old.userspace_addr,
6190 old.npages * PAGE_SIZE);
6191 up_write(&current->mm->mmap_sem);
6192 if (ret < 0)
6193 printk(KERN_WARNING
6194 "kvm_vm_ioctl_set_memory_region: "
6195 "failed to munmap memory\n");
6196 }
6197
48c0e4e9
XG		 6198 if (!kvm->arch.n_requested_mmu_pages)
6199 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6200
7c8a83b7 6201 spin_lock(&kvm->mmu_lock);
48c0e4e9 6202 if (nr_mmu_pages)
0de10343 6203 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6204 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6205 spin_unlock(&kvm->mmu_lock);
0de10343 6206}
1d737c8a 6207
34d4cb8f
MT		 6208void kvm_arch_flush_shadow(struct kvm *kvm)
6209{
6210 kvm_mmu_zap_all(kvm);
8986ecc0 6211 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6212}
6213
1d737c8a
ZX		 6214int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6215{
af585b92
GN		 6216 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6217 !vcpu->arch.apf.halted)
6218 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6219 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6220 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6221 (kvm_arch_interrupt_allowed(vcpu) &&
6222 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6223}
5736199a 6224
5736199a
ZX		 6225void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6226{
32f88400
MT		 6227 int me;
6228 int cpu = vcpu->cpu;
5736199a
ZX		 6229
6230 if (waitqueue_active(&vcpu->wq)) {
6231 wake_up_interruptible(&vcpu->wq);
6232 ++vcpu->stat.halt_wakeup;
6233 }
32f88400
MT		 6234
6235 me = get_cpu();
6236 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6237 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6238 smp_send_reschedule(cpu);
e9571ed5 6239 put_cpu();
5736199a 6240}
78646121
GN		 6241
6242int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6243{
6244 return kvm_x86_ops->interrupt_allowed(vcpu);
6245}
229456fc 6246
f92653ee
JK		 6247bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6248{
6249 unsigned long current_rip = kvm_rip_read(vcpu) +
6250 get_segment_base(vcpu, VCPU_SREG_CS);
6251
6252 return current_rip == linear_rip;
6253}
6254EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6255
94fe45da
JK		 6256unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6257{
6258 unsigned long rflags;
6259
6260 rflags = kvm_x86_ops->get_rflags(vcpu);
6261 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6262 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6263 return rflags;
6264}
6265EXPORT_SYMBOL_GPL(kvm_get_rflags);
6266
6267void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6268{
6269 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6270 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6271 rflags |= X86_EFLAGS_TF;
94fe45da 6272 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6273 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6274}
6275EXPORT_SYMBOL_GPL(kvm_set_rflags);
6276
56028d08
GN		 6277void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6278{
6279 int r;
6280
fb67e14f 6281 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6282 is_error_page(work->page))
56028d08
GN		 6283 return;
6284
6285 r = kvm_mmu_reload(vcpu);
6286 if (unlikely(r))
6287 return;
6288
fb67e14f
XG		 6289 if (!vcpu->arch.mmu.direct_map &&
6290 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6291 return;
6292
56028d08
GN		 6293 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6294}
6295
af585b92
GN		 6296static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6297{
6298 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6299}
6300
6301static inline u32 kvm_async_pf_next_probe(u32 key)
6302{
6303 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6304}
6305
6306static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6307{
6308 u32 key = kvm_async_pf_hash_fn(gfn);
6309
6310 while (vcpu->arch.apf.gfns[key] != ~0)
6311 key = kvm_async_pf_next_probe(key);
6312
6313 vcpu->arch.apf.gfns[key] = gfn;
6314}
6315
6316static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6317{
6318 int i;
6319 u32 key = kvm_async_pf_hash_fn(gfn);
6320
6321 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6322 (vcpu->arch.apf.gfns[key] != gfn &&
6323 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6324 key = kvm_async_pf_next_probe(key);
6325
6326 return key;
6327}
6328
6329bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6330{
6331 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6332}
6333
6334static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6335{
6336 u32 i, j, k;
6337
6338 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6339 while (true) {
6340 vcpu->arch.apf.gfns[i] = ~0;
6341 do {
6342 j = kvm_async_pf_next_probe(j);
6343 if (vcpu->arch.apf.gfns[j] == ~0)
6344 return;
6345 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6346 /*
6347 * k lies cyclically in ]i,j]
6348 * | i.k.j |
6349 * |....j i.k.| or |.k..j i...|
6350 */
6351 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6352 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6353 i = j;
6354 }
6355}
6356
7c90705b
GN		 6357static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6358{
6359
6360 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6361 sizeof(val));
6362}
6363
af585b92
GN		 6364void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6365 struct kvm_async_pf *work)
6366{
6389ee94
AK		 6367 struct x86_exception fault;
6368
7c90705b 6369 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6370 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6371
6372 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6373 (vcpu->arch.apf.send_user_only &&
6374 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6375 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6376 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6377 fault.vector = PF_VECTOR;
6378 fault.error_code_valid = true;
6379 fault.error_code = 0;
6380 fault.nested_page_fault = false;
6381 fault.address = work->arch.token;
6382 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6383 }
af585b92
GN		 6384}
6385
6386void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6387 struct kvm_async_pf *work)
6388{
6389ee94
AK		 6389 struct x86_exception fault;
6390
7c90705b
GN		 6391 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6392 if (is_error_page(work->page))
6393 work->arch.token = ~0; /* broadcast wakeup */
6394 else
6395 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6396
6397 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6398 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6399 fault.vector = PF_VECTOR;
6400 fault.error_code_valid = true;
6401 fault.error_code = 0;
6402 fault.nested_page_fault = false;
6403 fault.address = work->arch.token;
6404 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6405 }
e6d53e3b 6406 vcpu->arch.apf.halted = false;
7c90705b
GN		 6407}
6408
6409bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6410{
6411 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6412 return true;
6413 else
6414 return !kvm_event_needs_reinjection(vcpu) &&
6415 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6416}
6417
229456fc
MT		 6418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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