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KVM: Remove unnecessary ->decache_regs() call
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <avi@qumranet.com>
10 * Yaniv Kamay <yaniv@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
7837699f 20#include "i8254.h"
37817f29 21#include "tss.h"
313a3dc7 22
18068523 23#include <linux/clocksource.h>
313a3dc7
CO		 24#include <linux/kvm.h>
25#include <linux/fs.h>
26#include <linux/vmalloc.h>
5fb76f9b 27#include <linux/module.h>
0de10343 28#include <linux/mman.h>
2bacc55c 29#include <linux/highmem.h>
043405e1
CO		 30
31#include <asm/uaccess.h>
d825ed0a 32#include <asm/msr.h>
a5f61300 33#include <asm/desc.h>
043405e1 34
313a3dc7 35#define MAX_IO_MSRS 256
a03490ed
CO		 36#define CR0_RESERVED_BITS \
37 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
38 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
39 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
40#define CR4_RESERVED_BITS \
41 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
42 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
43 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
44 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
45
46#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 47/* EFER defaults:
48 * - enable syscall per default because its emulated by KVM
49 * - enable LME and LMA per default on 64 bit KVM
50 */
51#ifdef CONFIG_X86_64
52static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
53#else
54static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
55#endif
313a3dc7 56
ba1389b7
AK		 57#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
58#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 59
674eea0f
AK		 60static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
61 struct kvm_cpuid_entry2 __user *entries);
62
97896d04
ZX		 63struct kvm_x86_ops *kvm_x86_ops;
64
417bc304 65struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 66 { "pf_fixed", VCPU_STAT(pf_fixed) },
67 { "pf_guest", VCPU_STAT(pf_guest) },
68 { "tlb_flush", VCPU_STAT(tlb_flush) },
69 { "invlpg", VCPU_STAT(invlpg) },
70 { "exits", VCPU_STAT(exits) },
71 { "io_exits", VCPU_STAT(io_exits) },
72 { "mmio_exits", VCPU_STAT(mmio_exits) },
73 { "signal_exits", VCPU_STAT(signal_exits) },
74 { "irq_window", VCPU_STAT(irq_window_exits) },
75 { "halt_exits", VCPU_STAT(halt_exits) },
76 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 77 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 78 { "request_irq", VCPU_STAT(request_irq_exits) },
79 { "irq_exits", VCPU_STAT(irq_exits) },
80 { "host_state_reload", VCPU_STAT(host_state_reload) },
81 { "efer_reload", VCPU_STAT(efer_reload) },
82 { "fpu_reload", VCPU_STAT(fpu_reload) },
83 { "insn_emulation", VCPU_STAT(insn_emulation) },
84 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 85 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
86 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
87 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
88 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
89 { "mmu_flooded", VM_STAT(mmu_flooded) },
90 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 91 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 92 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 93 { "largepages", VM_STAT(lpages) },
417bc304
HB		 94 { NULL }
95};
96
97
5fb76f9b
CO		 98unsigned long segment_base(u16 selector)
99{
100 struct descriptor_table gdt;
a5f61300 101 struct desc_struct *d;
5fb76f9b
CO		 102 unsigned long table_base;
103 unsigned long v;
104
105 if (selector == 0)
106 return 0;
107
108 asm("sgdt %0" : "=m"(gdt));
109 table_base = gdt.base;
110
111 if (selector & 4) { /* from ldt */
112 u16 ldt_selector;
113
114 asm("sldt %0" : "=g"(ldt_selector));
115 table_base = segment_base(ldt_selector);
116 }
a5f61300
AK		 117 d = (struct desc_struct *)(table_base + (selector & ~7));
118 v = d->base0 | ((unsigned long)d->base1 << 16) |
119 ((unsigned long)d->base2 << 24);
5fb76f9b 120#ifdef CONFIG_X86_64
a5f61300
AK		 121 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
122 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 123#endif
124 return v;
125}
126EXPORT_SYMBOL_GPL(segment_base);
127
6866b83e
CO		 128u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
129{
130 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 131 return vcpu->arch.apic_base;
6866b83e 132 else
ad312c7c 133 return vcpu->arch.apic_base;
6866b83e
CO		 134}
135EXPORT_SYMBOL_GPL(kvm_get_apic_base);
136
137void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
138{
139 /* TODO: reserve bits check */
140 if (irqchip_in_kernel(vcpu->kvm))
141 kvm_lapic_set_base(vcpu, data);
142 else
ad312c7c 143 vcpu->arch.apic_base = data;
6866b83e
CO		 144}
145EXPORT_SYMBOL_GPL(kvm_set_apic_base);
146
298101da
AK		 147void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
148{
ad312c7c
ZX		 149 WARN_ON(vcpu->arch.exception.pending);
150 vcpu->arch.exception.pending = true;
151 vcpu->arch.exception.has_error_code = false;
152 vcpu->arch.exception.nr = nr;
298101da
AK		 153}
154EXPORT_SYMBOL_GPL(kvm_queue_exception);
155
c3c91fee
AK		 156void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
157 u32 error_code)
158{
159 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 160 if (vcpu->arch.exception.pending) {
161 if (vcpu->arch.exception.nr == PF_VECTOR) {
162 printk(KERN_DEBUG "kvm: inject_page_fault:"
163 " double fault 0x%lx\n", addr);
164 vcpu->arch.exception.nr = DF_VECTOR;
165 vcpu->arch.exception.error_code = 0;
166 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
167 /* triple fault -> shutdown */
168 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
169 }
c3c91fee
AK		 170 return;
171 }
ad312c7c 172 vcpu->arch.cr2 = addr;
c3c91fee
AK		 173 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
174}
175
298101da
AK		 176void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
177{
ad312c7c
ZX		 178 WARN_ON(vcpu->arch.exception.pending);
179 vcpu->arch.exception.pending = true;
180 vcpu->arch.exception.has_error_code = true;
181 vcpu->arch.exception.nr = nr;
182 vcpu->arch.exception.error_code = error_code;
298101da
AK		 183}
184EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
185
186static void __queue_exception(struct kvm_vcpu *vcpu)
187{
ad312c7c
ZX		 188 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
189 vcpu->arch.exception.has_error_code,
190 vcpu->arch.exception.error_code);
298101da
AK		 191}
192
a03490ed
CO		 193/*
194 * Load the pae pdptrs. Return true is they are all valid.
195 */
196int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
197{
198 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
199 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
200 int i;
201 int ret;
ad312c7c 202 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 203
a03490ed
CO		 204 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
205 offset * sizeof(u64), sizeof(pdpte));
206 if (ret < 0) {
207 ret = 0;
208 goto out;
209 }
210 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
211 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
212 ret = 0;
213 goto out;
214 }
215 }
216 ret = 1;
217
ad312c7c 218 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 219out:
a03490ed
CO		 220
221 return ret;
222}
cc4b6871 223EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 224
d835dfec
AK		 225static bool pdptrs_changed(struct kvm_vcpu *vcpu)
226{
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 228 bool changed = true;
229 int r;
230
231 if (is_long_mode(vcpu) || !is_pae(vcpu))
232 return false;
233
ad312c7c 234 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 235 if (r < 0)
236 goto out;
ad312c7c 237 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 238out:
d835dfec
AK		 239
240 return changed;
241}
242
2d3ad1f4 243void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 244{
245 if (cr0 & CR0_RESERVED_BITS) {
246 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 247 cr0, vcpu->arch.cr0);
c1a5d4f9 248 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 249 return;
250 }
251
252 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
253 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 254 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 255 return;
256 }
257
258 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
259 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
260 "and a clear PE flag\n");
c1a5d4f9 261 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 262 return;
263 }
264
265 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
266#ifdef CONFIG_X86_64
ad312c7c 267 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 268 int cs_db, cs_l;
269
270 if (!is_pae(vcpu)) {
271 printk(KERN_DEBUG "set_cr0: #GP, start paging "
272 "in long mode while PAE is disabled\n");
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
277 if (cs_l) {
278 printk(KERN_DEBUG "set_cr0: #GP, start paging "
279 "in long mode while CS.L == 1\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282
283 }
284 } else
285#endif
ad312c7c 286 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 287 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
288 "reserved bits\n");
c1a5d4f9 289 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 290 return;
291 }
292
293 }
294
295 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 296 vcpu->arch.cr0 = cr0;
a03490ed 297
a03490ed 298 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 299 return;
300}
2d3ad1f4 301EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 302
2d3ad1f4 303void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 304{
2d3ad1f4 305 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 306 KVMTRACE_1D(LMSW, vcpu,
307 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
308 handler);
a03490ed 309}
2d3ad1f4 310EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 311
2d3ad1f4 312void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 313{
314 if (cr4 & CR4_RESERVED_BITS) {
315 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 316 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 317 return;
318 }
319
320 if (is_long_mode(vcpu)) {
321 if (!(cr4 & X86_CR4_PAE)) {
322 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
323 "in long mode\n");
c1a5d4f9 324 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 325 return;
326 }
327 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 328 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 329 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 330 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 331 return;
332 }
333
334 if (cr4 & X86_CR4_VMXE) {
335 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 336 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 337 return;
338 }
339 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 340 vcpu->arch.cr4 = cr4;
a03490ed 341 kvm_mmu_reset_context(vcpu);
a03490ed 342}
2d3ad1f4 343EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 344
2d3ad1f4 345void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 346{
ad312c7c 347 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 348 kvm_mmu_flush_tlb(vcpu);
349 return;
350 }
351
a03490ed
CO		 352 if (is_long_mode(vcpu)) {
353 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
354 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 355 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 356 return;
357 }
358 } else {
359 if (is_pae(vcpu)) {
360 if (cr3 & CR3_PAE_RESERVED_BITS) {
361 printk(KERN_DEBUG
362 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 363 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 364 return;
365 }
366 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
367 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
368 "reserved bits\n");
c1a5d4f9 369 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 370 return;
371 }
372 }
373 /*
374 * We don't check reserved bits in nonpae mode, because
375 * this isn't enforced, and VMware depends on this.
376 */
377 }
378
a03490ed
CO		 379 /*
380 * Does the new cr3 value map to physical memory? (Note, we
381 * catch an invalid cr3 even in real-mode, because it would
382 * cause trouble later on when we turn on paging anyway.)
383 *
384 * A real CPU would silently accept an invalid cr3 and would
385 * attempt to use it - with largely undefined (and often hard
386 * to debug) behavior on the guest side.
387 */
388 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 389 kvm_inject_gp(vcpu, 0);
a03490ed 390 else {
ad312c7c
ZX		 391 vcpu->arch.cr3 = cr3;
392 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 393 }
a03490ed 394}
2d3ad1f4 395EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 396
2d3ad1f4 397void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 398{
399 if (cr8 & CR8_RESERVED_BITS) {
400 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 401 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 402 return;
403 }
404 if (irqchip_in_kernel(vcpu->kvm))
405 kvm_lapic_set_tpr(vcpu, cr8);
406 else
ad312c7c 407 vcpu->arch.cr8 = cr8;
a03490ed 408}
2d3ad1f4 409EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 410
2d3ad1f4 411unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 412{
413 if (irqchip_in_kernel(vcpu->kvm))
414 return kvm_lapic_get_cr8(vcpu);
415 else
ad312c7c 416 return vcpu->arch.cr8;
a03490ed 417}
2d3ad1f4 418EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 419
043405e1
CO		 420/*
421 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
422 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
423 *
424 * This list is modified at module load time to reflect the
425 * capabilities of the host cpu.
426 */
427static u32 msrs_to_save[] = {
428 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
429 MSR_K6_STAR,
430#ifdef CONFIG_X86_64
431 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
432#endif
18068523 433 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 434 MSR_IA32_PERF_STATUS,
043405e1
CO		 435};
436
437static unsigned num_msrs_to_save;
438
439static u32 emulated_msrs[] = {
440 MSR_IA32_MISC_ENABLE,
441};
442
15c4a640
CO		 443static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
444{
f2b4b7dd 445 if (efer & efer_reserved_bits) {
15c4a640
CO		 446 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
447 efer);
c1a5d4f9 448 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 449 return;
450 }
451
452 if (is_paging(vcpu)
ad312c7c 453 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 454 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 455 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 456 return;
457 }
458
459 kvm_x86_ops->set_efer(vcpu, efer);
460
461 efer &= ~EFER_LMA;
ad312c7c 462 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 463
ad312c7c 464 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 465}
466
f2b4b7dd
JR		 467void kvm_enable_efer_bits(u64 mask)
468{
469 efer_reserved_bits &= ~mask;
470}
471EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
472
473
15c4a640
CO		 474/*
475 * Writes msr value into into the appropriate "register".
476 * Returns 0 on success, non-0 otherwise.
477 * Assumes vcpu_load() was already called.
478 */
479int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
480{
481 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
482}
483
313a3dc7
CO		 484/*
485 * Adapt set_msr() to msr_io()'s calling convention
486 */
487static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
488{
489 return kvm_set_msr(vcpu, index, *data);
490}
491
18068523
GOC		 492static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
493{
494 static int version;
50d0a0f9
GH		 495 struct pvclock_wall_clock wc;
496 struct timespec now, sys, boot;
18068523
GOC		 497
498 if (!wall_clock)
499 return;
500
501 version++;
502
18068523
GOC		 503 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
504
50d0a0f9
GH		 505 /*
506 * The guest calculates current wall clock time by adding
507 * system time (updated by kvm_write_guest_time below) to the
508 * wall clock specified here. guest system time equals host
509 * system time for us, thus we must fill in host boot time here.
510 */
511 now = current_kernel_time();
512 ktime_get_ts(&sys);
513 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
514
515 wc.sec = boot.tv_sec;
516 wc.nsec = boot.tv_nsec;
517 wc.version = version;
18068523
GOC		 518
519 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
520
521 version++;
522 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 523}
524
50d0a0f9
GH		 525static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
526{
527 uint32_t quotient, remainder;
528
529 /* Don't try to replace with do_div(), this one calculates
530 * "(dividend << 32) / divisor" */
531 __asm__ ( "divl %4"
532 : "=a" (quotient), "=d" (remainder)
533 : "0" (0), "1" (dividend), "r" (divisor) );
534 return quotient;
535}
536
537static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
538{
539 uint64_t nsecs = 1000000000LL;
540 int32_t shift = 0;
541 uint64_t tps64;
542 uint32_t tps32;
543
544 tps64 = tsc_khz * 1000LL;
545 while (tps64 > nsecs*2) {
546 tps64 >>= 1;
547 shift--;
548 }
549
550 tps32 = (uint32_t)tps64;
551 while (tps32 <= (uint32_t)nsecs) {
552 tps32 <<= 1;
553 shift++;
554 }
555
556 hv_clock->tsc_shift = shift;
557 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
558
559 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
560 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
561 hv_clock->tsc_to_system_mul);
562}
563
18068523
GOC		 564static void kvm_write_guest_time(struct kvm_vcpu *v)
565{
566 struct timespec ts;
567 unsigned long flags;
568 struct kvm_vcpu_arch *vcpu = &v->arch;
569 void *shared_kaddr;
570
571 if ((!vcpu->time_page))
572 return;
573
50d0a0f9
GH		 574 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
575 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
576 vcpu->hv_clock_tsc_khz = tsc_khz;
577 }
578
18068523
GOC		 579 /* Keep irq disabled to prevent changes to the clock */
580 local_irq_save(flags);
581 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
582 &vcpu->hv_clock.tsc_timestamp);
583 ktime_get_ts(&ts);
584 local_irq_restore(flags);
585
586 /* With all the info we got, fill in the values */
587
588 vcpu->hv_clock.system_time = ts.tv_nsec +
589 (NSEC_PER_SEC * (u64)ts.tv_sec);
590 /*
591 * The interface expects us to write an even number signaling that the
592 * update is finished. Since the guest won't see the intermediate
50d0a0f9 593 * state, we just increase by 2 at the end.
18068523 594 */
50d0a0f9 595 vcpu->hv_clock.version += 2;
18068523
GOC		 596
597 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
598
599 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 600 sizeof(vcpu->hv_clock));
18068523
GOC		 601
602 kunmap_atomic(shared_kaddr, KM_USER0);
603
604 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
605}
606
15c4a640
CO		 607
608int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
609{
610 switch (msr) {
15c4a640
CO		 611 case MSR_EFER:
612 set_efer(vcpu, data);
613 break;
15c4a640
CO		 614 case MSR_IA32_MC0_STATUS:
615 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 616 __func__, data);
15c4a640
CO		 617 break;
618 case MSR_IA32_MCG_STATUS:
619 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 620 __func__, data);
15c4a640 621 break;
c7ac679c
JR		 622 case MSR_IA32_MCG_CTL:
623 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 624 __func__, data);
c7ac679c 625 break;
15c4a640
CO		 626 case MSR_IA32_UCODE_REV:
627 case MSR_IA32_UCODE_WRITE:
628 case 0x200 ... 0x2ff: /* MTRRs */
629 break;
630 case MSR_IA32_APICBASE:
631 kvm_set_apic_base(vcpu, data);
632 break;
633 case MSR_IA32_MISC_ENABLE:
ad312c7c 634 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 635 break;
18068523
GOC		 636 case MSR_KVM_WALL_CLOCK:
637 vcpu->kvm->arch.wall_clock = data;
638 kvm_write_wall_clock(vcpu->kvm, data);
639 break;
640 case MSR_KVM_SYSTEM_TIME: {
641 if (vcpu->arch.time_page) {
642 kvm_release_page_dirty(vcpu->arch.time_page);
643 vcpu->arch.time_page = NULL;
644 }
645
646 vcpu->arch.time = data;
647
648 /* we verify if the enable bit is set... */
649 if (!(data & 1))
650 break;
651
652 /* ...but clean it before doing the actual write */
653 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
654
18068523 655 down_read(&current->mm->mmap_sem);
18068523
GOC		 656 vcpu->arch.time_page =
657 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 658 up_read(&current->mm->mmap_sem);
659
660 if (is_error_page(vcpu->arch.time_page)) {
661 kvm_release_page_clean(vcpu->arch.time_page);
662 vcpu->arch.time_page = NULL;
663 }
664
665 kvm_write_guest_time(vcpu);
666 break;
667 }
15c4a640 668 default:
565f1fbd 669 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 670 return 1;
671 }
672 return 0;
673}
674EXPORT_SYMBOL_GPL(kvm_set_msr_common);
675
676
677/*
678 * Reads an msr value (of 'msr_index') into 'pdata'.
679 * Returns 0 on success, non-0 otherwise.
680 * Assumes vcpu_load() was already called.
681 */
682int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
683{
684 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
685}
686
687int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
688{
689 u64 data;
690
691 switch (msr) {
692 case 0xc0010010: /* SYSCFG */
693 case 0xc0010015: /* HWCR */
694 case MSR_IA32_PLATFORM_ID:
695 case MSR_IA32_P5_MC_ADDR:
696 case MSR_IA32_P5_MC_TYPE:
697 case MSR_IA32_MC0_CTL:
698 case MSR_IA32_MCG_STATUS:
699 case MSR_IA32_MCG_CAP:
c7ac679c 700 case MSR_IA32_MCG_CTL:
15c4a640
CO		 701 case MSR_IA32_MC0_MISC:
702 case MSR_IA32_MC0_MISC+4:
703 case MSR_IA32_MC0_MISC+8:
704 case MSR_IA32_MC0_MISC+12:
705 case MSR_IA32_MC0_MISC+16:
706 case MSR_IA32_UCODE_REV:
15c4a640
CO		 707 case MSR_IA32_EBL_CR_POWERON:
708 /* MTRR registers */
709 case 0xfe:
710 case 0x200 ... 0x2ff:
711 data = 0;
712 break;
713 case 0xcd: /* fsb frequency */
714 data = 3;
715 break;
716 case MSR_IA32_APICBASE:
717 data = kvm_get_apic_base(vcpu);
718 break;
719 case MSR_IA32_MISC_ENABLE:
ad312c7c 720 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 721 break;
847f0ad8
AG		 722 case MSR_IA32_PERF_STATUS:
723 /* TSC increment by tick */
724 data = 1000ULL;
725 /* CPU multiplier */
726 data |= (((uint64_t)4ULL) << 40);
727 break;
15c4a640 728 case MSR_EFER:
ad312c7c 729 data = vcpu->arch.shadow_efer;
15c4a640 730 break;
18068523
GOC		 731 case MSR_KVM_WALL_CLOCK:
732 data = vcpu->kvm->arch.wall_clock;
733 break;
734 case MSR_KVM_SYSTEM_TIME:
735 data = vcpu->arch.time;
736 break;
15c4a640
CO		 737 default:
738 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
739 return 1;
740 }
741 *pdata = data;
742 return 0;
743}
744EXPORT_SYMBOL_GPL(kvm_get_msr_common);
745
313a3dc7
CO		 746/*
747 * Read or write a bunch of msrs. All parameters are kernel addresses.
748 *
749 * @return number of msrs set successfully.
750 */
751static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
752 struct kvm_msr_entry *entries,
753 int (*do_msr)(struct kvm_vcpu *vcpu,
754 unsigned index, u64 *data))
755{
756 int i;
757
758 vcpu_load(vcpu);
759
3200f405 760 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 761 for (i = 0; i < msrs->nmsrs; ++i)
762 if (do_msr(vcpu, entries[i].index, &entries[i].data))
763 break;
3200f405 764 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 765
766 vcpu_put(vcpu);
767
768 return i;
769}
770
771/*
772 * Read or write a bunch of msrs. Parameters are user addresses.
773 *
774 * @return number of msrs set successfully.
775 */
776static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
777 int (*do_msr)(struct kvm_vcpu *vcpu,
778 unsigned index, u64 *data),
779 int writeback)
780{
781 struct kvm_msrs msrs;
782 struct kvm_msr_entry *entries;
783 int r, n;
784 unsigned size;
785
786 r = -EFAULT;
787 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
788 goto out;
789
790 r = -E2BIG;
791 if (msrs.nmsrs >= MAX_IO_MSRS)
792 goto out;
793
794 r = -ENOMEM;
795 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
796 entries = vmalloc(size);
797 if (!entries)
798 goto out;
799
800 r = -EFAULT;
801 if (copy_from_user(entries, user_msrs->entries, size))
802 goto out_free;
803
804 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
805 if (r < 0)
806 goto out_free;
807
808 r = -EFAULT;
809 if (writeback && copy_to_user(user_msrs->entries, entries, size))
810 goto out_free;
811
812 r = n;
813
814out_free:
815 vfree(entries);
816out:
817 return r;
818}
819
018d00d2
ZX		 820int kvm_dev_ioctl_check_extension(long ext)
821{
822 int r;
823
824 switch (ext) {
825 case KVM_CAP_IRQCHIP:
826 case KVM_CAP_HLT:
827 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
828 case KVM_CAP_USER_MEMORY:
829 case KVM_CAP_SET_TSS_ADDR:
07716717 830 case KVM_CAP_EXT_CPUID:
18068523 831 case KVM_CAP_CLOCKSOURCE:
7837699f 832 case KVM_CAP_PIT:
a28e4f5a 833 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 834 case KVM_CAP_MP_STATE:
018d00d2
ZX		 835 r = 1;
836 break;
774ead3a
AK		 837 case KVM_CAP_VAPIC:
838 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
839 break;
f725230a
AK		 840 case KVM_CAP_NR_VCPUS:
841 r = KVM_MAX_VCPUS;
842 break;
a988b910
AK		 843 case KVM_CAP_NR_MEMSLOTS:
844 r = KVM_MEMORY_SLOTS;
845 break;
2f333bcb
MT		 846 case KVM_CAP_PV_MMU:
847 r = !tdp_enabled;
848 break;
018d00d2
ZX		 849 default:
850 r = 0;
851 break;
852 }
853 return r;
854
855}
856
043405e1
CO		 857long kvm_arch_dev_ioctl(struct file *filp,
858 unsigned int ioctl, unsigned long arg)
859{
860 void __user *argp = (void __user *)arg;
861 long r;
862
863 switch (ioctl) {
864 case KVM_GET_MSR_INDEX_LIST: {
865 struct kvm_msr_list __user *user_msr_list = argp;
866 struct kvm_msr_list msr_list;
867 unsigned n;
868
869 r = -EFAULT;
870 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
871 goto out;
872 n = msr_list.nmsrs;
873 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
874 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
875 goto out;
876 r = -E2BIG;
877 if (n < num_msrs_to_save)
878 goto out;
879 r = -EFAULT;
880 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
881 num_msrs_to_save * sizeof(u32)))
882 goto out;
883 if (copy_to_user(user_msr_list->indices
884 + num_msrs_to_save * sizeof(u32),
885 &emulated_msrs,
886 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
887 goto out;
888 r = 0;
889 break;
890 }
674eea0f
AK		 891 case KVM_GET_SUPPORTED_CPUID: {
892 struct kvm_cpuid2 __user *cpuid_arg = argp;
893 struct kvm_cpuid2 cpuid;
894
895 r = -EFAULT;
896 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
897 goto out;
898 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
899 cpuid_arg->entries);
900 if (r)
901 goto out;
902
903 r = -EFAULT;
904 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
905 goto out;
906 r = 0;
907 break;
908 }
043405e1
CO		 909 default:
910 r = -EINVAL;
911 }
912out:
913 return r;
914}
915
313a3dc7
CO		 916void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
917{
918 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 919 kvm_write_guest_time(vcpu);
313a3dc7
CO		 920}
921
922void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
923{
924 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 925 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 926}
927
07716717 928static int is_efer_nx(void)
313a3dc7
CO		 929{
930 u64 efer;
313a3dc7
CO		 931
932 rdmsrl(MSR_EFER, efer);
07716717
DK		 933 return efer & EFER_NX;
934}
935
936static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
937{
938 int i;
939 struct kvm_cpuid_entry2 *e, *entry;
940
313a3dc7 941 entry = NULL;
ad312c7c
ZX		 942 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
943 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 944 if (e->function == 0x80000001) {
945 entry = e;
946 break;
947 }
948 }
07716717 949 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 950 entry->edx &= ~(1 << 20);
951 printk(KERN_INFO "kvm: guest NX capability removed\n");
952 }
953}
954
07716717 955/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 956static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
957 struct kvm_cpuid *cpuid,
958 struct kvm_cpuid_entry __user *entries)
07716717
DK		 959{
960 int r, i;
961 struct kvm_cpuid_entry *cpuid_entries;
962
963 r = -E2BIG;
964 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
965 goto out;
966 r = -ENOMEM;
967 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
968 if (!cpuid_entries)
969 goto out;
970 r = -EFAULT;
971 if (copy_from_user(cpuid_entries, entries,
972 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
973 goto out_free;
974 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 975 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
976 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
977 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
978 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
979 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
980 vcpu->arch.cpuid_entries[i].index = 0;
981 vcpu->arch.cpuid_entries[i].flags = 0;
982 vcpu->arch.cpuid_entries[i].padding[0] = 0;
983 vcpu->arch.cpuid_entries[i].padding[1] = 0;
984 vcpu->arch.cpuid_entries[i].padding[2] = 0;
985 }
986 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 987 cpuid_fix_nx_cap(vcpu);
988 r = 0;
989
990out_free:
991 vfree(cpuid_entries);
992out:
993 return r;
994}
995
996static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
997 struct kvm_cpuid2 *cpuid,
998 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 999{
1000 int r;
1001
1002 r = -E2BIG;
1003 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1004 goto out;
1005 r = -EFAULT;
ad312c7c 1006 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1007 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1008 goto out;
ad312c7c 1009 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1010 return 0;
1011
1012out:
1013 return r;
1014}
1015
07716717
DK		 1016static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1017 struct kvm_cpuid2 *cpuid,
1018 struct kvm_cpuid_entry2 __user *entries)
1019{
1020 int r;
1021
1022 r = -E2BIG;
ad312c7c 1023 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1024 goto out;
1025 r = -EFAULT;
ad312c7c
ZX		 1026 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1027 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1028 goto out;
1029 return 0;
1030
1031out:
ad312c7c 1032 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1033 return r;
1034}
1035
1036static inline u32 bit(int bitno)
1037{
1038 return 1 << (bitno & 31);
1039}
1040
1041static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1042 u32 index)
1043{
1044 entry->function = function;
1045 entry->index = index;
1046 cpuid_count(entry->function, entry->index,
1047 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1048 entry->flags = 0;
1049}
1050
1051static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1052 u32 index, int *nent, int maxnent)
1053{
1054 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1055 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1056 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1057 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1058 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1059 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1060 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1061 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1062 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1063 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1064 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1065 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1066 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1067 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1068 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1069 bit(X86_FEATURE_PGE) |
1070 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1071 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1072 bit(X86_FEATURE_SYSCALL) |
1073 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1074#ifdef CONFIG_X86_64
1075 bit(X86_FEATURE_LM) |
1076#endif
1077 bit(X86_FEATURE_MMXEXT) |
1078 bit(X86_FEATURE_3DNOWEXT) |
1079 bit(X86_FEATURE_3DNOW);
1080 const u32 kvm_supported_word3_x86_features =
1081 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1082 const u32 kvm_supported_word6_x86_features =
1083 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1084
1085 /* all func 2 cpuid_count() should be called on the same cpu */
1086 get_cpu();
1087 do_cpuid_1_ent(entry, function, index);
1088 ++*nent;
1089
1090 switch (function) {
1091 case 0:
1092 entry->eax = min(entry->eax, (u32)0xb);
1093 break;
1094 case 1:
1095 entry->edx &= kvm_supported_word0_x86_features;
1096 entry->ecx &= kvm_supported_word3_x86_features;
1097 break;
1098 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1099 * may return different values. This forces us to get_cpu() before
1100 * issuing the first command, and also to emulate this annoying behavior
1101 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1102 case 2: {
1103 int t, times = entry->eax & 0xff;
1104
1105 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1106 for (t = 1; t < times && *nent < maxnent; ++t) {
1107 do_cpuid_1_ent(&entry[t], function, 0);
1108 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1109 ++*nent;
1110 }
1111 break;
1112 }
1113 /* function 4 and 0xb have additional index. */
1114 case 4: {
14af3f3c 1115 int i, cache_type;
07716717
DK		 1116
1117 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1118 /* read more entries until cache_type is zero */
14af3f3c
HH		 1119 for (i = 1; *nent < maxnent; ++i) {
1120 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1121 if (!cache_type)
1122 break;
14af3f3c
HH		 1123 do_cpuid_1_ent(&entry[i], function, i);
1124 entry[i].flags |=
07716717
DK		 1125 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1126 ++*nent;
1127 }
1128 break;
1129 }
1130 case 0xb: {
14af3f3c 1131 int i, level_type;
07716717
DK		 1132
1133 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1134 /* read more entries until level_type is zero */
14af3f3c
HH		 1135 for (i = 1; *nent < maxnent; ++i) {
1136 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1137 if (!level_type)
1138 break;
14af3f3c
HH		 1139 do_cpuid_1_ent(&entry[i], function, i);
1140 entry[i].flags |=
07716717
DK		 1141 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1142 ++*nent;
1143 }
1144 break;
1145 }
1146 case 0x80000000:
1147 entry->eax = min(entry->eax, 0x8000001a);
1148 break;
1149 case 0x80000001:
1150 entry->edx &= kvm_supported_word1_x86_features;
1151 entry->ecx &= kvm_supported_word6_x86_features;
1152 break;
1153 }
1154 put_cpu();
1155}
1156
674eea0f 1157static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1158 struct kvm_cpuid_entry2 __user *entries)
1159{
1160 struct kvm_cpuid_entry2 *cpuid_entries;
1161 int limit, nent = 0, r = -E2BIG;
1162 u32 func;
1163
1164 if (cpuid->nent < 1)
1165 goto out;
1166 r = -ENOMEM;
1167 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1168 if (!cpuid_entries)
1169 goto out;
1170
1171 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1172 limit = cpuid_entries[0].eax;
1173 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1174 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1175 &nent, cpuid->nent);
1176 r = -E2BIG;
1177 if (nent >= cpuid->nent)
1178 goto out_free;
1179
1180 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1181 limit = cpuid_entries[nent - 1].eax;
1182 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1183 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1184 &nent, cpuid->nent);
1185 r = -EFAULT;
1186 if (copy_to_user(entries, cpuid_entries,
1187 nent * sizeof(struct kvm_cpuid_entry2)))
1188 goto out_free;
1189 cpuid->nent = nent;
1190 r = 0;
1191
1192out_free:
1193 vfree(cpuid_entries);
1194out:
1195 return r;
1196}
1197
313a3dc7
CO		 1198static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1199 struct kvm_lapic_state *s)
1200{
1201 vcpu_load(vcpu);
ad312c7c 1202 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1203 vcpu_put(vcpu);
1204
1205 return 0;
1206}
1207
1208static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1209 struct kvm_lapic_state *s)
1210{
1211 vcpu_load(vcpu);
ad312c7c 1212 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1213 kvm_apic_post_state_restore(vcpu);
1214 vcpu_put(vcpu);
1215
1216 return 0;
1217}
1218
f77bc6a4
ZX		 1219static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1220 struct kvm_interrupt *irq)
1221{
1222 if (irq->irq < 0 || irq->irq >= 256)
1223 return -EINVAL;
1224 if (irqchip_in_kernel(vcpu->kvm))
1225 return -ENXIO;
1226 vcpu_load(vcpu);
1227
ad312c7c
ZX		 1228 set_bit(irq->irq, vcpu->arch.irq_pending);
1229 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1230
1231 vcpu_put(vcpu);
1232
1233 return 0;
1234}
1235
b209749f
AK		 1236static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1237 struct kvm_tpr_access_ctl *tac)
1238{
1239 if (tac->flags)
1240 return -EINVAL;
1241 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1242 return 0;
1243}
1244
313a3dc7
CO		 1245long kvm_arch_vcpu_ioctl(struct file *filp,
1246 unsigned int ioctl, unsigned long arg)
1247{
1248 struct kvm_vcpu *vcpu = filp->private_data;
1249 void __user *argp = (void __user *)arg;
1250 int r;
1251
1252 switch (ioctl) {
1253 case KVM_GET_LAPIC: {
1254 struct kvm_lapic_state lapic;
1255
1256 memset(&lapic, 0, sizeof lapic);
1257 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1258 if (r)
1259 goto out;
1260 r = -EFAULT;
1261 if (copy_to_user(argp, &lapic, sizeof lapic))
1262 goto out;
1263 r = 0;
1264 break;
1265 }
1266 case KVM_SET_LAPIC: {
1267 struct kvm_lapic_state lapic;
1268
1269 r = -EFAULT;
1270 if (copy_from_user(&lapic, argp, sizeof lapic))
1271 goto out;
1272 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1273 if (r)
1274 goto out;
1275 r = 0;
1276 break;
1277 }
f77bc6a4
ZX		 1278 case KVM_INTERRUPT: {
1279 struct kvm_interrupt irq;
1280
1281 r = -EFAULT;
1282 if (copy_from_user(&irq, argp, sizeof irq))
1283 goto out;
1284 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1285 if (r)
1286 goto out;
1287 r = 0;
1288 break;
1289 }
313a3dc7
CO		 1290 case KVM_SET_CPUID: {
1291 struct kvm_cpuid __user *cpuid_arg = argp;
1292 struct kvm_cpuid cpuid;
1293
1294 r = -EFAULT;
1295 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1296 goto out;
1297 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1298 if (r)
1299 goto out;
1300 break;
1301 }
07716717
DK		 1302 case KVM_SET_CPUID2: {
1303 struct kvm_cpuid2 __user *cpuid_arg = argp;
1304 struct kvm_cpuid2 cpuid;
1305
1306 r = -EFAULT;
1307 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1308 goto out;
1309 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1310 cpuid_arg->entries);
1311 if (r)
1312 goto out;
1313 break;
1314 }
1315 case KVM_GET_CPUID2: {
1316 struct kvm_cpuid2 __user *cpuid_arg = argp;
1317 struct kvm_cpuid2 cpuid;
1318
1319 r = -EFAULT;
1320 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1321 goto out;
1322 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1323 cpuid_arg->entries);
1324 if (r)
1325 goto out;
1326 r = -EFAULT;
1327 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1328 goto out;
1329 r = 0;
1330 break;
1331 }
313a3dc7
CO		 1332 case KVM_GET_MSRS:
1333 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1334 break;
1335 case KVM_SET_MSRS:
1336 r = msr_io(vcpu, argp, do_set_msr, 0);
1337 break;
b209749f
AK		 1338 case KVM_TPR_ACCESS_REPORTING: {
1339 struct kvm_tpr_access_ctl tac;
1340
1341 r = -EFAULT;
1342 if (copy_from_user(&tac, argp, sizeof tac))
1343 goto out;
1344 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1345 if (r)
1346 goto out;
1347 r = -EFAULT;
1348 if (copy_to_user(argp, &tac, sizeof tac))
1349 goto out;
1350 r = 0;
1351 break;
1352 };
b93463aa
AK		 1353 case KVM_SET_VAPIC_ADDR: {
1354 struct kvm_vapic_addr va;
1355
1356 r = -EINVAL;
1357 if (!irqchip_in_kernel(vcpu->kvm))
1358 goto out;
1359 r = -EFAULT;
1360 if (copy_from_user(&va, argp, sizeof va))
1361 goto out;
1362 r = 0;
1363 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1364 break;
1365 }
313a3dc7
CO		 1366 default:
1367 r = -EINVAL;
1368 }
1369out:
1370 return r;
1371}
1372
1fe779f8
CO		 1373static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1374{
1375 int ret;
1376
1377 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1378 return -1;
1379 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1380 return ret;
1381}
1382
1383static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1384 u32 kvm_nr_mmu_pages)
1385{
1386 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1387 return -EINVAL;
1388
72dc67a6 1389 down_write(&kvm->slots_lock);
1fe779f8
CO		 1390
1391 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1392 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1393
72dc67a6 1394 up_write(&kvm->slots_lock);
1fe779f8
CO		 1395 return 0;
1396}
1397
1398static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1399{
f05e70ac 1400 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1401}
1402
e9f85cde
ZX		 1403gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1404{
1405 int i;
1406 struct kvm_mem_alias *alias;
1407
d69fb81f
ZX		 1408 for (i = 0; i < kvm->arch.naliases; ++i) {
1409 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1410 if (gfn >= alias->base_gfn
1411 && gfn < alias->base_gfn + alias->npages)
1412 return alias->target_gfn + gfn - alias->base_gfn;
1413 }
1414 return gfn;
1415}
1416
1fe779f8
CO		 1417/*
1418 * Set a new alias region. Aliases map a portion of physical memory into
1419 * another portion. This is useful for memory windows, for example the PC
1420 * VGA region.
1421 */
1422static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1423 struct kvm_memory_alias *alias)
1424{
1425 int r, n;
1426 struct kvm_mem_alias *p;
1427
1428 r = -EINVAL;
1429 /* General sanity checks */
1430 if (alias->memory_size & (PAGE_SIZE - 1))
1431 goto out;
1432 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1433 goto out;
1434 if (alias->slot >= KVM_ALIAS_SLOTS)
1435 goto out;
1436 if (alias->guest_phys_addr + alias->memory_size
1437 < alias->guest_phys_addr)
1438 goto out;
1439 if (alias->target_phys_addr + alias->memory_size
1440 < alias->target_phys_addr)
1441 goto out;
1442
72dc67a6 1443 down_write(&kvm->slots_lock);
1fe779f8 1444
d69fb81f 1445 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1446 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1447 p->npages = alias->memory_size >> PAGE_SHIFT;
1448 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1449
1450 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1451 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1452 break;
d69fb81f 1453 kvm->arch.naliases = n;
1fe779f8
CO		 1454
1455 kvm_mmu_zap_all(kvm);
1456
72dc67a6 1457 up_write(&kvm->slots_lock);
1fe779f8
CO		 1458
1459 return 0;
1460
1461out:
1462 return r;
1463}
1464
1465static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1466{
1467 int r;
1468
1469 r = 0;
1470 switch (chip->chip_id) {
1471 case KVM_IRQCHIP_PIC_MASTER:
1472 memcpy(&chip->chip.pic,
1473 &pic_irqchip(kvm)->pics[0],
1474 sizeof(struct kvm_pic_state));
1475 break;
1476 case KVM_IRQCHIP_PIC_SLAVE:
1477 memcpy(&chip->chip.pic,
1478 &pic_irqchip(kvm)->pics[1],
1479 sizeof(struct kvm_pic_state));
1480 break;
1481 case KVM_IRQCHIP_IOAPIC:
1482 memcpy(&chip->chip.ioapic,
1483 ioapic_irqchip(kvm),
1484 sizeof(struct kvm_ioapic_state));
1485 break;
1486 default:
1487 r = -EINVAL;
1488 break;
1489 }
1490 return r;
1491}
1492
1493static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1494{
1495 int r;
1496
1497 r = 0;
1498 switch (chip->chip_id) {
1499 case KVM_IRQCHIP_PIC_MASTER:
1500 memcpy(&pic_irqchip(kvm)->pics[0],
1501 &chip->chip.pic,
1502 sizeof(struct kvm_pic_state));
1503 break;
1504 case KVM_IRQCHIP_PIC_SLAVE:
1505 memcpy(&pic_irqchip(kvm)->pics[1],
1506 &chip->chip.pic,
1507 sizeof(struct kvm_pic_state));
1508 break;
1509 case KVM_IRQCHIP_IOAPIC:
1510 memcpy(ioapic_irqchip(kvm),
1511 &chip->chip.ioapic,
1512 sizeof(struct kvm_ioapic_state));
1513 break;
1514 default:
1515 r = -EINVAL;
1516 break;
1517 }
1518 kvm_pic_update_irq(pic_irqchip(kvm));
1519 return r;
1520}
1521
e0f63cb9
SY		 1522static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1523{
1524 int r = 0;
1525
1526 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1527 return r;
1528}
1529
1530static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1531{
1532 int r = 0;
1533
1534 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1535 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1536 return r;
1537}
1538
5bb064dc
ZX		 1539/*
1540 * Get (and clear) the dirty memory log for a memory slot.
1541 */
1542int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1543 struct kvm_dirty_log *log)
1544{
1545 int r;
1546 int n;
1547 struct kvm_memory_slot *memslot;
1548 int is_dirty = 0;
1549
72dc67a6 1550 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1551
1552 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1553 if (r)
1554 goto out;
1555
1556 /* If nothing is dirty, don't bother messing with page tables. */
1557 if (is_dirty) {
1558 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1559 kvm_flush_remote_tlbs(kvm);
1560 memslot = &kvm->memslots[log->slot];
1561 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1562 memset(memslot->dirty_bitmap, 0, n);
1563 }
1564 r = 0;
1565out:
72dc67a6 1566 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1567 return r;
1568}
1569
1fe779f8
CO		 1570long kvm_arch_vm_ioctl(struct file *filp,
1571 unsigned int ioctl, unsigned long arg)
1572{
1573 struct kvm *kvm = filp->private_data;
1574 void __user *argp = (void __user *)arg;
1575 int r = -EINVAL;
1576
1577 switch (ioctl) {
1578 case KVM_SET_TSS_ADDR:
1579 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1580 if (r < 0)
1581 goto out;
1582 break;
1583 case KVM_SET_MEMORY_REGION: {
1584 struct kvm_memory_region kvm_mem;
1585 struct kvm_userspace_memory_region kvm_userspace_mem;
1586
1587 r = -EFAULT;
1588 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1589 goto out;
1590 kvm_userspace_mem.slot = kvm_mem.slot;
1591 kvm_userspace_mem.flags = kvm_mem.flags;
1592 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1593 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1594 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1595 if (r)
1596 goto out;
1597 break;
1598 }
1599 case KVM_SET_NR_MMU_PAGES:
1600 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1601 if (r)
1602 goto out;
1603 break;
1604 case KVM_GET_NR_MMU_PAGES:
1605 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1606 break;
1607 case KVM_SET_MEMORY_ALIAS: {
1608 struct kvm_memory_alias alias;
1609
1610 r = -EFAULT;
1611 if (copy_from_user(&alias, argp, sizeof alias))
1612 goto out;
1613 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1614 if (r)
1615 goto out;
1616 break;
1617 }
1618 case KVM_CREATE_IRQCHIP:
1619 r = -ENOMEM;
d7deeeb0
ZX		 1620 kvm->arch.vpic = kvm_create_pic(kvm);
1621 if (kvm->arch.vpic) {
1fe779f8
CO		 1622 r = kvm_ioapic_init(kvm);
1623 if (r) {
d7deeeb0
ZX		 1624 kfree(kvm->arch.vpic);
1625 kvm->arch.vpic = NULL;
1fe779f8
CO		 1626 goto out;
1627 }
1628 } else
1629 goto out;
1630 break;
7837699f
SY		 1631 case KVM_CREATE_PIT:
1632 r = -ENOMEM;
1633 kvm->arch.vpit = kvm_create_pit(kvm);
1634 if (kvm->arch.vpit)
1635 r = 0;
1636 break;
1fe779f8
CO		 1637 case KVM_IRQ_LINE: {
1638 struct kvm_irq_level irq_event;
1639
1640 r = -EFAULT;
1641 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1642 goto out;
1643 if (irqchip_in_kernel(kvm)) {
1644 mutex_lock(&kvm->lock);
1645 if (irq_event.irq < 16)
1646 kvm_pic_set_irq(pic_irqchip(kvm),
1647 irq_event.irq,
1648 irq_event.level);
d7deeeb0 1649 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1650 irq_event.irq,
1651 irq_event.level);
1652 mutex_unlock(&kvm->lock);
1653 r = 0;
1654 }
1655 break;
1656 }
1657 case KVM_GET_IRQCHIP: {
1658 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1659 struct kvm_irqchip chip;
1660
1661 r = -EFAULT;
1662 if (copy_from_user(&chip, argp, sizeof chip))
1663 goto out;
1664 r = -ENXIO;
1665 if (!irqchip_in_kernel(kvm))
1666 goto out;
1667 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1668 if (r)
1669 goto out;
1670 r = -EFAULT;
1671 if (copy_to_user(argp, &chip, sizeof chip))
1672 goto out;
1673 r = 0;
1674 break;
1675 }
1676 case KVM_SET_IRQCHIP: {
1677 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1678 struct kvm_irqchip chip;
1679
1680 r = -EFAULT;
1681 if (copy_from_user(&chip, argp, sizeof chip))
1682 goto out;
1683 r = -ENXIO;
1684 if (!irqchip_in_kernel(kvm))
1685 goto out;
1686 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1687 if (r)
1688 goto out;
1689 r = 0;
1690 break;
1691 }
e0f63cb9
SY		 1692 case KVM_GET_PIT: {
1693 struct kvm_pit_state ps;
1694 r = -EFAULT;
1695 if (copy_from_user(&ps, argp, sizeof ps))
1696 goto out;
1697 r = -ENXIO;
1698 if (!kvm->arch.vpit)
1699 goto out;
1700 r = kvm_vm_ioctl_get_pit(kvm, &ps);
1701 if (r)
1702 goto out;
1703 r = -EFAULT;
1704 if (copy_to_user(argp, &ps, sizeof ps))
1705 goto out;
1706 r = 0;
1707 break;
1708 }
1709 case KVM_SET_PIT: {
1710 struct kvm_pit_state ps;
1711 r = -EFAULT;
1712 if (copy_from_user(&ps, argp, sizeof ps))
1713 goto out;
1714 r = -ENXIO;
1715 if (!kvm->arch.vpit)
1716 goto out;
1717 r = kvm_vm_ioctl_set_pit(kvm, &ps);
1718 if (r)
1719 goto out;
1720 r = 0;
1721 break;
1722 }
1fe779f8
CO		 1723 default:
1724 ;
1725 }
1726out:
1727 return r;
1728}
1729
a16b043c 1730static void kvm_init_msr_list(void)
043405e1
CO		 1731{
1732 u32 dummy[2];
1733 unsigned i, j;
1734
1735 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1736 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1737 continue;
1738 if (j < i)
1739 msrs_to_save[j] = msrs_to_save[i];
1740 j++;
1741 }
1742 num_msrs_to_save = j;
1743}
1744
bbd9b64e
CO		 1745/*
1746 * Only apic need an MMIO device hook, so shortcut now..
1747 */
1748static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
1749 gpa_t addr)
1750{
1751 struct kvm_io_device *dev;
1752
ad312c7c
ZX		 1753 if (vcpu->arch.apic) {
1754 dev = &vcpu->arch.apic->dev;
bbd9b64e
CO		 1755 if (dev->in_range(dev, addr))
1756 return dev;
1757 }
1758 return NULL;
1759}
1760
1761
1762static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
1763 gpa_t addr)
1764{
1765 struct kvm_io_device *dev;
1766
1767 dev = vcpu_find_pervcpu_dev(vcpu, addr);
1768 if (dev == NULL)
1769 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr);
1770 return dev;
1771}
1772
1773int emulator_read_std(unsigned long addr,
1774 void *val,
1775 unsigned int bytes,
1776 struct kvm_vcpu *vcpu)
1777{
1778 void *data = val;
10589a46 1779 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1780
1781 while (bytes) {
ad312c7c 1782 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1783 unsigned offset = addr & (PAGE_SIZE-1);
1784 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1785 int ret;
1786
10589a46
MT		 1787 if (gpa == UNMAPPED_GVA) {
1788 r = X86EMUL_PROPAGATE_FAULT;
1789 goto out;
1790 }
bbd9b64e 1791 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1792 if (ret < 0) {
1793 r = X86EMUL_UNHANDLEABLE;
1794 goto out;
1795 }
bbd9b64e
CO		 1796
1797 bytes -= tocopy;
1798 data += tocopy;
1799 addr += tocopy;
1800 }
10589a46 1801out:
10589a46 1802 return r;
bbd9b64e
CO		 1803}
1804EXPORT_SYMBOL_GPL(emulator_read_std);
1805
bbd9b64e
CO		 1806static int emulator_read_emulated(unsigned long addr,
1807 void *val,
1808 unsigned int bytes,
1809 struct kvm_vcpu *vcpu)
1810{
1811 struct kvm_io_device *mmio_dev;
1812 gpa_t gpa;
1813
1814 if (vcpu->mmio_read_completed) {
1815 memcpy(val, vcpu->mmio_data, bytes);
1816 vcpu->mmio_read_completed = 0;
1817 return X86EMUL_CONTINUE;
1818 }
1819
ad312c7c 1820 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1821
1822 /* For APIC access vmexit */
1823 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1824 goto mmio;
1825
1826 if (emulator_read_std(addr, val, bytes, vcpu)
1827 == X86EMUL_CONTINUE)
1828 return X86EMUL_CONTINUE;
1829 if (gpa == UNMAPPED_GVA)
1830 return X86EMUL_PROPAGATE_FAULT;
1831
1832mmio:
1833 /*
1834 * Is this MMIO handled locally?
1835 */
10589a46 1836 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1837 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1838 if (mmio_dev) {
1839 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1840 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1841 return X86EMUL_CONTINUE;
1842 }
10589a46 1843 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1844
1845 vcpu->mmio_needed = 1;
1846 vcpu->mmio_phys_addr = gpa;
1847 vcpu->mmio_size = bytes;
1848 vcpu->mmio_is_write = 0;
1849
1850 return X86EMUL_UNHANDLEABLE;
1851}
1852
3200f405 1853int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 1854 const void *val, int bytes)
bbd9b64e
CO		 1855{
1856 int ret;
1857
1858 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 1859 if (ret < 0)
bbd9b64e
CO		 1860 return 0;
1861 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
1862 return 1;
1863}
1864
1865static int emulator_write_emulated_onepage(unsigned long addr,
1866 const void *val,
1867 unsigned int bytes,
1868 struct kvm_vcpu *vcpu)
1869{
1870 struct kvm_io_device *mmio_dev;
10589a46
MT		 1871 gpa_t gpa;
1872
10589a46 1873 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1874
1875 if (gpa == UNMAPPED_GVA) {
c3c91fee 1876 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1877 return X86EMUL_PROPAGATE_FAULT;
1878 }
1879
1880 /* For APIC access vmexit */
1881 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1882 goto mmio;
1883
1884 if (emulator_write_phys(vcpu, gpa, val, bytes))
1885 return X86EMUL_CONTINUE;
1886
1887mmio:
1888 /*
1889 * Is this MMIO handled locally?
1890 */
10589a46 1891 mutex_lock(&vcpu->kvm->lock);
bbd9b64e
CO		 1892 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa);
1893 if (mmio_dev) {
1894 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1895 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1896 return X86EMUL_CONTINUE;
1897 }
10589a46 1898 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1899
1900 vcpu->mmio_needed = 1;
1901 vcpu->mmio_phys_addr = gpa;
1902 vcpu->mmio_size = bytes;
1903 vcpu->mmio_is_write = 1;
1904 memcpy(vcpu->mmio_data, val, bytes);
1905
1906 return X86EMUL_CONTINUE;
1907}
1908
1909int emulator_write_emulated(unsigned long addr,
1910 const void *val,
1911 unsigned int bytes,
1912 struct kvm_vcpu *vcpu)
1913{
1914 /* Crossing a page boundary? */
1915 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1916 int rc, now;
1917
1918 now = -addr & ~PAGE_MASK;
1919 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
1920 if (rc != X86EMUL_CONTINUE)
1921 return rc;
1922 addr += now;
1923 val += now;
1924 bytes -= now;
1925 }
1926 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
1927}
1928EXPORT_SYMBOL_GPL(emulator_write_emulated);
1929
1930static int emulator_cmpxchg_emulated(unsigned long addr,
1931 const void *old,
1932 const void *new,
1933 unsigned int bytes,
1934 struct kvm_vcpu *vcpu)
1935{
1936 static int reported;
1937
1938 if (!reported) {
1939 reported = 1;
1940 printk(KERN_WARNING "kvm: emulating exchange as write\n");
1941 }
2bacc55c
MT		 1942#ifndef CONFIG_X86_64
1943 /* guests cmpxchg8b have to be emulated atomically */
1944 if (bytes == 8) {
10589a46 1945 gpa_t gpa;
2bacc55c 1946 struct page *page;
c0b49b0d 1947 char *kaddr;
2bacc55c
MT		 1948 u64 val;
1949
10589a46
MT		 1950 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
1951
2bacc55c
MT		 1952 if (gpa == UNMAPPED_GVA ||
1953 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1954 goto emul_write;
1955
1956 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
1957 goto emul_write;
1958
1959 val = *(u64 *)new;
72dc67a6
IE		 1960
1961 down_read(&current->mm->mmap_sem);
2bacc55c 1962 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1963 up_read(&current->mm->mmap_sem);
1964
c0b49b0d
AM		 1965 kaddr = kmap_atomic(page, KM_USER0);
1966 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
1967 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 1968 kvm_release_page_dirty(page);
1969 }
3200f405 1970emul_write:
2bacc55c
MT		 1971#endif
1972
bbd9b64e
CO		 1973 return emulator_write_emulated(addr, new, bytes, vcpu);
1974}
1975
1976static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
1977{
1978 return kvm_x86_ops->get_segment_base(vcpu, seg);
1979}
1980
1981int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
1982{
1983 return X86EMUL_CONTINUE;
1984}
1985
1986int emulate_clts(struct kvm_vcpu *vcpu)
1987{
54e445ca 1988 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 1989 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 1990 return X86EMUL_CONTINUE;
1991}
1992
1993int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
1994{
1995 struct kvm_vcpu *vcpu = ctxt->vcpu;
1996
1997 switch (dr) {
1998 case 0 ... 3:
1999 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2000 return X86EMUL_CONTINUE;
2001 default:
b8688d51 2002 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2003 return X86EMUL_UNHANDLEABLE;
2004 }
2005}
2006
2007int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2008{
2009 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2010 int exception;
2011
2012 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2013 if (exception) {
2014 /* FIXME: better handling */
2015 return X86EMUL_UNHANDLEABLE;
2016 }
2017 return X86EMUL_CONTINUE;
2018}
2019
2020void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2021{
2022 static int reported;
2023 u8 opcodes[4];
ad312c7c 2024 unsigned long rip = vcpu->arch.rip;
bbd9b64e
CO		 2025 unsigned long rip_linear;
2026
2027 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2028
2029 if (reported)
2030 return;
2031
2032 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2033
2034 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2035 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2036 reported = 1;
2037}
2038EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2039
14af3f3c 2040static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2041 .read_std = emulator_read_std,
bbd9b64e
CO		 2042 .read_emulated = emulator_read_emulated,
2043 .write_emulated = emulator_write_emulated,
2044 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2045};
2046
2047int emulate_instruction(struct kvm_vcpu *vcpu,
2048 struct kvm_run *run,
2049 unsigned long cr2,
2050 u16 error_code,
571008da 2051 int emulation_type)
bbd9b64e
CO		 2052{
2053 int r;
571008da 2054 struct decode_cache *c;
bbd9b64e 2055
ad312c7c 2056 vcpu->arch.mmio_fault_cr2 = cr2;
bbd9b64e
CO		 2057 kvm_x86_ops->cache_regs(vcpu);
2058
2059 vcpu->mmio_is_write = 0;
ad312c7c 2060 vcpu->arch.pio.string = 0;
bbd9b64e 2061
571008da 2062 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2063 int cs_db, cs_l;
2064 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2065
ad312c7c
ZX		 2066 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2067 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2068 vcpu->arch.emulate_ctxt.mode =
2069 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2070 ? X86EMUL_MODE_REAL : cs_l
2071 ? X86EMUL_MODE_PROT64 : cs_db
2072 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2073
ad312c7c
ZX		 2074 if (vcpu->arch.emulate_ctxt.mode == X86EMUL_MODE_PROT64) {
2075 vcpu->arch.emulate_ctxt.cs_base = 0;
2076 vcpu->arch.emulate_ctxt.ds_base = 0;
2077 vcpu->arch.emulate_ctxt.es_base = 0;
2078 vcpu->arch.emulate_ctxt.ss_base = 0;
bbd9b64e 2079 } else {
ad312c7c 2080 vcpu->arch.emulate_ctxt.cs_base =
bbd9b64e 2081 get_segment_base(vcpu, VCPU_SREG_CS);
ad312c7c 2082 vcpu->arch.emulate_ctxt.ds_base =
bbd9b64e 2083 get_segment_base(vcpu, VCPU_SREG_DS);
ad312c7c 2084 vcpu->arch.emulate_ctxt.es_base =
bbd9b64e 2085 get_segment_base(vcpu, VCPU_SREG_ES);
ad312c7c 2086 vcpu->arch.emulate_ctxt.ss_base =
bbd9b64e
CO		 2087 get_segment_base(vcpu, VCPU_SREG_SS);
2088 }
2089
ad312c7c 2090 vcpu->arch.emulate_ctxt.gs_base =
bbd9b64e 2091 get_segment_base(vcpu, VCPU_SREG_GS);
ad312c7c 2092 vcpu->arch.emulate_ctxt.fs_base =
bbd9b64e
CO		 2093 get_segment_base(vcpu, VCPU_SREG_FS);
2094
ad312c7c 2095 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2096
2097 /* Reject the instructions other than VMCALL/VMMCALL when
2098 * try to emulate invalid opcode */
2099 c = &vcpu->arch.emulate_ctxt.decode;
2100 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2101 (!(c->twobyte && c->b == 0x01 &&
2102 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2103 c->modrm_mod == 3 && c->modrm_rm == 1)))
2104 return EMULATE_FAIL;
2105
f2b5756b 2106 ++vcpu->stat.insn_emulation;
bbd9b64e 2107 if (r) {
f2b5756b 2108 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2109 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2110 return EMULATE_DONE;
2111 return EMULATE_FAIL;
2112 }
2113 }
2114
ad312c7c 2115 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2116
ad312c7c 2117 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2118 return EMULATE_DO_MMIO;
2119
2120 if ((r || vcpu->mmio_is_write) && run) {
2121 run->exit_reason = KVM_EXIT_MMIO;
2122 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2123 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2124 run->mmio.len = vcpu->mmio_size;
2125 run->mmio.is_write = vcpu->mmio_is_write;
2126 }
2127
2128 if (r) {
2129 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2130 return EMULATE_DONE;
2131 if (!vcpu->mmio_needed) {
2132 kvm_report_emulation_failure(vcpu, "mmio");
2133 return EMULATE_FAIL;
2134 }
2135 return EMULATE_DO_MMIO;
2136 }
2137
2138 kvm_x86_ops->decache_regs(vcpu);
ad312c7c 2139 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2140
2141 if (vcpu->mmio_is_write) {
2142 vcpu->mmio_needed = 0;
2143 return EMULATE_DO_MMIO;
2144 }
2145
2146 return EMULATE_DONE;
2147}
2148EXPORT_SYMBOL_GPL(emulate_instruction);
2149
de7d789a
CO		 2150static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2151{
2152 int i;
2153
ad312c7c
ZX		 2154 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2155 if (vcpu->arch.pio.guest_pages[i]) {
2156 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2157 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2158 }
2159}
2160
2161static int pio_copy_data(struct kvm_vcpu *vcpu)
2162{
ad312c7c 2163 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2164 void *q;
2165 unsigned bytes;
ad312c7c 2166 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2167
ad312c7c 2168 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2169 PAGE_KERNEL);
2170 if (!q) {
2171 free_pio_guest_pages(vcpu);
2172 return -ENOMEM;
2173 }
ad312c7c
ZX		 2174 q += vcpu->arch.pio.guest_page_offset;
2175 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2176 if (vcpu->arch.pio.in)
de7d789a
CO		 2177 memcpy(q, p, bytes);
2178 else
2179 memcpy(p, q, bytes);
ad312c7c 2180 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2181 vunmap(q);
2182 free_pio_guest_pages(vcpu);
2183 return 0;
2184}
2185
2186int complete_pio(struct kvm_vcpu *vcpu)
2187{
ad312c7c 2188 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2189 long delta;
2190 int r;
2191
2192 kvm_x86_ops->cache_regs(vcpu);
2193
2194 if (!io->string) {
2195 if (io->in)
ad312c7c 2196 memcpy(&vcpu->arch.regs[VCPU_REGS_RAX], vcpu->arch.pio_data,
de7d789a
CO		 2197 io->size);
2198 } else {
2199 if (io->in) {
2200 r = pio_copy_data(vcpu);
2201 if (r) {
2202 kvm_x86_ops->cache_regs(vcpu);
2203 return r;
2204 }
2205 }
2206
2207 delta = 1;
2208 if (io->rep) {
2209 delta *= io->cur_count;
2210 /*
2211 * The size of the register should really depend on
2212 * current address size.
2213 */
ad312c7c 2214 vcpu->arch.regs[VCPU_REGS_RCX] -= delta;
de7d789a
CO		 2215 }
2216 if (io->down)
2217 delta = -delta;
2218 delta *= io->size;
2219 if (io->in)
ad312c7c 2220 vcpu->arch.regs[VCPU_REGS_RDI] += delta;
de7d789a 2221 else
ad312c7c 2222 vcpu->arch.regs[VCPU_REGS_RSI] += delta;
de7d789a
CO		 2223 }
2224
2225 kvm_x86_ops->decache_regs(vcpu);
2226
2227 io->count -= io->cur_count;
2228 io->cur_count = 0;
2229
2230 return 0;
2231}
2232
2233static void kernel_pio(struct kvm_io_device *pio_dev,
2234 struct kvm_vcpu *vcpu,
2235 void *pd)
2236{
2237 /* TODO: String I/O for in kernel device */
2238
2239 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2240 if (vcpu->arch.pio.in)
2241 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2242 vcpu->arch.pio.size,
de7d789a
CO		 2243 pd);
2244 else
ad312c7c
ZX		 2245 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2246 vcpu->arch.pio.size,
de7d789a
CO		 2247 pd);
2248 mutex_unlock(&vcpu->kvm->lock);
2249}
2250
2251static void pio_string_write(struct kvm_io_device *pio_dev,
2252 struct kvm_vcpu *vcpu)
2253{
ad312c7c
ZX		 2254 struct kvm_pio_request *io = &vcpu->arch.pio;
2255 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2256 int i;
2257
2258 mutex_lock(&vcpu->kvm->lock);
2259 for (i = 0; i < io->cur_count; i++) {
2260 kvm_iodevice_write(pio_dev, io->port,
2261 io->size,
2262 pd);
2263 pd += io->size;
2264 }
2265 mutex_unlock(&vcpu->kvm->lock);
2266}
2267
2268static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
2269 gpa_t addr)
2270{
2271 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr);
2272}
2273
2274int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2275 int size, unsigned port)
2276{
2277 struct kvm_io_device *pio_dev;
2278
2279 vcpu->run->exit_reason = KVM_EXIT_IO;
2280 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2281 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2282 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2283 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2284 vcpu->run->io.port = vcpu->arch.pio.port = port;
2285 vcpu->arch.pio.in = in;
2286 vcpu->arch.pio.string = 0;
2287 vcpu->arch.pio.down = 0;
2288 vcpu->arch.pio.guest_page_offset = 0;
2289 vcpu->arch.pio.rep = 0;
de7d789a 2290
2714d1d3
FEL		 2291 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2292 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2293 handler);
2294 else
2295 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2296 handler);
2297
de7d789a 2298 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2299 memcpy(vcpu->arch.pio_data, &vcpu->arch.regs[VCPU_REGS_RAX], 4);
de7d789a
CO		 2300
2301 kvm_x86_ops->skip_emulated_instruction(vcpu);
2302
2303 pio_dev = vcpu_find_pio_dev(vcpu, port);
2304 if (pio_dev) {
ad312c7c 2305 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2306 complete_pio(vcpu);
2307 return 1;
2308 }
2309 return 0;
2310}
2311EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2312
2313int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2314 int size, unsigned long count, int down,
2315 gva_t address, int rep, unsigned port)
2316{
2317 unsigned now, in_page;
2318 int i, ret = 0;
2319 int nr_pages = 1;
2320 struct page *page;
2321 struct kvm_io_device *pio_dev;
2322
2323 vcpu->run->exit_reason = KVM_EXIT_IO;
2324 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2325 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2326 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2327 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2328 vcpu->run->io.port = vcpu->arch.pio.port = port;
2329 vcpu->arch.pio.in = in;
2330 vcpu->arch.pio.string = 1;
2331 vcpu->arch.pio.down = down;
2332 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2333 vcpu->arch.pio.rep = rep;
de7d789a 2334
2714d1d3
FEL		 2335 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2336 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2337 handler);
2338 else
2339 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2340 handler);
2341
de7d789a
CO		 2342 if (!count) {
2343 kvm_x86_ops->skip_emulated_instruction(vcpu);
2344 return 1;
2345 }
2346
2347 if (!down)
2348 in_page = PAGE_SIZE - offset_in_page(address);
2349 else
2350 in_page = offset_in_page(address) + size;
2351 now = min(count, (unsigned long)in_page / size);
2352 if (!now) {
2353 /*
2354 * String I/O straddles page boundary. Pin two guest pages
2355 * so that we satisfy atomicity constraints. Do just one
2356 * transaction to avoid complexity.
2357 */
2358 nr_pages = 2;
2359 now = 1;
2360 }
2361 if (down) {
2362 /*
2363 * String I/O in reverse. Yuck. Kill the guest, fix later.
2364 */
2365 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2366 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2367 return 1;
2368 }
2369 vcpu->run->io.count = now;
ad312c7c 2370 vcpu->arch.pio.cur_count = now;
de7d789a 2371
ad312c7c 2372 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2373 kvm_x86_ops->skip_emulated_instruction(vcpu);
2374
2375 for (i = 0; i < nr_pages; ++i) {
de7d789a 2376 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2377 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2378 if (!page) {
c1a5d4f9 2379 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2380 free_pio_guest_pages(vcpu);
2381 return 1;
2382 }
2383 }
2384
2385 pio_dev = vcpu_find_pio_dev(vcpu, port);
ad312c7c 2386 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2387 /* string PIO write */
2388 ret = pio_copy_data(vcpu);
2389 if (ret >= 0 && pio_dev) {
2390 pio_string_write(pio_dev, vcpu);
2391 complete_pio(vcpu);
ad312c7c 2392 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2393 ret = 1;
2394 }
2395 } else if (pio_dev)
2396 pr_unimpl(vcpu, "no string pio read support yet, "
2397 "port %x size %d count %ld\n",
2398 port, size, count);
2399
2400 return ret;
2401}
2402EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2403
f8c16bba 2404int kvm_arch_init(void *opaque)
043405e1 2405{
56c6d28a 2406 int r;
f8c16bba
ZX		 2407 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2408
f8c16bba
ZX		 2409 if (kvm_x86_ops) {
2410 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2411 r = -EEXIST;
2412 goto out;
f8c16bba
ZX		 2413 }
2414
2415 if (!ops->cpu_has_kvm_support()) {
2416 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2417 r = -EOPNOTSUPP;
2418 goto out;
f8c16bba
ZX		 2419 }
2420 if (ops->disabled_by_bios()) {
2421 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2422 r = -EOPNOTSUPP;
2423 goto out;
f8c16bba
ZX		 2424 }
2425
97db56ce
AK		 2426 r = kvm_mmu_module_init();
2427 if (r)
2428 goto out;
2429
2430 kvm_init_msr_list();
2431
f8c16bba 2432 kvm_x86_ops = ops;
56c6d28a 2433 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2434 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2435 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2436 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2437 return 0;
56c6d28a
ZX		 2438
2439out:
56c6d28a 2440 return r;
043405e1 2441}
8776e519 2442
f8c16bba
ZX		 2443void kvm_arch_exit(void)
2444{
2445 kvm_x86_ops = NULL;
56c6d28a
ZX		 2446 kvm_mmu_module_exit();
2447}
f8c16bba 2448
8776e519
HB		 2449int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2450{
2451 ++vcpu->stat.halt_exits;
2714d1d3 2452 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2453 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2454 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3200f405 2455 up_read(&vcpu->kvm->slots_lock);
8776e519 2456 kvm_vcpu_block(vcpu);
3200f405 2457 down_read(&vcpu->kvm->slots_lock);
a4535290 2458 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
8776e519
HB		 2459 return -EINTR;
2460 return 1;
2461 } else {
2462 vcpu->run->exit_reason = KVM_EXIT_HLT;
2463 return 0;
2464 }
2465}
2466EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2467
2f333bcb
MT		 2468static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2469 unsigned long a1)
2470{
2471 if (is_long_mode(vcpu))
2472 return a0;
2473 else
2474 return a0 | ((gpa_t)a1 << 32);
2475}
2476
8776e519
HB		 2477int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2478{
2479 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2480 int r = 1;
8776e519
HB		 2481
2482 kvm_x86_ops->cache_regs(vcpu);
2483
ad312c7c
ZX		 2484 nr = vcpu->arch.regs[VCPU_REGS_RAX];
2485 a0 = vcpu->arch.regs[VCPU_REGS_RBX];
2486 a1 = vcpu->arch.regs[VCPU_REGS_RCX];
2487 a2 = vcpu->arch.regs[VCPU_REGS_RDX];
2488 a3 = vcpu->arch.regs[VCPU_REGS_RSI];
8776e519 2489
2714d1d3
FEL		 2490 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2491
8776e519
HB		 2492 if (!is_long_mode(vcpu)) {
2493 nr &= 0xFFFFFFFF;
2494 a0 &= 0xFFFFFFFF;
2495 a1 &= 0xFFFFFFFF;
2496 a2 &= 0xFFFFFFFF;
2497 a3 &= 0xFFFFFFFF;
2498 }
2499
2500 switch (nr) {
b93463aa
AK		 2501 case KVM_HC_VAPIC_POLL_IRQ:
2502 ret = 0;
2503 break;
2f333bcb
MT		 2504 case KVM_HC_MMU_OP:
2505 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2506 break;
8776e519
HB		 2507 default:
2508 ret = -KVM_ENOSYS;
2509 break;
2510 }
ad312c7c 2511 vcpu->arch.regs[VCPU_REGS_RAX] = ret;
8776e519 2512 kvm_x86_ops->decache_regs(vcpu);
f11c3a8d 2513 ++vcpu->stat.hypercalls;
2f333bcb 2514 return r;
8776e519
HB		 2515}
2516EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2517
2518int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2519{
2520 char instruction[3];
2521 int ret = 0;
2522
8776e519
HB		 2523
2524 /*
2525 * Blow out the MMU to ensure that no other VCPU has an active mapping
2526 * to ensure that the updated hypercall appears atomically across all
2527 * VCPUs.
2528 */
2529 kvm_mmu_zap_all(vcpu->kvm);
2530
2531 kvm_x86_ops->cache_regs(vcpu);
2532 kvm_x86_ops->patch_hypercall(vcpu, instruction);
ad312c7c 2533 if (emulator_write_emulated(vcpu->arch.rip, instruction, 3, vcpu)
8776e519
HB		 2534 != X86EMUL_CONTINUE)
2535 ret = -EFAULT;
2536
8776e519
HB		 2537 return ret;
2538}
2539
2540static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2541{
2542 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2543}
2544
2545void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2546{
2547 struct descriptor_table dt = { limit, base };
2548
2549 kvm_x86_ops->set_gdt(vcpu, &dt);
2550}
2551
2552void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2553{
2554 struct descriptor_table dt = { limit, base };
2555
2556 kvm_x86_ops->set_idt(vcpu, &dt);
2557}
2558
2559void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2560 unsigned long *rflags)
2561{
2d3ad1f4 2562 kvm_lmsw(vcpu, msw);
8776e519
HB		 2563 *rflags = kvm_x86_ops->get_rflags(vcpu);
2564}
2565
2566unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2567{
54e445ca
JR		 2568 unsigned long value;
2569
8776e519
HB		 2570 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2571 switch (cr) {
2572 case 0:
54e445ca
JR		 2573 value = vcpu->arch.cr0;
2574 break;
8776e519 2575 case 2:
54e445ca
JR		 2576 value = vcpu->arch.cr2;
2577 break;
8776e519 2578 case 3:
54e445ca
JR		 2579 value = vcpu->arch.cr3;
2580 break;
8776e519 2581 case 4:
54e445ca
JR		 2582 value = vcpu->arch.cr4;
2583 break;
152ff9be 2584 case 8:
54e445ca
JR		 2585 value = kvm_get_cr8(vcpu);
2586 break;
8776e519 2587 default:
b8688d51 2588 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2589 return 0;
2590 }
54e445ca
JR		 2591 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2592 (u32)((u64)value >> 32), handler);
2593
2594 return value;
8776e519
HB		 2595}
2596
2597void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2598 unsigned long *rflags)
2599{
54e445ca
JR		 2600 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2601 (u32)((u64)val >> 32), handler);
2602
8776e519
HB		 2603 switch (cr) {
2604 case 0:
2d3ad1f4 2605 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2606 *rflags = kvm_x86_ops->get_rflags(vcpu);
2607 break;
2608 case 2:
ad312c7c 2609 vcpu->arch.cr2 = val;
8776e519
HB		 2610 break;
2611 case 3:
2d3ad1f4 2612 kvm_set_cr3(vcpu, val);
8776e519
HB		 2613 break;
2614 case 4:
2d3ad1f4 2615 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2616 break;
152ff9be 2617 case 8:
2d3ad1f4 2618 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2619 break;
8776e519 2620 default:
b8688d51 2621 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2622 }
2623}
2624
07716717
DK		 2625static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2626{
ad312c7c
ZX		 2627 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2628 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2629
2630 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2631 /* when no next entry is found, the current entry[i] is reselected */
2632 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2633 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2634 if (ej->function == e->function) {
2635 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2636 return j;
2637 }
2638 }
2639 return 0; /* silence gcc, even though control never reaches here */
2640}
2641
2642/* find an entry with matching function, matching index (if needed), and that
2643 * should be read next (if it's stateful) */
2644static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2645 u32 function, u32 index)
2646{
2647 if (e->function != function)
2648 return 0;
2649 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2650 return 0;
2651 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2652 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2653 return 0;
2654 return 1;
2655}
2656
8776e519
HB		 2657void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2658{
2659 int i;
07716717
DK		 2660 u32 function, index;
2661 struct kvm_cpuid_entry2 *e, *best;
8776e519
HB		 2662
2663 kvm_x86_ops->cache_regs(vcpu);
ad312c7c
ZX		 2664 function = vcpu->arch.regs[VCPU_REGS_RAX];
2665 index = vcpu->arch.regs[VCPU_REGS_RCX];
2666 vcpu->arch.regs[VCPU_REGS_RAX] = 0;
2667 vcpu->arch.regs[VCPU_REGS_RBX] = 0;
2668 vcpu->arch.regs[VCPU_REGS_RCX] = 0;
2669 vcpu->arch.regs[VCPU_REGS_RDX] = 0;
8776e519 2670 best = NULL;
ad312c7c
ZX		 2671 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2672 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2673 if (is_matching_cpuid_entry(e, function, index)) {
2674 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2675 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2676 best = e;
2677 break;
2678 }
2679 /*
2680 * Both basic or both extended?
2681 */
2682 if (((e->function ^ function) & 0x80000000) == 0)
2683 if (!best || e->function > best->function)
2684 best = e;
2685 }
2686 if (best) {
ad312c7c
ZX		 2687 vcpu->arch.regs[VCPU_REGS_RAX] = best->eax;
2688 vcpu->arch.regs[VCPU_REGS_RBX] = best->ebx;
2689 vcpu->arch.regs[VCPU_REGS_RCX] = best->ecx;
2690 vcpu->arch.regs[VCPU_REGS_RDX] = best->edx;
8776e519
HB		 2691 }
2692 kvm_x86_ops->decache_regs(vcpu);
2693 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3
FEL		 2694 KVMTRACE_5D(CPUID, vcpu, function,
2695 (u32)vcpu->arch.regs[VCPU_REGS_RAX],
2696 (u32)vcpu->arch.regs[VCPU_REGS_RBX],
2697 (u32)vcpu->arch.regs[VCPU_REGS_RCX],
2698 (u32)vcpu->arch.regs[VCPU_REGS_RDX], handler);
8776e519
HB		 2699}
2700EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2701
b6c7a5dc
HB		 2702/*
2703 * Check if userspace requested an interrupt window, and that the
2704 * interrupt window is open.
2705 *
2706 * No need to exit to userspace if we already have an interrupt queued.
2707 */
2708static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2709 struct kvm_run *kvm_run)
2710{
ad312c7c 2711 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2712 kvm_run->request_interrupt_window &&
ad312c7c 2713 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2714 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2715}
2716
2717static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2718 struct kvm_run *kvm_run)
2719{
2720 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2721 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 2722 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2723 if (irqchip_in_kernel(vcpu->kvm))
2724 kvm_run->ready_for_interrupt_injection = 1;
2725 else
2726 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2727 (vcpu->arch.interrupt_window_open &&
2728 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2729}
2730
b93463aa
AK		 2731static void vapic_enter(struct kvm_vcpu *vcpu)
2732{
2733 struct kvm_lapic *apic = vcpu->arch.apic;
2734 struct page *page;
2735
2736 if (!apic || !apic->vapic_addr)
2737 return;
2738
10589a46 2739 down_read(&current->mm->mmap_sem);
b93463aa 2740 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2741 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2742
2743 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2744}
2745
2746static void vapic_exit(struct kvm_vcpu *vcpu)
2747{
2748 struct kvm_lapic *apic = vcpu->arch.apic;
2749
2750 if (!apic || !apic->vapic_addr)
2751 return;
2752
2753 kvm_release_page_dirty(apic->vapic_page);
2754 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
2755}
2756
b6c7a5dc
HB		 2757static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2758{
2759 int r;
2760
a4535290 2761 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2762 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2763 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2764 kvm_lapic_reset(vcpu);
2765 r = kvm_x86_ops->vcpu_reset(vcpu);
2766 if (r)
2767 return r;
a4535290 2768 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2769 }
2770
3200f405 2771 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2772 vapic_enter(vcpu);
2773
b6c7a5dc
HB		 2774preempted:
2775 if (vcpu->guest_debug.enabled)
2776 kvm_x86_ops->guest_debug_pre(vcpu);
2777
2778again:
2e53d63a
MT		 2779 if (vcpu->requests)
2780 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2781 kvm_mmu_unload(vcpu);
2782
b6c7a5dc
HB		 2783 r = kvm_mmu_reload(vcpu);
2784 if (unlikely(r))
2785 goto out;
2786
2f52d58c
AK		 2787 if (vcpu->requests) {
2788 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2789 __kvm_migrate_timers(vcpu);
d4acf7e7
MT		 2790 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2791 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2792 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2793 &vcpu->requests)) {
2794 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2795 r = 0;
2796 goto out;
2797 }
71c4dfaf
JR		 2798 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2799 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2800 r = 0;
2801 goto out;
2802 }
2f52d58c 2803 }
b93463aa 2804
06e05645 2805 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2806 kvm_inject_pending_timer_irqs(vcpu);
2807
2808 preempt_disable();
2809
2810 kvm_x86_ops->prepare_guest_switch(vcpu);
2811 kvm_load_guest_fpu(vcpu);
2812
2813 local_irq_disable();
2814
d4acf7e7 2815 if (vcpu->requests || need_resched()) {
6c142801
AK		 2816 local_irq_enable();
2817 preempt_enable();
2818 r = 1;
2819 goto out;
2820 }
2821
b6c7a5dc
HB		 2822 if (signal_pending(current)) {
2823 local_irq_enable();
2824 preempt_enable();
2825 r = -EINTR;
2826 kvm_run->exit_reason = KVM_EXIT_INTR;
2827 ++vcpu->stat.signal_exits;
2828 goto out;
2829 }
2830
e9571ed5
MT		 2831 vcpu->guest_mode = 1;
2832 /*
2833 * Make sure that guest_mode assignment won't happen after
2834 * testing the pending IRQ vector bitmap.
2835 */
2836 smp_wmb();
2837
ad312c7c 2838 if (vcpu->arch.exception.pending)
298101da
AK		 2839 __queue_exception(vcpu);
2840 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2841 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2842 else
b6c7a5dc
HB		 2843 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2844
b93463aa
AK		 2845 kvm_lapic_sync_to_vapic(vcpu);
2846
3200f405
MT		 2847 up_read(&vcpu->kvm->slots_lock);
2848
b6c7a5dc
HB		 2849 kvm_guest_enter();
2850
b6c7a5dc 2851
2714d1d3 2852 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 2853 kvm_x86_ops->run(vcpu, kvm_run);
2854
2855 vcpu->guest_mode = 0;
2856 local_irq_enable();
2857
2858 ++vcpu->stat.exits;
2859
2860 /*
2861 * We must have an instruction between local_irq_enable() and
2862 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2863 * the interrupt shadow. The stat.exits increment will do nicely.
2864 * But we need to prevent reordering, hence this barrier():
2865 */
2866 barrier();
2867
2868 kvm_guest_exit();
2869
2870 preempt_enable();
2871
3200f405
MT		 2872 down_read(&vcpu->kvm->slots_lock);
2873
b6c7a5dc
HB		 2874 /*
2875 * Profile KVM exit RIPs:
2876 */
2877 if (unlikely(prof_on == KVM_PROFILING)) {
2878 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2879 profile_hit(KVM_PROFILING, (void *)vcpu->arch.rip);
b6c7a5dc
HB		 2880 }
2881
ad312c7c
ZX		 2882 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2883 vcpu->arch.exception.pending = false;
298101da 2884
b93463aa
AK		 2885 kvm_lapic_sync_from_vapic(vcpu);
2886
b6c7a5dc
HB		 2887 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2888
2889 if (r > 0) {
2890 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2891 r = -EINTR;
2892 kvm_run->exit_reason = KVM_EXIT_INTR;
2893 ++vcpu->stat.request_irq_exits;
2894 goto out;
2895 }
e1beb1d3 2896 if (!need_resched())
b6c7a5dc 2897 goto again;
b6c7a5dc
HB		 2898 }
2899
2900out:
3200f405 2901 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2902 if (r > 0) {
2903 kvm_resched(vcpu);
3200f405 2904 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2905 goto preempted;
2906 }
2907
2908 post_kvm_run_save(vcpu, kvm_run);
2909
3200f405 2910 down_read(&vcpu->kvm->slots_lock);
b93463aa 2911 vapic_exit(vcpu);
3200f405 2912 up_read(&vcpu->kvm->slots_lock);
b93463aa 2913
b6c7a5dc
HB		 2914 return r;
2915}
2916
2917int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2918{
2919 int r;
2920 sigset_t sigsaved;
2921
2922 vcpu_load(vcpu);
2923
a4535290 2924 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc
HB		 2925 kvm_vcpu_block(vcpu);
2926 vcpu_put(vcpu);
2927 return -EAGAIN;
2928 }
2929
2930 if (vcpu->sigset_active)
2931 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
2932
2933 /* re-sync apic's tpr */
2934 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 2935 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 2936
ad312c7c 2937 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 2938 r = complete_pio(vcpu);
2939 if (r)
2940 goto out;
2941 }
2942#if CONFIG_HAS_IOMEM
2943 if (vcpu->mmio_needed) {
2944 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
2945 vcpu->mmio_read_completed = 1;
2946 vcpu->mmio_needed = 0;
3200f405
MT		 2947
2948 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 2949 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 2950 vcpu->arch.mmio_fault_cr2, 0,
2951 EMULTYPE_NO_DECODE);
3200f405 2952 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2953 if (r == EMULATE_DO_MMIO) {
2954 /*
2955 * Read-modify-write. Back to userspace.
2956 */
2957 r = 0;
2958 goto out;
2959 }
2960 }
2961#endif
2962 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) {
2963 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2964 vcpu->arch.regs[VCPU_REGS_RAX] = kvm_run->hypercall.ret;
b6c7a5dc
HB		 2965 kvm_x86_ops->decache_regs(vcpu);
2966 }
2967
2968 r = __vcpu_run(vcpu, kvm_run);
2969
2970out:
2971 if (vcpu->sigset_active)
2972 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
2973
2974 vcpu_put(vcpu);
2975 return r;
2976}
2977
2978int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
2979{
2980 vcpu_load(vcpu);
2981
2982 kvm_x86_ops->cache_regs(vcpu);
2983
ad312c7c
ZX		 2984 regs->rax = vcpu->arch.regs[VCPU_REGS_RAX];
2985 regs->rbx = vcpu->arch.regs[VCPU_REGS_RBX];
2986 regs->rcx = vcpu->arch.regs[VCPU_REGS_RCX];
2987 regs->rdx = vcpu->arch.regs[VCPU_REGS_RDX];
2988 regs->rsi = vcpu->arch.regs[VCPU_REGS_RSI];
2989 regs->rdi = vcpu->arch.regs[VCPU_REGS_RDI];
2990 regs->rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2991 regs->rbp = vcpu->arch.regs[VCPU_REGS_RBP];
b6c7a5dc 2992#ifdef CONFIG_X86_64
ad312c7c
ZX		 2993 regs->r8 = vcpu->arch.regs[VCPU_REGS_R8];
2994 regs->r9 = vcpu->arch.regs[VCPU_REGS_R9];
2995 regs->r10 = vcpu->arch.regs[VCPU_REGS_R10];
2996 regs->r11 = vcpu->arch.regs[VCPU_REGS_R11];
2997 regs->r12 = vcpu->arch.regs[VCPU_REGS_R12];
2998 regs->r13 = vcpu->arch.regs[VCPU_REGS_R13];
2999 regs->r14 = vcpu->arch.regs[VCPU_REGS_R14];
3000 regs->r15 = vcpu->arch.regs[VCPU_REGS_R15];
b6c7a5dc
HB		 3001#endif
3002
ad312c7c 3003 regs->rip = vcpu->arch.rip;
b6c7a5dc
HB		 3004 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3005
3006 /*
3007 * Don't leak debug flags in case they were set for guest debugging
3008 */
3009 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3010 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3011
3012 vcpu_put(vcpu);
3013
3014 return 0;
3015}
3016
3017int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3018{
3019 vcpu_load(vcpu);
3020
ad312c7c
ZX		 3021 vcpu->arch.regs[VCPU_REGS_RAX] = regs->rax;
3022 vcpu->arch.regs[VCPU_REGS_RBX] = regs->rbx;
3023 vcpu->arch.regs[VCPU_REGS_RCX] = regs->rcx;
3024 vcpu->arch.regs[VCPU_REGS_RDX] = regs->rdx;
3025 vcpu->arch.regs[VCPU_REGS_RSI] = regs->rsi;
3026 vcpu->arch.regs[VCPU_REGS_RDI] = regs->rdi;
3027 vcpu->arch.regs[VCPU_REGS_RSP] = regs->rsp;
3028 vcpu->arch.regs[VCPU_REGS_RBP] = regs->rbp;
b6c7a5dc 3029#ifdef CONFIG_X86_64
ad312c7c
ZX		 3030 vcpu->arch.regs[VCPU_REGS_R8] = regs->r8;
3031 vcpu->arch.regs[VCPU_REGS_R9] = regs->r9;
3032 vcpu->arch.regs[VCPU_REGS_R10] = regs->r10;
3033 vcpu->arch.regs[VCPU_REGS_R11] = regs->r11;
3034 vcpu->arch.regs[VCPU_REGS_R12] = regs->r12;
3035 vcpu->arch.regs[VCPU_REGS_R13] = regs->r13;
3036 vcpu->arch.regs[VCPU_REGS_R14] = regs->r14;
3037 vcpu->arch.regs[VCPU_REGS_R15] = regs->r15;
b6c7a5dc
HB		 3038#endif
3039
ad312c7c 3040 vcpu->arch.rip = regs->rip;
b6c7a5dc
HB		 3041 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3042
3043 kvm_x86_ops->decache_regs(vcpu);
3044
b4f14abd
JK		 3045 vcpu->arch.exception.pending = false;
3046
b6c7a5dc
HB		 3047 vcpu_put(vcpu);
3048
3049 return 0;
3050}
3051
3052static void get_segment(struct kvm_vcpu *vcpu,
3053 struct kvm_segment *var, int seg)
3054{
14af3f3c 3055 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3056}
3057
3058void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3059{
3060 struct kvm_segment cs;
3061
3062 get_segment(vcpu, &cs, VCPU_SREG_CS);
3063 *db = cs.db;
3064 *l = cs.l;
3065}
3066EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3067
3068int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3069 struct kvm_sregs *sregs)
3070{
3071 struct descriptor_table dt;
3072 int pending_vec;
3073
3074 vcpu_load(vcpu);
3075
3076 get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3077 get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3078 get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3079 get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3080 get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3081 get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3082
3083 get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3084 get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3085
3086 kvm_x86_ops->get_idt(vcpu, &dt);
3087 sregs->idt.limit = dt.limit;
3088 sregs->idt.base = dt.base;
3089 kvm_x86_ops->get_gdt(vcpu, &dt);
3090 sregs->gdt.limit = dt.limit;
3091 sregs->gdt.base = dt.base;
3092
3093 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3094 sregs->cr0 = vcpu->arch.cr0;
3095 sregs->cr2 = vcpu->arch.cr2;
3096 sregs->cr3 = vcpu->arch.cr3;
3097 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3098 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3099 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3100 sregs->apic_base = kvm_get_apic_base(vcpu);
3101
3102 if (irqchip_in_kernel(vcpu->kvm)) {
3103 memset(sregs->interrupt_bitmap, 0,
3104 sizeof sregs->interrupt_bitmap);
3105 pending_vec = kvm_x86_ops->get_irq(vcpu);
3106 if (pending_vec >= 0)
3107 set_bit(pending_vec,
3108 (unsigned long *)sregs->interrupt_bitmap);
3109 } else
ad312c7c 3110 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3111 sizeof sregs->interrupt_bitmap);
3112
3113 vcpu_put(vcpu);
3114
3115 return 0;
3116}
3117
62d9f0db
MT		 3118int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3119 struct kvm_mp_state *mp_state)
3120{
3121 vcpu_load(vcpu);
3122 mp_state->mp_state = vcpu->arch.mp_state;
3123 vcpu_put(vcpu);
3124 return 0;
3125}
3126
3127int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3128 struct kvm_mp_state *mp_state)
3129{
3130 vcpu_load(vcpu);
3131 vcpu->arch.mp_state = mp_state->mp_state;
3132 vcpu_put(vcpu);
3133 return 0;
3134}
3135
b6c7a5dc
HB		 3136static void set_segment(struct kvm_vcpu *vcpu,
3137 struct kvm_segment *var, int seg)
3138{
14af3f3c 3139 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3140}
3141
37817f29
IE		 3142static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3143 struct kvm_segment *kvm_desct)
3144{
3145 kvm_desct->base = seg_desc->base0;
3146 kvm_desct->base |= seg_desc->base1 << 16;
3147 kvm_desct->base |= seg_desc->base2 << 24;
3148 kvm_desct->limit = seg_desc->limit0;
3149 kvm_desct->limit |= seg_desc->limit << 16;
3150 kvm_desct->selector = selector;
3151 kvm_desct->type = seg_desc->type;
3152 kvm_desct->present = seg_desc->p;
3153 kvm_desct->dpl = seg_desc->dpl;
3154 kvm_desct->db = seg_desc->d;
3155 kvm_desct->s = seg_desc->s;
3156 kvm_desct->l = seg_desc->l;
3157 kvm_desct->g = seg_desc->g;
3158 kvm_desct->avl = seg_desc->avl;
3159 if (!selector)
3160 kvm_desct->unusable = 1;
3161 else
3162 kvm_desct->unusable = 0;
3163 kvm_desct->padding = 0;
3164}
3165
3166static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3167 u16 selector,
3168 struct descriptor_table *dtable)
3169{
3170 if (selector & 1 << 2) {
3171 struct kvm_segment kvm_seg;
3172
3173 get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
3174
3175 if (kvm_seg.unusable)
3176 dtable->limit = 0;
3177 else
3178 dtable->limit = kvm_seg.limit;
3179 dtable->base = kvm_seg.base;
3180 }
3181 else
3182 kvm_x86_ops->get_gdt(vcpu, dtable);
3183}
3184
3185/* allowed just for 8 bytes segments */
3186static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3187 struct desc_struct *seg_desc)
3188{
3189 struct descriptor_table dtable;
3190 u16 index = selector >> 3;
3191
3192 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3193
3194 if (dtable.limit < index * 8 + 7) {
3195 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3196 return 1;
3197 }
3198 return kvm_read_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3199}
3200
3201/* allowed just for 8 bytes segments */
3202static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3203 struct desc_struct *seg_desc)
3204{
3205 struct descriptor_table dtable;
3206 u16 index = selector >> 3;
3207
3208 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3209
3210 if (dtable.limit < index * 8 + 7)
3211 return 1;
3212 return kvm_write_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3213}
3214
3215static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3216 struct desc_struct *seg_desc)
3217{
3218 u32 base_addr;
3219
3220 base_addr = seg_desc->base0;
3221 base_addr |= (seg_desc->base1 << 16);
3222 base_addr |= (seg_desc->base2 << 24);
3223
3224 return base_addr;
3225}
3226
3227static int load_tss_segment32(struct kvm_vcpu *vcpu,
3228 struct desc_struct *seg_desc,
3229 struct tss_segment_32 *tss)
3230{
3231 u32 base_addr;
3232
3233 base_addr = get_tss_base_addr(vcpu, seg_desc);
3234
3235 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3236 sizeof(struct tss_segment_32));
3237}
3238
3239static int save_tss_segment32(struct kvm_vcpu *vcpu,
3240 struct desc_struct *seg_desc,
3241 struct tss_segment_32 *tss)
3242{
3243 u32 base_addr;
3244
3245 base_addr = get_tss_base_addr(vcpu, seg_desc);
3246
3247 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3248 sizeof(struct tss_segment_32));
3249}
3250
3251static int load_tss_segment16(struct kvm_vcpu *vcpu,
3252 struct desc_struct *seg_desc,
3253 struct tss_segment_16 *tss)
3254{
3255 u32 base_addr;
3256
3257 base_addr = get_tss_base_addr(vcpu, seg_desc);
3258
3259 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3260 sizeof(struct tss_segment_16));
3261}
3262
3263static int save_tss_segment16(struct kvm_vcpu *vcpu,
3264 struct desc_struct *seg_desc,
3265 struct tss_segment_16 *tss)
3266{
3267 u32 base_addr;
3268
3269 base_addr = get_tss_base_addr(vcpu, seg_desc);
3270
3271 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3272 sizeof(struct tss_segment_16));
3273}
3274
3275static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3276{
3277 struct kvm_segment kvm_seg;
3278
3279 get_segment(vcpu, &kvm_seg, seg);
3280 return kvm_seg.selector;
3281}
3282
3283static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3284 u16 selector,
3285 struct kvm_segment *kvm_seg)
3286{
3287 struct desc_struct seg_desc;
3288
3289 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3290 return 1;
3291 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3292 return 0;
3293}
3294
3295static int load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3296 int type_bits, int seg)
3297{
3298 struct kvm_segment kvm_seg;
3299
3300 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3301 return 1;
3302 kvm_seg.type |= type_bits;
3303
3304 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3305 seg != VCPU_SREG_LDTR)
3306 if (!kvm_seg.s)
3307 kvm_seg.unusable = 1;
3308
3309 set_segment(vcpu, &kvm_seg, seg);
3310 return 0;
3311}
3312
3313static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3314 struct tss_segment_32 *tss)
3315{
3316 tss->cr3 = vcpu->arch.cr3;
3317 tss->eip = vcpu->arch.rip;
3318 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
3319 tss->eax = vcpu->arch.regs[VCPU_REGS_RAX];
3320 tss->ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3321 tss->edx = vcpu->arch.regs[VCPU_REGS_RDX];
3322 tss->ebx = vcpu->arch.regs[VCPU_REGS_RBX];
3323 tss->esp = vcpu->arch.regs[VCPU_REGS_RSP];
3324 tss->ebp = vcpu->arch.regs[VCPU_REGS_RBP];
3325 tss->esi = vcpu->arch.regs[VCPU_REGS_RSI];
3326 tss->edi = vcpu->arch.regs[VCPU_REGS_RDI];
3327
3328 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3329 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3330 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3331 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3332 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3333 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3334 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3335 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3336}
3337
3338static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3339 struct tss_segment_32 *tss)
3340{
3341 kvm_set_cr3(vcpu, tss->cr3);
3342
3343 vcpu->arch.rip = tss->eip;
3344 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3345
3346 vcpu->arch.regs[VCPU_REGS_RAX] = tss->eax;
3347 vcpu->arch.regs[VCPU_REGS_RCX] = tss->ecx;
3348 vcpu->arch.regs[VCPU_REGS_RDX] = tss->edx;
3349 vcpu->arch.regs[VCPU_REGS_RBX] = tss->ebx;
3350 vcpu->arch.regs[VCPU_REGS_RSP] = tss->esp;
3351 vcpu->arch.regs[VCPU_REGS_RBP] = tss->ebp;
3352 vcpu->arch.regs[VCPU_REGS_RSI] = tss->esi;
3353 vcpu->arch.regs[VCPU_REGS_RDI] = tss->edi;
3354
3355 if (load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
3356 return 1;
3357
3358 if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
3359 return 1;
3360
3361 if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
3362 return 1;
3363
3364 if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
3365 return 1;
3366
3367 if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
3368 return 1;
3369
3370 if (load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
3371 return 1;
3372
3373 if (load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
3374 return 1;
3375 return 0;
3376}
3377
3378static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3379 struct tss_segment_16 *tss)
3380{
3381 tss->ip = vcpu->arch.rip;
3382 tss->flag = kvm_x86_ops->get_rflags(vcpu);
3383 tss->ax = vcpu->arch.regs[VCPU_REGS_RAX];
3384 tss->cx = vcpu->arch.regs[VCPU_REGS_RCX];
3385 tss->dx = vcpu->arch.regs[VCPU_REGS_RDX];
3386 tss->bx = vcpu->arch.regs[VCPU_REGS_RBX];
3387 tss->sp = vcpu->arch.regs[VCPU_REGS_RSP];
3388 tss->bp = vcpu->arch.regs[VCPU_REGS_RBP];
3389 tss->si = vcpu->arch.regs[VCPU_REGS_RSI];
3390 tss->di = vcpu->arch.regs[VCPU_REGS_RDI];
3391
3392 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3393 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3394 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3395 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3396 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3397 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3398}
3399
3400static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3401 struct tss_segment_16 *tss)
3402{
3403 vcpu->arch.rip = tss->ip;
3404 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
3405 vcpu->arch.regs[VCPU_REGS_RAX] = tss->ax;
3406 vcpu->arch.regs[VCPU_REGS_RCX] = tss->cx;
3407 vcpu->arch.regs[VCPU_REGS_RDX] = tss->dx;
3408 vcpu->arch.regs[VCPU_REGS_RBX] = tss->bx;
3409 vcpu->arch.regs[VCPU_REGS_RSP] = tss->sp;
3410 vcpu->arch.regs[VCPU_REGS_RBP] = tss->bp;
3411 vcpu->arch.regs[VCPU_REGS_RSI] = tss->si;
3412 vcpu->arch.regs[VCPU_REGS_RDI] = tss->di;
3413
3414 if (load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
3415 return 1;
3416
3417 if (load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
3418 return 1;
3419
3420 if (load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
3421 return 1;
3422
3423 if (load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
3424 return 1;
3425
3426 if (load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
3427 return 1;
3428 return 0;
3429}
3430
8b2cf73c 3431static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
37817f29
IE		 3432 struct desc_struct *cseg_desc,
3433 struct desc_struct *nseg_desc)
3434{
3435 struct tss_segment_16 tss_segment_16;
3436 int ret = 0;
3437
3438 if (load_tss_segment16(vcpu, cseg_desc, &tss_segment_16))
3439 goto out;
3440
3441 save_state_to_tss16(vcpu, &tss_segment_16);
3442 save_tss_segment16(vcpu, cseg_desc, &tss_segment_16);
3443
3444 if (load_tss_segment16(vcpu, nseg_desc, &tss_segment_16))
3445 goto out;
3446 if (load_state_from_tss16(vcpu, &tss_segment_16))
3447 goto out;
3448
3449 ret = 1;
3450out:
3451 return ret;
3452}
3453
8b2cf73c 3454static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
37817f29
IE		 3455 struct desc_struct *cseg_desc,
3456 struct desc_struct *nseg_desc)
3457{
3458 struct tss_segment_32 tss_segment_32;
3459 int ret = 0;
3460
3461 if (load_tss_segment32(vcpu, cseg_desc, &tss_segment_32))
3462 goto out;
3463
3464 save_state_to_tss32(vcpu, &tss_segment_32);
3465 save_tss_segment32(vcpu, cseg_desc, &tss_segment_32);
3466
3467 if (load_tss_segment32(vcpu, nseg_desc, &tss_segment_32))
3468 goto out;
3469 if (load_state_from_tss32(vcpu, &tss_segment_32))
3470 goto out;
3471
3472 ret = 1;
3473out:
3474 return ret;
3475}
3476
3477int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3478{
3479 struct kvm_segment tr_seg;
3480 struct desc_struct cseg_desc;
3481 struct desc_struct nseg_desc;
3482 int ret = 0;
3483
3484 get_segment(vcpu, &tr_seg, VCPU_SREG_TR);
3485
3486 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3487 goto out;
3488
3489 if (load_guest_segment_descriptor(vcpu, tr_seg.selector, &cseg_desc))
3490 goto out;
3491
3492
3493 if (reason != TASK_SWITCH_IRET) {
3494 int cpl;
3495
3496 cpl = kvm_x86_ops->get_cpl(vcpu);
3497 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3498 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3499 return 1;
3500 }
3501 }
3502
3503 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3504 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3505 return 1;
3506 }
3507
3508 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3509 cseg_desc.type &= ~(1 << 1); //clear the B flag
37817f29
IE		 3510 save_guest_segment_descriptor(vcpu, tr_seg.selector,
3511 &cseg_desc);
3512 }
3513
3514 if (reason == TASK_SWITCH_IRET) {
3515 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3516 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3517 }
3518
3519 kvm_x86_ops->skip_emulated_instruction(vcpu);
3520 kvm_x86_ops->cache_regs(vcpu);
3521
3522 if (nseg_desc.type & 8)
3523 ret = kvm_task_switch_32(vcpu, tss_selector, &cseg_desc,
3524 &nseg_desc);
3525 else
3526 ret = kvm_task_switch_16(vcpu, tss_selector, &cseg_desc,
3527 &nseg_desc);
3528
3529 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3530 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3531 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3532 }
3533
3534 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3535 nseg_desc.type |= (1 << 1);
37817f29
IE		 3536 save_guest_segment_descriptor(vcpu, tss_selector,
3537 &nseg_desc);
3538 }
3539
3540 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3541 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3542 tr_seg.type = 11;
3543 set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
3544out:
3545 kvm_x86_ops->decache_regs(vcpu);
3546 return ret;
3547}
3548EXPORT_SYMBOL_GPL(kvm_task_switch);
3549
b6c7a5dc
HB		 3550int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3551 struct kvm_sregs *sregs)
3552{
3553 int mmu_reset_needed = 0;
3554 int i, pending_vec, max_bits;
3555 struct descriptor_table dt;
3556
3557 vcpu_load(vcpu);
3558
3559 dt.limit = sregs->idt.limit;
3560 dt.base = sregs->idt.base;
3561 kvm_x86_ops->set_idt(vcpu, &dt);
3562 dt.limit = sregs->gdt.limit;
3563 dt.base = sregs->gdt.base;
3564 kvm_x86_ops->set_gdt(vcpu, &dt);
3565
ad312c7c
ZX		 3566 vcpu->arch.cr2 = sregs->cr2;
3567 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3568 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3569
2d3ad1f4 3570 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3571
ad312c7c 3572 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3573 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3574 kvm_set_apic_base(vcpu, sregs->apic_base);
3575
3576 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3577
ad312c7c 3578 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3579 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3580 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3581
ad312c7c 3582 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3583 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3584 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3585 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3586
3587 if (mmu_reset_needed)
3588 kvm_mmu_reset_context(vcpu);
3589
3590 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3591 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3592 sizeof vcpu->arch.irq_pending);
3593 vcpu->arch.irq_summary = 0;
3594 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3595 if (vcpu->arch.irq_pending[i])
3596 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3597 } else {
3598 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3599 pending_vec = find_first_bit(
3600 (const unsigned long *)sregs->interrupt_bitmap,
3601 max_bits);
3602 /* Only pending external irq is handled here */
3603 if (pending_vec < max_bits) {
3604 kvm_x86_ops->set_irq(vcpu, pending_vec);
3605 pr_debug("Set back pending irq %d\n",
3606 pending_vec);
3607 }
3608 }
3609
3610 set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3611 set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3612 set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3613 set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3614 set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3615 set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3616
3617 set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3618 set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3619
3620 vcpu_put(vcpu);
3621
3622 return 0;
3623}
3624
3625int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3626 struct kvm_debug_guest *dbg)
3627{
3628 int r;
3629
3630 vcpu_load(vcpu);
3631
3632 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3633
3634 vcpu_put(vcpu);
3635
3636 return r;
3637}
3638
d0752060
HB		 3639/*
3640 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3641 * we have asm/x86/processor.h
3642 */
3643struct fxsave {
3644 u16 cwd;
3645 u16 swd;
3646 u16 twd;
3647 u16 fop;
3648 u64 rip;
3649 u64 rdp;
3650 u32 mxcsr;
3651 u32 mxcsr_mask;
3652 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3653#ifdef CONFIG_X86_64
3654 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3655#else
3656 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3657#endif
3658};
3659
8b006791
ZX		 3660/*
3661 * Translate a guest virtual address to a guest physical address.
3662 */
3663int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3664 struct kvm_translation *tr)
3665{
3666 unsigned long vaddr = tr->linear_address;
3667 gpa_t gpa;
3668
3669 vcpu_load(vcpu);
72dc67a6 3670 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3671 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3672 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3673 tr->physical_address = gpa;
3674 tr->valid = gpa != UNMAPPED_GVA;
3675 tr->writeable = 1;
3676 tr->usermode = 0;
8b006791
ZX		 3677 vcpu_put(vcpu);
3678
3679 return 0;
3680}
3681
d0752060
HB		 3682int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3683{
ad312c7c 3684 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3685
3686 vcpu_load(vcpu);
3687
3688 memcpy(fpu->fpr, fxsave->st_space, 128);
3689 fpu->fcw = fxsave->cwd;
3690 fpu->fsw = fxsave->swd;
3691 fpu->ftwx = fxsave->twd;
3692 fpu->last_opcode = fxsave->fop;
3693 fpu->last_ip = fxsave->rip;
3694 fpu->last_dp = fxsave->rdp;
3695 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3696
3697 vcpu_put(vcpu);
3698
3699 return 0;
3700}
3701
3702int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3703{
ad312c7c 3704 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3705
3706 vcpu_load(vcpu);
3707
3708 memcpy(fxsave->st_space, fpu->fpr, 128);
3709 fxsave->cwd = fpu->fcw;
3710 fxsave->swd = fpu->fsw;
3711 fxsave->twd = fpu->ftwx;
3712 fxsave->fop = fpu->last_opcode;
3713 fxsave->rip = fpu->last_ip;
3714 fxsave->rdp = fpu->last_dp;
3715 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3716
3717 vcpu_put(vcpu);
3718
3719 return 0;
3720}
3721
3722void fx_init(struct kvm_vcpu *vcpu)
3723{
3724 unsigned after_mxcsr_mask;
3725
bc1a34f1
AA		 3726 /*
3727 * Touch the fpu the first time in non atomic context as if
3728 * this is the first fpu instruction the exception handler
3729 * will fire before the instruction returns and it'll have to
3730 * allocate ram with GFP_KERNEL.
3731 */
3732 if (!used_math())
3733 fx_save(&vcpu->arch.host_fx_image);
3734
d0752060
HB		 3735 /* Initialize guest FPU by resetting ours and saving into guest's */
3736 preempt_disable();
ad312c7c 3737 fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3738 fx_finit();
ad312c7c
ZX		 3739 fx_save(&vcpu->arch.guest_fx_image);
3740 fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3741 preempt_enable();
3742
ad312c7c 3743 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3744 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3745 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3746 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3747 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3748}
3749EXPORT_SYMBOL_GPL(fx_init);
3750
3751void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3752{
3753 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3754 return;
3755
3756 vcpu->guest_fpu_loaded = 1;
ad312c7c
ZX		 3757 fx_save(&vcpu->arch.host_fx_image);
3758 fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3759}
3760EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3761
3762void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3763{
3764 if (!vcpu->guest_fpu_loaded)
3765 return;
3766
3767 vcpu->guest_fpu_loaded = 0;
ad312c7c
ZX		 3768 fx_save(&vcpu->arch.guest_fx_image);
3769 fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3770 ++vcpu->stat.fpu_reload;
d0752060
HB		 3771}
3772EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3773
3774void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3775{
3776 kvm_x86_ops->vcpu_free(vcpu);
3777}
3778
3779struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3780 unsigned int id)
3781{
26e5215f
AK		 3782 return kvm_x86_ops->vcpu_create(kvm, id);
3783}
e9b11c17 3784
26e5215f
AK		 3785int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3786{
3787 int r;
e9b11c17
ZX		 3788
3789 /* We do fxsave: this must be aligned. */
ad312c7c 3790 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3791
3792 vcpu_load(vcpu);
3793 r = kvm_arch_vcpu_reset(vcpu);
3794 if (r == 0)
3795 r = kvm_mmu_setup(vcpu);
3796 vcpu_put(vcpu);
3797 if (r < 0)
3798 goto free_vcpu;
3799
26e5215f 3800 return 0;
e9b11c17
ZX		 3801free_vcpu:
3802 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3803 return r;
e9b11c17
ZX		 3804}
3805
d40ccc62 3806void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3807{
3808 vcpu_load(vcpu);
3809 kvm_mmu_unload(vcpu);
3810 vcpu_put(vcpu);
3811
3812 kvm_x86_ops->vcpu_free(vcpu);
3813}
3814
3815int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3816{
3817 return kvm_x86_ops->vcpu_reset(vcpu);
3818}
3819
3820void kvm_arch_hardware_enable(void *garbage)
3821{
3822 kvm_x86_ops->hardware_enable(garbage);
3823}
3824
3825void kvm_arch_hardware_disable(void *garbage)
3826{
3827 kvm_x86_ops->hardware_disable(garbage);
3828}
3829
3830int kvm_arch_hardware_setup(void)
3831{
3832 return kvm_x86_ops->hardware_setup();
3833}
3834
3835void kvm_arch_hardware_unsetup(void)
3836{
3837 kvm_x86_ops->hardware_unsetup();
3838}
3839
3840void kvm_arch_check_processor_compat(void *rtn)
3841{
3842 kvm_x86_ops->check_processor_compatibility(rtn);
3843}
3844
3845int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3846{
3847 struct page *page;
3848 struct kvm *kvm;
3849 int r;
3850
3851 BUG_ON(vcpu->kvm == NULL);
3852 kvm = vcpu->kvm;
3853
ad312c7c 3854 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3855 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 3856 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 3857 else
a4535290 3858 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3859
3860 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3861 if (!page) {
3862 r = -ENOMEM;
3863 goto fail;
3864 }
ad312c7c 3865 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3866
3867 r = kvm_mmu_create(vcpu);
3868 if (r < 0)
3869 goto fail_free_pio_data;
3870
3871 if (irqchip_in_kernel(kvm)) {
3872 r = kvm_create_lapic(vcpu);
3873 if (r < 0)
3874 goto fail_mmu_destroy;
3875 }
3876
3877 return 0;
3878
3879fail_mmu_destroy:
3880 kvm_mmu_destroy(vcpu);
3881fail_free_pio_data:
ad312c7c 3882 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3883fail:
3884 return r;
3885}
3886
3887void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3888{
3889 kvm_free_lapic(vcpu);
3200f405 3890 down_read(&vcpu->kvm->slots_lock);
e9b11c17 3891 kvm_mmu_destroy(vcpu);
3200f405 3892 up_read(&vcpu->kvm->slots_lock);
ad312c7c 3893 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3894}
d19a9cd2
ZX		 3895
3896struct kvm *kvm_arch_create_vm(void)
3897{
3898 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3899
3900 if (!kvm)
3901 return ERR_PTR(-ENOMEM);
3902
f05e70ac 3903 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3904
3905 return kvm;
3906}
3907
3908static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3909{
3910 vcpu_load(vcpu);
3911 kvm_mmu_unload(vcpu);
3912 vcpu_put(vcpu);
3913}
3914
3915static void kvm_free_vcpus(struct kvm *kvm)
3916{
3917 unsigned int i;
3918
3919 /*
3920 * Unpin any mmu pages first.
3921 */
3922 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3923 if (kvm->vcpus[i])
3924 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3925 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3926 if (kvm->vcpus[i]) {
3927 kvm_arch_vcpu_free(kvm->vcpus[i]);
3928 kvm->vcpus[i] = NULL;
3929 }
3930 }
3931
3932}
3933
3934void kvm_arch_destroy_vm(struct kvm *kvm)
3935{
7837699f 3936 kvm_free_pit(kvm);
d7deeeb0
ZX		 3937 kfree(kvm->arch.vpic);
3938 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3939 kvm_free_vcpus(kvm);
3940 kvm_free_physmem(kvm);
3d45830c
AK		 3941 if (kvm->arch.apic_access_page)
3942 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 3943 if (kvm->arch.ept_identity_pagetable)
3944 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 3945 kfree(kvm);
3946}
0de10343
ZX		 3947
3948int kvm_arch_set_memory_region(struct kvm *kvm,
3949 struct kvm_userspace_memory_region *mem,
3950 struct kvm_memory_slot old,
3951 int user_alloc)
3952{
3953 int npages = mem->memory_size >> PAGE_SHIFT;
3954 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
3955
3956 /*To keep backward compatibility with older userspace,
3957 *x86 needs to hanlde !user_alloc case.
3958 */
3959 if (!user_alloc) {
3960 if (npages && !old.rmap) {
72dc67a6 3961 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3962 memslot->userspace_addr = do_mmap(NULL, 0,
3963 npages * PAGE_SIZE,
3964 PROT_READ | PROT_WRITE,
3965 MAP_SHARED | MAP_ANONYMOUS,
3966 0);
72dc67a6 3967 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3968
3969 if (IS_ERR((void *)memslot->userspace_addr))
3970 return PTR_ERR((void *)memslot->userspace_addr);
3971 } else {
3972 if (!old.user_alloc && old.rmap) {
3973 int ret;
3974
72dc67a6 3975 down_write(&current->mm->mmap_sem);
0de10343
ZX		 3976 ret = do_munmap(current->mm, old.userspace_addr,
3977 old.npages * PAGE_SIZE);
72dc67a6 3978 up_write(&current->mm->mmap_sem);
0de10343
ZX		 3979 if (ret < 0)
3980 printk(KERN_WARNING
3981 "kvm_vm_ioctl_set_memory_region: "
3982 "failed to munmap memory\n");
3983 }
3984 }
3985 }
3986
f05e70ac 3987 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 3988 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
3989 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
3990 }
3991
3992 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3993 kvm_flush_remote_tlbs(kvm);
3994
3995 return 0;
3996}
1d737c8a
ZX		 3997
3998int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
3999{
a4535290
AK		 4000 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4001 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4002}
5736199a
ZX		 4003
4004static void vcpu_kick_intr(void *info)
4005{
4006#ifdef DEBUG
4007 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4008 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4009#endif
4010}
4011
4012void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4013{
4014 int ipi_pcpu = vcpu->cpu;
e9571ed5 4015 int cpu = get_cpu();
5736199a
ZX		 4016
4017 if (waitqueue_active(&vcpu->wq)) {
4018 wake_up_interruptible(&vcpu->wq);
4019 ++vcpu->stat.halt_wakeup;
4020 }
e9571ed5
MT		 4021 /*
4022 * We may be called synchronously with irqs disabled in guest mode,
4023 * So need not to call smp_call_function_single() in that case.
4024 */
4025 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4026 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4027 put_cpu();
5736199a 4028}
Linux kernel - Deliverables
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