Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
313a3dc7 | 30 | |
18068523 | 31 | #include <linux/clocksource.h> |
4d5c5d0f | 32 | #include <linux/interrupt.h> |
313a3dc7 CO |
33 | #include <linux/kvm.h> |
34 | #include <linux/fs.h> | |
35 | #include <linux/vmalloc.h> | |
5fb76f9b | 36 | #include <linux/module.h> |
0de10343 | 37 | #include <linux/mman.h> |
2bacc55c | 38 | #include <linux/highmem.h> |
19de40a8 | 39 | #include <linux/iommu.h> |
62c476c7 | 40 | #include <linux/intel-iommu.h> |
c8076604 | 41 | #include <linux/cpufreq.h> |
18863bdd | 42 | #include <linux/user-return-notifier.h> |
a983fb23 | 43 | #include <linux/srcu.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
ff9d07a0 | 45 | #include <linux/perf_event.h> |
7bee342a | 46 | #include <linux/uaccess.h> |
af585b92 | 47 | #include <linux/hash.h> |
a1b60c1c | 48 | #include <linux/pci.h> |
16e8d74d MT |
49 | #include <linux/timekeeper_internal.h> |
50 | #include <linux/pvclock_gtod.h> | |
aec51dc4 | 51 | #include <trace/events/kvm.h> |
2ed152af | 52 | |
229456fc MT |
53 | #define CREATE_TRACE_POINTS |
54 | #include "trace.h" | |
043405e1 | 55 | |
24f1e32c | 56 | #include <asm/debugreg.h> |
d825ed0a | 57 | #include <asm/msr.h> |
a5f61300 | 58 | #include <asm/desc.h> |
0bed3b56 | 59 | #include <asm/mtrr.h> |
890ca9ae | 60 | #include <asm/mce.h> |
7cf30855 | 61 | #include <asm/i387.h> |
1361b83a | 62 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 63 | #include <asm/xcr.h> |
1d5f066e | 64 | #include <asm/pvclock.h> |
217fc9cf | 65 | #include <asm/div64.h> |
043405e1 | 66 | |
313a3dc7 | 67 | #define MAX_IO_MSRS 256 |
890ca9ae | 68 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 69 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 70 | |
0f65dd70 AK |
71 | #define emul_to_vcpu(ctxt) \ |
72 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
73 | ||
50a37eb4 JR |
74 | /* EFER defaults: |
75 | * - enable syscall per default because its emulated by KVM | |
76 | * - enable LME and LMA per default on 64 bit KVM | |
77 | */ | |
78 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
79 | static |
80 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 81 | #else |
1260edbe | 82 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 83 | #endif |
313a3dc7 | 84 | |
ba1389b7 AK |
85 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
86 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 87 | |
cb142eb7 | 88 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 89 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 90 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
674eea0f | 91 | |
97896d04 | 92 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 93 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 94 | |
476bc001 RR |
95 | static bool ignore_msrs = 0; |
96 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 97 | |
9ed96e87 MT |
98 | unsigned int min_timer_period_us = 500; |
99 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
100 | ||
92a1f12d JR |
101 | bool kvm_has_tsc_control; |
102 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
103 | u32 kvm_max_guest_tsc_khz; | |
104 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
105 | ||
cc578287 ZA |
106 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
107 | static u32 tsc_tolerance_ppm = 250; | |
108 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
109 | ||
16a96021 MT |
110 | static bool backwards_tsc_observed = false; |
111 | ||
18863bdd AK |
112 | #define KVM_NR_SHARED_MSRS 16 |
113 | ||
114 | struct kvm_shared_msrs_global { | |
115 | int nr; | |
2bf78fa7 | 116 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
117 | }; |
118 | ||
119 | struct kvm_shared_msrs { | |
120 | struct user_return_notifier urn; | |
121 | bool registered; | |
2bf78fa7 SY |
122 | struct kvm_shared_msr_values { |
123 | u64 host; | |
124 | u64 curr; | |
125 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
126 | }; |
127 | ||
128 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 129 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 130 | |
417bc304 | 131 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
132 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
133 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
134 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
135 | { "invlpg", VCPU_STAT(invlpg) }, | |
136 | { "exits", VCPU_STAT(exits) }, | |
137 | { "io_exits", VCPU_STAT(io_exits) }, | |
138 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
139 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
140 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 141 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
142 | { "halt_exits", VCPU_STAT(halt_exits) }, |
143 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 144 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
145 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
146 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
147 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
148 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
149 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
150 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
151 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 152 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 153 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
154 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
155 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
156 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
157 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
158 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
159 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 160 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 161 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 162 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 163 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
164 | { NULL } |
165 | }; | |
166 | ||
2acf923e DC |
167 | u64 __read_mostly host_xcr0; |
168 | ||
b6785def | 169 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 170 | |
af585b92 GN |
171 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
172 | { | |
173 | int i; | |
174 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
175 | vcpu->arch.apf.gfns[i] = ~0; | |
176 | } | |
177 | ||
18863bdd AK |
178 | static void kvm_on_user_return(struct user_return_notifier *urn) |
179 | { | |
180 | unsigned slot; | |
18863bdd AK |
181 | struct kvm_shared_msrs *locals |
182 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 183 | struct kvm_shared_msr_values *values; |
18863bdd AK |
184 | |
185 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
186 | values = &locals->values[slot]; |
187 | if (values->host != values->curr) { | |
188 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
189 | values->curr = values->host; | |
18863bdd AK |
190 | } |
191 | } | |
192 | locals->registered = false; | |
193 | user_return_notifier_unregister(urn); | |
194 | } | |
195 | ||
2bf78fa7 | 196 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 197 | { |
18863bdd | 198 | u64 value; |
013f6a5d MT |
199 | unsigned int cpu = smp_processor_id(); |
200 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 201 | |
2bf78fa7 SY |
202 | /* only read, and nobody should modify it at this time, |
203 | * so don't need lock */ | |
204 | if (slot >= shared_msrs_global.nr) { | |
205 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
206 | return; | |
207 | } | |
208 | rdmsrl_safe(msr, &value); | |
209 | smsr->values[slot].host = value; | |
210 | smsr->values[slot].curr = value; | |
211 | } | |
212 | ||
213 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
214 | { | |
0123be42 | 215 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
18863bdd AK |
216 | if (slot >= shared_msrs_global.nr) |
217 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
218 | shared_msrs_global.msrs[slot] = msr; |
219 | /* we need ensured the shared_msr_global have been updated */ | |
220 | smp_wmb(); | |
18863bdd AK |
221 | } |
222 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
223 | ||
224 | static void kvm_shared_msr_cpu_online(void) | |
225 | { | |
226 | unsigned i; | |
18863bdd AK |
227 | |
228 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 229 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
230 | } |
231 | ||
8b3c3104 | 232 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 233 | { |
013f6a5d MT |
234 | unsigned int cpu = smp_processor_id(); |
235 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 236 | int err; |
18863bdd | 237 | |
2bf78fa7 | 238 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 239 | return 0; |
2bf78fa7 | 240 | smsr->values[slot].curr = value; |
8b3c3104 AH |
241 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
242 | if (err) | |
243 | return 1; | |
244 | ||
18863bdd AK |
245 | if (!smsr->registered) { |
246 | smsr->urn.on_user_return = kvm_on_user_return; | |
247 | user_return_notifier_register(&smsr->urn); | |
248 | smsr->registered = true; | |
249 | } | |
8b3c3104 | 250 | return 0; |
18863bdd AK |
251 | } |
252 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
253 | ||
13a34e06 | 254 | static void drop_user_return_notifiers(void) |
3548bab5 | 255 | { |
013f6a5d MT |
256 | unsigned int cpu = smp_processor_id(); |
257 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
258 | |
259 | if (smsr->registered) | |
260 | kvm_on_user_return(&smsr->urn); | |
261 | } | |
262 | ||
6866b83e CO |
263 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
264 | { | |
8a5a87d9 | 265 | return vcpu->arch.apic_base; |
6866b83e CO |
266 | } |
267 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
268 | ||
58cb628d JK |
269 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
270 | { | |
271 | u64 old_state = vcpu->arch.apic_base & | |
272 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
273 | u64 new_state = msr_info->data & | |
274 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
275 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | | |
276 | 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); | |
277 | ||
278 | if (!msr_info->host_initiated && | |
279 | ((msr_info->data & reserved_bits) != 0 || | |
280 | new_state == X2APIC_ENABLE || | |
281 | (new_state == MSR_IA32_APICBASE_ENABLE && | |
282 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || | |
283 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
284 | old_state == 0))) | |
285 | return 1; | |
286 | ||
287 | kvm_lapic_set_base(vcpu, msr_info->data); | |
288 | return 0; | |
6866b83e CO |
289 | } |
290 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
291 | ||
2605fc21 | 292 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
293 | { |
294 | /* Fault while not rebooting. We want the trace. */ | |
295 | BUG(); | |
296 | } | |
297 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
298 | ||
3fd28fce ED |
299 | #define EXCPT_BENIGN 0 |
300 | #define EXCPT_CONTRIBUTORY 1 | |
301 | #define EXCPT_PF 2 | |
302 | ||
303 | static int exception_class(int vector) | |
304 | { | |
305 | switch (vector) { | |
306 | case PF_VECTOR: | |
307 | return EXCPT_PF; | |
308 | case DE_VECTOR: | |
309 | case TS_VECTOR: | |
310 | case NP_VECTOR: | |
311 | case SS_VECTOR: | |
312 | case GP_VECTOR: | |
313 | return EXCPT_CONTRIBUTORY; | |
314 | default: | |
315 | break; | |
316 | } | |
317 | return EXCPT_BENIGN; | |
318 | } | |
319 | ||
d6e8c854 NA |
320 | #define EXCPT_FAULT 0 |
321 | #define EXCPT_TRAP 1 | |
322 | #define EXCPT_ABORT 2 | |
323 | #define EXCPT_INTERRUPT 3 | |
324 | ||
325 | static int exception_type(int vector) | |
326 | { | |
327 | unsigned int mask; | |
328 | ||
329 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
330 | return EXCPT_INTERRUPT; | |
331 | ||
332 | mask = 1 << vector; | |
333 | ||
334 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
335 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
336 | return EXCPT_TRAP; | |
337 | ||
338 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
339 | return EXCPT_ABORT; | |
340 | ||
341 | /* Reserved exceptions will result in fault */ | |
342 | return EXCPT_FAULT; | |
343 | } | |
344 | ||
3fd28fce | 345 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
346 | unsigned nr, bool has_error, u32 error_code, |
347 | bool reinject) | |
3fd28fce ED |
348 | { |
349 | u32 prev_nr; | |
350 | int class1, class2; | |
351 | ||
3842d135 AK |
352 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
353 | ||
3fd28fce ED |
354 | if (!vcpu->arch.exception.pending) { |
355 | queue: | |
3ffb2468 NA |
356 | if (has_error && !is_protmode(vcpu)) |
357 | has_error = false; | |
3fd28fce ED |
358 | vcpu->arch.exception.pending = true; |
359 | vcpu->arch.exception.has_error_code = has_error; | |
360 | vcpu->arch.exception.nr = nr; | |
361 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 362 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
363 | return; |
364 | } | |
365 | ||
366 | /* to check exception */ | |
367 | prev_nr = vcpu->arch.exception.nr; | |
368 | if (prev_nr == DF_VECTOR) { | |
369 | /* triple fault -> shutdown */ | |
a8eeb04a | 370 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
371 | return; |
372 | } | |
373 | class1 = exception_class(prev_nr); | |
374 | class2 = exception_class(nr); | |
375 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
376 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
377 | /* generate double fault per SDM Table 5-5 */ | |
378 | vcpu->arch.exception.pending = true; | |
379 | vcpu->arch.exception.has_error_code = true; | |
380 | vcpu->arch.exception.nr = DF_VECTOR; | |
381 | vcpu->arch.exception.error_code = 0; | |
382 | } else | |
383 | /* replace previous exception with a new one in a hope | |
384 | that instruction re-execution will regenerate lost | |
385 | exception */ | |
386 | goto queue; | |
387 | } | |
388 | ||
298101da AK |
389 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
390 | { | |
ce7ddec4 | 391 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
392 | } |
393 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
394 | ||
ce7ddec4 JR |
395 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
396 | { | |
397 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
398 | } | |
399 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
400 | ||
db8fcefa | 401 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 402 | { |
db8fcefa AP |
403 | if (err) |
404 | kvm_inject_gp(vcpu, 0); | |
405 | else | |
406 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
407 | } | |
408 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 409 | |
6389ee94 | 410 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
411 | { |
412 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
413 | vcpu->arch.cr2 = fault->address; |
414 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 415 | } |
27d6c865 | 416 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 417 | |
ef54bcfe | 418 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 419 | { |
6389ee94 AK |
420 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
421 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 422 | else |
6389ee94 | 423 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
424 | |
425 | return fault->nested_page_fault; | |
d4f8cf66 JR |
426 | } |
427 | ||
3419ffc8 SY |
428 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
429 | { | |
7460fb4a AK |
430 | atomic_inc(&vcpu->arch.nmi_queued); |
431 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
432 | } |
433 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
434 | ||
298101da AK |
435 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
436 | { | |
ce7ddec4 | 437 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
438 | } |
439 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
440 | ||
ce7ddec4 JR |
441 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
442 | { | |
443 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
444 | } | |
445 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
446 | ||
0a79b009 AK |
447 | /* |
448 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
449 | * a #GP and return false. | |
450 | */ | |
451 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 452 | { |
0a79b009 AK |
453 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
454 | return true; | |
455 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
456 | return false; | |
298101da | 457 | } |
0a79b009 | 458 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 459 | |
16f8a6f9 NA |
460 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
461 | { | |
462 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
463 | return true; | |
464 | ||
465 | kvm_queue_exception(vcpu, UD_VECTOR); | |
466 | return false; | |
467 | } | |
468 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
469 | ||
ec92fe44 JR |
470 | /* |
471 | * This function will be used to read from the physical memory of the currently | |
472 | * running guest. The difference to kvm_read_guest_page is that this function | |
473 | * can read from guest physical or from the guest's guest physical memory. | |
474 | */ | |
475 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
476 | gfn_t ngfn, void *data, int offset, int len, | |
477 | u32 access) | |
478 | { | |
54987b7a | 479 | struct x86_exception exception; |
ec92fe44 JR |
480 | gfn_t real_gfn; |
481 | gpa_t ngpa; | |
482 | ||
483 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 484 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
485 | if (real_gfn == UNMAPPED_GVA) |
486 | return -EFAULT; | |
487 | ||
488 | real_gfn = gpa_to_gfn(real_gfn); | |
489 | ||
490 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
491 | } | |
492 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
493 | ||
3d06b8bf JR |
494 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
495 | void *data, int offset, int len, u32 access) | |
496 | { | |
497 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
498 | data, offset, len, access); | |
499 | } | |
500 | ||
a03490ed CO |
501 | /* |
502 | * Load the pae pdptrs. Return true is they are all valid. | |
503 | */ | |
ff03a073 | 504 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
505 | { |
506 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
507 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
508 | int i; | |
509 | int ret; | |
ff03a073 | 510 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 511 | |
ff03a073 JR |
512 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
513 | offset * sizeof(u64), sizeof(pdpte), | |
514 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
515 | if (ret < 0) { |
516 | ret = 0; | |
517 | goto out; | |
518 | } | |
519 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 520 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 521 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
522 | ret = 0; |
523 | goto out; | |
524 | } | |
525 | } | |
526 | ret = 1; | |
527 | ||
ff03a073 | 528 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
529 | __set_bit(VCPU_EXREG_PDPTR, |
530 | (unsigned long *)&vcpu->arch.regs_avail); | |
531 | __set_bit(VCPU_EXREG_PDPTR, | |
532 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 533 | out: |
a03490ed CO |
534 | |
535 | return ret; | |
536 | } | |
cc4b6871 | 537 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 538 | |
d835dfec AK |
539 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
540 | { | |
ff03a073 | 541 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 542 | bool changed = true; |
3d06b8bf JR |
543 | int offset; |
544 | gfn_t gfn; | |
d835dfec AK |
545 | int r; |
546 | ||
547 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
548 | return false; | |
549 | ||
6de4f3ad AK |
550 | if (!test_bit(VCPU_EXREG_PDPTR, |
551 | (unsigned long *)&vcpu->arch.regs_avail)) | |
552 | return true; | |
553 | ||
9f8fe504 AK |
554 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
555 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
556 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
557 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
558 | if (r < 0) |
559 | goto out; | |
ff03a073 | 560 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 561 | out: |
d835dfec AK |
562 | |
563 | return changed; | |
564 | } | |
565 | ||
49a9b07e | 566 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 567 | { |
aad82703 SY |
568 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
569 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
570 | X86_CR0_CD | X86_CR0_NW; | |
571 | ||
f9a48e6a AK |
572 | cr0 |= X86_CR0_ET; |
573 | ||
ab344828 | 574 | #ifdef CONFIG_X86_64 |
0f12244f GN |
575 | if (cr0 & 0xffffffff00000000UL) |
576 | return 1; | |
ab344828 GN |
577 | #endif |
578 | ||
579 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 580 | |
0f12244f GN |
581 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
582 | return 1; | |
a03490ed | 583 | |
0f12244f GN |
584 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
585 | return 1; | |
a03490ed CO |
586 | |
587 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
588 | #ifdef CONFIG_X86_64 | |
f6801dff | 589 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
590 | int cs_db, cs_l; |
591 | ||
0f12244f GN |
592 | if (!is_pae(vcpu)) |
593 | return 1; | |
a03490ed | 594 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
595 | if (cs_l) |
596 | return 1; | |
a03490ed CO |
597 | } else |
598 | #endif | |
ff03a073 | 599 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 600 | kvm_read_cr3(vcpu))) |
0f12244f | 601 | return 1; |
a03490ed CO |
602 | } |
603 | ||
ad756a16 MJ |
604 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
605 | return 1; | |
606 | ||
a03490ed | 607 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 608 | |
d170c419 | 609 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 610 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
611 | kvm_async_pf_hash_reset(vcpu); |
612 | } | |
e5f3f027 | 613 | |
aad82703 SY |
614 | if ((cr0 ^ old_cr0) & update_bits) |
615 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
616 | return 0; |
617 | } | |
2d3ad1f4 | 618 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 619 | |
2d3ad1f4 | 620 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 621 | { |
49a9b07e | 622 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 623 | } |
2d3ad1f4 | 624 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 625 | |
42bdf991 MT |
626 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
627 | { | |
628 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
629 | !vcpu->guest_xcr0_loaded) { | |
630 | /* kvm_set_xcr() also depends on this */ | |
631 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
632 | vcpu->guest_xcr0_loaded = 1; | |
633 | } | |
634 | } | |
635 | ||
636 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
637 | { | |
638 | if (vcpu->guest_xcr0_loaded) { | |
639 | if (vcpu->arch.xcr0 != host_xcr0) | |
640 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
641 | vcpu->guest_xcr0_loaded = 0; | |
642 | } | |
643 | } | |
644 | ||
2acf923e DC |
645 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
646 | { | |
56c103ec LJ |
647 | u64 xcr0 = xcr; |
648 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 649 | u64 valid_bits; |
2acf923e DC |
650 | |
651 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
652 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
653 | return 1; | |
2acf923e DC |
654 | if (!(xcr0 & XSTATE_FP)) |
655 | return 1; | |
656 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
657 | return 1; | |
46c34cb0 PB |
658 | |
659 | /* | |
660 | * Do not allow the guest to set bits that we do not support | |
661 | * saving. However, xcr0 bit 0 is always set, even if the | |
662 | * emulated CPU does not support XSAVE (see fx_init). | |
663 | */ | |
664 | valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; | |
665 | if (xcr0 & ~valid_bits) | |
2acf923e | 666 | return 1; |
46c34cb0 | 667 | |
390bd528 LJ |
668 | if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) |
669 | return 1; | |
670 | ||
612263b3 CP |
671 | if (xcr0 & XSTATE_AVX512) { |
672 | if (!(xcr0 & XSTATE_YMM)) | |
673 | return 1; | |
674 | if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) | |
675 | return 1; | |
676 | } | |
42bdf991 | 677 | kvm_put_guest_xcr0(vcpu); |
2acf923e | 678 | vcpu->arch.xcr0 = xcr0; |
56c103ec LJ |
679 | |
680 | if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) | |
681 | kvm_update_cpuid(vcpu); | |
2acf923e DC |
682 | return 0; |
683 | } | |
684 | ||
685 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
686 | { | |
764bcbc5 Z |
687 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
688 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
689 | kvm_inject_gp(vcpu, 0); |
690 | return 1; | |
691 | } | |
692 | return 0; | |
693 | } | |
694 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
695 | ||
a83b29c6 | 696 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 697 | { |
fc78f519 | 698 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
c68b734f YW |
699 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | |
700 | X86_CR4_PAE | X86_CR4_SMEP; | |
0f12244f GN |
701 | if (cr4 & CR4_RESERVED_BITS) |
702 | return 1; | |
a03490ed | 703 | |
2acf923e DC |
704 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
705 | return 1; | |
706 | ||
c68b734f YW |
707 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
708 | return 1; | |
709 | ||
97ec8c06 FW |
710 | if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) |
711 | return 1; | |
712 | ||
afcbf13f | 713 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) |
74dc2b4f YW |
714 | return 1; |
715 | ||
a03490ed | 716 | if (is_long_mode(vcpu)) { |
0f12244f GN |
717 | if (!(cr4 & X86_CR4_PAE)) |
718 | return 1; | |
a2edf57f AK |
719 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
720 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
721 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
722 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
723 | return 1; |
724 | ||
ad756a16 MJ |
725 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
726 | if (!guest_cpuid_has_pcid(vcpu)) | |
727 | return 1; | |
728 | ||
729 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
730 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
731 | return 1; | |
732 | } | |
733 | ||
5e1746d6 | 734 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 735 | return 1; |
a03490ed | 736 | |
ad756a16 MJ |
737 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
738 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 739 | kvm_mmu_reset_context(vcpu); |
0f12244f | 740 | |
97ec8c06 FW |
741 | if ((cr4 ^ old_cr4) & X86_CR4_SMAP) |
742 | update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); | |
743 | ||
2acf923e | 744 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 745 | kvm_update_cpuid(vcpu); |
2acf923e | 746 | |
0f12244f GN |
747 | return 0; |
748 | } | |
2d3ad1f4 | 749 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 750 | |
2390218b | 751 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 752 | { |
ac146235 | 753 | #ifdef CONFIG_X86_64 |
9d88fca7 | 754 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 755 | #endif |
9d88fca7 | 756 | |
9f8fe504 | 757 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 758 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 759 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 760 | return 0; |
d835dfec AK |
761 | } |
762 | ||
a03490ed | 763 | if (is_long_mode(vcpu)) { |
d9f89b88 JK |
764 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
765 | return 1; | |
766 | } else if (is_pae(vcpu) && is_paging(vcpu) && | |
767 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 768 | return 1; |
a03490ed | 769 | |
0f12244f | 770 | vcpu->arch.cr3 = cr3; |
aff48baa | 771 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 772 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
773 | return 0; |
774 | } | |
2d3ad1f4 | 775 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 776 | |
eea1cff9 | 777 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 778 | { |
0f12244f GN |
779 | if (cr8 & CR8_RESERVED_BITS) |
780 | return 1; | |
a03490ed CO |
781 | if (irqchip_in_kernel(vcpu->kvm)) |
782 | kvm_lapic_set_tpr(vcpu, cr8); | |
783 | else | |
ad312c7c | 784 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
785 | return 0; |
786 | } | |
2d3ad1f4 | 787 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 788 | |
2d3ad1f4 | 789 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
790 | { |
791 | if (irqchip_in_kernel(vcpu->kvm)) | |
792 | return kvm_lapic_get_cr8(vcpu); | |
793 | else | |
ad312c7c | 794 | return vcpu->arch.cr8; |
a03490ed | 795 | } |
2d3ad1f4 | 796 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 797 | |
73aaf249 JK |
798 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
799 | { | |
800 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
801 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
802 | } | |
803 | ||
c8639010 JK |
804 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
805 | { | |
806 | unsigned long dr7; | |
807 | ||
808 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
809 | dr7 = vcpu->arch.guest_debug_dr7; | |
810 | else | |
811 | dr7 = vcpu->arch.dr7; | |
812 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
813 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
814 | if (dr7 & DR7_BP_EN_MASK) | |
815 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
816 | } |
817 | ||
6f43ed01 NA |
818 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
819 | { | |
820 | u64 fixed = DR6_FIXED_1; | |
821 | ||
822 | if (!guest_cpuid_has_rtm(vcpu)) | |
823 | fixed |= DR6_RTM; | |
824 | return fixed; | |
825 | } | |
826 | ||
338dbc97 | 827 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
828 | { |
829 | switch (dr) { | |
830 | case 0 ... 3: | |
831 | vcpu->arch.db[dr] = val; | |
832 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
833 | vcpu->arch.eff_db[dr] = val; | |
834 | break; | |
835 | case 4: | |
020df079 GN |
836 | /* fall through */ |
837 | case 6: | |
338dbc97 GN |
838 | if (val & 0xffffffff00000000ULL) |
839 | return -1; /* #GP */ | |
6f43ed01 | 840 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 841 | kvm_update_dr6(vcpu); |
020df079 GN |
842 | break; |
843 | case 5: | |
020df079 GN |
844 | /* fall through */ |
845 | default: /* 7 */ | |
338dbc97 GN |
846 | if (val & 0xffffffff00000000ULL) |
847 | return -1; /* #GP */ | |
020df079 | 848 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 849 | kvm_update_dr7(vcpu); |
020df079 GN |
850 | break; |
851 | } | |
852 | ||
853 | return 0; | |
854 | } | |
338dbc97 GN |
855 | |
856 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
857 | { | |
16f8a6f9 | 858 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 859 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
860 | return 1; |
861 | } | |
862 | return 0; | |
338dbc97 | 863 | } |
020df079 GN |
864 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
865 | ||
16f8a6f9 | 866 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
867 | { |
868 | switch (dr) { | |
869 | case 0 ... 3: | |
870 | *val = vcpu->arch.db[dr]; | |
871 | break; | |
872 | case 4: | |
020df079 GN |
873 | /* fall through */ |
874 | case 6: | |
73aaf249 JK |
875 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
876 | *val = vcpu->arch.dr6; | |
877 | else | |
878 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
879 | break; |
880 | case 5: | |
020df079 GN |
881 | /* fall through */ |
882 | default: /* 7 */ | |
883 | *val = vcpu->arch.dr7; | |
884 | break; | |
885 | } | |
338dbc97 GN |
886 | return 0; |
887 | } | |
020df079 GN |
888 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
889 | ||
022cd0e8 AK |
890 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
891 | { | |
892 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
893 | u64 data; | |
894 | int err; | |
895 | ||
896 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
897 | if (err) | |
898 | return err; | |
899 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
900 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
901 | return err; | |
902 | } | |
903 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
904 | ||
043405e1 CO |
905 | /* |
906 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
907 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
908 | * | |
909 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
910 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
911 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 912 | */ |
e3267cbb | 913 | |
e984097b | 914 | #define KVM_SAVE_MSRS_BEGIN 12 |
043405e1 | 915 | static u32 msrs_to_save[] = { |
e3267cbb | 916 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 917 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 918 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
e984097b | 919 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, |
c9aaa895 | 920 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
ae7a2a3f | 921 | MSR_KVM_PV_EOI_EN, |
043405e1 | 922 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 923 | MSR_STAR, |
043405e1 CO |
924 | #ifdef CONFIG_X86_64 |
925 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
926 | #endif | |
b3897a49 | 927 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
0dd376e7 | 928 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS |
043405e1 CO |
929 | }; |
930 | ||
931 | static unsigned num_msrs_to_save; | |
932 | ||
f1d24831 | 933 | static const u32 emulated_msrs[] = { |
ba904635 | 934 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 935 | MSR_IA32_TSCDEADLINE, |
043405e1 | 936 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
937 | MSR_IA32_MCG_STATUS, |
938 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
939 | }; |
940 | ||
384bb783 | 941 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 942 | { |
b69e8cae | 943 | if (efer & efer_reserved_bits) |
384bb783 | 944 | return false; |
15c4a640 | 945 | |
1b2fd70c AG |
946 | if (efer & EFER_FFXSR) { |
947 | struct kvm_cpuid_entry2 *feat; | |
948 | ||
949 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 950 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 951 | return false; |
1b2fd70c AG |
952 | } |
953 | ||
d8017474 AG |
954 | if (efer & EFER_SVME) { |
955 | struct kvm_cpuid_entry2 *feat; | |
956 | ||
957 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 958 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 959 | return false; |
d8017474 AG |
960 | } |
961 | ||
384bb783 JK |
962 | return true; |
963 | } | |
964 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
965 | ||
966 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
967 | { | |
968 | u64 old_efer = vcpu->arch.efer; | |
969 | ||
970 | if (!kvm_valid_efer(vcpu, efer)) | |
971 | return 1; | |
972 | ||
973 | if (is_paging(vcpu) | |
974 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
975 | return 1; | |
976 | ||
15c4a640 | 977 | efer &= ~EFER_LMA; |
f6801dff | 978 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 979 | |
a3d204e2 SY |
980 | kvm_x86_ops->set_efer(vcpu, efer); |
981 | ||
aad82703 SY |
982 | /* Update reserved bits */ |
983 | if ((efer ^ old_efer) & EFER_NX) | |
984 | kvm_mmu_reset_context(vcpu); | |
985 | ||
b69e8cae | 986 | return 0; |
15c4a640 CO |
987 | } |
988 | ||
f2b4b7dd JR |
989 | void kvm_enable_efer_bits(u64 mask) |
990 | { | |
991 | efer_reserved_bits &= ~mask; | |
992 | } | |
993 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
994 | ||
15c4a640 CO |
995 | /* |
996 | * Writes msr value into into the appropriate "register". | |
997 | * Returns 0 on success, non-0 otherwise. | |
998 | * Assumes vcpu_load() was already called. | |
999 | */ | |
8fe8ab46 | 1000 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1001 | { |
854e8bb1 NA |
1002 | switch (msr->index) { |
1003 | case MSR_FS_BASE: | |
1004 | case MSR_GS_BASE: | |
1005 | case MSR_KERNEL_GS_BASE: | |
1006 | case MSR_CSTAR: | |
1007 | case MSR_LSTAR: | |
1008 | if (is_noncanonical_address(msr->data)) | |
1009 | return 1; | |
1010 | break; | |
1011 | case MSR_IA32_SYSENTER_EIP: | |
1012 | case MSR_IA32_SYSENTER_ESP: | |
1013 | /* | |
1014 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1015 | * non-canonical address is written on Intel but not on | |
1016 | * AMD (which ignores the top 32-bits, because it does | |
1017 | * not implement 64-bit SYSENTER). | |
1018 | * | |
1019 | * 64-bit code should hence be able to write a non-canonical | |
1020 | * value on AMD. Making the address canonical ensures that | |
1021 | * vmentry does not fail on Intel after writing a non-canonical | |
1022 | * value, and that something deterministic happens if the guest | |
1023 | * invokes 64-bit SYSENTER. | |
1024 | */ | |
1025 | msr->data = get_canonical(msr->data); | |
1026 | } | |
8fe8ab46 | 1027 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1028 | } |
854e8bb1 | 1029 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1030 | |
313a3dc7 CO |
1031 | /* |
1032 | * Adapt set_msr() to msr_io()'s calling convention | |
1033 | */ | |
1034 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1035 | { | |
8fe8ab46 WA |
1036 | struct msr_data msr; |
1037 | ||
1038 | msr.data = *data; | |
1039 | msr.index = index; | |
1040 | msr.host_initiated = true; | |
1041 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1042 | } |
1043 | ||
16e8d74d MT |
1044 | #ifdef CONFIG_X86_64 |
1045 | struct pvclock_gtod_data { | |
1046 | seqcount_t seq; | |
1047 | ||
1048 | struct { /* extract of a clocksource struct */ | |
1049 | int vclock_mode; | |
1050 | cycle_t cycle_last; | |
1051 | cycle_t mask; | |
1052 | u32 mult; | |
1053 | u32 shift; | |
1054 | } clock; | |
1055 | ||
cbcf2dd3 TG |
1056 | u64 boot_ns; |
1057 | u64 nsec_base; | |
16e8d74d MT |
1058 | }; |
1059 | ||
1060 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1061 | ||
1062 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1063 | { | |
1064 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1065 | u64 boot_ns; |
1066 | ||
d28ede83 | 1067 | boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot)); |
16e8d74d MT |
1068 | |
1069 | write_seqcount_begin(&vdata->seq); | |
1070 | ||
1071 | /* copy pvclock gtod data */ | |
d28ede83 TG |
1072 | vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode; |
1073 | vdata->clock.cycle_last = tk->tkr.cycle_last; | |
1074 | vdata->clock.mask = tk->tkr.mask; | |
1075 | vdata->clock.mult = tk->tkr.mult; | |
1076 | vdata->clock.shift = tk->tkr.shift; | |
16e8d74d | 1077 | |
cbcf2dd3 | 1078 | vdata->boot_ns = boot_ns; |
d28ede83 | 1079 | vdata->nsec_base = tk->tkr.xtime_nsec; |
16e8d74d MT |
1080 | |
1081 | write_seqcount_end(&vdata->seq); | |
1082 | } | |
1083 | #endif | |
1084 | ||
1085 | ||
18068523 GOC |
1086 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1087 | { | |
9ed3c444 AK |
1088 | int version; |
1089 | int r; | |
50d0a0f9 | 1090 | struct pvclock_wall_clock wc; |
923de3cf | 1091 | struct timespec boot; |
18068523 GOC |
1092 | |
1093 | if (!wall_clock) | |
1094 | return; | |
1095 | ||
9ed3c444 AK |
1096 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1097 | if (r) | |
1098 | return; | |
1099 | ||
1100 | if (version & 1) | |
1101 | ++version; /* first time write, random junk */ | |
1102 | ||
1103 | ++version; | |
18068523 | 1104 | |
18068523 GOC |
1105 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
1106 | ||
50d0a0f9 GH |
1107 | /* |
1108 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1109 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1110 | * wall clock specified here. guest system time equals host |
1111 | * system time for us, thus we must fill in host boot time here. | |
1112 | */ | |
923de3cf | 1113 | getboottime(&boot); |
50d0a0f9 | 1114 | |
4b648665 BR |
1115 | if (kvm->arch.kvmclock_offset) { |
1116 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1117 | boot = timespec_sub(boot, ts); | |
1118 | } | |
50d0a0f9 GH |
1119 | wc.sec = boot.tv_sec; |
1120 | wc.nsec = boot.tv_nsec; | |
1121 | wc.version = version; | |
18068523 GOC |
1122 | |
1123 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1124 | ||
1125 | version++; | |
1126 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1127 | } |
1128 | ||
50d0a0f9 GH |
1129 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1130 | { | |
1131 | uint32_t quotient, remainder; | |
1132 | ||
1133 | /* Don't try to replace with do_div(), this one calculates | |
1134 | * "(dividend << 32) / divisor" */ | |
1135 | __asm__ ( "divl %4" | |
1136 | : "=a" (quotient), "=d" (remainder) | |
1137 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1138 | return quotient; | |
1139 | } | |
1140 | ||
5f4e3f88 ZA |
1141 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
1142 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 1143 | { |
5f4e3f88 | 1144 | uint64_t scaled64; |
50d0a0f9 GH |
1145 | int32_t shift = 0; |
1146 | uint64_t tps64; | |
1147 | uint32_t tps32; | |
1148 | ||
5f4e3f88 ZA |
1149 | tps64 = base_khz * 1000LL; |
1150 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 1151 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1152 | tps64 >>= 1; |
1153 | shift--; | |
1154 | } | |
1155 | ||
1156 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1157 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1158 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1159 | scaled64 >>= 1; |
1160 | else | |
1161 | tps32 <<= 1; | |
50d0a0f9 GH |
1162 | shift++; |
1163 | } | |
1164 | ||
5f4e3f88 ZA |
1165 | *pshift = shift; |
1166 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1167 | |
5f4e3f88 ZA |
1168 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
1169 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
1170 | } |
1171 | ||
759379dd ZA |
1172 | static inline u64 get_kernel_ns(void) |
1173 | { | |
bb0b5812 | 1174 | return ktime_get_boot_ns(); |
50d0a0f9 GH |
1175 | } |
1176 | ||
d828199e | 1177 | #ifdef CONFIG_X86_64 |
16e8d74d | 1178 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1179 | #endif |
16e8d74d | 1180 | |
c8076604 | 1181 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
c285545f | 1182 | unsigned long max_tsc_khz; |
c8076604 | 1183 | |
cc578287 | 1184 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1185 | { |
cc578287 ZA |
1186 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1187 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1188 | } |
1189 | ||
cc578287 | 1190 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1191 | { |
cc578287 ZA |
1192 | u64 v = (u64)khz * (1000000 + ppm); |
1193 | do_div(v, 1000000); | |
1194 | return v; | |
1e993611 JR |
1195 | } |
1196 | ||
cc578287 | 1197 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 1198 | { |
cc578287 ZA |
1199 | u32 thresh_lo, thresh_hi; |
1200 | int use_scaling = 0; | |
217fc9cf | 1201 | |
03ba32ca MT |
1202 | /* tsc_khz can be zero if TSC calibration fails */ |
1203 | if (this_tsc_khz == 0) | |
1204 | return; | |
1205 | ||
c285545f ZA |
1206 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1207 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1208 | &vcpu->arch.virtual_tsc_shift, |
1209 | &vcpu->arch.virtual_tsc_mult); | |
1210 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1211 | ||
1212 | /* | |
1213 | * Compute the variation in TSC rate which is acceptable | |
1214 | * within the range of tolerance and decide if the | |
1215 | * rate being applied is within that bounds of the hardware | |
1216 | * rate. If so, no scaling or compensation need be done. | |
1217 | */ | |
1218 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1219 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1220 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1221 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1222 | use_scaling = 1; | |
1223 | } | |
1224 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1225 | } |
1226 | ||
1227 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1228 | { | |
e26101b1 | 1229 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1230 | vcpu->arch.virtual_tsc_mult, |
1231 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1232 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1233 | return tsc; |
1234 | } | |
1235 | ||
b48aa97e MT |
1236 | void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
1237 | { | |
1238 | #ifdef CONFIG_X86_64 | |
1239 | bool vcpus_matched; | |
b48aa97e MT |
1240 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1241 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1242 | ||
1243 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1244 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1245 | ||
7f187922 MT |
1246 | /* |
1247 | * Once the masterclock is enabled, always perform request in | |
1248 | * order to update it. | |
1249 | * | |
1250 | * In order to enable masterclock, the host clocksource must be TSC | |
1251 | * and the vcpus need to have matched TSCs. When that happens, | |
1252 | * perform request to enable masterclock. | |
1253 | */ | |
1254 | if (ka->use_master_clock || | |
1255 | (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) | |
b48aa97e MT |
1256 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1257 | ||
1258 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1259 | atomic_read(&vcpu->kvm->online_vcpus), | |
1260 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1261 | #endif | |
1262 | } | |
1263 | ||
ba904635 WA |
1264 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1265 | { | |
1266 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1267 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1268 | } | |
1269 | ||
8fe8ab46 | 1270 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1271 | { |
1272 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1273 | u64 offset, ns, elapsed; |
99e3e30a | 1274 | unsigned long flags; |
02626b6a | 1275 | s64 usdiff; |
b48aa97e | 1276 | bool matched; |
0d3da0d2 | 1277 | bool already_matched; |
8fe8ab46 | 1278 | u64 data = msr->data; |
99e3e30a | 1279 | |
038f8c11 | 1280 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1281 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1282 | ns = get_kernel_ns(); |
f38e098f | 1283 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1284 | |
03ba32ca | 1285 | if (vcpu->arch.virtual_tsc_khz) { |
8915aa27 MT |
1286 | int faulted = 0; |
1287 | ||
03ba32ca MT |
1288 | /* n.b - signed multiplication and division required */ |
1289 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1290 | #ifdef CONFIG_X86_64 |
03ba32ca | 1291 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1292 | #else |
03ba32ca | 1293 | /* do_div() only does unsigned */ |
8915aa27 MT |
1294 | asm("1: idivl %[divisor]\n" |
1295 | "2: xor %%edx, %%edx\n" | |
1296 | " movl $0, %[faulted]\n" | |
1297 | "3:\n" | |
1298 | ".section .fixup,\"ax\"\n" | |
1299 | "4: movl $1, %[faulted]\n" | |
1300 | " jmp 3b\n" | |
1301 | ".previous\n" | |
1302 | ||
1303 | _ASM_EXTABLE(1b, 4b) | |
1304 | ||
1305 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1306 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1307 | ||
5d3cb0f6 | 1308 | #endif |
03ba32ca MT |
1309 | do_div(elapsed, 1000); |
1310 | usdiff -= elapsed; | |
1311 | if (usdiff < 0) | |
1312 | usdiff = -usdiff; | |
8915aa27 MT |
1313 | |
1314 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1315 | if (faulted) | |
1316 | usdiff = USEC_PER_SEC; | |
03ba32ca MT |
1317 | } else |
1318 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1319 | |
1320 | /* | |
5d3cb0f6 ZA |
1321 | * Special case: TSC write with a small delta (1 second) of virtual |
1322 | * cycle time against real time is interpreted as an attempt to | |
1323 | * synchronize the CPU. | |
1324 | * | |
1325 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1326 | * TSC, we add elapsed time in this computation. We could let the | |
1327 | * compensation code attempt to catch up if we fall behind, but | |
1328 | * it's better to try to match offsets from the beginning. | |
1329 | */ | |
02626b6a | 1330 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1331 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1332 | if (!check_tsc_unstable()) { |
e26101b1 | 1333 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1334 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1335 | } else { | |
857e4099 | 1336 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1337 | data += delta; |
1338 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1339 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1340 | } |
b48aa97e | 1341 | matched = true; |
0d3da0d2 | 1342 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1343 | } else { |
1344 | /* | |
1345 | * We split periods of matched TSC writes into generations. | |
1346 | * For each generation, we track the original measured | |
1347 | * nanosecond time, offset, and write, so if TSCs are in | |
1348 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1349 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1350 | * |
1351 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1352 | */ | |
1353 | kvm->arch.cur_tsc_generation++; | |
1354 | kvm->arch.cur_tsc_nsec = ns; | |
1355 | kvm->arch.cur_tsc_write = data; | |
1356 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1357 | matched = false; |
0d3da0d2 | 1358 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1359 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1360 | } |
e26101b1 ZA |
1361 | |
1362 | /* | |
1363 | * We also track th most recent recorded KHZ, write and time to | |
1364 | * allow the matching interval to be extended at each write. | |
1365 | */ | |
f38e098f ZA |
1366 | kvm->arch.last_tsc_nsec = ns; |
1367 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1368 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1369 | |
b183aa58 | 1370 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1371 | |
1372 | /* Keep track of which generation this VCPU has synchronized to */ | |
1373 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1374 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1375 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1376 | ||
ba904635 WA |
1377 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1378 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1379 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1380 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1381 | |
1382 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1383 | if (!matched) { |
b48aa97e | 1384 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1385 | } else if (!already_matched) { |
1386 | kvm->arch.nr_vcpus_matched_tsc++; | |
1387 | } | |
b48aa97e MT |
1388 | |
1389 | kvm_track_tsc_matching(vcpu); | |
1390 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1391 | } |
e26101b1 | 1392 | |
99e3e30a ZA |
1393 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1394 | ||
d828199e MT |
1395 | #ifdef CONFIG_X86_64 |
1396 | ||
1397 | static cycle_t read_tsc(void) | |
1398 | { | |
1399 | cycle_t ret; | |
1400 | u64 last; | |
1401 | ||
1402 | /* | |
1403 | * Empirically, a fence (of type that depends on the CPU) | |
1404 | * before rdtsc is enough to ensure that rdtsc is ordered | |
1405 | * with respect to loads. The various CPU manuals are unclear | |
1406 | * as to whether rdtsc can be reordered with later loads, | |
1407 | * but no one has ever seen it happen. | |
1408 | */ | |
1409 | rdtsc_barrier(); | |
1410 | ret = (cycle_t)vget_cycles(); | |
1411 | ||
1412 | last = pvclock_gtod_data.clock.cycle_last; | |
1413 | ||
1414 | if (likely(ret >= last)) | |
1415 | return ret; | |
1416 | ||
1417 | /* | |
1418 | * GCC likes to generate cmov here, but this branch is extremely | |
1419 | * predictable (it's just a funciton of time and the likely is | |
1420 | * very likely) and there's a data dependence, so force GCC | |
1421 | * to generate a branch instead. I don't barrier() because | |
1422 | * we don't actually need a barrier, and if this function | |
1423 | * ever gets inlined it will generate worse code. | |
1424 | */ | |
1425 | asm volatile (""); | |
1426 | return last; | |
1427 | } | |
1428 | ||
1429 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1430 | { | |
1431 | long v; | |
1432 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1433 | ||
1434 | *cycle_now = read_tsc(); | |
1435 | ||
1436 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1437 | return v * gtod->clock.mult; | |
1438 | } | |
1439 | ||
cbcf2dd3 | 1440 | static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) |
d828199e | 1441 | { |
cbcf2dd3 | 1442 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1443 | unsigned long seq; |
d828199e | 1444 | int mode; |
cbcf2dd3 | 1445 | u64 ns; |
d828199e | 1446 | |
d828199e MT |
1447 | do { |
1448 | seq = read_seqcount_begin(>od->seq); | |
1449 | mode = gtod->clock.vclock_mode; | |
cbcf2dd3 | 1450 | ns = gtod->nsec_base; |
d828199e MT |
1451 | ns += vgettsc(cycle_now); |
1452 | ns >>= gtod->clock.shift; | |
cbcf2dd3 | 1453 | ns += gtod->boot_ns; |
d828199e | 1454 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1455 | *t = ns; |
d828199e MT |
1456 | |
1457 | return mode; | |
1458 | } | |
1459 | ||
1460 | /* returns true if host is using tsc clocksource */ | |
1461 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1462 | { | |
d828199e MT |
1463 | /* checked again under seqlock below */ |
1464 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1465 | return false; | |
1466 | ||
cbcf2dd3 | 1467 | return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; |
d828199e MT |
1468 | } |
1469 | #endif | |
1470 | ||
1471 | /* | |
1472 | * | |
b48aa97e MT |
1473 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1474 | * across virtual CPUs, the following condition is possible. | |
1475 | * Each numbered line represents an event visible to both | |
d828199e MT |
1476 | * CPUs at the next numbered event. |
1477 | * | |
1478 | * "timespecX" represents host monotonic time. "tscX" represents | |
1479 | * RDTSC value. | |
1480 | * | |
1481 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1482 | * | |
1483 | * 1. read timespec0,tsc0 | |
1484 | * 2. | timespec1 = timespec0 + N | |
1485 | * | tsc1 = tsc0 + M | |
1486 | * 3. transition to guest | transition to guest | |
1487 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1488 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1489 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1490 | * | |
1491 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1492 | * | |
1493 | * - ret0 < ret1 | |
1494 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1495 | * ... | |
1496 | * - 0 < N - M => M < N | |
1497 | * | |
1498 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1499 | * always the case (the difference between two distinct xtime instances | |
1500 | * might be smaller then the difference between corresponding TSC reads, | |
1501 | * when updating guest vcpus pvclock areas). | |
1502 | * | |
1503 | * To avoid that problem, do not allow visibility of distinct | |
1504 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1505 | * copy of host monotonic time values. Update that master copy | |
1506 | * in lockstep. | |
1507 | * | |
b48aa97e | 1508 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1509 | * |
1510 | */ | |
1511 | ||
1512 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1513 | { | |
1514 | #ifdef CONFIG_X86_64 | |
1515 | struct kvm_arch *ka = &kvm->arch; | |
1516 | int vclock_mode; | |
b48aa97e MT |
1517 | bool host_tsc_clocksource, vcpus_matched; |
1518 | ||
1519 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1520 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1521 | |
1522 | /* | |
1523 | * If the host uses TSC clock, then passthrough TSC as stable | |
1524 | * to the guest. | |
1525 | */ | |
b48aa97e | 1526 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1527 | &ka->master_kernel_ns, |
1528 | &ka->master_cycle_now); | |
1529 | ||
16a96021 MT |
1530 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
1531 | && !backwards_tsc_observed; | |
b48aa97e | 1532 | |
d828199e MT |
1533 | if (ka->use_master_clock) |
1534 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1535 | ||
1536 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1537 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1538 | vcpus_matched); | |
d828199e MT |
1539 | #endif |
1540 | } | |
1541 | ||
2e762ff7 MT |
1542 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1543 | { | |
1544 | #ifdef CONFIG_X86_64 | |
1545 | int i; | |
1546 | struct kvm_vcpu *vcpu; | |
1547 | struct kvm_arch *ka = &kvm->arch; | |
1548 | ||
1549 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1550 | kvm_make_mclock_inprogress_request(kvm); | |
1551 | /* no guest entries from this point */ | |
1552 | pvclock_update_vm_gtod_copy(kvm); | |
1553 | ||
1554 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1555 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1556 | |
1557 | /* guest entries allowed */ | |
1558 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1559 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1560 | ||
1561 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1562 | #endif | |
1563 | } | |
1564 | ||
34c238a1 | 1565 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1566 | { |
d828199e | 1567 | unsigned long flags, this_tsc_khz; |
18068523 | 1568 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1569 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1570 | s64 kernel_ns; |
d828199e | 1571 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1572 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1573 | u8 pvclock_flags; |
d828199e MT |
1574 | bool use_master_clock; |
1575 | ||
1576 | kernel_ns = 0; | |
1577 | host_tsc = 0; | |
18068523 | 1578 | |
d828199e MT |
1579 | /* |
1580 | * If the host uses TSC clock, then passthrough TSC as stable | |
1581 | * to the guest. | |
1582 | */ | |
1583 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1584 | use_master_clock = ka->use_master_clock; | |
1585 | if (use_master_clock) { | |
1586 | host_tsc = ka->master_cycle_now; | |
1587 | kernel_ns = ka->master_kernel_ns; | |
1588 | } | |
1589 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1590 | |
1591 | /* Keep irq disabled to prevent changes to the clock */ | |
1592 | local_irq_save(flags); | |
89cbc767 | 1593 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
c09664bb MT |
1594 | if (unlikely(this_tsc_khz == 0)) { |
1595 | local_irq_restore(flags); | |
1596 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1597 | return 1; | |
1598 | } | |
d828199e MT |
1599 | if (!use_master_clock) { |
1600 | host_tsc = native_read_tsc(); | |
1601 | kernel_ns = get_kernel_ns(); | |
1602 | } | |
1603 | ||
1604 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); | |
1605 | ||
c285545f ZA |
1606 | /* |
1607 | * We may have to catch up the TSC to match elapsed wall clock | |
1608 | * time for two reasons, even if kvmclock is used. | |
1609 | * 1) CPU could have been running below the maximum TSC rate | |
1610 | * 2) Broken TSC compensation resets the base at each VCPU | |
1611 | * entry to avoid unknown leaps of TSC even when running | |
1612 | * again on the same CPU. This may cause apparent elapsed | |
1613 | * time to disappear, and the guest to stand still or run | |
1614 | * very slowly. | |
1615 | */ | |
1616 | if (vcpu->tsc_catchup) { | |
1617 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1618 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1619 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1620 | tsc_timestamp = tsc; |
1621 | } | |
50d0a0f9 GH |
1622 | } |
1623 | ||
18068523 GOC |
1624 | local_irq_restore(flags); |
1625 | ||
0b79459b | 1626 | if (!vcpu->pv_time_enabled) |
c285545f | 1627 | return 0; |
18068523 | 1628 | |
e48672fa | 1629 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1630 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1631 | &vcpu->hv_clock.tsc_shift, | |
1632 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1633 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1634 | } |
1635 | ||
1636 | /* With all the info we got, fill in the values */ | |
1d5f066e | 1637 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1638 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 1639 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1640 | |
09a0c3f1 OH |
1641 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1642 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1643 | return 0; | |
1644 | ||
18068523 GOC |
1645 | /* |
1646 | * The interface expects us to write an even number signaling that the | |
1647 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1648 | * state, we just increase by 2 at the end. |
18068523 | 1649 | */ |
09a0c3f1 | 1650 | vcpu->hv_clock.version = guest_hv_clock.version + 2; |
78c0337a MT |
1651 | |
1652 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1653 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1654 | |
1655 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1656 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1657 | vcpu->pvclock_set_guest_stopped_request = false; | |
1658 | } | |
1659 | ||
d828199e MT |
1660 | /* If the host uses TSC clocksource, then it is stable */ |
1661 | if (use_master_clock) | |
1662 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1663 | ||
78c0337a MT |
1664 | vcpu->hv_clock.flags = pvclock_flags; |
1665 | ||
ce1a5e60 DM |
1666 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
1667 | ||
0b79459b AH |
1668 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1669 | &vcpu->hv_clock, | |
1670 | sizeof(vcpu->hv_clock)); | |
8cfdc000 | 1671 | return 0; |
c8076604 GH |
1672 | } |
1673 | ||
0061d53d MT |
1674 | /* |
1675 | * kvmclock updates which are isolated to a given vcpu, such as | |
1676 | * vcpu->cpu migration, should not allow system_timestamp from | |
1677 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1678 | * correction applies to one vcpu's system_timestamp but not | |
1679 | * the others. | |
1680 | * | |
1681 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
1682 | * We need to rate-limit these requests though, as they can |
1683 | * considerably slow guests that have a large number of vcpus. | |
1684 | * The time for a remote vcpu to update its kvmclock is bound | |
1685 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
1686 | */ |
1687 | ||
7e44e449 AJ |
1688 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
1689 | ||
1690 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
1691 | { |
1692 | int i; | |
7e44e449 AJ |
1693 | struct delayed_work *dwork = to_delayed_work(work); |
1694 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1695 | kvmclock_update_work); | |
1696 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
1697 | struct kvm_vcpu *vcpu; |
1698 | ||
1699 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 1700 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
1701 | kvm_vcpu_kick(vcpu); |
1702 | } | |
1703 | } | |
1704 | ||
7e44e449 AJ |
1705 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
1706 | { | |
1707 | struct kvm *kvm = v->kvm; | |
1708 | ||
105b21bb | 1709 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
1710 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
1711 | KVMCLOCK_UPDATE_DELAY); | |
1712 | } | |
1713 | ||
332967a3 AJ |
1714 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
1715 | ||
1716 | static void kvmclock_sync_fn(struct work_struct *work) | |
1717 | { | |
1718 | struct delayed_work *dwork = to_delayed_work(work); | |
1719 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1720 | kvmclock_sync_work); | |
1721 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1722 | ||
1723 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); | |
1724 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
1725 | KVMCLOCK_SYNC_PERIOD); | |
1726 | } | |
1727 | ||
9ba075a6 AK |
1728 | static bool msr_mtrr_valid(unsigned msr) |
1729 | { | |
1730 | switch (msr) { | |
1731 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1732 | case MSR_MTRRfix64K_00000: | |
1733 | case MSR_MTRRfix16K_80000: | |
1734 | case MSR_MTRRfix16K_A0000: | |
1735 | case MSR_MTRRfix4K_C0000: | |
1736 | case MSR_MTRRfix4K_C8000: | |
1737 | case MSR_MTRRfix4K_D0000: | |
1738 | case MSR_MTRRfix4K_D8000: | |
1739 | case MSR_MTRRfix4K_E0000: | |
1740 | case MSR_MTRRfix4K_E8000: | |
1741 | case MSR_MTRRfix4K_F0000: | |
1742 | case MSR_MTRRfix4K_F8000: | |
1743 | case MSR_MTRRdefType: | |
1744 | case MSR_IA32_CR_PAT: | |
1745 | return true; | |
1746 | case 0x2f8: | |
1747 | return true; | |
1748 | } | |
1749 | return false; | |
1750 | } | |
1751 | ||
d6289b93 MT |
1752 | static bool valid_pat_type(unsigned t) |
1753 | { | |
1754 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1755 | } | |
1756 | ||
1757 | static bool valid_mtrr_type(unsigned t) | |
1758 | { | |
1759 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1760 | } | |
1761 | ||
4566654b | 1762 | bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
d6289b93 MT |
1763 | { |
1764 | int i; | |
fd275235 | 1765 | u64 mask; |
d6289b93 MT |
1766 | |
1767 | if (!msr_mtrr_valid(msr)) | |
1768 | return false; | |
1769 | ||
1770 | if (msr == MSR_IA32_CR_PAT) { | |
1771 | for (i = 0; i < 8; i++) | |
1772 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1773 | return false; | |
1774 | return true; | |
1775 | } else if (msr == MSR_MTRRdefType) { | |
1776 | if (data & ~0xcff) | |
1777 | return false; | |
1778 | return valid_mtrr_type(data & 0xff); | |
1779 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1780 | for (i = 0; i < 8 ; i++) | |
1781 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1782 | return false; | |
1783 | return true; | |
1784 | } | |
1785 | ||
1786 | /* variable MTRRs */ | |
adfb5d27 WL |
1787 | WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); |
1788 | ||
fd275235 | 1789 | mask = (~0ULL) << cpuid_maxphyaddr(vcpu); |
d7a2a246 | 1790 | if ((msr & 1) == 0) { |
adfb5d27 | 1791 | /* MTRR base */ |
d7a2a246 WL |
1792 | if (!valid_mtrr_type(data & 0xff)) |
1793 | return false; | |
1794 | mask |= 0xf00; | |
1795 | } else | |
1796 | /* MTRR mask */ | |
1797 | mask |= 0x7ff; | |
1798 | if (data & mask) { | |
1799 | kvm_inject_gp(vcpu, 0); | |
1800 | return false; | |
1801 | } | |
1802 | ||
adfb5d27 | 1803 | return true; |
d6289b93 | 1804 | } |
4566654b | 1805 | EXPORT_SYMBOL_GPL(kvm_mtrr_valid); |
d6289b93 | 1806 | |
9ba075a6 AK |
1807 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1808 | { | |
0bed3b56 SY |
1809 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1810 | ||
4566654b | 1811 | if (!kvm_mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1812 | return 1; |
1813 | ||
0bed3b56 SY |
1814 | if (msr == MSR_MTRRdefType) { |
1815 | vcpu->arch.mtrr_state.def_type = data; | |
1816 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1817 | } else if (msr == MSR_MTRRfix64K_00000) | |
1818 | p[0] = data; | |
1819 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1820 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1821 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1822 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1823 | else if (msr == MSR_IA32_CR_PAT) | |
1824 | vcpu->arch.pat = data; | |
1825 | else { /* Variable MTRRs */ | |
1826 | int idx, is_mtrr_mask; | |
1827 | u64 *pt; | |
1828 | ||
1829 | idx = (msr - 0x200) / 2; | |
1830 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1831 | if (!is_mtrr_mask) | |
1832 | pt = | |
1833 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1834 | else | |
1835 | pt = | |
1836 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1837 | *pt = data; | |
1838 | } | |
1839 | ||
1840 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1841 | return 0; |
1842 | } | |
15c4a640 | 1843 | |
890ca9ae | 1844 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1845 | { |
890ca9ae HY |
1846 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1847 | unsigned bank_num = mcg_cap & 0xff; | |
1848 | ||
15c4a640 | 1849 | switch (msr) { |
15c4a640 | 1850 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1851 | vcpu->arch.mcg_status = data; |
15c4a640 | 1852 | break; |
c7ac679c | 1853 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1854 | if (!(mcg_cap & MCG_CTL_P)) |
1855 | return 1; | |
1856 | if (data != 0 && data != ~(u64)0) | |
1857 | return -1; | |
1858 | vcpu->arch.mcg_ctl = data; | |
1859 | break; | |
1860 | default: | |
1861 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 1862 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 1863 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
1864 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1865 | * some Linux kernels though clear bit 10 in bank 4 to | |
1866 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1867 | * this to avoid an uncatched #GP in the guest | |
1868 | */ | |
890ca9ae | 1869 | if ((offset & 0x3) == 0 && |
114be429 | 1870 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1871 | return -1; |
1872 | vcpu->arch.mce_banks[offset] = data; | |
1873 | break; | |
1874 | } | |
1875 | return 1; | |
1876 | } | |
1877 | return 0; | |
1878 | } | |
1879 | ||
ffde22ac ES |
1880 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1881 | { | |
1882 | struct kvm *kvm = vcpu->kvm; | |
1883 | int lm = is_long_mode(vcpu); | |
1884 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1885 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1886 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1887 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1888 | u32 page_num = data & ~PAGE_MASK; | |
1889 | u64 page_addr = data & PAGE_MASK; | |
1890 | u8 *page; | |
1891 | int r; | |
1892 | ||
1893 | r = -E2BIG; | |
1894 | if (page_num >= blob_size) | |
1895 | goto out; | |
1896 | r = -ENOMEM; | |
ff5c2c03 SL |
1897 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1898 | if (IS_ERR(page)) { | |
1899 | r = PTR_ERR(page); | |
ffde22ac | 1900 | goto out; |
ff5c2c03 | 1901 | } |
ffde22ac ES |
1902 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) |
1903 | goto out_free; | |
1904 | r = 0; | |
1905 | out_free: | |
1906 | kfree(page); | |
1907 | out: | |
1908 | return r; | |
1909 | } | |
1910 | ||
55cd8e5a GN |
1911 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1912 | { | |
1913 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1914 | } | |
1915 | ||
1916 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1917 | { | |
1918 | bool r = false; | |
1919 | switch (msr) { | |
1920 | case HV_X64_MSR_GUEST_OS_ID: | |
1921 | case HV_X64_MSR_HYPERCALL: | |
e984097b VR |
1922 | case HV_X64_MSR_REFERENCE_TSC: |
1923 | case HV_X64_MSR_TIME_REF_COUNT: | |
55cd8e5a GN |
1924 | r = true; |
1925 | break; | |
1926 | } | |
1927 | ||
1928 | return r; | |
1929 | } | |
1930 | ||
1931 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1932 | { | |
1933 | struct kvm *kvm = vcpu->kvm; | |
1934 | ||
1935 | switch (msr) { | |
1936 | case HV_X64_MSR_GUEST_OS_ID: | |
1937 | kvm->arch.hv_guest_os_id = data; | |
1938 | /* setting guest os id to zero disables hypercall page */ | |
1939 | if (!kvm->arch.hv_guest_os_id) | |
1940 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1941 | break; | |
1942 | case HV_X64_MSR_HYPERCALL: { | |
1943 | u64 gfn; | |
1944 | unsigned long addr; | |
1945 | u8 instructions[4]; | |
1946 | ||
1947 | /* if guest os id is not set hypercall should remain disabled */ | |
1948 | if (!kvm->arch.hv_guest_os_id) | |
1949 | break; | |
1950 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1951 | kvm->arch.hv_hypercall = data; | |
1952 | break; | |
1953 | } | |
1954 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1955 | addr = gfn_to_hva(kvm, gfn); | |
1956 | if (kvm_is_error_hva(addr)) | |
1957 | return 1; | |
1958 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1959 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 1960 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
1961 | return 1; |
1962 | kvm->arch.hv_hypercall = data; | |
b94b64c9 | 1963 | mark_page_dirty(kvm, gfn); |
55cd8e5a GN |
1964 | break; |
1965 | } | |
e984097b VR |
1966 | case HV_X64_MSR_REFERENCE_TSC: { |
1967 | u64 gfn; | |
1968 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
1969 | memset(&tsc_ref, 0, sizeof(tsc_ref)); | |
1970 | kvm->arch.hv_tsc_page = data; | |
1971 | if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) | |
1972 | break; | |
1973 | gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; | |
e1fa108d | 1974 | if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, |
e984097b VR |
1975 | &tsc_ref, sizeof(tsc_ref))) |
1976 | return 1; | |
1977 | mark_page_dirty(kvm, gfn); | |
1978 | break; | |
1979 | } | |
55cd8e5a | 1980 | default: |
a737f256 CD |
1981 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
1982 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
1983 | return 1; |
1984 | } | |
1985 | return 0; | |
1986 | } | |
1987 | ||
1988 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1989 | { | |
10388a07 GN |
1990 | switch (msr) { |
1991 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
b3af1e88 | 1992 | u64 gfn; |
10388a07 | 1993 | unsigned long addr; |
55cd8e5a | 1994 | |
10388a07 GN |
1995 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1996 | vcpu->arch.hv_vapic = data; | |
b63cf42f MT |
1997 | if (kvm_lapic_enable_pv_eoi(vcpu, 0)) |
1998 | return 1; | |
10388a07 GN |
1999 | break; |
2000 | } | |
b3af1e88 VR |
2001 | gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; |
2002 | addr = gfn_to_hva(vcpu->kvm, gfn); | |
10388a07 GN |
2003 | if (kvm_is_error_hva(addr)) |
2004 | return 1; | |
8b0cedff | 2005 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
2006 | return 1; |
2007 | vcpu->arch.hv_vapic = data; | |
b3af1e88 | 2008 | mark_page_dirty(vcpu->kvm, gfn); |
b63cf42f MT |
2009 | if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) |
2010 | return 1; | |
10388a07 GN |
2011 | break; |
2012 | } | |
2013 | case HV_X64_MSR_EOI: | |
2014 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
2015 | case HV_X64_MSR_ICR: | |
2016 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
2017 | case HV_X64_MSR_TPR: | |
2018 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
2019 | default: | |
a737f256 CD |
2020 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
2021 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
2022 | return 1; |
2023 | } | |
2024 | ||
2025 | return 0; | |
55cd8e5a GN |
2026 | } |
2027 | ||
344d9588 GN |
2028 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2029 | { | |
2030 | gpa_t gpa = data & ~0x3f; | |
2031 | ||
4a969980 | 2032 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 2033 | if (data & 0x3c) |
344d9588 GN |
2034 | return 1; |
2035 | ||
2036 | vcpu->arch.apf.msr_val = data; | |
2037 | ||
2038 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2039 | kvm_clear_async_pf_completion_queue(vcpu); | |
2040 | kvm_async_pf_hash_reset(vcpu); | |
2041 | return 0; | |
2042 | } | |
2043 | ||
8f964525 AH |
2044 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
2045 | sizeof(u32))) | |
344d9588 GN |
2046 | return 1; |
2047 | ||
6adba527 | 2048 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
2049 | kvm_async_pf_wakeup_all(vcpu); |
2050 | return 0; | |
2051 | } | |
2052 | ||
12f9a48f GC |
2053 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2054 | { | |
0b79459b | 2055 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2056 | } |
2057 | ||
c9aaa895 GC |
2058 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
2059 | { | |
2060 | u64 delta; | |
2061 | ||
2062 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2063 | return; | |
2064 | ||
2065 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
2066 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2067 | vcpu->arch.st.accum_steal = delta; | |
2068 | } | |
2069 | ||
2070 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
2071 | { | |
2072 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2073 | return; | |
2074 | ||
2075 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2076 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
2077 | return; | |
2078 | ||
2079 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
2080 | vcpu->arch.st.steal.version += 2; | |
2081 | vcpu->arch.st.accum_steal = 0; | |
2082 | ||
2083 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2084 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2085 | } | |
2086 | ||
8fe8ab46 | 2087 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2088 | { |
5753785f | 2089 | bool pr = false; |
8fe8ab46 WA |
2090 | u32 msr = msr_info->index; |
2091 | u64 data = msr_info->data; | |
5753785f | 2092 | |
15c4a640 | 2093 | switch (msr) { |
2e32b719 BP |
2094 | case MSR_AMD64_NB_CFG: |
2095 | case MSR_IA32_UCODE_REV: | |
2096 | case MSR_IA32_UCODE_WRITE: | |
2097 | case MSR_VM_HSAVE_PA: | |
2098 | case MSR_AMD64_PATCH_LOADER: | |
2099 | case MSR_AMD64_BU_CFG2: | |
2100 | break; | |
2101 | ||
15c4a640 | 2102 | case MSR_EFER: |
b69e8cae | 2103 | return set_efer(vcpu, data); |
8f1589d9 AP |
2104 | case MSR_K7_HWCR: |
2105 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2106 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2107 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2108 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2109 | if (data != 0) { |
a737f256 CD |
2110 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2111 | data); | |
8f1589d9 AP |
2112 | return 1; |
2113 | } | |
15c4a640 | 2114 | break; |
f7c6d140 AP |
2115 | case MSR_FAM10H_MMIO_CONF_BASE: |
2116 | if (data != 0) { | |
a737f256 CD |
2117 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2118 | "0x%llx\n", data); | |
f7c6d140 AP |
2119 | return 1; |
2120 | } | |
15c4a640 | 2121 | break; |
b5e2fec0 AG |
2122 | case MSR_IA32_DEBUGCTLMSR: |
2123 | if (!data) { | |
2124 | /* We support the non-activated case already */ | |
2125 | break; | |
2126 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2127 | /* Values other than LBR and BTF are vendor-specific, | |
2128 | thus reserved and should throw a #GP */ | |
2129 | return 1; | |
2130 | } | |
a737f256 CD |
2131 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2132 | __func__, data); | |
b5e2fec0 | 2133 | break; |
9ba075a6 AK |
2134 | case 0x200 ... 0x2ff: |
2135 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 | 2136 | case MSR_IA32_APICBASE: |
58cb628d | 2137 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2138 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2139 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2140 | case MSR_IA32_TSCDEADLINE: |
2141 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2142 | break; | |
ba904635 WA |
2143 | case MSR_IA32_TSC_ADJUST: |
2144 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2145 | if (!msr_info->host_initiated) { | |
2146 | u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; | |
2147 | kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); | |
2148 | } | |
2149 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2150 | } | |
2151 | break; | |
15c4a640 | 2152 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2153 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2154 | break; |
11c6bffa | 2155 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2156 | case MSR_KVM_WALL_CLOCK: |
2157 | vcpu->kvm->arch.wall_clock = data; | |
2158 | kvm_write_wall_clock(vcpu->kvm, data); | |
2159 | break; | |
11c6bffa | 2160 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2161 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 2162 | u64 gpa_offset; |
12f9a48f | 2163 | kvmclock_reset(vcpu); |
18068523 GOC |
2164 | |
2165 | vcpu->arch.time = data; | |
0061d53d | 2166 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2167 | |
2168 | /* we verify if the enable bit is set... */ | |
2169 | if (!(data & 1)) | |
2170 | break; | |
2171 | ||
0b79459b | 2172 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 2173 | |
0b79459b | 2174 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2175 | &vcpu->arch.pv_time, data & ~1ULL, |
2176 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2177 | vcpu->arch.pv_time_enabled = false; |
2178 | else | |
2179 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2180 | |
18068523 GOC |
2181 | break; |
2182 | } | |
344d9588 GN |
2183 | case MSR_KVM_ASYNC_PF_EN: |
2184 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2185 | return 1; | |
2186 | break; | |
c9aaa895 GC |
2187 | case MSR_KVM_STEAL_TIME: |
2188 | ||
2189 | if (unlikely(!sched_info_on())) | |
2190 | return 1; | |
2191 | ||
2192 | if (data & KVM_STEAL_RESERVED_MASK) | |
2193 | return 1; | |
2194 | ||
2195 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2196 | data & KVM_STEAL_VALID_BITS, |
2197 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2198 | return 1; |
2199 | ||
2200 | vcpu->arch.st.msr_val = data; | |
2201 | ||
2202 | if (!(data & KVM_MSR_ENABLED)) | |
2203 | break; | |
2204 | ||
2205 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2206 | ||
2207 | preempt_disable(); | |
2208 | accumulate_steal_time(vcpu); | |
2209 | preempt_enable(); | |
2210 | ||
2211 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2212 | ||
2213 | break; | |
ae7a2a3f MT |
2214 | case MSR_KVM_PV_EOI_EN: |
2215 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2216 | return 1; | |
2217 | break; | |
c9aaa895 | 2218 | |
890ca9ae HY |
2219 | case MSR_IA32_MCG_CTL: |
2220 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2221 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2222 | return set_msr_mce(vcpu, msr, data); |
71db6023 AP |
2223 | |
2224 | /* Performance counters are not protected by a CPUID bit, | |
2225 | * so we should check all of them in the generic path for the sake of | |
2226 | * cross vendor migration. | |
2227 | * Writing a zero into the event select MSRs disables them, | |
2228 | * which we perfectly emulate ;-). Any other value should be at least | |
2229 | * reported, some guests depend on them. | |
2230 | */ | |
71db6023 AP |
2231 | case MSR_K7_EVNTSEL0: |
2232 | case MSR_K7_EVNTSEL1: | |
2233 | case MSR_K7_EVNTSEL2: | |
2234 | case MSR_K7_EVNTSEL3: | |
2235 | if (data != 0) | |
a737f256 CD |
2236 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2237 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
2238 | break; |
2239 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
2240 | * so we ignore writes to make it happy. | |
2241 | */ | |
71db6023 AP |
2242 | case MSR_K7_PERFCTR0: |
2243 | case MSR_K7_PERFCTR1: | |
2244 | case MSR_K7_PERFCTR2: | |
2245 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
2246 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2247 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 2248 | break; |
5753785f GN |
2249 | case MSR_P6_PERFCTR0: |
2250 | case MSR_P6_PERFCTR1: | |
2251 | pr = true; | |
2252 | case MSR_P6_EVNTSEL0: | |
2253 | case MSR_P6_EVNTSEL1: | |
2254 | if (kvm_pmu_msr(vcpu, msr)) | |
afd80d85 | 2255 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2256 | |
2257 | if (pr || data != 0) | |
a737f256 CD |
2258 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2259 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2260 | break; |
84e0cefa JS |
2261 | case MSR_K7_CLK_CTL: |
2262 | /* | |
2263 | * Ignore all writes to this no longer documented MSR. | |
2264 | * Writes are only relevant for old K7 processors, | |
2265 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2266 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2267 | * affected processor models on the command line, hence |
2268 | * the need to ignore the workaround. | |
2269 | */ | |
2270 | break; | |
55cd8e5a GN |
2271 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2272 | if (kvm_hv_msr_partition_wide(msr)) { | |
2273 | int r; | |
2274 | mutex_lock(&vcpu->kvm->lock); | |
2275 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
2276 | mutex_unlock(&vcpu->kvm->lock); | |
2277 | return r; | |
2278 | } else | |
2279 | return set_msr_hyperv(vcpu, msr, data); | |
2280 | break; | |
91c9c3ed | 2281 | case MSR_IA32_BBL_CR_CTL3: |
2282 | /* Drop writes to this legacy MSR -- see rdmsr | |
2283 | * counterpart for further detail. | |
2284 | */ | |
a737f256 | 2285 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2286 | break; |
2b036c6b BO |
2287 | case MSR_AMD64_OSVW_ID_LENGTH: |
2288 | if (!guest_cpuid_has_osvw(vcpu)) | |
2289 | return 1; | |
2290 | vcpu->arch.osvw.length = data; | |
2291 | break; | |
2292 | case MSR_AMD64_OSVW_STATUS: | |
2293 | if (!guest_cpuid_has_osvw(vcpu)) | |
2294 | return 1; | |
2295 | vcpu->arch.osvw.status = data; | |
2296 | break; | |
15c4a640 | 2297 | default: |
ffde22ac ES |
2298 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2299 | return xen_hvm_config(vcpu, data); | |
f5132b01 | 2300 | if (kvm_pmu_msr(vcpu, msr)) |
afd80d85 | 2301 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2302 | if (!ignore_msrs) { |
a737f256 CD |
2303 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2304 | msr, data); | |
ed85c068 AP |
2305 | return 1; |
2306 | } else { | |
a737f256 CD |
2307 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2308 | msr, data); | |
ed85c068 AP |
2309 | break; |
2310 | } | |
15c4a640 CO |
2311 | } |
2312 | return 0; | |
2313 | } | |
2314 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2315 | ||
2316 | ||
2317 | /* | |
2318 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2319 | * Returns 0 on success, non-0 otherwise. | |
2320 | * Assumes vcpu_load() was already called. | |
2321 | */ | |
2322 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
2323 | { | |
2324 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
2325 | } | |
2326 | ||
9ba075a6 AK |
2327 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2328 | { | |
0bed3b56 SY |
2329 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
2330 | ||
9ba075a6 AK |
2331 | if (!msr_mtrr_valid(msr)) |
2332 | return 1; | |
2333 | ||
0bed3b56 SY |
2334 | if (msr == MSR_MTRRdefType) |
2335 | *pdata = vcpu->arch.mtrr_state.def_type + | |
2336 | (vcpu->arch.mtrr_state.enabled << 10); | |
2337 | else if (msr == MSR_MTRRfix64K_00000) | |
2338 | *pdata = p[0]; | |
2339 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
2340 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
2341 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
2342 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
2343 | else if (msr == MSR_IA32_CR_PAT) | |
2344 | *pdata = vcpu->arch.pat; | |
2345 | else { /* Variable MTRRs */ | |
2346 | int idx, is_mtrr_mask; | |
2347 | u64 *pt; | |
2348 | ||
2349 | idx = (msr - 0x200) / 2; | |
2350 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
2351 | if (!is_mtrr_mask) | |
2352 | pt = | |
2353 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
2354 | else | |
2355 | pt = | |
2356 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
2357 | *pdata = *pt; | |
2358 | } | |
2359 | ||
9ba075a6 AK |
2360 | return 0; |
2361 | } | |
2362 | ||
890ca9ae | 2363 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2364 | { |
2365 | u64 data; | |
890ca9ae HY |
2366 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2367 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2368 | |
2369 | switch (msr) { | |
15c4a640 CO |
2370 | case MSR_IA32_P5_MC_ADDR: |
2371 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2372 | data = 0; |
2373 | break; | |
15c4a640 | 2374 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2375 | data = vcpu->arch.mcg_cap; |
2376 | break; | |
c7ac679c | 2377 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2378 | if (!(mcg_cap & MCG_CTL_P)) |
2379 | return 1; | |
2380 | data = vcpu->arch.mcg_ctl; | |
2381 | break; | |
2382 | case MSR_IA32_MCG_STATUS: | |
2383 | data = vcpu->arch.mcg_status; | |
2384 | break; | |
2385 | default: | |
2386 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2387 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2388 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2389 | data = vcpu->arch.mce_banks[offset]; | |
2390 | break; | |
2391 | } | |
2392 | return 1; | |
2393 | } | |
2394 | *pdata = data; | |
2395 | return 0; | |
2396 | } | |
2397 | ||
55cd8e5a GN |
2398 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2399 | { | |
2400 | u64 data = 0; | |
2401 | struct kvm *kvm = vcpu->kvm; | |
2402 | ||
2403 | switch (msr) { | |
2404 | case HV_X64_MSR_GUEST_OS_ID: | |
2405 | data = kvm->arch.hv_guest_os_id; | |
2406 | break; | |
2407 | case HV_X64_MSR_HYPERCALL: | |
2408 | data = kvm->arch.hv_hypercall; | |
2409 | break; | |
e984097b VR |
2410 | case HV_X64_MSR_TIME_REF_COUNT: { |
2411 | data = | |
2412 | div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); | |
2413 | break; | |
2414 | } | |
2415 | case HV_X64_MSR_REFERENCE_TSC: | |
2416 | data = kvm->arch.hv_tsc_page; | |
2417 | break; | |
55cd8e5a | 2418 | default: |
a737f256 | 2419 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2420 | return 1; |
2421 | } | |
2422 | ||
2423 | *pdata = data; | |
2424 | return 0; | |
2425 | } | |
2426 | ||
2427 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2428 | { | |
2429 | u64 data = 0; | |
2430 | ||
2431 | switch (msr) { | |
2432 | case HV_X64_MSR_VP_INDEX: { | |
2433 | int r; | |
2434 | struct kvm_vcpu *v; | |
684851a1 TY |
2435 | kvm_for_each_vcpu(r, v, vcpu->kvm) { |
2436 | if (v == vcpu) { | |
55cd8e5a | 2437 | data = r; |
684851a1 TY |
2438 | break; |
2439 | } | |
2440 | } | |
55cd8e5a GN |
2441 | break; |
2442 | } | |
10388a07 GN |
2443 | case HV_X64_MSR_EOI: |
2444 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
2445 | case HV_X64_MSR_ICR: | |
2446 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
2447 | case HV_X64_MSR_TPR: | |
2448 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 2449 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
2450 | data = vcpu->arch.hv_vapic; |
2451 | break; | |
55cd8e5a | 2452 | default: |
a737f256 | 2453 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2454 | return 1; |
2455 | } | |
2456 | *pdata = data; | |
2457 | return 0; | |
2458 | } | |
2459 | ||
890ca9ae HY |
2460 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2461 | { | |
2462 | u64 data; | |
2463 | ||
2464 | switch (msr) { | |
890ca9ae | 2465 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2466 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2467 | case MSR_IA32_DEBUGCTLMSR: |
2468 | case MSR_IA32_LASTBRANCHFROMIP: | |
2469 | case MSR_IA32_LASTBRANCHTOIP: | |
2470 | case MSR_IA32_LASTINTFROMIP: | |
2471 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
2472 | case MSR_K8_SYSCFG: |
2473 | case MSR_K7_HWCR: | |
61a6bd67 | 2474 | case MSR_VM_HSAVE_PA: |
9e699624 | 2475 | case MSR_K7_EVNTSEL0: |
dc9b2d93 WH |
2476 | case MSR_K7_EVNTSEL1: |
2477 | case MSR_K7_EVNTSEL2: | |
2478 | case MSR_K7_EVNTSEL3: | |
1f3ee616 | 2479 | case MSR_K7_PERFCTR0: |
dc9b2d93 WH |
2480 | case MSR_K7_PERFCTR1: |
2481 | case MSR_K7_PERFCTR2: | |
2482 | case MSR_K7_PERFCTR3: | |
1fdbd48c | 2483 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2484 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2485 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2486 | case MSR_AMD64_BU_CFG2: |
15c4a640 CO |
2487 | data = 0; |
2488 | break; | |
5753785f GN |
2489 | case MSR_P6_PERFCTR0: |
2490 | case MSR_P6_PERFCTR1: | |
2491 | case MSR_P6_EVNTSEL0: | |
2492 | case MSR_P6_EVNTSEL1: | |
2493 | if (kvm_pmu_msr(vcpu, msr)) | |
2494 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
2495 | data = 0; | |
2496 | break; | |
742bc670 MT |
2497 | case MSR_IA32_UCODE_REV: |
2498 | data = 0x100000000ULL; | |
2499 | break; | |
9ba075a6 AK |
2500 | case MSR_MTRRcap: |
2501 | data = 0x500 | KVM_NR_VAR_MTRR; | |
2502 | break; | |
2503 | case 0x200 ... 0x2ff: | |
2504 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
2505 | case 0xcd: /* fsb frequency */ |
2506 | data = 3; | |
2507 | break; | |
7b914098 JS |
2508 | /* |
2509 | * MSR_EBC_FREQUENCY_ID | |
2510 | * Conservative value valid for even the basic CPU models. | |
2511 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2512 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2513 | * and 266MHz for model 3, or 4. Set Core Clock | |
2514 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2515 | * 31:24) even though these are only valid for CPU | |
2516 | * models > 2, however guests may end up dividing or | |
2517 | * multiplying by zero otherwise. | |
2518 | */ | |
2519 | case MSR_EBC_FREQUENCY_ID: | |
2520 | data = 1 << 24; | |
2521 | break; | |
15c4a640 CO |
2522 | case MSR_IA32_APICBASE: |
2523 | data = kvm_get_apic_base(vcpu); | |
2524 | break; | |
0105d1a5 GN |
2525 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2526 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
2527 | break; | |
a3e06bbe LJ |
2528 | case MSR_IA32_TSCDEADLINE: |
2529 | data = kvm_get_lapic_tscdeadline_msr(vcpu); | |
2530 | break; | |
ba904635 WA |
2531 | case MSR_IA32_TSC_ADJUST: |
2532 | data = (u64)vcpu->arch.ia32_tsc_adjust_msr; | |
2533 | break; | |
15c4a640 | 2534 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2535 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2536 | break; |
847f0ad8 AG |
2537 | case MSR_IA32_PERF_STATUS: |
2538 | /* TSC increment by tick */ | |
2539 | data = 1000ULL; | |
2540 | /* CPU multiplier */ | |
2541 | data |= (((uint64_t)4ULL) << 40); | |
2542 | break; | |
15c4a640 | 2543 | case MSR_EFER: |
f6801dff | 2544 | data = vcpu->arch.efer; |
15c4a640 | 2545 | break; |
18068523 | 2546 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2547 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2548 | data = vcpu->kvm->arch.wall_clock; |
2549 | break; | |
2550 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2551 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
2552 | data = vcpu->arch.time; |
2553 | break; | |
344d9588 GN |
2554 | case MSR_KVM_ASYNC_PF_EN: |
2555 | data = vcpu->arch.apf.msr_val; | |
2556 | break; | |
c9aaa895 GC |
2557 | case MSR_KVM_STEAL_TIME: |
2558 | data = vcpu->arch.st.msr_val; | |
2559 | break; | |
1d92128f MT |
2560 | case MSR_KVM_PV_EOI_EN: |
2561 | data = vcpu->arch.pv_eoi.msr_val; | |
2562 | break; | |
890ca9ae HY |
2563 | case MSR_IA32_P5_MC_ADDR: |
2564 | case MSR_IA32_P5_MC_TYPE: | |
2565 | case MSR_IA32_MCG_CAP: | |
2566 | case MSR_IA32_MCG_CTL: | |
2567 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2568 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2569 | return get_msr_mce(vcpu, msr, pdata); |
84e0cefa JS |
2570 | case MSR_K7_CLK_CTL: |
2571 | /* | |
2572 | * Provide expected ramp-up count for K7. All other | |
2573 | * are set to zero, indicating minimum divisors for | |
2574 | * every field. | |
2575 | * | |
2576 | * This prevents guest kernels on AMD host with CPU | |
2577 | * type 6, model 8 and higher from exploding due to | |
2578 | * the rdmsr failing. | |
2579 | */ | |
2580 | data = 0x20000000; | |
2581 | break; | |
55cd8e5a GN |
2582 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2583 | if (kvm_hv_msr_partition_wide(msr)) { | |
2584 | int r; | |
2585 | mutex_lock(&vcpu->kvm->lock); | |
2586 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
2587 | mutex_unlock(&vcpu->kvm->lock); | |
2588 | return r; | |
2589 | } else | |
2590 | return get_msr_hyperv(vcpu, msr, pdata); | |
2591 | break; | |
91c9c3ed | 2592 | case MSR_IA32_BBL_CR_CTL3: |
2593 | /* This legacy MSR exists but isn't fully documented in current | |
2594 | * silicon. It is however accessed by winxp in very narrow | |
2595 | * scenarios where it sets bit #19, itself documented as | |
2596 | * a "reserved" bit. Best effort attempt to source coherent | |
2597 | * read data here should the balance of the register be | |
2598 | * interpreted by the guest: | |
2599 | * | |
2600 | * L2 cache control register 3: 64GB range, 256KB size, | |
2601 | * enabled, latency 0x1, configured | |
2602 | */ | |
2603 | data = 0xbe702111; | |
2604 | break; | |
2b036c6b BO |
2605 | case MSR_AMD64_OSVW_ID_LENGTH: |
2606 | if (!guest_cpuid_has_osvw(vcpu)) | |
2607 | return 1; | |
2608 | data = vcpu->arch.osvw.length; | |
2609 | break; | |
2610 | case MSR_AMD64_OSVW_STATUS: | |
2611 | if (!guest_cpuid_has_osvw(vcpu)) | |
2612 | return 1; | |
2613 | data = vcpu->arch.osvw.status; | |
2614 | break; | |
15c4a640 | 2615 | default: |
f5132b01 GN |
2616 | if (kvm_pmu_msr(vcpu, msr)) |
2617 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
ed85c068 | 2618 | if (!ignore_msrs) { |
a737f256 | 2619 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2620 | return 1; |
2621 | } else { | |
a737f256 | 2622 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); |
ed85c068 AP |
2623 | data = 0; |
2624 | } | |
2625 | break; | |
15c4a640 CO |
2626 | } |
2627 | *pdata = data; | |
2628 | return 0; | |
2629 | } | |
2630 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2631 | ||
313a3dc7 CO |
2632 | /* |
2633 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2634 | * | |
2635 | * @return number of msrs set successfully. | |
2636 | */ | |
2637 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2638 | struct kvm_msr_entry *entries, | |
2639 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2640 | unsigned index, u64 *data)) | |
2641 | { | |
f656ce01 | 2642 | int i, idx; |
313a3dc7 | 2643 | |
f656ce01 | 2644 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2645 | for (i = 0; i < msrs->nmsrs; ++i) |
2646 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2647 | break; | |
f656ce01 | 2648 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2649 | |
313a3dc7 CO |
2650 | return i; |
2651 | } | |
2652 | ||
2653 | /* | |
2654 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2655 | * | |
2656 | * @return number of msrs set successfully. | |
2657 | */ | |
2658 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2659 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2660 | unsigned index, u64 *data), | |
2661 | int writeback) | |
2662 | { | |
2663 | struct kvm_msrs msrs; | |
2664 | struct kvm_msr_entry *entries; | |
2665 | int r, n; | |
2666 | unsigned size; | |
2667 | ||
2668 | r = -EFAULT; | |
2669 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2670 | goto out; | |
2671 | ||
2672 | r = -E2BIG; | |
2673 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2674 | goto out; | |
2675 | ||
313a3dc7 | 2676 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2677 | entries = memdup_user(user_msrs->entries, size); |
2678 | if (IS_ERR(entries)) { | |
2679 | r = PTR_ERR(entries); | |
313a3dc7 | 2680 | goto out; |
ff5c2c03 | 2681 | } |
313a3dc7 CO |
2682 | |
2683 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2684 | if (r < 0) | |
2685 | goto out_free; | |
2686 | ||
2687 | r = -EFAULT; | |
2688 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2689 | goto out_free; | |
2690 | ||
2691 | r = n; | |
2692 | ||
2693 | out_free: | |
7a73c028 | 2694 | kfree(entries); |
313a3dc7 CO |
2695 | out: |
2696 | return r; | |
2697 | } | |
2698 | ||
784aa3d7 | 2699 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 ZX |
2700 | { |
2701 | int r; | |
2702 | ||
2703 | switch (ext) { | |
2704 | case KVM_CAP_IRQCHIP: | |
2705 | case KVM_CAP_HLT: | |
2706 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2707 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2708 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2709 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2710 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2711 | case KVM_CAP_PIT: |
a28e4f5a | 2712 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2713 | case KVM_CAP_MP_STATE: |
ed848624 | 2714 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2715 | case KVM_CAP_USER_NMI: |
52d939a0 | 2716 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2717 | case KVM_CAP_IRQ_INJECT_STATUS: |
721eecbf | 2718 | case KVM_CAP_IRQFD: |
d34e6b17 | 2719 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2720 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2721 | case KVM_CAP_PIT2: |
e9f42757 | 2722 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2723 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2724 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2725 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2726 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2727 | case KVM_CAP_HYPERV: |
10388a07 | 2728 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2729 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2730 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2731 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2732 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2733 | case KVM_CAP_XSAVE: |
344d9588 | 2734 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2735 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2736 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2737 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2738 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2739 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
2a5bab10 AW |
2740 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2741 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2742 | case KVM_CAP_PCI_2_3: | |
2743 | #endif | |
018d00d2 ZX |
2744 | r = 1; |
2745 | break; | |
542472b5 LV |
2746 | case KVM_CAP_COALESCED_MMIO: |
2747 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2748 | break; | |
774ead3a AK |
2749 | case KVM_CAP_VAPIC: |
2750 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2751 | break; | |
f725230a | 2752 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2753 | r = KVM_SOFT_MAX_VCPUS; |
2754 | break; | |
2755 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2756 | r = KVM_MAX_VCPUS; |
2757 | break; | |
a988b910 | 2758 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2759 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2760 | break; |
a68a6a72 MT |
2761 | case KVM_CAP_PV_MMU: /* obsolete */ |
2762 | r = 0; | |
2f333bcb | 2763 | break; |
4cee4b72 | 2764 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2765 | case KVM_CAP_IOMMU: |
a1b60c1c | 2766 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2767 | break; |
4cee4b72 | 2768 | #endif |
890ca9ae HY |
2769 | case KVM_CAP_MCE: |
2770 | r = KVM_MAX_MCE_BANKS; | |
2771 | break; | |
2d5b5a66 SY |
2772 | case KVM_CAP_XCRS: |
2773 | r = cpu_has_xsave; | |
2774 | break; | |
92a1f12d JR |
2775 | case KVM_CAP_TSC_CONTROL: |
2776 | r = kvm_has_tsc_control; | |
2777 | break; | |
4d25a066 JK |
2778 | case KVM_CAP_TSC_DEADLINE_TIMER: |
2779 | r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER); | |
2780 | break; | |
018d00d2 ZX |
2781 | default: |
2782 | r = 0; | |
2783 | break; | |
2784 | } | |
2785 | return r; | |
2786 | ||
2787 | } | |
2788 | ||
043405e1 CO |
2789 | long kvm_arch_dev_ioctl(struct file *filp, |
2790 | unsigned int ioctl, unsigned long arg) | |
2791 | { | |
2792 | void __user *argp = (void __user *)arg; | |
2793 | long r; | |
2794 | ||
2795 | switch (ioctl) { | |
2796 | case KVM_GET_MSR_INDEX_LIST: { | |
2797 | struct kvm_msr_list __user *user_msr_list = argp; | |
2798 | struct kvm_msr_list msr_list; | |
2799 | unsigned n; | |
2800 | ||
2801 | r = -EFAULT; | |
2802 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2803 | goto out; | |
2804 | n = msr_list.nmsrs; | |
2805 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2806 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2807 | goto out; | |
2808 | r = -E2BIG; | |
e125e7b6 | 2809 | if (n < msr_list.nmsrs) |
043405e1 CO |
2810 | goto out; |
2811 | r = -EFAULT; | |
2812 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2813 | num_msrs_to_save * sizeof(u32))) | |
2814 | goto out; | |
e125e7b6 | 2815 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
2816 | &emulated_msrs, |
2817 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2818 | goto out; | |
2819 | r = 0; | |
2820 | break; | |
2821 | } | |
9c15bb1d BP |
2822 | case KVM_GET_SUPPORTED_CPUID: |
2823 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2824 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2825 | struct kvm_cpuid2 cpuid; | |
2826 | ||
2827 | r = -EFAULT; | |
2828 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2829 | goto out; | |
9c15bb1d BP |
2830 | |
2831 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2832 | ioctl); | |
674eea0f AK |
2833 | if (r) |
2834 | goto out; | |
2835 | ||
2836 | r = -EFAULT; | |
2837 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2838 | goto out; | |
2839 | r = 0; | |
2840 | break; | |
2841 | } | |
890ca9ae HY |
2842 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2843 | u64 mce_cap; | |
2844 | ||
2845 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2846 | r = -EFAULT; | |
2847 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2848 | goto out; | |
2849 | r = 0; | |
2850 | break; | |
2851 | } | |
043405e1 CO |
2852 | default: |
2853 | r = -EINVAL; | |
2854 | } | |
2855 | out: | |
2856 | return r; | |
2857 | } | |
2858 | ||
f5f48ee1 SY |
2859 | static void wbinvd_ipi(void *garbage) |
2860 | { | |
2861 | wbinvd(); | |
2862 | } | |
2863 | ||
2864 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2865 | { | |
e0f0bbc5 | 2866 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
2867 | } |
2868 | ||
313a3dc7 CO |
2869 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2870 | { | |
f5f48ee1 SY |
2871 | /* Address WBINVD may be executed by guest */ |
2872 | if (need_emulate_wbinvd(vcpu)) { | |
2873 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2874 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2875 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2876 | smp_call_function_single(vcpu->cpu, | |
2877 | wbinvd_ipi, NULL, 1); | |
2878 | } | |
2879 | ||
313a3dc7 | 2880 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2881 | |
0dd6a6ed ZA |
2882 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2883 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2884 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2885 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 2886 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 2887 | } |
8f6055cb | 2888 | |
48434c20 | 2889 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
2890 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
2891 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
2892 | if (tsc_delta < 0) |
2893 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2894 | if (check_tsc_unstable()) { |
b183aa58 ZA |
2895 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
2896 | vcpu->arch.last_guest_tsc); | |
2897 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2898 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2899 | } |
d98d07ca MT |
2900 | /* |
2901 | * On a host with synchronized TSC, there is no need to update | |
2902 | * kvmclock on vcpu->cpu migration | |
2903 | */ | |
2904 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 2905 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2906 | if (vcpu->cpu != cpu) |
2907 | kvm_migrate_timers(vcpu); | |
e48672fa | 2908 | vcpu->cpu = cpu; |
6b7d7e76 | 2909 | } |
c9aaa895 GC |
2910 | |
2911 | accumulate_steal_time(vcpu); | |
2912 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
2913 | } |
2914 | ||
2915 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2916 | { | |
02daab21 | 2917 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2918 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 2919 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
2920 | } |
2921 | ||
313a3dc7 CO |
2922 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2923 | struct kvm_lapic_state *s) | |
2924 | { | |
5a71785d | 2925 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
ad312c7c | 2926 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2927 | |
2928 | return 0; | |
2929 | } | |
2930 | ||
2931 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2932 | struct kvm_lapic_state *s) | |
2933 | { | |
64eb0620 | 2934 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2935 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2936 | |
2937 | return 0; | |
2938 | } | |
2939 | ||
f77bc6a4 ZX |
2940 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2941 | struct kvm_interrupt *irq) | |
2942 | { | |
02cdb50f | 2943 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 ZX |
2944 | return -EINVAL; |
2945 | if (irqchip_in_kernel(vcpu->kvm)) | |
2946 | return -ENXIO; | |
f77bc6a4 | 2947 | |
66fd3f7f | 2948 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 2949 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 2950 | |
f77bc6a4 ZX |
2951 | return 0; |
2952 | } | |
2953 | ||
c4abb7c9 JK |
2954 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2955 | { | |
c4abb7c9 | 2956 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2957 | |
2958 | return 0; | |
2959 | } | |
2960 | ||
b209749f AK |
2961 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2962 | struct kvm_tpr_access_ctl *tac) | |
2963 | { | |
2964 | if (tac->flags) | |
2965 | return -EINVAL; | |
2966 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2967 | return 0; | |
2968 | } | |
2969 | ||
890ca9ae HY |
2970 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2971 | u64 mcg_cap) | |
2972 | { | |
2973 | int r; | |
2974 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2975 | ||
2976 | r = -EINVAL; | |
a9e38c3e | 2977 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2978 | goto out; |
2979 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2980 | goto out; | |
2981 | r = 0; | |
2982 | vcpu->arch.mcg_cap = mcg_cap; | |
2983 | /* Init IA32_MCG_CTL to all 1s */ | |
2984 | if (mcg_cap & MCG_CTL_P) | |
2985 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2986 | /* Init IA32_MCi_CTL to all 1s */ | |
2987 | for (bank = 0; bank < bank_num; bank++) | |
2988 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2989 | out: | |
2990 | return r; | |
2991 | } | |
2992 | ||
2993 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2994 | struct kvm_x86_mce *mce) | |
2995 | { | |
2996 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2997 | unsigned bank_num = mcg_cap & 0xff; | |
2998 | u64 *banks = vcpu->arch.mce_banks; | |
2999 | ||
3000 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3001 | return -EINVAL; | |
3002 | /* | |
3003 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3004 | * reporting is disabled | |
3005 | */ | |
3006 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3007 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3008 | return 0; | |
3009 | banks += 4 * mce->bank; | |
3010 | /* | |
3011 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3012 | * reporting is disabled for the bank | |
3013 | */ | |
3014 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3015 | return 0; | |
3016 | if (mce->status & MCI_STATUS_UC) { | |
3017 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3018 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3019 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3020 | return 0; |
3021 | } | |
3022 | if (banks[1] & MCI_STATUS_VAL) | |
3023 | mce->status |= MCI_STATUS_OVER; | |
3024 | banks[2] = mce->addr; | |
3025 | banks[3] = mce->misc; | |
3026 | vcpu->arch.mcg_status = mce->mcg_status; | |
3027 | banks[1] = mce->status; | |
3028 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3029 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3030 | || !(banks[1] & MCI_STATUS_UC)) { | |
3031 | if (banks[1] & MCI_STATUS_VAL) | |
3032 | mce->status |= MCI_STATUS_OVER; | |
3033 | banks[2] = mce->addr; | |
3034 | banks[3] = mce->misc; | |
3035 | banks[1] = mce->status; | |
3036 | } else | |
3037 | banks[1] |= MCI_STATUS_OVER; | |
3038 | return 0; | |
3039 | } | |
3040 | ||
3cfc3092 JK |
3041 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3042 | struct kvm_vcpu_events *events) | |
3043 | { | |
7460fb4a | 3044 | process_nmi(vcpu); |
03b82a30 JK |
3045 | events->exception.injected = |
3046 | vcpu->arch.exception.pending && | |
3047 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
3048 | events->exception.nr = vcpu->arch.exception.nr; |
3049 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 3050 | events->exception.pad = 0; |
3cfc3092 JK |
3051 | events->exception.error_code = vcpu->arch.exception.error_code; |
3052 | ||
03b82a30 JK |
3053 | events->interrupt.injected = |
3054 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 3055 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3056 | events->interrupt.soft = 0; |
37ccdcbe | 3057 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3058 | |
3059 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3060 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3061 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3062 | events->nmi.pad = 0; |
3cfc3092 | 3063 | |
66450a21 | 3064 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3065 | |
dab4b911 | 3066 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3067 | | KVM_VCPUEVENT_VALID_SHADOW); |
97e69aa6 | 3068 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3069 | } |
3070 | ||
3071 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
3072 | struct kvm_vcpu_events *events) | |
3073 | { | |
dab4b911 | 3074 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
3075 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
3076 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
3077 | return -EINVAL; |
3078 | ||
7460fb4a | 3079 | process_nmi(vcpu); |
3cfc3092 JK |
3080 | vcpu->arch.exception.pending = events->exception.injected; |
3081 | vcpu->arch.exception.nr = events->exception.nr; | |
3082 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3083 | vcpu->arch.exception.error_code = events->exception.error_code; | |
3084 | ||
3085 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
3086 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
3087 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3088 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3089 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3090 | events->interrupt.shadow); | |
3cfc3092 JK |
3091 | |
3092 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3093 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3094 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3095 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3096 | ||
66450a21 JK |
3097 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
3098 | kvm_vcpu_has_lapic(vcpu)) | |
3099 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
3cfc3092 | 3100 | |
3842d135 AK |
3101 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3102 | ||
3cfc3092 JK |
3103 | return 0; |
3104 | } | |
3105 | ||
a1efbe77 JK |
3106 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3107 | struct kvm_debugregs *dbgregs) | |
3108 | { | |
73aaf249 JK |
3109 | unsigned long val; |
3110 | ||
a1efbe77 | 3111 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3112 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3113 | dbgregs->dr6 = val; |
a1efbe77 JK |
3114 | dbgregs->dr7 = vcpu->arch.dr7; |
3115 | dbgregs->flags = 0; | |
97e69aa6 | 3116 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3117 | } |
3118 | ||
3119 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3120 | struct kvm_debugregs *dbgregs) | |
3121 | { | |
3122 | if (dbgregs->flags) | |
3123 | return -EINVAL; | |
3124 | ||
a1efbe77 JK |
3125 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
3126 | vcpu->arch.dr6 = dbgregs->dr6; | |
73aaf249 | 3127 | kvm_update_dr6(vcpu); |
a1efbe77 | 3128 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3129 | kvm_update_dr7(vcpu); |
a1efbe77 | 3130 | |
a1efbe77 JK |
3131 | return 0; |
3132 | } | |
3133 | ||
2d5b5a66 SY |
3134 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3135 | struct kvm_xsave *guest_xsave) | |
3136 | { | |
4344ee98 | 3137 | if (cpu_has_xsave) { |
2d5b5a66 SY |
3138 | memcpy(guest_xsave->region, |
3139 | &vcpu->arch.guest_fpu.state->xsave, | |
4344ee98 PB |
3140 | vcpu->arch.guest_xstate_size); |
3141 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &= | |
3142 | vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE; | |
3143 | } else { | |
2d5b5a66 SY |
3144 | memcpy(guest_xsave->region, |
3145 | &vcpu->arch.guest_fpu.state->fxsave, | |
3146 | sizeof(struct i387_fxsave_struct)); | |
3147 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
3148 | XSTATE_FPSSE; | |
3149 | } | |
3150 | } | |
3151 | ||
3152 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3153 | struct kvm_xsave *guest_xsave) | |
3154 | { | |
3155 | u64 xstate_bv = | |
3156 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3157 | ||
d7876f1b PB |
3158 | if (cpu_has_xsave) { |
3159 | /* | |
3160 | * Here we allow setting states that are not present in | |
3161 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3162 | * with old userspace. | |
3163 | */ | |
4ff41732 | 3164 | if (xstate_bv & ~kvm_supported_xcr0()) |
d7876f1b | 3165 | return -EINVAL; |
2d5b5a66 | 3166 | memcpy(&vcpu->arch.guest_fpu.state->xsave, |
4344ee98 | 3167 | guest_xsave->region, vcpu->arch.guest_xstate_size); |
d7876f1b | 3168 | } else { |
2d5b5a66 SY |
3169 | if (xstate_bv & ~XSTATE_FPSSE) |
3170 | return -EINVAL; | |
3171 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
3172 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
3173 | } | |
3174 | return 0; | |
3175 | } | |
3176 | ||
3177 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3178 | struct kvm_xcrs *guest_xcrs) | |
3179 | { | |
3180 | if (!cpu_has_xsave) { | |
3181 | guest_xcrs->nr_xcrs = 0; | |
3182 | return; | |
3183 | } | |
3184 | ||
3185 | guest_xcrs->nr_xcrs = 1; | |
3186 | guest_xcrs->flags = 0; | |
3187 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3188 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3189 | } | |
3190 | ||
3191 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3192 | struct kvm_xcrs *guest_xcrs) | |
3193 | { | |
3194 | int i, r = 0; | |
3195 | ||
3196 | if (!cpu_has_xsave) | |
3197 | return -EINVAL; | |
3198 | ||
3199 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3200 | return -EINVAL; | |
3201 | ||
3202 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3203 | /* Only support XCR0 currently */ | |
c67a04cb | 3204 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3205 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3206 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3207 | break; |
3208 | } | |
3209 | if (r) | |
3210 | r = -EINVAL; | |
3211 | return r; | |
3212 | } | |
3213 | ||
1c0b28c2 EM |
3214 | /* |
3215 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3216 | * stopped by the hypervisor. This function will be called from the host only. | |
3217 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3218 | * does not support pv clocks. | |
3219 | */ | |
3220 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3221 | { | |
0b79459b | 3222 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3223 | return -EINVAL; |
51d59c6b | 3224 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3225 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3226 | return 0; | |
3227 | } | |
3228 | ||
313a3dc7 CO |
3229 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3230 | unsigned int ioctl, unsigned long arg) | |
3231 | { | |
3232 | struct kvm_vcpu *vcpu = filp->private_data; | |
3233 | void __user *argp = (void __user *)arg; | |
3234 | int r; | |
d1ac91d8 AK |
3235 | union { |
3236 | struct kvm_lapic_state *lapic; | |
3237 | struct kvm_xsave *xsave; | |
3238 | struct kvm_xcrs *xcrs; | |
3239 | void *buffer; | |
3240 | } u; | |
3241 | ||
3242 | u.buffer = NULL; | |
313a3dc7 CO |
3243 | switch (ioctl) { |
3244 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
3245 | r = -EINVAL; |
3246 | if (!vcpu->arch.apic) | |
3247 | goto out; | |
d1ac91d8 | 3248 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3249 | |
b772ff36 | 3250 | r = -ENOMEM; |
d1ac91d8 | 3251 | if (!u.lapic) |
b772ff36 | 3252 | goto out; |
d1ac91d8 | 3253 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3254 | if (r) |
3255 | goto out; | |
3256 | r = -EFAULT; | |
d1ac91d8 | 3257 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3258 | goto out; |
3259 | r = 0; | |
3260 | break; | |
3261 | } | |
3262 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
3263 | r = -EINVAL; |
3264 | if (!vcpu->arch.apic) | |
3265 | goto out; | |
ff5c2c03 | 3266 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3267 | if (IS_ERR(u.lapic)) |
3268 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3269 | |
d1ac91d8 | 3270 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3271 | break; |
3272 | } | |
f77bc6a4 ZX |
3273 | case KVM_INTERRUPT: { |
3274 | struct kvm_interrupt irq; | |
3275 | ||
3276 | r = -EFAULT; | |
3277 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3278 | goto out; | |
3279 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3280 | break; |
3281 | } | |
c4abb7c9 JK |
3282 | case KVM_NMI: { |
3283 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3284 | break; |
3285 | } | |
313a3dc7 CO |
3286 | case KVM_SET_CPUID: { |
3287 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3288 | struct kvm_cpuid cpuid; | |
3289 | ||
3290 | r = -EFAULT; | |
3291 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3292 | goto out; | |
3293 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3294 | break; |
3295 | } | |
07716717 DK |
3296 | case KVM_SET_CPUID2: { |
3297 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3298 | struct kvm_cpuid2 cpuid; | |
3299 | ||
3300 | r = -EFAULT; | |
3301 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3302 | goto out; | |
3303 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3304 | cpuid_arg->entries); |
07716717 DK |
3305 | break; |
3306 | } | |
3307 | case KVM_GET_CPUID2: { | |
3308 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3309 | struct kvm_cpuid2 cpuid; | |
3310 | ||
3311 | r = -EFAULT; | |
3312 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3313 | goto out; | |
3314 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3315 | cpuid_arg->entries); |
07716717 DK |
3316 | if (r) |
3317 | goto out; | |
3318 | r = -EFAULT; | |
3319 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3320 | goto out; | |
3321 | r = 0; | |
3322 | break; | |
3323 | } | |
313a3dc7 CO |
3324 | case KVM_GET_MSRS: |
3325 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
3326 | break; | |
3327 | case KVM_SET_MSRS: | |
3328 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3329 | break; | |
b209749f AK |
3330 | case KVM_TPR_ACCESS_REPORTING: { |
3331 | struct kvm_tpr_access_ctl tac; | |
3332 | ||
3333 | r = -EFAULT; | |
3334 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3335 | goto out; | |
3336 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3337 | if (r) | |
3338 | goto out; | |
3339 | r = -EFAULT; | |
3340 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3341 | goto out; | |
3342 | r = 0; | |
3343 | break; | |
3344 | }; | |
b93463aa AK |
3345 | case KVM_SET_VAPIC_ADDR: { |
3346 | struct kvm_vapic_addr va; | |
3347 | ||
3348 | r = -EINVAL; | |
3349 | if (!irqchip_in_kernel(vcpu->kvm)) | |
3350 | goto out; | |
3351 | r = -EFAULT; | |
3352 | if (copy_from_user(&va, argp, sizeof va)) | |
3353 | goto out; | |
fda4e2e8 | 3354 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
b93463aa AK |
3355 | break; |
3356 | } | |
890ca9ae HY |
3357 | case KVM_X86_SETUP_MCE: { |
3358 | u64 mcg_cap; | |
3359 | ||
3360 | r = -EFAULT; | |
3361 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3362 | goto out; | |
3363 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3364 | break; | |
3365 | } | |
3366 | case KVM_X86_SET_MCE: { | |
3367 | struct kvm_x86_mce mce; | |
3368 | ||
3369 | r = -EFAULT; | |
3370 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3371 | goto out; | |
3372 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3373 | break; | |
3374 | } | |
3cfc3092 JK |
3375 | case KVM_GET_VCPU_EVENTS: { |
3376 | struct kvm_vcpu_events events; | |
3377 | ||
3378 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3379 | ||
3380 | r = -EFAULT; | |
3381 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3382 | break; | |
3383 | r = 0; | |
3384 | break; | |
3385 | } | |
3386 | case KVM_SET_VCPU_EVENTS: { | |
3387 | struct kvm_vcpu_events events; | |
3388 | ||
3389 | r = -EFAULT; | |
3390 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3391 | break; | |
3392 | ||
3393 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3394 | break; | |
3395 | } | |
a1efbe77 JK |
3396 | case KVM_GET_DEBUGREGS: { |
3397 | struct kvm_debugregs dbgregs; | |
3398 | ||
3399 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3400 | ||
3401 | r = -EFAULT; | |
3402 | if (copy_to_user(argp, &dbgregs, | |
3403 | sizeof(struct kvm_debugregs))) | |
3404 | break; | |
3405 | r = 0; | |
3406 | break; | |
3407 | } | |
3408 | case KVM_SET_DEBUGREGS: { | |
3409 | struct kvm_debugregs dbgregs; | |
3410 | ||
3411 | r = -EFAULT; | |
3412 | if (copy_from_user(&dbgregs, argp, | |
3413 | sizeof(struct kvm_debugregs))) | |
3414 | break; | |
3415 | ||
3416 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3417 | break; | |
3418 | } | |
2d5b5a66 | 3419 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3420 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3421 | r = -ENOMEM; |
d1ac91d8 | 3422 | if (!u.xsave) |
2d5b5a66 SY |
3423 | break; |
3424 | ||
d1ac91d8 | 3425 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3426 | |
3427 | r = -EFAULT; | |
d1ac91d8 | 3428 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3429 | break; |
3430 | r = 0; | |
3431 | break; | |
3432 | } | |
3433 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3434 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3435 | if (IS_ERR(u.xsave)) |
3436 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3437 | |
d1ac91d8 | 3438 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3439 | break; |
3440 | } | |
3441 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3442 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3443 | r = -ENOMEM; |
d1ac91d8 | 3444 | if (!u.xcrs) |
2d5b5a66 SY |
3445 | break; |
3446 | ||
d1ac91d8 | 3447 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3448 | |
3449 | r = -EFAULT; | |
d1ac91d8 | 3450 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3451 | sizeof(struct kvm_xcrs))) |
3452 | break; | |
3453 | r = 0; | |
3454 | break; | |
3455 | } | |
3456 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3457 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3458 | if (IS_ERR(u.xcrs)) |
3459 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3460 | |
d1ac91d8 | 3461 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3462 | break; |
3463 | } | |
92a1f12d JR |
3464 | case KVM_SET_TSC_KHZ: { |
3465 | u32 user_tsc_khz; | |
3466 | ||
3467 | r = -EINVAL; | |
92a1f12d JR |
3468 | user_tsc_khz = (u32)arg; |
3469 | ||
3470 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3471 | goto out; | |
3472 | ||
cc578287 ZA |
3473 | if (user_tsc_khz == 0) |
3474 | user_tsc_khz = tsc_khz; | |
3475 | ||
3476 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
3477 | |
3478 | r = 0; | |
3479 | goto out; | |
3480 | } | |
3481 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3482 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3483 | goto out; |
3484 | } | |
1c0b28c2 EM |
3485 | case KVM_KVMCLOCK_CTRL: { |
3486 | r = kvm_set_guest_paused(vcpu); | |
3487 | goto out; | |
3488 | } | |
313a3dc7 CO |
3489 | default: |
3490 | r = -EINVAL; | |
3491 | } | |
3492 | out: | |
d1ac91d8 | 3493 | kfree(u.buffer); |
313a3dc7 CO |
3494 | return r; |
3495 | } | |
3496 | ||
5b1c1493 CO |
3497 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3498 | { | |
3499 | return VM_FAULT_SIGBUS; | |
3500 | } | |
3501 | ||
1fe779f8 CO |
3502 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3503 | { | |
3504 | int ret; | |
3505 | ||
3506 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3507 | return -EINVAL; |
1fe779f8 CO |
3508 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3509 | return ret; | |
3510 | } | |
3511 | ||
b927a3ce SY |
3512 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3513 | u64 ident_addr) | |
3514 | { | |
3515 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3516 | return 0; | |
3517 | } | |
3518 | ||
1fe779f8 CO |
3519 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3520 | u32 kvm_nr_mmu_pages) | |
3521 | { | |
3522 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3523 | return -EINVAL; | |
3524 | ||
79fac95e | 3525 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3526 | |
3527 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3528 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3529 | |
79fac95e | 3530 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3531 | return 0; |
3532 | } | |
3533 | ||
3534 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3535 | { | |
39de71ec | 3536 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3537 | } |
3538 | ||
1fe779f8 CO |
3539 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3540 | { | |
3541 | int r; | |
3542 | ||
3543 | r = 0; | |
3544 | switch (chip->chip_id) { | |
3545 | case KVM_IRQCHIP_PIC_MASTER: | |
3546 | memcpy(&chip->chip.pic, | |
3547 | &pic_irqchip(kvm)->pics[0], | |
3548 | sizeof(struct kvm_pic_state)); | |
3549 | break; | |
3550 | case KVM_IRQCHIP_PIC_SLAVE: | |
3551 | memcpy(&chip->chip.pic, | |
3552 | &pic_irqchip(kvm)->pics[1], | |
3553 | sizeof(struct kvm_pic_state)); | |
3554 | break; | |
3555 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3556 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3557 | break; |
3558 | default: | |
3559 | r = -EINVAL; | |
3560 | break; | |
3561 | } | |
3562 | return r; | |
3563 | } | |
3564 | ||
3565 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3566 | { | |
3567 | int r; | |
3568 | ||
3569 | r = 0; | |
3570 | switch (chip->chip_id) { | |
3571 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3572 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3573 | memcpy(&pic_irqchip(kvm)->pics[0], |
3574 | &chip->chip.pic, | |
3575 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3576 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3577 | break; |
3578 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3579 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3580 | memcpy(&pic_irqchip(kvm)->pics[1], |
3581 | &chip->chip.pic, | |
3582 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3583 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3584 | break; |
3585 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3586 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3587 | break; |
3588 | default: | |
3589 | r = -EINVAL; | |
3590 | break; | |
3591 | } | |
3592 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3593 | return r; | |
3594 | } | |
3595 | ||
e0f63cb9 SY |
3596 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3597 | { | |
3598 | int r = 0; | |
3599 | ||
894a9c55 | 3600 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3601 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3602 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3603 | return r; |
3604 | } | |
3605 | ||
3606 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3607 | { | |
3608 | int r = 0; | |
3609 | ||
894a9c55 | 3610 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3611 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3612 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3613 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3614 | return r; | |
3615 | } | |
3616 | ||
3617 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3618 | { | |
3619 | int r = 0; | |
3620 | ||
3621 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3622 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3623 | sizeof(ps->channels)); | |
3624 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3625 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3626 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3627 | return r; |
3628 | } | |
3629 | ||
3630 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3631 | { | |
3632 | int r = 0, start = 0; | |
3633 | u32 prev_legacy, cur_legacy; | |
3634 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3635 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3636 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3637 | if (!prev_legacy && cur_legacy) | |
3638 | start = 1; | |
3639 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3640 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3641 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3642 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3643 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3644 | return r; |
3645 | } | |
3646 | ||
52d939a0 MT |
3647 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3648 | struct kvm_reinject_control *control) | |
3649 | { | |
3650 | if (!kvm->arch.vpit) | |
3651 | return -ENXIO; | |
894a9c55 | 3652 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3653 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3654 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3655 | return 0; |
3656 | } | |
3657 | ||
95d4c16c | 3658 | /** |
60c34612 TY |
3659 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3660 | * @kvm: kvm instance | |
3661 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3662 | * |
60c34612 TY |
3663 | * We need to keep it in mind that VCPU threads can write to the bitmap |
3664 | * concurrently. So, to avoid losing data, we keep the following order for | |
3665 | * each bit: | |
95d4c16c | 3666 | * |
60c34612 TY |
3667 | * 1. Take a snapshot of the bit and clear it if needed. |
3668 | * 2. Write protect the corresponding page. | |
3669 | * 3. Flush TLB's if needed. | |
3670 | * 4. Copy the snapshot to the userspace. | |
95d4c16c | 3671 | * |
60c34612 TY |
3672 | * Between 2 and 3, the guest may write to the page using the remaining TLB |
3673 | * entry. This is not a problem because the page will be reported dirty at | |
3674 | * step 4 using the snapshot taken before and step 3 ensures that successive | |
3675 | * writes will be logged for the next call. | |
5bb064dc | 3676 | */ |
60c34612 | 3677 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3678 | { |
7850ac54 | 3679 | int r; |
5bb064dc | 3680 | struct kvm_memory_slot *memslot; |
60c34612 TY |
3681 | unsigned long n, i; |
3682 | unsigned long *dirty_bitmap; | |
3683 | unsigned long *dirty_bitmap_buffer; | |
3684 | bool is_dirty = false; | |
5bb064dc | 3685 | |
79fac95e | 3686 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3687 | |
b050b015 | 3688 | r = -EINVAL; |
bbacc0c1 | 3689 | if (log->slot >= KVM_USER_MEM_SLOTS) |
b050b015 MT |
3690 | goto out; |
3691 | ||
28a37544 | 3692 | memslot = id_to_memslot(kvm->memslots, log->slot); |
60c34612 TY |
3693 | |
3694 | dirty_bitmap = memslot->dirty_bitmap; | |
b050b015 | 3695 | r = -ENOENT; |
60c34612 | 3696 | if (!dirty_bitmap) |
b050b015 MT |
3697 | goto out; |
3698 | ||
87bf6e7d | 3699 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3700 | |
60c34612 TY |
3701 | dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long); |
3702 | memset(dirty_bitmap_buffer, 0, n); | |
b050b015 | 3703 | |
60c34612 | 3704 | spin_lock(&kvm->mmu_lock); |
b050b015 | 3705 | |
60c34612 TY |
3706 | for (i = 0; i < n / sizeof(long); i++) { |
3707 | unsigned long mask; | |
3708 | gfn_t offset; | |
cdfca7b3 | 3709 | |
60c34612 TY |
3710 | if (!dirty_bitmap[i]) |
3711 | continue; | |
b050b015 | 3712 | |
60c34612 | 3713 | is_dirty = true; |
914ebccd | 3714 | |
60c34612 TY |
3715 | mask = xchg(&dirty_bitmap[i], 0); |
3716 | dirty_bitmap_buffer[i] = mask; | |
edde99ce | 3717 | |
60c34612 TY |
3718 | offset = i * BITS_PER_LONG; |
3719 | kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); | |
5bb064dc | 3720 | } |
60c34612 TY |
3721 | |
3722 | spin_unlock(&kvm->mmu_lock); | |
3723 | ||
198c74f4 XG |
3724 | /* See the comments in kvm_mmu_slot_remove_write_access(). */ |
3725 | lockdep_assert_held(&kvm->slots_lock); | |
3726 | ||
3727 | /* | |
3728 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
3729 | * kvm_mmu_slot_remove_write_access(). | |
3730 | */ | |
3731 | if (is_dirty) | |
3732 | kvm_flush_remote_tlbs(kvm); | |
3733 | ||
60c34612 TY |
3734 | r = -EFAULT; |
3735 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) | |
3736 | goto out; | |
b050b015 | 3737 | |
5bb064dc ZX |
3738 | r = 0; |
3739 | out: | |
79fac95e | 3740 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3741 | return r; |
3742 | } | |
3743 | ||
aa2fbe6d YZ |
3744 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3745 | bool line_status) | |
23d43cf9 CD |
3746 | { |
3747 | if (!irqchip_in_kernel(kvm)) | |
3748 | return -ENXIO; | |
3749 | ||
3750 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3751 | irq_event->irq, irq_event->level, |
3752 | line_status); | |
23d43cf9 CD |
3753 | return 0; |
3754 | } | |
3755 | ||
1fe779f8 CO |
3756 | long kvm_arch_vm_ioctl(struct file *filp, |
3757 | unsigned int ioctl, unsigned long arg) | |
3758 | { | |
3759 | struct kvm *kvm = filp->private_data; | |
3760 | void __user *argp = (void __user *)arg; | |
367e1319 | 3761 | int r = -ENOTTY; |
f0d66275 DH |
3762 | /* |
3763 | * This union makes it completely explicit to gcc-3.x | |
3764 | * that these two variables' stack usage should be | |
3765 | * combined, not added together. | |
3766 | */ | |
3767 | union { | |
3768 | struct kvm_pit_state ps; | |
e9f42757 | 3769 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3770 | struct kvm_pit_config pit_config; |
f0d66275 | 3771 | } u; |
1fe779f8 CO |
3772 | |
3773 | switch (ioctl) { | |
3774 | case KVM_SET_TSS_ADDR: | |
3775 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 3776 | break; |
b927a3ce SY |
3777 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3778 | u64 ident_addr; | |
3779 | ||
3780 | r = -EFAULT; | |
3781 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3782 | goto out; | |
3783 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
3784 | break; |
3785 | } | |
1fe779f8 CO |
3786 | case KVM_SET_NR_MMU_PAGES: |
3787 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
3788 | break; |
3789 | case KVM_GET_NR_MMU_PAGES: | |
3790 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3791 | break; | |
3ddea128 MT |
3792 | case KVM_CREATE_IRQCHIP: { |
3793 | struct kvm_pic *vpic; | |
3794 | ||
3795 | mutex_lock(&kvm->lock); | |
3796 | r = -EEXIST; | |
3797 | if (kvm->arch.vpic) | |
3798 | goto create_irqchip_unlock; | |
3e515705 AK |
3799 | r = -EINVAL; |
3800 | if (atomic_read(&kvm->online_vcpus)) | |
3801 | goto create_irqchip_unlock; | |
1fe779f8 | 3802 | r = -ENOMEM; |
3ddea128 MT |
3803 | vpic = kvm_create_pic(kvm); |
3804 | if (vpic) { | |
1fe779f8 CO |
3805 | r = kvm_ioapic_init(kvm); |
3806 | if (r) { | |
175504cd | 3807 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 3808 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
3809 | &vpic->dev_master); |
3810 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3811 | &vpic->dev_slave); | |
3812 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3813 | &vpic->dev_eclr); | |
175504cd | 3814 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
3815 | kfree(vpic); |
3816 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3817 | } |
3818 | } else | |
3ddea128 MT |
3819 | goto create_irqchip_unlock; |
3820 | smp_wmb(); | |
3821 | kvm->arch.vpic = vpic; | |
3822 | smp_wmb(); | |
399ec807 AK |
3823 | r = kvm_setup_default_irq_routing(kvm); |
3824 | if (r) { | |
175504cd | 3825 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3826 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3827 | kvm_ioapic_destroy(kvm); |
3828 | kvm_destroy_pic(kvm); | |
3ddea128 | 3829 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3830 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 3831 | } |
3ddea128 MT |
3832 | create_irqchip_unlock: |
3833 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3834 | break; |
3ddea128 | 3835 | } |
7837699f | 3836 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3837 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3838 | goto create_pit; | |
3839 | case KVM_CREATE_PIT2: | |
3840 | r = -EFAULT; | |
3841 | if (copy_from_user(&u.pit_config, argp, | |
3842 | sizeof(struct kvm_pit_config))) | |
3843 | goto out; | |
3844 | create_pit: | |
79fac95e | 3845 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3846 | r = -EEXIST; |
3847 | if (kvm->arch.vpit) | |
3848 | goto create_pit_unlock; | |
7837699f | 3849 | r = -ENOMEM; |
c5ff41ce | 3850 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3851 | if (kvm->arch.vpit) |
3852 | r = 0; | |
269e05e4 | 3853 | create_pit_unlock: |
79fac95e | 3854 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3855 | break; |
1fe779f8 CO |
3856 | case KVM_GET_IRQCHIP: { |
3857 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3858 | struct kvm_irqchip *chip; |
1fe779f8 | 3859 | |
ff5c2c03 SL |
3860 | chip = memdup_user(argp, sizeof(*chip)); |
3861 | if (IS_ERR(chip)) { | |
3862 | r = PTR_ERR(chip); | |
1fe779f8 | 3863 | goto out; |
ff5c2c03 SL |
3864 | } |
3865 | ||
1fe779f8 CO |
3866 | r = -ENXIO; |
3867 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3868 | goto get_irqchip_out; |
3869 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3870 | if (r) |
f0d66275 | 3871 | goto get_irqchip_out; |
1fe779f8 | 3872 | r = -EFAULT; |
f0d66275 DH |
3873 | if (copy_to_user(argp, chip, sizeof *chip)) |
3874 | goto get_irqchip_out; | |
1fe779f8 | 3875 | r = 0; |
f0d66275 DH |
3876 | get_irqchip_out: |
3877 | kfree(chip); | |
1fe779f8 CO |
3878 | break; |
3879 | } | |
3880 | case KVM_SET_IRQCHIP: { | |
3881 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3882 | struct kvm_irqchip *chip; |
1fe779f8 | 3883 | |
ff5c2c03 SL |
3884 | chip = memdup_user(argp, sizeof(*chip)); |
3885 | if (IS_ERR(chip)) { | |
3886 | r = PTR_ERR(chip); | |
1fe779f8 | 3887 | goto out; |
ff5c2c03 SL |
3888 | } |
3889 | ||
1fe779f8 CO |
3890 | r = -ENXIO; |
3891 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3892 | goto set_irqchip_out; |
3893 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3894 | if (r) |
f0d66275 | 3895 | goto set_irqchip_out; |
1fe779f8 | 3896 | r = 0; |
f0d66275 DH |
3897 | set_irqchip_out: |
3898 | kfree(chip); | |
1fe779f8 CO |
3899 | break; |
3900 | } | |
e0f63cb9 | 3901 | case KVM_GET_PIT: { |
e0f63cb9 | 3902 | r = -EFAULT; |
f0d66275 | 3903 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3904 | goto out; |
3905 | r = -ENXIO; | |
3906 | if (!kvm->arch.vpit) | |
3907 | goto out; | |
f0d66275 | 3908 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3909 | if (r) |
3910 | goto out; | |
3911 | r = -EFAULT; | |
f0d66275 | 3912 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3913 | goto out; |
3914 | r = 0; | |
3915 | break; | |
3916 | } | |
3917 | case KVM_SET_PIT: { | |
e0f63cb9 | 3918 | r = -EFAULT; |
f0d66275 | 3919 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3920 | goto out; |
3921 | r = -ENXIO; | |
3922 | if (!kvm->arch.vpit) | |
3923 | goto out; | |
f0d66275 | 3924 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3925 | break; |
3926 | } | |
e9f42757 BK |
3927 | case KVM_GET_PIT2: { |
3928 | r = -ENXIO; | |
3929 | if (!kvm->arch.vpit) | |
3930 | goto out; | |
3931 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3932 | if (r) | |
3933 | goto out; | |
3934 | r = -EFAULT; | |
3935 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3936 | goto out; | |
3937 | r = 0; | |
3938 | break; | |
3939 | } | |
3940 | case KVM_SET_PIT2: { | |
3941 | r = -EFAULT; | |
3942 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3943 | goto out; | |
3944 | r = -ENXIO; | |
3945 | if (!kvm->arch.vpit) | |
3946 | goto out; | |
3947 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
3948 | break; |
3949 | } | |
52d939a0 MT |
3950 | case KVM_REINJECT_CONTROL: { |
3951 | struct kvm_reinject_control control; | |
3952 | r = -EFAULT; | |
3953 | if (copy_from_user(&control, argp, sizeof(control))) | |
3954 | goto out; | |
3955 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
3956 | break; |
3957 | } | |
ffde22ac ES |
3958 | case KVM_XEN_HVM_CONFIG: { |
3959 | r = -EFAULT; | |
3960 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3961 | sizeof(struct kvm_xen_hvm_config))) | |
3962 | goto out; | |
3963 | r = -EINVAL; | |
3964 | if (kvm->arch.xen_hvm_config.flags) | |
3965 | goto out; | |
3966 | r = 0; | |
3967 | break; | |
3968 | } | |
afbcf7ab | 3969 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3970 | struct kvm_clock_data user_ns; |
3971 | u64 now_ns; | |
3972 | s64 delta; | |
3973 | ||
3974 | r = -EFAULT; | |
3975 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3976 | goto out; | |
3977 | ||
3978 | r = -EINVAL; | |
3979 | if (user_ns.flags) | |
3980 | goto out; | |
3981 | ||
3982 | r = 0; | |
395c6b0a | 3983 | local_irq_disable(); |
759379dd | 3984 | now_ns = get_kernel_ns(); |
afbcf7ab | 3985 | delta = user_ns.clock - now_ns; |
395c6b0a | 3986 | local_irq_enable(); |
afbcf7ab | 3987 | kvm->arch.kvmclock_offset = delta; |
2e762ff7 | 3988 | kvm_gen_update_masterclock(kvm); |
afbcf7ab GC |
3989 | break; |
3990 | } | |
3991 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3992 | struct kvm_clock_data user_ns; |
3993 | u64 now_ns; | |
3994 | ||
395c6b0a | 3995 | local_irq_disable(); |
759379dd | 3996 | now_ns = get_kernel_ns(); |
afbcf7ab | 3997 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3998 | local_irq_enable(); |
afbcf7ab | 3999 | user_ns.flags = 0; |
97e69aa6 | 4000 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4001 | |
4002 | r = -EFAULT; | |
4003 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4004 | goto out; | |
4005 | r = 0; | |
4006 | break; | |
4007 | } | |
4008 | ||
1fe779f8 CO |
4009 | default: |
4010 | ; | |
4011 | } | |
4012 | out: | |
4013 | return r; | |
4014 | } | |
4015 | ||
a16b043c | 4016 | static void kvm_init_msr_list(void) |
043405e1 CO |
4017 | { |
4018 | u32 dummy[2]; | |
4019 | unsigned i, j; | |
4020 | ||
e3267cbb GC |
4021 | /* skip the first msrs in the list. KVM-specific */ |
4022 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
4023 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4024 | continue; | |
93c4adc7 PB |
4025 | |
4026 | /* | |
4027 | * Even MSRs that are valid in the host may not be exposed | |
4028 | * to the guests in some cases. We could work around this | |
4029 | * in VMX with the generic MSR save/load machinery, but it | |
4030 | * is not really worthwhile since it will really only | |
4031 | * happen with nested virtualization. | |
4032 | */ | |
4033 | switch (msrs_to_save[i]) { | |
4034 | case MSR_IA32_BNDCFGS: | |
4035 | if (!kvm_x86_ops->mpx_supported()) | |
4036 | continue; | |
4037 | break; | |
4038 | default: | |
4039 | break; | |
4040 | } | |
4041 | ||
043405e1 CO |
4042 | if (j < i) |
4043 | msrs_to_save[j] = msrs_to_save[i]; | |
4044 | j++; | |
4045 | } | |
4046 | num_msrs_to_save = j; | |
4047 | } | |
4048 | ||
bda9020e MT |
4049 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4050 | const void *v) | |
bbd9b64e | 4051 | { |
70252a10 AK |
4052 | int handled = 0; |
4053 | int n; | |
4054 | ||
4055 | do { | |
4056 | n = min(len, 8); | |
4057 | if (!(vcpu->arch.apic && | |
4058 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) | |
4059 | && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
4060 | break; | |
4061 | handled += n; | |
4062 | addr += n; | |
4063 | len -= n; | |
4064 | v += n; | |
4065 | } while (len); | |
bbd9b64e | 4066 | |
70252a10 | 4067 | return handled; |
bbd9b64e CO |
4068 | } |
4069 | ||
bda9020e | 4070 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4071 | { |
70252a10 AK |
4072 | int handled = 0; |
4073 | int n; | |
4074 | ||
4075 | do { | |
4076 | n = min(len, 8); | |
4077 | if (!(vcpu->arch.apic && | |
4078 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) | |
4079 | && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
4080 | break; | |
4081 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
4082 | handled += n; | |
4083 | addr += n; | |
4084 | len -= n; | |
4085 | v += n; | |
4086 | } while (len); | |
bbd9b64e | 4087 | |
70252a10 | 4088 | return handled; |
bbd9b64e CO |
4089 | } |
4090 | ||
2dafc6c2 GN |
4091 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4092 | struct kvm_segment *var, int seg) | |
4093 | { | |
4094 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4095 | } | |
4096 | ||
4097 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4098 | struct kvm_segment *var, int seg) | |
4099 | { | |
4100 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4101 | } | |
4102 | ||
54987b7a PB |
4103 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4104 | struct x86_exception *exception) | |
02f59dc9 JR |
4105 | { |
4106 | gpa_t t_gpa; | |
02f59dc9 JR |
4107 | |
4108 | BUG_ON(!mmu_is_nested(vcpu)); | |
4109 | ||
4110 | /* NPT walks are always user-walks */ | |
4111 | access |= PFERR_USER_MASK; | |
54987b7a | 4112 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4113 | |
4114 | return t_gpa; | |
4115 | } | |
4116 | ||
ab9ae313 AK |
4117 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4118 | struct x86_exception *exception) | |
1871c602 GN |
4119 | { |
4120 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4121 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4122 | } |
4123 | ||
ab9ae313 AK |
4124 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4125 | struct x86_exception *exception) | |
1871c602 GN |
4126 | { |
4127 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4128 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4129 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4130 | } |
4131 | ||
ab9ae313 AK |
4132 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4133 | struct x86_exception *exception) | |
1871c602 GN |
4134 | { |
4135 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4136 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4137 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4138 | } |
4139 | ||
4140 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4141 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4142 | struct x86_exception *exception) | |
1871c602 | 4143 | { |
ab9ae313 | 4144 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4145 | } |
4146 | ||
4147 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4148 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4149 | struct x86_exception *exception) |
bbd9b64e CO |
4150 | { |
4151 | void *data = val; | |
10589a46 | 4152 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4153 | |
4154 | while (bytes) { | |
14dfe855 | 4155 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4156 | exception); |
bbd9b64e | 4157 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4158 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4159 | int ret; |
4160 | ||
bcc55cba | 4161 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4162 | return X86EMUL_PROPAGATE_FAULT; |
44583cba PB |
4163 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, |
4164 | offset, toread); | |
10589a46 | 4165 | if (ret < 0) { |
c3cd7ffa | 4166 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4167 | goto out; |
4168 | } | |
bbd9b64e | 4169 | |
77c2002e IE |
4170 | bytes -= toread; |
4171 | data += toread; | |
4172 | addr += toread; | |
bbd9b64e | 4173 | } |
10589a46 | 4174 | out: |
10589a46 | 4175 | return r; |
bbd9b64e | 4176 | } |
77c2002e | 4177 | |
1871c602 | 4178 | /* used for instruction fetching */ |
0f65dd70 AK |
4179 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4180 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4181 | struct x86_exception *exception) |
1871c602 | 4182 | { |
0f65dd70 | 4183 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4184 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4185 | unsigned offset; |
4186 | int ret; | |
0f65dd70 | 4187 | |
44583cba PB |
4188 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4189 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4190 | exception); | |
4191 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4192 | return X86EMUL_PROPAGATE_FAULT; | |
4193 | ||
4194 | offset = addr & (PAGE_SIZE-1); | |
4195 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4196 | bytes = (unsigned)PAGE_SIZE - offset; | |
4197 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, | |
4198 | offset, bytes); | |
4199 | if (unlikely(ret < 0)) | |
4200 | return X86EMUL_IO_NEEDED; | |
4201 | ||
4202 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4203 | } |
4204 | ||
064aea77 | 4205 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4206 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4207 | struct x86_exception *exception) |
1871c602 | 4208 | { |
0f65dd70 | 4209 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4210 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4211 | |
1871c602 | 4212 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4213 | exception); |
1871c602 | 4214 | } |
064aea77 | 4215 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4216 | |
0f65dd70 AK |
4217 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4218 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4219 | struct x86_exception *exception) |
1871c602 | 4220 | { |
0f65dd70 | 4221 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4222 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4223 | } |
4224 | ||
6a4d7550 | 4225 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4226 | gva_t addr, void *val, |
2dafc6c2 | 4227 | unsigned int bytes, |
bcc55cba | 4228 | struct x86_exception *exception) |
77c2002e | 4229 | { |
0f65dd70 | 4230 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4231 | void *data = val; |
4232 | int r = X86EMUL_CONTINUE; | |
4233 | ||
4234 | while (bytes) { | |
14dfe855 JR |
4235 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4236 | PFERR_WRITE_MASK, | |
ab9ae313 | 4237 | exception); |
77c2002e IE |
4238 | unsigned offset = addr & (PAGE_SIZE-1); |
4239 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4240 | int ret; | |
4241 | ||
bcc55cba | 4242 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4243 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
4244 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
4245 | if (ret < 0) { | |
c3cd7ffa | 4246 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4247 | goto out; |
4248 | } | |
4249 | ||
4250 | bytes -= towrite; | |
4251 | data += towrite; | |
4252 | addr += towrite; | |
4253 | } | |
4254 | out: | |
4255 | return r; | |
4256 | } | |
6a4d7550 | 4257 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4258 | |
af7cc7d1 XG |
4259 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4260 | gpa_t *gpa, struct x86_exception *exception, | |
4261 | bool write) | |
4262 | { | |
97d64b78 AK |
4263 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4264 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4265 | |
97d64b78 | 4266 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 FW |
4267 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
4268 | vcpu->arch.access, access)) { | |
bebb106a XG |
4269 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4270 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4271 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4272 | return 1; |
4273 | } | |
4274 | ||
af7cc7d1 XG |
4275 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4276 | ||
4277 | if (*gpa == UNMAPPED_GVA) | |
4278 | return -1; | |
4279 | ||
4280 | /* For APIC access vmexit */ | |
4281 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4282 | return 1; | |
4283 | ||
4f022648 XG |
4284 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4285 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4286 | return 1; |
4f022648 | 4287 | } |
bebb106a | 4288 | |
af7cc7d1 XG |
4289 | return 0; |
4290 | } | |
4291 | ||
3200f405 | 4292 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4293 | const void *val, int bytes) |
bbd9b64e CO |
4294 | { |
4295 | int ret; | |
4296 | ||
4297 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 4298 | if (ret < 0) |
bbd9b64e | 4299 | return 0; |
f57f2ef5 | 4300 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4301 | return 1; |
4302 | } | |
4303 | ||
77d197b2 XG |
4304 | struct read_write_emulator_ops { |
4305 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4306 | int bytes); | |
4307 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4308 | void *val, int bytes); | |
4309 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4310 | int bytes, void *val); | |
4311 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4312 | void *val, int bytes); | |
4313 | bool write; | |
4314 | }; | |
4315 | ||
4316 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4317 | { | |
4318 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4319 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4320 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4321 | vcpu->mmio_read_completed = 0; |
4322 | return 1; | |
4323 | } | |
4324 | ||
4325 | return 0; | |
4326 | } | |
4327 | ||
4328 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4329 | void *val, int bytes) | |
4330 | { | |
4331 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
4332 | } | |
4333 | ||
4334 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4335 | void *val, int bytes) | |
4336 | { | |
4337 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4338 | } | |
4339 | ||
4340 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4341 | { | |
4342 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4343 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4344 | } | |
4345 | ||
4346 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4347 | void *val, int bytes) | |
4348 | { | |
4349 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4350 | return X86EMUL_IO_NEEDED; | |
4351 | } | |
4352 | ||
4353 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4354 | void *val, int bytes) | |
4355 | { | |
f78146b0 AK |
4356 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4357 | ||
87da7e66 | 4358 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4359 | return X86EMUL_CONTINUE; |
4360 | } | |
4361 | ||
0fbe9b0b | 4362 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4363 | .read_write_prepare = read_prepare, |
4364 | .read_write_emulate = read_emulate, | |
4365 | .read_write_mmio = vcpu_mmio_read, | |
4366 | .read_write_exit_mmio = read_exit_mmio, | |
4367 | }; | |
4368 | ||
0fbe9b0b | 4369 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4370 | .read_write_emulate = write_emulate, |
4371 | .read_write_mmio = write_mmio, | |
4372 | .read_write_exit_mmio = write_exit_mmio, | |
4373 | .write = true, | |
4374 | }; | |
4375 | ||
22388a3c XG |
4376 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4377 | unsigned int bytes, | |
4378 | struct x86_exception *exception, | |
4379 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4380 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4381 | { |
af7cc7d1 XG |
4382 | gpa_t gpa; |
4383 | int handled, ret; | |
22388a3c | 4384 | bool write = ops->write; |
f78146b0 | 4385 | struct kvm_mmio_fragment *frag; |
10589a46 | 4386 | |
22388a3c | 4387 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4388 | |
af7cc7d1 | 4389 | if (ret < 0) |
bbd9b64e | 4390 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4391 | |
4392 | /* For APIC access vmexit */ | |
af7cc7d1 | 4393 | if (ret) |
bbd9b64e CO |
4394 | goto mmio; |
4395 | ||
22388a3c | 4396 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4397 | return X86EMUL_CONTINUE; |
4398 | ||
4399 | mmio: | |
4400 | /* | |
4401 | * Is this MMIO handled locally? | |
4402 | */ | |
22388a3c | 4403 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4404 | if (handled == bytes) |
bbd9b64e | 4405 | return X86EMUL_CONTINUE; |
bbd9b64e | 4406 | |
70252a10 AK |
4407 | gpa += handled; |
4408 | bytes -= handled; | |
4409 | val += handled; | |
4410 | ||
87da7e66 XG |
4411 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4412 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4413 | frag->gpa = gpa; | |
4414 | frag->data = val; | |
4415 | frag->len = bytes; | |
f78146b0 | 4416 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4417 | } |
4418 | ||
22388a3c XG |
4419 | int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, |
4420 | void *val, unsigned int bytes, | |
4421 | struct x86_exception *exception, | |
0fbe9b0b | 4422 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4423 | { |
0f65dd70 | 4424 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4425 | gpa_t gpa; |
4426 | int rc; | |
4427 | ||
4428 | if (ops->read_write_prepare && | |
4429 | ops->read_write_prepare(vcpu, val, bytes)) | |
4430 | return X86EMUL_CONTINUE; | |
4431 | ||
4432 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4433 | |
bbd9b64e CO |
4434 | /* Crossing a page boundary? */ |
4435 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4436 | int now; |
bbd9b64e CO |
4437 | |
4438 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4439 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4440 | vcpu, ops); | |
4441 | ||
bbd9b64e CO |
4442 | if (rc != X86EMUL_CONTINUE) |
4443 | return rc; | |
4444 | addr += now; | |
4445 | val += now; | |
4446 | bytes -= now; | |
4447 | } | |
22388a3c | 4448 | |
f78146b0 AK |
4449 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4450 | vcpu, ops); | |
4451 | if (rc != X86EMUL_CONTINUE) | |
4452 | return rc; | |
4453 | ||
4454 | if (!vcpu->mmio_nr_fragments) | |
4455 | return rc; | |
4456 | ||
4457 | gpa = vcpu->mmio_fragments[0].gpa; | |
4458 | ||
4459 | vcpu->mmio_needed = 1; | |
4460 | vcpu->mmio_cur_fragment = 0; | |
4461 | ||
87da7e66 | 4462 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4463 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4464 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4465 | vcpu->run->mmio.phys_addr = gpa; | |
4466 | ||
4467 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4468 | } |
4469 | ||
4470 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4471 | unsigned long addr, | |
4472 | void *val, | |
4473 | unsigned int bytes, | |
4474 | struct x86_exception *exception) | |
4475 | { | |
4476 | return emulator_read_write(ctxt, addr, val, bytes, | |
4477 | exception, &read_emultor); | |
4478 | } | |
4479 | ||
4480 | int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, | |
4481 | unsigned long addr, | |
4482 | const void *val, | |
4483 | unsigned int bytes, | |
4484 | struct x86_exception *exception) | |
4485 | { | |
4486 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4487 | exception, &write_emultor); | |
bbd9b64e | 4488 | } |
bbd9b64e | 4489 | |
daea3e73 AK |
4490 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4491 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4492 | ||
4493 | #ifdef CONFIG_X86_64 | |
4494 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4495 | #else | |
4496 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4497 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4498 | #endif |
4499 | ||
0f65dd70 AK |
4500 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4501 | unsigned long addr, | |
bbd9b64e CO |
4502 | const void *old, |
4503 | const void *new, | |
4504 | unsigned int bytes, | |
0f65dd70 | 4505 | struct x86_exception *exception) |
bbd9b64e | 4506 | { |
0f65dd70 | 4507 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4508 | gpa_t gpa; |
4509 | struct page *page; | |
4510 | char *kaddr; | |
4511 | bool exchanged; | |
2bacc55c | 4512 | |
daea3e73 AK |
4513 | /* guests cmpxchg8b have to be emulated atomically */ |
4514 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4515 | goto emul_write; | |
10589a46 | 4516 | |
daea3e73 | 4517 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4518 | |
daea3e73 AK |
4519 | if (gpa == UNMAPPED_GVA || |
4520 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4521 | goto emul_write; | |
2bacc55c | 4522 | |
daea3e73 AK |
4523 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4524 | goto emul_write; | |
72dc67a6 | 4525 | |
daea3e73 | 4526 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
32cad84f | 4527 | if (is_error_page(page)) |
c19b8bd6 | 4528 | goto emul_write; |
72dc67a6 | 4529 | |
8fd75e12 | 4530 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4531 | kaddr += offset_in_page(gpa); |
4532 | switch (bytes) { | |
4533 | case 1: | |
4534 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4535 | break; | |
4536 | case 2: | |
4537 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4538 | break; | |
4539 | case 4: | |
4540 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4541 | break; | |
4542 | case 8: | |
4543 | exchanged = CMPXCHG64(kaddr, old, new); | |
4544 | break; | |
4545 | default: | |
4546 | BUG(); | |
2bacc55c | 4547 | } |
8fd75e12 | 4548 | kunmap_atomic(kaddr); |
daea3e73 AK |
4549 | kvm_release_page_dirty(page); |
4550 | ||
4551 | if (!exchanged) | |
4552 | return X86EMUL_CMPXCHG_FAILED; | |
4553 | ||
d3714010 | 4554 | mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); |
f57f2ef5 | 4555 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4556 | |
4557 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4558 | |
3200f405 | 4559 | emul_write: |
daea3e73 | 4560 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4561 | |
0f65dd70 | 4562 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4563 | } |
4564 | ||
cf8f70bf GN |
4565 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4566 | { | |
4567 | /* TODO: String I/O for in kernel device */ | |
4568 | int r; | |
4569 | ||
4570 | if (vcpu->arch.pio.in) | |
4571 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
4572 | vcpu->arch.pio.size, pd); | |
4573 | else | |
4574 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
4575 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
4576 | pd); | |
4577 | return r; | |
4578 | } | |
4579 | ||
6f6fbe98 XG |
4580 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4581 | unsigned short port, void *val, | |
4582 | unsigned int count, bool in) | |
cf8f70bf | 4583 | { |
cf8f70bf | 4584 | vcpu->arch.pio.port = port; |
6f6fbe98 | 4585 | vcpu->arch.pio.in = in; |
7972995b | 4586 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4587 | vcpu->arch.pio.size = size; |
4588 | ||
4589 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4590 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4591 | return 1; |
4592 | } | |
4593 | ||
4594 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4595 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4596 | vcpu->run->io.size = size; |
4597 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4598 | vcpu->run->io.count = count; | |
4599 | vcpu->run->io.port = port; | |
4600 | ||
4601 | return 0; | |
4602 | } | |
4603 | ||
6f6fbe98 XG |
4604 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4605 | int size, unsigned short port, void *val, | |
4606 | unsigned int count) | |
cf8f70bf | 4607 | { |
ca1d4a9e | 4608 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4609 | int ret; |
ca1d4a9e | 4610 | |
6f6fbe98 XG |
4611 | if (vcpu->arch.pio.count) |
4612 | goto data_avail; | |
cf8f70bf | 4613 | |
6f6fbe98 XG |
4614 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4615 | if (ret) { | |
4616 | data_avail: | |
4617 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 4618 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 4619 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4620 | return 1; |
4621 | } | |
4622 | ||
cf8f70bf GN |
4623 | return 0; |
4624 | } | |
4625 | ||
6f6fbe98 XG |
4626 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4627 | int size, unsigned short port, | |
4628 | const void *val, unsigned int count) | |
4629 | { | |
4630 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4631 | ||
4632 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 4633 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
4634 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
4635 | } | |
4636 | ||
bbd9b64e CO |
4637 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4638 | { | |
4639 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4640 | } | |
4641 | ||
3cb16fe7 | 4642 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4643 | { |
3cb16fe7 | 4644 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4645 | } |
4646 | ||
f5f48ee1 SY |
4647 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
4648 | { | |
4649 | if (!need_emulate_wbinvd(vcpu)) | |
4650 | return X86EMUL_CONTINUE; | |
4651 | ||
4652 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4653 | int cpu = get_cpu(); |
4654 | ||
4655 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4656 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4657 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4658 | put_cpu(); |
f5f48ee1 | 4659 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4660 | } else |
4661 | wbinvd(); | |
f5f48ee1 SY |
4662 | return X86EMUL_CONTINUE; |
4663 | } | |
4664 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4665 | ||
bcaf5cc5 AK |
4666 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4667 | { | |
4668 | kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); | |
4669 | } | |
4670 | ||
717746e3 | 4671 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) |
bbd9b64e | 4672 | { |
16f8a6f9 | 4673 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4674 | } |
4675 | ||
717746e3 | 4676 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) |
bbd9b64e | 4677 | { |
338dbc97 | 4678 | |
717746e3 | 4679 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4680 | } |
4681 | ||
52a46617 | 4682 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4683 | { |
52a46617 | 4684 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4685 | } |
4686 | ||
717746e3 | 4687 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4688 | { |
717746e3 | 4689 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4690 | unsigned long value; |
4691 | ||
4692 | switch (cr) { | |
4693 | case 0: | |
4694 | value = kvm_read_cr0(vcpu); | |
4695 | break; | |
4696 | case 2: | |
4697 | value = vcpu->arch.cr2; | |
4698 | break; | |
4699 | case 3: | |
9f8fe504 | 4700 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4701 | break; |
4702 | case 4: | |
4703 | value = kvm_read_cr4(vcpu); | |
4704 | break; | |
4705 | case 8: | |
4706 | value = kvm_get_cr8(vcpu); | |
4707 | break; | |
4708 | default: | |
a737f256 | 4709 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4710 | return 0; |
4711 | } | |
4712 | ||
4713 | return value; | |
4714 | } | |
4715 | ||
717746e3 | 4716 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4717 | { |
717746e3 | 4718 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4719 | int res = 0; |
4720 | ||
52a46617 GN |
4721 | switch (cr) { |
4722 | case 0: | |
49a9b07e | 4723 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4724 | break; |
4725 | case 2: | |
4726 | vcpu->arch.cr2 = val; | |
4727 | break; | |
4728 | case 3: | |
2390218b | 4729 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4730 | break; |
4731 | case 4: | |
a83b29c6 | 4732 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4733 | break; |
4734 | case 8: | |
eea1cff9 | 4735 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4736 | break; |
4737 | default: | |
a737f256 | 4738 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4739 | res = -1; |
52a46617 | 4740 | } |
0f12244f GN |
4741 | |
4742 | return res; | |
52a46617 GN |
4743 | } |
4744 | ||
717746e3 | 4745 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4746 | { |
717746e3 | 4747 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4748 | } |
4749 | ||
4bff1e86 | 4750 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4751 | { |
4bff1e86 | 4752 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4753 | } |
4754 | ||
4bff1e86 | 4755 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4756 | { |
4bff1e86 | 4757 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4758 | } |
4759 | ||
1ac9d0cf AK |
4760 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4761 | { | |
4762 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4763 | } | |
4764 | ||
4765 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4766 | { | |
4767 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4768 | } | |
4769 | ||
4bff1e86 AK |
4770 | static unsigned long emulator_get_cached_segment_base( |
4771 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4772 | { |
4bff1e86 | 4773 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4774 | } |
4775 | ||
1aa36616 AK |
4776 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4777 | struct desc_struct *desc, u32 *base3, | |
4778 | int seg) | |
2dafc6c2 GN |
4779 | { |
4780 | struct kvm_segment var; | |
4781 | ||
4bff1e86 | 4782 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4783 | *selector = var.selector; |
2dafc6c2 | 4784 | |
378a8b09 GN |
4785 | if (var.unusable) { |
4786 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 4787 | return false; |
378a8b09 | 4788 | } |
2dafc6c2 GN |
4789 | |
4790 | if (var.g) | |
4791 | var.limit >>= 12; | |
4792 | set_desc_limit(desc, var.limit); | |
4793 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4794 | #ifdef CONFIG_X86_64 |
4795 | if (base3) | |
4796 | *base3 = var.base >> 32; | |
4797 | #endif | |
2dafc6c2 GN |
4798 | desc->type = var.type; |
4799 | desc->s = var.s; | |
4800 | desc->dpl = var.dpl; | |
4801 | desc->p = var.present; | |
4802 | desc->avl = var.avl; | |
4803 | desc->l = var.l; | |
4804 | desc->d = var.db; | |
4805 | desc->g = var.g; | |
4806 | ||
4807 | return true; | |
4808 | } | |
4809 | ||
1aa36616 AK |
4810 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4811 | struct desc_struct *desc, u32 base3, | |
4812 | int seg) | |
2dafc6c2 | 4813 | { |
4bff1e86 | 4814 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4815 | struct kvm_segment var; |
4816 | ||
1aa36616 | 4817 | var.selector = selector; |
2dafc6c2 | 4818 | var.base = get_desc_base(desc); |
5601d05b GN |
4819 | #ifdef CONFIG_X86_64 |
4820 | var.base |= ((u64)base3) << 32; | |
4821 | #endif | |
2dafc6c2 GN |
4822 | var.limit = get_desc_limit(desc); |
4823 | if (desc->g) | |
4824 | var.limit = (var.limit << 12) | 0xfff; | |
4825 | var.type = desc->type; | |
2dafc6c2 GN |
4826 | var.dpl = desc->dpl; |
4827 | var.db = desc->d; | |
4828 | var.s = desc->s; | |
4829 | var.l = desc->l; | |
4830 | var.g = desc->g; | |
4831 | var.avl = desc->avl; | |
4832 | var.present = desc->p; | |
4833 | var.unusable = !var.present; | |
4834 | var.padding = 0; | |
4835 | ||
4836 | kvm_set_segment(vcpu, &var, seg); | |
4837 | return; | |
4838 | } | |
4839 | ||
717746e3 AK |
4840 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4841 | u32 msr_index, u64 *pdata) | |
4842 | { | |
4843 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
4844 | } | |
4845 | ||
4846 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4847 | u32 msr_index, u64 data) | |
4848 | { | |
8fe8ab46 WA |
4849 | struct msr_data msr; |
4850 | ||
4851 | msr.data = data; | |
4852 | msr.index = msr_index; | |
4853 | msr.host_initiated = false; | |
4854 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
4855 | } |
4856 | ||
67f4d428 NA |
4857 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
4858 | u32 pmc) | |
4859 | { | |
4860 | return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); | |
4861 | } | |
4862 | ||
222d21aa AK |
4863 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4864 | u32 pmc, u64 *pdata) | |
4865 | { | |
4866 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4867 | } | |
4868 | ||
6c3287f7 AK |
4869 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4870 | { | |
4871 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4872 | } | |
4873 | ||
5037f6f3 AK |
4874 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4875 | { | |
4876 | preempt_disable(); | |
5197b808 | 4877 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4878 | /* |
4879 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4880 | * so it may be clear at this point. | |
4881 | */ | |
4882 | clts(); | |
4883 | } | |
4884 | ||
4885 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4886 | { | |
4887 | preempt_enable(); | |
4888 | } | |
4889 | ||
2953538e | 4890 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 4891 | struct x86_instruction_info *info, |
c4f035c6 AK |
4892 | enum x86_intercept_stage stage) |
4893 | { | |
2953538e | 4894 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
4895 | } |
4896 | ||
0017f93a | 4897 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
4898 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
4899 | { | |
0017f93a | 4900 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
4901 | } |
4902 | ||
dd856efa AK |
4903 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
4904 | { | |
4905 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
4906 | } | |
4907 | ||
4908 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
4909 | { | |
4910 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
4911 | } | |
4912 | ||
0225fb50 | 4913 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
4914 | .read_gpr = emulator_read_gpr, |
4915 | .write_gpr = emulator_write_gpr, | |
1871c602 | 4916 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4917 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4918 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4919 | .read_emulated = emulator_read_emulated, |
4920 | .write_emulated = emulator_write_emulated, | |
4921 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 4922 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
4923 | .pio_in_emulated = emulator_pio_in_emulated, |
4924 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
4925 | .get_segment = emulator_get_segment, |
4926 | .set_segment = emulator_set_segment, | |
5951c442 | 4927 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4928 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4929 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
4930 | .set_gdt = emulator_set_gdt, |
4931 | .set_idt = emulator_set_idt, | |
52a46617 GN |
4932 | .get_cr = emulator_get_cr, |
4933 | .set_cr = emulator_set_cr, | |
9c537244 | 4934 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4935 | .get_dr = emulator_get_dr, |
4936 | .set_dr = emulator_set_dr, | |
717746e3 AK |
4937 | .set_msr = emulator_set_msr, |
4938 | .get_msr = emulator_get_msr, | |
67f4d428 | 4939 | .check_pmc = emulator_check_pmc, |
222d21aa | 4940 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 4941 | .halt = emulator_halt, |
bcaf5cc5 | 4942 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 4943 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
4944 | .get_fpu = emulator_get_fpu, |
4945 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 4946 | .intercept = emulator_intercept, |
bdb42f5a | 4947 | .get_cpuid = emulator_get_cpuid, |
bbd9b64e CO |
4948 | }; |
4949 | ||
95cb2295 GN |
4950 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4951 | { | |
37ccdcbe | 4952 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
4953 | /* |
4954 | * an sti; sti; sequence only disable interrupts for the first | |
4955 | * instruction. So, if the last instruction, be it emulated or | |
4956 | * not, left the system with the INT_STI flag enabled, it | |
4957 | * means that the last instruction is an sti. We should not | |
4958 | * leave the flag on in this case. The same goes for mov ss | |
4959 | */ | |
37ccdcbe PB |
4960 | if (int_shadow & mask) |
4961 | mask = 0; | |
6addfc42 | 4962 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 4963 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
4964 | if (!mask) |
4965 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4966 | } | |
95cb2295 GN |
4967 | } |
4968 | ||
ef54bcfe | 4969 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
4970 | { |
4971 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 4972 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
4973 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
4974 | ||
4975 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
4976 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
4977 | ctxt->exception.error_code); | |
54b8486f | 4978 | else |
da9cb575 | 4979 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 4980 | return false; |
54b8486f GN |
4981 | } |
4982 | ||
8ec4722d MG |
4983 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4984 | { | |
adf52235 | 4985 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
4986 | int cs_db, cs_l; |
4987 | ||
8ec4722d MG |
4988 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
4989 | ||
adf52235 TY |
4990 | ctxt->eflags = kvm_get_rflags(vcpu); |
4991 | ctxt->eip = kvm_rip_read(vcpu); | |
4992 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4993 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 4994 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
4995 | cs_db ? X86EMUL_MODE_PROT32 : |
4996 | X86EMUL_MODE_PROT16; | |
4997 | ctxt->guest_mode = is_guest_mode(vcpu); | |
4998 | ||
dd856efa | 4999 | init_decode_cache(ctxt); |
7ae441ea | 5000 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5001 | } |
5002 | ||
71f9833b | 5003 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5004 | { |
9d74191a | 5005 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5006 | int ret; |
5007 | ||
5008 | init_emulate_ctxt(vcpu); | |
5009 | ||
9dac77fa AK |
5010 | ctxt->op_bytes = 2; |
5011 | ctxt->ad_bytes = 2; | |
5012 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5013 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5014 | |
5015 | if (ret != X86EMUL_CONTINUE) | |
5016 | return EMULATE_FAIL; | |
5017 | ||
9dac77fa | 5018 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5019 | kvm_rip_write(vcpu, ctxt->eip); |
5020 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
5021 | |
5022 | if (irq == NMI_VECTOR) | |
7460fb4a | 5023 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
5024 | else |
5025 | vcpu->arch.interrupt.pending = false; | |
5026 | ||
5027 | return EMULATE_DONE; | |
5028 | } | |
5029 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5030 | ||
6d77dbfc GN |
5031 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
5032 | { | |
fc3a9157 JR |
5033 | int r = EMULATE_DONE; |
5034 | ||
6d77dbfc GN |
5035 | ++vcpu->stat.insn_emulation_fail; |
5036 | trace_kvm_emulate_insn_failed(vcpu); | |
a2b9e6c1 | 5037 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5038 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5039 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5040 | vcpu->run->internal.ndata = 0; | |
5041 | r = EMULATE_FAIL; | |
5042 | } | |
6d77dbfc | 5043 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5044 | |
5045 | return r; | |
6d77dbfc GN |
5046 | } |
5047 | ||
93c05d3e | 5048 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5049 | bool write_fault_to_shadow_pgtable, |
5050 | int emulation_type) | |
a6f177ef | 5051 | { |
95b3cf69 | 5052 | gpa_t gpa = cr2; |
8e3d9d06 | 5053 | pfn_t pfn; |
a6f177ef | 5054 | |
991eebf9 GN |
5055 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5056 | return false; | |
5057 | ||
95b3cf69 XG |
5058 | if (!vcpu->arch.mmu.direct_map) { |
5059 | /* | |
5060 | * Write permission should be allowed since only | |
5061 | * write access need to be emulated. | |
5062 | */ | |
5063 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5064 | |
95b3cf69 XG |
5065 | /* |
5066 | * If the mapping is invalid in guest, let cpu retry | |
5067 | * it to generate fault. | |
5068 | */ | |
5069 | if (gpa == UNMAPPED_GVA) | |
5070 | return true; | |
5071 | } | |
a6f177ef | 5072 | |
8e3d9d06 XG |
5073 | /* |
5074 | * Do not retry the unhandleable instruction if it faults on the | |
5075 | * readonly host memory, otherwise it will goto a infinite loop: | |
5076 | * retry instruction -> write #PF -> emulation fail -> retry | |
5077 | * instruction -> ... | |
5078 | */ | |
5079 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5080 | |
5081 | /* | |
5082 | * If the instruction failed on the error pfn, it can not be fixed, | |
5083 | * report the error to userspace. | |
5084 | */ | |
5085 | if (is_error_noslot_pfn(pfn)) | |
5086 | return false; | |
5087 | ||
5088 | kvm_release_pfn_clean(pfn); | |
5089 | ||
5090 | /* The instructions are well-emulated on direct mmu. */ | |
5091 | if (vcpu->arch.mmu.direct_map) { | |
5092 | unsigned int indirect_shadow_pages; | |
5093 | ||
5094 | spin_lock(&vcpu->kvm->mmu_lock); | |
5095 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5096 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5097 | ||
5098 | if (indirect_shadow_pages) | |
5099 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5100 | ||
a6f177ef | 5101 | return true; |
8e3d9d06 | 5102 | } |
a6f177ef | 5103 | |
95b3cf69 XG |
5104 | /* |
5105 | * if emulation was due to access to shadowed page table | |
5106 | * and it failed try to unshadow page and re-enter the | |
5107 | * guest to let CPU execute the instruction. | |
5108 | */ | |
5109 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5110 | |
5111 | /* | |
5112 | * If the access faults on its page table, it can not | |
5113 | * be fixed by unprotecting shadow page and it should | |
5114 | * be reported to userspace. | |
5115 | */ | |
5116 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5117 | } |
5118 | ||
1cb3f3ae XG |
5119 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5120 | unsigned long cr2, int emulation_type) | |
5121 | { | |
5122 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5123 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5124 | ||
5125 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5126 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5127 | ||
5128 | /* | |
5129 | * If the emulation is caused by #PF and it is non-page_table | |
5130 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5131 | * page protected, we can zap the shadow page and retry this | |
5132 | * instruction directly. | |
5133 | * | |
5134 | * Note: if the guest uses a non-page-table modifying instruction | |
5135 | * on the PDE that points to the instruction, then we will unmap | |
5136 | * the instruction and go to an infinite loop. So, we cache the | |
5137 | * last retried eip and the last fault address, if we meet the eip | |
5138 | * and the address again, we can break out of the potential infinite | |
5139 | * loop. | |
5140 | */ | |
5141 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5142 | ||
5143 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5144 | return false; | |
5145 | ||
5146 | if (x86_page_table_writing_insn(ctxt)) | |
5147 | return false; | |
5148 | ||
5149 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5150 | return false; | |
5151 | ||
5152 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5153 | vcpu->arch.last_retry_addr = cr2; | |
5154 | ||
5155 | if (!vcpu->arch.mmu.direct_map) | |
5156 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5157 | ||
22368028 | 5158 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5159 | |
5160 | return true; | |
5161 | } | |
5162 | ||
716d51ab GN |
5163 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5164 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5165 | ||
4a1e10d5 PB |
5166 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5167 | unsigned long *db) | |
5168 | { | |
5169 | u32 dr6 = 0; | |
5170 | int i; | |
5171 | u32 enable, rwlen; | |
5172 | ||
5173 | enable = dr7; | |
5174 | rwlen = dr7 >> 16; | |
5175 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5176 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5177 | dr6 |= (1 << i); | |
5178 | return dr6; | |
5179 | } | |
5180 | ||
6addfc42 | 5181 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) |
663f4c61 PB |
5182 | { |
5183 | struct kvm_run *kvm_run = vcpu->run; | |
5184 | ||
5185 | /* | |
6addfc42 PB |
5186 | * rflags is the old, "raw" value of the flags. The new value has |
5187 | * not been saved yet. | |
663f4c61 PB |
5188 | * |
5189 | * This is correct even for TF set by the guest, because "the | |
5190 | * processor will not generate this exception after the instruction | |
5191 | * that sets the TF flag". | |
5192 | */ | |
663f4c61 PB |
5193 | if (unlikely(rflags & X86_EFLAGS_TF)) { |
5194 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
6f43ed01 NA |
5195 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | |
5196 | DR6_RTM; | |
663f4c61 PB |
5197 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; |
5198 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5199 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5200 | *r = EMULATE_USER_EXIT; | |
5201 | } else { | |
5202 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5203 | /* | |
5204 | * "Certain debug exceptions may clear bit 0-3. The | |
5205 | * remaining contents of the DR6 register are never | |
5206 | * cleared by the processor". | |
5207 | */ | |
5208 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5209 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; |
663f4c61 PB |
5210 | kvm_queue_exception(vcpu, DB_VECTOR); |
5211 | } | |
5212 | } | |
5213 | } | |
5214 | ||
4a1e10d5 PB |
5215 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5216 | { | |
4a1e10d5 PB |
5217 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5218 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5219 | struct kvm_run *kvm_run = vcpu->run; |
5220 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5221 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5222 | vcpu->arch.guest_debug_dr7, |
5223 | vcpu->arch.eff_db); | |
5224 | ||
5225 | if (dr6 != 0) { | |
6f43ed01 | 5226 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5227 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5228 | kvm_run->debug.arch.exception = DB_VECTOR; |
5229 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5230 | *r = EMULATE_USER_EXIT; | |
5231 | return true; | |
5232 | } | |
5233 | } | |
5234 | ||
4161a569 NA |
5235 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5236 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5237 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5238 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5239 | vcpu->arch.dr7, |
5240 | vcpu->arch.db); | |
5241 | ||
5242 | if (dr6 != 0) { | |
5243 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5244 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5245 | kvm_queue_exception(vcpu, DB_VECTOR); |
5246 | *r = EMULATE_DONE; | |
5247 | return true; | |
5248 | } | |
5249 | } | |
5250 | ||
5251 | return false; | |
5252 | } | |
5253 | ||
51d8b661 AP |
5254 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5255 | unsigned long cr2, | |
dc25e89e AP |
5256 | int emulation_type, |
5257 | void *insn, | |
5258 | int insn_len) | |
bbd9b64e | 5259 | { |
95cb2295 | 5260 | int r; |
9d74191a | 5261 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5262 | bool writeback = true; |
93c05d3e | 5263 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5264 | |
93c05d3e XG |
5265 | /* |
5266 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5267 | * never reused. | |
5268 | */ | |
5269 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5270 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5271 | |
571008da | 5272 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5273 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5274 | |
5275 | /* | |
5276 | * We will reenter on the same instruction since | |
5277 | * we do not set complete_userspace_io. This does not | |
5278 | * handle watchpoints yet, those would be handled in | |
5279 | * the emulate_ops. | |
5280 | */ | |
5281 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5282 | return r; | |
5283 | ||
9d74191a TY |
5284 | ctxt->interruptibility = 0; |
5285 | ctxt->have_exception = false; | |
e0ad0b47 | 5286 | ctxt->exception.vector = -1; |
9d74191a | 5287 | ctxt->perm_ok = false; |
bbd9b64e | 5288 | |
b51e974f | 5289 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 5290 | |
9d74191a | 5291 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 5292 | |
e46479f8 | 5293 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 5294 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 5295 | if (r != EMULATION_OK) { |
4005996e AK |
5296 | if (emulation_type & EMULTYPE_TRAP_UD) |
5297 | return EMULATE_FAIL; | |
991eebf9 GN |
5298 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5299 | emulation_type)) | |
bbd9b64e | 5300 | return EMULATE_DONE; |
6d77dbfc GN |
5301 | if (emulation_type & EMULTYPE_SKIP) |
5302 | return EMULATE_FAIL; | |
5303 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
5304 | } |
5305 | } | |
5306 | ||
ba8afb6b | 5307 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 5308 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
5309 | if (ctxt->eflags & X86_EFLAGS_RF) |
5310 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
5311 | return EMULATE_DONE; |
5312 | } | |
5313 | ||
1cb3f3ae XG |
5314 | if (retry_instruction(ctxt, cr2, emulation_type)) |
5315 | return EMULATE_DONE; | |
5316 | ||
7ae441ea | 5317 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 5318 | changes registers values during IO operation */ |
7ae441ea GN |
5319 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
5320 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 5321 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 5322 | } |
4d2179e1 | 5323 | |
5cd21917 | 5324 | restart: |
9d74191a | 5325 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 5326 | |
775fde86 JR |
5327 | if (r == EMULATION_INTERCEPTED) |
5328 | return EMULATE_DONE; | |
5329 | ||
d2ddd1c4 | 5330 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
5331 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5332 | emulation_type)) | |
c3cd7ffa GN |
5333 | return EMULATE_DONE; |
5334 | ||
6d77dbfc | 5335 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
5336 | } |
5337 | ||
9d74191a | 5338 | if (ctxt->have_exception) { |
d2ddd1c4 | 5339 | r = EMULATE_DONE; |
ef54bcfe PB |
5340 | if (inject_emulated_exception(vcpu)) |
5341 | return r; | |
d2ddd1c4 | 5342 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
5343 | if (!vcpu->arch.pio.in) { |
5344 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 5345 | vcpu->arch.pio.count = 0; |
0912c977 | 5346 | } else { |
7ae441ea | 5347 | writeback = false; |
716d51ab GN |
5348 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
5349 | } | |
ac0a48c3 | 5350 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
5351 | } else if (vcpu->mmio_needed) { |
5352 | if (!vcpu->mmio_is_write) | |
5353 | writeback = false; | |
ac0a48c3 | 5354 | r = EMULATE_USER_EXIT; |
716d51ab | 5355 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5356 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5357 | goto restart; |
d2ddd1c4 GN |
5358 | else |
5359 | r = EMULATE_DONE; | |
f850e2e6 | 5360 | |
7ae441ea | 5361 | if (writeback) { |
6addfc42 | 5362 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 5363 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 5364 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
9d74191a | 5365 | kvm_rip_write(vcpu, ctxt->eip); |
663f4c61 | 5366 | if (r == EMULATE_DONE) |
6addfc42 | 5367 | kvm_vcpu_check_singlestep(vcpu, rflags, &r); |
38827dbd NA |
5368 | if (!ctxt->have_exception || |
5369 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
5370 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
5371 | |
5372 | /* | |
5373 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
5374 | * do nothing, and it will be requested again as soon as | |
5375 | * the shadow expires. But we still need to check here, | |
5376 | * because POPF has no interrupt shadow. | |
5377 | */ | |
5378 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
5379 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
5380 | } else |
5381 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5382 | |
5383 | return r; | |
de7d789a | 5384 | } |
51d8b661 | 5385 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5386 | |
cf8f70bf | 5387 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5388 | { |
cf8f70bf | 5389 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5390 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5391 | size, port, &val, 1); | |
cf8f70bf | 5392 | /* do not return to emulator after return from userspace */ |
7972995b | 5393 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5394 | return ret; |
5395 | } | |
cf8f70bf | 5396 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5397 | |
8cfdc000 ZA |
5398 | static void tsc_bad(void *info) |
5399 | { | |
0a3aee0d | 5400 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5401 | } |
5402 | ||
5403 | static void tsc_khz_changed(void *data) | |
c8076604 | 5404 | { |
8cfdc000 ZA |
5405 | struct cpufreq_freqs *freq = data; |
5406 | unsigned long khz = 0; | |
5407 | ||
5408 | if (data) | |
5409 | khz = freq->new; | |
5410 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5411 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5412 | if (!khz) | |
5413 | khz = tsc_khz; | |
0a3aee0d | 5414 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5415 | } |
5416 | ||
c8076604 GH |
5417 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5418 | void *data) | |
5419 | { | |
5420 | struct cpufreq_freqs *freq = data; | |
5421 | struct kvm *kvm; | |
5422 | struct kvm_vcpu *vcpu; | |
5423 | int i, send_ipi = 0; | |
5424 | ||
8cfdc000 ZA |
5425 | /* |
5426 | * We allow guests to temporarily run on slowing clocks, | |
5427 | * provided we notify them after, or to run on accelerating | |
5428 | * clocks, provided we notify them before. Thus time never | |
5429 | * goes backwards. | |
5430 | * | |
5431 | * However, we have a problem. We can't atomically update | |
5432 | * the frequency of a given CPU from this function; it is | |
5433 | * merely a notifier, which can be called from any CPU. | |
5434 | * Changing the TSC frequency at arbitrary points in time | |
5435 | * requires a recomputation of local variables related to | |
5436 | * the TSC for each VCPU. We must flag these local variables | |
5437 | * to be updated and be sure the update takes place with the | |
5438 | * new frequency before any guests proceed. | |
5439 | * | |
5440 | * Unfortunately, the combination of hotplug CPU and frequency | |
5441 | * change creates an intractable locking scenario; the order | |
5442 | * of when these callouts happen is undefined with respect to | |
5443 | * CPU hotplug, and they can race with each other. As such, | |
5444 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5445 | * undefined; you can actually have a CPU frequency change take | |
5446 | * place in between the computation of X and the setting of the | |
5447 | * variable. To protect against this problem, all updates of | |
5448 | * the per_cpu tsc_khz variable are done in an interrupt | |
5449 | * protected IPI, and all callers wishing to update the value | |
5450 | * must wait for a synchronous IPI to complete (which is trivial | |
5451 | * if the caller is on the CPU already). This establishes the | |
5452 | * necessary total order on variable updates. | |
5453 | * | |
5454 | * Note that because a guest time update may take place | |
5455 | * anytime after the setting of the VCPU's request bit, the | |
5456 | * correct TSC value must be set before the request. However, | |
5457 | * to ensure the update actually makes it to any guest which | |
5458 | * starts running in hardware virtualization between the set | |
5459 | * and the acquisition of the spinlock, we must also ping the | |
5460 | * CPU after setting the request bit. | |
5461 | * | |
5462 | */ | |
5463 | ||
c8076604 GH |
5464 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5465 | return 0; | |
5466 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5467 | return 0; | |
8cfdc000 ZA |
5468 | |
5469 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5470 | |
2f303b74 | 5471 | spin_lock(&kvm_lock); |
c8076604 | 5472 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5473 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5474 | if (vcpu->cpu != freq->cpu) |
5475 | continue; | |
c285545f | 5476 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5477 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5478 | send_ipi = 1; |
c8076604 GH |
5479 | } |
5480 | } | |
2f303b74 | 5481 | spin_unlock(&kvm_lock); |
c8076604 GH |
5482 | |
5483 | if (freq->old < freq->new && send_ipi) { | |
5484 | /* | |
5485 | * We upscale the frequency. Must make the guest | |
5486 | * doesn't see old kvmclock values while running with | |
5487 | * the new frequency, otherwise we risk the guest sees | |
5488 | * time go backwards. | |
5489 | * | |
5490 | * In case we update the frequency for another cpu | |
5491 | * (which might be in guest context) send an interrupt | |
5492 | * to kick the cpu out of guest context. Next time | |
5493 | * guest context is entered kvmclock will be updated, | |
5494 | * so the guest will not see stale values. | |
5495 | */ | |
8cfdc000 | 5496 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5497 | } |
5498 | return 0; | |
5499 | } | |
5500 | ||
5501 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5502 | .notifier_call = kvmclock_cpufreq_notifier |
5503 | }; | |
5504 | ||
5505 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5506 | unsigned long action, void *hcpu) | |
5507 | { | |
5508 | unsigned int cpu = (unsigned long)hcpu; | |
5509 | ||
5510 | switch (action) { | |
5511 | case CPU_ONLINE: | |
5512 | case CPU_DOWN_FAILED: | |
5513 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5514 | break; | |
5515 | case CPU_DOWN_PREPARE: | |
5516 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5517 | break; | |
5518 | } | |
5519 | return NOTIFY_OK; | |
5520 | } | |
5521 | ||
5522 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5523 | .notifier_call = kvmclock_cpu_notifier, | |
5524 | .priority = -INT_MAX | |
c8076604 GH |
5525 | }; |
5526 | ||
b820cc0c ZA |
5527 | static void kvm_timer_init(void) |
5528 | { | |
5529 | int cpu; | |
5530 | ||
c285545f | 5531 | max_tsc_khz = tsc_khz; |
460dd42e SB |
5532 | |
5533 | cpu_notifier_register_begin(); | |
b820cc0c | 5534 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5535 | #ifdef CONFIG_CPU_FREQ |
5536 | struct cpufreq_policy policy; | |
5537 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5538 | cpu = get_cpu(); |
5539 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5540 | if (policy.cpuinfo.max_freq) |
5541 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5542 | put_cpu(); |
c285545f | 5543 | #endif |
b820cc0c ZA |
5544 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5545 | CPUFREQ_TRANSITION_NOTIFIER); | |
5546 | } | |
c285545f | 5547 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5548 | for_each_online_cpu(cpu) |
5549 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
460dd42e SB |
5550 | |
5551 | __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5552 | cpu_notifier_register_done(); | |
5553 | ||
b820cc0c ZA |
5554 | } |
5555 | ||
ff9d07a0 ZY |
5556 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5557 | ||
f5132b01 | 5558 | int kvm_is_in_guest(void) |
ff9d07a0 | 5559 | { |
086c9855 | 5560 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5561 | } |
5562 | ||
5563 | static int kvm_is_user_mode(void) | |
5564 | { | |
5565 | int user_mode = 3; | |
dcf46b94 | 5566 | |
086c9855 AS |
5567 | if (__this_cpu_read(current_vcpu)) |
5568 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5569 | |
ff9d07a0 ZY |
5570 | return user_mode != 0; |
5571 | } | |
5572 | ||
5573 | static unsigned long kvm_get_guest_ip(void) | |
5574 | { | |
5575 | unsigned long ip = 0; | |
dcf46b94 | 5576 | |
086c9855 AS |
5577 | if (__this_cpu_read(current_vcpu)) |
5578 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5579 | |
ff9d07a0 ZY |
5580 | return ip; |
5581 | } | |
5582 | ||
5583 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5584 | .is_in_guest = kvm_is_in_guest, | |
5585 | .is_user_mode = kvm_is_user_mode, | |
5586 | .get_guest_ip = kvm_get_guest_ip, | |
5587 | }; | |
5588 | ||
5589 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5590 | { | |
086c9855 | 5591 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5592 | } |
5593 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5594 | ||
5595 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5596 | { | |
086c9855 | 5597 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5598 | } |
5599 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5600 | ||
ce88decf XG |
5601 | static void kvm_set_mmio_spte_mask(void) |
5602 | { | |
5603 | u64 mask; | |
5604 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5605 | ||
5606 | /* | |
5607 | * Set the reserved bits and the present bit of an paging-structure | |
5608 | * entry to generate page fault with PFER.RSV = 1. | |
5609 | */ | |
885032b9 | 5610 | /* Mask the reserved physical address bits. */ |
d1431483 | 5611 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 XG |
5612 | |
5613 | /* Bit 62 is always reserved for 32bit host. */ | |
5614 | mask |= 0x3ull << 62; | |
5615 | ||
5616 | /* Set the present bit. */ | |
ce88decf XG |
5617 | mask |= 1ull; |
5618 | ||
5619 | #ifdef CONFIG_X86_64 | |
5620 | /* | |
5621 | * If reserved bit is not supported, clear the present bit to disable | |
5622 | * mmio page fault. | |
5623 | */ | |
5624 | if (maxphyaddr == 52) | |
5625 | mask &= ~1ull; | |
5626 | #endif | |
5627 | ||
5628 | kvm_mmu_set_mmio_spte_mask(mask); | |
5629 | } | |
5630 | ||
16e8d74d MT |
5631 | #ifdef CONFIG_X86_64 |
5632 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5633 | { | |
d828199e MT |
5634 | struct kvm *kvm; |
5635 | ||
5636 | struct kvm_vcpu *vcpu; | |
5637 | int i; | |
5638 | ||
2f303b74 | 5639 | spin_lock(&kvm_lock); |
d828199e MT |
5640 | list_for_each_entry(kvm, &vm_list, vm_list) |
5641 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 5642 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 5643 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 5644 | spin_unlock(&kvm_lock); |
16e8d74d MT |
5645 | } |
5646 | ||
5647 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5648 | ||
5649 | /* | |
5650 | * Notification about pvclock gtod data update. | |
5651 | */ | |
5652 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5653 | void *priv) | |
5654 | { | |
5655 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5656 | struct timekeeper *tk = priv; | |
5657 | ||
5658 | update_pvclock_gtod(tk); | |
5659 | ||
5660 | /* disable master clock if host does not trust, or does not | |
5661 | * use, TSC clocksource | |
5662 | */ | |
5663 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5664 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5665 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5666 | ||
5667 | return 0; | |
5668 | } | |
5669 | ||
5670 | static struct notifier_block pvclock_gtod_notifier = { | |
5671 | .notifier_call = pvclock_gtod_notify, | |
5672 | }; | |
5673 | #endif | |
5674 | ||
f8c16bba | 5675 | int kvm_arch_init(void *opaque) |
043405e1 | 5676 | { |
b820cc0c | 5677 | int r; |
6b61edf7 | 5678 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 5679 | |
f8c16bba ZX |
5680 | if (kvm_x86_ops) { |
5681 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
5682 | r = -EEXIST; |
5683 | goto out; | |
f8c16bba ZX |
5684 | } |
5685 | ||
5686 | if (!ops->cpu_has_kvm_support()) { | |
5687 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
5688 | r = -EOPNOTSUPP; |
5689 | goto out; | |
f8c16bba ZX |
5690 | } |
5691 | if (ops->disabled_by_bios()) { | |
5692 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
5693 | r = -EOPNOTSUPP; |
5694 | goto out; | |
f8c16bba ZX |
5695 | } |
5696 | ||
013f6a5d MT |
5697 | r = -ENOMEM; |
5698 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5699 | if (!shared_msrs) { | |
5700 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5701 | goto out; | |
5702 | } | |
5703 | ||
97db56ce AK |
5704 | r = kvm_mmu_module_init(); |
5705 | if (r) | |
013f6a5d | 5706 | goto out_free_percpu; |
97db56ce | 5707 | |
ce88decf | 5708 | kvm_set_mmio_spte_mask(); |
97db56ce | 5709 | |
f8c16bba | 5710 | kvm_x86_ops = ops; |
920c8377 PB |
5711 | kvm_init_msr_list(); |
5712 | ||
7b52345e | 5713 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 5714 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 5715 | |
b820cc0c | 5716 | kvm_timer_init(); |
c8076604 | 5717 | |
ff9d07a0 ZY |
5718 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
5719 | ||
2acf923e DC |
5720 | if (cpu_has_xsave) |
5721 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
5722 | ||
c5cc421b | 5723 | kvm_lapic_init(); |
16e8d74d MT |
5724 | #ifdef CONFIG_X86_64 |
5725 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5726 | #endif | |
5727 | ||
f8c16bba | 5728 | return 0; |
56c6d28a | 5729 | |
013f6a5d MT |
5730 | out_free_percpu: |
5731 | free_percpu(shared_msrs); | |
56c6d28a | 5732 | out: |
56c6d28a | 5733 | return r; |
043405e1 | 5734 | } |
8776e519 | 5735 | |
f8c16bba ZX |
5736 | void kvm_arch_exit(void) |
5737 | { | |
ff9d07a0 ZY |
5738 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
5739 | ||
888d256e JK |
5740 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
5741 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5742 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 5743 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
5744 | #ifdef CONFIG_X86_64 |
5745 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5746 | #endif | |
f8c16bba | 5747 | kvm_x86_ops = NULL; |
56c6d28a | 5748 | kvm_mmu_module_exit(); |
013f6a5d | 5749 | free_percpu(shared_msrs); |
56c6d28a | 5750 | } |
f8c16bba | 5751 | |
8776e519 HB |
5752 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
5753 | { | |
5754 | ++vcpu->stat.halt_exits; | |
5755 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 5756 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
5757 | return 1; |
5758 | } else { | |
5759 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5760 | return 0; | |
5761 | } | |
5762 | } | |
5763 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
5764 | ||
55cd8e5a GN |
5765 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
5766 | { | |
5767 | u64 param, ingpa, outgpa, ret; | |
5768 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
5769 | bool fast, longmode; | |
55cd8e5a GN |
5770 | |
5771 | /* | |
5772 | * hypercall generates UD from non zero cpl and real mode | |
5773 | * per HYPER-V spec | |
5774 | */ | |
3eeb3288 | 5775 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
5776 | kvm_queue_exception(vcpu, UD_VECTOR); |
5777 | return 0; | |
5778 | } | |
5779 | ||
a449c7aa | 5780 | longmode = is_64_bit_mode(vcpu); |
55cd8e5a GN |
5781 | |
5782 | if (!longmode) { | |
ccd46936 GN |
5783 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
5784 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
5785 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
5786 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
5787 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
5788 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
5789 | } |
5790 | #ifdef CONFIG_X86_64 | |
5791 | else { | |
5792 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5793 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5794 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
5795 | } | |
5796 | #endif | |
5797 | ||
5798 | code = param & 0xffff; | |
5799 | fast = (param >> 16) & 0x1; | |
5800 | rep_cnt = (param >> 32) & 0xfff; | |
5801 | rep_idx = (param >> 48) & 0xfff; | |
5802 | ||
5803 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
5804 | ||
c25bc163 GN |
5805 | switch (code) { |
5806 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
5807 | kvm_vcpu_on_spin(vcpu); | |
5808 | break; | |
5809 | default: | |
5810 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
5811 | break; | |
5812 | } | |
55cd8e5a GN |
5813 | |
5814 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
5815 | if (longmode) { | |
5816 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5817 | } else { | |
5818 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
5819 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
5820 | } | |
5821 | ||
5822 | return 1; | |
5823 | } | |
5824 | ||
6aef266c SV |
5825 | /* |
5826 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
5827 | * | |
5828 | * @apicid - apicid of vcpu to be kicked. | |
5829 | */ | |
5830 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
5831 | { | |
24d2166b | 5832 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 5833 | |
24d2166b R |
5834 | lapic_irq.shorthand = 0; |
5835 | lapic_irq.dest_mode = 0; | |
5836 | lapic_irq.dest_id = apicid; | |
6aef266c | 5837 | |
24d2166b R |
5838 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
5839 | kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL); | |
6aef266c SV |
5840 | } |
5841 | ||
8776e519 HB |
5842 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5843 | { | |
5844 | unsigned long nr, a0, a1, a2, a3, ret; | |
a449c7aa | 5845 | int op_64_bit, r = 1; |
8776e519 | 5846 | |
55cd8e5a GN |
5847 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5848 | return kvm_hv_hypercall(vcpu); | |
5849 | ||
5fdbf976 MT |
5850 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5851 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5852 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5853 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5854 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5855 | |
229456fc | 5856 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5857 | |
a449c7aa NA |
5858 | op_64_bit = is_64_bit_mode(vcpu); |
5859 | if (!op_64_bit) { | |
8776e519 HB |
5860 | nr &= 0xFFFFFFFF; |
5861 | a0 &= 0xFFFFFFFF; | |
5862 | a1 &= 0xFFFFFFFF; | |
5863 | a2 &= 0xFFFFFFFF; | |
5864 | a3 &= 0xFFFFFFFF; | |
5865 | } | |
5866 | ||
07708c4a JK |
5867 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5868 | ret = -KVM_EPERM; | |
5869 | goto out; | |
5870 | } | |
5871 | ||
8776e519 | 5872 | switch (nr) { |
b93463aa AK |
5873 | case KVM_HC_VAPIC_POLL_IRQ: |
5874 | ret = 0; | |
5875 | break; | |
6aef266c SV |
5876 | case KVM_HC_KICK_CPU: |
5877 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
5878 | ret = 0; | |
5879 | break; | |
8776e519 HB |
5880 | default: |
5881 | ret = -KVM_ENOSYS; | |
5882 | break; | |
5883 | } | |
07708c4a | 5884 | out: |
a449c7aa NA |
5885 | if (!op_64_bit) |
5886 | ret = (u32)ret; | |
5fdbf976 | 5887 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 5888 | ++vcpu->stat.hypercalls; |
2f333bcb | 5889 | return r; |
8776e519 HB |
5890 | } |
5891 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
5892 | ||
b6785def | 5893 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 5894 | { |
d6aa1000 | 5895 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 5896 | char instruction[3]; |
5fdbf976 | 5897 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 5898 | |
8776e519 | 5899 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 5900 | |
9d74191a | 5901 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
5902 | } |
5903 | ||
b6c7a5dc HB |
5904 | /* |
5905 | * Check if userspace requested an interrupt window, and that the | |
5906 | * interrupt window is open. | |
5907 | * | |
5908 | * No need to exit to userspace if we already have an interrupt queued. | |
5909 | */ | |
851ba692 | 5910 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5911 | { |
8061823a | 5912 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 5913 | vcpu->run->request_interrupt_window && |
5df56646 | 5914 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
5915 | } |
5916 | ||
851ba692 | 5917 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5918 | { |
851ba692 AK |
5919 | struct kvm_run *kvm_run = vcpu->run; |
5920 | ||
91586a3b | 5921 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 5922 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5923 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 5924 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 5925 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 5926 | else |
b6c7a5dc | 5927 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
5928 | kvm_arch_interrupt_allowed(vcpu) && |
5929 | !kvm_cpu_has_interrupt(vcpu) && | |
5930 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
5931 | } |
5932 | ||
95ba8273 GN |
5933 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5934 | { | |
5935 | int max_irr, tpr; | |
5936 | ||
5937 | if (!kvm_x86_ops->update_cr8_intercept) | |
5938 | return; | |
5939 | ||
88c808fd AK |
5940 | if (!vcpu->arch.apic) |
5941 | return; | |
5942 | ||
8db3baa2 GN |
5943 | if (!vcpu->arch.apic->vapic_addr) |
5944 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5945 | else | |
5946 | max_irr = -1; | |
95ba8273 GN |
5947 | |
5948 | if (max_irr != -1) | |
5949 | max_irr >>= 4; | |
5950 | ||
5951 | tpr = kvm_lapic_get_cr8(vcpu); | |
5952 | ||
5953 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5954 | } | |
5955 | ||
b6b8a145 | 5956 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 5957 | { |
b6b8a145 JK |
5958 | int r; |
5959 | ||
95ba8273 | 5960 | /* try to reinject previous events if any */ |
b59bb7bd | 5961 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
5962 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
5963 | vcpu->arch.exception.has_error_code, | |
5964 | vcpu->arch.exception.error_code); | |
d6e8c854 NA |
5965 | |
5966 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) | |
5967 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
5968 | X86_EFLAGS_RF); | |
5969 | ||
6bdf0662 NA |
5970 | if (vcpu->arch.exception.nr == DB_VECTOR && |
5971 | (vcpu->arch.dr7 & DR7_GD)) { | |
5972 | vcpu->arch.dr7 &= ~DR7_GD; | |
5973 | kvm_update_dr7(vcpu); | |
5974 | } | |
5975 | ||
b59bb7bd GN |
5976 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
5977 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
5978 | vcpu->arch.exception.error_code, |
5979 | vcpu->arch.exception.reinject); | |
b6b8a145 | 5980 | return 0; |
b59bb7bd GN |
5981 | } |
5982 | ||
95ba8273 GN |
5983 | if (vcpu->arch.nmi_injected) { |
5984 | kvm_x86_ops->set_nmi(vcpu); | |
b6b8a145 | 5985 | return 0; |
95ba8273 GN |
5986 | } |
5987 | ||
5988 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 5989 | kvm_x86_ops->set_irq(vcpu); |
b6b8a145 JK |
5990 | return 0; |
5991 | } | |
5992 | ||
5993 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
5994 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
5995 | if (r != 0) | |
5996 | return r; | |
95ba8273 GN |
5997 | } |
5998 | ||
5999 | /* try to inject new event if pending */ | |
6000 | if (vcpu->arch.nmi_pending) { | |
6001 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 6002 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
6003 | vcpu->arch.nmi_injected = true; |
6004 | kvm_x86_ops->set_nmi(vcpu); | |
6005 | } | |
c7c9c56c | 6006 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6007 | /* |
6008 | * Because interrupts can be injected asynchronously, we are | |
6009 | * calling check_nested_events again here to avoid a race condition. | |
6010 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6011 | * proposal and current concerns. Perhaps we should be setting | |
6012 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6013 | */ | |
6014 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6015 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6016 | if (r != 0) | |
6017 | return r; | |
6018 | } | |
95ba8273 | 6019 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6020 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6021 | false); | |
6022 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6023 | } |
6024 | } | |
b6b8a145 | 6025 | return 0; |
95ba8273 GN |
6026 | } |
6027 | ||
7460fb4a AK |
6028 | static void process_nmi(struct kvm_vcpu *vcpu) |
6029 | { | |
6030 | unsigned limit = 2; | |
6031 | ||
6032 | /* | |
6033 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6034 | * If an NMI is already in progress, limit further NMIs to just one. | |
6035 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6036 | */ | |
6037 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6038 | limit = 1; | |
6039 | ||
6040 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6041 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6042 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6043 | } | |
6044 | ||
3d81bc7e | 6045 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c YZ |
6046 | { |
6047 | u64 eoi_exit_bitmap[4]; | |
cf9e65b7 | 6048 | u32 tmr[8]; |
c7c9c56c | 6049 | |
3d81bc7e YZ |
6050 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
6051 | return; | |
c7c9c56c YZ |
6052 | |
6053 | memset(eoi_exit_bitmap, 0, 32); | |
cf9e65b7 | 6054 | memset(tmr, 0, 32); |
c7c9c56c | 6055 | |
cf9e65b7 | 6056 | kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); |
c7c9c56c | 6057 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
cf9e65b7 | 6058 | kvm_apic_update_tmr(vcpu, tmr); |
c7c9c56c YZ |
6059 | } |
6060 | ||
a70656b6 RK |
6061 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) |
6062 | { | |
6063 | ++vcpu->stat.tlb_flush; | |
6064 | kvm_x86_ops->tlb_flush(vcpu); | |
6065 | } | |
6066 | ||
4256f43f TC |
6067 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
6068 | { | |
c24ae0dc TC |
6069 | struct page *page = NULL; |
6070 | ||
f439ed27 PB |
6071 | if (!irqchip_in_kernel(vcpu->kvm)) |
6072 | return; | |
6073 | ||
4256f43f TC |
6074 | if (!kvm_x86_ops->set_apic_access_page_addr) |
6075 | return; | |
6076 | ||
c24ae0dc TC |
6077 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
6078 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); | |
6079 | ||
6080 | /* | |
6081 | * Do not pin apic access page in memory, the MMU notifier | |
6082 | * will call us again if it is migrated or swapped out. | |
6083 | */ | |
6084 | put_page(page); | |
4256f43f TC |
6085 | } |
6086 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
6087 | ||
fe71557a TC |
6088 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
6089 | unsigned long address) | |
6090 | { | |
c24ae0dc TC |
6091 | /* |
6092 | * The physical address of apic access page is stored in the VMCS. | |
6093 | * Update it when it becomes invalid. | |
6094 | */ | |
6095 | if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) | |
6096 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
fe71557a TC |
6097 | } |
6098 | ||
9357d939 TY |
6099 | /* |
6100 | * Returns 1 to let __vcpu_run() continue the guest execution loop without | |
6101 | * exiting to the userspace. Otherwise, the value will be returned to the | |
6102 | * userspace. | |
6103 | */ | |
851ba692 | 6104 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
6105 | { |
6106 | int r; | |
6a8b1d13 | 6107 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 6108 | vcpu->run->request_interrupt_window; |
730dca42 | 6109 | bool req_immediate_exit = false; |
b6c7a5dc | 6110 | |
3e007509 | 6111 | if (vcpu->requests) { |
a8eeb04a | 6112 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 6113 | kvm_mmu_unload(vcpu); |
a8eeb04a | 6114 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 6115 | __kvm_migrate_timers(vcpu); |
d828199e MT |
6116 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6117 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
6118 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
6119 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
6120 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
6121 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
6122 | if (unlikely(r)) |
6123 | goto out; | |
6124 | } | |
a8eeb04a | 6125 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 6126 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 6127 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
a70656b6 | 6128 | kvm_vcpu_flush_tlb(vcpu); |
a8eeb04a | 6129 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 6130 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
6131 | r = 0; |
6132 | goto out; | |
6133 | } | |
a8eeb04a | 6134 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 6135 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
6136 | r = 0; |
6137 | goto out; | |
6138 | } | |
a8eeb04a | 6139 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
6140 | vcpu->fpu_active = 0; |
6141 | kvm_x86_ops->fpu_deactivate(vcpu); | |
6142 | } | |
af585b92 GN |
6143 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
6144 | /* Page is swapped out. Do synthetic halt */ | |
6145 | vcpu->arch.apf.halted = true; | |
6146 | r = 1; | |
6147 | goto out; | |
6148 | } | |
c9aaa895 GC |
6149 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
6150 | record_steal_time(vcpu); | |
7460fb4a AK |
6151 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
6152 | process_nmi(vcpu); | |
f5132b01 GN |
6153 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
6154 | kvm_handle_pmu_event(vcpu); | |
6155 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
6156 | kvm_deliver_pmi(vcpu); | |
3d81bc7e YZ |
6157 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
6158 | vcpu_scan_ioapic(vcpu); | |
4256f43f TC |
6159 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
6160 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2f52d58c | 6161 | } |
b93463aa | 6162 | |
b463a6f7 | 6163 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
6164 | kvm_apic_accept_events(vcpu); |
6165 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
6166 | r = 1; | |
6167 | goto out; | |
6168 | } | |
6169 | ||
b6b8a145 JK |
6170 | if (inject_pending_event(vcpu, req_int_win) != 0) |
6171 | req_immediate_exit = true; | |
b463a6f7 | 6172 | /* enable NMI/IRQ window open exits if needed */ |
b6b8a145 | 6173 | else if (vcpu->arch.nmi_pending) |
c9a7953f | 6174 | kvm_x86_ops->enable_nmi_window(vcpu); |
c7c9c56c | 6175 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) |
c9a7953f | 6176 | kvm_x86_ops->enable_irq_window(vcpu); |
b463a6f7 AK |
6177 | |
6178 | if (kvm_lapic_enabled(vcpu)) { | |
c7c9c56c YZ |
6179 | /* |
6180 | * Update architecture specific hints for APIC | |
6181 | * virtual interrupt delivery. | |
6182 | */ | |
6183 | if (kvm_x86_ops->hwapic_irr_update) | |
6184 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
6185 | kvm_lapic_find_highest_irr(vcpu)); | |
b463a6f7 AK |
6186 | update_cr8_intercept(vcpu); |
6187 | kvm_lapic_sync_to_vapic(vcpu); | |
6188 | } | |
6189 | } | |
6190 | ||
d8368af8 AK |
6191 | r = kvm_mmu_reload(vcpu); |
6192 | if (unlikely(r)) { | |
d905c069 | 6193 | goto cancel_injection; |
d8368af8 AK |
6194 | } |
6195 | ||
b6c7a5dc HB |
6196 | preempt_disable(); |
6197 | ||
6198 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
6199 | if (vcpu->fpu_active) |
6200 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 6201 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 6202 | |
6b7e2d09 XG |
6203 | vcpu->mode = IN_GUEST_MODE; |
6204 | ||
01b71917 MT |
6205 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6206 | ||
6b7e2d09 XG |
6207 | /* We should set ->mode before check ->requests, |
6208 | * see the comment in make_all_cpus_request. | |
6209 | */ | |
01b71917 | 6210 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 6211 | |
d94e1dc9 | 6212 | local_irq_disable(); |
32f88400 | 6213 | |
6b7e2d09 | 6214 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 6215 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 6216 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6217 | smp_wmb(); |
6c142801 AK |
6218 | local_irq_enable(); |
6219 | preempt_enable(); | |
01b71917 | 6220 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 6221 | r = 1; |
d905c069 | 6222 | goto cancel_injection; |
6c142801 AK |
6223 | } |
6224 | ||
d6185f20 NHE |
6225 | if (req_immediate_exit) |
6226 | smp_send_reschedule(vcpu->cpu); | |
6227 | ||
b6c7a5dc HB |
6228 | kvm_guest_enter(); |
6229 | ||
42dbaa5a | 6230 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
6231 | set_debugreg(0, 7); |
6232 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
6233 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
6234 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
6235 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 6236 | set_debugreg(vcpu->arch.dr6, 6); |
42dbaa5a | 6237 | } |
b6c7a5dc | 6238 | |
229456fc | 6239 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 6240 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 6241 | |
c77fb5fe PB |
6242 | /* |
6243 | * Do this here before restoring debug registers on the host. And | |
6244 | * since we do this before handling the vmexit, a DR access vmexit | |
6245 | * can (a) read the correct value of the debug registers, (b) set | |
6246 | * KVM_DEBUGREG_WONT_EXIT again. | |
6247 | */ | |
6248 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
6249 | int i; | |
6250 | ||
6251 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); | |
6252 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
6253 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6254 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
6255 | } | |
6256 | ||
24f1e32c FW |
6257 | /* |
6258 | * If the guest has used debug registers, at least dr7 | |
6259 | * will be disabled while returning to the host. | |
6260 | * If we don't have active breakpoints in the host, we don't | |
6261 | * care about the messed up debug address registers. But if | |
6262 | * we have some of them active, restore the old state. | |
6263 | */ | |
59d8eb53 | 6264 | if (hw_breakpoint_active()) |
24f1e32c | 6265 | hw_breakpoint_restore(); |
42dbaa5a | 6266 | |
886b470c MT |
6267 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, |
6268 | native_read_tsc()); | |
1d5f066e | 6269 | |
6b7e2d09 | 6270 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6271 | smp_wmb(); |
a547c6db YZ |
6272 | |
6273 | /* Interrupt is enabled by handle_external_intr() */ | |
6274 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
6275 | |
6276 | ++vcpu->stat.exits; | |
6277 | ||
6278 | /* | |
6279 | * We must have an instruction between local_irq_enable() and | |
6280 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6281 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6282 | * But we need to prevent reordering, hence this barrier(): | |
6283 | */ | |
6284 | barrier(); | |
6285 | ||
6286 | kvm_guest_exit(); | |
6287 | ||
6288 | preempt_enable(); | |
6289 | ||
f656ce01 | 6290 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 6291 | |
b6c7a5dc HB |
6292 | /* |
6293 | * Profile KVM exit RIPs: | |
6294 | */ | |
6295 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
6296 | unsigned long rip = kvm_rip_read(vcpu); |
6297 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
6298 | } |
6299 | ||
cc578287 ZA |
6300 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
6301 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 6302 | |
5cfb1d5a MT |
6303 | if (vcpu->arch.apic_attention) |
6304 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 6305 | |
851ba692 | 6306 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
6307 | return r; |
6308 | ||
6309 | cancel_injection: | |
6310 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
6311 | if (unlikely(vcpu->arch.apic_attention)) |
6312 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
6313 | out: |
6314 | return r; | |
6315 | } | |
b6c7a5dc | 6316 | |
09cec754 | 6317 | |
851ba692 | 6318 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
6319 | { |
6320 | int r; | |
f656ce01 | 6321 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 6322 | |
f656ce01 | 6323 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
6324 | |
6325 | r = 1; | |
6326 | while (r > 0) { | |
af585b92 GN |
6327 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6328 | !vcpu->arch.apf.halted) | |
851ba692 | 6329 | r = vcpu_enter_guest(vcpu); |
d7690175 | 6330 | else { |
f656ce01 | 6331 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 6332 | kvm_vcpu_block(vcpu); |
f656ce01 | 6333 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
66450a21 JK |
6334 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { |
6335 | kvm_apic_accept_events(vcpu); | |
09cec754 GN |
6336 | switch(vcpu->arch.mp_state) { |
6337 | case KVM_MP_STATE_HALTED: | |
6aef266c | 6338 | vcpu->arch.pv.pv_unhalted = false; |
d7690175 | 6339 | vcpu->arch.mp_state = |
09cec754 GN |
6340 | KVM_MP_STATE_RUNNABLE; |
6341 | case KVM_MP_STATE_RUNNABLE: | |
af585b92 | 6342 | vcpu->arch.apf.halted = false; |
09cec754 | 6343 | break; |
66450a21 JK |
6344 | case KVM_MP_STATE_INIT_RECEIVED: |
6345 | break; | |
09cec754 GN |
6346 | default: |
6347 | r = -EINTR; | |
6348 | break; | |
6349 | } | |
6350 | } | |
d7690175 MT |
6351 | } |
6352 | ||
09cec754 GN |
6353 | if (r <= 0) |
6354 | break; | |
6355 | ||
6356 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6357 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6358 | kvm_inject_pending_timer_irqs(vcpu); | |
6359 | ||
851ba692 | 6360 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 6361 | r = -EINTR; |
851ba692 | 6362 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
6363 | ++vcpu->stat.request_irq_exits; |
6364 | } | |
af585b92 GN |
6365 | |
6366 | kvm_check_async_pf_completion(vcpu); | |
6367 | ||
09cec754 GN |
6368 | if (signal_pending(current)) { |
6369 | r = -EINTR; | |
851ba692 | 6370 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
6371 | ++vcpu->stat.signal_exits; |
6372 | } | |
6373 | if (need_resched()) { | |
f656ce01 | 6374 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 6375 | cond_resched(); |
f656ce01 | 6376 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6377 | } |
b6c7a5dc HB |
6378 | } |
6379 | ||
f656ce01 | 6380 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
6381 | |
6382 | return r; | |
6383 | } | |
6384 | ||
716d51ab GN |
6385 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
6386 | { | |
6387 | int r; | |
6388 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6389 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6390 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6391 | if (r != EMULATE_DONE) | |
6392 | return 0; | |
6393 | return 1; | |
6394 | } | |
6395 | ||
6396 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6397 | { | |
6398 | BUG_ON(!vcpu->arch.pio.count); | |
6399 | ||
6400 | return complete_emulated_io(vcpu); | |
6401 | } | |
6402 | ||
f78146b0 AK |
6403 | /* |
6404 | * Implements the following, as a state machine: | |
6405 | * | |
6406 | * read: | |
6407 | * for each fragment | |
87da7e66 XG |
6408 | * for each mmio piece in the fragment |
6409 | * write gpa, len | |
6410 | * exit | |
6411 | * copy data | |
f78146b0 AK |
6412 | * execute insn |
6413 | * | |
6414 | * write: | |
6415 | * for each fragment | |
87da7e66 XG |
6416 | * for each mmio piece in the fragment |
6417 | * write gpa, len | |
6418 | * copy data | |
6419 | * exit | |
f78146b0 | 6420 | */ |
716d51ab | 6421 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
6422 | { |
6423 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 6424 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6425 | unsigned len; |
5287f194 | 6426 | |
716d51ab | 6427 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6428 | |
716d51ab | 6429 | /* Complete previous fragment */ |
87da7e66 XG |
6430 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6431 | len = min(8u, frag->len); | |
716d51ab | 6432 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6433 | memcpy(frag->data, run->mmio.data, len); |
6434 | ||
6435 | if (frag->len <= 8) { | |
6436 | /* Switch to the next fragment. */ | |
6437 | frag++; | |
6438 | vcpu->mmio_cur_fragment++; | |
6439 | } else { | |
6440 | /* Go forward to the next mmio piece. */ | |
6441 | frag->data += len; | |
6442 | frag->gpa += len; | |
6443 | frag->len -= len; | |
6444 | } | |
6445 | ||
a08d3b3b | 6446 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 6447 | vcpu->mmio_needed = 0; |
0912c977 PB |
6448 | |
6449 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 6450 | if (vcpu->mmio_is_write) |
716d51ab GN |
6451 | return 1; |
6452 | vcpu->mmio_read_completed = 1; | |
6453 | return complete_emulated_io(vcpu); | |
6454 | } | |
87da7e66 | 6455 | |
716d51ab GN |
6456 | run->exit_reason = KVM_EXIT_MMIO; |
6457 | run->mmio.phys_addr = frag->gpa; | |
6458 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6459 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6460 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6461 | run->mmio.is_write = vcpu->mmio_is_write; |
6462 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6463 | return 0; | |
5287f194 AK |
6464 | } |
6465 | ||
716d51ab | 6466 | |
b6c7a5dc HB |
6467 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6468 | { | |
6469 | int r; | |
6470 | sigset_t sigsaved; | |
6471 | ||
e5c30142 AK |
6472 | if (!tsk_used_math(current) && init_fpu(current)) |
6473 | return -ENOMEM; | |
6474 | ||
ac9f6dc0 AK |
6475 | if (vcpu->sigset_active) |
6476 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6477 | ||
a4535290 | 6478 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6479 | kvm_vcpu_block(vcpu); |
66450a21 | 6480 | kvm_apic_accept_events(vcpu); |
d7690175 | 6481 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6482 | r = -EAGAIN; |
6483 | goto out; | |
b6c7a5dc HB |
6484 | } |
6485 | ||
b6c7a5dc | 6486 | /* re-sync apic's tpr */ |
eea1cff9 AP |
6487 | if (!irqchip_in_kernel(vcpu->kvm)) { |
6488 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
6489 | r = -EINVAL; | |
6490 | goto out; | |
6491 | } | |
6492 | } | |
b6c7a5dc | 6493 | |
716d51ab GN |
6494 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6495 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6496 | vcpu->arch.complete_userspace_io = NULL; | |
6497 | r = cui(vcpu); | |
6498 | if (r <= 0) | |
6499 | goto out; | |
6500 | } else | |
6501 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6502 | |
851ba692 | 6503 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
6504 | |
6505 | out: | |
f1d86e46 | 6506 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6507 | if (vcpu->sigset_active) |
6508 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6509 | ||
b6c7a5dc HB |
6510 | return r; |
6511 | } | |
6512 | ||
6513 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6514 | { | |
7ae441ea GN |
6515 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6516 | /* | |
6517 | * We are here if userspace calls get_regs() in the middle of | |
6518 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6519 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6520 | * that usually, but some bad designed PV devices (vmware |
6521 | * backdoor interface) need this to work | |
6522 | */ | |
dd856efa | 6523 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6524 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6525 | } | |
5fdbf976 MT |
6526 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6527 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6528 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6529 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6530 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6531 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6532 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6533 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6534 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6535 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6536 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6537 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6538 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6539 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6540 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6541 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6542 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6543 | #endif |
6544 | ||
5fdbf976 | 6545 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6546 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6547 | |
b6c7a5dc HB |
6548 | return 0; |
6549 | } | |
6550 | ||
6551 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6552 | { | |
7ae441ea GN |
6553 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
6554 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6555 | ||
5fdbf976 MT |
6556 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
6557 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6558 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6559 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6560 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6561 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6562 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6563 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 6564 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6565 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
6566 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6567 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6568 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6569 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6570 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6571 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6572 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
6573 | #endif |
6574 | ||
5fdbf976 | 6575 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 6576 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 6577 | |
b4f14abd JK |
6578 | vcpu->arch.exception.pending = false; |
6579 | ||
3842d135 AK |
6580 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6581 | ||
b6c7a5dc HB |
6582 | return 0; |
6583 | } | |
6584 | ||
b6c7a5dc HB |
6585 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
6586 | { | |
6587 | struct kvm_segment cs; | |
6588 | ||
3e6e0aab | 6589 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
6590 | *db = cs.db; |
6591 | *l = cs.l; | |
6592 | } | |
6593 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6594 | ||
6595 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6596 | struct kvm_sregs *sregs) | |
6597 | { | |
89a27f4d | 6598 | struct desc_ptr dt; |
b6c7a5dc | 6599 | |
3e6e0aab GT |
6600 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6601 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6602 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6603 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6604 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6605 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6606 | |
3e6e0aab GT |
6607 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6608 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
6609 | |
6610 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
6611 | sregs->idt.limit = dt.size; |
6612 | sregs->idt.base = dt.address; | |
b6c7a5dc | 6613 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
6614 | sregs->gdt.limit = dt.size; |
6615 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 6616 | |
4d4ec087 | 6617 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 6618 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 6619 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 6620 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 6621 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 6622 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
6623 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6624 | ||
923c61bb | 6625 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 6626 | |
36752c9b | 6627 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
6628 | set_bit(vcpu->arch.interrupt.nr, |
6629 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 6630 | |
b6c7a5dc HB |
6631 | return 0; |
6632 | } | |
6633 | ||
62d9f0db MT |
6634 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
6635 | struct kvm_mp_state *mp_state) | |
6636 | { | |
66450a21 | 6637 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
6638 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
6639 | vcpu->arch.pv.pv_unhalted) | |
6640 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
6641 | else | |
6642 | mp_state->mp_state = vcpu->arch.mp_state; | |
6643 | ||
62d9f0db MT |
6644 | return 0; |
6645 | } | |
6646 | ||
6647 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
6648 | struct kvm_mp_state *mp_state) | |
6649 | { | |
66450a21 JK |
6650 | if (!kvm_vcpu_has_lapic(vcpu) && |
6651 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
6652 | return -EINVAL; | |
6653 | ||
6654 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
6655 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
6656 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
6657 | } else | |
6658 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 6659 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
6660 | return 0; |
6661 | } | |
6662 | ||
7f3d35fd KW |
6663 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
6664 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 6665 | { |
9d74191a | 6666 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 6667 | int ret; |
e01c2426 | 6668 | |
8ec4722d | 6669 | init_emulate_ctxt(vcpu); |
c697518a | 6670 | |
7f3d35fd | 6671 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 6672 | has_error_code, error_code); |
c697518a | 6673 | |
c697518a | 6674 | if (ret) |
19d04437 | 6675 | return EMULATE_FAIL; |
37817f29 | 6676 | |
9d74191a TY |
6677 | kvm_rip_write(vcpu, ctxt->eip); |
6678 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 6679 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 6680 | return EMULATE_DONE; |
37817f29 IE |
6681 | } |
6682 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
6683 | ||
b6c7a5dc HB |
6684 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
6685 | struct kvm_sregs *sregs) | |
6686 | { | |
58cb628d | 6687 | struct msr_data apic_base_msr; |
b6c7a5dc | 6688 | int mmu_reset_needed = 0; |
63f42e02 | 6689 | int pending_vec, max_bits, idx; |
89a27f4d | 6690 | struct desc_ptr dt; |
b6c7a5dc | 6691 | |
6d1068b3 PM |
6692 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
6693 | return -EINVAL; | |
6694 | ||
89a27f4d GN |
6695 | dt.size = sregs->idt.limit; |
6696 | dt.address = sregs->idt.base; | |
b6c7a5dc | 6697 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
6698 | dt.size = sregs->gdt.limit; |
6699 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
6700 | kvm_x86_ops->set_gdt(vcpu, &dt); |
6701 | ||
ad312c7c | 6702 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 6703 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 6704 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 6705 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 6706 | |
2d3ad1f4 | 6707 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 6708 | |
f6801dff | 6709 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 6710 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
58cb628d JK |
6711 | apic_base_msr.data = sregs->apic_base; |
6712 | apic_base_msr.host_initiated = true; | |
6713 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
b6c7a5dc | 6714 | |
4d4ec087 | 6715 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 6716 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 6717 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 6718 | |
fc78f519 | 6719 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 6720 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 6721 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 6722 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
6723 | |
6724 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 6725 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 6726 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
6727 | mmu_reset_needed = 1; |
6728 | } | |
63f42e02 | 6729 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
6730 | |
6731 | if (mmu_reset_needed) | |
6732 | kvm_mmu_reset_context(vcpu); | |
6733 | ||
a50abc3b | 6734 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
6735 | pending_vec = find_first_bit( |
6736 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6737 | if (pending_vec < max_bits) { | |
66fd3f7f | 6738 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 6739 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
6740 | } |
6741 | ||
3e6e0aab GT |
6742 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6743 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6744 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6745 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6746 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6747 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6748 | |
3e6e0aab GT |
6749 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6750 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 6751 | |
5f0269f5 ME |
6752 | update_cr8_intercept(vcpu); |
6753 | ||
9c3e4aab | 6754 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 6755 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 6756 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 6757 | !is_protmode(vcpu)) |
9c3e4aab MT |
6758 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
6759 | ||
3842d135 AK |
6760 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6761 | ||
b6c7a5dc HB |
6762 | return 0; |
6763 | } | |
6764 | ||
d0bfb940 JK |
6765 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
6766 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 6767 | { |
355be0b9 | 6768 | unsigned long rflags; |
ae675ef0 | 6769 | int i, r; |
b6c7a5dc | 6770 | |
4f926bf2 JK |
6771 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
6772 | r = -EBUSY; | |
6773 | if (vcpu->arch.exception.pending) | |
2122ff5e | 6774 | goto out; |
4f926bf2 JK |
6775 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
6776 | kvm_queue_exception(vcpu, DB_VECTOR); | |
6777 | else | |
6778 | kvm_queue_exception(vcpu, BP_VECTOR); | |
6779 | } | |
6780 | ||
91586a3b JK |
6781 | /* |
6782 | * Read rflags as long as potentially injected trace flags are still | |
6783 | * filtered out. | |
6784 | */ | |
6785 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
6786 | |
6787 | vcpu->guest_debug = dbg->control; | |
6788 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
6789 | vcpu->guest_debug = 0; | |
6790 | ||
6791 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
6792 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
6793 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 6794 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
6795 | } else { |
6796 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6797 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 6798 | } |
c8639010 | 6799 | kvm_update_dr7(vcpu); |
ae675ef0 | 6800 | |
f92653ee JK |
6801 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
6802 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
6803 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 6804 | |
91586a3b JK |
6805 | /* |
6806 | * Trigger an rflags update that will inject or remove the trace | |
6807 | * flags. | |
6808 | */ | |
6809 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 6810 | |
c8639010 | 6811 | kvm_x86_ops->update_db_bp_intercept(vcpu); |
b6c7a5dc | 6812 | |
4f926bf2 | 6813 | r = 0; |
d0bfb940 | 6814 | |
2122ff5e | 6815 | out: |
b6c7a5dc HB |
6816 | |
6817 | return r; | |
6818 | } | |
6819 | ||
8b006791 ZX |
6820 | /* |
6821 | * Translate a guest virtual address to a guest physical address. | |
6822 | */ | |
6823 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
6824 | struct kvm_translation *tr) | |
6825 | { | |
6826 | unsigned long vaddr = tr->linear_address; | |
6827 | gpa_t gpa; | |
f656ce01 | 6828 | int idx; |
8b006791 | 6829 | |
f656ce01 | 6830 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 6831 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 6832 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
6833 | tr->physical_address = gpa; |
6834 | tr->valid = gpa != UNMAPPED_GVA; | |
6835 | tr->writeable = 1; | |
6836 | tr->usermode = 0; | |
8b006791 ZX |
6837 | |
6838 | return 0; | |
6839 | } | |
6840 | ||
d0752060 HB |
6841 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
6842 | { | |
98918833 SY |
6843 | struct i387_fxsave_struct *fxsave = |
6844 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6845 | |
d0752060 HB |
6846 | memcpy(fpu->fpr, fxsave->st_space, 128); |
6847 | fpu->fcw = fxsave->cwd; | |
6848 | fpu->fsw = fxsave->swd; | |
6849 | fpu->ftwx = fxsave->twd; | |
6850 | fpu->last_opcode = fxsave->fop; | |
6851 | fpu->last_ip = fxsave->rip; | |
6852 | fpu->last_dp = fxsave->rdp; | |
6853 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
6854 | ||
d0752060 HB |
6855 | return 0; |
6856 | } | |
6857 | ||
6858 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
6859 | { | |
98918833 SY |
6860 | struct i387_fxsave_struct *fxsave = |
6861 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 6862 | |
d0752060 HB |
6863 | memcpy(fxsave->st_space, fpu->fpr, 128); |
6864 | fxsave->cwd = fpu->fcw; | |
6865 | fxsave->swd = fpu->fsw; | |
6866 | fxsave->twd = fpu->ftwx; | |
6867 | fxsave->fop = fpu->last_opcode; | |
6868 | fxsave->rip = fpu->last_ip; | |
6869 | fxsave->rdp = fpu->last_dp; | |
6870 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
6871 | ||
d0752060 HB |
6872 | return 0; |
6873 | } | |
6874 | ||
10ab25cd | 6875 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 6876 | { |
10ab25cd JK |
6877 | int err; |
6878 | ||
6879 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
6880 | if (err) | |
6881 | return err; | |
6882 | ||
98918833 | 6883 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 6884 | |
2acf923e DC |
6885 | /* |
6886 | * Ensure guest xcr0 is valid for loading | |
6887 | */ | |
6888 | vcpu->arch.xcr0 = XSTATE_FP; | |
6889 | ||
ad312c7c | 6890 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
6891 | |
6892 | return 0; | |
d0752060 HB |
6893 | } |
6894 | EXPORT_SYMBOL_GPL(fx_init); | |
6895 | ||
98918833 SY |
6896 | static void fx_free(struct kvm_vcpu *vcpu) |
6897 | { | |
6898 | fpu_free(&vcpu->arch.guest_fpu); | |
6899 | } | |
6900 | ||
d0752060 HB |
6901 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
6902 | { | |
2608d7a1 | 6903 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
6904 | return; |
6905 | ||
2acf923e DC |
6906 | /* |
6907 | * Restore all possible states in the guest, | |
6908 | * and assume host would use all available bits. | |
6909 | * Guest xcr0 would be loaded later. | |
6910 | */ | |
6911 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 6912 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 6913 | __kernel_fpu_begin(); |
98918833 | 6914 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 6915 | trace_kvm_fpu(1); |
d0752060 | 6916 | } |
d0752060 HB |
6917 | |
6918 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
6919 | { | |
2acf923e DC |
6920 | kvm_put_guest_xcr0(vcpu); |
6921 | ||
d0752060 HB |
6922 | if (!vcpu->guest_fpu_loaded) |
6923 | return; | |
6924 | ||
6925 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 6926 | fpu_save_init(&vcpu->arch.guest_fpu); |
b1a74bf8 | 6927 | __kernel_fpu_end(); |
f096ed85 | 6928 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 6929 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 6930 | trace_kvm_fpu(0); |
d0752060 | 6931 | } |
e9b11c17 ZX |
6932 | |
6933 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
6934 | { | |
12f9a48f | 6935 | kvmclock_reset(vcpu); |
7f1ea208 | 6936 | |
f5f48ee1 | 6937 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 6938 | fx_free(vcpu); |
e9b11c17 ZX |
6939 | kvm_x86_ops->vcpu_free(vcpu); |
6940 | } | |
6941 | ||
6942 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
6943 | unsigned int id) | |
6944 | { | |
6755bae8 ZA |
6945 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
6946 | printk_once(KERN_WARNING | |
6947 | "kvm: SMP vm created on host with unstable TSC; " | |
6948 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
6949 | return kvm_x86_ops->vcpu_create(kvm, id); |
6950 | } | |
e9b11c17 | 6951 | |
26e5215f AK |
6952 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
6953 | { | |
6954 | int r; | |
e9b11c17 | 6955 | |
0bed3b56 | 6956 | vcpu->arch.mtrr_state.have_fixed = 1; |
9fc77441 MT |
6957 | r = vcpu_load(vcpu); |
6958 | if (r) | |
6959 | return r; | |
57f252f2 | 6960 | kvm_vcpu_reset(vcpu); |
8a3c1a33 | 6961 | kvm_mmu_setup(vcpu); |
e9b11c17 | 6962 | vcpu_put(vcpu); |
e9b11c17 | 6963 | |
26e5215f | 6964 | return r; |
e9b11c17 ZX |
6965 | } |
6966 | ||
42897d86 MT |
6967 | int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
6968 | { | |
6969 | int r; | |
8fe8ab46 | 6970 | struct msr_data msr; |
332967a3 | 6971 | struct kvm *kvm = vcpu->kvm; |
42897d86 MT |
6972 | |
6973 | r = vcpu_load(vcpu); | |
6974 | if (r) | |
6975 | return r; | |
8fe8ab46 WA |
6976 | msr.data = 0x0; |
6977 | msr.index = MSR_IA32_TSC; | |
6978 | msr.host_initiated = true; | |
6979 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
6980 | vcpu_put(vcpu); |
6981 | ||
332967a3 AJ |
6982 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
6983 | KVMCLOCK_SYNC_PERIOD); | |
6984 | ||
42897d86 MT |
6985 | return r; |
6986 | } | |
6987 | ||
d40ccc62 | 6988 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 6989 | { |
9fc77441 | 6990 | int r; |
344d9588 GN |
6991 | vcpu->arch.apf.msr_val = 0; |
6992 | ||
9fc77441 MT |
6993 | r = vcpu_load(vcpu); |
6994 | BUG_ON(r); | |
e9b11c17 ZX |
6995 | kvm_mmu_unload(vcpu); |
6996 | vcpu_put(vcpu); | |
6997 | ||
98918833 | 6998 | fx_free(vcpu); |
e9b11c17 ZX |
6999 | kvm_x86_ops->vcpu_free(vcpu); |
7000 | } | |
7001 | ||
66450a21 | 7002 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu) |
e9b11c17 | 7003 | { |
7460fb4a AK |
7004 | atomic_set(&vcpu->arch.nmi_queued, 0); |
7005 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 7006 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
7007 | kvm_clear_interrupt_queue(vcpu); |
7008 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 7009 | |
42dbaa5a | 7010 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
6f43ed01 | 7011 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 7012 | kvm_update_dr6(vcpu); |
42dbaa5a | 7013 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 7014 | kvm_update_dr7(vcpu); |
42dbaa5a | 7015 | |
3842d135 | 7016 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 7017 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 7018 | vcpu->arch.st.msr_val = 0; |
3842d135 | 7019 | |
12f9a48f GC |
7020 | kvmclock_reset(vcpu); |
7021 | ||
af585b92 GN |
7022 | kvm_clear_async_pf_completion_queue(vcpu); |
7023 | kvm_async_pf_hash_reset(vcpu); | |
7024 | vcpu->arch.apf.halted = false; | |
3842d135 | 7025 | |
f5132b01 GN |
7026 | kvm_pmu_reset(vcpu); |
7027 | ||
66f7b72e JS |
7028 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
7029 | vcpu->arch.regs_avail = ~0; | |
7030 | vcpu->arch.regs_dirty = ~0; | |
7031 | ||
57f252f2 | 7032 | kvm_x86_ops->vcpu_reset(vcpu); |
e9b11c17 ZX |
7033 | } |
7034 | ||
66450a21 JK |
7035 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector) |
7036 | { | |
7037 | struct kvm_segment cs; | |
7038 | ||
7039 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7040 | cs.selector = vector << 8; | |
7041 | cs.base = vector << 12; | |
7042 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7043 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
7044 | } |
7045 | ||
13a34e06 | 7046 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 7047 | { |
ca84d1a2 ZA |
7048 | struct kvm *kvm; |
7049 | struct kvm_vcpu *vcpu; | |
7050 | int i; | |
0dd6a6ed ZA |
7051 | int ret; |
7052 | u64 local_tsc; | |
7053 | u64 max_tsc = 0; | |
7054 | bool stable, backwards_tsc = false; | |
18863bdd AK |
7055 | |
7056 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 7057 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
7058 | if (ret != 0) |
7059 | return ret; | |
7060 | ||
7061 | local_tsc = native_read_tsc(); | |
7062 | stable = !check_tsc_unstable(); | |
7063 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7064 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7065 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 7066 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7067 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
7068 | backwards_tsc = true; | |
7069 | if (vcpu->arch.last_host_tsc > max_tsc) | |
7070 | max_tsc = vcpu->arch.last_host_tsc; | |
7071 | } | |
7072 | } | |
7073 | } | |
7074 | ||
7075 | /* | |
7076 | * Sometimes, even reliable TSCs go backwards. This happens on | |
7077 | * platforms that reset TSC during suspend or hibernate actions, but | |
7078 | * maintain synchronization. We must compensate. Fortunately, we can | |
7079 | * detect that condition here, which happens early in CPU bringup, | |
7080 | * before any KVM threads can be running. Unfortunately, we can't | |
7081 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
7082 | * enough into CPU bringup that we know how much real time has actually | |
7083 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
7084 | * variables that haven't been updated yet. | |
7085 | * | |
7086 | * So we simply find the maximum observed TSC above, then record the | |
7087 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
7088 | * the adjustment will be applied. Note that we accumulate | |
7089 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
7090 | * gets a chance to run again. In the event that no KVM threads get a | |
7091 | * chance to run, we will miss the entire elapsed period, as we'll have | |
7092 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
7093 | * loose cycle time. This isn't too big a deal, since the loss will be | |
7094 | * uniform across all VCPUs (not to mention the scenario is extremely | |
7095 | * unlikely). It is possible that a second hibernate recovery happens | |
7096 | * much faster than a first, causing the observed TSC here to be | |
7097 | * smaller; this would require additional padding adjustment, which is | |
7098 | * why we set last_host_tsc to the local tsc observed here. | |
7099 | * | |
7100 | * N.B. - this code below runs only on platforms with reliable TSC, | |
7101 | * as that is the only way backwards_tsc is set above. Also note | |
7102 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
7103 | * have the same delta_cyc adjustment applied if backwards_tsc | |
7104 | * is detected. Note further, this adjustment is only done once, | |
7105 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
7106 | * called multiple times (one for each physical CPU bringup). | |
7107 | * | |
4a969980 | 7108 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
7109 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
7110 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
7111 | * guarantee that they stay in perfect synchronization. | |
7112 | */ | |
7113 | if (backwards_tsc) { | |
7114 | u64 delta_cyc = max_tsc - local_tsc; | |
16a96021 | 7115 | backwards_tsc_observed = true; |
0dd6a6ed ZA |
7116 | list_for_each_entry(kvm, &vm_list, vm_list) { |
7117 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7118 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
7119 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 7120 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7121 | } |
7122 | ||
7123 | /* | |
7124 | * We have to disable TSC offset matching.. if you were | |
7125 | * booting a VM while issuing an S4 host suspend.... | |
7126 | * you may have some problem. Solving this issue is | |
7127 | * left as an exercise to the reader. | |
7128 | */ | |
7129 | kvm->arch.last_tsc_nsec = 0; | |
7130 | kvm->arch.last_tsc_write = 0; | |
7131 | } | |
7132 | ||
7133 | } | |
7134 | return 0; | |
e9b11c17 ZX |
7135 | } |
7136 | ||
13a34e06 | 7137 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 7138 | { |
13a34e06 RK |
7139 | kvm_x86_ops->hardware_disable(); |
7140 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
7141 | } |
7142 | ||
7143 | int kvm_arch_hardware_setup(void) | |
7144 | { | |
7145 | return kvm_x86_ops->hardware_setup(); | |
7146 | } | |
7147 | ||
7148 | void kvm_arch_hardware_unsetup(void) | |
7149 | { | |
7150 | kvm_x86_ops->hardware_unsetup(); | |
7151 | } | |
7152 | ||
7153 | void kvm_arch_check_processor_compat(void *rtn) | |
7154 | { | |
7155 | kvm_x86_ops->check_processor_compatibility(rtn); | |
7156 | } | |
7157 | ||
3e515705 AK |
7158 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
7159 | { | |
7160 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
7161 | } | |
7162 | ||
54e9818f GN |
7163 | struct static_key kvm_no_apic_vcpu __read_mostly; |
7164 | ||
e9b11c17 ZX |
7165 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
7166 | { | |
7167 | struct page *page; | |
7168 | struct kvm *kvm; | |
7169 | int r; | |
7170 | ||
7171 | BUG_ON(vcpu->kvm == NULL); | |
7172 | kvm = vcpu->kvm; | |
7173 | ||
6aef266c | 7174 | vcpu->arch.pv.pv_unhalted = false; |
9aabc88f | 7175 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
c5af89b6 | 7176 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 7177 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 7178 | else |
a4535290 | 7179 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
7180 | |
7181 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
7182 | if (!page) { | |
7183 | r = -ENOMEM; | |
7184 | goto fail; | |
7185 | } | |
ad312c7c | 7186 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 7187 | |
cc578287 | 7188 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 7189 | |
e9b11c17 ZX |
7190 | r = kvm_mmu_create(vcpu); |
7191 | if (r < 0) | |
7192 | goto fail_free_pio_data; | |
7193 | ||
7194 | if (irqchip_in_kernel(kvm)) { | |
7195 | r = kvm_create_lapic(vcpu); | |
7196 | if (r < 0) | |
7197 | goto fail_mmu_destroy; | |
54e9818f GN |
7198 | } else |
7199 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 7200 | |
890ca9ae HY |
7201 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
7202 | GFP_KERNEL); | |
7203 | if (!vcpu->arch.mce_banks) { | |
7204 | r = -ENOMEM; | |
443c39bc | 7205 | goto fail_free_lapic; |
890ca9ae HY |
7206 | } |
7207 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
7208 | ||
f1797359 WY |
7209 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
7210 | r = -ENOMEM; | |
f5f48ee1 | 7211 | goto fail_free_mce_banks; |
f1797359 | 7212 | } |
f5f48ee1 | 7213 | |
66f7b72e JS |
7214 | r = fx_init(vcpu); |
7215 | if (r) | |
7216 | goto fail_free_wbinvd_dirty_mask; | |
7217 | ||
ba904635 | 7218 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 7219 | vcpu->arch.pv_time_enabled = false; |
d7876f1b PB |
7220 | |
7221 | vcpu->arch.guest_supported_xcr0 = 0; | |
4344ee98 | 7222 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 7223 | |
af585b92 | 7224 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 7225 | kvm_pmu_init(vcpu); |
af585b92 | 7226 | |
e9b11c17 | 7227 | return 0; |
66f7b72e JS |
7228 | fail_free_wbinvd_dirty_mask: |
7229 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
7230 | fail_free_mce_banks: |
7231 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
7232 | fail_free_lapic: |
7233 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
7234 | fail_mmu_destroy: |
7235 | kvm_mmu_destroy(vcpu); | |
7236 | fail_free_pio_data: | |
ad312c7c | 7237 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
7238 | fail: |
7239 | return r; | |
7240 | } | |
7241 | ||
7242 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
7243 | { | |
f656ce01 MT |
7244 | int idx; |
7245 | ||
f5132b01 | 7246 | kvm_pmu_destroy(vcpu); |
36cb93fd | 7247 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 7248 | kvm_free_lapic(vcpu); |
f656ce01 | 7249 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 7250 | kvm_mmu_destroy(vcpu); |
f656ce01 | 7251 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 7252 | free_page((unsigned long)vcpu->arch.pio_data); |
54e9818f GN |
7253 | if (!irqchip_in_kernel(vcpu->kvm)) |
7254 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 | 7255 | } |
d19a9cd2 | 7256 | |
e790d9ef RK |
7257 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
7258 | { | |
ae97a3b8 | 7259 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
7260 | } |
7261 | ||
e08b9637 | 7262 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 7263 | { |
e08b9637 CO |
7264 | if (type) |
7265 | return -EINVAL; | |
7266 | ||
f05e70ac | 7267 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 7268 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 7269 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 7270 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 7271 | |
5550af4d SY |
7272 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
7273 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
7274 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
7275 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7276 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 7277 | |
038f8c11 | 7278 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 7279 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
7280 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
7281 | ||
7282 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 7283 | |
7e44e449 | 7284 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 7285 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 7286 | |
d89f5eff | 7287 | return 0; |
d19a9cd2 ZX |
7288 | } |
7289 | ||
7290 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7291 | { | |
9fc77441 MT |
7292 | int r; |
7293 | r = vcpu_load(vcpu); | |
7294 | BUG_ON(r); | |
d19a9cd2 ZX |
7295 | kvm_mmu_unload(vcpu); |
7296 | vcpu_put(vcpu); | |
7297 | } | |
7298 | ||
7299 | static void kvm_free_vcpus(struct kvm *kvm) | |
7300 | { | |
7301 | unsigned int i; | |
988a2cae | 7302 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
7303 | |
7304 | /* | |
7305 | * Unpin any mmu pages first. | |
7306 | */ | |
af585b92 GN |
7307 | kvm_for_each_vcpu(i, vcpu, kvm) { |
7308 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 7309 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 7310 | } |
988a2cae GN |
7311 | kvm_for_each_vcpu(i, vcpu, kvm) |
7312 | kvm_arch_vcpu_free(vcpu); | |
7313 | ||
7314 | mutex_lock(&kvm->lock); | |
7315 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7316 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 7317 | |
988a2cae GN |
7318 | atomic_set(&kvm->online_vcpus, 0); |
7319 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
7320 | } |
7321 | ||
ad8ba2cd SY |
7322 | void kvm_arch_sync_events(struct kvm *kvm) |
7323 | { | |
332967a3 | 7324 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 7325 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
ba4cef31 | 7326 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 7327 | kvm_free_pit(kvm); |
ad8ba2cd SY |
7328 | } |
7329 | ||
d19a9cd2 ZX |
7330 | void kvm_arch_destroy_vm(struct kvm *kvm) |
7331 | { | |
27469d29 AH |
7332 | if (current->mm == kvm->mm) { |
7333 | /* | |
7334 | * Free memory regions allocated on behalf of userspace, | |
7335 | * unless the the memory map has changed due to process exit | |
7336 | * or fd copying. | |
7337 | */ | |
7338 | struct kvm_userspace_memory_region mem; | |
7339 | memset(&mem, 0, sizeof(mem)); | |
7340 | mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
7341 | kvm_set_memory_region(kvm, &mem); | |
7342 | ||
7343 | mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
7344 | kvm_set_memory_region(kvm, &mem); | |
7345 | ||
7346 | mem.slot = TSS_PRIVATE_MEMSLOT; | |
7347 | kvm_set_memory_region(kvm, &mem); | |
7348 | } | |
6eb55818 | 7349 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
7350 | kfree(kvm->arch.vpic); |
7351 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 7352 | kvm_free_vcpus(kvm); |
1e08ec4a | 7353 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 7354 | } |
0de10343 | 7355 | |
5587027c | 7356 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
7357 | struct kvm_memory_slot *dont) |
7358 | { | |
7359 | int i; | |
7360 | ||
d89cc617 TY |
7361 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7362 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
7363 | kvm_kvfree(free->arch.rmap[i]); | |
7364 | free->arch.rmap[i] = NULL; | |
77d11309 | 7365 | } |
d89cc617 TY |
7366 | if (i == 0) |
7367 | continue; | |
7368 | ||
7369 | if (!dont || free->arch.lpage_info[i - 1] != | |
7370 | dont->arch.lpage_info[i - 1]) { | |
7371 | kvm_kvfree(free->arch.lpage_info[i - 1]); | |
7372 | free->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb TY |
7373 | } |
7374 | } | |
7375 | } | |
7376 | ||
5587027c AK |
7377 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
7378 | unsigned long npages) | |
db3fe4eb TY |
7379 | { |
7380 | int i; | |
7381 | ||
d89cc617 | 7382 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
7383 | unsigned long ugfn; |
7384 | int lpages; | |
d89cc617 | 7385 | int level = i + 1; |
db3fe4eb TY |
7386 | |
7387 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7388 | slot->base_gfn, level) + 1; | |
7389 | ||
d89cc617 TY |
7390 | slot->arch.rmap[i] = |
7391 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7392 | if (!slot->arch.rmap[i]) | |
77d11309 | 7393 | goto out_free; |
d89cc617 TY |
7394 | if (i == 0) |
7395 | continue; | |
77d11309 | 7396 | |
d89cc617 TY |
7397 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
7398 | sizeof(*slot->arch.lpage_info[i - 1])); | |
7399 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
7400 | goto out_free; |
7401 | ||
7402 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 7403 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 7404 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 7405 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
7406 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
7407 | /* | |
7408 | * If the gfn and userspace address are not aligned wrt each | |
7409 | * other, or if explicitly asked to, disable large page | |
7410 | * support for this slot | |
7411 | */ | |
7412 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7413 | !kvm_largepages_enabled()) { | |
7414 | unsigned long j; | |
7415 | ||
7416 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 7417 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
7418 | } |
7419 | } | |
7420 | ||
7421 | return 0; | |
7422 | ||
7423 | out_free: | |
d89cc617 TY |
7424 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7425 | kvm_kvfree(slot->arch.rmap[i]); | |
7426 | slot->arch.rmap[i] = NULL; | |
7427 | if (i == 0) | |
7428 | continue; | |
7429 | ||
7430 | kvm_kvfree(slot->arch.lpage_info[i - 1]); | |
7431 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb TY |
7432 | } |
7433 | return -ENOMEM; | |
7434 | } | |
7435 | ||
e59dbe09 TY |
7436 | void kvm_arch_memslots_updated(struct kvm *kvm) |
7437 | { | |
e6dff7d1 TY |
7438 | /* |
7439 | * memslots->generation has been incremented. | |
7440 | * mmio generation may have reached its maximum value. | |
7441 | */ | |
7442 | kvm_mmu_invalidate_mmio_sptes(kvm); | |
e59dbe09 TY |
7443 | } |
7444 | ||
f7784b8e MT |
7445 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
7446 | struct kvm_memory_slot *memslot, | |
f7784b8e | 7447 | struct kvm_userspace_memory_region *mem, |
7b6195a9 | 7448 | enum kvm_mr_change change) |
0de10343 | 7449 | { |
7a905b14 TY |
7450 | /* |
7451 | * Only private memory slots need to be mapped here since | |
7452 | * KVM_SET_MEMORY_REGION ioctl is no longer supported. | |
0de10343 | 7453 | */ |
7b6195a9 | 7454 | if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { |
7a905b14 | 7455 | unsigned long userspace_addr; |
604b38ac | 7456 | |
7a905b14 TY |
7457 | /* |
7458 | * MAP_SHARED to prevent internal slot pages from being moved | |
7459 | * by fork()/COW. | |
7460 | */ | |
7b6195a9 | 7461 | userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, |
7a905b14 TY |
7462 | PROT_READ | PROT_WRITE, |
7463 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
0de10343 | 7464 | |
7a905b14 TY |
7465 | if (IS_ERR((void *)userspace_addr)) |
7466 | return PTR_ERR((void *)userspace_addr); | |
604b38ac | 7467 | |
7a905b14 | 7468 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
7469 | } |
7470 | ||
f7784b8e MT |
7471 | return 0; |
7472 | } | |
7473 | ||
7474 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
7475 | struct kvm_userspace_memory_region *mem, | |
8482644a TY |
7476 | const struct kvm_memory_slot *old, |
7477 | enum kvm_mr_change change) | |
f7784b8e MT |
7478 | { |
7479 | ||
8482644a | 7480 | int nr_mmu_pages = 0; |
f7784b8e | 7481 | |
8482644a | 7482 | if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { |
f7784b8e MT |
7483 | int ret; |
7484 | ||
8482644a TY |
7485 | ret = vm_munmap(old->userspace_addr, |
7486 | old->npages * PAGE_SIZE); | |
f7784b8e MT |
7487 | if (ret < 0) |
7488 | printk(KERN_WARNING | |
7489 | "kvm_vm_ioctl_set_memory_region: " | |
7490 | "failed to munmap memory\n"); | |
7491 | } | |
7492 | ||
48c0e4e9 XG |
7493 | if (!kvm->arch.n_requested_mmu_pages) |
7494 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
7495 | ||
48c0e4e9 | 7496 | if (nr_mmu_pages) |
0de10343 | 7497 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
c972f3b1 TY |
7498 | /* |
7499 | * Write protect all pages for dirty logging. | |
c126d94f XG |
7500 | * |
7501 | * All the sptes including the large sptes which point to this | |
7502 | * slot are set to readonly. We can not create any new large | |
7503 | * spte on this slot until the end of the logging. | |
7504 | * | |
7505 | * See the comments in fast_page_fault(). | |
c972f3b1 | 7506 | */ |
8482644a | 7507 | if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES)) |
c972f3b1 | 7508 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); |
0de10343 | 7509 | } |
1d737c8a | 7510 | |
2df72e9b | 7511 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 7512 | { |
6ca18b69 | 7513 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
7514 | } |
7515 | ||
2df72e9b MT |
7516 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
7517 | struct kvm_memory_slot *slot) | |
7518 | { | |
6ca18b69 | 7519 | kvm_mmu_invalidate_zap_all_pages(kvm); |
2df72e9b MT |
7520 | } |
7521 | ||
1d737c8a ZX |
7522 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
7523 | { | |
b6b8a145 JK |
7524 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
7525 | kvm_x86_ops->check_nested_events(vcpu, false); | |
7526 | ||
af585b92 GN |
7527 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
7528 | !vcpu->arch.apf.halted) | |
7529 | || !list_empty_careful(&vcpu->async_pf.done) | |
66450a21 | 7530 | || kvm_apic_has_events(vcpu) |
6aef266c | 7531 | || vcpu->arch.pv.pv_unhalted |
7460fb4a | 7532 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
7533 | (kvm_arch_interrupt_allowed(vcpu) && |
7534 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 7535 | } |
5736199a | 7536 | |
b6d33834 | 7537 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 7538 | { |
b6d33834 | 7539 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 7540 | } |
78646121 GN |
7541 | |
7542 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
7543 | { | |
7544 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
7545 | } | |
229456fc | 7546 | |
82b32774 | 7547 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 7548 | { |
82b32774 NA |
7549 | if (is_64_bit_mode(vcpu)) |
7550 | return kvm_rip_read(vcpu); | |
7551 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
7552 | kvm_rip_read(vcpu)); | |
7553 | } | |
7554 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 7555 | |
82b32774 NA |
7556 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
7557 | { | |
7558 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
7559 | } |
7560 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
7561 | ||
94fe45da JK |
7562 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
7563 | { | |
7564 | unsigned long rflags; | |
7565 | ||
7566 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
7567 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 7568 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
7569 | return rflags; |
7570 | } | |
7571 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
7572 | ||
6addfc42 | 7573 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
7574 | { |
7575 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 7576 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 7577 | rflags |= X86_EFLAGS_TF; |
94fe45da | 7578 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
7579 | } |
7580 | ||
7581 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
7582 | { | |
7583 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 7584 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
7585 | } |
7586 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
7587 | ||
56028d08 GN |
7588 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
7589 | { | |
7590 | int r; | |
7591 | ||
fb67e14f | 7592 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 7593 | work->wakeup_all) |
56028d08 GN |
7594 | return; |
7595 | ||
7596 | r = kvm_mmu_reload(vcpu); | |
7597 | if (unlikely(r)) | |
7598 | return; | |
7599 | ||
fb67e14f XG |
7600 | if (!vcpu->arch.mmu.direct_map && |
7601 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
7602 | return; | |
7603 | ||
56028d08 GN |
7604 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
7605 | } | |
7606 | ||
af585b92 GN |
7607 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
7608 | { | |
7609 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
7610 | } | |
7611 | ||
7612 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
7613 | { | |
7614 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
7615 | } | |
7616 | ||
7617 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7618 | { | |
7619 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7620 | ||
7621 | while (vcpu->arch.apf.gfns[key] != ~0) | |
7622 | key = kvm_async_pf_next_probe(key); | |
7623 | ||
7624 | vcpu->arch.apf.gfns[key] = gfn; | |
7625 | } | |
7626 | ||
7627 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7628 | { | |
7629 | int i; | |
7630 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7631 | ||
7632 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
7633 | (vcpu->arch.apf.gfns[key] != gfn && |
7634 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
7635 | key = kvm_async_pf_next_probe(key); |
7636 | ||
7637 | return key; | |
7638 | } | |
7639 | ||
7640 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7641 | { | |
7642 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
7643 | } | |
7644 | ||
7645 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7646 | { | |
7647 | u32 i, j, k; | |
7648 | ||
7649 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
7650 | while (true) { | |
7651 | vcpu->arch.apf.gfns[i] = ~0; | |
7652 | do { | |
7653 | j = kvm_async_pf_next_probe(j); | |
7654 | if (vcpu->arch.apf.gfns[j] == ~0) | |
7655 | return; | |
7656 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
7657 | /* | |
7658 | * k lies cyclically in ]i,j] | |
7659 | * | i.k.j | | |
7660 | * |....j i.k.| or |.k..j i...| | |
7661 | */ | |
7662 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
7663 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
7664 | i = j; | |
7665 | } | |
7666 | } | |
7667 | ||
7c90705b GN |
7668 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
7669 | { | |
7670 | ||
7671 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
7672 | sizeof(val)); | |
7673 | } | |
7674 | ||
af585b92 GN |
7675 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
7676 | struct kvm_async_pf *work) | |
7677 | { | |
6389ee94 AK |
7678 | struct x86_exception fault; |
7679 | ||
7c90705b | 7680 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 7681 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
7682 | |
7683 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
7684 | (vcpu->arch.apf.send_user_only && |
7685 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
7686 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
7687 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
7688 | fault.vector = PF_VECTOR; |
7689 | fault.error_code_valid = true; | |
7690 | fault.error_code = 0; | |
7691 | fault.nested_page_fault = false; | |
7692 | fault.address = work->arch.token; | |
7693 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7694 | } |
af585b92 GN |
7695 | } |
7696 | ||
7697 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
7698 | struct kvm_async_pf *work) | |
7699 | { | |
6389ee94 AK |
7700 | struct x86_exception fault; |
7701 | ||
7c90705b | 7702 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
f2e10669 | 7703 | if (work->wakeup_all) |
7c90705b GN |
7704 | work->arch.token = ~0; /* broadcast wakeup */ |
7705 | else | |
7706 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
7707 | ||
7708 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
7709 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
7710 | fault.vector = PF_VECTOR; |
7711 | fault.error_code_valid = true; | |
7712 | fault.error_code = 0; | |
7713 | fault.nested_page_fault = false; | |
7714 | fault.address = work->arch.token; | |
7715 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 7716 | } |
e6d53e3b | 7717 | vcpu->arch.apf.halted = false; |
a4fa1635 | 7718 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
7719 | } |
7720 | ||
7721 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
7722 | { | |
7723 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
7724 | return true; | |
7725 | else | |
7726 | return !kvm_event_needs_reinjection(vcpu) && | |
7727 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
7728 | } |
7729 | ||
e0f0bbc5 AW |
7730 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
7731 | { | |
7732 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
7733 | } | |
7734 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
7735 | ||
7736 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
7737 | { | |
7738 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
7739 | } | |
7740 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
7741 | ||
7742 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
7743 | { | |
7744 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
7745 | } | |
7746 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
7747 | ||
229456fc MT |
7748 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
7749 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
7750 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
7751 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
7752 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 7753 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 7754 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 7755 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 7756 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 7757 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 7758 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 7759 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 7760 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 7761 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |