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KVM: Implement bare minimum of HYPER-V MSRs
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
aec51dc4
AK		 42#include <trace/events/kvm.h>
43#undef TRACE_INCLUDE_FILE
229456fc
MT		 44#define CREATE_TRACE_POINTS
45#include "trace.h"
043405e1 46
24f1e32c 47#include <asm/debugreg.h>
043405e1 48#include <asm/uaccess.h>
d825ed0a 49#include <asm/msr.h>
a5f61300 50#include <asm/desc.h>
0bed3b56 51#include <asm/mtrr.h>
890ca9ae 52#include <asm/mce.h>
043405e1 53
313a3dc7 54#define MAX_IO_MSRS 256
a03490ed
CO		 55#define CR0_RESERVED_BITS \
56 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
57 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
58 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
59#define CR4_RESERVED_BITS \
60 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
61 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
62 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
63 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
64
65#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 66
67#define KVM_MAX_MCE_BANKS 32
68#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
75static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
76#else
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
18863bdd
AK		 93#define KVM_NR_SHARED_MSRS 16
94
95struct kvm_shared_msrs_global {
96 int nr;
2bf78fa7 97 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 98};
99
100struct kvm_shared_msrs {
101 struct user_return_notifier urn;
102 bool registered;
2bf78fa7
SY		 103 struct kvm_shared_msr_values {
104 u64 host;
105 u64 curr;
106 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
110static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
111
417bc304 112struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 113 { "pf_fixed", VCPU_STAT(pf_fixed) },
114 { "pf_guest", VCPU_STAT(pf_guest) },
115 { "tlb_flush", VCPU_STAT(tlb_flush) },
116 { "invlpg", VCPU_STAT(invlpg) },
117 { "exits", VCPU_STAT(exits) },
118 { "io_exits", VCPU_STAT(io_exits) },
119 { "mmio_exits", VCPU_STAT(mmio_exits) },
120 { "signal_exits", VCPU_STAT(signal_exits) },
121 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 122 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 123 { "halt_exits", VCPU_STAT(halt_exits) },
124 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 125 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 126 { "request_irq", VCPU_STAT(request_irq_exits) },
127 { "irq_exits", VCPU_STAT(irq_exits) },
128 { "host_state_reload", VCPU_STAT(host_state_reload) },
129 { "efer_reload", VCPU_STAT(efer_reload) },
130 { "fpu_reload", VCPU_STAT(fpu_reload) },
131 { "insn_emulation", VCPU_STAT(insn_emulation) },
132 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 133 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 134 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 135 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
136 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
137 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
138 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
139 { "mmu_flooded", VM_STAT(mmu_flooded) },
140 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 141 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 142 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 143 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 144 { "largepages", VM_STAT(lpages) },
417bc304
HB		 145 { NULL }
146};
147
18863bdd
AK		 148static void kvm_on_user_return(struct user_return_notifier *urn)
149{
150 unsigned slot;
18863bdd
AK		 151 struct kvm_shared_msrs *locals
152 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 153 struct kvm_shared_msr_values *values;
18863bdd
AK		 154
155 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 156 values = &locals->values[slot];
157 if (values->host != values->curr) {
158 wrmsrl(shared_msrs_global.msrs[slot], values->host);
159 values->curr = values->host;
18863bdd
AK		 160 }
161 }
162 locals->registered = false;
163 user_return_notifier_unregister(urn);
164}
165
2bf78fa7 166static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 167{
2bf78fa7 168 struct kvm_shared_msrs *smsr;
18863bdd
AK		 169 u64 value;
170
2bf78fa7
SY		 171 smsr = &__get_cpu_var(shared_msrs);
172 /* only read, and nobody should modify it at this time,
173 * so don't need lock */
174 if (slot >= shared_msrs_global.nr) {
175 printk(KERN_ERR "kvm: invalid MSR slot!");
176 return;
177 }
178 rdmsrl_safe(msr, &value);
179 smsr->values[slot].host = value;
180 smsr->values[slot].curr = value;
181}
182
183void kvm_define_shared_msr(unsigned slot, u32 msr)
184{
18863bdd
AK		 185 if (slot >= shared_msrs_global.nr)
186 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 187 shared_msrs_global.msrs[slot] = msr;
188 /* we need ensured the shared_msr_global have been updated */
189 smp_wmb();
18863bdd
AK		 190}
191EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
192
193static void kvm_shared_msr_cpu_online(void)
194{
195 unsigned i;
18863bdd
AK		 196
197 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 198 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 199}
200
d5696725 201void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 202{
203 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
204
2bf78fa7 205 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 206 return;
2bf78fa7
SY		 207 smsr->values[slot].curr = value;
208 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 209 if (!smsr->registered) {
210 smsr->urn.on_user_return = kvm_on_user_return;
211 user_return_notifier_register(&smsr->urn);
212 smsr->registered = true;
213 }
214}
215EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
216
3548bab5
AK		 217static void drop_user_return_notifiers(void *ignore)
218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
221 if (smsr->registered)
222 kvm_on_user_return(&smsr->urn);
223}
224
5fb76f9b
CO		 225unsigned long segment_base(u16 selector)
226{
227 struct descriptor_table gdt;
a5f61300 228 struct desc_struct *d;
5fb76f9b
CO		 229 unsigned long table_base;
230 unsigned long v;
231
232 if (selector == 0)
233 return 0;
234
b792c344 235 kvm_get_gdt(&gdt);
5fb76f9b
CO		 236 table_base = gdt.base;
237
238 if (selector & 4) { /* from ldt */
b792c344 239 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 240
5fb76f9b
CO		 241 table_base = segment_base(ldt_selector);
242 }
a5f61300 243 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 244 v = get_desc_base(d);
5fb76f9b 245#ifdef CONFIG_X86_64
a5f61300
AK		 246 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
247 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 248#endif
249 return v;
250}
251EXPORT_SYMBOL_GPL(segment_base);
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
255 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 256 return vcpu->arch.apic_base;
6866b83e 257 else
ad312c7c 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
262void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
263{
264 /* TODO: reserve bits check */
265 if (irqchip_in_kernel(vcpu->kvm))
266 kvm_lapic_set_base(vcpu, data);
267 else
ad312c7c 268 vcpu->arch.apic_base = data;
6866b83e
CO		 269}
270EXPORT_SYMBOL_GPL(kvm_set_apic_base);
271
3fd28fce
ED		 272#define EXCPT_BENIGN 0
273#define EXCPT_CONTRIBUTORY 1
274#define EXCPT_PF 2
275
276static int exception_class(int vector)
277{
278 switch (vector) {
279 case PF_VECTOR:
280 return EXCPT_PF;
281 case DE_VECTOR:
282 case TS_VECTOR:
283 case NP_VECTOR:
284 case SS_VECTOR:
285 case GP_VECTOR:
286 return EXCPT_CONTRIBUTORY;
287 default:
288 break;
289 }
290 return EXCPT_BENIGN;
291}
292
293static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
294 unsigned nr, bool has_error, u32 error_code)
295{
296 u32 prev_nr;
297 int class1, class2;
298
299 if (!vcpu->arch.exception.pending) {
300 queue:
301 vcpu->arch.exception.pending = true;
302 vcpu->arch.exception.has_error_code = has_error;
303 vcpu->arch.exception.nr = nr;
304 vcpu->arch.exception.error_code = error_code;
305 return;
306 }
307
308 /* to check exception */
309 prev_nr = vcpu->arch.exception.nr;
310 if (prev_nr == DF_VECTOR) {
311 /* triple fault -> shutdown */
312 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
313 return;
314 }
315 class1 = exception_class(prev_nr);
316 class2 = exception_class(nr);
317 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
318 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
319 /* generate double fault per SDM Table 5-5 */
320 vcpu->arch.exception.pending = true;
321 vcpu->arch.exception.has_error_code = true;
322 vcpu->arch.exception.nr = DF_VECTOR;
323 vcpu->arch.exception.error_code = 0;
324 } else
325 /* replace previous exception with a new one in a hope
326 that instruction re-execution will regenerate lost
327 exception */
328 goto queue;
329}
330
298101da
AK		 331void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
3fd28fce 333 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 334}
335EXPORT_SYMBOL_GPL(kvm_queue_exception);
336
c3c91fee
AK		 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
338 u32 error_code)
339{
340 ++vcpu->stat.pf_guest;
ad312c7c 341 vcpu->arch.cr2 = addr;
c3c91fee
AK		 342 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
343}
344
3419ffc8
SY		 345void kvm_inject_nmi(struct kvm_vcpu *vcpu)
346{
347 vcpu->arch.nmi_pending = 1;
348}
349EXPORT_SYMBOL_GPL(kvm_inject_nmi);
350
298101da
AK		 351void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
352{
3fd28fce 353 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 354}
355EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
356
0a79b009
AK		 357/*
358 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
359 * a #GP and return false.
360 */
361bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 362{
0a79b009
AK		 363 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
364 return true;
365 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
366 return false;
298101da 367}
0a79b009 368EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 369
a03490ed
CO		 370/*
371 * Load the pae pdptrs. Return true is they are all valid.
372 */
373int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
374{
375 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
376 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
377 int i;
378 int ret;
ad312c7c 379 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 380
a03490ed
CO		 381 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
382 offset * sizeof(u64), sizeof(pdpte));
383 if (ret < 0) {
384 ret = 0;
385 goto out;
386 }
387 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 388 if (is_present_gpte(pdpte[i]) &&
20c466b5 389 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 390 ret = 0;
391 goto out;
392 }
393 }
394 ret = 1;
395
ad312c7c 396 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 397 __set_bit(VCPU_EXREG_PDPTR,
398 (unsigned long *)&vcpu->arch.regs_avail);
399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 401out:
a03490ed
CO		 402
403 return ret;
404}
cc4b6871 405EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 406
d835dfec
AK		 407static bool pdptrs_changed(struct kvm_vcpu *vcpu)
408{
ad312c7c 409 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 410 bool changed = true;
411 int r;
412
413 if (is_long_mode(vcpu) || !is_pae(vcpu))
414 return false;
415
6de4f3ad
AK		 416 if (!test_bit(VCPU_EXREG_PDPTR,
417 (unsigned long *)&vcpu->arch.regs_avail))
418 return true;
419
ad312c7c 420 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 421 if (r < 0)
422 goto out;
ad312c7c 423 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 424out:
d835dfec
AK		 425
426 return changed;
427}
428
2d3ad1f4 429void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 430{
f9a48e6a
AK		 431 cr0 |= X86_CR0_ET;
432
a03490ed
CO		 433 if (cr0 & CR0_RESERVED_BITS) {
434 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
4d4ec087 435 cr0, kvm_read_cr0(vcpu));
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
439
440 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
441 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 442 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 443 return;
444 }
445
446 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
447 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
448 "and a clear PE flag\n");
c1a5d4f9 449 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 450 return;
451 }
452
453 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
454#ifdef CONFIG_X86_64
ad312c7c 455 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 456 int cs_db, cs_l;
457
458 if (!is_pae(vcpu)) {
459 printk(KERN_DEBUG "set_cr0: #GP, start paging "
460 "in long mode while PAE is disabled\n");
c1a5d4f9 461 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 462 return;
463 }
464 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
465 if (cs_l) {
466 printk(KERN_DEBUG "set_cr0: #GP, start paging "
467 "in long mode while CS.L == 1\n");
c1a5d4f9 468 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 469 return;
470
471 }
472 } else
473#endif
ad312c7c 474 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 475 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
476 "reserved bits\n");
c1a5d4f9 477 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 478 return;
479 }
480
481 }
482
483 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 484 vcpu->arch.cr0 = cr0;
a03490ed 485
a03490ed 486 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 487 return;
488}
2d3ad1f4 489EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 490
2d3ad1f4 491void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 492{
4d4ec087 493 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 494}
2d3ad1f4 495EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 496
2d3ad1f4 497void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 498{
fc78f519 499 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 500 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
501
a03490ed
CO		 502 if (cr4 & CR4_RESERVED_BITS) {
503 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 504 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 505 return;
506 }
507
508 if (is_long_mode(vcpu)) {
509 if (!(cr4 & X86_CR4_PAE)) {
510 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
511 "in long mode\n");
c1a5d4f9 512 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 513 return;
514 }
a2edf57f
AK		 515 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
516 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 517 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 518 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 519 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 520 return;
521 }
522
523 if (cr4 & X86_CR4_VMXE) {
524 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 525 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 526 return;
527 }
528 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 529 vcpu->arch.cr4 = cr4;
5a41accd 530 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 531 kvm_mmu_reset_context(vcpu);
a03490ed 532}
2d3ad1f4 533EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 534
2d3ad1f4 535void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 536{
ad312c7c 537 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 538 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 539 kvm_mmu_flush_tlb(vcpu);
540 return;
541 }
542
a03490ed
CO		 543 if (is_long_mode(vcpu)) {
544 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
545 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 546 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 547 return;
548 }
549 } else {
550 if (is_pae(vcpu)) {
551 if (cr3 & CR3_PAE_RESERVED_BITS) {
552 printk(KERN_DEBUG
553 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 554 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 555 return;
556 }
557 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
558 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
559 "reserved bits\n");
c1a5d4f9 560 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 561 return;
562 }
563 }
564 /*
565 * We don't check reserved bits in nonpae mode, because
566 * this isn't enforced, and VMware depends on this.
567 */
568 }
569
a03490ed
CO		 570 /*
571 * Does the new cr3 value map to physical memory? (Note, we
572 * catch an invalid cr3 even in real-mode, because it would
573 * cause trouble later on when we turn on paging anyway.)
574 *
575 * A real CPU would silently accept an invalid cr3 and would
576 * attempt to use it - with largely undefined (and often hard
577 * to debug) behavior on the guest side.
578 */
579 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 580 kvm_inject_gp(vcpu, 0);
a03490ed 581 else {
ad312c7c
ZX		 582 vcpu->arch.cr3 = cr3;
583 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 584 }
a03490ed 585}
2d3ad1f4 586EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 587
2d3ad1f4 588void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 589{
590 if (cr8 & CR8_RESERVED_BITS) {
591 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 592 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 593 return;
594 }
595 if (irqchip_in_kernel(vcpu->kvm))
596 kvm_lapic_set_tpr(vcpu, cr8);
597 else
ad312c7c 598 vcpu->arch.cr8 = cr8;
a03490ed 599}
2d3ad1f4 600EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 601
2d3ad1f4 602unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 603{
604 if (irqchip_in_kernel(vcpu->kvm))
605 return kvm_lapic_get_cr8(vcpu);
606 else
ad312c7c 607 return vcpu->arch.cr8;
a03490ed 608}
2d3ad1f4 609EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 610
d8017474
AG		 611static inline u32 bit(int bitno)
612{
613 return 1 << (bitno & 31);
614}
615
043405e1
CO		 616/*
617 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
618 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
619 *
620 * This list is modified at module load time to reflect the
e3267cbb
GC		 621 * capabilities of the host cpu. This capabilities test skips MSRs that are
622 * kvm-specific. Those are put in the beginning of the list.
043405e1 623 */
e3267cbb 624
55cd8e5a 625#define KVM_SAVE_MSRS_BEGIN 4
043405e1 626static u32 msrs_to_save[] = {
e3267cbb 627 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 628 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
043405e1
CO		 629 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
630 MSR_K6_STAR,
631#ifdef CONFIG_X86_64
632 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
633#endif
e3267cbb 634 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 635};
636
637static unsigned num_msrs_to_save;
638
639static u32 emulated_msrs[] = {
640 MSR_IA32_MISC_ENABLE,
641};
642
15c4a640
CO		 643static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
644{
f2b4b7dd 645 if (efer & efer_reserved_bits) {
15c4a640
CO		 646 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
647 efer);
c1a5d4f9 648 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 649 return;
650 }
651
652 if (is_paging(vcpu)
ad312c7c 653 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 654 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 655 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 656 return;
657 }
658
1b2fd70c
AG		 659 if (efer & EFER_FFXSR) {
660 struct kvm_cpuid_entry2 *feat;
661
662 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
663 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
664 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
665 kvm_inject_gp(vcpu, 0);
666 return;
667 }
668 }
669
d8017474
AG		 670 if (efer & EFER_SVME) {
671 struct kvm_cpuid_entry2 *feat;
672
673 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
674 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
675 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
676 kvm_inject_gp(vcpu, 0);
677 return;
678 }
679 }
680
15c4a640
CO		 681 kvm_x86_ops->set_efer(vcpu, efer);
682
683 efer &= ~EFER_LMA;
ad312c7c 684 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 685
ad312c7c 686 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 687
688 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
689 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 690}
691
f2b4b7dd
JR		 692void kvm_enable_efer_bits(u64 mask)
693{
694 efer_reserved_bits &= ~mask;
695}
696EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
697
698
15c4a640
CO		 699/*
700 * Writes msr value into into the appropriate "register".
701 * Returns 0 on success, non-0 otherwise.
702 * Assumes vcpu_load() was already called.
703 */
704int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
705{
706 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
707}
708
313a3dc7
CO		 709/*
710 * Adapt set_msr() to msr_io()'s calling convention
711 */
712static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
713{
714 return kvm_set_msr(vcpu, index, *data);
715}
716
18068523
GOC		 717static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
718{
719 static int version;
50d0a0f9 720 struct pvclock_wall_clock wc;
923de3cf 721 struct timespec boot;
18068523
GOC		 722
723 if (!wall_clock)
724 return;
725
726 version++;
727
18068523
GOC		 728 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
729
50d0a0f9
GH		 730 /*
731 * The guest calculates current wall clock time by adding
732 * system time (updated by kvm_write_guest_time below) to the
733 * wall clock specified here. guest system time equals host
734 * system time for us, thus we must fill in host boot time here.
735 */
923de3cf 736 getboottime(&boot);
50d0a0f9
GH		 737
738 wc.sec = boot.tv_sec;
739 wc.nsec = boot.tv_nsec;
740 wc.version = version;
18068523
GOC		 741
742 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
743
744 version++;
745 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 746}
747
50d0a0f9
GH		 748static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
749{
750 uint32_t quotient, remainder;
751
752 /* Don't try to replace with do_div(), this one calculates
753 * "(dividend << 32) / divisor" */
754 __asm__ ( "divl %4"
755 : "=a" (quotient), "=d" (remainder)
756 : "0" (0), "1" (dividend), "r" (divisor) );
757 return quotient;
758}
759
760static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
761{
762 uint64_t nsecs = 1000000000LL;
763 int32_t shift = 0;
764 uint64_t tps64;
765 uint32_t tps32;
766
767 tps64 = tsc_khz * 1000LL;
768 while (tps64 > nsecs*2) {
769 tps64 >>= 1;
770 shift--;
771 }
772
773 tps32 = (uint32_t)tps64;
774 while (tps32 <= (uint32_t)nsecs) {
775 tps32 <<= 1;
776 shift++;
777 }
778
779 hv_clock->tsc_shift = shift;
780 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
781
782 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 783 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 784 hv_clock->tsc_to_system_mul);
785}
786
c8076604
GH		 787static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
788
18068523
GOC		 789static void kvm_write_guest_time(struct kvm_vcpu *v)
790{
791 struct timespec ts;
792 unsigned long flags;
793 struct kvm_vcpu_arch *vcpu = &v->arch;
794 void *shared_kaddr;
463656c0 795 unsigned long this_tsc_khz;
18068523
GOC		 796
797 if ((!vcpu->time_page))
798 return;
799
463656c0
AK		 800 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
801 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
802 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
803 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 804 }
463656c0 805 put_cpu_var(cpu_tsc_khz);
50d0a0f9 806
18068523
GOC		 807 /* Keep irq disabled to prevent changes to the clock */
808 local_irq_save(flags);
af24a4e4 809 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 810 ktime_get_ts(&ts);
923de3cf 811 monotonic_to_bootbased(&ts);
18068523
GOC		 812 local_irq_restore(flags);
813
814 /* With all the info we got, fill in the values */
815
816 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 817 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
818
18068523
GOC		 819 /*
820 * The interface expects us to write an even number signaling that the
821 * update is finished. Since the guest won't see the intermediate
50d0a0f9 822 * state, we just increase by 2 at the end.
18068523 823 */
50d0a0f9 824 vcpu->hv_clock.version += 2;
18068523
GOC		 825
826 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
827
828 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 829 sizeof(vcpu->hv_clock));
18068523
GOC		 830
831 kunmap_atomic(shared_kaddr, KM_USER0);
832
833 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
834}
835
c8076604
GH		 836static int kvm_request_guest_time_update(struct kvm_vcpu *v)
837{
838 struct kvm_vcpu_arch *vcpu = &v->arch;
839
840 if (!vcpu->time_page)
841 return 0;
842 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
843 return 1;
844}
845
9ba075a6
AK		 846static bool msr_mtrr_valid(unsigned msr)
847{
848 switch (msr) {
849 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
850 case MSR_MTRRfix64K_00000:
851 case MSR_MTRRfix16K_80000:
852 case MSR_MTRRfix16K_A0000:
853 case MSR_MTRRfix4K_C0000:
854 case MSR_MTRRfix4K_C8000:
855 case MSR_MTRRfix4K_D0000:
856 case MSR_MTRRfix4K_D8000:
857 case MSR_MTRRfix4K_E0000:
858 case MSR_MTRRfix4K_E8000:
859 case MSR_MTRRfix4K_F0000:
860 case MSR_MTRRfix4K_F8000:
861 case MSR_MTRRdefType:
862 case MSR_IA32_CR_PAT:
863 return true;
864 case 0x2f8:
865 return true;
866 }
867 return false;
868}
869
d6289b93
MT		 870static bool valid_pat_type(unsigned t)
871{
872 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
873}
874
875static bool valid_mtrr_type(unsigned t)
876{
877 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
878}
879
880static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
881{
882 int i;
883
884 if (!msr_mtrr_valid(msr))
885 return false;
886
887 if (msr == MSR_IA32_CR_PAT) {
888 for (i = 0; i < 8; i++)
889 if (!valid_pat_type((data >> (i * 8)) & 0xff))
890 return false;
891 return true;
892 } else if (msr == MSR_MTRRdefType) {
893 if (data & ~0xcff)
894 return false;
895 return valid_mtrr_type(data & 0xff);
896 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
897 for (i = 0; i < 8 ; i++)
898 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
899 return false;
900 return true;
901 }
902
903 /* variable MTRRs */
904 return valid_mtrr_type(data & 0xff);
905}
906
9ba075a6
AK		 907static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
908{
0bed3b56
SY		 909 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
910
d6289b93 911 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 912 return 1;
913
0bed3b56
SY		 914 if (msr == MSR_MTRRdefType) {
915 vcpu->arch.mtrr_state.def_type = data;
916 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
917 } else if (msr == MSR_MTRRfix64K_00000)
918 p[0] = data;
919 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
920 p[1 + msr - MSR_MTRRfix16K_80000] = data;
921 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
922 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
923 else if (msr == MSR_IA32_CR_PAT)
924 vcpu->arch.pat = data;
925 else { /* Variable MTRRs */
926 int idx, is_mtrr_mask;
927 u64 *pt;
928
929 idx = (msr - 0x200) / 2;
930 is_mtrr_mask = msr - 0x200 - 2 * idx;
931 if (!is_mtrr_mask)
932 pt =
933 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
934 else
935 pt =
936 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
937 *pt = data;
938 }
939
940 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 941 return 0;
942}
15c4a640 943
890ca9ae 944static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 945{
890ca9ae
HY		 946 u64 mcg_cap = vcpu->arch.mcg_cap;
947 unsigned bank_num = mcg_cap & 0xff;
948
15c4a640 949 switch (msr) {
15c4a640 950 case MSR_IA32_MCG_STATUS:
890ca9ae 951 vcpu->arch.mcg_status = data;
15c4a640 952 break;
c7ac679c 953 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 954 if (!(mcg_cap & MCG_CTL_P))
955 return 1;
956 if (data != 0 && data != ~(u64)0)
957 return -1;
958 vcpu->arch.mcg_ctl = data;
959 break;
960 default:
961 if (msr >= MSR_IA32_MC0_CTL &&
962 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
963 u32 offset = msr - MSR_IA32_MC0_CTL;
964 /* only 0 or all 1s can be written to IA32_MCi_CTL */
965 if ((offset & 0x3) == 0 &&
966 data != 0 && data != ~(u64)0)
967 return -1;
968 vcpu->arch.mce_banks[offset] = data;
969 break;
970 }
971 return 1;
972 }
973 return 0;
974}
975
ffde22ac
ES		 976static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
977{
978 struct kvm *kvm = vcpu->kvm;
979 int lm = is_long_mode(vcpu);
980 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
981 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
982 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
983 : kvm->arch.xen_hvm_config.blob_size_32;
984 u32 page_num = data & ~PAGE_MASK;
985 u64 page_addr = data & PAGE_MASK;
986 u8 *page;
987 int r;
988
989 r = -E2BIG;
990 if (page_num >= blob_size)
991 goto out;
992 r = -ENOMEM;
993 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
994 if (!page)
995 goto out;
996 r = -EFAULT;
997 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
998 goto out_free;
999 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1000 goto out_free;
1001 r = 0;
1002out_free:
1003 kfree(page);
1004out:
1005 return r;
1006}
1007
55cd8e5a
GN		 1008static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1009{
1010 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1011}
1012
1013static bool kvm_hv_msr_partition_wide(u32 msr)
1014{
1015 bool r = false;
1016 switch (msr) {
1017 case HV_X64_MSR_GUEST_OS_ID:
1018 case HV_X64_MSR_HYPERCALL:
1019 r = true;
1020 break;
1021 }
1022
1023 return r;
1024}
1025
1026static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1027{
1028 struct kvm *kvm = vcpu->kvm;
1029
1030 switch (msr) {
1031 case HV_X64_MSR_GUEST_OS_ID:
1032 kvm->arch.hv_guest_os_id = data;
1033 /* setting guest os id to zero disables hypercall page */
1034 if (!kvm->arch.hv_guest_os_id)
1035 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1036 break;
1037 case HV_X64_MSR_HYPERCALL: {
1038 u64 gfn;
1039 unsigned long addr;
1040 u8 instructions[4];
1041
1042 /* if guest os id is not set hypercall should remain disabled */
1043 if (!kvm->arch.hv_guest_os_id)
1044 break;
1045 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1046 kvm->arch.hv_hypercall = data;
1047 break;
1048 }
1049 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1050 addr = gfn_to_hva(kvm, gfn);
1051 if (kvm_is_error_hva(addr))
1052 return 1;
1053 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1054 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1055 if (copy_to_user((void __user *)addr, instructions, 4))
1056 return 1;
1057 kvm->arch.hv_hypercall = data;
1058 break;
1059 }
1060 default:
1061 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1062 "data 0x%llx\n", msr, data);
1063 return 1;
1064 }
1065 return 0;
1066}
1067
1068static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1069{
1070 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x data 0x%llx\n",
1071 msr, data);
1072
1073 return 1;
1074}
1075
15c4a640
CO		 1076int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1077{
1078 switch (msr) {
15c4a640
CO		 1079 case MSR_EFER:
1080 set_efer(vcpu, data);
1081 break;
8f1589d9
AP		 1082 case MSR_K7_HWCR:
1083 data &= ~(u64)0x40; /* ignore flush filter disable */
1084 if (data != 0) {
1085 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1086 data);
1087 return 1;
1088 }
15c4a640 1089 break;
f7c6d140
AP		 1090 case MSR_FAM10H_MMIO_CONF_BASE:
1091 if (data != 0) {
1092 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1093 "0x%llx\n", data);
1094 return 1;
1095 }
15c4a640 1096 break;
c323c0e5 1097 case MSR_AMD64_NB_CFG:
c7ac679c 1098 break;
b5e2fec0
AG		 1099 case MSR_IA32_DEBUGCTLMSR:
1100 if (!data) {
1101 /* We support the non-activated case already */
1102 break;
1103 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1104 /* Values other than LBR and BTF are vendor-specific,
1105 thus reserved and should throw a #GP */
1106 return 1;
1107 }
1108 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1109 __func__, data);
1110 break;
15c4a640
CO		 1111 case MSR_IA32_UCODE_REV:
1112 case MSR_IA32_UCODE_WRITE:
61a6bd67 1113 case MSR_VM_HSAVE_PA:
6098ca93 1114 case MSR_AMD64_PATCH_LOADER:
15c4a640 1115 break;
9ba075a6
AK		 1116 case 0x200 ... 0x2ff:
1117 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1118 case MSR_IA32_APICBASE:
1119 kvm_set_apic_base(vcpu, data);
1120 break;
0105d1a5
GN		 1121 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1122 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1123 case MSR_IA32_MISC_ENABLE:
ad312c7c 1124 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1125 break;
18068523
GOC		 1126 case MSR_KVM_WALL_CLOCK:
1127 vcpu->kvm->arch.wall_clock = data;
1128 kvm_write_wall_clock(vcpu->kvm, data);
1129 break;
1130 case MSR_KVM_SYSTEM_TIME: {
1131 if (vcpu->arch.time_page) {
1132 kvm_release_page_dirty(vcpu->arch.time_page);
1133 vcpu->arch.time_page = NULL;
1134 }
1135
1136 vcpu->arch.time = data;
1137
1138 /* we verify if the enable bit is set... */
1139 if (!(data & 1))
1140 break;
1141
1142 /* ...but clean it before doing the actual write */
1143 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1144
18068523
GOC		 1145 vcpu->arch.time_page =
1146 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1147
1148 if (is_error_page(vcpu->arch.time_page)) {
1149 kvm_release_page_clean(vcpu->arch.time_page);
1150 vcpu->arch.time_page = NULL;
1151 }
1152
c8076604 1153 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1154 break;
1155 }
890ca9ae
HY		 1156 case MSR_IA32_MCG_CTL:
1157 case MSR_IA32_MCG_STATUS:
1158 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1159 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1160
1161 /* Performance counters are not protected by a CPUID bit,
1162 * so we should check all of them in the generic path for the sake of
1163 * cross vendor migration.
1164 * Writing a zero into the event select MSRs disables them,
1165 * which we perfectly emulate ;-). Any other value should be at least
1166 * reported, some guests depend on them.
1167 */
1168 case MSR_P6_EVNTSEL0:
1169 case MSR_P6_EVNTSEL1:
1170 case MSR_K7_EVNTSEL0:
1171 case MSR_K7_EVNTSEL1:
1172 case MSR_K7_EVNTSEL2:
1173 case MSR_K7_EVNTSEL3:
1174 if (data != 0)
1175 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1176 "0x%x data 0x%llx\n", msr, data);
1177 break;
1178 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1179 * so we ignore writes to make it happy.
1180 */
1181 case MSR_P6_PERFCTR0:
1182 case MSR_P6_PERFCTR1:
1183 case MSR_K7_PERFCTR0:
1184 case MSR_K7_PERFCTR1:
1185 case MSR_K7_PERFCTR2:
1186 case MSR_K7_PERFCTR3:
1187 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1188 "0x%x data 0x%llx\n", msr, data);
1189 break;
55cd8e5a
GN		 1190 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1191 if (kvm_hv_msr_partition_wide(msr)) {
1192 int r;
1193 mutex_lock(&vcpu->kvm->lock);
1194 r = set_msr_hyperv_pw(vcpu, msr, data);
1195 mutex_unlock(&vcpu->kvm->lock);
1196 return r;
1197 } else
1198 return set_msr_hyperv(vcpu, msr, data);
1199 break;
15c4a640 1200 default:
ffde22ac
ES		 1201 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1202 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1203 if (!ignore_msrs) {
1204 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1205 msr, data);
1206 return 1;
1207 } else {
1208 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1209 msr, data);
1210 break;
1211 }
15c4a640
CO		 1212 }
1213 return 0;
1214}
1215EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1216
1217
1218/*
1219 * Reads an msr value (of 'msr_index') into 'pdata'.
1220 * Returns 0 on success, non-0 otherwise.
1221 * Assumes vcpu_load() was already called.
1222 */
1223int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1224{
1225 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1226}
1227
9ba075a6
AK		 1228static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1229{
0bed3b56
SY		 1230 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1231
9ba075a6
AK		 1232 if (!msr_mtrr_valid(msr))
1233 return 1;
1234
0bed3b56
SY		 1235 if (msr == MSR_MTRRdefType)
1236 *pdata = vcpu->arch.mtrr_state.def_type +
1237 (vcpu->arch.mtrr_state.enabled << 10);
1238 else if (msr == MSR_MTRRfix64K_00000)
1239 *pdata = p[0];
1240 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1241 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1242 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1243 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1244 else if (msr == MSR_IA32_CR_PAT)
1245 *pdata = vcpu->arch.pat;
1246 else { /* Variable MTRRs */
1247 int idx, is_mtrr_mask;
1248 u64 *pt;
1249
1250 idx = (msr - 0x200) / 2;
1251 is_mtrr_mask = msr - 0x200 - 2 * idx;
1252 if (!is_mtrr_mask)
1253 pt =
1254 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1255 else
1256 pt =
1257 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1258 *pdata = *pt;
1259 }
1260
9ba075a6
AK		 1261 return 0;
1262}
1263
890ca9ae 1264static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1265{
1266 u64 data;
890ca9ae
HY		 1267 u64 mcg_cap = vcpu->arch.mcg_cap;
1268 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1269
1270 switch (msr) {
15c4a640
CO		 1271 case MSR_IA32_P5_MC_ADDR:
1272 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1273 data = 0;
1274 break;
15c4a640 1275 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1276 data = vcpu->arch.mcg_cap;
1277 break;
c7ac679c 1278 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1279 if (!(mcg_cap & MCG_CTL_P))
1280 return 1;
1281 data = vcpu->arch.mcg_ctl;
1282 break;
1283 case MSR_IA32_MCG_STATUS:
1284 data = vcpu->arch.mcg_status;
1285 break;
1286 default:
1287 if (msr >= MSR_IA32_MC0_CTL &&
1288 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1289 u32 offset = msr - MSR_IA32_MC0_CTL;
1290 data = vcpu->arch.mce_banks[offset];
1291 break;
1292 }
1293 return 1;
1294 }
1295 *pdata = data;
1296 return 0;
1297}
1298
55cd8e5a
GN		 1299static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1300{
1301 u64 data = 0;
1302 struct kvm *kvm = vcpu->kvm;
1303
1304 switch (msr) {
1305 case HV_X64_MSR_GUEST_OS_ID:
1306 data = kvm->arch.hv_guest_os_id;
1307 break;
1308 case HV_X64_MSR_HYPERCALL:
1309 data = kvm->arch.hv_hypercall;
1310 break;
1311 default:
1312 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1313 return 1;
1314 }
1315
1316 *pdata = data;
1317 return 0;
1318}
1319
1320static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1321{
1322 u64 data = 0;
1323
1324 switch (msr) {
1325 case HV_X64_MSR_VP_INDEX: {
1326 int r;
1327 struct kvm_vcpu *v;
1328 kvm_for_each_vcpu(r, v, vcpu->kvm)
1329 if (v == vcpu)
1330 data = r;
1331 break;
1332 }
1333 default:
1334 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1335 return 1;
1336 }
1337 *pdata = data;
1338 return 0;
1339}
1340
890ca9ae
HY		 1341int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1342{
1343 u64 data;
1344
1345 switch (msr) {
890ca9ae 1346 case MSR_IA32_PLATFORM_ID:
15c4a640 1347 case MSR_IA32_UCODE_REV:
15c4a640 1348 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1349 case MSR_IA32_DEBUGCTLMSR:
1350 case MSR_IA32_LASTBRANCHFROMIP:
1351 case MSR_IA32_LASTBRANCHTOIP:
1352 case MSR_IA32_LASTINTFROMIP:
1353 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1354 case MSR_K8_SYSCFG:
1355 case MSR_K7_HWCR:
61a6bd67 1356 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1357 case MSR_P6_PERFCTR0:
1358 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1359 case MSR_P6_EVNTSEL0:
1360 case MSR_P6_EVNTSEL1:
9e699624 1361 case MSR_K7_EVNTSEL0:
1f3ee616 1362 case MSR_K7_PERFCTR0:
1fdbd48c 1363 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1364 case MSR_AMD64_NB_CFG:
f7c6d140 1365 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1366 data = 0;
1367 break;
9ba075a6
AK		 1368 case MSR_MTRRcap:
1369 data = 0x500 | KVM_NR_VAR_MTRR;
1370 break;
1371 case 0x200 ... 0x2ff:
1372 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1373 case 0xcd: /* fsb frequency */
1374 data = 3;
1375 break;
1376 case MSR_IA32_APICBASE:
1377 data = kvm_get_apic_base(vcpu);
1378 break;
0105d1a5
GN		 1379 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1380 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1381 break;
15c4a640 1382 case MSR_IA32_MISC_ENABLE:
ad312c7c 1383 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1384 break;
847f0ad8
AG		 1385 case MSR_IA32_PERF_STATUS:
1386 /* TSC increment by tick */
1387 data = 1000ULL;
1388 /* CPU multiplier */
1389 data |= (((uint64_t)4ULL) << 40);
1390 break;
15c4a640 1391 case MSR_EFER:
ad312c7c 1392 data = vcpu->arch.shadow_efer;
15c4a640 1393 break;
18068523
GOC		 1394 case MSR_KVM_WALL_CLOCK:
1395 data = vcpu->kvm->arch.wall_clock;
1396 break;
1397 case MSR_KVM_SYSTEM_TIME:
1398 data = vcpu->arch.time;
1399 break;
890ca9ae
HY		 1400 case MSR_IA32_P5_MC_ADDR:
1401 case MSR_IA32_P5_MC_TYPE:
1402 case MSR_IA32_MCG_CAP:
1403 case MSR_IA32_MCG_CTL:
1404 case MSR_IA32_MCG_STATUS:
1405 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1406 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1407 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1408 if (kvm_hv_msr_partition_wide(msr)) {
1409 int r;
1410 mutex_lock(&vcpu->kvm->lock);
1411 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1412 mutex_unlock(&vcpu->kvm->lock);
1413 return r;
1414 } else
1415 return get_msr_hyperv(vcpu, msr, pdata);
1416 break;
15c4a640 1417 default:
ed85c068
AP		 1418 if (!ignore_msrs) {
1419 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1420 return 1;
1421 } else {
1422 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1423 data = 0;
1424 }
1425 break;
15c4a640
CO		 1426 }
1427 *pdata = data;
1428 return 0;
1429}
1430EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1431
313a3dc7
CO		 1432/*
1433 * Read or write a bunch of msrs. All parameters are kernel addresses.
1434 *
1435 * @return number of msrs set successfully.
1436 */
1437static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1438 struct kvm_msr_entry *entries,
1439 int (*do_msr)(struct kvm_vcpu *vcpu,
1440 unsigned index, u64 *data))
1441{
f656ce01 1442 int i, idx;
313a3dc7
CO		 1443
1444 vcpu_load(vcpu);
1445
f656ce01 1446 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1447 for (i = 0; i < msrs->nmsrs; ++i)
1448 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1449 break;
f656ce01 1450 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1451
1452 vcpu_put(vcpu);
1453
1454 return i;
1455}
1456
1457/*
1458 * Read or write a bunch of msrs. Parameters are user addresses.
1459 *
1460 * @return number of msrs set successfully.
1461 */
1462static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1463 int (*do_msr)(struct kvm_vcpu *vcpu,
1464 unsigned index, u64 *data),
1465 int writeback)
1466{
1467 struct kvm_msrs msrs;
1468 struct kvm_msr_entry *entries;
1469 int r, n;
1470 unsigned size;
1471
1472 r = -EFAULT;
1473 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1474 goto out;
1475
1476 r = -E2BIG;
1477 if (msrs.nmsrs >= MAX_IO_MSRS)
1478 goto out;
1479
1480 r = -ENOMEM;
1481 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1482 entries = vmalloc(size);
1483 if (!entries)
1484 goto out;
1485
1486 r = -EFAULT;
1487 if (copy_from_user(entries, user_msrs->entries, size))
1488 goto out_free;
1489
1490 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1491 if (r < 0)
1492 goto out_free;
1493
1494 r = -EFAULT;
1495 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1496 goto out_free;
1497
1498 r = n;
1499
1500out_free:
1501 vfree(entries);
1502out:
1503 return r;
1504}
1505
018d00d2
ZX		 1506int kvm_dev_ioctl_check_extension(long ext)
1507{
1508 int r;
1509
1510 switch (ext) {
1511 case KVM_CAP_IRQCHIP:
1512 case KVM_CAP_HLT:
1513 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1514 case KVM_CAP_SET_TSS_ADDR:
07716717 1515 case KVM_CAP_EXT_CPUID:
c8076604 1516 case KVM_CAP_CLOCKSOURCE:
7837699f 1517 case KVM_CAP_PIT:
a28e4f5a 1518 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1519 case KVM_CAP_MP_STATE:
ed848624 1520 case KVM_CAP_SYNC_MMU:
52d939a0 1521 case KVM_CAP_REINJECT_CONTROL:
4925663a 1522 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1523 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1524 case KVM_CAP_IRQFD:
d34e6b17 1525 case KVM_CAP_IOEVENTFD:
c5ff41ce 1526 case KVM_CAP_PIT2:
e9f42757 1527 case KVM_CAP_PIT_STATE2:
b927a3ce 1528 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1529 case KVM_CAP_XEN_HVM:
afbcf7ab 1530 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1531 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1532 case KVM_CAP_HYPERV:
018d00d2
ZX		 1533 r = 1;
1534 break;
542472b5
LV		 1535 case KVM_CAP_COALESCED_MMIO:
1536 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1537 break;
774ead3a
AK		 1538 case KVM_CAP_VAPIC:
1539 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1540 break;
f725230a
AK		 1541 case KVM_CAP_NR_VCPUS:
1542 r = KVM_MAX_VCPUS;
1543 break;
a988b910
AK		 1544 case KVM_CAP_NR_MEMSLOTS:
1545 r = KVM_MEMORY_SLOTS;
1546 break;
a68a6a72
MT		 1547 case KVM_CAP_PV_MMU: /* obsolete */
1548 r = 0;
2f333bcb 1549 break;
62c476c7 1550 case KVM_CAP_IOMMU:
19de40a8 1551 r = iommu_found();
62c476c7 1552 break;
890ca9ae
HY		 1553 case KVM_CAP_MCE:
1554 r = KVM_MAX_MCE_BANKS;
1555 break;
018d00d2
ZX		 1556 default:
1557 r = 0;
1558 break;
1559 }
1560 return r;
1561
1562}
1563
043405e1
CO		 1564long kvm_arch_dev_ioctl(struct file *filp,
1565 unsigned int ioctl, unsigned long arg)
1566{
1567 void __user *argp = (void __user *)arg;
1568 long r;
1569
1570 switch (ioctl) {
1571 case KVM_GET_MSR_INDEX_LIST: {
1572 struct kvm_msr_list __user *user_msr_list = argp;
1573 struct kvm_msr_list msr_list;
1574 unsigned n;
1575
1576 r = -EFAULT;
1577 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1578 goto out;
1579 n = msr_list.nmsrs;
1580 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1581 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1582 goto out;
1583 r = -E2BIG;
e125e7b6 1584 if (n < msr_list.nmsrs)
043405e1
CO		 1585 goto out;
1586 r = -EFAULT;
1587 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1588 num_msrs_to_save * sizeof(u32)))
1589 goto out;
e125e7b6 1590 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1591 &emulated_msrs,
1592 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1593 goto out;
1594 r = 0;
1595 break;
1596 }
674eea0f
AK		 1597 case KVM_GET_SUPPORTED_CPUID: {
1598 struct kvm_cpuid2 __user *cpuid_arg = argp;
1599 struct kvm_cpuid2 cpuid;
1600
1601 r = -EFAULT;
1602 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1603 goto out;
1604 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1605 cpuid_arg->entries);
674eea0f
AK		 1606 if (r)
1607 goto out;
1608
1609 r = -EFAULT;
1610 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1611 goto out;
1612 r = 0;
1613 break;
1614 }
890ca9ae
HY		 1615 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1616 u64 mce_cap;
1617
1618 mce_cap = KVM_MCE_CAP_SUPPORTED;
1619 r = -EFAULT;
1620 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1621 goto out;
1622 r = 0;
1623 break;
1624 }
043405e1
CO		 1625 default:
1626 r = -EINVAL;
1627 }
1628out:
1629 return r;
1630}
1631
313a3dc7
CO		 1632void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1633{
1634 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1635 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1636 unsigned long khz = cpufreq_quick_get(cpu);
1637 if (!khz)
1638 khz = tsc_khz;
1639 per_cpu(cpu_tsc_khz, cpu) = khz;
1640 }
c8076604 1641 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1642}
1643
1644void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1645{
9327fd11 1646 kvm_put_guest_fpu(vcpu);
02daab21 1647 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1648}
1649
07716717 1650static int is_efer_nx(void)
313a3dc7 1651{
e286e86e 1652 unsigned long long efer = 0;
313a3dc7 1653
e286e86e 1654 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1655 return efer & EFER_NX;
1656}
1657
1658static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1659{
1660 int i;
1661 struct kvm_cpuid_entry2 *e, *entry;
1662
313a3dc7 1663 entry = NULL;
ad312c7c
ZX		 1664 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1665 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1666 if (e->function == 0x80000001) {
1667 entry = e;
1668 break;
1669 }
1670 }
07716717 1671 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1672 entry->edx &= ~(1 << 20);
1673 printk(KERN_INFO "kvm: guest NX capability removed\n");
1674 }
1675}
1676
07716717 1677/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1678static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1679 struct kvm_cpuid *cpuid,
1680 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1681{
1682 int r, i;
1683 struct kvm_cpuid_entry *cpuid_entries;
1684
1685 r = -E2BIG;
1686 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1687 goto out;
1688 r = -ENOMEM;
1689 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1690 if (!cpuid_entries)
1691 goto out;
1692 r = -EFAULT;
1693 if (copy_from_user(cpuid_entries, entries,
1694 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1695 goto out_free;
1696 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1697 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1698 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1699 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1700 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1701 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1702 vcpu->arch.cpuid_entries[i].index = 0;
1703 vcpu->arch.cpuid_entries[i].flags = 0;
1704 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1705 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1706 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1707 }
1708 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1709 cpuid_fix_nx_cap(vcpu);
1710 r = 0;
fc61b800 1711 kvm_apic_set_version(vcpu);
0e851880 1712 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1713
1714out_free:
1715 vfree(cpuid_entries);
1716out:
1717 return r;
1718}
1719
1720static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1721 struct kvm_cpuid2 *cpuid,
1722 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1723{
1724 int r;
1725
1726 r = -E2BIG;
1727 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1728 goto out;
1729 r = -EFAULT;
ad312c7c 1730 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1731 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1732 goto out;
ad312c7c 1733 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1734 kvm_apic_set_version(vcpu);
0e851880 1735 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1736 return 0;
1737
1738out:
1739 return r;
1740}
1741
07716717 1742static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1743 struct kvm_cpuid2 *cpuid,
1744 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1745{
1746 int r;
1747
1748 r = -E2BIG;
ad312c7c 1749 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1750 goto out;
1751 r = -EFAULT;
ad312c7c 1752 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1753 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1754 goto out;
1755 return 0;
1756
1757out:
ad312c7c 1758 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1759 return r;
1760}
1761
07716717 1762static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1763 u32 index)
07716717
DK		 1764{
1765 entry->function = function;
1766 entry->index = index;
1767 cpuid_count(entry->function, entry->index,
19355475 1768 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1769 entry->flags = 0;
1770}
1771
7faa4ee1
AK		 1772#define F(x) bit(X86_FEATURE_##x)
1773
07716717
DK		 1774static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1775 u32 index, int *nent, int maxnent)
1776{
7faa4ee1 1777 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1778#ifdef CONFIG_X86_64
17cc3935
SY		 1779 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1780 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1781 unsigned f_lm = F(LM);
1782#else
17cc3935 1783 unsigned f_gbpages = 0;
7faa4ee1 1784 unsigned f_lm = 0;
07716717 1785#endif
4e47c7a6 1786 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1787
1788 /* cpuid 1.edx */
1789 const u32 kvm_supported_word0_x86_features =
1790 F(FPU) | F(VME) | F(DE) | F(PSE) |
1791 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1792 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1793 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1794 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1795 0 /* Reserved, DS, ACPI */ | F(MMX) |
1796 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1797 0 /* HTT, TM, Reserved, PBE */;
1798 /* cpuid 0x80000001.edx */
1799 const u32 kvm_supported_word1_x86_features =
1800 F(FPU) | F(VME) | F(DE) | F(PSE) |
1801 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1802 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1803 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1804 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1805 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1806 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1807 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1808 /* cpuid 1.ecx */
1809 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1810 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1811 0 /* DS-CPL, VMX, SMX, EST */ |
1812 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1813 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1814 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1815 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1816 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1817 /* cpuid 0x80000001.ecx */
07716717 1818 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1819 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1820 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1821 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1822 0 /* SKINIT */ | 0 /* WDT */;
07716717 1823
19355475 1824 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1825 get_cpu();
1826 do_cpuid_1_ent(entry, function, index);
1827 ++*nent;
1828
1829 switch (function) {
1830 case 0:
1831 entry->eax = min(entry->eax, (u32)0xb);
1832 break;
1833 case 1:
1834 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1835 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1836 /* we support x2apic emulation even if host does not support
1837 * it since we emulate x2apic in software */
1838 entry->ecx |= F(X2APIC);
07716717
DK		 1839 break;
1840 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1841 * may return different values. This forces us to get_cpu() before
1842 * issuing the first command, and also to emulate this annoying behavior
1843 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1844 case 2: {
1845 int t, times = entry->eax & 0xff;
1846
1847 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1848 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1849 for (t = 1; t < times && *nent < maxnent; ++t) {
1850 do_cpuid_1_ent(&entry[t], function, 0);
1851 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1852 ++*nent;
1853 }
1854 break;
1855 }
1856 /* function 4 and 0xb have additional index. */
1857 case 4: {
14af3f3c 1858 int i, cache_type;
07716717
DK		 1859
1860 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1861 /* read more entries until cache_type is zero */
14af3f3c
HH		 1862 for (i = 1; *nent < maxnent; ++i) {
1863 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1864 if (!cache_type)
1865 break;
14af3f3c
HH		 1866 do_cpuid_1_ent(&entry[i], function, i);
1867 entry[i].flags |=
07716717
DK		 1868 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1869 ++*nent;
1870 }
1871 break;
1872 }
1873 case 0xb: {
14af3f3c 1874 int i, level_type;
07716717
DK		 1875
1876 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1877 /* read more entries until level_type is zero */
14af3f3c 1878 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1879 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1880 if (!level_type)
1881 break;
14af3f3c
HH		 1882 do_cpuid_1_ent(&entry[i], function, i);
1883 entry[i].flags |=
07716717
DK		 1884 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1885 ++*nent;
1886 }
1887 break;
1888 }
1889 case 0x80000000:
1890 entry->eax = min(entry->eax, 0x8000001a);
1891 break;
1892 case 0x80000001:
1893 entry->edx &= kvm_supported_word1_x86_features;
1894 entry->ecx &= kvm_supported_word6_x86_features;
1895 break;
1896 }
1897 put_cpu();
1898}
1899
7faa4ee1
AK		 1900#undef F
1901
674eea0f 1902static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1903 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1904{
1905 struct kvm_cpuid_entry2 *cpuid_entries;
1906 int limit, nent = 0, r = -E2BIG;
1907 u32 func;
1908
1909 if (cpuid->nent < 1)
1910 goto out;
6a544355
AK		 1911 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1912 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1913 r = -ENOMEM;
1914 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1915 if (!cpuid_entries)
1916 goto out;
1917
1918 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1919 limit = cpuid_entries[0].eax;
1920 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1921 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1922 &nent, cpuid->nent);
07716717
DK		 1923 r = -E2BIG;
1924 if (nent >= cpuid->nent)
1925 goto out_free;
1926
1927 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1928 limit = cpuid_entries[nent - 1].eax;
1929 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1930 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1931 &nent, cpuid->nent);
cb007648
MM		 1932 r = -E2BIG;
1933 if (nent >= cpuid->nent)
1934 goto out_free;
1935
07716717
DK		 1936 r = -EFAULT;
1937 if (copy_to_user(entries, cpuid_entries,
19355475 1938 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1939 goto out_free;
1940 cpuid->nent = nent;
1941 r = 0;
1942
1943out_free:
1944 vfree(cpuid_entries);
1945out:
1946 return r;
1947}
1948
313a3dc7
CO		 1949static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1950 struct kvm_lapic_state *s)
1951{
1952 vcpu_load(vcpu);
ad312c7c 1953 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1954 vcpu_put(vcpu);
1955
1956 return 0;
1957}
1958
1959static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1960 struct kvm_lapic_state *s)
1961{
1962 vcpu_load(vcpu);
ad312c7c 1963 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1964 kvm_apic_post_state_restore(vcpu);
cb142eb7 1965 update_cr8_intercept(vcpu);
313a3dc7
CO		 1966 vcpu_put(vcpu);
1967
1968 return 0;
1969}
1970
f77bc6a4
ZX		 1971static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1972 struct kvm_interrupt *irq)
1973{
1974 if (irq->irq < 0 || irq->irq >= 256)
1975 return -EINVAL;
1976 if (irqchip_in_kernel(vcpu->kvm))
1977 return -ENXIO;
1978 vcpu_load(vcpu);
1979
66fd3f7f 1980 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1981
1982 vcpu_put(vcpu);
1983
1984 return 0;
1985}
1986
c4abb7c9
JK		 1987static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1988{
1989 vcpu_load(vcpu);
1990 kvm_inject_nmi(vcpu);
1991 vcpu_put(vcpu);
1992
1993 return 0;
1994}
1995
b209749f
AK		 1996static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1997 struct kvm_tpr_access_ctl *tac)
1998{
1999 if (tac->flags)
2000 return -EINVAL;
2001 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2002 return 0;
2003}
2004
890ca9ae
HY		 2005static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2006 u64 mcg_cap)
2007{
2008 int r;
2009 unsigned bank_num = mcg_cap & 0xff, bank;
2010
2011 r = -EINVAL;
a9e38c3e 2012 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2013 goto out;
2014 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2015 goto out;
2016 r = 0;
2017 vcpu->arch.mcg_cap = mcg_cap;
2018 /* Init IA32_MCG_CTL to all 1s */
2019 if (mcg_cap & MCG_CTL_P)
2020 vcpu->arch.mcg_ctl = ~(u64)0;
2021 /* Init IA32_MCi_CTL to all 1s */
2022 for (bank = 0; bank < bank_num; bank++)
2023 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2024out:
2025 return r;
2026}
2027
2028static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2029 struct kvm_x86_mce *mce)
2030{
2031 u64 mcg_cap = vcpu->arch.mcg_cap;
2032 unsigned bank_num = mcg_cap & 0xff;
2033 u64 *banks = vcpu->arch.mce_banks;
2034
2035 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2036 return -EINVAL;
2037 /*
2038 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2039 * reporting is disabled
2040 */
2041 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2042 vcpu->arch.mcg_ctl != ~(u64)0)
2043 return 0;
2044 banks += 4 * mce->bank;
2045 /*
2046 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2047 * reporting is disabled for the bank
2048 */
2049 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2050 return 0;
2051 if (mce->status & MCI_STATUS_UC) {
2052 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2053 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2054 printk(KERN_DEBUG "kvm: set_mce: "
2055 "injects mce exception while "
2056 "previous one is in progress!\n");
2057 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2058 return 0;
2059 }
2060 if (banks[1] & MCI_STATUS_VAL)
2061 mce->status |= MCI_STATUS_OVER;
2062 banks[2] = mce->addr;
2063 banks[3] = mce->misc;
2064 vcpu->arch.mcg_status = mce->mcg_status;
2065 banks[1] = mce->status;
2066 kvm_queue_exception(vcpu, MC_VECTOR);
2067 } else if (!(banks[1] & MCI_STATUS_VAL)
2068 || !(banks[1] & MCI_STATUS_UC)) {
2069 if (banks[1] & MCI_STATUS_VAL)
2070 mce->status |= MCI_STATUS_OVER;
2071 banks[2] = mce->addr;
2072 banks[3] = mce->misc;
2073 banks[1] = mce->status;
2074 } else
2075 banks[1] |= MCI_STATUS_OVER;
2076 return 0;
2077}
2078
3cfc3092
JK		 2079static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2080 struct kvm_vcpu_events *events)
2081{
2082 vcpu_load(vcpu);
2083
2084 events->exception.injected = vcpu->arch.exception.pending;
2085 events->exception.nr = vcpu->arch.exception.nr;
2086 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2087 events->exception.error_code = vcpu->arch.exception.error_code;
2088
2089 events->interrupt.injected = vcpu->arch.interrupt.pending;
2090 events->interrupt.nr = vcpu->arch.interrupt.nr;
2091 events->interrupt.soft = vcpu->arch.interrupt.soft;
2092
2093 events->nmi.injected = vcpu->arch.nmi_injected;
2094 events->nmi.pending = vcpu->arch.nmi_pending;
2095 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2096
2097 events->sipi_vector = vcpu->arch.sipi_vector;
2098
dab4b911
JK		 2099 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2100 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 2101
2102 vcpu_put(vcpu);
2103}
2104
2105static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2106 struct kvm_vcpu_events *events)
2107{
dab4b911
JK		 2108 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2109 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 2110 return -EINVAL;
2111
2112 vcpu_load(vcpu);
2113
2114 vcpu->arch.exception.pending = events->exception.injected;
2115 vcpu->arch.exception.nr = events->exception.nr;
2116 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2117 vcpu->arch.exception.error_code = events->exception.error_code;
2118
2119 vcpu->arch.interrupt.pending = events->interrupt.injected;
2120 vcpu->arch.interrupt.nr = events->interrupt.nr;
2121 vcpu->arch.interrupt.soft = events->interrupt.soft;
2122 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2123 kvm_pic_clear_isr_ack(vcpu->kvm);
2124
2125 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2126 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2127 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2128 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2129
dab4b911
JK		 2130 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2131 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2132
2133 vcpu_put(vcpu);
2134
2135 return 0;
2136}
2137
313a3dc7
CO		 2138long kvm_arch_vcpu_ioctl(struct file *filp,
2139 unsigned int ioctl, unsigned long arg)
2140{
2141 struct kvm_vcpu *vcpu = filp->private_data;
2142 void __user *argp = (void __user *)arg;
2143 int r;
b772ff36 2144 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2145
2146 switch (ioctl) {
2147 case KVM_GET_LAPIC: {
2204ae3c
MT		 2148 r = -EINVAL;
2149 if (!vcpu->arch.apic)
2150 goto out;
b772ff36 2151 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2152
b772ff36
DH		 2153 r = -ENOMEM;
2154 if (!lapic)
2155 goto out;
2156 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2157 if (r)
2158 goto out;
2159 r = -EFAULT;
b772ff36 2160 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2161 goto out;
2162 r = 0;
2163 break;
2164 }
2165 case KVM_SET_LAPIC: {
2204ae3c
MT		 2166 r = -EINVAL;
2167 if (!vcpu->arch.apic)
2168 goto out;
b772ff36
DH		 2169 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2170 r = -ENOMEM;
2171 if (!lapic)
2172 goto out;
313a3dc7 2173 r = -EFAULT;
b772ff36 2174 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2175 goto out;
b772ff36 2176 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2177 if (r)
2178 goto out;
2179 r = 0;
2180 break;
2181 }
f77bc6a4
ZX		 2182 case KVM_INTERRUPT: {
2183 struct kvm_interrupt irq;
2184
2185 r = -EFAULT;
2186 if (copy_from_user(&irq, argp, sizeof irq))
2187 goto out;
2188 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2189 if (r)
2190 goto out;
2191 r = 0;
2192 break;
2193 }
c4abb7c9
JK		 2194 case KVM_NMI: {
2195 r = kvm_vcpu_ioctl_nmi(vcpu);
2196 if (r)
2197 goto out;
2198 r = 0;
2199 break;
2200 }
313a3dc7
CO		 2201 case KVM_SET_CPUID: {
2202 struct kvm_cpuid __user *cpuid_arg = argp;
2203 struct kvm_cpuid cpuid;
2204
2205 r = -EFAULT;
2206 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2207 goto out;
2208 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2209 if (r)
2210 goto out;
2211 break;
2212 }
07716717
DK		 2213 case KVM_SET_CPUID2: {
2214 struct kvm_cpuid2 __user *cpuid_arg = argp;
2215 struct kvm_cpuid2 cpuid;
2216
2217 r = -EFAULT;
2218 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2219 goto out;
2220 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2221 cpuid_arg->entries);
07716717
DK		 2222 if (r)
2223 goto out;
2224 break;
2225 }
2226 case KVM_GET_CPUID2: {
2227 struct kvm_cpuid2 __user *cpuid_arg = argp;
2228 struct kvm_cpuid2 cpuid;
2229
2230 r = -EFAULT;
2231 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2232 goto out;
2233 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2234 cpuid_arg->entries);
07716717
DK		 2235 if (r)
2236 goto out;
2237 r = -EFAULT;
2238 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2239 goto out;
2240 r = 0;
2241 break;
2242 }
313a3dc7
CO		 2243 case KVM_GET_MSRS:
2244 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2245 break;
2246 case KVM_SET_MSRS:
2247 r = msr_io(vcpu, argp, do_set_msr, 0);
2248 break;
b209749f
AK		 2249 case KVM_TPR_ACCESS_REPORTING: {
2250 struct kvm_tpr_access_ctl tac;
2251
2252 r = -EFAULT;
2253 if (copy_from_user(&tac, argp, sizeof tac))
2254 goto out;
2255 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2256 if (r)
2257 goto out;
2258 r = -EFAULT;
2259 if (copy_to_user(argp, &tac, sizeof tac))
2260 goto out;
2261 r = 0;
2262 break;
2263 };
b93463aa
AK		 2264 case KVM_SET_VAPIC_ADDR: {
2265 struct kvm_vapic_addr va;
2266
2267 r = -EINVAL;
2268 if (!irqchip_in_kernel(vcpu->kvm))
2269 goto out;
2270 r = -EFAULT;
2271 if (copy_from_user(&va, argp, sizeof va))
2272 goto out;
2273 r = 0;
2274 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2275 break;
2276 }
890ca9ae
HY		 2277 case KVM_X86_SETUP_MCE: {
2278 u64 mcg_cap;
2279
2280 r = -EFAULT;
2281 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2282 goto out;
2283 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2284 break;
2285 }
2286 case KVM_X86_SET_MCE: {
2287 struct kvm_x86_mce mce;
2288
2289 r = -EFAULT;
2290 if (copy_from_user(&mce, argp, sizeof mce))
2291 goto out;
2292 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2293 break;
2294 }
3cfc3092
JK		 2295 case KVM_GET_VCPU_EVENTS: {
2296 struct kvm_vcpu_events events;
2297
2298 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2299
2300 r = -EFAULT;
2301 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2302 break;
2303 r = 0;
2304 break;
2305 }
2306 case KVM_SET_VCPU_EVENTS: {
2307 struct kvm_vcpu_events events;
2308
2309 r = -EFAULT;
2310 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2311 break;
2312
2313 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2314 break;
2315 }
313a3dc7
CO		 2316 default:
2317 r = -EINVAL;
2318 }
2319out:
7a6ce84c 2320 kfree(lapic);
313a3dc7
CO		 2321 return r;
2322}
2323
1fe779f8
CO		 2324static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2325{
2326 int ret;
2327
2328 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2329 return -1;
2330 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2331 return ret;
2332}
2333
b927a3ce
SY		 2334static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2335 u64 ident_addr)
2336{
2337 kvm->arch.ept_identity_map_addr = ident_addr;
2338 return 0;
2339}
2340
1fe779f8
CO		 2341static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2342 u32 kvm_nr_mmu_pages)
2343{
2344 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2345 return -EINVAL;
2346
79fac95e 2347 mutex_lock(&kvm->slots_lock);
7c8a83b7 2348 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2349
2350 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2351 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2352
7c8a83b7 2353 spin_unlock(&kvm->mmu_lock);
79fac95e 2354 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2355 return 0;
2356}
2357
2358static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2359{
f05e70ac 2360 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2361}
2362
a983fb23
MT		 2363gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2364{
2365 int i;
2366 struct kvm_mem_alias *alias;
2367 struct kvm_mem_aliases *aliases;
2368
2369 aliases = rcu_dereference(kvm->arch.aliases);
2370
2371 for (i = 0; i < aliases->naliases; ++i) {
2372 alias = &aliases->aliases[i];
2373 if (alias->flags & KVM_ALIAS_INVALID)
2374 continue;
2375 if (gfn >= alias->base_gfn
2376 && gfn < alias->base_gfn + alias->npages)
2377 return alias->target_gfn + gfn - alias->base_gfn;
2378 }
2379 return gfn;
2380}
2381
e9f85cde
ZX		 2382gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2383{
2384 int i;
2385 struct kvm_mem_alias *alias;
a983fb23
MT		 2386 struct kvm_mem_aliases *aliases;
2387
2388 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2389
fef9cce0
MT		 2390 for (i = 0; i < aliases->naliases; ++i) {
2391 alias = &aliases->aliases[i];
e9f85cde
ZX		 2392 if (gfn >= alias->base_gfn
2393 && gfn < alias->base_gfn + alias->npages)
2394 return alias->target_gfn + gfn - alias->base_gfn;
2395 }
2396 return gfn;
2397}
2398
1fe779f8
CO		 2399/*
2400 * Set a new alias region. Aliases map a portion of physical memory into
2401 * another portion. This is useful for memory windows, for example the PC
2402 * VGA region.
2403 */
2404static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2405 struct kvm_memory_alias *alias)
2406{
2407 int r, n;
2408 struct kvm_mem_alias *p;
a983fb23 2409 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2410
2411 r = -EINVAL;
2412 /* General sanity checks */
2413 if (alias->memory_size & (PAGE_SIZE - 1))
2414 goto out;
2415 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2416 goto out;
2417 if (alias->slot >= KVM_ALIAS_SLOTS)
2418 goto out;
2419 if (alias->guest_phys_addr + alias->memory_size
2420 < alias->guest_phys_addr)
2421 goto out;
2422 if (alias->target_phys_addr + alias->memory_size
2423 < alias->target_phys_addr)
2424 goto out;
2425
a983fb23
MT		 2426 r = -ENOMEM;
2427 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2428 if (!aliases)
2429 goto out;
2430
79fac95e 2431 mutex_lock(&kvm->slots_lock);
1fe779f8 2432
a983fb23
MT		 2433 /* invalidate any gfn reference in case of deletion/shrinking */
2434 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2435 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2436 old_aliases = kvm->arch.aliases;
2437 rcu_assign_pointer(kvm->arch.aliases, aliases);
2438 synchronize_srcu_expedited(&kvm->srcu);
2439 kvm_mmu_zap_all(kvm);
2440 kfree(old_aliases);
2441
2442 r = -ENOMEM;
2443 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2444 if (!aliases)
2445 goto out_unlock;
2446
2447 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2448
2449 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2450 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2451 p->npages = alias->memory_size >> PAGE_SHIFT;
2452 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2453 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2454
2455 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2456 if (aliases->aliases[n - 1].npages)
1fe779f8 2457 break;
fef9cce0 2458 aliases->naliases = n;
1fe779f8 2459
a983fb23
MT		 2460 old_aliases = kvm->arch.aliases;
2461 rcu_assign_pointer(kvm->arch.aliases, aliases);
2462 synchronize_srcu_expedited(&kvm->srcu);
2463 kfree(old_aliases);
2464 r = 0;
1fe779f8 2465
a983fb23 2466out_unlock:
79fac95e 2467 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2468out:
2469 return r;
2470}
2471
2472static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2473{
2474 int r;
2475
2476 r = 0;
2477 switch (chip->chip_id) {
2478 case KVM_IRQCHIP_PIC_MASTER:
2479 memcpy(&chip->chip.pic,
2480 &pic_irqchip(kvm)->pics[0],
2481 sizeof(struct kvm_pic_state));
2482 break;
2483 case KVM_IRQCHIP_PIC_SLAVE:
2484 memcpy(&chip->chip.pic,
2485 &pic_irqchip(kvm)->pics[1],
2486 sizeof(struct kvm_pic_state));
2487 break;
2488 case KVM_IRQCHIP_IOAPIC:
eba0226b 2489 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2490 break;
2491 default:
2492 r = -EINVAL;
2493 break;
2494 }
2495 return r;
2496}
2497
2498static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2499{
2500 int r;
2501
2502 r = 0;
2503 switch (chip->chip_id) {
2504 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2505 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2506 memcpy(&pic_irqchip(kvm)->pics[0],
2507 &chip->chip.pic,
2508 sizeof(struct kvm_pic_state));
894a9c55 2509 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2510 break;
2511 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2512 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2513 memcpy(&pic_irqchip(kvm)->pics[1],
2514 &chip->chip.pic,
2515 sizeof(struct kvm_pic_state));
894a9c55 2516 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2517 break;
2518 case KVM_IRQCHIP_IOAPIC:
eba0226b 2519 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2520 break;
2521 default:
2522 r = -EINVAL;
2523 break;
2524 }
2525 kvm_pic_update_irq(pic_irqchip(kvm));
2526 return r;
2527}
2528
e0f63cb9
SY		 2529static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2530{
2531 int r = 0;
2532
894a9c55 2533 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2534 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2535 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2536 return r;
2537}
2538
2539static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2540{
2541 int r = 0;
2542
894a9c55 2543 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2544 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2545 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2546 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2547 return r;
2548}
2549
2550static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2551{
2552 int r = 0;
2553
2554 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2555 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2556 sizeof(ps->channels));
2557 ps->flags = kvm->arch.vpit->pit_state.flags;
2558 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2559 return r;
2560}
2561
2562static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2563{
2564 int r = 0, start = 0;
2565 u32 prev_legacy, cur_legacy;
2566 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2567 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2568 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2569 if (!prev_legacy && cur_legacy)
2570 start = 1;
2571 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2572 sizeof(kvm->arch.vpit->pit_state.channels));
2573 kvm->arch.vpit->pit_state.flags = ps->flags;
2574 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2575 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2576 return r;
2577}
2578
52d939a0
MT		 2579static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2580 struct kvm_reinject_control *control)
2581{
2582 if (!kvm->arch.vpit)
2583 return -ENXIO;
894a9c55 2584 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2585 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2586 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2587 return 0;
2588}
2589
5bb064dc
ZX		 2590/*
2591 * Get (and clear) the dirty memory log for a memory slot.
2592 */
2593int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2594 struct kvm_dirty_log *log)
2595{
b050b015 2596 int r, n, i;
5bb064dc 2597 struct kvm_memory_slot *memslot;
b050b015
MT		 2598 unsigned long is_dirty = 0;
2599 unsigned long *dirty_bitmap = NULL;
5bb064dc 2600
79fac95e 2601 mutex_lock(&kvm->slots_lock);
5bb064dc 2602
b050b015
MT		 2603 r = -EINVAL;
2604 if (log->slot >= KVM_MEMORY_SLOTS)
2605 goto out;
2606
2607 memslot = &kvm->memslots->memslots[log->slot];
2608 r = -ENOENT;
2609 if (!memslot->dirty_bitmap)
2610 goto out;
2611
2612 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2613
2614 r = -ENOMEM;
2615 dirty_bitmap = vmalloc(n);
2616 if (!dirty_bitmap)
5bb064dc 2617 goto out;
b050b015
MT		 2618 memset(dirty_bitmap, 0, n);
2619
2620 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2621 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2622
2623 /* If nothing is dirty, don't bother messing with page tables. */
2624 if (is_dirty) {
b050b015
MT		 2625 struct kvm_memslots *slots, *old_slots;
2626
7c8a83b7 2627 spin_lock(&kvm->mmu_lock);
5bb064dc 2628 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2629 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2630
2631 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2632 if (!slots)
2633 goto out_free;
2634
2635 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2636 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2637
2638 old_slots = kvm->memslots;
2639 rcu_assign_pointer(kvm->memslots, slots);
2640 synchronize_srcu_expedited(&kvm->srcu);
2641 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2642 kfree(old_slots);
5bb064dc 2643 }
b050b015 2644
5bb064dc 2645 r = 0;
b050b015
MT		 2646 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2647 r = -EFAULT;
2648out_free:
2649 vfree(dirty_bitmap);
5bb064dc 2650out:
79fac95e 2651 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2652 return r;
2653}
2654
1fe779f8
CO		 2655long kvm_arch_vm_ioctl(struct file *filp,
2656 unsigned int ioctl, unsigned long arg)
2657{
2658 struct kvm *kvm = filp->private_data;
2659 void __user *argp = (void __user *)arg;
367e1319 2660 int r = -ENOTTY;
f0d66275
DH		 2661 /*
2662 * This union makes it completely explicit to gcc-3.x
2663 * that these two variables' stack usage should be
2664 * combined, not added together.
2665 */
2666 union {
2667 struct kvm_pit_state ps;
e9f42757 2668 struct kvm_pit_state2 ps2;
f0d66275 2669 struct kvm_memory_alias alias;
c5ff41ce 2670 struct kvm_pit_config pit_config;
f0d66275 2671 } u;
1fe779f8
CO		 2672
2673 switch (ioctl) {
2674 case KVM_SET_TSS_ADDR:
2675 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2676 if (r < 0)
2677 goto out;
2678 break;
b927a3ce
SY		 2679 case KVM_SET_IDENTITY_MAP_ADDR: {
2680 u64 ident_addr;
2681
2682 r = -EFAULT;
2683 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2684 goto out;
2685 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2686 if (r < 0)
2687 goto out;
2688 break;
2689 }
1fe779f8
CO		 2690 case KVM_SET_MEMORY_REGION: {
2691 struct kvm_memory_region kvm_mem;
2692 struct kvm_userspace_memory_region kvm_userspace_mem;
2693
2694 r = -EFAULT;
2695 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2696 goto out;
2697 kvm_userspace_mem.slot = kvm_mem.slot;
2698 kvm_userspace_mem.flags = kvm_mem.flags;
2699 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2700 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2701 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2702 if (r)
2703 goto out;
2704 break;
2705 }
2706 case KVM_SET_NR_MMU_PAGES:
2707 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2708 if (r)
2709 goto out;
2710 break;
2711 case KVM_GET_NR_MMU_PAGES:
2712 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2713 break;
f0d66275 2714 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2715 r = -EFAULT;
f0d66275 2716 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2717 goto out;
f0d66275 2718 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2719 if (r)
2720 goto out;
2721 break;
3ddea128
MT		 2722 case KVM_CREATE_IRQCHIP: {
2723 struct kvm_pic *vpic;
2724
2725 mutex_lock(&kvm->lock);
2726 r = -EEXIST;
2727 if (kvm->arch.vpic)
2728 goto create_irqchip_unlock;
1fe779f8 2729 r = -ENOMEM;
3ddea128
MT		 2730 vpic = kvm_create_pic(kvm);
2731 if (vpic) {
1fe779f8
CO		 2732 r = kvm_ioapic_init(kvm);
2733 if (r) {
3ddea128
MT		 2734 kfree(vpic);
2735 goto create_irqchip_unlock;
1fe779f8
CO		 2736 }
2737 } else
3ddea128
MT		 2738 goto create_irqchip_unlock;
2739 smp_wmb();
2740 kvm->arch.vpic = vpic;
2741 smp_wmb();
399ec807
AK		 2742 r = kvm_setup_default_irq_routing(kvm);
2743 if (r) {
3ddea128 2744 mutex_lock(&kvm->irq_lock);
399ec807
AK		 2745 kfree(kvm->arch.vpic);
2746 kfree(kvm->arch.vioapic);
3ddea128
MT		 2747 kvm->arch.vpic = NULL;
2748 kvm->arch.vioapic = NULL;
2749 mutex_unlock(&kvm->irq_lock);
399ec807 2750 }
3ddea128
MT		 2751 create_irqchip_unlock:
2752 mutex_unlock(&kvm->lock);
1fe779f8 2753 break;
3ddea128 2754 }
7837699f 2755 case KVM_CREATE_PIT:
c5ff41ce
JK		 2756 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2757 goto create_pit;
2758 case KVM_CREATE_PIT2:
2759 r = -EFAULT;
2760 if (copy_from_user(&u.pit_config, argp,
2761 sizeof(struct kvm_pit_config)))
2762 goto out;
2763 create_pit:
79fac95e 2764 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2765 r = -EEXIST;
2766 if (kvm->arch.vpit)
2767 goto create_pit_unlock;
7837699f 2768 r = -ENOMEM;
c5ff41ce 2769 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2770 if (kvm->arch.vpit)
2771 r = 0;
269e05e4 2772 create_pit_unlock:
79fac95e 2773 mutex_unlock(&kvm->slots_lock);
7837699f 2774 break;
4925663a 2775 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2776 case KVM_IRQ_LINE: {
2777 struct kvm_irq_level irq_event;
2778
2779 r = -EFAULT;
2780 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2781 goto out;
2782 if (irqchip_in_kernel(kvm)) {
4925663a 2783 __s32 status;
4925663a
GN		 2784 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2785 irq_event.irq, irq_event.level);
4925663a
GN		 2786 if (ioctl == KVM_IRQ_LINE_STATUS) {
2787 irq_event.status = status;
2788 if (copy_to_user(argp, &irq_event,
2789 sizeof irq_event))
2790 goto out;
2791 }
1fe779f8
CO		 2792 r = 0;
2793 }
2794 break;
2795 }
2796 case KVM_GET_IRQCHIP: {
2797 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2798 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2799
f0d66275
DH		 2800 r = -ENOMEM;
2801 if (!chip)
1fe779f8 2802 goto out;
f0d66275
DH		 2803 r = -EFAULT;
2804 if (copy_from_user(chip, argp, sizeof *chip))
2805 goto get_irqchip_out;
1fe779f8
CO		 2806 r = -ENXIO;
2807 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2808 goto get_irqchip_out;
2809 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2810 if (r)
f0d66275 2811 goto get_irqchip_out;
1fe779f8 2812 r = -EFAULT;
f0d66275
DH		 2813 if (copy_to_user(argp, chip, sizeof *chip))
2814 goto get_irqchip_out;
1fe779f8 2815 r = 0;
f0d66275
DH		 2816 get_irqchip_out:
2817 kfree(chip);
2818 if (r)
2819 goto out;
1fe779f8
CO		 2820 break;
2821 }
2822 case KVM_SET_IRQCHIP: {
2823 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2824 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2825
f0d66275
DH		 2826 r = -ENOMEM;
2827 if (!chip)
1fe779f8 2828 goto out;
f0d66275
DH		 2829 r = -EFAULT;
2830 if (copy_from_user(chip, argp, sizeof *chip))
2831 goto set_irqchip_out;
1fe779f8
CO		 2832 r = -ENXIO;
2833 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2834 goto set_irqchip_out;
2835 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2836 if (r)
f0d66275 2837 goto set_irqchip_out;
1fe779f8 2838 r = 0;
f0d66275
DH		 2839 set_irqchip_out:
2840 kfree(chip);
2841 if (r)
2842 goto out;
1fe779f8
CO		 2843 break;
2844 }
e0f63cb9 2845 case KVM_GET_PIT: {
e0f63cb9 2846 r = -EFAULT;
f0d66275 2847 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2848 goto out;
2849 r = -ENXIO;
2850 if (!kvm->arch.vpit)
2851 goto out;
f0d66275 2852 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2853 if (r)
2854 goto out;
2855 r = -EFAULT;
f0d66275 2856 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2857 goto out;
2858 r = 0;
2859 break;
2860 }
2861 case KVM_SET_PIT: {
e0f63cb9 2862 r = -EFAULT;
f0d66275 2863 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2864 goto out;
2865 r = -ENXIO;
2866 if (!kvm->arch.vpit)
2867 goto out;
f0d66275 2868 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2869 if (r)
2870 goto out;
2871 r = 0;
2872 break;
2873 }
e9f42757
BK		 2874 case KVM_GET_PIT2: {
2875 r = -ENXIO;
2876 if (!kvm->arch.vpit)
2877 goto out;
2878 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2879 if (r)
2880 goto out;
2881 r = -EFAULT;
2882 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2883 goto out;
2884 r = 0;
2885 break;
2886 }
2887 case KVM_SET_PIT2: {
2888 r = -EFAULT;
2889 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2890 goto out;
2891 r = -ENXIO;
2892 if (!kvm->arch.vpit)
2893 goto out;
2894 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2895 if (r)
2896 goto out;
2897 r = 0;
2898 break;
2899 }
52d939a0
MT		 2900 case KVM_REINJECT_CONTROL: {
2901 struct kvm_reinject_control control;
2902 r = -EFAULT;
2903 if (copy_from_user(&control, argp, sizeof(control)))
2904 goto out;
2905 r = kvm_vm_ioctl_reinject(kvm, &control);
2906 if (r)
2907 goto out;
2908 r = 0;
2909 break;
2910 }
ffde22ac
ES		 2911 case KVM_XEN_HVM_CONFIG: {
2912 r = -EFAULT;
2913 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2914 sizeof(struct kvm_xen_hvm_config)))
2915 goto out;
2916 r = -EINVAL;
2917 if (kvm->arch.xen_hvm_config.flags)
2918 goto out;
2919 r = 0;
2920 break;
2921 }
afbcf7ab
GC		 2922 case KVM_SET_CLOCK: {
2923 struct timespec now;
2924 struct kvm_clock_data user_ns;
2925 u64 now_ns;
2926 s64 delta;
2927
2928 r = -EFAULT;
2929 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2930 goto out;
2931
2932 r = -EINVAL;
2933 if (user_ns.flags)
2934 goto out;
2935
2936 r = 0;
2937 ktime_get_ts(&now);
2938 now_ns = timespec_to_ns(&now);
2939 delta = user_ns.clock - now_ns;
2940 kvm->arch.kvmclock_offset = delta;
2941 break;
2942 }
2943 case KVM_GET_CLOCK: {
2944 struct timespec now;
2945 struct kvm_clock_data user_ns;
2946 u64 now_ns;
2947
2948 ktime_get_ts(&now);
2949 now_ns = timespec_to_ns(&now);
2950 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2951 user_ns.flags = 0;
2952
2953 r = -EFAULT;
2954 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2955 goto out;
2956 r = 0;
2957 break;
2958 }
2959
1fe779f8
CO		 2960 default:
2961 ;
2962 }
2963out:
2964 return r;
2965}
2966
a16b043c 2967static void kvm_init_msr_list(void)
043405e1
CO		 2968{
2969 u32 dummy[2];
2970 unsigned i, j;
2971
e3267cbb
GC		 2972 /* skip the first msrs in the list. KVM-specific */
2973 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2974 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2975 continue;
2976 if (j < i)
2977 msrs_to_save[j] = msrs_to_save[i];
2978 j++;
2979 }
2980 num_msrs_to_save = j;
2981}
2982
bda9020e
MT		 2983static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2984 const void *v)
bbd9b64e 2985{
bda9020e
MT		 2986 if (vcpu->arch.apic &&
2987 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2988 return 0;
bbd9b64e 2989
e93f8a0f 2990 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 2991}
2992
bda9020e 2993static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2994{
bda9020e
MT		 2995 if (vcpu->arch.apic &&
2996 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2997 return 0;
bbd9b64e 2998
e93f8a0f 2999 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3000}
3001
cded19f3
HE		 3002static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3003 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3004{
3005 void *data = val;
10589a46 3006 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3007
3008 while (bytes) {
ad312c7c 3009 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 3010 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3011 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3012 int ret;
3013
10589a46
MT		 3014 if (gpa == UNMAPPED_GVA) {
3015 r = X86EMUL_PROPAGATE_FAULT;
3016 goto out;
3017 }
77c2002e 3018 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3019 if (ret < 0) {
3020 r = X86EMUL_UNHANDLEABLE;
3021 goto out;
3022 }
bbd9b64e 3023
77c2002e
IE		 3024 bytes -= toread;
3025 data += toread;
3026 addr += toread;
bbd9b64e 3027 }
10589a46 3028out:
10589a46 3029 return r;
bbd9b64e 3030}
77c2002e 3031
cded19f3
HE		 3032static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
3033 struct kvm_vcpu *vcpu)
77c2002e
IE		 3034{
3035 void *data = val;
3036 int r = X86EMUL_CONTINUE;
3037
3038 while (bytes) {
3039 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
3040 unsigned offset = addr & (PAGE_SIZE-1);
3041 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3042 int ret;
3043
3044 if (gpa == UNMAPPED_GVA) {
3045 r = X86EMUL_PROPAGATE_FAULT;
3046 goto out;
3047 }
3048 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3049 if (ret < 0) {
3050 r = X86EMUL_UNHANDLEABLE;
3051 goto out;
3052 }
3053
3054 bytes -= towrite;
3055 data += towrite;
3056 addr += towrite;
3057 }
3058out:
3059 return r;
3060}
3061
bbd9b64e 3062
bbd9b64e
CO		 3063static int emulator_read_emulated(unsigned long addr,
3064 void *val,
3065 unsigned int bytes,
3066 struct kvm_vcpu *vcpu)
3067{
bbd9b64e
CO		 3068 gpa_t gpa;
3069
3070 if (vcpu->mmio_read_completed) {
3071 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3072 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3073 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3074 vcpu->mmio_read_completed = 0;
3075 return X86EMUL_CONTINUE;
3076 }
3077
ad312c7c 3078 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 3079
3080 /* For APIC access vmexit */
3081 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3082 goto mmio;
3083
77c2002e
IE		 3084 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
3085 == X86EMUL_CONTINUE)
bbd9b64e
CO		 3086 return X86EMUL_CONTINUE;
3087 if (gpa == UNMAPPED_GVA)
3088 return X86EMUL_PROPAGATE_FAULT;
3089
3090mmio:
3091 /*
3092 * Is this MMIO handled locally?
3093 */
aec51dc4
AK		 3094 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3095 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3096 return X86EMUL_CONTINUE;
3097 }
aec51dc4
AK		 3098
3099 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3100
3101 vcpu->mmio_needed = 1;
3102 vcpu->mmio_phys_addr = gpa;
3103 vcpu->mmio_size = bytes;
3104 vcpu->mmio_is_write = 0;
3105
3106 return X86EMUL_UNHANDLEABLE;
3107}
3108
3200f405 3109int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3110 const void *val, int bytes)
bbd9b64e
CO		 3111{
3112 int ret;
3113
3114 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3115 if (ret < 0)
bbd9b64e 3116 return 0;
ad218f85 3117 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3118 return 1;
3119}
3120
3121static int emulator_write_emulated_onepage(unsigned long addr,
3122 const void *val,
3123 unsigned int bytes,
3124 struct kvm_vcpu *vcpu)
3125{
10589a46
MT		 3126 gpa_t gpa;
3127
10589a46 3128 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 3129
3130 if (gpa == UNMAPPED_GVA) {
c3c91fee 3131 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 3132 return X86EMUL_PROPAGATE_FAULT;
3133 }
3134
3135 /* For APIC access vmexit */
3136 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3137 goto mmio;
3138
3139 if (emulator_write_phys(vcpu, gpa, val, bytes))
3140 return X86EMUL_CONTINUE;
3141
3142mmio:
aec51dc4 3143 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3144 /*
3145 * Is this MMIO handled locally?
3146 */
bda9020e 3147 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3148 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3149
3150 vcpu->mmio_needed = 1;
3151 vcpu->mmio_phys_addr = gpa;
3152 vcpu->mmio_size = bytes;
3153 vcpu->mmio_is_write = 1;
3154 memcpy(vcpu->mmio_data, val, bytes);
3155
3156 return X86EMUL_CONTINUE;
3157}
3158
3159int emulator_write_emulated(unsigned long addr,
3160 const void *val,
3161 unsigned int bytes,
3162 struct kvm_vcpu *vcpu)
3163{
3164 /* Crossing a page boundary? */
3165 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3166 int rc, now;
3167
3168 now = -addr & ~PAGE_MASK;
3169 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3170 if (rc != X86EMUL_CONTINUE)
3171 return rc;
3172 addr += now;
3173 val += now;
3174 bytes -= now;
3175 }
3176 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3177}
3178EXPORT_SYMBOL_GPL(emulator_write_emulated);
3179
3180static int emulator_cmpxchg_emulated(unsigned long addr,
3181 const void *old,
3182 const void *new,
3183 unsigned int bytes,
3184 struct kvm_vcpu *vcpu)
3185{
9f51e24e 3186 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3187#ifndef CONFIG_X86_64
3188 /* guests cmpxchg8b have to be emulated atomically */
3189 if (bytes == 8) {
10589a46 3190 gpa_t gpa;
2bacc55c 3191 struct page *page;
c0b49b0d 3192 char *kaddr;
2bacc55c
MT		 3193 u64 val;
3194
10589a46
MT		 3195 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
3196
2bacc55c
MT		 3197 if (gpa == UNMAPPED_GVA ||
3198 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3199 goto emul_write;
3200
3201 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3202 goto emul_write;
3203
3204 val = *(u64 *)new;
72dc67a6 3205
2bacc55c 3206 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3207
c0b49b0d
AM		 3208 kaddr = kmap_atomic(page, KM_USER0);
3209 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3210 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3211 kvm_release_page_dirty(page);
3212 }
3200f405 3213emul_write:
2bacc55c
MT		 3214#endif
3215
bbd9b64e
CO		 3216 return emulator_write_emulated(addr, new, bytes, vcpu);
3217}
3218
3219static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3220{
3221 return kvm_x86_ops->get_segment_base(vcpu, seg);
3222}
3223
3224int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3225{
a7052897 3226 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3227 return X86EMUL_CONTINUE;
3228}
3229
3230int emulate_clts(struct kvm_vcpu *vcpu)
3231{
4d4ec087 3232 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
bbd9b64e
CO		 3233 return X86EMUL_CONTINUE;
3234}
3235
3236int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3237{
3238 struct kvm_vcpu *vcpu = ctxt->vcpu;
3239
3240 switch (dr) {
3241 case 0 ... 3:
3242 *dest = kvm_x86_ops->get_dr(vcpu, dr);
3243 return X86EMUL_CONTINUE;
3244 default:
b8688d51 3245 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 3246 return X86EMUL_UNHANDLEABLE;
3247 }
3248}
3249
3250int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3251{
3252 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
3253 int exception;
3254
3255 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
3256 if (exception) {
3257 /* FIXME: better handling */
3258 return X86EMUL_UNHANDLEABLE;
3259 }
3260 return X86EMUL_CONTINUE;
3261}
3262
3263void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3264{
bbd9b64e 3265 u8 opcodes[4];
5fdbf976 3266 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3267 unsigned long rip_linear;
3268
f76c710d 3269 if (!printk_ratelimit())
bbd9b64e
CO		 3270 return;
3271
25be4608
GC		 3272 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3273
77c2002e 3274 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 3275
3276 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3277 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3278}
3279EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3280
14af3f3c 3281static struct x86_emulate_ops emulate_ops = {
77c2002e 3282 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 3283 .read_emulated = emulator_read_emulated,
3284 .write_emulated = emulator_write_emulated,
3285 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3286};
3287
5fdbf976
MT		 3288static void cache_all_regs(struct kvm_vcpu *vcpu)
3289{
3290 kvm_register_read(vcpu, VCPU_REGS_RAX);
3291 kvm_register_read(vcpu, VCPU_REGS_RSP);
3292 kvm_register_read(vcpu, VCPU_REGS_RIP);
3293 vcpu->arch.regs_dirty = ~0;
3294}
3295
bbd9b64e 3296int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3297 unsigned long cr2,
3298 u16 error_code,
571008da 3299 int emulation_type)
bbd9b64e 3300{
310b5d30 3301 int r, shadow_mask;
571008da 3302 struct decode_cache *c;
851ba692 3303 struct kvm_run *run = vcpu->run;
bbd9b64e 3304
26eef70c 3305 kvm_clear_exception_queue(vcpu);
ad312c7c 3306 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3307 /*
56e82318 3308 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3309 * instead of direct ->regs accesses, can save hundred cycles
3310 * on Intel for instructions that don't read/change RSP, for
3311 * for example.
3312 */
3313 cache_all_regs(vcpu);
bbd9b64e
CO		 3314
3315 vcpu->mmio_is_write = 0;
ad312c7c 3316 vcpu->arch.pio.string = 0;
bbd9b64e 3317
571008da 3318 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3319 int cs_db, cs_l;
3320 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3321
ad312c7c 3322 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3323 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 3324 vcpu->arch.emulate_ctxt.mode =
3325 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 3326 ? X86EMUL_MODE_REAL : cs_l
3327 ? X86EMUL_MODE_PROT64 : cs_db
3328 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3329
ad312c7c 3330 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3331
0cb5762e
AP		 3332 /* Only allow emulation of specific instructions on #UD
3333 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3334 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3335 if (emulation_type & EMULTYPE_TRAP_UD) {
3336 if (!c->twobyte)
3337 return EMULATE_FAIL;
3338 switch (c->b) {
3339 case 0x01: /* VMMCALL */
3340 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3341 return EMULATE_FAIL;
3342 break;
3343 case 0x34: /* sysenter */
3344 case 0x35: /* sysexit */
3345 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3346 return EMULATE_FAIL;
3347 break;
3348 case 0x05: /* syscall */
3349 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3350 return EMULATE_FAIL;
3351 break;
3352 default:
3353 return EMULATE_FAIL;
3354 }
3355
3356 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3357 return EMULATE_FAIL;
3358 }
571008da 3359
f2b5756b 3360 ++vcpu->stat.insn_emulation;
bbd9b64e 3361 if (r) {
f2b5756b 3362 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3363 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3364 return EMULATE_DONE;
3365 return EMULATE_FAIL;
3366 }
3367 }
3368
ba8afb6b
GN		 3369 if (emulation_type & EMULTYPE_SKIP) {
3370 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3371 return EMULATE_DONE;
3372 }
3373
ad312c7c 3374 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3375 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3376
3377 if (r == 0)
3378 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3379
ad312c7c 3380 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3381 return EMULATE_DO_MMIO;
3382
3383 if ((r || vcpu->mmio_is_write) && run) {
3384 run->exit_reason = KVM_EXIT_MMIO;
3385 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3386 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3387 run->mmio.len = vcpu->mmio_size;
3388 run->mmio.is_write = vcpu->mmio_is_write;
3389 }
3390
3391 if (r) {
3392 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3393 return EMULATE_DONE;
3394 if (!vcpu->mmio_needed) {
3395 kvm_report_emulation_failure(vcpu, "mmio");
3396 return EMULATE_FAIL;
3397 }
3398 return EMULATE_DO_MMIO;
3399 }
3400
91586a3b 3401 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3402
3403 if (vcpu->mmio_is_write) {
3404 vcpu->mmio_needed = 0;
3405 return EMULATE_DO_MMIO;
3406 }
3407
3408 return EMULATE_DONE;
3409}
3410EXPORT_SYMBOL_GPL(emulate_instruction);
3411
de7d789a
CO		 3412static int pio_copy_data(struct kvm_vcpu *vcpu)
3413{
ad312c7c 3414 void *p = vcpu->arch.pio_data;
0f346074 3415 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3416 unsigned bytes;
0f346074 3417 int ret;
de7d789a 3418
ad312c7c
ZX		 3419 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3420 if (vcpu->arch.pio.in)
0f346074 3421 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 3422 else
0f346074
IE		 3423 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3424 return ret;
de7d789a
CO		 3425}
3426
3427int complete_pio(struct kvm_vcpu *vcpu)
3428{
ad312c7c 3429 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3430 long delta;
3431 int r;
5fdbf976 3432 unsigned long val;
de7d789a
CO		 3433
3434 if (!io->string) {
5fdbf976
MT		 3435 if (io->in) {
3436 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3437 memcpy(&val, vcpu->arch.pio_data, io->size);
3438 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3439 }
de7d789a
CO		 3440 } else {
3441 if (io->in) {
3442 r = pio_copy_data(vcpu);
5fdbf976 3443 if (r)
de7d789a 3444 return r;
de7d789a
CO		 3445 }
3446
3447 delta = 1;
3448 if (io->rep) {
3449 delta *= io->cur_count;
3450 /*
3451 * The size of the register should really depend on
3452 * current address size.
3453 */
5fdbf976
MT		 3454 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3455 val -= delta;
3456 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3457 }
3458 if (io->down)
3459 delta = -delta;
3460 delta *= io->size;
5fdbf976
MT		 3461 if (io->in) {
3462 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3463 val += delta;
3464 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3465 } else {
3466 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3467 val += delta;
3468 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3469 }
de7d789a
CO		 3470 }
3471
de7d789a
CO		 3472 io->count -= io->cur_count;
3473 io->cur_count = 0;
3474
3475 return 0;
3476}
3477
bda9020e 3478static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3479{
3480 /* TODO: String I/O for in kernel device */
bda9020e 3481 int r;
de7d789a 3482
ad312c7c 3483 if (vcpu->arch.pio.in)
e93f8a0f 3484 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3485 vcpu->arch.pio.size, pd);
de7d789a 3486 else
e93f8a0f
MT		 3487 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3488 vcpu->arch.pio.port, vcpu->arch.pio.size,
3489 pd);
bda9020e 3490 return r;
de7d789a
CO		 3491}
3492
bda9020e 3493static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3494{
ad312c7c
ZX		 3495 struct kvm_pio_request *io = &vcpu->arch.pio;
3496 void *pd = vcpu->arch.pio_data;
bda9020e 3497 int i, r = 0;
de7d789a 3498
de7d789a 3499 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3500 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3501 io->port, io->size, pd)) {
3502 r = -EOPNOTSUPP;
3503 break;
3504 }
de7d789a
CO		 3505 pd += io->size;
3506 }
bda9020e 3507 return r;
de7d789a
CO		 3508}
3509
851ba692 3510int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3511{
5fdbf976 3512 unsigned long val;
de7d789a
CO		 3513
3514 vcpu->run->exit_reason = KVM_EXIT_IO;
3515 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3516 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3517 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3518 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3519 vcpu->run->io.port = vcpu->arch.pio.port = port;
3520 vcpu->arch.pio.in = in;
3521 vcpu->arch.pio.string = 0;
3522 vcpu->arch.pio.down = 0;
ad312c7c 3523 vcpu->arch.pio.rep = 0;
de7d789a 3524
229456fc
MT		 3525 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3526 size, 1);
2714d1d3 3527
5fdbf976
MT		 3528 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3529 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3530
bda9020e 3531 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3532 complete_pio(vcpu);
3533 return 1;
3534 }
3535 return 0;
3536}
3537EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3538
851ba692 3539int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3540 int size, unsigned long count, int down,
3541 gva_t address, int rep, unsigned port)
3542{
3543 unsigned now, in_page;
0f346074 3544 int ret = 0;
de7d789a
CO		 3545
3546 vcpu->run->exit_reason = KVM_EXIT_IO;
3547 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3548 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3549 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3550 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3551 vcpu->run->io.port = vcpu->arch.pio.port = port;
3552 vcpu->arch.pio.in = in;
3553 vcpu->arch.pio.string = 1;
3554 vcpu->arch.pio.down = down;
ad312c7c 3555 vcpu->arch.pio.rep = rep;
de7d789a 3556
229456fc
MT		 3557 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3558 size, count);
2714d1d3 3559
de7d789a
CO		 3560 if (!count) {
3561 kvm_x86_ops->skip_emulated_instruction(vcpu);
3562 return 1;
3563 }
3564
3565 if (!down)
3566 in_page = PAGE_SIZE - offset_in_page(address);
3567 else
3568 in_page = offset_in_page(address) + size;
3569 now = min(count, (unsigned long)in_page / size);
0f346074 3570 if (!now)
de7d789a 3571 now = 1;
de7d789a
CO		 3572 if (down) {
3573 /*
3574 * String I/O in reverse. Yuck. Kill the guest, fix later.
3575 */
3576 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3577 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3578 return 1;
3579 }
3580 vcpu->run->io.count = now;
ad312c7c 3581 vcpu->arch.pio.cur_count = now;
de7d789a 3582
ad312c7c 3583 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3584 kvm_x86_ops->skip_emulated_instruction(vcpu);
3585
0f346074 3586 vcpu->arch.pio.guest_gva = address;
de7d789a 3587
ad312c7c 3588 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3589 /* string PIO write */
3590 ret = pio_copy_data(vcpu);
0f346074
IE		 3591 if (ret == X86EMUL_PROPAGATE_FAULT) {
3592 kvm_inject_gp(vcpu, 0);
3593 return 1;
3594 }
bda9020e 3595 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3596 complete_pio(vcpu);
ad312c7c 3597 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3598 ret = 1;
3599 }
bda9020e
MT		 3600 }
3601 /* no string PIO read support yet */
de7d789a
CO		 3602
3603 return ret;
3604}
3605EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3606
c8076604
GH		 3607static void bounce_off(void *info)
3608{
3609 /* nothing */
3610}
3611
c8076604
GH		 3612static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3613 void *data)
3614{
3615 struct cpufreq_freqs *freq = data;
3616 struct kvm *kvm;
3617 struct kvm_vcpu *vcpu;
3618 int i, send_ipi = 0;
3619
c8076604
GH		 3620 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3621 return 0;
3622 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3623 return 0;
0cca7907 3624 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3625
3626 spin_lock(&kvm_lock);
3627 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3628 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3629 if (vcpu->cpu != freq->cpu)
3630 continue;
3631 if (!kvm_request_guest_time_update(vcpu))
3632 continue;
3633 if (vcpu->cpu != smp_processor_id())
3634 send_ipi++;
3635 }
3636 }
3637 spin_unlock(&kvm_lock);
3638
3639 if (freq->old < freq->new && send_ipi) {
3640 /*
3641 * We upscale the frequency. Must make the guest
3642 * doesn't see old kvmclock values while running with
3643 * the new frequency, otherwise we risk the guest sees
3644 * time go backwards.
3645 *
3646 * In case we update the frequency for another cpu
3647 * (which might be in guest context) send an interrupt
3648 * to kick the cpu out of guest context. Next time
3649 * guest context is entered kvmclock will be updated,
3650 * so the guest will not see stale values.
3651 */
3652 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3653 }
3654 return 0;
3655}
3656
3657static struct notifier_block kvmclock_cpufreq_notifier_block = {
3658 .notifier_call = kvmclock_cpufreq_notifier
3659};
3660
b820cc0c
ZA		 3661static void kvm_timer_init(void)
3662{
3663 int cpu;
3664
b820cc0c 3665 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3666 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3667 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3668 for_each_online_cpu(cpu) {
3669 unsigned long khz = cpufreq_get(cpu);
3670 if (!khz)
3671 khz = tsc_khz;
3672 per_cpu(cpu_tsc_khz, cpu) = khz;
3673 }
0cca7907
ZA		 3674 } else {
3675 for_each_possible_cpu(cpu)
3676 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3677 }
3678}
3679
f8c16bba 3680int kvm_arch_init(void *opaque)
043405e1 3681{
b820cc0c 3682 int r;
f8c16bba
ZX		 3683 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3684
f8c16bba
ZX		 3685 if (kvm_x86_ops) {
3686 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3687 r = -EEXIST;
3688 goto out;
f8c16bba
ZX		 3689 }
3690
3691 if (!ops->cpu_has_kvm_support()) {
3692 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3693 r = -EOPNOTSUPP;
3694 goto out;
f8c16bba
ZX		 3695 }
3696 if (ops->disabled_by_bios()) {
3697 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3698 r = -EOPNOTSUPP;
3699 goto out;
f8c16bba
ZX		 3700 }
3701
97db56ce
AK		 3702 r = kvm_mmu_module_init();
3703 if (r)
3704 goto out;
3705
3706 kvm_init_msr_list();
3707
f8c16bba 3708 kvm_x86_ops = ops;
56c6d28a 3709 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3710 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3711 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3712 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3713
b820cc0c 3714 kvm_timer_init();
c8076604 3715
f8c16bba 3716 return 0;
56c6d28a
ZX		 3717
3718out:
56c6d28a 3719 return r;
043405e1 3720}
8776e519 3721
f8c16bba
ZX		 3722void kvm_arch_exit(void)
3723{
888d256e
JK		 3724 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3725 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3726 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3727 kvm_x86_ops = NULL;
56c6d28a
ZX		 3728 kvm_mmu_module_exit();
3729}
f8c16bba 3730
8776e519
HB		 3731int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3732{
3733 ++vcpu->stat.halt_exits;
3734 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3735 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3736 return 1;
3737 } else {
3738 vcpu->run->exit_reason = KVM_EXIT_HLT;
3739 return 0;
3740 }
3741}
3742EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3743
2f333bcb
MT		 3744static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3745 unsigned long a1)
3746{
3747 if (is_long_mode(vcpu))
3748 return a0;
3749 else
3750 return a0 | ((gpa_t)a1 << 32);
3751}
3752
55cd8e5a
GN		 3753int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3754{
3755 u64 param, ingpa, outgpa, ret;
3756 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3757 bool fast, longmode;
3758 int cs_db, cs_l;
3759
3760 /*
3761 * hypercall generates UD from non zero cpl and real mode
3762 * per HYPER-V spec
3763 */
3764 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
3765 !kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
3766 kvm_queue_exception(vcpu, UD_VECTOR);
3767 return 0;
3768 }
3769
3770 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3771 longmode = is_long_mode(vcpu) && cs_l == 1;
3772
3773 if (!longmode) {
3774 param = (kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3775 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffff);
3776 ingpa = (kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3777 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffff);
3778 outgpa = (kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3779 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffff);
3780 }
3781#ifdef CONFIG_X86_64
3782 else {
3783 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3784 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3785 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3786 }
3787#endif
3788
3789 code = param & 0xffff;
3790 fast = (param >> 16) & 0x1;
3791 rep_cnt = (param >> 32) & 0xfff;
3792 rep_idx = (param >> 48) & 0xfff;
3793
3794 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3795
3796 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3797
3798 ret = res | (((u64)rep_done & 0xfff) << 32);
3799 if (longmode) {
3800 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3801 } else {
3802 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3803 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3804 }
3805
3806 return 1;
3807}
3808
8776e519
HB		 3809int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3810{
3811 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3812 int r = 1;
8776e519 3813
55cd8e5a
GN		 3814 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3815 return kvm_hv_hypercall(vcpu);
3816
5fdbf976
MT		 3817 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3818 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3819 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3820 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3821 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3822
229456fc 3823 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3824
8776e519
HB		 3825 if (!is_long_mode(vcpu)) {
3826 nr &= 0xFFFFFFFF;
3827 a0 &= 0xFFFFFFFF;
3828 a1 &= 0xFFFFFFFF;
3829 a2 &= 0xFFFFFFFF;
3830 a3 &= 0xFFFFFFFF;
3831 }
3832
07708c4a
JK		 3833 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3834 ret = -KVM_EPERM;
3835 goto out;
3836 }
3837
8776e519 3838 switch (nr) {
b93463aa
AK		 3839 case KVM_HC_VAPIC_POLL_IRQ:
3840 ret = 0;
3841 break;
2f333bcb
MT		 3842 case KVM_HC_MMU_OP:
3843 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3844 break;
8776e519
HB		 3845 default:
3846 ret = -KVM_ENOSYS;
3847 break;
3848 }
07708c4a 3849out:
5fdbf976 3850 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3851 ++vcpu->stat.hypercalls;
2f333bcb 3852 return r;
8776e519
HB		 3853}
3854EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3855
3856int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3857{
3858 char instruction[3];
3859 int ret = 0;
5fdbf976 3860 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3861
8776e519
HB		 3862
3863 /*
3864 * Blow out the MMU to ensure that no other VCPU has an active mapping
3865 * to ensure that the updated hypercall appears atomically across all
3866 * VCPUs.
3867 */
3868 kvm_mmu_zap_all(vcpu->kvm);
3869
8776e519 3870 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3871 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3872 != X86EMUL_CONTINUE)
3873 ret = -EFAULT;
3874
8776e519
HB		 3875 return ret;
3876}
3877
3878static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3879{
3880 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3881}
3882
3883void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3884{
3885 struct descriptor_table dt = { limit, base };
3886
3887 kvm_x86_ops->set_gdt(vcpu, &dt);
3888}
3889
3890void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3891{
3892 struct descriptor_table dt = { limit, base };
3893
3894 kvm_x86_ops->set_idt(vcpu, &dt);
3895}
3896
3897void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3898 unsigned long *rflags)
3899{
2d3ad1f4 3900 kvm_lmsw(vcpu, msw);
91586a3b 3901 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3902}
3903
3904unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3905{
54e445ca
JR		 3906 unsigned long value;
3907
8776e519
HB		 3908 switch (cr) {
3909 case 0:
4d4ec087 3910 value = kvm_read_cr0(vcpu);
54e445ca 3911 break;
8776e519 3912 case 2:
54e445ca
JR		 3913 value = vcpu->arch.cr2;
3914 break;
8776e519 3915 case 3:
54e445ca
JR		 3916 value = vcpu->arch.cr3;
3917 break;
8776e519 3918 case 4:
fc78f519 3919 value = kvm_read_cr4(vcpu);
54e445ca 3920 break;
152ff9be 3921 case 8:
54e445ca
JR		 3922 value = kvm_get_cr8(vcpu);
3923 break;
8776e519 3924 default:
b8688d51 3925 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3926 return 0;
3927 }
54e445ca
JR		 3928
3929 return value;
8776e519
HB		 3930}
3931
3932void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3933 unsigned long *rflags)
3934{
3935 switch (cr) {
3936 case 0:
4d4ec087 3937 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 3938 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3939 break;
3940 case 2:
ad312c7c 3941 vcpu->arch.cr2 = val;
8776e519
HB		 3942 break;
3943 case 3:
2d3ad1f4 3944 kvm_set_cr3(vcpu, val);
8776e519
HB		 3945 break;
3946 case 4:
fc78f519 3947 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 3948 break;
152ff9be 3949 case 8:
2d3ad1f4 3950 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3951 break;
8776e519 3952 default:
b8688d51 3953 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3954 }
3955}
3956
07716717
DK		 3957static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3958{
ad312c7c
ZX		 3959 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3960 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3961
3962 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3963 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3964 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3965 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3966 if (ej->function == e->function) {
3967 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3968 return j;
3969 }
3970 }
3971 return 0; /* silence gcc, even though control never reaches here */
3972}
3973
3974/* find an entry with matching function, matching index (if needed), and that
3975 * should be read next (if it's stateful) */
3976static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3977 u32 function, u32 index)
3978{
3979 if (e->function != function)
3980 return 0;
3981 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3982 return 0;
3983 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3984 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3985 return 0;
3986 return 1;
3987}
3988
d8017474
AG		 3989struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3990 u32 function, u32 index)
8776e519
HB		 3991{
3992 int i;
d8017474 3993 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3994
ad312c7c 3995 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3996 struct kvm_cpuid_entry2 *e;
3997
ad312c7c 3998 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3999 if (is_matching_cpuid_entry(e, function, index)) {
4000 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4001 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4002 best = e;
4003 break;
4004 }
4005 /*
4006 * Both basic or both extended?
4007 */
4008 if (((e->function ^ function) & 0x80000000) == 0)
4009 if (!best || e->function > best->function)
4010 best = e;
4011 }
d8017474
AG		 4012 return best;
4013}
0e851880 4014EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4015
82725b20
DE		 4016int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4017{
4018 struct kvm_cpuid_entry2 *best;
4019
4020 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4021 if (best)
4022 return best->eax & 0xff;
4023 return 36;
4024}
4025
d8017474
AG		 4026void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4027{
4028 u32 function, index;
4029 struct kvm_cpuid_entry2 *best;
4030
4031 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4032 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4033 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4034 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4035 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4036 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4037 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4038 if (best) {
5fdbf976
MT		 4039 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4040 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4041 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4042 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4043 }
8776e519 4044 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4045 trace_kvm_cpuid(function,
4046 kvm_register_read(vcpu, VCPU_REGS_RAX),
4047 kvm_register_read(vcpu, VCPU_REGS_RBX),
4048 kvm_register_read(vcpu, VCPU_REGS_RCX),
4049 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4050}
4051EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4052
b6c7a5dc
HB		 4053/*
4054 * Check if userspace requested an interrupt window, and that the
4055 * interrupt window is open.
4056 *
4057 * No need to exit to userspace if we already have an interrupt queued.
4058 */
851ba692 4059static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4060{
8061823a 4061 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4062 vcpu->run->request_interrupt_window &&
5df56646 4063 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4064}
4065
851ba692 4066static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4067{
851ba692
AK		 4068 struct kvm_run *kvm_run = vcpu->run;
4069
91586a3b 4070 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4071 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4072 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4073 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4074 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4075 else
b6c7a5dc 4076 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4077 kvm_arch_interrupt_allowed(vcpu) &&
4078 !kvm_cpu_has_interrupt(vcpu) &&
4079 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4080}
4081
b93463aa
AK		 4082static void vapic_enter(struct kvm_vcpu *vcpu)
4083{
4084 struct kvm_lapic *apic = vcpu->arch.apic;
4085 struct page *page;
4086
4087 if (!apic || !apic->vapic_addr)
4088 return;
4089
4090 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4091
4092 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4093}
4094
4095static void vapic_exit(struct kvm_vcpu *vcpu)
4096{
4097 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4098 int idx;
b93463aa
AK		 4099
4100 if (!apic || !apic->vapic_addr)
4101 return;
4102
f656ce01 4103 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4104 kvm_release_page_dirty(apic->vapic_page);
4105 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4106 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4107}
4108
95ba8273
GN		 4109static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4110{
4111 int max_irr, tpr;
4112
4113 if (!kvm_x86_ops->update_cr8_intercept)
4114 return;
4115
88c808fd
AK		 4116 if (!vcpu->arch.apic)
4117 return;
4118
8db3baa2
GN		 4119 if (!vcpu->arch.apic->vapic_addr)
4120 max_irr = kvm_lapic_find_highest_irr(vcpu);
4121 else
4122 max_irr = -1;
95ba8273
GN		 4123
4124 if (max_irr != -1)
4125 max_irr >>= 4;
4126
4127 tpr = kvm_lapic_get_cr8(vcpu);
4128
4129 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4130}
4131
851ba692 4132static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4133{
4134 /* try to reinject previous events if any */
b59bb7bd
GN		 4135 if (vcpu->arch.exception.pending) {
4136 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4137 vcpu->arch.exception.has_error_code,
4138 vcpu->arch.exception.error_code);
4139 return;
4140 }
4141
95ba8273
GN		 4142 if (vcpu->arch.nmi_injected) {
4143 kvm_x86_ops->set_nmi(vcpu);
4144 return;
4145 }
4146
4147 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4148 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4149 return;
4150 }
4151
4152 /* try to inject new event if pending */
4153 if (vcpu->arch.nmi_pending) {
4154 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4155 vcpu->arch.nmi_pending = false;
4156 vcpu->arch.nmi_injected = true;
4157 kvm_x86_ops->set_nmi(vcpu);
4158 }
4159 } else if (kvm_cpu_has_interrupt(vcpu)) {
4160 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4161 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4162 false);
4163 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4164 }
4165 }
4166}
4167
851ba692 4168static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4169{
4170 int r;
6a8b1d13 4171 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4172 vcpu->run->request_interrupt_window;
b6c7a5dc 4173
2e53d63a
MT		 4174 if (vcpu->requests)
4175 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4176 kvm_mmu_unload(vcpu);
4177
b6c7a5dc
HB		 4178 r = kvm_mmu_reload(vcpu);
4179 if (unlikely(r))
4180 goto out;
4181
2f52d58c
AK		 4182 if (vcpu->requests) {
4183 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4184 __kvm_migrate_timers(vcpu);
c8076604
GH		 4185 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4186 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4187 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4188 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4189 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4190 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4191 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4192 &vcpu->requests)) {
851ba692 4193 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4194 r = 0;
4195 goto out;
4196 }
71c4dfaf 4197 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4198 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4199 r = 0;
4200 goto out;
4201 }
02daab21
AK		 4202 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4203 vcpu->fpu_active = 0;
4204 kvm_x86_ops->fpu_deactivate(vcpu);
4205 }
2f52d58c 4206 }
b93463aa 4207
b6c7a5dc
HB		 4208 preempt_disable();
4209
4210 kvm_x86_ops->prepare_guest_switch(vcpu);
4211 kvm_load_guest_fpu(vcpu);
4212
4213 local_irq_disable();
4214
32f88400
MT		 4215 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4216 smp_mb__after_clear_bit();
4217
d7690175 4218 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4219 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4220 local_irq_enable();
4221 preempt_enable();
4222 r = 1;
4223 goto out;
4224 }
4225
851ba692 4226 inject_pending_event(vcpu);
b6c7a5dc 4227
6a8b1d13
GN		 4228 /* enable NMI/IRQ window open exits if needed */
4229 if (vcpu->arch.nmi_pending)
4230 kvm_x86_ops->enable_nmi_window(vcpu);
4231 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4232 kvm_x86_ops->enable_irq_window(vcpu);
4233
95ba8273 4234 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4235 update_cr8_intercept(vcpu);
4236 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4237 }
b93463aa 4238
f656ce01 4239 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4240
b6c7a5dc
HB		 4241 kvm_guest_enter();
4242
42dbaa5a 4243 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4244 set_debugreg(0, 7);
4245 set_debugreg(vcpu->arch.eff_db[0], 0);
4246 set_debugreg(vcpu->arch.eff_db[1], 1);
4247 set_debugreg(vcpu->arch.eff_db[2], 2);
4248 set_debugreg(vcpu->arch.eff_db[3], 3);
4249 }
b6c7a5dc 4250
229456fc 4251 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4252 kvm_x86_ops->run(vcpu);
b6c7a5dc 4253
24f1e32c
FW		 4254 /*
4255 * If the guest has used debug registers, at least dr7
4256 * will be disabled while returning to the host.
4257 * If we don't have active breakpoints in the host, we don't
4258 * care about the messed up debug address registers. But if
4259 * we have some of them active, restore the old state.
4260 */
59d8eb53 4261 if (hw_breakpoint_active())
24f1e32c 4262 hw_breakpoint_restore();
42dbaa5a 4263
32f88400 4264 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4265 local_irq_enable();
4266
4267 ++vcpu->stat.exits;
4268
4269 /*
4270 * We must have an instruction between local_irq_enable() and
4271 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4272 * the interrupt shadow. The stat.exits increment will do nicely.
4273 * But we need to prevent reordering, hence this barrier():
4274 */
4275 barrier();
4276
4277 kvm_guest_exit();
4278
4279 preempt_enable();
4280
f656ce01 4281 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4282
b6c7a5dc
HB		 4283 /*
4284 * Profile KVM exit RIPs:
4285 */
4286 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4287 unsigned long rip = kvm_rip_read(vcpu);
4288 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4289 }
4290
298101da 4291
b93463aa
AK		 4292 kvm_lapic_sync_from_vapic(vcpu);
4293
851ba692 4294 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4295out:
4296 return r;
4297}
b6c7a5dc 4298
09cec754 4299
851ba692 4300static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4301{
4302 int r;
f656ce01 4303 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4304
4305 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4306 pr_debug("vcpu %d received sipi with vector # %x\n",
4307 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4308 kvm_lapic_reset(vcpu);
5f179287 4309 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4310 if (r)
4311 return r;
4312 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4313 }
4314
f656ce01 4315 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4316 vapic_enter(vcpu);
4317
4318 r = 1;
4319 while (r > 0) {
af2152f5 4320 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4321 r = vcpu_enter_guest(vcpu);
d7690175 4322 else {
f656ce01 4323 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4324 kvm_vcpu_block(vcpu);
f656ce01 4325 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4326 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4327 {
4328 switch(vcpu->arch.mp_state) {
4329 case KVM_MP_STATE_HALTED:
d7690175 4330 vcpu->arch.mp_state =
09cec754
GN		 4331 KVM_MP_STATE_RUNNABLE;
4332 case KVM_MP_STATE_RUNNABLE:
4333 break;
4334 case KVM_MP_STATE_SIPI_RECEIVED:
4335 default:
4336 r = -EINTR;
4337 break;
4338 }
4339 }
d7690175
MT		 4340 }
4341
09cec754
GN		 4342 if (r <= 0)
4343 break;
4344
4345 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4346 if (kvm_cpu_has_pending_timer(vcpu))
4347 kvm_inject_pending_timer_irqs(vcpu);
4348
851ba692 4349 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4350 r = -EINTR;
851ba692 4351 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4352 ++vcpu->stat.request_irq_exits;
4353 }
4354 if (signal_pending(current)) {
4355 r = -EINTR;
851ba692 4356 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4357 ++vcpu->stat.signal_exits;
4358 }
4359 if (need_resched()) {
f656ce01 4360 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4361 kvm_resched(vcpu);
f656ce01 4362 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4363 }
b6c7a5dc
HB		 4364 }
4365
f656ce01 4366 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4367 post_kvm_run_save(vcpu);
b6c7a5dc 4368
b93463aa
AK		 4369 vapic_exit(vcpu);
4370
b6c7a5dc
HB		 4371 return r;
4372}
4373
4374int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4375{
4376 int r;
4377 sigset_t sigsaved;
4378
4379 vcpu_load(vcpu);
4380
ac9f6dc0
AK		 4381 if (vcpu->sigset_active)
4382 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4383
a4535290 4384 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4385 kvm_vcpu_block(vcpu);
d7690175 4386 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4387 r = -EAGAIN;
4388 goto out;
b6c7a5dc
HB		 4389 }
4390
b6c7a5dc
HB		 4391 /* re-sync apic's tpr */
4392 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4393 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4394
ad312c7c 4395 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4396 r = complete_pio(vcpu);
4397 if (r)
4398 goto out;
4399 }
b6c7a5dc
HB		 4400 if (vcpu->mmio_needed) {
4401 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4402 vcpu->mmio_read_completed = 1;
4403 vcpu->mmio_needed = 0;
3200f405 4404
f656ce01 4405 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4406 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4407 EMULTYPE_NO_DECODE);
f656ce01 4408 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4409 if (r == EMULATE_DO_MMIO) {
4410 /*
4411 * Read-modify-write. Back to userspace.
4412 */
4413 r = 0;
4414 goto out;
4415 }
4416 }
5fdbf976
MT		 4417 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4418 kvm_register_write(vcpu, VCPU_REGS_RAX,
4419 kvm_run->hypercall.ret);
b6c7a5dc 4420
851ba692 4421 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4422
4423out:
4424 if (vcpu->sigset_active)
4425 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4426
4427 vcpu_put(vcpu);
4428 return r;
4429}
4430
4431int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4432{
4433 vcpu_load(vcpu);
4434
5fdbf976
MT		 4435 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4436 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4437 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4438 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4439 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4440 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4441 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4442 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4443#ifdef CONFIG_X86_64
5fdbf976
MT		 4444 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4445 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4446 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4447 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4448 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4449 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4450 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4451 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4452#endif
4453
5fdbf976 4454 regs->rip = kvm_rip_read(vcpu);
91586a3b 4455 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4456
4457 vcpu_put(vcpu);
4458
4459 return 0;
4460}
4461
4462int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4463{
4464 vcpu_load(vcpu);
4465
5fdbf976
MT		 4466 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4467 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4468 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4469 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4470 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4471 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4472 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4473 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4474#ifdef CONFIG_X86_64
5fdbf976
MT		 4475 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4476 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4477 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4478 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4479 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4480 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4481 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4482 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4483#endif
4484
5fdbf976 4485 kvm_rip_write(vcpu, regs->rip);
91586a3b 4486 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4487
b4f14abd
JK		 4488 vcpu->arch.exception.pending = false;
4489
b6c7a5dc
HB		 4490 vcpu_put(vcpu);
4491
4492 return 0;
4493}
4494
3e6e0aab
GT		 4495void kvm_get_segment(struct kvm_vcpu *vcpu,
4496 struct kvm_segment *var, int seg)
b6c7a5dc 4497{
14af3f3c 4498 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4499}
4500
4501void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4502{
4503 struct kvm_segment cs;
4504
3e6e0aab 4505 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4506 *db = cs.db;
4507 *l = cs.l;
4508}
4509EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4510
4511int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4512 struct kvm_sregs *sregs)
4513{
4514 struct descriptor_table dt;
b6c7a5dc
HB		 4515
4516 vcpu_load(vcpu);
4517
3e6e0aab
GT		 4518 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4519 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4520 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4521 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4522 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4523 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4524
3e6e0aab
GT		 4525 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4526 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4527
4528 kvm_x86_ops->get_idt(vcpu, &dt);
4529 sregs->idt.limit = dt.limit;
4530 sregs->idt.base = dt.base;
4531 kvm_x86_ops->get_gdt(vcpu, &dt);
4532 sregs->gdt.limit = dt.limit;
4533 sregs->gdt.base = dt.base;
4534
4d4ec087 4535 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4536 sregs->cr2 = vcpu->arch.cr2;
4537 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4538 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4539 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 4540 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 4541 sregs->apic_base = kvm_get_apic_base(vcpu);
4542
923c61bb 4543 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4544
36752c9b 4545 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4546 set_bit(vcpu->arch.interrupt.nr,
4547 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4548
b6c7a5dc
HB		 4549 vcpu_put(vcpu);
4550
4551 return 0;
4552}
4553
62d9f0db
MT		 4554int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4555 struct kvm_mp_state *mp_state)
4556{
4557 vcpu_load(vcpu);
4558 mp_state->mp_state = vcpu->arch.mp_state;
4559 vcpu_put(vcpu);
4560 return 0;
4561}
4562
4563int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4564 struct kvm_mp_state *mp_state)
4565{
4566 vcpu_load(vcpu);
4567 vcpu->arch.mp_state = mp_state->mp_state;
4568 vcpu_put(vcpu);
4569 return 0;
4570}
4571
3e6e0aab 4572static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4573 struct kvm_segment *var, int seg)
4574{
14af3f3c 4575 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4576}
4577
37817f29
IE		 4578static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4579 struct kvm_segment *kvm_desct)
4580{
46a359e7
AM		 4581 kvm_desct->base = get_desc_base(seg_desc);
4582 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4583 if (seg_desc->g) {
4584 kvm_desct->limit <<= 12;
4585 kvm_desct->limit |= 0xfff;
4586 }
37817f29
IE		 4587 kvm_desct->selector = selector;
4588 kvm_desct->type = seg_desc->type;
4589 kvm_desct->present = seg_desc->p;
4590 kvm_desct->dpl = seg_desc->dpl;
4591 kvm_desct->db = seg_desc->d;
4592 kvm_desct->s = seg_desc->s;
4593 kvm_desct->l = seg_desc->l;
4594 kvm_desct->g = seg_desc->g;
4595 kvm_desct->avl = seg_desc->avl;
4596 if (!selector)
4597 kvm_desct->unusable = 1;
4598 else
4599 kvm_desct->unusable = 0;
4600 kvm_desct->padding = 0;
4601}
4602
b8222ad2
AS		 4603static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4604 u16 selector,
4605 struct descriptor_table *dtable)
37817f29
IE		 4606{
4607 if (selector & 1 << 2) {
4608 struct kvm_segment kvm_seg;
4609
3e6e0aab 4610 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4611
4612 if (kvm_seg.unusable)
4613 dtable->limit = 0;
4614 else
4615 dtable->limit = kvm_seg.limit;
4616 dtable->base = kvm_seg.base;
4617 }
4618 else
4619 kvm_x86_ops->get_gdt(vcpu, dtable);
4620}
4621
4622/* allowed just for 8 bytes segments */
4623static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4624 struct desc_struct *seg_desc)
4625{
4626 struct descriptor_table dtable;
4627 u16 index = selector >> 3;
4628
b8222ad2 4629 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4630
4631 if (dtable.limit < index * 8 + 7) {
4632 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4633 return 1;
4634 }
d9048d32 4635 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4636}
4637
4638/* allowed just for 8 bytes segments */
4639static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4640 struct desc_struct *seg_desc)
4641{
4642 struct descriptor_table dtable;
4643 u16 index = selector >> 3;
4644
b8222ad2 4645 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4646
4647 if (dtable.limit < index * 8 + 7)
4648 return 1;
d9048d32 4649 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4650}
4651
abb39119 4652static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4653 struct desc_struct *seg_desc)
4654{
46a359e7 4655 u32 base_addr = get_desc_base(seg_desc);
37817f29 4656
98899aa0 4657 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4658}
4659
37817f29
IE		 4660static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4661{
4662 struct kvm_segment kvm_seg;
4663
3e6e0aab 4664 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4665 return kvm_seg.selector;
4666}
4667
4668static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4669 u16 selector,
4670 struct kvm_segment *kvm_seg)
4671{
4672 struct desc_struct seg_desc;
4673
4674 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4675 return 1;
4676 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4677 return 0;
4678}
4679
2259e3a7 4680static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4681{
4682 struct kvm_segment segvar = {
4683 .base = selector << 4,
4684 .limit = 0xffff,
4685 .selector = selector,
4686 .type = 3,
4687 .present = 1,
4688 .dpl = 3,
4689 .db = 0,
4690 .s = 1,
4691 .l = 0,
4692 .g = 0,
4693 .avl = 0,
4694 .unusable = 0,
4695 };
4696 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4697 return 0;
4698}
4699
c0c7c04b
AL		 4700static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4701{
4702 return (seg != VCPU_SREG_LDTR) &&
4703 (seg != VCPU_SREG_TR) &&
91586a3b 4704 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4705}
4706
cb84b55f
MT		 4707static void kvm_check_segment_descriptor(struct kvm_vcpu *vcpu, int seg,
4708 u16 selector)
4709{
4710 /* NULL selector is not valid for CS and SS */
4711 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4712 if (!selector)
4713 kvm_queue_exception_e(vcpu, TS_VECTOR, selector >> 3);
4714}
4715
3e6e0aab
GT		 4716int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4717 int type_bits, int seg)
37817f29
IE		 4718{
4719 struct kvm_segment kvm_seg;
4720
4d4ec087 4721 if (is_vm86_segment(vcpu, seg) || !(kvm_read_cr0_bits(vcpu, X86_CR0_PE)))
f4bbd9aa 4722 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4723 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4724 return 1;
cb84b55f
MT		 4725
4726 kvm_check_segment_descriptor(vcpu, seg, selector);
37817f29
IE		 4727 kvm_seg.type |= type_bits;
4728
4729 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4730 seg != VCPU_SREG_LDTR)
4731 if (!kvm_seg.s)
4732 kvm_seg.unusable = 1;
4733
3e6e0aab 4734 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4735 return 0;
4736}
4737
4738static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4739 struct tss_segment_32 *tss)
4740{
4741 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4742 tss->eip = kvm_rip_read(vcpu);
91586a3b 4743 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4744 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4745 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4746 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4747 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4748 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4749 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4750 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4751 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4752 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4753 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4754 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4755 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4756 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4757 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4758 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4759}
4760
4761static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4762 struct tss_segment_32 *tss)
4763{
4764 kvm_set_cr3(vcpu, tss->cr3);
4765
5fdbf976 4766 kvm_rip_write(vcpu, tss->eip);
91586a3b 4767 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4768
5fdbf976
MT		 4769 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4770 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4771 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4772 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4773 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4774 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4775 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4776 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4777
3e6e0aab 4778 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4779 return 1;
4780
3e6e0aab 4781 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4782 return 1;
4783
3e6e0aab 4784 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4785 return 1;
4786
3e6e0aab 4787 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4788 return 1;
4789
3e6e0aab 4790 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4791 return 1;
4792
3e6e0aab 4793 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4794 return 1;
4795
3e6e0aab 4796 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4797 return 1;
4798 return 0;
4799}
4800
4801static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4802 struct tss_segment_16 *tss)
4803{
5fdbf976 4804 tss->ip = kvm_rip_read(vcpu);
91586a3b 4805 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4806 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4807 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4808 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4809 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4810 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4811 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4812 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4813 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4814
4815 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4816 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4817 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4818 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4819 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4820}
4821
4822static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4823 struct tss_segment_16 *tss)
4824{
5fdbf976 4825 kvm_rip_write(vcpu, tss->ip);
91586a3b 4826 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4827 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4828 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4829 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4830 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4831 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4832 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4833 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4834 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4835
3e6e0aab 4836 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4837 return 1;
4838
3e6e0aab 4839 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4840 return 1;
4841
3e6e0aab 4842 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4843 return 1;
4844
3e6e0aab 4845 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4846 return 1;
4847
3e6e0aab 4848 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4849 return 1;
4850 return 0;
4851}
4852
8b2cf73c 4853static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4854 u16 old_tss_sel, u32 old_tss_base,
4855 struct desc_struct *nseg_desc)
37817f29
IE		 4856{
4857 struct tss_segment_16 tss_segment_16;
4858 int ret = 0;
4859
34198bf8
MT		 4860 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4861 sizeof tss_segment_16))
37817f29
IE		 4862 goto out;
4863
4864 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4865
34198bf8
MT		 4866 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4867 sizeof tss_segment_16))
37817f29 4868 goto out;
34198bf8
MT		 4869
4870 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4871 &tss_segment_16, sizeof tss_segment_16))
4872 goto out;
4873
b237ac37
GN		 4874 if (old_tss_sel != 0xffff) {
4875 tss_segment_16.prev_task_link = old_tss_sel;
4876
4877 if (kvm_write_guest(vcpu->kvm,
4878 get_tss_base_addr(vcpu, nseg_desc),
4879 &tss_segment_16.prev_task_link,
4880 sizeof tss_segment_16.prev_task_link))
4881 goto out;
4882 }
4883
37817f29
IE		 4884 if (load_state_from_tss16(vcpu, &tss_segment_16))
4885 goto out;
4886
4887 ret = 1;
4888out:
4889 return ret;
4890}
4891
8b2cf73c 4892static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4893 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4894 struct desc_struct *nseg_desc)
4895{
4896 struct tss_segment_32 tss_segment_32;
4897 int ret = 0;
4898
34198bf8
MT		 4899 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4900 sizeof tss_segment_32))
37817f29
IE		 4901 goto out;
4902
4903 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4904
34198bf8
MT		 4905 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4906 sizeof tss_segment_32))
4907 goto out;
4908
4909 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4910 &tss_segment_32, sizeof tss_segment_32))
37817f29 4911 goto out;
34198bf8 4912
b237ac37
GN		 4913 if (old_tss_sel != 0xffff) {
4914 tss_segment_32.prev_task_link = old_tss_sel;
4915
4916 if (kvm_write_guest(vcpu->kvm,
4917 get_tss_base_addr(vcpu, nseg_desc),
4918 &tss_segment_32.prev_task_link,
4919 sizeof tss_segment_32.prev_task_link))
4920 goto out;
4921 }
4922
37817f29
IE		 4923 if (load_state_from_tss32(vcpu, &tss_segment_32))
4924 goto out;
4925
4926 ret = 1;
4927out:
4928 return ret;
4929}
4930
4931int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4932{
4933 struct kvm_segment tr_seg;
4934 struct desc_struct cseg_desc;
4935 struct desc_struct nseg_desc;
4936 int ret = 0;
34198bf8
MT		 4937 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4938 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4939
34198bf8 4940 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4941
34198bf8
MT		 4942 /* FIXME: Handle errors. Failure to read either TSS or their
4943 * descriptors should generate a pagefault.
4944 */
37817f29
IE		 4945 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4946 goto out;
4947
34198bf8 4948 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4949 goto out;
4950
37817f29
IE		 4951 if (reason != TASK_SWITCH_IRET) {
4952 int cpl;
4953
4954 cpl = kvm_x86_ops->get_cpl(vcpu);
4955 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4956 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4957 return 1;
4958 }
4959 }
4960
46a359e7 4961 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4962 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4963 return 1;
4964 }
4965
4966 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4967 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4968 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4969 }
4970
4971 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4972 u32 eflags = kvm_get_rflags(vcpu);
4973 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4974 }
4975
b237ac37
GN		 4976 /* set back link to prev task only if NT bit is set in eflags
4977 note that old_tss_sel is not used afetr this point */
4978 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4979 old_tss_sel = 0xffff;
4980
37817f29 4981 if (nseg_desc.type & 8)
b237ac37
GN		 4982 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4983 old_tss_base, &nseg_desc);
37817f29 4984 else
b237ac37
GN		 4985 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4986 old_tss_base, &nseg_desc);
37817f29
IE		 4987
4988 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4989 u32 eflags = kvm_get_rflags(vcpu);
4990 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4991 }
4992
4993 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4994 nseg_desc.type |= (1 << 1);
37817f29
IE		 4995 save_guest_segment_descriptor(vcpu, tss_selector,
4996 &nseg_desc);
4997 }
4998
4d4ec087 4999 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5000 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5001 tr_seg.type = 11;
3e6e0aab 5002 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5003out:
37817f29
IE		 5004 return ret;
5005}
5006EXPORT_SYMBOL_GPL(kvm_task_switch);
5007
b6c7a5dc
HB		 5008int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5009 struct kvm_sregs *sregs)
5010{
5011 int mmu_reset_needed = 0;
923c61bb 5012 int pending_vec, max_bits;
b6c7a5dc
HB		 5013 struct descriptor_table dt;
5014
5015 vcpu_load(vcpu);
5016
5017 dt.limit = sregs->idt.limit;
5018 dt.base = sregs->idt.base;
5019 kvm_x86_ops->set_idt(vcpu, &dt);
5020 dt.limit = sregs->gdt.limit;
5021 dt.base = sregs->gdt.base;
5022 kvm_x86_ops->set_gdt(vcpu, &dt);
5023
ad312c7c
ZX		 5024 vcpu->arch.cr2 = sregs->cr2;
5025 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5026 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5027
2d3ad1f4 5028 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5029
ad312c7c 5030 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 5031 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5032 kvm_set_apic_base(vcpu, sregs->apic_base);
5033
4d4ec087 5034 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5035 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5036 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5037
fc78f519 5038 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5039 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5040 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5041 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5042 mmu_reset_needed = 1;
5043 }
b6c7a5dc
HB		 5044
5045 if (mmu_reset_needed)
5046 kvm_mmu_reset_context(vcpu);
5047
923c61bb
GN		 5048 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5049 pending_vec = find_first_bit(
5050 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5051 if (pending_vec < max_bits) {
66fd3f7f 5052 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5053 pr_debug("Set back pending irq %d\n", pending_vec);
5054 if (irqchip_in_kernel(vcpu->kvm))
5055 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5056 }
5057
3e6e0aab
GT		 5058 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5059 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5060 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5061 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5062 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5063 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5064
3e6e0aab
GT		 5065 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5066 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5067
5f0269f5
ME		 5068 update_cr8_intercept(vcpu);
5069
9c3e4aab 5070 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5071 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5072 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4d4ec087 5073 !(kvm_read_cr0_bits(vcpu, X86_CR0_PE)))
9c3e4aab
MT		 5074 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5075
b6c7a5dc
HB		 5076 vcpu_put(vcpu);
5077
5078 return 0;
5079}
5080
d0bfb940
JK		 5081int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5082 struct kvm_guest_debug *dbg)
b6c7a5dc 5083{
355be0b9 5084 unsigned long rflags;
ae675ef0 5085 int i, r;
b6c7a5dc
HB		 5086
5087 vcpu_load(vcpu);
5088
4f926bf2
JK		 5089 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5090 r = -EBUSY;
5091 if (vcpu->arch.exception.pending)
5092 goto unlock_out;
5093 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5094 kvm_queue_exception(vcpu, DB_VECTOR);
5095 else
5096 kvm_queue_exception(vcpu, BP_VECTOR);
5097 }
5098
91586a3b
JK		 5099 /*
5100 * Read rflags as long as potentially injected trace flags are still
5101 * filtered out.
5102 */
5103 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5104
5105 vcpu->guest_debug = dbg->control;
5106 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5107 vcpu->guest_debug = 0;
5108
5109 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5110 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5111 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5112 vcpu->arch.switch_db_regs =
5113 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5114 } else {
5115 for (i = 0; i < KVM_NR_DB_REGS; i++)
5116 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5117 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5118 }
5119
94fe45da
JK		 5120 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5121 vcpu->arch.singlestep_cs =
5122 get_segment_selector(vcpu, VCPU_SREG_CS);
5123 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
5124 }
5125
91586a3b
JK		 5126 /*
5127 * Trigger an rflags update that will inject or remove the trace
5128 * flags.
5129 */
5130 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5131
355be0b9 5132 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5133
4f926bf2 5134 r = 0;
d0bfb940 5135
4f926bf2 5136unlock_out:
b6c7a5dc
HB		 5137 vcpu_put(vcpu);
5138
5139 return r;
5140}
5141
d0752060
HB		 5142/*
5143 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5144 * we have asm/x86/processor.h
5145 */
5146struct fxsave {
5147 u16 cwd;
5148 u16 swd;
5149 u16 twd;
5150 u16 fop;
5151 u64 rip;
5152 u64 rdp;
5153 u32 mxcsr;
5154 u32 mxcsr_mask;
5155 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5156#ifdef CONFIG_X86_64
5157 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5158#else
5159 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5160#endif
5161};
5162
8b006791
ZX		 5163/*
5164 * Translate a guest virtual address to a guest physical address.
5165 */
5166int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5167 struct kvm_translation *tr)
5168{
5169 unsigned long vaddr = tr->linear_address;
5170 gpa_t gpa;
f656ce01 5171 int idx;
8b006791
ZX		 5172
5173 vcpu_load(vcpu);
f656ce01 5174 idx = srcu_read_lock(&vcpu->kvm->srcu);
ad312c7c 5175 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
f656ce01 5176 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5177 tr->physical_address = gpa;
5178 tr->valid = gpa != UNMAPPED_GVA;
5179 tr->writeable = 1;
5180 tr->usermode = 0;
8b006791
ZX		 5181 vcpu_put(vcpu);
5182
5183 return 0;
5184}
5185
d0752060
HB		 5186int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5187{
ad312c7c 5188 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5189
5190 vcpu_load(vcpu);
5191
5192 memcpy(fpu->fpr, fxsave->st_space, 128);
5193 fpu->fcw = fxsave->cwd;
5194 fpu->fsw = fxsave->swd;
5195 fpu->ftwx = fxsave->twd;
5196 fpu->last_opcode = fxsave->fop;
5197 fpu->last_ip = fxsave->rip;
5198 fpu->last_dp = fxsave->rdp;
5199 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5200
5201 vcpu_put(vcpu);
5202
5203 return 0;
5204}
5205
5206int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5207{
ad312c7c 5208 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5209
5210 vcpu_load(vcpu);
5211
5212 memcpy(fxsave->st_space, fpu->fpr, 128);
5213 fxsave->cwd = fpu->fcw;
5214 fxsave->swd = fpu->fsw;
5215 fxsave->twd = fpu->ftwx;
5216 fxsave->fop = fpu->last_opcode;
5217 fxsave->rip = fpu->last_ip;
5218 fxsave->rdp = fpu->last_dp;
5219 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5220
5221 vcpu_put(vcpu);
5222
5223 return 0;
5224}
5225
5226void fx_init(struct kvm_vcpu *vcpu)
5227{
5228 unsigned after_mxcsr_mask;
5229
bc1a34f1
AA		 5230 /*
5231 * Touch the fpu the first time in non atomic context as if
5232 * this is the first fpu instruction the exception handler
5233 * will fire before the instruction returns and it'll have to
5234 * allocate ram with GFP_KERNEL.
5235 */
5236 if (!used_math())
d6e88aec 5237 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5238
d0752060
HB		 5239 /* Initialize guest FPU by resetting ours and saving into guest's */
5240 preempt_disable();
d6e88aec
AK		 5241 kvm_fx_save(&vcpu->arch.host_fx_image);
5242 kvm_fx_finit();
5243 kvm_fx_save(&vcpu->arch.guest_fx_image);
5244 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5245 preempt_enable();
5246
ad312c7c 5247 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5248 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5249 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5250 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5251 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5252}
5253EXPORT_SYMBOL_GPL(fx_init);
5254
5255void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5256{
5257 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
5258 return;
5259
5260 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5261 kvm_fx_save(&vcpu->arch.host_fx_image);
5262 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 5263}
5264EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
5265
5266void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5267{
5268 if (!vcpu->guest_fpu_loaded)
5269 return;
5270
5271 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5272 kvm_fx_save(&vcpu->arch.guest_fx_image);
5273 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5274 ++vcpu->stat.fpu_reload;
02daab21 5275 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
d0752060
HB		 5276}
5277EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 5278
5279void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5280{
7f1ea208
JR		 5281 if (vcpu->arch.time_page) {
5282 kvm_release_page_dirty(vcpu->arch.time_page);
5283 vcpu->arch.time_page = NULL;
5284 }
5285
e9b11c17
ZX		 5286 kvm_x86_ops->vcpu_free(vcpu);
5287}
5288
5289struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5290 unsigned int id)
5291{
26e5215f
AK		 5292 return kvm_x86_ops->vcpu_create(kvm, id);
5293}
e9b11c17 5294
26e5215f
AK		 5295int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5296{
5297 int r;
e9b11c17
ZX		 5298
5299 /* We do fxsave: this must be aligned. */
ad312c7c 5300 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5301
0bed3b56 5302 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5303 vcpu_load(vcpu);
5304 r = kvm_arch_vcpu_reset(vcpu);
5305 if (r == 0)
5306 r = kvm_mmu_setup(vcpu);
5307 vcpu_put(vcpu);
5308 if (r < 0)
5309 goto free_vcpu;
5310
26e5215f 5311 return 0;
e9b11c17
ZX		 5312free_vcpu:
5313 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5314 return r;
e9b11c17
ZX		 5315}
5316
d40ccc62 5317void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5318{
5319 vcpu_load(vcpu);
5320 kvm_mmu_unload(vcpu);
5321 vcpu_put(vcpu);
5322
5323 kvm_x86_ops->vcpu_free(vcpu);
5324}
5325
5326int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5327{
448fa4a9
JK		 5328 vcpu->arch.nmi_pending = false;
5329 vcpu->arch.nmi_injected = false;
5330
42dbaa5a
JK		 5331 vcpu->arch.switch_db_regs = 0;
5332 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5333 vcpu->arch.dr6 = DR6_FIXED_1;
5334 vcpu->arch.dr7 = DR7_FIXED_1;
5335
e9b11c17
ZX		 5336 return kvm_x86_ops->vcpu_reset(vcpu);
5337}
5338
10474ae8 5339int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5340{
0cca7907
ZA		 5341 /*
5342 * Since this may be called from a hotplug notifcation,
5343 * we can't get the CPU frequency directly.
5344 */
5345 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5346 int cpu = raw_smp_processor_id();
5347 per_cpu(cpu_tsc_khz, cpu) = 0;
5348 }
18863bdd
AK		 5349
5350 kvm_shared_msr_cpu_online();
5351
10474ae8 5352 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5353}
5354
5355void kvm_arch_hardware_disable(void *garbage)
5356{
5357 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5358 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5359}
5360
5361int kvm_arch_hardware_setup(void)
5362{
5363 return kvm_x86_ops->hardware_setup();
5364}
5365
5366void kvm_arch_hardware_unsetup(void)
5367{
5368 kvm_x86_ops->hardware_unsetup();
5369}
5370
5371void kvm_arch_check_processor_compat(void *rtn)
5372{
5373 kvm_x86_ops->check_processor_compatibility(rtn);
5374}
5375
5376int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5377{
5378 struct page *page;
5379 struct kvm *kvm;
5380 int r;
5381
5382 BUG_ON(vcpu->kvm == NULL);
5383 kvm = vcpu->kvm;
5384
ad312c7c 5385 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5386 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5387 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5388 else
a4535290 5389 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5390
5391 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5392 if (!page) {
5393 r = -ENOMEM;
5394 goto fail;
5395 }
ad312c7c 5396 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5397
5398 r = kvm_mmu_create(vcpu);
5399 if (r < 0)
5400 goto fail_free_pio_data;
5401
5402 if (irqchip_in_kernel(kvm)) {
5403 r = kvm_create_lapic(vcpu);
5404 if (r < 0)
5405 goto fail_mmu_destroy;
5406 }
5407
890ca9ae
HY		 5408 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5409 GFP_KERNEL);
5410 if (!vcpu->arch.mce_banks) {
5411 r = -ENOMEM;
443c39bc 5412 goto fail_free_lapic;
890ca9ae
HY		 5413 }
5414 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5415
e9b11c17 5416 return 0;
443c39bc
WY		 5417fail_free_lapic:
5418 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5419fail_mmu_destroy:
5420 kvm_mmu_destroy(vcpu);
5421fail_free_pio_data:
ad312c7c 5422 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5423fail:
5424 return r;
5425}
5426
5427void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5428{
f656ce01
MT		 5429 int idx;
5430
36cb93fd 5431 kfree(vcpu->arch.mce_banks);
e9b11c17 5432 kvm_free_lapic(vcpu);
f656ce01 5433 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5434 kvm_mmu_destroy(vcpu);
f656ce01 5435 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5436 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5437}
d19a9cd2
ZX		 5438
5439struct kvm *kvm_arch_create_vm(void)
5440{
5441 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5442
5443 if (!kvm)
5444 return ERR_PTR(-ENOMEM);
5445
fef9cce0
MT		 5446 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5447 if (!kvm->arch.aliases) {
5448 kfree(kvm);
5449 return ERR_PTR(-ENOMEM);
5450 }
5451
f05e70ac 5452 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5453 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5454
5550af4d
SY		 5455 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5456 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5457
53f658b3
MT		 5458 rdtscll(kvm->arch.vm_init_tsc);
5459
d19a9cd2
ZX		 5460 return kvm;
5461}
5462
5463static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5464{
5465 vcpu_load(vcpu);
5466 kvm_mmu_unload(vcpu);
5467 vcpu_put(vcpu);
5468}
5469
5470static void kvm_free_vcpus(struct kvm *kvm)
5471{
5472 unsigned int i;
988a2cae 5473 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5474
5475 /*
5476 * Unpin any mmu pages first.
5477 */
988a2cae
GN		 5478 kvm_for_each_vcpu(i, vcpu, kvm)
5479 kvm_unload_vcpu_mmu(vcpu);
5480 kvm_for_each_vcpu(i, vcpu, kvm)
5481 kvm_arch_vcpu_free(vcpu);
5482
5483 mutex_lock(&kvm->lock);
5484 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5485 kvm->vcpus[i] = NULL;
d19a9cd2 5486
988a2cae
GN		 5487 atomic_set(&kvm->online_vcpus, 0);
5488 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5489}
5490
ad8ba2cd
SY		 5491void kvm_arch_sync_events(struct kvm *kvm)
5492{
ba4cef31 5493 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5494}
5495
d19a9cd2
ZX		 5496void kvm_arch_destroy_vm(struct kvm *kvm)
5497{
6eb55818 5498 kvm_iommu_unmap_guest(kvm);
7837699f 5499 kvm_free_pit(kvm);
d7deeeb0
ZX		 5500 kfree(kvm->arch.vpic);
5501 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5502 kvm_free_vcpus(kvm);
5503 kvm_free_physmem(kvm);
3d45830c
AK		 5504 if (kvm->arch.apic_access_page)
5505 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5506 if (kvm->arch.ept_identity_pagetable)
5507 put_page(kvm->arch.ept_identity_pagetable);
fef9cce0 5508 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5509 kfree(kvm);
5510}
0de10343 5511
f7784b8e
MT		 5512int kvm_arch_prepare_memory_region(struct kvm *kvm,
5513 struct kvm_memory_slot *memslot,
0de10343 5514 struct kvm_memory_slot old,
f7784b8e 5515 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5516 int user_alloc)
5517{
f7784b8e 5518 int npages = memslot->npages;
0de10343
ZX		 5519
5520 /*To keep backward compatibility with older userspace,
5521 *x86 needs to hanlde !user_alloc case.
5522 */
5523 if (!user_alloc) {
5524 if (npages && !old.rmap) {
604b38ac
AA		 5525 unsigned long userspace_addr;
5526
72dc67a6 5527 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5528 userspace_addr = do_mmap(NULL, 0,
5529 npages * PAGE_SIZE,
5530 PROT_READ | PROT_WRITE,
acee3c04 5531 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5532 0);
72dc67a6 5533 up_write(&current->mm->mmap_sem);
0de10343 5534
604b38ac
AA		 5535 if (IS_ERR((void *)userspace_addr))
5536 return PTR_ERR((void *)userspace_addr);
5537
604b38ac 5538 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5539 }
5540 }
5541
f7784b8e
MT		 5542
5543 return 0;
5544}
5545
5546void kvm_arch_commit_memory_region(struct kvm *kvm,
5547 struct kvm_userspace_memory_region *mem,
5548 struct kvm_memory_slot old,
5549 int user_alloc)
5550{
5551
5552 int npages = mem->memory_size >> PAGE_SHIFT;
5553
5554 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5555 int ret;
5556
5557 down_write(&current->mm->mmap_sem);
5558 ret = do_munmap(current->mm, old.userspace_addr,
5559 old.npages * PAGE_SIZE);
5560 up_write(&current->mm->mmap_sem);
5561 if (ret < 0)
5562 printk(KERN_WARNING
5563 "kvm_vm_ioctl_set_memory_region: "
5564 "failed to munmap memory\n");
5565 }
5566
7c8a83b7 5567 spin_lock(&kvm->mmu_lock);
f05e70ac 5568 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5569 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5570 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5571 }
5572
5573 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5574 spin_unlock(&kvm->mmu_lock);
0de10343 5575}
1d737c8a 5576
34d4cb8f
MT		 5577void kvm_arch_flush_shadow(struct kvm *kvm)
5578{
5579 kvm_mmu_zap_all(kvm);
8986ecc0 5580 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5581}
5582
1d737c8a
ZX		 5583int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5584{
a4535290 5585 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5586 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5587 || vcpu->arch.nmi_pending ||
5588 (kvm_arch_interrupt_allowed(vcpu) &&
5589 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5590}
5736199a 5591
5736199a
ZX		 5592void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5593{
32f88400
MT		 5594 int me;
5595 int cpu = vcpu->cpu;
5736199a
ZX		 5596
5597 if (waitqueue_active(&vcpu->wq)) {
5598 wake_up_interruptible(&vcpu->wq);
5599 ++vcpu->stat.halt_wakeup;
5600 }
32f88400
MT		 5601
5602 me = get_cpu();
5603 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5604 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5605 smp_send_reschedule(cpu);
e9571ed5 5606 put_cpu();
5736199a 5607}
78646121
GN		 5608
5609int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5610{
5611 return kvm_x86_ops->interrupt_allowed(vcpu);
5612}
229456fc 5613
94fe45da
JK		 5614unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5615{
5616 unsigned long rflags;
5617
5618 rflags = kvm_x86_ops->get_rflags(vcpu);
5619 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5620 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5621 return rflags;
5622}
5623EXPORT_SYMBOL_GPL(kvm_get_rflags);
5624
5625void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5626{
5627 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5628 vcpu->arch.singlestep_cs ==
5629 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5630 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5631 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5632 kvm_x86_ops->set_rflags(vcpu, rflags);
5633}
5634EXPORT_SYMBOL_GPL(kvm_set_rflags);
5635
229456fc
MT		 5636EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5637EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5638EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5641EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5643EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5644EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5645EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5646EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
Linux kernel - Deliverables
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