Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
c9eab58f | 30 | #include "assigned-dev.h" |
474a5bb9 | 31 | #include "pmu.h" |
e83d5887 | 32 | #include "hyperv.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
5fb76f9b | 39 | #include <linux/module.h> |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
aec51dc4 | 56 | #include <trace/events/kvm.h> |
2ed152af | 57 | |
229456fc MT |
58 | #define CREATE_TRACE_POINTS |
59 | #include "trace.h" | |
043405e1 | 60 | |
24f1e32c | 61 | #include <asm/debugreg.h> |
d825ed0a | 62 | #include <asm/msr.h> |
a5f61300 | 63 | #include <asm/desc.h> |
890ca9ae | 64 | #include <asm/mce.h> |
f89e32e0 | 65 | #include <linux/kernel_stat.h> |
78f7f1e5 | 66 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 67 | #include <asm/pvclock.h> |
217fc9cf | 68 | #include <asm/div64.h> |
efc64404 | 69 | #include <asm/irq_remapping.h> |
043405e1 | 70 | |
313a3dc7 | 71 | #define MAX_IO_MSRS 256 |
890ca9ae | 72 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 73 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 74 | |
0f65dd70 AK |
75 | #define emul_to_vcpu(ctxt) \ |
76 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
77 | ||
50a37eb4 JR |
78 | /* EFER defaults: |
79 | * - enable syscall per default because its emulated by KVM | |
80 | * - enable LME and LMA per default on 64 bit KVM | |
81 | */ | |
82 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
83 | static |
84 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 85 | #else |
1260edbe | 86 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 87 | #endif |
313a3dc7 | 88 | |
ba1389b7 AK |
89 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
90 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 91 | |
cb142eb7 | 92 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 93 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 94 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
674eea0f | 95 | |
893590c7 | 96 | struct kvm_x86_ops *kvm_x86_ops __read_mostly; |
5fdbf976 | 97 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 98 | |
893590c7 | 99 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 100 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 101 | |
9ed96e87 MT |
102 | unsigned int min_timer_period_us = 500; |
103 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
104 | ||
630994b3 MT |
105 | static bool __read_mostly kvmclock_periodic_sync = true; |
106 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
107 | ||
893590c7 | 108 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 109 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 110 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 111 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
112 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
113 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
114 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
115 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
ad721883 | 116 | static u64 __read_mostly kvm_default_tsc_scaling_ratio; |
92a1f12d | 117 | |
cc578287 | 118 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 119 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
120 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
121 | ||
d0659d94 | 122 | /* lapic timer advance (tscdeadline mode only) in nanoseconds */ |
893590c7 | 123 | unsigned int __read_mostly lapic_timer_advance_ns = 0; |
d0659d94 MT |
124 | module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); |
125 | ||
893590c7 | 126 | static bool __read_mostly backwards_tsc_observed = false; |
16a96021 | 127 | |
18863bdd AK |
128 | #define KVM_NR_SHARED_MSRS 16 |
129 | ||
130 | struct kvm_shared_msrs_global { | |
131 | int nr; | |
2bf78fa7 | 132 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
133 | }; |
134 | ||
135 | struct kvm_shared_msrs { | |
136 | struct user_return_notifier urn; | |
137 | bool registered; | |
2bf78fa7 SY |
138 | struct kvm_shared_msr_values { |
139 | u64 host; | |
140 | u64 curr; | |
141 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
142 | }; |
143 | ||
144 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 145 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 146 | |
417bc304 | 147 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
148 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
149 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
150 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
151 | { "invlpg", VCPU_STAT(invlpg) }, | |
152 | { "exits", VCPU_STAT(exits) }, | |
153 | { "io_exits", VCPU_STAT(io_exits) }, | |
154 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
155 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
156 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 157 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 158 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 159 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
62bea5bf | 160 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, |
ba1389b7 | 161 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 162 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
163 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
164 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
165 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
166 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
167 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
168 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
169 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 170 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 171 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
172 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
173 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
174 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
175 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
176 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
177 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 178 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 179 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 180 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 181 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
182 | { NULL } |
183 | }; | |
184 | ||
2acf923e DC |
185 | u64 __read_mostly host_xcr0; |
186 | ||
b6785def | 187 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 188 | |
af585b92 GN |
189 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
190 | { | |
191 | int i; | |
192 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
193 | vcpu->arch.apf.gfns[i] = ~0; | |
194 | } | |
195 | ||
18863bdd AK |
196 | static void kvm_on_user_return(struct user_return_notifier *urn) |
197 | { | |
198 | unsigned slot; | |
18863bdd AK |
199 | struct kvm_shared_msrs *locals |
200 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 201 | struct kvm_shared_msr_values *values; |
18863bdd AK |
202 | |
203 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
204 | values = &locals->values[slot]; |
205 | if (values->host != values->curr) { | |
206 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
207 | values->curr = values->host; | |
18863bdd AK |
208 | } |
209 | } | |
210 | locals->registered = false; | |
211 | user_return_notifier_unregister(urn); | |
212 | } | |
213 | ||
2bf78fa7 | 214 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 215 | { |
18863bdd | 216 | u64 value; |
013f6a5d MT |
217 | unsigned int cpu = smp_processor_id(); |
218 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 219 | |
2bf78fa7 SY |
220 | /* only read, and nobody should modify it at this time, |
221 | * so don't need lock */ | |
222 | if (slot >= shared_msrs_global.nr) { | |
223 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
224 | return; | |
225 | } | |
226 | rdmsrl_safe(msr, &value); | |
227 | smsr->values[slot].host = value; | |
228 | smsr->values[slot].curr = value; | |
229 | } | |
230 | ||
231 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
232 | { | |
0123be42 | 233 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
c847fe88 | 234 | shared_msrs_global.msrs[slot] = msr; |
18863bdd AK |
235 | if (slot >= shared_msrs_global.nr) |
236 | shared_msrs_global.nr = slot + 1; | |
18863bdd AK |
237 | } |
238 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
239 | ||
240 | static void kvm_shared_msr_cpu_online(void) | |
241 | { | |
242 | unsigned i; | |
18863bdd AK |
243 | |
244 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 245 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
246 | } |
247 | ||
8b3c3104 | 248 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 249 | { |
013f6a5d MT |
250 | unsigned int cpu = smp_processor_id(); |
251 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 252 | int err; |
18863bdd | 253 | |
2bf78fa7 | 254 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 255 | return 0; |
2bf78fa7 | 256 | smsr->values[slot].curr = value; |
8b3c3104 AH |
257 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
258 | if (err) | |
259 | return 1; | |
260 | ||
18863bdd AK |
261 | if (!smsr->registered) { |
262 | smsr->urn.on_user_return = kvm_on_user_return; | |
263 | user_return_notifier_register(&smsr->urn); | |
264 | smsr->registered = true; | |
265 | } | |
8b3c3104 | 266 | return 0; |
18863bdd AK |
267 | } |
268 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
269 | ||
13a34e06 | 270 | static void drop_user_return_notifiers(void) |
3548bab5 | 271 | { |
013f6a5d MT |
272 | unsigned int cpu = smp_processor_id(); |
273 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
274 | |
275 | if (smsr->registered) | |
276 | kvm_on_user_return(&smsr->urn); | |
277 | } | |
278 | ||
6866b83e CO |
279 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
280 | { | |
8a5a87d9 | 281 | return vcpu->arch.apic_base; |
6866b83e CO |
282 | } |
283 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
284 | ||
58cb628d JK |
285 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
286 | { | |
287 | u64 old_state = vcpu->arch.apic_base & | |
288 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
289 | u64 new_state = msr_info->data & | |
290 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
291 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | | |
292 | 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); | |
293 | ||
294 | if (!msr_info->host_initiated && | |
295 | ((msr_info->data & reserved_bits) != 0 || | |
296 | new_state == X2APIC_ENABLE || | |
297 | (new_state == MSR_IA32_APICBASE_ENABLE && | |
298 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || | |
299 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
300 | old_state == 0))) | |
301 | return 1; | |
302 | ||
303 | kvm_lapic_set_base(vcpu, msr_info->data); | |
304 | return 0; | |
6866b83e CO |
305 | } |
306 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
307 | ||
2605fc21 | 308 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
309 | { |
310 | /* Fault while not rebooting. We want the trace. */ | |
311 | BUG(); | |
312 | } | |
313 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
314 | ||
3fd28fce ED |
315 | #define EXCPT_BENIGN 0 |
316 | #define EXCPT_CONTRIBUTORY 1 | |
317 | #define EXCPT_PF 2 | |
318 | ||
319 | static int exception_class(int vector) | |
320 | { | |
321 | switch (vector) { | |
322 | case PF_VECTOR: | |
323 | return EXCPT_PF; | |
324 | case DE_VECTOR: | |
325 | case TS_VECTOR: | |
326 | case NP_VECTOR: | |
327 | case SS_VECTOR: | |
328 | case GP_VECTOR: | |
329 | return EXCPT_CONTRIBUTORY; | |
330 | default: | |
331 | break; | |
332 | } | |
333 | return EXCPT_BENIGN; | |
334 | } | |
335 | ||
d6e8c854 NA |
336 | #define EXCPT_FAULT 0 |
337 | #define EXCPT_TRAP 1 | |
338 | #define EXCPT_ABORT 2 | |
339 | #define EXCPT_INTERRUPT 3 | |
340 | ||
341 | static int exception_type(int vector) | |
342 | { | |
343 | unsigned int mask; | |
344 | ||
345 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
346 | return EXCPT_INTERRUPT; | |
347 | ||
348 | mask = 1 << vector; | |
349 | ||
350 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
351 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
352 | return EXCPT_TRAP; | |
353 | ||
354 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
355 | return EXCPT_ABORT; | |
356 | ||
357 | /* Reserved exceptions will result in fault */ | |
358 | return EXCPT_FAULT; | |
359 | } | |
360 | ||
3fd28fce | 361 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
362 | unsigned nr, bool has_error, u32 error_code, |
363 | bool reinject) | |
3fd28fce ED |
364 | { |
365 | u32 prev_nr; | |
366 | int class1, class2; | |
367 | ||
3842d135 AK |
368 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
369 | ||
3fd28fce ED |
370 | if (!vcpu->arch.exception.pending) { |
371 | queue: | |
3ffb2468 NA |
372 | if (has_error && !is_protmode(vcpu)) |
373 | has_error = false; | |
3fd28fce ED |
374 | vcpu->arch.exception.pending = true; |
375 | vcpu->arch.exception.has_error_code = has_error; | |
376 | vcpu->arch.exception.nr = nr; | |
377 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 378 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
379 | return; |
380 | } | |
381 | ||
382 | /* to check exception */ | |
383 | prev_nr = vcpu->arch.exception.nr; | |
384 | if (prev_nr == DF_VECTOR) { | |
385 | /* triple fault -> shutdown */ | |
a8eeb04a | 386 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
387 | return; |
388 | } | |
389 | class1 = exception_class(prev_nr); | |
390 | class2 = exception_class(nr); | |
391 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
392 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
393 | /* generate double fault per SDM Table 5-5 */ | |
394 | vcpu->arch.exception.pending = true; | |
395 | vcpu->arch.exception.has_error_code = true; | |
396 | vcpu->arch.exception.nr = DF_VECTOR; | |
397 | vcpu->arch.exception.error_code = 0; | |
398 | } else | |
399 | /* replace previous exception with a new one in a hope | |
400 | that instruction re-execution will regenerate lost | |
401 | exception */ | |
402 | goto queue; | |
403 | } | |
404 | ||
298101da AK |
405 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
406 | { | |
ce7ddec4 | 407 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
408 | } |
409 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
410 | ||
ce7ddec4 JR |
411 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
412 | { | |
413 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
414 | } | |
415 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
416 | ||
db8fcefa | 417 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 418 | { |
db8fcefa AP |
419 | if (err) |
420 | kvm_inject_gp(vcpu, 0); | |
421 | else | |
422 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
423 | } | |
424 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 425 | |
6389ee94 | 426 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
427 | { |
428 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
429 | vcpu->arch.cr2 = fault->address; |
430 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 431 | } |
27d6c865 | 432 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 433 | |
ef54bcfe | 434 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 435 | { |
6389ee94 AK |
436 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
437 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 438 | else |
6389ee94 | 439 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
440 | |
441 | return fault->nested_page_fault; | |
d4f8cf66 JR |
442 | } |
443 | ||
3419ffc8 SY |
444 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
445 | { | |
7460fb4a AK |
446 | atomic_inc(&vcpu->arch.nmi_queued); |
447 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
448 | } |
449 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
450 | ||
298101da AK |
451 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
452 | { | |
ce7ddec4 | 453 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
454 | } |
455 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
456 | ||
ce7ddec4 JR |
457 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
458 | { | |
459 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
460 | } | |
461 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
462 | ||
0a79b009 AK |
463 | /* |
464 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
465 | * a #GP and return false. | |
466 | */ | |
467 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 468 | { |
0a79b009 AK |
469 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
470 | return true; | |
471 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
472 | return false; | |
298101da | 473 | } |
0a79b009 | 474 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 475 | |
16f8a6f9 NA |
476 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
477 | { | |
478 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
479 | return true; | |
480 | ||
481 | kvm_queue_exception(vcpu, UD_VECTOR); | |
482 | return false; | |
483 | } | |
484 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
485 | ||
ec92fe44 JR |
486 | /* |
487 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 488 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
489 | * can read from guest physical or from the guest's guest physical memory. |
490 | */ | |
491 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
492 | gfn_t ngfn, void *data, int offset, int len, | |
493 | u32 access) | |
494 | { | |
54987b7a | 495 | struct x86_exception exception; |
ec92fe44 JR |
496 | gfn_t real_gfn; |
497 | gpa_t ngpa; | |
498 | ||
499 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 500 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
501 | if (real_gfn == UNMAPPED_GVA) |
502 | return -EFAULT; | |
503 | ||
504 | real_gfn = gpa_to_gfn(real_gfn); | |
505 | ||
54bf36aa | 506 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
507 | } |
508 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
509 | ||
69b0049a | 510 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
511 | void *data, int offset, int len, u32 access) |
512 | { | |
513 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
514 | data, offset, len, access); | |
515 | } | |
516 | ||
a03490ed CO |
517 | /* |
518 | * Load the pae pdptrs. Return true is they are all valid. | |
519 | */ | |
ff03a073 | 520 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
521 | { |
522 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
523 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
524 | int i; | |
525 | int ret; | |
ff03a073 | 526 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 527 | |
ff03a073 JR |
528 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
529 | offset * sizeof(u64), sizeof(pdpte), | |
530 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
531 | if (ret < 0) { |
532 | ret = 0; | |
533 | goto out; | |
534 | } | |
535 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 536 | if (is_present_gpte(pdpte[i]) && |
a0a64f50 XG |
537 | (pdpte[i] & |
538 | vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { | |
a03490ed CO |
539 | ret = 0; |
540 | goto out; | |
541 | } | |
542 | } | |
543 | ret = 1; | |
544 | ||
ff03a073 | 545 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
546 | __set_bit(VCPU_EXREG_PDPTR, |
547 | (unsigned long *)&vcpu->arch.regs_avail); | |
548 | __set_bit(VCPU_EXREG_PDPTR, | |
549 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 550 | out: |
a03490ed CO |
551 | |
552 | return ret; | |
553 | } | |
cc4b6871 | 554 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 555 | |
d835dfec AK |
556 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
557 | { | |
ff03a073 | 558 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 559 | bool changed = true; |
3d06b8bf JR |
560 | int offset; |
561 | gfn_t gfn; | |
d835dfec AK |
562 | int r; |
563 | ||
564 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
565 | return false; | |
566 | ||
6de4f3ad AK |
567 | if (!test_bit(VCPU_EXREG_PDPTR, |
568 | (unsigned long *)&vcpu->arch.regs_avail)) | |
569 | return true; | |
570 | ||
9f8fe504 AK |
571 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
572 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
573 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
574 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
575 | if (r < 0) |
576 | goto out; | |
ff03a073 | 577 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 578 | out: |
d835dfec AK |
579 | |
580 | return changed; | |
581 | } | |
582 | ||
49a9b07e | 583 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 584 | { |
aad82703 | 585 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 586 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 587 | |
f9a48e6a AK |
588 | cr0 |= X86_CR0_ET; |
589 | ||
ab344828 | 590 | #ifdef CONFIG_X86_64 |
0f12244f GN |
591 | if (cr0 & 0xffffffff00000000UL) |
592 | return 1; | |
ab344828 GN |
593 | #endif |
594 | ||
595 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 596 | |
0f12244f GN |
597 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
598 | return 1; | |
a03490ed | 599 | |
0f12244f GN |
600 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
601 | return 1; | |
a03490ed CO |
602 | |
603 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
604 | #ifdef CONFIG_X86_64 | |
f6801dff | 605 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
606 | int cs_db, cs_l; |
607 | ||
0f12244f GN |
608 | if (!is_pae(vcpu)) |
609 | return 1; | |
a03490ed | 610 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
611 | if (cs_l) |
612 | return 1; | |
a03490ed CO |
613 | } else |
614 | #endif | |
ff03a073 | 615 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 616 | kvm_read_cr3(vcpu))) |
0f12244f | 617 | return 1; |
a03490ed CO |
618 | } |
619 | ||
ad756a16 MJ |
620 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
621 | return 1; | |
622 | ||
a03490ed | 623 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 624 | |
d170c419 | 625 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 626 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
627 | kvm_async_pf_hash_reset(vcpu); |
628 | } | |
e5f3f027 | 629 | |
aad82703 SY |
630 | if ((cr0 ^ old_cr0) & update_bits) |
631 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 632 | |
879ae188 LE |
633 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
634 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
635 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
636 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
637 | ||
0f12244f GN |
638 | return 0; |
639 | } | |
2d3ad1f4 | 640 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 641 | |
2d3ad1f4 | 642 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 643 | { |
49a9b07e | 644 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 645 | } |
2d3ad1f4 | 646 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 647 | |
42bdf991 MT |
648 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
649 | { | |
650 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
651 | !vcpu->guest_xcr0_loaded) { | |
652 | /* kvm_set_xcr() also depends on this */ | |
653 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
654 | vcpu->guest_xcr0_loaded = 1; | |
655 | } | |
656 | } | |
657 | ||
658 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
659 | { | |
660 | if (vcpu->guest_xcr0_loaded) { | |
661 | if (vcpu->arch.xcr0 != host_xcr0) | |
662 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
663 | vcpu->guest_xcr0_loaded = 0; | |
664 | } | |
665 | } | |
666 | ||
69b0049a | 667 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 668 | { |
56c103ec LJ |
669 | u64 xcr0 = xcr; |
670 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 671 | u64 valid_bits; |
2acf923e DC |
672 | |
673 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
674 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
675 | return 1; | |
d91cab78 | 676 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 677 | return 1; |
d91cab78 | 678 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 679 | return 1; |
46c34cb0 PB |
680 | |
681 | /* | |
682 | * Do not allow the guest to set bits that we do not support | |
683 | * saving. However, xcr0 bit 0 is always set, even if the | |
684 | * emulated CPU does not support XSAVE (see fx_init). | |
685 | */ | |
d91cab78 | 686 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 687 | if (xcr0 & ~valid_bits) |
2acf923e | 688 | return 1; |
46c34cb0 | 689 | |
d91cab78 DH |
690 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
691 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
692 | return 1; |
693 | ||
d91cab78 DH |
694 | if (xcr0 & XFEATURE_MASK_AVX512) { |
695 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 696 | return 1; |
d91cab78 | 697 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
698 | return 1; |
699 | } | |
42bdf991 | 700 | kvm_put_guest_xcr0(vcpu); |
2acf923e | 701 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 702 | |
d91cab78 | 703 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
56c103ec | 704 | kvm_update_cpuid(vcpu); |
2acf923e DC |
705 | return 0; |
706 | } | |
707 | ||
708 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
709 | { | |
764bcbc5 Z |
710 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
711 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
712 | kvm_inject_gp(vcpu, 0); |
713 | return 1; | |
714 | } | |
715 | return 0; | |
716 | } | |
717 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
718 | ||
a83b29c6 | 719 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 720 | { |
fc78f519 | 721 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
0be0226f XG |
722 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | |
723 | X86_CR4_SMEP | X86_CR4_SMAP; | |
724 | ||
0f12244f GN |
725 | if (cr4 & CR4_RESERVED_BITS) |
726 | return 1; | |
a03490ed | 727 | |
2acf923e DC |
728 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
729 | return 1; | |
730 | ||
c68b734f YW |
731 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
732 | return 1; | |
733 | ||
97ec8c06 FW |
734 | if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) |
735 | return 1; | |
736 | ||
afcbf13f | 737 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) |
74dc2b4f YW |
738 | return 1; |
739 | ||
a03490ed | 740 | if (is_long_mode(vcpu)) { |
0f12244f GN |
741 | if (!(cr4 & X86_CR4_PAE)) |
742 | return 1; | |
a2edf57f AK |
743 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
744 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
745 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
746 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
747 | return 1; |
748 | ||
ad756a16 MJ |
749 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
750 | if (!guest_cpuid_has_pcid(vcpu)) | |
751 | return 1; | |
752 | ||
753 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
754 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
755 | return 1; | |
756 | } | |
757 | ||
5e1746d6 | 758 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 759 | return 1; |
a03490ed | 760 | |
ad756a16 MJ |
761 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
762 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 763 | kvm_mmu_reset_context(vcpu); |
0f12244f | 764 | |
2acf923e | 765 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 766 | kvm_update_cpuid(vcpu); |
2acf923e | 767 | |
0f12244f GN |
768 | return 0; |
769 | } | |
2d3ad1f4 | 770 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 771 | |
2390218b | 772 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 773 | { |
ac146235 | 774 | #ifdef CONFIG_X86_64 |
9d88fca7 | 775 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 776 | #endif |
9d88fca7 | 777 | |
9f8fe504 | 778 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 779 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 780 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 781 | return 0; |
d835dfec AK |
782 | } |
783 | ||
a03490ed | 784 | if (is_long_mode(vcpu)) { |
d9f89b88 JK |
785 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
786 | return 1; | |
787 | } else if (is_pae(vcpu) && is_paging(vcpu) && | |
788 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 789 | return 1; |
a03490ed | 790 | |
0f12244f | 791 | vcpu->arch.cr3 = cr3; |
aff48baa | 792 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 793 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
794 | return 0; |
795 | } | |
2d3ad1f4 | 796 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 797 | |
eea1cff9 | 798 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 799 | { |
0f12244f GN |
800 | if (cr8 & CR8_RESERVED_BITS) |
801 | return 1; | |
35754c98 | 802 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
803 | kvm_lapic_set_tpr(vcpu, cr8); |
804 | else | |
ad312c7c | 805 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
806 | return 0; |
807 | } | |
2d3ad1f4 | 808 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 809 | |
2d3ad1f4 | 810 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 811 | { |
35754c98 | 812 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
813 | return kvm_lapic_get_cr8(vcpu); |
814 | else | |
ad312c7c | 815 | return vcpu->arch.cr8; |
a03490ed | 816 | } |
2d3ad1f4 | 817 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 818 | |
ae561ede NA |
819 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
820 | { | |
821 | int i; | |
822 | ||
823 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
824 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
825 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
826 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
827 | } | |
828 | } | |
829 | ||
73aaf249 JK |
830 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
831 | { | |
832 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
833 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
834 | } | |
835 | ||
c8639010 JK |
836 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
837 | { | |
838 | unsigned long dr7; | |
839 | ||
840 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
841 | dr7 = vcpu->arch.guest_debug_dr7; | |
842 | else | |
843 | dr7 = vcpu->arch.dr7; | |
844 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
845 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
846 | if (dr7 & DR7_BP_EN_MASK) | |
847 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
848 | } |
849 | ||
6f43ed01 NA |
850 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
851 | { | |
852 | u64 fixed = DR6_FIXED_1; | |
853 | ||
854 | if (!guest_cpuid_has_rtm(vcpu)) | |
855 | fixed |= DR6_RTM; | |
856 | return fixed; | |
857 | } | |
858 | ||
338dbc97 | 859 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
860 | { |
861 | switch (dr) { | |
862 | case 0 ... 3: | |
863 | vcpu->arch.db[dr] = val; | |
864 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
865 | vcpu->arch.eff_db[dr] = val; | |
866 | break; | |
867 | case 4: | |
020df079 GN |
868 | /* fall through */ |
869 | case 6: | |
338dbc97 GN |
870 | if (val & 0xffffffff00000000ULL) |
871 | return -1; /* #GP */ | |
6f43ed01 | 872 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 873 | kvm_update_dr6(vcpu); |
020df079 GN |
874 | break; |
875 | case 5: | |
020df079 GN |
876 | /* fall through */ |
877 | default: /* 7 */ | |
338dbc97 GN |
878 | if (val & 0xffffffff00000000ULL) |
879 | return -1; /* #GP */ | |
020df079 | 880 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 881 | kvm_update_dr7(vcpu); |
020df079 GN |
882 | break; |
883 | } | |
884 | ||
885 | return 0; | |
886 | } | |
338dbc97 GN |
887 | |
888 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
889 | { | |
16f8a6f9 | 890 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 891 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
892 | return 1; |
893 | } | |
894 | return 0; | |
338dbc97 | 895 | } |
020df079 GN |
896 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
897 | ||
16f8a6f9 | 898 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
899 | { |
900 | switch (dr) { | |
901 | case 0 ... 3: | |
902 | *val = vcpu->arch.db[dr]; | |
903 | break; | |
904 | case 4: | |
020df079 GN |
905 | /* fall through */ |
906 | case 6: | |
73aaf249 JK |
907 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
908 | *val = vcpu->arch.dr6; | |
909 | else | |
910 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
911 | break; |
912 | case 5: | |
020df079 GN |
913 | /* fall through */ |
914 | default: /* 7 */ | |
915 | *val = vcpu->arch.dr7; | |
916 | break; | |
917 | } | |
338dbc97 GN |
918 | return 0; |
919 | } | |
020df079 GN |
920 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
921 | ||
022cd0e8 AK |
922 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
923 | { | |
924 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
925 | u64 data; | |
926 | int err; | |
927 | ||
c6702c9d | 928 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
929 | if (err) |
930 | return err; | |
931 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
932 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
933 | return err; | |
934 | } | |
935 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
936 | ||
043405e1 CO |
937 | /* |
938 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
939 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
940 | * | |
941 | * This list is modified at module load time to reflect the | |
e3267cbb | 942 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
62ef68bb PB |
943 | * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs |
944 | * may depend on host virtualization features rather than host cpu features. | |
043405e1 | 945 | */ |
e3267cbb | 946 | |
043405e1 CO |
947 | static u32 msrs_to_save[] = { |
948 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
8c06585d | 949 | MSR_STAR, |
043405e1 CO |
950 | #ifdef CONFIG_X86_64 |
951 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
952 | #endif | |
b3897a49 | 953 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
0dd376e7 | 954 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS |
043405e1 CO |
955 | }; |
956 | ||
957 | static unsigned num_msrs_to_save; | |
958 | ||
62ef68bb PB |
959 | static u32 emulated_msrs[] = { |
960 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
961 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
962 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
963 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
e7d9513b AS |
964 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
965 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 966 | HV_X64_MSR_RESET, |
11c4b1ca | 967 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 968 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 969 | HV_X64_MSR_SCONTROL, |
62ef68bb PB |
970 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, |
971 | MSR_KVM_PV_EOI_EN, | |
972 | ||
ba904635 | 973 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 974 | MSR_IA32_TSCDEADLINE, |
043405e1 | 975 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
976 | MSR_IA32_MCG_STATUS, |
977 | MSR_IA32_MCG_CTL, | |
64d60670 | 978 | MSR_IA32_SMBASE, |
043405e1 CO |
979 | }; |
980 | ||
62ef68bb PB |
981 | static unsigned num_emulated_msrs; |
982 | ||
384bb783 | 983 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 984 | { |
b69e8cae | 985 | if (efer & efer_reserved_bits) |
384bb783 | 986 | return false; |
15c4a640 | 987 | |
1b2fd70c AG |
988 | if (efer & EFER_FFXSR) { |
989 | struct kvm_cpuid_entry2 *feat; | |
990 | ||
991 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 992 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 993 | return false; |
1b2fd70c AG |
994 | } |
995 | ||
d8017474 AG |
996 | if (efer & EFER_SVME) { |
997 | struct kvm_cpuid_entry2 *feat; | |
998 | ||
999 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 1000 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 1001 | return false; |
d8017474 AG |
1002 | } |
1003 | ||
384bb783 JK |
1004 | return true; |
1005 | } | |
1006 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1007 | ||
1008 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1009 | { | |
1010 | u64 old_efer = vcpu->arch.efer; | |
1011 | ||
1012 | if (!kvm_valid_efer(vcpu, efer)) | |
1013 | return 1; | |
1014 | ||
1015 | if (is_paging(vcpu) | |
1016 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1017 | return 1; | |
1018 | ||
15c4a640 | 1019 | efer &= ~EFER_LMA; |
f6801dff | 1020 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1021 | |
a3d204e2 SY |
1022 | kvm_x86_ops->set_efer(vcpu, efer); |
1023 | ||
aad82703 SY |
1024 | /* Update reserved bits */ |
1025 | if ((efer ^ old_efer) & EFER_NX) | |
1026 | kvm_mmu_reset_context(vcpu); | |
1027 | ||
b69e8cae | 1028 | return 0; |
15c4a640 CO |
1029 | } |
1030 | ||
f2b4b7dd JR |
1031 | void kvm_enable_efer_bits(u64 mask) |
1032 | { | |
1033 | efer_reserved_bits &= ~mask; | |
1034 | } | |
1035 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1036 | ||
15c4a640 CO |
1037 | /* |
1038 | * Writes msr value into into the appropriate "register". | |
1039 | * Returns 0 on success, non-0 otherwise. | |
1040 | * Assumes vcpu_load() was already called. | |
1041 | */ | |
8fe8ab46 | 1042 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1043 | { |
854e8bb1 NA |
1044 | switch (msr->index) { |
1045 | case MSR_FS_BASE: | |
1046 | case MSR_GS_BASE: | |
1047 | case MSR_KERNEL_GS_BASE: | |
1048 | case MSR_CSTAR: | |
1049 | case MSR_LSTAR: | |
1050 | if (is_noncanonical_address(msr->data)) | |
1051 | return 1; | |
1052 | break; | |
1053 | case MSR_IA32_SYSENTER_EIP: | |
1054 | case MSR_IA32_SYSENTER_ESP: | |
1055 | /* | |
1056 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1057 | * non-canonical address is written on Intel but not on | |
1058 | * AMD (which ignores the top 32-bits, because it does | |
1059 | * not implement 64-bit SYSENTER). | |
1060 | * | |
1061 | * 64-bit code should hence be able to write a non-canonical | |
1062 | * value on AMD. Making the address canonical ensures that | |
1063 | * vmentry does not fail on Intel after writing a non-canonical | |
1064 | * value, and that something deterministic happens if the guest | |
1065 | * invokes 64-bit SYSENTER. | |
1066 | */ | |
1067 | msr->data = get_canonical(msr->data); | |
1068 | } | |
8fe8ab46 | 1069 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1070 | } |
854e8bb1 | 1071 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1072 | |
313a3dc7 CO |
1073 | /* |
1074 | * Adapt set_msr() to msr_io()'s calling convention | |
1075 | */ | |
609e36d3 PB |
1076 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1077 | { | |
1078 | struct msr_data msr; | |
1079 | int r; | |
1080 | ||
1081 | msr.index = index; | |
1082 | msr.host_initiated = true; | |
1083 | r = kvm_get_msr(vcpu, &msr); | |
1084 | if (r) | |
1085 | return r; | |
1086 | ||
1087 | *data = msr.data; | |
1088 | return 0; | |
1089 | } | |
1090 | ||
313a3dc7 CO |
1091 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1092 | { | |
8fe8ab46 WA |
1093 | struct msr_data msr; |
1094 | ||
1095 | msr.data = *data; | |
1096 | msr.index = index; | |
1097 | msr.host_initiated = true; | |
1098 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1099 | } |
1100 | ||
16e8d74d MT |
1101 | #ifdef CONFIG_X86_64 |
1102 | struct pvclock_gtod_data { | |
1103 | seqcount_t seq; | |
1104 | ||
1105 | struct { /* extract of a clocksource struct */ | |
1106 | int vclock_mode; | |
1107 | cycle_t cycle_last; | |
1108 | cycle_t mask; | |
1109 | u32 mult; | |
1110 | u32 shift; | |
1111 | } clock; | |
1112 | ||
cbcf2dd3 TG |
1113 | u64 boot_ns; |
1114 | u64 nsec_base; | |
16e8d74d MT |
1115 | }; |
1116 | ||
1117 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1118 | ||
1119 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1120 | { | |
1121 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1122 | u64 boot_ns; |
1123 | ||
876e7881 | 1124 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1125 | |
1126 | write_seqcount_begin(&vdata->seq); | |
1127 | ||
1128 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1129 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1130 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1131 | vdata->clock.mask = tk->tkr_mono.mask; | |
1132 | vdata->clock.mult = tk->tkr_mono.mult; | |
1133 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1134 | |
cbcf2dd3 | 1135 | vdata->boot_ns = boot_ns; |
876e7881 | 1136 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d MT |
1137 | |
1138 | write_seqcount_end(&vdata->seq); | |
1139 | } | |
1140 | #endif | |
1141 | ||
bab5bb39 NK |
1142 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1143 | { | |
1144 | /* | |
1145 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1146 | * vcpu_enter_guest. This function is only called from | |
1147 | * the physical CPU that is running vcpu. | |
1148 | */ | |
1149 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1150 | } | |
16e8d74d | 1151 | |
18068523 GOC |
1152 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1153 | { | |
9ed3c444 AK |
1154 | int version; |
1155 | int r; | |
50d0a0f9 | 1156 | struct pvclock_wall_clock wc; |
923de3cf | 1157 | struct timespec boot; |
18068523 GOC |
1158 | |
1159 | if (!wall_clock) | |
1160 | return; | |
1161 | ||
9ed3c444 AK |
1162 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1163 | if (r) | |
1164 | return; | |
1165 | ||
1166 | if (version & 1) | |
1167 | ++version; /* first time write, random junk */ | |
1168 | ||
1169 | ++version; | |
18068523 | 1170 | |
18068523 GOC |
1171 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
1172 | ||
50d0a0f9 GH |
1173 | /* |
1174 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1175 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1176 | * wall clock specified here. guest system time equals host |
1177 | * system time for us, thus we must fill in host boot time here. | |
1178 | */ | |
923de3cf | 1179 | getboottime(&boot); |
50d0a0f9 | 1180 | |
4b648665 BR |
1181 | if (kvm->arch.kvmclock_offset) { |
1182 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1183 | boot = timespec_sub(boot, ts); | |
1184 | } | |
50d0a0f9 GH |
1185 | wc.sec = boot.tv_sec; |
1186 | wc.nsec = boot.tv_nsec; | |
1187 | wc.version = version; | |
18068523 GOC |
1188 | |
1189 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1190 | ||
1191 | version++; | |
1192 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1193 | } |
1194 | ||
50d0a0f9 GH |
1195 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1196 | { | |
1197 | uint32_t quotient, remainder; | |
1198 | ||
1199 | /* Don't try to replace with do_div(), this one calculates | |
1200 | * "(dividend << 32) / divisor" */ | |
1201 | __asm__ ( "divl %4" | |
1202 | : "=a" (quotient), "=d" (remainder) | |
1203 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1204 | return quotient; | |
1205 | } | |
1206 | ||
5f4e3f88 ZA |
1207 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
1208 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 1209 | { |
5f4e3f88 | 1210 | uint64_t scaled64; |
50d0a0f9 GH |
1211 | int32_t shift = 0; |
1212 | uint64_t tps64; | |
1213 | uint32_t tps32; | |
1214 | ||
5f4e3f88 ZA |
1215 | tps64 = base_khz * 1000LL; |
1216 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 1217 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1218 | tps64 >>= 1; |
1219 | shift--; | |
1220 | } | |
1221 | ||
1222 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1223 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1224 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1225 | scaled64 >>= 1; |
1226 | else | |
1227 | tps32 <<= 1; | |
50d0a0f9 GH |
1228 | shift++; |
1229 | } | |
1230 | ||
5f4e3f88 ZA |
1231 | *pshift = shift; |
1232 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1233 | |
5f4e3f88 ZA |
1234 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
1235 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
1236 | } |
1237 | ||
d828199e | 1238 | #ifdef CONFIG_X86_64 |
16e8d74d | 1239 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1240 | #endif |
16e8d74d | 1241 | |
c8076604 | 1242 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1243 | static unsigned long max_tsc_khz; |
c8076604 | 1244 | |
cc578287 | 1245 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1246 | { |
cc578287 ZA |
1247 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1248 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1249 | } |
1250 | ||
cc578287 | 1251 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1252 | { |
cc578287 ZA |
1253 | u64 v = (u64)khz * (1000000 + ppm); |
1254 | do_div(v, 1000000); | |
1255 | return v; | |
1e993611 JR |
1256 | } |
1257 | ||
381d585c HZ |
1258 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
1259 | { | |
1260 | u64 ratio; | |
1261 | ||
1262 | /* Guest TSC same frequency as host TSC? */ | |
1263 | if (!scale) { | |
1264 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | /* TSC scaling supported? */ | |
1269 | if (!kvm_has_tsc_control) { | |
1270 | if (user_tsc_khz > tsc_khz) { | |
1271 | vcpu->arch.tsc_catchup = 1; | |
1272 | vcpu->arch.tsc_always_catchup = 1; | |
1273 | return 0; | |
1274 | } else { | |
1275 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
1276 | return -1; | |
1277 | } | |
1278 | } | |
1279 | ||
1280 | /* TSC scaling required - calculate ratio */ | |
1281 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
1282 | user_tsc_khz, tsc_khz); | |
1283 | ||
1284 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
1285 | WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", | |
1286 | user_tsc_khz); | |
1287 | return -1; | |
1288 | } | |
1289 | ||
1290 | vcpu->arch.tsc_scaling_ratio = ratio; | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) | |
759379dd | 1295 | { |
cc578287 ZA |
1296 | u32 thresh_lo, thresh_hi; |
1297 | int use_scaling = 0; | |
217fc9cf | 1298 | |
03ba32ca | 1299 | /* tsc_khz can be zero if TSC calibration fails */ |
ad721883 HZ |
1300 | if (this_tsc_khz == 0) { |
1301 | /* set tsc_scaling_ratio to a safe value */ | |
1302 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 1303 | return -1; |
ad721883 | 1304 | } |
03ba32ca | 1305 | |
c285545f ZA |
1306 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1307 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1308 | &vcpu->arch.virtual_tsc_shift, |
1309 | &vcpu->arch.virtual_tsc_mult); | |
1310 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1311 | ||
1312 | /* | |
1313 | * Compute the variation in TSC rate which is acceptable | |
1314 | * within the range of tolerance and decide if the | |
1315 | * rate being applied is within that bounds of the hardware | |
1316 | * rate. If so, no scaling or compensation need be done. | |
1317 | */ | |
1318 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1319 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1320 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1321 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1322 | use_scaling = 1; | |
1323 | } | |
381d585c | 1324 | return set_tsc_khz(vcpu, this_tsc_khz, use_scaling); |
c285545f ZA |
1325 | } |
1326 | ||
1327 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1328 | { | |
e26101b1 | 1329 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1330 | vcpu->arch.virtual_tsc_mult, |
1331 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1332 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1333 | return tsc; |
1334 | } | |
1335 | ||
69b0049a | 1336 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1337 | { |
1338 | #ifdef CONFIG_X86_64 | |
1339 | bool vcpus_matched; | |
b48aa97e MT |
1340 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1341 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1342 | ||
1343 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1344 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1345 | ||
7f187922 MT |
1346 | /* |
1347 | * Once the masterclock is enabled, always perform request in | |
1348 | * order to update it. | |
1349 | * | |
1350 | * In order to enable masterclock, the host clocksource must be TSC | |
1351 | * and the vcpus need to have matched TSCs. When that happens, | |
1352 | * perform request to enable masterclock. | |
1353 | */ | |
1354 | if (ka->use_master_clock || | |
1355 | (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) | |
b48aa97e MT |
1356 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1357 | ||
1358 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1359 | atomic_read(&vcpu->kvm->online_vcpus), | |
1360 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1361 | #endif | |
1362 | } | |
1363 | ||
ba904635 WA |
1364 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1365 | { | |
1366 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1367 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1368 | } | |
1369 | ||
35181e86 HZ |
1370 | /* |
1371 | * Multiply tsc by a fixed point number represented by ratio. | |
1372 | * | |
1373 | * The most significant 64-N bits (mult) of ratio represent the | |
1374 | * integral part of the fixed point number; the remaining N bits | |
1375 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
1376 | * point number (mult + frac * 2^(-N)). | |
1377 | * | |
1378 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
1379 | */ | |
1380 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
1381 | { | |
1382 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
1383 | } | |
1384 | ||
1385 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
1386 | { | |
1387 | u64 _tsc = tsc; | |
1388 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
1389 | ||
1390 | if (ratio != kvm_default_tsc_scaling_ratio) | |
1391 | _tsc = __scale_tsc(ratio, tsc); | |
1392 | ||
1393 | return _tsc; | |
1394 | } | |
1395 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
1396 | ||
07c1419a HZ |
1397 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1398 | { | |
1399 | u64 tsc; | |
1400 | ||
1401 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
1402 | ||
1403 | return target_tsc - tsc; | |
1404 | } | |
1405 | ||
4ba76538 HZ |
1406 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
1407 | { | |
1408 | return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc)); | |
1409 | } | |
1410 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
1411 | ||
8fe8ab46 | 1412 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1413 | { |
1414 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1415 | u64 offset, ns, elapsed; |
99e3e30a | 1416 | unsigned long flags; |
02626b6a | 1417 | s64 usdiff; |
b48aa97e | 1418 | bool matched; |
0d3da0d2 | 1419 | bool already_matched; |
8fe8ab46 | 1420 | u64 data = msr->data; |
99e3e30a | 1421 | |
038f8c11 | 1422 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 1423 | offset = kvm_compute_tsc_offset(vcpu, data); |
759379dd | 1424 | ns = get_kernel_ns(); |
f38e098f | 1425 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1426 | |
03ba32ca | 1427 | if (vcpu->arch.virtual_tsc_khz) { |
8915aa27 MT |
1428 | int faulted = 0; |
1429 | ||
03ba32ca MT |
1430 | /* n.b - signed multiplication and division required */ |
1431 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1432 | #ifdef CONFIG_X86_64 |
03ba32ca | 1433 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1434 | #else |
03ba32ca | 1435 | /* do_div() only does unsigned */ |
8915aa27 MT |
1436 | asm("1: idivl %[divisor]\n" |
1437 | "2: xor %%edx, %%edx\n" | |
1438 | " movl $0, %[faulted]\n" | |
1439 | "3:\n" | |
1440 | ".section .fixup,\"ax\"\n" | |
1441 | "4: movl $1, %[faulted]\n" | |
1442 | " jmp 3b\n" | |
1443 | ".previous\n" | |
1444 | ||
1445 | _ASM_EXTABLE(1b, 4b) | |
1446 | ||
1447 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1448 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1449 | ||
5d3cb0f6 | 1450 | #endif |
03ba32ca MT |
1451 | do_div(elapsed, 1000); |
1452 | usdiff -= elapsed; | |
1453 | if (usdiff < 0) | |
1454 | usdiff = -usdiff; | |
8915aa27 MT |
1455 | |
1456 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1457 | if (faulted) | |
1458 | usdiff = USEC_PER_SEC; | |
03ba32ca MT |
1459 | } else |
1460 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1461 | |
1462 | /* | |
5d3cb0f6 ZA |
1463 | * Special case: TSC write with a small delta (1 second) of virtual |
1464 | * cycle time against real time is interpreted as an attempt to | |
1465 | * synchronize the CPU. | |
1466 | * | |
1467 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1468 | * TSC, we add elapsed time in this computation. We could let the | |
1469 | * compensation code attempt to catch up if we fall behind, but | |
1470 | * it's better to try to match offsets from the beginning. | |
1471 | */ | |
02626b6a | 1472 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1473 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1474 | if (!check_tsc_unstable()) { |
e26101b1 | 1475 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1476 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1477 | } else { | |
857e4099 | 1478 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 1479 | data += delta; |
07c1419a | 1480 | offset = kvm_compute_tsc_offset(vcpu, data); |
759379dd | 1481 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1482 | } |
b48aa97e | 1483 | matched = true; |
0d3da0d2 | 1484 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1485 | } else { |
1486 | /* | |
1487 | * We split periods of matched TSC writes into generations. | |
1488 | * For each generation, we track the original measured | |
1489 | * nanosecond time, offset, and write, so if TSCs are in | |
1490 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1491 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1492 | * |
1493 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1494 | */ | |
1495 | kvm->arch.cur_tsc_generation++; | |
1496 | kvm->arch.cur_tsc_nsec = ns; | |
1497 | kvm->arch.cur_tsc_write = data; | |
1498 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1499 | matched = false; |
0d3da0d2 | 1500 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1501 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1502 | } |
e26101b1 ZA |
1503 | |
1504 | /* | |
1505 | * We also track th most recent recorded KHZ, write and time to | |
1506 | * allow the matching interval to be extended at each write. | |
1507 | */ | |
f38e098f ZA |
1508 | kvm->arch.last_tsc_nsec = ns; |
1509 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1510 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1511 | |
b183aa58 | 1512 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1513 | |
1514 | /* Keep track of which generation this VCPU has synchronized to */ | |
1515 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1516 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1517 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1518 | ||
ba904635 WA |
1519 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1520 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1521 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1522 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1523 | |
1524 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1525 | if (!matched) { |
b48aa97e | 1526 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1527 | } else if (!already_matched) { |
1528 | kvm->arch.nr_vcpus_matched_tsc++; | |
1529 | } | |
b48aa97e MT |
1530 | |
1531 | kvm_track_tsc_matching(vcpu); | |
1532 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1533 | } |
e26101b1 | 1534 | |
99e3e30a ZA |
1535 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1536 | ||
58ea6767 HZ |
1537 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
1538 | s64 adjustment) | |
1539 | { | |
1540 | kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); | |
1541 | } | |
1542 | ||
1543 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
1544 | { | |
1545 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
1546 | WARN_ON(adjustment < 0); | |
1547 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
1548 | kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); | |
1549 | } | |
1550 | ||
d828199e MT |
1551 | #ifdef CONFIG_X86_64 |
1552 | ||
1553 | static cycle_t read_tsc(void) | |
1554 | { | |
03b9730b AL |
1555 | cycle_t ret = (cycle_t)rdtsc_ordered(); |
1556 | u64 last = pvclock_gtod_data.clock.cycle_last; | |
d828199e MT |
1557 | |
1558 | if (likely(ret >= last)) | |
1559 | return ret; | |
1560 | ||
1561 | /* | |
1562 | * GCC likes to generate cmov here, but this branch is extremely | |
1563 | * predictable (it's just a funciton of time and the likely is | |
1564 | * very likely) and there's a data dependence, so force GCC | |
1565 | * to generate a branch instead. I don't barrier() because | |
1566 | * we don't actually need a barrier, and if this function | |
1567 | * ever gets inlined it will generate worse code. | |
1568 | */ | |
1569 | asm volatile (""); | |
1570 | return last; | |
1571 | } | |
1572 | ||
1573 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1574 | { | |
1575 | long v; | |
1576 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1577 | ||
1578 | *cycle_now = read_tsc(); | |
1579 | ||
1580 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1581 | return v * gtod->clock.mult; | |
1582 | } | |
1583 | ||
cbcf2dd3 | 1584 | static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) |
d828199e | 1585 | { |
cbcf2dd3 | 1586 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1587 | unsigned long seq; |
d828199e | 1588 | int mode; |
cbcf2dd3 | 1589 | u64 ns; |
d828199e | 1590 | |
d828199e MT |
1591 | do { |
1592 | seq = read_seqcount_begin(>od->seq); | |
1593 | mode = gtod->clock.vclock_mode; | |
cbcf2dd3 | 1594 | ns = gtod->nsec_base; |
d828199e MT |
1595 | ns += vgettsc(cycle_now); |
1596 | ns >>= gtod->clock.shift; | |
cbcf2dd3 | 1597 | ns += gtod->boot_ns; |
d828199e | 1598 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1599 | *t = ns; |
d828199e MT |
1600 | |
1601 | return mode; | |
1602 | } | |
1603 | ||
1604 | /* returns true if host is using tsc clocksource */ | |
1605 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1606 | { | |
d828199e MT |
1607 | /* checked again under seqlock below */ |
1608 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1609 | return false; | |
1610 | ||
cbcf2dd3 | 1611 | return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; |
d828199e MT |
1612 | } |
1613 | #endif | |
1614 | ||
1615 | /* | |
1616 | * | |
b48aa97e MT |
1617 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1618 | * across virtual CPUs, the following condition is possible. | |
1619 | * Each numbered line represents an event visible to both | |
d828199e MT |
1620 | * CPUs at the next numbered event. |
1621 | * | |
1622 | * "timespecX" represents host monotonic time. "tscX" represents | |
1623 | * RDTSC value. | |
1624 | * | |
1625 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1626 | * | |
1627 | * 1. read timespec0,tsc0 | |
1628 | * 2. | timespec1 = timespec0 + N | |
1629 | * | tsc1 = tsc0 + M | |
1630 | * 3. transition to guest | transition to guest | |
1631 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1632 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1633 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1634 | * | |
1635 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1636 | * | |
1637 | * - ret0 < ret1 | |
1638 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1639 | * ... | |
1640 | * - 0 < N - M => M < N | |
1641 | * | |
1642 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1643 | * always the case (the difference between two distinct xtime instances | |
1644 | * might be smaller then the difference between corresponding TSC reads, | |
1645 | * when updating guest vcpus pvclock areas). | |
1646 | * | |
1647 | * To avoid that problem, do not allow visibility of distinct | |
1648 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1649 | * copy of host monotonic time values. Update that master copy | |
1650 | * in lockstep. | |
1651 | * | |
b48aa97e | 1652 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1653 | * |
1654 | */ | |
1655 | ||
1656 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1657 | { | |
1658 | #ifdef CONFIG_X86_64 | |
1659 | struct kvm_arch *ka = &kvm->arch; | |
1660 | int vclock_mode; | |
b48aa97e MT |
1661 | bool host_tsc_clocksource, vcpus_matched; |
1662 | ||
1663 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1664 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1665 | |
1666 | /* | |
1667 | * If the host uses TSC clock, then passthrough TSC as stable | |
1668 | * to the guest. | |
1669 | */ | |
b48aa97e | 1670 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1671 | &ka->master_kernel_ns, |
1672 | &ka->master_cycle_now); | |
1673 | ||
16a96021 | 1674 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
54750f2c MT |
1675 | && !backwards_tsc_observed |
1676 | && !ka->boot_vcpu_runs_old_kvmclock; | |
b48aa97e | 1677 | |
d828199e MT |
1678 | if (ka->use_master_clock) |
1679 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1680 | ||
1681 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1682 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1683 | vcpus_matched); | |
d828199e MT |
1684 | #endif |
1685 | } | |
1686 | ||
2e762ff7 MT |
1687 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1688 | { | |
1689 | #ifdef CONFIG_X86_64 | |
1690 | int i; | |
1691 | struct kvm_vcpu *vcpu; | |
1692 | struct kvm_arch *ka = &kvm->arch; | |
1693 | ||
1694 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1695 | kvm_make_mclock_inprogress_request(kvm); | |
1696 | /* no guest entries from this point */ | |
1697 | pvclock_update_vm_gtod_copy(kvm); | |
1698 | ||
1699 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1700 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1701 | |
1702 | /* guest entries allowed */ | |
1703 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1704 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1705 | ||
1706 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1707 | #endif | |
1708 | } | |
1709 | ||
34c238a1 | 1710 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1711 | { |
27cca94e | 1712 | unsigned long flags, this_tsc_khz, tgt_tsc_khz; |
18068523 | 1713 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1714 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1715 | s64 kernel_ns; |
d828199e | 1716 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1717 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1718 | u8 pvclock_flags; |
d828199e MT |
1719 | bool use_master_clock; |
1720 | ||
1721 | kernel_ns = 0; | |
1722 | host_tsc = 0; | |
18068523 | 1723 | |
d828199e MT |
1724 | /* |
1725 | * If the host uses TSC clock, then passthrough TSC as stable | |
1726 | * to the guest. | |
1727 | */ | |
1728 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1729 | use_master_clock = ka->use_master_clock; | |
1730 | if (use_master_clock) { | |
1731 | host_tsc = ka->master_cycle_now; | |
1732 | kernel_ns = ka->master_kernel_ns; | |
1733 | } | |
1734 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1735 | |
1736 | /* Keep irq disabled to prevent changes to the clock */ | |
1737 | local_irq_save(flags); | |
89cbc767 | 1738 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
c09664bb MT |
1739 | if (unlikely(this_tsc_khz == 0)) { |
1740 | local_irq_restore(flags); | |
1741 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1742 | return 1; | |
1743 | } | |
d828199e | 1744 | if (!use_master_clock) { |
4ea1636b | 1745 | host_tsc = rdtsc(); |
d828199e MT |
1746 | kernel_ns = get_kernel_ns(); |
1747 | } | |
1748 | ||
4ba76538 | 1749 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 1750 | |
c285545f ZA |
1751 | /* |
1752 | * We may have to catch up the TSC to match elapsed wall clock | |
1753 | * time for two reasons, even if kvmclock is used. | |
1754 | * 1) CPU could have been running below the maximum TSC rate | |
1755 | * 2) Broken TSC compensation resets the base at each VCPU | |
1756 | * entry to avoid unknown leaps of TSC even when running | |
1757 | * again on the same CPU. This may cause apparent elapsed | |
1758 | * time to disappear, and the guest to stand still or run | |
1759 | * very slowly. | |
1760 | */ | |
1761 | if (vcpu->tsc_catchup) { | |
1762 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1763 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1764 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1765 | tsc_timestamp = tsc; |
1766 | } | |
50d0a0f9 GH |
1767 | } |
1768 | ||
18068523 GOC |
1769 | local_irq_restore(flags); |
1770 | ||
0b79459b | 1771 | if (!vcpu->pv_time_enabled) |
c285545f | 1772 | return 0; |
18068523 | 1773 | |
e48672fa | 1774 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
27cca94e HZ |
1775 | tgt_tsc_khz = kvm_has_tsc_control ? |
1776 | vcpu->virtual_tsc_khz : this_tsc_khz; | |
1777 | kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz, | |
5f4e3f88 ZA |
1778 | &vcpu->hv_clock.tsc_shift, |
1779 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1780 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1781 | } |
1782 | ||
1783 | /* With all the info we got, fill in the values */ | |
1d5f066e | 1784 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1785 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 1786 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1787 | |
09a0c3f1 OH |
1788 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1789 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1790 | return 0; | |
1791 | ||
5dca0d91 RK |
1792 | /* This VCPU is paused, but it's legal for a guest to read another |
1793 | * VCPU's kvmclock, so we really have to follow the specification where | |
1794 | * it says that version is odd if data is being modified, and even after | |
1795 | * it is consistent. | |
1796 | * | |
1797 | * Version field updates must be kept separate. This is because | |
1798 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
1799 | * writes within a string instruction are weakly ordered. So there | |
1800 | * are three writes overall. | |
1801 | * | |
1802 | * As a small optimization, only write the version field in the first | |
1803 | * and third write. The vcpu->pv_time cache is still valid, because the | |
1804 | * version field is the first in the struct. | |
18068523 | 1805 | */ |
5dca0d91 RK |
1806 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); |
1807 | ||
1808 | vcpu->hv_clock.version = guest_hv_clock.version + 1; | |
1809 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1810 | &vcpu->hv_clock, | |
1811 | sizeof(vcpu->hv_clock.version)); | |
1812 | ||
1813 | smp_wmb(); | |
78c0337a MT |
1814 | |
1815 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1816 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1817 | |
1818 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1819 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1820 | vcpu->pvclock_set_guest_stopped_request = false; | |
1821 | } | |
1822 | ||
d828199e MT |
1823 | /* If the host uses TSC clocksource, then it is stable */ |
1824 | if (use_master_clock) | |
1825 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1826 | ||
78c0337a MT |
1827 | vcpu->hv_clock.flags = pvclock_flags; |
1828 | ||
ce1a5e60 DM |
1829 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
1830 | ||
0b79459b AH |
1831 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1832 | &vcpu->hv_clock, | |
1833 | sizeof(vcpu->hv_clock)); | |
5dca0d91 RK |
1834 | |
1835 | smp_wmb(); | |
1836 | ||
1837 | vcpu->hv_clock.version++; | |
1838 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1839 | &vcpu->hv_clock, | |
1840 | sizeof(vcpu->hv_clock.version)); | |
8cfdc000 | 1841 | return 0; |
c8076604 GH |
1842 | } |
1843 | ||
0061d53d MT |
1844 | /* |
1845 | * kvmclock updates which are isolated to a given vcpu, such as | |
1846 | * vcpu->cpu migration, should not allow system_timestamp from | |
1847 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1848 | * correction applies to one vcpu's system_timestamp but not | |
1849 | * the others. | |
1850 | * | |
1851 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
1852 | * We need to rate-limit these requests though, as they can |
1853 | * considerably slow guests that have a large number of vcpus. | |
1854 | * The time for a remote vcpu to update its kvmclock is bound | |
1855 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
1856 | */ |
1857 | ||
7e44e449 AJ |
1858 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
1859 | ||
1860 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
1861 | { |
1862 | int i; | |
7e44e449 AJ |
1863 | struct delayed_work *dwork = to_delayed_work(work); |
1864 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1865 | kvmclock_update_work); | |
1866 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
1867 | struct kvm_vcpu *vcpu; |
1868 | ||
1869 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 1870 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
1871 | kvm_vcpu_kick(vcpu); |
1872 | } | |
1873 | } | |
1874 | ||
7e44e449 AJ |
1875 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
1876 | { | |
1877 | struct kvm *kvm = v->kvm; | |
1878 | ||
105b21bb | 1879 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
1880 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
1881 | KVMCLOCK_UPDATE_DELAY); | |
1882 | } | |
1883 | ||
332967a3 AJ |
1884 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
1885 | ||
1886 | static void kvmclock_sync_fn(struct work_struct *work) | |
1887 | { | |
1888 | struct delayed_work *dwork = to_delayed_work(work); | |
1889 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1890 | kvmclock_sync_work); | |
1891 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1892 | ||
630994b3 MT |
1893 | if (!kvmclock_periodic_sync) |
1894 | return; | |
1895 | ||
332967a3 AJ |
1896 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
1897 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
1898 | KVMCLOCK_SYNC_PERIOD); | |
1899 | } | |
1900 | ||
890ca9ae | 1901 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1902 | { |
890ca9ae HY |
1903 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1904 | unsigned bank_num = mcg_cap & 0xff; | |
1905 | ||
15c4a640 | 1906 | switch (msr) { |
15c4a640 | 1907 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1908 | vcpu->arch.mcg_status = data; |
15c4a640 | 1909 | break; |
c7ac679c | 1910 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1911 | if (!(mcg_cap & MCG_CTL_P)) |
1912 | return 1; | |
1913 | if (data != 0 && data != ~(u64)0) | |
1914 | return -1; | |
1915 | vcpu->arch.mcg_ctl = data; | |
1916 | break; | |
1917 | default: | |
1918 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 1919 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 1920 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
1921 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1922 | * some Linux kernels though clear bit 10 in bank 4 to | |
1923 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1924 | * this to avoid an uncatched #GP in the guest | |
1925 | */ | |
890ca9ae | 1926 | if ((offset & 0x3) == 0 && |
114be429 | 1927 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1928 | return -1; |
1929 | vcpu->arch.mce_banks[offset] = data; | |
1930 | break; | |
1931 | } | |
1932 | return 1; | |
1933 | } | |
1934 | return 0; | |
1935 | } | |
1936 | ||
ffde22ac ES |
1937 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1938 | { | |
1939 | struct kvm *kvm = vcpu->kvm; | |
1940 | int lm = is_long_mode(vcpu); | |
1941 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1942 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1943 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1944 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1945 | u32 page_num = data & ~PAGE_MASK; | |
1946 | u64 page_addr = data & PAGE_MASK; | |
1947 | u8 *page; | |
1948 | int r; | |
1949 | ||
1950 | r = -E2BIG; | |
1951 | if (page_num >= blob_size) | |
1952 | goto out; | |
1953 | r = -ENOMEM; | |
ff5c2c03 SL |
1954 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
1955 | if (IS_ERR(page)) { | |
1956 | r = PTR_ERR(page); | |
ffde22ac | 1957 | goto out; |
ff5c2c03 | 1958 | } |
54bf36aa | 1959 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
1960 | goto out_free; |
1961 | r = 0; | |
1962 | out_free: | |
1963 | kfree(page); | |
1964 | out: | |
1965 | return r; | |
1966 | } | |
1967 | ||
344d9588 GN |
1968 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
1969 | { | |
1970 | gpa_t gpa = data & ~0x3f; | |
1971 | ||
4a969980 | 1972 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 1973 | if (data & 0x3c) |
344d9588 GN |
1974 | return 1; |
1975 | ||
1976 | vcpu->arch.apf.msr_val = data; | |
1977 | ||
1978 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1979 | kvm_clear_async_pf_completion_queue(vcpu); | |
1980 | kvm_async_pf_hash_reset(vcpu); | |
1981 | return 0; | |
1982 | } | |
1983 | ||
8f964525 AH |
1984 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
1985 | sizeof(u32))) | |
344d9588 GN |
1986 | return 1; |
1987 | ||
6adba527 | 1988 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
1989 | kvm_async_pf_wakeup_all(vcpu); |
1990 | return 0; | |
1991 | } | |
1992 | ||
12f9a48f GC |
1993 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
1994 | { | |
0b79459b | 1995 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
1996 | } |
1997 | ||
c9aaa895 GC |
1998 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
1999 | { | |
2000 | u64 delta; | |
2001 | ||
2002 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2003 | return; | |
2004 | ||
2005 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
2006 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2007 | vcpu->arch.st.accum_steal = delta; | |
2008 | } | |
2009 | ||
2010 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
2011 | { | |
7cae2bed MT |
2012 | accumulate_steal_time(vcpu); |
2013 | ||
c9aaa895 GC |
2014 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
2015 | return; | |
2016 | ||
2017 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2018 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
2019 | return; | |
2020 | ||
2021 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
2022 | vcpu->arch.st.steal.version += 2; | |
2023 | vcpu->arch.st.accum_steal = 0; | |
2024 | ||
2025 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2026 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2027 | } | |
2028 | ||
8fe8ab46 | 2029 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2030 | { |
5753785f | 2031 | bool pr = false; |
8fe8ab46 WA |
2032 | u32 msr = msr_info->index; |
2033 | u64 data = msr_info->data; | |
5753785f | 2034 | |
15c4a640 | 2035 | switch (msr) { |
2e32b719 BP |
2036 | case MSR_AMD64_NB_CFG: |
2037 | case MSR_IA32_UCODE_REV: | |
2038 | case MSR_IA32_UCODE_WRITE: | |
2039 | case MSR_VM_HSAVE_PA: | |
2040 | case MSR_AMD64_PATCH_LOADER: | |
2041 | case MSR_AMD64_BU_CFG2: | |
2042 | break; | |
2043 | ||
15c4a640 | 2044 | case MSR_EFER: |
b69e8cae | 2045 | return set_efer(vcpu, data); |
8f1589d9 AP |
2046 | case MSR_K7_HWCR: |
2047 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2048 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2049 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2050 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2051 | if (data != 0) { |
a737f256 CD |
2052 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2053 | data); | |
8f1589d9 AP |
2054 | return 1; |
2055 | } | |
15c4a640 | 2056 | break; |
f7c6d140 AP |
2057 | case MSR_FAM10H_MMIO_CONF_BASE: |
2058 | if (data != 0) { | |
a737f256 CD |
2059 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2060 | "0x%llx\n", data); | |
f7c6d140 AP |
2061 | return 1; |
2062 | } | |
15c4a640 | 2063 | break; |
b5e2fec0 AG |
2064 | case MSR_IA32_DEBUGCTLMSR: |
2065 | if (!data) { | |
2066 | /* We support the non-activated case already */ | |
2067 | break; | |
2068 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2069 | /* Values other than LBR and BTF are vendor-specific, | |
2070 | thus reserved and should throw a #GP */ | |
2071 | return 1; | |
2072 | } | |
a737f256 CD |
2073 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2074 | __func__, data); | |
b5e2fec0 | 2075 | break; |
9ba075a6 | 2076 | case 0x200 ... 0x2ff: |
ff53604b | 2077 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2078 | case MSR_IA32_APICBASE: |
58cb628d | 2079 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2080 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2081 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2082 | case MSR_IA32_TSCDEADLINE: |
2083 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2084 | break; | |
ba904635 WA |
2085 | case MSR_IA32_TSC_ADJUST: |
2086 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2087 | if (!msr_info->host_initiated) { | |
d913b904 | 2088 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 2089 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
2090 | } |
2091 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2092 | } | |
2093 | break; | |
15c4a640 | 2094 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2095 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2096 | break; |
64d60670 PB |
2097 | case MSR_IA32_SMBASE: |
2098 | if (!msr_info->host_initiated) | |
2099 | return 1; | |
2100 | vcpu->arch.smbase = data; | |
2101 | break; | |
11c6bffa | 2102 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2103 | case MSR_KVM_WALL_CLOCK: |
2104 | vcpu->kvm->arch.wall_clock = data; | |
2105 | kvm_write_wall_clock(vcpu->kvm, data); | |
2106 | break; | |
11c6bffa | 2107 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2108 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 2109 | u64 gpa_offset; |
54750f2c MT |
2110 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2111 | ||
12f9a48f | 2112 | kvmclock_reset(vcpu); |
18068523 | 2113 | |
54750f2c MT |
2114 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2115 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2116 | ||
2117 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
2118 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, | |
2119 | &vcpu->requests); | |
2120 | ||
2121 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2122 | } | |
2123 | ||
18068523 | 2124 | vcpu->arch.time = data; |
0061d53d | 2125 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2126 | |
2127 | /* we verify if the enable bit is set... */ | |
2128 | if (!(data & 1)) | |
2129 | break; | |
2130 | ||
0b79459b | 2131 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 2132 | |
0b79459b | 2133 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2134 | &vcpu->arch.pv_time, data & ~1ULL, |
2135 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2136 | vcpu->arch.pv_time_enabled = false; |
2137 | else | |
2138 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2139 | |
18068523 GOC |
2140 | break; |
2141 | } | |
344d9588 GN |
2142 | case MSR_KVM_ASYNC_PF_EN: |
2143 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2144 | return 1; | |
2145 | break; | |
c9aaa895 GC |
2146 | case MSR_KVM_STEAL_TIME: |
2147 | ||
2148 | if (unlikely(!sched_info_on())) | |
2149 | return 1; | |
2150 | ||
2151 | if (data & KVM_STEAL_RESERVED_MASK) | |
2152 | return 1; | |
2153 | ||
2154 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2155 | data & KVM_STEAL_VALID_BITS, |
2156 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2157 | return 1; |
2158 | ||
2159 | vcpu->arch.st.msr_val = data; | |
2160 | ||
2161 | if (!(data & KVM_MSR_ENABLED)) | |
2162 | break; | |
2163 | ||
c9aaa895 GC |
2164 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
2165 | ||
2166 | break; | |
ae7a2a3f MT |
2167 | case MSR_KVM_PV_EOI_EN: |
2168 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2169 | return 1; | |
2170 | break; | |
c9aaa895 | 2171 | |
890ca9ae HY |
2172 | case MSR_IA32_MCG_CTL: |
2173 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2174 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2175 | return set_msr_mce(vcpu, msr, data); |
71db6023 | 2176 | |
6912ac32 WH |
2177 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
2178 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2179 | pr = true; /* fall through */ | |
2180 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: | |
2181 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2182 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2183 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2184 | |
2185 | if (pr || data != 0) | |
a737f256 CD |
2186 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2187 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2188 | break; |
84e0cefa JS |
2189 | case MSR_K7_CLK_CTL: |
2190 | /* | |
2191 | * Ignore all writes to this no longer documented MSR. | |
2192 | * Writes are only relevant for old K7 processors, | |
2193 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2194 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2195 | * affected processor models on the command line, hence |
2196 | * the need to ignore the workaround. | |
2197 | */ | |
2198 | break; | |
55cd8e5a | 2199 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2200 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2201 | case HV_X64_MSR_CRASH_CTL: | |
2202 | return kvm_hv_set_msr_common(vcpu, msr, data, | |
2203 | msr_info->host_initiated); | |
91c9c3ed | 2204 | case MSR_IA32_BBL_CR_CTL3: |
2205 | /* Drop writes to this legacy MSR -- see rdmsr | |
2206 | * counterpart for further detail. | |
2207 | */ | |
a737f256 | 2208 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2209 | break; |
2b036c6b BO |
2210 | case MSR_AMD64_OSVW_ID_LENGTH: |
2211 | if (!guest_cpuid_has_osvw(vcpu)) | |
2212 | return 1; | |
2213 | vcpu->arch.osvw.length = data; | |
2214 | break; | |
2215 | case MSR_AMD64_OSVW_STATUS: | |
2216 | if (!guest_cpuid_has_osvw(vcpu)) | |
2217 | return 1; | |
2218 | vcpu->arch.osvw.status = data; | |
2219 | break; | |
15c4a640 | 2220 | default: |
ffde22ac ES |
2221 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2222 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 2223 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2224 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2225 | if (!ignore_msrs) { |
a737f256 CD |
2226 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2227 | msr, data); | |
ed85c068 AP |
2228 | return 1; |
2229 | } else { | |
a737f256 CD |
2230 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2231 | msr, data); | |
ed85c068 AP |
2232 | break; |
2233 | } | |
15c4a640 CO |
2234 | } |
2235 | return 0; | |
2236 | } | |
2237 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2238 | ||
2239 | ||
2240 | /* | |
2241 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2242 | * Returns 0 on success, non-0 otherwise. | |
2243 | * Assumes vcpu_load() was already called. | |
2244 | */ | |
609e36d3 | 2245 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 2246 | { |
609e36d3 | 2247 | return kvm_x86_ops->get_msr(vcpu, msr); |
15c4a640 | 2248 | } |
ff651cb6 | 2249 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2250 | |
890ca9ae | 2251 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2252 | { |
2253 | u64 data; | |
890ca9ae HY |
2254 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2255 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2256 | |
2257 | switch (msr) { | |
15c4a640 CO |
2258 | case MSR_IA32_P5_MC_ADDR: |
2259 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2260 | data = 0; |
2261 | break; | |
15c4a640 | 2262 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2263 | data = vcpu->arch.mcg_cap; |
2264 | break; | |
c7ac679c | 2265 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2266 | if (!(mcg_cap & MCG_CTL_P)) |
2267 | return 1; | |
2268 | data = vcpu->arch.mcg_ctl; | |
2269 | break; | |
2270 | case MSR_IA32_MCG_STATUS: | |
2271 | data = vcpu->arch.mcg_status; | |
2272 | break; | |
2273 | default: | |
2274 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2275 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2276 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2277 | data = vcpu->arch.mce_banks[offset]; | |
2278 | break; | |
2279 | } | |
2280 | return 1; | |
2281 | } | |
2282 | *pdata = data; | |
2283 | return 0; | |
2284 | } | |
2285 | ||
609e36d3 | 2286 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 2287 | { |
609e36d3 | 2288 | switch (msr_info->index) { |
890ca9ae | 2289 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2290 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2291 | case MSR_IA32_DEBUGCTLMSR: |
2292 | case MSR_IA32_LASTBRANCHFROMIP: | |
2293 | case MSR_IA32_LASTBRANCHTOIP: | |
2294 | case MSR_IA32_LASTINTFROMIP: | |
2295 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 2296 | case MSR_K8_SYSCFG: |
3afb1121 PB |
2297 | case MSR_K8_TSEG_ADDR: |
2298 | case MSR_K8_TSEG_MASK: | |
60af2ecd | 2299 | case MSR_K7_HWCR: |
61a6bd67 | 2300 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 2301 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2302 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2303 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2304 | case MSR_AMD64_BU_CFG2: |
609e36d3 | 2305 | msr_info->data = 0; |
15c4a640 | 2306 | break; |
6912ac32 WH |
2307 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
2308 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
2309 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2310 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2311 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 PB |
2312 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
2313 | msr_info->data = 0; | |
5753785f | 2314 | break; |
742bc670 | 2315 | case MSR_IA32_UCODE_REV: |
609e36d3 | 2316 | msr_info->data = 0x100000000ULL; |
742bc670 | 2317 | break; |
9ba075a6 | 2318 | case MSR_MTRRcap: |
9ba075a6 | 2319 | case 0x200 ... 0x2ff: |
ff53604b | 2320 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 2321 | case 0xcd: /* fsb frequency */ |
609e36d3 | 2322 | msr_info->data = 3; |
15c4a640 | 2323 | break; |
7b914098 JS |
2324 | /* |
2325 | * MSR_EBC_FREQUENCY_ID | |
2326 | * Conservative value valid for even the basic CPU models. | |
2327 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2328 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2329 | * and 266MHz for model 3, or 4. Set Core Clock | |
2330 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2331 | * 31:24) even though these are only valid for CPU | |
2332 | * models > 2, however guests may end up dividing or | |
2333 | * multiplying by zero otherwise. | |
2334 | */ | |
2335 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 2336 | msr_info->data = 1 << 24; |
7b914098 | 2337 | break; |
15c4a640 | 2338 | case MSR_IA32_APICBASE: |
609e36d3 | 2339 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 2340 | break; |
0105d1a5 | 2341 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 2342 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 2343 | break; |
a3e06bbe | 2344 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 2345 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 2346 | break; |
ba904635 | 2347 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 2348 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 2349 | break; |
15c4a640 | 2350 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 2351 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2352 | break; |
64d60670 PB |
2353 | case MSR_IA32_SMBASE: |
2354 | if (!msr_info->host_initiated) | |
2355 | return 1; | |
2356 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 2357 | break; |
847f0ad8 AG |
2358 | case MSR_IA32_PERF_STATUS: |
2359 | /* TSC increment by tick */ | |
609e36d3 | 2360 | msr_info->data = 1000ULL; |
847f0ad8 | 2361 | /* CPU multiplier */ |
b0996ae4 | 2362 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 2363 | break; |
15c4a640 | 2364 | case MSR_EFER: |
609e36d3 | 2365 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 2366 | break; |
18068523 | 2367 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2368 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 2369 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
2370 | break; |
2371 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2372 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 2373 | msr_info->data = vcpu->arch.time; |
18068523 | 2374 | break; |
344d9588 | 2375 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 2376 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 2377 | break; |
c9aaa895 | 2378 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 2379 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 2380 | break; |
1d92128f | 2381 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 2382 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 2383 | break; |
890ca9ae HY |
2384 | case MSR_IA32_P5_MC_ADDR: |
2385 | case MSR_IA32_P5_MC_TYPE: | |
2386 | case MSR_IA32_MCG_CAP: | |
2387 | case MSR_IA32_MCG_CTL: | |
2388 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2389 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
609e36d3 | 2390 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data); |
84e0cefa JS |
2391 | case MSR_K7_CLK_CTL: |
2392 | /* | |
2393 | * Provide expected ramp-up count for K7. All other | |
2394 | * are set to zero, indicating minimum divisors for | |
2395 | * every field. | |
2396 | * | |
2397 | * This prevents guest kernels on AMD host with CPU | |
2398 | * type 6, model 8 and higher from exploding due to | |
2399 | * the rdmsr failing. | |
2400 | */ | |
609e36d3 | 2401 | msr_info->data = 0x20000000; |
84e0cefa | 2402 | break; |
55cd8e5a | 2403 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2404 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2405 | case HV_X64_MSR_CRASH_CTL: | |
e83d5887 AS |
2406 | return kvm_hv_get_msr_common(vcpu, |
2407 | msr_info->index, &msr_info->data); | |
55cd8e5a | 2408 | break; |
91c9c3ed | 2409 | case MSR_IA32_BBL_CR_CTL3: |
2410 | /* This legacy MSR exists but isn't fully documented in current | |
2411 | * silicon. It is however accessed by winxp in very narrow | |
2412 | * scenarios where it sets bit #19, itself documented as | |
2413 | * a "reserved" bit. Best effort attempt to source coherent | |
2414 | * read data here should the balance of the register be | |
2415 | * interpreted by the guest: | |
2416 | * | |
2417 | * L2 cache control register 3: 64GB range, 256KB size, | |
2418 | * enabled, latency 0x1, configured | |
2419 | */ | |
609e36d3 | 2420 | msr_info->data = 0xbe702111; |
91c9c3ed | 2421 | break; |
2b036c6b BO |
2422 | case MSR_AMD64_OSVW_ID_LENGTH: |
2423 | if (!guest_cpuid_has_osvw(vcpu)) | |
2424 | return 1; | |
609e36d3 | 2425 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
2426 | break; |
2427 | case MSR_AMD64_OSVW_STATUS: | |
2428 | if (!guest_cpuid_has_osvw(vcpu)) | |
2429 | return 1; | |
609e36d3 | 2430 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 2431 | break; |
15c4a640 | 2432 | default: |
c6702c9d | 2433 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 | 2434 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
ed85c068 | 2435 | if (!ignore_msrs) { |
609e36d3 | 2436 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); |
ed85c068 AP |
2437 | return 1; |
2438 | } else { | |
609e36d3 PB |
2439 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); |
2440 | msr_info->data = 0; | |
ed85c068 AP |
2441 | } |
2442 | break; | |
15c4a640 | 2443 | } |
15c4a640 CO |
2444 | return 0; |
2445 | } | |
2446 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2447 | ||
313a3dc7 CO |
2448 | /* |
2449 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2450 | * | |
2451 | * @return number of msrs set successfully. | |
2452 | */ | |
2453 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2454 | struct kvm_msr_entry *entries, | |
2455 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2456 | unsigned index, u64 *data)) | |
2457 | { | |
f656ce01 | 2458 | int i, idx; |
313a3dc7 | 2459 | |
f656ce01 | 2460 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2461 | for (i = 0; i < msrs->nmsrs; ++i) |
2462 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2463 | break; | |
f656ce01 | 2464 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2465 | |
313a3dc7 CO |
2466 | return i; |
2467 | } | |
2468 | ||
2469 | /* | |
2470 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2471 | * | |
2472 | * @return number of msrs set successfully. | |
2473 | */ | |
2474 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2475 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2476 | unsigned index, u64 *data), | |
2477 | int writeback) | |
2478 | { | |
2479 | struct kvm_msrs msrs; | |
2480 | struct kvm_msr_entry *entries; | |
2481 | int r, n; | |
2482 | unsigned size; | |
2483 | ||
2484 | r = -EFAULT; | |
2485 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2486 | goto out; | |
2487 | ||
2488 | r = -E2BIG; | |
2489 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2490 | goto out; | |
2491 | ||
313a3dc7 | 2492 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2493 | entries = memdup_user(user_msrs->entries, size); |
2494 | if (IS_ERR(entries)) { | |
2495 | r = PTR_ERR(entries); | |
313a3dc7 | 2496 | goto out; |
ff5c2c03 | 2497 | } |
313a3dc7 CO |
2498 | |
2499 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2500 | if (r < 0) | |
2501 | goto out_free; | |
2502 | ||
2503 | r = -EFAULT; | |
2504 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2505 | goto out_free; | |
2506 | ||
2507 | r = n; | |
2508 | ||
2509 | out_free: | |
7a73c028 | 2510 | kfree(entries); |
313a3dc7 CO |
2511 | out: |
2512 | return r; | |
2513 | } | |
2514 | ||
784aa3d7 | 2515 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 ZX |
2516 | { |
2517 | int r; | |
2518 | ||
2519 | switch (ext) { | |
2520 | case KVM_CAP_IRQCHIP: | |
2521 | case KVM_CAP_HLT: | |
2522 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2523 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2524 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2525 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2526 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2527 | case KVM_CAP_PIT: |
a28e4f5a | 2528 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2529 | case KVM_CAP_MP_STATE: |
ed848624 | 2530 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2531 | case KVM_CAP_USER_NMI: |
52d939a0 | 2532 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2533 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 2534 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2535 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2536 | case KVM_CAP_PIT2: |
e9f42757 | 2537 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2538 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2539 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2540 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2541 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2542 | case KVM_CAP_HYPERV: |
10388a07 | 2543 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2544 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 2545 | case KVM_CAP_HYPERV_SYNIC: |
ab9f4ecb | 2546 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2547 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2548 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2549 | case KVM_CAP_XSAVE: |
344d9588 | 2550 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2551 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2552 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2553 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2554 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2555 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 2556 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 NA |
2557 | case KVM_CAP_ENABLE_CAP_VM: |
2558 | case KVM_CAP_DISABLE_QUIRKS: | |
d71ba788 | 2559 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 2560 | case KVM_CAP_SPLIT_IRQCHIP: |
2a5bab10 AW |
2561 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2562 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2563 | case KVM_CAP_PCI_2_3: | |
2564 | #endif | |
018d00d2 ZX |
2565 | r = 1; |
2566 | break; | |
6d396b55 PB |
2567 | case KVM_CAP_X86_SMM: |
2568 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
2569 | * and SMM handlers might indeed rely on 4G segment limits, | |
2570 | * so do not report SMM to be available if real mode is | |
2571 | * emulated via vm86 mode. Still, do not go to great lengths | |
2572 | * to avoid userspace's usage of the feature, because it is a | |
2573 | * fringe case that is not enabled except via specific settings | |
2574 | * of the module parameters. | |
2575 | */ | |
2576 | r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); | |
2577 | break; | |
542472b5 LV |
2578 | case KVM_CAP_COALESCED_MMIO: |
2579 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2580 | break; | |
774ead3a AK |
2581 | case KVM_CAP_VAPIC: |
2582 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2583 | break; | |
f725230a | 2584 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2585 | r = KVM_SOFT_MAX_VCPUS; |
2586 | break; | |
2587 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2588 | r = KVM_MAX_VCPUS; |
2589 | break; | |
a988b910 | 2590 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2591 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2592 | break; |
a68a6a72 MT |
2593 | case KVM_CAP_PV_MMU: /* obsolete */ |
2594 | r = 0; | |
2f333bcb | 2595 | break; |
4cee4b72 | 2596 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2597 | case KVM_CAP_IOMMU: |
a1b60c1c | 2598 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2599 | break; |
4cee4b72 | 2600 | #endif |
890ca9ae HY |
2601 | case KVM_CAP_MCE: |
2602 | r = KVM_MAX_MCE_BANKS; | |
2603 | break; | |
2d5b5a66 SY |
2604 | case KVM_CAP_XCRS: |
2605 | r = cpu_has_xsave; | |
2606 | break; | |
92a1f12d JR |
2607 | case KVM_CAP_TSC_CONTROL: |
2608 | r = kvm_has_tsc_control; | |
2609 | break; | |
018d00d2 ZX |
2610 | default: |
2611 | r = 0; | |
2612 | break; | |
2613 | } | |
2614 | return r; | |
2615 | ||
2616 | } | |
2617 | ||
043405e1 CO |
2618 | long kvm_arch_dev_ioctl(struct file *filp, |
2619 | unsigned int ioctl, unsigned long arg) | |
2620 | { | |
2621 | void __user *argp = (void __user *)arg; | |
2622 | long r; | |
2623 | ||
2624 | switch (ioctl) { | |
2625 | case KVM_GET_MSR_INDEX_LIST: { | |
2626 | struct kvm_msr_list __user *user_msr_list = argp; | |
2627 | struct kvm_msr_list msr_list; | |
2628 | unsigned n; | |
2629 | ||
2630 | r = -EFAULT; | |
2631 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2632 | goto out; | |
2633 | n = msr_list.nmsrs; | |
62ef68bb | 2634 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
043405e1 CO |
2635 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) |
2636 | goto out; | |
2637 | r = -E2BIG; | |
e125e7b6 | 2638 | if (n < msr_list.nmsrs) |
043405e1 CO |
2639 | goto out; |
2640 | r = -EFAULT; | |
2641 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2642 | num_msrs_to_save * sizeof(u32))) | |
2643 | goto out; | |
e125e7b6 | 2644 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 2645 | &emulated_msrs, |
62ef68bb | 2646 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
2647 | goto out; |
2648 | r = 0; | |
2649 | break; | |
2650 | } | |
9c15bb1d BP |
2651 | case KVM_GET_SUPPORTED_CPUID: |
2652 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2653 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2654 | struct kvm_cpuid2 cpuid; | |
2655 | ||
2656 | r = -EFAULT; | |
2657 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2658 | goto out; | |
9c15bb1d BP |
2659 | |
2660 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2661 | ioctl); | |
674eea0f AK |
2662 | if (r) |
2663 | goto out; | |
2664 | ||
2665 | r = -EFAULT; | |
2666 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2667 | goto out; | |
2668 | r = 0; | |
2669 | break; | |
2670 | } | |
890ca9ae HY |
2671 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2672 | u64 mce_cap; | |
2673 | ||
2674 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2675 | r = -EFAULT; | |
2676 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2677 | goto out; | |
2678 | r = 0; | |
2679 | break; | |
2680 | } | |
043405e1 CO |
2681 | default: |
2682 | r = -EINVAL; | |
2683 | } | |
2684 | out: | |
2685 | return r; | |
2686 | } | |
2687 | ||
f5f48ee1 SY |
2688 | static void wbinvd_ipi(void *garbage) |
2689 | { | |
2690 | wbinvd(); | |
2691 | } | |
2692 | ||
2693 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2694 | { | |
e0f0bbc5 | 2695 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
2696 | } |
2697 | ||
313a3dc7 CO |
2698 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
2699 | { | |
f5f48ee1 SY |
2700 | /* Address WBINVD may be executed by guest */ |
2701 | if (need_emulate_wbinvd(vcpu)) { | |
2702 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2703 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2704 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2705 | smp_call_function_single(vcpu->cpu, | |
2706 | wbinvd_ipi, NULL, 1); | |
2707 | } | |
2708 | ||
313a3dc7 | 2709 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 2710 | |
0dd6a6ed ZA |
2711 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
2712 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2713 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2714 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 2715 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 2716 | } |
8f6055cb | 2717 | |
48434c20 | 2718 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 | 2719 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 2720 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
2721 | if (tsc_delta < 0) |
2722 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 2723 | if (check_tsc_unstable()) { |
07c1419a | 2724 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 ZA |
2725 | vcpu->arch.last_guest_tsc); |
2726 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 2727 | vcpu->arch.tsc_catchup = 1; |
c285545f | 2728 | } |
d98d07ca MT |
2729 | /* |
2730 | * On a host with synchronized TSC, there is no need to update | |
2731 | * kvmclock on vcpu->cpu migration | |
2732 | */ | |
2733 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 2734 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f ZA |
2735 | if (vcpu->cpu != cpu) |
2736 | kvm_migrate_timers(vcpu); | |
e48672fa | 2737 | vcpu->cpu = cpu; |
6b7d7e76 | 2738 | } |
c9aaa895 | 2739 | |
c9aaa895 | 2740 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
2741 | } |
2742 | ||
2743 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2744 | { | |
02daab21 | 2745 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 2746 | kvm_put_guest_fpu(vcpu); |
4ea1636b | 2747 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
2748 | } |
2749 | ||
313a3dc7 CO |
2750 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2751 | struct kvm_lapic_state *s) | |
2752 | { | |
d62caabb AS |
2753 | if (vcpu->arch.apicv_active) |
2754 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
2755 | ||
ad312c7c | 2756 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2757 | |
2758 | return 0; | |
2759 | } | |
2760 | ||
2761 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2762 | struct kvm_lapic_state *s) | |
2763 | { | |
64eb0620 | 2764 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 2765 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2766 | |
2767 | return 0; | |
2768 | } | |
2769 | ||
127a457a MG |
2770 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
2771 | { | |
2772 | return (!lapic_in_kernel(vcpu) || | |
2773 | kvm_apic_accept_pic_intr(vcpu)); | |
2774 | } | |
2775 | ||
782d422b MG |
2776 | /* |
2777 | * if userspace requested an interrupt window, check that the | |
2778 | * interrupt window is open. | |
2779 | * | |
2780 | * No need to exit to userspace if we already have an interrupt queued. | |
2781 | */ | |
2782 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
2783 | { | |
2784 | return kvm_arch_interrupt_allowed(vcpu) && | |
2785 | !kvm_cpu_has_interrupt(vcpu) && | |
2786 | !kvm_event_needs_reinjection(vcpu) && | |
2787 | kvm_cpu_accept_dm_intr(vcpu); | |
2788 | } | |
2789 | ||
f77bc6a4 ZX |
2790 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2791 | struct kvm_interrupt *irq) | |
2792 | { | |
02cdb50f | 2793 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 2794 | return -EINVAL; |
1c1a9ce9 SR |
2795 | |
2796 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
2797 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
2798 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
2799 | return 0; | |
2800 | } | |
2801 | ||
2802 | /* | |
2803 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
2804 | * fail for in-kernel 8259. | |
2805 | */ | |
2806 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 2807 | return -ENXIO; |
f77bc6a4 | 2808 | |
1c1a9ce9 SR |
2809 | if (vcpu->arch.pending_external_vector != -1) |
2810 | return -EEXIST; | |
f77bc6a4 | 2811 | |
1c1a9ce9 | 2812 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 2813 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
2814 | return 0; |
2815 | } | |
2816 | ||
c4abb7c9 JK |
2817 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2818 | { | |
c4abb7c9 | 2819 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2820 | |
2821 | return 0; | |
2822 | } | |
2823 | ||
f077825a PB |
2824 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
2825 | { | |
64d60670 PB |
2826 | kvm_make_request(KVM_REQ_SMI, vcpu); |
2827 | ||
f077825a PB |
2828 | return 0; |
2829 | } | |
2830 | ||
b209749f AK |
2831 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2832 | struct kvm_tpr_access_ctl *tac) | |
2833 | { | |
2834 | if (tac->flags) | |
2835 | return -EINVAL; | |
2836 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2837 | return 0; | |
2838 | } | |
2839 | ||
890ca9ae HY |
2840 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2841 | u64 mcg_cap) | |
2842 | { | |
2843 | int r; | |
2844 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2845 | ||
2846 | r = -EINVAL; | |
a9e38c3e | 2847 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2848 | goto out; |
2849 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2850 | goto out; | |
2851 | r = 0; | |
2852 | vcpu->arch.mcg_cap = mcg_cap; | |
2853 | /* Init IA32_MCG_CTL to all 1s */ | |
2854 | if (mcg_cap & MCG_CTL_P) | |
2855 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2856 | /* Init IA32_MCi_CTL to all 1s */ | |
2857 | for (bank = 0; bank < bank_num; bank++) | |
2858 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2859 | out: | |
2860 | return r; | |
2861 | } | |
2862 | ||
2863 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2864 | struct kvm_x86_mce *mce) | |
2865 | { | |
2866 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2867 | unsigned bank_num = mcg_cap & 0xff; | |
2868 | u64 *banks = vcpu->arch.mce_banks; | |
2869 | ||
2870 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2871 | return -EINVAL; | |
2872 | /* | |
2873 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2874 | * reporting is disabled | |
2875 | */ | |
2876 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2877 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2878 | return 0; | |
2879 | banks += 4 * mce->bank; | |
2880 | /* | |
2881 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2882 | * reporting is disabled for the bank | |
2883 | */ | |
2884 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2885 | return 0; | |
2886 | if (mce->status & MCI_STATUS_UC) { | |
2887 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2888 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 2889 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2890 | return 0; |
2891 | } | |
2892 | if (banks[1] & MCI_STATUS_VAL) | |
2893 | mce->status |= MCI_STATUS_OVER; | |
2894 | banks[2] = mce->addr; | |
2895 | banks[3] = mce->misc; | |
2896 | vcpu->arch.mcg_status = mce->mcg_status; | |
2897 | banks[1] = mce->status; | |
2898 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2899 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2900 | || !(banks[1] & MCI_STATUS_UC)) { | |
2901 | if (banks[1] & MCI_STATUS_VAL) | |
2902 | mce->status |= MCI_STATUS_OVER; | |
2903 | banks[2] = mce->addr; | |
2904 | banks[3] = mce->misc; | |
2905 | banks[1] = mce->status; | |
2906 | } else | |
2907 | banks[1] |= MCI_STATUS_OVER; | |
2908 | return 0; | |
2909 | } | |
2910 | ||
3cfc3092 JK |
2911 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2912 | struct kvm_vcpu_events *events) | |
2913 | { | |
7460fb4a | 2914 | process_nmi(vcpu); |
03b82a30 JK |
2915 | events->exception.injected = |
2916 | vcpu->arch.exception.pending && | |
2917 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2918 | events->exception.nr = vcpu->arch.exception.nr; |
2919 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 2920 | events->exception.pad = 0; |
3cfc3092 JK |
2921 | events->exception.error_code = vcpu->arch.exception.error_code; |
2922 | ||
03b82a30 JK |
2923 | events->interrupt.injected = |
2924 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2925 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2926 | events->interrupt.soft = 0; |
37ccdcbe | 2927 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
2928 | |
2929 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 2930 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 2931 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 2932 | events->nmi.pad = 0; |
3cfc3092 | 2933 | |
66450a21 | 2934 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 2935 | |
f077825a PB |
2936 | events->smi.smm = is_smm(vcpu); |
2937 | events->smi.pending = vcpu->arch.smi_pending; | |
2938 | events->smi.smm_inside_nmi = | |
2939 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
2940 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
2941 | ||
dab4b911 | 2942 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
2943 | | KVM_VCPUEVENT_VALID_SHADOW |
2944 | | KVM_VCPUEVENT_VALID_SMM); | |
97e69aa6 | 2945 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
2946 | } |
2947 | ||
2948 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2949 | struct kvm_vcpu_events *events) | |
2950 | { | |
dab4b911 | 2951 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 2952 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a PB |
2953 | | KVM_VCPUEVENT_VALID_SHADOW |
2954 | | KVM_VCPUEVENT_VALID_SMM)) | |
3cfc3092 JK |
2955 | return -EINVAL; |
2956 | ||
7460fb4a | 2957 | process_nmi(vcpu); |
3cfc3092 JK |
2958 | vcpu->arch.exception.pending = events->exception.injected; |
2959 | vcpu->arch.exception.nr = events->exception.nr; | |
2960 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2961 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2962 | ||
2963 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2964 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2965 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
2966 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2967 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2968 | events->interrupt.shadow); | |
3cfc3092 JK |
2969 | |
2970 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2971 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2972 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2973 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2974 | ||
66450a21 JK |
2975 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
2976 | kvm_vcpu_has_lapic(vcpu)) | |
2977 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
3cfc3092 | 2978 | |
f077825a PB |
2979 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
2980 | if (events->smi.smm) | |
2981 | vcpu->arch.hflags |= HF_SMM_MASK; | |
2982 | else | |
2983 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
2984 | vcpu->arch.smi_pending = events->smi.pending; | |
2985 | if (events->smi.smm_inside_nmi) | |
2986 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
2987 | else | |
2988 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; | |
2989 | if (kvm_vcpu_has_lapic(vcpu)) { | |
2990 | if (events->smi.latched_init) | |
2991 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
2992 | else | |
2993 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
2994 | } | |
2995 | } | |
2996 | ||
3842d135 AK |
2997 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2998 | ||
3cfc3092 JK |
2999 | return 0; |
3000 | } | |
3001 | ||
a1efbe77 JK |
3002 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3003 | struct kvm_debugregs *dbgregs) | |
3004 | { | |
73aaf249 JK |
3005 | unsigned long val; |
3006 | ||
a1efbe77 | 3007 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3008 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3009 | dbgregs->dr6 = val; |
a1efbe77 JK |
3010 | dbgregs->dr7 = vcpu->arch.dr7; |
3011 | dbgregs->flags = 0; | |
97e69aa6 | 3012 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3013 | } |
3014 | ||
3015 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3016 | struct kvm_debugregs *dbgregs) | |
3017 | { | |
3018 | if (dbgregs->flags) | |
3019 | return -EINVAL; | |
3020 | ||
a1efbe77 | 3021 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3022 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3023 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3024 | kvm_update_dr6(vcpu); |
a1efbe77 | 3025 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3026 | kvm_update_dr7(vcpu); |
a1efbe77 | 3027 | |
a1efbe77 JK |
3028 | return 0; |
3029 | } | |
3030 | ||
df1daba7 PB |
3031 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3032 | ||
3033 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3034 | { | |
c47ada30 | 3035 | struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; |
400e4b20 | 3036 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
3037 | u64 valid; |
3038 | ||
3039 | /* | |
3040 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3041 | * leaves 0 and 1 in the loop below. | |
3042 | */ | |
3043 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3044 | ||
3045 | /* Set XSTATE_BV */ | |
3046 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; | |
3047 | ||
3048 | /* | |
3049 | * Copy each region from the possibly compacted offset to the | |
3050 | * non-compacted offset. | |
3051 | */ | |
d91cab78 | 3052 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3053 | while (valid) { |
3054 | u64 feature = valid & -valid; | |
3055 | int index = fls64(feature) - 1; | |
3056 | void *src = get_xsave_addr(xsave, feature); | |
3057 | ||
3058 | if (src) { | |
3059 | u32 size, offset, ecx, edx; | |
3060 | cpuid_count(XSTATE_CPUID, index, | |
3061 | &size, &offset, &ecx, &edx); | |
3062 | memcpy(dest + offset, src, size); | |
3063 | } | |
3064 | ||
3065 | valid -= feature; | |
3066 | } | |
3067 | } | |
3068 | ||
3069 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3070 | { | |
c47ada30 | 3071 | struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; |
df1daba7 PB |
3072 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
3073 | u64 valid; | |
3074 | ||
3075 | /* | |
3076 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3077 | * leaves 0 and 1 in the loop below. | |
3078 | */ | |
3079 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3080 | ||
3081 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 3082 | xsave->header.xfeatures = xstate_bv; |
df1daba7 | 3083 | if (cpu_has_xsaves) |
3a54450b | 3084 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
3085 | |
3086 | /* | |
3087 | * Copy each region from the non-compacted offset to the | |
3088 | * possibly compacted offset. | |
3089 | */ | |
d91cab78 | 3090 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3091 | while (valid) { |
3092 | u64 feature = valid & -valid; | |
3093 | int index = fls64(feature) - 1; | |
3094 | void *dest = get_xsave_addr(xsave, feature); | |
3095 | ||
3096 | if (dest) { | |
3097 | u32 size, offset, ecx, edx; | |
3098 | cpuid_count(XSTATE_CPUID, index, | |
3099 | &size, &offset, &ecx, &edx); | |
3100 | memcpy(dest, src + offset, size); | |
ee4100da | 3101 | } |
df1daba7 PB |
3102 | |
3103 | valid -= feature; | |
3104 | } | |
3105 | } | |
3106 | ||
2d5b5a66 SY |
3107 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3108 | struct kvm_xsave *guest_xsave) | |
3109 | { | |
4344ee98 | 3110 | if (cpu_has_xsave) { |
df1daba7 PB |
3111 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3112 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3113 | } else { |
2d5b5a66 | 3114 | memcpy(guest_xsave->region, |
7366ed77 | 3115 | &vcpu->arch.guest_fpu.state.fxsave, |
c47ada30 | 3116 | sizeof(struct fxregs_state)); |
2d5b5a66 | 3117 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 3118 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
3119 | } |
3120 | } | |
3121 | ||
3122 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3123 | struct kvm_xsave *guest_xsave) | |
3124 | { | |
3125 | u64 xstate_bv = | |
3126 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3127 | ||
d7876f1b PB |
3128 | if (cpu_has_xsave) { |
3129 | /* | |
3130 | * Here we allow setting states that are not present in | |
3131 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3132 | * with old userspace. | |
3133 | */ | |
4ff41732 | 3134 | if (xstate_bv & ~kvm_supported_xcr0()) |
d7876f1b | 3135 | return -EINVAL; |
df1daba7 | 3136 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3137 | } else { |
d91cab78 | 3138 | if (xstate_bv & ~XFEATURE_MASK_FPSSE) |
2d5b5a66 | 3139 | return -EINVAL; |
7366ed77 | 3140 | memcpy(&vcpu->arch.guest_fpu.state.fxsave, |
c47ada30 | 3141 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
3142 | } |
3143 | return 0; | |
3144 | } | |
3145 | ||
3146 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3147 | struct kvm_xcrs *guest_xcrs) | |
3148 | { | |
3149 | if (!cpu_has_xsave) { | |
3150 | guest_xcrs->nr_xcrs = 0; | |
3151 | return; | |
3152 | } | |
3153 | ||
3154 | guest_xcrs->nr_xcrs = 1; | |
3155 | guest_xcrs->flags = 0; | |
3156 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3157 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3158 | } | |
3159 | ||
3160 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3161 | struct kvm_xcrs *guest_xcrs) | |
3162 | { | |
3163 | int i, r = 0; | |
3164 | ||
3165 | if (!cpu_has_xsave) | |
3166 | return -EINVAL; | |
3167 | ||
3168 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3169 | return -EINVAL; | |
3170 | ||
3171 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3172 | /* Only support XCR0 currently */ | |
c67a04cb | 3173 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3174 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3175 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3176 | break; |
3177 | } | |
3178 | if (r) | |
3179 | r = -EINVAL; | |
3180 | return r; | |
3181 | } | |
3182 | ||
1c0b28c2 EM |
3183 | /* |
3184 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3185 | * stopped by the hypervisor. This function will be called from the host only. | |
3186 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3187 | * does not support pv clocks. | |
3188 | */ | |
3189 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3190 | { | |
0b79459b | 3191 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3192 | return -EINVAL; |
51d59c6b | 3193 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3194 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3195 | return 0; | |
3196 | } | |
3197 | ||
5c919412 AS |
3198 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
3199 | struct kvm_enable_cap *cap) | |
3200 | { | |
3201 | if (cap->flags) | |
3202 | return -EINVAL; | |
3203 | ||
3204 | switch (cap->cap) { | |
3205 | case KVM_CAP_HYPERV_SYNIC: | |
3206 | return kvm_hv_activate_synic(vcpu); | |
3207 | default: | |
3208 | return -EINVAL; | |
3209 | } | |
3210 | } | |
3211 | ||
313a3dc7 CO |
3212 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3213 | unsigned int ioctl, unsigned long arg) | |
3214 | { | |
3215 | struct kvm_vcpu *vcpu = filp->private_data; | |
3216 | void __user *argp = (void __user *)arg; | |
3217 | int r; | |
d1ac91d8 AK |
3218 | union { |
3219 | struct kvm_lapic_state *lapic; | |
3220 | struct kvm_xsave *xsave; | |
3221 | struct kvm_xcrs *xcrs; | |
3222 | void *buffer; | |
3223 | } u; | |
3224 | ||
3225 | u.buffer = NULL; | |
313a3dc7 CO |
3226 | switch (ioctl) { |
3227 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
3228 | r = -EINVAL; |
3229 | if (!vcpu->arch.apic) | |
3230 | goto out; | |
d1ac91d8 | 3231 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3232 | |
b772ff36 | 3233 | r = -ENOMEM; |
d1ac91d8 | 3234 | if (!u.lapic) |
b772ff36 | 3235 | goto out; |
d1ac91d8 | 3236 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3237 | if (r) |
3238 | goto out; | |
3239 | r = -EFAULT; | |
d1ac91d8 | 3240 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3241 | goto out; |
3242 | r = 0; | |
3243 | break; | |
3244 | } | |
3245 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
3246 | r = -EINVAL; |
3247 | if (!vcpu->arch.apic) | |
3248 | goto out; | |
ff5c2c03 | 3249 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3250 | if (IS_ERR(u.lapic)) |
3251 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3252 | |
d1ac91d8 | 3253 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3254 | break; |
3255 | } | |
f77bc6a4 ZX |
3256 | case KVM_INTERRUPT: { |
3257 | struct kvm_interrupt irq; | |
3258 | ||
3259 | r = -EFAULT; | |
3260 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3261 | goto out; | |
3262 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3263 | break; |
3264 | } | |
c4abb7c9 JK |
3265 | case KVM_NMI: { |
3266 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3267 | break; |
3268 | } | |
f077825a PB |
3269 | case KVM_SMI: { |
3270 | r = kvm_vcpu_ioctl_smi(vcpu); | |
3271 | break; | |
3272 | } | |
313a3dc7 CO |
3273 | case KVM_SET_CPUID: { |
3274 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3275 | struct kvm_cpuid cpuid; | |
3276 | ||
3277 | r = -EFAULT; | |
3278 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3279 | goto out; | |
3280 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3281 | break; |
3282 | } | |
07716717 DK |
3283 | case KVM_SET_CPUID2: { |
3284 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3285 | struct kvm_cpuid2 cpuid; | |
3286 | ||
3287 | r = -EFAULT; | |
3288 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3289 | goto out; | |
3290 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3291 | cpuid_arg->entries); |
07716717 DK |
3292 | break; |
3293 | } | |
3294 | case KVM_GET_CPUID2: { | |
3295 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3296 | struct kvm_cpuid2 cpuid; | |
3297 | ||
3298 | r = -EFAULT; | |
3299 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3300 | goto out; | |
3301 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3302 | cpuid_arg->entries); |
07716717 DK |
3303 | if (r) |
3304 | goto out; | |
3305 | r = -EFAULT; | |
3306 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3307 | goto out; | |
3308 | r = 0; | |
3309 | break; | |
3310 | } | |
313a3dc7 | 3311 | case KVM_GET_MSRS: |
609e36d3 | 3312 | r = msr_io(vcpu, argp, do_get_msr, 1); |
313a3dc7 CO |
3313 | break; |
3314 | case KVM_SET_MSRS: | |
3315 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3316 | break; | |
b209749f AK |
3317 | case KVM_TPR_ACCESS_REPORTING: { |
3318 | struct kvm_tpr_access_ctl tac; | |
3319 | ||
3320 | r = -EFAULT; | |
3321 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3322 | goto out; | |
3323 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3324 | if (r) | |
3325 | goto out; | |
3326 | r = -EFAULT; | |
3327 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3328 | goto out; | |
3329 | r = 0; | |
3330 | break; | |
3331 | }; | |
b93463aa AK |
3332 | case KVM_SET_VAPIC_ADDR: { |
3333 | struct kvm_vapic_addr va; | |
3334 | ||
3335 | r = -EINVAL; | |
35754c98 | 3336 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
3337 | goto out; |
3338 | r = -EFAULT; | |
3339 | if (copy_from_user(&va, argp, sizeof va)) | |
3340 | goto out; | |
fda4e2e8 | 3341 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
b93463aa AK |
3342 | break; |
3343 | } | |
890ca9ae HY |
3344 | case KVM_X86_SETUP_MCE: { |
3345 | u64 mcg_cap; | |
3346 | ||
3347 | r = -EFAULT; | |
3348 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3349 | goto out; | |
3350 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3351 | break; | |
3352 | } | |
3353 | case KVM_X86_SET_MCE: { | |
3354 | struct kvm_x86_mce mce; | |
3355 | ||
3356 | r = -EFAULT; | |
3357 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3358 | goto out; | |
3359 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3360 | break; | |
3361 | } | |
3cfc3092 JK |
3362 | case KVM_GET_VCPU_EVENTS: { |
3363 | struct kvm_vcpu_events events; | |
3364 | ||
3365 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3366 | ||
3367 | r = -EFAULT; | |
3368 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3369 | break; | |
3370 | r = 0; | |
3371 | break; | |
3372 | } | |
3373 | case KVM_SET_VCPU_EVENTS: { | |
3374 | struct kvm_vcpu_events events; | |
3375 | ||
3376 | r = -EFAULT; | |
3377 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3378 | break; | |
3379 | ||
3380 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3381 | break; | |
3382 | } | |
a1efbe77 JK |
3383 | case KVM_GET_DEBUGREGS: { |
3384 | struct kvm_debugregs dbgregs; | |
3385 | ||
3386 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3387 | ||
3388 | r = -EFAULT; | |
3389 | if (copy_to_user(argp, &dbgregs, | |
3390 | sizeof(struct kvm_debugregs))) | |
3391 | break; | |
3392 | r = 0; | |
3393 | break; | |
3394 | } | |
3395 | case KVM_SET_DEBUGREGS: { | |
3396 | struct kvm_debugregs dbgregs; | |
3397 | ||
3398 | r = -EFAULT; | |
3399 | if (copy_from_user(&dbgregs, argp, | |
3400 | sizeof(struct kvm_debugregs))) | |
3401 | break; | |
3402 | ||
3403 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3404 | break; | |
3405 | } | |
2d5b5a66 | 3406 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3407 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3408 | r = -ENOMEM; |
d1ac91d8 | 3409 | if (!u.xsave) |
2d5b5a66 SY |
3410 | break; |
3411 | ||
d1ac91d8 | 3412 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3413 | |
3414 | r = -EFAULT; | |
d1ac91d8 | 3415 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3416 | break; |
3417 | r = 0; | |
3418 | break; | |
3419 | } | |
3420 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3421 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3422 | if (IS_ERR(u.xsave)) |
3423 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3424 | |
d1ac91d8 | 3425 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3426 | break; |
3427 | } | |
3428 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3429 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3430 | r = -ENOMEM; |
d1ac91d8 | 3431 | if (!u.xcrs) |
2d5b5a66 SY |
3432 | break; |
3433 | ||
d1ac91d8 | 3434 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3435 | |
3436 | r = -EFAULT; | |
d1ac91d8 | 3437 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3438 | sizeof(struct kvm_xcrs))) |
3439 | break; | |
3440 | r = 0; | |
3441 | break; | |
3442 | } | |
3443 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3444 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3445 | if (IS_ERR(u.xcrs)) |
3446 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3447 | |
d1ac91d8 | 3448 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3449 | break; |
3450 | } | |
92a1f12d JR |
3451 | case KVM_SET_TSC_KHZ: { |
3452 | u32 user_tsc_khz; | |
3453 | ||
3454 | r = -EINVAL; | |
92a1f12d JR |
3455 | user_tsc_khz = (u32)arg; |
3456 | ||
3457 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3458 | goto out; | |
3459 | ||
cc578287 ZA |
3460 | if (user_tsc_khz == 0) |
3461 | user_tsc_khz = tsc_khz; | |
3462 | ||
381d585c HZ |
3463 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
3464 | r = 0; | |
92a1f12d | 3465 | |
92a1f12d JR |
3466 | goto out; |
3467 | } | |
3468 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3469 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3470 | goto out; |
3471 | } | |
1c0b28c2 EM |
3472 | case KVM_KVMCLOCK_CTRL: { |
3473 | r = kvm_set_guest_paused(vcpu); | |
3474 | goto out; | |
3475 | } | |
5c919412 AS |
3476 | case KVM_ENABLE_CAP: { |
3477 | struct kvm_enable_cap cap; | |
3478 | ||
3479 | r = -EFAULT; | |
3480 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
3481 | goto out; | |
3482 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
3483 | break; | |
3484 | } | |
313a3dc7 CO |
3485 | default: |
3486 | r = -EINVAL; | |
3487 | } | |
3488 | out: | |
d1ac91d8 | 3489 | kfree(u.buffer); |
313a3dc7 CO |
3490 | return r; |
3491 | } | |
3492 | ||
5b1c1493 CO |
3493 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3494 | { | |
3495 | return VM_FAULT_SIGBUS; | |
3496 | } | |
3497 | ||
1fe779f8 CO |
3498 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3499 | { | |
3500 | int ret; | |
3501 | ||
3502 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3503 | return -EINVAL; |
1fe779f8 CO |
3504 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3505 | return ret; | |
3506 | } | |
3507 | ||
b927a3ce SY |
3508 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3509 | u64 ident_addr) | |
3510 | { | |
3511 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3512 | return 0; | |
3513 | } | |
3514 | ||
1fe779f8 CO |
3515 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3516 | u32 kvm_nr_mmu_pages) | |
3517 | { | |
3518 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3519 | return -EINVAL; | |
3520 | ||
79fac95e | 3521 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3522 | |
3523 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3524 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3525 | |
79fac95e | 3526 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3527 | return 0; |
3528 | } | |
3529 | ||
3530 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3531 | { | |
39de71ec | 3532 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3533 | } |
3534 | ||
1fe779f8 CO |
3535 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3536 | { | |
3537 | int r; | |
3538 | ||
3539 | r = 0; | |
3540 | switch (chip->chip_id) { | |
3541 | case KVM_IRQCHIP_PIC_MASTER: | |
3542 | memcpy(&chip->chip.pic, | |
3543 | &pic_irqchip(kvm)->pics[0], | |
3544 | sizeof(struct kvm_pic_state)); | |
3545 | break; | |
3546 | case KVM_IRQCHIP_PIC_SLAVE: | |
3547 | memcpy(&chip->chip.pic, | |
3548 | &pic_irqchip(kvm)->pics[1], | |
3549 | sizeof(struct kvm_pic_state)); | |
3550 | break; | |
3551 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3552 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3553 | break; |
3554 | default: | |
3555 | r = -EINVAL; | |
3556 | break; | |
3557 | } | |
3558 | return r; | |
3559 | } | |
3560 | ||
3561 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3562 | { | |
3563 | int r; | |
3564 | ||
3565 | r = 0; | |
3566 | switch (chip->chip_id) { | |
3567 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3568 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3569 | memcpy(&pic_irqchip(kvm)->pics[0], |
3570 | &chip->chip.pic, | |
3571 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3572 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3573 | break; |
3574 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3575 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3576 | memcpy(&pic_irqchip(kvm)->pics[1], |
3577 | &chip->chip.pic, | |
3578 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3579 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3580 | break; |
3581 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3582 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3583 | break; |
3584 | default: | |
3585 | r = -EINVAL; | |
3586 | break; | |
3587 | } | |
3588 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3589 | return r; | |
3590 | } | |
3591 | ||
e0f63cb9 SY |
3592 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3593 | { | |
894a9c55 | 3594 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3595 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3596 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
2da29bcc | 3597 | return 0; |
e0f63cb9 SY |
3598 | } |
3599 | ||
3600 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3601 | { | |
894a9c55 | 3602 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3603 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3604 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3605 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2da29bcc | 3606 | return 0; |
e9f42757 BK |
3607 | } |
3608 | ||
3609 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3610 | { | |
e9f42757 BK |
3611 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
3612 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3613 | sizeof(ps->channels)); | |
3614 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3615 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3616 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 3617 | return 0; |
e9f42757 BK |
3618 | } |
3619 | ||
3620 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3621 | { | |
2da29bcc | 3622 | int start = 0; |
e9f42757 BK |
3623 | u32 prev_legacy, cur_legacy; |
3624 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3625 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3626 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3627 | if (!prev_legacy && cur_legacy) | |
3628 | start = 1; | |
3629 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3630 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3631 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3632 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3633 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
2da29bcc | 3634 | return 0; |
e0f63cb9 SY |
3635 | } |
3636 | ||
52d939a0 MT |
3637 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3638 | struct kvm_reinject_control *control) | |
3639 | { | |
3640 | if (!kvm->arch.vpit) | |
3641 | return -ENXIO; | |
894a9c55 | 3642 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3643 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3644 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3645 | return 0; |
3646 | } | |
3647 | ||
95d4c16c | 3648 | /** |
60c34612 TY |
3649 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3650 | * @kvm: kvm instance | |
3651 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3652 | * |
e108ff2f PB |
3653 | * Steps 1-4 below provide general overview of dirty page logging. See |
3654 | * kvm_get_dirty_log_protect() function description for additional details. | |
3655 | * | |
3656 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
3657 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
3658 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
3659 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
3660 | * writes will be marked dirty for next log read. | |
95d4c16c | 3661 | * |
60c34612 TY |
3662 | * 1. Take a snapshot of the bit and clear it if needed. |
3663 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
3664 | * 3. Copy the snapshot to the userspace. |
3665 | * 4. Flush TLB's if needed. | |
5bb064dc | 3666 | */ |
60c34612 | 3667 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3668 | { |
60c34612 | 3669 | bool is_dirty = false; |
e108ff2f | 3670 | int r; |
5bb064dc | 3671 | |
79fac95e | 3672 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3673 | |
88178fd4 KH |
3674 | /* |
3675 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
3676 | */ | |
3677 | if (kvm_x86_ops->flush_log_dirty) | |
3678 | kvm_x86_ops->flush_log_dirty(kvm); | |
3679 | ||
e108ff2f | 3680 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
198c74f4 XG |
3681 | |
3682 | /* | |
3683 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
3684 | * kvm_mmu_slot_remove_write_access(). | |
3685 | */ | |
e108ff2f | 3686 | lockdep_assert_held(&kvm->slots_lock); |
198c74f4 XG |
3687 | if (is_dirty) |
3688 | kvm_flush_remote_tlbs(kvm); | |
3689 | ||
79fac95e | 3690 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3691 | return r; |
3692 | } | |
3693 | ||
aa2fbe6d YZ |
3694 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3695 | bool line_status) | |
23d43cf9 CD |
3696 | { |
3697 | if (!irqchip_in_kernel(kvm)) | |
3698 | return -ENXIO; | |
3699 | ||
3700 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3701 | irq_event->irq, irq_event->level, |
3702 | line_status); | |
23d43cf9 CD |
3703 | return 0; |
3704 | } | |
3705 | ||
90de4a18 NA |
3706 | static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
3707 | struct kvm_enable_cap *cap) | |
3708 | { | |
3709 | int r; | |
3710 | ||
3711 | if (cap->flags) | |
3712 | return -EINVAL; | |
3713 | ||
3714 | switch (cap->cap) { | |
3715 | case KVM_CAP_DISABLE_QUIRKS: | |
3716 | kvm->arch.disabled_quirks = cap->args[0]; | |
3717 | r = 0; | |
3718 | break; | |
49df6397 SR |
3719 | case KVM_CAP_SPLIT_IRQCHIP: { |
3720 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
3721 | r = -EINVAL; |
3722 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
3723 | goto split_irqchip_unlock; | |
49df6397 SR |
3724 | r = -EEXIST; |
3725 | if (irqchip_in_kernel(kvm)) | |
3726 | goto split_irqchip_unlock; | |
3727 | if (atomic_read(&kvm->online_vcpus)) | |
3728 | goto split_irqchip_unlock; | |
3729 | r = kvm_setup_empty_irq_routing(kvm); | |
3730 | if (r) | |
3731 | goto split_irqchip_unlock; | |
3732 | /* Pairs with irqchip_in_kernel. */ | |
3733 | smp_wmb(); | |
3734 | kvm->arch.irqchip_split = true; | |
b053b2ae | 3735 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
3736 | r = 0; |
3737 | split_irqchip_unlock: | |
3738 | mutex_unlock(&kvm->lock); | |
3739 | break; | |
3740 | } | |
90de4a18 NA |
3741 | default: |
3742 | r = -EINVAL; | |
3743 | break; | |
3744 | } | |
3745 | return r; | |
3746 | } | |
3747 | ||
1fe779f8 CO |
3748 | long kvm_arch_vm_ioctl(struct file *filp, |
3749 | unsigned int ioctl, unsigned long arg) | |
3750 | { | |
3751 | struct kvm *kvm = filp->private_data; | |
3752 | void __user *argp = (void __user *)arg; | |
367e1319 | 3753 | int r = -ENOTTY; |
f0d66275 DH |
3754 | /* |
3755 | * This union makes it completely explicit to gcc-3.x | |
3756 | * that these two variables' stack usage should be | |
3757 | * combined, not added together. | |
3758 | */ | |
3759 | union { | |
3760 | struct kvm_pit_state ps; | |
e9f42757 | 3761 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3762 | struct kvm_pit_config pit_config; |
f0d66275 | 3763 | } u; |
1fe779f8 CO |
3764 | |
3765 | switch (ioctl) { | |
3766 | case KVM_SET_TSS_ADDR: | |
3767 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 3768 | break; |
b927a3ce SY |
3769 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3770 | u64 ident_addr; | |
3771 | ||
3772 | r = -EFAULT; | |
3773 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3774 | goto out; | |
3775 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
3776 | break; |
3777 | } | |
1fe779f8 CO |
3778 | case KVM_SET_NR_MMU_PAGES: |
3779 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
3780 | break; |
3781 | case KVM_GET_NR_MMU_PAGES: | |
3782 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3783 | break; | |
3ddea128 MT |
3784 | case KVM_CREATE_IRQCHIP: { |
3785 | struct kvm_pic *vpic; | |
3786 | ||
3787 | mutex_lock(&kvm->lock); | |
3788 | r = -EEXIST; | |
3789 | if (kvm->arch.vpic) | |
3790 | goto create_irqchip_unlock; | |
3e515705 AK |
3791 | r = -EINVAL; |
3792 | if (atomic_read(&kvm->online_vcpus)) | |
3793 | goto create_irqchip_unlock; | |
1fe779f8 | 3794 | r = -ENOMEM; |
3ddea128 MT |
3795 | vpic = kvm_create_pic(kvm); |
3796 | if (vpic) { | |
1fe779f8 CO |
3797 | r = kvm_ioapic_init(kvm); |
3798 | if (r) { | |
175504cd | 3799 | mutex_lock(&kvm->slots_lock); |
71ba994c | 3800 | kvm_destroy_pic(vpic); |
175504cd | 3801 | mutex_unlock(&kvm->slots_lock); |
3ddea128 | 3802 | goto create_irqchip_unlock; |
1fe779f8 CO |
3803 | } |
3804 | } else | |
3ddea128 | 3805 | goto create_irqchip_unlock; |
399ec807 AK |
3806 | r = kvm_setup_default_irq_routing(kvm); |
3807 | if (r) { | |
175504cd | 3808 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 3809 | mutex_lock(&kvm->irq_lock); |
72bb2fcd | 3810 | kvm_ioapic_destroy(kvm); |
71ba994c | 3811 | kvm_destroy_pic(vpic); |
3ddea128 | 3812 | mutex_unlock(&kvm->irq_lock); |
175504cd | 3813 | mutex_unlock(&kvm->slots_lock); |
71ba994c | 3814 | goto create_irqchip_unlock; |
399ec807 | 3815 | } |
71ba994c PB |
3816 | /* Write kvm->irq_routing before kvm->arch.vpic. */ |
3817 | smp_wmb(); | |
3818 | kvm->arch.vpic = vpic; | |
3ddea128 MT |
3819 | create_irqchip_unlock: |
3820 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3821 | break; |
3ddea128 | 3822 | } |
7837699f | 3823 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3824 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3825 | goto create_pit; | |
3826 | case KVM_CREATE_PIT2: | |
3827 | r = -EFAULT; | |
3828 | if (copy_from_user(&u.pit_config, argp, | |
3829 | sizeof(struct kvm_pit_config))) | |
3830 | goto out; | |
3831 | create_pit: | |
79fac95e | 3832 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3833 | r = -EEXIST; |
3834 | if (kvm->arch.vpit) | |
3835 | goto create_pit_unlock; | |
7837699f | 3836 | r = -ENOMEM; |
c5ff41ce | 3837 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3838 | if (kvm->arch.vpit) |
3839 | r = 0; | |
269e05e4 | 3840 | create_pit_unlock: |
79fac95e | 3841 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3842 | break; |
1fe779f8 CO |
3843 | case KVM_GET_IRQCHIP: { |
3844 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3845 | struct kvm_irqchip *chip; |
1fe779f8 | 3846 | |
ff5c2c03 SL |
3847 | chip = memdup_user(argp, sizeof(*chip)); |
3848 | if (IS_ERR(chip)) { | |
3849 | r = PTR_ERR(chip); | |
1fe779f8 | 3850 | goto out; |
ff5c2c03 SL |
3851 | } |
3852 | ||
1fe779f8 | 3853 | r = -ENXIO; |
49df6397 | 3854 | if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) |
f0d66275 DH |
3855 | goto get_irqchip_out; |
3856 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3857 | if (r) |
f0d66275 | 3858 | goto get_irqchip_out; |
1fe779f8 | 3859 | r = -EFAULT; |
f0d66275 DH |
3860 | if (copy_to_user(argp, chip, sizeof *chip)) |
3861 | goto get_irqchip_out; | |
1fe779f8 | 3862 | r = 0; |
f0d66275 DH |
3863 | get_irqchip_out: |
3864 | kfree(chip); | |
1fe779f8 CO |
3865 | break; |
3866 | } | |
3867 | case KVM_SET_IRQCHIP: { | |
3868 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 3869 | struct kvm_irqchip *chip; |
1fe779f8 | 3870 | |
ff5c2c03 SL |
3871 | chip = memdup_user(argp, sizeof(*chip)); |
3872 | if (IS_ERR(chip)) { | |
3873 | r = PTR_ERR(chip); | |
1fe779f8 | 3874 | goto out; |
ff5c2c03 SL |
3875 | } |
3876 | ||
1fe779f8 | 3877 | r = -ENXIO; |
49df6397 | 3878 | if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) |
f0d66275 DH |
3879 | goto set_irqchip_out; |
3880 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3881 | if (r) |
f0d66275 | 3882 | goto set_irqchip_out; |
1fe779f8 | 3883 | r = 0; |
f0d66275 DH |
3884 | set_irqchip_out: |
3885 | kfree(chip); | |
1fe779f8 CO |
3886 | break; |
3887 | } | |
e0f63cb9 | 3888 | case KVM_GET_PIT: { |
e0f63cb9 | 3889 | r = -EFAULT; |
f0d66275 | 3890 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3891 | goto out; |
3892 | r = -ENXIO; | |
3893 | if (!kvm->arch.vpit) | |
3894 | goto out; | |
f0d66275 | 3895 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3896 | if (r) |
3897 | goto out; | |
3898 | r = -EFAULT; | |
f0d66275 | 3899 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3900 | goto out; |
3901 | r = 0; | |
3902 | break; | |
3903 | } | |
3904 | case KVM_SET_PIT: { | |
e0f63cb9 | 3905 | r = -EFAULT; |
f0d66275 | 3906 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3907 | goto out; |
3908 | r = -ENXIO; | |
3909 | if (!kvm->arch.vpit) | |
3910 | goto out; | |
f0d66275 | 3911 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3912 | break; |
3913 | } | |
e9f42757 BK |
3914 | case KVM_GET_PIT2: { |
3915 | r = -ENXIO; | |
3916 | if (!kvm->arch.vpit) | |
3917 | goto out; | |
3918 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3919 | if (r) | |
3920 | goto out; | |
3921 | r = -EFAULT; | |
3922 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3923 | goto out; | |
3924 | r = 0; | |
3925 | break; | |
3926 | } | |
3927 | case KVM_SET_PIT2: { | |
3928 | r = -EFAULT; | |
3929 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3930 | goto out; | |
3931 | r = -ENXIO; | |
3932 | if (!kvm->arch.vpit) | |
3933 | goto out; | |
3934 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
3935 | break; |
3936 | } | |
52d939a0 MT |
3937 | case KVM_REINJECT_CONTROL: { |
3938 | struct kvm_reinject_control control; | |
3939 | r = -EFAULT; | |
3940 | if (copy_from_user(&control, argp, sizeof(control))) | |
3941 | goto out; | |
3942 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
3943 | break; |
3944 | } | |
d71ba788 PB |
3945 | case KVM_SET_BOOT_CPU_ID: |
3946 | r = 0; | |
3947 | mutex_lock(&kvm->lock); | |
3948 | if (atomic_read(&kvm->online_vcpus) != 0) | |
3949 | r = -EBUSY; | |
3950 | else | |
3951 | kvm->arch.bsp_vcpu_id = arg; | |
3952 | mutex_unlock(&kvm->lock); | |
3953 | break; | |
ffde22ac ES |
3954 | case KVM_XEN_HVM_CONFIG: { |
3955 | r = -EFAULT; | |
3956 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3957 | sizeof(struct kvm_xen_hvm_config))) | |
3958 | goto out; | |
3959 | r = -EINVAL; | |
3960 | if (kvm->arch.xen_hvm_config.flags) | |
3961 | goto out; | |
3962 | r = 0; | |
3963 | break; | |
3964 | } | |
afbcf7ab | 3965 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3966 | struct kvm_clock_data user_ns; |
3967 | u64 now_ns; | |
3968 | s64 delta; | |
3969 | ||
3970 | r = -EFAULT; | |
3971 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3972 | goto out; | |
3973 | ||
3974 | r = -EINVAL; | |
3975 | if (user_ns.flags) | |
3976 | goto out; | |
3977 | ||
3978 | r = 0; | |
395c6b0a | 3979 | local_irq_disable(); |
759379dd | 3980 | now_ns = get_kernel_ns(); |
afbcf7ab | 3981 | delta = user_ns.clock - now_ns; |
395c6b0a | 3982 | local_irq_enable(); |
afbcf7ab | 3983 | kvm->arch.kvmclock_offset = delta; |
2e762ff7 | 3984 | kvm_gen_update_masterclock(kvm); |
afbcf7ab GC |
3985 | break; |
3986 | } | |
3987 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3988 | struct kvm_clock_data user_ns; |
3989 | u64 now_ns; | |
3990 | ||
395c6b0a | 3991 | local_irq_disable(); |
759379dd | 3992 | now_ns = get_kernel_ns(); |
afbcf7ab | 3993 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 3994 | local_irq_enable(); |
afbcf7ab | 3995 | user_ns.flags = 0; |
97e69aa6 | 3996 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
3997 | |
3998 | r = -EFAULT; | |
3999 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4000 | goto out; | |
4001 | r = 0; | |
4002 | break; | |
4003 | } | |
90de4a18 NA |
4004 | case KVM_ENABLE_CAP: { |
4005 | struct kvm_enable_cap cap; | |
afbcf7ab | 4006 | |
90de4a18 NA |
4007 | r = -EFAULT; |
4008 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4009 | goto out; | |
4010 | r = kvm_vm_ioctl_enable_cap(kvm, &cap); | |
4011 | break; | |
4012 | } | |
1fe779f8 | 4013 | default: |
c274e03a | 4014 | r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); |
1fe779f8 CO |
4015 | } |
4016 | out: | |
4017 | return r; | |
4018 | } | |
4019 | ||
a16b043c | 4020 | static void kvm_init_msr_list(void) |
043405e1 CO |
4021 | { |
4022 | u32 dummy[2]; | |
4023 | unsigned i, j; | |
4024 | ||
62ef68bb | 4025 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { |
043405e1 CO |
4026 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4027 | continue; | |
93c4adc7 PB |
4028 | |
4029 | /* | |
4030 | * Even MSRs that are valid in the host may not be exposed | |
4031 | * to the guests in some cases. We could work around this | |
4032 | * in VMX with the generic MSR save/load machinery, but it | |
4033 | * is not really worthwhile since it will really only | |
4034 | * happen with nested virtualization. | |
4035 | */ | |
4036 | switch (msrs_to_save[i]) { | |
4037 | case MSR_IA32_BNDCFGS: | |
4038 | if (!kvm_x86_ops->mpx_supported()) | |
4039 | continue; | |
4040 | break; | |
4041 | default: | |
4042 | break; | |
4043 | } | |
4044 | ||
043405e1 CO |
4045 | if (j < i) |
4046 | msrs_to_save[j] = msrs_to_save[i]; | |
4047 | j++; | |
4048 | } | |
4049 | num_msrs_to_save = j; | |
62ef68bb PB |
4050 | |
4051 | for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { | |
4052 | switch (emulated_msrs[i]) { | |
6d396b55 PB |
4053 | case MSR_IA32_SMBASE: |
4054 | if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) | |
4055 | continue; | |
4056 | break; | |
62ef68bb PB |
4057 | default: |
4058 | break; | |
4059 | } | |
4060 | ||
4061 | if (j < i) | |
4062 | emulated_msrs[j] = emulated_msrs[i]; | |
4063 | j++; | |
4064 | } | |
4065 | num_emulated_msrs = j; | |
043405e1 CO |
4066 | } |
4067 | ||
bda9020e MT |
4068 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4069 | const void *v) | |
bbd9b64e | 4070 | { |
70252a10 AK |
4071 | int handled = 0; |
4072 | int n; | |
4073 | ||
4074 | do { | |
4075 | n = min(len, 8); | |
4076 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4077 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
4078 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4079 | break; |
4080 | handled += n; | |
4081 | addr += n; | |
4082 | len -= n; | |
4083 | v += n; | |
4084 | } while (len); | |
bbd9b64e | 4085 | |
70252a10 | 4086 | return handled; |
bbd9b64e CO |
4087 | } |
4088 | ||
bda9020e | 4089 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4090 | { |
70252a10 AK |
4091 | int handled = 0; |
4092 | int n; | |
4093 | ||
4094 | do { | |
4095 | n = min(len, 8); | |
4096 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4097 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
4098 | addr, n, v)) | |
4099 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4100 | break; |
4101 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
4102 | handled += n; | |
4103 | addr += n; | |
4104 | len -= n; | |
4105 | v += n; | |
4106 | } while (len); | |
bbd9b64e | 4107 | |
70252a10 | 4108 | return handled; |
bbd9b64e CO |
4109 | } |
4110 | ||
2dafc6c2 GN |
4111 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4112 | struct kvm_segment *var, int seg) | |
4113 | { | |
4114 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4115 | } | |
4116 | ||
4117 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4118 | struct kvm_segment *var, int seg) | |
4119 | { | |
4120 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4121 | } | |
4122 | ||
54987b7a PB |
4123 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4124 | struct x86_exception *exception) | |
02f59dc9 JR |
4125 | { |
4126 | gpa_t t_gpa; | |
02f59dc9 JR |
4127 | |
4128 | BUG_ON(!mmu_is_nested(vcpu)); | |
4129 | ||
4130 | /* NPT walks are always user-walks */ | |
4131 | access |= PFERR_USER_MASK; | |
54987b7a | 4132 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4133 | |
4134 | return t_gpa; | |
4135 | } | |
4136 | ||
ab9ae313 AK |
4137 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4138 | struct x86_exception *exception) | |
1871c602 GN |
4139 | { |
4140 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4141 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4142 | } |
4143 | ||
ab9ae313 AK |
4144 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4145 | struct x86_exception *exception) | |
1871c602 GN |
4146 | { |
4147 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4148 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4149 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4150 | } |
4151 | ||
ab9ae313 AK |
4152 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4153 | struct x86_exception *exception) | |
1871c602 GN |
4154 | { |
4155 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4156 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4157 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4158 | } |
4159 | ||
4160 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4161 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4162 | struct x86_exception *exception) | |
1871c602 | 4163 | { |
ab9ae313 | 4164 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4165 | } |
4166 | ||
4167 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4168 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4169 | struct x86_exception *exception) |
bbd9b64e CO |
4170 | { |
4171 | void *data = val; | |
10589a46 | 4172 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4173 | |
4174 | while (bytes) { | |
14dfe855 | 4175 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4176 | exception); |
bbd9b64e | 4177 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4178 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4179 | int ret; |
4180 | ||
bcc55cba | 4181 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4182 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
4183 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
4184 | offset, toread); | |
10589a46 | 4185 | if (ret < 0) { |
c3cd7ffa | 4186 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4187 | goto out; |
4188 | } | |
bbd9b64e | 4189 | |
77c2002e IE |
4190 | bytes -= toread; |
4191 | data += toread; | |
4192 | addr += toread; | |
bbd9b64e | 4193 | } |
10589a46 | 4194 | out: |
10589a46 | 4195 | return r; |
bbd9b64e | 4196 | } |
77c2002e | 4197 | |
1871c602 | 4198 | /* used for instruction fetching */ |
0f65dd70 AK |
4199 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4200 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4201 | struct x86_exception *exception) |
1871c602 | 4202 | { |
0f65dd70 | 4203 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4204 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4205 | unsigned offset; |
4206 | int ret; | |
0f65dd70 | 4207 | |
44583cba PB |
4208 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4209 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4210 | exception); | |
4211 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4212 | return X86EMUL_PROPAGATE_FAULT; | |
4213 | ||
4214 | offset = addr & (PAGE_SIZE-1); | |
4215 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4216 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
4217 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
4218 | offset, bytes); | |
44583cba PB |
4219 | if (unlikely(ret < 0)) |
4220 | return X86EMUL_IO_NEEDED; | |
4221 | ||
4222 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4223 | } |
4224 | ||
064aea77 | 4225 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4226 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4227 | struct x86_exception *exception) |
1871c602 | 4228 | { |
0f65dd70 | 4229 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4230 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4231 | |
1871c602 | 4232 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4233 | exception); |
1871c602 | 4234 | } |
064aea77 | 4235 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4236 | |
0f65dd70 AK |
4237 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4238 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4239 | struct x86_exception *exception) |
1871c602 | 4240 | { |
0f65dd70 | 4241 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4242 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4243 | } |
4244 | ||
7a036a6f RK |
4245 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
4246 | unsigned long addr, void *val, unsigned int bytes) | |
4247 | { | |
4248 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4249 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
4250 | ||
4251 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
4252 | } | |
4253 | ||
6a4d7550 | 4254 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4255 | gva_t addr, void *val, |
2dafc6c2 | 4256 | unsigned int bytes, |
bcc55cba | 4257 | struct x86_exception *exception) |
77c2002e | 4258 | { |
0f65dd70 | 4259 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4260 | void *data = val; |
4261 | int r = X86EMUL_CONTINUE; | |
4262 | ||
4263 | while (bytes) { | |
14dfe855 JR |
4264 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4265 | PFERR_WRITE_MASK, | |
ab9ae313 | 4266 | exception); |
77c2002e IE |
4267 | unsigned offset = addr & (PAGE_SIZE-1); |
4268 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4269 | int ret; | |
4270 | ||
bcc55cba | 4271 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4272 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 4273 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 4274 | if (ret < 0) { |
c3cd7ffa | 4275 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4276 | goto out; |
4277 | } | |
4278 | ||
4279 | bytes -= towrite; | |
4280 | data += towrite; | |
4281 | addr += towrite; | |
4282 | } | |
4283 | out: | |
4284 | return r; | |
4285 | } | |
6a4d7550 | 4286 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4287 | |
af7cc7d1 XG |
4288 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4289 | gpa_t *gpa, struct x86_exception *exception, | |
4290 | bool write) | |
4291 | { | |
97d64b78 AK |
4292 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4293 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4294 | |
97d64b78 | 4295 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 FW |
4296 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
4297 | vcpu->arch.access, access)) { | |
bebb106a XG |
4298 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4299 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4300 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4301 | return 1; |
4302 | } | |
4303 | ||
af7cc7d1 XG |
4304 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4305 | ||
4306 | if (*gpa == UNMAPPED_GVA) | |
4307 | return -1; | |
4308 | ||
4309 | /* For APIC access vmexit */ | |
4310 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4311 | return 1; | |
4312 | ||
4f022648 XG |
4313 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4314 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4315 | return 1; |
4f022648 | 4316 | } |
bebb106a | 4317 | |
af7cc7d1 XG |
4318 | return 0; |
4319 | } | |
4320 | ||
3200f405 | 4321 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4322 | const void *val, int bytes) |
bbd9b64e CO |
4323 | { |
4324 | int ret; | |
4325 | ||
54bf36aa | 4326 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 4327 | if (ret < 0) |
bbd9b64e | 4328 | return 0; |
f57f2ef5 | 4329 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4330 | return 1; |
4331 | } | |
4332 | ||
77d197b2 XG |
4333 | struct read_write_emulator_ops { |
4334 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4335 | int bytes); | |
4336 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4337 | void *val, int bytes); | |
4338 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4339 | int bytes, void *val); | |
4340 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4341 | void *val, int bytes); | |
4342 | bool write; | |
4343 | }; | |
4344 | ||
4345 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4346 | { | |
4347 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4348 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4349 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4350 | vcpu->mmio_read_completed = 0; |
4351 | return 1; | |
4352 | } | |
4353 | ||
4354 | return 0; | |
4355 | } | |
4356 | ||
4357 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4358 | void *val, int bytes) | |
4359 | { | |
54bf36aa | 4360 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
4361 | } |
4362 | ||
4363 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4364 | void *val, int bytes) | |
4365 | { | |
4366 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4367 | } | |
4368 | ||
4369 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4370 | { | |
4371 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4372 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4373 | } | |
4374 | ||
4375 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4376 | void *val, int bytes) | |
4377 | { | |
4378 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4379 | return X86EMUL_IO_NEEDED; | |
4380 | } | |
4381 | ||
4382 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4383 | void *val, int bytes) | |
4384 | { | |
f78146b0 AK |
4385 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4386 | ||
87da7e66 | 4387 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4388 | return X86EMUL_CONTINUE; |
4389 | } | |
4390 | ||
0fbe9b0b | 4391 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4392 | .read_write_prepare = read_prepare, |
4393 | .read_write_emulate = read_emulate, | |
4394 | .read_write_mmio = vcpu_mmio_read, | |
4395 | .read_write_exit_mmio = read_exit_mmio, | |
4396 | }; | |
4397 | ||
0fbe9b0b | 4398 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4399 | .read_write_emulate = write_emulate, |
4400 | .read_write_mmio = write_mmio, | |
4401 | .read_write_exit_mmio = write_exit_mmio, | |
4402 | .write = true, | |
4403 | }; | |
4404 | ||
22388a3c XG |
4405 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4406 | unsigned int bytes, | |
4407 | struct x86_exception *exception, | |
4408 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4409 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4410 | { |
af7cc7d1 XG |
4411 | gpa_t gpa; |
4412 | int handled, ret; | |
22388a3c | 4413 | bool write = ops->write; |
f78146b0 | 4414 | struct kvm_mmio_fragment *frag; |
10589a46 | 4415 | |
22388a3c | 4416 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4417 | |
af7cc7d1 | 4418 | if (ret < 0) |
bbd9b64e | 4419 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4420 | |
4421 | /* For APIC access vmexit */ | |
af7cc7d1 | 4422 | if (ret) |
bbd9b64e CO |
4423 | goto mmio; |
4424 | ||
22388a3c | 4425 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4426 | return X86EMUL_CONTINUE; |
4427 | ||
4428 | mmio: | |
4429 | /* | |
4430 | * Is this MMIO handled locally? | |
4431 | */ | |
22388a3c | 4432 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4433 | if (handled == bytes) |
bbd9b64e | 4434 | return X86EMUL_CONTINUE; |
bbd9b64e | 4435 | |
70252a10 AK |
4436 | gpa += handled; |
4437 | bytes -= handled; | |
4438 | val += handled; | |
4439 | ||
87da7e66 XG |
4440 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4441 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4442 | frag->gpa = gpa; | |
4443 | frag->data = val; | |
4444 | frag->len = bytes; | |
f78146b0 | 4445 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4446 | } |
4447 | ||
52eb5a6d XL |
4448 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
4449 | unsigned long addr, | |
22388a3c XG |
4450 | void *val, unsigned int bytes, |
4451 | struct x86_exception *exception, | |
0fbe9b0b | 4452 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4453 | { |
0f65dd70 | 4454 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4455 | gpa_t gpa; |
4456 | int rc; | |
4457 | ||
4458 | if (ops->read_write_prepare && | |
4459 | ops->read_write_prepare(vcpu, val, bytes)) | |
4460 | return X86EMUL_CONTINUE; | |
4461 | ||
4462 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4463 | |
bbd9b64e CO |
4464 | /* Crossing a page boundary? */ |
4465 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4466 | int now; |
bbd9b64e CO |
4467 | |
4468 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4469 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4470 | vcpu, ops); | |
4471 | ||
bbd9b64e CO |
4472 | if (rc != X86EMUL_CONTINUE) |
4473 | return rc; | |
4474 | addr += now; | |
bac15531 NA |
4475 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
4476 | addr = (u32)addr; | |
bbd9b64e CO |
4477 | val += now; |
4478 | bytes -= now; | |
4479 | } | |
22388a3c | 4480 | |
f78146b0 AK |
4481 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4482 | vcpu, ops); | |
4483 | if (rc != X86EMUL_CONTINUE) | |
4484 | return rc; | |
4485 | ||
4486 | if (!vcpu->mmio_nr_fragments) | |
4487 | return rc; | |
4488 | ||
4489 | gpa = vcpu->mmio_fragments[0].gpa; | |
4490 | ||
4491 | vcpu->mmio_needed = 1; | |
4492 | vcpu->mmio_cur_fragment = 0; | |
4493 | ||
87da7e66 | 4494 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4495 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4496 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4497 | vcpu->run->mmio.phys_addr = gpa; | |
4498 | ||
4499 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4500 | } |
4501 | ||
4502 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4503 | unsigned long addr, | |
4504 | void *val, | |
4505 | unsigned int bytes, | |
4506 | struct x86_exception *exception) | |
4507 | { | |
4508 | return emulator_read_write(ctxt, addr, val, bytes, | |
4509 | exception, &read_emultor); | |
4510 | } | |
4511 | ||
52eb5a6d | 4512 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
4513 | unsigned long addr, |
4514 | const void *val, | |
4515 | unsigned int bytes, | |
4516 | struct x86_exception *exception) | |
4517 | { | |
4518 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4519 | exception, &write_emultor); | |
bbd9b64e | 4520 | } |
bbd9b64e | 4521 | |
daea3e73 AK |
4522 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4523 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4524 | ||
4525 | #ifdef CONFIG_X86_64 | |
4526 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4527 | #else | |
4528 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4529 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4530 | #endif |
4531 | ||
0f65dd70 AK |
4532 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4533 | unsigned long addr, | |
bbd9b64e CO |
4534 | const void *old, |
4535 | const void *new, | |
4536 | unsigned int bytes, | |
0f65dd70 | 4537 | struct x86_exception *exception) |
bbd9b64e | 4538 | { |
0f65dd70 | 4539 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4540 | gpa_t gpa; |
4541 | struct page *page; | |
4542 | char *kaddr; | |
4543 | bool exchanged; | |
2bacc55c | 4544 | |
daea3e73 AK |
4545 | /* guests cmpxchg8b have to be emulated atomically */ |
4546 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4547 | goto emul_write; | |
10589a46 | 4548 | |
daea3e73 | 4549 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4550 | |
daea3e73 AK |
4551 | if (gpa == UNMAPPED_GVA || |
4552 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4553 | goto emul_write; | |
2bacc55c | 4554 | |
daea3e73 AK |
4555 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4556 | goto emul_write; | |
72dc67a6 | 4557 | |
54bf36aa | 4558 | page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); |
32cad84f | 4559 | if (is_error_page(page)) |
c19b8bd6 | 4560 | goto emul_write; |
72dc67a6 | 4561 | |
8fd75e12 | 4562 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4563 | kaddr += offset_in_page(gpa); |
4564 | switch (bytes) { | |
4565 | case 1: | |
4566 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4567 | break; | |
4568 | case 2: | |
4569 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4570 | break; | |
4571 | case 4: | |
4572 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4573 | break; | |
4574 | case 8: | |
4575 | exchanged = CMPXCHG64(kaddr, old, new); | |
4576 | break; | |
4577 | default: | |
4578 | BUG(); | |
2bacc55c | 4579 | } |
8fd75e12 | 4580 | kunmap_atomic(kaddr); |
daea3e73 AK |
4581 | kvm_release_page_dirty(page); |
4582 | ||
4583 | if (!exchanged) | |
4584 | return X86EMUL_CMPXCHG_FAILED; | |
4585 | ||
54bf36aa | 4586 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
f57f2ef5 | 4587 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4588 | |
4589 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4590 | |
3200f405 | 4591 | emul_write: |
daea3e73 | 4592 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4593 | |
0f65dd70 | 4594 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4595 | } |
4596 | ||
cf8f70bf GN |
4597 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4598 | { | |
4599 | /* TODO: String I/O for in kernel device */ | |
4600 | int r; | |
4601 | ||
4602 | if (vcpu->arch.pio.in) | |
e32edf4f | 4603 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, |
cf8f70bf GN |
4604 | vcpu->arch.pio.size, pd); |
4605 | else | |
e32edf4f | 4606 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, |
cf8f70bf GN |
4607 | vcpu->arch.pio.port, vcpu->arch.pio.size, |
4608 | pd); | |
4609 | return r; | |
4610 | } | |
4611 | ||
6f6fbe98 XG |
4612 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4613 | unsigned short port, void *val, | |
4614 | unsigned int count, bool in) | |
cf8f70bf | 4615 | { |
cf8f70bf | 4616 | vcpu->arch.pio.port = port; |
6f6fbe98 | 4617 | vcpu->arch.pio.in = in; |
7972995b | 4618 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4619 | vcpu->arch.pio.size = size; |
4620 | ||
4621 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4622 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4623 | return 1; |
4624 | } | |
4625 | ||
4626 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4627 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4628 | vcpu->run->io.size = size; |
4629 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4630 | vcpu->run->io.count = count; | |
4631 | vcpu->run->io.port = port; | |
4632 | ||
4633 | return 0; | |
4634 | } | |
4635 | ||
6f6fbe98 XG |
4636 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4637 | int size, unsigned short port, void *val, | |
4638 | unsigned int count) | |
cf8f70bf | 4639 | { |
ca1d4a9e | 4640 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4641 | int ret; |
ca1d4a9e | 4642 | |
6f6fbe98 XG |
4643 | if (vcpu->arch.pio.count) |
4644 | goto data_avail; | |
cf8f70bf | 4645 | |
6f6fbe98 XG |
4646 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4647 | if (ret) { | |
4648 | data_avail: | |
4649 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 4650 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 4651 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4652 | return 1; |
4653 | } | |
4654 | ||
cf8f70bf GN |
4655 | return 0; |
4656 | } | |
4657 | ||
6f6fbe98 XG |
4658 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4659 | int size, unsigned short port, | |
4660 | const void *val, unsigned int count) | |
4661 | { | |
4662 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4663 | ||
4664 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 4665 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
4666 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
4667 | } | |
4668 | ||
bbd9b64e CO |
4669 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4670 | { | |
4671 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4672 | } | |
4673 | ||
3cb16fe7 | 4674 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4675 | { |
3cb16fe7 | 4676 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4677 | } |
4678 | ||
5cb56059 | 4679 | int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
4680 | { |
4681 | if (!need_emulate_wbinvd(vcpu)) | |
4682 | return X86EMUL_CONTINUE; | |
4683 | ||
4684 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4685 | int cpu = get_cpu(); |
4686 | ||
4687 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4688 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4689 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4690 | put_cpu(); |
f5f48ee1 | 4691 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4692 | } else |
4693 | wbinvd(); | |
f5f48ee1 SY |
4694 | return X86EMUL_CONTINUE; |
4695 | } | |
5cb56059 JS |
4696 | |
4697 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4698 | { | |
4699 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
4700 | return kvm_emulate_wbinvd_noskip(vcpu); | |
4701 | } | |
f5f48ee1 SY |
4702 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
4703 | ||
5cb56059 JS |
4704 | |
4705 | ||
bcaf5cc5 AK |
4706 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4707 | { | |
5cb56059 | 4708 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
4709 | } |
4710 | ||
52eb5a6d XL |
4711 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4712 | unsigned long *dest) | |
bbd9b64e | 4713 | { |
16f8a6f9 | 4714 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4715 | } |
4716 | ||
52eb5a6d XL |
4717 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4718 | unsigned long value) | |
bbd9b64e | 4719 | { |
338dbc97 | 4720 | |
717746e3 | 4721 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4722 | } |
4723 | ||
52a46617 | 4724 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4725 | { |
52a46617 | 4726 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4727 | } |
4728 | ||
717746e3 | 4729 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4730 | { |
717746e3 | 4731 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4732 | unsigned long value; |
4733 | ||
4734 | switch (cr) { | |
4735 | case 0: | |
4736 | value = kvm_read_cr0(vcpu); | |
4737 | break; | |
4738 | case 2: | |
4739 | value = vcpu->arch.cr2; | |
4740 | break; | |
4741 | case 3: | |
9f8fe504 | 4742 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4743 | break; |
4744 | case 4: | |
4745 | value = kvm_read_cr4(vcpu); | |
4746 | break; | |
4747 | case 8: | |
4748 | value = kvm_get_cr8(vcpu); | |
4749 | break; | |
4750 | default: | |
a737f256 | 4751 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4752 | return 0; |
4753 | } | |
4754 | ||
4755 | return value; | |
4756 | } | |
4757 | ||
717746e3 | 4758 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4759 | { |
717746e3 | 4760 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4761 | int res = 0; |
4762 | ||
52a46617 GN |
4763 | switch (cr) { |
4764 | case 0: | |
49a9b07e | 4765 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
4766 | break; |
4767 | case 2: | |
4768 | vcpu->arch.cr2 = val; | |
4769 | break; | |
4770 | case 3: | |
2390218b | 4771 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
4772 | break; |
4773 | case 4: | |
a83b29c6 | 4774 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
4775 | break; |
4776 | case 8: | |
eea1cff9 | 4777 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
4778 | break; |
4779 | default: | |
a737f256 | 4780 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 4781 | res = -1; |
52a46617 | 4782 | } |
0f12244f GN |
4783 | |
4784 | return res; | |
52a46617 GN |
4785 | } |
4786 | ||
717746e3 | 4787 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 4788 | { |
717746e3 | 4789 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
4790 | } |
4791 | ||
4bff1e86 | 4792 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 4793 | { |
4bff1e86 | 4794 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
4795 | } |
4796 | ||
4bff1e86 | 4797 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 4798 | { |
4bff1e86 | 4799 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
4800 | } |
4801 | ||
1ac9d0cf AK |
4802 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
4803 | { | |
4804 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4805 | } | |
4806 | ||
4807 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4808 | { | |
4809 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4810 | } | |
4811 | ||
4bff1e86 AK |
4812 | static unsigned long emulator_get_cached_segment_base( |
4813 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 4814 | { |
4bff1e86 | 4815 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
4816 | } |
4817 | ||
1aa36616 AK |
4818 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
4819 | struct desc_struct *desc, u32 *base3, | |
4820 | int seg) | |
2dafc6c2 GN |
4821 | { |
4822 | struct kvm_segment var; | |
4823 | ||
4bff1e86 | 4824 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 4825 | *selector = var.selector; |
2dafc6c2 | 4826 | |
378a8b09 GN |
4827 | if (var.unusable) { |
4828 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 4829 | return false; |
378a8b09 | 4830 | } |
2dafc6c2 GN |
4831 | |
4832 | if (var.g) | |
4833 | var.limit >>= 12; | |
4834 | set_desc_limit(desc, var.limit); | |
4835 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
4836 | #ifdef CONFIG_X86_64 |
4837 | if (base3) | |
4838 | *base3 = var.base >> 32; | |
4839 | #endif | |
2dafc6c2 GN |
4840 | desc->type = var.type; |
4841 | desc->s = var.s; | |
4842 | desc->dpl = var.dpl; | |
4843 | desc->p = var.present; | |
4844 | desc->avl = var.avl; | |
4845 | desc->l = var.l; | |
4846 | desc->d = var.db; | |
4847 | desc->g = var.g; | |
4848 | ||
4849 | return true; | |
4850 | } | |
4851 | ||
1aa36616 AK |
4852 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
4853 | struct desc_struct *desc, u32 base3, | |
4854 | int seg) | |
2dafc6c2 | 4855 | { |
4bff1e86 | 4856 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
4857 | struct kvm_segment var; |
4858 | ||
1aa36616 | 4859 | var.selector = selector; |
2dafc6c2 | 4860 | var.base = get_desc_base(desc); |
5601d05b GN |
4861 | #ifdef CONFIG_X86_64 |
4862 | var.base |= ((u64)base3) << 32; | |
4863 | #endif | |
2dafc6c2 GN |
4864 | var.limit = get_desc_limit(desc); |
4865 | if (desc->g) | |
4866 | var.limit = (var.limit << 12) | 0xfff; | |
4867 | var.type = desc->type; | |
2dafc6c2 GN |
4868 | var.dpl = desc->dpl; |
4869 | var.db = desc->d; | |
4870 | var.s = desc->s; | |
4871 | var.l = desc->l; | |
4872 | var.g = desc->g; | |
4873 | var.avl = desc->avl; | |
4874 | var.present = desc->p; | |
4875 | var.unusable = !var.present; | |
4876 | var.padding = 0; | |
4877 | ||
4878 | kvm_set_segment(vcpu, &var, seg); | |
4879 | return; | |
4880 | } | |
4881 | ||
717746e3 AK |
4882 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
4883 | u32 msr_index, u64 *pdata) | |
4884 | { | |
609e36d3 PB |
4885 | struct msr_data msr; |
4886 | int r; | |
4887 | ||
4888 | msr.index = msr_index; | |
4889 | msr.host_initiated = false; | |
4890 | r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); | |
4891 | if (r) | |
4892 | return r; | |
4893 | ||
4894 | *pdata = msr.data; | |
4895 | return 0; | |
717746e3 AK |
4896 | } |
4897 | ||
4898 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4899 | u32 msr_index, u64 data) | |
4900 | { | |
8fe8ab46 WA |
4901 | struct msr_data msr; |
4902 | ||
4903 | msr.data = data; | |
4904 | msr.index = msr_index; | |
4905 | msr.host_initiated = false; | |
4906 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
4907 | } |
4908 | ||
64d60670 PB |
4909 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
4910 | { | |
4911 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4912 | ||
4913 | return vcpu->arch.smbase; | |
4914 | } | |
4915 | ||
4916 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
4917 | { | |
4918 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4919 | ||
4920 | vcpu->arch.smbase = smbase; | |
4921 | } | |
4922 | ||
67f4d428 NA |
4923 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
4924 | u32 pmc) | |
4925 | { | |
c6702c9d | 4926 | return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
4927 | } |
4928 | ||
222d21aa AK |
4929 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
4930 | u32 pmc, u64 *pdata) | |
4931 | { | |
c6702c9d | 4932 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
4933 | } |
4934 | ||
6c3287f7 AK |
4935 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
4936 | { | |
4937 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4938 | } | |
4939 | ||
5037f6f3 AK |
4940 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
4941 | { | |
4942 | preempt_disable(); | |
5197b808 | 4943 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
4944 | /* |
4945 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4946 | * so it may be clear at this point. | |
4947 | */ | |
4948 | clts(); | |
4949 | } | |
4950 | ||
4951 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4952 | { | |
4953 | preempt_enable(); | |
4954 | } | |
4955 | ||
2953538e | 4956 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 4957 | struct x86_instruction_info *info, |
c4f035c6 AK |
4958 | enum x86_intercept_stage stage) |
4959 | { | |
2953538e | 4960 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
4961 | } |
4962 | ||
0017f93a | 4963 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
4964 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
4965 | { | |
0017f93a | 4966 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
4967 | } |
4968 | ||
dd856efa AK |
4969 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
4970 | { | |
4971 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
4972 | } | |
4973 | ||
4974 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
4975 | { | |
4976 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
4977 | } | |
4978 | ||
801806d9 NA |
4979 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
4980 | { | |
4981 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
4982 | } | |
4983 | ||
0225fb50 | 4984 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
4985 | .read_gpr = emulator_read_gpr, |
4986 | .write_gpr = emulator_write_gpr, | |
1871c602 | 4987 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4988 | .write_std = kvm_write_guest_virt_system, |
7a036a6f | 4989 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 4990 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4991 | .read_emulated = emulator_read_emulated, |
4992 | .write_emulated = emulator_write_emulated, | |
4993 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 4994 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
4995 | .pio_in_emulated = emulator_pio_in_emulated, |
4996 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
4997 | .get_segment = emulator_get_segment, |
4998 | .set_segment = emulator_set_segment, | |
5951c442 | 4999 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 5000 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 5001 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
5002 | .set_gdt = emulator_set_gdt, |
5003 | .set_idt = emulator_set_idt, | |
52a46617 GN |
5004 | .get_cr = emulator_get_cr, |
5005 | .set_cr = emulator_set_cr, | |
9c537244 | 5006 | .cpl = emulator_get_cpl, |
35aa5375 GN |
5007 | .get_dr = emulator_get_dr, |
5008 | .set_dr = emulator_set_dr, | |
64d60670 PB |
5009 | .get_smbase = emulator_get_smbase, |
5010 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
5011 | .set_msr = emulator_set_msr, |
5012 | .get_msr = emulator_get_msr, | |
67f4d428 | 5013 | .check_pmc = emulator_check_pmc, |
222d21aa | 5014 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 5015 | .halt = emulator_halt, |
bcaf5cc5 | 5016 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 5017 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
5018 | .get_fpu = emulator_get_fpu, |
5019 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 5020 | .intercept = emulator_intercept, |
bdb42f5a | 5021 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 5022 | .set_nmi_mask = emulator_set_nmi_mask, |
bbd9b64e CO |
5023 | }; |
5024 | ||
95cb2295 GN |
5025 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
5026 | { | |
37ccdcbe | 5027 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
5028 | /* |
5029 | * an sti; sti; sequence only disable interrupts for the first | |
5030 | * instruction. So, if the last instruction, be it emulated or | |
5031 | * not, left the system with the INT_STI flag enabled, it | |
5032 | * means that the last instruction is an sti. We should not | |
5033 | * leave the flag on in this case. The same goes for mov ss | |
5034 | */ | |
37ccdcbe PB |
5035 | if (int_shadow & mask) |
5036 | mask = 0; | |
6addfc42 | 5037 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 5038 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
5039 | if (!mask) |
5040 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5041 | } | |
95cb2295 GN |
5042 | } |
5043 | ||
ef54bcfe | 5044 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
5045 | { |
5046 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 5047 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
5048 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
5049 | ||
5050 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
5051 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
5052 | ctxt->exception.error_code); | |
54b8486f | 5053 | else |
da9cb575 | 5054 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 5055 | return false; |
54b8486f GN |
5056 | } |
5057 | ||
8ec4722d MG |
5058 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
5059 | { | |
adf52235 | 5060 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
5061 | int cs_db, cs_l; |
5062 | ||
8ec4722d MG |
5063 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
5064 | ||
adf52235 TY |
5065 | ctxt->eflags = kvm_get_rflags(vcpu); |
5066 | ctxt->eip = kvm_rip_read(vcpu); | |
5067 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5068 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 5069 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
5070 | cs_db ? X86EMUL_MODE_PROT32 : |
5071 | X86EMUL_MODE_PROT16; | |
a584539b | 5072 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
5073 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
5074 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
a584539b | 5075 | ctxt->emul_flags = vcpu->arch.hflags; |
adf52235 | 5076 | |
dd856efa | 5077 | init_decode_cache(ctxt); |
7ae441ea | 5078 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5079 | } |
5080 | ||
71f9833b | 5081 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5082 | { |
9d74191a | 5083 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5084 | int ret; |
5085 | ||
5086 | init_emulate_ctxt(vcpu); | |
5087 | ||
9dac77fa AK |
5088 | ctxt->op_bytes = 2; |
5089 | ctxt->ad_bytes = 2; | |
5090 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5091 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5092 | |
5093 | if (ret != X86EMUL_CONTINUE) | |
5094 | return EMULATE_FAIL; | |
5095 | ||
9dac77fa | 5096 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5097 | kvm_rip_write(vcpu, ctxt->eip); |
5098 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
5099 | |
5100 | if (irq == NMI_VECTOR) | |
7460fb4a | 5101 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
5102 | else |
5103 | vcpu->arch.interrupt.pending = false; | |
5104 | ||
5105 | return EMULATE_DONE; | |
5106 | } | |
5107 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5108 | ||
6d77dbfc GN |
5109 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
5110 | { | |
fc3a9157 JR |
5111 | int r = EMULATE_DONE; |
5112 | ||
6d77dbfc GN |
5113 | ++vcpu->stat.insn_emulation_fail; |
5114 | trace_kvm_emulate_insn_failed(vcpu); | |
a2b9e6c1 | 5115 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5116 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5117 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5118 | vcpu->run->internal.ndata = 0; | |
5119 | r = EMULATE_FAIL; | |
5120 | } | |
6d77dbfc | 5121 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5122 | |
5123 | return r; | |
6d77dbfc GN |
5124 | } |
5125 | ||
93c05d3e | 5126 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5127 | bool write_fault_to_shadow_pgtable, |
5128 | int emulation_type) | |
a6f177ef | 5129 | { |
95b3cf69 | 5130 | gpa_t gpa = cr2; |
8e3d9d06 | 5131 | pfn_t pfn; |
a6f177ef | 5132 | |
991eebf9 GN |
5133 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5134 | return false; | |
5135 | ||
95b3cf69 XG |
5136 | if (!vcpu->arch.mmu.direct_map) { |
5137 | /* | |
5138 | * Write permission should be allowed since only | |
5139 | * write access need to be emulated. | |
5140 | */ | |
5141 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5142 | |
95b3cf69 XG |
5143 | /* |
5144 | * If the mapping is invalid in guest, let cpu retry | |
5145 | * it to generate fault. | |
5146 | */ | |
5147 | if (gpa == UNMAPPED_GVA) | |
5148 | return true; | |
5149 | } | |
a6f177ef | 5150 | |
8e3d9d06 XG |
5151 | /* |
5152 | * Do not retry the unhandleable instruction if it faults on the | |
5153 | * readonly host memory, otherwise it will goto a infinite loop: | |
5154 | * retry instruction -> write #PF -> emulation fail -> retry | |
5155 | * instruction -> ... | |
5156 | */ | |
5157 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5158 | |
5159 | /* | |
5160 | * If the instruction failed on the error pfn, it can not be fixed, | |
5161 | * report the error to userspace. | |
5162 | */ | |
5163 | if (is_error_noslot_pfn(pfn)) | |
5164 | return false; | |
5165 | ||
5166 | kvm_release_pfn_clean(pfn); | |
5167 | ||
5168 | /* The instructions are well-emulated on direct mmu. */ | |
5169 | if (vcpu->arch.mmu.direct_map) { | |
5170 | unsigned int indirect_shadow_pages; | |
5171 | ||
5172 | spin_lock(&vcpu->kvm->mmu_lock); | |
5173 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5174 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5175 | ||
5176 | if (indirect_shadow_pages) | |
5177 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5178 | ||
a6f177ef | 5179 | return true; |
8e3d9d06 | 5180 | } |
a6f177ef | 5181 | |
95b3cf69 XG |
5182 | /* |
5183 | * if emulation was due to access to shadowed page table | |
5184 | * and it failed try to unshadow page and re-enter the | |
5185 | * guest to let CPU execute the instruction. | |
5186 | */ | |
5187 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5188 | |
5189 | /* | |
5190 | * If the access faults on its page table, it can not | |
5191 | * be fixed by unprotecting shadow page and it should | |
5192 | * be reported to userspace. | |
5193 | */ | |
5194 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5195 | } |
5196 | ||
1cb3f3ae XG |
5197 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5198 | unsigned long cr2, int emulation_type) | |
5199 | { | |
5200 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5201 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5202 | ||
5203 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5204 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5205 | ||
5206 | /* | |
5207 | * If the emulation is caused by #PF and it is non-page_table | |
5208 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5209 | * page protected, we can zap the shadow page and retry this | |
5210 | * instruction directly. | |
5211 | * | |
5212 | * Note: if the guest uses a non-page-table modifying instruction | |
5213 | * on the PDE that points to the instruction, then we will unmap | |
5214 | * the instruction and go to an infinite loop. So, we cache the | |
5215 | * last retried eip and the last fault address, if we meet the eip | |
5216 | * and the address again, we can break out of the potential infinite | |
5217 | * loop. | |
5218 | */ | |
5219 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5220 | ||
5221 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5222 | return false; | |
5223 | ||
5224 | if (x86_page_table_writing_insn(ctxt)) | |
5225 | return false; | |
5226 | ||
5227 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5228 | return false; | |
5229 | ||
5230 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5231 | vcpu->arch.last_retry_addr = cr2; | |
5232 | ||
5233 | if (!vcpu->arch.mmu.direct_map) | |
5234 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5235 | ||
22368028 | 5236 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5237 | |
5238 | return true; | |
5239 | } | |
5240 | ||
716d51ab GN |
5241 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5242 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5243 | ||
64d60670 | 5244 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 5245 | { |
64d60670 | 5246 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
5247 | /* This is a good place to trace that we are exiting SMM. */ |
5248 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
5249 | ||
64d60670 PB |
5250 | if (unlikely(vcpu->arch.smi_pending)) { |
5251 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
5252 | vcpu->arch.smi_pending = 0; | |
cd7764fe PB |
5253 | } else { |
5254 | /* Process a latched INIT, if any. */ | |
5255 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 PB |
5256 | } |
5257 | } | |
699023e2 PB |
5258 | |
5259 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
5260 | } |
5261 | ||
5262 | static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) | |
5263 | { | |
5264 | unsigned changed = vcpu->arch.hflags ^ emul_flags; | |
5265 | ||
a584539b | 5266 | vcpu->arch.hflags = emul_flags; |
64d60670 PB |
5267 | |
5268 | if (changed & HF_SMM_MASK) | |
5269 | kvm_smm_changed(vcpu); | |
a584539b PB |
5270 | } |
5271 | ||
4a1e10d5 PB |
5272 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5273 | unsigned long *db) | |
5274 | { | |
5275 | u32 dr6 = 0; | |
5276 | int i; | |
5277 | u32 enable, rwlen; | |
5278 | ||
5279 | enable = dr7; | |
5280 | rwlen = dr7 >> 16; | |
5281 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5282 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5283 | dr6 |= (1 << i); | |
5284 | return dr6; | |
5285 | } | |
5286 | ||
6addfc42 | 5287 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) |
663f4c61 PB |
5288 | { |
5289 | struct kvm_run *kvm_run = vcpu->run; | |
5290 | ||
5291 | /* | |
6addfc42 PB |
5292 | * rflags is the old, "raw" value of the flags. The new value has |
5293 | * not been saved yet. | |
663f4c61 PB |
5294 | * |
5295 | * This is correct even for TF set by the guest, because "the | |
5296 | * processor will not generate this exception after the instruction | |
5297 | * that sets the TF flag". | |
5298 | */ | |
663f4c61 PB |
5299 | if (unlikely(rflags & X86_EFLAGS_TF)) { |
5300 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
6f43ed01 NA |
5301 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | |
5302 | DR6_RTM; | |
663f4c61 PB |
5303 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; |
5304 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5305 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5306 | *r = EMULATE_USER_EXIT; | |
5307 | } else { | |
5308 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5309 | /* | |
5310 | * "Certain debug exceptions may clear bit 0-3. The | |
5311 | * remaining contents of the DR6 register are never | |
5312 | * cleared by the processor". | |
5313 | */ | |
5314 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5315 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; |
663f4c61 PB |
5316 | kvm_queue_exception(vcpu, DB_VECTOR); |
5317 | } | |
5318 | } | |
5319 | } | |
5320 | ||
4a1e10d5 PB |
5321 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5322 | { | |
4a1e10d5 PB |
5323 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5324 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5325 | struct kvm_run *kvm_run = vcpu->run; |
5326 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5327 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5328 | vcpu->arch.guest_debug_dr7, |
5329 | vcpu->arch.eff_db); | |
5330 | ||
5331 | if (dr6 != 0) { | |
6f43ed01 | 5332 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5333 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5334 | kvm_run->debug.arch.exception = DB_VECTOR; |
5335 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5336 | *r = EMULATE_USER_EXIT; | |
5337 | return true; | |
5338 | } | |
5339 | } | |
5340 | ||
4161a569 NA |
5341 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5342 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5343 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5344 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5345 | vcpu->arch.dr7, |
5346 | vcpu->arch.db); | |
5347 | ||
5348 | if (dr6 != 0) { | |
5349 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5350 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5351 | kvm_queue_exception(vcpu, DB_VECTOR); |
5352 | *r = EMULATE_DONE; | |
5353 | return true; | |
5354 | } | |
5355 | } | |
5356 | ||
5357 | return false; | |
5358 | } | |
5359 | ||
51d8b661 AP |
5360 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5361 | unsigned long cr2, | |
dc25e89e AP |
5362 | int emulation_type, |
5363 | void *insn, | |
5364 | int insn_len) | |
bbd9b64e | 5365 | { |
95cb2295 | 5366 | int r; |
9d74191a | 5367 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5368 | bool writeback = true; |
93c05d3e | 5369 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5370 | |
93c05d3e XG |
5371 | /* |
5372 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5373 | * never reused. | |
5374 | */ | |
5375 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5376 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5377 | |
571008da | 5378 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5379 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5380 | |
5381 | /* | |
5382 | * We will reenter on the same instruction since | |
5383 | * we do not set complete_userspace_io. This does not | |
5384 | * handle watchpoints yet, those would be handled in | |
5385 | * the emulate_ops. | |
5386 | */ | |
5387 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5388 | return r; | |
5389 | ||
9d74191a TY |
5390 | ctxt->interruptibility = 0; |
5391 | ctxt->have_exception = false; | |
e0ad0b47 | 5392 | ctxt->exception.vector = -1; |
9d74191a | 5393 | ctxt->perm_ok = false; |
bbd9b64e | 5394 | |
b51e974f | 5395 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 5396 | |
9d74191a | 5397 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 5398 | |
e46479f8 | 5399 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 5400 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 5401 | if (r != EMULATION_OK) { |
4005996e AK |
5402 | if (emulation_type & EMULTYPE_TRAP_UD) |
5403 | return EMULATE_FAIL; | |
991eebf9 GN |
5404 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5405 | emulation_type)) | |
bbd9b64e | 5406 | return EMULATE_DONE; |
6d77dbfc GN |
5407 | if (emulation_type & EMULTYPE_SKIP) |
5408 | return EMULATE_FAIL; | |
5409 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
5410 | } |
5411 | } | |
5412 | ||
ba8afb6b | 5413 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 5414 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
5415 | if (ctxt->eflags & X86_EFLAGS_RF) |
5416 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
5417 | return EMULATE_DONE; |
5418 | } | |
5419 | ||
1cb3f3ae XG |
5420 | if (retry_instruction(ctxt, cr2, emulation_type)) |
5421 | return EMULATE_DONE; | |
5422 | ||
7ae441ea | 5423 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 5424 | changes registers values during IO operation */ |
7ae441ea GN |
5425 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
5426 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 5427 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 5428 | } |
4d2179e1 | 5429 | |
5cd21917 | 5430 | restart: |
9d74191a | 5431 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 5432 | |
775fde86 JR |
5433 | if (r == EMULATION_INTERCEPTED) |
5434 | return EMULATE_DONE; | |
5435 | ||
d2ddd1c4 | 5436 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
5437 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5438 | emulation_type)) | |
c3cd7ffa GN |
5439 | return EMULATE_DONE; |
5440 | ||
6d77dbfc | 5441 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
5442 | } |
5443 | ||
9d74191a | 5444 | if (ctxt->have_exception) { |
d2ddd1c4 | 5445 | r = EMULATE_DONE; |
ef54bcfe PB |
5446 | if (inject_emulated_exception(vcpu)) |
5447 | return r; | |
d2ddd1c4 | 5448 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
5449 | if (!vcpu->arch.pio.in) { |
5450 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 5451 | vcpu->arch.pio.count = 0; |
0912c977 | 5452 | } else { |
7ae441ea | 5453 | writeback = false; |
716d51ab GN |
5454 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
5455 | } | |
ac0a48c3 | 5456 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
5457 | } else if (vcpu->mmio_needed) { |
5458 | if (!vcpu->mmio_is_write) | |
5459 | writeback = false; | |
ac0a48c3 | 5460 | r = EMULATE_USER_EXIT; |
716d51ab | 5461 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5462 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5463 | goto restart; |
d2ddd1c4 GN |
5464 | else |
5465 | r = EMULATE_DONE; | |
f850e2e6 | 5466 | |
7ae441ea | 5467 | if (writeback) { |
6addfc42 | 5468 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 5469 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 5470 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
a584539b PB |
5471 | if (vcpu->arch.hflags != ctxt->emul_flags) |
5472 | kvm_set_hflags(vcpu, ctxt->emul_flags); | |
9d74191a | 5473 | kvm_rip_write(vcpu, ctxt->eip); |
663f4c61 | 5474 | if (r == EMULATE_DONE) |
6addfc42 | 5475 | kvm_vcpu_check_singlestep(vcpu, rflags, &r); |
38827dbd NA |
5476 | if (!ctxt->have_exception || |
5477 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
5478 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
5479 | |
5480 | /* | |
5481 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
5482 | * do nothing, and it will be requested again as soon as | |
5483 | * the shadow expires. But we still need to check here, | |
5484 | * because POPF has no interrupt shadow. | |
5485 | */ | |
5486 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
5487 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
5488 | } else |
5489 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5490 | |
5491 | return r; | |
de7d789a | 5492 | } |
51d8b661 | 5493 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5494 | |
cf8f70bf | 5495 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5496 | { |
cf8f70bf | 5497 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5498 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5499 | size, port, &val, 1); | |
cf8f70bf | 5500 | /* do not return to emulator after return from userspace */ |
7972995b | 5501 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5502 | return ret; |
5503 | } | |
cf8f70bf | 5504 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5505 | |
8cfdc000 ZA |
5506 | static void tsc_bad(void *info) |
5507 | { | |
0a3aee0d | 5508 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5509 | } |
5510 | ||
5511 | static void tsc_khz_changed(void *data) | |
c8076604 | 5512 | { |
8cfdc000 ZA |
5513 | struct cpufreq_freqs *freq = data; |
5514 | unsigned long khz = 0; | |
5515 | ||
5516 | if (data) | |
5517 | khz = freq->new; | |
5518 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5519 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5520 | if (!khz) | |
5521 | khz = tsc_khz; | |
0a3aee0d | 5522 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5523 | } |
5524 | ||
c8076604 GH |
5525 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5526 | void *data) | |
5527 | { | |
5528 | struct cpufreq_freqs *freq = data; | |
5529 | struct kvm *kvm; | |
5530 | struct kvm_vcpu *vcpu; | |
5531 | int i, send_ipi = 0; | |
5532 | ||
8cfdc000 ZA |
5533 | /* |
5534 | * We allow guests to temporarily run on slowing clocks, | |
5535 | * provided we notify them after, or to run on accelerating | |
5536 | * clocks, provided we notify them before. Thus time never | |
5537 | * goes backwards. | |
5538 | * | |
5539 | * However, we have a problem. We can't atomically update | |
5540 | * the frequency of a given CPU from this function; it is | |
5541 | * merely a notifier, which can be called from any CPU. | |
5542 | * Changing the TSC frequency at arbitrary points in time | |
5543 | * requires a recomputation of local variables related to | |
5544 | * the TSC for each VCPU. We must flag these local variables | |
5545 | * to be updated and be sure the update takes place with the | |
5546 | * new frequency before any guests proceed. | |
5547 | * | |
5548 | * Unfortunately, the combination of hotplug CPU and frequency | |
5549 | * change creates an intractable locking scenario; the order | |
5550 | * of when these callouts happen is undefined with respect to | |
5551 | * CPU hotplug, and they can race with each other. As such, | |
5552 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5553 | * undefined; you can actually have a CPU frequency change take | |
5554 | * place in between the computation of X and the setting of the | |
5555 | * variable. To protect against this problem, all updates of | |
5556 | * the per_cpu tsc_khz variable are done in an interrupt | |
5557 | * protected IPI, and all callers wishing to update the value | |
5558 | * must wait for a synchronous IPI to complete (which is trivial | |
5559 | * if the caller is on the CPU already). This establishes the | |
5560 | * necessary total order on variable updates. | |
5561 | * | |
5562 | * Note that because a guest time update may take place | |
5563 | * anytime after the setting of the VCPU's request bit, the | |
5564 | * correct TSC value must be set before the request. However, | |
5565 | * to ensure the update actually makes it to any guest which | |
5566 | * starts running in hardware virtualization between the set | |
5567 | * and the acquisition of the spinlock, we must also ping the | |
5568 | * CPU after setting the request bit. | |
5569 | * | |
5570 | */ | |
5571 | ||
c8076604 GH |
5572 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5573 | return 0; | |
5574 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5575 | return 0; | |
8cfdc000 ZA |
5576 | |
5577 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5578 | |
2f303b74 | 5579 | spin_lock(&kvm_lock); |
c8076604 | 5580 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5581 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5582 | if (vcpu->cpu != freq->cpu) |
5583 | continue; | |
c285545f | 5584 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5585 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5586 | send_ipi = 1; |
c8076604 GH |
5587 | } |
5588 | } | |
2f303b74 | 5589 | spin_unlock(&kvm_lock); |
c8076604 GH |
5590 | |
5591 | if (freq->old < freq->new && send_ipi) { | |
5592 | /* | |
5593 | * We upscale the frequency. Must make the guest | |
5594 | * doesn't see old kvmclock values while running with | |
5595 | * the new frequency, otherwise we risk the guest sees | |
5596 | * time go backwards. | |
5597 | * | |
5598 | * In case we update the frequency for another cpu | |
5599 | * (which might be in guest context) send an interrupt | |
5600 | * to kick the cpu out of guest context. Next time | |
5601 | * guest context is entered kvmclock will be updated, | |
5602 | * so the guest will not see stale values. | |
5603 | */ | |
8cfdc000 | 5604 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5605 | } |
5606 | return 0; | |
5607 | } | |
5608 | ||
5609 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5610 | .notifier_call = kvmclock_cpufreq_notifier |
5611 | }; | |
5612 | ||
5613 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5614 | unsigned long action, void *hcpu) | |
5615 | { | |
5616 | unsigned int cpu = (unsigned long)hcpu; | |
5617 | ||
5618 | switch (action) { | |
5619 | case CPU_ONLINE: | |
5620 | case CPU_DOWN_FAILED: | |
5621 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5622 | break; | |
5623 | case CPU_DOWN_PREPARE: | |
5624 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5625 | break; | |
5626 | } | |
5627 | return NOTIFY_OK; | |
5628 | } | |
5629 | ||
5630 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5631 | .notifier_call = kvmclock_cpu_notifier, | |
5632 | .priority = -INT_MAX | |
c8076604 GH |
5633 | }; |
5634 | ||
b820cc0c ZA |
5635 | static void kvm_timer_init(void) |
5636 | { | |
5637 | int cpu; | |
5638 | ||
c285545f | 5639 | max_tsc_khz = tsc_khz; |
460dd42e SB |
5640 | |
5641 | cpu_notifier_register_begin(); | |
b820cc0c | 5642 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5643 | #ifdef CONFIG_CPU_FREQ |
5644 | struct cpufreq_policy policy; | |
5645 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5646 | cpu = get_cpu(); |
5647 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5648 | if (policy.cpuinfo.max_freq) |
5649 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5650 | put_cpu(); |
c285545f | 5651 | #endif |
b820cc0c ZA |
5652 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5653 | CPUFREQ_TRANSITION_NOTIFIER); | |
5654 | } | |
c285545f | 5655 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5656 | for_each_online_cpu(cpu) |
5657 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
460dd42e SB |
5658 | |
5659 | __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5660 | cpu_notifier_register_done(); | |
5661 | ||
b820cc0c ZA |
5662 | } |
5663 | ||
ff9d07a0 ZY |
5664 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5665 | ||
f5132b01 | 5666 | int kvm_is_in_guest(void) |
ff9d07a0 | 5667 | { |
086c9855 | 5668 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5669 | } |
5670 | ||
5671 | static int kvm_is_user_mode(void) | |
5672 | { | |
5673 | int user_mode = 3; | |
dcf46b94 | 5674 | |
086c9855 AS |
5675 | if (__this_cpu_read(current_vcpu)) |
5676 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5677 | |
ff9d07a0 ZY |
5678 | return user_mode != 0; |
5679 | } | |
5680 | ||
5681 | static unsigned long kvm_get_guest_ip(void) | |
5682 | { | |
5683 | unsigned long ip = 0; | |
dcf46b94 | 5684 | |
086c9855 AS |
5685 | if (__this_cpu_read(current_vcpu)) |
5686 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5687 | |
ff9d07a0 ZY |
5688 | return ip; |
5689 | } | |
5690 | ||
5691 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5692 | .is_in_guest = kvm_is_in_guest, | |
5693 | .is_user_mode = kvm_is_user_mode, | |
5694 | .get_guest_ip = kvm_get_guest_ip, | |
5695 | }; | |
5696 | ||
5697 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5698 | { | |
086c9855 | 5699 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5700 | } |
5701 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5702 | ||
5703 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5704 | { | |
086c9855 | 5705 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5706 | } |
5707 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5708 | ||
ce88decf XG |
5709 | static void kvm_set_mmio_spte_mask(void) |
5710 | { | |
5711 | u64 mask; | |
5712 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5713 | ||
5714 | /* | |
5715 | * Set the reserved bits and the present bit of an paging-structure | |
5716 | * entry to generate page fault with PFER.RSV = 1. | |
5717 | */ | |
885032b9 | 5718 | /* Mask the reserved physical address bits. */ |
d1431483 | 5719 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 XG |
5720 | |
5721 | /* Bit 62 is always reserved for 32bit host. */ | |
5722 | mask |= 0x3ull << 62; | |
5723 | ||
5724 | /* Set the present bit. */ | |
ce88decf XG |
5725 | mask |= 1ull; |
5726 | ||
5727 | #ifdef CONFIG_X86_64 | |
5728 | /* | |
5729 | * If reserved bit is not supported, clear the present bit to disable | |
5730 | * mmio page fault. | |
5731 | */ | |
5732 | if (maxphyaddr == 52) | |
5733 | mask &= ~1ull; | |
5734 | #endif | |
5735 | ||
5736 | kvm_mmu_set_mmio_spte_mask(mask); | |
5737 | } | |
5738 | ||
16e8d74d MT |
5739 | #ifdef CONFIG_X86_64 |
5740 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5741 | { | |
d828199e MT |
5742 | struct kvm *kvm; |
5743 | ||
5744 | struct kvm_vcpu *vcpu; | |
5745 | int i; | |
5746 | ||
2f303b74 | 5747 | spin_lock(&kvm_lock); |
d828199e MT |
5748 | list_for_each_entry(kvm, &vm_list, vm_list) |
5749 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 5750 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 5751 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 5752 | spin_unlock(&kvm_lock); |
16e8d74d MT |
5753 | } |
5754 | ||
5755 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5756 | ||
5757 | /* | |
5758 | * Notification about pvclock gtod data update. | |
5759 | */ | |
5760 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5761 | void *priv) | |
5762 | { | |
5763 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5764 | struct timekeeper *tk = priv; | |
5765 | ||
5766 | update_pvclock_gtod(tk); | |
5767 | ||
5768 | /* disable master clock if host does not trust, or does not | |
5769 | * use, TSC clocksource | |
5770 | */ | |
5771 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5772 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5773 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5774 | ||
5775 | return 0; | |
5776 | } | |
5777 | ||
5778 | static struct notifier_block pvclock_gtod_notifier = { | |
5779 | .notifier_call = pvclock_gtod_notify, | |
5780 | }; | |
5781 | #endif | |
5782 | ||
f8c16bba | 5783 | int kvm_arch_init(void *opaque) |
043405e1 | 5784 | { |
b820cc0c | 5785 | int r; |
6b61edf7 | 5786 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 5787 | |
f8c16bba ZX |
5788 | if (kvm_x86_ops) { |
5789 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
5790 | r = -EEXIST; |
5791 | goto out; | |
f8c16bba ZX |
5792 | } |
5793 | ||
5794 | if (!ops->cpu_has_kvm_support()) { | |
5795 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
5796 | r = -EOPNOTSUPP; |
5797 | goto out; | |
f8c16bba ZX |
5798 | } |
5799 | if (ops->disabled_by_bios()) { | |
5800 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
5801 | r = -EOPNOTSUPP; |
5802 | goto out; | |
f8c16bba ZX |
5803 | } |
5804 | ||
013f6a5d MT |
5805 | r = -ENOMEM; |
5806 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5807 | if (!shared_msrs) { | |
5808 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5809 | goto out; | |
5810 | } | |
5811 | ||
97db56ce AK |
5812 | r = kvm_mmu_module_init(); |
5813 | if (r) | |
013f6a5d | 5814 | goto out_free_percpu; |
97db56ce | 5815 | |
ce88decf | 5816 | kvm_set_mmio_spte_mask(); |
97db56ce | 5817 | |
f8c16bba | 5818 | kvm_x86_ops = ops; |
920c8377 | 5819 | |
7b52345e | 5820 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 5821 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 5822 | |
b820cc0c | 5823 | kvm_timer_init(); |
c8076604 | 5824 | |
ff9d07a0 ZY |
5825 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
5826 | ||
2acf923e DC |
5827 | if (cpu_has_xsave) |
5828 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
5829 | ||
c5cc421b | 5830 | kvm_lapic_init(); |
16e8d74d MT |
5831 | #ifdef CONFIG_X86_64 |
5832 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5833 | #endif | |
5834 | ||
f8c16bba | 5835 | return 0; |
56c6d28a | 5836 | |
013f6a5d MT |
5837 | out_free_percpu: |
5838 | free_percpu(shared_msrs); | |
56c6d28a | 5839 | out: |
56c6d28a | 5840 | return r; |
043405e1 | 5841 | } |
8776e519 | 5842 | |
f8c16bba ZX |
5843 | void kvm_arch_exit(void) |
5844 | { | |
ff9d07a0 ZY |
5845 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
5846 | ||
888d256e JK |
5847 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
5848 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5849 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 5850 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
5851 | #ifdef CONFIG_X86_64 |
5852 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5853 | #endif | |
f8c16bba | 5854 | kvm_x86_ops = NULL; |
56c6d28a | 5855 | kvm_mmu_module_exit(); |
013f6a5d | 5856 | free_percpu(shared_msrs); |
56c6d28a | 5857 | } |
f8c16bba | 5858 | |
5cb56059 | 5859 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
5860 | { |
5861 | ++vcpu->stat.halt_exits; | |
35754c98 | 5862 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 5863 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
5864 | return 1; |
5865 | } else { | |
5866 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5867 | return 0; | |
5868 | } | |
5869 | } | |
5cb56059 JS |
5870 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
5871 | ||
5872 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
5873 | { | |
5874 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
5875 | return kvm_vcpu_halt(vcpu); | |
5876 | } | |
8776e519 HB |
5877 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
5878 | ||
6aef266c SV |
5879 | /* |
5880 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
5881 | * | |
5882 | * @apicid - apicid of vcpu to be kicked. | |
5883 | */ | |
5884 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
5885 | { | |
24d2166b | 5886 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 5887 | |
24d2166b R |
5888 | lapic_irq.shorthand = 0; |
5889 | lapic_irq.dest_mode = 0; | |
5890 | lapic_irq.dest_id = apicid; | |
93bbf0b8 | 5891 | lapic_irq.msi_redir_hint = false; |
6aef266c | 5892 | |
24d2166b | 5893 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 5894 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
5895 | } |
5896 | ||
d62caabb AS |
5897 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) |
5898 | { | |
5899 | vcpu->arch.apicv_active = false; | |
5900 | kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); | |
5901 | } | |
5902 | ||
8776e519 HB |
5903 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
5904 | { | |
5905 | unsigned long nr, a0, a1, a2, a3, ret; | |
a449c7aa | 5906 | int op_64_bit, r = 1; |
8776e519 | 5907 | |
5cb56059 JS |
5908 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
5909 | ||
55cd8e5a GN |
5910 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
5911 | return kvm_hv_hypercall(vcpu); | |
5912 | ||
5fdbf976 MT |
5913 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5914 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5915 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5916 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5917 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 5918 | |
229456fc | 5919 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 5920 | |
a449c7aa NA |
5921 | op_64_bit = is_64_bit_mode(vcpu); |
5922 | if (!op_64_bit) { | |
8776e519 HB |
5923 | nr &= 0xFFFFFFFF; |
5924 | a0 &= 0xFFFFFFFF; | |
5925 | a1 &= 0xFFFFFFFF; | |
5926 | a2 &= 0xFFFFFFFF; | |
5927 | a3 &= 0xFFFFFFFF; | |
5928 | } | |
5929 | ||
07708c4a JK |
5930 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
5931 | ret = -KVM_EPERM; | |
5932 | goto out; | |
5933 | } | |
5934 | ||
8776e519 | 5935 | switch (nr) { |
b93463aa AK |
5936 | case KVM_HC_VAPIC_POLL_IRQ: |
5937 | ret = 0; | |
5938 | break; | |
6aef266c SV |
5939 | case KVM_HC_KICK_CPU: |
5940 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
5941 | ret = 0; | |
5942 | break; | |
8776e519 HB |
5943 | default: |
5944 | ret = -KVM_ENOSYS; | |
5945 | break; | |
5946 | } | |
07708c4a | 5947 | out: |
a449c7aa NA |
5948 | if (!op_64_bit) |
5949 | ret = (u32)ret; | |
5fdbf976 | 5950 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 5951 | ++vcpu->stat.hypercalls; |
2f333bcb | 5952 | return r; |
8776e519 HB |
5953 | } |
5954 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
5955 | ||
b6785def | 5956 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 5957 | { |
d6aa1000 | 5958 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 5959 | char instruction[3]; |
5fdbf976 | 5960 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 5961 | |
8776e519 | 5962 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 5963 | |
9d74191a | 5964 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
5965 | } |
5966 | ||
851ba692 | 5967 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5968 | { |
782d422b MG |
5969 | return vcpu->run->request_interrupt_window && |
5970 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
5971 | } |
5972 | ||
851ba692 | 5973 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 5974 | { |
851ba692 AK |
5975 | struct kvm_run *kvm_run = vcpu->run; |
5976 | ||
91586a3b | 5977 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 5978 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 5979 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 5980 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
5981 | kvm_run->ready_for_interrupt_injection = |
5982 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 5983 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
5984 | } |
5985 | ||
95ba8273 GN |
5986 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
5987 | { | |
5988 | int max_irr, tpr; | |
5989 | ||
5990 | if (!kvm_x86_ops->update_cr8_intercept) | |
5991 | return; | |
5992 | ||
88c808fd AK |
5993 | if (!vcpu->arch.apic) |
5994 | return; | |
5995 | ||
d62caabb AS |
5996 | if (vcpu->arch.apicv_active) |
5997 | return; | |
5998 | ||
8db3baa2 GN |
5999 | if (!vcpu->arch.apic->vapic_addr) |
6000 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
6001 | else | |
6002 | max_irr = -1; | |
95ba8273 GN |
6003 | |
6004 | if (max_irr != -1) | |
6005 | max_irr >>= 4; | |
6006 | ||
6007 | tpr = kvm_lapic_get_cr8(vcpu); | |
6008 | ||
6009 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
6010 | } | |
6011 | ||
b6b8a145 | 6012 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 6013 | { |
b6b8a145 JK |
6014 | int r; |
6015 | ||
95ba8273 | 6016 | /* try to reinject previous events if any */ |
b59bb7bd | 6017 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
6018 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
6019 | vcpu->arch.exception.has_error_code, | |
6020 | vcpu->arch.exception.error_code); | |
d6e8c854 NA |
6021 | |
6022 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) | |
6023 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
6024 | X86_EFLAGS_RF); | |
6025 | ||
6bdf0662 NA |
6026 | if (vcpu->arch.exception.nr == DB_VECTOR && |
6027 | (vcpu->arch.dr7 & DR7_GD)) { | |
6028 | vcpu->arch.dr7 &= ~DR7_GD; | |
6029 | kvm_update_dr7(vcpu); | |
6030 | } | |
6031 | ||
b59bb7bd GN |
6032 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
6033 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
6034 | vcpu->arch.exception.error_code, |
6035 | vcpu->arch.exception.reinject); | |
b6b8a145 | 6036 | return 0; |
b59bb7bd GN |
6037 | } |
6038 | ||
95ba8273 GN |
6039 | if (vcpu->arch.nmi_injected) { |
6040 | kvm_x86_ops->set_nmi(vcpu); | |
b6b8a145 | 6041 | return 0; |
95ba8273 GN |
6042 | } |
6043 | ||
6044 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 6045 | kvm_x86_ops->set_irq(vcpu); |
b6b8a145 JK |
6046 | return 0; |
6047 | } | |
6048 | ||
6049 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6050 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6051 | if (r != 0) | |
6052 | return r; | |
95ba8273 GN |
6053 | } |
6054 | ||
6055 | /* try to inject new event if pending */ | |
6056 | if (vcpu->arch.nmi_pending) { | |
6057 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 6058 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
6059 | vcpu->arch.nmi_injected = true; |
6060 | kvm_x86_ops->set_nmi(vcpu); | |
6061 | } | |
c7c9c56c | 6062 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6063 | /* |
6064 | * Because interrupts can be injected asynchronously, we are | |
6065 | * calling check_nested_events again here to avoid a race condition. | |
6066 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6067 | * proposal and current concerns. Perhaps we should be setting | |
6068 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6069 | */ | |
6070 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6071 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6072 | if (r != 0) | |
6073 | return r; | |
6074 | } | |
95ba8273 | 6075 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6076 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6077 | false); | |
6078 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6079 | } |
6080 | } | |
b6b8a145 | 6081 | return 0; |
95ba8273 GN |
6082 | } |
6083 | ||
7460fb4a AK |
6084 | static void process_nmi(struct kvm_vcpu *vcpu) |
6085 | { | |
6086 | unsigned limit = 2; | |
6087 | ||
6088 | /* | |
6089 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6090 | * If an NMI is already in progress, limit further NMIs to just one. | |
6091 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6092 | */ | |
6093 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6094 | limit = 1; | |
6095 | ||
6096 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6097 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6098 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6099 | } | |
6100 | ||
660a5d51 PB |
6101 | #define put_smstate(type, buf, offset, val) \ |
6102 | *(type *)((buf) + (offset) - 0x7e00) = val | |
6103 | ||
6104 | static u32 process_smi_get_segment_flags(struct kvm_segment *seg) | |
6105 | { | |
6106 | u32 flags = 0; | |
6107 | flags |= seg->g << 23; | |
6108 | flags |= seg->db << 22; | |
6109 | flags |= seg->l << 21; | |
6110 | flags |= seg->avl << 20; | |
6111 | flags |= seg->present << 15; | |
6112 | flags |= seg->dpl << 13; | |
6113 | flags |= seg->s << 12; | |
6114 | flags |= seg->type << 8; | |
6115 | return flags; | |
6116 | } | |
6117 | ||
6118 | static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) | |
6119 | { | |
6120 | struct kvm_segment seg; | |
6121 | int offset; | |
6122 | ||
6123 | kvm_get_segment(vcpu, &seg, n); | |
6124 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
6125 | ||
6126 | if (n < 3) | |
6127 | offset = 0x7f84 + n * 12; | |
6128 | else | |
6129 | offset = 0x7f2c + (n - 3) * 12; | |
6130 | ||
6131 | put_smstate(u32, buf, offset + 8, seg.base); | |
6132 | put_smstate(u32, buf, offset + 4, seg.limit); | |
6133 | put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); | |
6134 | } | |
6135 | ||
efbb288a | 6136 | #ifdef CONFIG_X86_64 |
660a5d51 PB |
6137 | static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
6138 | { | |
6139 | struct kvm_segment seg; | |
6140 | int offset; | |
6141 | u16 flags; | |
6142 | ||
6143 | kvm_get_segment(vcpu, &seg, n); | |
6144 | offset = 0x7e00 + n * 16; | |
6145 | ||
6146 | flags = process_smi_get_segment_flags(&seg) >> 8; | |
6147 | put_smstate(u16, buf, offset, seg.selector); | |
6148 | put_smstate(u16, buf, offset + 2, flags); | |
6149 | put_smstate(u32, buf, offset + 4, seg.limit); | |
6150 | put_smstate(u64, buf, offset + 8, seg.base); | |
6151 | } | |
efbb288a | 6152 | #endif |
660a5d51 PB |
6153 | |
6154 | static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) | |
6155 | { | |
6156 | struct desc_ptr dt; | |
6157 | struct kvm_segment seg; | |
6158 | unsigned long val; | |
6159 | int i; | |
6160 | ||
6161 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
6162 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
6163 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
6164 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
6165 | ||
6166 | for (i = 0; i < 8; i++) | |
6167 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
6168 | ||
6169 | kvm_get_dr(vcpu, 6, &val); | |
6170 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
6171 | kvm_get_dr(vcpu, 7, &val); | |
6172 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
6173 | ||
6174 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6175 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
6176 | put_smstate(u32, buf, 0x7f64, seg.base); | |
6177 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
6178 | put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); | |
6179 | ||
6180 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6181 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
6182 | put_smstate(u32, buf, 0x7f80, seg.base); | |
6183 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
6184 | put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); | |
6185 | ||
6186 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6187 | put_smstate(u32, buf, 0x7f74, dt.address); | |
6188 | put_smstate(u32, buf, 0x7f70, dt.size); | |
6189 | ||
6190 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6191 | put_smstate(u32, buf, 0x7f58, dt.address); | |
6192 | put_smstate(u32, buf, 0x7f54, dt.size); | |
6193 | ||
6194 | for (i = 0; i < 6; i++) | |
6195 | process_smi_save_seg_32(vcpu, buf, i); | |
6196 | ||
6197 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
6198 | ||
6199 | /* revision id */ | |
6200 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
6201 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
6202 | } | |
6203 | ||
6204 | static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) | |
6205 | { | |
6206 | #ifdef CONFIG_X86_64 | |
6207 | struct desc_ptr dt; | |
6208 | struct kvm_segment seg; | |
6209 | unsigned long val; | |
6210 | int i; | |
6211 | ||
6212 | for (i = 0; i < 16; i++) | |
6213 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
6214 | ||
6215 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
6216 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
6217 | ||
6218 | kvm_get_dr(vcpu, 6, &val); | |
6219 | put_smstate(u64, buf, 0x7f68, val); | |
6220 | kvm_get_dr(vcpu, 7, &val); | |
6221 | put_smstate(u64, buf, 0x7f60, val); | |
6222 | ||
6223 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
6224 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
6225 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
6226 | ||
6227 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
6228 | ||
6229 | /* revision id */ | |
6230 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
6231 | ||
6232 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
6233 | ||
6234 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
6235 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
6236 | put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); | |
6237 | put_smstate(u32, buf, 0x7e94, seg.limit); | |
6238 | put_smstate(u64, buf, 0x7e98, seg.base); | |
6239 | ||
6240 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6241 | put_smstate(u32, buf, 0x7e84, dt.size); | |
6242 | put_smstate(u64, buf, 0x7e88, dt.address); | |
6243 | ||
6244 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
6245 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
6246 | put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); | |
6247 | put_smstate(u32, buf, 0x7e74, seg.limit); | |
6248 | put_smstate(u64, buf, 0x7e78, seg.base); | |
6249 | ||
6250 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6251 | put_smstate(u32, buf, 0x7e64, dt.size); | |
6252 | put_smstate(u64, buf, 0x7e68, dt.address); | |
6253 | ||
6254 | for (i = 0; i < 6; i++) | |
6255 | process_smi_save_seg_64(vcpu, buf, i); | |
6256 | #else | |
6257 | WARN_ON_ONCE(1); | |
6258 | #endif | |
6259 | } | |
6260 | ||
64d60670 PB |
6261 | static void process_smi(struct kvm_vcpu *vcpu) |
6262 | { | |
660a5d51 | 6263 | struct kvm_segment cs, ds; |
18c3626e | 6264 | struct desc_ptr dt; |
660a5d51 PB |
6265 | char buf[512]; |
6266 | u32 cr0; | |
6267 | ||
64d60670 PB |
6268 | if (is_smm(vcpu)) { |
6269 | vcpu->arch.smi_pending = true; | |
6270 | return; | |
6271 | } | |
6272 | ||
660a5d51 PB |
6273 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
6274 | vcpu->arch.hflags |= HF_SMM_MASK; | |
6275 | memset(buf, 0, 512); | |
6276 | if (guest_cpuid_has_longmode(vcpu)) | |
6277 | process_smi_save_state_64(vcpu, buf); | |
6278 | else | |
6279 | process_smi_save_state_32(vcpu, buf); | |
6280 | ||
54bf36aa | 6281 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 PB |
6282 | |
6283 | if (kvm_x86_ops->get_nmi_mask(vcpu)) | |
6284 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
6285 | else | |
6286 | kvm_x86_ops->set_nmi_mask(vcpu, true); | |
6287 | ||
6288 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
6289 | kvm_rip_write(vcpu, 0x8000); | |
6290 | ||
6291 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
6292 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
6293 | vcpu->arch.cr0 = cr0; | |
6294 | ||
6295 | kvm_x86_ops->set_cr4(vcpu, 0); | |
6296 | ||
18c3626e PB |
6297 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
6298 | dt.address = dt.size = 0; | |
6299 | kvm_x86_ops->set_idt(vcpu, &dt); | |
6300 | ||
660a5d51 PB |
6301 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
6302 | ||
6303 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
6304 | cs.base = vcpu->arch.smbase; | |
6305 | ||
6306 | ds.selector = 0; | |
6307 | ds.base = 0; | |
6308 | ||
6309 | cs.limit = ds.limit = 0xffffffff; | |
6310 | cs.type = ds.type = 0x3; | |
6311 | cs.dpl = ds.dpl = 0; | |
6312 | cs.db = ds.db = 0; | |
6313 | cs.s = ds.s = 1; | |
6314 | cs.l = ds.l = 0; | |
6315 | cs.g = ds.g = 1; | |
6316 | cs.avl = ds.avl = 0; | |
6317 | cs.present = ds.present = 1; | |
6318 | cs.unusable = ds.unusable = 0; | |
6319 | cs.padding = ds.padding = 0; | |
6320 | ||
6321 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
6322 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
6323 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
6324 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
6325 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
6326 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
6327 | ||
6328 | if (guest_cpuid_has_longmode(vcpu)) | |
6329 | kvm_x86_ops->set_efer(vcpu, 0); | |
6330 | ||
6331 | kvm_update_cpuid(vcpu); | |
6332 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
6333 | } |
6334 | ||
3d81bc7e | 6335 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 6336 | { |
5c919412 AS |
6337 | u64 eoi_exit_bitmap[4]; |
6338 | ||
3d81bc7e YZ |
6339 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
6340 | return; | |
c7c9c56c | 6341 | |
6308630b | 6342 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 6343 | |
b053b2ae | 6344 | if (irqchip_split(vcpu->kvm)) |
6308630b | 6345 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 6346 | else { |
d62caabb AS |
6347 | if (vcpu->arch.apicv_active) |
6348 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
6308630b | 6349 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 6350 | } |
5c919412 AS |
6351 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
6352 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
6353 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); | |
c7c9c56c YZ |
6354 | } |
6355 | ||
a70656b6 RK |
6356 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) |
6357 | { | |
6358 | ++vcpu->stat.tlb_flush; | |
6359 | kvm_x86_ops->tlb_flush(vcpu); | |
6360 | } | |
6361 | ||
4256f43f TC |
6362 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
6363 | { | |
c24ae0dc TC |
6364 | struct page *page = NULL; |
6365 | ||
35754c98 | 6366 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
6367 | return; |
6368 | ||
4256f43f TC |
6369 | if (!kvm_x86_ops->set_apic_access_page_addr) |
6370 | return; | |
6371 | ||
c24ae0dc | 6372 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
6373 | if (is_error_page(page)) |
6374 | return; | |
c24ae0dc TC |
6375 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
6376 | ||
6377 | /* | |
6378 | * Do not pin apic access page in memory, the MMU notifier | |
6379 | * will call us again if it is migrated or swapped out. | |
6380 | */ | |
6381 | put_page(page); | |
4256f43f TC |
6382 | } |
6383 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
6384 | ||
fe71557a TC |
6385 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
6386 | unsigned long address) | |
6387 | { | |
c24ae0dc TC |
6388 | /* |
6389 | * The physical address of apic access page is stored in the VMCS. | |
6390 | * Update it when it becomes invalid. | |
6391 | */ | |
6392 | if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) | |
6393 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
fe71557a TC |
6394 | } |
6395 | ||
9357d939 | 6396 | /* |
362c698f | 6397 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
6398 | * exiting to the userspace. Otherwise, the value will be returned to the |
6399 | * userspace. | |
6400 | */ | |
851ba692 | 6401 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
6402 | { |
6403 | int r; | |
62a193ed MG |
6404 | bool req_int_win = |
6405 | dm_request_for_irq_injection(vcpu) && | |
6406 | kvm_cpu_accept_dm_intr(vcpu); | |
6407 | ||
730dca42 | 6408 | bool req_immediate_exit = false; |
b6c7a5dc | 6409 | |
3e007509 | 6410 | if (vcpu->requests) { |
a8eeb04a | 6411 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 6412 | kvm_mmu_unload(vcpu); |
a8eeb04a | 6413 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 6414 | __kvm_migrate_timers(vcpu); |
d828199e MT |
6415 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6416 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
6417 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
6418 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
6419 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
6420 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
6421 | if (unlikely(r)) |
6422 | goto out; | |
6423 | } | |
a8eeb04a | 6424 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 6425 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 6426 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
a70656b6 | 6427 | kvm_vcpu_flush_tlb(vcpu); |
a8eeb04a | 6428 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 6429 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
6430 | r = 0; |
6431 | goto out; | |
6432 | } | |
a8eeb04a | 6433 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 6434 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
6435 | r = 0; |
6436 | goto out; | |
6437 | } | |
a8eeb04a | 6438 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
6439 | vcpu->fpu_active = 0; |
6440 | kvm_x86_ops->fpu_deactivate(vcpu); | |
6441 | } | |
af585b92 GN |
6442 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
6443 | /* Page is swapped out. Do synthetic halt */ | |
6444 | vcpu->arch.apf.halted = true; | |
6445 | r = 1; | |
6446 | goto out; | |
6447 | } | |
c9aaa895 GC |
6448 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
6449 | record_steal_time(vcpu); | |
64d60670 PB |
6450 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
6451 | process_smi(vcpu); | |
7460fb4a AK |
6452 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
6453 | process_nmi(vcpu); | |
f5132b01 | 6454 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 6455 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 6456 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 6457 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
6458 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
6459 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
6460 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 6461 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
6462 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
6463 | vcpu->run->eoi.vector = | |
6464 | vcpu->arch.pending_ioapic_eoi; | |
6465 | r = 0; | |
6466 | goto out; | |
6467 | } | |
6468 | } | |
3d81bc7e YZ |
6469 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
6470 | vcpu_scan_ioapic(vcpu); | |
4256f43f TC |
6471 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
6472 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
6473 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
6474 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
6475 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
6476 | r = 0; | |
6477 | goto out; | |
6478 | } | |
e516cebb AS |
6479 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
6480 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
6481 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
6482 | r = 0; | |
6483 | goto out; | |
6484 | } | |
2f52d58c | 6485 | } |
b93463aa | 6486 | |
bf9f6ac8 FW |
6487 | /* |
6488 | * KVM_REQ_EVENT is not set when posted interrupts are set by | |
6489 | * VT-d hardware, so we have to update RVI unconditionally. | |
6490 | */ | |
6491 | if (kvm_lapic_enabled(vcpu)) { | |
6492 | /* | |
6493 | * Update architecture specific hints for APIC | |
6494 | * virtual interrupt delivery. | |
6495 | */ | |
d62caabb | 6496 | if (vcpu->arch.apicv_active) |
bf9f6ac8 FW |
6497 | kvm_x86_ops->hwapic_irr_update(vcpu, |
6498 | kvm_lapic_find_highest_irr(vcpu)); | |
2f52d58c | 6499 | } |
b93463aa | 6500 | |
b463a6f7 | 6501 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
6502 | kvm_apic_accept_events(vcpu); |
6503 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
6504 | r = 1; | |
6505 | goto out; | |
6506 | } | |
6507 | ||
b6b8a145 JK |
6508 | if (inject_pending_event(vcpu, req_int_win) != 0) |
6509 | req_immediate_exit = true; | |
b463a6f7 | 6510 | /* enable NMI/IRQ window open exits if needed */ |
b6b8a145 | 6511 | else if (vcpu->arch.nmi_pending) |
c9a7953f | 6512 | kvm_x86_ops->enable_nmi_window(vcpu); |
c7c9c56c | 6513 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) |
c9a7953f | 6514 | kvm_x86_ops->enable_irq_window(vcpu); |
b463a6f7 AK |
6515 | |
6516 | if (kvm_lapic_enabled(vcpu)) { | |
6517 | update_cr8_intercept(vcpu); | |
6518 | kvm_lapic_sync_to_vapic(vcpu); | |
6519 | } | |
6520 | } | |
6521 | ||
d8368af8 AK |
6522 | r = kvm_mmu_reload(vcpu); |
6523 | if (unlikely(r)) { | |
d905c069 | 6524 | goto cancel_injection; |
d8368af8 AK |
6525 | } |
6526 | ||
b6c7a5dc HB |
6527 | preempt_disable(); |
6528 | ||
6529 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
6530 | if (vcpu->fpu_active) |
6531 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 6532 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 6533 | |
6b7e2d09 XG |
6534 | vcpu->mode = IN_GUEST_MODE; |
6535 | ||
01b71917 MT |
6536 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6537 | ||
6b7e2d09 XG |
6538 | /* We should set ->mode before check ->requests, |
6539 | * see the comment in make_all_cpus_request. | |
6540 | */ | |
01b71917 | 6541 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 6542 | |
d94e1dc9 | 6543 | local_irq_disable(); |
32f88400 | 6544 | |
6b7e2d09 | 6545 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 6546 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 6547 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6548 | smp_wmb(); |
6c142801 AK |
6549 | local_irq_enable(); |
6550 | preempt_enable(); | |
01b71917 | 6551 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 6552 | r = 1; |
d905c069 | 6553 | goto cancel_injection; |
6c142801 AK |
6554 | } |
6555 | ||
d6185f20 NHE |
6556 | if (req_immediate_exit) |
6557 | smp_send_reschedule(vcpu->cpu); | |
6558 | ||
ccf73aaf | 6559 | __kvm_guest_enter(); |
b6c7a5dc | 6560 | |
42dbaa5a | 6561 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
6562 | set_debugreg(0, 7); |
6563 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
6564 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
6565 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
6566 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 6567 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 6568 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 6569 | } |
b6c7a5dc | 6570 | |
229456fc | 6571 | trace_kvm_entry(vcpu->vcpu_id); |
d0659d94 | 6572 | wait_lapic_expire(vcpu); |
851ba692 | 6573 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 6574 | |
c77fb5fe PB |
6575 | /* |
6576 | * Do this here before restoring debug registers on the host. And | |
6577 | * since we do this before handling the vmexit, a DR access vmexit | |
6578 | * can (a) read the correct value of the debug registers, (b) set | |
6579 | * KVM_DEBUGREG_WONT_EXIT again. | |
6580 | */ | |
6581 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
6582 | int i; | |
6583 | ||
6584 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); | |
6585 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
6586 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6587 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
6588 | } | |
6589 | ||
24f1e32c FW |
6590 | /* |
6591 | * If the guest has used debug registers, at least dr7 | |
6592 | * will be disabled while returning to the host. | |
6593 | * If we don't have active breakpoints in the host, we don't | |
6594 | * care about the messed up debug address registers. But if | |
6595 | * we have some of them active, restore the old state. | |
6596 | */ | |
59d8eb53 | 6597 | if (hw_breakpoint_active()) |
24f1e32c | 6598 | hw_breakpoint_restore(); |
42dbaa5a | 6599 | |
4ba76538 | 6600 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 6601 | |
6b7e2d09 | 6602 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6603 | smp_wmb(); |
a547c6db YZ |
6604 | |
6605 | /* Interrupt is enabled by handle_external_intr() */ | |
6606 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
6607 | |
6608 | ++vcpu->stat.exits; | |
6609 | ||
6610 | /* | |
6611 | * We must have an instruction between local_irq_enable() and | |
6612 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6613 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6614 | * But we need to prevent reordering, hence this barrier(): | |
6615 | */ | |
6616 | barrier(); | |
6617 | ||
6618 | kvm_guest_exit(); | |
6619 | ||
6620 | preempt_enable(); | |
6621 | ||
f656ce01 | 6622 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 6623 | |
b6c7a5dc HB |
6624 | /* |
6625 | * Profile KVM exit RIPs: | |
6626 | */ | |
6627 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
6628 | unsigned long rip = kvm_rip_read(vcpu); |
6629 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
6630 | } |
6631 | ||
cc578287 ZA |
6632 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
6633 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 6634 | |
5cfb1d5a MT |
6635 | if (vcpu->arch.apic_attention) |
6636 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 6637 | |
851ba692 | 6638 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
6639 | return r; |
6640 | ||
6641 | cancel_injection: | |
6642 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
6643 | if (unlikely(vcpu->arch.apic_attention)) |
6644 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
6645 | out: |
6646 | return r; | |
6647 | } | |
b6c7a5dc | 6648 | |
362c698f PB |
6649 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
6650 | { | |
bf9f6ac8 FW |
6651 | if (!kvm_arch_vcpu_runnable(vcpu) && |
6652 | (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { | |
9c8fd1ba PB |
6653 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
6654 | kvm_vcpu_block(vcpu); | |
6655 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 FW |
6656 | |
6657 | if (kvm_x86_ops->post_block) | |
6658 | kvm_x86_ops->post_block(vcpu); | |
6659 | ||
9c8fd1ba PB |
6660 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
6661 | return 1; | |
6662 | } | |
362c698f PB |
6663 | |
6664 | kvm_apic_accept_events(vcpu); | |
6665 | switch(vcpu->arch.mp_state) { | |
6666 | case KVM_MP_STATE_HALTED: | |
6667 | vcpu->arch.pv.pv_unhalted = false; | |
6668 | vcpu->arch.mp_state = | |
6669 | KVM_MP_STATE_RUNNABLE; | |
6670 | case KVM_MP_STATE_RUNNABLE: | |
6671 | vcpu->arch.apf.halted = false; | |
6672 | break; | |
6673 | case KVM_MP_STATE_INIT_RECEIVED: | |
6674 | break; | |
6675 | default: | |
6676 | return -EINTR; | |
6677 | break; | |
6678 | } | |
6679 | return 1; | |
6680 | } | |
09cec754 | 6681 | |
5d9bc648 PB |
6682 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
6683 | { | |
6684 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && | |
6685 | !vcpu->arch.apf.halted); | |
6686 | } | |
6687 | ||
362c698f | 6688 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
6689 | { |
6690 | int r; | |
f656ce01 | 6691 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 6692 | |
f656ce01 | 6693 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6694 | |
362c698f | 6695 | for (;;) { |
58f800d5 | 6696 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 6697 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 6698 | } else { |
362c698f | 6699 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
6700 | } |
6701 | ||
09cec754 GN |
6702 | if (r <= 0) |
6703 | break; | |
6704 | ||
6705 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6706 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6707 | kvm_inject_pending_timer_irqs(vcpu); | |
6708 | ||
782d422b MG |
6709 | if (dm_request_for_irq_injection(vcpu) && |
6710 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
6711 | r = 0; |
6712 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 6713 | ++vcpu->stat.request_irq_exits; |
362c698f | 6714 | break; |
09cec754 | 6715 | } |
af585b92 GN |
6716 | |
6717 | kvm_check_async_pf_completion(vcpu); | |
6718 | ||
09cec754 GN |
6719 | if (signal_pending(current)) { |
6720 | r = -EINTR; | |
851ba692 | 6721 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6722 | ++vcpu->stat.signal_exits; |
362c698f | 6723 | break; |
09cec754 GN |
6724 | } |
6725 | if (need_resched()) { | |
f656ce01 | 6726 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 6727 | cond_resched(); |
f656ce01 | 6728 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6729 | } |
b6c7a5dc HB |
6730 | } |
6731 | ||
f656ce01 | 6732 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
6733 | |
6734 | return r; | |
6735 | } | |
6736 | ||
716d51ab GN |
6737 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
6738 | { | |
6739 | int r; | |
6740 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6741 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6742 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6743 | if (r != EMULATE_DONE) | |
6744 | return 0; | |
6745 | return 1; | |
6746 | } | |
6747 | ||
6748 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6749 | { | |
6750 | BUG_ON(!vcpu->arch.pio.count); | |
6751 | ||
6752 | return complete_emulated_io(vcpu); | |
6753 | } | |
6754 | ||
f78146b0 AK |
6755 | /* |
6756 | * Implements the following, as a state machine: | |
6757 | * | |
6758 | * read: | |
6759 | * for each fragment | |
87da7e66 XG |
6760 | * for each mmio piece in the fragment |
6761 | * write gpa, len | |
6762 | * exit | |
6763 | * copy data | |
f78146b0 AK |
6764 | * execute insn |
6765 | * | |
6766 | * write: | |
6767 | * for each fragment | |
87da7e66 XG |
6768 | * for each mmio piece in the fragment |
6769 | * write gpa, len | |
6770 | * copy data | |
6771 | * exit | |
f78146b0 | 6772 | */ |
716d51ab | 6773 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
6774 | { |
6775 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 6776 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6777 | unsigned len; |
5287f194 | 6778 | |
716d51ab | 6779 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6780 | |
716d51ab | 6781 | /* Complete previous fragment */ |
87da7e66 XG |
6782 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6783 | len = min(8u, frag->len); | |
716d51ab | 6784 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6785 | memcpy(frag->data, run->mmio.data, len); |
6786 | ||
6787 | if (frag->len <= 8) { | |
6788 | /* Switch to the next fragment. */ | |
6789 | frag++; | |
6790 | vcpu->mmio_cur_fragment++; | |
6791 | } else { | |
6792 | /* Go forward to the next mmio piece. */ | |
6793 | frag->data += len; | |
6794 | frag->gpa += len; | |
6795 | frag->len -= len; | |
6796 | } | |
6797 | ||
a08d3b3b | 6798 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 6799 | vcpu->mmio_needed = 0; |
0912c977 PB |
6800 | |
6801 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 6802 | if (vcpu->mmio_is_write) |
716d51ab GN |
6803 | return 1; |
6804 | vcpu->mmio_read_completed = 1; | |
6805 | return complete_emulated_io(vcpu); | |
6806 | } | |
87da7e66 | 6807 | |
716d51ab GN |
6808 | run->exit_reason = KVM_EXIT_MMIO; |
6809 | run->mmio.phys_addr = frag->gpa; | |
6810 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6811 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6812 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6813 | run->mmio.is_write = vcpu->mmio_is_write; |
6814 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6815 | return 0; | |
5287f194 AK |
6816 | } |
6817 | ||
716d51ab | 6818 | |
b6c7a5dc HB |
6819 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6820 | { | |
c5bedc68 | 6821 | struct fpu *fpu = ¤t->thread.fpu; |
b6c7a5dc HB |
6822 | int r; |
6823 | sigset_t sigsaved; | |
6824 | ||
c4d72e2d | 6825 | fpu__activate_curr(fpu); |
e5c30142 | 6826 | |
ac9f6dc0 AK |
6827 | if (vcpu->sigset_active) |
6828 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6829 | ||
a4535290 | 6830 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6831 | kvm_vcpu_block(vcpu); |
66450a21 | 6832 | kvm_apic_accept_events(vcpu); |
d7690175 | 6833 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6834 | r = -EAGAIN; |
6835 | goto out; | |
b6c7a5dc HB |
6836 | } |
6837 | ||
b6c7a5dc | 6838 | /* re-sync apic's tpr */ |
35754c98 | 6839 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
6840 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
6841 | r = -EINVAL; | |
6842 | goto out; | |
6843 | } | |
6844 | } | |
b6c7a5dc | 6845 | |
716d51ab GN |
6846 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6847 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6848 | vcpu->arch.complete_userspace_io = NULL; | |
6849 | r = cui(vcpu); | |
6850 | if (r <= 0) | |
6851 | goto out; | |
6852 | } else | |
6853 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6854 | |
362c698f | 6855 | r = vcpu_run(vcpu); |
b6c7a5dc HB |
6856 | |
6857 | out: | |
f1d86e46 | 6858 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6859 | if (vcpu->sigset_active) |
6860 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6861 | ||
b6c7a5dc HB |
6862 | return r; |
6863 | } | |
6864 | ||
6865 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6866 | { | |
7ae441ea GN |
6867 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6868 | /* | |
6869 | * We are here if userspace calls get_regs() in the middle of | |
6870 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6871 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6872 | * that usually, but some bad designed PV devices (vmware |
6873 | * backdoor interface) need this to work | |
6874 | */ | |
dd856efa | 6875 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6876 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6877 | } | |
5fdbf976 MT |
6878 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6879 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6880 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6881 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6882 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6883 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6884 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6885 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6886 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6887 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6888 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6889 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6890 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6891 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6892 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6893 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6894 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6895 | #endif |
6896 | ||
5fdbf976 | 6897 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6898 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6899 | |
b6c7a5dc HB |
6900 | return 0; |
6901 | } | |
6902 | ||
6903 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6904 | { | |
7ae441ea GN |
6905 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
6906 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6907 | ||
5fdbf976 MT |
6908 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
6909 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6910 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6911 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6912 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6913 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6914 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6915 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 6916 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6917 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
6918 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6919 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6920 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6921 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6922 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6923 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6924 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
6925 | #endif |
6926 | ||
5fdbf976 | 6927 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 6928 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 6929 | |
b4f14abd JK |
6930 | vcpu->arch.exception.pending = false; |
6931 | ||
3842d135 AK |
6932 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6933 | ||
b6c7a5dc HB |
6934 | return 0; |
6935 | } | |
6936 | ||
b6c7a5dc HB |
6937 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
6938 | { | |
6939 | struct kvm_segment cs; | |
6940 | ||
3e6e0aab | 6941 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
6942 | *db = cs.db; |
6943 | *l = cs.l; | |
6944 | } | |
6945 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6946 | ||
6947 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6948 | struct kvm_sregs *sregs) | |
6949 | { | |
89a27f4d | 6950 | struct desc_ptr dt; |
b6c7a5dc | 6951 | |
3e6e0aab GT |
6952 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6953 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6954 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6955 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6956 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6957 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6958 | |
3e6e0aab GT |
6959 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6960 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
6961 | |
6962 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
6963 | sregs->idt.limit = dt.size; |
6964 | sregs->idt.base = dt.address; | |
b6c7a5dc | 6965 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
6966 | sregs->gdt.limit = dt.size; |
6967 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 6968 | |
4d4ec087 | 6969 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 6970 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 6971 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 6972 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 6973 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 6974 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
6975 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6976 | ||
923c61bb | 6977 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 6978 | |
36752c9b | 6979 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
6980 | set_bit(vcpu->arch.interrupt.nr, |
6981 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 6982 | |
b6c7a5dc HB |
6983 | return 0; |
6984 | } | |
6985 | ||
62d9f0db MT |
6986 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
6987 | struct kvm_mp_state *mp_state) | |
6988 | { | |
66450a21 | 6989 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
6990 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
6991 | vcpu->arch.pv.pv_unhalted) | |
6992 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
6993 | else | |
6994 | mp_state->mp_state = vcpu->arch.mp_state; | |
6995 | ||
62d9f0db MT |
6996 | return 0; |
6997 | } | |
6998 | ||
6999 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
7000 | struct kvm_mp_state *mp_state) | |
7001 | { | |
66450a21 JK |
7002 | if (!kvm_vcpu_has_lapic(vcpu) && |
7003 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
7004 | return -EINVAL; | |
7005 | ||
7006 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
7007 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
7008 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
7009 | } else | |
7010 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 7011 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
7012 | return 0; |
7013 | } | |
7014 | ||
7f3d35fd KW |
7015 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
7016 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 7017 | { |
9d74191a | 7018 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 7019 | int ret; |
e01c2426 | 7020 | |
8ec4722d | 7021 | init_emulate_ctxt(vcpu); |
c697518a | 7022 | |
7f3d35fd | 7023 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 7024 | has_error_code, error_code); |
c697518a | 7025 | |
c697518a | 7026 | if (ret) |
19d04437 | 7027 | return EMULATE_FAIL; |
37817f29 | 7028 | |
9d74191a TY |
7029 | kvm_rip_write(vcpu, ctxt->eip); |
7030 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 7031 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 7032 | return EMULATE_DONE; |
37817f29 IE |
7033 | } |
7034 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
7035 | ||
b6c7a5dc HB |
7036 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
7037 | struct kvm_sregs *sregs) | |
7038 | { | |
58cb628d | 7039 | struct msr_data apic_base_msr; |
b6c7a5dc | 7040 | int mmu_reset_needed = 0; |
63f42e02 | 7041 | int pending_vec, max_bits, idx; |
89a27f4d | 7042 | struct desc_ptr dt; |
b6c7a5dc | 7043 | |
6d1068b3 PM |
7044 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
7045 | return -EINVAL; | |
7046 | ||
89a27f4d GN |
7047 | dt.size = sregs->idt.limit; |
7048 | dt.address = sregs->idt.base; | |
b6c7a5dc | 7049 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
7050 | dt.size = sregs->gdt.limit; |
7051 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
7052 | kvm_x86_ops->set_gdt(vcpu, &dt); |
7053 | ||
ad312c7c | 7054 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 7055 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 7056 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 7057 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 7058 | |
2d3ad1f4 | 7059 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 7060 | |
f6801dff | 7061 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 7062 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
58cb628d JK |
7063 | apic_base_msr.data = sregs->apic_base; |
7064 | apic_base_msr.host_initiated = true; | |
7065 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
b6c7a5dc | 7066 | |
4d4ec087 | 7067 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 7068 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 7069 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 7070 | |
fc78f519 | 7071 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 7072 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 7073 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 7074 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
7075 | |
7076 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 7077 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 7078 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
7079 | mmu_reset_needed = 1; |
7080 | } | |
63f42e02 | 7081 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
7082 | |
7083 | if (mmu_reset_needed) | |
7084 | kvm_mmu_reset_context(vcpu); | |
7085 | ||
a50abc3b | 7086 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
7087 | pending_vec = find_first_bit( |
7088 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
7089 | if (pending_vec < max_bits) { | |
66fd3f7f | 7090 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 7091 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
7092 | } |
7093 | ||
3e6e0aab GT |
7094 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7095 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7096 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7097 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7098 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7099 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7100 | |
3e6e0aab GT |
7101 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7102 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 7103 | |
5f0269f5 ME |
7104 | update_cr8_intercept(vcpu); |
7105 | ||
9c3e4aab | 7106 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 7107 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 7108 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 7109 | !is_protmode(vcpu)) |
9c3e4aab MT |
7110 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7111 | ||
3842d135 AK |
7112 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
7113 | ||
b6c7a5dc HB |
7114 | return 0; |
7115 | } | |
7116 | ||
d0bfb940 JK |
7117 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
7118 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 7119 | { |
355be0b9 | 7120 | unsigned long rflags; |
ae675ef0 | 7121 | int i, r; |
b6c7a5dc | 7122 | |
4f926bf2 JK |
7123 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
7124 | r = -EBUSY; | |
7125 | if (vcpu->arch.exception.pending) | |
2122ff5e | 7126 | goto out; |
4f926bf2 JK |
7127 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
7128 | kvm_queue_exception(vcpu, DB_VECTOR); | |
7129 | else | |
7130 | kvm_queue_exception(vcpu, BP_VECTOR); | |
7131 | } | |
7132 | ||
91586a3b JK |
7133 | /* |
7134 | * Read rflags as long as potentially injected trace flags are still | |
7135 | * filtered out. | |
7136 | */ | |
7137 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
7138 | |
7139 | vcpu->guest_debug = dbg->control; | |
7140 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
7141 | vcpu->guest_debug = 0; | |
7142 | ||
7143 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
7144 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
7145 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 7146 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
7147 | } else { |
7148 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
7149 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 7150 | } |
c8639010 | 7151 | kvm_update_dr7(vcpu); |
ae675ef0 | 7152 | |
f92653ee JK |
7153 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
7154 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
7155 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 7156 | |
91586a3b JK |
7157 | /* |
7158 | * Trigger an rflags update that will inject or remove the trace | |
7159 | * flags. | |
7160 | */ | |
7161 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 7162 | |
a96036b8 | 7163 | kvm_x86_ops->update_bp_intercept(vcpu); |
b6c7a5dc | 7164 | |
4f926bf2 | 7165 | r = 0; |
d0bfb940 | 7166 | |
2122ff5e | 7167 | out: |
b6c7a5dc HB |
7168 | |
7169 | return r; | |
7170 | } | |
7171 | ||
8b006791 ZX |
7172 | /* |
7173 | * Translate a guest virtual address to a guest physical address. | |
7174 | */ | |
7175 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
7176 | struct kvm_translation *tr) | |
7177 | { | |
7178 | unsigned long vaddr = tr->linear_address; | |
7179 | gpa_t gpa; | |
f656ce01 | 7180 | int idx; |
8b006791 | 7181 | |
f656ce01 | 7182 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 7183 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 7184 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
7185 | tr->physical_address = gpa; |
7186 | tr->valid = gpa != UNMAPPED_GVA; | |
7187 | tr->writeable = 1; | |
7188 | tr->usermode = 0; | |
8b006791 ZX |
7189 | |
7190 | return 0; | |
7191 | } | |
7192 | ||
d0752060 HB |
7193 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
7194 | { | |
c47ada30 | 7195 | struct fxregs_state *fxsave = |
7366ed77 | 7196 | &vcpu->arch.guest_fpu.state.fxsave; |
d0752060 | 7197 | |
d0752060 HB |
7198 | memcpy(fpu->fpr, fxsave->st_space, 128); |
7199 | fpu->fcw = fxsave->cwd; | |
7200 | fpu->fsw = fxsave->swd; | |
7201 | fpu->ftwx = fxsave->twd; | |
7202 | fpu->last_opcode = fxsave->fop; | |
7203 | fpu->last_ip = fxsave->rip; | |
7204 | fpu->last_dp = fxsave->rdp; | |
7205 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
7206 | ||
d0752060 HB |
7207 | return 0; |
7208 | } | |
7209 | ||
7210 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
7211 | { | |
c47ada30 | 7212 | struct fxregs_state *fxsave = |
7366ed77 | 7213 | &vcpu->arch.guest_fpu.state.fxsave; |
d0752060 | 7214 | |
d0752060 HB |
7215 | memcpy(fxsave->st_space, fpu->fpr, 128); |
7216 | fxsave->cwd = fpu->fcw; | |
7217 | fxsave->swd = fpu->fsw; | |
7218 | fxsave->twd = fpu->ftwx; | |
7219 | fxsave->fop = fpu->last_opcode; | |
7220 | fxsave->rip = fpu->last_ip; | |
7221 | fxsave->rdp = fpu->last_dp; | |
7222 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
7223 | ||
d0752060 HB |
7224 | return 0; |
7225 | } | |
7226 | ||
0ee6a517 | 7227 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 7228 | { |
bf935b0b | 7229 | fpstate_init(&vcpu->arch.guest_fpu.state); |
df1daba7 | 7230 | if (cpu_has_xsaves) |
7366ed77 | 7231 | vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = |
df1daba7 | 7232 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 7233 | |
2acf923e DC |
7234 | /* |
7235 | * Ensure guest xcr0 is valid for loading | |
7236 | */ | |
d91cab78 | 7237 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 7238 | |
ad312c7c | 7239 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 7240 | } |
d0752060 HB |
7241 | |
7242 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
7243 | { | |
2608d7a1 | 7244 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
7245 | return; |
7246 | ||
2acf923e DC |
7247 | /* |
7248 | * Restore all possible states in the guest, | |
7249 | * and assume host would use all available bits. | |
7250 | * Guest xcr0 would be loaded later. | |
7251 | */ | |
7252 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 7253 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 7254 | __kernel_fpu_begin(); |
003e2e8b | 7255 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); |
0c04851c | 7256 | trace_kvm_fpu(1); |
d0752060 | 7257 | } |
d0752060 HB |
7258 | |
7259 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
7260 | { | |
2acf923e DC |
7261 | kvm_put_guest_xcr0(vcpu); |
7262 | ||
653f52c3 RR |
7263 | if (!vcpu->guest_fpu_loaded) { |
7264 | vcpu->fpu_counter = 0; | |
d0752060 | 7265 | return; |
653f52c3 | 7266 | } |
d0752060 HB |
7267 | |
7268 | vcpu->guest_fpu_loaded = 0; | |
4f836347 | 7269 | copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); |
b1a74bf8 | 7270 | __kernel_fpu_end(); |
f096ed85 | 7271 | ++vcpu->stat.fpu_reload; |
653f52c3 RR |
7272 | /* |
7273 | * If using eager FPU mode, or if the guest is a frequent user | |
7274 | * of the FPU, just leave the FPU active for next time. | |
7275 | * Every 255 times fpu_counter rolls over to 0; a guest that uses | |
7276 | * the FPU in bursts will revert to loading it on demand. | |
7277 | */ | |
a9b4fb7e | 7278 | if (!vcpu->arch.eager_fpu) { |
653f52c3 RR |
7279 | if (++vcpu->fpu_counter < 5) |
7280 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); | |
7281 | } | |
0c04851c | 7282 | trace_kvm_fpu(0); |
d0752060 | 7283 | } |
e9b11c17 ZX |
7284 | |
7285 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
7286 | { | |
12f9a48f | 7287 | kvmclock_reset(vcpu); |
7f1ea208 | 7288 | |
f5f48ee1 | 7289 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
e9b11c17 ZX |
7290 | kvm_x86_ops->vcpu_free(vcpu); |
7291 | } | |
7292 | ||
7293 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
7294 | unsigned int id) | |
7295 | { | |
c447e76b LL |
7296 | struct kvm_vcpu *vcpu; |
7297 | ||
6755bae8 ZA |
7298 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
7299 | printk_once(KERN_WARNING | |
7300 | "kvm: SMP vm created on host with unstable TSC; " | |
7301 | "guest TSC will not be reliable\n"); | |
c447e76b LL |
7302 | |
7303 | vcpu = kvm_x86_ops->vcpu_create(kvm, id); | |
7304 | ||
c447e76b | 7305 | return vcpu; |
26e5215f | 7306 | } |
e9b11c17 | 7307 | |
26e5215f AK |
7308 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
7309 | { | |
7310 | int r; | |
e9b11c17 | 7311 | |
19efffa2 | 7312 | kvm_vcpu_mtrr_init(vcpu); |
9fc77441 MT |
7313 | r = vcpu_load(vcpu); |
7314 | if (r) | |
7315 | return r; | |
d28bc9dd | 7316 | kvm_vcpu_reset(vcpu, false); |
8a3c1a33 | 7317 | kvm_mmu_setup(vcpu); |
e9b11c17 | 7318 | vcpu_put(vcpu); |
26e5215f | 7319 | return r; |
e9b11c17 ZX |
7320 | } |
7321 | ||
31928aa5 | 7322 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 7323 | { |
8fe8ab46 | 7324 | struct msr_data msr; |
332967a3 | 7325 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 7326 | |
31928aa5 DD |
7327 | if (vcpu_load(vcpu)) |
7328 | return; | |
8fe8ab46 WA |
7329 | msr.data = 0x0; |
7330 | msr.index = MSR_IA32_TSC; | |
7331 | msr.host_initiated = true; | |
7332 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
7333 | vcpu_put(vcpu); |
7334 | ||
630994b3 MT |
7335 | if (!kvmclock_periodic_sync) |
7336 | return; | |
7337 | ||
332967a3 AJ |
7338 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
7339 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
7340 | } |
7341 | ||
d40ccc62 | 7342 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 7343 | { |
9fc77441 | 7344 | int r; |
344d9588 GN |
7345 | vcpu->arch.apf.msr_val = 0; |
7346 | ||
9fc77441 MT |
7347 | r = vcpu_load(vcpu); |
7348 | BUG_ON(r); | |
e9b11c17 ZX |
7349 | kvm_mmu_unload(vcpu); |
7350 | vcpu_put(vcpu); | |
7351 | ||
7352 | kvm_x86_ops->vcpu_free(vcpu); | |
7353 | } | |
7354 | ||
d28bc9dd | 7355 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 7356 | { |
e69fab5d PB |
7357 | vcpu->arch.hflags = 0; |
7358 | ||
7460fb4a AK |
7359 | atomic_set(&vcpu->arch.nmi_queued, 0); |
7360 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 7361 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
7362 | kvm_clear_interrupt_queue(vcpu); |
7363 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 7364 | |
42dbaa5a | 7365 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 7366 | kvm_update_dr0123(vcpu); |
6f43ed01 | 7367 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 7368 | kvm_update_dr6(vcpu); |
42dbaa5a | 7369 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 7370 | kvm_update_dr7(vcpu); |
42dbaa5a | 7371 | |
1119022c NA |
7372 | vcpu->arch.cr2 = 0; |
7373 | ||
3842d135 | 7374 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 7375 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 7376 | vcpu->arch.st.msr_val = 0; |
3842d135 | 7377 | |
12f9a48f GC |
7378 | kvmclock_reset(vcpu); |
7379 | ||
af585b92 GN |
7380 | kvm_clear_async_pf_completion_queue(vcpu); |
7381 | kvm_async_pf_hash_reset(vcpu); | |
7382 | vcpu->arch.apf.halted = false; | |
3842d135 | 7383 | |
64d60670 | 7384 | if (!init_event) { |
d28bc9dd | 7385 | kvm_pmu_reset(vcpu); |
64d60670 PB |
7386 | vcpu->arch.smbase = 0x30000; |
7387 | } | |
f5132b01 | 7388 | |
66f7b72e JS |
7389 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
7390 | vcpu->arch.regs_avail = ~0; | |
7391 | vcpu->arch.regs_dirty = ~0; | |
7392 | ||
d28bc9dd | 7393 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
7394 | } |
7395 | ||
2b4a273b | 7396 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
7397 | { |
7398 | struct kvm_segment cs; | |
7399 | ||
7400 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7401 | cs.selector = vector << 8; | |
7402 | cs.base = vector << 12; | |
7403 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7404 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
7405 | } |
7406 | ||
13a34e06 | 7407 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 7408 | { |
ca84d1a2 ZA |
7409 | struct kvm *kvm; |
7410 | struct kvm_vcpu *vcpu; | |
7411 | int i; | |
0dd6a6ed ZA |
7412 | int ret; |
7413 | u64 local_tsc; | |
7414 | u64 max_tsc = 0; | |
7415 | bool stable, backwards_tsc = false; | |
18863bdd AK |
7416 | |
7417 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 7418 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
7419 | if (ret != 0) |
7420 | return ret; | |
7421 | ||
4ea1636b | 7422 | local_tsc = rdtsc(); |
0dd6a6ed ZA |
7423 | stable = !check_tsc_unstable(); |
7424 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7425 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7426 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 7427 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7428 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
7429 | backwards_tsc = true; | |
7430 | if (vcpu->arch.last_host_tsc > max_tsc) | |
7431 | max_tsc = vcpu->arch.last_host_tsc; | |
7432 | } | |
7433 | } | |
7434 | } | |
7435 | ||
7436 | /* | |
7437 | * Sometimes, even reliable TSCs go backwards. This happens on | |
7438 | * platforms that reset TSC during suspend or hibernate actions, but | |
7439 | * maintain synchronization. We must compensate. Fortunately, we can | |
7440 | * detect that condition here, which happens early in CPU bringup, | |
7441 | * before any KVM threads can be running. Unfortunately, we can't | |
7442 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
7443 | * enough into CPU bringup that we know how much real time has actually | |
7444 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
7445 | * variables that haven't been updated yet. | |
7446 | * | |
7447 | * So we simply find the maximum observed TSC above, then record the | |
7448 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
7449 | * the adjustment will be applied. Note that we accumulate | |
7450 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
7451 | * gets a chance to run again. In the event that no KVM threads get a | |
7452 | * chance to run, we will miss the entire elapsed period, as we'll have | |
7453 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
7454 | * loose cycle time. This isn't too big a deal, since the loss will be | |
7455 | * uniform across all VCPUs (not to mention the scenario is extremely | |
7456 | * unlikely). It is possible that a second hibernate recovery happens | |
7457 | * much faster than a first, causing the observed TSC here to be | |
7458 | * smaller; this would require additional padding adjustment, which is | |
7459 | * why we set last_host_tsc to the local tsc observed here. | |
7460 | * | |
7461 | * N.B. - this code below runs only on platforms with reliable TSC, | |
7462 | * as that is the only way backwards_tsc is set above. Also note | |
7463 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
7464 | * have the same delta_cyc adjustment applied if backwards_tsc | |
7465 | * is detected. Note further, this adjustment is only done once, | |
7466 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
7467 | * called multiple times (one for each physical CPU bringup). | |
7468 | * | |
4a969980 | 7469 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
7470 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
7471 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
7472 | * guarantee that they stay in perfect synchronization. | |
7473 | */ | |
7474 | if (backwards_tsc) { | |
7475 | u64 delta_cyc = max_tsc - local_tsc; | |
16a96021 | 7476 | backwards_tsc_observed = true; |
0dd6a6ed ZA |
7477 | list_for_each_entry(kvm, &vm_list, vm_list) { |
7478 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7479 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
7480 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 7481 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7482 | } |
7483 | ||
7484 | /* | |
7485 | * We have to disable TSC offset matching.. if you were | |
7486 | * booting a VM while issuing an S4 host suspend.... | |
7487 | * you may have some problem. Solving this issue is | |
7488 | * left as an exercise to the reader. | |
7489 | */ | |
7490 | kvm->arch.last_tsc_nsec = 0; | |
7491 | kvm->arch.last_tsc_write = 0; | |
7492 | } | |
7493 | ||
7494 | } | |
7495 | return 0; | |
e9b11c17 ZX |
7496 | } |
7497 | ||
13a34e06 | 7498 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 7499 | { |
13a34e06 RK |
7500 | kvm_x86_ops->hardware_disable(); |
7501 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
7502 | } |
7503 | ||
7504 | int kvm_arch_hardware_setup(void) | |
7505 | { | |
9e9c3fe4 NA |
7506 | int r; |
7507 | ||
7508 | r = kvm_x86_ops->hardware_setup(); | |
7509 | if (r != 0) | |
7510 | return r; | |
7511 | ||
35181e86 HZ |
7512 | if (kvm_has_tsc_control) { |
7513 | /* | |
7514 | * Make sure the user can only configure tsc_khz values that | |
7515 | * fit into a signed integer. | |
7516 | * A min value is not calculated needed because it will always | |
7517 | * be 1 on all machines. | |
7518 | */ | |
7519 | u64 max = min(0x7fffffffULL, | |
7520 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
7521 | kvm_max_guest_tsc_khz = max; | |
7522 | ||
ad721883 | 7523 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 7524 | } |
ad721883 | 7525 | |
9e9c3fe4 NA |
7526 | kvm_init_msr_list(); |
7527 | return 0; | |
e9b11c17 ZX |
7528 | } |
7529 | ||
7530 | void kvm_arch_hardware_unsetup(void) | |
7531 | { | |
7532 | kvm_x86_ops->hardware_unsetup(); | |
7533 | } | |
7534 | ||
7535 | void kvm_arch_check_processor_compat(void *rtn) | |
7536 | { | |
7537 | kvm_x86_ops->check_processor_compatibility(rtn); | |
d71ba788 PB |
7538 | } |
7539 | ||
7540 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
7541 | { | |
7542 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
7543 | } | |
7544 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
7545 | ||
7546 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
7547 | { | |
7548 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
7549 | } |
7550 | ||
3e515705 AK |
7551 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
7552 | { | |
35754c98 | 7553 | return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu); |
3e515705 AK |
7554 | } |
7555 | ||
54e9818f GN |
7556 | struct static_key kvm_no_apic_vcpu __read_mostly; |
7557 | ||
e9b11c17 ZX |
7558 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
7559 | { | |
7560 | struct page *page; | |
7561 | struct kvm *kvm; | |
7562 | int r; | |
7563 | ||
7564 | BUG_ON(vcpu->kvm == NULL); | |
7565 | kvm = vcpu->kvm; | |
7566 | ||
d62caabb | 7567 | vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(); |
6aef266c | 7568 | vcpu->arch.pv.pv_unhalted = false; |
9aabc88f | 7569 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
58d269d8 | 7570 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 7571 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 7572 | else |
a4535290 | 7573 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
7574 | |
7575 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
7576 | if (!page) { | |
7577 | r = -ENOMEM; | |
7578 | goto fail; | |
7579 | } | |
ad312c7c | 7580 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 7581 | |
cc578287 | 7582 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 7583 | |
e9b11c17 ZX |
7584 | r = kvm_mmu_create(vcpu); |
7585 | if (r < 0) | |
7586 | goto fail_free_pio_data; | |
7587 | ||
7588 | if (irqchip_in_kernel(kvm)) { | |
7589 | r = kvm_create_lapic(vcpu); | |
7590 | if (r < 0) | |
7591 | goto fail_mmu_destroy; | |
54e9818f GN |
7592 | } else |
7593 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 7594 | |
890ca9ae HY |
7595 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
7596 | GFP_KERNEL); | |
7597 | if (!vcpu->arch.mce_banks) { | |
7598 | r = -ENOMEM; | |
443c39bc | 7599 | goto fail_free_lapic; |
890ca9ae HY |
7600 | } |
7601 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
7602 | ||
f1797359 WY |
7603 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
7604 | r = -ENOMEM; | |
f5f48ee1 | 7605 | goto fail_free_mce_banks; |
f1797359 | 7606 | } |
f5f48ee1 | 7607 | |
0ee6a517 | 7608 | fx_init(vcpu); |
66f7b72e | 7609 | |
ba904635 | 7610 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 7611 | vcpu->arch.pv_time_enabled = false; |
d7876f1b PB |
7612 | |
7613 | vcpu->arch.guest_supported_xcr0 = 0; | |
4344ee98 | 7614 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 7615 | |
5a4f55cd EK |
7616 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
7617 | ||
74545705 RK |
7618 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; |
7619 | ||
af585b92 | 7620 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 7621 | kvm_pmu_init(vcpu); |
af585b92 | 7622 | |
1c1a9ce9 SR |
7623 | vcpu->arch.pending_external_vector = -1; |
7624 | ||
5c919412 AS |
7625 | kvm_hv_vcpu_init(vcpu); |
7626 | ||
e9b11c17 | 7627 | return 0; |
0ee6a517 | 7628 | |
f5f48ee1 SY |
7629 | fail_free_mce_banks: |
7630 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
7631 | fail_free_lapic: |
7632 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
7633 | fail_mmu_destroy: |
7634 | kvm_mmu_destroy(vcpu); | |
7635 | fail_free_pio_data: | |
ad312c7c | 7636 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
7637 | fail: |
7638 | return r; | |
7639 | } | |
7640 | ||
7641 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
7642 | { | |
f656ce01 MT |
7643 | int idx; |
7644 | ||
f5132b01 | 7645 | kvm_pmu_destroy(vcpu); |
36cb93fd | 7646 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 7647 | kvm_free_lapic(vcpu); |
f656ce01 | 7648 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 7649 | kvm_mmu_destroy(vcpu); |
f656ce01 | 7650 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 7651 | free_page((unsigned long)vcpu->arch.pio_data); |
35754c98 | 7652 | if (!lapic_in_kernel(vcpu)) |
54e9818f | 7653 | static_key_slow_dec(&kvm_no_apic_vcpu); |
e9b11c17 | 7654 | } |
d19a9cd2 | 7655 | |
e790d9ef RK |
7656 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
7657 | { | |
ae97a3b8 | 7658 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
7659 | } |
7660 | ||
e08b9637 | 7661 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 7662 | { |
e08b9637 CO |
7663 | if (type) |
7664 | return -EINVAL; | |
7665 | ||
6ef768fa | 7666 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 7667 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 7668 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 7669 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 7670 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 7671 | |
5550af4d SY |
7672 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
7673 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
7674 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
7675 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7676 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 7677 | |
038f8c11 | 7678 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 7679 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
7680 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
7681 | ||
7682 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 7683 | |
7e44e449 | 7684 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 7685 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 7686 | |
d89f5eff | 7687 | return 0; |
d19a9cd2 ZX |
7688 | } |
7689 | ||
7690 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7691 | { | |
9fc77441 MT |
7692 | int r; |
7693 | r = vcpu_load(vcpu); | |
7694 | BUG_ON(r); | |
d19a9cd2 ZX |
7695 | kvm_mmu_unload(vcpu); |
7696 | vcpu_put(vcpu); | |
7697 | } | |
7698 | ||
7699 | static void kvm_free_vcpus(struct kvm *kvm) | |
7700 | { | |
7701 | unsigned int i; | |
988a2cae | 7702 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
7703 | |
7704 | /* | |
7705 | * Unpin any mmu pages first. | |
7706 | */ | |
af585b92 GN |
7707 | kvm_for_each_vcpu(i, vcpu, kvm) { |
7708 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 7709 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 7710 | } |
988a2cae GN |
7711 | kvm_for_each_vcpu(i, vcpu, kvm) |
7712 | kvm_arch_vcpu_free(vcpu); | |
7713 | ||
7714 | mutex_lock(&kvm->lock); | |
7715 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7716 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 7717 | |
988a2cae GN |
7718 | atomic_set(&kvm->online_vcpus, 0); |
7719 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
7720 | } |
7721 | ||
ad8ba2cd SY |
7722 | void kvm_arch_sync_events(struct kvm *kvm) |
7723 | { | |
332967a3 | 7724 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 7725 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
ba4cef31 | 7726 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 7727 | kvm_free_pit(kvm); |
ad8ba2cd SY |
7728 | } |
7729 | ||
1d8007bd | 7730 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
7731 | { |
7732 | int i, r; | |
25188b99 | 7733 | unsigned long hva; |
f0d648bd PB |
7734 | struct kvm_memslots *slots = kvm_memslots(kvm); |
7735 | struct kvm_memory_slot *slot, old; | |
9da0e4d5 PB |
7736 | |
7737 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
7738 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
7739 | return -EINVAL; | |
9da0e4d5 | 7740 | |
f0d648bd PB |
7741 | slot = id_to_memslot(slots, id); |
7742 | if (size) { | |
7743 | if (WARN_ON(slot->npages)) | |
7744 | return -EEXIST; | |
7745 | ||
7746 | /* | |
7747 | * MAP_SHARED to prevent internal slot pages from being moved | |
7748 | * by fork()/COW. | |
7749 | */ | |
7750 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
7751 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
7752 | if (IS_ERR((void *)hva)) | |
7753 | return PTR_ERR((void *)hva); | |
7754 | } else { | |
7755 | if (!slot->npages) | |
7756 | return 0; | |
7757 | ||
7758 | hva = 0; | |
7759 | } | |
7760 | ||
7761 | old = *slot; | |
9da0e4d5 | 7762 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 7763 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 7764 | |
1d8007bd PB |
7765 | m.slot = id | (i << 16); |
7766 | m.flags = 0; | |
7767 | m.guest_phys_addr = gpa; | |
f0d648bd | 7768 | m.userspace_addr = hva; |
1d8007bd | 7769 | m.memory_size = size; |
9da0e4d5 PB |
7770 | r = __kvm_set_memory_region(kvm, &m); |
7771 | if (r < 0) | |
7772 | return r; | |
7773 | } | |
7774 | ||
f0d648bd PB |
7775 | if (!size) { |
7776 | r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); | |
7777 | WARN_ON(r < 0); | |
7778 | } | |
7779 | ||
9da0e4d5 PB |
7780 | return 0; |
7781 | } | |
7782 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
7783 | ||
1d8007bd | 7784 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
7785 | { |
7786 | int r; | |
7787 | ||
7788 | mutex_lock(&kvm->slots_lock); | |
1d8007bd | 7789 | r = __x86_set_memory_region(kvm, id, gpa, size); |
9da0e4d5 PB |
7790 | mutex_unlock(&kvm->slots_lock); |
7791 | ||
7792 | return r; | |
7793 | } | |
7794 | EXPORT_SYMBOL_GPL(x86_set_memory_region); | |
7795 | ||
d19a9cd2 ZX |
7796 | void kvm_arch_destroy_vm(struct kvm *kvm) |
7797 | { | |
27469d29 AH |
7798 | if (current->mm == kvm->mm) { |
7799 | /* | |
7800 | * Free memory regions allocated on behalf of userspace, | |
7801 | * unless the the memory map has changed due to process exit | |
7802 | * or fd copying. | |
7803 | */ | |
1d8007bd PB |
7804 | x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); |
7805 | x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); | |
7806 | x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
27469d29 | 7807 | } |
6eb55818 | 7808 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
7809 | kfree(kvm->arch.vpic); |
7810 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 7811 | kvm_free_vcpus(kvm); |
1e08ec4a | 7812 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 7813 | } |
0de10343 | 7814 | |
5587027c | 7815 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
7816 | struct kvm_memory_slot *dont) |
7817 | { | |
7818 | int i; | |
7819 | ||
d89cc617 TY |
7820 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7821 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 7822 | kvfree(free->arch.rmap[i]); |
d89cc617 | 7823 | free->arch.rmap[i] = NULL; |
77d11309 | 7824 | } |
d89cc617 TY |
7825 | if (i == 0) |
7826 | continue; | |
7827 | ||
7828 | if (!dont || free->arch.lpage_info[i - 1] != | |
7829 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 7830 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 7831 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7832 | } |
7833 | } | |
7834 | } | |
7835 | ||
5587027c AK |
7836 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
7837 | unsigned long npages) | |
db3fe4eb TY |
7838 | { |
7839 | int i; | |
7840 | ||
d89cc617 | 7841 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
7842 | unsigned long ugfn; |
7843 | int lpages; | |
d89cc617 | 7844 | int level = i + 1; |
db3fe4eb TY |
7845 | |
7846 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7847 | slot->base_gfn, level) + 1; | |
7848 | ||
d89cc617 TY |
7849 | slot->arch.rmap[i] = |
7850 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7851 | if (!slot->arch.rmap[i]) | |
77d11309 | 7852 | goto out_free; |
d89cc617 TY |
7853 | if (i == 0) |
7854 | continue; | |
77d11309 | 7855 | |
d89cc617 TY |
7856 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
7857 | sizeof(*slot->arch.lpage_info[i - 1])); | |
7858 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
7859 | goto out_free; |
7860 | ||
7861 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 7862 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 7863 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 7864 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
7865 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
7866 | /* | |
7867 | * If the gfn and userspace address are not aligned wrt each | |
7868 | * other, or if explicitly asked to, disable large page | |
7869 | * support for this slot | |
7870 | */ | |
7871 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7872 | !kvm_largepages_enabled()) { | |
7873 | unsigned long j; | |
7874 | ||
7875 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 7876 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
7877 | } |
7878 | } | |
7879 | ||
7880 | return 0; | |
7881 | ||
7882 | out_free: | |
d89cc617 | 7883 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 7884 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
7885 | slot->arch.rmap[i] = NULL; |
7886 | if (i == 0) | |
7887 | continue; | |
7888 | ||
548ef284 | 7889 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 7890 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7891 | } |
7892 | return -ENOMEM; | |
7893 | } | |
7894 | ||
15f46015 | 7895 | void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) |
e59dbe09 | 7896 | { |
e6dff7d1 TY |
7897 | /* |
7898 | * memslots->generation has been incremented. | |
7899 | * mmio generation may have reached its maximum value. | |
7900 | */ | |
54bf36aa | 7901 | kvm_mmu_invalidate_mmio_sptes(kvm, slots); |
e59dbe09 TY |
7902 | } |
7903 | ||
f7784b8e MT |
7904 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
7905 | struct kvm_memory_slot *memslot, | |
09170a49 | 7906 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 7907 | enum kvm_mr_change change) |
0de10343 | 7908 | { |
f7784b8e MT |
7909 | return 0; |
7910 | } | |
7911 | ||
88178fd4 KH |
7912 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
7913 | struct kvm_memory_slot *new) | |
7914 | { | |
7915 | /* Still write protect RO slot */ | |
7916 | if (new->flags & KVM_MEM_READONLY) { | |
7917 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7918 | return; | |
7919 | } | |
7920 | ||
7921 | /* | |
7922 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
7923 | * | |
7924 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
7925 | * | |
7926 | * - KVM_MR_CREATE with dirty logging is disabled | |
7927 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
7928 | * | |
7929 | * The reason is, in case of PML, we need to set D-bit for any slots | |
7930 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
7931 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
7932 | * guarantees leaving PML enabled during guest's lifetime won't have | |
7933 | * any additonal overhead from PML when guest is running with dirty | |
7934 | * logging disabled for memory slots. | |
7935 | * | |
7936 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
7937 | * to dirty logging mode. | |
7938 | * | |
7939 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
7940 | * | |
7941 | * In case of write protect: | |
7942 | * | |
7943 | * Write protect all pages for dirty logging. | |
7944 | * | |
7945 | * All the sptes including the large sptes which point to this | |
7946 | * slot are set to readonly. We can not create any new large | |
7947 | * spte on this slot until the end of the logging. | |
7948 | * | |
7949 | * See the comments in fast_page_fault(). | |
7950 | */ | |
7951 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
7952 | if (kvm_x86_ops->slot_enable_log_dirty) | |
7953 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
7954 | else | |
7955 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7956 | } else { | |
7957 | if (kvm_x86_ops->slot_disable_log_dirty) | |
7958 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
7959 | } | |
7960 | } | |
7961 | ||
f7784b8e | 7962 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 7963 | const struct kvm_userspace_memory_region *mem, |
8482644a | 7964 | const struct kvm_memory_slot *old, |
f36f3f28 | 7965 | const struct kvm_memory_slot *new, |
8482644a | 7966 | enum kvm_mr_change change) |
f7784b8e | 7967 | { |
8482644a | 7968 | int nr_mmu_pages = 0; |
f7784b8e | 7969 | |
48c0e4e9 XG |
7970 | if (!kvm->arch.n_requested_mmu_pages) |
7971 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
7972 | ||
48c0e4e9 | 7973 | if (nr_mmu_pages) |
0de10343 | 7974 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
1c91cad4 | 7975 | |
3ea3b7fa WL |
7976 | /* |
7977 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
7978 | * sptes have to be split. If live migration is successful, the guest | |
7979 | * in the source machine will be destroyed and large sptes will be | |
7980 | * created in the destination. However, if the guest continues to run | |
7981 | * in the source machine (for example if live migration fails), small | |
7982 | * sptes will remain around and cause bad performance. | |
7983 | * | |
7984 | * Scan sptes if dirty logging has been stopped, dropping those | |
7985 | * which can be collapsed into a single large-page spte. Later | |
7986 | * page faults will create the large-page sptes. | |
7987 | */ | |
7988 | if ((change != KVM_MR_DELETE) && | |
7989 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
7990 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
7991 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
7992 | ||
c972f3b1 | 7993 | /* |
88178fd4 | 7994 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 7995 | * |
88178fd4 KH |
7996 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
7997 | * been zapped so no dirty logging staff is needed for old slot. For | |
7998 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
7999 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
8000 | * |
8001 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 8002 | */ |
88178fd4 | 8003 | if (change != KVM_MR_DELETE) |
f36f3f28 | 8004 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 8005 | } |
1d737c8a | 8006 | |
2df72e9b | 8007 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 8008 | { |
6ca18b69 | 8009 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
8010 | } |
8011 | ||
2df72e9b MT |
8012 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
8013 | struct kvm_memory_slot *slot) | |
8014 | { | |
6ca18b69 | 8015 | kvm_mmu_invalidate_zap_all_pages(kvm); |
2df72e9b MT |
8016 | } |
8017 | ||
5d9bc648 PB |
8018 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
8019 | { | |
8020 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
8021 | return true; | |
8022 | ||
8023 | if (kvm_apic_has_events(vcpu)) | |
8024 | return true; | |
8025 | ||
8026 | if (vcpu->arch.pv.pv_unhalted) | |
8027 | return true; | |
8028 | ||
8029 | if (atomic_read(&vcpu->arch.nmi_queued)) | |
8030 | return true; | |
8031 | ||
73917739 PB |
8032 | if (test_bit(KVM_REQ_SMI, &vcpu->requests)) |
8033 | return true; | |
8034 | ||
5d9bc648 PB |
8035 | if (kvm_arch_interrupt_allowed(vcpu) && |
8036 | kvm_cpu_has_interrupt(vcpu)) | |
8037 | return true; | |
8038 | ||
8039 | return false; | |
8040 | } | |
8041 | ||
1d737c8a ZX |
8042 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
8043 | { | |
b6b8a145 JK |
8044 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
8045 | kvm_x86_ops->check_nested_events(vcpu, false); | |
8046 | ||
5d9bc648 | 8047 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 8048 | } |
5736199a | 8049 | |
b6d33834 | 8050 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 8051 | { |
b6d33834 | 8052 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 8053 | } |
78646121 GN |
8054 | |
8055 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
8056 | { | |
8057 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
8058 | } | |
229456fc | 8059 | |
82b32774 | 8060 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 8061 | { |
82b32774 NA |
8062 | if (is_64_bit_mode(vcpu)) |
8063 | return kvm_rip_read(vcpu); | |
8064 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
8065 | kvm_rip_read(vcpu)); | |
8066 | } | |
8067 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 8068 | |
82b32774 NA |
8069 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
8070 | { | |
8071 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
8072 | } |
8073 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
8074 | ||
94fe45da JK |
8075 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
8076 | { | |
8077 | unsigned long rflags; | |
8078 | ||
8079 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
8080 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 8081 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
8082 | return rflags; |
8083 | } | |
8084 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
8085 | ||
6addfc42 | 8086 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
8087 | { |
8088 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 8089 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 8090 | rflags |= X86_EFLAGS_TF; |
94fe45da | 8091 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
8092 | } |
8093 | ||
8094 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
8095 | { | |
8096 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 8097 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
8098 | } |
8099 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
8100 | ||
56028d08 GN |
8101 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
8102 | { | |
8103 | int r; | |
8104 | ||
fb67e14f | 8105 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 8106 | work->wakeup_all) |
56028d08 GN |
8107 | return; |
8108 | ||
8109 | r = kvm_mmu_reload(vcpu); | |
8110 | if (unlikely(r)) | |
8111 | return; | |
8112 | ||
fb67e14f XG |
8113 | if (!vcpu->arch.mmu.direct_map && |
8114 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
8115 | return; | |
8116 | ||
56028d08 GN |
8117 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
8118 | } | |
8119 | ||
af585b92 GN |
8120 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
8121 | { | |
8122 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
8123 | } | |
8124 | ||
8125 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
8126 | { | |
8127 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
8128 | } | |
8129 | ||
8130 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8131 | { | |
8132 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8133 | ||
8134 | while (vcpu->arch.apf.gfns[key] != ~0) | |
8135 | key = kvm_async_pf_next_probe(key); | |
8136 | ||
8137 | vcpu->arch.apf.gfns[key] = gfn; | |
8138 | } | |
8139 | ||
8140 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8141 | { | |
8142 | int i; | |
8143 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8144 | ||
8145 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
8146 | (vcpu->arch.apf.gfns[key] != gfn && |
8147 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
8148 | key = kvm_async_pf_next_probe(key); |
8149 | ||
8150 | return key; | |
8151 | } | |
8152 | ||
8153 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8154 | { | |
8155 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
8156 | } | |
8157 | ||
8158 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8159 | { | |
8160 | u32 i, j, k; | |
8161 | ||
8162 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
8163 | while (true) { | |
8164 | vcpu->arch.apf.gfns[i] = ~0; | |
8165 | do { | |
8166 | j = kvm_async_pf_next_probe(j); | |
8167 | if (vcpu->arch.apf.gfns[j] == ~0) | |
8168 | return; | |
8169 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
8170 | /* | |
8171 | * k lies cyclically in ]i,j] | |
8172 | * | i.k.j | | |
8173 | * |....j i.k.| or |.k..j i...| | |
8174 | */ | |
8175 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
8176 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
8177 | i = j; | |
8178 | } | |
8179 | } | |
8180 | ||
7c90705b GN |
8181 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
8182 | { | |
8183 | ||
8184 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
8185 | sizeof(val)); | |
8186 | } | |
8187 | ||
af585b92 GN |
8188 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
8189 | struct kvm_async_pf *work) | |
8190 | { | |
6389ee94 AK |
8191 | struct x86_exception fault; |
8192 | ||
7c90705b | 8193 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 8194 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
8195 | |
8196 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
8197 | (vcpu->arch.apf.send_user_only && |
8198 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
8199 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
8200 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
8201 | fault.vector = PF_VECTOR; |
8202 | fault.error_code_valid = true; | |
8203 | fault.error_code = 0; | |
8204 | fault.nested_page_fault = false; | |
8205 | fault.address = work->arch.token; | |
8206 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8207 | } |
af585b92 GN |
8208 | } |
8209 | ||
8210 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
8211 | struct kvm_async_pf *work) | |
8212 | { | |
6389ee94 AK |
8213 | struct x86_exception fault; |
8214 | ||
7c90705b | 8215 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
f2e10669 | 8216 | if (work->wakeup_all) |
7c90705b GN |
8217 | work->arch.token = ~0; /* broadcast wakeup */ |
8218 | else | |
8219 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
8220 | ||
8221 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
8222 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
8223 | fault.vector = PF_VECTOR; |
8224 | fault.error_code_valid = true; | |
8225 | fault.error_code = 0; | |
8226 | fault.nested_page_fault = false; | |
8227 | fault.address = work->arch.token; | |
8228 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8229 | } |
e6d53e3b | 8230 | vcpu->arch.apf.halted = false; |
a4fa1635 | 8231 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
8232 | } |
8233 | ||
8234 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
8235 | { | |
8236 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
8237 | return true; | |
8238 | else | |
8239 | return !kvm_event_needs_reinjection(vcpu) && | |
8240 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
8241 | } |
8242 | ||
5544eb9b PB |
8243 | void kvm_arch_start_assignment(struct kvm *kvm) |
8244 | { | |
8245 | atomic_inc(&kvm->arch.assigned_device_count); | |
8246 | } | |
8247 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
8248 | ||
8249 | void kvm_arch_end_assignment(struct kvm *kvm) | |
8250 | { | |
8251 | atomic_dec(&kvm->arch.assigned_device_count); | |
8252 | } | |
8253 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
8254 | ||
8255 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
8256 | { | |
8257 | return atomic_read(&kvm->arch.assigned_device_count); | |
8258 | } | |
8259 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
8260 | ||
e0f0bbc5 AW |
8261 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
8262 | { | |
8263 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
8264 | } | |
8265 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
8266 | ||
8267 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
8268 | { | |
8269 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
8270 | } | |
8271 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
8272 | ||
8273 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
8274 | { | |
8275 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
8276 | } | |
8277 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
8278 | ||
87276880 FW |
8279 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
8280 | struct irq_bypass_producer *prod) | |
8281 | { | |
8282 | struct kvm_kernel_irqfd *irqfd = | |
8283 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
8284 | ||
8285 | if (kvm_x86_ops->update_pi_irte) { | |
8286 | irqfd->producer = prod; | |
8287 | return kvm_x86_ops->update_pi_irte(irqfd->kvm, | |
8288 | prod->irq, irqfd->gsi, 1); | |
8289 | } | |
8290 | ||
8291 | return -EINVAL; | |
8292 | } | |
8293 | ||
8294 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
8295 | struct irq_bypass_producer *prod) | |
8296 | { | |
8297 | int ret; | |
8298 | struct kvm_kernel_irqfd *irqfd = | |
8299 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
8300 | ||
8301 | if (!kvm_x86_ops->update_pi_irte) { | |
8302 | WARN_ON(irqfd->producer != NULL); | |
8303 | return; | |
8304 | } | |
8305 | ||
8306 | WARN_ON(irqfd->producer != prod); | |
8307 | irqfd->producer = NULL; | |
8308 | ||
8309 | /* | |
8310 | * When producer of consumer is unregistered, we change back to | |
8311 | * remapped mode, so we can re-use the current implementation | |
8312 | * when the irq is masked/disabed or the consumer side (KVM | |
8313 | * int this case doesn't want to receive the interrupts. | |
8314 | */ | |
8315 | ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); | |
8316 | if (ret) | |
8317 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
8318 | " fails: %d\n", irqfd->consumer.token, ret); | |
8319 | } | |
8320 | ||
8321 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
8322 | uint32_t guest_irq, bool set) | |
8323 | { | |
8324 | if (!kvm_x86_ops->update_pi_irte) | |
8325 | return -EINVAL; | |
8326 | ||
8327 | return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); | |
8328 | } | |
8329 | ||
229456fc | 8330 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 8331 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
8332 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
8333 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
8334 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
8335 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 8336 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 8337 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 8338 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 8339 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 8340 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 8341 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 8342 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 8343 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 8344 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 8345 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 8346 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |