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KVM: x86: pass host_initiated to functions that read MSRs
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 225 if (slot >= shared_msrs_global.nr)
226 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 227 shared_msrs_global.msrs[slot] = msr;
228 /* we need ensured the shared_msr_global have been updated */
229 smp_wmb();
18863bdd
AK		 230}
231EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
232
233static void kvm_shared_msr_cpu_online(void)
234{
235 unsigned i;
18863bdd
AK		 236
237 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 238 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 239}
240
8b3c3104 241int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 242{
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 245 int err;
18863bdd 246
2bf78fa7 247 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 248 return 0;
2bf78fa7 249 smsr->values[slot].curr = value;
8b3c3104
AH		 250 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
251 if (err)
252 return 1;
253
18863bdd
AK		 254 if (!smsr->registered) {
255 smsr->urn.on_user_return = kvm_on_user_return;
256 user_return_notifier_register(&smsr->urn);
257 smsr->registered = true;
258 }
8b3c3104 259 return 0;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
262
13a34e06 263static void drop_user_return_notifiers(void)
3548bab5 264{
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 267
268 if (smsr->registered)
269 kvm_on_user_return(&smsr->urn);
270}
271
6866b83e
CO		 272u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
273{
8a5a87d9 274 return vcpu->arch.apic_base;
6866b83e
CO		 275}
276EXPORT_SYMBOL_GPL(kvm_get_apic_base);
277
58cb628d
JK		 278int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
279{
280 u64 old_state = vcpu->arch.apic_base &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 new_state = msr_info->data &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
285 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
286
287 if (!msr_info->host_initiated &&
288 ((msr_info->data & reserved_bits) != 0 ||
289 new_state == X2APIC_ENABLE ||
290 (new_state == MSR_IA32_APICBASE_ENABLE &&
291 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
292 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
293 old_state == 0)))
294 return 1;
295
296 kvm_lapic_set_base(vcpu, msr_info->data);
297 return 0;
6866b83e
CO		 298}
299EXPORT_SYMBOL_GPL(kvm_set_apic_base);
300
2605fc21 301asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 302{
303 /* Fault while not rebooting. We want the trace. */
304 BUG();
305}
306EXPORT_SYMBOL_GPL(kvm_spurious_fault);
307
3fd28fce
ED		 308#define EXCPT_BENIGN 0
309#define EXCPT_CONTRIBUTORY 1
310#define EXCPT_PF 2
311
312static int exception_class(int vector)
313{
314 switch (vector) {
315 case PF_VECTOR:
316 return EXCPT_PF;
317 case DE_VECTOR:
318 case TS_VECTOR:
319 case NP_VECTOR:
320 case SS_VECTOR:
321 case GP_VECTOR:
322 return EXCPT_CONTRIBUTORY;
323 default:
324 break;
325 }
326 return EXCPT_BENIGN;
327}
328
d6e8c854
NA		 329#define EXCPT_FAULT 0
330#define EXCPT_TRAP 1
331#define EXCPT_ABORT 2
332#define EXCPT_INTERRUPT 3
333
334static int exception_type(int vector)
335{
336 unsigned int mask;
337
338 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
339 return EXCPT_INTERRUPT;
340
341 mask = 1 << vector;
342
343 /* #DB is trap, as instruction watchpoints are handled elsewhere */
344 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
345 return EXCPT_TRAP;
346
347 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
348 return EXCPT_ABORT;
349
350 /* Reserved exceptions will result in fault */
351 return EXCPT_FAULT;
352}
353
3fd28fce 354static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 355 unsigned nr, bool has_error, u32 error_code,
356 bool reinject)
3fd28fce
ED		 357{
358 u32 prev_nr;
359 int class1, class2;
360
3842d135
AK		 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
362
3fd28fce
ED		 363 if (!vcpu->arch.exception.pending) {
364 queue:
3ffb2468
NA		 365 if (has_error && !is_protmode(vcpu))
366 has_error = false;
3fd28fce
ED		 367 vcpu->arch.exception.pending = true;
368 vcpu->arch.exception.has_error_code = has_error;
369 vcpu->arch.exception.nr = nr;
370 vcpu->arch.exception.error_code = error_code;
3f0fd292 371 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 372 return;
373 }
374
375 /* to check exception */
376 prev_nr = vcpu->arch.exception.nr;
377 if (prev_nr == DF_VECTOR) {
378 /* triple fault -> shutdown */
a8eeb04a 379 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 380 return;
381 }
382 class1 = exception_class(prev_nr);
383 class2 = exception_class(nr);
384 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
385 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
386 /* generate double fault per SDM Table 5-5 */
387 vcpu->arch.exception.pending = true;
388 vcpu->arch.exception.has_error_code = true;
389 vcpu->arch.exception.nr = DF_VECTOR;
390 vcpu->arch.exception.error_code = 0;
391 } else
392 /* replace previous exception with a new one in a hope
393 that instruction re-execution will regenerate lost
394 exception */
395 goto queue;
396}
397
298101da
AK		 398void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
399{
ce7ddec4 400 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 401}
402EXPORT_SYMBOL_GPL(kvm_queue_exception);
403
ce7ddec4
JR		 404void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
405{
406 kvm_multiple_exception(vcpu, nr, false, 0, true);
407}
408EXPORT_SYMBOL_GPL(kvm_requeue_exception);
409
db8fcefa 410void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 411{
db8fcefa
AP		 412 if (err)
413 kvm_inject_gp(vcpu, 0);
414 else
415 kvm_x86_ops->skip_emulated_instruction(vcpu);
416}
417EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 418
6389ee94 419void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 420{
421 ++vcpu->stat.pf_guest;
6389ee94
AK		 422 vcpu->arch.cr2 = fault->address;
423 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 424}
27d6c865 425EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 426
ef54bcfe 427static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 428{
6389ee94
AK		 429 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
430 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 431 else
6389ee94 432 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 433
434 return fault->nested_page_fault;
d4f8cf66
JR		 435}
436
3419ffc8
SY		 437void kvm_inject_nmi(struct kvm_vcpu *vcpu)
438{
7460fb4a
AK		 439 atomic_inc(&vcpu->arch.nmi_queued);
440 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 441}
442EXPORT_SYMBOL_GPL(kvm_inject_nmi);
443
298101da
AK		 444void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
445{
ce7ddec4 446 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 447}
448EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
449
ce7ddec4
JR		 450void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
451{
452 kvm_multiple_exception(vcpu, nr, true, error_code, true);
453}
454EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
455
0a79b009
AK		 456/*
457 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
458 * a #GP and return false.
459 */
460bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 461{
0a79b009
AK		 462 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
463 return true;
464 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
465 return false;
298101da 466}
0a79b009 467EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 468
16f8a6f9
NA		 469bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
470{
471 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
472 return true;
473
474 kvm_queue_exception(vcpu, UD_VECTOR);
475 return false;
476}
477EXPORT_SYMBOL_GPL(kvm_require_dr);
478
ec92fe44
JR		 479/*
480 * This function will be used to read from the physical memory of the currently
481 * running guest. The difference to kvm_read_guest_page is that this function
482 * can read from guest physical or from the guest's guest physical memory.
483 */
484int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
485 gfn_t ngfn, void *data, int offset, int len,
486 u32 access)
487{
54987b7a 488 struct x86_exception exception;
ec92fe44
JR		 489 gfn_t real_gfn;
490 gpa_t ngpa;
491
492 ngpa = gfn_to_gpa(ngfn);
54987b7a 493 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 494 if (real_gfn == UNMAPPED_GVA)
495 return -EFAULT;
496
497 real_gfn = gpa_to_gfn(real_gfn);
498
499 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
500}
501EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
502
69b0049a 503static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 504 void *data, int offset, int len, u32 access)
505{
506 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
507 data, offset, len, access);
508}
509
a03490ed
CO		 510/*
511 * Load the pae pdptrs. Return true is they are all valid.
512 */
ff03a073 513int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 514{
515 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
516 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
517 int i;
518 int ret;
ff03a073 519 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 520
ff03a073
JR		 521 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
522 offset * sizeof(u64), sizeof(pdpte),
523 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 524 if (ret < 0) {
525 ret = 0;
526 goto out;
527 }
528 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 529 if (is_present_gpte(pdpte[i]) &&
20c466b5 530 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 624 return 0;
625}
2d3ad1f4 626EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 627
2d3ad1f4 628void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 629{
49a9b07e 630 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 631}
2d3ad1f4 632EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 633
42bdf991
MT		 634static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
635{
636 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
637 !vcpu->guest_xcr0_loaded) {
638 /* kvm_set_xcr() also depends on this */
639 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
640 vcpu->guest_xcr0_loaded = 1;
641 }
642}
643
644static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
645{
646 if (vcpu->guest_xcr0_loaded) {
647 if (vcpu->arch.xcr0 != host_xcr0)
648 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
649 vcpu->guest_xcr0_loaded = 0;
650 }
651}
652
69b0049a 653static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 654{
56c103ec
LJ		 655 u64 xcr0 = xcr;
656 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 657 u64 valid_bits;
2acf923e
DC		 658
659 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
660 if (index != XCR_XFEATURE_ENABLED_MASK)
661 return 1;
2acf923e
DC		 662 if (!(xcr0 & XSTATE_FP))
663 return 1;
664 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
665 return 1;
46c34cb0
PB		 666
667 /*
668 * Do not allow the guest to set bits that we do not support
669 * saving. However, xcr0 bit 0 is always set, even if the
670 * emulated CPU does not support XSAVE (see fx_init).
671 */
672 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
673 if (xcr0 & ~valid_bits)
2acf923e 674 return 1;
46c34cb0 675
390bd528
LJ		 676 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
677 return 1;
678
612263b3
CP		 679 if (xcr0 & XSTATE_AVX512) {
680 if (!(xcr0 & XSTATE_YMM))
681 return 1;
682 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
683 return 1;
684 }
42bdf991 685 kvm_put_guest_xcr0(vcpu);
2acf923e 686 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 687
688 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
689 kvm_update_cpuid(vcpu);
2acf923e
DC		 690 return 0;
691}
692
693int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
694{
764bcbc5
Z		 695 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
696 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 697 kvm_inject_gp(vcpu, 0);
698 return 1;
699 }
700 return 0;
701}
702EXPORT_SYMBOL_GPL(kvm_set_xcr);
703
a83b29c6 704int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 705{
fc78f519 706 unsigned long old_cr4 = kvm_read_cr4(vcpu);
edc90b7d
XG		 707 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
708 X86_CR4_SMEP | X86_CR4_SMAP;
709
0f12244f
GN		 710 if (cr4 & CR4_RESERVED_BITS)
711 return 1;
a03490ed 712
2acf923e
DC		 713 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
714 return 1;
715
c68b734f
YW		 716 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
717 return 1;
718
97ec8c06
FW		 719 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
720 return 1;
721
afcbf13f 722 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 723 return 1;
724
a03490ed 725 if (is_long_mode(vcpu)) {
0f12244f
GN		 726 if (!(cr4 & X86_CR4_PAE))
727 return 1;
a2edf57f
AK		 728 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
729 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 730 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
731 kvm_read_cr3(vcpu)))
0f12244f
GN		 732 return 1;
733
ad756a16
MJ		 734 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
735 if (!guest_cpuid_has_pcid(vcpu))
736 return 1;
737
738 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
739 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
740 return 1;
741 }
742
5e1746d6 743 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 744 return 1;
a03490ed 745
ad756a16
MJ		 746 if (((cr4 ^ old_cr4) & pdptr_bits) ||
747 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 748 kvm_mmu_reset_context(vcpu);
0f12244f 749
2acf923e 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 751 kvm_update_cpuid(vcpu);
2acf923e 752
0f12244f
GN		 753 return 0;
754}
2d3ad1f4 755EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 756
2390218b 757int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 758{
ac146235 759#ifdef CONFIG_X86_64
9d88fca7 760 cr3 &= ~CR3_PCID_INVD;
ac146235 761#endif
9d88fca7 762
9f8fe504 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 764 kvm_mmu_sync_roots(vcpu);
77c3913b 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 766 return 0;
d835dfec
AK		 767 }
768
a03490ed 769 if (is_long_mode(vcpu)) {
d9f89b88
JK		 770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 774 return 1;
a03490ed 775
0f12244f 776 vcpu->arch.cr3 = cr3;
aff48baa 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 778 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 782
eea1cff9 783int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 784{
0f12244f
GN		 785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
a03490ed
CO		 787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
ad312c7c 790 vcpu->arch.cr8 = cr8;
0f12244f
GN		 791 return 0;
792}
2d3ad1f4 793EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 794
2d3ad1f4 795unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 796{
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
ad312c7c 800 return vcpu->arch.cr8;
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 803
ae561ede
NA		 804static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805{
806 int i;
807
808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809 for (i = 0; i < KVM_NR_DB_REGS; i++)
810 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 }
813}
814
73aaf249
JK		 815static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816{
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819}
820
c8639010
JK		 821static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822{
823 unsigned long dr7;
824
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 dr7 = vcpu->arch.guest_debug_dr7;
827 else
828 dr7 = vcpu->arch.dr7;
829 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831 if (dr7 & DR7_BP_EN_MASK)
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 833}
834
6f43ed01
NA		 835static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836{
837 u64 fixed = DR6_FIXED_1;
838
839 if (!guest_cpuid_has_rtm(vcpu))
840 fixed |= DR6_RTM;
841 return fixed;
842}
843
338dbc97 844static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 vcpu->arch.db[dr] = val;
849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850 vcpu->arch.eff_db[dr] = val;
851 break;
852 case 4:
020df079
GN		 853 /* fall through */
854 case 6:
338dbc97
GN		 855 if (val & 0xffffffff00000000ULL)
856 return -1; /* #GP */
6f43ed01 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 858 kvm_update_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
020df079
GN		 861 /* fall through */
862 default: /* 7 */
338dbc97
GN		 863 if (val & 0xffffffff00000000ULL)
864 return -1; /* #GP */
020df079 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 866 kvm_update_dr7(vcpu);
020df079
GN		 867 break;
868 }
869
870 return 0;
871}
338dbc97
GN		 872
873int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874{
16f8a6f9 875 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 876 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 877 return 1;
878 }
879 return 0;
338dbc97 880}
020df079
GN		 881EXPORT_SYMBOL_GPL(kvm_set_dr);
882
16f8a6f9 883int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 884{
885 switch (dr) {
886 case 0 ... 3:
887 *val = vcpu->arch.db[dr];
888 break;
889 case 4:
020df079
GN		 890 /* fall through */
891 case 6:
73aaf249
JK		 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893 *val = vcpu->arch.dr6;
894 else
895 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 896 break;
897 case 5:
020df079
GN		 898 /* fall through */
899 default: /* 7 */
900 *val = vcpu->arch.dr7;
901 break;
902 }
338dbc97
GN		 903 return 0;
904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_get_dr);
906
022cd0e8
AK		 907bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908{
909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 u64 data;
911 int err;
912
913 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914 if (err)
915 return err;
916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918 return err;
919}
920EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
043405e1
CO		 922/*
923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925 *
926 * This list is modified at module load time to reflect the
e3267cbb 927 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 928 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
929 * may depend on host virtualization features rather than host cpu features.
043405e1 930 */
e3267cbb 931
043405e1
CO		 932static u32 msrs_to_save[] = {
933 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 934 MSR_STAR,
043405e1
CO		 935#ifdef CONFIG_X86_64
936 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
937#endif
b3897a49 938 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 939 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 940};
941
942static unsigned num_msrs_to_save;
943
62ef68bb
PB		 944static u32 emulated_msrs[] = {
945 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
946 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
947 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
948 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
949 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
950 MSR_KVM_PV_EOI_EN,
951
ba904635 952 MSR_IA32_TSC_ADJUST,
a3e06bbe 953 MSR_IA32_TSCDEADLINE,
043405e1 954 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 955 MSR_IA32_MCG_STATUS,
956 MSR_IA32_MCG_CTL,
043405e1
CO		 957};
958
62ef68bb
PB		 959static unsigned num_emulated_msrs;
960
384bb783 961bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 962{
b69e8cae 963 if (efer & efer_reserved_bits)
384bb783 964 return false;
15c4a640 965
1b2fd70c
AG		 966 if (efer & EFER_FFXSR) {
967 struct kvm_cpuid_entry2 *feat;
968
969 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 970 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 971 return false;
1b2fd70c
AG		 972 }
973
d8017474
AG		 974 if (efer & EFER_SVME) {
975 struct kvm_cpuid_entry2 *feat;
976
977 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 978 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 979 return false;
d8017474
AG		 980 }
981
384bb783
JK		 982 return true;
983}
984EXPORT_SYMBOL_GPL(kvm_valid_efer);
985
986static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
987{
988 u64 old_efer = vcpu->arch.efer;
989
990 if (!kvm_valid_efer(vcpu, efer))
991 return 1;
992
993 if (is_paging(vcpu)
994 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
995 return 1;
996
15c4a640 997 efer &= ~EFER_LMA;
f6801dff 998 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 999
a3d204e2
SY		 1000 kvm_x86_ops->set_efer(vcpu, efer);
1001
aad82703
SY		 1002 /* Update reserved bits */
1003 if ((efer ^ old_efer) & EFER_NX)
1004 kvm_mmu_reset_context(vcpu);
1005
b69e8cae 1006 return 0;
15c4a640
CO		 1007}
1008
f2b4b7dd
JR		 1009void kvm_enable_efer_bits(u64 mask)
1010{
1011 efer_reserved_bits &= ~mask;
1012}
1013EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1014
15c4a640
CO		 1015/*
1016 * Writes msr value into into the appropriate "register".
1017 * Returns 0 on success, non-0 otherwise.
1018 * Assumes vcpu_load() was already called.
1019 */
8fe8ab46 1020int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1021{
854e8bb1
NA		 1022 switch (msr->index) {
1023 case MSR_FS_BASE:
1024 case MSR_GS_BASE:
1025 case MSR_KERNEL_GS_BASE:
1026 case MSR_CSTAR:
1027 case MSR_LSTAR:
1028 if (is_noncanonical_address(msr->data))
1029 return 1;
1030 break;
1031 case MSR_IA32_SYSENTER_EIP:
1032 case MSR_IA32_SYSENTER_ESP:
1033 /*
1034 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1035 * non-canonical address is written on Intel but not on
1036 * AMD (which ignores the top 32-bits, because it does
1037 * not implement 64-bit SYSENTER).
1038 *
1039 * 64-bit code should hence be able to write a non-canonical
1040 * value on AMD. Making the address canonical ensures that
1041 * vmentry does not fail on Intel after writing a non-canonical
1042 * value, and that something deterministic happens if the guest
1043 * invokes 64-bit SYSENTER.
1044 */
1045 msr->data = get_canonical(msr->data);
1046 }
8fe8ab46 1047 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1048}
854e8bb1 1049EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1050
313a3dc7
CO		 1051/*
1052 * Adapt set_msr() to msr_io()'s calling convention
1053 */
609e36d3
PB		 1054static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1055{
1056 struct msr_data msr;
1057 int r;
1058
1059 msr.index = index;
1060 msr.host_initiated = true;
1061 r = kvm_get_msr(vcpu, &msr);
1062 if (r)
1063 return r;
1064
1065 *data = msr.data;
1066 return 0;
1067}
1068
313a3dc7
CO		 1069static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1070{
8fe8ab46
WA		 1071 struct msr_data msr;
1072
1073 msr.data = *data;
1074 msr.index = index;
1075 msr.host_initiated = true;
1076 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1077}
1078
16e8d74d
MT		 1079#ifdef CONFIG_X86_64
1080struct pvclock_gtod_data {
1081 seqcount_t seq;
1082
1083 struct { /* extract of a clocksource struct */
1084 int vclock_mode;
1085 cycle_t cycle_last;
1086 cycle_t mask;
1087 u32 mult;
1088 u32 shift;
1089 } clock;
1090
cbcf2dd3
TG		 1091 u64 boot_ns;
1092 u64 nsec_base;
16e8d74d
MT		 1093};
1094
1095static struct pvclock_gtod_data pvclock_gtod_data;
1096
1097static void update_pvclock_gtod(struct timekeeper *tk)
1098{
1099 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1100 u64 boot_ns;
1101
876e7881 1102 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1103
1104 write_seqcount_begin(&vdata->seq);
1105
1106 /* copy pvclock gtod data */
876e7881
PZ		 1107 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1108 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1109 vdata->clock.mask = tk->tkr_mono.mask;
1110 vdata->clock.mult = tk->tkr_mono.mult;
1111 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1112
cbcf2dd3 1113 vdata->boot_ns = boot_ns;
876e7881 1114 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1115
1116 write_seqcount_end(&vdata->seq);
1117}
1118#endif
1119
bab5bb39
NK		 1120void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1121{
1122 /*
1123 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1124 * vcpu_enter_guest. This function is only called from
1125 * the physical CPU that is running vcpu.
1126 */
1127 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1128}
16e8d74d 1129
18068523
GOC		 1130static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1131{
9ed3c444
AK		 1132 int version;
1133 int r;
50d0a0f9 1134 struct pvclock_wall_clock wc;
923de3cf 1135 struct timespec boot;
18068523
GOC		 1136
1137 if (!wall_clock)
1138 return;
1139
9ed3c444
AK		 1140 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1141 if (r)
1142 return;
1143
1144 if (version & 1)
1145 ++version; /* first time write, random junk */
1146
1147 ++version;
18068523 1148
18068523
GOC		 1149 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1150
50d0a0f9
GH		 1151 /*
1152 * The guest calculates current wall clock time by adding
34c238a1 1153 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1154 * wall clock specified here. guest system time equals host
1155 * system time for us, thus we must fill in host boot time here.
1156 */
923de3cf 1157 getboottime(&boot);
50d0a0f9 1158
4b648665
BR		 1159 if (kvm->arch.kvmclock_offset) {
1160 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1161 boot = timespec_sub(boot, ts);
1162 }
50d0a0f9
GH		 1163 wc.sec = boot.tv_sec;
1164 wc.nsec = boot.tv_nsec;
1165 wc.version = version;
18068523
GOC		 1166
1167 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1168
1169 version++;
1170 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1171}
1172
50d0a0f9
GH		 1173static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1174{
1175 uint32_t quotient, remainder;
1176
1177 /* Don't try to replace with do_div(), this one calculates
1178 * "(dividend << 32) / divisor" */
1179 __asm__ ( "divl %4"
1180 : "=a" (quotient), "=d" (remainder)
1181 : "0" (0), "1" (dividend), "r" (divisor) );
1182 return quotient;
1183}
1184
5f4e3f88
ZA		 1185static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1186 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1187{
5f4e3f88 1188 uint64_t scaled64;
50d0a0f9
GH		 1189 int32_t shift = 0;
1190 uint64_t tps64;
1191 uint32_t tps32;
1192
5f4e3f88
ZA		 1193 tps64 = base_khz * 1000LL;
1194 scaled64 = scaled_khz * 1000LL;
50933623 1195 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1196 tps64 >>= 1;
1197 shift--;
1198 }
1199
1200 tps32 = (uint32_t)tps64;
50933623
JK		 1201 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1202 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1203 scaled64 >>= 1;
1204 else
1205 tps32 <<= 1;
50d0a0f9
GH		 1206 shift++;
1207 }
1208
5f4e3f88
ZA		 1209 *pshift = shift;
1210 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1211
5f4e3f88
ZA		 1212 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1213 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1214}
1215
759379dd
ZA		 1216static inline u64 get_kernel_ns(void)
1217{
bb0b5812 1218 return ktime_get_boot_ns();
50d0a0f9
GH		 1219}
1220
d828199e 1221#ifdef CONFIG_X86_64
16e8d74d 1222static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1223#endif
16e8d74d 1224
c8076604 1225static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1226static unsigned long max_tsc_khz;
c8076604 1227
cc578287 1228static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1229{
cc578287
ZA		 1230 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1231 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1232}
1233
cc578287 1234static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1235{
cc578287
ZA		 1236 u64 v = (u64)khz * (1000000 + ppm);
1237 do_div(v, 1000000);
1238 return v;
1e993611
JR		 1239}
1240
cc578287 1241static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1242{
cc578287
ZA		 1243 u32 thresh_lo, thresh_hi;
1244 int use_scaling = 0;
217fc9cf 1245
03ba32ca
MT		 1246 /* tsc_khz can be zero if TSC calibration fails */
1247 if (this_tsc_khz == 0)
1248 return;
1249
c285545f
ZA		 1250 /* Compute a scale to convert nanoseconds in TSC cycles */
1251 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1252 &vcpu->arch.virtual_tsc_shift,
1253 &vcpu->arch.virtual_tsc_mult);
1254 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1255
1256 /*
1257 * Compute the variation in TSC rate which is acceptable
1258 * within the range of tolerance and decide if the
1259 * rate being applied is within that bounds of the hardware
1260 * rate. If so, no scaling or compensation need be done.
1261 */
1262 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1263 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1264 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1265 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1266 use_scaling = 1;
1267 }
1268 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1269}
1270
1271static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1272{
e26101b1 1273 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1274 vcpu->arch.virtual_tsc_mult,
1275 vcpu->arch.virtual_tsc_shift);
e26101b1 1276 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1277 return tsc;
1278}
1279
69b0049a 1280static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1281{
1282#ifdef CONFIG_X86_64
1283 bool vcpus_matched;
b48aa97e
MT		 1284 struct kvm_arch *ka = &vcpu->kvm->arch;
1285 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1286
1287 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1288 atomic_read(&vcpu->kvm->online_vcpus));
1289
7f187922
MT		 1290 /*
1291 * Once the masterclock is enabled, always perform request in
1292 * order to update it.
1293 *
1294 * In order to enable masterclock, the host clocksource must be TSC
1295 * and the vcpus need to have matched TSCs. When that happens,
1296 * perform request to enable masterclock.
1297 */
1298 if (ka->use_master_clock ||
1299 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1300 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1301
1302 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1303 atomic_read(&vcpu->kvm->online_vcpus),
1304 ka->use_master_clock, gtod->clock.vclock_mode);
1305#endif
1306}
1307
ba904635
WA		 1308static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1309{
1310 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1311 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1312}
1313
8fe8ab46 1314void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1315{
1316 struct kvm *kvm = vcpu->kvm;
f38e098f 1317 u64 offset, ns, elapsed;
99e3e30a 1318 unsigned long flags;
02626b6a 1319 s64 usdiff;
b48aa97e 1320 bool matched;
0d3da0d2 1321 bool already_matched;
8fe8ab46 1322 u64 data = msr->data;
99e3e30a 1323
038f8c11 1324 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1325 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1326 ns = get_kernel_ns();
f38e098f 1327 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1328
03ba32ca 1329 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1330 int faulted = 0;
1331
03ba32ca
MT		 1332 /* n.b - signed multiplication and division required */
1333 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1334#ifdef CONFIG_X86_64
03ba32ca 1335 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1336#else
03ba32ca 1337 /* do_div() only does unsigned */
8915aa27
MT		 1338 asm("1: idivl %[divisor]\n"
1339 "2: xor %%edx, %%edx\n"
1340 " movl $0, %[faulted]\n"
1341 "3:\n"
1342 ".section .fixup,\"ax\"\n"
1343 "4: movl $1, %[faulted]\n"
1344 " jmp 3b\n"
1345 ".previous\n"
1346
1347 _ASM_EXTABLE(1b, 4b)
1348
1349 : "=A"(usdiff), [faulted] "=r" (faulted)
1350 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1351
5d3cb0f6 1352#endif
03ba32ca
MT		 1353 do_div(elapsed, 1000);
1354 usdiff -= elapsed;
1355 if (usdiff < 0)
1356 usdiff = -usdiff;
8915aa27
MT		 1357
1358 /* idivl overflow => difference is larger than USEC_PER_SEC */
1359 if (faulted)
1360 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1361 } else
1362 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1363
1364 /*
5d3cb0f6
ZA		 1365 * Special case: TSC write with a small delta (1 second) of virtual
1366 * cycle time against real time is interpreted as an attempt to
1367 * synchronize the CPU.
1368 *
1369 * For a reliable TSC, we can match TSC offsets, and for an unstable
1370 * TSC, we add elapsed time in this computation. We could let the
1371 * compensation code attempt to catch up if we fall behind, but
1372 * it's better to try to match offsets from the beginning.
1373 */
02626b6a 1374 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1375 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1376 if (!check_tsc_unstable()) {
e26101b1 1377 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1378 pr_debug("kvm: matched tsc offset for %llu\n", data);
1379 } else {
857e4099 1380 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1381 data += delta;
1382 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1383 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1384 }
b48aa97e 1385 matched = true;
0d3da0d2 1386 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1387 } else {
1388 /*
1389 * We split periods of matched TSC writes into generations.
1390 * For each generation, we track the original measured
1391 * nanosecond time, offset, and write, so if TSCs are in
1392 * sync, we can match exact offset, and if not, we can match
4a969980 1393 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1394 *
1395 * These values are tracked in kvm->arch.cur_xxx variables.
1396 */
1397 kvm->arch.cur_tsc_generation++;
1398 kvm->arch.cur_tsc_nsec = ns;
1399 kvm->arch.cur_tsc_write = data;
1400 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1401 matched = false;
0d3da0d2 1402 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1403 kvm->arch.cur_tsc_generation, data);
f38e098f 1404 }
e26101b1
ZA		 1405
1406 /*
1407 * We also track th most recent recorded KHZ, write and time to
1408 * allow the matching interval to be extended at each write.
1409 */
f38e098f
ZA		 1410 kvm->arch.last_tsc_nsec = ns;
1411 kvm->arch.last_tsc_write = data;
5d3cb0f6 1412 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1413
b183aa58 1414 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1415
1416 /* Keep track of which generation this VCPU has synchronized to */
1417 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1418 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1419 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1420
ba904635
WA		 1421 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1422 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1423 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1424 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1425
1426 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1427 if (!matched) {
b48aa97e 1428 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1429 } else if (!already_matched) {
1430 kvm->arch.nr_vcpus_matched_tsc++;
1431 }
b48aa97e
MT		 1432
1433 kvm_track_tsc_matching(vcpu);
1434 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1435}
e26101b1 1436
99e3e30a
ZA		 1437EXPORT_SYMBOL_GPL(kvm_write_tsc);
1438
d828199e
MT		 1439#ifdef CONFIG_X86_64
1440
1441static cycle_t read_tsc(void)
1442{
1443 cycle_t ret;
1444 u64 last;
1445
1446 /*
1447 * Empirically, a fence (of type that depends on the CPU)
1448 * before rdtsc is enough to ensure that rdtsc is ordered
1449 * with respect to loads. The various CPU manuals are unclear
1450 * as to whether rdtsc can be reordered with later loads,
1451 * but no one has ever seen it happen.
1452 */
1453 rdtsc_barrier();
1454 ret = (cycle_t)vget_cycles();
1455
1456 last = pvclock_gtod_data.clock.cycle_last;
1457
1458 if (likely(ret >= last))
1459 return ret;
1460
1461 /*
1462 * GCC likes to generate cmov here, but this branch is extremely
1463 * predictable (it's just a funciton of time and the likely is
1464 * very likely) and there's a data dependence, so force GCC
1465 * to generate a branch instead. I don't barrier() because
1466 * we don't actually need a barrier, and if this function
1467 * ever gets inlined it will generate worse code.
1468 */
1469 asm volatile ("");
1470 return last;
1471}
1472
1473static inline u64 vgettsc(cycle_t *cycle_now)
1474{
1475 long v;
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477
1478 *cycle_now = read_tsc();
1479
1480 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1481 return v * gtod->clock.mult;
1482}
1483
cbcf2dd3 1484static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1485{
cbcf2dd3 1486 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1487 unsigned long seq;
d828199e 1488 int mode;
cbcf2dd3 1489 u64 ns;
d828199e 1490
d828199e
MT		 1491 do {
1492 seq = read_seqcount_begin(&gtod->seq);
1493 mode = gtod->clock.vclock_mode;
cbcf2dd3 1494 ns = gtod->nsec_base;
d828199e
MT		 1495 ns += vgettsc(cycle_now);
1496 ns >>= gtod->clock.shift;
cbcf2dd3 1497 ns += gtod->boot_ns;
d828199e 1498 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1499 *t = ns;
d828199e
MT		 1500
1501 return mode;
1502}
1503
1504/* returns true if host is using tsc clocksource */
1505static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1506{
d828199e
MT		 1507 /* checked again under seqlock below */
1508 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1509 return false;
1510
cbcf2dd3 1511 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1512}
1513#endif
1514
1515/*
1516 *
b48aa97e
MT		 1517 * Assuming a stable TSC across physical CPUS, and a stable TSC
1518 * across virtual CPUs, the following condition is possible.
1519 * Each numbered line represents an event visible to both
d828199e
MT		 1520 * CPUs at the next numbered event.
1521 *
1522 * "timespecX" represents host monotonic time. "tscX" represents
1523 * RDTSC value.
1524 *
1525 * VCPU0 on CPU0 | VCPU1 on CPU1
1526 *
1527 * 1. read timespec0,tsc0
1528 * 2. | timespec1 = timespec0 + N
1529 * | tsc1 = tsc0 + M
1530 * 3. transition to guest | transition to guest
1531 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1532 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1533 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1534 *
1535 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1536 *
1537 * - ret0 < ret1
1538 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1539 * ...
1540 * - 0 < N - M => M < N
1541 *
1542 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1543 * always the case (the difference between two distinct xtime instances
1544 * might be smaller then the difference between corresponding TSC reads,
1545 * when updating guest vcpus pvclock areas).
1546 *
1547 * To avoid that problem, do not allow visibility of distinct
1548 * system_timestamp/tsc_timestamp values simultaneously: use a master
1549 * copy of host monotonic time values. Update that master copy
1550 * in lockstep.
1551 *
b48aa97e 1552 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1553 *
1554 */
1555
1556static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1557{
1558#ifdef CONFIG_X86_64
1559 struct kvm_arch *ka = &kvm->arch;
1560 int vclock_mode;
b48aa97e
MT		 1561 bool host_tsc_clocksource, vcpus_matched;
1562
1563 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1564 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1565
1566 /*
1567 * If the host uses TSC clock, then passthrough TSC as stable
1568 * to the guest.
1569 */
b48aa97e 1570 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1571 &ka->master_kernel_ns,
1572 &ka->master_cycle_now);
1573
16a96021 1574 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1575 && !backwards_tsc_observed
1576 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1577
d828199e
MT		 1578 if (ka->use_master_clock)
1579 atomic_set(&kvm_guest_has_master_clock, 1);
1580
1581 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1582 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1583 vcpus_matched);
d828199e
MT		 1584#endif
1585}
1586
2e762ff7
MT		 1587static void kvm_gen_update_masterclock(struct kvm *kvm)
1588{
1589#ifdef CONFIG_X86_64
1590 int i;
1591 struct kvm_vcpu *vcpu;
1592 struct kvm_arch *ka = &kvm->arch;
1593
1594 spin_lock(&ka->pvclock_gtod_sync_lock);
1595 kvm_make_mclock_inprogress_request(kvm);
1596 /* no guest entries from this point */
1597 pvclock_update_vm_gtod_copy(kvm);
1598
1599 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1600 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1601
1602 /* guest entries allowed */
1603 kvm_for_each_vcpu(i, vcpu, kvm)
1604 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1605
1606 spin_unlock(&ka->pvclock_gtod_sync_lock);
1607#endif
1608}
1609
34c238a1 1610static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1611{
d828199e 1612 unsigned long flags, this_tsc_khz;
18068523 1613 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1614 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1615 s64 kernel_ns;
d828199e 1616 u64 tsc_timestamp, host_tsc;
0b79459b 1617 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1618 u8 pvclock_flags;
d828199e
MT		 1619 bool use_master_clock;
1620
1621 kernel_ns = 0;
1622 host_tsc = 0;
18068523 1623
d828199e
MT		 1624 /*
1625 * If the host uses TSC clock, then passthrough TSC as stable
1626 * to the guest.
1627 */
1628 spin_lock(&ka->pvclock_gtod_sync_lock);
1629 use_master_clock = ka->use_master_clock;
1630 if (use_master_clock) {
1631 host_tsc = ka->master_cycle_now;
1632 kernel_ns = ka->master_kernel_ns;
1633 }
1634 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1635
1636 /* Keep irq disabled to prevent changes to the clock */
1637 local_irq_save(flags);
89cbc767 1638 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1639 if (unlikely(this_tsc_khz == 0)) {
1640 local_irq_restore(flags);
1641 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1642 return 1;
1643 }
d828199e
MT		 1644 if (!use_master_clock) {
1645 host_tsc = native_read_tsc();
1646 kernel_ns = get_kernel_ns();
1647 }
1648
1649 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1650
c285545f
ZA		 1651 /*
1652 * We may have to catch up the TSC to match elapsed wall clock
1653 * time for two reasons, even if kvmclock is used.
1654 * 1) CPU could have been running below the maximum TSC rate
1655 * 2) Broken TSC compensation resets the base at each VCPU
1656 * entry to avoid unknown leaps of TSC even when running
1657 * again on the same CPU. This may cause apparent elapsed
1658 * time to disappear, and the guest to stand still or run
1659 * very slowly.
1660 */
1661 if (vcpu->tsc_catchup) {
1662 u64 tsc = compute_guest_tsc(v, kernel_ns);
1663 if (tsc > tsc_timestamp) {
f1e2b260 1664 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1665 tsc_timestamp = tsc;
1666 }
50d0a0f9
GH		 1667 }
1668
18068523
GOC		 1669 local_irq_restore(flags);
1670
0b79459b 1671 if (!vcpu->pv_time_enabled)
c285545f 1672 return 0;
18068523 1673
e48672fa 1674 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1675 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1676 &vcpu->hv_clock.tsc_shift,
1677 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1678 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1679 }
1680
1681 /* With all the info we got, fill in the values */
1d5f066e 1682 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1683 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1684 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1685
09a0c3f1
OH		 1686 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1687 &guest_hv_clock, sizeof(guest_hv_clock))))
1688 return 0;
1689
5dca0d91
RK		 1690 /* This VCPU is paused, but it's legal for a guest to read another
1691 * VCPU's kvmclock, so we really have to follow the specification where
1692 * it says that version is odd if data is being modified, and even after
1693 * it is consistent.
1694 *
1695 * Version field updates must be kept separate. This is because
1696 * kvm_write_guest_cached might use a "rep movs" instruction, and
1697 * writes within a string instruction are weakly ordered. So there
1698 * are three writes overall.
1699 *
1700 * As a small optimization, only write the version field in the first
1701 * and third write. The vcpu->pv_time cache is still valid, because the
1702 * version field is the first in the struct.
18068523 1703 */
5dca0d91
RK		 1704 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1705
1706 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1707 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1708 &vcpu->hv_clock,
1709 sizeof(vcpu->hv_clock.version));
1710
1711 smp_wmb();
78c0337a
MT		 1712
1713 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1714 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1715
1716 if (vcpu->pvclock_set_guest_stopped_request) {
1717 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1718 vcpu->pvclock_set_guest_stopped_request = false;
1719 }
1720
b7e60c5a
MT		 1721 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1722
d828199e
MT		 1723 /* If the host uses TSC clocksource, then it is stable */
1724 if (use_master_clock)
1725 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1726
78c0337a
MT		 1727 vcpu->hv_clock.flags = pvclock_flags;
1728
ce1a5e60
DM		 1729 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1730
0b79459b
AH		 1731 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1732 &vcpu->hv_clock,
1733 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1734
1735 smp_wmb();
1736
1737 vcpu->hv_clock.version++;
1738 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1739 &vcpu->hv_clock,
1740 sizeof(vcpu->hv_clock.version));
8cfdc000 1741 return 0;
c8076604
GH		 1742}
1743
0061d53d
MT		 1744/*
1745 * kvmclock updates which are isolated to a given vcpu, such as
1746 * vcpu->cpu migration, should not allow system_timestamp from
1747 * the rest of the vcpus to remain static. Otherwise ntp frequency
1748 * correction applies to one vcpu's system_timestamp but not
1749 * the others.
1750 *
1751 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1752 * We need to rate-limit these requests though, as they can
1753 * considerably slow guests that have a large number of vcpus.
1754 * The time for a remote vcpu to update its kvmclock is bound
1755 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1756 */
1757
7e44e449
AJ		 1758#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1759
1760static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1761{
1762 int i;
7e44e449
AJ		 1763 struct delayed_work *dwork = to_delayed_work(work);
1764 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1765 kvmclock_update_work);
1766 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1767 struct kvm_vcpu *vcpu;
1768
1769 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1771 kvm_vcpu_kick(vcpu);
1772 }
1773}
1774
7e44e449
AJ		 1775static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1776{
1777 struct kvm *kvm = v->kvm;
1778
105b21bb 1779 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1780 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1781 KVMCLOCK_UPDATE_DELAY);
1782}
1783
332967a3
AJ		 1784#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1785
1786static void kvmclock_sync_fn(struct work_struct *work)
1787{
1788 struct delayed_work *dwork = to_delayed_work(work);
1789 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1790 kvmclock_sync_work);
1791 struct kvm *kvm = container_of(ka, struct kvm, arch);
1792
630994b3
MT		 1793 if (!kvmclock_periodic_sync)
1794 return;
1795
332967a3
AJ		 1796 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1797 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1798 KVMCLOCK_SYNC_PERIOD);
1799}
1800
9ba075a6
AK		 1801static bool msr_mtrr_valid(unsigned msr)
1802{
1803 switch (msr) {
1804 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1805 case MSR_MTRRfix64K_00000:
1806 case MSR_MTRRfix16K_80000:
1807 case MSR_MTRRfix16K_A0000:
1808 case MSR_MTRRfix4K_C0000:
1809 case MSR_MTRRfix4K_C8000:
1810 case MSR_MTRRfix4K_D0000:
1811 case MSR_MTRRfix4K_D8000:
1812 case MSR_MTRRfix4K_E0000:
1813 case MSR_MTRRfix4K_E8000:
1814 case MSR_MTRRfix4K_F0000:
1815 case MSR_MTRRfix4K_F8000:
1816 case MSR_MTRRdefType:
1817 case MSR_IA32_CR_PAT:
1818 return true;
1819 case 0x2f8:
1820 return true;
1821 }
1822 return false;
1823}
1824
d6289b93
MT		 1825static bool valid_pat_type(unsigned t)
1826{
1827 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1828}
1829
1830static bool valid_mtrr_type(unsigned t)
1831{
1832 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1833}
1834
4566654b 1835bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1836{
1837 int i;
fd275235 1838 u64 mask;
d6289b93
MT		 1839
1840 if (!msr_mtrr_valid(msr))
1841 return false;
1842
1843 if (msr == MSR_IA32_CR_PAT) {
1844 for (i = 0; i < 8; i++)
1845 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1846 return false;
1847 return true;
1848 } else if (msr == MSR_MTRRdefType) {
1849 if (data & ~0xcff)
1850 return false;
1851 return valid_mtrr_type(data & 0xff);
1852 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1853 for (i = 0; i < 8 ; i++)
1854 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1855 return false;
1856 return true;
1857 }
1858
1859 /* variable MTRRs */
adfb5d27
WL		 1860 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1861
fd275235 1862 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1863 if ((msr & 1) == 0) {
adfb5d27 1864 /* MTRR base */
d7a2a246
WL		 1865 if (!valid_mtrr_type(data & 0xff))
1866 return false;
1867 mask |= 0xf00;
1868 } else
1869 /* MTRR mask */
1870 mask |= 0x7ff;
1871 if (data & mask) {
1872 kvm_inject_gp(vcpu, 0);
1873 return false;
1874 }
1875
adfb5d27 1876 return true;
d6289b93 1877}
4566654b 1878EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1879
efdfe536
XG		 1880static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr)
1881{
1882 struct mtrr_state_type *mtrr_state = &vcpu->arch.mtrr_state;
1883 unsigned char mtrr_enabled = mtrr_state->enabled;
1884 gfn_t start, end, mask;
1885 int index;
1886 bool is_fixed = true;
1887
1888 if (msr == MSR_IA32_CR_PAT || !tdp_enabled ||
1889 !kvm_arch_has_noncoherent_dma(vcpu->kvm))
1890 return;
1891
1892 if (!(mtrr_enabled & 0x2) && msr != MSR_MTRRdefType)
1893 return;
1894
1895 switch (msr) {
1896 case MSR_MTRRfix64K_00000:
1897 start = 0x0;
1898 end = 0x80000;
1899 break;
1900 case MSR_MTRRfix16K_80000:
1901 start = 0x80000;
1902 end = 0xa0000;
1903 break;
1904 case MSR_MTRRfix16K_A0000:
1905 start = 0xa0000;
1906 end = 0xc0000;
1907 break;
1908 case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000:
1909 index = msr - MSR_MTRRfix4K_C0000;
1910 start = 0xc0000 + index * (32 << 10);
1911 end = start + (32 << 10);
1912 break;
1913 case MSR_MTRRdefType:
1914 is_fixed = false;
1915 start = 0x0;
1916 end = ~0ULL;
1917 break;
1918 default:
1919 /* variable range MTRRs. */
1920 is_fixed = false;
1921 index = (msr - 0x200) / 2;
1922 start = (((u64)mtrr_state->var_ranges[index].base_hi) << 32) +
1923 (mtrr_state->var_ranges[index].base_lo & PAGE_MASK);
1924 mask = (((u64)mtrr_state->var_ranges[index].mask_hi) << 32) +
1925 (mtrr_state->var_ranges[index].mask_lo & PAGE_MASK);
1926 mask |= ~0ULL << cpuid_maxphyaddr(vcpu);
1927
1928 end = ((start & mask) | ~mask) + 1;
1929 }
1930
1931 if (is_fixed && !(mtrr_enabled & 0x1))
1932 return;
1933
1934 kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end));
1935}
1936
9ba075a6
AK		 1937static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1938{
0bed3b56
SY		 1939 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1940
4566654b 1941 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1942 return 1;
1943
0bed3b56
SY		 1944 if (msr == MSR_MTRRdefType) {
1945 vcpu->arch.mtrr_state.def_type = data;
1946 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1947 } else if (msr == MSR_MTRRfix64K_00000)
1948 p[0] = data;
1949 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1950 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1951 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1952 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1953 else if (msr == MSR_IA32_CR_PAT)
1954 vcpu->arch.pat = data;
1955 else { /* Variable MTRRs */
1956 int idx, is_mtrr_mask;
1957 u64 *pt;
1958
1959 idx = (msr - 0x200) / 2;
1960 is_mtrr_mask = msr - 0x200 - 2 * idx;
1961 if (!is_mtrr_mask)
1962 pt =
1963 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1964 else
1965 pt =
1966 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1967 *pt = data;
1968 }
1969
efdfe536 1970 update_mtrr(vcpu, msr);
9ba075a6
AK		 1971 return 0;
1972}
15c4a640 1973
890ca9ae 1974static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1975{
890ca9ae
HY		 1976 u64 mcg_cap = vcpu->arch.mcg_cap;
1977 unsigned bank_num = mcg_cap & 0xff;
1978
15c4a640 1979 switch (msr) {
15c4a640 1980 case MSR_IA32_MCG_STATUS:
890ca9ae 1981 vcpu->arch.mcg_status = data;
15c4a640 1982 break;
c7ac679c 1983 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1984 if (!(mcg_cap & MCG_CTL_P))
1985 return 1;
1986 if (data != 0 && data != ~(u64)0)
1987 return -1;
1988 vcpu->arch.mcg_ctl = data;
1989 break;
1990 default:
1991 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1992 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1993 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1994 /* only 0 or all 1s can be written to IA32_MCi_CTL
1995 * some Linux kernels though clear bit 10 in bank 4 to
1996 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1997 * this to avoid an uncatched #GP in the guest
1998 */
890ca9ae 1999 if ((offset & 0x3) == 0 &&
114be429 2000 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2001 return -1;
2002 vcpu->arch.mce_banks[offset] = data;
2003 break;
2004 }
2005 return 1;
2006 }
2007 return 0;
2008}
2009
ffde22ac
ES		 2010static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2011{
2012 struct kvm *kvm = vcpu->kvm;
2013 int lm = is_long_mode(vcpu);
2014 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2015 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2016 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2017 : kvm->arch.xen_hvm_config.blob_size_32;
2018 u32 page_num = data & ~PAGE_MASK;
2019 u64 page_addr = data & PAGE_MASK;
2020 u8 *page;
2021 int r;
2022
2023 r = -E2BIG;
2024 if (page_num >= blob_size)
2025 goto out;
2026 r = -ENOMEM;
ff5c2c03
SL		 2027 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2028 if (IS_ERR(page)) {
2029 r = PTR_ERR(page);
ffde22ac 2030 goto out;
ff5c2c03 2031 }
ffde22ac
ES		 2032 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
2033 goto out_free;
2034 r = 0;
2035out_free:
2036 kfree(page);
2037out:
2038 return r;
2039}
2040
55cd8e5a
GN		 2041static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
2042{
2043 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
2044}
2045
2046static bool kvm_hv_msr_partition_wide(u32 msr)
2047{
2048 bool r = false;
2049 switch (msr) {
2050 case HV_X64_MSR_GUEST_OS_ID:
2051 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 2052 case HV_X64_MSR_REFERENCE_TSC:
2053 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 2054 r = true;
2055 break;
2056 }
2057
2058 return r;
2059}
2060
2061static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2062{
2063 struct kvm *kvm = vcpu->kvm;
2064
2065 switch (msr) {
2066 case HV_X64_MSR_GUEST_OS_ID:
2067 kvm->arch.hv_guest_os_id = data;
2068 /* setting guest os id to zero disables hypercall page */
2069 if (!kvm->arch.hv_guest_os_id)
2070 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
2071 break;
2072 case HV_X64_MSR_HYPERCALL: {
2073 u64 gfn;
2074 unsigned long addr;
2075 u8 instructions[4];
2076
2077 /* if guest os id is not set hypercall should remain disabled */
2078 if (!kvm->arch.hv_guest_os_id)
2079 break;
2080 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2081 kvm->arch.hv_hypercall = data;
2082 break;
2083 }
2084 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2085 addr = gfn_to_hva(kvm, gfn);
2086 if (kvm_is_error_hva(addr))
2087 return 1;
2088 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2089 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2090 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2091 return 1;
2092 kvm->arch.hv_hypercall = data;
b94b64c9 2093 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2094 break;
2095 }
e984097b
VR		 2096 case HV_X64_MSR_REFERENCE_TSC: {
2097 u64 gfn;
2098 HV_REFERENCE_TSC_PAGE tsc_ref;
2099 memset(&tsc_ref, 0, sizeof(tsc_ref));
2100 kvm->arch.hv_tsc_page = data;
2101 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2102 break;
2103 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2104 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2105 &tsc_ref, sizeof(tsc_ref)))
2106 return 1;
2107 mark_page_dirty(kvm, gfn);
2108 break;
2109 }
55cd8e5a 2110 default:
a737f256
CD		 2111 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2112 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2113 return 1;
2114 }
2115 return 0;
2116}
2117
2118static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2119{
10388a07
GN		 2120 switch (msr) {
2121 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2122 u64 gfn;
10388a07 2123 unsigned long addr;
55cd8e5a 2124
10388a07
GN		 2125 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2126 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2127 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2128 return 1;
10388a07
GN		 2129 break;
2130 }
b3af1e88
VR		 2131 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2132 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2133 if (kvm_is_error_hva(addr))
2134 return 1;
8b0cedff 2135 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2136 return 1;
2137 vcpu->arch.hv_vapic = data;
b3af1e88 2138 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2139 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2140 return 1;
10388a07
GN		 2141 break;
2142 }
2143 case HV_X64_MSR_EOI:
2144 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2145 case HV_X64_MSR_ICR:
2146 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2147 case HV_X64_MSR_TPR:
2148 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2149 default:
a737f256
CD		 2150 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2151 "data 0x%llx\n", msr, data);
10388a07
GN		 2152 return 1;
2153 }
2154
2155 return 0;
55cd8e5a
GN		 2156}
2157
344d9588
GN		 2158static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2159{
2160 gpa_t gpa = data & ~0x3f;
2161
4a969980 2162 /* Bits 2:5 are reserved, Should be zero */
6adba527 2163 if (data & 0x3c)
344d9588
GN		 2164 return 1;
2165
2166 vcpu->arch.apf.msr_val = data;
2167
2168 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2169 kvm_clear_async_pf_completion_queue(vcpu);
2170 kvm_async_pf_hash_reset(vcpu);
2171 return 0;
2172 }
2173
8f964525
AH		 2174 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2175 sizeof(u32)))
344d9588
GN		 2176 return 1;
2177
6adba527 2178 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2179 kvm_async_pf_wakeup_all(vcpu);
2180 return 0;
2181}
2182
12f9a48f
GC		 2183static void kvmclock_reset(struct kvm_vcpu *vcpu)
2184{
0b79459b 2185 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2186}
2187
c9aaa895
GC		 2188static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2189{
2190 u64 delta;
2191
2192 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2193 return;
2194
2195 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2196 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2197 vcpu->arch.st.accum_steal = delta;
2198}
2199
2200static void record_steal_time(struct kvm_vcpu *vcpu)
2201{
2202 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2203 return;
2204
2205 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2206 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2207 return;
2208
2209 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2210 vcpu->arch.st.steal.version += 2;
2211 vcpu->arch.st.accum_steal = 0;
2212
2213 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2214 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2215}
2216
8fe8ab46 2217int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2218{
5753785f 2219 bool pr = false;
8fe8ab46
WA		 2220 u32 msr = msr_info->index;
2221 u64 data = msr_info->data;
5753785f 2222
15c4a640 2223 switch (msr) {
2e32b719
BP		 2224 case MSR_AMD64_NB_CFG:
2225 case MSR_IA32_UCODE_REV:
2226 case MSR_IA32_UCODE_WRITE:
2227 case MSR_VM_HSAVE_PA:
2228 case MSR_AMD64_PATCH_LOADER:
2229 case MSR_AMD64_BU_CFG2:
2230 break;
2231
15c4a640 2232 case MSR_EFER:
b69e8cae 2233 return set_efer(vcpu, data);
8f1589d9
AP		 2234 case MSR_K7_HWCR:
2235 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2236 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2237 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2238 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2239 if (data != 0) {
a737f256
CD		 2240 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2241 data);
8f1589d9
AP		 2242 return 1;
2243 }
15c4a640 2244 break;
f7c6d140
AP		 2245 case MSR_FAM10H_MMIO_CONF_BASE:
2246 if (data != 0) {
a737f256
CD		 2247 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2248 "0x%llx\n", data);
f7c6d140
AP		 2249 return 1;
2250 }
15c4a640 2251 break;
b5e2fec0
AG		 2252 case MSR_IA32_DEBUGCTLMSR:
2253 if (!data) {
2254 /* We support the non-activated case already */
2255 break;
2256 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2257 /* Values other than LBR and BTF are vendor-specific,
2258 thus reserved and should throw a #GP */
2259 return 1;
2260 }
a737f256
CD		 2261 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2262 __func__, data);
b5e2fec0 2263 break;
9ba075a6
AK		 2264 case 0x200 ... 0x2ff:
2265 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2266 case MSR_IA32_APICBASE:
58cb628d 2267 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2268 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2269 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2270 case MSR_IA32_TSCDEADLINE:
2271 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2272 break;
ba904635
WA		 2273 case MSR_IA32_TSC_ADJUST:
2274 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2275 if (!msr_info->host_initiated) {
d913b904 2276 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2277 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2278 }
2279 vcpu->arch.ia32_tsc_adjust_msr = data;
2280 }
2281 break;
15c4a640 2282 case MSR_IA32_MISC_ENABLE:
ad312c7c 2283 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2284 break;
11c6bffa 2285 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2286 case MSR_KVM_WALL_CLOCK:
2287 vcpu->kvm->arch.wall_clock = data;
2288 kvm_write_wall_clock(vcpu->kvm, data);
2289 break;
11c6bffa 2290 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2291 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2292 u64 gpa_offset;
54750f2c
MT		 2293 struct kvm_arch *ka = &vcpu->kvm->arch;
2294
12f9a48f 2295 kvmclock_reset(vcpu);
18068523 2296
54750f2c
MT		 2297 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2298 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2299
2300 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2301 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2302 &vcpu->requests);
2303
2304 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2305
2306 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2307 }
2308
18068523 2309 vcpu->arch.time = data;
0061d53d 2310 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2311
2312 /* we verify if the enable bit is set... */
2313 if (!(data & 1))
2314 break;
2315
0b79459b 2316 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2317
0b79459b 2318 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2319 &vcpu->arch.pv_time, data & ~1ULL,
2320 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2321 vcpu->arch.pv_time_enabled = false;
2322 else
2323 vcpu->arch.pv_time_enabled = true;
32cad84f 2324
18068523
GOC		 2325 break;
2326 }
344d9588
GN		 2327 case MSR_KVM_ASYNC_PF_EN:
2328 if (kvm_pv_enable_async_pf(vcpu, data))
2329 return 1;
2330 break;
c9aaa895
GC		 2331 case MSR_KVM_STEAL_TIME:
2332
2333 if (unlikely(!sched_info_on()))
2334 return 1;
2335
2336 if (data & KVM_STEAL_RESERVED_MASK)
2337 return 1;
2338
2339 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2340 data & KVM_STEAL_VALID_BITS,
2341 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2342 return 1;
2343
2344 vcpu->arch.st.msr_val = data;
2345
2346 if (!(data & KVM_MSR_ENABLED))
2347 break;
2348
2349 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2350
2351 preempt_disable();
2352 accumulate_steal_time(vcpu);
2353 preempt_enable();
2354
2355 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2356
2357 break;
ae7a2a3f
MT		 2358 case MSR_KVM_PV_EOI_EN:
2359 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2360 return 1;
2361 break;
c9aaa895 2362
890ca9ae
HY		 2363 case MSR_IA32_MCG_CTL:
2364 case MSR_IA32_MCG_STATUS:
81760dcc 2365 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2366 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2367
2368 /* Performance counters are not protected by a CPUID bit,
2369 * so we should check all of them in the generic path for the sake of
2370 * cross vendor migration.
2371 * Writing a zero into the event select MSRs disables them,
2372 * which we perfectly emulate ;-). Any other value should be at least
2373 * reported, some guests depend on them.
2374 */
71db6023
AP		 2375 case MSR_K7_EVNTSEL0:
2376 case MSR_K7_EVNTSEL1:
2377 case MSR_K7_EVNTSEL2:
2378 case MSR_K7_EVNTSEL3:
2379 if (data != 0)
a737f256
CD		 2380 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2381 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2382 break;
2383 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2384 * so we ignore writes to make it happy.
2385 */
71db6023
AP		 2386 case MSR_K7_PERFCTR0:
2387 case MSR_K7_PERFCTR1:
2388 case MSR_K7_PERFCTR2:
2389 case MSR_K7_PERFCTR3:
a737f256
CD		 2390 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2391 "0x%x data 0x%llx\n", msr, data);
71db6023 2392 break;
5753785f
GN		 2393 case MSR_P6_PERFCTR0:
2394 case MSR_P6_PERFCTR1:
2395 pr = true;
2396 case MSR_P6_EVNTSEL0:
2397 case MSR_P6_EVNTSEL1:
2398 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2399 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2400
2401 if (pr || data != 0)
a737f256
CD		 2402 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2403 "0x%x data 0x%llx\n", msr, data);
5753785f 2404 break;
84e0cefa
JS		 2405 case MSR_K7_CLK_CTL:
2406 /*
2407 * Ignore all writes to this no longer documented MSR.
2408 * Writes are only relevant for old K7 processors,
2409 * all pre-dating SVM, but a recommended workaround from
4a969980 2410 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2411 * affected processor models on the command line, hence
2412 * the need to ignore the workaround.
2413 */
2414 break;
55cd8e5a
GN		 2415 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2416 if (kvm_hv_msr_partition_wide(msr)) {
2417 int r;
2418 mutex_lock(&vcpu->kvm->lock);
2419 r = set_msr_hyperv_pw(vcpu, msr, data);
2420 mutex_unlock(&vcpu->kvm->lock);
2421 return r;
2422 } else
2423 return set_msr_hyperv(vcpu, msr, data);
2424 break;
91c9c3ed 2425 case MSR_IA32_BBL_CR_CTL3:
2426 /* Drop writes to this legacy MSR -- see rdmsr
2427 * counterpart for further detail.
2428 */
a737f256 2429 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2430 break;
2b036c6b
BO		 2431 case MSR_AMD64_OSVW_ID_LENGTH:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
2434 vcpu->arch.osvw.length = data;
2435 break;
2436 case MSR_AMD64_OSVW_STATUS:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
2439 vcpu->arch.osvw.status = data;
2440 break;
15c4a640 2441 default:
ffde22ac
ES		 2442 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2443 return xen_hvm_config(vcpu, data);
f5132b01 2444 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2445 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2446 if (!ignore_msrs) {
a737f256
CD		 2447 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2448 msr, data);
ed85c068
AP		 2449 return 1;
2450 } else {
a737f256
CD		 2451 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2452 msr, data);
ed85c068
AP		 2453 break;
2454 }
15c4a640
CO		 2455 }
2456 return 0;
2457}
2458EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2459
2460
2461/*
2462 * Reads an msr value (of 'msr_index') into 'pdata'.
2463 * Returns 0 on success, non-0 otherwise.
2464 * Assumes vcpu_load() was already called.
2465 */
609e36d3 2466int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2467{
609e36d3 2468 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2469}
ff651cb6 2470EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2471
9ba075a6
AK		 2472static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2473{
0bed3b56
SY		 2474 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2475
9ba075a6
AK		 2476 if (!msr_mtrr_valid(msr))
2477 return 1;
2478
0bed3b56
SY		 2479 if (msr == MSR_MTRRdefType)
2480 *pdata = vcpu->arch.mtrr_state.def_type +
2481 (vcpu->arch.mtrr_state.enabled << 10);
2482 else if (msr == MSR_MTRRfix64K_00000)
2483 *pdata = p[0];
2484 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2485 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2486 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2487 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2488 else if (msr == MSR_IA32_CR_PAT)
2489 *pdata = vcpu->arch.pat;
2490 else { /* Variable MTRRs */
2491 int idx, is_mtrr_mask;
2492 u64 *pt;
2493
2494 idx = (msr - 0x200) / 2;
2495 is_mtrr_mask = msr - 0x200 - 2 * idx;
2496 if (!is_mtrr_mask)
2497 pt =
2498 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2499 else
2500 pt =
2501 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2502 *pdata = *pt;
2503 }
2504
9ba075a6
AK		 2505 return 0;
2506}
2507
890ca9ae 2508static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2509{
2510 u64 data;
890ca9ae
HY		 2511 u64 mcg_cap = vcpu->arch.mcg_cap;
2512 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2513
2514 switch (msr) {
15c4a640
CO		 2515 case MSR_IA32_P5_MC_ADDR:
2516 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2517 data = 0;
2518 break;
15c4a640 2519 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2520 data = vcpu->arch.mcg_cap;
2521 break;
c7ac679c 2522 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2523 if (!(mcg_cap & MCG_CTL_P))
2524 return 1;
2525 data = vcpu->arch.mcg_ctl;
2526 break;
2527 case MSR_IA32_MCG_STATUS:
2528 data = vcpu->arch.mcg_status;
2529 break;
2530 default:
2531 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2532 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2533 u32 offset = msr - MSR_IA32_MC0_CTL;
2534 data = vcpu->arch.mce_banks[offset];
2535 break;
2536 }
2537 return 1;
2538 }
2539 *pdata = data;
2540 return 0;
2541}
2542
55cd8e5a
GN		 2543static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2544{
2545 u64 data = 0;
2546 struct kvm *kvm = vcpu->kvm;
2547
2548 switch (msr) {
2549 case HV_X64_MSR_GUEST_OS_ID:
2550 data = kvm->arch.hv_guest_os_id;
2551 break;
2552 case HV_X64_MSR_HYPERCALL:
2553 data = kvm->arch.hv_hypercall;
2554 break;
e984097b
VR		 2555 case HV_X64_MSR_TIME_REF_COUNT: {
2556 data =
2557 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2558 break;
2559 }
2560 case HV_X64_MSR_REFERENCE_TSC:
2561 data = kvm->arch.hv_tsc_page;
2562 break;
55cd8e5a 2563 default:
a737f256 2564 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2565 return 1;
2566 }
2567
2568 *pdata = data;
2569 return 0;
2570}
2571
2572static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2573{
2574 u64 data = 0;
2575
2576 switch (msr) {
2577 case HV_X64_MSR_VP_INDEX: {
2578 int r;
2579 struct kvm_vcpu *v;
684851a1
TY		 2580 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2581 if (v == vcpu) {
55cd8e5a 2582 data = r;
684851a1
TY		 2583 break;
2584 }
2585 }
55cd8e5a
GN		 2586 break;
2587 }
10388a07
GN		 2588 case HV_X64_MSR_EOI:
2589 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2590 case HV_X64_MSR_ICR:
2591 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2592 case HV_X64_MSR_TPR:
2593 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2594 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2595 data = vcpu->arch.hv_vapic;
2596 break;
55cd8e5a 2597 default:
a737f256 2598 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2599 return 1;
2600 }
2601 *pdata = data;
2602 return 0;
2603}
2604
609e36d3 2605int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae
HY		 2606{
2607 u64 data;
2608
609e36d3 2609 switch (msr_info->index) {
890ca9ae 2610 case MSR_IA32_PLATFORM_ID:
15c4a640 2611 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2612 case MSR_IA32_DEBUGCTLMSR:
2613 case MSR_IA32_LASTBRANCHFROMIP:
2614 case MSR_IA32_LASTBRANCHTOIP:
2615 case MSR_IA32_LASTINTFROMIP:
2616 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2617 case MSR_K8_SYSCFG:
2618 case MSR_K7_HWCR:
61a6bd67 2619 case MSR_VM_HSAVE_PA:
9e699624 2620 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2621 case MSR_K7_EVNTSEL1:
2622 case MSR_K7_EVNTSEL2:
2623 case MSR_K7_EVNTSEL3:
1f3ee616 2624 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2625 case MSR_K7_PERFCTR1:
2626 case MSR_K7_PERFCTR2:
2627 case MSR_K7_PERFCTR3:
1fdbd48c 2628 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2629 case MSR_AMD64_NB_CFG:
f7c6d140 2630 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2631 case MSR_AMD64_BU_CFG2:
609e36d3 2632 msr_info->data = 0;
15c4a640 2633 break;
5753785f
GN		 2634 case MSR_P6_PERFCTR0:
2635 case MSR_P6_PERFCTR1:
2636 case MSR_P6_EVNTSEL0:
2637 case MSR_P6_EVNTSEL1:
609e36d3
PB		 2638 if (kvm_pmu_msr(vcpu, msr_info->index))
2639 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2640 msr_info->data = 0;
5753785f 2641 break;
742bc670 2642 case MSR_IA32_UCODE_REV:
609e36d3 2643 msr_info->data = 0x100000000ULL;
742bc670 2644 break;
9ba075a6 2645 case MSR_MTRRcap:
609e36d3 2646 msr_info->data = 0x500 | KVM_NR_VAR_MTRR;
9ba075a6
AK		 2647 break;
2648 case 0x200 ... 0x2ff:
609e36d3 2649 return get_msr_mtrr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2650 case 0xcd: /* fsb frequency */
609e36d3 2651 msr_info->data = 3;
15c4a640 2652 break;
7b914098
JS		 2653 /*
2654 * MSR_EBC_FREQUENCY_ID
2655 * Conservative value valid for even the basic CPU models.
2656 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2657 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2658 * and 266MHz for model 3, or 4. Set Core Clock
2659 * Frequency to System Bus Frequency Ratio to 1 (bits
2660 * 31:24) even though these are only valid for CPU
2661 * models > 2, however guests may end up dividing or
2662 * multiplying by zero otherwise.
2663 */
2664 case MSR_EBC_FREQUENCY_ID:
609e36d3 2665 msr_info->data = 1 << 24;
7b914098 2666 break;
15c4a640 2667 case MSR_IA32_APICBASE:
609e36d3 2668 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2669 break;
0105d1a5 2670 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2671 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2672 break;
a3e06bbe 2673 case MSR_IA32_TSCDEADLINE:
609e36d3 2674 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2675 break;
ba904635 2676 case MSR_IA32_TSC_ADJUST:
609e36d3 2677 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2678 break;
15c4a640 2679 case MSR_IA32_MISC_ENABLE:
609e36d3 2680 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2681 break;
847f0ad8
AG		 2682 case MSR_IA32_PERF_STATUS:
2683 /* TSC increment by tick */
609e36d3 2684 msr_info->data = 1000ULL;
847f0ad8
AG		 2685 /* CPU multiplier */
2686 data |= (((uint64_t)4ULL) << 40);
2687 break;
15c4a640 2688 case MSR_EFER:
609e36d3 2689 msr_info->data = vcpu->arch.efer;
15c4a640 2690 break;
18068523 2691 case MSR_KVM_WALL_CLOCK:
11c6bffa 2692 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2693 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2694 break;
2695 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2696 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2697 msr_info->data = vcpu->arch.time;
18068523 2698 break;
344d9588 2699 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2700 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2701 break;
c9aaa895 2702 case MSR_KVM_STEAL_TIME:
609e36d3 2703 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2704 break;
1d92128f 2705 case MSR_KVM_PV_EOI_EN:
609e36d3 2706 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2707 break;
890ca9ae
HY		 2708 case MSR_IA32_P5_MC_ADDR:
2709 case MSR_IA32_P5_MC_TYPE:
2710 case MSR_IA32_MCG_CAP:
2711 case MSR_IA32_MCG_CTL:
2712 case MSR_IA32_MCG_STATUS:
81760dcc 2713 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2714 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2715 case MSR_K7_CLK_CTL:
2716 /*
2717 * Provide expected ramp-up count for K7. All other
2718 * are set to zero, indicating minimum divisors for
2719 * every field.
2720 *
2721 * This prevents guest kernels on AMD host with CPU
2722 * type 6, model 8 and higher from exploding due to
2723 * the rdmsr failing.
2724 */
609e36d3 2725 msr_info->data = 0x20000000;
84e0cefa 2726 break;
55cd8e5a 2727 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
609e36d3 2728 if (kvm_hv_msr_partition_wide(msr_info->index)) {
55cd8e5a
GN		 2729 int r;
2730 mutex_lock(&vcpu->kvm->lock);
609e36d3 2731 r = get_msr_hyperv_pw(vcpu, msr_info->index, &msr_info->data);
55cd8e5a
GN		 2732 mutex_unlock(&vcpu->kvm->lock);
2733 return r;
2734 } else
609e36d3 2735 return get_msr_hyperv(vcpu, msr_info->index, &msr_info->data);
55cd8e5a 2736 break;
91c9c3ed 2737 case MSR_IA32_BBL_CR_CTL3:
2738 /* This legacy MSR exists but isn't fully documented in current
2739 * silicon. It is however accessed by winxp in very narrow
2740 * scenarios where it sets bit #19, itself documented as
2741 * a "reserved" bit. Best effort attempt to source coherent
2742 * read data here should the balance of the register be
2743 * interpreted by the guest:
2744 *
2745 * L2 cache control register 3: 64GB range, 256KB size,
2746 * enabled, latency 0x1, configured
2747 */
609e36d3 2748 msr_info->data = 0xbe702111;
91c9c3ed 2749 break;
2b036c6b
BO		 2750 case MSR_AMD64_OSVW_ID_LENGTH:
2751 if (!guest_cpuid_has_osvw(vcpu))
2752 return 1;
609e36d3 2753 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2754 break;
2755 case MSR_AMD64_OSVW_STATUS:
2756 if (!guest_cpuid_has_osvw(vcpu))
2757 return 1;
609e36d3 2758 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2759 break;
15c4a640 2760 default:
609e36d3
PB		 2761 if (kvm_pmu_msr(vcpu, msr_info->index))
2762 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2763 if (!ignore_msrs) {
609e36d3 2764 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2765 return 1;
2766 } else {
609e36d3
PB		 2767 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2768 msr_info->data = 0;
ed85c068
AP		 2769 }
2770 break;
15c4a640 2771 }
15c4a640
CO		 2772 return 0;
2773}
2774EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2775
313a3dc7
CO		 2776/*
2777 * Read or write a bunch of msrs. All parameters are kernel addresses.
2778 *
2779 * @return number of msrs set successfully.
2780 */
2781static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2782 struct kvm_msr_entry *entries,
2783 int (*do_msr)(struct kvm_vcpu *vcpu,
2784 unsigned index, u64 *data))
2785{
f656ce01 2786 int i, idx;
313a3dc7 2787
f656ce01 2788 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2789 for (i = 0; i < msrs->nmsrs; ++i)
2790 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2791 break;
f656ce01 2792 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2793
313a3dc7
CO		 2794 return i;
2795}
2796
2797/*
2798 * Read or write a bunch of msrs. Parameters are user addresses.
2799 *
2800 * @return number of msrs set successfully.
2801 */
2802static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2803 int (*do_msr)(struct kvm_vcpu *vcpu,
2804 unsigned index, u64 *data),
2805 int writeback)
2806{
2807 struct kvm_msrs msrs;
2808 struct kvm_msr_entry *entries;
2809 int r, n;
2810 unsigned size;
2811
2812 r = -EFAULT;
2813 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2814 goto out;
2815
2816 r = -E2BIG;
2817 if (msrs.nmsrs >= MAX_IO_MSRS)
2818 goto out;
2819
313a3dc7 2820 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2821 entries = memdup_user(user_msrs->entries, size);
2822 if (IS_ERR(entries)) {
2823 r = PTR_ERR(entries);
313a3dc7 2824 goto out;
ff5c2c03 2825 }
313a3dc7
CO		 2826
2827 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2828 if (r < 0)
2829 goto out_free;
2830
2831 r = -EFAULT;
2832 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2833 goto out_free;
2834
2835 r = n;
2836
2837out_free:
7a73c028 2838 kfree(entries);
313a3dc7
CO		 2839out:
2840 return r;
2841}
2842
784aa3d7 2843int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2844{
2845 int r;
2846
2847 switch (ext) {
2848 case KVM_CAP_IRQCHIP:
2849 case KVM_CAP_HLT:
2850 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2851 case KVM_CAP_SET_TSS_ADDR:
07716717 2852 case KVM_CAP_EXT_CPUID:
9c15bb1d 2853 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2854 case KVM_CAP_CLOCKSOURCE:
7837699f 2855 case KVM_CAP_PIT:
a28e4f5a 2856 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2857 case KVM_CAP_MP_STATE:
ed848624 2858 case KVM_CAP_SYNC_MMU:
a355c85c 2859 case KVM_CAP_USER_NMI:
52d939a0 2860 case KVM_CAP_REINJECT_CONTROL:
4925663a 2861 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2862 case KVM_CAP_IOEVENTFD:
f848a5a8 2863 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2864 case KVM_CAP_PIT2:
e9f42757 2865 case KVM_CAP_PIT_STATE2:
b927a3ce 2866 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2867 case KVM_CAP_XEN_HVM:
afbcf7ab 2868 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2869 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2870 case KVM_CAP_HYPERV:
10388a07 2871 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2872 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2873 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2874 case KVM_CAP_DEBUGREGS:
d2be1651 2875 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2876 case KVM_CAP_XSAVE:
344d9588 2877 case KVM_CAP_ASYNC_PF:
92a1f12d 2878 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2879 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2880 case KVM_CAP_READONLY_MEM:
5f66b620 2881 case KVM_CAP_HYPERV_TIME:
100943c5 2882 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2883 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2884 case KVM_CAP_ENABLE_CAP_VM:
2885 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2886#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2887 case KVM_CAP_ASSIGN_DEV_IRQ:
2888 case KVM_CAP_PCI_2_3:
2889#endif
018d00d2
ZX		 2890 r = 1;
2891 break;
542472b5
LV		 2892 case KVM_CAP_COALESCED_MMIO:
2893 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2894 break;
774ead3a
AK		 2895 case KVM_CAP_VAPIC:
2896 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2897 break;
f725230a 2898 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2899 r = KVM_SOFT_MAX_VCPUS;
2900 break;
2901 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2902 r = KVM_MAX_VCPUS;
2903 break;
a988b910 2904 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2905 r = KVM_USER_MEM_SLOTS;
a988b910 2906 break;
a68a6a72
MT		 2907 case KVM_CAP_PV_MMU: /* obsolete */
2908 r = 0;
2f333bcb 2909 break;
4cee4b72 2910#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2911 case KVM_CAP_IOMMU:
a1b60c1c 2912 r = iommu_present(&pci_bus_type);
62c476c7 2913 break;
4cee4b72 2914#endif
890ca9ae
HY		 2915 case KVM_CAP_MCE:
2916 r = KVM_MAX_MCE_BANKS;
2917 break;
2d5b5a66
SY		 2918 case KVM_CAP_XCRS:
2919 r = cpu_has_xsave;
2920 break;
92a1f12d
JR		 2921 case KVM_CAP_TSC_CONTROL:
2922 r = kvm_has_tsc_control;
2923 break;
018d00d2
ZX		 2924 default:
2925 r = 0;
2926 break;
2927 }
2928 return r;
2929
2930}
2931
043405e1
CO		 2932long kvm_arch_dev_ioctl(struct file *filp,
2933 unsigned int ioctl, unsigned long arg)
2934{
2935 void __user *argp = (void __user *)arg;
2936 long r;
2937
2938 switch (ioctl) {
2939 case KVM_GET_MSR_INDEX_LIST: {
2940 struct kvm_msr_list __user *user_msr_list = argp;
2941 struct kvm_msr_list msr_list;
2942 unsigned n;
2943
2944 r = -EFAULT;
2945 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2946 goto out;
2947 n = msr_list.nmsrs;
62ef68bb 2948 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2949 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2950 goto out;
2951 r = -E2BIG;
e125e7b6 2952 if (n < msr_list.nmsrs)
043405e1
CO		 2953 goto out;
2954 r = -EFAULT;
2955 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2956 num_msrs_to_save * sizeof(u32)))
2957 goto out;
e125e7b6 2958 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2959 &emulated_msrs,
62ef68bb 2960 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2961 goto out;
2962 r = 0;
2963 break;
2964 }
9c15bb1d
BP		 2965 case KVM_GET_SUPPORTED_CPUID:
2966 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2967 struct kvm_cpuid2 __user *cpuid_arg = argp;
2968 struct kvm_cpuid2 cpuid;
2969
2970 r = -EFAULT;
2971 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2972 goto out;
9c15bb1d
BP		 2973
2974 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2975 ioctl);
674eea0f
AK		 2976 if (r)
2977 goto out;
2978
2979 r = -EFAULT;
2980 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2981 goto out;
2982 r = 0;
2983 break;
2984 }
890ca9ae
HY		 2985 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2986 u64 mce_cap;
2987
2988 mce_cap = KVM_MCE_CAP_SUPPORTED;
2989 r = -EFAULT;
2990 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2991 goto out;
2992 r = 0;
2993 break;
2994 }
043405e1
CO		 2995 default:
2996 r = -EINVAL;
2997 }
2998out:
2999 return r;
3000}
3001
f5f48ee1
SY		 3002static void wbinvd_ipi(void *garbage)
3003{
3004 wbinvd();
3005}
3006
3007static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3008{
e0f0bbc5 3009 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3010}
3011
313a3dc7
CO		 3012void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3013{
f5f48ee1
SY		 3014 /* Address WBINVD may be executed by guest */
3015 if (need_emulate_wbinvd(vcpu)) {
3016 if (kvm_x86_ops->has_wbinvd_exit())
3017 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3018 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3019 smp_call_function_single(vcpu->cpu,
3020 wbinvd_ipi, NULL, 1);
3021 }
3022
313a3dc7 3023 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3024
0dd6a6ed
ZA		 3025 /* Apply any externally detected TSC adjustments (due to suspend) */
3026 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3027 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3028 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3030 }
8f6055cb 3031
48434c20 3032 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 3033 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3034 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3035 if (tsc_delta < 0)
3036 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 3037 if (check_tsc_unstable()) {
b183aa58
ZA		 3038 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
3039 vcpu->arch.last_guest_tsc);
3040 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 3041 vcpu->arch.tsc_catchup = 1;
c285545f 3042 }
d98d07ca
MT		 3043 /*
3044 * On a host with synchronized TSC, there is no need to update
3045 * kvmclock on vcpu->cpu migration
3046 */
3047 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3048 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 3049 if (vcpu->cpu != cpu)
3050 kvm_migrate_timers(vcpu);
e48672fa 3051 vcpu->cpu = cpu;
6b7d7e76 3052 }
c9aaa895
GC		 3053
3054 accumulate_steal_time(vcpu);
3055 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3056}
3057
3058void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3059{
02daab21 3060 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 3061 kvm_put_guest_fpu(vcpu);
6f526ec5 3062 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 3063}
3064
313a3dc7
CO		 3065static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3066 struct kvm_lapic_state *s)
3067{
5a71785d 3068 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 3069 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 3070
3071 return 0;
3072}
3073
3074static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3075 struct kvm_lapic_state *s)
3076{
64eb0620 3077 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 3078 update_cr8_intercept(vcpu);
313a3dc7
CO		 3079
3080 return 0;
3081}
3082
f77bc6a4
ZX		 3083static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3084 struct kvm_interrupt *irq)
3085{
02cdb50f 3086 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3087 return -EINVAL;
3088 if (irqchip_in_kernel(vcpu->kvm))
3089 return -ENXIO;
f77bc6a4 3090
66fd3f7f 3091 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3092 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3093
f77bc6a4
ZX		 3094 return 0;
3095}
3096
c4abb7c9
JK		 3097static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3098{
c4abb7c9 3099 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3100
3101 return 0;
3102}
3103
b209749f
AK		 3104static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3105 struct kvm_tpr_access_ctl *tac)
3106{
3107 if (tac->flags)
3108 return -EINVAL;
3109 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3110 return 0;
3111}
3112
890ca9ae
HY		 3113static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3114 u64 mcg_cap)
3115{
3116 int r;
3117 unsigned bank_num = mcg_cap & 0xff, bank;
3118
3119 r = -EINVAL;
a9e38c3e 3120 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3121 goto out;
3122 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3123 goto out;
3124 r = 0;
3125 vcpu->arch.mcg_cap = mcg_cap;
3126 /* Init IA32_MCG_CTL to all 1s */
3127 if (mcg_cap & MCG_CTL_P)
3128 vcpu->arch.mcg_ctl = ~(u64)0;
3129 /* Init IA32_MCi_CTL to all 1s */
3130 for (bank = 0; bank < bank_num; bank++)
3131 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3132out:
3133 return r;
3134}
3135
3136static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3137 struct kvm_x86_mce *mce)
3138{
3139 u64 mcg_cap = vcpu->arch.mcg_cap;
3140 unsigned bank_num = mcg_cap & 0xff;
3141 u64 *banks = vcpu->arch.mce_banks;
3142
3143 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3144 return -EINVAL;
3145 /*
3146 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3147 * reporting is disabled
3148 */
3149 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3150 vcpu->arch.mcg_ctl != ~(u64)0)
3151 return 0;
3152 banks += 4 * mce->bank;
3153 /*
3154 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3155 * reporting is disabled for the bank
3156 */
3157 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3158 return 0;
3159 if (mce->status & MCI_STATUS_UC) {
3160 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3161 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3162 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3163 return 0;
3164 }
3165 if (banks[1] & MCI_STATUS_VAL)
3166 mce->status |= MCI_STATUS_OVER;
3167 banks[2] = mce->addr;
3168 banks[3] = mce->misc;
3169 vcpu->arch.mcg_status = mce->mcg_status;
3170 banks[1] = mce->status;
3171 kvm_queue_exception(vcpu, MC_VECTOR);
3172 } else if (!(banks[1] & MCI_STATUS_VAL)
3173 || !(banks[1] & MCI_STATUS_UC)) {
3174 if (banks[1] & MCI_STATUS_VAL)
3175 mce->status |= MCI_STATUS_OVER;
3176 banks[2] = mce->addr;
3177 banks[3] = mce->misc;
3178 banks[1] = mce->status;
3179 } else
3180 banks[1] |= MCI_STATUS_OVER;
3181 return 0;
3182}
3183
3cfc3092
JK		 3184static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3185 struct kvm_vcpu_events *events)
3186{
7460fb4a 3187 process_nmi(vcpu);
03b82a30
JK		 3188 events->exception.injected =
3189 vcpu->arch.exception.pending &&
3190 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3191 events->exception.nr = vcpu->arch.exception.nr;
3192 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3193 events->exception.pad = 0;
3cfc3092
JK		 3194 events->exception.error_code = vcpu->arch.exception.error_code;
3195
03b82a30
JK		 3196 events->interrupt.injected =
3197 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3198 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3199 events->interrupt.soft = 0;
37ccdcbe 3200 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3201
3202 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3203 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3204 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3205 events->nmi.pad = 0;
3cfc3092 3206
66450a21 3207 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3208
dab4b911 3209 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3210 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3211 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3212}
3213
3214static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3215 struct kvm_vcpu_events *events)
3216{
dab4b911 3217 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3218 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3219 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3220 return -EINVAL;
3221
7460fb4a 3222 process_nmi(vcpu);
3cfc3092
JK		 3223 vcpu->arch.exception.pending = events->exception.injected;
3224 vcpu->arch.exception.nr = events->exception.nr;
3225 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3226 vcpu->arch.exception.error_code = events->exception.error_code;
3227
3228 vcpu->arch.interrupt.pending = events->interrupt.injected;
3229 vcpu->arch.interrupt.nr = events->interrupt.nr;
3230 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3231 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3232 kvm_x86_ops->set_interrupt_shadow(vcpu,
3233 events->interrupt.shadow);
3cfc3092
JK		 3234
3235 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3236 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3237 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3238 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3239
66450a21
JK		 3240 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3241 kvm_vcpu_has_lapic(vcpu))
3242 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3243
3842d135
AK		 3244 kvm_make_request(KVM_REQ_EVENT, vcpu);
3245
3cfc3092
JK		 3246 return 0;
3247}
3248
a1efbe77
JK		 3249static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3250 struct kvm_debugregs *dbgregs)
3251{
73aaf249
JK		 3252 unsigned long val;
3253
a1efbe77 3254 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3255 kvm_get_dr(vcpu, 6, &val);
73aaf249 3256 dbgregs->dr6 = val;
a1efbe77
JK		 3257 dbgregs->dr7 = vcpu->arch.dr7;
3258 dbgregs->flags = 0;
97e69aa6 3259 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3260}
3261
3262static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3263 struct kvm_debugregs *dbgregs)
3264{
3265 if (dbgregs->flags)
3266 return -EINVAL;
3267
a1efbe77 3268 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3269 kvm_update_dr0123(vcpu);
a1efbe77 3270 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3271 kvm_update_dr6(vcpu);
a1efbe77 3272 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3273 kvm_update_dr7(vcpu);
a1efbe77 3274
a1efbe77
JK		 3275 return 0;
3276}
3277
df1daba7
PB		 3278#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3279
3280static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3281{
3282 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3283 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3284 u64 valid;
3285
3286 /*
3287 * Copy legacy XSAVE area, to avoid complications with CPUID
3288 * leaves 0 and 1 in the loop below.
3289 */
3290 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3291
3292 /* Set XSTATE_BV */
3293 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3294
3295 /*
3296 * Copy each region from the possibly compacted offset to the
3297 * non-compacted offset.
3298 */
3299 valid = xstate_bv & ~XSTATE_FPSSE;
3300 while (valid) {
3301 u64 feature = valid & -valid;
3302 int index = fls64(feature) - 1;
3303 void *src = get_xsave_addr(xsave, feature);
3304
3305 if (src) {
3306 u32 size, offset, ecx, edx;
3307 cpuid_count(XSTATE_CPUID, index,
3308 &size, &offset, &ecx, &edx);
3309 memcpy(dest + offset, src, size);
3310 }
3311
3312 valid -= feature;
3313 }
3314}
3315
3316static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3317{
3318 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3319 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3320 u64 valid;
3321
3322 /*
3323 * Copy legacy XSAVE area, to avoid complications with CPUID
3324 * leaves 0 and 1 in the loop below.
3325 */
3326 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3327
3328 /* Set XSTATE_BV and possibly XCOMP_BV. */
3329 xsave->xsave_hdr.xstate_bv = xstate_bv;
3330 if (cpu_has_xsaves)
3331 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3332
3333 /*
3334 * Copy each region from the non-compacted offset to the
3335 * possibly compacted offset.
3336 */
3337 valid = xstate_bv & ~XSTATE_FPSSE;
3338 while (valid) {
3339 u64 feature = valid & -valid;
3340 int index = fls64(feature) - 1;
3341 void *dest = get_xsave_addr(xsave, feature);
3342
3343 if (dest) {
3344 u32 size, offset, ecx, edx;
3345 cpuid_count(XSTATE_CPUID, index,
3346 &size, &offset, &ecx, &edx);
3347 memcpy(dest, src + offset, size);
3348 } else
3349 WARN_ON_ONCE(1);
3350
3351 valid -= feature;
3352 }
3353}
3354
2d5b5a66
SY		 3355static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3356 struct kvm_xsave *guest_xsave)
3357{
4344ee98 3358 if (cpu_has_xsave) {
df1daba7
PB		 3359 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3360 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3361 } else {
2d5b5a66
SY		 3362 memcpy(guest_xsave->region,
3363 &vcpu->arch.guest_fpu.state->fxsave,
3364 sizeof(struct i387_fxsave_struct));
3365 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3366 XSTATE_FPSSE;
3367 }
3368}
3369
3370static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3371 struct kvm_xsave *guest_xsave)
3372{
3373 u64 xstate_bv =
3374 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3375
d7876f1b
PB		 3376 if (cpu_has_xsave) {
3377 /*
3378 * Here we allow setting states that are not present in
3379 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3380 * with old userspace.
3381 */
4ff41732 3382 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3383 return -EINVAL;
df1daba7 3384 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3385 } else {
2d5b5a66
SY		 3386 if (xstate_bv & ~XSTATE_FPSSE)
3387 return -EINVAL;
3388 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3389 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3390 }
3391 return 0;
3392}
3393
3394static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3395 struct kvm_xcrs *guest_xcrs)
3396{
3397 if (!cpu_has_xsave) {
3398 guest_xcrs->nr_xcrs = 0;
3399 return;
3400 }
3401
3402 guest_xcrs->nr_xcrs = 1;
3403 guest_xcrs->flags = 0;
3404 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3405 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3406}
3407
3408static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3409 struct kvm_xcrs *guest_xcrs)
3410{
3411 int i, r = 0;
3412
3413 if (!cpu_has_xsave)
3414 return -EINVAL;
3415
3416 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3417 return -EINVAL;
3418
3419 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3420 /* Only support XCR0 currently */
c67a04cb 3421 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3422 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3423 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3424 break;
3425 }
3426 if (r)
3427 r = -EINVAL;
3428 return r;
3429}
3430
1c0b28c2
EM		 3431/*
3432 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3433 * stopped by the hypervisor. This function will be called from the host only.
3434 * EINVAL is returned when the host attempts to set the flag for a guest that
3435 * does not support pv clocks.
3436 */
3437static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3438{
0b79459b 3439 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3440 return -EINVAL;
51d59c6b 3441 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3442 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3443 return 0;
3444}
3445
313a3dc7
CO		 3446long kvm_arch_vcpu_ioctl(struct file *filp,
3447 unsigned int ioctl, unsigned long arg)
3448{
3449 struct kvm_vcpu *vcpu = filp->private_data;
3450 void __user *argp = (void __user *)arg;
3451 int r;
d1ac91d8
AK		 3452 union {
3453 struct kvm_lapic_state *lapic;
3454 struct kvm_xsave *xsave;
3455 struct kvm_xcrs *xcrs;
3456 void *buffer;
3457 } u;
3458
3459 u.buffer = NULL;
313a3dc7
CO		 3460 switch (ioctl) {
3461 case KVM_GET_LAPIC: {
2204ae3c
MT		 3462 r = -EINVAL;
3463 if (!vcpu->arch.apic)
3464 goto out;
d1ac91d8 3465 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3466
b772ff36 3467 r = -ENOMEM;
d1ac91d8 3468 if (!u.lapic)
b772ff36 3469 goto out;
d1ac91d8 3470 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3471 if (r)
3472 goto out;
3473 r = -EFAULT;
d1ac91d8 3474 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3475 goto out;
3476 r = 0;
3477 break;
3478 }
3479 case KVM_SET_LAPIC: {
2204ae3c
MT		 3480 r = -EINVAL;
3481 if (!vcpu->arch.apic)
3482 goto out;
ff5c2c03 3483 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3484 if (IS_ERR(u.lapic))
3485 return PTR_ERR(u.lapic);
ff5c2c03 3486
d1ac91d8 3487 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3488 break;
3489 }
f77bc6a4
ZX		 3490 case KVM_INTERRUPT: {
3491 struct kvm_interrupt irq;
3492
3493 r = -EFAULT;
3494 if (copy_from_user(&irq, argp, sizeof irq))
3495 goto out;
3496 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3497 break;
3498 }
c4abb7c9
JK		 3499 case KVM_NMI: {
3500 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3501 break;
3502 }
313a3dc7
CO		 3503 case KVM_SET_CPUID: {
3504 struct kvm_cpuid __user *cpuid_arg = argp;
3505 struct kvm_cpuid cpuid;
3506
3507 r = -EFAULT;
3508 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3509 goto out;
3510 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3511 break;
3512 }
07716717
DK		 3513 case KVM_SET_CPUID2: {
3514 struct kvm_cpuid2 __user *cpuid_arg = argp;
3515 struct kvm_cpuid2 cpuid;
3516
3517 r = -EFAULT;
3518 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3519 goto out;
3520 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3521 cpuid_arg->entries);
07716717
DK		 3522 break;
3523 }
3524 case KVM_GET_CPUID2: {
3525 struct kvm_cpuid2 __user *cpuid_arg = argp;
3526 struct kvm_cpuid2 cpuid;
3527
3528 r = -EFAULT;
3529 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3530 goto out;
3531 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3532 cpuid_arg->entries);
07716717
DK		 3533 if (r)
3534 goto out;
3535 r = -EFAULT;
3536 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3537 goto out;
3538 r = 0;
3539 break;
3540 }
313a3dc7 3541 case KVM_GET_MSRS:
609e36d3 3542 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3543 break;
3544 case KVM_SET_MSRS:
3545 r = msr_io(vcpu, argp, do_set_msr, 0);
3546 break;
b209749f
AK		 3547 case KVM_TPR_ACCESS_REPORTING: {
3548 struct kvm_tpr_access_ctl tac;
3549
3550 r = -EFAULT;
3551 if (copy_from_user(&tac, argp, sizeof tac))
3552 goto out;
3553 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3554 if (r)
3555 goto out;
3556 r = -EFAULT;
3557 if (copy_to_user(argp, &tac, sizeof tac))
3558 goto out;
3559 r = 0;
3560 break;
3561 };
b93463aa
AK		 3562 case KVM_SET_VAPIC_ADDR: {
3563 struct kvm_vapic_addr va;
3564
3565 r = -EINVAL;
3566 if (!irqchip_in_kernel(vcpu->kvm))
3567 goto out;
3568 r = -EFAULT;
3569 if (copy_from_user(&va, argp, sizeof va))
3570 goto out;
fda4e2e8 3571 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3572 break;
3573 }
890ca9ae
HY		 3574 case KVM_X86_SETUP_MCE: {
3575 u64 mcg_cap;
3576
3577 r = -EFAULT;
3578 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3579 goto out;
3580 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3581 break;
3582 }
3583 case KVM_X86_SET_MCE: {
3584 struct kvm_x86_mce mce;
3585
3586 r = -EFAULT;
3587 if (copy_from_user(&mce, argp, sizeof mce))
3588 goto out;
3589 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3590 break;
3591 }
3cfc3092
JK		 3592 case KVM_GET_VCPU_EVENTS: {
3593 struct kvm_vcpu_events events;
3594
3595 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3596
3597 r = -EFAULT;
3598 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3599 break;
3600 r = 0;
3601 break;
3602 }
3603 case KVM_SET_VCPU_EVENTS: {
3604 struct kvm_vcpu_events events;
3605
3606 r = -EFAULT;
3607 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3608 break;
3609
3610 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3611 break;
3612 }
a1efbe77
JK		 3613 case KVM_GET_DEBUGREGS: {
3614 struct kvm_debugregs dbgregs;
3615
3616 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3617
3618 r = -EFAULT;
3619 if (copy_to_user(argp, &dbgregs,
3620 sizeof(struct kvm_debugregs)))
3621 break;
3622 r = 0;
3623 break;
3624 }
3625 case KVM_SET_DEBUGREGS: {
3626 struct kvm_debugregs dbgregs;
3627
3628 r = -EFAULT;
3629 if (copy_from_user(&dbgregs, argp,
3630 sizeof(struct kvm_debugregs)))
3631 break;
3632
3633 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3634 break;
3635 }
2d5b5a66 3636 case KVM_GET_XSAVE: {
d1ac91d8 3637 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3638 r = -ENOMEM;
d1ac91d8 3639 if (!u.xsave)
2d5b5a66
SY		 3640 break;
3641
d1ac91d8 3642 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3643
3644 r = -EFAULT;
d1ac91d8 3645 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3646 break;
3647 r = 0;
3648 break;
3649 }
3650 case KVM_SET_XSAVE: {
ff5c2c03 3651 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3652 if (IS_ERR(u.xsave))
3653 return PTR_ERR(u.xsave);
2d5b5a66 3654
d1ac91d8 3655 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3656 break;
3657 }
3658 case KVM_GET_XCRS: {
d1ac91d8 3659 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3660 r = -ENOMEM;
d1ac91d8 3661 if (!u.xcrs)
2d5b5a66
SY		 3662 break;
3663
d1ac91d8 3664 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3665
3666 r = -EFAULT;
d1ac91d8 3667 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3668 sizeof(struct kvm_xcrs)))
3669 break;
3670 r = 0;
3671 break;
3672 }
3673 case KVM_SET_XCRS: {
ff5c2c03 3674 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3675 if (IS_ERR(u.xcrs))
3676 return PTR_ERR(u.xcrs);
2d5b5a66 3677
d1ac91d8 3678 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3679 break;
3680 }
92a1f12d
JR		 3681 case KVM_SET_TSC_KHZ: {
3682 u32 user_tsc_khz;
3683
3684 r = -EINVAL;
92a1f12d
JR		 3685 user_tsc_khz = (u32)arg;
3686
3687 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3688 goto out;
3689
cc578287
ZA		 3690 if (user_tsc_khz == 0)
3691 user_tsc_khz = tsc_khz;
3692
3693 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3694
3695 r = 0;
3696 goto out;
3697 }
3698 case KVM_GET_TSC_KHZ: {
cc578287 3699 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3700 goto out;
3701 }
1c0b28c2
EM		 3702 case KVM_KVMCLOCK_CTRL: {
3703 r = kvm_set_guest_paused(vcpu);
3704 goto out;
3705 }
313a3dc7
CO		 3706 default:
3707 r = -EINVAL;
3708 }
3709out:
d1ac91d8 3710 kfree(u.buffer);
313a3dc7
CO		 3711 return r;
3712}
3713
5b1c1493
CO		 3714int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3715{
3716 return VM_FAULT_SIGBUS;
3717}
3718
1fe779f8
CO		 3719static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3720{
3721 int ret;
3722
3723 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3724 return -EINVAL;
1fe779f8
CO		 3725 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3726 return ret;
3727}
3728
b927a3ce
SY		 3729static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3730 u64 ident_addr)
3731{
3732 kvm->arch.ept_identity_map_addr = ident_addr;
3733 return 0;
3734}
3735
1fe779f8
CO		 3736static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3737 u32 kvm_nr_mmu_pages)
3738{
3739 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3740 return -EINVAL;
3741
79fac95e 3742 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3743
3744 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3745 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3746
79fac95e 3747 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3748 return 0;
3749}
3750
3751static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3752{
39de71ec 3753 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3754}
3755
1fe779f8
CO		 3756static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3757{
3758 int r;
3759
3760 r = 0;
3761 switch (chip->chip_id) {
3762 case KVM_IRQCHIP_PIC_MASTER:
3763 memcpy(&chip->chip.pic,
3764 &pic_irqchip(kvm)->pics[0],
3765 sizeof(struct kvm_pic_state));
3766 break;
3767 case KVM_IRQCHIP_PIC_SLAVE:
3768 memcpy(&chip->chip.pic,
3769 &pic_irqchip(kvm)->pics[1],
3770 sizeof(struct kvm_pic_state));
3771 break;
3772 case KVM_IRQCHIP_IOAPIC:
eba0226b 3773 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3774 break;
3775 default:
3776 r = -EINVAL;
3777 break;
3778 }
3779 return r;
3780}
3781
3782static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3783{
3784 int r;
3785
3786 r = 0;
3787 switch (chip->chip_id) {
3788 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3789 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3790 memcpy(&pic_irqchip(kvm)->pics[0],
3791 &chip->chip.pic,
3792 sizeof(struct kvm_pic_state));
f4f51050 3793 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3794 break;
3795 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3796 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3797 memcpy(&pic_irqchip(kvm)->pics[1],
3798 &chip->chip.pic,
3799 sizeof(struct kvm_pic_state));
f4f51050 3800 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3801 break;
3802 case KVM_IRQCHIP_IOAPIC:
eba0226b 3803 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3804 break;
3805 default:
3806 r = -EINVAL;
3807 break;
3808 }
3809 kvm_pic_update_irq(pic_irqchip(kvm));
3810 return r;
3811}
3812
e0f63cb9
SY		 3813static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3814{
3815 int r = 0;
3816
894a9c55 3817 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3818 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3819 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3820 return r;
3821}
3822
3823static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3824{
3825 int r = 0;
3826
894a9c55 3827 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3828 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3829 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3830 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3831 return r;
3832}
3833
3834static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3835{
3836 int r = 0;
3837
3838 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3839 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3840 sizeof(ps->channels));
3841 ps->flags = kvm->arch.vpit->pit_state.flags;
3842 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3843 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3844 return r;
3845}
3846
3847static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3848{
3849 int r = 0, start = 0;
3850 u32 prev_legacy, cur_legacy;
3851 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3852 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3853 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3854 if (!prev_legacy && cur_legacy)
3855 start = 1;
3856 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3857 sizeof(kvm->arch.vpit->pit_state.channels));
3858 kvm->arch.vpit->pit_state.flags = ps->flags;
3859 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3860 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3861 return r;
3862}
3863
52d939a0
MT		 3864static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3865 struct kvm_reinject_control *control)
3866{
3867 if (!kvm->arch.vpit)
3868 return -ENXIO;
894a9c55 3869 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3870 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3871 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3872 return 0;
3873}
3874
95d4c16c 3875/**
60c34612
TY		 3876 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3877 * @kvm: kvm instance
3878 * @log: slot id and address to which we copy the log
95d4c16c 3879 *
e108ff2f
PB		 3880 * Steps 1-4 below provide general overview of dirty page logging. See
3881 * kvm_get_dirty_log_protect() function description for additional details.
3882 *
3883 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3884 * always flush the TLB (step 4) even if previous step failed and the dirty
3885 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3886 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3887 * writes will be marked dirty for next log read.
95d4c16c 3888 *
60c34612
TY		 3889 * 1. Take a snapshot of the bit and clear it if needed.
3890 * 2. Write protect the corresponding page.
e108ff2f
PB		 3891 * 3. Copy the snapshot to the userspace.
3892 * 4. Flush TLB's if needed.
5bb064dc 3893 */
60c34612 3894int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3895{
60c34612 3896 bool is_dirty = false;
e108ff2f 3897 int r;
5bb064dc 3898
79fac95e 3899 mutex_lock(&kvm->slots_lock);
5bb064dc 3900
88178fd4
KH		 3901 /*
3902 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3903 */
3904 if (kvm_x86_ops->flush_log_dirty)
3905 kvm_x86_ops->flush_log_dirty(kvm);
3906
e108ff2f 3907 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3908
3909 /*
3910 * All the TLBs can be flushed out of mmu lock, see the comments in
3911 * kvm_mmu_slot_remove_write_access().
3912 */
e108ff2f 3913 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3914 if (is_dirty)
3915 kvm_flush_remote_tlbs(kvm);
3916
79fac95e 3917 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3918 return r;
3919}
3920
aa2fbe6d
YZ		 3921int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3922 bool line_status)
23d43cf9
CD		 3923{
3924 if (!irqchip_in_kernel(kvm))
3925 return -ENXIO;
3926
3927 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3928 irq_event->irq, irq_event->level,
3929 line_status);
23d43cf9
CD		 3930 return 0;
3931}
3932
90de4a18
NA		 3933static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3934 struct kvm_enable_cap *cap)
3935{
3936 int r;
3937
3938 if (cap->flags)
3939 return -EINVAL;
3940
3941 switch (cap->cap) {
3942 case KVM_CAP_DISABLE_QUIRKS:
3943 kvm->arch.disabled_quirks = cap->args[0];
3944 r = 0;
3945 break;
3946 default:
3947 r = -EINVAL;
3948 break;
3949 }
3950 return r;
3951}
3952
1fe779f8
CO		 3953long kvm_arch_vm_ioctl(struct file *filp,
3954 unsigned int ioctl, unsigned long arg)
3955{
3956 struct kvm *kvm = filp->private_data;
3957 void __user *argp = (void __user *)arg;
367e1319 3958 int r = -ENOTTY;
f0d66275
DH		 3959 /*
3960 * This union makes it completely explicit to gcc-3.x
3961 * that these two variables' stack usage should be
3962 * combined, not added together.
3963 */
3964 union {
3965 struct kvm_pit_state ps;
e9f42757 3966 struct kvm_pit_state2 ps2;
c5ff41ce 3967 struct kvm_pit_config pit_config;
f0d66275 3968 } u;
1fe779f8
CO		 3969
3970 switch (ioctl) {
3971 case KVM_SET_TSS_ADDR:
3972 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3973 break;
b927a3ce
SY		 3974 case KVM_SET_IDENTITY_MAP_ADDR: {
3975 u64 ident_addr;
3976
3977 r = -EFAULT;
3978 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3979 goto out;
3980 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3981 break;
3982 }
1fe779f8
CO		 3983 case KVM_SET_NR_MMU_PAGES:
3984 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3985 break;
3986 case KVM_GET_NR_MMU_PAGES:
3987 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3988 break;
3ddea128
MT		 3989 case KVM_CREATE_IRQCHIP: {
3990 struct kvm_pic *vpic;
3991
3992 mutex_lock(&kvm->lock);
3993 r = -EEXIST;
3994 if (kvm->arch.vpic)
3995 goto create_irqchip_unlock;
3e515705
AK		 3996 r = -EINVAL;
3997 if (atomic_read(&kvm->online_vcpus))
3998 goto create_irqchip_unlock;
1fe779f8 3999 r = -ENOMEM;
3ddea128
MT		 4000 vpic = kvm_create_pic(kvm);
4001 if (vpic) {
1fe779f8
CO		 4002 r = kvm_ioapic_init(kvm);
4003 if (r) {
175504cd 4004 mutex_lock(&kvm->slots_lock);
72bb2fcd 4005 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 4006 &vpic->dev_master);
4007 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
4008 &vpic->dev_slave);
4009 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
4010 &vpic->dev_eclr);
175504cd 4011 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 4012 kfree(vpic);
4013 goto create_irqchip_unlock;
1fe779f8
CO		 4014 }
4015 } else
3ddea128
MT		 4016 goto create_irqchip_unlock;
4017 smp_wmb();
4018 kvm->arch.vpic = vpic;
4019 smp_wmb();
399ec807
AK		 4020 r = kvm_setup_default_irq_routing(kvm);
4021 if (r) {
175504cd 4022 mutex_lock(&kvm->slots_lock);
3ddea128 4023 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 4024 kvm_ioapic_destroy(kvm);
4025 kvm_destroy_pic(kvm);
3ddea128 4026 mutex_unlock(&kvm->irq_lock);
175504cd 4027 mutex_unlock(&kvm->slots_lock);
399ec807 4028 }
3ddea128
MT		 4029 create_irqchip_unlock:
4030 mutex_unlock(&kvm->lock);
1fe779f8 4031 break;
3ddea128 4032 }
7837699f 4033 case KVM_CREATE_PIT:
c5ff41ce
JK		 4034 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4035 goto create_pit;
4036 case KVM_CREATE_PIT2:
4037 r = -EFAULT;
4038 if (copy_from_user(&u.pit_config, argp,
4039 sizeof(struct kvm_pit_config)))
4040 goto out;
4041 create_pit:
79fac95e 4042 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 4043 r = -EEXIST;
4044 if (kvm->arch.vpit)
4045 goto create_pit_unlock;
7837699f 4046 r = -ENOMEM;
c5ff41ce 4047 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4048 if (kvm->arch.vpit)
4049 r = 0;
269e05e4 4050 create_pit_unlock:
79fac95e 4051 mutex_unlock(&kvm->slots_lock);
7837699f 4052 break;
1fe779f8
CO		 4053 case KVM_GET_IRQCHIP: {
4054 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4055 struct kvm_irqchip *chip;
1fe779f8 4056
ff5c2c03
SL		 4057 chip = memdup_user(argp, sizeof(*chip));
4058 if (IS_ERR(chip)) {
4059 r = PTR_ERR(chip);
1fe779f8 4060 goto out;
ff5c2c03
SL		 4061 }
4062
1fe779f8
CO		 4063 r = -ENXIO;
4064 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4065 goto get_irqchip_out;
4066 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4067 if (r)
f0d66275 4068 goto get_irqchip_out;
1fe779f8 4069 r = -EFAULT;
f0d66275
DH		 4070 if (copy_to_user(argp, chip, sizeof *chip))
4071 goto get_irqchip_out;
1fe779f8 4072 r = 0;
f0d66275
DH		 4073 get_irqchip_out:
4074 kfree(chip);
1fe779f8
CO		 4075 break;
4076 }
4077 case KVM_SET_IRQCHIP: {
4078 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4079 struct kvm_irqchip *chip;
1fe779f8 4080
ff5c2c03
SL		 4081 chip = memdup_user(argp, sizeof(*chip));
4082 if (IS_ERR(chip)) {
4083 r = PTR_ERR(chip);
1fe779f8 4084 goto out;
ff5c2c03
SL		 4085 }
4086
1fe779f8
CO		 4087 r = -ENXIO;
4088 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4089 goto set_irqchip_out;
4090 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4091 if (r)
f0d66275 4092 goto set_irqchip_out;
1fe779f8 4093 r = 0;
f0d66275
DH		 4094 set_irqchip_out:
4095 kfree(chip);
1fe779f8
CO		 4096 break;
4097 }
e0f63cb9 4098 case KVM_GET_PIT: {
e0f63cb9 4099 r = -EFAULT;
f0d66275 4100 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4101 goto out;
4102 r = -ENXIO;
4103 if (!kvm->arch.vpit)
4104 goto out;
f0d66275 4105 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4106 if (r)
4107 goto out;
4108 r = -EFAULT;
f0d66275 4109 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4110 goto out;
4111 r = 0;
4112 break;
4113 }
4114 case KVM_SET_PIT: {
e0f63cb9 4115 r = -EFAULT;
f0d66275 4116 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4117 goto out;
4118 r = -ENXIO;
4119 if (!kvm->arch.vpit)
4120 goto out;
f0d66275 4121 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4122 break;
4123 }
e9f42757
BK		 4124 case KVM_GET_PIT2: {
4125 r = -ENXIO;
4126 if (!kvm->arch.vpit)
4127 goto out;
4128 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4129 if (r)
4130 goto out;
4131 r = -EFAULT;
4132 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4133 goto out;
4134 r = 0;
4135 break;
4136 }
4137 case KVM_SET_PIT2: {
4138 r = -EFAULT;
4139 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4140 goto out;
4141 r = -ENXIO;
4142 if (!kvm->arch.vpit)
4143 goto out;
4144 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4145 break;
4146 }
52d939a0
MT		 4147 case KVM_REINJECT_CONTROL: {
4148 struct kvm_reinject_control control;
4149 r = -EFAULT;
4150 if (copy_from_user(&control, argp, sizeof(control)))
4151 goto out;
4152 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4153 break;
4154 }
ffde22ac
ES		 4155 case KVM_XEN_HVM_CONFIG: {
4156 r = -EFAULT;
4157 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4158 sizeof(struct kvm_xen_hvm_config)))
4159 goto out;
4160 r = -EINVAL;
4161 if (kvm->arch.xen_hvm_config.flags)
4162 goto out;
4163 r = 0;
4164 break;
4165 }
afbcf7ab 4166 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4167 struct kvm_clock_data user_ns;
4168 u64 now_ns;
4169 s64 delta;
4170
4171 r = -EFAULT;
4172 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4173 goto out;
4174
4175 r = -EINVAL;
4176 if (user_ns.flags)
4177 goto out;
4178
4179 r = 0;
395c6b0a 4180 local_irq_disable();
759379dd 4181 now_ns = get_kernel_ns();
afbcf7ab 4182 delta = user_ns.clock - now_ns;
395c6b0a 4183 local_irq_enable();
afbcf7ab 4184 kvm->arch.kvmclock_offset = delta;
2e762ff7 4185 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4186 break;
4187 }
4188 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4189 struct kvm_clock_data user_ns;
4190 u64 now_ns;
4191
395c6b0a 4192 local_irq_disable();
759379dd 4193 now_ns = get_kernel_ns();
afbcf7ab 4194 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4195 local_irq_enable();
afbcf7ab 4196 user_ns.flags = 0;
97e69aa6 4197 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4198
4199 r = -EFAULT;
4200 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4201 goto out;
4202 r = 0;
4203 break;
4204 }
90de4a18
NA		 4205 case KVM_ENABLE_CAP: {
4206 struct kvm_enable_cap cap;
afbcf7ab 4207
90de4a18
NA		 4208 r = -EFAULT;
4209 if (copy_from_user(&cap, argp, sizeof(cap)))
4210 goto out;
4211 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4212 break;
4213 }
1fe779f8 4214 default:
c274e03a 4215 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4216 }
4217out:
4218 return r;
4219}
4220
a16b043c 4221static void kvm_init_msr_list(void)
043405e1
CO		 4222{
4223 u32 dummy[2];
4224 unsigned i, j;
4225
62ef68bb 4226 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4227 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4228 continue;
93c4adc7
PB		 4229
4230 /*
4231 * Even MSRs that are valid in the host may not be exposed
4232 * to the guests in some cases. We could work around this
4233 * in VMX with the generic MSR save/load machinery, but it
4234 * is not really worthwhile since it will really only
4235 * happen with nested virtualization.
4236 */
4237 switch (msrs_to_save[i]) {
4238 case MSR_IA32_BNDCFGS:
4239 if (!kvm_x86_ops->mpx_supported())
4240 continue;
4241 break;
4242 default:
4243 break;
4244 }
4245
043405e1
CO		 4246 if (j < i)
4247 msrs_to_save[j] = msrs_to_save[i];
4248 j++;
4249 }
4250 num_msrs_to_save = j;
62ef68bb
PB		 4251
4252 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4253 switch (emulated_msrs[i]) {
4254 default:
4255 break;
4256 }
4257
4258 if (j < i)
4259 emulated_msrs[j] = emulated_msrs[i];
4260 j++;
4261 }
4262 num_emulated_msrs = j;
043405e1
CO		 4263}
4264
bda9020e
MT		 4265static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4266 const void *v)
bbd9b64e 4267{
70252a10
AK		 4268 int handled = 0;
4269 int n;
4270
4271 do {
4272 n = min(len, 8);
4273 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4274 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4275 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4276 break;
4277 handled += n;
4278 addr += n;
4279 len -= n;
4280 v += n;
4281 } while (len);
bbd9b64e 4282
70252a10 4283 return handled;
bbd9b64e
CO		 4284}
4285
bda9020e 4286static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4287{
70252a10
AK		 4288 int handled = 0;
4289 int n;
4290
4291 do {
4292 n = min(len, 8);
4293 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4294 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4295 addr, n, v))
4296 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4297 break;
4298 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4299 handled += n;
4300 addr += n;
4301 len -= n;
4302 v += n;
4303 } while (len);
bbd9b64e 4304
70252a10 4305 return handled;
bbd9b64e
CO		 4306}
4307
2dafc6c2
GN		 4308static void kvm_set_segment(struct kvm_vcpu *vcpu,
4309 struct kvm_segment *var, int seg)
4310{
4311 kvm_x86_ops->set_segment(vcpu, var, seg);
4312}
4313
4314void kvm_get_segment(struct kvm_vcpu *vcpu,
4315 struct kvm_segment *var, int seg)
4316{
4317 kvm_x86_ops->get_segment(vcpu, var, seg);
4318}
4319
54987b7a
PB		 4320gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4321 struct x86_exception *exception)
02f59dc9
JR		 4322{
4323 gpa_t t_gpa;
02f59dc9
JR		 4324
4325 BUG_ON(!mmu_is_nested(vcpu));
4326
4327 /* NPT walks are always user-walks */
4328 access |= PFERR_USER_MASK;
54987b7a 4329 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4330
4331 return t_gpa;
4332}
4333
ab9ae313
AK		 4334gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4335 struct x86_exception *exception)
1871c602
GN		 4336{
4337 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4338 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4339}
4340
ab9ae313
AK		 4341 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4342 struct x86_exception *exception)
1871c602
GN		 4343{
4344 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4345 access |= PFERR_FETCH_MASK;
ab9ae313 4346 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4347}
4348
ab9ae313
AK		 4349gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4350 struct x86_exception *exception)
1871c602
GN		 4351{
4352 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4353 access |= PFERR_WRITE_MASK;
ab9ae313 4354 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4355}
4356
4357/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4358gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4359 struct x86_exception *exception)
1871c602 4360{
ab9ae313 4361 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4362}
4363
4364static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4365 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4366 struct x86_exception *exception)
bbd9b64e
CO		 4367{
4368 void *data = val;
10589a46 4369 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4370
4371 while (bytes) {
14dfe855 4372 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4373 exception);
bbd9b64e 4374 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4375 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4376 int ret;
4377
bcc55cba 4378 if (gpa == UNMAPPED_GVA)
ab9ae313 4379 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4380 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4381 offset, toread);
10589a46 4382 if (ret < 0) {
c3cd7ffa 4383 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4384 goto out;
4385 }
bbd9b64e 4386
77c2002e
IE		 4387 bytes -= toread;
4388 data += toread;
4389 addr += toread;
bbd9b64e 4390 }
10589a46 4391out:
10589a46 4392 return r;
bbd9b64e 4393}
77c2002e 4394
1871c602 4395/* used for instruction fetching */
0f65dd70
AK		 4396static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4397 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4398 struct x86_exception *exception)
1871c602 4399{
0f65dd70 4400 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4401 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4402 unsigned offset;
4403 int ret;
0f65dd70 4404
44583cba
PB		 4405 /* Inline kvm_read_guest_virt_helper for speed. */
4406 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4407 exception);
4408 if (unlikely(gpa == UNMAPPED_GVA))
4409 return X86EMUL_PROPAGATE_FAULT;
4410
4411 offset = addr & (PAGE_SIZE-1);
4412 if (WARN_ON(offset + bytes > PAGE_SIZE))
4413 bytes = (unsigned)PAGE_SIZE - offset;
4414 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4415 offset, bytes);
4416 if (unlikely(ret < 0))
4417 return X86EMUL_IO_NEEDED;
4418
4419 return X86EMUL_CONTINUE;
1871c602
GN		 4420}
4421
064aea77 4422int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4423 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4424 struct x86_exception *exception)
1871c602 4425{
0f65dd70 4426 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4427 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4428
1871c602 4429 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4430 exception);
1871c602 4431}
064aea77 4432EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4433
0f65dd70
AK		 4434static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4435 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4436 struct x86_exception *exception)
1871c602 4437{
0f65dd70 4438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4439 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4440}
4441
6a4d7550 4442int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4443 gva_t addr, void *val,
2dafc6c2 4444 unsigned int bytes,
bcc55cba 4445 struct x86_exception *exception)
77c2002e 4446{
0f65dd70 4447 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4448 void *data = val;
4449 int r = X86EMUL_CONTINUE;
4450
4451 while (bytes) {
14dfe855
JR		 4452 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4453 PFERR_WRITE_MASK,
ab9ae313 4454 exception);
77c2002e
IE		 4455 unsigned offset = addr & (PAGE_SIZE-1);
4456 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4457 int ret;
4458
bcc55cba 4459 if (gpa == UNMAPPED_GVA)
ab9ae313 4460 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4461 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4462 if (ret < 0) {
c3cd7ffa 4463 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4464 goto out;
4465 }
4466
4467 bytes -= towrite;
4468 data += towrite;
4469 addr += towrite;
4470 }
4471out:
4472 return r;
4473}
6a4d7550 4474EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4475
af7cc7d1
XG		 4476static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4477 gpa_t *gpa, struct x86_exception *exception,
4478 bool write)
4479{
97d64b78
AK		 4480 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4481 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4482
97d64b78 4483 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4484 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4485 vcpu->arch.access, access)) {
bebb106a
XG		 4486 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4487 (gva & (PAGE_SIZE - 1));
4f022648 4488 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4489 return 1;
4490 }
4491
af7cc7d1
XG		 4492 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4493
4494 if (*gpa == UNMAPPED_GVA)
4495 return -1;
4496
4497 /* For APIC access vmexit */
4498 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4499 return 1;
4500
4f022648
XG		 4501 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4502 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4503 return 1;
4f022648 4504 }
bebb106a 4505
af7cc7d1
XG		 4506 return 0;
4507}
4508
3200f405 4509int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4510 const void *val, int bytes)
bbd9b64e
CO		 4511{
4512 int ret;
4513
4514 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4515 if (ret < 0)
bbd9b64e 4516 return 0;
f57f2ef5 4517 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4518 return 1;
4519}
4520
77d197b2
XG		 4521struct read_write_emulator_ops {
4522 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4523 int bytes);
4524 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4525 void *val, int bytes);
4526 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4527 int bytes, void *val);
4528 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4529 void *val, int bytes);
4530 bool write;
4531};
4532
4533static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4534{
4535 if (vcpu->mmio_read_completed) {
77d197b2 4536 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4537 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4538 vcpu->mmio_read_completed = 0;
4539 return 1;
4540 }
4541
4542 return 0;
4543}
4544
4545static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4546 void *val, int bytes)
4547{
4548 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4549}
4550
4551static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4552 void *val, int bytes)
4553{
4554 return emulator_write_phys(vcpu, gpa, val, bytes);
4555}
4556
4557static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4558{
4559 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4560 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4561}
4562
4563static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4564 void *val, int bytes)
4565{
4566 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4567 return X86EMUL_IO_NEEDED;
4568}
4569
4570static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4571 void *val, int bytes)
4572{
f78146b0
AK		 4573 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4574
87da7e66 4575 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4576 return X86EMUL_CONTINUE;
4577}
4578
0fbe9b0b 4579static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4580 .read_write_prepare = read_prepare,
4581 .read_write_emulate = read_emulate,
4582 .read_write_mmio = vcpu_mmio_read,
4583 .read_write_exit_mmio = read_exit_mmio,
4584};
4585
0fbe9b0b 4586static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4587 .read_write_emulate = write_emulate,
4588 .read_write_mmio = write_mmio,
4589 .read_write_exit_mmio = write_exit_mmio,
4590 .write = true,
4591};
4592
22388a3c
XG		 4593static int emulator_read_write_onepage(unsigned long addr, void *val,
4594 unsigned int bytes,
4595 struct x86_exception *exception,
4596 struct kvm_vcpu *vcpu,
0fbe9b0b 4597 const struct read_write_emulator_ops *ops)
bbd9b64e 4598{
af7cc7d1
XG		 4599 gpa_t gpa;
4600 int handled, ret;
22388a3c 4601 bool write = ops->write;
f78146b0 4602 struct kvm_mmio_fragment *frag;
10589a46 4603
22388a3c 4604 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4605
af7cc7d1 4606 if (ret < 0)
bbd9b64e 4607 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4608
4609 /* For APIC access vmexit */
af7cc7d1 4610 if (ret)
bbd9b64e
CO		 4611 goto mmio;
4612
22388a3c 4613 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4614 return X86EMUL_CONTINUE;
4615
4616mmio:
4617 /*
4618 * Is this MMIO handled locally?
4619 */
22388a3c 4620 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4621 if (handled == bytes)
bbd9b64e 4622 return X86EMUL_CONTINUE;
bbd9b64e 4623
70252a10
AK		 4624 gpa += handled;
4625 bytes -= handled;
4626 val += handled;
4627
87da7e66
XG		 4628 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4629 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4630 frag->gpa = gpa;
4631 frag->data = val;
4632 frag->len = bytes;
f78146b0 4633 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4634}
4635
52eb5a6d
XL		 4636static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4637 unsigned long addr,
22388a3c
XG		 4638 void *val, unsigned int bytes,
4639 struct x86_exception *exception,
0fbe9b0b 4640 const struct read_write_emulator_ops *ops)
bbd9b64e 4641{
0f65dd70 4642 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4643 gpa_t gpa;
4644 int rc;
4645
4646 if (ops->read_write_prepare &&
4647 ops->read_write_prepare(vcpu, val, bytes))
4648 return X86EMUL_CONTINUE;
4649
4650 vcpu->mmio_nr_fragments = 0;
0f65dd70 4651
bbd9b64e
CO		 4652 /* Crossing a page boundary? */
4653 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4654 int now;
bbd9b64e
CO		 4655
4656 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4657 rc = emulator_read_write_onepage(addr, val, now, exception,
4658 vcpu, ops);
4659
bbd9b64e
CO		 4660 if (rc != X86EMUL_CONTINUE)
4661 return rc;
4662 addr += now;
bac15531
NA		 4663 if (ctxt->mode != X86EMUL_MODE_PROT64)
4664 addr = (u32)addr;
bbd9b64e
CO		 4665 val += now;
4666 bytes -= now;
4667 }
22388a3c 4668
f78146b0
AK		 4669 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4670 vcpu, ops);
4671 if (rc != X86EMUL_CONTINUE)
4672 return rc;
4673
4674 if (!vcpu->mmio_nr_fragments)
4675 return rc;
4676
4677 gpa = vcpu->mmio_fragments[0].gpa;
4678
4679 vcpu->mmio_needed = 1;
4680 vcpu->mmio_cur_fragment = 0;
4681
87da7e66 4682 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4683 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4684 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4685 vcpu->run->mmio.phys_addr = gpa;
4686
4687 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4688}
4689
4690static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4691 unsigned long addr,
4692 void *val,
4693 unsigned int bytes,
4694 struct x86_exception *exception)
4695{
4696 return emulator_read_write(ctxt, addr, val, bytes,
4697 exception, &read_emultor);
4698}
4699
52eb5a6d 4700static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4701 unsigned long addr,
4702 const void *val,
4703 unsigned int bytes,
4704 struct x86_exception *exception)
4705{
4706 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4707 exception, &write_emultor);
bbd9b64e 4708}
bbd9b64e 4709
daea3e73
AK		 4710#define CMPXCHG_TYPE(t, ptr, old, new) \
4711 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4712
4713#ifdef CONFIG_X86_64
4714# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4715#else
4716# define CMPXCHG64(ptr, old, new) \
9749a6c0 4717 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4718#endif
4719
0f65dd70
AK		 4720static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4721 unsigned long addr,
bbd9b64e
CO		 4722 const void *old,
4723 const void *new,
4724 unsigned int bytes,
0f65dd70 4725 struct x86_exception *exception)
bbd9b64e 4726{
0f65dd70 4727 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4728 gpa_t gpa;
4729 struct page *page;
4730 char *kaddr;
4731 bool exchanged;
2bacc55c 4732
daea3e73
AK		 4733 /* guests cmpxchg8b have to be emulated atomically */
4734 if (bytes > 8 || (bytes & (bytes - 1)))
4735 goto emul_write;
10589a46 4736
daea3e73 4737 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4738
daea3e73
AK		 4739 if (gpa == UNMAPPED_GVA ||
4740 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4741 goto emul_write;
2bacc55c 4742
daea3e73
AK		 4743 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4744 goto emul_write;
72dc67a6 4745
daea3e73 4746 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4747 if (is_error_page(page))
c19b8bd6 4748 goto emul_write;
72dc67a6 4749
8fd75e12 4750 kaddr = kmap_atomic(page);
daea3e73
AK		 4751 kaddr += offset_in_page(gpa);
4752 switch (bytes) {
4753 case 1:
4754 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4755 break;
4756 case 2:
4757 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4758 break;
4759 case 4:
4760 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4761 break;
4762 case 8:
4763 exchanged = CMPXCHG64(kaddr, old, new);
4764 break;
4765 default:
4766 BUG();
2bacc55c 4767 }
8fd75e12 4768 kunmap_atomic(kaddr);
daea3e73
AK		 4769 kvm_release_page_dirty(page);
4770
4771 if (!exchanged)
4772 return X86EMUL_CMPXCHG_FAILED;
4773
d3714010 4774 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4775 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4776
4777 return X86EMUL_CONTINUE;
4a5f48f6 4778
3200f405 4779emul_write:
daea3e73 4780 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4781
0f65dd70 4782 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4783}
4784
cf8f70bf
GN		 4785static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4786{
4787 /* TODO: String I/O for in kernel device */
4788 int r;
4789
4790 if (vcpu->arch.pio.in)
e32edf4f 4791 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4792 vcpu->arch.pio.size, pd);
4793 else
e32edf4f 4794 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4795 vcpu->arch.pio.port, vcpu->arch.pio.size,
4796 pd);
4797 return r;
4798}
4799
6f6fbe98
XG		 4800static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4801 unsigned short port, void *val,
4802 unsigned int count, bool in)
cf8f70bf 4803{
cf8f70bf 4804 vcpu->arch.pio.port = port;
6f6fbe98 4805 vcpu->arch.pio.in = in;
7972995b 4806 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4807 vcpu->arch.pio.size = size;
4808
4809 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4810 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4811 return 1;
4812 }
4813
4814 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4815 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4816 vcpu->run->io.size = size;
4817 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4818 vcpu->run->io.count = count;
4819 vcpu->run->io.port = port;
4820
4821 return 0;
4822}
4823
6f6fbe98
XG		 4824static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4825 int size, unsigned short port, void *val,
4826 unsigned int count)
cf8f70bf 4827{
ca1d4a9e 4828 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4829 int ret;
ca1d4a9e 4830
6f6fbe98
XG		 4831 if (vcpu->arch.pio.count)
4832 goto data_avail;
cf8f70bf 4833
6f6fbe98
XG		 4834 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4835 if (ret) {
4836data_avail:
4837 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4838 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4839 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4840 return 1;
4841 }
4842
cf8f70bf
GN		 4843 return 0;
4844}
4845
6f6fbe98
XG		 4846static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4847 int size, unsigned short port,
4848 const void *val, unsigned int count)
4849{
4850 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4851
4852 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4853 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4854 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4855}
4856
bbd9b64e
CO		 4857static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4858{
4859 return kvm_x86_ops->get_segment_base(vcpu, seg);
4860}
4861
3cb16fe7 4862static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4863{
3cb16fe7 4864 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4865}
4866
5cb56059 4867int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4868{
4869 if (!need_emulate_wbinvd(vcpu))
4870 return X86EMUL_CONTINUE;
4871
4872 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4873 int cpu = get_cpu();
4874
4875 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4876 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4877 wbinvd_ipi, NULL, 1);
2eec7343 4878 put_cpu();
f5f48ee1 4879 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4880 } else
4881 wbinvd();
f5f48ee1
SY		 4882 return X86EMUL_CONTINUE;
4883}
5cb56059
JS		 4884
4885int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4886{
4887 kvm_x86_ops->skip_emulated_instruction(vcpu);
4888 return kvm_emulate_wbinvd_noskip(vcpu);
4889}
f5f48ee1
SY		 4890EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4891
5cb56059
JS		 4892
4893
bcaf5cc5
AK		 4894static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4895{
5cb56059 4896 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4897}
4898
52eb5a6d
XL		 4899static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4900 unsigned long *dest)
bbd9b64e 4901{
16f8a6f9 4902 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4903}
4904
52eb5a6d
XL		 4905static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4906 unsigned long value)
bbd9b64e 4907{
338dbc97 4908
717746e3 4909 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4910}
4911
52a46617 4912static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4913{
52a46617 4914 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4915}
4916
717746e3 4917static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4918{
717746e3 4919 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4920 unsigned long value;
4921
4922 switch (cr) {
4923 case 0:
4924 value = kvm_read_cr0(vcpu);
4925 break;
4926 case 2:
4927 value = vcpu->arch.cr2;
4928 break;
4929 case 3:
9f8fe504 4930 value = kvm_read_cr3(vcpu);
52a46617
GN		 4931 break;
4932 case 4:
4933 value = kvm_read_cr4(vcpu);
4934 break;
4935 case 8:
4936 value = kvm_get_cr8(vcpu);
4937 break;
4938 default:
a737f256 4939 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4940 return 0;
4941 }
4942
4943 return value;
4944}
4945
717746e3 4946static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4947{
717746e3 4948 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4949 int res = 0;
4950
52a46617
GN		 4951 switch (cr) {
4952 case 0:
49a9b07e 4953 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4954 break;
4955 case 2:
4956 vcpu->arch.cr2 = val;
4957 break;
4958 case 3:
2390218b 4959 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4960 break;
4961 case 4:
a83b29c6 4962 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4963 break;
4964 case 8:
eea1cff9 4965 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4966 break;
4967 default:
a737f256 4968 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4969 res = -1;
52a46617 4970 }
0f12244f
GN		 4971
4972 return res;
52a46617
GN		 4973}
4974
717746e3 4975static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4976{
717746e3 4977 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4978}
4979
4bff1e86 4980static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4981{
4bff1e86 4982 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4983}
4984
4bff1e86 4985static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4986{
4bff1e86 4987 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4988}
4989
1ac9d0cf
AK		 4990static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4991{
4992 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4993}
4994
4995static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4996{
4997 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4998}
4999
4bff1e86
AK		 5000static unsigned long emulator_get_cached_segment_base(
5001 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5002{
4bff1e86 5003 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5004}
5005
1aa36616
AK		 5006static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5007 struct desc_struct *desc, u32 *base3,
5008 int seg)
2dafc6c2
GN		 5009{
5010 struct kvm_segment var;
5011
4bff1e86 5012 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5013 *selector = var.selector;
2dafc6c2 5014
378a8b09
GN		 5015 if (var.unusable) {
5016 memset(desc, 0, sizeof(*desc));
2dafc6c2 5017 return false;
378a8b09 5018 }
2dafc6c2
GN		 5019
5020 if (var.g)
5021 var.limit >>= 12;
5022 set_desc_limit(desc, var.limit);
5023 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5024#ifdef CONFIG_X86_64
5025 if (base3)
5026 *base3 = var.base >> 32;
5027#endif
2dafc6c2
GN		 5028 desc->type = var.type;
5029 desc->s = var.s;
5030 desc->dpl = var.dpl;
5031 desc->p = var.present;
5032 desc->avl = var.avl;
5033 desc->l = var.l;
5034 desc->d = var.db;
5035 desc->g = var.g;
5036
5037 return true;
5038}
5039
1aa36616
AK		 5040static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5041 struct desc_struct *desc, u32 base3,
5042 int seg)
2dafc6c2 5043{
4bff1e86 5044 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5045 struct kvm_segment var;
5046
1aa36616 5047 var.selector = selector;
2dafc6c2 5048 var.base = get_desc_base(desc);
5601d05b
GN		 5049#ifdef CONFIG_X86_64
5050 var.base |= ((u64)base3) << 32;
5051#endif
2dafc6c2
GN		 5052 var.limit = get_desc_limit(desc);
5053 if (desc->g)
5054 var.limit = (var.limit << 12) | 0xfff;
5055 var.type = desc->type;
2dafc6c2
GN		 5056 var.dpl = desc->dpl;
5057 var.db = desc->d;
5058 var.s = desc->s;
5059 var.l = desc->l;
5060 var.g = desc->g;
5061 var.avl = desc->avl;
5062 var.present = desc->p;
5063 var.unusable = !var.present;
5064 var.padding = 0;
5065
5066 kvm_set_segment(vcpu, &var, seg);
5067 return;
5068}
5069
717746e3
AK		 5070static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5071 u32 msr_index, u64 *pdata)
5072{
609e36d3
PB		 5073 struct msr_data msr;
5074 int r;
5075
5076 msr.index = msr_index;
5077 msr.host_initiated = false;
5078 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5079 if (r)
5080 return r;
5081
5082 *pdata = msr.data;
5083 return 0;
717746e3
AK		 5084}
5085
5086static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5087 u32 msr_index, u64 data)
5088{
8fe8ab46
WA		 5089 struct msr_data msr;
5090
5091 msr.data = data;
5092 msr.index = msr_index;
5093 msr.host_initiated = false;
5094 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5095}
5096
67f4d428
NA		 5097static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5098 u32 pmc)
5099{
5100 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
5101}
5102
222d21aa
AK		 5103static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5104 u32 pmc, u64 *pdata)
5105{
5106 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
5107}
5108
6c3287f7
AK		 5109static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5110{
5111 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5112}
5113
5037f6f3
AK		 5114static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5115{
5116 preempt_disable();
5197b808 5117 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5118 /*
5119 * CR0.TS may reference the host fpu state, not the guest fpu state,
5120 * so it may be clear at this point.
5121 */
5122 clts();
5123}
5124
5125static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5126{
5127 preempt_enable();
5128}
5129
2953538e 5130static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5131 struct x86_instruction_info *info,
c4f035c6
AK		 5132 enum x86_intercept_stage stage)
5133{
2953538e 5134 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5135}
5136
0017f93a 5137static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5138 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5139{
0017f93a 5140 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5141}
5142
dd856efa
AK		 5143static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5144{
5145 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5146}
5147
5148static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5149{
5150 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5151}
5152
801806d9
NA		 5153static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5154{
5155 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5156}
5157
0225fb50 5158static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5159 .read_gpr = emulator_read_gpr,
5160 .write_gpr = emulator_write_gpr,
1871c602 5161 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5162 .write_std = kvm_write_guest_virt_system,
1871c602 5163 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5164 .read_emulated = emulator_read_emulated,
5165 .write_emulated = emulator_write_emulated,
5166 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5167 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5168 .pio_in_emulated = emulator_pio_in_emulated,
5169 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5170 .get_segment = emulator_get_segment,
5171 .set_segment = emulator_set_segment,
5951c442 5172 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5173 .get_gdt = emulator_get_gdt,
160ce1f1 5174 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5175 .set_gdt = emulator_set_gdt,
5176 .set_idt = emulator_set_idt,
52a46617
GN		 5177 .get_cr = emulator_get_cr,
5178 .set_cr = emulator_set_cr,
9c537244 5179 .cpl = emulator_get_cpl,
35aa5375
GN		 5180 .get_dr = emulator_get_dr,
5181 .set_dr = emulator_set_dr,
717746e3
AK		 5182 .set_msr = emulator_set_msr,
5183 .get_msr = emulator_get_msr,
67f4d428 5184 .check_pmc = emulator_check_pmc,
222d21aa 5185 .read_pmc = emulator_read_pmc,
6c3287f7 5186 .halt = emulator_halt,
bcaf5cc5 5187 .wbinvd = emulator_wbinvd,
d6aa1000 5188 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5189 .get_fpu = emulator_get_fpu,
5190 .put_fpu = emulator_put_fpu,
c4f035c6 5191 .intercept = emulator_intercept,
bdb42f5a 5192 .get_cpuid = emulator_get_cpuid,
801806d9 5193 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5194};
5195
95cb2295
GN		 5196static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5197{
37ccdcbe 5198 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5199 /*
5200 * an sti; sti; sequence only disable interrupts for the first
5201 * instruction. So, if the last instruction, be it emulated or
5202 * not, left the system with the INT_STI flag enabled, it
5203 * means that the last instruction is an sti. We should not
5204 * leave the flag on in this case. The same goes for mov ss
5205 */
37ccdcbe
PB		 5206 if (int_shadow & mask)
5207 mask = 0;
6addfc42 5208 if (unlikely(int_shadow || mask)) {
95cb2295 5209 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5210 if (!mask)
5211 kvm_make_request(KVM_REQ_EVENT, vcpu);
5212 }
95cb2295
GN		 5213}
5214
ef54bcfe 5215static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5216{
5217 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5218 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5219 return kvm_propagate_fault(vcpu, &ctxt->exception);
5220
5221 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5222 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5223 ctxt->exception.error_code);
54b8486f 5224 else
da9cb575 5225 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5226 return false;
54b8486f
GN		 5227}
5228
8ec4722d
MG		 5229static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5230{
adf52235 5231 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5232 int cs_db, cs_l;
5233
8ec4722d
MG		 5234 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5235
adf52235
TY		 5236 ctxt->eflags = kvm_get_rflags(vcpu);
5237 ctxt->eip = kvm_rip_read(vcpu);
5238 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5239 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5240 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5241 cs_db ? X86EMUL_MODE_PROT32 :
5242 X86EMUL_MODE_PROT16;
5243 ctxt->guest_mode = is_guest_mode(vcpu);
5244
dd856efa 5245 init_decode_cache(ctxt);
7ae441ea 5246 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5247}
5248
71f9833b 5249int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5250{
9d74191a 5251 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5252 int ret;
5253
5254 init_emulate_ctxt(vcpu);
5255
9dac77fa
AK		 5256 ctxt->op_bytes = 2;
5257 ctxt->ad_bytes = 2;
5258 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5259 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5260
5261 if (ret != X86EMUL_CONTINUE)
5262 return EMULATE_FAIL;
5263
9dac77fa 5264 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5265 kvm_rip_write(vcpu, ctxt->eip);
5266 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5267
5268 if (irq == NMI_VECTOR)
7460fb4a 5269 vcpu->arch.nmi_pending = 0;
63995653
MG		 5270 else
5271 vcpu->arch.interrupt.pending = false;
5272
5273 return EMULATE_DONE;
5274}
5275EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5276
6d77dbfc
GN		 5277static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5278{
fc3a9157
JR		 5279 int r = EMULATE_DONE;
5280
6d77dbfc
GN		 5281 ++vcpu->stat.insn_emulation_fail;
5282 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5283 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5284 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5285 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5286 vcpu->run->internal.ndata = 0;
5287 r = EMULATE_FAIL;
5288 }
6d77dbfc 5289 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5290
5291 return r;
6d77dbfc
GN		 5292}
5293
93c05d3e 5294static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5295 bool write_fault_to_shadow_pgtable,
5296 int emulation_type)
a6f177ef 5297{
95b3cf69 5298 gpa_t gpa = cr2;
8e3d9d06 5299 pfn_t pfn;
a6f177ef 5300
991eebf9
GN		 5301 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5302 return false;
5303
95b3cf69
XG		 5304 if (!vcpu->arch.mmu.direct_map) {
5305 /*
5306 * Write permission should be allowed since only
5307 * write access need to be emulated.
5308 */
5309 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5310
95b3cf69
XG		 5311 /*
5312 * If the mapping is invalid in guest, let cpu retry
5313 * it to generate fault.
5314 */
5315 if (gpa == UNMAPPED_GVA)
5316 return true;
5317 }
a6f177ef 5318
8e3d9d06
XG		 5319 /*
5320 * Do not retry the unhandleable instruction if it faults on the
5321 * readonly host memory, otherwise it will goto a infinite loop:
5322 * retry instruction -> write #PF -> emulation fail -> retry
5323 * instruction -> ...
5324 */
5325 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5326
5327 /*
5328 * If the instruction failed on the error pfn, it can not be fixed,
5329 * report the error to userspace.
5330 */
5331 if (is_error_noslot_pfn(pfn))
5332 return false;
5333
5334 kvm_release_pfn_clean(pfn);
5335
5336 /* The instructions are well-emulated on direct mmu. */
5337 if (vcpu->arch.mmu.direct_map) {
5338 unsigned int indirect_shadow_pages;
5339
5340 spin_lock(&vcpu->kvm->mmu_lock);
5341 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5342 spin_unlock(&vcpu->kvm->mmu_lock);
5343
5344 if (indirect_shadow_pages)
5345 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5346
a6f177ef 5347 return true;
8e3d9d06 5348 }
a6f177ef 5349
95b3cf69
XG		 5350 /*
5351 * if emulation was due to access to shadowed page table
5352 * and it failed try to unshadow page and re-enter the
5353 * guest to let CPU execute the instruction.
5354 */
5355 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5356
5357 /*
5358 * If the access faults on its page table, it can not
5359 * be fixed by unprotecting shadow page and it should
5360 * be reported to userspace.
5361 */
5362 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5363}
5364
1cb3f3ae
XG		 5365static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5366 unsigned long cr2, int emulation_type)
5367{
5368 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5369 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5370
5371 last_retry_eip = vcpu->arch.last_retry_eip;
5372 last_retry_addr = vcpu->arch.last_retry_addr;
5373
5374 /*
5375 * If the emulation is caused by #PF and it is non-page_table
5376 * writing instruction, it means the VM-EXIT is caused by shadow
5377 * page protected, we can zap the shadow page and retry this
5378 * instruction directly.
5379 *
5380 * Note: if the guest uses a non-page-table modifying instruction
5381 * on the PDE that points to the instruction, then we will unmap
5382 * the instruction and go to an infinite loop. So, we cache the
5383 * last retried eip and the last fault address, if we meet the eip
5384 * and the address again, we can break out of the potential infinite
5385 * loop.
5386 */
5387 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5388
5389 if (!(emulation_type & EMULTYPE_RETRY))
5390 return false;
5391
5392 if (x86_page_table_writing_insn(ctxt))
5393 return false;
5394
5395 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5396 return false;
5397
5398 vcpu->arch.last_retry_eip = ctxt->eip;
5399 vcpu->arch.last_retry_addr = cr2;
5400
5401 if (!vcpu->arch.mmu.direct_map)
5402 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5403
22368028 5404 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5405
5406 return true;
5407}
5408
716d51ab
GN		 5409static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5410static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5411
4a1e10d5
PB		 5412static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5413 unsigned long *db)
5414{
5415 u32 dr6 = 0;
5416 int i;
5417 u32 enable, rwlen;
5418
5419 enable = dr7;
5420 rwlen = dr7 >> 16;
5421 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5422 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5423 dr6 |= (1 << i);
5424 return dr6;
5425}
5426
6addfc42 5427static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5428{
5429 struct kvm_run *kvm_run = vcpu->run;
5430
5431 /*
6addfc42
PB		 5432 * rflags is the old, "raw" value of the flags. The new value has
5433 * not been saved yet.
663f4c61
PB		 5434 *
5435 * This is correct even for TF set by the guest, because "the
5436 * processor will not generate this exception after the instruction
5437 * that sets the TF flag".
5438 */
663f4c61
PB		 5439 if (unlikely(rflags & X86_EFLAGS_TF)) {
5440 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5441 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5442 DR6_RTM;
663f4c61
PB		 5443 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5444 kvm_run->debug.arch.exception = DB_VECTOR;
5445 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5446 *r = EMULATE_USER_EXIT;
5447 } else {
5448 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5449 /*
5450 * "Certain debug exceptions may clear bit 0-3. The
5451 * remaining contents of the DR6 register are never
5452 * cleared by the processor".
5453 */
5454 vcpu->arch.dr6 &= ~15;
6f43ed01 5455 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5456 kvm_queue_exception(vcpu, DB_VECTOR);
5457 }
5458 }
5459}
5460
4a1e10d5
PB		 5461static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5462{
4a1e10d5
PB		 5463 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5464 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5465 struct kvm_run *kvm_run = vcpu->run;
5466 unsigned long eip = kvm_get_linear_rip(vcpu);
5467 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5468 vcpu->arch.guest_debug_dr7,
5469 vcpu->arch.eff_db);
5470
5471 if (dr6 != 0) {
6f43ed01 5472 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5473 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5474 kvm_run->debug.arch.exception = DB_VECTOR;
5475 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5476 *r = EMULATE_USER_EXIT;
5477 return true;
5478 }
5479 }
5480
4161a569
NA		 5481 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5482 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5483 unsigned long eip = kvm_get_linear_rip(vcpu);
5484 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5485 vcpu->arch.dr7,
5486 vcpu->arch.db);
5487
5488 if (dr6 != 0) {
5489 vcpu->arch.dr6 &= ~15;
6f43ed01 5490 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5491 kvm_queue_exception(vcpu, DB_VECTOR);
5492 *r = EMULATE_DONE;
5493 return true;
5494 }
5495 }
5496
5497 return false;
5498}
5499
51d8b661
AP		 5500int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5501 unsigned long cr2,
dc25e89e
AP		 5502 int emulation_type,
5503 void *insn,
5504 int insn_len)
bbd9b64e 5505{
95cb2295 5506 int r;
9d74191a 5507 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5508 bool writeback = true;
93c05d3e 5509 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5510
93c05d3e
XG		 5511 /*
5512 * Clear write_fault_to_shadow_pgtable here to ensure it is
5513 * never reused.
5514 */
5515 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5516 kvm_clear_exception_queue(vcpu);
8d7d8102 5517
571008da 5518 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5519 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5520
5521 /*
5522 * We will reenter on the same instruction since
5523 * we do not set complete_userspace_io. This does not
5524 * handle watchpoints yet, those would be handled in
5525 * the emulate_ops.
5526 */
5527 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5528 return r;
5529
9d74191a
TY		 5530 ctxt->interruptibility = 0;
5531 ctxt->have_exception = false;
e0ad0b47 5532 ctxt->exception.vector = -1;
9d74191a 5533 ctxt->perm_ok = false;
bbd9b64e 5534
b51e974f 5535 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5536
9d74191a 5537 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5538
e46479f8 5539 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5540 ++vcpu->stat.insn_emulation;
1d2887e2 5541 if (r != EMULATION_OK) {
4005996e
AK		 5542 if (emulation_type & EMULTYPE_TRAP_UD)
5543 return EMULATE_FAIL;
991eebf9
GN		 5544 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5545 emulation_type))
bbd9b64e 5546 return EMULATE_DONE;
6d77dbfc
GN		 5547 if (emulation_type & EMULTYPE_SKIP)
5548 return EMULATE_FAIL;
5549 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5550 }
5551 }
5552
ba8afb6b 5553 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5554 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5555 if (ctxt->eflags & X86_EFLAGS_RF)
5556 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5557 return EMULATE_DONE;
5558 }
5559
1cb3f3ae
XG		 5560 if (retry_instruction(ctxt, cr2, emulation_type))
5561 return EMULATE_DONE;
5562
7ae441ea 5563 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5564 changes registers values during IO operation */
7ae441ea
GN		 5565 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5566 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5567 emulator_invalidate_register_cache(ctxt);
7ae441ea 5568 }
4d2179e1 5569
5cd21917 5570restart:
9d74191a 5571 r = x86_emulate_insn(ctxt);
bbd9b64e 5572
775fde86
JR		 5573 if (r == EMULATION_INTERCEPTED)
5574 return EMULATE_DONE;
5575
d2ddd1c4 5576 if (r == EMULATION_FAILED) {
991eebf9
GN		 5577 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5578 emulation_type))
c3cd7ffa
GN		 5579 return EMULATE_DONE;
5580
6d77dbfc 5581 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5582 }
5583
9d74191a 5584 if (ctxt->have_exception) {
d2ddd1c4 5585 r = EMULATE_DONE;
ef54bcfe
PB		 5586 if (inject_emulated_exception(vcpu))
5587 return r;
d2ddd1c4 5588 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5589 if (!vcpu->arch.pio.in) {
5590 /* FIXME: return into emulator if single-stepping. */
3457e419 5591 vcpu->arch.pio.count = 0;
0912c977 5592 } else {
7ae441ea 5593 writeback = false;
716d51ab
GN		 5594 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5595 }
ac0a48c3 5596 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5597 } else if (vcpu->mmio_needed) {
5598 if (!vcpu->mmio_is_write)
5599 writeback = false;
ac0a48c3 5600 r = EMULATE_USER_EXIT;
716d51ab 5601 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5602 } else if (r == EMULATION_RESTART)
5cd21917 5603 goto restart;
d2ddd1c4
GN		 5604 else
5605 r = EMULATE_DONE;
f850e2e6 5606
7ae441ea 5607 if (writeback) {
6addfc42 5608 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5609 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5610 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5611 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5612 if (r == EMULATE_DONE)
6addfc42 5613 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5614 if (!ctxt->have_exception ||
5615 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5616 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5617
5618 /*
5619 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5620 * do nothing, and it will be requested again as soon as
5621 * the shadow expires. But we still need to check here,
5622 * because POPF has no interrupt shadow.
5623 */
5624 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5625 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5626 } else
5627 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5628
5629 return r;
de7d789a 5630}
51d8b661 5631EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5632
cf8f70bf 5633int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5634{
cf8f70bf 5635 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5636 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5637 size, port, &val, 1);
cf8f70bf 5638 /* do not return to emulator after return from userspace */
7972995b 5639 vcpu->arch.pio.count = 0;
de7d789a
CO		 5640 return ret;
5641}
cf8f70bf 5642EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5643
8cfdc000
ZA		 5644static void tsc_bad(void *info)
5645{
0a3aee0d 5646 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5647}
5648
5649static void tsc_khz_changed(void *data)
c8076604 5650{
8cfdc000
ZA		 5651 struct cpufreq_freqs *freq = data;
5652 unsigned long khz = 0;
5653
5654 if (data)
5655 khz = freq->new;
5656 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5657 khz = cpufreq_quick_get(raw_smp_processor_id());
5658 if (!khz)
5659 khz = tsc_khz;
0a3aee0d 5660 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5661}
5662
c8076604
GH		 5663static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5664 void *data)
5665{
5666 struct cpufreq_freqs *freq = data;
5667 struct kvm *kvm;
5668 struct kvm_vcpu *vcpu;
5669 int i, send_ipi = 0;
5670
8cfdc000
ZA		 5671 /*
5672 * We allow guests to temporarily run on slowing clocks,
5673 * provided we notify them after, or to run on accelerating
5674 * clocks, provided we notify them before. Thus time never
5675 * goes backwards.
5676 *
5677 * However, we have a problem. We can't atomically update
5678 * the frequency of a given CPU from this function; it is
5679 * merely a notifier, which can be called from any CPU.
5680 * Changing the TSC frequency at arbitrary points in time
5681 * requires a recomputation of local variables related to
5682 * the TSC for each VCPU. We must flag these local variables
5683 * to be updated and be sure the update takes place with the
5684 * new frequency before any guests proceed.
5685 *
5686 * Unfortunately, the combination of hotplug CPU and frequency
5687 * change creates an intractable locking scenario; the order
5688 * of when these callouts happen is undefined with respect to
5689 * CPU hotplug, and they can race with each other. As such,
5690 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5691 * undefined; you can actually have a CPU frequency change take
5692 * place in between the computation of X and the setting of the
5693 * variable. To protect against this problem, all updates of
5694 * the per_cpu tsc_khz variable are done in an interrupt
5695 * protected IPI, and all callers wishing to update the value
5696 * must wait for a synchronous IPI to complete (which is trivial
5697 * if the caller is on the CPU already). This establishes the
5698 * necessary total order on variable updates.
5699 *
5700 * Note that because a guest time update may take place
5701 * anytime after the setting of the VCPU's request bit, the
5702 * correct TSC value must be set before the request. However,
5703 * to ensure the update actually makes it to any guest which
5704 * starts running in hardware virtualization between the set
5705 * and the acquisition of the spinlock, we must also ping the
5706 * CPU after setting the request bit.
5707 *
5708 */
5709
c8076604
GH		 5710 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5711 return 0;
5712 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5713 return 0;
8cfdc000
ZA		 5714
5715 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5716
2f303b74 5717 spin_lock(&kvm_lock);
c8076604 5718 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5719 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5720 if (vcpu->cpu != freq->cpu)
5721 continue;
c285545f 5722 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5723 if (vcpu->cpu != smp_processor_id())
8cfdc000 5724 send_ipi = 1;
c8076604
GH		 5725 }
5726 }
2f303b74 5727 spin_unlock(&kvm_lock);
c8076604
GH		 5728
5729 if (freq->old < freq->new && send_ipi) {
5730 /*
5731 * We upscale the frequency. Must make the guest
5732 * doesn't see old kvmclock values while running with
5733 * the new frequency, otherwise we risk the guest sees
5734 * time go backwards.
5735 *
5736 * In case we update the frequency for another cpu
5737 * (which might be in guest context) send an interrupt
5738 * to kick the cpu out of guest context. Next time
5739 * guest context is entered kvmclock will be updated,
5740 * so the guest will not see stale values.
5741 */
8cfdc000 5742 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5743 }
5744 return 0;
5745}
5746
5747static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5748 .notifier_call = kvmclock_cpufreq_notifier
5749};
5750
5751static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5752 unsigned long action, void *hcpu)
5753{
5754 unsigned int cpu = (unsigned long)hcpu;
5755
5756 switch (action) {
5757 case CPU_ONLINE:
5758 case CPU_DOWN_FAILED:
5759 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5760 break;
5761 case CPU_DOWN_PREPARE:
5762 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5763 break;
5764 }
5765 return NOTIFY_OK;
5766}
5767
5768static struct notifier_block kvmclock_cpu_notifier_block = {
5769 .notifier_call = kvmclock_cpu_notifier,
5770 .priority = -INT_MAX
c8076604
GH		 5771};
5772
b820cc0c
ZA		 5773static void kvm_timer_init(void)
5774{
5775 int cpu;
5776
c285545f 5777 max_tsc_khz = tsc_khz;
460dd42e
SB		 5778
5779 cpu_notifier_register_begin();
b820cc0c 5780 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5781#ifdef CONFIG_CPU_FREQ
5782 struct cpufreq_policy policy;
5783 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5784 cpu = get_cpu();
5785 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5786 if (policy.cpuinfo.max_freq)
5787 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5788 put_cpu();
c285545f 5789#endif
b820cc0c
ZA		 5790 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5791 CPUFREQ_TRANSITION_NOTIFIER);
5792 }
c285545f 5793 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5794 for_each_online_cpu(cpu)
5795 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5796
5797 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5798 cpu_notifier_register_done();
5799
b820cc0c
ZA		 5800}
5801
ff9d07a0
ZY		 5802static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5803
f5132b01 5804int kvm_is_in_guest(void)
ff9d07a0 5805{
086c9855 5806 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5807}
5808
5809static int kvm_is_user_mode(void)
5810{
5811 int user_mode = 3;
dcf46b94 5812
086c9855
AS		 5813 if (__this_cpu_read(current_vcpu))
5814 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5815
ff9d07a0
ZY		 5816 return user_mode != 0;
5817}
5818
5819static unsigned long kvm_get_guest_ip(void)
5820{
5821 unsigned long ip = 0;
dcf46b94 5822
086c9855
AS		 5823 if (__this_cpu_read(current_vcpu))
5824 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5825
ff9d07a0
ZY		 5826 return ip;
5827}
5828
5829static struct perf_guest_info_callbacks kvm_guest_cbs = {
5830 .is_in_guest = kvm_is_in_guest,
5831 .is_user_mode = kvm_is_user_mode,
5832 .get_guest_ip = kvm_get_guest_ip,
5833};
5834
5835void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5836{
086c9855 5837 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5838}
5839EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5840
5841void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5842{
086c9855 5843 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5844}
5845EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5846
ce88decf
XG		 5847static void kvm_set_mmio_spte_mask(void)
5848{
5849 u64 mask;
5850 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5851
5852 /*
5853 * Set the reserved bits and the present bit of an paging-structure
5854 * entry to generate page fault with PFER.RSV = 1.
5855 */
885032b9 5856 /* Mask the reserved physical address bits. */
d1431483 5857 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5858
5859 /* Bit 62 is always reserved for 32bit host. */
5860 mask |= 0x3ull << 62;
5861
5862 /* Set the present bit. */
ce88decf
XG		 5863 mask |= 1ull;
5864
5865#ifdef CONFIG_X86_64
5866 /*
5867 * If reserved bit is not supported, clear the present bit to disable
5868 * mmio page fault.
5869 */
5870 if (maxphyaddr == 52)
5871 mask &= ~1ull;
5872#endif
5873
5874 kvm_mmu_set_mmio_spte_mask(mask);
5875}
5876
16e8d74d
MT		 5877#ifdef CONFIG_X86_64
5878static void pvclock_gtod_update_fn(struct work_struct *work)
5879{
d828199e
MT		 5880 struct kvm *kvm;
5881
5882 struct kvm_vcpu *vcpu;
5883 int i;
5884
2f303b74 5885 spin_lock(&kvm_lock);
d828199e
MT		 5886 list_for_each_entry(kvm, &vm_list, vm_list)
5887 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5888 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5889 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5890 spin_unlock(&kvm_lock);
16e8d74d
MT		 5891}
5892
5893static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5894
5895/*
5896 * Notification about pvclock gtod data update.
5897 */
5898static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5899 void *priv)
5900{
5901 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5902 struct timekeeper *tk = priv;
5903
5904 update_pvclock_gtod(tk);
5905
5906 /* disable master clock if host does not trust, or does not
5907 * use, TSC clocksource
5908 */
5909 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5910 atomic_read(&kvm_guest_has_master_clock) != 0)
5911 queue_work(system_long_wq, &pvclock_gtod_work);
5912
5913 return 0;
5914}
5915
5916static struct notifier_block pvclock_gtod_notifier = {
5917 .notifier_call = pvclock_gtod_notify,
5918};
5919#endif
5920
f8c16bba 5921int kvm_arch_init(void *opaque)
043405e1 5922{
b820cc0c 5923 int r;
6b61edf7 5924 struct kvm_x86_ops *ops = opaque;
f8c16bba 5925
f8c16bba
ZX		 5926 if (kvm_x86_ops) {
5927 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5928 r = -EEXIST;
5929 goto out;
f8c16bba
ZX		 5930 }
5931
5932 if (!ops->cpu_has_kvm_support()) {
5933 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5934 r = -EOPNOTSUPP;
5935 goto out;
f8c16bba
ZX		 5936 }
5937 if (ops->disabled_by_bios()) {
5938 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5939 r = -EOPNOTSUPP;
5940 goto out;
f8c16bba
ZX		 5941 }
5942
013f6a5d
MT		 5943 r = -ENOMEM;
5944 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5945 if (!shared_msrs) {
5946 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5947 goto out;
5948 }
5949
97db56ce
AK		 5950 r = kvm_mmu_module_init();
5951 if (r)
013f6a5d 5952 goto out_free_percpu;
97db56ce 5953
ce88decf 5954 kvm_set_mmio_spte_mask();
97db56ce 5955
f8c16bba 5956 kvm_x86_ops = ops;
920c8377 5957
7b52345e 5958 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5959 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5960
b820cc0c 5961 kvm_timer_init();
c8076604 5962
ff9d07a0
ZY		 5963 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5964
2acf923e
DC		 5965 if (cpu_has_xsave)
5966 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5967
c5cc421b 5968 kvm_lapic_init();
16e8d74d
MT		 5969#ifdef CONFIG_X86_64
5970 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5971#endif
5972
f8c16bba 5973 return 0;
56c6d28a 5974
013f6a5d
MT		 5975out_free_percpu:
5976 free_percpu(shared_msrs);
56c6d28a 5977out:
56c6d28a 5978 return r;
043405e1 5979}
8776e519 5980
f8c16bba
ZX		 5981void kvm_arch_exit(void)
5982{
ff9d07a0
ZY		 5983 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5984
888d256e
JK		 5985 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5986 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5987 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5988 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5989#ifdef CONFIG_X86_64
5990 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5991#endif
f8c16bba 5992 kvm_x86_ops = NULL;
56c6d28a 5993 kvm_mmu_module_exit();
013f6a5d 5994 free_percpu(shared_msrs);
56c6d28a 5995}
f8c16bba 5996
5cb56059 5997int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5998{
5999 ++vcpu->stat.halt_exits;
6000 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 6001 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6002 return 1;
6003 } else {
6004 vcpu->run->exit_reason = KVM_EXIT_HLT;
6005 return 0;
6006 }
6007}
5cb56059
JS		 6008EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6009
6010int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6011{
6012 kvm_x86_ops->skip_emulated_instruction(vcpu);
6013 return kvm_vcpu_halt(vcpu);
6014}
8776e519
HB		 6015EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6016
55cd8e5a
GN		 6017int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
6018{
6019 u64 param, ingpa, outgpa, ret;
6020 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
6021 bool fast, longmode;
55cd8e5a
GN		 6022
6023 /*
6024 * hypercall generates UD from non zero cpl and real mode
6025 * per HYPER-V spec
6026 */
3eeb3288 6027 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 6028 kvm_queue_exception(vcpu, UD_VECTOR);
6029 return 0;
6030 }
6031
a449c7aa 6032 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 6033
6034 if (!longmode) {
ccd46936
GN		 6035 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
6036 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
6037 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
6038 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
6039 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
6040 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 6041 }
6042#ifdef CONFIG_X86_64
6043 else {
6044 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
6045 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
6046 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
6047 }
6048#endif
6049
6050 code = param & 0xffff;
6051 fast = (param >> 16) & 0x1;
6052 rep_cnt = (param >> 32) & 0xfff;
6053 rep_idx = (param >> 48) & 0xfff;
6054
6055 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
6056
c25bc163
GN		 6057 switch (code) {
6058 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
6059 kvm_vcpu_on_spin(vcpu);
6060 break;
6061 default:
6062 res = HV_STATUS_INVALID_HYPERCALL_CODE;
6063 break;
6064 }
55cd8e5a
GN		 6065
6066 ret = res | (((u64)rep_done & 0xfff) << 32);
6067 if (longmode) {
6068 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6069 } else {
6070 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
6071 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
6072 }
6073
6074 return 1;
6075}
6076
6aef266c
SV		 6077/*
6078 * kvm_pv_kick_cpu_op: Kick a vcpu.
6079 *
6080 * @apicid - apicid of vcpu to be kicked.
6081 */
6082static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6083{
24d2166b 6084 struct kvm_lapic_irq lapic_irq;
6aef266c 6085
24d2166b
R		 6086 lapic_irq.shorthand = 0;
6087 lapic_irq.dest_mode = 0;
6088 lapic_irq.dest_id = apicid;
93bbf0b8 6089 lapic_irq.msi_redir_hint = false;
6aef266c 6090
24d2166b 6091 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6092 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6093}
6094
8776e519
HB		 6095int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6096{
6097 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6098 int op_64_bit, r = 1;
8776e519 6099
5cb56059
JS		 6100 kvm_x86_ops->skip_emulated_instruction(vcpu);
6101
55cd8e5a
GN		 6102 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6103 return kvm_hv_hypercall(vcpu);
6104
5fdbf976
MT		 6105 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6106 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6107 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6108 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6109 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6110
229456fc 6111 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6112
a449c7aa
NA		 6113 op_64_bit = is_64_bit_mode(vcpu);
6114 if (!op_64_bit) {
8776e519
HB		 6115 nr &= 0xFFFFFFFF;
6116 a0 &= 0xFFFFFFFF;
6117 a1 &= 0xFFFFFFFF;
6118 a2 &= 0xFFFFFFFF;
6119 a3 &= 0xFFFFFFFF;
6120 }
6121
07708c4a
JK		 6122 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6123 ret = -KVM_EPERM;
6124 goto out;
6125 }
6126
8776e519 6127 switch (nr) {
b93463aa
AK		 6128 case KVM_HC_VAPIC_POLL_IRQ:
6129 ret = 0;
6130 break;
6aef266c
SV		 6131 case KVM_HC_KICK_CPU:
6132 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6133 ret = 0;
6134 break;
8776e519
HB		 6135 default:
6136 ret = -KVM_ENOSYS;
6137 break;
6138 }
07708c4a 6139out:
a449c7aa
NA		 6140 if (!op_64_bit)
6141 ret = (u32)ret;
5fdbf976 6142 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6143 ++vcpu->stat.hypercalls;
2f333bcb 6144 return r;
8776e519
HB		 6145}
6146EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6147
b6785def 6148static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6149{
d6aa1000 6150 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6151 char instruction[3];
5fdbf976 6152 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6153
8776e519 6154 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6155
9d74191a 6156 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6157}
6158
b6c7a5dc
HB		 6159/*
6160 * Check if userspace requested an interrupt window, and that the
6161 * interrupt window is open.
6162 *
6163 * No need to exit to userspace if we already have an interrupt queued.
6164 */
851ba692 6165static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6166{
8061823a 6167 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6168 vcpu->run->request_interrupt_window &&
5df56646 6169 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6170}
6171
851ba692 6172static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6173{
851ba692
AK		 6174 struct kvm_run *kvm_run = vcpu->run;
6175
91586a3b 6176 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6177 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6178 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6179 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6180 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6181 else
b6c7a5dc 6182 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6183 kvm_arch_interrupt_allowed(vcpu) &&
6184 !kvm_cpu_has_interrupt(vcpu) &&
6185 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6186}
6187
95ba8273
GN		 6188static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6189{
6190 int max_irr, tpr;
6191
6192 if (!kvm_x86_ops->update_cr8_intercept)
6193 return;
6194
88c808fd
AK		 6195 if (!vcpu->arch.apic)
6196 return;
6197
8db3baa2
GN		 6198 if (!vcpu->arch.apic->vapic_addr)
6199 max_irr = kvm_lapic_find_highest_irr(vcpu);
6200 else
6201 max_irr = -1;
95ba8273
GN		 6202
6203 if (max_irr != -1)
6204 max_irr >>= 4;
6205
6206 tpr = kvm_lapic_get_cr8(vcpu);
6207
6208 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6209}
6210
b6b8a145 6211static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6212{
b6b8a145
JK		 6213 int r;
6214
95ba8273 6215 /* try to reinject previous events if any */
b59bb7bd 6216 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6217 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6218 vcpu->arch.exception.has_error_code,
6219 vcpu->arch.exception.error_code);
d6e8c854
NA		 6220
6221 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6222 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6223 X86_EFLAGS_RF);
6224
6bdf0662
NA		 6225 if (vcpu->arch.exception.nr == DB_VECTOR &&
6226 (vcpu->arch.dr7 & DR7_GD)) {
6227 vcpu->arch.dr7 &= ~DR7_GD;
6228 kvm_update_dr7(vcpu);
6229 }
6230
b59bb7bd
GN		 6231 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6232 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6233 vcpu->arch.exception.error_code,
6234 vcpu->arch.exception.reinject);
b6b8a145 6235 return 0;
b59bb7bd
GN		 6236 }
6237
95ba8273
GN		 6238 if (vcpu->arch.nmi_injected) {
6239 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6240 return 0;
95ba8273
GN		 6241 }
6242
6243 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6244 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6245 return 0;
6246 }
6247
6248 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6249 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6250 if (r != 0)
6251 return r;
95ba8273
GN		 6252 }
6253
6254 /* try to inject new event if pending */
6255 if (vcpu->arch.nmi_pending) {
6256 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6257 --vcpu->arch.nmi_pending;
95ba8273
GN		 6258 vcpu->arch.nmi_injected = true;
6259 kvm_x86_ops->set_nmi(vcpu);
6260 }
c7c9c56c 6261 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6262 /*
6263 * Because interrupts can be injected asynchronously, we are
6264 * calling check_nested_events again here to avoid a race condition.
6265 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6266 * proposal and current concerns. Perhaps we should be setting
6267 * KVM_REQ_EVENT only on certain events and not unconditionally?
6268 */
6269 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6270 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6271 if (r != 0)
6272 return r;
6273 }
95ba8273 6274 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6275 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6276 false);
6277 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6278 }
6279 }
b6b8a145 6280 return 0;
95ba8273
GN		 6281}
6282
7460fb4a
AK		 6283static void process_nmi(struct kvm_vcpu *vcpu)
6284{
6285 unsigned limit = 2;
6286
6287 /*
6288 * x86 is limited to one NMI running, and one NMI pending after it.
6289 * If an NMI is already in progress, limit further NMIs to just one.
6290 * Otherwise, allow two (and we'll inject the first one immediately).
6291 */
6292 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6293 limit = 1;
6294
6295 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6296 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6297 kvm_make_request(KVM_REQ_EVENT, vcpu);
6298}
6299
3d81bc7e 6300static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6301{
6302 u64 eoi_exit_bitmap[4];
cf9e65b7 6303 u32 tmr[8];
c7c9c56c 6304
3d81bc7e
YZ		 6305 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6306 return;
c7c9c56c
YZ		 6307
6308 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6309 memset(tmr, 0, 32);
c7c9c56c 6310
cf9e65b7 6311 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6312 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6313 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6314}
6315
a70656b6
RK		 6316static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6317{
6318 ++vcpu->stat.tlb_flush;
6319 kvm_x86_ops->tlb_flush(vcpu);
6320}
6321
4256f43f
TC		 6322void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6323{
c24ae0dc
TC		 6324 struct page *page = NULL;
6325
f439ed27
PB		 6326 if (!irqchip_in_kernel(vcpu->kvm))
6327 return;
6328
4256f43f
TC		 6329 if (!kvm_x86_ops->set_apic_access_page_addr)
6330 return;
6331
c24ae0dc 6332 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6333 if (is_error_page(page))
6334 return;
c24ae0dc
TC		 6335 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6336
6337 /*
6338 * Do not pin apic access page in memory, the MMU notifier
6339 * will call us again if it is migrated or swapped out.
6340 */
6341 put_page(page);
4256f43f
TC		 6342}
6343EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6344
fe71557a
TC		 6345void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6346 unsigned long address)
6347{
c24ae0dc
TC		 6348 /*
6349 * The physical address of apic access page is stored in the VMCS.
6350 * Update it when it becomes invalid.
6351 */
6352 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6353 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6354}
6355
9357d939 6356/*
362c698f 6357 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6358 * exiting to the userspace. Otherwise, the value will be returned to the
6359 * userspace.
6360 */
851ba692 6361static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6362{
6363 int r;
6a8b1d13 6364 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6365 vcpu->run->request_interrupt_window;
730dca42 6366 bool req_immediate_exit = false;
b6c7a5dc 6367
3e007509 6368 if (vcpu->requests) {
a8eeb04a 6369 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6370 kvm_mmu_unload(vcpu);
a8eeb04a 6371 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6372 __kvm_migrate_timers(vcpu);
d828199e
MT		 6373 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6374 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6375 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6376 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6377 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6378 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6379 if (unlikely(r))
6380 goto out;
6381 }
a8eeb04a 6382 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6383 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6384 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6385 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6386 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6387 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6388 r = 0;
6389 goto out;
6390 }
a8eeb04a 6391 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6392 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6393 r = 0;
6394 goto out;
6395 }
a8eeb04a 6396 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6397 vcpu->fpu_active = 0;
6398 kvm_x86_ops->fpu_deactivate(vcpu);
6399 }
af585b92
GN		 6400 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6401 /* Page is swapped out. Do synthetic halt */
6402 vcpu->arch.apf.halted = true;
6403 r = 1;
6404 goto out;
6405 }
c9aaa895
GC		 6406 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6407 record_steal_time(vcpu);
7460fb4a
AK		 6408 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6409 process_nmi(vcpu);
f5132b01
GN		 6410 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6411 kvm_handle_pmu_event(vcpu);
6412 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6413 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6414 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6415 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6416 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6417 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6418 }
b93463aa 6419
b463a6f7 6420 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6421 kvm_apic_accept_events(vcpu);
6422 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6423 r = 1;
6424 goto out;
6425 }
6426
b6b8a145
JK		 6427 if (inject_pending_event(vcpu, req_int_win) != 0)
6428 req_immediate_exit = true;
b463a6f7 6429 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6430 else if (vcpu->arch.nmi_pending)
c9a7953f 6431 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6432 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6433 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6434
6435 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6436 /*
6437 * Update architecture specific hints for APIC
6438 * virtual interrupt delivery.
6439 */
6440 if (kvm_x86_ops->hwapic_irr_update)
6441 kvm_x86_ops->hwapic_irr_update(vcpu,
6442 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6443 update_cr8_intercept(vcpu);
6444 kvm_lapic_sync_to_vapic(vcpu);
6445 }
6446 }
6447
d8368af8
AK		 6448 r = kvm_mmu_reload(vcpu);
6449 if (unlikely(r)) {
d905c069 6450 goto cancel_injection;
d8368af8
AK		 6451 }
6452
b6c7a5dc
HB		 6453 preempt_disable();
6454
6455 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6456 if (vcpu->fpu_active)
6457 kvm_load_guest_fpu(vcpu);
2acf923e 6458 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6459
6b7e2d09
XG		 6460 vcpu->mode = IN_GUEST_MODE;
6461
01b71917
MT		 6462 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6463
6b7e2d09
XG		 6464 /* We should set ->mode before check ->requests,
6465 * see the comment in make_all_cpus_request.
6466 */
01b71917 6467 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6468
d94e1dc9 6469 local_irq_disable();
32f88400 6470
6b7e2d09 6471 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6472 || need_resched() || signal_pending(current)) {
6b7e2d09 6473 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6474 smp_wmb();
6c142801
AK		 6475 local_irq_enable();
6476 preempt_enable();
01b71917 6477 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6478 r = 1;
d905c069 6479 goto cancel_injection;
6c142801
AK		 6480 }
6481
d6185f20
NHE		 6482 if (req_immediate_exit)
6483 smp_send_reschedule(vcpu->cpu);
6484
ccf73aaf 6485 __kvm_guest_enter();
b6c7a5dc 6486
42dbaa5a 6487 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6488 set_debugreg(0, 7);
6489 set_debugreg(vcpu->arch.eff_db[0], 0);
6490 set_debugreg(vcpu->arch.eff_db[1], 1);
6491 set_debugreg(vcpu->arch.eff_db[2], 2);
6492 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6493 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6494 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6495 }
b6c7a5dc 6496
229456fc 6497 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6498 wait_lapic_expire(vcpu);
851ba692 6499 kvm_x86_ops->run(vcpu);
b6c7a5dc 6500
c77fb5fe
PB		 6501 /*
6502 * Do this here before restoring debug registers on the host. And
6503 * since we do this before handling the vmexit, a DR access vmexit
6504 * can (a) read the correct value of the debug registers, (b) set
6505 * KVM_DEBUGREG_WONT_EXIT again.
6506 */
6507 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6508 int i;
6509
6510 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6511 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6512 for (i = 0; i < KVM_NR_DB_REGS; i++)
6513 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6514 }
6515
24f1e32c
FW		 6516 /*
6517 * If the guest has used debug registers, at least dr7
6518 * will be disabled while returning to the host.
6519 * If we don't have active breakpoints in the host, we don't
6520 * care about the messed up debug address registers. But if
6521 * we have some of them active, restore the old state.
6522 */
59d8eb53 6523 if (hw_breakpoint_active())
24f1e32c 6524 hw_breakpoint_restore();
42dbaa5a 6525
886b470c
MT		 6526 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6527 native_read_tsc());
1d5f066e 6528
6b7e2d09 6529 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6530 smp_wmb();
a547c6db
YZ		 6531
6532 /* Interrupt is enabled by handle_external_intr() */
6533 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6534
6535 ++vcpu->stat.exits;
6536
6537 /*
6538 * We must have an instruction between local_irq_enable() and
6539 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6540 * the interrupt shadow. The stat.exits increment will do nicely.
6541 * But we need to prevent reordering, hence this barrier():
6542 */
6543 barrier();
6544
6545 kvm_guest_exit();
6546
6547 preempt_enable();
6548
f656ce01 6549 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6550
b6c7a5dc
HB		 6551 /*
6552 * Profile KVM exit RIPs:
6553 */
6554 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6555 unsigned long rip = kvm_rip_read(vcpu);
6556 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6557 }
6558
cc578287
ZA		 6559 if (unlikely(vcpu->arch.tsc_always_catchup))
6560 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6561
5cfb1d5a
MT		 6562 if (vcpu->arch.apic_attention)
6563 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6564
851ba692 6565 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6566 return r;
6567
6568cancel_injection:
6569 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6570 if (unlikely(vcpu->arch.apic_attention))
6571 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6572out:
6573 return r;
6574}
b6c7a5dc 6575
362c698f
PB		 6576static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6577{
9c8fd1ba
PB		 6578 if (!kvm_arch_vcpu_runnable(vcpu)) {
6579 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6580 kvm_vcpu_block(vcpu);
6581 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6582 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6583 return 1;
6584 }
362c698f
PB		 6585
6586 kvm_apic_accept_events(vcpu);
6587 switch(vcpu->arch.mp_state) {
6588 case KVM_MP_STATE_HALTED:
6589 vcpu->arch.pv.pv_unhalted = false;
6590 vcpu->arch.mp_state =
6591 KVM_MP_STATE_RUNNABLE;
6592 case KVM_MP_STATE_RUNNABLE:
6593 vcpu->arch.apf.halted = false;
6594 break;
6595 case KVM_MP_STATE_INIT_RECEIVED:
6596 break;
6597 default:
6598 return -EINTR;
6599 break;
6600 }
6601 return 1;
6602}
09cec754 6603
362c698f 6604static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6605{
6606 int r;
f656ce01 6607 struct kvm *kvm = vcpu->kvm;
d7690175 6608
f656ce01 6609 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6610
362c698f 6611 for (;;) {
af585b92
GN		 6612 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6613 !vcpu->arch.apf.halted)
851ba692 6614 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6615 else
6616 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6617 if (r <= 0)
6618 break;
6619
6620 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6621 if (kvm_cpu_has_pending_timer(vcpu))
6622 kvm_inject_pending_timer_irqs(vcpu);
6623
851ba692 6624 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6625 r = -EINTR;
851ba692 6626 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6627 ++vcpu->stat.request_irq_exits;
362c698f 6628 break;
09cec754 6629 }
af585b92
GN		 6630
6631 kvm_check_async_pf_completion(vcpu);
6632
09cec754
GN		 6633 if (signal_pending(current)) {
6634 r = -EINTR;
851ba692 6635 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6636 ++vcpu->stat.signal_exits;
362c698f 6637 break;
09cec754
GN		 6638 }
6639 if (need_resched()) {
f656ce01 6640 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6641 cond_resched();
f656ce01 6642 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6643 }
b6c7a5dc
HB		 6644 }
6645
f656ce01 6646 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6647
6648 return r;
6649}
6650
716d51ab
GN		 6651static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6652{
6653 int r;
6654 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6655 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6656 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6657 if (r != EMULATE_DONE)
6658 return 0;
6659 return 1;
6660}
6661
6662static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6663{
6664 BUG_ON(!vcpu->arch.pio.count);
6665
6666 return complete_emulated_io(vcpu);
6667}
6668
f78146b0
AK		 6669/*
6670 * Implements the following, as a state machine:
6671 *
6672 * read:
6673 * for each fragment
87da7e66
XG		 6674 * for each mmio piece in the fragment
6675 * write gpa, len
6676 * exit
6677 * copy data
f78146b0
AK		 6678 * execute insn
6679 *
6680 * write:
6681 * for each fragment
87da7e66
XG		 6682 * for each mmio piece in the fragment
6683 * write gpa, len
6684 * copy data
6685 * exit
f78146b0 6686 */
716d51ab 6687static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6688{
6689 struct kvm_run *run = vcpu->run;
f78146b0 6690 struct kvm_mmio_fragment *frag;
87da7e66 6691 unsigned len;
5287f194 6692
716d51ab 6693 BUG_ON(!vcpu->mmio_needed);
5287f194 6694
716d51ab 6695 /* Complete previous fragment */
87da7e66
XG		 6696 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6697 len = min(8u, frag->len);
716d51ab 6698 if (!vcpu->mmio_is_write)
87da7e66
XG		 6699 memcpy(frag->data, run->mmio.data, len);
6700
6701 if (frag->len <= 8) {
6702 /* Switch to the next fragment. */
6703 frag++;
6704 vcpu->mmio_cur_fragment++;
6705 } else {
6706 /* Go forward to the next mmio piece. */
6707 frag->data += len;
6708 frag->gpa += len;
6709 frag->len -= len;
6710 }
6711
a08d3b3b 6712 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6713 vcpu->mmio_needed = 0;
0912c977
PB		 6714
6715 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6716 if (vcpu->mmio_is_write)
716d51ab
GN		 6717 return 1;
6718 vcpu->mmio_read_completed = 1;
6719 return complete_emulated_io(vcpu);
6720 }
87da7e66 6721
716d51ab
GN		 6722 run->exit_reason = KVM_EXIT_MMIO;
6723 run->mmio.phys_addr = frag->gpa;
6724 if (vcpu->mmio_is_write)
87da7e66
XG		 6725 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6726 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6727 run->mmio.is_write = vcpu->mmio_is_write;
6728 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6729 return 0;
5287f194
AK		 6730}
6731
716d51ab 6732
b6c7a5dc
HB		 6733int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6734{
6735 int r;
6736 sigset_t sigsaved;
6737
e5c30142
AK		 6738 if (!tsk_used_math(current) && init_fpu(current))
6739 return -ENOMEM;
6740
ac9f6dc0
AK		 6741 if (vcpu->sigset_active)
6742 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6743
a4535290 6744 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6745 kvm_vcpu_block(vcpu);
66450a21 6746 kvm_apic_accept_events(vcpu);
d7690175 6747 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6748 r = -EAGAIN;
6749 goto out;
b6c7a5dc
HB		 6750 }
6751
b6c7a5dc 6752 /* re-sync apic's tpr */
eea1cff9
AP		 6753 if (!irqchip_in_kernel(vcpu->kvm)) {
6754 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6755 r = -EINVAL;
6756 goto out;
6757 }
6758 }
b6c7a5dc 6759
716d51ab
GN		 6760 if (unlikely(vcpu->arch.complete_userspace_io)) {
6761 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6762 vcpu->arch.complete_userspace_io = NULL;
6763 r = cui(vcpu);
6764 if (r <= 0)
6765 goto out;
6766 } else
6767 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6768
362c698f 6769 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6770
6771out:
f1d86e46 6772 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6773 if (vcpu->sigset_active)
6774 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6775
b6c7a5dc
HB		 6776 return r;
6777}
6778
6779int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6780{
7ae441ea
GN		 6781 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6782 /*
6783 * We are here if userspace calls get_regs() in the middle of
6784 * instruction emulation. Registers state needs to be copied
4a969980 6785 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6786 * that usually, but some bad designed PV devices (vmware
6787 * backdoor interface) need this to work
6788 */
dd856efa 6789 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6790 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6791 }
5fdbf976
MT		 6792 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6793 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6794 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6795 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6796 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6797 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6798 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6799 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6800#ifdef CONFIG_X86_64
5fdbf976
MT		 6801 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6802 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6803 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6804 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6805 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6806 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6807 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6808 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6809#endif
6810
5fdbf976 6811 regs->rip = kvm_rip_read(vcpu);
91586a3b 6812 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6813
b6c7a5dc
HB		 6814 return 0;
6815}
6816
6817int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6818{
7ae441ea
GN		 6819 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6820 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6821
5fdbf976
MT		 6822 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6823 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6824 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6825 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6826 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6827 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6828 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6829 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6830#ifdef CONFIG_X86_64
5fdbf976
MT		 6831 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6832 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6833 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6834 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6835 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6836 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6837 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6838 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6839#endif
6840
5fdbf976 6841 kvm_rip_write(vcpu, regs->rip);
91586a3b 6842 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6843
b4f14abd
JK		 6844 vcpu->arch.exception.pending = false;
6845
3842d135
AK		 6846 kvm_make_request(KVM_REQ_EVENT, vcpu);
6847
b6c7a5dc
HB		 6848 return 0;
6849}
6850
b6c7a5dc
HB		 6851void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6852{
6853 struct kvm_segment cs;
6854
3e6e0aab 6855 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6856 *db = cs.db;
6857 *l = cs.l;
6858}
6859EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6860
6861int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6862 struct kvm_sregs *sregs)
6863{
89a27f4d 6864 struct desc_ptr dt;
b6c7a5dc 6865
3e6e0aab
GT		 6866 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6867 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6868 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6869 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6870 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6871 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6872
3e6e0aab
GT		 6873 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6874 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6875
6876 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6877 sregs->idt.limit = dt.size;
6878 sregs->idt.base = dt.address;
b6c7a5dc 6879 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6880 sregs->gdt.limit = dt.size;
6881 sregs->gdt.base = dt.address;
b6c7a5dc 6882
4d4ec087 6883 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6884 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6885 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6886 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6887 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6888 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6889 sregs->apic_base = kvm_get_apic_base(vcpu);
6890
923c61bb 6891 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6892
36752c9b 6893 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6894 set_bit(vcpu->arch.interrupt.nr,
6895 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6896
b6c7a5dc
HB		 6897 return 0;
6898}
6899
62d9f0db
MT		 6900int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6901 struct kvm_mp_state *mp_state)
6902{
66450a21 6903 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6904 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6905 vcpu->arch.pv.pv_unhalted)
6906 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6907 else
6908 mp_state->mp_state = vcpu->arch.mp_state;
6909
62d9f0db
MT		 6910 return 0;
6911}
6912
6913int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6914 struct kvm_mp_state *mp_state)
6915{
66450a21
JK		 6916 if (!kvm_vcpu_has_lapic(vcpu) &&
6917 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6918 return -EINVAL;
6919
6920 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6921 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6922 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6923 } else
6924 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6925 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6926 return 0;
6927}
6928
7f3d35fd
KW		 6929int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6930 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6931{
9d74191a 6932 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6933 int ret;
e01c2426 6934
8ec4722d 6935 init_emulate_ctxt(vcpu);
c697518a 6936
7f3d35fd 6937 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6938 has_error_code, error_code);
c697518a 6939
c697518a 6940 if (ret)
19d04437 6941 return EMULATE_FAIL;
37817f29 6942
9d74191a
TY		 6943 kvm_rip_write(vcpu, ctxt->eip);
6944 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6945 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6946 return EMULATE_DONE;
37817f29
IE		 6947}
6948EXPORT_SYMBOL_GPL(kvm_task_switch);
6949
b6c7a5dc
HB		 6950int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6951 struct kvm_sregs *sregs)
6952{
58cb628d 6953 struct msr_data apic_base_msr;
b6c7a5dc 6954 int mmu_reset_needed = 0;
63f42e02 6955 int pending_vec, max_bits, idx;
89a27f4d 6956 struct desc_ptr dt;
b6c7a5dc 6957
6d1068b3
PM		 6958 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6959 return -EINVAL;
6960
89a27f4d
GN		 6961 dt.size = sregs->idt.limit;
6962 dt.address = sregs->idt.base;
b6c7a5dc 6963 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6964 dt.size = sregs->gdt.limit;
6965 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6966 kvm_x86_ops->set_gdt(vcpu, &dt);
6967
ad312c7c 6968 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6969 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6970 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6971 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6972
2d3ad1f4 6973 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6974
f6801dff 6975 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6976 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6977 apic_base_msr.data = sregs->apic_base;
6978 apic_base_msr.host_initiated = true;
6979 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6980
4d4ec087 6981 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6982 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6983 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6984
fc78f519 6985 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6986 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6987 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6988 kvm_update_cpuid(vcpu);
63f42e02
XG		 6989
6990 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6991 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6992 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6993 mmu_reset_needed = 1;
6994 }
63f42e02 6995 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6996
6997 if (mmu_reset_needed)
6998 kvm_mmu_reset_context(vcpu);
6999
a50abc3b 7000 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7001 pending_vec = find_first_bit(
7002 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7003 if (pending_vec < max_bits) {
66fd3f7f 7004 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7005 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7006 }
7007
3e6e0aab
GT		 7008 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7009 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7010 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7011 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7012 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7013 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7014
3e6e0aab
GT		 7015 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7016 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7017
5f0269f5
ME		 7018 update_cr8_intercept(vcpu);
7019
9c3e4aab 7020 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7021 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7022 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7023 !is_protmode(vcpu))
9c3e4aab
MT		 7024 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7025
3842d135
AK		 7026 kvm_make_request(KVM_REQ_EVENT, vcpu);
7027
b6c7a5dc
HB		 7028 return 0;
7029}
7030
d0bfb940
JK		 7031int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7032 struct kvm_guest_debug *dbg)
b6c7a5dc 7033{
355be0b9 7034 unsigned long rflags;
ae675ef0 7035 int i, r;
b6c7a5dc 7036
4f926bf2
JK		 7037 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7038 r = -EBUSY;
7039 if (vcpu->arch.exception.pending)
2122ff5e 7040 goto out;
4f926bf2
JK		 7041 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7042 kvm_queue_exception(vcpu, DB_VECTOR);
7043 else
7044 kvm_queue_exception(vcpu, BP_VECTOR);
7045 }
7046
91586a3b
JK		 7047 /*
7048 * Read rflags as long as potentially injected trace flags are still
7049 * filtered out.
7050 */
7051 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7052
7053 vcpu->guest_debug = dbg->control;
7054 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7055 vcpu->guest_debug = 0;
7056
7057 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7058 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7059 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7060 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7061 } else {
7062 for (i = 0; i < KVM_NR_DB_REGS; i++)
7063 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7064 }
c8639010 7065 kvm_update_dr7(vcpu);
ae675ef0 7066
f92653ee
JK		 7067 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7068 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7069 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7070
91586a3b
JK		 7071 /*
7072 * Trigger an rflags update that will inject or remove the trace
7073 * flags.
7074 */
7075 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7076
c8639010 7077 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7078
4f926bf2 7079 r = 0;
d0bfb940 7080
2122ff5e 7081out:
b6c7a5dc
HB		 7082
7083 return r;
7084}
7085
8b006791
ZX		 7086/*
7087 * Translate a guest virtual address to a guest physical address.
7088 */
7089int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7090 struct kvm_translation *tr)
7091{
7092 unsigned long vaddr = tr->linear_address;
7093 gpa_t gpa;
f656ce01 7094 int idx;
8b006791 7095
f656ce01 7096 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7097 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7098 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7099 tr->physical_address = gpa;
7100 tr->valid = gpa != UNMAPPED_GVA;
7101 tr->writeable = 1;
7102 tr->usermode = 0;
8b006791
ZX		 7103
7104 return 0;
7105}
7106
d0752060
HB		 7107int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7108{
98918833
SY		 7109 struct i387_fxsave_struct *fxsave =
7110 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7111
d0752060
HB		 7112 memcpy(fpu->fpr, fxsave->st_space, 128);
7113 fpu->fcw = fxsave->cwd;
7114 fpu->fsw = fxsave->swd;
7115 fpu->ftwx = fxsave->twd;
7116 fpu->last_opcode = fxsave->fop;
7117 fpu->last_ip = fxsave->rip;
7118 fpu->last_dp = fxsave->rdp;
7119 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7120
d0752060
HB		 7121 return 0;
7122}
7123
7124int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7125{
98918833
SY		 7126 struct i387_fxsave_struct *fxsave =
7127 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7128
d0752060
HB		 7129 memcpy(fxsave->st_space, fpu->fpr, 128);
7130 fxsave->cwd = fpu->fcw;
7131 fxsave->swd = fpu->fsw;
7132 fxsave->twd = fpu->ftwx;
7133 fxsave->fop = fpu->last_opcode;
7134 fxsave->rip = fpu->last_ip;
7135 fxsave->rdp = fpu->last_dp;
7136 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7137
d0752060
HB		 7138 return 0;
7139}
7140
d28bc9dd 7141int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7142{
10ab25cd
JK		 7143 int err;
7144
7145 err = fpu_alloc(&vcpu->arch.guest_fpu);
7146 if (err)
7147 return err;
7148
d28bc9dd
NA		 7149 if (!init_event)
7150 fpu_finit(&vcpu->arch.guest_fpu);
7151
df1daba7
PB		 7152 if (cpu_has_xsaves)
7153 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7154 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7155
2acf923e
DC		 7156 /*
7157 * Ensure guest xcr0 is valid for loading
7158 */
7159 vcpu->arch.xcr0 = XSTATE_FP;
7160
ad312c7c 7161 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7162
7163 return 0;
d0752060
HB		 7164}
7165EXPORT_SYMBOL_GPL(fx_init);
7166
98918833
SY		 7167static void fx_free(struct kvm_vcpu *vcpu)
7168{
7169 fpu_free(&vcpu->arch.guest_fpu);
7170}
7171
d0752060
HB		 7172void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7173{
2608d7a1 7174 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7175 return;
7176
2acf923e
DC		 7177 /*
7178 * Restore all possible states in the guest,
7179 * and assume host would use all available bits.
7180 * Guest xcr0 would be loaded later.
7181 */
7182 kvm_put_guest_xcr0(vcpu);
d0752060 7183 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7184 __kernel_fpu_begin();
98918833 7185 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7186 trace_kvm_fpu(1);
d0752060 7187}
d0752060
HB		 7188
7189void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7190{
2acf923e
DC		 7191 kvm_put_guest_xcr0(vcpu);
7192
653f52c3
RR		 7193 if (!vcpu->guest_fpu_loaded) {
7194 vcpu->fpu_counter = 0;
d0752060 7195 return;
653f52c3 7196 }
d0752060
HB		 7197
7198 vcpu->guest_fpu_loaded = 0;
98918833 7199 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7200 __kernel_fpu_end();
f096ed85 7201 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7202 /*
7203 * If using eager FPU mode, or if the guest is a frequent user
7204 * of the FPU, just leave the FPU active for next time.
7205 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7206 * the FPU in bursts will revert to loading it on demand.
7207 */
a9b4fb7e 7208 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7209 if (++vcpu->fpu_counter < 5)
7210 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7211 }
0c04851c 7212 trace_kvm_fpu(0);
d0752060 7213}
e9b11c17
ZX		 7214
7215void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7216{
12f9a48f 7217 kvmclock_reset(vcpu);
7f1ea208 7218
f5f48ee1 7219 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7220 fx_free(vcpu);
e9b11c17
ZX		 7221 kvm_x86_ops->vcpu_free(vcpu);
7222}
7223
7224struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7225 unsigned int id)
7226{
c447e76b
LL		 7227 struct kvm_vcpu *vcpu;
7228
6755bae8
ZA		 7229 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7230 printk_once(KERN_WARNING
7231 "kvm: SMP vm created on host with unstable TSC; "
7232 "guest TSC will not be reliable\n");
c447e76b
LL		 7233
7234 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7235
7236 /*
7237 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7238 * deactivated soon if it doesn't.
7239 */
7240 kvm_x86_ops->fpu_activate(vcpu);
7241 return vcpu;
26e5215f 7242}
e9b11c17 7243
26e5215f
AK		 7244int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7245{
7246 int r;
e9b11c17 7247
0bed3b56 7248 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7249 r = vcpu_load(vcpu);
7250 if (r)
7251 return r;
d28bc9dd 7252 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7253 kvm_mmu_setup(vcpu);
e9b11c17 7254 vcpu_put(vcpu);
e9b11c17 7255
26e5215f 7256 return r;
e9b11c17
ZX		 7257}
7258
31928aa5 7259void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7260{
8fe8ab46 7261 struct msr_data msr;
332967a3 7262 struct kvm *kvm = vcpu->kvm;
42897d86 7263
31928aa5
DD		 7264 if (vcpu_load(vcpu))
7265 return;
8fe8ab46
WA		 7266 msr.data = 0x0;
7267 msr.index = MSR_IA32_TSC;
7268 msr.host_initiated = true;
7269 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7270 vcpu_put(vcpu);
7271
630994b3
MT		 7272 if (!kvmclock_periodic_sync)
7273 return;
7274
332967a3
AJ		 7275 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7276 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7277}
7278
d40ccc62 7279void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7280{
9fc77441 7281 int r;
344d9588
GN		 7282 vcpu->arch.apf.msr_val = 0;
7283
9fc77441
MT		 7284 r = vcpu_load(vcpu);
7285 BUG_ON(r);
e9b11c17
ZX		 7286 kvm_mmu_unload(vcpu);
7287 vcpu_put(vcpu);
7288
98918833 7289 fx_free(vcpu);
e9b11c17
ZX		 7290 kvm_x86_ops->vcpu_free(vcpu);
7291}
7292
d28bc9dd 7293void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7294{
e69fab5d
PB		 7295 vcpu->arch.hflags = 0;
7296
7460fb4a
AK		 7297 atomic_set(&vcpu->arch.nmi_queued, 0);
7298 vcpu->arch.nmi_pending = 0;
448fa4a9 7299 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7300 kvm_clear_interrupt_queue(vcpu);
7301 kvm_clear_exception_queue(vcpu);
448fa4a9 7302
42dbaa5a 7303 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7304 kvm_update_dr0123(vcpu);
6f43ed01 7305 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7306 kvm_update_dr6(vcpu);
42dbaa5a 7307 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7308 kvm_update_dr7(vcpu);
42dbaa5a 7309
1119022c
NA		 7310 vcpu->arch.cr2 = 0;
7311
3842d135 7312 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7313 vcpu->arch.apf.msr_val = 0;
c9aaa895 7314 vcpu->arch.st.msr_val = 0;
3842d135 7315
12f9a48f
GC		 7316 kvmclock_reset(vcpu);
7317
af585b92
GN		 7318 kvm_clear_async_pf_completion_queue(vcpu);
7319 kvm_async_pf_hash_reset(vcpu);
7320 vcpu->arch.apf.halted = false;
3842d135 7321
d28bc9dd
NA		 7322 if (!init_event)
7323 kvm_pmu_reset(vcpu);
f5132b01 7324
66f7b72e
JS		 7325 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7326 vcpu->arch.regs_avail = ~0;
7327 vcpu->arch.regs_dirty = ~0;
7328
d28bc9dd 7329 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7330}
7331
2b4a273b 7332void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7333{
7334 struct kvm_segment cs;
7335
7336 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7337 cs.selector = vector << 8;
7338 cs.base = vector << 12;
7339 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7340 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7341}
7342
13a34e06 7343int kvm_arch_hardware_enable(void)
e9b11c17 7344{
ca84d1a2
ZA		 7345 struct kvm *kvm;
7346 struct kvm_vcpu *vcpu;
7347 int i;
0dd6a6ed
ZA		 7348 int ret;
7349 u64 local_tsc;
7350 u64 max_tsc = 0;
7351 bool stable, backwards_tsc = false;
18863bdd
AK		 7352
7353 kvm_shared_msr_cpu_online();
13a34e06 7354 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7355 if (ret != 0)
7356 return ret;
7357
7358 local_tsc = native_read_tsc();
7359 stable = !check_tsc_unstable();
7360 list_for_each_entry(kvm, &vm_list, vm_list) {
7361 kvm_for_each_vcpu(i, vcpu, kvm) {
7362 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7363 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7364 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7365 backwards_tsc = true;
7366 if (vcpu->arch.last_host_tsc > max_tsc)
7367 max_tsc = vcpu->arch.last_host_tsc;
7368 }
7369 }
7370 }
7371
7372 /*
7373 * Sometimes, even reliable TSCs go backwards. This happens on
7374 * platforms that reset TSC during suspend or hibernate actions, but
7375 * maintain synchronization. We must compensate. Fortunately, we can
7376 * detect that condition here, which happens early in CPU bringup,
7377 * before any KVM threads can be running. Unfortunately, we can't
7378 * bring the TSCs fully up to date with real time, as we aren't yet far
7379 * enough into CPU bringup that we know how much real time has actually
7380 * elapsed; our helper function, get_kernel_ns() will be using boot
7381 * variables that haven't been updated yet.
7382 *
7383 * So we simply find the maximum observed TSC above, then record the
7384 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7385 * the adjustment will be applied. Note that we accumulate
7386 * adjustments, in case multiple suspend cycles happen before some VCPU
7387 * gets a chance to run again. In the event that no KVM threads get a
7388 * chance to run, we will miss the entire elapsed period, as we'll have
7389 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7390 * loose cycle time. This isn't too big a deal, since the loss will be
7391 * uniform across all VCPUs (not to mention the scenario is extremely
7392 * unlikely). It is possible that a second hibernate recovery happens
7393 * much faster than a first, causing the observed TSC here to be
7394 * smaller; this would require additional padding adjustment, which is
7395 * why we set last_host_tsc to the local tsc observed here.
7396 *
7397 * N.B. - this code below runs only on platforms with reliable TSC,
7398 * as that is the only way backwards_tsc is set above. Also note
7399 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7400 * have the same delta_cyc adjustment applied if backwards_tsc
7401 * is detected. Note further, this adjustment is only done once,
7402 * as we reset last_host_tsc on all VCPUs to stop this from being
7403 * called multiple times (one for each physical CPU bringup).
7404 *
4a969980 7405 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7406 * will be compensated by the logic in vcpu_load, which sets the TSC to
7407 * catchup mode. This will catchup all VCPUs to real time, but cannot
7408 * guarantee that they stay in perfect synchronization.
7409 */
7410 if (backwards_tsc) {
7411 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7412 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7413 list_for_each_entry(kvm, &vm_list, vm_list) {
7414 kvm_for_each_vcpu(i, vcpu, kvm) {
7415 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7416 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7417 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7418 }
7419
7420 /*
7421 * We have to disable TSC offset matching.. if you were
7422 * booting a VM while issuing an S4 host suspend....
7423 * you may have some problem. Solving this issue is
7424 * left as an exercise to the reader.
7425 */
7426 kvm->arch.last_tsc_nsec = 0;
7427 kvm->arch.last_tsc_write = 0;
7428 }
7429
7430 }
7431 return 0;
e9b11c17
ZX		 7432}
7433
13a34e06 7434void kvm_arch_hardware_disable(void)
e9b11c17 7435{
13a34e06
RK		 7436 kvm_x86_ops->hardware_disable();
7437 drop_user_return_notifiers();
e9b11c17
ZX		 7438}
7439
7440int kvm_arch_hardware_setup(void)
7441{
9e9c3fe4
NA		 7442 int r;
7443
7444 r = kvm_x86_ops->hardware_setup();
7445 if (r != 0)
7446 return r;
7447
7448 kvm_init_msr_list();
7449 return 0;
e9b11c17
ZX		 7450}
7451
7452void kvm_arch_hardware_unsetup(void)
7453{
7454 kvm_x86_ops->hardware_unsetup();
7455}
7456
7457void kvm_arch_check_processor_compat(void *rtn)
7458{
7459 kvm_x86_ops->check_processor_compatibility(rtn);
7460}
7461
3e515705
AK		 7462bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7463{
7464 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7465}
7466
54e9818f
GN		 7467struct static_key kvm_no_apic_vcpu __read_mostly;
7468
e9b11c17
ZX		 7469int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7470{
7471 struct page *page;
7472 struct kvm *kvm;
7473 int r;
7474
7475 BUG_ON(vcpu->kvm == NULL);
7476 kvm = vcpu->kvm;
7477
6aef266c 7478 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7479 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7480 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7481 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7482 else
a4535290 7483 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7484
7485 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7486 if (!page) {
7487 r = -ENOMEM;
7488 goto fail;
7489 }
ad312c7c 7490 vcpu->arch.pio_data = page_address(page);
e9b11c17 7491
cc578287 7492 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7493
e9b11c17
ZX		 7494 r = kvm_mmu_create(vcpu);
7495 if (r < 0)
7496 goto fail_free_pio_data;
7497
7498 if (irqchip_in_kernel(kvm)) {
7499 r = kvm_create_lapic(vcpu);
7500 if (r < 0)
7501 goto fail_mmu_destroy;
54e9818f
GN		 7502 } else
7503 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7504
890ca9ae
HY		 7505 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7506 GFP_KERNEL);
7507 if (!vcpu->arch.mce_banks) {
7508 r = -ENOMEM;
443c39bc 7509 goto fail_free_lapic;
890ca9ae
HY		 7510 }
7511 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7512
f1797359
WY		 7513 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7514 r = -ENOMEM;
f5f48ee1 7515 goto fail_free_mce_banks;
f1797359 7516 }
f5f48ee1 7517
d28bc9dd 7518 r = fx_init(vcpu, false);
66f7b72e
JS		 7519 if (r)
7520 goto fail_free_wbinvd_dirty_mask;
7521
ba904635 7522 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7523 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7524
7525 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7526 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7527
5a4f55cd
EK		 7528 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7529
74545705
RK		 7530 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7531
af585b92 7532 kvm_async_pf_hash_reset(vcpu);
f5132b01 7533 kvm_pmu_init(vcpu);
af585b92 7534
e9b11c17 7535 return 0;
66f7b72e
JS		 7536fail_free_wbinvd_dirty_mask:
7537 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7538fail_free_mce_banks:
7539 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7540fail_free_lapic:
7541 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7542fail_mmu_destroy:
7543 kvm_mmu_destroy(vcpu);
7544fail_free_pio_data:
ad312c7c 7545 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7546fail:
7547 return r;
7548}
7549
7550void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7551{
f656ce01
MT		 7552 int idx;
7553
f5132b01 7554 kvm_pmu_destroy(vcpu);
36cb93fd 7555 kfree(vcpu->arch.mce_banks);
e9b11c17 7556 kvm_free_lapic(vcpu);
f656ce01 7557 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7558 kvm_mmu_destroy(vcpu);
f656ce01 7559 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7560 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7561 if (!irqchip_in_kernel(vcpu->kvm))
7562 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7563}
d19a9cd2 7564
e790d9ef
RK		 7565void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7566{
ae97a3b8 7567 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7568}
7569
e08b9637 7570int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7571{
e08b9637
CO		 7572 if (type)
7573 return -EINVAL;
7574
6ef768fa 7575 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7576 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7577 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7578 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7579 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7580
5550af4d
SY		 7581 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7582 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7583 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7584 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7585 &kvm->arch.irq_sources_bitmap);
5550af4d 7586
038f8c11 7587 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7588 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7589 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7590
7591 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7592
7e44e449 7593 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7594 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7595
d89f5eff 7596 return 0;
d19a9cd2
ZX		 7597}
7598
7599static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7600{
9fc77441
MT		 7601 int r;
7602 r = vcpu_load(vcpu);
7603 BUG_ON(r);
d19a9cd2
ZX		 7604 kvm_mmu_unload(vcpu);
7605 vcpu_put(vcpu);
7606}
7607
7608static void kvm_free_vcpus(struct kvm *kvm)
7609{
7610 unsigned int i;
988a2cae 7611 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7612
7613 /*
7614 * Unpin any mmu pages first.
7615 */
af585b92
GN		 7616 kvm_for_each_vcpu(i, vcpu, kvm) {
7617 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7618 kvm_unload_vcpu_mmu(vcpu);
af585b92 7619 }
988a2cae
GN		 7620 kvm_for_each_vcpu(i, vcpu, kvm)
7621 kvm_arch_vcpu_free(vcpu);
7622
7623 mutex_lock(&kvm->lock);
7624 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7625 kvm->vcpus[i] = NULL;
d19a9cd2 7626
988a2cae
GN		 7627 atomic_set(&kvm->online_vcpus, 0);
7628 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7629}
7630
ad8ba2cd
SY		 7631void kvm_arch_sync_events(struct kvm *kvm)
7632{
332967a3 7633 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7634 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7635 kvm_free_all_assigned_devices(kvm);
aea924f6 7636 kvm_free_pit(kvm);
ad8ba2cd
SY		 7637}
7638
d19a9cd2
ZX		 7639void kvm_arch_destroy_vm(struct kvm *kvm)
7640{
27469d29
AH		 7641 if (current->mm == kvm->mm) {
7642 /*
7643 * Free memory regions allocated on behalf of userspace,
7644 * unless the the memory map has changed due to process exit
7645 * or fd copying.
7646 */
7647 struct kvm_userspace_memory_region mem;
7648 memset(&mem, 0, sizeof(mem));
7649 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7650 kvm_set_memory_region(kvm, &mem);
7651
7652 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7653 kvm_set_memory_region(kvm, &mem);
7654
7655 mem.slot = TSS_PRIVATE_MEMSLOT;
7656 kvm_set_memory_region(kvm, &mem);
7657 }
6eb55818 7658 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7659 kfree(kvm->arch.vpic);
7660 kfree(kvm->arch.vioapic);
d19a9cd2 7661 kvm_free_vcpus(kvm);
1e08ec4a 7662 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7663}
0de10343 7664
5587027c 7665void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7666 struct kvm_memory_slot *dont)
7667{
7668 int i;
7669
d89cc617
TY		 7670 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7671 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7672 kvfree(free->arch.rmap[i]);
d89cc617 7673 free->arch.rmap[i] = NULL;
77d11309 7674 }
d89cc617
TY		 7675 if (i == 0)
7676 continue;
7677
7678 if (!dont || free->arch.lpage_info[i - 1] !=
7679 dont->arch.lpage_info[i - 1]) {
548ef284 7680 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7681 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7682 }
7683 }
7684}
7685
5587027c
AK		 7686int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7687 unsigned long npages)
db3fe4eb
TY		 7688{
7689 int i;
7690
d89cc617 7691 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7692 unsigned long ugfn;
7693 int lpages;
d89cc617 7694 int level = i + 1;
db3fe4eb
TY		 7695
7696 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7697 slot->base_gfn, level) + 1;
7698
d89cc617
TY		 7699 slot->arch.rmap[i] =
7700 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7701 if (!slot->arch.rmap[i])
77d11309 7702 goto out_free;
d89cc617
TY		 7703 if (i == 0)
7704 continue;
77d11309 7705
d89cc617
TY		 7706 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7707 sizeof(*slot->arch.lpage_info[i - 1]));
7708 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7709 goto out_free;
7710
7711 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7712 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7713 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7714 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7715 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7716 /*
7717 * If the gfn and userspace address are not aligned wrt each
7718 * other, or if explicitly asked to, disable large page
7719 * support for this slot
7720 */
7721 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7722 !kvm_largepages_enabled()) {
7723 unsigned long j;
7724
7725 for (j = 0; j < lpages; ++j)
d89cc617 7726 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7727 }
7728 }
7729
7730 return 0;
7731
7732out_free:
d89cc617 7733 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7734 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7735 slot->arch.rmap[i] = NULL;
7736 if (i == 0)
7737 continue;
7738
548ef284 7739 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7740 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7741 }
7742 return -ENOMEM;
7743}
7744
15f46015 7745void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7746{
e6dff7d1
TY		 7747 /*
7748 * memslots->generation has been incremented.
7749 * mmio generation may have reached its maximum value.
7750 */
7751 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7752}
7753
f7784b8e
MT		 7754int kvm_arch_prepare_memory_region(struct kvm *kvm,
7755 struct kvm_memory_slot *memslot,
09170a49 7756 const struct kvm_userspace_memory_region *mem,
7b6195a9 7757 enum kvm_mr_change change)
0de10343 7758{
7a905b14
TY		 7759 /*
7760 * Only private memory slots need to be mapped here since
7761 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7762 */
7b6195a9 7763 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7764 unsigned long userspace_addr;
604b38ac 7765
7a905b14
TY		 7766 /*
7767 * MAP_SHARED to prevent internal slot pages from being moved
7768 * by fork()/COW.
7769 */
7b6195a9 7770 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7771 PROT_READ | PROT_WRITE,
7772 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7773
7a905b14
TY		 7774 if (IS_ERR((void *)userspace_addr))
7775 return PTR_ERR((void *)userspace_addr);
604b38ac 7776
7a905b14 7777 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7778 }
7779
f7784b8e
MT		 7780 return 0;
7781}
7782
88178fd4
KH		 7783static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7784 struct kvm_memory_slot *new)
7785{
7786 /* Still write protect RO slot */
7787 if (new->flags & KVM_MEM_READONLY) {
7788 kvm_mmu_slot_remove_write_access(kvm, new);
7789 return;
7790 }
7791
7792 /*
7793 * Call kvm_x86_ops dirty logging hooks when they are valid.
7794 *
7795 * kvm_x86_ops->slot_disable_log_dirty is called when:
7796 *
7797 * - KVM_MR_CREATE with dirty logging is disabled
7798 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7799 *
7800 * The reason is, in case of PML, we need to set D-bit for any slots
7801 * with dirty logging disabled in order to eliminate unnecessary GPA
7802 * logging in PML buffer (and potential PML buffer full VMEXT). This
7803 * guarantees leaving PML enabled during guest's lifetime won't have
7804 * any additonal overhead from PML when guest is running with dirty
7805 * logging disabled for memory slots.
7806 *
7807 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7808 * to dirty logging mode.
7809 *
7810 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7811 *
7812 * In case of write protect:
7813 *
7814 * Write protect all pages for dirty logging.
7815 *
7816 * All the sptes including the large sptes which point to this
7817 * slot are set to readonly. We can not create any new large
7818 * spte on this slot until the end of the logging.
7819 *
7820 * See the comments in fast_page_fault().
7821 */
7822 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7823 if (kvm_x86_ops->slot_enable_log_dirty)
7824 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7825 else
7826 kvm_mmu_slot_remove_write_access(kvm, new);
7827 } else {
7828 if (kvm_x86_ops->slot_disable_log_dirty)
7829 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7830 }
7831}
7832
f7784b8e 7833void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7834 const struct kvm_userspace_memory_region *mem,
8482644a 7835 const struct kvm_memory_slot *old,
f36f3f28 7836 const struct kvm_memory_slot *new,
8482644a 7837 enum kvm_mr_change change)
f7784b8e 7838{
8482644a 7839 int nr_mmu_pages = 0;
f7784b8e 7840
f36f3f28 7841 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7842 int ret;
7843
8482644a
TY		 7844 ret = vm_munmap(old->userspace_addr,
7845 old->npages * PAGE_SIZE);
f7784b8e
MT		 7846 if (ret < 0)
7847 printk(KERN_WARNING
7848 "kvm_vm_ioctl_set_memory_region: "
7849 "failed to munmap memory\n");
7850 }
7851
48c0e4e9
XG		 7852 if (!kvm->arch.n_requested_mmu_pages)
7853 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7854
48c0e4e9 7855 if (nr_mmu_pages)
0de10343 7856 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7857
3ea3b7fa
WL		 7858 /*
7859 * Dirty logging tracks sptes in 4k granularity, meaning that large
7860 * sptes have to be split. If live migration is successful, the guest
7861 * in the source machine will be destroyed and large sptes will be
7862 * created in the destination. However, if the guest continues to run
7863 * in the source machine (for example if live migration fails), small
7864 * sptes will remain around and cause bad performance.
7865 *
7866 * Scan sptes if dirty logging has been stopped, dropping those
7867 * which can be collapsed into a single large-page spte. Later
7868 * page faults will create the large-page sptes.
7869 */
7870 if ((change != KVM_MR_DELETE) &&
7871 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7872 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7873 kvm_mmu_zap_collapsible_sptes(kvm, new);
7874
c972f3b1 7875 /*
88178fd4 7876 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7877 *
88178fd4
KH		 7878 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7879 * been zapped so no dirty logging staff is needed for old slot. For
7880 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7881 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7882 *
7883 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7884 */
88178fd4 7885 if (change != KVM_MR_DELETE)
f36f3f28 7886 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7887}
1d737c8a 7888
2df72e9b 7889void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7890{
6ca18b69 7891 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7892}
7893
2df72e9b
MT		 7894void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7895 struct kvm_memory_slot *slot)
7896{
6ca18b69 7897 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7898}
7899
1d737c8a
ZX		 7900int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7901{
b6b8a145
JK		 7902 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7903 kvm_x86_ops->check_nested_events(vcpu, false);
7904
af585b92
GN		 7905 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7906 !vcpu->arch.apf.halted)
7907 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7908 || kvm_apic_has_events(vcpu)
6aef266c 7909 || vcpu->arch.pv.pv_unhalted
7460fb4a 7910 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7911 (kvm_arch_interrupt_allowed(vcpu) &&
7912 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7913}
5736199a 7914
b6d33834 7915int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7916{
b6d33834 7917 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7918}
78646121
GN		 7919
7920int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7921{
7922 return kvm_x86_ops->interrupt_allowed(vcpu);
7923}
229456fc 7924
82b32774 7925unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7926{
82b32774
NA		 7927 if (is_64_bit_mode(vcpu))
7928 return kvm_rip_read(vcpu);
7929 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7930 kvm_rip_read(vcpu));
7931}
7932EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7933
82b32774
NA		 7934bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7935{
7936 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7937}
7938EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7939
94fe45da
JK		 7940unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7941{
7942 unsigned long rflags;
7943
7944 rflags = kvm_x86_ops->get_rflags(vcpu);
7945 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7946 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7947 return rflags;
7948}
7949EXPORT_SYMBOL_GPL(kvm_get_rflags);
7950
6addfc42 7951static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7952{
7953 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7954 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7955 rflags |= X86_EFLAGS_TF;
94fe45da 7956 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7957}
7958
7959void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7960{
7961 __kvm_set_rflags(vcpu, rflags);
3842d135 7962 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7963}
7964EXPORT_SYMBOL_GPL(kvm_set_rflags);
7965
56028d08
GN		 7966void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7967{
7968 int r;
7969
fb67e14f 7970 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7971 work->wakeup_all)
56028d08
GN		 7972 return;
7973
7974 r = kvm_mmu_reload(vcpu);
7975 if (unlikely(r))
7976 return;
7977
fb67e14f
XG		 7978 if (!vcpu->arch.mmu.direct_map &&
7979 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7980 return;
7981
56028d08
GN		 7982 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7983}
7984
af585b92
GN		 7985static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7986{
7987 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7988}
7989
7990static inline u32 kvm_async_pf_next_probe(u32 key)
7991{
7992 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7993}
7994
7995static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7996{
7997 u32 key = kvm_async_pf_hash_fn(gfn);
7998
7999 while (vcpu->arch.apf.gfns[key] != ~0)
8000 key = kvm_async_pf_next_probe(key);
8001
8002 vcpu->arch.apf.gfns[key] = gfn;
8003}
8004
8005static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8006{
8007 int i;
8008 u32 key = kvm_async_pf_hash_fn(gfn);
8009
8010 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8011 (vcpu->arch.apf.gfns[key] != gfn &&
8012 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8013 key = kvm_async_pf_next_probe(key);
8014
8015 return key;
8016}
8017
8018bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8019{
8020 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8021}
8022
8023static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8024{
8025 u32 i, j, k;
8026
8027 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8028 while (true) {
8029 vcpu->arch.apf.gfns[i] = ~0;
8030 do {
8031 j = kvm_async_pf_next_probe(j);
8032 if (vcpu->arch.apf.gfns[j] == ~0)
8033 return;
8034 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8035 /*
8036 * k lies cyclically in ]i,j]
8037 * | i.k.j |
8038 * |....j i.k.| or |.k..j i...|
8039 */
8040 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8041 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8042 i = j;
8043 }
8044}
8045
7c90705b
GN		 8046static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8047{
8048
8049 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8050 sizeof(val));
8051}
8052
af585b92
GN		 8053void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8054 struct kvm_async_pf *work)
8055{
6389ee94
AK		 8056 struct x86_exception fault;
8057
7c90705b 8058 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8059 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8060
8061 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8062 (vcpu->arch.apf.send_user_only &&
8063 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8064 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8065 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8066 fault.vector = PF_VECTOR;
8067 fault.error_code_valid = true;
8068 fault.error_code = 0;
8069 fault.nested_page_fault = false;
8070 fault.address = work->arch.token;
8071 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8072 }
af585b92
GN		 8073}
8074
8075void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8076 struct kvm_async_pf *work)
8077{
6389ee94
AK		 8078 struct x86_exception fault;
8079
7c90705b 8080 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8081 if (work->wakeup_all)
7c90705b
GN		 8082 work->arch.token = ~0; /* broadcast wakeup */
8083 else
8084 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8085
8086 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8087 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8088 fault.vector = PF_VECTOR;
8089 fault.error_code_valid = true;
8090 fault.error_code = 0;
8091 fault.nested_page_fault = false;
8092 fault.address = work->arch.token;
8093 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8094 }
e6d53e3b 8095 vcpu->arch.apf.halted = false;
a4fa1635 8096 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8097}
8098
8099bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8100{
8101 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8102 return true;
8103 else
8104 return !kvm_event_needs_reinjection(vcpu) &&
8105 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8106}
8107
e0f0bbc5
AW		 8108void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8109{
8110 atomic_inc(&kvm->arch.noncoherent_dma_count);
8111}
8112EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8113
8114void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8115{
8116 atomic_dec(&kvm->arch.noncoherent_dma_count);
8117}
8118EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8119
8120bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8121{
8122 return atomic_read(&kvm->arch.noncoherent_dma_count);
8123}
8124EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8125
229456fc
MT		 8126EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8127EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8128EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8129EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8130EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8131EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8132EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8133EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8134EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8135EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8136EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8137EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8138EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8139EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8140EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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