Commit | Line | Data |
---|---|---|
043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
221d059d | 9 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
313a3dc7 | 29 | |
18068523 | 30 | #include <linux/clocksource.h> |
4d5c5d0f | 31 | #include <linux/interrupt.h> |
313a3dc7 CO |
32 | #include <linux/kvm.h> |
33 | #include <linux/fs.h> | |
34 | #include <linux/vmalloc.h> | |
5fb76f9b | 35 | #include <linux/module.h> |
0de10343 | 36 | #include <linux/mman.h> |
2bacc55c | 37 | #include <linux/highmem.h> |
19de40a8 | 38 | #include <linux/iommu.h> |
62c476c7 | 39 | #include <linux/intel-iommu.h> |
c8076604 | 40 | #include <linux/cpufreq.h> |
18863bdd | 41 | #include <linux/user-return-notifier.h> |
a983fb23 | 42 | #include <linux/srcu.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
ff9d07a0 | 44 | #include <linux/perf_event.h> |
7bee342a | 45 | #include <linux/uaccess.h> |
aec51dc4 | 46 | #include <trace/events/kvm.h> |
2ed152af | 47 | |
229456fc MT |
48 | #define CREATE_TRACE_POINTS |
49 | #include "trace.h" | |
043405e1 | 50 | |
24f1e32c | 51 | #include <asm/debugreg.h> |
d825ed0a | 52 | #include <asm/msr.h> |
a5f61300 | 53 | #include <asm/desc.h> |
0bed3b56 | 54 | #include <asm/mtrr.h> |
890ca9ae | 55 | #include <asm/mce.h> |
7cf30855 | 56 | #include <asm/i387.h> |
98918833 | 57 | #include <asm/xcr.h> |
1d5f066e | 58 | #include <asm/pvclock.h> |
217fc9cf | 59 | #include <asm/div64.h> |
043405e1 | 60 | |
313a3dc7 | 61 | #define MAX_IO_MSRS 256 |
a03490ed CO |
62 | #define CR0_RESERVED_BITS \ |
63 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
64 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
65 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
66 | #define CR4_RESERVED_BITS \ | |
67 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
68 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
69 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
2acf923e | 70 | | X86_CR4_OSXSAVE \ |
a03490ed CO |
71 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
72 | ||
73 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
74 | |
75 | #define KVM_MAX_MCE_BANKS 32 | |
76 | #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P | |
77 | ||
50a37eb4 JR |
78 | /* EFER defaults: |
79 | * - enable syscall per default because its emulated by KVM | |
80 | * - enable LME and LMA per default on 64 bit KVM | |
81 | */ | |
82 | #ifdef CONFIG_X86_64 | |
83 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
84 | #else | |
85 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
86 | #endif | |
313a3dc7 | 87 | |
ba1389b7 AK |
88 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
89 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 90 | |
cb142eb7 | 91 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
92 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
93 | struct kvm_cpuid_entry2 __user *entries); | |
94 | ||
97896d04 | 95 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 96 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 97 | |
ed85c068 AP |
98 | int ignore_msrs = 0; |
99 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
100 | ||
18863bdd AK |
101 | #define KVM_NR_SHARED_MSRS 16 |
102 | ||
103 | struct kvm_shared_msrs_global { | |
104 | int nr; | |
2bf78fa7 | 105 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
106 | }; |
107 | ||
108 | struct kvm_shared_msrs { | |
109 | struct user_return_notifier urn; | |
110 | bool registered; | |
2bf78fa7 SY |
111 | struct kvm_shared_msr_values { |
112 | u64 host; | |
113 | u64 curr; | |
114 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
115 | }; |
116 | ||
117 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
118 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
119 | ||
417bc304 | 120 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
121 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
122 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
123 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
124 | { "invlpg", VCPU_STAT(invlpg) }, | |
125 | { "exits", VCPU_STAT(exits) }, | |
126 | { "io_exits", VCPU_STAT(io_exits) }, | |
127 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
128 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
129 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 130 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
131 | { "halt_exits", VCPU_STAT(halt_exits) }, |
132 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 133 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
134 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
135 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
136 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
137 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
138 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
139 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
140 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 141 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 142 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
143 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
144 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
145 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
146 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
147 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
148 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 149 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 150 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 151 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 152 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
153 | { NULL } |
154 | }; | |
155 | ||
2acf923e DC |
156 | u64 __read_mostly host_xcr0; |
157 | ||
158 | static inline u32 bit(int bitno) | |
159 | { | |
160 | return 1 << (bitno & 31); | |
161 | } | |
162 | ||
18863bdd AK |
163 | static void kvm_on_user_return(struct user_return_notifier *urn) |
164 | { | |
165 | unsigned slot; | |
18863bdd AK |
166 | struct kvm_shared_msrs *locals |
167 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 168 | struct kvm_shared_msr_values *values; |
18863bdd AK |
169 | |
170 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
171 | values = &locals->values[slot]; |
172 | if (values->host != values->curr) { | |
173 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
174 | values->curr = values->host; | |
18863bdd AK |
175 | } |
176 | } | |
177 | locals->registered = false; | |
178 | user_return_notifier_unregister(urn); | |
179 | } | |
180 | ||
2bf78fa7 | 181 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 182 | { |
2bf78fa7 | 183 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
184 | u64 value; |
185 | ||
2bf78fa7 SY |
186 | smsr = &__get_cpu_var(shared_msrs); |
187 | /* only read, and nobody should modify it at this time, | |
188 | * so don't need lock */ | |
189 | if (slot >= shared_msrs_global.nr) { | |
190 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
191 | return; | |
192 | } | |
193 | rdmsrl_safe(msr, &value); | |
194 | smsr->values[slot].host = value; | |
195 | smsr->values[slot].curr = value; | |
196 | } | |
197 | ||
198 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
199 | { | |
18863bdd AK |
200 | if (slot >= shared_msrs_global.nr) |
201 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
202 | shared_msrs_global.msrs[slot] = msr; |
203 | /* we need ensured the shared_msr_global have been updated */ | |
204 | smp_wmb(); | |
18863bdd AK |
205 | } |
206 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
207 | ||
208 | static void kvm_shared_msr_cpu_online(void) | |
209 | { | |
210 | unsigned i; | |
18863bdd AK |
211 | |
212 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 213 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
214 | } |
215 | ||
d5696725 | 216 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
217 | { |
218 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
219 | ||
2bf78fa7 | 220 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 221 | return; |
2bf78fa7 SY |
222 | smsr->values[slot].curr = value; |
223 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
224 | if (!smsr->registered) { |
225 | smsr->urn.on_user_return = kvm_on_user_return; | |
226 | user_return_notifier_register(&smsr->urn); | |
227 | smsr->registered = true; | |
228 | } | |
229 | } | |
230 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
231 | ||
3548bab5 AK |
232 | static void drop_user_return_notifiers(void *ignore) |
233 | { | |
234 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
235 | ||
236 | if (smsr->registered) | |
237 | kvm_on_user_return(&smsr->urn); | |
238 | } | |
239 | ||
6866b83e CO |
240 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
241 | { | |
242 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 243 | return vcpu->arch.apic_base; |
6866b83e | 244 | else |
ad312c7c | 245 | return vcpu->arch.apic_base; |
6866b83e CO |
246 | } |
247 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
248 | ||
249 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
250 | { | |
251 | /* TODO: reserve bits check */ | |
252 | if (irqchip_in_kernel(vcpu->kvm)) | |
253 | kvm_lapic_set_base(vcpu, data); | |
254 | else | |
ad312c7c | 255 | vcpu->arch.apic_base = data; |
6866b83e CO |
256 | } |
257 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
258 | ||
3fd28fce ED |
259 | #define EXCPT_BENIGN 0 |
260 | #define EXCPT_CONTRIBUTORY 1 | |
261 | #define EXCPT_PF 2 | |
262 | ||
263 | static int exception_class(int vector) | |
264 | { | |
265 | switch (vector) { | |
266 | case PF_VECTOR: | |
267 | return EXCPT_PF; | |
268 | case DE_VECTOR: | |
269 | case TS_VECTOR: | |
270 | case NP_VECTOR: | |
271 | case SS_VECTOR: | |
272 | case GP_VECTOR: | |
273 | return EXCPT_CONTRIBUTORY; | |
274 | default: | |
275 | break; | |
276 | } | |
277 | return EXCPT_BENIGN; | |
278 | } | |
279 | ||
280 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
ce7ddec4 JR |
281 | unsigned nr, bool has_error, u32 error_code, |
282 | bool reinject) | |
3fd28fce ED |
283 | { |
284 | u32 prev_nr; | |
285 | int class1, class2; | |
286 | ||
287 | if (!vcpu->arch.exception.pending) { | |
288 | queue: | |
289 | vcpu->arch.exception.pending = true; | |
290 | vcpu->arch.exception.has_error_code = has_error; | |
291 | vcpu->arch.exception.nr = nr; | |
292 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 293 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
294 | return; |
295 | } | |
296 | ||
297 | /* to check exception */ | |
298 | prev_nr = vcpu->arch.exception.nr; | |
299 | if (prev_nr == DF_VECTOR) { | |
300 | /* triple fault -> shutdown */ | |
a8eeb04a | 301 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
302 | return; |
303 | } | |
304 | class1 = exception_class(prev_nr); | |
305 | class2 = exception_class(nr); | |
306 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
307 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
308 | /* generate double fault per SDM Table 5-5 */ | |
309 | vcpu->arch.exception.pending = true; | |
310 | vcpu->arch.exception.has_error_code = true; | |
311 | vcpu->arch.exception.nr = DF_VECTOR; | |
312 | vcpu->arch.exception.error_code = 0; | |
313 | } else | |
314 | /* replace previous exception with a new one in a hope | |
315 | that instruction re-execution will regenerate lost | |
316 | exception */ | |
317 | goto queue; | |
318 | } | |
319 | ||
298101da AK |
320 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
321 | { | |
ce7ddec4 | 322 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
323 | } |
324 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
325 | ||
ce7ddec4 JR |
326 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
327 | { | |
328 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
329 | } | |
330 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
331 | ||
8df25a32 | 332 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu) |
c3c91fee | 333 | { |
8df25a32 JR |
334 | unsigned error_code = vcpu->arch.fault.error_code; |
335 | ||
c3c91fee | 336 | ++vcpu->stat.pf_guest; |
8df25a32 | 337 | vcpu->arch.cr2 = vcpu->arch.fault.address; |
c3c91fee AK |
338 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
339 | } | |
340 | ||
3419ffc8 SY |
341 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
342 | { | |
343 | vcpu->arch.nmi_pending = 1; | |
344 | } | |
345 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
346 | ||
298101da AK |
347 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
348 | { | |
ce7ddec4 | 349 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
350 | } |
351 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
352 | ||
ce7ddec4 JR |
353 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
354 | { | |
355 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
356 | } | |
357 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
358 | ||
0a79b009 AK |
359 | /* |
360 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
361 | * a #GP and return false. | |
362 | */ | |
363 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 364 | { |
0a79b009 AK |
365 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
366 | return true; | |
367 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
368 | return false; | |
298101da | 369 | } |
0a79b009 | 370 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 371 | |
a03490ed CO |
372 | /* |
373 | * Load the pae pdptrs. Return true is they are all valid. | |
374 | */ | |
375 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
376 | { | |
377 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
378 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
379 | int i; | |
380 | int ret; | |
ad312c7c | 381 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 382 | |
a03490ed CO |
383 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
384 | offset * sizeof(u64), sizeof(pdpte)); | |
385 | if (ret < 0) { | |
386 | ret = 0; | |
387 | goto out; | |
388 | } | |
389 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 390 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 391 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
392 | ret = 0; |
393 | goto out; | |
394 | } | |
395 | } | |
396 | ret = 1; | |
397 | ||
ad312c7c | 398 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
6de4f3ad AK |
399 | __set_bit(VCPU_EXREG_PDPTR, |
400 | (unsigned long *)&vcpu->arch.regs_avail); | |
401 | __set_bit(VCPU_EXREG_PDPTR, | |
402 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 403 | out: |
a03490ed CO |
404 | |
405 | return ret; | |
406 | } | |
cc4b6871 | 407 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 408 | |
d835dfec AK |
409 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
410 | { | |
ad312c7c | 411 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
412 | bool changed = true; |
413 | int r; | |
414 | ||
415 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
416 | return false; | |
417 | ||
6de4f3ad AK |
418 | if (!test_bit(VCPU_EXREG_PDPTR, |
419 | (unsigned long *)&vcpu->arch.regs_avail)) | |
420 | return true; | |
421 | ||
ad312c7c | 422 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
423 | if (r < 0) |
424 | goto out; | |
ad312c7c | 425 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 426 | out: |
d835dfec AK |
427 | |
428 | return changed; | |
429 | } | |
430 | ||
49a9b07e | 431 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 432 | { |
aad82703 SY |
433 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
434 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
435 | X86_CR0_CD | X86_CR0_NW; | |
436 | ||
f9a48e6a AK |
437 | cr0 |= X86_CR0_ET; |
438 | ||
ab344828 | 439 | #ifdef CONFIG_X86_64 |
0f12244f GN |
440 | if (cr0 & 0xffffffff00000000UL) |
441 | return 1; | |
ab344828 GN |
442 | #endif |
443 | ||
444 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 445 | |
0f12244f GN |
446 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
447 | return 1; | |
a03490ed | 448 | |
0f12244f GN |
449 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
450 | return 1; | |
a03490ed CO |
451 | |
452 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
453 | #ifdef CONFIG_X86_64 | |
f6801dff | 454 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
455 | int cs_db, cs_l; |
456 | ||
0f12244f GN |
457 | if (!is_pae(vcpu)) |
458 | return 1; | |
a03490ed | 459 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
460 | if (cs_l) |
461 | return 1; | |
a03490ed CO |
462 | } else |
463 | #endif | |
0f12244f GN |
464 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) |
465 | return 1; | |
a03490ed CO |
466 | } |
467 | ||
468 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
a03490ed | 469 | |
aad82703 SY |
470 | if ((cr0 ^ old_cr0) & update_bits) |
471 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
472 | return 0; |
473 | } | |
2d3ad1f4 | 474 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 475 | |
2d3ad1f4 | 476 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 477 | { |
49a9b07e | 478 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 479 | } |
2d3ad1f4 | 480 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 481 | |
2acf923e DC |
482 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
483 | { | |
484 | u64 xcr0; | |
485 | ||
486 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
487 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
488 | return 1; | |
489 | xcr0 = xcr; | |
490 | if (kvm_x86_ops->get_cpl(vcpu) != 0) | |
491 | return 1; | |
492 | if (!(xcr0 & XSTATE_FP)) | |
493 | return 1; | |
494 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
495 | return 1; | |
496 | if (xcr0 & ~host_xcr0) | |
497 | return 1; | |
498 | vcpu->arch.xcr0 = xcr0; | |
499 | vcpu->guest_xcr0_loaded = 0; | |
500 | return 0; | |
501 | } | |
502 | ||
503 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
504 | { | |
505 | if (__kvm_set_xcr(vcpu, index, xcr)) { | |
506 | kvm_inject_gp(vcpu, 0); | |
507 | return 1; | |
508 | } | |
509 | return 0; | |
510 | } | |
511 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
512 | ||
513 | static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu) | |
514 | { | |
515 | struct kvm_cpuid_entry2 *best; | |
516 | ||
517 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
518 | return best && (best->ecx & bit(X86_FEATURE_XSAVE)); | |
519 | } | |
520 | ||
521 | static void update_cpuid(struct kvm_vcpu *vcpu) | |
522 | { | |
523 | struct kvm_cpuid_entry2 *best; | |
524 | ||
525 | best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
526 | if (!best) | |
527 | return; | |
528 | ||
529 | /* Update OSXSAVE bit */ | |
530 | if (cpu_has_xsave && best->function == 0x1) { | |
531 | best->ecx &= ~(bit(X86_FEATURE_OSXSAVE)); | |
532 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) | |
533 | best->ecx |= bit(X86_FEATURE_OSXSAVE); | |
534 | } | |
535 | } | |
536 | ||
a83b29c6 | 537 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 538 | { |
fc78f519 | 539 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
a2edf57f AK |
540 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; |
541 | ||
0f12244f GN |
542 | if (cr4 & CR4_RESERVED_BITS) |
543 | return 1; | |
a03490ed | 544 | |
2acf923e DC |
545 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
546 | return 1; | |
547 | ||
a03490ed | 548 | if (is_long_mode(vcpu)) { |
0f12244f GN |
549 | if (!(cr4 & X86_CR4_PAE)) |
550 | return 1; | |
a2edf57f AK |
551 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
552 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
0f12244f GN |
553 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) |
554 | return 1; | |
555 | ||
556 | if (cr4 & X86_CR4_VMXE) | |
557 | return 1; | |
a03490ed | 558 | |
a03490ed | 559 | kvm_x86_ops->set_cr4(vcpu, cr4); |
62ad0755 | 560 | |
aad82703 SY |
561 | if ((cr4 ^ old_cr4) & pdptr_bits) |
562 | kvm_mmu_reset_context(vcpu); | |
0f12244f | 563 | |
2acf923e DC |
564 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
565 | update_cpuid(vcpu); | |
566 | ||
0f12244f GN |
567 | return 0; |
568 | } | |
2d3ad1f4 | 569 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 570 | |
2390218b | 571 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 572 | { |
ad312c7c | 573 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 574 | kvm_mmu_sync_roots(vcpu); |
d835dfec | 575 | kvm_mmu_flush_tlb(vcpu); |
0f12244f | 576 | return 0; |
d835dfec AK |
577 | } |
578 | ||
a03490ed | 579 | if (is_long_mode(vcpu)) { |
0f12244f GN |
580 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
581 | return 1; | |
a03490ed CO |
582 | } else { |
583 | if (is_pae(vcpu)) { | |
0f12244f GN |
584 | if (cr3 & CR3_PAE_RESERVED_BITS) |
585 | return 1; | |
586 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) | |
587 | return 1; | |
a03490ed CO |
588 | } |
589 | /* | |
590 | * We don't check reserved bits in nonpae mode, because | |
591 | * this isn't enforced, and VMware depends on this. | |
592 | */ | |
593 | } | |
594 | ||
a03490ed CO |
595 | /* |
596 | * Does the new cr3 value map to physical memory? (Note, we | |
597 | * catch an invalid cr3 even in real-mode, because it would | |
598 | * cause trouble later on when we turn on paging anyway.) | |
599 | * | |
600 | * A real CPU would silently accept an invalid cr3 and would | |
601 | * attempt to use it - with largely undefined (and often hard | |
602 | * to debug) behavior on the guest side. | |
603 | */ | |
604 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
0f12244f GN |
605 | return 1; |
606 | vcpu->arch.cr3 = cr3; | |
607 | vcpu->arch.mmu.new_cr3(vcpu); | |
608 | return 0; | |
609 | } | |
2d3ad1f4 | 610 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 611 | |
0f12244f | 612 | int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 613 | { |
0f12244f GN |
614 | if (cr8 & CR8_RESERVED_BITS) |
615 | return 1; | |
a03490ed CO |
616 | if (irqchip_in_kernel(vcpu->kvm)) |
617 | kvm_lapic_set_tpr(vcpu, cr8); | |
618 | else | |
ad312c7c | 619 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
620 | return 0; |
621 | } | |
622 | ||
623 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) | |
624 | { | |
625 | if (__kvm_set_cr8(vcpu, cr8)) | |
626 | kvm_inject_gp(vcpu, 0); | |
a03490ed | 627 | } |
2d3ad1f4 | 628 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 629 | |
2d3ad1f4 | 630 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
631 | { |
632 | if (irqchip_in_kernel(vcpu->kvm)) | |
633 | return kvm_lapic_get_cr8(vcpu); | |
634 | else | |
ad312c7c | 635 | return vcpu->arch.cr8; |
a03490ed | 636 | } |
2d3ad1f4 | 637 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 638 | |
338dbc97 | 639 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
640 | { |
641 | switch (dr) { | |
642 | case 0 ... 3: | |
643 | vcpu->arch.db[dr] = val; | |
644 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
645 | vcpu->arch.eff_db[dr] = val; | |
646 | break; | |
647 | case 4: | |
338dbc97 GN |
648 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
649 | return 1; /* #UD */ | |
020df079 GN |
650 | /* fall through */ |
651 | case 6: | |
338dbc97 GN |
652 | if (val & 0xffffffff00000000ULL) |
653 | return -1; /* #GP */ | |
020df079 GN |
654 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; |
655 | break; | |
656 | case 5: | |
338dbc97 GN |
657 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
658 | return 1; /* #UD */ | |
020df079 GN |
659 | /* fall through */ |
660 | default: /* 7 */ | |
338dbc97 GN |
661 | if (val & 0xffffffff00000000ULL) |
662 | return -1; /* #GP */ | |
020df079 GN |
663 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
664 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
665 | kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7); | |
666 | vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK); | |
667 | } | |
668 | break; | |
669 | } | |
670 | ||
671 | return 0; | |
672 | } | |
338dbc97 GN |
673 | |
674 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
675 | { | |
676 | int res; | |
677 | ||
678 | res = __kvm_set_dr(vcpu, dr, val); | |
679 | if (res > 0) | |
680 | kvm_queue_exception(vcpu, UD_VECTOR); | |
681 | else if (res < 0) | |
682 | kvm_inject_gp(vcpu, 0); | |
683 | ||
684 | return res; | |
685 | } | |
020df079 GN |
686 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
687 | ||
338dbc97 | 688 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
689 | { |
690 | switch (dr) { | |
691 | case 0 ... 3: | |
692 | *val = vcpu->arch.db[dr]; | |
693 | break; | |
694 | case 4: | |
338dbc97 | 695 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 696 | return 1; |
020df079 GN |
697 | /* fall through */ |
698 | case 6: | |
699 | *val = vcpu->arch.dr6; | |
700 | break; | |
701 | case 5: | |
338dbc97 | 702 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) |
020df079 | 703 | return 1; |
020df079 GN |
704 | /* fall through */ |
705 | default: /* 7 */ | |
706 | *val = vcpu->arch.dr7; | |
707 | break; | |
708 | } | |
709 | ||
710 | return 0; | |
711 | } | |
338dbc97 GN |
712 | |
713 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
714 | { | |
715 | if (_kvm_get_dr(vcpu, dr, val)) { | |
716 | kvm_queue_exception(vcpu, UD_VECTOR); | |
717 | return 1; | |
718 | } | |
719 | return 0; | |
720 | } | |
020df079 GN |
721 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
722 | ||
043405e1 CO |
723 | /* |
724 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
725 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
726 | * | |
727 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
728 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
729 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 730 | */ |
e3267cbb | 731 | |
11c6bffa | 732 | #define KVM_SAVE_MSRS_BEGIN 7 |
043405e1 | 733 | static u32 msrs_to_save[] = { |
e3267cbb | 734 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
11c6bffa | 735 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, |
55cd8e5a | 736 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
10388a07 | 737 | HV_X64_MSR_APIC_ASSIST_PAGE, |
043405e1 | 738 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 739 | MSR_STAR, |
043405e1 CO |
740 | #ifdef CONFIG_X86_64 |
741 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
742 | #endif | |
e90aa41e | 743 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
744 | }; |
745 | ||
746 | static unsigned num_msrs_to_save; | |
747 | ||
748 | static u32 emulated_msrs[] = { | |
749 | MSR_IA32_MISC_ENABLE, | |
908e75f3 AK |
750 | MSR_IA32_MCG_STATUS, |
751 | MSR_IA32_MCG_CTL, | |
043405e1 CO |
752 | }; |
753 | ||
b69e8cae | 754 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 755 | { |
aad82703 SY |
756 | u64 old_efer = vcpu->arch.efer; |
757 | ||
b69e8cae RJ |
758 | if (efer & efer_reserved_bits) |
759 | return 1; | |
15c4a640 CO |
760 | |
761 | if (is_paging(vcpu) | |
b69e8cae RJ |
762 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) |
763 | return 1; | |
15c4a640 | 764 | |
1b2fd70c AG |
765 | if (efer & EFER_FFXSR) { |
766 | struct kvm_cpuid_entry2 *feat; | |
767 | ||
768 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
769 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
770 | return 1; | |
1b2fd70c AG |
771 | } |
772 | ||
d8017474 AG |
773 | if (efer & EFER_SVME) { |
774 | struct kvm_cpuid_entry2 *feat; | |
775 | ||
776 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae RJ |
777 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
778 | return 1; | |
d8017474 AG |
779 | } |
780 | ||
15c4a640 | 781 | efer &= ~EFER_LMA; |
f6801dff | 782 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 783 | |
a3d204e2 SY |
784 | kvm_x86_ops->set_efer(vcpu, efer); |
785 | ||
9645bb56 AK |
786 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; |
787 | kvm_mmu_reset_context(vcpu); | |
b69e8cae | 788 | |
aad82703 SY |
789 | /* Update reserved bits */ |
790 | if ((efer ^ old_efer) & EFER_NX) | |
791 | kvm_mmu_reset_context(vcpu); | |
792 | ||
b69e8cae | 793 | return 0; |
15c4a640 CO |
794 | } |
795 | ||
f2b4b7dd JR |
796 | void kvm_enable_efer_bits(u64 mask) |
797 | { | |
798 | efer_reserved_bits &= ~mask; | |
799 | } | |
800 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
801 | ||
802 | ||
15c4a640 CO |
803 | /* |
804 | * Writes msr value into into the appropriate "register". | |
805 | * Returns 0 on success, non-0 otherwise. | |
806 | * Assumes vcpu_load() was already called. | |
807 | */ | |
808 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
809 | { | |
810 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
811 | } | |
812 | ||
313a3dc7 CO |
813 | /* |
814 | * Adapt set_msr() to msr_io()'s calling convention | |
815 | */ | |
816 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
817 | { | |
818 | return kvm_set_msr(vcpu, index, *data); | |
819 | } | |
820 | ||
18068523 GOC |
821 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
822 | { | |
9ed3c444 AK |
823 | int version; |
824 | int r; | |
50d0a0f9 | 825 | struct pvclock_wall_clock wc; |
923de3cf | 826 | struct timespec boot; |
18068523 GOC |
827 | |
828 | if (!wall_clock) | |
829 | return; | |
830 | ||
9ed3c444 AK |
831 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
832 | if (r) | |
833 | return; | |
834 | ||
835 | if (version & 1) | |
836 | ++version; /* first time write, random junk */ | |
837 | ||
838 | ++version; | |
18068523 | 839 | |
18068523 GOC |
840 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
841 | ||
50d0a0f9 GH |
842 | /* |
843 | * The guest calculates current wall clock time by adding | |
844 | * system time (updated by kvm_write_guest_time below) to the | |
845 | * wall clock specified here. guest system time equals host | |
846 | * system time for us, thus we must fill in host boot time here. | |
847 | */ | |
923de3cf | 848 | getboottime(&boot); |
50d0a0f9 GH |
849 | |
850 | wc.sec = boot.tv_sec; | |
851 | wc.nsec = boot.tv_nsec; | |
852 | wc.version = version; | |
18068523 GOC |
853 | |
854 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
855 | ||
856 | version++; | |
857 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
858 | } |
859 | ||
50d0a0f9 GH |
860 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
861 | { | |
862 | uint32_t quotient, remainder; | |
863 | ||
864 | /* Don't try to replace with do_div(), this one calculates | |
865 | * "(dividend << 32) / divisor" */ | |
866 | __asm__ ( "divl %4" | |
867 | : "=a" (quotient), "=d" (remainder) | |
868 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
869 | return quotient; | |
870 | } | |
871 | ||
872 | static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock) | |
873 | { | |
874 | uint64_t nsecs = 1000000000LL; | |
875 | int32_t shift = 0; | |
876 | uint64_t tps64; | |
877 | uint32_t tps32; | |
878 | ||
879 | tps64 = tsc_khz * 1000LL; | |
880 | while (tps64 > nsecs*2) { | |
881 | tps64 >>= 1; | |
882 | shift--; | |
883 | } | |
884 | ||
885 | tps32 = (uint32_t)tps64; | |
886 | while (tps32 <= (uint32_t)nsecs) { | |
887 | tps32 <<= 1; | |
888 | shift++; | |
889 | } | |
890 | ||
891 | hv_clock->tsc_shift = shift; | |
892 | hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32); | |
893 | ||
894 | pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n", | |
80a914dc | 895 | __func__, tsc_khz, hv_clock->tsc_shift, |
50d0a0f9 GH |
896 | hv_clock->tsc_to_system_mul); |
897 | } | |
898 | ||
759379dd ZA |
899 | static inline u64 get_kernel_ns(void) |
900 | { | |
901 | struct timespec ts; | |
902 | ||
903 | WARN_ON(preemptible()); | |
904 | ktime_get_ts(&ts); | |
905 | monotonic_to_bootbased(&ts); | |
906 | return timespec_to_ns(&ts); | |
907 | } | |
908 | ||
c8076604 GH |
909 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
910 | ||
8cfdc000 ZA |
911 | static inline int kvm_tsc_changes_freq(void) |
912 | { | |
913 | int cpu = get_cpu(); | |
914 | int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && | |
915 | cpufreq_quick_get(cpu) != 0; | |
916 | put_cpu(); | |
917 | return ret; | |
918 | } | |
919 | ||
759379dd ZA |
920 | static inline u64 nsec_to_cycles(u64 nsec) |
921 | { | |
217fc9cf AK |
922 | u64 ret; |
923 | ||
759379dd ZA |
924 | WARN_ON(preemptible()); |
925 | if (kvm_tsc_changes_freq()) | |
926 | printk_once(KERN_WARNING | |
927 | "kvm: unreliable cycle conversion on adjustable rate TSC\n"); | |
217fc9cf AK |
928 | ret = nsec * __get_cpu_var(cpu_tsc_khz); |
929 | do_div(ret, USEC_PER_SEC); | |
930 | return ret; | |
759379dd ZA |
931 | } |
932 | ||
99e3e30a ZA |
933 | void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data) |
934 | { | |
935 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 936 | u64 offset, ns, elapsed; |
99e3e30a | 937 | unsigned long flags; |
46543ba4 | 938 | s64 sdiff; |
99e3e30a ZA |
939 | |
940 | spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
941 | offset = data - native_read_tsc(); | |
759379dd | 942 | ns = get_kernel_ns(); |
f38e098f | 943 | elapsed = ns - kvm->arch.last_tsc_nsec; |
46543ba4 ZA |
944 | sdiff = data - kvm->arch.last_tsc_write; |
945 | if (sdiff < 0) | |
946 | sdiff = -sdiff; | |
f38e098f ZA |
947 | |
948 | /* | |
46543ba4 | 949 | * Special case: close write to TSC within 5 seconds of |
f38e098f | 950 | * another CPU is interpreted as an attempt to synchronize |
46543ba4 ZA |
951 | * The 5 seconds is to accomodate host load / swapping as |
952 | * well as any reset of TSC during the boot process. | |
f38e098f ZA |
953 | * |
954 | * In that case, for a reliable TSC, we can match TSC offsets, | |
46543ba4 | 955 | * or make a best guest using elapsed value. |
f38e098f | 956 | */ |
46543ba4 ZA |
957 | if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) && |
958 | elapsed < 5ULL * NSEC_PER_SEC) { | |
f38e098f ZA |
959 | if (!check_tsc_unstable()) { |
960 | offset = kvm->arch.last_tsc_offset; | |
961 | pr_debug("kvm: matched tsc offset for %llu\n", data); | |
962 | } else { | |
759379dd ZA |
963 | u64 delta = nsec_to_cycles(elapsed); |
964 | offset += delta; | |
965 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); | |
f38e098f ZA |
966 | } |
967 | ns = kvm->arch.last_tsc_nsec; | |
968 | } | |
969 | kvm->arch.last_tsc_nsec = ns; | |
970 | kvm->arch.last_tsc_write = data; | |
971 | kvm->arch.last_tsc_offset = offset; | |
99e3e30a ZA |
972 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
973 | spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
974 | ||
975 | /* Reset of TSC must disable overshoot protection below */ | |
976 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
977 | } | |
978 | EXPORT_SYMBOL_GPL(kvm_write_tsc); | |
979 | ||
8cfdc000 | 980 | static int kvm_write_guest_time(struct kvm_vcpu *v) |
18068523 | 981 | { |
18068523 GOC |
982 | unsigned long flags; |
983 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
984 | void *shared_kaddr; | |
463656c0 | 985 | unsigned long this_tsc_khz; |
1d5f066e ZA |
986 | s64 kernel_ns, max_kernel_ns; |
987 | u64 tsc_timestamp; | |
18068523 GOC |
988 | |
989 | if ((!vcpu->time_page)) | |
8cfdc000 | 990 | return 0; |
50d0a0f9 | 991 | |
18068523 GOC |
992 | /* Keep irq disabled to prevent changes to the clock */ |
993 | local_irq_save(flags); | |
1d5f066e | 994 | kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp); |
759379dd | 995 | kernel_ns = get_kernel_ns(); |
8cfdc000 | 996 | this_tsc_khz = __get_cpu_var(cpu_tsc_khz); |
18068523 GOC |
997 | local_irq_restore(flags); |
998 | ||
8cfdc000 ZA |
999 | if (unlikely(this_tsc_khz == 0)) { |
1000 | kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v); | |
1001 | return 1; | |
1002 | } | |
18068523 | 1003 | |
1d5f066e ZA |
1004 | /* |
1005 | * Time as measured by the TSC may go backwards when resetting the base | |
1006 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1007 | * higher than the resolution of the other clock scales. Thus, many | |
1008 | * possible measurments of the TSC correspond to one measurement of any | |
1009 | * other clock, and so a spread of values is possible. This is not a | |
1010 | * problem for the computation of the nanosecond clock; with TSC rates | |
1011 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1012 | * nanosecond value, and any path through this code will inevitably | |
1013 | * take longer than that. However, with the kernel_ns value itself, | |
1014 | * the precision may be much lower, down to HZ granularity. If the | |
1015 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1016 | * range, and the second in the high end of the range, we can get: | |
1017 | * | |
1018 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1019 | * | |
1020 | * As the sampling errors potentially range in the thousands of cycles, | |
1021 | * it is possible such a time value has already been observed by the | |
1022 | * guest. To protect against this, we must compute the system time as | |
1023 | * observed by the guest and ensure the new system time is greater. | |
1024 | */ | |
1025 | max_kernel_ns = 0; | |
1026 | if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) { | |
1027 | max_kernel_ns = vcpu->last_guest_tsc - | |
1028 | vcpu->hv_clock.tsc_timestamp; | |
1029 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1030 | vcpu->hv_clock.tsc_to_system_mul, | |
1031 | vcpu->hv_clock.tsc_shift); | |
1032 | max_kernel_ns += vcpu->last_kernel_ns; | |
1033 | } | |
1034 | ||
e48672fa | 1035 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
8cfdc000 | 1036 | kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock); |
e48672fa | 1037 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1038 | } |
1039 | ||
1d5f066e ZA |
1040 | if (max_kernel_ns > kernel_ns) |
1041 | kernel_ns = max_kernel_ns; | |
1042 | ||
8cfdc000 | 1043 | /* With all the info we got, fill in the values */ |
1d5f066e | 1044 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1045 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
1d5f066e | 1046 | vcpu->last_kernel_ns = kernel_ns; |
371bcf64 GC |
1047 | vcpu->hv_clock.flags = 0; |
1048 | ||
18068523 GOC |
1049 | /* |
1050 | * The interface expects us to write an even number signaling that the | |
1051 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 1052 | * state, we just increase by 2 at the end. |
18068523 | 1053 | */ |
50d0a0f9 | 1054 | vcpu->hv_clock.version += 2; |
18068523 GOC |
1055 | |
1056 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
1057 | ||
1058 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 1059 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
1060 | |
1061 | kunmap_atomic(shared_kaddr, KM_USER0); | |
1062 | ||
1063 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
8cfdc000 | 1064 | return 0; |
18068523 GOC |
1065 | } |
1066 | ||
c8076604 GH |
1067 | static int kvm_request_guest_time_update(struct kvm_vcpu *v) |
1068 | { | |
1069 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1070 | ||
1071 | if (!vcpu->time_page) | |
1072 | return 0; | |
a8eeb04a | 1073 | kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v); |
c8076604 GH |
1074 | return 1; |
1075 | } | |
1076 | ||
9ba075a6 AK |
1077 | static bool msr_mtrr_valid(unsigned msr) |
1078 | { | |
1079 | switch (msr) { | |
1080 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1081 | case MSR_MTRRfix64K_00000: | |
1082 | case MSR_MTRRfix16K_80000: | |
1083 | case MSR_MTRRfix16K_A0000: | |
1084 | case MSR_MTRRfix4K_C0000: | |
1085 | case MSR_MTRRfix4K_C8000: | |
1086 | case MSR_MTRRfix4K_D0000: | |
1087 | case MSR_MTRRfix4K_D8000: | |
1088 | case MSR_MTRRfix4K_E0000: | |
1089 | case MSR_MTRRfix4K_E8000: | |
1090 | case MSR_MTRRfix4K_F0000: | |
1091 | case MSR_MTRRfix4K_F8000: | |
1092 | case MSR_MTRRdefType: | |
1093 | case MSR_IA32_CR_PAT: | |
1094 | return true; | |
1095 | case 0x2f8: | |
1096 | return true; | |
1097 | } | |
1098 | return false; | |
1099 | } | |
1100 | ||
d6289b93 MT |
1101 | static bool valid_pat_type(unsigned t) |
1102 | { | |
1103 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1104 | } | |
1105 | ||
1106 | static bool valid_mtrr_type(unsigned t) | |
1107 | { | |
1108 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1109 | } | |
1110 | ||
1111 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1112 | { | |
1113 | int i; | |
1114 | ||
1115 | if (!msr_mtrr_valid(msr)) | |
1116 | return false; | |
1117 | ||
1118 | if (msr == MSR_IA32_CR_PAT) { | |
1119 | for (i = 0; i < 8; i++) | |
1120 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1121 | return false; | |
1122 | return true; | |
1123 | } else if (msr == MSR_MTRRdefType) { | |
1124 | if (data & ~0xcff) | |
1125 | return false; | |
1126 | return valid_mtrr_type(data & 0xff); | |
1127 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1128 | for (i = 0; i < 8 ; i++) | |
1129 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1130 | return false; | |
1131 | return true; | |
1132 | } | |
1133 | ||
1134 | /* variable MTRRs */ | |
1135 | return valid_mtrr_type(data & 0xff); | |
1136 | } | |
1137 | ||
9ba075a6 AK |
1138 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1139 | { | |
0bed3b56 SY |
1140 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1141 | ||
d6289b93 | 1142 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1143 | return 1; |
1144 | ||
0bed3b56 SY |
1145 | if (msr == MSR_MTRRdefType) { |
1146 | vcpu->arch.mtrr_state.def_type = data; | |
1147 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1148 | } else if (msr == MSR_MTRRfix64K_00000) | |
1149 | p[0] = data; | |
1150 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1151 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1152 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1153 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1154 | else if (msr == MSR_IA32_CR_PAT) | |
1155 | vcpu->arch.pat = data; | |
1156 | else { /* Variable MTRRs */ | |
1157 | int idx, is_mtrr_mask; | |
1158 | u64 *pt; | |
1159 | ||
1160 | idx = (msr - 0x200) / 2; | |
1161 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1162 | if (!is_mtrr_mask) | |
1163 | pt = | |
1164 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1165 | else | |
1166 | pt = | |
1167 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1168 | *pt = data; | |
1169 | } | |
1170 | ||
1171 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
1172 | return 0; |
1173 | } | |
15c4a640 | 1174 | |
890ca9ae | 1175 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1176 | { |
890ca9ae HY |
1177 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1178 | unsigned bank_num = mcg_cap & 0xff; | |
1179 | ||
15c4a640 | 1180 | switch (msr) { |
15c4a640 | 1181 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1182 | vcpu->arch.mcg_status = data; |
15c4a640 | 1183 | break; |
c7ac679c | 1184 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1185 | if (!(mcg_cap & MCG_CTL_P)) |
1186 | return 1; | |
1187 | if (data != 0 && data != ~(u64)0) | |
1188 | return -1; | |
1189 | vcpu->arch.mcg_ctl = data; | |
1190 | break; | |
1191 | default: | |
1192 | if (msr >= MSR_IA32_MC0_CTL && | |
1193 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1194 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
1195 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1196 | * some Linux kernels though clear bit 10 in bank 4 to | |
1197 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1198 | * this to avoid an uncatched #GP in the guest | |
1199 | */ | |
890ca9ae | 1200 | if ((offset & 0x3) == 0 && |
114be429 | 1201 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
1202 | return -1; |
1203 | vcpu->arch.mce_banks[offset] = data; | |
1204 | break; | |
1205 | } | |
1206 | return 1; | |
1207 | } | |
1208 | return 0; | |
1209 | } | |
1210 | ||
ffde22ac ES |
1211 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
1212 | { | |
1213 | struct kvm *kvm = vcpu->kvm; | |
1214 | int lm = is_long_mode(vcpu); | |
1215 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1216 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1217 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1218 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1219 | u32 page_num = data & ~PAGE_MASK; | |
1220 | u64 page_addr = data & PAGE_MASK; | |
1221 | u8 *page; | |
1222 | int r; | |
1223 | ||
1224 | r = -E2BIG; | |
1225 | if (page_num >= blob_size) | |
1226 | goto out; | |
1227 | r = -ENOMEM; | |
1228 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
1229 | if (!page) | |
1230 | goto out; | |
1231 | r = -EFAULT; | |
1232 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
1233 | goto out_free; | |
1234 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
1235 | goto out_free; | |
1236 | r = 0; | |
1237 | out_free: | |
1238 | kfree(page); | |
1239 | out: | |
1240 | return r; | |
1241 | } | |
1242 | ||
55cd8e5a GN |
1243 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
1244 | { | |
1245 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1246 | } | |
1247 | ||
1248 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1249 | { | |
1250 | bool r = false; | |
1251 | switch (msr) { | |
1252 | case HV_X64_MSR_GUEST_OS_ID: | |
1253 | case HV_X64_MSR_HYPERCALL: | |
1254 | r = true; | |
1255 | break; | |
1256 | } | |
1257 | ||
1258 | return r; | |
1259 | } | |
1260 | ||
1261 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1262 | { | |
1263 | struct kvm *kvm = vcpu->kvm; | |
1264 | ||
1265 | switch (msr) { | |
1266 | case HV_X64_MSR_GUEST_OS_ID: | |
1267 | kvm->arch.hv_guest_os_id = data; | |
1268 | /* setting guest os id to zero disables hypercall page */ | |
1269 | if (!kvm->arch.hv_guest_os_id) | |
1270 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1271 | break; | |
1272 | case HV_X64_MSR_HYPERCALL: { | |
1273 | u64 gfn; | |
1274 | unsigned long addr; | |
1275 | u8 instructions[4]; | |
1276 | ||
1277 | /* if guest os id is not set hypercall should remain disabled */ | |
1278 | if (!kvm->arch.hv_guest_os_id) | |
1279 | break; | |
1280 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1281 | kvm->arch.hv_hypercall = data; | |
1282 | break; | |
1283 | } | |
1284 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1285 | addr = gfn_to_hva(kvm, gfn); | |
1286 | if (kvm_is_error_hva(addr)) | |
1287 | return 1; | |
1288 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1289 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1290 | if (copy_to_user((void __user *)addr, instructions, 4)) | |
1291 | return 1; | |
1292 | kvm->arch.hv_hypercall = data; | |
1293 | break; | |
1294 | } | |
1295 | default: | |
1296 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1297 | "data 0x%llx\n", msr, data); | |
1298 | return 1; | |
1299 | } | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1304 | { | |
10388a07 GN |
1305 | switch (msr) { |
1306 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1307 | unsigned long addr; | |
55cd8e5a | 1308 | |
10388a07 GN |
1309 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1310 | vcpu->arch.hv_vapic = data; | |
1311 | break; | |
1312 | } | |
1313 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1314 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1315 | if (kvm_is_error_hva(addr)) | |
1316 | return 1; | |
1317 | if (clear_user((void __user *)addr, PAGE_SIZE)) | |
1318 | return 1; | |
1319 | vcpu->arch.hv_vapic = data; | |
1320 | break; | |
1321 | } | |
1322 | case HV_X64_MSR_EOI: | |
1323 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1324 | case HV_X64_MSR_ICR: | |
1325 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1326 | case HV_X64_MSR_TPR: | |
1327 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1328 | default: | |
1329 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1330 | "data 0x%llx\n", msr, data); | |
1331 | return 1; | |
1332 | } | |
1333 | ||
1334 | return 0; | |
55cd8e5a GN |
1335 | } |
1336 | ||
15c4a640 CO |
1337 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1338 | { | |
1339 | switch (msr) { | |
15c4a640 | 1340 | case MSR_EFER: |
b69e8cae | 1341 | return set_efer(vcpu, data); |
8f1589d9 AP |
1342 | case MSR_K7_HWCR: |
1343 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1344 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
8f1589d9 AP |
1345 | if (data != 0) { |
1346 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1347 | data); | |
1348 | return 1; | |
1349 | } | |
15c4a640 | 1350 | break; |
f7c6d140 AP |
1351 | case MSR_FAM10H_MMIO_CONF_BASE: |
1352 | if (data != 0) { | |
1353 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
1354 | "0x%llx\n", data); | |
1355 | return 1; | |
1356 | } | |
15c4a640 | 1357 | break; |
c323c0e5 | 1358 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1359 | break; |
b5e2fec0 AG |
1360 | case MSR_IA32_DEBUGCTLMSR: |
1361 | if (!data) { | |
1362 | /* We support the non-activated case already */ | |
1363 | break; | |
1364 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1365 | /* Values other than LBR and BTF are vendor-specific, | |
1366 | thus reserved and should throw a #GP */ | |
1367 | return 1; | |
1368 | } | |
1369 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1370 | __func__, data); | |
1371 | break; | |
15c4a640 CO |
1372 | case MSR_IA32_UCODE_REV: |
1373 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1374 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1375 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1376 | break; |
9ba075a6 AK |
1377 | case 0x200 ... 0x2ff: |
1378 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1379 | case MSR_IA32_APICBASE: |
1380 | kvm_set_apic_base(vcpu, data); | |
1381 | break; | |
0105d1a5 GN |
1382 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1383 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 1384 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1385 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1386 | break; |
11c6bffa | 1387 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1388 | case MSR_KVM_WALL_CLOCK: |
1389 | vcpu->kvm->arch.wall_clock = data; | |
1390 | kvm_write_wall_clock(vcpu->kvm, data); | |
1391 | break; | |
11c6bffa | 1392 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1393 | case MSR_KVM_SYSTEM_TIME: { |
1394 | if (vcpu->arch.time_page) { | |
1395 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1396 | vcpu->arch.time_page = NULL; | |
1397 | } | |
1398 | ||
1399 | vcpu->arch.time = data; | |
1400 | ||
1401 | /* we verify if the enable bit is set... */ | |
1402 | if (!(data & 1)) | |
1403 | break; | |
1404 | ||
1405 | /* ...but clean it before doing the actual write */ | |
1406 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1407 | ||
18068523 GOC |
1408 | vcpu->arch.time_page = |
1409 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1410 | |
1411 | if (is_error_page(vcpu->arch.time_page)) { | |
1412 | kvm_release_page_clean(vcpu->arch.time_page); | |
1413 | vcpu->arch.time_page = NULL; | |
1414 | } | |
1415 | ||
c8076604 | 1416 | kvm_request_guest_time_update(vcpu); |
18068523 GOC |
1417 | break; |
1418 | } | |
890ca9ae HY |
1419 | case MSR_IA32_MCG_CTL: |
1420 | case MSR_IA32_MCG_STATUS: | |
1421 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1422 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1423 | |
1424 | /* Performance counters are not protected by a CPUID bit, | |
1425 | * so we should check all of them in the generic path for the sake of | |
1426 | * cross vendor migration. | |
1427 | * Writing a zero into the event select MSRs disables them, | |
1428 | * which we perfectly emulate ;-). Any other value should be at least | |
1429 | * reported, some guests depend on them. | |
1430 | */ | |
1431 | case MSR_P6_EVNTSEL0: | |
1432 | case MSR_P6_EVNTSEL1: | |
1433 | case MSR_K7_EVNTSEL0: | |
1434 | case MSR_K7_EVNTSEL1: | |
1435 | case MSR_K7_EVNTSEL2: | |
1436 | case MSR_K7_EVNTSEL3: | |
1437 | if (data != 0) | |
1438 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1439 | "0x%x data 0x%llx\n", msr, data); | |
1440 | break; | |
1441 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1442 | * so we ignore writes to make it happy. | |
1443 | */ | |
1444 | case MSR_P6_PERFCTR0: | |
1445 | case MSR_P6_PERFCTR1: | |
1446 | case MSR_K7_PERFCTR0: | |
1447 | case MSR_K7_PERFCTR1: | |
1448 | case MSR_K7_PERFCTR2: | |
1449 | case MSR_K7_PERFCTR3: | |
1450 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1451 | "0x%x data 0x%llx\n", msr, data); | |
1452 | break; | |
84e0cefa JS |
1453 | case MSR_K7_CLK_CTL: |
1454 | /* | |
1455 | * Ignore all writes to this no longer documented MSR. | |
1456 | * Writes are only relevant for old K7 processors, | |
1457 | * all pre-dating SVM, but a recommended workaround from | |
1458 | * AMD for these chips. It is possible to speicify the | |
1459 | * affected processor models on the command line, hence | |
1460 | * the need to ignore the workaround. | |
1461 | */ | |
1462 | break; | |
55cd8e5a GN |
1463 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1464 | if (kvm_hv_msr_partition_wide(msr)) { | |
1465 | int r; | |
1466 | mutex_lock(&vcpu->kvm->lock); | |
1467 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1468 | mutex_unlock(&vcpu->kvm->lock); | |
1469 | return r; | |
1470 | } else | |
1471 | return set_msr_hyperv(vcpu, msr, data); | |
1472 | break; | |
15c4a640 | 1473 | default: |
ffde22ac ES |
1474 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1475 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1476 | if (!ignore_msrs) { |
1477 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1478 | msr, data); | |
1479 | return 1; | |
1480 | } else { | |
1481 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1482 | msr, data); | |
1483 | break; | |
1484 | } | |
15c4a640 CO |
1485 | } |
1486 | return 0; | |
1487 | } | |
1488 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1489 | ||
1490 | ||
1491 | /* | |
1492 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1493 | * Returns 0 on success, non-0 otherwise. | |
1494 | * Assumes vcpu_load() was already called. | |
1495 | */ | |
1496 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1497 | { | |
1498 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1499 | } | |
1500 | ||
9ba075a6 AK |
1501 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1502 | { | |
0bed3b56 SY |
1503 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1504 | ||
9ba075a6 AK |
1505 | if (!msr_mtrr_valid(msr)) |
1506 | return 1; | |
1507 | ||
0bed3b56 SY |
1508 | if (msr == MSR_MTRRdefType) |
1509 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1510 | (vcpu->arch.mtrr_state.enabled << 10); | |
1511 | else if (msr == MSR_MTRRfix64K_00000) | |
1512 | *pdata = p[0]; | |
1513 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1514 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1515 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1516 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1517 | else if (msr == MSR_IA32_CR_PAT) | |
1518 | *pdata = vcpu->arch.pat; | |
1519 | else { /* Variable MTRRs */ | |
1520 | int idx, is_mtrr_mask; | |
1521 | u64 *pt; | |
1522 | ||
1523 | idx = (msr - 0x200) / 2; | |
1524 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1525 | if (!is_mtrr_mask) | |
1526 | pt = | |
1527 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1528 | else | |
1529 | pt = | |
1530 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1531 | *pdata = *pt; | |
1532 | } | |
1533 | ||
9ba075a6 AK |
1534 | return 0; |
1535 | } | |
1536 | ||
890ca9ae | 1537 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1538 | { |
1539 | u64 data; | |
890ca9ae HY |
1540 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1541 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1542 | |
1543 | switch (msr) { | |
15c4a640 CO |
1544 | case MSR_IA32_P5_MC_ADDR: |
1545 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1546 | data = 0; |
1547 | break; | |
15c4a640 | 1548 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1549 | data = vcpu->arch.mcg_cap; |
1550 | break; | |
c7ac679c | 1551 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1552 | if (!(mcg_cap & MCG_CTL_P)) |
1553 | return 1; | |
1554 | data = vcpu->arch.mcg_ctl; | |
1555 | break; | |
1556 | case MSR_IA32_MCG_STATUS: | |
1557 | data = vcpu->arch.mcg_status; | |
1558 | break; | |
1559 | default: | |
1560 | if (msr >= MSR_IA32_MC0_CTL && | |
1561 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1562 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1563 | data = vcpu->arch.mce_banks[offset]; | |
1564 | break; | |
1565 | } | |
1566 | return 1; | |
1567 | } | |
1568 | *pdata = data; | |
1569 | return 0; | |
1570 | } | |
1571 | ||
55cd8e5a GN |
1572 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1573 | { | |
1574 | u64 data = 0; | |
1575 | struct kvm *kvm = vcpu->kvm; | |
1576 | ||
1577 | switch (msr) { | |
1578 | case HV_X64_MSR_GUEST_OS_ID: | |
1579 | data = kvm->arch.hv_guest_os_id; | |
1580 | break; | |
1581 | case HV_X64_MSR_HYPERCALL: | |
1582 | data = kvm->arch.hv_hypercall; | |
1583 | break; | |
1584 | default: | |
1585 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1586 | return 1; | |
1587 | } | |
1588 | ||
1589 | *pdata = data; | |
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1594 | { | |
1595 | u64 data = 0; | |
1596 | ||
1597 | switch (msr) { | |
1598 | case HV_X64_MSR_VP_INDEX: { | |
1599 | int r; | |
1600 | struct kvm_vcpu *v; | |
1601 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1602 | if (v == vcpu) | |
1603 | data = r; | |
1604 | break; | |
1605 | } | |
10388a07 GN |
1606 | case HV_X64_MSR_EOI: |
1607 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1608 | case HV_X64_MSR_ICR: | |
1609 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1610 | case HV_X64_MSR_TPR: | |
1611 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
55cd8e5a GN |
1612 | default: |
1613 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1614 | return 1; | |
1615 | } | |
1616 | *pdata = data; | |
1617 | return 0; | |
1618 | } | |
1619 | ||
890ca9ae HY |
1620 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1621 | { | |
1622 | u64 data; | |
1623 | ||
1624 | switch (msr) { | |
890ca9ae | 1625 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1626 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1627 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1628 | case MSR_IA32_DEBUGCTLMSR: |
1629 | case MSR_IA32_LASTBRANCHFROMIP: | |
1630 | case MSR_IA32_LASTBRANCHTOIP: | |
1631 | case MSR_IA32_LASTINTFROMIP: | |
1632 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1633 | case MSR_K8_SYSCFG: |
1634 | case MSR_K7_HWCR: | |
61a6bd67 | 1635 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1636 | case MSR_P6_PERFCTR0: |
1637 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1638 | case MSR_P6_EVNTSEL0: |
1639 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1640 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1641 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1642 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1643 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1644 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1645 | data = 0; |
1646 | break; | |
9ba075a6 AK |
1647 | case MSR_MTRRcap: |
1648 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1649 | break; | |
1650 | case 0x200 ... 0x2ff: | |
1651 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1652 | case 0xcd: /* fsb frequency */ |
1653 | data = 3; | |
1654 | break; | |
7b914098 JS |
1655 | /* |
1656 | * MSR_EBC_FREQUENCY_ID | |
1657 | * Conservative value valid for even the basic CPU models. | |
1658 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
1659 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
1660 | * and 266MHz for model 3, or 4. Set Core Clock | |
1661 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
1662 | * 31:24) even though these are only valid for CPU | |
1663 | * models > 2, however guests may end up dividing or | |
1664 | * multiplying by zero otherwise. | |
1665 | */ | |
1666 | case MSR_EBC_FREQUENCY_ID: | |
1667 | data = 1 << 24; | |
1668 | break; | |
15c4a640 CO |
1669 | case MSR_IA32_APICBASE: |
1670 | data = kvm_get_apic_base(vcpu); | |
1671 | break; | |
0105d1a5 GN |
1672 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1673 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1674 | break; | |
15c4a640 | 1675 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1676 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1677 | break; |
847f0ad8 AG |
1678 | case MSR_IA32_PERF_STATUS: |
1679 | /* TSC increment by tick */ | |
1680 | data = 1000ULL; | |
1681 | /* CPU multiplier */ | |
1682 | data |= (((uint64_t)4ULL) << 40); | |
1683 | break; | |
15c4a640 | 1684 | case MSR_EFER: |
f6801dff | 1685 | data = vcpu->arch.efer; |
15c4a640 | 1686 | break; |
18068523 | 1687 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 1688 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
1689 | data = vcpu->kvm->arch.wall_clock; |
1690 | break; | |
1691 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 1692 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 GOC |
1693 | data = vcpu->arch.time; |
1694 | break; | |
890ca9ae HY |
1695 | case MSR_IA32_P5_MC_ADDR: |
1696 | case MSR_IA32_P5_MC_TYPE: | |
1697 | case MSR_IA32_MCG_CAP: | |
1698 | case MSR_IA32_MCG_CTL: | |
1699 | case MSR_IA32_MCG_STATUS: | |
1700 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1701 | return get_msr_mce(vcpu, msr, pdata); | |
84e0cefa JS |
1702 | case MSR_K7_CLK_CTL: |
1703 | /* | |
1704 | * Provide expected ramp-up count for K7. All other | |
1705 | * are set to zero, indicating minimum divisors for | |
1706 | * every field. | |
1707 | * | |
1708 | * This prevents guest kernels on AMD host with CPU | |
1709 | * type 6, model 8 and higher from exploding due to | |
1710 | * the rdmsr failing. | |
1711 | */ | |
1712 | data = 0x20000000; | |
1713 | break; | |
55cd8e5a GN |
1714 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1715 | if (kvm_hv_msr_partition_wide(msr)) { | |
1716 | int r; | |
1717 | mutex_lock(&vcpu->kvm->lock); | |
1718 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
1719 | mutex_unlock(&vcpu->kvm->lock); | |
1720 | return r; | |
1721 | } else | |
1722 | return get_msr_hyperv(vcpu, msr, pdata); | |
1723 | break; | |
15c4a640 | 1724 | default: |
ed85c068 AP |
1725 | if (!ignore_msrs) { |
1726 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1727 | return 1; | |
1728 | } else { | |
1729 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1730 | data = 0; | |
1731 | } | |
1732 | break; | |
15c4a640 CO |
1733 | } |
1734 | *pdata = data; | |
1735 | return 0; | |
1736 | } | |
1737 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1738 | ||
313a3dc7 CO |
1739 | /* |
1740 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1741 | * | |
1742 | * @return number of msrs set successfully. | |
1743 | */ | |
1744 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1745 | struct kvm_msr_entry *entries, | |
1746 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1747 | unsigned index, u64 *data)) | |
1748 | { | |
f656ce01 | 1749 | int i, idx; |
313a3dc7 | 1750 | |
f656ce01 | 1751 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
1752 | for (i = 0; i < msrs->nmsrs; ++i) |
1753 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1754 | break; | |
f656ce01 | 1755 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 1756 | |
313a3dc7 CO |
1757 | return i; |
1758 | } | |
1759 | ||
1760 | /* | |
1761 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1762 | * | |
1763 | * @return number of msrs set successfully. | |
1764 | */ | |
1765 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1766 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1767 | unsigned index, u64 *data), | |
1768 | int writeback) | |
1769 | { | |
1770 | struct kvm_msrs msrs; | |
1771 | struct kvm_msr_entry *entries; | |
1772 | int r, n; | |
1773 | unsigned size; | |
1774 | ||
1775 | r = -EFAULT; | |
1776 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1777 | goto out; | |
1778 | ||
1779 | r = -E2BIG; | |
1780 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1781 | goto out; | |
1782 | ||
1783 | r = -ENOMEM; | |
1784 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
7a73c028 | 1785 | entries = kmalloc(size, GFP_KERNEL); |
313a3dc7 CO |
1786 | if (!entries) |
1787 | goto out; | |
1788 | ||
1789 | r = -EFAULT; | |
1790 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1791 | goto out_free; | |
1792 | ||
1793 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1794 | if (r < 0) | |
1795 | goto out_free; | |
1796 | ||
1797 | r = -EFAULT; | |
1798 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1799 | goto out_free; | |
1800 | ||
1801 | r = n; | |
1802 | ||
1803 | out_free: | |
7a73c028 | 1804 | kfree(entries); |
313a3dc7 CO |
1805 | out: |
1806 | return r; | |
1807 | } | |
1808 | ||
018d00d2 ZX |
1809 | int kvm_dev_ioctl_check_extension(long ext) |
1810 | { | |
1811 | int r; | |
1812 | ||
1813 | switch (ext) { | |
1814 | case KVM_CAP_IRQCHIP: | |
1815 | case KVM_CAP_HLT: | |
1816 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1817 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1818 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1819 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1820 | case KVM_CAP_PIT: |
a28e4f5a | 1821 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1822 | case KVM_CAP_MP_STATE: |
ed848624 | 1823 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1824 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1825 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1826 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1827 | case KVM_CAP_IRQFD: |
d34e6b17 | 1828 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1829 | case KVM_CAP_PIT2: |
e9f42757 | 1830 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1831 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1832 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1833 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1834 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 1835 | case KVM_CAP_HYPERV: |
10388a07 | 1836 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 1837 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 1838 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 1839 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 1840 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 1841 | case KVM_CAP_XSAVE: |
018d00d2 ZX |
1842 | r = 1; |
1843 | break; | |
542472b5 LV |
1844 | case KVM_CAP_COALESCED_MMIO: |
1845 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1846 | break; | |
774ead3a AK |
1847 | case KVM_CAP_VAPIC: |
1848 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1849 | break; | |
f725230a AK |
1850 | case KVM_CAP_NR_VCPUS: |
1851 | r = KVM_MAX_VCPUS; | |
1852 | break; | |
a988b910 AK |
1853 | case KVM_CAP_NR_MEMSLOTS: |
1854 | r = KVM_MEMORY_SLOTS; | |
1855 | break; | |
a68a6a72 MT |
1856 | case KVM_CAP_PV_MMU: /* obsolete */ |
1857 | r = 0; | |
2f333bcb | 1858 | break; |
62c476c7 | 1859 | case KVM_CAP_IOMMU: |
19de40a8 | 1860 | r = iommu_found(); |
62c476c7 | 1861 | break; |
890ca9ae HY |
1862 | case KVM_CAP_MCE: |
1863 | r = KVM_MAX_MCE_BANKS; | |
1864 | break; | |
2d5b5a66 SY |
1865 | case KVM_CAP_XCRS: |
1866 | r = cpu_has_xsave; | |
1867 | break; | |
018d00d2 ZX |
1868 | default: |
1869 | r = 0; | |
1870 | break; | |
1871 | } | |
1872 | return r; | |
1873 | ||
1874 | } | |
1875 | ||
043405e1 CO |
1876 | long kvm_arch_dev_ioctl(struct file *filp, |
1877 | unsigned int ioctl, unsigned long arg) | |
1878 | { | |
1879 | void __user *argp = (void __user *)arg; | |
1880 | long r; | |
1881 | ||
1882 | switch (ioctl) { | |
1883 | case KVM_GET_MSR_INDEX_LIST: { | |
1884 | struct kvm_msr_list __user *user_msr_list = argp; | |
1885 | struct kvm_msr_list msr_list; | |
1886 | unsigned n; | |
1887 | ||
1888 | r = -EFAULT; | |
1889 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
1890 | goto out; | |
1891 | n = msr_list.nmsrs; | |
1892 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
1893 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
1894 | goto out; | |
1895 | r = -E2BIG; | |
e125e7b6 | 1896 | if (n < msr_list.nmsrs) |
043405e1 CO |
1897 | goto out; |
1898 | r = -EFAULT; | |
1899 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
1900 | num_msrs_to_save * sizeof(u32))) | |
1901 | goto out; | |
e125e7b6 | 1902 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
1903 | &emulated_msrs, |
1904 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
1905 | goto out; | |
1906 | r = 0; | |
1907 | break; | |
1908 | } | |
674eea0f AK |
1909 | case KVM_GET_SUPPORTED_CPUID: { |
1910 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1911 | struct kvm_cpuid2 cpuid; | |
1912 | ||
1913 | r = -EFAULT; | |
1914 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1915 | goto out; | |
1916 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 1917 | cpuid_arg->entries); |
674eea0f AK |
1918 | if (r) |
1919 | goto out; | |
1920 | ||
1921 | r = -EFAULT; | |
1922 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1923 | goto out; | |
1924 | r = 0; | |
1925 | break; | |
1926 | } | |
890ca9ae HY |
1927 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
1928 | u64 mce_cap; | |
1929 | ||
1930 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
1931 | r = -EFAULT; | |
1932 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
1933 | goto out; | |
1934 | r = 0; | |
1935 | break; | |
1936 | } | |
043405e1 CO |
1937 | default: |
1938 | r = -EINVAL; | |
1939 | } | |
1940 | out: | |
1941 | return r; | |
1942 | } | |
1943 | ||
f5f48ee1 SY |
1944 | static void wbinvd_ipi(void *garbage) |
1945 | { | |
1946 | wbinvd(); | |
1947 | } | |
1948 | ||
1949 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
1950 | { | |
1951 | return vcpu->kvm->arch.iommu_domain && | |
1952 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY); | |
1953 | } | |
1954 | ||
313a3dc7 CO |
1955 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1956 | { | |
f5f48ee1 SY |
1957 | /* Address WBINVD may be executed by guest */ |
1958 | if (need_emulate_wbinvd(vcpu)) { | |
1959 | if (kvm_x86_ops->has_wbinvd_exit()) | |
1960 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
1961 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
1962 | smp_call_function_single(vcpu->cpu, | |
1963 | wbinvd_ipi, NULL, 1); | |
1964 | } | |
1965 | ||
313a3dc7 | 1966 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
48434c20 | 1967 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
e48672fa ZA |
1968 | /* Make sure TSC doesn't go backwards */ |
1969 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : | |
1970 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
1971 | if (tsc_delta < 0) | |
1972 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
1973 | if (check_tsc_unstable()) | |
1974 | kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta); | |
1975 | kvm_migrate_timers(vcpu); | |
1976 | vcpu->cpu = cpu; | |
1977 | } | |
313a3dc7 CO |
1978 | } |
1979 | ||
1980 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
1981 | { | |
02daab21 | 1982 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 1983 | kvm_put_guest_fpu(vcpu); |
e48672fa | 1984 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
1985 | } |
1986 | ||
07716717 | 1987 | static int is_efer_nx(void) |
313a3dc7 | 1988 | { |
e286e86e | 1989 | unsigned long long efer = 0; |
313a3dc7 | 1990 | |
e286e86e | 1991 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
1992 | return efer & EFER_NX; |
1993 | } | |
1994 | ||
1995 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
1996 | { | |
1997 | int i; | |
1998 | struct kvm_cpuid_entry2 *e, *entry; | |
1999 | ||
313a3dc7 | 2000 | entry = NULL; |
ad312c7c ZX |
2001 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
2002 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
2003 | if (e->function == 0x80000001) { |
2004 | entry = e; | |
2005 | break; | |
2006 | } | |
2007 | } | |
07716717 | 2008 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
2009 | entry->edx &= ~(1 << 20); |
2010 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
2011 | } | |
2012 | } | |
2013 | ||
07716717 | 2014 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
2015 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
2016 | struct kvm_cpuid *cpuid, | |
2017 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
2018 | { |
2019 | int r, i; | |
2020 | struct kvm_cpuid_entry *cpuid_entries; | |
2021 | ||
2022 | r = -E2BIG; | |
2023 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2024 | goto out; | |
2025 | r = -ENOMEM; | |
2026 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
2027 | if (!cpuid_entries) | |
2028 | goto out; | |
2029 | r = -EFAULT; | |
2030 | if (copy_from_user(cpuid_entries, entries, | |
2031 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
2032 | goto out_free; | |
2033 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
2034 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
2035 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
2036 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
2037 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
2038 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
2039 | vcpu->arch.cpuid_entries[i].index = 0; | |
2040 | vcpu->arch.cpuid_entries[i].flags = 0; | |
2041 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
2042 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
2043 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
2044 | } | |
2045 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
2046 | cpuid_fix_nx_cap(vcpu); |
2047 | r = 0; | |
fc61b800 | 2048 | kvm_apic_set_version(vcpu); |
0e851880 | 2049 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2050 | update_cpuid(vcpu); |
07716717 DK |
2051 | |
2052 | out_free: | |
2053 | vfree(cpuid_entries); | |
2054 | out: | |
2055 | return r; | |
2056 | } | |
2057 | ||
2058 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
2059 | struct kvm_cpuid2 *cpuid, |
2060 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
2061 | { |
2062 | int r; | |
2063 | ||
2064 | r = -E2BIG; | |
2065 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
2066 | goto out; | |
2067 | r = -EFAULT; | |
ad312c7c | 2068 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 2069 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 2070 | goto out; |
ad312c7c | 2071 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 2072 | kvm_apic_set_version(vcpu); |
0e851880 | 2073 | kvm_x86_ops->cpuid_update(vcpu); |
2acf923e | 2074 | update_cpuid(vcpu); |
313a3dc7 CO |
2075 | return 0; |
2076 | ||
2077 | out: | |
2078 | return r; | |
2079 | } | |
2080 | ||
07716717 | 2081 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
2082 | struct kvm_cpuid2 *cpuid, |
2083 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
2084 | { |
2085 | int r; | |
2086 | ||
2087 | r = -E2BIG; | |
ad312c7c | 2088 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
2089 | goto out; |
2090 | r = -EFAULT; | |
ad312c7c | 2091 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 2092 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2093 | goto out; |
2094 | return 0; | |
2095 | ||
2096 | out: | |
ad312c7c | 2097 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
2098 | return r; |
2099 | } | |
2100 | ||
07716717 | 2101 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 2102 | u32 index) |
07716717 DK |
2103 | { |
2104 | entry->function = function; | |
2105 | entry->index = index; | |
2106 | cpuid_count(entry->function, entry->index, | |
19355475 | 2107 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
2108 | entry->flags = 0; |
2109 | } | |
2110 | ||
7faa4ee1 AK |
2111 | #define F(x) bit(X86_FEATURE_##x) |
2112 | ||
07716717 DK |
2113 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
2114 | u32 index, int *nent, int maxnent) | |
2115 | { | |
7faa4ee1 | 2116 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 2117 | #ifdef CONFIG_X86_64 |
17cc3935 SY |
2118 | unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL) |
2119 | ? F(GBPAGES) : 0; | |
7faa4ee1 AK |
2120 | unsigned f_lm = F(LM); |
2121 | #else | |
17cc3935 | 2122 | unsigned f_gbpages = 0; |
7faa4ee1 | 2123 | unsigned f_lm = 0; |
07716717 | 2124 | #endif |
4e47c7a6 | 2125 | unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0; |
7faa4ee1 AK |
2126 | |
2127 | /* cpuid 1.edx */ | |
2128 | const u32 kvm_supported_word0_x86_features = | |
2129 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2130 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2131 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
2132 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2133 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
2134 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
2135 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
2136 | 0 /* HTT, TM, Reserved, PBE */; | |
2137 | /* cpuid 0x80000001.edx */ | |
2138 | const u32 kvm_supported_word1_x86_features = | |
2139 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
2140 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
2141 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
2142 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
2143 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
2144 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
4e47c7a6 | 2145 | F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp | |
7faa4ee1 AK |
2146 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
2147 | /* cpuid 1.ecx */ | |
2148 | const u32 kvm_supported_word4_x86_features = | |
6c3f6041 | 2149 | F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | |
d149c731 AK |
2150 | 0 /* DS-CPL, VMX, SMX, EST */ | |
2151 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
2152 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
2153 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 2154 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
6c3f6041 | 2155 | 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX); |
7faa4ee1 | 2156 | /* cpuid 0x80000001.ecx */ |
07716717 | 2157 | const u32 kvm_supported_word6_x86_features = |
7faa4ee1 AK |
2158 | F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ | |
2159 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
2160 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) | | |
2161 | 0 /* SKINIT */ | 0 /* WDT */; | |
07716717 | 2162 | |
19355475 | 2163 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
2164 | get_cpu(); |
2165 | do_cpuid_1_ent(entry, function, index); | |
2166 | ++*nent; | |
2167 | ||
2168 | switch (function) { | |
2169 | case 0: | |
2acf923e | 2170 | entry->eax = min(entry->eax, (u32)0xd); |
07716717 DK |
2171 | break; |
2172 | case 1: | |
2173 | entry->edx &= kvm_supported_word0_x86_features; | |
7faa4ee1 | 2174 | entry->ecx &= kvm_supported_word4_x86_features; |
0d1de2d9 GN |
2175 | /* we support x2apic emulation even if host does not support |
2176 | * it since we emulate x2apic in software */ | |
2177 | entry->ecx |= F(X2APIC); | |
07716717 DK |
2178 | break; |
2179 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
2180 | * may return different values. This forces us to get_cpu() before | |
2181 | * issuing the first command, and also to emulate this annoying behavior | |
2182 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
2183 | case 2: { | |
2184 | int t, times = entry->eax & 0xff; | |
2185 | ||
2186 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 2187 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
2188 | for (t = 1; t < times && *nent < maxnent; ++t) { |
2189 | do_cpuid_1_ent(&entry[t], function, 0); | |
2190 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
2191 | ++*nent; | |
2192 | } | |
2193 | break; | |
2194 | } | |
2195 | /* function 4 and 0xb have additional index. */ | |
2196 | case 4: { | |
14af3f3c | 2197 | int i, cache_type; |
07716717 DK |
2198 | |
2199 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2200 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
2201 | for (i = 1; *nent < maxnent; ++i) { |
2202 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
2203 | if (!cache_type) |
2204 | break; | |
14af3f3c HH |
2205 | do_cpuid_1_ent(&entry[i], function, i); |
2206 | entry[i].flags |= | |
07716717 DK |
2207 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2208 | ++*nent; | |
2209 | } | |
2210 | break; | |
2211 | } | |
2212 | case 0xb: { | |
14af3f3c | 2213 | int i, level_type; |
07716717 DK |
2214 | |
2215 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2216 | /* read more entries until level_type is zero */ | |
14af3f3c | 2217 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 2218 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
2219 | if (!level_type) |
2220 | break; | |
14af3f3c HH |
2221 | do_cpuid_1_ent(&entry[i], function, i); |
2222 | entry[i].flags |= | |
07716717 DK |
2223 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
2224 | ++*nent; | |
2225 | } | |
2226 | break; | |
2227 | } | |
2acf923e DC |
2228 | case 0xd: { |
2229 | int i; | |
2230 | ||
2231 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2232 | for (i = 1; *nent < maxnent; ++i) { | |
2233 | if (entry[i - 1].eax == 0 && i != 2) | |
2234 | break; | |
2235 | do_cpuid_1_ent(&entry[i], function, i); | |
2236 | entry[i].flags |= | |
2237 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
2238 | ++*nent; | |
2239 | } | |
2240 | break; | |
2241 | } | |
84478c82 GC |
2242 | case KVM_CPUID_SIGNATURE: { |
2243 | char signature[12] = "KVMKVMKVM\0\0"; | |
2244 | u32 *sigptr = (u32 *)signature; | |
2245 | entry->eax = 0; | |
2246 | entry->ebx = sigptr[0]; | |
2247 | entry->ecx = sigptr[1]; | |
2248 | entry->edx = sigptr[2]; | |
2249 | break; | |
2250 | } | |
2251 | case KVM_CPUID_FEATURES: | |
2252 | entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
2253 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
371bcf64 GC |
2254 | (1 << KVM_FEATURE_CLOCKSOURCE2) | |
2255 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); | |
84478c82 GC |
2256 | entry->ebx = 0; |
2257 | entry->ecx = 0; | |
2258 | entry->edx = 0; | |
2259 | break; | |
07716717 DK |
2260 | case 0x80000000: |
2261 | entry->eax = min(entry->eax, 0x8000001a); | |
2262 | break; | |
2263 | case 0x80000001: | |
2264 | entry->edx &= kvm_supported_word1_x86_features; | |
2265 | entry->ecx &= kvm_supported_word6_x86_features; | |
2266 | break; | |
2267 | } | |
d4330ef2 JR |
2268 | |
2269 | kvm_x86_ops->set_supported_cpuid(function, entry); | |
2270 | ||
07716717 DK |
2271 | put_cpu(); |
2272 | } | |
2273 | ||
7faa4ee1 AK |
2274 | #undef F |
2275 | ||
674eea0f | 2276 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 2277 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
2278 | { |
2279 | struct kvm_cpuid_entry2 *cpuid_entries; | |
2280 | int limit, nent = 0, r = -E2BIG; | |
2281 | u32 func; | |
2282 | ||
2283 | if (cpuid->nent < 1) | |
2284 | goto out; | |
6a544355 AK |
2285 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
2286 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
2287 | r = -ENOMEM; |
2288 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
2289 | if (!cpuid_entries) | |
2290 | goto out; | |
2291 | ||
2292 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
2293 | limit = cpuid_entries[0].eax; | |
2294 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
2295 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2296 | &nent, cpuid->nent); |
07716717 DK |
2297 | r = -E2BIG; |
2298 | if (nent >= cpuid->nent) | |
2299 | goto out_free; | |
2300 | ||
2301 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
2302 | limit = cpuid_entries[nent - 1].eax; | |
2303 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
2304 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 2305 | &nent, cpuid->nent); |
84478c82 GC |
2306 | |
2307 | ||
2308 | ||
2309 | r = -E2BIG; | |
2310 | if (nent >= cpuid->nent) | |
2311 | goto out_free; | |
2312 | ||
2313 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent, | |
2314 | cpuid->nent); | |
2315 | ||
2316 | r = -E2BIG; | |
2317 | if (nent >= cpuid->nent) | |
2318 | goto out_free; | |
2319 | ||
2320 | do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent, | |
2321 | cpuid->nent); | |
2322 | ||
cb007648 MM |
2323 | r = -E2BIG; |
2324 | if (nent >= cpuid->nent) | |
2325 | goto out_free; | |
2326 | ||
07716717 DK |
2327 | r = -EFAULT; |
2328 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 2329 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
2330 | goto out_free; |
2331 | cpuid->nent = nent; | |
2332 | r = 0; | |
2333 | ||
2334 | out_free: | |
2335 | vfree(cpuid_entries); | |
2336 | out: | |
2337 | return r; | |
2338 | } | |
2339 | ||
313a3dc7 CO |
2340 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
2341 | struct kvm_lapic_state *s) | |
2342 | { | |
ad312c7c | 2343 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
2344 | |
2345 | return 0; | |
2346 | } | |
2347 | ||
2348 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2349 | struct kvm_lapic_state *s) | |
2350 | { | |
ad312c7c | 2351 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 2352 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 2353 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
2354 | |
2355 | return 0; | |
2356 | } | |
2357 | ||
f77bc6a4 ZX |
2358 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
2359 | struct kvm_interrupt *irq) | |
2360 | { | |
2361 | if (irq->irq < 0 || irq->irq >= 256) | |
2362 | return -EINVAL; | |
2363 | if (irqchip_in_kernel(vcpu->kvm)) | |
2364 | return -ENXIO; | |
f77bc6a4 | 2365 | |
66fd3f7f | 2366 | kvm_queue_interrupt(vcpu, irq->irq, false); |
f77bc6a4 | 2367 | |
f77bc6a4 ZX |
2368 | return 0; |
2369 | } | |
2370 | ||
c4abb7c9 JK |
2371 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
2372 | { | |
c4abb7c9 | 2373 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
2374 | |
2375 | return 0; | |
2376 | } | |
2377 | ||
b209749f AK |
2378 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
2379 | struct kvm_tpr_access_ctl *tac) | |
2380 | { | |
2381 | if (tac->flags) | |
2382 | return -EINVAL; | |
2383 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2384 | return 0; | |
2385 | } | |
2386 | ||
890ca9ae HY |
2387 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
2388 | u64 mcg_cap) | |
2389 | { | |
2390 | int r; | |
2391 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2392 | ||
2393 | r = -EINVAL; | |
a9e38c3e | 2394 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2395 | goto out; |
2396 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2397 | goto out; | |
2398 | r = 0; | |
2399 | vcpu->arch.mcg_cap = mcg_cap; | |
2400 | /* Init IA32_MCG_CTL to all 1s */ | |
2401 | if (mcg_cap & MCG_CTL_P) | |
2402 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2403 | /* Init IA32_MCi_CTL to all 1s */ | |
2404 | for (bank = 0; bank < bank_num; bank++) | |
2405 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2406 | out: | |
2407 | return r; | |
2408 | } | |
2409 | ||
2410 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2411 | struct kvm_x86_mce *mce) | |
2412 | { | |
2413 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2414 | unsigned bank_num = mcg_cap & 0xff; | |
2415 | u64 *banks = vcpu->arch.mce_banks; | |
2416 | ||
2417 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2418 | return -EINVAL; | |
2419 | /* | |
2420 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2421 | * reporting is disabled | |
2422 | */ | |
2423 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2424 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2425 | return 0; | |
2426 | banks += 4 * mce->bank; | |
2427 | /* | |
2428 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2429 | * reporting is disabled for the bank | |
2430 | */ | |
2431 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2432 | return 0; | |
2433 | if (mce->status & MCI_STATUS_UC) { | |
2434 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2435 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
890ca9ae HY |
2436 | printk(KERN_DEBUG "kvm: set_mce: " |
2437 | "injects mce exception while " | |
2438 | "previous one is in progress!\n"); | |
a8eeb04a | 2439 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
2440 | return 0; |
2441 | } | |
2442 | if (banks[1] & MCI_STATUS_VAL) | |
2443 | mce->status |= MCI_STATUS_OVER; | |
2444 | banks[2] = mce->addr; | |
2445 | banks[3] = mce->misc; | |
2446 | vcpu->arch.mcg_status = mce->mcg_status; | |
2447 | banks[1] = mce->status; | |
2448 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2449 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2450 | || !(banks[1] & MCI_STATUS_UC)) { | |
2451 | if (banks[1] & MCI_STATUS_VAL) | |
2452 | mce->status |= MCI_STATUS_OVER; | |
2453 | banks[2] = mce->addr; | |
2454 | banks[3] = mce->misc; | |
2455 | banks[1] = mce->status; | |
2456 | } else | |
2457 | banks[1] |= MCI_STATUS_OVER; | |
2458 | return 0; | |
2459 | } | |
2460 | ||
3cfc3092 JK |
2461 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2462 | struct kvm_vcpu_events *events) | |
2463 | { | |
03b82a30 JK |
2464 | events->exception.injected = |
2465 | vcpu->arch.exception.pending && | |
2466 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2467 | events->exception.nr = vcpu->arch.exception.nr; |
2468 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
2469 | events->exception.error_code = vcpu->arch.exception.error_code; | |
2470 | ||
03b82a30 JK |
2471 | events->interrupt.injected = |
2472 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2473 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2474 | events->interrupt.soft = 0; |
48005f64 JK |
2475 | events->interrupt.shadow = |
2476 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2477 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2478 | |
2479 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2480 | events->nmi.pending = vcpu->arch.nmi_pending; | |
2481 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
2482 | ||
2483 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2484 | ||
dab4b911 | 2485 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2486 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2487 | | KVM_VCPUEVENT_VALID_SHADOW); | |
3cfc3092 JK |
2488 | } |
2489 | ||
2490 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2491 | struct kvm_vcpu_events *events) | |
2492 | { | |
dab4b911 | 2493 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2494 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2495 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2496 | return -EINVAL; |
2497 | ||
3cfc3092 JK |
2498 | vcpu->arch.exception.pending = events->exception.injected; |
2499 | vcpu->arch.exception.nr = events->exception.nr; | |
2500 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2501 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2502 | ||
2503 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2504 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2505 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
2506 | if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm)) | |
2507 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
48005f64 JK |
2508 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2509 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2510 | events->interrupt.shadow); | |
3cfc3092 JK |
2511 | |
2512 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2513 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2514 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2515 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2516 | ||
dab4b911 JK |
2517 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2518 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 | 2519 | |
3cfc3092 JK |
2520 | return 0; |
2521 | } | |
2522 | ||
a1efbe77 JK |
2523 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2524 | struct kvm_debugregs *dbgregs) | |
2525 | { | |
a1efbe77 JK |
2526 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
2527 | dbgregs->dr6 = vcpu->arch.dr6; | |
2528 | dbgregs->dr7 = vcpu->arch.dr7; | |
2529 | dbgregs->flags = 0; | |
a1efbe77 JK |
2530 | } |
2531 | ||
2532 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2533 | struct kvm_debugregs *dbgregs) | |
2534 | { | |
2535 | if (dbgregs->flags) | |
2536 | return -EINVAL; | |
2537 | ||
a1efbe77 JK |
2538 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
2539 | vcpu->arch.dr6 = dbgregs->dr6; | |
2540 | vcpu->arch.dr7 = dbgregs->dr7; | |
2541 | ||
a1efbe77 JK |
2542 | return 0; |
2543 | } | |
2544 | ||
2d5b5a66 SY |
2545 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
2546 | struct kvm_xsave *guest_xsave) | |
2547 | { | |
2548 | if (cpu_has_xsave) | |
2549 | memcpy(guest_xsave->region, | |
2550 | &vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2551 | xstate_size); |
2d5b5a66 SY |
2552 | else { |
2553 | memcpy(guest_xsave->region, | |
2554 | &vcpu->arch.guest_fpu.state->fxsave, | |
2555 | sizeof(struct i387_fxsave_struct)); | |
2556 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
2557 | XSTATE_FPSSE; | |
2558 | } | |
2559 | } | |
2560 | ||
2561 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
2562 | struct kvm_xsave *guest_xsave) | |
2563 | { | |
2564 | u64 xstate_bv = | |
2565 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
2566 | ||
2567 | if (cpu_has_xsave) | |
2568 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
f45755b8 | 2569 | guest_xsave->region, xstate_size); |
2d5b5a66 SY |
2570 | else { |
2571 | if (xstate_bv & ~XSTATE_FPSSE) | |
2572 | return -EINVAL; | |
2573 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
2574 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
2575 | } | |
2576 | return 0; | |
2577 | } | |
2578 | ||
2579 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
2580 | struct kvm_xcrs *guest_xcrs) | |
2581 | { | |
2582 | if (!cpu_has_xsave) { | |
2583 | guest_xcrs->nr_xcrs = 0; | |
2584 | return; | |
2585 | } | |
2586 | ||
2587 | guest_xcrs->nr_xcrs = 1; | |
2588 | guest_xcrs->flags = 0; | |
2589 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
2590 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
2591 | } | |
2592 | ||
2593 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
2594 | struct kvm_xcrs *guest_xcrs) | |
2595 | { | |
2596 | int i, r = 0; | |
2597 | ||
2598 | if (!cpu_has_xsave) | |
2599 | return -EINVAL; | |
2600 | ||
2601 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
2602 | return -EINVAL; | |
2603 | ||
2604 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
2605 | /* Only support XCR0 currently */ | |
2606 | if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
2607 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
2608 | guest_xcrs->xcrs[0].value); | |
2609 | break; | |
2610 | } | |
2611 | if (r) | |
2612 | r = -EINVAL; | |
2613 | return r; | |
2614 | } | |
2615 | ||
313a3dc7 CO |
2616 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2617 | unsigned int ioctl, unsigned long arg) | |
2618 | { | |
2619 | struct kvm_vcpu *vcpu = filp->private_data; | |
2620 | void __user *argp = (void __user *)arg; | |
2621 | int r; | |
d1ac91d8 AK |
2622 | union { |
2623 | struct kvm_lapic_state *lapic; | |
2624 | struct kvm_xsave *xsave; | |
2625 | struct kvm_xcrs *xcrs; | |
2626 | void *buffer; | |
2627 | } u; | |
2628 | ||
2629 | u.buffer = NULL; | |
313a3dc7 CO |
2630 | switch (ioctl) { |
2631 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2632 | r = -EINVAL; |
2633 | if (!vcpu->arch.apic) | |
2634 | goto out; | |
d1ac91d8 | 2635 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2636 | |
b772ff36 | 2637 | r = -ENOMEM; |
d1ac91d8 | 2638 | if (!u.lapic) |
b772ff36 | 2639 | goto out; |
d1ac91d8 | 2640 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2641 | if (r) |
2642 | goto out; | |
2643 | r = -EFAULT; | |
d1ac91d8 | 2644 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2645 | goto out; |
2646 | r = 0; | |
2647 | break; | |
2648 | } | |
2649 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2650 | r = -EINVAL; |
2651 | if (!vcpu->arch.apic) | |
2652 | goto out; | |
d1ac91d8 | 2653 | u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
b772ff36 | 2654 | r = -ENOMEM; |
d1ac91d8 | 2655 | if (!u.lapic) |
b772ff36 | 2656 | goto out; |
313a3dc7 | 2657 | r = -EFAULT; |
d1ac91d8 | 2658 | if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 2659 | goto out; |
d1ac91d8 | 2660 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
2661 | if (r) |
2662 | goto out; | |
2663 | r = 0; | |
2664 | break; | |
2665 | } | |
f77bc6a4 ZX |
2666 | case KVM_INTERRUPT: { |
2667 | struct kvm_interrupt irq; | |
2668 | ||
2669 | r = -EFAULT; | |
2670 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2671 | goto out; | |
2672 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2673 | if (r) | |
2674 | goto out; | |
2675 | r = 0; | |
2676 | break; | |
2677 | } | |
c4abb7c9 JK |
2678 | case KVM_NMI: { |
2679 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2680 | if (r) | |
2681 | goto out; | |
2682 | r = 0; | |
2683 | break; | |
2684 | } | |
313a3dc7 CO |
2685 | case KVM_SET_CPUID: { |
2686 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2687 | struct kvm_cpuid cpuid; | |
2688 | ||
2689 | r = -EFAULT; | |
2690 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2691 | goto out; | |
2692 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2693 | if (r) | |
2694 | goto out; | |
2695 | break; | |
2696 | } | |
07716717 DK |
2697 | case KVM_SET_CPUID2: { |
2698 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2699 | struct kvm_cpuid2 cpuid; | |
2700 | ||
2701 | r = -EFAULT; | |
2702 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2703 | goto out; | |
2704 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2705 | cpuid_arg->entries); |
07716717 DK |
2706 | if (r) |
2707 | goto out; | |
2708 | break; | |
2709 | } | |
2710 | case KVM_GET_CPUID2: { | |
2711 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2712 | struct kvm_cpuid2 cpuid; | |
2713 | ||
2714 | r = -EFAULT; | |
2715 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2716 | goto out; | |
2717 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2718 | cpuid_arg->entries); |
07716717 DK |
2719 | if (r) |
2720 | goto out; | |
2721 | r = -EFAULT; | |
2722 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2723 | goto out; | |
2724 | r = 0; | |
2725 | break; | |
2726 | } | |
313a3dc7 CO |
2727 | case KVM_GET_MSRS: |
2728 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2729 | break; | |
2730 | case KVM_SET_MSRS: | |
2731 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2732 | break; | |
b209749f AK |
2733 | case KVM_TPR_ACCESS_REPORTING: { |
2734 | struct kvm_tpr_access_ctl tac; | |
2735 | ||
2736 | r = -EFAULT; | |
2737 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2738 | goto out; | |
2739 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2740 | if (r) | |
2741 | goto out; | |
2742 | r = -EFAULT; | |
2743 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2744 | goto out; | |
2745 | r = 0; | |
2746 | break; | |
2747 | }; | |
b93463aa AK |
2748 | case KVM_SET_VAPIC_ADDR: { |
2749 | struct kvm_vapic_addr va; | |
2750 | ||
2751 | r = -EINVAL; | |
2752 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2753 | goto out; | |
2754 | r = -EFAULT; | |
2755 | if (copy_from_user(&va, argp, sizeof va)) | |
2756 | goto out; | |
2757 | r = 0; | |
2758 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2759 | break; | |
2760 | } | |
890ca9ae HY |
2761 | case KVM_X86_SETUP_MCE: { |
2762 | u64 mcg_cap; | |
2763 | ||
2764 | r = -EFAULT; | |
2765 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2766 | goto out; | |
2767 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2768 | break; | |
2769 | } | |
2770 | case KVM_X86_SET_MCE: { | |
2771 | struct kvm_x86_mce mce; | |
2772 | ||
2773 | r = -EFAULT; | |
2774 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2775 | goto out; | |
2776 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2777 | break; | |
2778 | } | |
3cfc3092 JK |
2779 | case KVM_GET_VCPU_EVENTS: { |
2780 | struct kvm_vcpu_events events; | |
2781 | ||
2782 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2783 | ||
2784 | r = -EFAULT; | |
2785 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2786 | break; | |
2787 | r = 0; | |
2788 | break; | |
2789 | } | |
2790 | case KVM_SET_VCPU_EVENTS: { | |
2791 | struct kvm_vcpu_events events; | |
2792 | ||
2793 | r = -EFAULT; | |
2794 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2795 | break; | |
2796 | ||
2797 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2798 | break; | |
2799 | } | |
a1efbe77 JK |
2800 | case KVM_GET_DEBUGREGS: { |
2801 | struct kvm_debugregs dbgregs; | |
2802 | ||
2803 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2804 | ||
2805 | r = -EFAULT; | |
2806 | if (copy_to_user(argp, &dbgregs, | |
2807 | sizeof(struct kvm_debugregs))) | |
2808 | break; | |
2809 | r = 0; | |
2810 | break; | |
2811 | } | |
2812 | case KVM_SET_DEBUGREGS: { | |
2813 | struct kvm_debugregs dbgregs; | |
2814 | ||
2815 | r = -EFAULT; | |
2816 | if (copy_from_user(&dbgregs, argp, | |
2817 | sizeof(struct kvm_debugregs))) | |
2818 | break; | |
2819 | ||
2820 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2821 | break; | |
2822 | } | |
2d5b5a66 | 2823 | case KVM_GET_XSAVE: { |
d1ac91d8 | 2824 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2825 | r = -ENOMEM; |
d1ac91d8 | 2826 | if (!u.xsave) |
2d5b5a66 SY |
2827 | break; |
2828 | ||
d1ac91d8 | 2829 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2830 | |
2831 | r = -EFAULT; | |
d1ac91d8 | 2832 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2833 | break; |
2834 | r = 0; | |
2835 | break; | |
2836 | } | |
2837 | case KVM_SET_XSAVE: { | |
d1ac91d8 | 2838 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 2839 | r = -ENOMEM; |
d1ac91d8 | 2840 | if (!u.xsave) |
2d5b5a66 SY |
2841 | break; |
2842 | ||
2843 | r = -EFAULT; | |
d1ac91d8 | 2844 | if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
2845 | break; |
2846 | ||
d1ac91d8 | 2847 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
2848 | break; |
2849 | } | |
2850 | case KVM_GET_XCRS: { | |
d1ac91d8 | 2851 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 2852 | r = -ENOMEM; |
d1ac91d8 | 2853 | if (!u.xcrs) |
2d5b5a66 SY |
2854 | break; |
2855 | ||
d1ac91d8 | 2856 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2857 | |
2858 | r = -EFAULT; | |
d1ac91d8 | 2859 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
2860 | sizeof(struct kvm_xcrs))) |
2861 | break; | |
2862 | r = 0; | |
2863 | break; | |
2864 | } | |
2865 | case KVM_SET_XCRS: { | |
d1ac91d8 | 2866 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 2867 | r = -ENOMEM; |
d1ac91d8 | 2868 | if (!u.xcrs) |
2d5b5a66 SY |
2869 | break; |
2870 | ||
2871 | r = -EFAULT; | |
d1ac91d8 | 2872 | if (copy_from_user(u.xcrs, argp, |
2d5b5a66 SY |
2873 | sizeof(struct kvm_xcrs))) |
2874 | break; | |
2875 | ||
d1ac91d8 | 2876 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
2877 | break; |
2878 | } | |
313a3dc7 CO |
2879 | default: |
2880 | r = -EINVAL; | |
2881 | } | |
2882 | out: | |
d1ac91d8 | 2883 | kfree(u.buffer); |
313a3dc7 CO |
2884 | return r; |
2885 | } | |
2886 | ||
1fe779f8 CO |
2887 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
2888 | { | |
2889 | int ret; | |
2890 | ||
2891 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
2892 | return -1; | |
2893 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
2894 | return ret; | |
2895 | } | |
2896 | ||
b927a3ce SY |
2897 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
2898 | u64 ident_addr) | |
2899 | { | |
2900 | kvm->arch.ept_identity_map_addr = ident_addr; | |
2901 | return 0; | |
2902 | } | |
2903 | ||
1fe779f8 CO |
2904 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
2905 | u32 kvm_nr_mmu_pages) | |
2906 | { | |
2907 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
2908 | return -EINVAL; | |
2909 | ||
79fac95e | 2910 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 2911 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
2912 | |
2913 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 2914 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 2915 | |
7c8a83b7 | 2916 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 2917 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2918 | return 0; |
2919 | } | |
2920 | ||
2921 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
2922 | { | |
39de71ec | 2923 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
2924 | } |
2925 | ||
1fe779f8 CO |
2926 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
2927 | { | |
2928 | int r; | |
2929 | ||
2930 | r = 0; | |
2931 | switch (chip->chip_id) { | |
2932 | case KVM_IRQCHIP_PIC_MASTER: | |
2933 | memcpy(&chip->chip.pic, | |
2934 | &pic_irqchip(kvm)->pics[0], | |
2935 | sizeof(struct kvm_pic_state)); | |
2936 | break; | |
2937 | case KVM_IRQCHIP_PIC_SLAVE: | |
2938 | memcpy(&chip->chip.pic, | |
2939 | &pic_irqchip(kvm)->pics[1], | |
2940 | sizeof(struct kvm_pic_state)); | |
2941 | break; | |
2942 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2943 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2944 | break; |
2945 | default: | |
2946 | r = -EINVAL; | |
2947 | break; | |
2948 | } | |
2949 | return r; | |
2950 | } | |
2951 | ||
2952 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2953 | { | |
2954 | int r; | |
2955 | ||
2956 | r = 0; | |
2957 | switch (chip->chip_id) { | |
2958 | case KVM_IRQCHIP_PIC_MASTER: | |
fa8273e9 | 2959 | raw_spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2960 | memcpy(&pic_irqchip(kvm)->pics[0], |
2961 | &chip->chip.pic, | |
2962 | sizeof(struct kvm_pic_state)); | |
fa8273e9 | 2963 | raw_spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2964 | break; |
2965 | case KVM_IRQCHIP_PIC_SLAVE: | |
fa8273e9 | 2966 | raw_spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2967 | memcpy(&pic_irqchip(kvm)->pics[1], |
2968 | &chip->chip.pic, | |
2969 | sizeof(struct kvm_pic_state)); | |
fa8273e9 | 2970 | raw_spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2971 | break; |
2972 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2973 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2974 | break; |
2975 | default: | |
2976 | r = -EINVAL; | |
2977 | break; | |
2978 | } | |
2979 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
2980 | return r; | |
2981 | } | |
2982 | ||
e0f63cb9 SY |
2983 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
2984 | { | |
2985 | int r = 0; | |
2986 | ||
894a9c55 | 2987 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2988 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 2989 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2990 | return r; |
2991 | } | |
2992 | ||
2993 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
2994 | { | |
2995 | int r = 0; | |
2996 | ||
894a9c55 | 2997 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2998 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
2999 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3000 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3001 | return r; | |
3002 | } | |
3003 | ||
3004 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3005 | { | |
3006 | int r = 0; | |
3007 | ||
3008 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3009 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3010 | sizeof(ps->channels)); | |
3011 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3012 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3013 | return r; | |
3014 | } | |
3015 | ||
3016 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3017 | { | |
3018 | int r = 0, start = 0; | |
3019 | u32 prev_legacy, cur_legacy; | |
3020 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3021 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3022 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3023 | if (!prev_legacy && cur_legacy) | |
3024 | start = 1; | |
3025 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3026 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3027 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3028 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3029 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3030 | return r; |
3031 | } | |
3032 | ||
52d939a0 MT |
3033 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3034 | struct kvm_reinject_control *control) | |
3035 | { | |
3036 | if (!kvm->arch.vpit) | |
3037 | return -ENXIO; | |
894a9c55 | 3038 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 3039 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 3040 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3041 | return 0; |
3042 | } | |
3043 | ||
5bb064dc ZX |
3044 | /* |
3045 | * Get (and clear) the dirty memory log for a memory slot. | |
3046 | */ | |
3047 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
3048 | struct kvm_dirty_log *log) | |
3049 | { | |
87bf6e7d | 3050 | int r, i; |
5bb064dc | 3051 | struct kvm_memory_slot *memslot; |
87bf6e7d | 3052 | unsigned long n; |
b050b015 | 3053 | unsigned long is_dirty = 0; |
5bb064dc | 3054 | |
79fac95e | 3055 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3056 | |
b050b015 MT |
3057 | r = -EINVAL; |
3058 | if (log->slot >= KVM_MEMORY_SLOTS) | |
3059 | goto out; | |
3060 | ||
3061 | memslot = &kvm->memslots->memslots[log->slot]; | |
3062 | r = -ENOENT; | |
3063 | if (!memslot->dirty_bitmap) | |
3064 | goto out; | |
3065 | ||
87bf6e7d | 3066 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 | 3067 | |
b050b015 MT |
3068 | for (i = 0; !is_dirty && i < n/sizeof(long); i++) |
3069 | is_dirty = memslot->dirty_bitmap[i]; | |
5bb064dc ZX |
3070 | |
3071 | /* If nothing is dirty, don't bother messing with page tables. */ | |
3072 | if (is_dirty) { | |
b050b015 | 3073 | struct kvm_memslots *slots, *old_slots; |
914ebccd | 3074 | unsigned long *dirty_bitmap; |
b050b015 | 3075 | |
7c8a83b7 | 3076 | spin_lock(&kvm->mmu_lock); |
5bb064dc | 3077 | kvm_mmu_slot_remove_write_access(kvm, log->slot); |
7c8a83b7 | 3078 | spin_unlock(&kvm->mmu_lock); |
b050b015 | 3079 | |
914ebccd TY |
3080 | r = -ENOMEM; |
3081 | dirty_bitmap = vmalloc(n); | |
3082 | if (!dirty_bitmap) | |
3083 | goto out; | |
3084 | memset(dirty_bitmap, 0, n); | |
b050b015 | 3085 | |
914ebccd TY |
3086 | r = -ENOMEM; |
3087 | slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL); | |
3088 | if (!slots) { | |
3089 | vfree(dirty_bitmap); | |
3090 | goto out; | |
3091 | } | |
b050b015 MT |
3092 | memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots)); |
3093 | slots->memslots[log->slot].dirty_bitmap = dirty_bitmap; | |
3094 | ||
3095 | old_slots = kvm->memslots; | |
3096 | rcu_assign_pointer(kvm->memslots, slots); | |
3097 | synchronize_srcu_expedited(&kvm->srcu); | |
3098 | dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap; | |
3099 | kfree(old_slots); | |
914ebccd TY |
3100 | |
3101 | r = -EFAULT; | |
3102 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) { | |
3103 | vfree(dirty_bitmap); | |
3104 | goto out; | |
3105 | } | |
3106 | vfree(dirty_bitmap); | |
3107 | } else { | |
3108 | r = -EFAULT; | |
3109 | if (clear_user(log->dirty_bitmap, n)) | |
3110 | goto out; | |
5bb064dc | 3111 | } |
b050b015 | 3112 | |
5bb064dc ZX |
3113 | r = 0; |
3114 | out: | |
79fac95e | 3115 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3116 | return r; |
3117 | } | |
3118 | ||
1fe779f8 CO |
3119 | long kvm_arch_vm_ioctl(struct file *filp, |
3120 | unsigned int ioctl, unsigned long arg) | |
3121 | { | |
3122 | struct kvm *kvm = filp->private_data; | |
3123 | void __user *argp = (void __user *)arg; | |
367e1319 | 3124 | int r = -ENOTTY; |
f0d66275 DH |
3125 | /* |
3126 | * This union makes it completely explicit to gcc-3.x | |
3127 | * that these two variables' stack usage should be | |
3128 | * combined, not added together. | |
3129 | */ | |
3130 | union { | |
3131 | struct kvm_pit_state ps; | |
e9f42757 | 3132 | struct kvm_pit_state2 ps2; |
c5ff41ce | 3133 | struct kvm_pit_config pit_config; |
f0d66275 | 3134 | } u; |
1fe779f8 CO |
3135 | |
3136 | switch (ioctl) { | |
3137 | case KVM_SET_TSS_ADDR: | |
3138 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
3139 | if (r < 0) | |
3140 | goto out; | |
3141 | break; | |
b927a3ce SY |
3142 | case KVM_SET_IDENTITY_MAP_ADDR: { |
3143 | u64 ident_addr; | |
3144 | ||
3145 | r = -EFAULT; | |
3146 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3147 | goto out; | |
3148 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
3149 | if (r < 0) | |
3150 | goto out; | |
3151 | break; | |
3152 | } | |
1fe779f8 CO |
3153 | case KVM_SET_NR_MMU_PAGES: |
3154 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
3155 | if (r) | |
3156 | goto out; | |
3157 | break; | |
3158 | case KVM_GET_NR_MMU_PAGES: | |
3159 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3160 | break; | |
3ddea128 MT |
3161 | case KVM_CREATE_IRQCHIP: { |
3162 | struct kvm_pic *vpic; | |
3163 | ||
3164 | mutex_lock(&kvm->lock); | |
3165 | r = -EEXIST; | |
3166 | if (kvm->arch.vpic) | |
3167 | goto create_irqchip_unlock; | |
1fe779f8 | 3168 | r = -ENOMEM; |
3ddea128 MT |
3169 | vpic = kvm_create_pic(kvm); |
3170 | if (vpic) { | |
1fe779f8 CO |
3171 | r = kvm_ioapic_init(kvm); |
3172 | if (r) { | |
72bb2fcd WY |
3173 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
3174 | &vpic->dev); | |
3ddea128 MT |
3175 | kfree(vpic); |
3176 | goto create_irqchip_unlock; | |
1fe779f8 CO |
3177 | } |
3178 | } else | |
3ddea128 MT |
3179 | goto create_irqchip_unlock; |
3180 | smp_wmb(); | |
3181 | kvm->arch.vpic = vpic; | |
3182 | smp_wmb(); | |
399ec807 AK |
3183 | r = kvm_setup_default_irq_routing(kvm); |
3184 | if (r) { | |
3ddea128 | 3185 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
3186 | kvm_ioapic_destroy(kvm); |
3187 | kvm_destroy_pic(kvm); | |
3ddea128 | 3188 | mutex_unlock(&kvm->irq_lock); |
399ec807 | 3189 | } |
3ddea128 MT |
3190 | create_irqchip_unlock: |
3191 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 3192 | break; |
3ddea128 | 3193 | } |
7837699f | 3194 | case KVM_CREATE_PIT: |
c5ff41ce JK |
3195 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
3196 | goto create_pit; | |
3197 | case KVM_CREATE_PIT2: | |
3198 | r = -EFAULT; | |
3199 | if (copy_from_user(&u.pit_config, argp, | |
3200 | sizeof(struct kvm_pit_config))) | |
3201 | goto out; | |
3202 | create_pit: | |
79fac95e | 3203 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
3204 | r = -EEXIST; |
3205 | if (kvm->arch.vpit) | |
3206 | goto create_pit_unlock; | |
7837699f | 3207 | r = -ENOMEM; |
c5ff41ce | 3208 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
3209 | if (kvm->arch.vpit) |
3210 | r = 0; | |
269e05e4 | 3211 | create_pit_unlock: |
79fac95e | 3212 | mutex_unlock(&kvm->slots_lock); |
7837699f | 3213 | break; |
4925663a | 3214 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
3215 | case KVM_IRQ_LINE: { |
3216 | struct kvm_irq_level irq_event; | |
3217 | ||
3218 | r = -EFAULT; | |
3219 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
3220 | goto out; | |
160d2f6c | 3221 | r = -ENXIO; |
1fe779f8 | 3222 | if (irqchip_in_kernel(kvm)) { |
4925663a | 3223 | __s32 status; |
4925663a GN |
3224 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
3225 | irq_event.irq, irq_event.level); | |
4925663a | 3226 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
160d2f6c | 3227 | r = -EFAULT; |
4925663a GN |
3228 | irq_event.status = status; |
3229 | if (copy_to_user(argp, &irq_event, | |
3230 | sizeof irq_event)) | |
3231 | goto out; | |
3232 | } | |
1fe779f8 CO |
3233 | r = 0; |
3234 | } | |
3235 | break; | |
3236 | } | |
3237 | case KVM_GET_IRQCHIP: { | |
3238 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3239 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3240 | |
f0d66275 DH |
3241 | r = -ENOMEM; |
3242 | if (!chip) | |
1fe779f8 | 3243 | goto out; |
f0d66275 DH |
3244 | r = -EFAULT; |
3245 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3246 | goto get_irqchip_out; | |
1fe779f8 CO |
3247 | r = -ENXIO; |
3248 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3249 | goto get_irqchip_out; |
3250 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 3251 | if (r) |
f0d66275 | 3252 | goto get_irqchip_out; |
1fe779f8 | 3253 | r = -EFAULT; |
f0d66275 DH |
3254 | if (copy_to_user(argp, chip, sizeof *chip)) |
3255 | goto get_irqchip_out; | |
1fe779f8 | 3256 | r = 0; |
f0d66275 DH |
3257 | get_irqchip_out: |
3258 | kfree(chip); | |
3259 | if (r) | |
3260 | goto out; | |
1fe779f8 CO |
3261 | break; |
3262 | } | |
3263 | case KVM_SET_IRQCHIP: { | |
3264 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 3265 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 3266 | |
f0d66275 DH |
3267 | r = -ENOMEM; |
3268 | if (!chip) | |
1fe779f8 | 3269 | goto out; |
f0d66275 DH |
3270 | r = -EFAULT; |
3271 | if (copy_from_user(chip, argp, sizeof *chip)) | |
3272 | goto set_irqchip_out; | |
1fe779f8 CO |
3273 | r = -ENXIO; |
3274 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
3275 | goto set_irqchip_out; |
3276 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 3277 | if (r) |
f0d66275 | 3278 | goto set_irqchip_out; |
1fe779f8 | 3279 | r = 0; |
f0d66275 DH |
3280 | set_irqchip_out: |
3281 | kfree(chip); | |
3282 | if (r) | |
3283 | goto out; | |
1fe779f8 CO |
3284 | break; |
3285 | } | |
e0f63cb9 | 3286 | case KVM_GET_PIT: { |
e0f63cb9 | 3287 | r = -EFAULT; |
f0d66275 | 3288 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3289 | goto out; |
3290 | r = -ENXIO; | |
3291 | if (!kvm->arch.vpit) | |
3292 | goto out; | |
f0d66275 | 3293 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
3294 | if (r) |
3295 | goto out; | |
3296 | r = -EFAULT; | |
f0d66275 | 3297 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
3298 | goto out; |
3299 | r = 0; | |
3300 | break; | |
3301 | } | |
3302 | case KVM_SET_PIT: { | |
e0f63cb9 | 3303 | r = -EFAULT; |
f0d66275 | 3304 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
3305 | goto out; |
3306 | r = -ENXIO; | |
3307 | if (!kvm->arch.vpit) | |
3308 | goto out; | |
f0d66275 | 3309 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
3310 | if (r) |
3311 | goto out; | |
3312 | r = 0; | |
3313 | break; | |
3314 | } | |
e9f42757 BK |
3315 | case KVM_GET_PIT2: { |
3316 | r = -ENXIO; | |
3317 | if (!kvm->arch.vpit) | |
3318 | goto out; | |
3319 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3320 | if (r) | |
3321 | goto out; | |
3322 | r = -EFAULT; | |
3323 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3324 | goto out; | |
3325 | r = 0; | |
3326 | break; | |
3327 | } | |
3328 | case KVM_SET_PIT2: { | |
3329 | r = -EFAULT; | |
3330 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3331 | goto out; | |
3332 | r = -ENXIO; | |
3333 | if (!kvm->arch.vpit) | |
3334 | goto out; | |
3335 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3336 | if (r) | |
3337 | goto out; | |
3338 | r = 0; | |
3339 | break; | |
3340 | } | |
52d939a0 MT |
3341 | case KVM_REINJECT_CONTROL: { |
3342 | struct kvm_reinject_control control; | |
3343 | r = -EFAULT; | |
3344 | if (copy_from_user(&control, argp, sizeof(control))) | |
3345 | goto out; | |
3346 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3347 | if (r) | |
3348 | goto out; | |
3349 | r = 0; | |
3350 | break; | |
3351 | } | |
ffde22ac ES |
3352 | case KVM_XEN_HVM_CONFIG: { |
3353 | r = -EFAULT; | |
3354 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3355 | sizeof(struct kvm_xen_hvm_config))) | |
3356 | goto out; | |
3357 | r = -EINVAL; | |
3358 | if (kvm->arch.xen_hvm_config.flags) | |
3359 | goto out; | |
3360 | r = 0; | |
3361 | break; | |
3362 | } | |
afbcf7ab | 3363 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
3364 | struct kvm_clock_data user_ns; |
3365 | u64 now_ns; | |
3366 | s64 delta; | |
3367 | ||
3368 | r = -EFAULT; | |
3369 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3370 | goto out; | |
3371 | ||
3372 | r = -EINVAL; | |
3373 | if (user_ns.flags) | |
3374 | goto out; | |
3375 | ||
3376 | r = 0; | |
759379dd | 3377 | now_ns = get_kernel_ns(); |
afbcf7ab GC |
3378 | delta = user_ns.clock - now_ns; |
3379 | kvm->arch.kvmclock_offset = delta; | |
3380 | break; | |
3381 | } | |
3382 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
3383 | struct kvm_clock_data user_ns; |
3384 | u64 now_ns; | |
3385 | ||
759379dd | 3386 | now_ns = get_kernel_ns(); |
afbcf7ab GC |
3387 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
3388 | user_ns.flags = 0; | |
3389 | ||
3390 | r = -EFAULT; | |
3391 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3392 | goto out; | |
3393 | r = 0; | |
3394 | break; | |
3395 | } | |
3396 | ||
1fe779f8 CO |
3397 | default: |
3398 | ; | |
3399 | } | |
3400 | out: | |
3401 | return r; | |
3402 | } | |
3403 | ||
a16b043c | 3404 | static void kvm_init_msr_list(void) |
043405e1 CO |
3405 | { |
3406 | u32 dummy[2]; | |
3407 | unsigned i, j; | |
3408 | ||
e3267cbb GC |
3409 | /* skip the first msrs in the list. KVM-specific */ |
3410 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3411 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3412 | continue; | |
3413 | if (j < i) | |
3414 | msrs_to_save[j] = msrs_to_save[i]; | |
3415 | j++; | |
3416 | } | |
3417 | num_msrs_to_save = j; | |
3418 | } | |
3419 | ||
bda9020e MT |
3420 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3421 | const void *v) | |
bbd9b64e | 3422 | { |
bda9020e MT |
3423 | if (vcpu->arch.apic && |
3424 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v)) | |
3425 | return 0; | |
bbd9b64e | 3426 | |
e93f8a0f | 3427 | return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3428 | } |
3429 | ||
bda9020e | 3430 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3431 | { |
bda9020e MT |
3432 | if (vcpu->arch.apic && |
3433 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v)) | |
3434 | return 0; | |
bbd9b64e | 3435 | |
e93f8a0f | 3436 | return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3437 | } |
3438 | ||
2dafc6c2 GN |
3439 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
3440 | struct kvm_segment *var, int seg) | |
3441 | { | |
3442 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3443 | } | |
3444 | ||
3445 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3446 | struct kvm_segment *var, int seg) | |
3447 | { | |
3448 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3449 | } | |
3450 | ||
c30a358d JR |
3451 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
3452 | { | |
3453 | return gpa; | |
3454 | } | |
3455 | ||
1871c602 GN |
3456 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) |
3457 | { | |
3458 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
14dfe855 | 3459 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error); |
1871c602 GN |
3460 | } |
3461 | ||
3462 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3463 | { | |
3464 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3465 | access |= PFERR_FETCH_MASK; | |
14dfe855 | 3466 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error); |
1871c602 GN |
3467 | } |
3468 | ||
3469 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3470 | { | |
3471 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3472 | access |= PFERR_WRITE_MASK; | |
14dfe855 | 3473 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error); |
1871c602 GN |
3474 | } |
3475 | ||
3476 | /* uses this to access any guest's mapped memory without checking CPL */ | |
3477 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3478 | { | |
14dfe855 | 3479 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error); |
1871c602 GN |
3480 | } |
3481 | ||
3482 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3483 | struct kvm_vcpu *vcpu, u32 access, | |
3484 | u32 *error) | |
bbd9b64e CO |
3485 | { |
3486 | void *data = val; | |
10589a46 | 3487 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3488 | |
3489 | while (bytes) { | |
14dfe855 JR |
3490 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
3491 | error); | |
bbd9b64e | 3492 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3493 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3494 | int ret; |
3495 | ||
10589a46 MT |
3496 | if (gpa == UNMAPPED_GVA) { |
3497 | r = X86EMUL_PROPAGATE_FAULT; | |
3498 | goto out; | |
3499 | } | |
77c2002e | 3500 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 | 3501 | if (ret < 0) { |
c3cd7ffa | 3502 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
3503 | goto out; |
3504 | } | |
bbd9b64e | 3505 | |
77c2002e IE |
3506 | bytes -= toread; |
3507 | data += toread; | |
3508 | addr += toread; | |
bbd9b64e | 3509 | } |
10589a46 | 3510 | out: |
10589a46 | 3511 | return r; |
bbd9b64e | 3512 | } |
77c2002e | 3513 | |
1871c602 GN |
3514 | /* used for instruction fetching */ |
3515 | static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3516 | struct kvm_vcpu *vcpu, u32 *error) | |
3517 | { | |
3518 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3519 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, | |
3520 | access | PFERR_FETCH_MASK, error); | |
3521 | } | |
3522 | ||
3523 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3524 | struct kvm_vcpu *vcpu, u32 *error) | |
3525 | { | |
3526 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3527 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, | |
3528 | error); | |
3529 | } | |
3530 | ||
3531 | static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes, | |
3532 | struct kvm_vcpu *vcpu, u32 *error) | |
3533 | { | |
3534 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error); | |
3535 | } | |
3536 | ||
7972995b | 3537 | static int kvm_write_guest_virt_system(gva_t addr, void *val, |
2dafc6c2 | 3538 | unsigned int bytes, |
7972995b | 3539 | struct kvm_vcpu *vcpu, |
2dafc6c2 | 3540 | u32 *error) |
77c2002e IE |
3541 | { |
3542 | void *data = val; | |
3543 | int r = X86EMUL_CONTINUE; | |
3544 | ||
3545 | while (bytes) { | |
14dfe855 JR |
3546 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
3547 | PFERR_WRITE_MASK, | |
3548 | error); | |
77c2002e IE |
3549 | unsigned offset = addr & (PAGE_SIZE-1); |
3550 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3551 | int ret; | |
3552 | ||
3553 | if (gpa == UNMAPPED_GVA) { | |
3554 | r = X86EMUL_PROPAGATE_FAULT; | |
3555 | goto out; | |
3556 | } | |
3557 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
3558 | if (ret < 0) { | |
c3cd7ffa | 3559 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
3560 | goto out; |
3561 | } | |
3562 | ||
3563 | bytes -= towrite; | |
3564 | data += towrite; | |
3565 | addr += towrite; | |
3566 | } | |
3567 | out: | |
3568 | return r; | |
3569 | } | |
3570 | ||
bbd9b64e CO |
3571 | static int emulator_read_emulated(unsigned long addr, |
3572 | void *val, | |
3573 | unsigned int bytes, | |
8fe681e9 | 3574 | unsigned int *error_code, |
bbd9b64e CO |
3575 | struct kvm_vcpu *vcpu) |
3576 | { | |
bbd9b64e CO |
3577 | gpa_t gpa; |
3578 | ||
3579 | if (vcpu->mmio_read_completed) { | |
3580 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
3581 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
3582 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
3583 | vcpu->mmio_read_completed = 0; |
3584 | return X86EMUL_CONTINUE; | |
3585 | } | |
3586 | ||
8fe681e9 | 3587 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code); |
1871c602 | 3588 | |
8fe681e9 | 3589 | if (gpa == UNMAPPED_GVA) |
1871c602 | 3590 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3591 | |
3592 | /* For APIC access vmexit */ | |
3593 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3594 | goto mmio; | |
3595 | ||
1871c602 | 3596 | if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL) |
77c2002e | 3597 | == X86EMUL_CONTINUE) |
bbd9b64e | 3598 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3599 | |
3600 | mmio: | |
3601 | /* | |
3602 | * Is this MMIO handled locally? | |
3603 | */ | |
aec51dc4 AK |
3604 | if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) { |
3605 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val); | |
bbd9b64e CO |
3606 | return X86EMUL_CONTINUE; |
3607 | } | |
aec51dc4 AK |
3608 | |
3609 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
3610 | |
3611 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3612 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3613 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3614 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3615 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0; | |
bbd9b64e | 3616 | |
c3cd7ffa | 3617 | return X86EMUL_IO_NEEDED; |
bbd9b64e CO |
3618 | } |
3619 | ||
3200f405 | 3620 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 3621 | const void *val, int bytes) |
bbd9b64e CO |
3622 | { |
3623 | int ret; | |
3624 | ||
3625 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3626 | if (ret < 0) |
bbd9b64e | 3627 | return 0; |
ad218f85 | 3628 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
3629 | return 1; |
3630 | } | |
3631 | ||
3632 | static int emulator_write_emulated_onepage(unsigned long addr, | |
3633 | const void *val, | |
3634 | unsigned int bytes, | |
8fe681e9 | 3635 | unsigned int *error_code, |
bbd9b64e CO |
3636 | struct kvm_vcpu *vcpu) |
3637 | { | |
10589a46 MT |
3638 | gpa_t gpa; |
3639 | ||
8fe681e9 | 3640 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code); |
bbd9b64e | 3641 | |
8fe681e9 | 3642 | if (gpa == UNMAPPED_GVA) |
bbd9b64e | 3643 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
3644 | |
3645 | /* For APIC access vmexit */ | |
3646 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3647 | goto mmio; | |
3648 | ||
3649 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
3650 | return X86EMUL_CONTINUE; | |
3651 | ||
3652 | mmio: | |
aec51dc4 | 3653 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
3654 | /* |
3655 | * Is this MMIO handled locally? | |
3656 | */ | |
bda9020e | 3657 | if (!vcpu_mmio_write(vcpu, gpa, bytes, val)) |
bbd9b64e | 3658 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3659 | |
3660 | vcpu->mmio_needed = 1; | |
411c35b7 GN |
3661 | vcpu->run->exit_reason = KVM_EXIT_MMIO; |
3662 | vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa; | |
3663 | vcpu->run->mmio.len = vcpu->mmio_size = bytes; | |
3664 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1; | |
3665 | memcpy(vcpu->run->mmio.data, val, bytes); | |
bbd9b64e CO |
3666 | |
3667 | return X86EMUL_CONTINUE; | |
3668 | } | |
3669 | ||
3670 | int emulator_write_emulated(unsigned long addr, | |
8f6abd06 GN |
3671 | const void *val, |
3672 | unsigned int bytes, | |
8fe681e9 | 3673 | unsigned int *error_code, |
8f6abd06 | 3674 | struct kvm_vcpu *vcpu) |
bbd9b64e CO |
3675 | { |
3676 | /* Crossing a page boundary? */ | |
3677 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
3678 | int rc, now; | |
3679 | ||
3680 | now = -addr & ~PAGE_MASK; | |
8fe681e9 GN |
3681 | rc = emulator_write_emulated_onepage(addr, val, now, error_code, |
3682 | vcpu); | |
bbd9b64e CO |
3683 | if (rc != X86EMUL_CONTINUE) |
3684 | return rc; | |
3685 | addr += now; | |
3686 | val += now; | |
3687 | bytes -= now; | |
3688 | } | |
8fe681e9 GN |
3689 | return emulator_write_emulated_onepage(addr, val, bytes, error_code, |
3690 | vcpu); | |
bbd9b64e | 3691 | } |
bbd9b64e | 3692 | |
daea3e73 AK |
3693 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3694 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3695 | ||
3696 | #ifdef CONFIG_X86_64 | |
3697 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3698 | #else | |
3699 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 3700 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
3701 | #endif |
3702 | ||
bbd9b64e CO |
3703 | static int emulator_cmpxchg_emulated(unsigned long addr, |
3704 | const void *old, | |
3705 | const void *new, | |
3706 | unsigned int bytes, | |
8fe681e9 | 3707 | unsigned int *error_code, |
bbd9b64e CO |
3708 | struct kvm_vcpu *vcpu) |
3709 | { | |
daea3e73 AK |
3710 | gpa_t gpa; |
3711 | struct page *page; | |
3712 | char *kaddr; | |
3713 | bool exchanged; | |
2bacc55c | 3714 | |
daea3e73 AK |
3715 | /* guests cmpxchg8b have to be emulated atomically */ |
3716 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3717 | goto emul_write; | |
10589a46 | 3718 | |
daea3e73 | 3719 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3720 | |
daea3e73 AK |
3721 | if (gpa == UNMAPPED_GVA || |
3722 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3723 | goto emul_write; | |
2bacc55c | 3724 | |
daea3e73 AK |
3725 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3726 | goto emul_write; | |
72dc67a6 | 3727 | |
daea3e73 | 3728 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
c19b8bd6 WY |
3729 | if (is_error_page(page)) { |
3730 | kvm_release_page_clean(page); | |
3731 | goto emul_write; | |
3732 | } | |
72dc67a6 | 3733 | |
daea3e73 AK |
3734 | kaddr = kmap_atomic(page, KM_USER0); |
3735 | kaddr += offset_in_page(gpa); | |
3736 | switch (bytes) { | |
3737 | case 1: | |
3738 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3739 | break; | |
3740 | case 2: | |
3741 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3742 | break; | |
3743 | case 4: | |
3744 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3745 | break; | |
3746 | case 8: | |
3747 | exchanged = CMPXCHG64(kaddr, old, new); | |
3748 | break; | |
3749 | default: | |
3750 | BUG(); | |
2bacc55c | 3751 | } |
daea3e73 AK |
3752 | kunmap_atomic(kaddr, KM_USER0); |
3753 | kvm_release_page_dirty(page); | |
3754 | ||
3755 | if (!exchanged) | |
3756 | return X86EMUL_CMPXCHG_FAILED; | |
3757 | ||
8f6abd06 GN |
3758 | kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1); |
3759 | ||
3760 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 3761 | |
3200f405 | 3762 | emul_write: |
daea3e73 | 3763 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3764 | |
8fe681e9 | 3765 | return emulator_write_emulated(addr, new, bytes, error_code, vcpu); |
bbd9b64e CO |
3766 | } |
3767 | ||
cf8f70bf GN |
3768 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
3769 | { | |
3770 | /* TODO: String I/O for in kernel device */ | |
3771 | int r; | |
3772 | ||
3773 | if (vcpu->arch.pio.in) | |
3774 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
3775 | vcpu->arch.pio.size, pd); | |
3776 | else | |
3777 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
3778 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
3779 | pd); | |
3780 | return r; | |
3781 | } | |
3782 | ||
3783 | ||
3784 | static int emulator_pio_in_emulated(int size, unsigned short port, void *val, | |
3785 | unsigned int count, struct kvm_vcpu *vcpu) | |
3786 | { | |
7972995b | 3787 | if (vcpu->arch.pio.count) |
cf8f70bf GN |
3788 | goto data_avail; |
3789 | ||
c41a15dd | 3790 | trace_kvm_pio(0, port, size, 1); |
cf8f70bf GN |
3791 | |
3792 | vcpu->arch.pio.port = port; | |
3793 | vcpu->arch.pio.in = 1; | |
7972995b | 3794 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
3795 | vcpu->arch.pio.size = size; |
3796 | ||
3797 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
3798 | data_avail: | |
3799 | memcpy(val, vcpu->arch.pio_data, size * count); | |
7972995b | 3800 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
3801 | return 1; |
3802 | } | |
3803 | ||
3804 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3805 | vcpu->run->io.direction = KVM_EXIT_IO_IN; | |
3806 | vcpu->run->io.size = size; | |
3807 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
3808 | vcpu->run->io.count = count; | |
3809 | vcpu->run->io.port = port; | |
3810 | ||
3811 | return 0; | |
3812 | } | |
3813 | ||
3814 | static int emulator_pio_out_emulated(int size, unsigned short port, | |
3815 | const void *val, unsigned int count, | |
3816 | struct kvm_vcpu *vcpu) | |
3817 | { | |
c41a15dd | 3818 | trace_kvm_pio(1, port, size, 1); |
cf8f70bf GN |
3819 | |
3820 | vcpu->arch.pio.port = port; | |
3821 | vcpu->arch.pio.in = 0; | |
7972995b | 3822 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
3823 | vcpu->arch.pio.size = size; |
3824 | ||
3825 | memcpy(vcpu->arch.pio_data, val, size * count); | |
3826 | ||
3827 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 3828 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
3829 | return 1; |
3830 | } | |
3831 | ||
3832 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3833 | vcpu->run->io.direction = KVM_EXIT_IO_OUT; | |
3834 | vcpu->run->io.size = size; | |
3835 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
3836 | vcpu->run->io.count = count; | |
3837 | vcpu->run->io.port = port; | |
3838 | ||
3839 | return 0; | |
3840 | } | |
3841 | ||
bbd9b64e CO |
3842 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
3843 | { | |
3844 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
3845 | } | |
3846 | ||
3847 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
3848 | { | |
a7052897 | 3849 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
3850 | return X86EMUL_CONTINUE; |
3851 | } | |
3852 | ||
f5f48ee1 SY |
3853 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) |
3854 | { | |
3855 | if (!need_emulate_wbinvd(vcpu)) | |
3856 | return X86EMUL_CONTINUE; | |
3857 | ||
3858 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
3859 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, | |
3860 | wbinvd_ipi, NULL, 1); | |
3861 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); | |
3862 | } | |
3863 | wbinvd(); | |
3864 | return X86EMUL_CONTINUE; | |
3865 | } | |
3866 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
3867 | ||
bbd9b64e CO |
3868 | int emulate_clts(struct kvm_vcpu *vcpu) |
3869 | { | |
4d4ec087 | 3870 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
6b52d186 | 3871 | kvm_x86_ops->fpu_activate(vcpu); |
bbd9b64e CO |
3872 | return X86EMUL_CONTINUE; |
3873 | } | |
3874 | ||
35aa5375 | 3875 | int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu) |
bbd9b64e | 3876 | { |
338dbc97 | 3877 | return _kvm_get_dr(vcpu, dr, dest); |
bbd9b64e CO |
3878 | } |
3879 | ||
35aa5375 | 3880 | int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu) |
bbd9b64e | 3881 | { |
338dbc97 GN |
3882 | |
3883 | return __kvm_set_dr(vcpu, dr, value); | |
bbd9b64e CO |
3884 | } |
3885 | ||
52a46617 | 3886 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 3887 | { |
52a46617 | 3888 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
3889 | } |
3890 | ||
52a46617 | 3891 | static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu) |
bbd9b64e | 3892 | { |
52a46617 GN |
3893 | unsigned long value; |
3894 | ||
3895 | switch (cr) { | |
3896 | case 0: | |
3897 | value = kvm_read_cr0(vcpu); | |
3898 | break; | |
3899 | case 2: | |
3900 | value = vcpu->arch.cr2; | |
3901 | break; | |
3902 | case 3: | |
3903 | value = vcpu->arch.cr3; | |
3904 | break; | |
3905 | case 4: | |
3906 | value = kvm_read_cr4(vcpu); | |
3907 | break; | |
3908 | case 8: | |
3909 | value = kvm_get_cr8(vcpu); | |
3910 | break; | |
3911 | default: | |
3912 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
3913 | return 0; | |
3914 | } | |
3915 | ||
3916 | return value; | |
3917 | } | |
3918 | ||
0f12244f | 3919 | static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu) |
52a46617 | 3920 | { |
0f12244f GN |
3921 | int res = 0; |
3922 | ||
52a46617 GN |
3923 | switch (cr) { |
3924 | case 0: | |
49a9b07e | 3925 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
3926 | break; |
3927 | case 2: | |
3928 | vcpu->arch.cr2 = val; | |
3929 | break; | |
3930 | case 3: | |
2390218b | 3931 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
3932 | break; |
3933 | case 4: | |
a83b29c6 | 3934 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
3935 | break; |
3936 | case 8: | |
0f12244f | 3937 | res = __kvm_set_cr8(vcpu, val & 0xfUL); |
52a46617 GN |
3938 | break; |
3939 | default: | |
3940 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); | |
0f12244f | 3941 | res = -1; |
52a46617 | 3942 | } |
0f12244f GN |
3943 | |
3944 | return res; | |
52a46617 GN |
3945 | } |
3946 | ||
9c537244 GN |
3947 | static int emulator_get_cpl(struct kvm_vcpu *vcpu) |
3948 | { | |
3949 | return kvm_x86_ops->get_cpl(vcpu); | |
3950 | } | |
3951 | ||
2dafc6c2 GN |
3952 | static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
3953 | { | |
3954 | kvm_x86_ops->get_gdt(vcpu, dt); | |
3955 | } | |
3956 | ||
160ce1f1 MG |
3957 | static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu) |
3958 | { | |
3959 | kvm_x86_ops->get_idt(vcpu, dt); | |
3960 | } | |
3961 | ||
5951c442 GN |
3962 | static unsigned long emulator_get_cached_segment_base(int seg, |
3963 | struct kvm_vcpu *vcpu) | |
3964 | { | |
3965 | return get_segment_base(vcpu, seg); | |
3966 | } | |
3967 | ||
2dafc6c2 GN |
3968 | static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg, |
3969 | struct kvm_vcpu *vcpu) | |
3970 | { | |
3971 | struct kvm_segment var; | |
3972 | ||
3973 | kvm_get_segment(vcpu, &var, seg); | |
3974 | ||
3975 | if (var.unusable) | |
3976 | return false; | |
3977 | ||
3978 | if (var.g) | |
3979 | var.limit >>= 12; | |
3980 | set_desc_limit(desc, var.limit); | |
3981 | set_desc_base(desc, (unsigned long)var.base); | |
3982 | desc->type = var.type; | |
3983 | desc->s = var.s; | |
3984 | desc->dpl = var.dpl; | |
3985 | desc->p = var.present; | |
3986 | desc->avl = var.avl; | |
3987 | desc->l = var.l; | |
3988 | desc->d = var.db; | |
3989 | desc->g = var.g; | |
3990 | ||
3991 | return true; | |
3992 | } | |
3993 | ||
3994 | static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg, | |
3995 | struct kvm_vcpu *vcpu) | |
3996 | { | |
3997 | struct kvm_segment var; | |
3998 | ||
3999 | /* needed to preserve selector */ | |
4000 | kvm_get_segment(vcpu, &var, seg); | |
4001 | ||
4002 | var.base = get_desc_base(desc); | |
4003 | var.limit = get_desc_limit(desc); | |
4004 | if (desc->g) | |
4005 | var.limit = (var.limit << 12) | 0xfff; | |
4006 | var.type = desc->type; | |
4007 | var.present = desc->p; | |
4008 | var.dpl = desc->dpl; | |
4009 | var.db = desc->d; | |
4010 | var.s = desc->s; | |
4011 | var.l = desc->l; | |
4012 | var.g = desc->g; | |
4013 | var.avl = desc->avl; | |
4014 | var.present = desc->p; | |
4015 | var.unusable = !var.present; | |
4016 | var.padding = 0; | |
4017 | ||
4018 | kvm_set_segment(vcpu, &var, seg); | |
4019 | return; | |
4020 | } | |
4021 | ||
4022 | static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu) | |
4023 | { | |
4024 | struct kvm_segment kvm_seg; | |
4025 | ||
4026 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4027 | return kvm_seg.selector; | |
4028 | } | |
4029 | ||
4030 | static void emulator_set_segment_selector(u16 sel, int seg, | |
4031 | struct kvm_vcpu *vcpu) | |
4032 | { | |
4033 | struct kvm_segment kvm_seg; | |
4034 | ||
4035 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4036 | kvm_seg.selector = sel; | |
4037 | kvm_set_segment(vcpu, &kvm_seg, seg); | |
4038 | } | |
4039 | ||
14af3f3c | 4040 | static struct x86_emulate_ops emulate_ops = { |
1871c602 | 4041 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 4042 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 4043 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
4044 | .read_emulated = emulator_read_emulated, |
4045 | .write_emulated = emulator_write_emulated, | |
4046 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
cf8f70bf GN |
4047 | .pio_in_emulated = emulator_pio_in_emulated, |
4048 | .pio_out_emulated = emulator_pio_out_emulated, | |
2dafc6c2 GN |
4049 | .get_cached_descriptor = emulator_get_cached_descriptor, |
4050 | .set_cached_descriptor = emulator_set_cached_descriptor, | |
4051 | .get_segment_selector = emulator_get_segment_selector, | |
4052 | .set_segment_selector = emulator_set_segment_selector, | |
5951c442 | 4053 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 4054 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 4055 | .get_idt = emulator_get_idt, |
52a46617 GN |
4056 | .get_cr = emulator_get_cr, |
4057 | .set_cr = emulator_set_cr, | |
9c537244 | 4058 | .cpl = emulator_get_cpl, |
35aa5375 GN |
4059 | .get_dr = emulator_get_dr, |
4060 | .set_dr = emulator_set_dr, | |
3fb1b5db GN |
4061 | .set_msr = kvm_set_msr, |
4062 | .get_msr = kvm_get_msr, | |
bbd9b64e CO |
4063 | }; |
4064 | ||
5fdbf976 MT |
4065 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
4066 | { | |
4067 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4068 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4069 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
4070 | vcpu->arch.regs_dirty = ~0; | |
4071 | } | |
4072 | ||
95cb2295 GN |
4073 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
4074 | { | |
4075 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4076 | /* | |
4077 | * an sti; sti; sequence only disable interrupts for the first | |
4078 | * instruction. So, if the last instruction, be it emulated or | |
4079 | * not, left the system with the INT_STI flag enabled, it | |
4080 | * means that the last instruction is an sti. We should not | |
4081 | * leave the flag on in this case. The same goes for mov ss | |
4082 | */ | |
4083 | if (!(int_shadow & mask)) | |
4084 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4085 | } | |
4086 | ||
54b8486f GN |
4087 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
4088 | { | |
4089 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
4090 | if (ctxt->exception == PF_VECTOR) | |
8df25a32 | 4091 | kvm_inject_page_fault(vcpu); |
54b8486f GN |
4092 | else if (ctxt->error_code_valid) |
4093 | kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code); | |
4094 | else | |
4095 | kvm_queue_exception(vcpu, ctxt->exception); | |
4096 | } | |
4097 | ||
8ec4722d MG |
4098 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
4099 | { | |
4100 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; | |
4101 | int cs_db, cs_l; | |
4102 | ||
4103 | cache_all_regs(vcpu); | |
4104 | ||
4105 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4106 | ||
4107 | vcpu->arch.emulate_ctxt.vcpu = vcpu; | |
4108 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); | |
4109 | vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu); | |
4110 | vcpu->arch.emulate_ctxt.mode = | |
4111 | (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4112 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
4113 | ? X86EMUL_MODE_VM86 : cs_l | |
4114 | ? X86EMUL_MODE_PROT64 : cs_db | |
4115 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
4116 | memset(c, 0, sizeof(struct decode_cache)); | |
4117 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4118 | } | |
4119 | ||
6d77dbfc GN |
4120 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
4121 | { | |
6d77dbfc GN |
4122 | ++vcpu->stat.insn_emulation_fail; |
4123 | trace_kvm_emulate_insn_failed(vcpu); | |
4124 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4125 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4126 | vcpu->run->internal.ndata = 0; | |
4127 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4128 | return EMULATE_FAIL; | |
4129 | } | |
4130 | ||
a6f177ef GN |
4131 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva) |
4132 | { | |
4133 | gpa_t gpa; | |
4134 | ||
68be0803 GN |
4135 | if (tdp_enabled) |
4136 | return false; | |
4137 | ||
a6f177ef GN |
4138 | /* |
4139 | * if emulation was due to access to shadowed page table | |
4140 | * and it failed try to unshadow page and re-entetr the | |
4141 | * guest to let CPU execute the instruction. | |
4142 | */ | |
4143 | if (kvm_mmu_unprotect_page_virt(vcpu, gva)) | |
4144 | return true; | |
4145 | ||
4146 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL); | |
4147 | ||
4148 | if (gpa == UNMAPPED_GVA) | |
4149 | return true; /* let cpu generate fault */ | |
4150 | ||
4151 | if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT))) | |
4152 | return true; | |
4153 | ||
4154 | return false; | |
4155 | } | |
4156 | ||
bbd9b64e | 4157 | int emulate_instruction(struct kvm_vcpu *vcpu, |
bbd9b64e CO |
4158 | unsigned long cr2, |
4159 | u16 error_code, | |
571008da | 4160 | int emulation_type) |
bbd9b64e | 4161 | { |
95cb2295 | 4162 | int r; |
4d2179e1 | 4163 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
bbd9b64e | 4164 | |
26eef70c | 4165 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 4166 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 4167 | /* |
56e82318 | 4168 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
4169 | * instead of direct ->regs accesses, can save hundred cycles |
4170 | * on Intel for instructions that don't read/change RSP, for | |
4171 | * for example. | |
4172 | */ | |
4173 | cache_all_regs(vcpu); | |
bbd9b64e | 4174 | |
571008da | 4175 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 4176 | init_emulate_ctxt(vcpu); |
95cb2295 | 4177 | vcpu->arch.emulate_ctxt.interruptibility = 0; |
54b8486f | 4178 | vcpu->arch.emulate_ctxt.exception = -1; |
4fc40f07 | 4179 | vcpu->arch.emulate_ctxt.perm_ok = false; |
bbd9b64e | 4180 | |
9aabc88f | 4181 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt); |
e46479f8 | 4182 | trace_kvm_emulate_insn_start(vcpu); |
571008da | 4183 | |
0cb5762e AP |
4184 | /* Only allow emulation of specific instructions on #UD |
4185 | * (namely VMMCALL, sysenter, sysexit, syscall)*/ | |
0cb5762e AP |
4186 | if (emulation_type & EMULTYPE_TRAP_UD) { |
4187 | if (!c->twobyte) | |
4188 | return EMULATE_FAIL; | |
4189 | switch (c->b) { | |
4190 | case 0x01: /* VMMCALL */ | |
4191 | if (c->modrm_mod != 3 || c->modrm_rm != 1) | |
4192 | return EMULATE_FAIL; | |
4193 | break; | |
4194 | case 0x34: /* sysenter */ | |
4195 | case 0x35: /* sysexit */ | |
4196 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
4197 | return EMULATE_FAIL; | |
4198 | break; | |
4199 | case 0x05: /* syscall */ | |
4200 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
4201 | return EMULATE_FAIL; | |
4202 | break; | |
4203 | default: | |
4204 | return EMULATE_FAIL; | |
4205 | } | |
4206 | ||
4207 | if (!(c->modrm_reg == 0 || c->modrm_reg == 3)) | |
4208 | return EMULATE_FAIL; | |
4209 | } | |
571008da | 4210 | |
f2b5756b | 4211 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 4212 | if (r) { |
a6f177ef | 4213 | if (reexecute_instruction(vcpu, cr2)) |
bbd9b64e | 4214 | return EMULATE_DONE; |
6d77dbfc GN |
4215 | if (emulation_type & EMULTYPE_SKIP) |
4216 | return EMULATE_FAIL; | |
4217 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
4218 | } |
4219 | } | |
4220 | ||
ba8afb6b GN |
4221 | if (emulation_type & EMULTYPE_SKIP) { |
4222 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
4223 | return EMULATE_DONE; | |
4224 | } | |
4225 | ||
4d2179e1 GN |
4226 | /* this is needed for vmware backdor interface to work since it |
4227 | changes registers values during IO operation */ | |
4228 | memcpy(c->regs, vcpu->arch.regs, sizeof c->regs); | |
4229 | ||
5cd21917 | 4230 | restart: |
9aabc88f | 4231 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt); |
bbd9b64e | 4232 | |
d2ddd1c4 | 4233 | if (r == EMULATION_FAILED) { |
a6f177ef | 4234 | if (reexecute_instruction(vcpu, cr2)) |
c3cd7ffa GN |
4235 | return EMULATE_DONE; |
4236 | ||
6d77dbfc | 4237 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
4238 | } |
4239 | ||
d2ddd1c4 | 4240 | if (vcpu->arch.emulate_ctxt.exception >= 0) { |
54b8486f | 4241 | inject_emulated_exception(vcpu); |
d2ddd1c4 GN |
4242 | r = EMULATE_DONE; |
4243 | } else if (vcpu->arch.pio.count) { | |
3457e419 GN |
4244 | if (!vcpu->arch.pio.in) |
4245 | vcpu->arch.pio.count = 0; | |
e85d28f8 GN |
4246 | r = EMULATE_DO_MMIO; |
4247 | } else if (vcpu->mmio_needed) { | |
3457e419 GN |
4248 | if (vcpu->mmio_is_write) |
4249 | vcpu->mmio_needed = 0; | |
e85d28f8 | 4250 | r = EMULATE_DO_MMIO; |
d2ddd1c4 | 4251 | } else if (r == EMULATION_RESTART) |
5cd21917 | 4252 | goto restart; |
d2ddd1c4 GN |
4253 | else |
4254 | r = EMULATE_DONE; | |
f850e2e6 | 4255 | |
e85d28f8 GN |
4256 | toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility); |
4257 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); | |
4258 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); | |
4259 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); | |
4260 | ||
4261 | return r; | |
de7d789a | 4262 | } |
bbd9b64e | 4263 | EXPORT_SYMBOL_GPL(emulate_instruction); |
de7d789a | 4264 | |
cf8f70bf | 4265 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 4266 | { |
cf8f70bf GN |
4267 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4268 | int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu); | |
4269 | /* do not return to emulator after return from userspace */ | |
7972995b | 4270 | vcpu->arch.pio.count = 0; |
de7d789a CO |
4271 | return ret; |
4272 | } | |
cf8f70bf | 4273 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 4274 | |
8cfdc000 ZA |
4275 | static void tsc_bad(void *info) |
4276 | { | |
4277 | __get_cpu_var(cpu_tsc_khz) = 0; | |
4278 | } | |
4279 | ||
4280 | static void tsc_khz_changed(void *data) | |
c8076604 | 4281 | { |
8cfdc000 ZA |
4282 | struct cpufreq_freqs *freq = data; |
4283 | unsigned long khz = 0; | |
4284 | ||
4285 | if (data) | |
4286 | khz = freq->new; | |
4287 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
4288 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
4289 | if (!khz) | |
4290 | khz = tsc_khz; | |
4291 | __get_cpu_var(cpu_tsc_khz) = khz; | |
c8076604 GH |
4292 | } |
4293 | ||
c8076604 GH |
4294 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
4295 | void *data) | |
4296 | { | |
4297 | struct cpufreq_freqs *freq = data; | |
4298 | struct kvm *kvm; | |
4299 | struct kvm_vcpu *vcpu; | |
4300 | int i, send_ipi = 0; | |
4301 | ||
8cfdc000 ZA |
4302 | /* |
4303 | * We allow guests to temporarily run on slowing clocks, | |
4304 | * provided we notify them after, or to run on accelerating | |
4305 | * clocks, provided we notify them before. Thus time never | |
4306 | * goes backwards. | |
4307 | * | |
4308 | * However, we have a problem. We can't atomically update | |
4309 | * the frequency of a given CPU from this function; it is | |
4310 | * merely a notifier, which can be called from any CPU. | |
4311 | * Changing the TSC frequency at arbitrary points in time | |
4312 | * requires a recomputation of local variables related to | |
4313 | * the TSC for each VCPU. We must flag these local variables | |
4314 | * to be updated and be sure the update takes place with the | |
4315 | * new frequency before any guests proceed. | |
4316 | * | |
4317 | * Unfortunately, the combination of hotplug CPU and frequency | |
4318 | * change creates an intractable locking scenario; the order | |
4319 | * of when these callouts happen is undefined with respect to | |
4320 | * CPU hotplug, and they can race with each other. As such, | |
4321 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
4322 | * undefined; you can actually have a CPU frequency change take | |
4323 | * place in between the computation of X and the setting of the | |
4324 | * variable. To protect against this problem, all updates of | |
4325 | * the per_cpu tsc_khz variable are done in an interrupt | |
4326 | * protected IPI, and all callers wishing to update the value | |
4327 | * must wait for a synchronous IPI to complete (which is trivial | |
4328 | * if the caller is on the CPU already). This establishes the | |
4329 | * necessary total order on variable updates. | |
4330 | * | |
4331 | * Note that because a guest time update may take place | |
4332 | * anytime after the setting of the VCPU's request bit, the | |
4333 | * correct TSC value must be set before the request. However, | |
4334 | * to ensure the update actually makes it to any guest which | |
4335 | * starts running in hardware virtualization between the set | |
4336 | * and the acquisition of the spinlock, we must also ping the | |
4337 | * CPU after setting the request bit. | |
4338 | * | |
4339 | */ | |
4340 | ||
c8076604 GH |
4341 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
4342 | return 0; | |
4343 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
4344 | return 0; | |
8cfdc000 ZA |
4345 | |
4346 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 GH |
4347 | |
4348 | spin_lock(&kvm_lock); | |
4349 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
988a2cae | 4350 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
4351 | if (vcpu->cpu != freq->cpu) |
4352 | continue; | |
4353 | if (!kvm_request_guest_time_update(vcpu)) | |
4354 | continue; | |
4355 | if (vcpu->cpu != smp_processor_id()) | |
8cfdc000 | 4356 | send_ipi = 1; |
c8076604 GH |
4357 | } |
4358 | } | |
4359 | spin_unlock(&kvm_lock); | |
4360 | ||
4361 | if (freq->old < freq->new && send_ipi) { | |
4362 | /* | |
4363 | * We upscale the frequency. Must make the guest | |
4364 | * doesn't see old kvmclock values while running with | |
4365 | * the new frequency, otherwise we risk the guest sees | |
4366 | * time go backwards. | |
4367 | * | |
4368 | * In case we update the frequency for another cpu | |
4369 | * (which might be in guest context) send an interrupt | |
4370 | * to kick the cpu out of guest context. Next time | |
4371 | * guest context is entered kvmclock will be updated, | |
4372 | * so the guest will not see stale values. | |
4373 | */ | |
8cfdc000 | 4374 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
4375 | } |
4376 | return 0; | |
4377 | } | |
4378 | ||
4379 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
4380 | .notifier_call = kvmclock_cpufreq_notifier |
4381 | }; | |
4382 | ||
4383 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
4384 | unsigned long action, void *hcpu) | |
4385 | { | |
4386 | unsigned int cpu = (unsigned long)hcpu; | |
4387 | ||
4388 | switch (action) { | |
4389 | case CPU_ONLINE: | |
4390 | case CPU_DOWN_FAILED: | |
4391 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
4392 | break; | |
4393 | case CPU_DOWN_PREPARE: | |
4394 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
4395 | break; | |
4396 | } | |
4397 | return NOTIFY_OK; | |
4398 | } | |
4399 | ||
4400 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
4401 | .notifier_call = kvmclock_cpu_notifier, | |
4402 | .priority = -INT_MAX | |
c8076604 GH |
4403 | }; |
4404 | ||
b820cc0c ZA |
4405 | static void kvm_timer_init(void) |
4406 | { | |
4407 | int cpu; | |
4408 | ||
8cfdc000 | 4409 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
b820cc0c | 4410 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
b820cc0c ZA |
4411 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
4412 | CPUFREQ_TRANSITION_NOTIFIER); | |
4413 | } | |
8cfdc000 ZA |
4414 | for_each_online_cpu(cpu) |
4415 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
b820cc0c ZA |
4416 | } |
4417 | ||
ff9d07a0 ZY |
4418 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
4419 | ||
4420 | static int kvm_is_in_guest(void) | |
4421 | { | |
4422 | return percpu_read(current_vcpu) != NULL; | |
4423 | } | |
4424 | ||
4425 | static int kvm_is_user_mode(void) | |
4426 | { | |
4427 | int user_mode = 3; | |
dcf46b94 | 4428 | |
ff9d07a0 ZY |
4429 | if (percpu_read(current_vcpu)) |
4430 | user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu)); | |
dcf46b94 | 4431 | |
ff9d07a0 ZY |
4432 | return user_mode != 0; |
4433 | } | |
4434 | ||
4435 | static unsigned long kvm_get_guest_ip(void) | |
4436 | { | |
4437 | unsigned long ip = 0; | |
dcf46b94 | 4438 | |
ff9d07a0 ZY |
4439 | if (percpu_read(current_vcpu)) |
4440 | ip = kvm_rip_read(percpu_read(current_vcpu)); | |
dcf46b94 | 4441 | |
ff9d07a0 ZY |
4442 | return ip; |
4443 | } | |
4444 | ||
4445 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
4446 | .is_in_guest = kvm_is_in_guest, | |
4447 | .is_user_mode = kvm_is_user_mode, | |
4448 | .get_guest_ip = kvm_get_guest_ip, | |
4449 | }; | |
4450 | ||
4451 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
4452 | { | |
4453 | percpu_write(current_vcpu, vcpu); | |
4454 | } | |
4455 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
4456 | ||
4457 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
4458 | { | |
4459 | percpu_write(current_vcpu, NULL); | |
4460 | } | |
4461 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
4462 | ||
f8c16bba | 4463 | int kvm_arch_init(void *opaque) |
043405e1 | 4464 | { |
b820cc0c | 4465 | int r; |
f8c16bba ZX |
4466 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
4467 | ||
f8c16bba ZX |
4468 | if (kvm_x86_ops) { |
4469 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
4470 | r = -EEXIST; |
4471 | goto out; | |
f8c16bba ZX |
4472 | } |
4473 | ||
4474 | if (!ops->cpu_has_kvm_support()) { | |
4475 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
4476 | r = -EOPNOTSUPP; |
4477 | goto out; | |
f8c16bba ZX |
4478 | } |
4479 | if (ops->disabled_by_bios()) { | |
4480 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
4481 | r = -EOPNOTSUPP; |
4482 | goto out; | |
f8c16bba ZX |
4483 | } |
4484 | ||
97db56ce AK |
4485 | r = kvm_mmu_module_init(); |
4486 | if (r) | |
4487 | goto out; | |
4488 | ||
4489 | kvm_init_msr_list(); | |
4490 | ||
f8c16bba | 4491 | kvm_x86_ops = ops; |
56c6d28a | 4492 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e SY |
4493 | kvm_mmu_set_base_ptes(PT_PRESENT_MASK); |
4494 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
4b12f0de | 4495 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 4496 | |
b820cc0c | 4497 | kvm_timer_init(); |
c8076604 | 4498 | |
ff9d07a0 ZY |
4499 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
4500 | ||
2acf923e DC |
4501 | if (cpu_has_xsave) |
4502 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
4503 | ||
f8c16bba | 4504 | return 0; |
56c6d28a ZX |
4505 | |
4506 | out: | |
56c6d28a | 4507 | return r; |
043405e1 | 4508 | } |
8776e519 | 4509 | |
f8c16bba ZX |
4510 | void kvm_arch_exit(void) |
4511 | { | |
ff9d07a0 ZY |
4512 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
4513 | ||
888d256e JK |
4514 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
4515 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
4516 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 4517 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
f8c16bba | 4518 | kvm_x86_ops = NULL; |
56c6d28a ZX |
4519 | kvm_mmu_module_exit(); |
4520 | } | |
f8c16bba | 4521 | |
8776e519 HB |
4522 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
4523 | { | |
4524 | ++vcpu->stat.halt_exits; | |
4525 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 4526 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
4527 | return 1; |
4528 | } else { | |
4529 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
4530 | return 0; | |
4531 | } | |
4532 | } | |
4533 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
4534 | ||
2f333bcb MT |
4535 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
4536 | unsigned long a1) | |
4537 | { | |
4538 | if (is_long_mode(vcpu)) | |
4539 | return a0; | |
4540 | else | |
4541 | return a0 | ((gpa_t)a1 << 32); | |
4542 | } | |
4543 | ||
55cd8e5a GN |
4544 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
4545 | { | |
4546 | u64 param, ingpa, outgpa, ret; | |
4547 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
4548 | bool fast, longmode; | |
4549 | int cs_db, cs_l; | |
4550 | ||
4551 | /* | |
4552 | * hypercall generates UD from non zero cpl and real mode | |
4553 | * per HYPER-V spec | |
4554 | */ | |
3eeb3288 | 4555 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
4556 | kvm_queue_exception(vcpu, UD_VECTOR); |
4557 | return 0; | |
4558 | } | |
4559 | ||
4560 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4561 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
4562 | ||
4563 | if (!longmode) { | |
ccd46936 GN |
4564 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
4565 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
4566 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
4567 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
4568 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
4569 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
4570 | } |
4571 | #ifdef CONFIG_X86_64 | |
4572 | else { | |
4573 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4574 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4575 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
4576 | } | |
4577 | #endif | |
4578 | ||
4579 | code = param & 0xffff; | |
4580 | fast = (param >> 16) & 0x1; | |
4581 | rep_cnt = (param >> 32) & 0xfff; | |
4582 | rep_idx = (param >> 48) & 0xfff; | |
4583 | ||
4584 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
4585 | ||
c25bc163 GN |
4586 | switch (code) { |
4587 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
4588 | kvm_vcpu_on_spin(vcpu); | |
4589 | break; | |
4590 | default: | |
4591 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
4592 | break; | |
4593 | } | |
55cd8e5a GN |
4594 | |
4595 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
4596 | if (longmode) { | |
4597 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
4598 | } else { | |
4599 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
4600 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
4601 | } | |
4602 | ||
4603 | return 1; | |
4604 | } | |
4605 | ||
8776e519 HB |
4606 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
4607 | { | |
4608 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 4609 | int r = 1; |
8776e519 | 4610 | |
55cd8e5a GN |
4611 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
4612 | return kvm_hv_hypercall(vcpu); | |
4613 | ||
5fdbf976 MT |
4614 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4615 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4616 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4617 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4618 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 4619 | |
229456fc | 4620 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 4621 | |
8776e519 HB |
4622 | if (!is_long_mode(vcpu)) { |
4623 | nr &= 0xFFFFFFFF; | |
4624 | a0 &= 0xFFFFFFFF; | |
4625 | a1 &= 0xFFFFFFFF; | |
4626 | a2 &= 0xFFFFFFFF; | |
4627 | a3 &= 0xFFFFFFFF; | |
4628 | } | |
4629 | ||
07708c4a JK |
4630 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
4631 | ret = -KVM_EPERM; | |
4632 | goto out; | |
4633 | } | |
4634 | ||
8776e519 | 4635 | switch (nr) { |
b93463aa AK |
4636 | case KVM_HC_VAPIC_POLL_IRQ: |
4637 | ret = 0; | |
4638 | break; | |
2f333bcb MT |
4639 | case KVM_HC_MMU_OP: |
4640 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
4641 | break; | |
8776e519 HB |
4642 | default: |
4643 | ret = -KVM_ENOSYS; | |
4644 | break; | |
4645 | } | |
07708c4a | 4646 | out: |
5fdbf976 | 4647 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 4648 | ++vcpu->stat.hypercalls; |
2f333bcb | 4649 | return r; |
8776e519 HB |
4650 | } |
4651 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
4652 | ||
4653 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
4654 | { | |
4655 | char instruction[3]; | |
5fdbf976 | 4656 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 4657 | |
8776e519 HB |
4658 | /* |
4659 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
4660 | * to ensure that the updated hypercall appears atomically across all | |
4661 | * VCPUs. | |
4662 | */ | |
4663 | kvm_mmu_zap_all(vcpu->kvm); | |
4664 | ||
8776e519 | 4665 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 4666 | |
8fe681e9 | 4667 | return emulator_write_emulated(rip, instruction, 3, NULL, vcpu); |
8776e519 HB |
4668 | } |
4669 | ||
8776e519 HB |
4670 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) |
4671 | { | |
89a27f4d | 4672 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4673 | |
4674 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4675 | } | |
4676 | ||
4677 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
4678 | { | |
89a27f4d | 4679 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4680 | |
4681 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4682 | } | |
4683 | ||
07716717 DK |
4684 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
4685 | { | |
ad312c7c ZX |
4686 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
4687 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
4688 | |
4689 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4690 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 4691 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 4692 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
4693 | if (ej->function == e->function) { |
4694 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4695 | return j; | |
4696 | } | |
4697 | } | |
4698 | return 0; /* silence gcc, even though control never reaches here */ | |
4699 | } | |
4700 | ||
4701 | /* find an entry with matching function, matching index (if needed), and that | |
4702 | * should be read next (if it's stateful) */ | |
4703 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
4704 | u32 function, u32 index) | |
4705 | { | |
4706 | if (e->function != function) | |
4707 | return 0; | |
4708 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
4709 | return 0; | |
4710 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 4711 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
4712 | return 0; |
4713 | return 1; | |
4714 | } | |
4715 | ||
d8017474 AG |
4716 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
4717 | u32 function, u32 index) | |
8776e519 HB |
4718 | { |
4719 | int i; | |
d8017474 | 4720 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 4721 | |
ad312c7c | 4722 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
4723 | struct kvm_cpuid_entry2 *e; |
4724 | ||
ad312c7c | 4725 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
4726 | if (is_matching_cpuid_entry(e, function, index)) { |
4727 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
4728 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
4729 | best = e; |
4730 | break; | |
4731 | } | |
4732 | /* | |
4733 | * Both basic or both extended? | |
4734 | */ | |
4735 | if (((e->function ^ function) & 0x80000000) == 0) | |
4736 | if (!best || e->function > best->function) | |
4737 | best = e; | |
4738 | } | |
d8017474 AG |
4739 | return best; |
4740 | } | |
0e851880 | 4741 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
d8017474 | 4742 | |
82725b20 DE |
4743 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
4744 | { | |
4745 | struct kvm_cpuid_entry2 *best; | |
4746 | ||
f7a71197 AK |
4747 | best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); |
4748 | if (!best || best->eax < 0x80000008) | |
4749 | goto not_found; | |
82725b20 DE |
4750 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); |
4751 | if (best) | |
4752 | return best->eax & 0xff; | |
f7a71197 | 4753 | not_found: |
82725b20 DE |
4754 | return 36; |
4755 | } | |
4756 | ||
d8017474 AG |
4757 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
4758 | { | |
4759 | u32 function, index; | |
4760 | struct kvm_cpuid_entry2 *best; | |
4761 | ||
4762 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4763 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4764 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
4765 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
4766 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
4767 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
4768 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 4769 | if (best) { |
5fdbf976 MT |
4770 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
4771 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
4772 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
4773 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 4774 | } |
8776e519 | 4775 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
4776 | trace_kvm_cpuid(function, |
4777 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
4778 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
4779 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
4780 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
4781 | } |
4782 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 4783 | |
b6c7a5dc HB |
4784 | /* |
4785 | * Check if userspace requested an interrupt window, and that the | |
4786 | * interrupt window is open. | |
4787 | * | |
4788 | * No need to exit to userspace if we already have an interrupt queued. | |
4789 | */ | |
851ba692 | 4790 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4791 | { |
8061823a | 4792 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 4793 | vcpu->run->request_interrupt_window && |
5df56646 | 4794 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
4795 | } |
4796 | ||
851ba692 | 4797 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4798 | { |
851ba692 AK |
4799 | struct kvm_run *kvm_run = vcpu->run; |
4800 | ||
91586a3b | 4801 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 4802 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 4803 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 4804 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 4805 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 4806 | else |
b6c7a5dc | 4807 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
4808 | kvm_arch_interrupt_allowed(vcpu) && |
4809 | !kvm_cpu_has_interrupt(vcpu) && | |
4810 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
4811 | } |
4812 | ||
b93463aa AK |
4813 | static void vapic_enter(struct kvm_vcpu *vcpu) |
4814 | { | |
4815 | struct kvm_lapic *apic = vcpu->arch.apic; | |
4816 | struct page *page; | |
4817 | ||
4818 | if (!apic || !apic->vapic_addr) | |
4819 | return; | |
4820 | ||
4821 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
4822 | |
4823 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
4824 | } |
4825 | ||
4826 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
4827 | { | |
4828 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 4829 | int idx; |
b93463aa AK |
4830 | |
4831 | if (!apic || !apic->vapic_addr) | |
4832 | return; | |
4833 | ||
f656ce01 | 4834 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
4835 | kvm_release_page_dirty(apic->vapic_page); |
4836 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 4837 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4838 | } |
4839 | ||
95ba8273 GN |
4840 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
4841 | { | |
4842 | int max_irr, tpr; | |
4843 | ||
4844 | if (!kvm_x86_ops->update_cr8_intercept) | |
4845 | return; | |
4846 | ||
88c808fd AK |
4847 | if (!vcpu->arch.apic) |
4848 | return; | |
4849 | ||
8db3baa2 GN |
4850 | if (!vcpu->arch.apic->vapic_addr) |
4851 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
4852 | else | |
4853 | max_irr = -1; | |
95ba8273 GN |
4854 | |
4855 | if (max_irr != -1) | |
4856 | max_irr >>= 4; | |
4857 | ||
4858 | tpr = kvm_lapic_get_cr8(vcpu); | |
4859 | ||
4860 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
4861 | } | |
4862 | ||
851ba692 | 4863 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
4864 | { |
4865 | /* try to reinject previous events if any */ | |
b59bb7bd | 4866 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
4867 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
4868 | vcpu->arch.exception.has_error_code, | |
4869 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
4870 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
4871 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
4872 | vcpu->arch.exception.error_code, |
4873 | vcpu->arch.exception.reinject); | |
b59bb7bd GN |
4874 | return; |
4875 | } | |
4876 | ||
95ba8273 GN |
4877 | if (vcpu->arch.nmi_injected) { |
4878 | kvm_x86_ops->set_nmi(vcpu); | |
4879 | return; | |
4880 | } | |
4881 | ||
4882 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 4883 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
4884 | return; |
4885 | } | |
4886 | ||
4887 | /* try to inject new event if pending */ | |
4888 | if (vcpu->arch.nmi_pending) { | |
4889 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
4890 | vcpu->arch.nmi_pending = false; | |
4891 | vcpu->arch.nmi_injected = true; | |
4892 | kvm_x86_ops->set_nmi(vcpu); | |
4893 | } | |
4894 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
4895 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
4896 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
4897 | false); | |
4898 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
4899 | } |
4900 | } | |
4901 | } | |
4902 | ||
2acf923e DC |
4903 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
4904 | { | |
4905 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
4906 | !vcpu->guest_xcr0_loaded) { | |
4907 | /* kvm_set_xcr() also depends on this */ | |
4908 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
4909 | vcpu->guest_xcr0_loaded = 1; | |
4910 | } | |
4911 | } | |
4912 | ||
4913 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
4914 | { | |
4915 | if (vcpu->guest_xcr0_loaded) { | |
4916 | if (vcpu->arch.xcr0 != host_xcr0) | |
4917 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
4918 | vcpu->guest_xcr0_loaded = 0; | |
4919 | } | |
4920 | } | |
4921 | ||
851ba692 | 4922 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
4923 | { |
4924 | int r; | |
6a8b1d13 | 4925 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 4926 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 4927 | |
3e007509 | 4928 | if (vcpu->requests) { |
a8eeb04a | 4929 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 4930 | kvm_mmu_unload(vcpu); |
a8eeb04a | 4931 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 4932 | __kvm_migrate_timers(vcpu); |
8cfdc000 ZA |
4933 | if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) { |
4934 | r = kvm_write_guest_time(vcpu); | |
4935 | if (unlikely(r)) | |
4936 | goto out; | |
4937 | } | |
a8eeb04a | 4938 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 4939 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 4940 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
d4acf7e7 | 4941 | kvm_x86_ops->tlb_flush(vcpu); |
a8eeb04a | 4942 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 4943 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
4944 | r = 0; |
4945 | goto out; | |
4946 | } | |
a8eeb04a | 4947 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 4948 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
4949 | r = 0; |
4950 | goto out; | |
4951 | } | |
a8eeb04a | 4952 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
4953 | vcpu->fpu_active = 0; |
4954 | kvm_x86_ops->fpu_deactivate(vcpu); | |
4955 | } | |
2f52d58c | 4956 | } |
b93463aa | 4957 | |
3e007509 AK |
4958 | r = kvm_mmu_reload(vcpu); |
4959 | if (unlikely(r)) | |
4960 | goto out; | |
4961 | ||
b6c7a5dc HB |
4962 | preempt_disable(); |
4963 | ||
4964 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
4965 | if (vcpu->fpu_active) |
4966 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 4967 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 4968 | |
d94e1dc9 AK |
4969 | atomic_set(&vcpu->guest_mode, 1); |
4970 | smp_wmb(); | |
b6c7a5dc | 4971 | |
d94e1dc9 | 4972 | local_irq_disable(); |
32f88400 | 4973 | |
d94e1dc9 AK |
4974 | if (!atomic_read(&vcpu->guest_mode) || vcpu->requests |
4975 | || need_resched() || signal_pending(current)) { | |
4976 | atomic_set(&vcpu->guest_mode, 0); | |
4977 | smp_wmb(); | |
6c142801 AK |
4978 | local_irq_enable(); |
4979 | preempt_enable(); | |
4980 | r = 1; | |
4981 | goto out; | |
4982 | } | |
4983 | ||
851ba692 | 4984 | inject_pending_event(vcpu); |
b6c7a5dc | 4985 | |
6a8b1d13 GN |
4986 | /* enable NMI/IRQ window open exits if needed */ |
4987 | if (vcpu->arch.nmi_pending) | |
4988 | kvm_x86_ops->enable_nmi_window(vcpu); | |
4989 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
4990 | kvm_x86_ops->enable_irq_window(vcpu); | |
4991 | ||
95ba8273 | 4992 | if (kvm_lapic_enabled(vcpu)) { |
8db3baa2 GN |
4993 | update_cr8_intercept(vcpu); |
4994 | kvm_lapic_sync_to_vapic(vcpu); | |
95ba8273 | 4995 | } |
b93463aa | 4996 | |
f656ce01 | 4997 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 4998 | |
b6c7a5dc HB |
4999 | kvm_guest_enter(); |
5000 | ||
42dbaa5a | 5001 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
5002 | set_debugreg(0, 7); |
5003 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5004 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5005 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5006 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
5007 | } | |
b6c7a5dc | 5008 | |
229456fc | 5009 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 5010 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 5011 | |
24f1e32c FW |
5012 | /* |
5013 | * If the guest has used debug registers, at least dr7 | |
5014 | * will be disabled while returning to the host. | |
5015 | * If we don't have active breakpoints in the host, we don't | |
5016 | * care about the messed up debug address registers. But if | |
5017 | * we have some of them active, restore the old state. | |
5018 | */ | |
59d8eb53 | 5019 | if (hw_breakpoint_active()) |
24f1e32c | 5020 | hw_breakpoint_restore(); |
42dbaa5a | 5021 | |
1d5f066e ZA |
5022 | kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc); |
5023 | ||
d94e1dc9 AK |
5024 | atomic_set(&vcpu->guest_mode, 0); |
5025 | smp_wmb(); | |
b6c7a5dc HB |
5026 | local_irq_enable(); |
5027 | ||
5028 | ++vcpu->stat.exits; | |
5029 | ||
5030 | /* | |
5031 | * We must have an instruction between local_irq_enable() and | |
5032 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
5033 | * the interrupt shadow. The stat.exits increment will do nicely. | |
5034 | * But we need to prevent reordering, hence this barrier(): | |
5035 | */ | |
5036 | barrier(); | |
5037 | ||
5038 | kvm_guest_exit(); | |
5039 | ||
5040 | preempt_enable(); | |
5041 | ||
f656ce01 | 5042 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 5043 | |
b6c7a5dc HB |
5044 | /* |
5045 | * Profile KVM exit RIPs: | |
5046 | */ | |
5047 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
5048 | unsigned long rip = kvm_rip_read(vcpu); |
5049 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
5050 | } |
5051 | ||
298101da | 5052 | |
b93463aa AK |
5053 | kvm_lapic_sync_from_vapic(vcpu); |
5054 | ||
851ba692 | 5055 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
5056 | out: |
5057 | return r; | |
5058 | } | |
b6c7a5dc | 5059 | |
09cec754 | 5060 | |
851ba692 | 5061 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
5062 | { |
5063 | int r; | |
f656ce01 | 5064 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
5065 | |
5066 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
5067 | pr_debug("vcpu %d received sipi with vector # %x\n", |
5068 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 5069 | kvm_lapic_reset(vcpu); |
5f179287 | 5070 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
5071 | if (r) |
5072 | return r; | |
5073 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
5074 | } |
5075 | ||
f656ce01 | 5076 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
5077 | vapic_enter(vcpu); |
5078 | ||
5079 | r = 1; | |
5080 | while (r > 0) { | |
af2152f5 | 5081 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
851ba692 | 5082 | r = vcpu_enter_guest(vcpu); |
d7690175 | 5083 | else { |
f656ce01 | 5084 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 5085 | kvm_vcpu_block(vcpu); |
f656ce01 | 5086 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
a8eeb04a | 5087 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
09cec754 GN |
5088 | { |
5089 | switch(vcpu->arch.mp_state) { | |
5090 | case KVM_MP_STATE_HALTED: | |
d7690175 | 5091 | vcpu->arch.mp_state = |
09cec754 GN |
5092 | KVM_MP_STATE_RUNNABLE; |
5093 | case KVM_MP_STATE_RUNNABLE: | |
5094 | break; | |
5095 | case KVM_MP_STATE_SIPI_RECEIVED: | |
5096 | default: | |
5097 | r = -EINTR; | |
5098 | break; | |
5099 | } | |
5100 | } | |
d7690175 MT |
5101 | } |
5102 | ||
09cec754 GN |
5103 | if (r <= 0) |
5104 | break; | |
5105 | ||
5106 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
5107 | if (kvm_cpu_has_pending_timer(vcpu)) | |
5108 | kvm_inject_pending_timer_irqs(vcpu); | |
5109 | ||
851ba692 | 5110 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 5111 | r = -EINTR; |
851ba692 | 5112 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5113 | ++vcpu->stat.request_irq_exits; |
5114 | } | |
5115 | if (signal_pending(current)) { | |
5116 | r = -EINTR; | |
851ba692 | 5117 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
5118 | ++vcpu->stat.signal_exits; |
5119 | } | |
5120 | if (need_resched()) { | |
f656ce01 | 5121 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 5122 | kvm_resched(vcpu); |
f656ce01 | 5123 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 5124 | } |
b6c7a5dc HB |
5125 | } |
5126 | ||
f656ce01 | 5127 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc | 5128 | |
b93463aa AK |
5129 | vapic_exit(vcpu); |
5130 | ||
b6c7a5dc HB |
5131 | return r; |
5132 | } | |
5133 | ||
5134 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
5135 | { | |
5136 | int r; | |
5137 | sigset_t sigsaved; | |
5138 | ||
ac9f6dc0 AK |
5139 | if (vcpu->sigset_active) |
5140 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
5141 | ||
a4535290 | 5142 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 5143 | kvm_vcpu_block(vcpu); |
d7690175 | 5144 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
5145 | r = -EAGAIN; |
5146 | goto out; | |
b6c7a5dc HB |
5147 | } |
5148 | ||
b6c7a5dc HB |
5149 | /* re-sync apic's tpr */ |
5150 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 5151 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 5152 | |
d2ddd1c4 | 5153 | if (vcpu->arch.pio.count || vcpu->mmio_needed) { |
92bf9748 GN |
5154 | if (vcpu->mmio_needed) { |
5155 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
5156 | vcpu->mmio_read_completed = 1; | |
5157 | vcpu->mmio_needed = 0; | |
b6c7a5dc | 5158 | } |
f656ce01 | 5159 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
5cd21917 | 5160 | r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE); |
f656ce01 | 5161 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6d77dbfc | 5162 | if (r != EMULATE_DONE) { |
b6c7a5dc HB |
5163 | r = 0; |
5164 | goto out; | |
5165 | } | |
5166 | } | |
5fdbf976 MT |
5167 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
5168 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
5169 | kvm_run->hypercall.ret); | |
b6c7a5dc | 5170 | |
851ba692 | 5171 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
5172 | |
5173 | out: | |
f1d86e46 | 5174 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
5175 | if (vcpu->sigset_active) |
5176 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
5177 | ||
b6c7a5dc HB |
5178 | return r; |
5179 | } | |
5180 | ||
5181 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5182 | { | |
5fdbf976 MT |
5183 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5184 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5185 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5186 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5187 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5188 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
5189 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
5190 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 5191 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5192 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
5193 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
5194 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
5195 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
5196 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
5197 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
5198 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
5199 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
5200 | #endif |
5201 | ||
5fdbf976 | 5202 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 5203 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 5204 | |
b6c7a5dc HB |
5205 | return 0; |
5206 | } | |
5207 | ||
5208 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
5209 | { | |
5fdbf976 MT |
5210 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
5211 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
5212 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
5213 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
5214 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
5215 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
5216 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
5217 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 5218 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
5219 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
5220 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
5221 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
5222 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
5223 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
5224 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
5225 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
5226 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
5227 | #endif |
5228 | ||
5fdbf976 | 5229 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 5230 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 5231 | |
b4f14abd JK |
5232 | vcpu->arch.exception.pending = false; |
5233 | ||
b6c7a5dc HB |
5234 | return 0; |
5235 | } | |
5236 | ||
b6c7a5dc HB |
5237 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
5238 | { | |
5239 | struct kvm_segment cs; | |
5240 | ||
3e6e0aab | 5241 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
5242 | *db = cs.db; |
5243 | *l = cs.l; | |
5244 | } | |
5245 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
5246 | ||
5247 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
5248 | struct kvm_sregs *sregs) | |
5249 | { | |
89a27f4d | 5250 | struct desc_ptr dt; |
b6c7a5dc | 5251 | |
3e6e0aab GT |
5252 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5253 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5254 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5255 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5256 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5257 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5258 | |
3e6e0aab GT |
5259 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5260 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
5261 | |
5262 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
5263 | sregs->idt.limit = dt.size; |
5264 | sregs->idt.base = dt.address; | |
b6c7a5dc | 5265 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
5266 | sregs->gdt.limit = dt.size; |
5267 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 5268 | |
4d4ec087 | 5269 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c ZX |
5270 | sregs->cr2 = vcpu->arch.cr2; |
5271 | sregs->cr3 = vcpu->arch.cr3; | |
fc78f519 | 5272 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 5273 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 5274 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
5275 | sregs->apic_base = kvm_get_apic_base(vcpu); |
5276 | ||
923c61bb | 5277 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 5278 | |
36752c9b | 5279 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
5280 | set_bit(vcpu->arch.interrupt.nr, |
5281 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 5282 | |
b6c7a5dc HB |
5283 | return 0; |
5284 | } | |
5285 | ||
62d9f0db MT |
5286 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
5287 | struct kvm_mp_state *mp_state) | |
5288 | { | |
62d9f0db | 5289 | mp_state->mp_state = vcpu->arch.mp_state; |
62d9f0db MT |
5290 | return 0; |
5291 | } | |
5292 | ||
5293 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
5294 | struct kvm_mp_state *mp_state) | |
5295 | { | |
62d9f0db | 5296 | vcpu->arch.mp_state = mp_state->mp_state; |
62d9f0db MT |
5297 | return 0; |
5298 | } | |
5299 | ||
e269fb21 JK |
5300 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason, |
5301 | bool has_error_code, u32 error_code) | |
b6c7a5dc | 5302 | { |
4d2179e1 | 5303 | struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode; |
8ec4722d | 5304 | int ret; |
e01c2426 | 5305 | |
8ec4722d | 5306 | init_emulate_ctxt(vcpu); |
c697518a | 5307 | |
9aabc88f | 5308 | ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, |
e269fb21 JK |
5309 | tss_selector, reason, has_error_code, |
5310 | error_code); | |
c697518a | 5311 | |
c697518a | 5312 | if (ret) |
19d04437 | 5313 | return EMULATE_FAIL; |
37817f29 | 5314 | |
4d2179e1 | 5315 | memcpy(vcpu->arch.regs, c->regs, sizeof c->regs); |
95c55886 | 5316 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip); |
19d04437 GN |
5317 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
5318 | return EMULATE_DONE; | |
37817f29 IE |
5319 | } |
5320 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5321 | ||
b6c7a5dc HB |
5322 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5323 | struct kvm_sregs *sregs) | |
5324 | { | |
5325 | int mmu_reset_needed = 0; | |
923c61bb | 5326 | int pending_vec, max_bits; |
89a27f4d | 5327 | struct desc_ptr dt; |
b6c7a5dc | 5328 | |
89a27f4d GN |
5329 | dt.size = sregs->idt.limit; |
5330 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5331 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5332 | dt.size = sregs->gdt.limit; |
5333 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5334 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5335 | ||
ad312c7c ZX |
5336 | vcpu->arch.cr2 = sregs->cr2; |
5337 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
dc7e795e | 5338 | vcpu->arch.cr3 = sregs->cr3; |
b6c7a5dc | 5339 | |
2d3ad1f4 | 5340 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5341 | |
f6801dff | 5342 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5343 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5344 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5345 | ||
4d4ec087 | 5346 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5347 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5348 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5349 | |
fc78f519 | 5350 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5351 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
7c93be44 | 5352 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
ad312c7c | 5353 | load_pdptrs(vcpu, vcpu->arch.cr3); |
7c93be44 MT |
5354 | mmu_reset_needed = 1; |
5355 | } | |
b6c7a5dc HB |
5356 | |
5357 | if (mmu_reset_needed) | |
5358 | kvm_mmu_reset_context(vcpu); | |
5359 | ||
923c61bb GN |
5360 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5361 | pending_vec = find_first_bit( | |
5362 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5363 | if (pending_vec < max_bits) { | |
66fd3f7f | 5364 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb GN |
5365 | pr_debug("Set back pending irq %d\n", pending_vec); |
5366 | if (irqchip_in_kernel(vcpu->kvm)) | |
5367 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
b6c7a5dc HB |
5368 | } |
5369 | ||
3e6e0aab GT |
5370 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5371 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5372 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5373 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5374 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5375 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5376 | |
3e6e0aab GT |
5377 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5378 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5379 | |
5f0269f5 ME |
5380 | update_cr8_intercept(vcpu); |
5381 | ||
9c3e4aab | 5382 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5383 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5384 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5385 | !is_protmode(vcpu)) |
9c3e4aab MT |
5386 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5387 | ||
b6c7a5dc HB |
5388 | return 0; |
5389 | } | |
5390 | ||
d0bfb940 JK |
5391 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5392 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5393 | { |
355be0b9 | 5394 | unsigned long rflags; |
ae675ef0 | 5395 | int i, r; |
b6c7a5dc | 5396 | |
4f926bf2 JK |
5397 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5398 | r = -EBUSY; | |
5399 | if (vcpu->arch.exception.pending) | |
2122ff5e | 5400 | goto out; |
4f926bf2 JK |
5401 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
5402 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5403 | else | |
5404 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5405 | } | |
5406 | ||
91586a3b JK |
5407 | /* |
5408 | * Read rflags as long as potentially injected trace flags are still | |
5409 | * filtered out. | |
5410 | */ | |
5411 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5412 | |
5413 | vcpu->guest_debug = dbg->control; | |
5414 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5415 | vcpu->guest_debug = 0; | |
5416 | ||
5417 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5418 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5419 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5420 | vcpu->arch.switch_db_regs = | |
5421 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5422 | } else { | |
5423 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5424 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5425 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5426 | } | |
5427 | ||
f92653ee JK |
5428 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5429 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5430 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5431 | |
91586a3b JK |
5432 | /* |
5433 | * Trigger an rflags update that will inject or remove the trace | |
5434 | * flags. | |
5435 | */ | |
5436 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5437 | |
355be0b9 | 5438 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5439 | |
4f926bf2 | 5440 | r = 0; |
d0bfb940 | 5441 | |
2122ff5e | 5442 | out: |
b6c7a5dc HB |
5443 | |
5444 | return r; | |
5445 | } | |
5446 | ||
8b006791 ZX |
5447 | /* |
5448 | * Translate a guest virtual address to a guest physical address. | |
5449 | */ | |
5450 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5451 | struct kvm_translation *tr) | |
5452 | { | |
5453 | unsigned long vaddr = tr->linear_address; | |
5454 | gpa_t gpa; | |
f656ce01 | 5455 | int idx; |
8b006791 | 5456 | |
f656ce01 | 5457 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5458 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5459 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5460 | tr->physical_address = gpa; |
5461 | tr->valid = gpa != UNMAPPED_GVA; | |
5462 | tr->writeable = 1; | |
5463 | tr->usermode = 0; | |
8b006791 ZX |
5464 | |
5465 | return 0; | |
5466 | } | |
5467 | ||
d0752060 HB |
5468 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5469 | { | |
98918833 SY |
5470 | struct i387_fxsave_struct *fxsave = |
5471 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5472 | |
d0752060 HB |
5473 | memcpy(fpu->fpr, fxsave->st_space, 128); |
5474 | fpu->fcw = fxsave->cwd; | |
5475 | fpu->fsw = fxsave->swd; | |
5476 | fpu->ftwx = fxsave->twd; | |
5477 | fpu->last_opcode = fxsave->fop; | |
5478 | fpu->last_ip = fxsave->rip; | |
5479 | fpu->last_dp = fxsave->rdp; | |
5480 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5481 | ||
d0752060 HB |
5482 | return 0; |
5483 | } | |
5484 | ||
5485 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5486 | { | |
98918833 SY |
5487 | struct i387_fxsave_struct *fxsave = |
5488 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 5489 | |
d0752060 HB |
5490 | memcpy(fxsave->st_space, fpu->fpr, 128); |
5491 | fxsave->cwd = fpu->fcw; | |
5492 | fxsave->swd = fpu->fsw; | |
5493 | fxsave->twd = fpu->ftwx; | |
5494 | fxsave->fop = fpu->last_opcode; | |
5495 | fxsave->rip = fpu->last_ip; | |
5496 | fxsave->rdp = fpu->last_dp; | |
5497 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5498 | ||
d0752060 HB |
5499 | return 0; |
5500 | } | |
5501 | ||
10ab25cd | 5502 | int fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 5503 | { |
10ab25cd JK |
5504 | int err; |
5505 | ||
5506 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
5507 | if (err) | |
5508 | return err; | |
5509 | ||
98918833 | 5510 | fpu_finit(&vcpu->arch.guest_fpu); |
d0752060 | 5511 | |
2acf923e DC |
5512 | /* |
5513 | * Ensure guest xcr0 is valid for loading | |
5514 | */ | |
5515 | vcpu->arch.xcr0 = XSTATE_FP; | |
5516 | ||
ad312c7c | 5517 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
5518 | |
5519 | return 0; | |
d0752060 HB |
5520 | } |
5521 | EXPORT_SYMBOL_GPL(fx_init); | |
5522 | ||
98918833 SY |
5523 | static void fx_free(struct kvm_vcpu *vcpu) |
5524 | { | |
5525 | fpu_free(&vcpu->arch.guest_fpu); | |
5526 | } | |
5527 | ||
d0752060 HB |
5528 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
5529 | { | |
2608d7a1 | 5530 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5531 | return; |
5532 | ||
2acf923e DC |
5533 | /* |
5534 | * Restore all possible states in the guest, | |
5535 | * and assume host would use all available bits. | |
5536 | * Guest xcr0 would be loaded later. | |
5537 | */ | |
5538 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 5539 | vcpu->guest_fpu_loaded = 1; |
7cf30855 | 5540 | unlazy_fpu(current); |
98918833 | 5541 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 5542 | trace_kvm_fpu(1); |
d0752060 | 5543 | } |
d0752060 HB |
5544 | |
5545 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5546 | { | |
2acf923e DC |
5547 | kvm_put_guest_xcr0(vcpu); |
5548 | ||
d0752060 HB |
5549 | if (!vcpu->guest_fpu_loaded) |
5550 | return; | |
5551 | ||
5552 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 5553 | fpu_save_init(&vcpu->arch.guest_fpu); |
f096ed85 | 5554 | ++vcpu->stat.fpu_reload; |
a8eeb04a | 5555 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); |
0c04851c | 5556 | trace_kvm_fpu(0); |
d0752060 | 5557 | } |
e9b11c17 ZX |
5558 | |
5559 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5560 | { | |
7f1ea208 JR |
5561 | if (vcpu->arch.time_page) { |
5562 | kvm_release_page_dirty(vcpu->arch.time_page); | |
5563 | vcpu->arch.time_page = NULL; | |
5564 | } | |
5565 | ||
f5f48ee1 | 5566 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 5567 | fx_free(vcpu); |
e9b11c17 ZX |
5568 | kvm_x86_ops->vcpu_free(vcpu); |
5569 | } | |
5570 | ||
5571 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5572 | unsigned int id) | |
5573 | { | |
6755bae8 ZA |
5574 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
5575 | printk_once(KERN_WARNING | |
5576 | "kvm: SMP vm created on host with unstable TSC; " | |
5577 | "guest TSC will not be reliable\n"); | |
26e5215f AK |
5578 | return kvm_x86_ops->vcpu_create(kvm, id); |
5579 | } | |
e9b11c17 | 5580 | |
26e5215f AK |
5581 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5582 | { | |
5583 | int r; | |
e9b11c17 | 5584 | |
0bed3b56 | 5585 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5586 | vcpu_load(vcpu); |
5587 | r = kvm_arch_vcpu_reset(vcpu); | |
5588 | if (r == 0) | |
5589 | r = kvm_mmu_setup(vcpu); | |
5590 | vcpu_put(vcpu); | |
5591 | if (r < 0) | |
5592 | goto free_vcpu; | |
5593 | ||
26e5215f | 5594 | return 0; |
e9b11c17 ZX |
5595 | free_vcpu: |
5596 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 5597 | return r; |
e9b11c17 ZX |
5598 | } |
5599 | ||
d40ccc62 | 5600 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
5601 | { |
5602 | vcpu_load(vcpu); | |
5603 | kvm_mmu_unload(vcpu); | |
5604 | vcpu_put(vcpu); | |
5605 | ||
98918833 | 5606 | fx_free(vcpu); |
e9b11c17 ZX |
5607 | kvm_x86_ops->vcpu_free(vcpu); |
5608 | } | |
5609 | ||
5610 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
5611 | { | |
448fa4a9 JK |
5612 | vcpu->arch.nmi_pending = false; |
5613 | vcpu->arch.nmi_injected = false; | |
5614 | ||
42dbaa5a JK |
5615 | vcpu->arch.switch_db_regs = 0; |
5616 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
5617 | vcpu->arch.dr6 = DR6_FIXED_1; | |
5618 | vcpu->arch.dr7 = DR7_FIXED_1; | |
5619 | ||
e9b11c17 ZX |
5620 | return kvm_x86_ops->vcpu_reset(vcpu); |
5621 | } | |
5622 | ||
10474ae8 | 5623 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 5624 | { |
ca84d1a2 ZA |
5625 | struct kvm *kvm; |
5626 | struct kvm_vcpu *vcpu; | |
5627 | int i; | |
5628 | ||
18863bdd | 5629 | kvm_shared_msr_cpu_online(); |
ca84d1a2 ZA |
5630 | list_for_each_entry(kvm, &vm_list, vm_list) |
5631 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5632 | if (vcpu->cpu == smp_processor_id()) | |
5633 | kvm_request_guest_time_update(vcpu); | |
10474ae8 | 5634 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5635 | } |
5636 | ||
5637 | void kvm_arch_hardware_disable(void *garbage) | |
5638 | { | |
5639 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 5640 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
5641 | } |
5642 | ||
5643 | int kvm_arch_hardware_setup(void) | |
5644 | { | |
5645 | return kvm_x86_ops->hardware_setup(); | |
5646 | } | |
5647 | ||
5648 | void kvm_arch_hardware_unsetup(void) | |
5649 | { | |
5650 | kvm_x86_ops->hardware_unsetup(); | |
5651 | } | |
5652 | ||
5653 | void kvm_arch_check_processor_compat(void *rtn) | |
5654 | { | |
5655 | kvm_x86_ops->check_processor_compatibility(rtn); | |
5656 | } | |
5657 | ||
5658 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
5659 | { | |
5660 | struct page *page; | |
5661 | struct kvm *kvm; | |
5662 | int r; | |
5663 | ||
5664 | BUG_ON(vcpu->kvm == NULL); | |
5665 | kvm = vcpu->kvm; | |
5666 | ||
9aabc88f | 5667 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
14dfe855 | 5668 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
ad312c7c | 5669 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c30a358d | 5670 | vcpu->arch.mmu.translate_gpa = translate_gpa; |
c5af89b6 | 5671 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 5672 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 5673 | else |
a4535290 | 5674 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
5675 | |
5676 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
5677 | if (!page) { | |
5678 | r = -ENOMEM; | |
5679 | goto fail; | |
5680 | } | |
ad312c7c | 5681 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
5682 | |
5683 | r = kvm_mmu_create(vcpu); | |
5684 | if (r < 0) | |
5685 | goto fail_free_pio_data; | |
5686 | ||
5687 | if (irqchip_in_kernel(kvm)) { | |
5688 | r = kvm_create_lapic(vcpu); | |
5689 | if (r < 0) | |
5690 | goto fail_mmu_destroy; | |
5691 | } | |
5692 | ||
890ca9ae HY |
5693 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
5694 | GFP_KERNEL); | |
5695 | if (!vcpu->arch.mce_banks) { | |
5696 | r = -ENOMEM; | |
443c39bc | 5697 | goto fail_free_lapic; |
890ca9ae HY |
5698 | } |
5699 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
5700 | ||
f5f48ee1 SY |
5701 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) |
5702 | goto fail_free_mce_banks; | |
5703 | ||
e9b11c17 | 5704 | return 0; |
f5f48ee1 SY |
5705 | fail_free_mce_banks: |
5706 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
5707 | fail_free_lapic: |
5708 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
5709 | fail_mmu_destroy: |
5710 | kvm_mmu_destroy(vcpu); | |
5711 | fail_free_pio_data: | |
ad312c7c | 5712 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
5713 | fail: |
5714 | return r; | |
5715 | } | |
5716 | ||
5717 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
5718 | { | |
f656ce01 MT |
5719 | int idx; |
5720 | ||
36cb93fd | 5721 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 5722 | kvm_free_lapic(vcpu); |
f656ce01 | 5723 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 5724 | kvm_mmu_destroy(vcpu); |
f656ce01 | 5725 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 5726 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 5727 | } |
d19a9cd2 ZX |
5728 | |
5729 | struct kvm *kvm_arch_create_vm(void) | |
5730 | { | |
5731 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
5732 | ||
5733 | if (!kvm) | |
5734 | return ERR_PTR(-ENOMEM); | |
5735 | ||
f05e70ac | 5736 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 5737 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 5738 | |
5550af4d SY |
5739 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
5740 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
5741 | ||
99e3e30a ZA |
5742 | spin_lock_init(&kvm->arch.tsc_write_lock); |
5743 | ||
d19a9cd2 ZX |
5744 | return kvm; |
5745 | } | |
5746 | ||
5747 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
5748 | { | |
5749 | vcpu_load(vcpu); | |
5750 | kvm_mmu_unload(vcpu); | |
5751 | vcpu_put(vcpu); | |
5752 | } | |
5753 | ||
5754 | static void kvm_free_vcpus(struct kvm *kvm) | |
5755 | { | |
5756 | unsigned int i; | |
988a2cae | 5757 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
5758 | |
5759 | /* | |
5760 | * Unpin any mmu pages first. | |
5761 | */ | |
988a2cae GN |
5762 | kvm_for_each_vcpu(i, vcpu, kvm) |
5763 | kvm_unload_vcpu_mmu(vcpu); | |
5764 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5765 | kvm_arch_vcpu_free(vcpu); | |
5766 | ||
5767 | mutex_lock(&kvm->lock); | |
5768 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
5769 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 5770 | |
988a2cae GN |
5771 | atomic_set(&kvm->online_vcpus, 0); |
5772 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
5773 | } |
5774 | ||
ad8ba2cd SY |
5775 | void kvm_arch_sync_events(struct kvm *kvm) |
5776 | { | |
ba4cef31 | 5777 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 5778 | kvm_free_pit(kvm); |
ad8ba2cd SY |
5779 | } |
5780 | ||
d19a9cd2 ZX |
5781 | void kvm_arch_destroy_vm(struct kvm *kvm) |
5782 | { | |
6eb55818 | 5783 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
5784 | kfree(kvm->arch.vpic); |
5785 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
5786 | kvm_free_vcpus(kvm); |
5787 | kvm_free_physmem(kvm); | |
3d45830c AK |
5788 | if (kvm->arch.apic_access_page) |
5789 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
5790 | if (kvm->arch.ept_identity_pagetable) |
5791 | put_page(kvm->arch.ept_identity_pagetable); | |
64749204 | 5792 | cleanup_srcu_struct(&kvm->srcu); |
d19a9cd2 ZX |
5793 | kfree(kvm); |
5794 | } | |
0de10343 | 5795 | |
f7784b8e MT |
5796 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
5797 | struct kvm_memory_slot *memslot, | |
0de10343 | 5798 | struct kvm_memory_slot old, |
f7784b8e | 5799 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
5800 | int user_alloc) |
5801 | { | |
f7784b8e | 5802 | int npages = memslot->npages; |
7ac77099 AK |
5803 | int map_flags = MAP_PRIVATE | MAP_ANONYMOUS; |
5804 | ||
5805 | /* Prevent internal slot pages from being moved by fork()/COW. */ | |
5806 | if (memslot->id >= KVM_MEMORY_SLOTS) | |
5807 | map_flags = MAP_SHARED | MAP_ANONYMOUS; | |
0de10343 ZX |
5808 | |
5809 | /*To keep backward compatibility with older userspace, | |
5810 | *x86 needs to hanlde !user_alloc case. | |
5811 | */ | |
5812 | if (!user_alloc) { | |
5813 | if (npages && !old.rmap) { | |
604b38ac AA |
5814 | unsigned long userspace_addr; |
5815 | ||
72dc67a6 | 5816 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
5817 | userspace_addr = do_mmap(NULL, 0, |
5818 | npages * PAGE_SIZE, | |
5819 | PROT_READ | PROT_WRITE, | |
7ac77099 | 5820 | map_flags, |
604b38ac | 5821 | 0); |
72dc67a6 | 5822 | up_write(¤t->mm->mmap_sem); |
0de10343 | 5823 | |
604b38ac AA |
5824 | if (IS_ERR((void *)userspace_addr)) |
5825 | return PTR_ERR((void *)userspace_addr); | |
5826 | ||
604b38ac | 5827 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
5828 | } |
5829 | } | |
5830 | ||
f7784b8e MT |
5831 | |
5832 | return 0; | |
5833 | } | |
5834 | ||
5835 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
5836 | struct kvm_userspace_memory_region *mem, | |
5837 | struct kvm_memory_slot old, | |
5838 | int user_alloc) | |
5839 | { | |
5840 | ||
5841 | int npages = mem->memory_size >> PAGE_SHIFT; | |
5842 | ||
5843 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
5844 | int ret; | |
5845 | ||
5846 | down_write(¤t->mm->mmap_sem); | |
5847 | ret = do_munmap(current->mm, old.userspace_addr, | |
5848 | old.npages * PAGE_SIZE); | |
5849 | up_write(¤t->mm->mmap_sem); | |
5850 | if (ret < 0) | |
5851 | printk(KERN_WARNING | |
5852 | "kvm_vm_ioctl_set_memory_region: " | |
5853 | "failed to munmap memory\n"); | |
5854 | } | |
5855 | ||
7c8a83b7 | 5856 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 5857 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
5858 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
5859 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
5860 | } | |
5861 | ||
5862 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 5863 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 5864 | } |
1d737c8a | 5865 | |
34d4cb8f MT |
5866 | void kvm_arch_flush_shadow(struct kvm *kvm) |
5867 | { | |
5868 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 5869 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
5870 | } |
5871 | ||
1d737c8a ZX |
5872 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
5873 | { | |
a4535290 | 5874 | return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE |
a1b37100 GN |
5875 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
5876 | || vcpu->arch.nmi_pending || | |
5877 | (kvm_arch_interrupt_allowed(vcpu) && | |
5878 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 5879 | } |
5736199a | 5880 | |
5736199a ZX |
5881 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
5882 | { | |
32f88400 MT |
5883 | int me; |
5884 | int cpu = vcpu->cpu; | |
5736199a ZX |
5885 | |
5886 | if (waitqueue_active(&vcpu->wq)) { | |
5887 | wake_up_interruptible(&vcpu->wq); | |
5888 | ++vcpu->stat.halt_wakeup; | |
5889 | } | |
32f88400 MT |
5890 | |
5891 | me = get_cpu(); | |
5892 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
d94e1dc9 | 5893 | if (atomic_xchg(&vcpu->guest_mode, 0)) |
32f88400 | 5894 | smp_send_reschedule(cpu); |
e9571ed5 | 5895 | put_cpu(); |
5736199a | 5896 | } |
78646121 GN |
5897 | |
5898 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
5899 | { | |
5900 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
5901 | } | |
229456fc | 5902 | |
f92653ee JK |
5903 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
5904 | { | |
5905 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
5906 | get_segment_base(vcpu, VCPU_SREG_CS); | |
5907 | ||
5908 | return current_rip == linear_rip; | |
5909 | } | |
5910 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
5911 | ||
94fe45da JK |
5912 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
5913 | { | |
5914 | unsigned long rflags; | |
5915 | ||
5916 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
5917 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 5918 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
5919 | return rflags; |
5920 | } | |
5921 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
5922 | ||
5923 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
5924 | { | |
5925 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 5926 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 5927 | rflags |= X86_EFLAGS_TF; |
94fe45da JK |
5928 | kvm_x86_ops->set_rflags(vcpu, rflags); |
5929 | } | |
5930 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
5931 | ||
229456fc MT |
5932 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
5933 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
5934 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
5935 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
5936 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 5937 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 5938 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 5939 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 5940 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 5941 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 5942 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 5943 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |