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KVM: fix "Should it be static?" warnings from sparse
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
92a1f12d
JR		 102bool kvm_has_tsc_control;
103EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104u32 kvm_max_guest_tsc_khz;
105EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
cc578287
ZA		 107/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108static u32 tsc_tolerance_ppm = 250;
109module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
d0659d94
MT		 111/* lapic timer advance (tscdeadline mode only) in nanoseconds */
112unsigned int lapic_timer_advance_ns = 0;
113module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
16a96021
MT		 115static bool backwards_tsc_observed = false;
116
18863bdd
AK		 117#define KVM_NR_SHARED_MSRS 16
118
119struct kvm_shared_msrs_global {
120 int nr;
2bf78fa7 121 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 122};
123
124struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
2bf78fa7
SY		 127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 131};
132
133static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 134static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 135
417bc304 136struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 147 { "halt_exits", VCPU_STAT(halt_exits) },
148 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 149 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 150 { "request_irq", VCPU_STAT(request_irq_exits) },
151 { "irq_exits", VCPU_STAT(irq_exits) },
152 { "host_state_reload", VCPU_STAT(host_state_reload) },
153 { "efer_reload", VCPU_STAT(efer_reload) },
154 { "fpu_reload", VCPU_STAT(fpu_reload) },
155 { "insn_emulation", VCPU_STAT(insn_emulation) },
156 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 157 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 158 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 159 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
160 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
161 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
162 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
163 { "mmu_flooded", VM_STAT(mmu_flooded) },
164 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 165 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 166 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 167 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 168 { "largepages", VM_STAT(lpages) },
417bc304
HB		 169 { NULL }
170};
171
2acf923e
DC		 172u64 __read_mostly host_xcr0;
173
b6785def 174static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 175
af585b92
GN		 176static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
177{
178 int i;
179 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
180 vcpu->arch.apf.gfns[i] = ~0;
181}
182
18863bdd
AK		 183static void kvm_on_user_return(struct user_return_notifier *urn)
184{
185 unsigned slot;
18863bdd
AK		 186 struct kvm_shared_msrs *locals
187 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 188 struct kvm_shared_msr_values *values;
18863bdd
AK		 189
190 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 191 values = &locals->values[slot];
192 if (values->host != values->curr) {
193 wrmsrl(shared_msrs_global.msrs[slot], values->host);
194 values->curr = values->host;
18863bdd
AK		 195 }
196 }
197 locals->registered = false;
198 user_return_notifier_unregister(urn);
199}
200
2bf78fa7 201static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 202{
18863bdd 203 u64 value;
013f6a5d
MT		 204 unsigned int cpu = smp_processor_id();
205 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 206
2bf78fa7
SY		 207 /* only read, and nobody should modify it at this time,
208 * so don't need lock */
209 if (slot >= shared_msrs_global.nr) {
210 printk(KERN_ERR "kvm: invalid MSR slot!");
211 return;
212 }
213 rdmsrl_safe(msr, &value);
214 smsr->values[slot].host = value;
215 smsr->values[slot].curr = value;
216}
217
218void kvm_define_shared_msr(unsigned slot, u32 msr)
219{
0123be42 220 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 221 if (slot >= shared_msrs_global.nr)
222 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 223 shared_msrs_global.msrs[slot] = msr;
224 /* we need ensured the shared_msr_global have been updated */
225 smp_wmb();
18863bdd
AK		 226}
227EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
228
229static void kvm_shared_msr_cpu_online(void)
230{
231 unsigned i;
18863bdd
AK		 232
233 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 234 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 235}
236
8b3c3104 237int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 238{
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 241 int err;
18863bdd 242
2bf78fa7 243 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 244 return 0;
2bf78fa7 245 smsr->values[slot].curr = value;
8b3c3104
AH		 246 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
247 if (err)
248 return 1;
249
18863bdd
AK		 250 if (!smsr->registered) {
251 smsr->urn.on_user_return = kvm_on_user_return;
252 user_return_notifier_register(&smsr->urn);
253 smsr->registered = true;
254 }
8b3c3104 255 return 0;
18863bdd
AK		 256}
257EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
258
13a34e06 259static void drop_user_return_notifiers(void)
3548bab5 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 263
264 if (smsr->registered)
265 kvm_on_user_return(&smsr->urn);
266}
267
6866b83e
CO		 268u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
269{
8a5a87d9 270 return vcpu->arch.apic_base;
6866b83e
CO		 271}
272EXPORT_SYMBOL_GPL(kvm_get_apic_base);
273
58cb628d
JK		 274int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
275{
276 u64 old_state = vcpu->arch.apic_base &
277 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
278 u64 new_state = msr_info->data &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
281 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
282
283 if (!msr_info->host_initiated &&
284 ((msr_info->data & reserved_bits) != 0 ||
285 new_state == X2APIC_ENABLE ||
286 (new_state == MSR_IA32_APICBASE_ENABLE &&
287 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
288 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
289 old_state == 0)))
290 return 1;
291
292 kvm_lapic_set_base(vcpu, msr_info->data);
293 return 0;
6866b83e
CO		 294}
295EXPORT_SYMBOL_GPL(kvm_set_apic_base);
296
2605fc21 297asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 298{
299 /* Fault while not rebooting. We want the trace. */
300 BUG();
301}
302EXPORT_SYMBOL_GPL(kvm_spurious_fault);
303
3fd28fce
ED		 304#define EXCPT_BENIGN 0
305#define EXCPT_CONTRIBUTORY 1
306#define EXCPT_PF 2
307
308static int exception_class(int vector)
309{
310 switch (vector) {
311 case PF_VECTOR:
312 return EXCPT_PF;
313 case DE_VECTOR:
314 case TS_VECTOR:
315 case NP_VECTOR:
316 case SS_VECTOR:
317 case GP_VECTOR:
318 return EXCPT_CONTRIBUTORY;
319 default:
320 break;
321 }
322 return EXCPT_BENIGN;
323}
324
d6e8c854
NA		 325#define EXCPT_FAULT 0
326#define EXCPT_TRAP 1
327#define EXCPT_ABORT 2
328#define EXCPT_INTERRUPT 3
329
330static int exception_type(int vector)
331{
332 unsigned int mask;
333
334 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
335 return EXCPT_INTERRUPT;
336
337 mask = 1 << vector;
338
339 /* #DB is trap, as instruction watchpoints are handled elsewhere */
340 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
341 return EXCPT_TRAP;
342
343 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
344 return EXCPT_ABORT;
345
346 /* Reserved exceptions will result in fault */
347 return EXCPT_FAULT;
348}
349
3fd28fce 350static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 351 unsigned nr, bool has_error, u32 error_code,
352 bool reinject)
3fd28fce
ED		 353{
354 u32 prev_nr;
355 int class1, class2;
356
3842d135
AK		 357 kvm_make_request(KVM_REQ_EVENT, vcpu);
358
3fd28fce
ED		 359 if (!vcpu->arch.exception.pending) {
360 queue:
3ffb2468
NA		 361 if (has_error && !is_protmode(vcpu))
362 has_error = false;
3fd28fce
ED		 363 vcpu->arch.exception.pending = true;
364 vcpu->arch.exception.has_error_code = has_error;
365 vcpu->arch.exception.nr = nr;
366 vcpu->arch.exception.error_code = error_code;
3f0fd292 367 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 368 return;
369 }
370
371 /* to check exception */
372 prev_nr = vcpu->arch.exception.nr;
373 if (prev_nr == DF_VECTOR) {
374 /* triple fault -> shutdown */
a8eeb04a 375 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 376 return;
377 }
378 class1 = exception_class(prev_nr);
379 class2 = exception_class(nr);
380 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
381 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
382 /* generate double fault per SDM Table 5-5 */
383 vcpu->arch.exception.pending = true;
384 vcpu->arch.exception.has_error_code = true;
385 vcpu->arch.exception.nr = DF_VECTOR;
386 vcpu->arch.exception.error_code = 0;
387 } else
388 /* replace previous exception with a new one in a hope
389 that instruction re-execution will regenerate lost
390 exception */
391 goto queue;
392}
393
298101da
AK		 394void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
395{
ce7ddec4 396 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 397}
398EXPORT_SYMBOL_GPL(kvm_queue_exception);
399
ce7ddec4
JR		 400void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
401{
402 kvm_multiple_exception(vcpu, nr, false, 0, true);
403}
404EXPORT_SYMBOL_GPL(kvm_requeue_exception);
405
db8fcefa 406void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 407{
db8fcefa
AP		 408 if (err)
409 kvm_inject_gp(vcpu, 0);
410 else
411 kvm_x86_ops->skip_emulated_instruction(vcpu);
412}
413EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 414
6389ee94 415void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 416{
417 ++vcpu->stat.pf_guest;
6389ee94
AK		 418 vcpu->arch.cr2 = fault->address;
419 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 420}
27d6c865 421EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 422
ef54bcfe 423static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 424{
6389ee94
AK		 425 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
426 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 427 else
6389ee94 428 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 429
430 return fault->nested_page_fault;
d4f8cf66
JR		 431}
432
3419ffc8
SY		 433void kvm_inject_nmi(struct kvm_vcpu *vcpu)
434{
7460fb4a
AK		 435 atomic_inc(&vcpu->arch.nmi_queued);
436 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 437}
438EXPORT_SYMBOL_GPL(kvm_inject_nmi);
439
298101da
AK		 440void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
441{
ce7ddec4 442 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 443}
444EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
445
ce7ddec4
JR		 446void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
447{
448 kvm_multiple_exception(vcpu, nr, true, error_code, true);
449}
450EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
451
0a79b009
AK		 452/*
453 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
454 * a #GP and return false.
455 */
456bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 457{
0a79b009
AK		 458 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
459 return true;
460 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
461 return false;
298101da 462}
0a79b009 463EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 464
16f8a6f9
NA		 465bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
466{
467 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
468 return true;
469
470 kvm_queue_exception(vcpu, UD_VECTOR);
471 return false;
472}
473EXPORT_SYMBOL_GPL(kvm_require_dr);
474
ec92fe44
JR		 475/*
476 * This function will be used to read from the physical memory of the currently
477 * running guest. The difference to kvm_read_guest_page is that this function
478 * can read from guest physical or from the guest's guest physical memory.
479 */
480int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
481 gfn_t ngfn, void *data, int offset, int len,
482 u32 access)
483{
54987b7a 484 struct x86_exception exception;
ec92fe44
JR		 485 gfn_t real_gfn;
486 gpa_t ngpa;
487
488 ngpa = gfn_to_gpa(ngfn);
54987b7a 489 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 490 if (real_gfn == UNMAPPED_GVA)
491 return -EFAULT;
492
493 real_gfn = gpa_to_gfn(real_gfn);
494
495 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
496}
497EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
498
69b0049a 499static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 500 void *data, int offset, int len, u32 access)
501{
502 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
503 data, offset, len, access);
504}
505
a03490ed
CO		 506/*
507 * Load the pae pdptrs. Return true is they are all valid.
508 */
ff03a073 509int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 510{
511 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
512 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
513 int i;
514 int ret;
ff03a073 515 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 516
ff03a073
JR		 517 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
518 offset * sizeof(u64), sizeof(pdpte),
519 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 520 if (ret < 0) {
521 ret = 0;
522 goto out;
523 }
524 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 525 if (is_present_gpte(pdpte[i]) &&
20c466b5 526 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 527 ret = 0;
528 goto out;
529 }
530 }
531 ret = 1;
532
ff03a073 533 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 534 __set_bit(VCPU_EXREG_PDPTR,
535 (unsigned long *)&vcpu->arch.regs_avail);
536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 538out:
a03490ed
CO		 539
540 return ret;
541}
cc4b6871 542EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 543
d835dfec
AK		 544static bool pdptrs_changed(struct kvm_vcpu *vcpu)
545{
ff03a073 546 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 547 bool changed = true;
3d06b8bf
JR		 548 int offset;
549 gfn_t gfn;
d835dfec
AK		 550 int r;
551
552 if (is_long_mode(vcpu) || !is_pae(vcpu))
553 return false;
554
6de4f3ad
AK		 555 if (!test_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_avail))
557 return true;
558
9f8fe504
AK		 559 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
560 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 561 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
562 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 563 if (r < 0)
564 goto out;
ff03a073 565 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 566out:
d835dfec
AK		 567
568 return changed;
569}
570
49a9b07e 571int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 572{
aad82703
SY		 573 unsigned long old_cr0 = kvm_read_cr0(vcpu);
574 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
575 X86_CR0_CD | X86_CR0_NW;
576
f9a48e6a
AK		 577 cr0 |= X86_CR0_ET;
578
ab344828 579#ifdef CONFIG_X86_64
0f12244f
GN		 580 if (cr0 & 0xffffffff00000000UL)
581 return 1;
ab344828
GN		 582#endif
583
584 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 585
0f12244f
GN		 586 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
587 return 1;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
590 return 1;
a03490ed
CO		 591
592 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
593#ifdef CONFIG_X86_64
f6801dff 594 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 595 int cs_db, cs_l;
596
0f12244f
GN		 597 if (!is_pae(vcpu))
598 return 1;
a03490ed 599 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 600 if (cs_l)
601 return 1;
a03490ed
CO		 602 } else
603#endif
ff03a073 604 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 605 kvm_read_cr3(vcpu)))
0f12244f 606 return 1;
a03490ed
CO		 607 }
608
ad756a16
MJ		 609 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
610 return 1;
611
a03490ed 612 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 613
d170c419 614 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 615 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 616 kvm_async_pf_hash_reset(vcpu);
617 }
e5f3f027 618
aad82703
SY		 619 if ((cr0 ^ old_cr0) & update_bits)
620 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 621 return 0;
622}
2d3ad1f4 623EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 624
2d3ad1f4 625void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 626{
49a9b07e 627 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 630
42bdf991
MT		 631static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
632{
633 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
634 !vcpu->guest_xcr0_loaded) {
635 /* kvm_set_xcr() also depends on this */
636 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
637 vcpu->guest_xcr0_loaded = 1;
638 }
639}
640
641static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
642{
643 if (vcpu->guest_xcr0_loaded) {
644 if (vcpu->arch.xcr0 != host_xcr0)
645 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
646 vcpu->guest_xcr0_loaded = 0;
647 }
648}
649
69b0049a 650static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 651{
56c103ec
LJ		 652 u64 xcr0 = xcr;
653 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 654 u64 valid_bits;
2acf923e
DC		 655
656 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
657 if (index != XCR_XFEATURE_ENABLED_MASK)
658 return 1;
2acf923e
DC		 659 if (!(xcr0 & XSTATE_FP))
660 return 1;
661 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
662 return 1;
46c34cb0
PB		 663
664 /*
665 * Do not allow the guest to set bits that we do not support
666 * saving. However, xcr0 bit 0 is always set, even if the
667 * emulated CPU does not support XSAVE (see fx_init).
668 */
669 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
670 if (xcr0 & ~valid_bits)
2acf923e 671 return 1;
46c34cb0 672
390bd528
LJ		 673 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
674 return 1;
675
612263b3
CP		 676 if (xcr0 & XSTATE_AVX512) {
677 if (!(xcr0 & XSTATE_YMM))
678 return 1;
679 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
680 return 1;
681 }
42bdf991 682 kvm_put_guest_xcr0(vcpu);
2acf923e 683 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 684
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
2acf923e
DC		 687 return 0;
688}
689
690int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
691{
764bcbc5
Z		 692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 694 kvm_inject_gp(vcpu, 0);
695 return 1;
696 }
697 return 0;
698}
699EXPORT_SYMBOL_GPL(kvm_set_xcr);
700
a83b29c6 701int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 702{
fc78f519 703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
705 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 706 if (cr4 & CR4_RESERVED_BITS)
707 return 1;
a03490ed 708
2acf923e
DC		 709 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
710 return 1;
711
c68b734f
YW		 712 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
713 return 1;
714
97ec8c06
FW		 715 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
716 return 1;
717
afcbf13f 718 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 719 return 1;
720
a03490ed 721 if (is_long_mode(vcpu)) {
0f12244f
GN		 722 if (!(cr4 & X86_CR4_PAE))
723 return 1;
a2edf57f
AK		 724 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
725 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 726 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
727 kvm_read_cr3(vcpu)))
0f12244f
GN		 728 return 1;
729
ad756a16
MJ		 730 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
731 if (!guest_cpuid_has_pcid(vcpu))
732 return 1;
733
734 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
735 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
736 return 1;
737 }
738
5e1746d6 739 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 740 return 1;
a03490ed 741
ad756a16
MJ		 742 if (((cr4 ^ old_cr4) & pdptr_bits) ||
743 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 744 kvm_mmu_reset_context(vcpu);
0f12244f 745
97ec8c06
FW		 746 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
747 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
748
2acf923e 749 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 750 kvm_update_cpuid(vcpu);
2acf923e 751
0f12244f
GN		 752 return 0;
753}
2d3ad1f4 754EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 755
2390218b 756int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 757{
ac146235 758#ifdef CONFIG_X86_64
9d88fca7 759 cr3 &= ~CR3_PCID_INVD;
ac146235 760#endif
9d88fca7 761
9f8fe504 762 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 763 kvm_mmu_sync_roots(vcpu);
77c3913b 764 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 765 return 0;
d835dfec
AK		 766 }
767
a03490ed 768 if (is_long_mode(vcpu)) {
d9f89b88
JK		 769 if (cr3 & CR3_L_MODE_RESERVED_BITS)
770 return 1;
771 } else if (is_pae(vcpu) && is_paging(vcpu) &&
772 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 773 return 1;
a03490ed 774
0f12244f 775 vcpu->arch.cr3 = cr3;
aff48baa 776 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 777 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 778 return 0;
779}
2d3ad1f4 780EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 781
eea1cff9 782int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 783{
0f12244f
GN		 784 if (cr8 & CR8_RESERVED_BITS)
785 return 1;
a03490ed
CO		 786 if (irqchip_in_kernel(vcpu->kvm))
787 kvm_lapic_set_tpr(vcpu, cr8);
788 else
ad312c7c 789 vcpu->arch.cr8 = cr8;
0f12244f
GN		 790 return 0;
791}
2d3ad1f4 792EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 793
2d3ad1f4 794unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 795{
796 if (irqchip_in_kernel(vcpu->kvm))
797 return kvm_lapic_get_cr8(vcpu);
798 else
ad312c7c 799 return vcpu->arch.cr8;
a03490ed 800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 802
73aaf249
JK		 803static void kvm_update_dr6(struct kvm_vcpu *vcpu)
804{
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
807}
808
c8639010
JK		 809static void kvm_update_dr7(struct kvm_vcpu *vcpu)
810{
811 unsigned long dr7;
812
813 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
814 dr7 = vcpu->arch.guest_debug_dr7;
815 else
816 dr7 = vcpu->arch.dr7;
817 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 818 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
819 if (dr7 & DR7_BP_EN_MASK)
820 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 821}
822
6f43ed01
NA		 823static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
824{
825 u64 fixed = DR6_FIXED_1;
826
827 if (!guest_cpuid_has_rtm(vcpu))
828 fixed |= DR6_RTM;
829 return fixed;
830}
831
338dbc97 832static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 833{
834 switch (dr) {
835 case 0 ... 3:
836 vcpu->arch.db[dr] = val;
837 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
838 vcpu->arch.eff_db[dr] = val;
839 break;
840 case 4:
020df079
GN		 841 /* fall through */
842 case 6:
338dbc97
GN		 843 if (val & 0xffffffff00000000ULL)
844 return -1; /* #GP */
6f43ed01 845 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 846 kvm_update_dr6(vcpu);
020df079
GN		 847 break;
848 case 5:
020df079
GN		 849 /* fall through */
850 default: /* 7 */
338dbc97
GN		 851 if (val & 0xffffffff00000000ULL)
852 return -1; /* #GP */
020df079 853 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 854 kvm_update_dr7(vcpu);
020df079
GN		 855 break;
856 }
857
858 return 0;
859}
338dbc97
GN		 860
861int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
862{
16f8a6f9 863 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 864 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 865 return 1;
866 }
867 return 0;
338dbc97 868}
020df079
GN		 869EXPORT_SYMBOL_GPL(kvm_set_dr);
870
16f8a6f9 871int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 872{
873 switch (dr) {
874 case 0 ... 3:
875 *val = vcpu->arch.db[dr];
876 break;
877 case 4:
020df079
GN		 878 /* fall through */
879 case 6:
73aaf249
JK		 880 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
881 *val = vcpu->arch.dr6;
882 else
883 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 884 break;
885 case 5:
020df079
GN		 886 /* fall through */
887 default: /* 7 */
888 *val = vcpu->arch.dr7;
889 break;
890 }
338dbc97
GN		 891 return 0;
892}
020df079
GN		 893EXPORT_SYMBOL_GPL(kvm_get_dr);
894
022cd0e8
AK		 895bool kvm_rdpmc(struct kvm_vcpu *vcpu)
896{
897 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
898 u64 data;
899 int err;
900
901 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
902 if (err)
903 return err;
904 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
905 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
906 return err;
907}
908EXPORT_SYMBOL_GPL(kvm_rdpmc);
909
043405e1
CO		 910/*
911 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
912 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
913 *
914 * This list is modified at module load time to reflect the
e3267cbb
GC		 915 * capabilities of the host cpu. This capabilities test skips MSRs that are
916 * kvm-specific. Those are put in the beginning of the list.
043405e1 917 */
e3267cbb 918
e984097b 919#define KVM_SAVE_MSRS_BEGIN 12
043405e1 920static u32 msrs_to_save[] = {
e3267cbb 921 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 922 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 923 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 924 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 925 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 926 MSR_KVM_PV_EOI_EN,
043405e1 927 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 928 MSR_STAR,
043405e1
CO		 929#ifdef CONFIG_X86_64
930 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
931#endif
b3897a49 932 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 933 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 934};
935
936static unsigned num_msrs_to_save;
937
f1d24831 938static const u32 emulated_msrs[] = {
ba904635 939 MSR_IA32_TSC_ADJUST,
a3e06bbe 940 MSR_IA32_TSCDEADLINE,
043405e1 941 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 942 MSR_IA32_MCG_STATUS,
943 MSR_IA32_MCG_CTL,
043405e1
CO		 944};
945
384bb783 946bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 947{
b69e8cae 948 if (efer & efer_reserved_bits)
384bb783 949 return false;
15c4a640 950
1b2fd70c
AG		 951 if (efer & EFER_FFXSR) {
952 struct kvm_cpuid_entry2 *feat;
953
954 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 955 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 956 return false;
1b2fd70c
AG		 957 }
958
d8017474
AG		 959 if (efer & EFER_SVME) {
960 struct kvm_cpuid_entry2 *feat;
961
962 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 963 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 964 return false;
d8017474
AG		 965 }
966
384bb783
JK		 967 return true;
968}
969EXPORT_SYMBOL_GPL(kvm_valid_efer);
970
971static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
972{
973 u64 old_efer = vcpu->arch.efer;
974
975 if (!kvm_valid_efer(vcpu, efer))
976 return 1;
977
978 if (is_paging(vcpu)
979 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
980 return 1;
981
15c4a640 982 efer &= ~EFER_LMA;
f6801dff 983 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 984
a3d204e2
SY		 985 kvm_x86_ops->set_efer(vcpu, efer);
986
aad82703
SY		 987 /* Update reserved bits */
988 if ((efer ^ old_efer) & EFER_NX)
989 kvm_mmu_reset_context(vcpu);
990
b69e8cae 991 return 0;
15c4a640
CO		 992}
993
f2b4b7dd
JR		 994void kvm_enable_efer_bits(u64 mask)
995{
996 efer_reserved_bits &= ~mask;
997}
998EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
999
15c4a640
CO		 1000/*
1001 * Writes msr value into into the appropriate "register".
1002 * Returns 0 on success, non-0 otherwise.
1003 * Assumes vcpu_load() was already called.
1004 */
8fe8ab46 1005int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1006{
854e8bb1
NA		 1007 switch (msr->index) {
1008 case MSR_FS_BASE:
1009 case MSR_GS_BASE:
1010 case MSR_KERNEL_GS_BASE:
1011 case MSR_CSTAR:
1012 case MSR_LSTAR:
1013 if (is_noncanonical_address(msr->data))
1014 return 1;
1015 break;
1016 case MSR_IA32_SYSENTER_EIP:
1017 case MSR_IA32_SYSENTER_ESP:
1018 /*
1019 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1020 * non-canonical address is written on Intel but not on
1021 * AMD (which ignores the top 32-bits, because it does
1022 * not implement 64-bit SYSENTER).
1023 *
1024 * 64-bit code should hence be able to write a non-canonical
1025 * value on AMD. Making the address canonical ensures that
1026 * vmentry does not fail on Intel after writing a non-canonical
1027 * value, and that something deterministic happens if the guest
1028 * invokes 64-bit SYSENTER.
1029 */
1030 msr->data = get_canonical(msr->data);
1031 }
8fe8ab46 1032 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1033}
854e8bb1 1034EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1035
313a3dc7
CO		 1036/*
1037 * Adapt set_msr() to msr_io()'s calling convention
1038 */
1039static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1040{
8fe8ab46
WA		 1041 struct msr_data msr;
1042
1043 msr.data = *data;
1044 msr.index = index;
1045 msr.host_initiated = true;
1046 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1047}
1048
16e8d74d
MT		 1049#ifdef CONFIG_X86_64
1050struct pvclock_gtod_data {
1051 seqcount_t seq;
1052
1053 struct { /* extract of a clocksource struct */
1054 int vclock_mode;
1055 cycle_t cycle_last;
1056 cycle_t mask;
1057 u32 mult;
1058 u32 shift;
1059 } clock;
1060
cbcf2dd3
TG		 1061 u64 boot_ns;
1062 u64 nsec_base;
16e8d74d
MT		 1063};
1064
1065static struct pvclock_gtod_data pvclock_gtod_data;
1066
1067static void update_pvclock_gtod(struct timekeeper *tk)
1068{
1069 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1070 u64 boot_ns;
1071
d28ede83 1072 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1073
1074 write_seqcount_begin(&vdata->seq);
1075
1076 /* copy pvclock gtod data */
d28ede83
TG		 1077 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1078 vdata->clock.cycle_last = tk->tkr.cycle_last;
1079 vdata->clock.mask = tk->tkr.mask;
1080 vdata->clock.mult = tk->tkr.mult;
1081 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1082
cbcf2dd3 1083 vdata->boot_ns = boot_ns;
d28ede83 1084 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1085
1086 write_seqcount_end(&vdata->seq);
1087}
1088#endif
1089
bab5bb39
NK		 1090void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1091{
1092 /*
1093 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1094 * vcpu_enter_guest. This function is only called from
1095 * the physical CPU that is running vcpu.
1096 */
1097 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1098}
16e8d74d 1099
18068523
GOC		 1100static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1101{
9ed3c444
AK		 1102 int version;
1103 int r;
50d0a0f9 1104 struct pvclock_wall_clock wc;
923de3cf 1105 struct timespec boot;
18068523
GOC		 1106
1107 if (!wall_clock)
1108 return;
1109
9ed3c444
AK		 1110 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1111 if (r)
1112 return;
1113
1114 if (version & 1)
1115 ++version; /* first time write, random junk */
1116
1117 ++version;
18068523 1118
18068523
GOC		 1119 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1120
50d0a0f9
GH		 1121 /*
1122 * The guest calculates current wall clock time by adding
34c238a1 1123 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1124 * wall clock specified here. guest system time equals host
1125 * system time for us, thus we must fill in host boot time here.
1126 */
923de3cf 1127 getboottime(&boot);
50d0a0f9 1128
4b648665
BR		 1129 if (kvm->arch.kvmclock_offset) {
1130 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1131 boot = timespec_sub(boot, ts);
1132 }
50d0a0f9
GH		 1133 wc.sec = boot.tv_sec;
1134 wc.nsec = boot.tv_nsec;
1135 wc.version = version;
18068523
GOC		 1136
1137 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1138
1139 version++;
1140 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1141}
1142
50d0a0f9
GH		 1143static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1144{
1145 uint32_t quotient, remainder;
1146
1147 /* Don't try to replace with do_div(), this one calculates
1148 * "(dividend << 32) / divisor" */
1149 __asm__ ( "divl %4"
1150 : "=a" (quotient), "=d" (remainder)
1151 : "0" (0), "1" (dividend), "r" (divisor) );
1152 return quotient;
1153}
1154
5f4e3f88
ZA		 1155static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1156 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1157{
5f4e3f88 1158 uint64_t scaled64;
50d0a0f9
GH		 1159 int32_t shift = 0;
1160 uint64_t tps64;
1161 uint32_t tps32;
1162
5f4e3f88
ZA		 1163 tps64 = base_khz * 1000LL;
1164 scaled64 = scaled_khz * 1000LL;
50933623 1165 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1166 tps64 >>= 1;
1167 shift--;
1168 }
1169
1170 tps32 = (uint32_t)tps64;
50933623
JK		 1171 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1172 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1173 scaled64 >>= 1;
1174 else
1175 tps32 <<= 1;
50d0a0f9
GH		 1176 shift++;
1177 }
1178
5f4e3f88
ZA		 1179 *pshift = shift;
1180 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1181
5f4e3f88
ZA		 1182 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1183 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1184}
1185
759379dd
ZA		 1186static inline u64 get_kernel_ns(void)
1187{
bb0b5812 1188 return ktime_get_boot_ns();
50d0a0f9
GH		 1189}
1190
d828199e 1191#ifdef CONFIG_X86_64
16e8d74d 1192static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1193#endif
16e8d74d 1194
c8076604 1195static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1196static unsigned long max_tsc_khz;
c8076604 1197
cc578287 1198static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1199{
cc578287
ZA		 1200 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1201 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1202}
1203
cc578287 1204static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1205{
cc578287
ZA		 1206 u64 v = (u64)khz * (1000000 + ppm);
1207 do_div(v, 1000000);
1208 return v;
1e993611
JR		 1209}
1210
cc578287 1211static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1212{
cc578287
ZA		 1213 u32 thresh_lo, thresh_hi;
1214 int use_scaling = 0;
217fc9cf 1215
03ba32ca
MT		 1216 /* tsc_khz can be zero if TSC calibration fails */
1217 if (this_tsc_khz == 0)
1218 return;
1219
c285545f
ZA		 1220 /* Compute a scale to convert nanoseconds in TSC cycles */
1221 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1222 &vcpu->arch.virtual_tsc_shift,
1223 &vcpu->arch.virtual_tsc_mult);
1224 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1225
1226 /*
1227 * Compute the variation in TSC rate which is acceptable
1228 * within the range of tolerance and decide if the
1229 * rate being applied is within that bounds of the hardware
1230 * rate. If so, no scaling or compensation need be done.
1231 */
1232 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1233 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1234 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1235 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1236 use_scaling = 1;
1237 }
1238 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1239}
1240
1241static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1242{
e26101b1 1243 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1244 vcpu->arch.virtual_tsc_mult,
1245 vcpu->arch.virtual_tsc_shift);
e26101b1 1246 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1247 return tsc;
1248}
1249
69b0049a 1250static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1251{
1252#ifdef CONFIG_X86_64
1253 bool vcpus_matched;
b48aa97e
MT		 1254 struct kvm_arch *ka = &vcpu->kvm->arch;
1255 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1256
1257 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1258 atomic_read(&vcpu->kvm->online_vcpus));
1259
7f187922
MT		 1260 /*
1261 * Once the masterclock is enabled, always perform request in
1262 * order to update it.
1263 *
1264 * In order to enable masterclock, the host clocksource must be TSC
1265 * and the vcpus need to have matched TSCs. When that happens,
1266 * perform request to enable masterclock.
1267 */
1268 if (ka->use_master_clock ||
1269 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1270 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1271
1272 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1273 atomic_read(&vcpu->kvm->online_vcpus),
1274 ka->use_master_clock, gtod->clock.vclock_mode);
1275#endif
1276}
1277
ba904635
WA		 1278static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1279{
1280 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1281 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1282}
1283
8fe8ab46 1284void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1285{
1286 struct kvm *kvm = vcpu->kvm;
f38e098f 1287 u64 offset, ns, elapsed;
99e3e30a 1288 unsigned long flags;
02626b6a 1289 s64 usdiff;
b48aa97e 1290 bool matched;
0d3da0d2 1291 bool already_matched;
8fe8ab46 1292 u64 data = msr->data;
99e3e30a 1293
038f8c11 1294 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1295 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1296 ns = get_kernel_ns();
f38e098f 1297 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1298
03ba32ca 1299 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1300 int faulted = 0;
1301
03ba32ca
MT		 1302 /* n.b - signed multiplication and division required */
1303 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1304#ifdef CONFIG_X86_64
03ba32ca 1305 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1306#else
03ba32ca 1307 /* do_div() only does unsigned */
8915aa27
MT		 1308 asm("1: idivl %[divisor]\n"
1309 "2: xor %%edx, %%edx\n"
1310 " movl $0, %[faulted]\n"
1311 "3:\n"
1312 ".section .fixup,\"ax\"\n"
1313 "4: movl $1, %[faulted]\n"
1314 " jmp 3b\n"
1315 ".previous\n"
1316
1317 _ASM_EXTABLE(1b, 4b)
1318
1319 : "=A"(usdiff), [faulted] "=r" (faulted)
1320 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1321
5d3cb0f6 1322#endif
03ba32ca
MT		 1323 do_div(elapsed, 1000);
1324 usdiff -= elapsed;
1325 if (usdiff < 0)
1326 usdiff = -usdiff;
8915aa27
MT		 1327
1328 /* idivl overflow => difference is larger than USEC_PER_SEC */
1329 if (faulted)
1330 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1331 } else
1332 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1333
1334 /*
5d3cb0f6
ZA		 1335 * Special case: TSC write with a small delta (1 second) of virtual
1336 * cycle time against real time is interpreted as an attempt to
1337 * synchronize the CPU.
1338 *
1339 * For a reliable TSC, we can match TSC offsets, and for an unstable
1340 * TSC, we add elapsed time in this computation. We could let the
1341 * compensation code attempt to catch up if we fall behind, but
1342 * it's better to try to match offsets from the beginning.
1343 */
02626b6a 1344 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1345 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1346 if (!check_tsc_unstable()) {
e26101b1 1347 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1348 pr_debug("kvm: matched tsc offset for %llu\n", data);
1349 } else {
857e4099 1350 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1351 data += delta;
1352 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1353 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1354 }
b48aa97e 1355 matched = true;
0d3da0d2 1356 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1357 } else {
1358 /*
1359 * We split periods of matched TSC writes into generations.
1360 * For each generation, we track the original measured
1361 * nanosecond time, offset, and write, so if TSCs are in
1362 * sync, we can match exact offset, and if not, we can match
4a969980 1363 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1364 *
1365 * These values are tracked in kvm->arch.cur_xxx variables.
1366 */
1367 kvm->arch.cur_tsc_generation++;
1368 kvm->arch.cur_tsc_nsec = ns;
1369 kvm->arch.cur_tsc_write = data;
1370 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1371 matched = false;
0d3da0d2 1372 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1373 kvm->arch.cur_tsc_generation, data);
f38e098f 1374 }
e26101b1
ZA		 1375
1376 /*
1377 * We also track th most recent recorded KHZ, write and time to
1378 * allow the matching interval to be extended at each write.
1379 */
f38e098f
ZA		 1380 kvm->arch.last_tsc_nsec = ns;
1381 kvm->arch.last_tsc_write = data;
5d3cb0f6 1382 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1383
b183aa58 1384 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1385
1386 /* Keep track of which generation this VCPU has synchronized to */
1387 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1388 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1389 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1390
ba904635
WA		 1391 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1392 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1393 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1394 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1395
1396 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1397 if (!matched) {
b48aa97e 1398 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1399 } else if (!already_matched) {
1400 kvm->arch.nr_vcpus_matched_tsc++;
1401 }
b48aa97e
MT		 1402
1403 kvm_track_tsc_matching(vcpu);
1404 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1405}
e26101b1 1406
99e3e30a
ZA		 1407EXPORT_SYMBOL_GPL(kvm_write_tsc);
1408
d828199e
MT		 1409#ifdef CONFIG_X86_64
1410
1411static cycle_t read_tsc(void)
1412{
1413 cycle_t ret;
1414 u64 last;
1415
1416 /*
1417 * Empirically, a fence (of type that depends on the CPU)
1418 * before rdtsc is enough to ensure that rdtsc is ordered
1419 * with respect to loads. The various CPU manuals are unclear
1420 * as to whether rdtsc can be reordered with later loads,
1421 * but no one has ever seen it happen.
1422 */
1423 rdtsc_barrier();
1424 ret = (cycle_t)vget_cycles();
1425
1426 last = pvclock_gtod_data.clock.cycle_last;
1427
1428 if (likely(ret >= last))
1429 return ret;
1430
1431 /*
1432 * GCC likes to generate cmov here, but this branch is extremely
1433 * predictable (it's just a funciton of time and the likely is
1434 * very likely) and there's a data dependence, so force GCC
1435 * to generate a branch instead. I don't barrier() because
1436 * we don't actually need a barrier, and if this function
1437 * ever gets inlined it will generate worse code.
1438 */
1439 asm volatile ("");
1440 return last;
1441}
1442
1443static inline u64 vgettsc(cycle_t *cycle_now)
1444{
1445 long v;
1446 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1447
1448 *cycle_now = read_tsc();
1449
1450 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1451 return v * gtod->clock.mult;
1452}
1453
cbcf2dd3 1454static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1455{
cbcf2dd3 1456 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1457 unsigned long seq;
d828199e 1458 int mode;
cbcf2dd3 1459 u64 ns;
d828199e 1460
d828199e
MT		 1461 do {
1462 seq = read_seqcount_begin(&gtod->seq);
1463 mode = gtod->clock.vclock_mode;
cbcf2dd3 1464 ns = gtod->nsec_base;
d828199e
MT		 1465 ns += vgettsc(cycle_now);
1466 ns >>= gtod->clock.shift;
cbcf2dd3 1467 ns += gtod->boot_ns;
d828199e 1468 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1469 *t = ns;
d828199e
MT		 1470
1471 return mode;
1472}
1473
1474/* returns true if host is using tsc clocksource */
1475static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1476{
d828199e
MT		 1477 /* checked again under seqlock below */
1478 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1479 return false;
1480
cbcf2dd3 1481 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1482}
1483#endif
1484
1485/*
1486 *
b48aa97e
MT		 1487 * Assuming a stable TSC across physical CPUS, and a stable TSC
1488 * across virtual CPUs, the following condition is possible.
1489 * Each numbered line represents an event visible to both
d828199e
MT		 1490 * CPUs at the next numbered event.
1491 *
1492 * "timespecX" represents host monotonic time. "tscX" represents
1493 * RDTSC value.
1494 *
1495 * VCPU0 on CPU0 | VCPU1 on CPU1
1496 *
1497 * 1. read timespec0,tsc0
1498 * 2. | timespec1 = timespec0 + N
1499 * | tsc1 = tsc0 + M
1500 * 3. transition to guest | transition to guest
1501 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1502 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1503 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1504 *
1505 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1506 *
1507 * - ret0 < ret1
1508 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1509 * ...
1510 * - 0 < N - M => M < N
1511 *
1512 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1513 * always the case (the difference between two distinct xtime instances
1514 * might be smaller then the difference between corresponding TSC reads,
1515 * when updating guest vcpus pvclock areas).
1516 *
1517 * To avoid that problem, do not allow visibility of distinct
1518 * system_timestamp/tsc_timestamp values simultaneously: use a master
1519 * copy of host monotonic time values. Update that master copy
1520 * in lockstep.
1521 *
b48aa97e 1522 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1523 *
1524 */
1525
1526static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1527{
1528#ifdef CONFIG_X86_64
1529 struct kvm_arch *ka = &kvm->arch;
1530 int vclock_mode;
b48aa97e
MT		 1531 bool host_tsc_clocksource, vcpus_matched;
1532
1533 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1534 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1535
1536 /*
1537 * If the host uses TSC clock, then passthrough TSC as stable
1538 * to the guest.
1539 */
b48aa97e 1540 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1541 &ka->master_kernel_ns,
1542 &ka->master_cycle_now);
1543
16a96021
MT		 1544 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1545 && !backwards_tsc_observed;
b48aa97e 1546
d828199e
MT		 1547 if (ka->use_master_clock)
1548 atomic_set(&kvm_guest_has_master_clock, 1);
1549
1550 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1551 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1552 vcpus_matched);
d828199e
MT		 1553#endif
1554}
1555
2e762ff7
MT		 1556static void kvm_gen_update_masterclock(struct kvm *kvm)
1557{
1558#ifdef CONFIG_X86_64
1559 int i;
1560 struct kvm_vcpu *vcpu;
1561 struct kvm_arch *ka = &kvm->arch;
1562
1563 spin_lock(&ka->pvclock_gtod_sync_lock);
1564 kvm_make_mclock_inprogress_request(kvm);
1565 /* no guest entries from this point */
1566 pvclock_update_vm_gtod_copy(kvm);
1567
1568 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1569 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1570
1571 /* guest entries allowed */
1572 kvm_for_each_vcpu(i, vcpu, kvm)
1573 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1574
1575 spin_unlock(&ka->pvclock_gtod_sync_lock);
1576#endif
1577}
1578
34c238a1 1579static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1580{
d828199e 1581 unsigned long flags, this_tsc_khz;
18068523 1582 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1583 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1584 s64 kernel_ns;
d828199e 1585 u64 tsc_timestamp, host_tsc;
0b79459b 1586 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1587 u8 pvclock_flags;
d828199e
MT		 1588 bool use_master_clock;
1589
1590 kernel_ns = 0;
1591 host_tsc = 0;
18068523 1592
d828199e
MT		 1593 /*
1594 * If the host uses TSC clock, then passthrough TSC as stable
1595 * to the guest.
1596 */
1597 spin_lock(&ka->pvclock_gtod_sync_lock);
1598 use_master_clock = ka->use_master_clock;
1599 if (use_master_clock) {
1600 host_tsc = ka->master_cycle_now;
1601 kernel_ns = ka->master_kernel_ns;
1602 }
1603 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1604
1605 /* Keep irq disabled to prevent changes to the clock */
1606 local_irq_save(flags);
89cbc767 1607 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1608 if (unlikely(this_tsc_khz == 0)) {
1609 local_irq_restore(flags);
1610 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1611 return 1;
1612 }
d828199e
MT		 1613 if (!use_master_clock) {
1614 host_tsc = native_read_tsc();
1615 kernel_ns = get_kernel_ns();
1616 }
1617
1618 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1619
c285545f
ZA		 1620 /*
1621 * We may have to catch up the TSC to match elapsed wall clock
1622 * time for two reasons, even if kvmclock is used.
1623 * 1) CPU could have been running below the maximum TSC rate
1624 * 2) Broken TSC compensation resets the base at each VCPU
1625 * entry to avoid unknown leaps of TSC even when running
1626 * again on the same CPU. This may cause apparent elapsed
1627 * time to disappear, and the guest to stand still or run
1628 * very slowly.
1629 */
1630 if (vcpu->tsc_catchup) {
1631 u64 tsc = compute_guest_tsc(v, kernel_ns);
1632 if (tsc > tsc_timestamp) {
f1e2b260 1633 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1634 tsc_timestamp = tsc;
1635 }
50d0a0f9
GH		 1636 }
1637
18068523
GOC		 1638 local_irq_restore(flags);
1639
0b79459b 1640 if (!vcpu->pv_time_enabled)
c285545f 1641 return 0;
18068523 1642
e48672fa 1643 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1644 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1645 &vcpu->hv_clock.tsc_shift,
1646 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1647 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1648 }
1649
1650 /* With all the info we got, fill in the values */
1d5f066e 1651 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1652 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1653 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1654
09a0c3f1
OH		 1655 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1656 &guest_hv_clock, sizeof(guest_hv_clock))))
1657 return 0;
1658
18068523
GOC		 1659 /*
1660 * The interface expects us to write an even number signaling that the
1661 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1662 * state, we just increase by 2 at the end.
18068523 1663 */
09a0c3f1 1664 vcpu->hv_clock.version = guest_hv_clock.version + 2;
78c0337a
MT		 1665
1666 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1667 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1668
1669 if (vcpu->pvclock_set_guest_stopped_request) {
1670 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1671 vcpu->pvclock_set_guest_stopped_request = false;
1672 }
1673
d828199e
MT		 1674 /* If the host uses TSC clocksource, then it is stable */
1675 if (use_master_clock)
1676 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1677
78c0337a
MT		 1678 vcpu->hv_clock.flags = pvclock_flags;
1679
ce1a5e60
DM		 1680 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1681
0b79459b
AH		 1682 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1683 &vcpu->hv_clock,
1684 sizeof(vcpu->hv_clock));
8cfdc000 1685 return 0;
c8076604
GH		 1686}
1687
0061d53d
MT		 1688/*
1689 * kvmclock updates which are isolated to a given vcpu, such as
1690 * vcpu->cpu migration, should not allow system_timestamp from
1691 * the rest of the vcpus to remain static. Otherwise ntp frequency
1692 * correction applies to one vcpu's system_timestamp but not
1693 * the others.
1694 *
1695 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1696 * We need to rate-limit these requests though, as they can
1697 * considerably slow guests that have a large number of vcpus.
1698 * The time for a remote vcpu to update its kvmclock is bound
1699 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1700 */
1701
7e44e449
AJ		 1702#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1703
1704static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1705{
1706 int i;
7e44e449
AJ		 1707 struct delayed_work *dwork = to_delayed_work(work);
1708 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1709 kvmclock_update_work);
1710 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1711 struct kvm_vcpu *vcpu;
1712
1713 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1714 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1715 kvm_vcpu_kick(vcpu);
1716 }
1717}
1718
7e44e449
AJ		 1719static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1720{
1721 struct kvm *kvm = v->kvm;
1722
105b21bb 1723 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1724 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1725 KVMCLOCK_UPDATE_DELAY);
1726}
1727
332967a3
AJ		 1728#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1729
1730static void kvmclock_sync_fn(struct work_struct *work)
1731{
1732 struct delayed_work *dwork = to_delayed_work(work);
1733 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1734 kvmclock_sync_work);
1735 struct kvm *kvm = container_of(ka, struct kvm, arch);
1736
1737 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1738 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1739 KVMCLOCK_SYNC_PERIOD);
1740}
1741
9ba075a6
AK		 1742static bool msr_mtrr_valid(unsigned msr)
1743{
1744 switch (msr) {
1745 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1746 case MSR_MTRRfix64K_00000:
1747 case MSR_MTRRfix16K_80000:
1748 case MSR_MTRRfix16K_A0000:
1749 case MSR_MTRRfix4K_C0000:
1750 case MSR_MTRRfix4K_C8000:
1751 case MSR_MTRRfix4K_D0000:
1752 case MSR_MTRRfix4K_D8000:
1753 case MSR_MTRRfix4K_E0000:
1754 case MSR_MTRRfix4K_E8000:
1755 case MSR_MTRRfix4K_F0000:
1756 case MSR_MTRRfix4K_F8000:
1757 case MSR_MTRRdefType:
1758 case MSR_IA32_CR_PAT:
1759 return true;
1760 case 0x2f8:
1761 return true;
1762 }
1763 return false;
1764}
1765
d6289b93
MT		 1766static bool valid_pat_type(unsigned t)
1767{
1768 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1769}
1770
1771static bool valid_mtrr_type(unsigned t)
1772{
1773 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1774}
1775
4566654b 1776bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1777{
1778 int i;
fd275235 1779 u64 mask;
d6289b93
MT		 1780
1781 if (!msr_mtrr_valid(msr))
1782 return false;
1783
1784 if (msr == MSR_IA32_CR_PAT) {
1785 for (i = 0; i < 8; i++)
1786 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1787 return false;
1788 return true;
1789 } else if (msr == MSR_MTRRdefType) {
1790 if (data & ~0xcff)
1791 return false;
1792 return valid_mtrr_type(data & 0xff);
1793 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1794 for (i = 0; i < 8 ; i++)
1795 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1796 return false;
1797 return true;
1798 }
1799
1800 /* variable MTRRs */
adfb5d27
WL		 1801 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1802
fd275235 1803 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1804 if ((msr & 1) == 0) {
adfb5d27 1805 /* MTRR base */
d7a2a246
WL		 1806 if (!valid_mtrr_type(data & 0xff))
1807 return false;
1808 mask |= 0xf00;
1809 } else
1810 /* MTRR mask */
1811 mask |= 0x7ff;
1812 if (data & mask) {
1813 kvm_inject_gp(vcpu, 0);
1814 return false;
1815 }
1816
adfb5d27 1817 return true;
d6289b93 1818}
4566654b 1819EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1820
9ba075a6
AK		 1821static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1822{
0bed3b56
SY		 1823 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1824
4566654b 1825 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1826 return 1;
1827
0bed3b56
SY		 1828 if (msr == MSR_MTRRdefType) {
1829 vcpu->arch.mtrr_state.def_type = data;
1830 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1831 } else if (msr == MSR_MTRRfix64K_00000)
1832 p[0] = data;
1833 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1834 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1835 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1836 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1837 else if (msr == MSR_IA32_CR_PAT)
1838 vcpu->arch.pat = data;
1839 else { /* Variable MTRRs */
1840 int idx, is_mtrr_mask;
1841 u64 *pt;
1842
1843 idx = (msr - 0x200) / 2;
1844 is_mtrr_mask = msr - 0x200 - 2 * idx;
1845 if (!is_mtrr_mask)
1846 pt =
1847 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1848 else
1849 pt =
1850 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1851 *pt = data;
1852 }
1853
1854 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1855 return 0;
1856}
15c4a640 1857
890ca9ae 1858static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1859{
890ca9ae
HY		 1860 u64 mcg_cap = vcpu->arch.mcg_cap;
1861 unsigned bank_num = mcg_cap & 0xff;
1862
15c4a640 1863 switch (msr) {
15c4a640 1864 case MSR_IA32_MCG_STATUS:
890ca9ae 1865 vcpu->arch.mcg_status = data;
15c4a640 1866 break;
c7ac679c 1867 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1868 if (!(mcg_cap & MCG_CTL_P))
1869 return 1;
1870 if (data != 0 && data != ~(u64)0)
1871 return -1;
1872 vcpu->arch.mcg_ctl = data;
1873 break;
1874 default:
1875 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1876 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1877 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1878 /* only 0 or all 1s can be written to IA32_MCi_CTL
1879 * some Linux kernels though clear bit 10 in bank 4 to
1880 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1881 * this to avoid an uncatched #GP in the guest
1882 */
890ca9ae 1883 if ((offset & 0x3) == 0 &&
114be429 1884 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1885 return -1;
1886 vcpu->arch.mce_banks[offset] = data;
1887 break;
1888 }
1889 return 1;
1890 }
1891 return 0;
1892}
1893
ffde22ac
ES		 1894static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1895{
1896 struct kvm *kvm = vcpu->kvm;
1897 int lm = is_long_mode(vcpu);
1898 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1899 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1900 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1901 : kvm->arch.xen_hvm_config.blob_size_32;
1902 u32 page_num = data & ~PAGE_MASK;
1903 u64 page_addr = data & PAGE_MASK;
1904 u8 *page;
1905 int r;
1906
1907 r = -E2BIG;
1908 if (page_num >= blob_size)
1909 goto out;
1910 r = -ENOMEM;
ff5c2c03
SL		 1911 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1912 if (IS_ERR(page)) {
1913 r = PTR_ERR(page);
ffde22ac 1914 goto out;
ff5c2c03 1915 }
ffde22ac
ES		 1916 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1917 goto out_free;
1918 r = 0;
1919out_free:
1920 kfree(page);
1921out:
1922 return r;
1923}
1924
55cd8e5a
GN		 1925static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1926{
1927 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1928}
1929
1930static bool kvm_hv_msr_partition_wide(u32 msr)
1931{
1932 bool r = false;
1933 switch (msr) {
1934 case HV_X64_MSR_GUEST_OS_ID:
1935 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1936 case HV_X64_MSR_REFERENCE_TSC:
1937 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1938 r = true;
1939 break;
1940 }
1941
1942 return r;
1943}
1944
1945static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1946{
1947 struct kvm *kvm = vcpu->kvm;
1948
1949 switch (msr) {
1950 case HV_X64_MSR_GUEST_OS_ID:
1951 kvm->arch.hv_guest_os_id = data;
1952 /* setting guest os id to zero disables hypercall page */
1953 if (!kvm->arch.hv_guest_os_id)
1954 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1955 break;
1956 case HV_X64_MSR_HYPERCALL: {
1957 u64 gfn;
1958 unsigned long addr;
1959 u8 instructions[4];
1960
1961 /* if guest os id is not set hypercall should remain disabled */
1962 if (!kvm->arch.hv_guest_os_id)
1963 break;
1964 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1965 kvm->arch.hv_hypercall = data;
1966 break;
1967 }
1968 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1969 addr = gfn_to_hva(kvm, gfn);
1970 if (kvm_is_error_hva(addr))
1971 return 1;
1972 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1973 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1974 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1975 return 1;
1976 kvm->arch.hv_hypercall = data;
b94b64c9 1977 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1978 break;
1979 }
e984097b
VR		 1980 case HV_X64_MSR_REFERENCE_TSC: {
1981 u64 gfn;
1982 HV_REFERENCE_TSC_PAGE tsc_ref;
1983 memset(&tsc_ref, 0, sizeof(tsc_ref));
1984 kvm->arch.hv_tsc_page = data;
1985 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1986 break;
1987 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1988 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1989 &tsc_ref, sizeof(tsc_ref)))
1990 return 1;
1991 mark_page_dirty(kvm, gfn);
1992 break;
1993 }
55cd8e5a 1994 default:
a737f256
CD		 1995 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1996 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1997 return 1;
1998 }
1999 return 0;
2000}
2001
2002static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2003{
10388a07
GN		 2004 switch (msr) {
2005 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2006 u64 gfn;
10388a07 2007 unsigned long addr;
55cd8e5a 2008
10388a07
GN		 2009 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2010 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2011 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2012 return 1;
10388a07
GN		 2013 break;
2014 }
b3af1e88
VR		 2015 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2016 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2017 if (kvm_is_error_hva(addr))
2018 return 1;
8b0cedff 2019 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2020 return 1;
2021 vcpu->arch.hv_vapic = data;
b3af1e88 2022 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2023 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2024 return 1;
10388a07
GN		 2025 break;
2026 }
2027 case HV_X64_MSR_EOI:
2028 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2029 case HV_X64_MSR_ICR:
2030 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2031 case HV_X64_MSR_TPR:
2032 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2033 default:
a737f256
CD		 2034 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2035 "data 0x%llx\n", msr, data);
10388a07
GN		 2036 return 1;
2037 }
2038
2039 return 0;
55cd8e5a
GN		 2040}
2041
344d9588
GN		 2042static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2043{
2044 gpa_t gpa = data & ~0x3f;
2045
4a969980 2046 /* Bits 2:5 are reserved, Should be zero */
6adba527 2047 if (data & 0x3c)
344d9588
GN		 2048 return 1;
2049
2050 vcpu->arch.apf.msr_val = data;
2051
2052 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2053 kvm_clear_async_pf_completion_queue(vcpu);
2054 kvm_async_pf_hash_reset(vcpu);
2055 return 0;
2056 }
2057
8f964525
AH		 2058 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2059 sizeof(u32)))
344d9588
GN		 2060 return 1;
2061
6adba527 2062 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2063 kvm_async_pf_wakeup_all(vcpu);
2064 return 0;
2065}
2066
12f9a48f
GC		 2067static void kvmclock_reset(struct kvm_vcpu *vcpu)
2068{
0b79459b 2069 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2070}
2071
c9aaa895
GC		 2072static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2073{
2074 u64 delta;
2075
2076 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2077 return;
2078
2079 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2080 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2081 vcpu->arch.st.accum_steal = delta;
2082}
2083
2084static void record_steal_time(struct kvm_vcpu *vcpu)
2085{
2086 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2087 return;
2088
2089 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2090 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2091 return;
2092
2093 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2094 vcpu->arch.st.steal.version += 2;
2095 vcpu->arch.st.accum_steal = 0;
2096
2097 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2098 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2099}
2100
8fe8ab46 2101int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2102{
5753785f 2103 bool pr = false;
8fe8ab46
WA		 2104 u32 msr = msr_info->index;
2105 u64 data = msr_info->data;
5753785f 2106
15c4a640 2107 switch (msr) {
2e32b719
BP		 2108 case MSR_AMD64_NB_CFG:
2109 case MSR_IA32_UCODE_REV:
2110 case MSR_IA32_UCODE_WRITE:
2111 case MSR_VM_HSAVE_PA:
2112 case MSR_AMD64_PATCH_LOADER:
2113 case MSR_AMD64_BU_CFG2:
2114 break;
2115
15c4a640 2116 case MSR_EFER:
b69e8cae 2117 return set_efer(vcpu, data);
8f1589d9
AP		 2118 case MSR_K7_HWCR:
2119 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2120 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2121 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2122 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2123 if (data != 0) {
a737f256
CD		 2124 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2125 data);
8f1589d9
AP		 2126 return 1;
2127 }
15c4a640 2128 break;
f7c6d140
AP		 2129 case MSR_FAM10H_MMIO_CONF_BASE:
2130 if (data != 0) {
a737f256
CD		 2131 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2132 "0x%llx\n", data);
f7c6d140
AP		 2133 return 1;
2134 }
15c4a640 2135 break;
b5e2fec0
AG		 2136 case MSR_IA32_DEBUGCTLMSR:
2137 if (!data) {
2138 /* We support the non-activated case already */
2139 break;
2140 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2141 /* Values other than LBR and BTF are vendor-specific,
2142 thus reserved and should throw a #GP */
2143 return 1;
2144 }
a737f256
CD		 2145 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2146 __func__, data);
b5e2fec0 2147 break;
9ba075a6
AK		 2148 case 0x200 ... 0x2ff:
2149 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2150 case MSR_IA32_APICBASE:
58cb628d 2151 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2152 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2153 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2154 case MSR_IA32_TSCDEADLINE:
2155 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2156 break;
ba904635
WA		 2157 case MSR_IA32_TSC_ADJUST:
2158 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2159 if (!msr_info->host_initiated) {
d913b904 2160 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2161 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2162 }
2163 vcpu->arch.ia32_tsc_adjust_msr = data;
2164 }
2165 break;
15c4a640 2166 case MSR_IA32_MISC_ENABLE:
ad312c7c 2167 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2168 break;
11c6bffa 2169 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2170 case MSR_KVM_WALL_CLOCK:
2171 vcpu->kvm->arch.wall_clock = data;
2172 kvm_write_wall_clock(vcpu->kvm, data);
2173 break;
11c6bffa 2174 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2175 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2176 u64 gpa_offset;
12f9a48f 2177 kvmclock_reset(vcpu);
18068523
GOC		 2178
2179 vcpu->arch.time = data;
0061d53d 2180 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2181
2182 /* we verify if the enable bit is set... */
2183 if (!(data & 1))
2184 break;
2185
0b79459b 2186 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2187
0b79459b 2188 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2189 &vcpu->arch.pv_time, data & ~1ULL,
2190 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2191 vcpu->arch.pv_time_enabled = false;
2192 else
2193 vcpu->arch.pv_time_enabled = true;
32cad84f 2194
18068523
GOC		 2195 break;
2196 }
344d9588
GN		 2197 case MSR_KVM_ASYNC_PF_EN:
2198 if (kvm_pv_enable_async_pf(vcpu, data))
2199 return 1;
2200 break;
c9aaa895
GC		 2201 case MSR_KVM_STEAL_TIME:
2202
2203 if (unlikely(!sched_info_on()))
2204 return 1;
2205
2206 if (data & KVM_STEAL_RESERVED_MASK)
2207 return 1;
2208
2209 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2210 data & KVM_STEAL_VALID_BITS,
2211 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2212 return 1;
2213
2214 vcpu->arch.st.msr_val = data;
2215
2216 if (!(data & KVM_MSR_ENABLED))
2217 break;
2218
2219 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2220
2221 preempt_disable();
2222 accumulate_steal_time(vcpu);
2223 preempt_enable();
2224
2225 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2226
2227 break;
ae7a2a3f
MT		 2228 case MSR_KVM_PV_EOI_EN:
2229 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2230 return 1;
2231 break;
c9aaa895 2232
890ca9ae
HY		 2233 case MSR_IA32_MCG_CTL:
2234 case MSR_IA32_MCG_STATUS:
81760dcc 2235 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2236 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2237
2238 /* Performance counters are not protected by a CPUID bit,
2239 * so we should check all of them in the generic path for the sake of
2240 * cross vendor migration.
2241 * Writing a zero into the event select MSRs disables them,
2242 * which we perfectly emulate ;-). Any other value should be at least
2243 * reported, some guests depend on them.
2244 */
71db6023
AP		 2245 case MSR_K7_EVNTSEL0:
2246 case MSR_K7_EVNTSEL1:
2247 case MSR_K7_EVNTSEL2:
2248 case MSR_K7_EVNTSEL3:
2249 if (data != 0)
a737f256
CD		 2250 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2251 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2252 break;
2253 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2254 * so we ignore writes to make it happy.
2255 */
71db6023
AP		 2256 case MSR_K7_PERFCTR0:
2257 case MSR_K7_PERFCTR1:
2258 case MSR_K7_PERFCTR2:
2259 case MSR_K7_PERFCTR3:
a737f256
CD		 2260 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2261 "0x%x data 0x%llx\n", msr, data);
71db6023 2262 break;
5753785f
GN		 2263 case MSR_P6_PERFCTR0:
2264 case MSR_P6_PERFCTR1:
2265 pr = true;
2266 case MSR_P6_EVNTSEL0:
2267 case MSR_P6_EVNTSEL1:
2268 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2269 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2270
2271 if (pr || data != 0)
a737f256
CD		 2272 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2273 "0x%x data 0x%llx\n", msr, data);
5753785f 2274 break;
84e0cefa
JS		 2275 case MSR_K7_CLK_CTL:
2276 /*
2277 * Ignore all writes to this no longer documented MSR.
2278 * Writes are only relevant for old K7 processors,
2279 * all pre-dating SVM, but a recommended workaround from
4a969980 2280 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2281 * affected processor models on the command line, hence
2282 * the need to ignore the workaround.
2283 */
2284 break;
55cd8e5a
GN		 2285 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2286 if (kvm_hv_msr_partition_wide(msr)) {
2287 int r;
2288 mutex_lock(&vcpu->kvm->lock);
2289 r = set_msr_hyperv_pw(vcpu, msr, data);
2290 mutex_unlock(&vcpu->kvm->lock);
2291 return r;
2292 } else
2293 return set_msr_hyperv(vcpu, msr, data);
2294 break;
91c9c3ed 2295 case MSR_IA32_BBL_CR_CTL3:
2296 /* Drop writes to this legacy MSR -- see rdmsr
2297 * counterpart for further detail.
2298 */
a737f256 2299 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2300 break;
2b036c6b
BO		 2301 case MSR_AMD64_OSVW_ID_LENGTH:
2302 if (!guest_cpuid_has_osvw(vcpu))
2303 return 1;
2304 vcpu->arch.osvw.length = data;
2305 break;
2306 case MSR_AMD64_OSVW_STATUS:
2307 if (!guest_cpuid_has_osvw(vcpu))
2308 return 1;
2309 vcpu->arch.osvw.status = data;
2310 break;
15c4a640 2311 default:
ffde22ac
ES		 2312 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2313 return xen_hvm_config(vcpu, data);
f5132b01 2314 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2315 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2316 if (!ignore_msrs) {
a737f256
CD		 2317 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2318 msr, data);
ed85c068
AP		 2319 return 1;
2320 } else {
a737f256
CD		 2321 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2322 msr, data);
ed85c068
AP		 2323 break;
2324 }
15c4a640
CO		 2325 }
2326 return 0;
2327}
2328EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2329
2330
2331/*
2332 * Reads an msr value (of 'msr_index') into 'pdata'.
2333 * Returns 0 on success, non-0 otherwise.
2334 * Assumes vcpu_load() was already called.
2335 */
2336int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2337{
2338 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2339}
ff651cb6 2340EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2341
9ba075a6
AK		 2342static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2343{
0bed3b56
SY		 2344 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2345
9ba075a6
AK		 2346 if (!msr_mtrr_valid(msr))
2347 return 1;
2348
0bed3b56
SY		 2349 if (msr == MSR_MTRRdefType)
2350 *pdata = vcpu->arch.mtrr_state.def_type +
2351 (vcpu->arch.mtrr_state.enabled << 10);
2352 else if (msr == MSR_MTRRfix64K_00000)
2353 *pdata = p[0];
2354 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2355 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2356 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2357 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2358 else if (msr == MSR_IA32_CR_PAT)
2359 *pdata = vcpu->arch.pat;
2360 else { /* Variable MTRRs */
2361 int idx, is_mtrr_mask;
2362 u64 *pt;
2363
2364 idx = (msr - 0x200) / 2;
2365 is_mtrr_mask = msr - 0x200 - 2 * idx;
2366 if (!is_mtrr_mask)
2367 pt =
2368 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2369 else
2370 pt =
2371 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2372 *pdata = *pt;
2373 }
2374
9ba075a6
AK		 2375 return 0;
2376}
2377
890ca9ae 2378static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2379{
2380 u64 data;
890ca9ae
HY		 2381 u64 mcg_cap = vcpu->arch.mcg_cap;
2382 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2383
2384 switch (msr) {
15c4a640
CO		 2385 case MSR_IA32_P5_MC_ADDR:
2386 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2387 data = 0;
2388 break;
15c4a640 2389 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2390 data = vcpu->arch.mcg_cap;
2391 break;
c7ac679c 2392 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2393 if (!(mcg_cap & MCG_CTL_P))
2394 return 1;
2395 data = vcpu->arch.mcg_ctl;
2396 break;
2397 case MSR_IA32_MCG_STATUS:
2398 data = vcpu->arch.mcg_status;
2399 break;
2400 default:
2401 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2402 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2403 u32 offset = msr - MSR_IA32_MC0_CTL;
2404 data = vcpu->arch.mce_banks[offset];
2405 break;
2406 }
2407 return 1;
2408 }
2409 *pdata = data;
2410 return 0;
2411}
2412
55cd8e5a
GN		 2413static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2414{
2415 u64 data = 0;
2416 struct kvm *kvm = vcpu->kvm;
2417
2418 switch (msr) {
2419 case HV_X64_MSR_GUEST_OS_ID:
2420 data = kvm->arch.hv_guest_os_id;
2421 break;
2422 case HV_X64_MSR_HYPERCALL:
2423 data = kvm->arch.hv_hypercall;
2424 break;
e984097b
VR		 2425 case HV_X64_MSR_TIME_REF_COUNT: {
2426 data =
2427 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2428 break;
2429 }
2430 case HV_X64_MSR_REFERENCE_TSC:
2431 data = kvm->arch.hv_tsc_page;
2432 break;
55cd8e5a 2433 default:
a737f256 2434 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2435 return 1;
2436 }
2437
2438 *pdata = data;
2439 return 0;
2440}
2441
2442static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2443{
2444 u64 data = 0;
2445
2446 switch (msr) {
2447 case HV_X64_MSR_VP_INDEX: {
2448 int r;
2449 struct kvm_vcpu *v;
684851a1
TY		 2450 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2451 if (v == vcpu) {
55cd8e5a 2452 data = r;
684851a1
TY		 2453 break;
2454 }
2455 }
55cd8e5a
GN		 2456 break;
2457 }
10388a07
GN		 2458 case HV_X64_MSR_EOI:
2459 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2460 case HV_X64_MSR_ICR:
2461 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2462 case HV_X64_MSR_TPR:
2463 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2464 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2465 data = vcpu->arch.hv_vapic;
2466 break;
55cd8e5a 2467 default:
a737f256 2468 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2469 return 1;
2470 }
2471 *pdata = data;
2472 return 0;
2473}
2474
890ca9ae
HY		 2475int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2476{
2477 u64 data;
2478
2479 switch (msr) {
890ca9ae 2480 case MSR_IA32_PLATFORM_ID:
15c4a640 2481 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2482 case MSR_IA32_DEBUGCTLMSR:
2483 case MSR_IA32_LASTBRANCHFROMIP:
2484 case MSR_IA32_LASTBRANCHTOIP:
2485 case MSR_IA32_LASTINTFROMIP:
2486 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2487 case MSR_K8_SYSCFG:
2488 case MSR_K7_HWCR:
61a6bd67 2489 case MSR_VM_HSAVE_PA:
9e699624 2490 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2491 case MSR_K7_EVNTSEL1:
2492 case MSR_K7_EVNTSEL2:
2493 case MSR_K7_EVNTSEL3:
1f3ee616 2494 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2495 case MSR_K7_PERFCTR1:
2496 case MSR_K7_PERFCTR2:
2497 case MSR_K7_PERFCTR3:
1fdbd48c 2498 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2499 case MSR_AMD64_NB_CFG:
f7c6d140 2500 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2501 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2502 data = 0;
2503 break;
5753785f
GN		 2504 case MSR_P6_PERFCTR0:
2505 case MSR_P6_PERFCTR1:
2506 case MSR_P6_EVNTSEL0:
2507 case MSR_P6_EVNTSEL1:
2508 if (kvm_pmu_msr(vcpu, msr))
2509 return kvm_pmu_get_msr(vcpu, msr, pdata);
2510 data = 0;
2511 break;
742bc670
MT		 2512 case MSR_IA32_UCODE_REV:
2513 data = 0x100000000ULL;
2514 break;
9ba075a6
AK		 2515 case MSR_MTRRcap:
2516 data = 0x500 | KVM_NR_VAR_MTRR;
2517 break;
2518 case 0x200 ... 0x2ff:
2519 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2520 case 0xcd: /* fsb frequency */
2521 data = 3;
2522 break;
7b914098
JS		 2523 /*
2524 * MSR_EBC_FREQUENCY_ID
2525 * Conservative value valid for even the basic CPU models.
2526 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2527 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2528 * and 266MHz for model 3, or 4. Set Core Clock
2529 * Frequency to System Bus Frequency Ratio to 1 (bits
2530 * 31:24) even though these are only valid for CPU
2531 * models > 2, however guests may end up dividing or
2532 * multiplying by zero otherwise.
2533 */
2534 case MSR_EBC_FREQUENCY_ID:
2535 data = 1 << 24;
2536 break;
15c4a640
CO		 2537 case MSR_IA32_APICBASE:
2538 data = kvm_get_apic_base(vcpu);
2539 break;
0105d1a5
GN		 2540 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2541 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2542 break;
a3e06bbe
LJ		 2543 case MSR_IA32_TSCDEADLINE:
2544 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2545 break;
ba904635
WA		 2546 case MSR_IA32_TSC_ADJUST:
2547 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2548 break;
15c4a640 2549 case MSR_IA32_MISC_ENABLE:
ad312c7c 2550 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2551 break;
847f0ad8
AG		 2552 case MSR_IA32_PERF_STATUS:
2553 /* TSC increment by tick */
2554 data = 1000ULL;
2555 /* CPU multiplier */
2556 data |= (((uint64_t)4ULL) << 40);
2557 break;
15c4a640 2558 case MSR_EFER:
f6801dff 2559 data = vcpu->arch.efer;
15c4a640 2560 break;
18068523 2561 case MSR_KVM_WALL_CLOCK:
11c6bffa 2562 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2563 data = vcpu->kvm->arch.wall_clock;
2564 break;
2565 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2566 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2567 data = vcpu->arch.time;
2568 break;
344d9588
GN		 2569 case MSR_KVM_ASYNC_PF_EN:
2570 data = vcpu->arch.apf.msr_val;
2571 break;
c9aaa895
GC		 2572 case MSR_KVM_STEAL_TIME:
2573 data = vcpu->arch.st.msr_val;
2574 break;
1d92128f
MT		 2575 case MSR_KVM_PV_EOI_EN:
2576 data = vcpu->arch.pv_eoi.msr_val;
2577 break;
890ca9ae
HY		 2578 case MSR_IA32_P5_MC_ADDR:
2579 case MSR_IA32_P5_MC_TYPE:
2580 case MSR_IA32_MCG_CAP:
2581 case MSR_IA32_MCG_CTL:
2582 case MSR_IA32_MCG_STATUS:
81760dcc 2583 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2584 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2585 case MSR_K7_CLK_CTL:
2586 /*
2587 * Provide expected ramp-up count for K7. All other
2588 * are set to zero, indicating minimum divisors for
2589 * every field.
2590 *
2591 * This prevents guest kernels on AMD host with CPU
2592 * type 6, model 8 and higher from exploding due to
2593 * the rdmsr failing.
2594 */
2595 data = 0x20000000;
2596 break;
55cd8e5a
GN		 2597 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2598 if (kvm_hv_msr_partition_wide(msr)) {
2599 int r;
2600 mutex_lock(&vcpu->kvm->lock);
2601 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2602 mutex_unlock(&vcpu->kvm->lock);
2603 return r;
2604 } else
2605 return get_msr_hyperv(vcpu, msr, pdata);
2606 break;
91c9c3ed 2607 case MSR_IA32_BBL_CR_CTL3:
2608 /* This legacy MSR exists but isn't fully documented in current
2609 * silicon. It is however accessed by winxp in very narrow
2610 * scenarios where it sets bit #19, itself documented as
2611 * a "reserved" bit. Best effort attempt to source coherent
2612 * read data here should the balance of the register be
2613 * interpreted by the guest:
2614 *
2615 * L2 cache control register 3: 64GB range, 256KB size,
2616 * enabled, latency 0x1, configured
2617 */
2618 data = 0xbe702111;
2619 break;
2b036c6b
BO		 2620 case MSR_AMD64_OSVW_ID_LENGTH:
2621 if (!guest_cpuid_has_osvw(vcpu))
2622 return 1;
2623 data = vcpu->arch.osvw.length;
2624 break;
2625 case MSR_AMD64_OSVW_STATUS:
2626 if (!guest_cpuid_has_osvw(vcpu))
2627 return 1;
2628 data = vcpu->arch.osvw.status;
2629 break;
15c4a640 2630 default:
f5132b01
GN		 2631 if (kvm_pmu_msr(vcpu, msr))
2632 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2633 if (!ignore_msrs) {
a737f256 2634 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2635 return 1;
2636 } else {
a737f256 2637 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2638 data = 0;
2639 }
2640 break;
15c4a640
CO		 2641 }
2642 *pdata = data;
2643 return 0;
2644}
2645EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2646
313a3dc7
CO		 2647/*
2648 * Read or write a bunch of msrs. All parameters are kernel addresses.
2649 *
2650 * @return number of msrs set successfully.
2651 */
2652static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2653 struct kvm_msr_entry *entries,
2654 int (*do_msr)(struct kvm_vcpu *vcpu,
2655 unsigned index, u64 *data))
2656{
f656ce01 2657 int i, idx;
313a3dc7 2658
f656ce01 2659 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2660 for (i = 0; i < msrs->nmsrs; ++i)
2661 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2662 break;
f656ce01 2663 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2664
313a3dc7
CO		 2665 return i;
2666}
2667
2668/*
2669 * Read or write a bunch of msrs. Parameters are user addresses.
2670 *
2671 * @return number of msrs set successfully.
2672 */
2673static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2674 int (*do_msr)(struct kvm_vcpu *vcpu,
2675 unsigned index, u64 *data),
2676 int writeback)
2677{
2678 struct kvm_msrs msrs;
2679 struct kvm_msr_entry *entries;
2680 int r, n;
2681 unsigned size;
2682
2683 r = -EFAULT;
2684 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2685 goto out;
2686
2687 r = -E2BIG;
2688 if (msrs.nmsrs >= MAX_IO_MSRS)
2689 goto out;
2690
313a3dc7 2691 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2692 entries = memdup_user(user_msrs->entries, size);
2693 if (IS_ERR(entries)) {
2694 r = PTR_ERR(entries);
313a3dc7 2695 goto out;
ff5c2c03 2696 }
313a3dc7
CO		 2697
2698 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2699 if (r < 0)
2700 goto out_free;
2701
2702 r = -EFAULT;
2703 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2704 goto out_free;
2705
2706 r = n;
2707
2708out_free:
7a73c028 2709 kfree(entries);
313a3dc7
CO		 2710out:
2711 return r;
2712}
2713
784aa3d7 2714int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2715{
2716 int r;
2717
2718 switch (ext) {
2719 case KVM_CAP_IRQCHIP:
2720 case KVM_CAP_HLT:
2721 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2722 case KVM_CAP_SET_TSS_ADDR:
07716717 2723 case KVM_CAP_EXT_CPUID:
9c15bb1d 2724 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2725 case KVM_CAP_CLOCKSOURCE:
7837699f 2726 case KVM_CAP_PIT:
a28e4f5a 2727 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2728 case KVM_CAP_MP_STATE:
ed848624 2729 case KVM_CAP_SYNC_MMU:
a355c85c 2730 case KVM_CAP_USER_NMI:
52d939a0 2731 case KVM_CAP_REINJECT_CONTROL:
4925663a 2732 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2733 case KVM_CAP_IRQFD:
d34e6b17 2734 case KVM_CAP_IOEVENTFD:
f848a5a8 2735 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2736 case KVM_CAP_PIT2:
e9f42757 2737 case KVM_CAP_PIT_STATE2:
b927a3ce 2738 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2739 case KVM_CAP_XEN_HVM:
afbcf7ab 2740 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2741 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2742 case KVM_CAP_HYPERV:
10388a07 2743 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2744 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2745 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2746 case KVM_CAP_DEBUGREGS:
d2be1651 2747 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2748 case KVM_CAP_XSAVE:
344d9588 2749 case KVM_CAP_ASYNC_PF:
92a1f12d 2750 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2751 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2752 case KVM_CAP_READONLY_MEM:
5f66b620 2753 case KVM_CAP_HYPERV_TIME:
100943c5 2754 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2755 case KVM_CAP_TSC_DEADLINE_TIMER:
2a5bab10
AW		 2756#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2757 case KVM_CAP_ASSIGN_DEV_IRQ:
2758 case KVM_CAP_PCI_2_3:
2759#endif
018d00d2
ZX		 2760 r = 1;
2761 break;
542472b5
LV		 2762 case KVM_CAP_COALESCED_MMIO:
2763 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2764 break;
774ead3a
AK		 2765 case KVM_CAP_VAPIC:
2766 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2767 break;
f725230a 2768 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2769 r = KVM_SOFT_MAX_VCPUS;
2770 break;
2771 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2772 r = KVM_MAX_VCPUS;
2773 break;
a988b910 2774 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2775 r = KVM_USER_MEM_SLOTS;
a988b910 2776 break;
a68a6a72
MT		 2777 case KVM_CAP_PV_MMU: /* obsolete */
2778 r = 0;
2f333bcb 2779 break;
4cee4b72 2780#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2781 case KVM_CAP_IOMMU:
a1b60c1c 2782 r = iommu_present(&pci_bus_type);
62c476c7 2783 break;
4cee4b72 2784#endif
890ca9ae
HY		 2785 case KVM_CAP_MCE:
2786 r = KVM_MAX_MCE_BANKS;
2787 break;
2d5b5a66
SY		 2788 case KVM_CAP_XCRS:
2789 r = cpu_has_xsave;
2790 break;
92a1f12d
JR		 2791 case KVM_CAP_TSC_CONTROL:
2792 r = kvm_has_tsc_control;
2793 break;
018d00d2
ZX		 2794 default:
2795 r = 0;
2796 break;
2797 }
2798 return r;
2799
2800}
2801
043405e1
CO		 2802long kvm_arch_dev_ioctl(struct file *filp,
2803 unsigned int ioctl, unsigned long arg)
2804{
2805 void __user *argp = (void __user *)arg;
2806 long r;
2807
2808 switch (ioctl) {
2809 case KVM_GET_MSR_INDEX_LIST: {
2810 struct kvm_msr_list __user *user_msr_list = argp;
2811 struct kvm_msr_list msr_list;
2812 unsigned n;
2813
2814 r = -EFAULT;
2815 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2816 goto out;
2817 n = msr_list.nmsrs;
2818 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2819 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2820 goto out;
2821 r = -E2BIG;
e125e7b6 2822 if (n < msr_list.nmsrs)
043405e1
CO		 2823 goto out;
2824 r = -EFAULT;
2825 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2826 num_msrs_to_save * sizeof(u32)))
2827 goto out;
e125e7b6 2828 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2829 &emulated_msrs,
2830 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2831 goto out;
2832 r = 0;
2833 break;
2834 }
9c15bb1d
BP		 2835 case KVM_GET_SUPPORTED_CPUID:
2836 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2837 struct kvm_cpuid2 __user *cpuid_arg = argp;
2838 struct kvm_cpuid2 cpuid;
2839
2840 r = -EFAULT;
2841 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2842 goto out;
9c15bb1d
BP		 2843
2844 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2845 ioctl);
674eea0f
AK		 2846 if (r)
2847 goto out;
2848
2849 r = -EFAULT;
2850 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2851 goto out;
2852 r = 0;
2853 break;
2854 }
890ca9ae
HY		 2855 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2856 u64 mce_cap;
2857
2858 mce_cap = KVM_MCE_CAP_SUPPORTED;
2859 r = -EFAULT;
2860 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2861 goto out;
2862 r = 0;
2863 break;
2864 }
043405e1
CO		 2865 default:
2866 r = -EINVAL;
2867 }
2868out:
2869 return r;
2870}
2871
f5f48ee1
SY		 2872static void wbinvd_ipi(void *garbage)
2873{
2874 wbinvd();
2875}
2876
2877static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2878{
e0f0bbc5 2879 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2880}
2881
313a3dc7
CO		 2882void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2883{
f5f48ee1
SY		 2884 /* Address WBINVD may be executed by guest */
2885 if (need_emulate_wbinvd(vcpu)) {
2886 if (kvm_x86_ops->has_wbinvd_exit())
2887 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2888 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2889 smp_call_function_single(vcpu->cpu,
2890 wbinvd_ipi, NULL, 1);
2891 }
2892
313a3dc7 2893 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2894
0dd6a6ed
ZA		 2895 /* Apply any externally detected TSC adjustments (due to suspend) */
2896 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2897 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2898 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2899 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2900 }
8f6055cb 2901
48434c20 2902 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2903 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2904 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2905 if (tsc_delta < 0)
2906 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2907 if (check_tsc_unstable()) {
b183aa58
ZA		 2908 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2909 vcpu->arch.last_guest_tsc);
2910 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2911 vcpu->arch.tsc_catchup = 1;
c285545f 2912 }
d98d07ca
MT		 2913 /*
2914 * On a host with synchronized TSC, there is no need to update
2915 * kvmclock on vcpu->cpu migration
2916 */
2917 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2918 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2919 if (vcpu->cpu != cpu)
2920 kvm_migrate_timers(vcpu);
e48672fa 2921 vcpu->cpu = cpu;
6b7d7e76 2922 }
c9aaa895
GC		 2923
2924 accumulate_steal_time(vcpu);
2925 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2926}
2927
2928void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2929{
02daab21 2930 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2931 kvm_put_guest_fpu(vcpu);
6f526ec5 2932 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2933}
2934
313a3dc7
CO		 2935static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2936 struct kvm_lapic_state *s)
2937{
5a71785d 2938 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2939 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2940
2941 return 0;
2942}
2943
2944static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2945 struct kvm_lapic_state *s)
2946{
64eb0620 2947 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2948 update_cr8_intercept(vcpu);
313a3dc7
CO		 2949
2950 return 0;
2951}
2952
f77bc6a4
ZX		 2953static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2954 struct kvm_interrupt *irq)
2955{
02cdb50f 2956 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2957 return -EINVAL;
2958 if (irqchip_in_kernel(vcpu->kvm))
2959 return -ENXIO;
f77bc6a4 2960
66fd3f7f 2961 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2962 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2963
f77bc6a4
ZX		 2964 return 0;
2965}
2966
c4abb7c9
JK		 2967static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2968{
c4abb7c9 2969 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2970
2971 return 0;
2972}
2973
b209749f
AK		 2974static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2975 struct kvm_tpr_access_ctl *tac)
2976{
2977 if (tac->flags)
2978 return -EINVAL;
2979 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2980 return 0;
2981}
2982
890ca9ae
HY		 2983static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2984 u64 mcg_cap)
2985{
2986 int r;
2987 unsigned bank_num = mcg_cap & 0xff, bank;
2988
2989 r = -EINVAL;
a9e38c3e 2990 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2991 goto out;
2992 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2993 goto out;
2994 r = 0;
2995 vcpu->arch.mcg_cap = mcg_cap;
2996 /* Init IA32_MCG_CTL to all 1s */
2997 if (mcg_cap & MCG_CTL_P)
2998 vcpu->arch.mcg_ctl = ~(u64)0;
2999 /* Init IA32_MCi_CTL to all 1s */
3000 for (bank = 0; bank < bank_num; bank++)
3001 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3002out:
3003 return r;
3004}
3005
3006static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3007 struct kvm_x86_mce *mce)
3008{
3009 u64 mcg_cap = vcpu->arch.mcg_cap;
3010 unsigned bank_num = mcg_cap & 0xff;
3011 u64 *banks = vcpu->arch.mce_banks;
3012
3013 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3014 return -EINVAL;
3015 /*
3016 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3017 * reporting is disabled
3018 */
3019 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3020 vcpu->arch.mcg_ctl != ~(u64)0)
3021 return 0;
3022 banks += 4 * mce->bank;
3023 /*
3024 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3025 * reporting is disabled for the bank
3026 */
3027 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3028 return 0;
3029 if (mce->status & MCI_STATUS_UC) {
3030 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3031 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3032 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3033 return 0;
3034 }
3035 if (banks[1] & MCI_STATUS_VAL)
3036 mce->status |= MCI_STATUS_OVER;
3037 banks[2] = mce->addr;
3038 banks[3] = mce->misc;
3039 vcpu->arch.mcg_status = mce->mcg_status;
3040 banks[1] = mce->status;
3041 kvm_queue_exception(vcpu, MC_VECTOR);
3042 } else if (!(banks[1] & MCI_STATUS_VAL)
3043 || !(banks[1] & MCI_STATUS_UC)) {
3044 if (banks[1] & MCI_STATUS_VAL)
3045 mce->status |= MCI_STATUS_OVER;
3046 banks[2] = mce->addr;
3047 banks[3] = mce->misc;
3048 banks[1] = mce->status;
3049 } else
3050 banks[1] |= MCI_STATUS_OVER;
3051 return 0;
3052}
3053
3cfc3092
JK		 3054static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3055 struct kvm_vcpu_events *events)
3056{
7460fb4a 3057 process_nmi(vcpu);
03b82a30
JK		 3058 events->exception.injected =
3059 vcpu->arch.exception.pending &&
3060 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3061 events->exception.nr = vcpu->arch.exception.nr;
3062 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3063 events->exception.pad = 0;
3cfc3092
JK		 3064 events->exception.error_code = vcpu->arch.exception.error_code;
3065
03b82a30
JK		 3066 events->interrupt.injected =
3067 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3068 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3069 events->interrupt.soft = 0;
37ccdcbe 3070 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3071
3072 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3073 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3074 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3075 events->nmi.pad = 0;
3cfc3092 3076
66450a21 3077 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3078
dab4b911 3079 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3080 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3081 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3082}
3083
3084static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3085 struct kvm_vcpu_events *events)
3086{
dab4b911 3087 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3088 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3089 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3090 return -EINVAL;
3091
7460fb4a 3092 process_nmi(vcpu);
3cfc3092
JK		 3093 vcpu->arch.exception.pending = events->exception.injected;
3094 vcpu->arch.exception.nr = events->exception.nr;
3095 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3096 vcpu->arch.exception.error_code = events->exception.error_code;
3097
3098 vcpu->arch.interrupt.pending = events->interrupt.injected;
3099 vcpu->arch.interrupt.nr = events->interrupt.nr;
3100 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3101 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3102 kvm_x86_ops->set_interrupt_shadow(vcpu,
3103 events->interrupt.shadow);
3cfc3092
JK		 3104
3105 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3106 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3107 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3108 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3109
66450a21
JK		 3110 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3111 kvm_vcpu_has_lapic(vcpu))
3112 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3113
3842d135
AK		 3114 kvm_make_request(KVM_REQ_EVENT, vcpu);
3115
3cfc3092
JK		 3116 return 0;
3117}
3118
a1efbe77
JK		 3119static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3120 struct kvm_debugregs *dbgregs)
3121{
73aaf249
JK		 3122 unsigned long val;
3123
a1efbe77 3124 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3125 kvm_get_dr(vcpu, 6, &val);
73aaf249 3126 dbgregs->dr6 = val;
a1efbe77
JK		 3127 dbgregs->dr7 = vcpu->arch.dr7;
3128 dbgregs->flags = 0;
97e69aa6 3129 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3130}
3131
3132static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3133 struct kvm_debugregs *dbgregs)
3134{
3135 if (dbgregs->flags)
3136 return -EINVAL;
3137
a1efbe77
JK		 3138 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3139 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3140 kvm_update_dr6(vcpu);
a1efbe77 3141 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3142 kvm_update_dr7(vcpu);
a1efbe77 3143
a1efbe77
JK		 3144 return 0;
3145}
3146
df1daba7
PB		 3147#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3148
3149static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3150{
3151 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3152 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3153 u64 valid;
3154
3155 /*
3156 * Copy legacy XSAVE area, to avoid complications with CPUID
3157 * leaves 0 and 1 in the loop below.
3158 */
3159 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3160
3161 /* Set XSTATE_BV */
3162 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3163
3164 /*
3165 * Copy each region from the possibly compacted offset to the
3166 * non-compacted offset.
3167 */
3168 valid = xstate_bv & ~XSTATE_FPSSE;
3169 while (valid) {
3170 u64 feature = valid & -valid;
3171 int index = fls64(feature) - 1;
3172 void *src = get_xsave_addr(xsave, feature);
3173
3174 if (src) {
3175 u32 size, offset, ecx, edx;
3176 cpuid_count(XSTATE_CPUID, index,
3177 &size, &offset, &ecx, &edx);
3178 memcpy(dest + offset, src, size);
3179 }
3180
3181 valid -= feature;
3182 }
3183}
3184
3185static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3186{
3187 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3188 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3189 u64 valid;
3190
3191 /*
3192 * Copy legacy XSAVE area, to avoid complications with CPUID
3193 * leaves 0 and 1 in the loop below.
3194 */
3195 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3196
3197 /* Set XSTATE_BV and possibly XCOMP_BV. */
3198 xsave->xsave_hdr.xstate_bv = xstate_bv;
3199 if (cpu_has_xsaves)
3200 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3201
3202 /*
3203 * Copy each region from the non-compacted offset to the
3204 * possibly compacted offset.
3205 */
3206 valid = xstate_bv & ~XSTATE_FPSSE;
3207 while (valid) {
3208 u64 feature = valid & -valid;
3209 int index = fls64(feature) - 1;
3210 void *dest = get_xsave_addr(xsave, feature);
3211
3212 if (dest) {
3213 u32 size, offset, ecx, edx;
3214 cpuid_count(XSTATE_CPUID, index,
3215 &size, &offset, &ecx, &edx);
3216 memcpy(dest, src + offset, size);
3217 } else
3218 WARN_ON_ONCE(1);
3219
3220 valid -= feature;
3221 }
3222}
3223
2d5b5a66
SY		 3224static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3225 struct kvm_xsave *guest_xsave)
3226{
4344ee98 3227 if (cpu_has_xsave) {
df1daba7
PB		 3228 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3229 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3230 } else {
2d5b5a66
SY		 3231 memcpy(guest_xsave->region,
3232 &vcpu->arch.guest_fpu.state->fxsave,
3233 sizeof(struct i387_fxsave_struct));
3234 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3235 XSTATE_FPSSE;
3236 }
3237}
3238
3239static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3240 struct kvm_xsave *guest_xsave)
3241{
3242 u64 xstate_bv =
3243 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3244
d7876f1b
PB		 3245 if (cpu_has_xsave) {
3246 /*
3247 * Here we allow setting states that are not present in
3248 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3249 * with old userspace.
3250 */
4ff41732 3251 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3252 return -EINVAL;
df1daba7 3253 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3254 } else {
2d5b5a66
SY		 3255 if (xstate_bv & ~XSTATE_FPSSE)
3256 return -EINVAL;
3257 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3258 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3259 }
3260 return 0;
3261}
3262
3263static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3264 struct kvm_xcrs *guest_xcrs)
3265{
3266 if (!cpu_has_xsave) {
3267 guest_xcrs->nr_xcrs = 0;
3268 return;
3269 }
3270
3271 guest_xcrs->nr_xcrs = 1;
3272 guest_xcrs->flags = 0;
3273 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3274 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3275}
3276
3277static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3278 struct kvm_xcrs *guest_xcrs)
3279{
3280 int i, r = 0;
3281
3282 if (!cpu_has_xsave)
3283 return -EINVAL;
3284
3285 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3286 return -EINVAL;
3287
3288 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3289 /* Only support XCR0 currently */
c67a04cb 3290 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3291 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3292 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3293 break;
3294 }
3295 if (r)
3296 r = -EINVAL;
3297 return r;
3298}
3299
1c0b28c2
EM		 3300/*
3301 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3302 * stopped by the hypervisor. This function will be called from the host only.
3303 * EINVAL is returned when the host attempts to set the flag for a guest that
3304 * does not support pv clocks.
3305 */
3306static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3307{
0b79459b 3308 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3309 return -EINVAL;
51d59c6b 3310 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3311 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3312 return 0;
3313}
3314
313a3dc7
CO		 3315long kvm_arch_vcpu_ioctl(struct file *filp,
3316 unsigned int ioctl, unsigned long arg)
3317{
3318 struct kvm_vcpu *vcpu = filp->private_data;
3319 void __user *argp = (void __user *)arg;
3320 int r;
d1ac91d8
AK		 3321 union {
3322 struct kvm_lapic_state *lapic;
3323 struct kvm_xsave *xsave;
3324 struct kvm_xcrs *xcrs;
3325 void *buffer;
3326 } u;
3327
3328 u.buffer = NULL;
313a3dc7
CO		 3329 switch (ioctl) {
3330 case KVM_GET_LAPIC: {
2204ae3c
MT		 3331 r = -EINVAL;
3332 if (!vcpu->arch.apic)
3333 goto out;
d1ac91d8 3334 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3335
b772ff36 3336 r = -ENOMEM;
d1ac91d8 3337 if (!u.lapic)
b772ff36 3338 goto out;
d1ac91d8 3339 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3340 if (r)
3341 goto out;
3342 r = -EFAULT;
d1ac91d8 3343 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3344 goto out;
3345 r = 0;
3346 break;
3347 }
3348 case KVM_SET_LAPIC: {
2204ae3c
MT		 3349 r = -EINVAL;
3350 if (!vcpu->arch.apic)
3351 goto out;
ff5c2c03 3352 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3353 if (IS_ERR(u.lapic))
3354 return PTR_ERR(u.lapic);
ff5c2c03 3355
d1ac91d8 3356 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3357 break;
3358 }
f77bc6a4
ZX		 3359 case KVM_INTERRUPT: {
3360 struct kvm_interrupt irq;
3361
3362 r = -EFAULT;
3363 if (copy_from_user(&irq, argp, sizeof irq))
3364 goto out;
3365 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3366 break;
3367 }
c4abb7c9
JK		 3368 case KVM_NMI: {
3369 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3370 break;
3371 }
313a3dc7
CO		 3372 case KVM_SET_CPUID: {
3373 struct kvm_cpuid __user *cpuid_arg = argp;
3374 struct kvm_cpuid cpuid;
3375
3376 r = -EFAULT;
3377 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3378 goto out;
3379 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3380 break;
3381 }
07716717
DK		 3382 case KVM_SET_CPUID2: {
3383 struct kvm_cpuid2 __user *cpuid_arg = argp;
3384 struct kvm_cpuid2 cpuid;
3385
3386 r = -EFAULT;
3387 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3388 goto out;
3389 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3390 cpuid_arg->entries);
07716717
DK		 3391 break;
3392 }
3393 case KVM_GET_CPUID2: {
3394 struct kvm_cpuid2 __user *cpuid_arg = argp;
3395 struct kvm_cpuid2 cpuid;
3396
3397 r = -EFAULT;
3398 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3399 goto out;
3400 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3401 cpuid_arg->entries);
07716717
DK		 3402 if (r)
3403 goto out;
3404 r = -EFAULT;
3405 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3406 goto out;
3407 r = 0;
3408 break;
3409 }
313a3dc7
CO		 3410 case KVM_GET_MSRS:
3411 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3412 break;
3413 case KVM_SET_MSRS:
3414 r = msr_io(vcpu, argp, do_set_msr, 0);
3415 break;
b209749f
AK		 3416 case KVM_TPR_ACCESS_REPORTING: {
3417 struct kvm_tpr_access_ctl tac;
3418
3419 r = -EFAULT;
3420 if (copy_from_user(&tac, argp, sizeof tac))
3421 goto out;
3422 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3423 if (r)
3424 goto out;
3425 r = -EFAULT;
3426 if (copy_to_user(argp, &tac, sizeof tac))
3427 goto out;
3428 r = 0;
3429 break;
3430 };
b93463aa
AK		 3431 case KVM_SET_VAPIC_ADDR: {
3432 struct kvm_vapic_addr va;
3433
3434 r = -EINVAL;
3435 if (!irqchip_in_kernel(vcpu->kvm))
3436 goto out;
3437 r = -EFAULT;
3438 if (copy_from_user(&va, argp, sizeof va))
3439 goto out;
fda4e2e8 3440 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3441 break;
3442 }
890ca9ae
HY		 3443 case KVM_X86_SETUP_MCE: {
3444 u64 mcg_cap;
3445
3446 r = -EFAULT;
3447 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3448 goto out;
3449 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3450 break;
3451 }
3452 case KVM_X86_SET_MCE: {
3453 struct kvm_x86_mce mce;
3454
3455 r = -EFAULT;
3456 if (copy_from_user(&mce, argp, sizeof mce))
3457 goto out;
3458 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3459 break;
3460 }
3cfc3092
JK		 3461 case KVM_GET_VCPU_EVENTS: {
3462 struct kvm_vcpu_events events;
3463
3464 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3465
3466 r = -EFAULT;
3467 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3468 break;
3469 r = 0;
3470 break;
3471 }
3472 case KVM_SET_VCPU_EVENTS: {
3473 struct kvm_vcpu_events events;
3474
3475 r = -EFAULT;
3476 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3477 break;
3478
3479 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3480 break;
3481 }
a1efbe77
JK		 3482 case KVM_GET_DEBUGREGS: {
3483 struct kvm_debugregs dbgregs;
3484
3485 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3486
3487 r = -EFAULT;
3488 if (copy_to_user(argp, &dbgregs,
3489 sizeof(struct kvm_debugregs)))
3490 break;
3491 r = 0;
3492 break;
3493 }
3494 case KVM_SET_DEBUGREGS: {
3495 struct kvm_debugregs dbgregs;
3496
3497 r = -EFAULT;
3498 if (copy_from_user(&dbgregs, argp,
3499 sizeof(struct kvm_debugregs)))
3500 break;
3501
3502 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3503 break;
3504 }
2d5b5a66 3505 case KVM_GET_XSAVE: {
d1ac91d8 3506 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3507 r = -ENOMEM;
d1ac91d8 3508 if (!u.xsave)
2d5b5a66
SY		 3509 break;
3510
d1ac91d8 3511 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3512
3513 r = -EFAULT;
d1ac91d8 3514 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3515 break;
3516 r = 0;
3517 break;
3518 }
3519 case KVM_SET_XSAVE: {
ff5c2c03 3520 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3521 if (IS_ERR(u.xsave))
3522 return PTR_ERR(u.xsave);
2d5b5a66 3523
d1ac91d8 3524 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3525 break;
3526 }
3527 case KVM_GET_XCRS: {
d1ac91d8 3528 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3529 r = -ENOMEM;
d1ac91d8 3530 if (!u.xcrs)
2d5b5a66
SY		 3531 break;
3532
d1ac91d8 3533 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3534
3535 r = -EFAULT;
d1ac91d8 3536 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3537 sizeof(struct kvm_xcrs)))
3538 break;
3539 r = 0;
3540 break;
3541 }
3542 case KVM_SET_XCRS: {
ff5c2c03 3543 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3544 if (IS_ERR(u.xcrs))
3545 return PTR_ERR(u.xcrs);
2d5b5a66 3546
d1ac91d8 3547 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3548 break;
3549 }
92a1f12d
JR		 3550 case KVM_SET_TSC_KHZ: {
3551 u32 user_tsc_khz;
3552
3553 r = -EINVAL;
92a1f12d
JR		 3554 user_tsc_khz = (u32)arg;
3555
3556 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3557 goto out;
3558
cc578287
ZA		 3559 if (user_tsc_khz == 0)
3560 user_tsc_khz = tsc_khz;
3561
3562 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3563
3564 r = 0;
3565 goto out;
3566 }
3567 case KVM_GET_TSC_KHZ: {
cc578287 3568 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3569 goto out;
3570 }
1c0b28c2
EM		 3571 case KVM_KVMCLOCK_CTRL: {
3572 r = kvm_set_guest_paused(vcpu);
3573 goto out;
3574 }
313a3dc7
CO		 3575 default:
3576 r = -EINVAL;
3577 }
3578out:
d1ac91d8 3579 kfree(u.buffer);
313a3dc7
CO		 3580 return r;
3581}
3582
5b1c1493
CO		 3583int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3584{
3585 return VM_FAULT_SIGBUS;
3586}
3587
1fe779f8
CO		 3588static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3589{
3590 int ret;
3591
3592 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3593 return -EINVAL;
1fe779f8
CO		 3594 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3595 return ret;
3596}
3597
b927a3ce
SY		 3598static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3599 u64 ident_addr)
3600{
3601 kvm->arch.ept_identity_map_addr = ident_addr;
3602 return 0;
3603}
3604
1fe779f8
CO		 3605static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3606 u32 kvm_nr_mmu_pages)
3607{
3608 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3609 return -EINVAL;
3610
79fac95e 3611 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3612
3613 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3614 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3615
79fac95e 3616 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3617 return 0;
3618}
3619
3620static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3621{
39de71ec 3622 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3623}
3624
1fe779f8
CO		 3625static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3626{
3627 int r;
3628
3629 r = 0;
3630 switch (chip->chip_id) {
3631 case KVM_IRQCHIP_PIC_MASTER:
3632 memcpy(&chip->chip.pic,
3633 &pic_irqchip(kvm)->pics[0],
3634 sizeof(struct kvm_pic_state));
3635 break;
3636 case KVM_IRQCHIP_PIC_SLAVE:
3637 memcpy(&chip->chip.pic,
3638 &pic_irqchip(kvm)->pics[1],
3639 sizeof(struct kvm_pic_state));
3640 break;
3641 case KVM_IRQCHIP_IOAPIC:
eba0226b 3642 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3643 break;
3644 default:
3645 r = -EINVAL;
3646 break;
3647 }
3648 return r;
3649}
3650
3651static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3652{
3653 int r;
3654
3655 r = 0;
3656 switch (chip->chip_id) {
3657 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3658 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3659 memcpy(&pic_irqchip(kvm)->pics[0],
3660 &chip->chip.pic,
3661 sizeof(struct kvm_pic_state));
f4f51050 3662 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3663 break;
3664 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3665 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3666 memcpy(&pic_irqchip(kvm)->pics[1],
3667 &chip->chip.pic,
3668 sizeof(struct kvm_pic_state));
f4f51050 3669 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3670 break;
3671 case KVM_IRQCHIP_IOAPIC:
eba0226b 3672 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3673 break;
3674 default:
3675 r = -EINVAL;
3676 break;
3677 }
3678 kvm_pic_update_irq(pic_irqchip(kvm));
3679 return r;
3680}
3681
e0f63cb9
SY		 3682static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3683{
3684 int r = 0;
3685
894a9c55 3686 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3687 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3688 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3689 return r;
3690}
3691
3692static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3693{
3694 int r = 0;
3695
894a9c55 3696 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3697 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3698 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3699 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3700 return r;
3701}
3702
3703static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3704{
3705 int r = 0;
3706
3707 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3708 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3709 sizeof(ps->channels));
3710 ps->flags = kvm->arch.vpit->pit_state.flags;
3711 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3712 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3713 return r;
3714}
3715
3716static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3717{
3718 int r = 0, start = 0;
3719 u32 prev_legacy, cur_legacy;
3720 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3721 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3722 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3723 if (!prev_legacy && cur_legacy)
3724 start = 1;
3725 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3726 sizeof(kvm->arch.vpit->pit_state.channels));
3727 kvm->arch.vpit->pit_state.flags = ps->flags;
3728 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3729 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3730 return r;
3731}
3732
52d939a0
MT		 3733static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3734 struct kvm_reinject_control *control)
3735{
3736 if (!kvm->arch.vpit)
3737 return -ENXIO;
894a9c55 3738 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3739 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3740 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3741 return 0;
3742}
3743
95d4c16c 3744/**
60c34612
TY		 3745 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3746 * @kvm: kvm instance
3747 * @log: slot id and address to which we copy the log
95d4c16c 3748 *
60c34612
TY		 3749 * We need to keep it in mind that VCPU threads can write to the bitmap
3750 * concurrently. So, to avoid losing data, we keep the following order for
3751 * each bit:
95d4c16c 3752 *
60c34612
TY		 3753 * 1. Take a snapshot of the bit and clear it if needed.
3754 * 2. Write protect the corresponding page.
3755 * 3. Flush TLB's if needed.
3756 * 4. Copy the snapshot to the userspace.
95d4c16c 3757 *
60c34612
TY		 3758 * Between 2 and 3, the guest may write to the page using the remaining TLB
3759 * entry. This is not a problem because the page will be reported dirty at
3760 * step 4 using the snapshot taken before and step 3 ensures that successive
3761 * writes will be logged for the next call.
5bb064dc 3762 */
60c34612 3763int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3764{
7850ac54 3765 int r;
5bb064dc 3766 struct kvm_memory_slot *memslot;
60c34612
TY		 3767 unsigned long n, i;
3768 unsigned long *dirty_bitmap;
3769 unsigned long *dirty_bitmap_buffer;
3770 bool is_dirty = false;
5bb064dc 3771
79fac95e 3772 mutex_lock(&kvm->slots_lock);
5bb064dc 3773
b050b015 3774 r = -EINVAL;
bbacc0c1 3775 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3776 goto out;
3777
28a37544 3778 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3779
3780 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3781 r = -ENOENT;
60c34612 3782 if (!dirty_bitmap)
b050b015
MT		 3783 goto out;
3784
87bf6e7d 3785 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3786
60c34612
TY		 3787 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3788 memset(dirty_bitmap_buffer, 0, n);
b050b015 3789
60c34612 3790 spin_lock(&kvm->mmu_lock);
b050b015 3791
60c34612
TY		 3792 for (i = 0; i < n / sizeof(long); i++) {
3793 unsigned long mask;
3794 gfn_t offset;
cdfca7b3 3795
60c34612
TY		 3796 if (!dirty_bitmap[i])
3797 continue;
b050b015 3798
60c34612 3799 is_dirty = true;
914ebccd 3800
60c34612
TY		 3801 mask = xchg(&dirty_bitmap[i], 0);
3802 dirty_bitmap_buffer[i] = mask;
edde99ce 3803
60c34612
TY		 3804 offset = i * BITS_PER_LONG;
3805 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3806 }
60c34612
TY		 3807
3808 spin_unlock(&kvm->mmu_lock);
3809
198c74f4
XG		 3810 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3811 lockdep_assert_held(&kvm->slots_lock);
3812
3813 /*
3814 * All the TLBs can be flushed out of mmu lock, see the comments in
3815 * kvm_mmu_slot_remove_write_access().
3816 */
3817 if (is_dirty)
3818 kvm_flush_remote_tlbs(kvm);
3819
60c34612
TY		 3820 r = -EFAULT;
3821 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3822 goto out;
b050b015 3823
5bb064dc
ZX		 3824 r = 0;
3825out:
79fac95e 3826 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3827 return r;
3828}
3829
aa2fbe6d
YZ		 3830int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3831 bool line_status)
23d43cf9
CD		 3832{
3833 if (!irqchip_in_kernel(kvm))
3834 return -ENXIO;
3835
3836 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3837 irq_event->irq, irq_event->level,
3838 line_status);
23d43cf9
CD		 3839 return 0;
3840}
3841
1fe779f8
CO		 3842long kvm_arch_vm_ioctl(struct file *filp,
3843 unsigned int ioctl, unsigned long arg)
3844{
3845 struct kvm *kvm = filp->private_data;
3846 void __user *argp = (void __user *)arg;
367e1319 3847 int r = -ENOTTY;
f0d66275
DH		 3848 /*
3849 * This union makes it completely explicit to gcc-3.x
3850 * that these two variables' stack usage should be
3851 * combined, not added together.
3852 */
3853 union {
3854 struct kvm_pit_state ps;
e9f42757 3855 struct kvm_pit_state2 ps2;
c5ff41ce 3856 struct kvm_pit_config pit_config;
f0d66275 3857 } u;
1fe779f8
CO		 3858
3859 switch (ioctl) {
3860 case KVM_SET_TSS_ADDR:
3861 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3862 break;
b927a3ce
SY		 3863 case KVM_SET_IDENTITY_MAP_ADDR: {
3864 u64 ident_addr;
3865
3866 r = -EFAULT;
3867 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3868 goto out;
3869 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3870 break;
3871 }
1fe779f8
CO		 3872 case KVM_SET_NR_MMU_PAGES:
3873 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3874 break;
3875 case KVM_GET_NR_MMU_PAGES:
3876 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3877 break;
3ddea128
MT		 3878 case KVM_CREATE_IRQCHIP: {
3879 struct kvm_pic *vpic;
3880
3881 mutex_lock(&kvm->lock);
3882 r = -EEXIST;
3883 if (kvm->arch.vpic)
3884 goto create_irqchip_unlock;
3e515705
AK		 3885 r = -EINVAL;
3886 if (atomic_read(&kvm->online_vcpus))
3887 goto create_irqchip_unlock;
1fe779f8 3888 r = -ENOMEM;
3ddea128
MT		 3889 vpic = kvm_create_pic(kvm);
3890 if (vpic) {
1fe779f8
CO		 3891 r = kvm_ioapic_init(kvm);
3892 if (r) {
175504cd 3893 mutex_lock(&kvm->slots_lock);
72bb2fcd 3894 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3895 &vpic->dev_master);
3896 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3897 &vpic->dev_slave);
3898 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3899 &vpic->dev_eclr);
175504cd 3900 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3901 kfree(vpic);
3902 goto create_irqchip_unlock;
1fe779f8
CO		 3903 }
3904 } else
3ddea128
MT		 3905 goto create_irqchip_unlock;
3906 smp_wmb();
3907 kvm->arch.vpic = vpic;
3908 smp_wmb();
399ec807
AK		 3909 r = kvm_setup_default_irq_routing(kvm);
3910 if (r) {
175504cd 3911 mutex_lock(&kvm->slots_lock);
3ddea128 3912 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3913 kvm_ioapic_destroy(kvm);
3914 kvm_destroy_pic(kvm);
3ddea128 3915 mutex_unlock(&kvm->irq_lock);
175504cd 3916 mutex_unlock(&kvm->slots_lock);
399ec807 3917 }
3ddea128
MT		 3918 create_irqchip_unlock:
3919 mutex_unlock(&kvm->lock);
1fe779f8 3920 break;
3ddea128 3921 }
7837699f 3922 case KVM_CREATE_PIT:
c5ff41ce
JK		 3923 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3924 goto create_pit;
3925 case KVM_CREATE_PIT2:
3926 r = -EFAULT;
3927 if (copy_from_user(&u.pit_config, argp,
3928 sizeof(struct kvm_pit_config)))
3929 goto out;
3930 create_pit:
79fac95e 3931 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3932 r = -EEXIST;
3933 if (kvm->arch.vpit)
3934 goto create_pit_unlock;
7837699f 3935 r = -ENOMEM;
c5ff41ce 3936 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3937 if (kvm->arch.vpit)
3938 r = 0;
269e05e4 3939 create_pit_unlock:
79fac95e 3940 mutex_unlock(&kvm->slots_lock);
7837699f 3941 break;
1fe779f8
CO		 3942 case KVM_GET_IRQCHIP: {
3943 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3944 struct kvm_irqchip *chip;
1fe779f8 3945
ff5c2c03
SL		 3946 chip = memdup_user(argp, sizeof(*chip));
3947 if (IS_ERR(chip)) {
3948 r = PTR_ERR(chip);
1fe779f8 3949 goto out;
ff5c2c03
SL		 3950 }
3951
1fe779f8
CO		 3952 r = -ENXIO;
3953 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3954 goto get_irqchip_out;
3955 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3956 if (r)
f0d66275 3957 goto get_irqchip_out;
1fe779f8 3958 r = -EFAULT;
f0d66275
DH		 3959 if (copy_to_user(argp, chip, sizeof *chip))
3960 goto get_irqchip_out;
1fe779f8 3961 r = 0;
f0d66275
DH		 3962 get_irqchip_out:
3963 kfree(chip);
1fe779f8
CO		 3964 break;
3965 }
3966 case KVM_SET_IRQCHIP: {
3967 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3968 struct kvm_irqchip *chip;
1fe779f8 3969
ff5c2c03
SL		 3970 chip = memdup_user(argp, sizeof(*chip));
3971 if (IS_ERR(chip)) {
3972 r = PTR_ERR(chip);
1fe779f8 3973 goto out;
ff5c2c03
SL		 3974 }
3975
1fe779f8
CO		 3976 r = -ENXIO;
3977 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3978 goto set_irqchip_out;
3979 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3980 if (r)
f0d66275 3981 goto set_irqchip_out;
1fe779f8 3982 r = 0;
f0d66275
DH		 3983 set_irqchip_out:
3984 kfree(chip);
1fe779f8
CO		 3985 break;
3986 }
e0f63cb9 3987 case KVM_GET_PIT: {
e0f63cb9 3988 r = -EFAULT;
f0d66275 3989 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3990 goto out;
3991 r = -ENXIO;
3992 if (!kvm->arch.vpit)
3993 goto out;
f0d66275 3994 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3995 if (r)
3996 goto out;
3997 r = -EFAULT;
f0d66275 3998 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3999 goto out;
4000 r = 0;
4001 break;
4002 }
4003 case KVM_SET_PIT: {
e0f63cb9 4004 r = -EFAULT;
f0d66275 4005 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4006 goto out;
4007 r = -ENXIO;
4008 if (!kvm->arch.vpit)
4009 goto out;
f0d66275 4010 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4011 break;
4012 }
e9f42757
BK		 4013 case KVM_GET_PIT2: {
4014 r = -ENXIO;
4015 if (!kvm->arch.vpit)
4016 goto out;
4017 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4018 if (r)
4019 goto out;
4020 r = -EFAULT;
4021 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4022 goto out;
4023 r = 0;
4024 break;
4025 }
4026 case KVM_SET_PIT2: {
4027 r = -EFAULT;
4028 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4029 goto out;
4030 r = -ENXIO;
4031 if (!kvm->arch.vpit)
4032 goto out;
4033 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4034 break;
4035 }
52d939a0
MT		 4036 case KVM_REINJECT_CONTROL: {
4037 struct kvm_reinject_control control;
4038 r = -EFAULT;
4039 if (copy_from_user(&control, argp, sizeof(control)))
4040 goto out;
4041 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4042 break;
4043 }
ffde22ac
ES		 4044 case KVM_XEN_HVM_CONFIG: {
4045 r = -EFAULT;
4046 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4047 sizeof(struct kvm_xen_hvm_config)))
4048 goto out;
4049 r = -EINVAL;
4050 if (kvm->arch.xen_hvm_config.flags)
4051 goto out;
4052 r = 0;
4053 break;
4054 }
afbcf7ab 4055 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4056 struct kvm_clock_data user_ns;
4057 u64 now_ns;
4058 s64 delta;
4059
4060 r = -EFAULT;
4061 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4062 goto out;
4063
4064 r = -EINVAL;
4065 if (user_ns.flags)
4066 goto out;
4067
4068 r = 0;
395c6b0a 4069 local_irq_disable();
759379dd 4070 now_ns = get_kernel_ns();
afbcf7ab 4071 delta = user_ns.clock - now_ns;
395c6b0a 4072 local_irq_enable();
afbcf7ab 4073 kvm->arch.kvmclock_offset = delta;
2e762ff7 4074 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4075 break;
4076 }
4077 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4078 struct kvm_clock_data user_ns;
4079 u64 now_ns;
4080
395c6b0a 4081 local_irq_disable();
759379dd 4082 now_ns = get_kernel_ns();
afbcf7ab 4083 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4084 local_irq_enable();
afbcf7ab 4085 user_ns.flags = 0;
97e69aa6 4086 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4087
4088 r = -EFAULT;
4089 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4090 goto out;
4091 r = 0;
4092 break;
4093 }
4094
1fe779f8 4095 default:
c274e03a 4096 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4097 }
4098out:
4099 return r;
4100}
4101
a16b043c 4102static void kvm_init_msr_list(void)
043405e1
CO		 4103{
4104 u32 dummy[2];
4105 unsigned i, j;
4106
e3267cbb
GC		 4107 /* skip the first msrs in the list. KVM-specific */
4108 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4109 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4110 continue;
93c4adc7
PB		 4111
4112 /*
4113 * Even MSRs that are valid in the host may not be exposed
4114 * to the guests in some cases. We could work around this
4115 * in VMX with the generic MSR save/load machinery, but it
4116 * is not really worthwhile since it will really only
4117 * happen with nested virtualization.
4118 */
4119 switch (msrs_to_save[i]) {
4120 case MSR_IA32_BNDCFGS:
4121 if (!kvm_x86_ops->mpx_supported())
4122 continue;
4123 break;
4124 default:
4125 break;
4126 }
4127
043405e1
CO		 4128 if (j < i)
4129 msrs_to_save[j] = msrs_to_save[i];
4130 j++;
4131 }
4132 num_msrs_to_save = j;
4133}
4134
bda9020e
MT		 4135static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4136 const void *v)
bbd9b64e 4137{
70252a10
AK		 4138 int handled = 0;
4139 int n;
4140
4141 do {
4142 n = min(len, 8);
4143 if (!(vcpu->arch.apic &&
4144 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4145 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4146 break;
4147 handled += n;
4148 addr += n;
4149 len -= n;
4150 v += n;
4151 } while (len);
bbd9b64e 4152
70252a10 4153 return handled;
bbd9b64e
CO		 4154}
4155
bda9020e 4156static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4157{
70252a10
AK		 4158 int handled = 0;
4159 int n;
4160
4161 do {
4162 n = min(len, 8);
4163 if (!(vcpu->arch.apic &&
4164 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4165 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4166 break;
4167 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4168 handled += n;
4169 addr += n;
4170 len -= n;
4171 v += n;
4172 } while (len);
bbd9b64e 4173
70252a10 4174 return handled;
bbd9b64e
CO		 4175}
4176
2dafc6c2
GN		 4177static void kvm_set_segment(struct kvm_vcpu *vcpu,
4178 struct kvm_segment *var, int seg)
4179{
4180 kvm_x86_ops->set_segment(vcpu, var, seg);
4181}
4182
4183void kvm_get_segment(struct kvm_vcpu *vcpu,
4184 struct kvm_segment *var, int seg)
4185{
4186 kvm_x86_ops->get_segment(vcpu, var, seg);
4187}
4188
54987b7a
PB		 4189gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4190 struct x86_exception *exception)
02f59dc9
JR		 4191{
4192 gpa_t t_gpa;
02f59dc9
JR		 4193
4194 BUG_ON(!mmu_is_nested(vcpu));
4195
4196 /* NPT walks are always user-walks */
4197 access |= PFERR_USER_MASK;
54987b7a 4198 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4199
4200 return t_gpa;
4201}
4202
ab9ae313
AK		 4203gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4204 struct x86_exception *exception)
1871c602
GN		 4205{
4206 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4207 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4208}
4209
ab9ae313
AK		 4210 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4211 struct x86_exception *exception)
1871c602
GN		 4212{
4213 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4214 access |= PFERR_FETCH_MASK;
ab9ae313 4215 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4216}
4217
ab9ae313
AK		 4218gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4219 struct x86_exception *exception)
1871c602
GN		 4220{
4221 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4222 access |= PFERR_WRITE_MASK;
ab9ae313 4223 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4224}
4225
4226/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4227gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4228 struct x86_exception *exception)
1871c602 4229{
ab9ae313 4230 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4231}
4232
4233static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4234 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4235 struct x86_exception *exception)
bbd9b64e
CO		 4236{
4237 void *data = val;
10589a46 4238 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4239
4240 while (bytes) {
14dfe855 4241 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4242 exception);
bbd9b64e 4243 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4244 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4245 int ret;
4246
bcc55cba 4247 if (gpa == UNMAPPED_GVA)
ab9ae313 4248 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4249 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4250 offset, toread);
10589a46 4251 if (ret < 0) {
c3cd7ffa 4252 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4253 goto out;
4254 }
bbd9b64e 4255
77c2002e
IE		 4256 bytes -= toread;
4257 data += toread;
4258 addr += toread;
bbd9b64e 4259 }
10589a46 4260out:
10589a46 4261 return r;
bbd9b64e 4262}
77c2002e 4263
1871c602 4264/* used for instruction fetching */
0f65dd70
AK		 4265static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4266 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4267 struct x86_exception *exception)
1871c602 4268{
0f65dd70 4269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4270 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4271 unsigned offset;
4272 int ret;
0f65dd70 4273
44583cba
PB		 4274 /* Inline kvm_read_guest_virt_helper for speed. */
4275 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4276 exception);
4277 if (unlikely(gpa == UNMAPPED_GVA))
4278 return X86EMUL_PROPAGATE_FAULT;
4279
4280 offset = addr & (PAGE_SIZE-1);
4281 if (WARN_ON(offset + bytes > PAGE_SIZE))
4282 bytes = (unsigned)PAGE_SIZE - offset;
4283 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4284 offset, bytes);
4285 if (unlikely(ret < 0))
4286 return X86EMUL_IO_NEEDED;
4287
4288 return X86EMUL_CONTINUE;
1871c602
GN		 4289}
4290
064aea77 4291int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4292 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4293 struct x86_exception *exception)
1871c602 4294{
0f65dd70 4295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4296 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4297
1871c602 4298 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4299 exception);
1871c602 4300}
064aea77 4301EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4302
0f65dd70
AK		 4303static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4304 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4305 struct x86_exception *exception)
1871c602 4306{
0f65dd70 4307 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4308 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4309}
4310
6a4d7550 4311int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4312 gva_t addr, void *val,
2dafc6c2 4313 unsigned int bytes,
bcc55cba 4314 struct x86_exception *exception)
77c2002e 4315{
0f65dd70 4316 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4317 void *data = val;
4318 int r = X86EMUL_CONTINUE;
4319
4320 while (bytes) {
14dfe855
JR		 4321 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4322 PFERR_WRITE_MASK,
ab9ae313 4323 exception);
77c2002e
IE		 4324 unsigned offset = addr & (PAGE_SIZE-1);
4325 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4326 int ret;
4327
bcc55cba 4328 if (gpa == UNMAPPED_GVA)
ab9ae313 4329 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4330 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4331 if (ret < 0) {
c3cd7ffa 4332 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4333 goto out;
4334 }
4335
4336 bytes -= towrite;
4337 data += towrite;
4338 addr += towrite;
4339 }
4340out:
4341 return r;
4342}
6a4d7550 4343EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4344
af7cc7d1
XG		 4345static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4346 gpa_t *gpa, struct x86_exception *exception,
4347 bool write)
4348{
97d64b78
AK		 4349 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4350 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4351
97d64b78 4352 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4353 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4354 vcpu->arch.access, access)) {
bebb106a
XG		 4355 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4356 (gva & (PAGE_SIZE - 1));
4f022648 4357 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4358 return 1;
4359 }
4360
af7cc7d1
XG		 4361 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4362
4363 if (*gpa == UNMAPPED_GVA)
4364 return -1;
4365
4366 /* For APIC access vmexit */
4367 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4368 return 1;
4369
4f022648
XG		 4370 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4371 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4372 return 1;
4f022648 4373 }
bebb106a 4374
af7cc7d1
XG		 4375 return 0;
4376}
4377
3200f405 4378int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4379 const void *val, int bytes)
bbd9b64e
CO		 4380{
4381 int ret;
4382
4383 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4384 if (ret < 0)
bbd9b64e 4385 return 0;
f57f2ef5 4386 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4387 return 1;
4388}
4389
77d197b2
XG		 4390struct read_write_emulator_ops {
4391 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4392 int bytes);
4393 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4394 void *val, int bytes);
4395 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4396 int bytes, void *val);
4397 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4398 void *val, int bytes);
4399 bool write;
4400};
4401
4402static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4403{
4404 if (vcpu->mmio_read_completed) {
77d197b2 4405 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4406 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4407 vcpu->mmio_read_completed = 0;
4408 return 1;
4409 }
4410
4411 return 0;
4412}
4413
4414static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4415 void *val, int bytes)
4416{
4417 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4418}
4419
4420static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 void *val, int bytes)
4422{
4423 return emulator_write_phys(vcpu, gpa, val, bytes);
4424}
4425
4426static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4427{
4428 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4429 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4430}
4431
4432static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4433 void *val, int bytes)
4434{
4435 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4436 return X86EMUL_IO_NEEDED;
4437}
4438
4439static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4440 void *val, int bytes)
4441{
f78146b0
AK		 4442 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4443
87da7e66 4444 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4445 return X86EMUL_CONTINUE;
4446}
4447
0fbe9b0b 4448static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4449 .read_write_prepare = read_prepare,
4450 .read_write_emulate = read_emulate,
4451 .read_write_mmio = vcpu_mmio_read,
4452 .read_write_exit_mmio = read_exit_mmio,
4453};
4454
0fbe9b0b 4455static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4456 .read_write_emulate = write_emulate,
4457 .read_write_mmio = write_mmio,
4458 .read_write_exit_mmio = write_exit_mmio,
4459 .write = true,
4460};
4461
22388a3c
XG		 4462static int emulator_read_write_onepage(unsigned long addr, void *val,
4463 unsigned int bytes,
4464 struct x86_exception *exception,
4465 struct kvm_vcpu *vcpu,
0fbe9b0b 4466 const struct read_write_emulator_ops *ops)
bbd9b64e 4467{
af7cc7d1
XG		 4468 gpa_t gpa;
4469 int handled, ret;
22388a3c 4470 bool write = ops->write;
f78146b0 4471 struct kvm_mmio_fragment *frag;
10589a46 4472
22388a3c 4473 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4474
af7cc7d1 4475 if (ret < 0)
bbd9b64e 4476 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4477
4478 /* For APIC access vmexit */
af7cc7d1 4479 if (ret)
bbd9b64e
CO		 4480 goto mmio;
4481
22388a3c 4482 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4483 return X86EMUL_CONTINUE;
4484
4485mmio:
4486 /*
4487 * Is this MMIO handled locally?
4488 */
22388a3c 4489 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4490 if (handled == bytes)
bbd9b64e 4491 return X86EMUL_CONTINUE;
bbd9b64e 4492
70252a10
AK		 4493 gpa += handled;
4494 bytes -= handled;
4495 val += handled;
4496
87da7e66
XG		 4497 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4498 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4499 frag->gpa = gpa;
4500 frag->data = val;
4501 frag->len = bytes;
f78146b0 4502 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4503}
4504
22388a3c
XG		 4505int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4506 void *val, unsigned int bytes,
4507 struct x86_exception *exception,
0fbe9b0b 4508 const struct read_write_emulator_ops *ops)
bbd9b64e 4509{
0f65dd70 4510 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4511 gpa_t gpa;
4512 int rc;
4513
4514 if (ops->read_write_prepare &&
4515 ops->read_write_prepare(vcpu, val, bytes))
4516 return X86EMUL_CONTINUE;
4517
4518 vcpu->mmio_nr_fragments = 0;
0f65dd70 4519
bbd9b64e
CO		 4520 /* Crossing a page boundary? */
4521 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4522 int now;
bbd9b64e
CO		 4523
4524 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4525 rc = emulator_read_write_onepage(addr, val, now, exception,
4526 vcpu, ops);
4527
bbd9b64e
CO		 4528 if (rc != X86EMUL_CONTINUE)
4529 return rc;
4530 addr += now;
4531 val += now;
4532 bytes -= now;
4533 }
22388a3c 4534
f78146b0
AK		 4535 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4536 vcpu, ops);
4537 if (rc != X86EMUL_CONTINUE)
4538 return rc;
4539
4540 if (!vcpu->mmio_nr_fragments)
4541 return rc;
4542
4543 gpa = vcpu->mmio_fragments[0].gpa;
4544
4545 vcpu->mmio_needed = 1;
4546 vcpu->mmio_cur_fragment = 0;
4547
87da7e66 4548 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4549 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4550 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4551 vcpu->run->mmio.phys_addr = gpa;
4552
4553 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4554}
4555
4556static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4557 unsigned long addr,
4558 void *val,
4559 unsigned int bytes,
4560 struct x86_exception *exception)
4561{
4562 return emulator_read_write(ctxt, addr, val, bytes,
4563 exception, &read_emultor);
4564}
4565
4566int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4567 unsigned long addr,
4568 const void *val,
4569 unsigned int bytes,
4570 struct x86_exception *exception)
4571{
4572 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4573 exception, &write_emultor);
bbd9b64e 4574}
bbd9b64e 4575
daea3e73
AK		 4576#define CMPXCHG_TYPE(t, ptr, old, new) \
4577 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4578
4579#ifdef CONFIG_X86_64
4580# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4581#else
4582# define CMPXCHG64(ptr, old, new) \
9749a6c0 4583 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4584#endif
4585
0f65dd70
AK		 4586static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4587 unsigned long addr,
bbd9b64e
CO		 4588 const void *old,
4589 const void *new,
4590 unsigned int bytes,
0f65dd70 4591 struct x86_exception *exception)
bbd9b64e 4592{
0f65dd70 4593 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4594 gpa_t gpa;
4595 struct page *page;
4596 char *kaddr;
4597 bool exchanged;
2bacc55c 4598
daea3e73
AK		 4599 /* guests cmpxchg8b have to be emulated atomically */
4600 if (bytes > 8 || (bytes & (bytes - 1)))
4601 goto emul_write;
10589a46 4602
daea3e73 4603 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4604
daea3e73
AK		 4605 if (gpa == UNMAPPED_GVA ||
4606 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4607 goto emul_write;
2bacc55c 4608
daea3e73
AK		 4609 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4610 goto emul_write;
72dc67a6 4611
daea3e73 4612 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4613 if (is_error_page(page))
c19b8bd6 4614 goto emul_write;
72dc67a6 4615
8fd75e12 4616 kaddr = kmap_atomic(page);
daea3e73
AK		 4617 kaddr += offset_in_page(gpa);
4618 switch (bytes) {
4619 case 1:
4620 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4621 break;
4622 case 2:
4623 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4624 break;
4625 case 4:
4626 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4627 break;
4628 case 8:
4629 exchanged = CMPXCHG64(kaddr, old, new);
4630 break;
4631 default:
4632 BUG();
2bacc55c 4633 }
8fd75e12 4634 kunmap_atomic(kaddr);
daea3e73
AK		 4635 kvm_release_page_dirty(page);
4636
4637 if (!exchanged)
4638 return X86EMUL_CMPXCHG_FAILED;
4639
d3714010 4640 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4641 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4642
4643 return X86EMUL_CONTINUE;
4a5f48f6 4644
3200f405 4645emul_write:
daea3e73 4646 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4647
0f65dd70 4648 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4649}
4650
cf8f70bf
GN		 4651static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4652{
4653 /* TODO: String I/O for in kernel device */
4654 int r;
4655
4656 if (vcpu->arch.pio.in)
4657 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4658 vcpu->arch.pio.size, pd);
4659 else
4660 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4661 vcpu->arch.pio.port, vcpu->arch.pio.size,
4662 pd);
4663 return r;
4664}
4665
6f6fbe98
XG		 4666static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4667 unsigned short port, void *val,
4668 unsigned int count, bool in)
cf8f70bf 4669{
cf8f70bf 4670 vcpu->arch.pio.port = port;
6f6fbe98 4671 vcpu->arch.pio.in = in;
7972995b 4672 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4673 vcpu->arch.pio.size = size;
4674
4675 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4676 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4677 return 1;
4678 }
4679
4680 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4681 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4682 vcpu->run->io.size = size;
4683 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4684 vcpu->run->io.count = count;
4685 vcpu->run->io.port = port;
4686
4687 return 0;
4688}
4689
6f6fbe98
XG		 4690static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4691 int size, unsigned short port, void *val,
4692 unsigned int count)
cf8f70bf 4693{
ca1d4a9e 4694 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4695 int ret;
ca1d4a9e 4696
6f6fbe98
XG		 4697 if (vcpu->arch.pio.count)
4698 goto data_avail;
cf8f70bf 4699
6f6fbe98
XG		 4700 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4701 if (ret) {
4702data_avail:
4703 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4704 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4705 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4706 return 1;
4707 }
4708
cf8f70bf
GN		 4709 return 0;
4710}
4711
6f6fbe98
XG		 4712static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4713 int size, unsigned short port,
4714 const void *val, unsigned int count)
4715{
4716 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4717
4718 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4719 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4720 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4721}
4722
bbd9b64e
CO		 4723static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4724{
4725 return kvm_x86_ops->get_segment_base(vcpu, seg);
4726}
4727
3cb16fe7 4728static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4729{
3cb16fe7 4730 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4731}
4732
f5f48ee1
SY		 4733int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4734{
4735 if (!need_emulate_wbinvd(vcpu))
4736 return X86EMUL_CONTINUE;
4737
4738 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4739 int cpu = get_cpu();
4740
4741 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4742 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4743 wbinvd_ipi, NULL, 1);
2eec7343 4744 put_cpu();
f5f48ee1 4745 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4746 } else
4747 wbinvd();
f5f48ee1
SY		 4748 return X86EMUL_CONTINUE;
4749}
4750EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4751
bcaf5cc5
AK		 4752static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4753{
4754 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4755}
4756
717746e3 4757int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4758{
16f8a6f9 4759 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4760}
4761
717746e3 4762int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4763{
338dbc97 4764
717746e3 4765 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4766}
4767
52a46617 4768static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4769{
52a46617 4770 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4771}
4772
717746e3 4773static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4774{
717746e3 4775 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4776 unsigned long value;
4777
4778 switch (cr) {
4779 case 0:
4780 value = kvm_read_cr0(vcpu);
4781 break;
4782 case 2:
4783 value = vcpu->arch.cr2;
4784 break;
4785 case 3:
9f8fe504 4786 value = kvm_read_cr3(vcpu);
52a46617
GN		 4787 break;
4788 case 4:
4789 value = kvm_read_cr4(vcpu);
4790 break;
4791 case 8:
4792 value = kvm_get_cr8(vcpu);
4793 break;
4794 default:
a737f256 4795 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4796 return 0;
4797 }
4798
4799 return value;
4800}
4801
717746e3 4802static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4803{
717746e3 4804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4805 int res = 0;
4806
52a46617
GN		 4807 switch (cr) {
4808 case 0:
49a9b07e 4809 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4810 break;
4811 case 2:
4812 vcpu->arch.cr2 = val;
4813 break;
4814 case 3:
2390218b 4815 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4816 break;
4817 case 4:
a83b29c6 4818 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4819 break;
4820 case 8:
eea1cff9 4821 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4822 break;
4823 default:
a737f256 4824 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4825 res = -1;
52a46617 4826 }
0f12244f
GN		 4827
4828 return res;
52a46617
GN		 4829}
4830
717746e3 4831static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4832{
717746e3 4833 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4834}
4835
4bff1e86 4836static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4837{
4bff1e86 4838 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4839}
4840
4bff1e86 4841static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4842{
4bff1e86 4843 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4844}
4845
1ac9d0cf
AK		 4846static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4847{
4848 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4849}
4850
4851static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4852{
4853 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4854}
4855
4bff1e86
AK		 4856static unsigned long emulator_get_cached_segment_base(
4857 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4858{
4bff1e86 4859 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4860}
4861
1aa36616
AK		 4862static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4863 struct desc_struct *desc, u32 *base3,
4864 int seg)
2dafc6c2
GN		 4865{
4866 struct kvm_segment var;
4867
4bff1e86 4868 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4869 *selector = var.selector;
2dafc6c2 4870
378a8b09
GN		 4871 if (var.unusable) {
4872 memset(desc, 0, sizeof(*desc));
2dafc6c2 4873 return false;
378a8b09 4874 }
2dafc6c2
GN		 4875
4876 if (var.g)
4877 var.limit >>= 12;
4878 set_desc_limit(desc, var.limit);
4879 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4880#ifdef CONFIG_X86_64
4881 if (base3)
4882 *base3 = var.base >> 32;
4883#endif
2dafc6c2
GN		 4884 desc->type = var.type;
4885 desc->s = var.s;
4886 desc->dpl = var.dpl;
4887 desc->p = var.present;
4888 desc->avl = var.avl;
4889 desc->l = var.l;
4890 desc->d = var.db;
4891 desc->g = var.g;
4892
4893 return true;
4894}
4895
1aa36616
AK		 4896static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4897 struct desc_struct *desc, u32 base3,
4898 int seg)
2dafc6c2 4899{
4bff1e86 4900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4901 struct kvm_segment var;
4902
1aa36616 4903 var.selector = selector;
2dafc6c2 4904 var.base = get_desc_base(desc);
5601d05b
GN		 4905#ifdef CONFIG_X86_64
4906 var.base |= ((u64)base3) << 32;
4907#endif
2dafc6c2
GN		 4908 var.limit = get_desc_limit(desc);
4909 if (desc->g)
4910 var.limit = (var.limit << 12) | 0xfff;
4911 var.type = desc->type;
2dafc6c2
GN		 4912 var.dpl = desc->dpl;
4913 var.db = desc->d;
4914 var.s = desc->s;
4915 var.l = desc->l;
4916 var.g = desc->g;
4917 var.avl = desc->avl;
4918 var.present = desc->p;
4919 var.unusable = !var.present;
4920 var.padding = 0;
4921
4922 kvm_set_segment(vcpu, &var, seg);
4923 return;
4924}
4925
717746e3
AK		 4926static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4927 u32 msr_index, u64 *pdata)
4928{
4929 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4930}
4931
4932static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4933 u32 msr_index, u64 data)
4934{
8fe8ab46
WA		 4935 struct msr_data msr;
4936
4937 msr.data = data;
4938 msr.index = msr_index;
4939 msr.host_initiated = false;
4940 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4941}
4942
67f4d428
NA		 4943static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4944 u32 pmc)
4945{
4946 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4947}
4948
222d21aa
AK		 4949static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4950 u32 pmc, u64 *pdata)
4951{
4952 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4953}
4954
6c3287f7
AK		 4955static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4956{
4957 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4958}
4959
5037f6f3
AK		 4960static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4961{
4962 preempt_disable();
5197b808 4963 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4964 /*
4965 * CR0.TS may reference the host fpu state, not the guest fpu state,
4966 * so it may be clear at this point.
4967 */
4968 clts();
4969}
4970
4971static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4972{
4973 preempt_enable();
4974}
4975
2953538e 4976static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4977 struct x86_instruction_info *info,
c4f035c6
AK		 4978 enum x86_intercept_stage stage)
4979{
2953538e 4980 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4981}
4982
0017f93a 4983static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4984 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4985{
0017f93a 4986 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4987}
4988
dd856efa
AK		 4989static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4990{
4991 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4992}
4993
4994static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4995{
4996 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4997}
4998
0225fb50 4999static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5000 .read_gpr = emulator_read_gpr,
5001 .write_gpr = emulator_write_gpr,
1871c602 5002 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5003 .write_std = kvm_write_guest_virt_system,
1871c602 5004 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5005 .read_emulated = emulator_read_emulated,
5006 .write_emulated = emulator_write_emulated,
5007 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5008 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5009 .pio_in_emulated = emulator_pio_in_emulated,
5010 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5011 .get_segment = emulator_get_segment,
5012 .set_segment = emulator_set_segment,
5951c442 5013 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5014 .get_gdt = emulator_get_gdt,
160ce1f1 5015 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5016 .set_gdt = emulator_set_gdt,
5017 .set_idt = emulator_set_idt,
52a46617
GN		 5018 .get_cr = emulator_get_cr,
5019 .set_cr = emulator_set_cr,
9c537244 5020 .cpl = emulator_get_cpl,
35aa5375
GN		 5021 .get_dr = emulator_get_dr,
5022 .set_dr = emulator_set_dr,
717746e3
AK		 5023 .set_msr = emulator_set_msr,
5024 .get_msr = emulator_get_msr,
67f4d428 5025 .check_pmc = emulator_check_pmc,
222d21aa 5026 .read_pmc = emulator_read_pmc,
6c3287f7 5027 .halt = emulator_halt,
bcaf5cc5 5028 .wbinvd = emulator_wbinvd,
d6aa1000 5029 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5030 .get_fpu = emulator_get_fpu,
5031 .put_fpu = emulator_put_fpu,
c4f035c6 5032 .intercept = emulator_intercept,
bdb42f5a 5033 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 5034};
5035
95cb2295
GN		 5036static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5037{
37ccdcbe 5038 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5039 /*
5040 * an sti; sti; sequence only disable interrupts for the first
5041 * instruction. So, if the last instruction, be it emulated or
5042 * not, left the system with the INT_STI flag enabled, it
5043 * means that the last instruction is an sti. We should not
5044 * leave the flag on in this case. The same goes for mov ss
5045 */
37ccdcbe
PB		 5046 if (int_shadow & mask)
5047 mask = 0;
6addfc42 5048 if (unlikely(int_shadow || mask)) {
95cb2295 5049 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5050 if (!mask)
5051 kvm_make_request(KVM_REQ_EVENT, vcpu);
5052 }
95cb2295
GN		 5053}
5054
ef54bcfe 5055static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5056{
5057 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5058 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5059 return kvm_propagate_fault(vcpu, &ctxt->exception);
5060
5061 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5062 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5063 ctxt->exception.error_code);
54b8486f 5064 else
da9cb575 5065 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5066 return false;
54b8486f
GN		 5067}
5068
8ec4722d
MG		 5069static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5070{
adf52235 5071 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5072 int cs_db, cs_l;
5073
8ec4722d
MG		 5074 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5075
adf52235
TY		 5076 ctxt->eflags = kvm_get_rflags(vcpu);
5077 ctxt->eip = kvm_rip_read(vcpu);
5078 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5079 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5080 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5081 cs_db ? X86EMUL_MODE_PROT32 :
5082 X86EMUL_MODE_PROT16;
5083 ctxt->guest_mode = is_guest_mode(vcpu);
5084
dd856efa 5085 init_decode_cache(ctxt);
7ae441ea 5086 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5087}
5088
71f9833b 5089int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5090{
9d74191a 5091 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5092 int ret;
5093
5094 init_emulate_ctxt(vcpu);
5095
9dac77fa
AK		 5096 ctxt->op_bytes = 2;
5097 ctxt->ad_bytes = 2;
5098 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5099 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5100
5101 if (ret != X86EMUL_CONTINUE)
5102 return EMULATE_FAIL;
5103
9dac77fa 5104 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5105 kvm_rip_write(vcpu, ctxt->eip);
5106 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5107
5108 if (irq == NMI_VECTOR)
7460fb4a 5109 vcpu->arch.nmi_pending = 0;
63995653
MG		 5110 else
5111 vcpu->arch.interrupt.pending = false;
5112
5113 return EMULATE_DONE;
5114}
5115EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5116
6d77dbfc
GN		 5117static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5118{
fc3a9157
JR		 5119 int r = EMULATE_DONE;
5120
6d77dbfc
GN		 5121 ++vcpu->stat.insn_emulation_fail;
5122 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5123 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5124 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5125 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5126 vcpu->run->internal.ndata = 0;
5127 r = EMULATE_FAIL;
5128 }
6d77dbfc 5129 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5130
5131 return r;
6d77dbfc
GN		 5132}
5133
93c05d3e 5134static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5135 bool write_fault_to_shadow_pgtable,
5136 int emulation_type)
a6f177ef 5137{
95b3cf69 5138 gpa_t gpa = cr2;
8e3d9d06 5139 pfn_t pfn;
a6f177ef 5140
991eebf9
GN		 5141 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5142 return false;
5143
95b3cf69
XG		 5144 if (!vcpu->arch.mmu.direct_map) {
5145 /*
5146 * Write permission should be allowed since only
5147 * write access need to be emulated.
5148 */
5149 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5150
95b3cf69
XG		 5151 /*
5152 * If the mapping is invalid in guest, let cpu retry
5153 * it to generate fault.
5154 */
5155 if (gpa == UNMAPPED_GVA)
5156 return true;
5157 }
a6f177ef 5158
8e3d9d06
XG		 5159 /*
5160 * Do not retry the unhandleable instruction if it faults on the
5161 * readonly host memory, otherwise it will goto a infinite loop:
5162 * retry instruction -> write #PF -> emulation fail -> retry
5163 * instruction -> ...
5164 */
5165 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5166
5167 /*
5168 * If the instruction failed on the error pfn, it can not be fixed,
5169 * report the error to userspace.
5170 */
5171 if (is_error_noslot_pfn(pfn))
5172 return false;
5173
5174 kvm_release_pfn_clean(pfn);
5175
5176 /* The instructions are well-emulated on direct mmu. */
5177 if (vcpu->arch.mmu.direct_map) {
5178 unsigned int indirect_shadow_pages;
5179
5180 spin_lock(&vcpu->kvm->mmu_lock);
5181 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5182 spin_unlock(&vcpu->kvm->mmu_lock);
5183
5184 if (indirect_shadow_pages)
5185 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5186
a6f177ef 5187 return true;
8e3d9d06 5188 }
a6f177ef 5189
95b3cf69
XG		 5190 /*
5191 * if emulation was due to access to shadowed page table
5192 * and it failed try to unshadow page and re-enter the
5193 * guest to let CPU execute the instruction.
5194 */
5195 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5196
5197 /*
5198 * If the access faults on its page table, it can not
5199 * be fixed by unprotecting shadow page and it should
5200 * be reported to userspace.
5201 */
5202 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5203}
5204
1cb3f3ae
XG		 5205static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5206 unsigned long cr2, int emulation_type)
5207{
5208 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5209 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5210
5211 last_retry_eip = vcpu->arch.last_retry_eip;
5212 last_retry_addr = vcpu->arch.last_retry_addr;
5213
5214 /*
5215 * If the emulation is caused by #PF and it is non-page_table
5216 * writing instruction, it means the VM-EXIT is caused by shadow
5217 * page protected, we can zap the shadow page and retry this
5218 * instruction directly.
5219 *
5220 * Note: if the guest uses a non-page-table modifying instruction
5221 * on the PDE that points to the instruction, then we will unmap
5222 * the instruction and go to an infinite loop. So, we cache the
5223 * last retried eip and the last fault address, if we meet the eip
5224 * and the address again, we can break out of the potential infinite
5225 * loop.
5226 */
5227 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5228
5229 if (!(emulation_type & EMULTYPE_RETRY))
5230 return false;
5231
5232 if (x86_page_table_writing_insn(ctxt))
5233 return false;
5234
5235 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5236 return false;
5237
5238 vcpu->arch.last_retry_eip = ctxt->eip;
5239 vcpu->arch.last_retry_addr = cr2;
5240
5241 if (!vcpu->arch.mmu.direct_map)
5242 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5243
22368028 5244 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5245
5246 return true;
5247}
5248
716d51ab
GN		 5249static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5250static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5251
4a1e10d5
PB		 5252static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5253 unsigned long *db)
5254{
5255 u32 dr6 = 0;
5256 int i;
5257 u32 enable, rwlen;
5258
5259 enable = dr7;
5260 rwlen = dr7 >> 16;
5261 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5262 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5263 dr6 |= (1 << i);
5264 return dr6;
5265}
5266
6addfc42 5267static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5268{
5269 struct kvm_run *kvm_run = vcpu->run;
5270
5271 /*
6addfc42
PB		 5272 * rflags is the old, "raw" value of the flags. The new value has
5273 * not been saved yet.
663f4c61
PB		 5274 *
5275 * This is correct even for TF set by the guest, because "the
5276 * processor will not generate this exception after the instruction
5277 * that sets the TF flag".
5278 */
663f4c61
PB		 5279 if (unlikely(rflags & X86_EFLAGS_TF)) {
5280 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5281 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5282 DR6_RTM;
663f4c61
PB		 5283 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5284 kvm_run->debug.arch.exception = DB_VECTOR;
5285 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5286 *r = EMULATE_USER_EXIT;
5287 } else {
5288 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5289 /*
5290 * "Certain debug exceptions may clear bit 0-3. The
5291 * remaining contents of the DR6 register are never
5292 * cleared by the processor".
5293 */
5294 vcpu->arch.dr6 &= ~15;
6f43ed01 5295 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5296 kvm_queue_exception(vcpu, DB_VECTOR);
5297 }
5298 }
5299}
5300
4a1e10d5
PB		 5301static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5302{
4a1e10d5
PB		 5303 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5304 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5305 struct kvm_run *kvm_run = vcpu->run;
5306 unsigned long eip = kvm_get_linear_rip(vcpu);
5307 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5308 vcpu->arch.guest_debug_dr7,
5309 vcpu->arch.eff_db);
5310
5311 if (dr6 != 0) {
6f43ed01 5312 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5313 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5314 kvm_run->debug.arch.exception = DB_VECTOR;
5315 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5316 *r = EMULATE_USER_EXIT;
5317 return true;
5318 }
5319 }
5320
4161a569
NA		 5321 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5322 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5323 unsigned long eip = kvm_get_linear_rip(vcpu);
5324 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5325 vcpu->arch.dr7,
5326 vcpu->arch.db);
5327
5328 if (dr6 != 0) {
5329 vcpu->arch.dr6 &= ~15;
6f43ed01 5330 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5331 kvm_queue_exception(vcpu, DB_VECTOR);
5332 *r = EMULATE_DONE;
5333 return true;
5334 }
5335 }
5336
5337 return false;
5338}
5339
51d8b661
AP		 5340int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5341 unsigned long cr2,
dc25e89e
AP		 5342 int emulation_type,
5343 void *insn,
5344 int insn_len)
bbd9b64e 5345{
95cb2295 5346 int r;
9d74191a 5347 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5348 bool writeback = true;
93c05d3e 5349 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5350
93c05d3e
XG		 5351 /*
5352 * Clear write_fault_to_shadow_pgtable here to ensure it is
5353 * never reused.
5354 */
5355 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5356 kvm_clear_exception_queue(vcpu);
8d7d8102 5357
571008da 5358 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5359 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5360
5361 /*
5362 * We will reenter on the same instruction since
5363 * we do not set complete_userspace_io. This does not
5364 * handle watchpoints yet, those would be handled in
5365 * the emulate_ops.
5366 */
5367 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5368 return r;
5369
9d74191a
TY		 5370 ctxt->interruptibility = 0;
5371 ctxt->have_exception = false;
e0ad0b47 5372 ctxt->exception.vector = -1;
9d74191a 5373 ctxt->perm_ok = false;
bbd9b64e 5374
b51e974f 5375 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5376
9d74191a 5377 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5378
e46479f8 5379 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5380 ++vcpu->stat.insn_emulation;
1d2887e2 5381 if (r != EMULATION_OK) {
4005996e
AK		 5382 if (emulation_type & EMULTYPE_TRAP_UD)
5383 return EMULATE_FAIL;
991eebf9
GN		 5384 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5385 emulation_type))
bbd9b64e 5386 return EMULATE_DONE;
6d77dbfc
GN		 5387 if (emulation_type & EMULTYPE_SKIP)
5388 return EMULATE_FAIL;
5389 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5390 }
5391 }
5392
ba8afb6b 5393 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5394 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5395 if (ctxt->eflags & X86_EFLAGS_RF)
5396 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5397 return EMULATE_DONE;
5398 }
5399
1cb3f3ae
XG		 5400 if (retry_instruction(ctxt, cr2, emulation_type))
5401 return EMULATE_DONE;
5402
7ae441ea 5403 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5404 changes registers values during IO operation */
7ae441ea
GN		 5405 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5406 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5407 emulator_invalidate_register_cache(ctxt);
7ae441ea 5408 }
4d2179e1 5409
5cd21917 5410restart:
9d74191a 5411 r = x86_emulate_insn(ctxt);
bbd9b64e 5412
775fde86
JR		 5413 if (r == EMULATION_INTERCEPTED)
5414 return EMULATE_DONE;
5415
d2ddd1c4 5416 if (r == EMULATION_FAILED) {
991eebf9
GN		 5417 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5418 emulation_type))
c3cd7ffa
GN		 5419 return EMULATE_DONE;
5420
6d77dbfc 5421 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5422 }
5423
9d74191a 5424 if (ctxt->have_exception) {
d2ddd1c4 5425 r = EMULATE_DONE;
ef54bcfe
PB		 5426 if (inject_emulated_exception(vcpu))
5427 return r;
d2ddd1c4 5428 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5429 if (!vcpu->arch.pio.in) {
5430 /* FIXME: return into emulator if single-stepping. */
3457e419 5431 vcpu->arch.pio.count = 0;
0912c977 5432 } else {
7ae441ea 5433 writeback = false;
716d51ab
GN		 5434 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5435 }
ac0a48c3 5436 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5437 } else if (vcpu->mmio_needed) {
5438 if (!vcpu->mmio_is_write)
5439 writeback = false;
ac0a48c3 5440 r = EMULATE_USER_EXIT;
716d51ab 5441 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5442 } else if (r == EMULATION_RESTART)
5cd21917 5443 goto restart;
d2ddd1c4
GN		 5444 else
5445 r = EMULATE_DONE;
f850e2e6 5446
7ae441ea 5447 if (writeback) {
6addfc42 5448 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5449 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5450 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5451 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5452 if (r == EMULATE_DONE)
6addfc42 5453 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5454 if (!ctxt->have_exception ||
5455 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5456 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5457
5458 /*
5459 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5460 * do nothing, and it will be requested again as soon as
5461 * the shadow expires. But we still need to check here,
5462 * because POPF has no interrupt shadow.
5463 */
5464 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5465 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5466 } else
5467 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5468
5469 return r;
de7d789a 5470}
51d8b661 5471EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5472
cf8f70bf 5473int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5474{
cf8f70bf 5475 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5476 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5477 size, port, &val, 1);
cf8f70bf 5478 /* do not return to emulator after return from userspace */
7972995b 5479 vcpu->arch.pio.count = 0;
de7d789a
CO		 5480 return ret;
5481}
cf8f70bf 5482EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5483
8cfdc000
ZA		 5484static void tsc_bad(void *info)
5485{
0a3aee0d 5486 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5487}
5488
5489static void tsc_khz_changed(void *data)
c8076604 5490{
8cfdc000
ZA		 5491 struct cpufreq_freqs *freq = data;
5492 unsigned long khz = 0;
5493
5494 if (data)
5495 khz = freq->new;
5496 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5497 khz = cpufreq_quick_get(raw_smp_processor_id());
5498 if (!khz)
5499 khz = tsc_khz;
0a3aee0d 5500 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5501}
5502
c8076604
GH		 5503static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5504 void *data)
5505{
5506 struct cpufreq_freqs *freq = data;
5507 struct kvm *kvm;
5508 struct kvm_vcpu *vcpu;
5509 int i, send_ipi = 0;
5510
8cfdc000
ZA		 5511 /*
5512 * We allow guests to temporarily run on slowing clocks,
5513 * provided we notify them after, or to run on accelerating
5514 * clocks, provided we notify them before. Thus time never
5515 * goes backwards.
5516 *
5517 * However, we have a problem. We can't atomically update
5518 * the frequency of a given CPU from this function; it is
5519 * merely a notifier, which can be called from any CPU.
5520 * Changing the TSC frequency at arbitrary points in time
5521 * requires a recomputation of local variables related to
5522 * the TSC for each VCPU. We must flag these local variables
5523 * to be updated and be sure the update takes place with the
5524 * new frequency before any guests proceed.
5525 *
5526 * Unfortunately, the combination of hotplug CPU and frequency
5527 * change creates an intractable locking scenario; the order
5528 * of when these callouts happen is undefined with respect to
5529 * CPU hotplug, and they can race with each other. As such,
5530 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5531 * undefined; you can actually have a CPU frequency change take
5532 * place in between the computation of X and the setting of the
5533 * variable. To protect against this problem, all updates of
5534 * the per_cpu tsc_khz variable are done in an interrupt
5535 * protected IPI, and all callers wishing to update the value
5536 * must wait for a synchronous IPI to complete (which is trivial
5537 * if the caller is on the CPU already). This establishes the
5538 * necessary total order on variable updates.
5539 *
5540 * Note that because a guest time update may take place
5541 * anytime after the setting of the VCPU's request bit, the
5542 * correct TSC value must be set before the request. However,
5543 * to ensure the update actually makes it to any guest which
5544 * starts running in hardware virtualization between the set
5545 * and the acquisition of the spinlock, we must also ping the
5546 * CPU after setting the request bit.
5547 *
5548 */
5549
c8076604
GH		 5550 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5551 return 0;
5552 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5553 return 0;
8cfdc000
ZA		 5554
5555 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5556
2f303b74 5557 spin_lock(&kvm_lock);
c8076604 5558 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5559 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5560 if (vcpu->cpu != freq->cpu)
5561 continue;
c285545f 5562 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5563 if (vcpu->cpu != smp_processor_id())
8cfdc000 5564 send_ipi = 1;
c8076604
GH		 5565 }
5566 }
2f303b74 5567 spin_unlock(&kvm_lock);
c8076604
GH		 5568
5569 if (freq->old < freq->new && send_ipi) {
5570 /*
5571 * We upscale the frequency. Must make the guest
5572 * doesn't see old kvmclock values while running with
5573 * the new frequency, otherwise we risk the guest sees
5574 * time go backwards.
5575 *
5576 * In case we update the frequency for another cpu
5577 * (which might be in guest context) send an interrupt
5578 * to kick the cpu out of guest context. Next time
5579 * guest context is entered kvmclock will be updated,
5580 * so the guest will not see stale values.
5581 */
8cfdc000 5582 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5583 }
5584 return 0;
5585}
5586
5587static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5588 .notifier_call = kvmclock_cpufreq_notifier
5589};
5590
5591static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5592 unsigned long action, void *hcpu)
5593{
5594 unsigned int cpu = (unsigned long)hcpu;
5595
5596 switch (action) {
5597 case CPU_ONLINE:
5598 case CPU_DOWN_FAILED:
5599 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5600 break;
5601 case CPU_DOWN_PREPARE:
5602 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5603 break;
5604 }
5605 return NOTIFY_OK;
5606}
5607
5608static struct notifier_block kvmclock_cpu_notifier_block = {
5609 .notifier_call = kvmclock_cpu_notifier,
5610 .priority = -INT_MAX
c8076604
GH		 5611};
5612
b820cc0c
ZA		 5613static void kvm_timer_init(void)
5614{
5615 int cpu;
5616
c285545f 5617 max_tsc_khz = tsc_khz;
460dd42e
SB		 5618
5619 cpu_notifier_register_begin();
b820cc0c 5620 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5621#ifdef CONFIG_CPU_FREQ
5622 struct cpufreq_policy policy;
5623 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5624 cpu = get_cpu();
5625 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5626 if (policy.cpuinfo.max_freq)
5627 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5628 put_cpu();
c285545f 5629#endif
b820cc0c
ZA		 5630 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5631 CPUFREQ_TRANSITION_NOTIFIER);
5632 }
c285545f 5633 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5634 for_each_online_cpu(cpu)
5635 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5636
5637 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5638 cpu_notifier_register_done();
5639
b820cc0c
ZA		 5640}
5641
ff9d07a0
ZY		 5642static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5643
f5132b01 5644int kvm_is_in_guest(void)
ff9d07a0 5645{
086c9855 5646 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5647}
5648
5649static int kvm_is_user_mode(void)
5650{
5651 int user_mode = 3;
dcf46b94 5652
086c9855
AS		 5653 if (__this_cpu_read(current_vcpu))
5654 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5655
ff9d07a0
ZY		 5656 return user_mode != 0;
5657}
5658
5659static unsigned long kvm_get_guest_ip(void)
5660{
5661 unsigned long ip = 0;
dcf46b94 5662
086c9855
AS		 5663 if (__this_cpu_read(current_vcpu))
5664 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5665
ff9d07a0
ZY		 5666 return ip;
5667}
5668
5669static struct perf_guest_info_callbacks kvm_guest_cbs = {
5670 .is_in_guest = kvm_is_in_guest,
5671 .is_user_mode = kvm_is_user_mode,
5672 .get_guest_ip = kvm_get_guest_ip,
5673};
5674
5675void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5676{
086c9855 5677 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5678}
5679EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5680
5681void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5682{
086c9855 5683 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5684}
5685EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5686
ce88decf
XG		 5687static void kvm_set_mmio_spte_mask(void)
5688{
5689 u64 mask;
5690 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5691
5692 /*
5693 * Set the reserved bits and the present bit of an paging-structure
5694 * entry to generate page fault with PFER.RSV = 1.
5695 */
885032b9 5696 /* Mask the reserved physical address bits. */
d1431483 5697 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5698
5699 /* Bit 62 is always reserved for 32bit host. */
5700 mask |= 0x3ull << 62;
5701
5702 /* Set the present bit. */
ce88decf
XG		 5703 mask |= 1ull;
5704
5705#ifdef CONFIG_X86_64
5706 /*
5707 * If reserved bit is not supported, clear the present bit to disable
5708 * mmio page fault.
5709 */
5710 if (maxphyaddr == 52)
5711 mask &= ~1ull;
5712#endif
5713
5714 kvm_mmu_set_mmio_spte_mask(mask);
5715}
5716
16e8d74d
MT		 5717#ifdef CONFIG_X86_64
5718static void pvclock_gtod_update_fn(struct work_struct *work)
5719{
d828199e
MT		 5720 struct kvm *kvm;
5721
5722 struct kvm_vcpu *vcpu;
5723 int i;
5724
2f303b74 5725 spin_lock(&kvm_lock);
d828199e
MT		 5726 list_for_each_entry(kvm, &vm_list, vm_list)
5727 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5728 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5729 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5730 spin_unlock(&kvm_lock);
16e8d74d
MT		 5731}
5732
5733static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5734
5735/*
5736 * Notification about pvclock gtod data update.
5737 */
5738static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5739 void *priv)
5740{
5741 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5742 struct timekeeper *tk = priv;
5743
5744 update_pvclock_gtod(tk);
5745
5746 /* disable master clock if host does not trust, or does not
5747 * use, TSC clocksource
5748 */
5749 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5750 atomic_read(&kvm_guest_has_master_clock) != 0)
5751 queue_work(system_long_wq, &pvclock_gtod_work);
5752
5753 return 0;
5754}
5755
5756static struct notifier_block pvclock_gtod_notifier = {
5757 .notifier_call = pvclock_gtod_notify,
5758};
5759#endif
5760
f8c16bba 5761int kvm_arch_init(void *opaque)
043405e1 5762{
b820cc0c 5763 int r;
6b61edf7 5764 struct kvm_x86_ops *ops = opaque;
f8c16bba 5765
f8c16bba
ZX		 5766 if (kvm_x86_ops) {
5767 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5768 r = -EEXIST;
5769 goto out;
f8c16bba
ZX		 5770 }
5771
5772 if (!ops->cpu_has_kvm_support()) {
5773 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5774 r = -EOPNOTSUPP;
5775 goto out;
f8c16bba
ZX		 5776 }
5777 if (ops->disabled_by_bios()) {
5778 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5779 r = -EOPNOTSUPP;
5780 goto out;
f8c16bba
ZX		 5781 }
5782
013f6a5d
MT		 5783 r = -ENOMEM;
5784 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5785 if (!shared_msrs) {
5786 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5787 goto out;
5788 }
5789
97db56ce
AK		 5790 r = kvm_mmu_module_init();
5791 if (r)
013f6a5d 5792 goto out_free_percpu;
97db56ce 5793
ce88decf 5794 kvm_set_mmio_spte_mask();
97db56ce 5795
f8c16bba 5796 kvm_x86_ops = ops;
920c8377
PB		 5797 kvm_init_msr_list();
5798
7b52345e 5799 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5800 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5801
b820cc0c 5802 kvm_timer_init();
c8076604 5803
ff9d07a0
ZY		 5804 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5805
2acf923e
DC		 5806 if (cpu_has_xsave)
5807 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5808
c5cc421b 5809 kvm_lapic_init();
16e8d74d
MT		 5810#ifdef CONFIG_X86_64
5811 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5812#endif
5813
f8c16bba 5814 return 0;
56c6d28a 5815
013f6a5d
MT		 5816out_free_percpu:
5817 free_percpu(shared_msrs);
56c6d28a 5818out:
56c6d28a 5819 return r;
043405e1 5820}
8776e519 5821
f8c16bba
ZX		 5822void kvm_arch_exit(void)
5823{
ff9d07a0
ZY		 5824 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5825
888d256e
JK		 5826 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5827 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5828 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5829 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5830#ifdef CONFIG_X86_64
5831 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5832#endif
f8c16bba 5833 kvm_x86_ops = NULL;
56c6d28a 5834 kvm_mmu_module_exit();
013f6a5d 5835 free_percpu(shared_msrs);
56c6d28a 5836}
f8c16bba 5837
8776e519
HB		 5838int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5839{
5840 ++vcpu->stat.halt_exits;
5841 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5842 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5843 return 1;
5844 } else {
5845 vcpu->run->exit_reason = KVM_EXIT_HLT;
5846 return 0;
5847 }
5848}
5849EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5850
55cd8e5a
GN		 5851int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5852{
5853 u64 param, ingpa, outgpa, ret;
5854 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5855 bool fast, longmode;
55cd8e5a
GN		 5856
5857 /*
5858 * hypercall generates UD from non zero cpl and real mode
5859 * per HYPER-V spec
5860 */
3eeb3288 5861 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5862 kvm_queue_exception(vcpu, UD_VECTOR);
5863 return 0;
5864 }
5865
a449c7aa 5866 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5867
5868 if (!longmode) {
ccd46936
GN		 5869 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5870 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5871 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5872 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5873 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5874 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5875 }
5876#ifdef CONFIG_X86_64
5877 else {
5878 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5879 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5880 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5881 }
5882#endif
5883
5884 code = param & 0xffff;
5885 fast = (param >> 16) & 0x1;
5886 rep_cnt = (param >> 32) & 0xfff;
5887 rep_idx = (param >> 48) & 0xfff;
5888
5889 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5890
c25bc163
GN		 5891 switch (code) {
5892 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5893 kvm_vcpu_on_spin(vcpu);
5894 break;
5895 default:
5896 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5897 break;
5898 }
55cd8e5a
GN		 5899
5900 ret = res | (((u64)rep_done & 0xfff) << 32);
5901 if (longmode) {
5902 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5903 } else {
5904 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5905 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5906 }
5907
5908 return 1;
5909}
5910
6aef266c
SV		 5911/*
5912 * kvm_pv_kick_cpu_op: Kick a vcpu.
5913 *
5914 * @apicid - apicid of vcpu to be kicked.
5915 */
5916static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5917{
24d2166b 5918 struct kvm_lapic_irq lapic_irq;
6aef266c 5919
24d2166b
R		 5920 lapic_irq.shorthand = 0;
5921 lapic_irq.dest_mode = 0;
5922 lapic_irq.dest_id = apicid;
6aef266c 5923
24d2166b
R		 5924 lapic_irq.delivery_mode = APIC_DM_REMRD;
5925 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5926}
5927
8776e519
HB		 5928int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5929{
5930 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5931 int op_64_bit, r = 1;
8776e519 5932
55cd8e5a
GN		 5933 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5934 return kvm_hv_hypercall(vcpu);
5935
5fdbf976
MT		 5936 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5937 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5938 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5939 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5940 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5941
229456fc 5942 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5943
a449c7aa
NA		 5944 op_64_bit = is_64_bit_mode(vcpu);
5945 if (!op_64_bit) {
8776e519
HB		 5946 nr &= 0xFFFFFFFF;
5947 a0 &= 0xFFFFFFFF;
5948 a1 &= 0xFFFFFFFF;
5949 a2 &= 0xFFFFFFFF;
5950 a3 &= 0xFFFFFFFF;
5951 }
5952
07708c4a
JK		 5953 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5954 ret = -KVM_EPERM;
5955 goto out;
5956 }
5957
8776e519 5958 switch (nr) {
b93463aa
AK		 5959 case KVM_HC_VAPIC_POLL_IRQ:
5960 ret = 0;
5961 break;
6aef266c
SV		 5962 case KVM_HC_KICK_CPU:
5963 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5964 ret = 0;
5965 break;
8776e519
HB		 5966 default:
5967 ret = -KVM_ENOSYS;
5968 break;
5969 }
07708c4a 5970out:
a449c7aa
NA		 5971 if (!op_64_bit)
5972 ret = (u32)ret;
5fdbf976 5973 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5974 ++vcpu->stat.hypercalls;
2f333bcb 5975 return r;
8776e519
HB		 5976}
5977EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5978
b6785def 5979static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5980{
d6aa1000 5981 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5982 char instruction[3];
5fdbf976 5983 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5984
8776e519 5985 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5986
9d74191a 5987 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5988}
5989
b6c7a5dc
HB		 5990/*
5991 * Check if userspace requested an interrupt window, and that the
5992 * interrupt window is open.
5993 *
5994 * No need to exit to userspace if we already have an interrupt queued.
5995 */
851ba692 5996static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5997{
8061823a 5998 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5999 vcpu->run->request_interrupt_window &&
5df56646 6000 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6001}
6002
851ba692 6003static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6004{
851ba692
AK		 6005 struct kvm_run *kvm_run = vcpu->run;
6006
91586a3b 6007 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6008 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6009 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6010 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6011 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6012 else
b6c7a5dc 6013 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6014 kvm_arch_interrupt_allowed(vcpu) &&
6015 !kvm_cpu_has_interrupt(vcpu) &&
6016 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6017}
6018
95ba8273
GN		 6019static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6020{
6021 int max_irr, tpr;
6022
6023 if (!kvm_x86_ops->update_cr8_intercept)
6024 return;
6025
88c808fd
AK		 6026 if (!vcpu->arch.apic)
6027 return;
6028
8db3baa2
GN		 6029 if (!vcpu->arch.apic->vapic_addr)
6030 max_irr = kvm_lapic_find_highest_irr(vcpu);
6031 else
6032 max_irr = -1;
95ba8273
GN		 6033
6034 if (max_irr != -1)
6035 max_irr >>= 4;
6036
6037 tpr = kvm_lapic_get_cr8(vcpu);
6038
6039 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6040}
6041
b6b8a145 6042static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6043{
b6b8a145
JK		 6044 int r;
6045
95ba8273 6046 /* try to reinject previous events if any */
b59bb7bd 6047 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6048 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6049 vcpu->arch.exception.has_error_code,
6050 vcpu->arch.exception.error_code);
d6e8c854
NA		 6051
6052 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6053 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6054 X86_EFLAGS_RF);
6055
6bdf0662
NA		 6056 if (vcpu->arch.exception.nr == DB_VECTOR &&
6057 (vcpu->arch.dr7 & DR7_GD)) {
6058 vcpu->arch.dr7 &= ~DR7_GD;
6059 kvm_update_dr7(vcpu);
6060 }
6061
b59bb7bd
GN		 6062 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6063 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6064 vcpu->arch.exception.error_code,
6065 vcpu->arch.exception.reinject);
b6b8a145 6066 return 0;
b59bb7bd
GN		 6067 }
6068
95ba8273
GN		 6069 if (vcpu->arch.nmi_injected) {
6070 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6071 return 0;
95ba8273
GN		 6072 }
6073
6074 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6075 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6076 return 0;
6077 }
6078
6079 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6080 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6081 if (r != 0)
6082 return r;
95ba8273
GN		 6083 }
6084
6085 /* try to inject new event if pending */
6086 if (vcpu->arch.nmi_pending) {
6087 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6088 --vcpu->arch.nmi_pending;
95ba8273
GN		 6089 vcpu->arch.nmi_injected = true;
6090 kvm_x86_ops->set_nmi(vcpu);
6091 }
c7c9c56c 6092 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6093 /*
6094 * Because interrupts can be injected asynchronously, we are
6095 * calling check_nested_events again here to avoid a race condition.
6096 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6097 * proposal and current concerns. Perhaps we should be setting
6098 * KVM_REQ_EVENT only on certain events and not unconditionally?
6099 */
6100 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6101 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6102 if (r != 0)
6103 return r;
6104 }
95ba8273 6105 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6106 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6107 false);
6108 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6109 }
6110 }
b6b8a145 6111 return 0;
95ba8273
GN		 6112}
6113
7460fb4a
AK		 6114static void process_nmi(struct kvm_vcpu *vcpu)
6115{
6116 unsigned limit = 2;
6117
6118 /*
6119 * x86 is limited to one NMI running, and one NMI pending after it.
6120 * If an NMI is already in progress, limit further NMIs to just one.
6121 * Otherwise, allow two (and we'll inject the first one immediately).
6122 */
6123 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6124 limit = 1;
6125
6126 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6127 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6128 kvm_make_request(KVM_REQ_EVENT, vcpu);
6129}
6130
3d81bc7e 6131static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6132{
6133 u64 eoi_exit_bitmap[4];
cf9e65b7 6134 u32 tmr[8];
c7c9c56c 6135
3d81bc7e
YZ		 6136 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6137 return;
c7c9c56c
YZ		 6138
6139 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6140 memset(tmr, 0, 32);
c7c9c56c 6141
cf9e65b7 6142 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6143 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6144 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6145}
6146
a70656b6
RK		 6147static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6148{
6149 ++vcpu->stat.tlb_flush;
6150 kvm_x86_ops->tlb_flush(vcpu);
6151}
6152
4256f43f
TC		 6153void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6154{
c24ae0dc
TC		 6155 struct page *page = NULL;
6156
f439ed27
PB		 6157 if (!irqchip_in_kernel(vcpu->kvm))
6158 return;
6159
4256f43f
TC		 6160 if (!kvm_x86_ops->set_apic_access_page_addr)
6161 return;
6162
c24ae0dc
TC		 6163 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6164 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6165
6166 /*
6167 * Do not pin apic access page in memory, the MMU notifier
6168 * will call us again if it is migrated or swapped out.
6169 */
6170 put_page(page);
4256f43f
TC		 6171}
6172EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6173
fe71557a
TC		 6174void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6175 unsigned long address)
6176{
c24ae0dc
TC		 6177 /*
6178 * The physical address of apic access page is stored in the VMCS.
6179 * Update it when it becomes invalid.
6180 */
6181 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6182 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6183}
6184
9357d939
TY		 6185/*
6186 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6187 * exiting to the userspace. Otherwise, the value will be returned to the
6188 * userspace.
6189 */
851ba692 6190static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6191{
6192 int r;
6a8b1d13 6193 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6194 vcpu->run->request_interrupt_window;
730dca42 6195 bool req_immediate_exit = false;
b6c7a5dc 6196
3e007509 6197 if (vcpu->requests) {
a8eeb04a 6198 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6199 kvm_mmu_unload(vcpu);
a8eeb04a 6200 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6201 __kvm_migrate_timers(vcpu);
d828199e
MT		 6202 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6203 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6204 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6205 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6206 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6207 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6208 if (unlikely(r))
6209 goto out;
6210 }
a8eeb04a 6211 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6212 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6213 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6214 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6215 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6216 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6217 r = 0;
6218 goto out;
6219 }
a8eeb04a 6220 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6221 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6222 r = 0;
6223 goto out;
6224 }
a8eeb04a 6225 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6226 vcpu->fpu_active = 0;
6227 kvm_x86_ops->fpu_deactivate(vcpu);
6228 }
af585b92
GN		 6229 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6230 /* Page is swapped out. Do synthetic halt */
6231 vcpu->arch.apf.halted = true;
6232 r = 1;
6233 goto out;
6234 }
c9aaa895
GC		 6235 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6236 record_steal_time(vcpu);
7460fb4a
AK		 6237 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6238 process_nmi(vcpu);
f5132b01
GN		 6239 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6240 kvm_handle_pmu_event(vcpu);
6241 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6242 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6243 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6244 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6245 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6246 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6247 }
b93463aa 6248
b463a6f7 6249 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6250 kvm_apic_accept_events(vcpu);
6251 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6252 r = 1;
6253 goto out;
6254 }
6255
b6b8a145
JK		 6256 if (inject_pending_event(vcpu, req_int_win) != 0)
6257 req_immediate_exit = true;
b463a6f7 6258 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6259 else if (vcpu->arch.nmi_pending)
c9a7953f 6260 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6261 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6262 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6263
6264 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6265 /*
6266 * Update architecture specific hints for APIC
6267 * virtual interrupt delivery.
6268 */
6269 if (kvm_x86_ops->hwapic_irr_update)
6270 kvm_x86_ops->hwapic_irr_update(vcpu,
6271 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6272 update_cr8_intercept(vcpu);
6273 kvm_lapic_sync_to_vapic(vcpu);
6274 }
6275 }
6276
d8368af8
AK		 6277 r = kvm_mmu_reload(vcpu);
6278 if (unlikely(r)) {
d905c069 6279 goto cancel_injection;
d8368af8
AK		 6280 }
6281
b6c7a5dc
HB		 6282 preempt_disable();
6283
6284 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6285 if (vcpu->fpu_active)
6286 kvm_load_guest_fpu(vcpu);
2acf923e 6287 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6288
6b7e2d09
XG		 6289 vcpu->mode = IN_GUEST_MODE;
6290
01b71917
MT		 6291 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6292
6b7e2d09
XG		 6293 /* We should set ->mode before check ->requests,
6294 * see the comment in make_all_cpus_request.
6295 */
01b71917 6296 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6297
d94e1dc9 6298 local_irq_disable();
32f88400 6299
6b7e2d09 6300 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6301 || need_resched() || signal_pending(current)) {
6b7e2d09 6302 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6303 smp_wmb();
6c142801
AK		 6304 local_irq_enable();
6305 preempt_enable();
01b71917 6306 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6307 r = 1;
d905c069 6308 goto cancel_injection;
6c142801
AK		 6309 }
6310
d6185f20
NHE		 6311 if (req_immediate_exit)
6312 smp_send_reschedule(vcpu->cpu);
6313
b6c7a5dc
HB		 6314 kvm_guest_enter();
6315
42dbaa5a 6316 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6317 set_debugreg(0, 7);
6318 set_debugreg(vcpu->arch.eff_db[0], 0);
6319 set_debugreg(vcpu->arch.eff_db[1], 1);
6320 set_debugreg(vcpu->arch.eff_db[2], 2);
6321 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6322 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6323 }
b6c7a5dc 6324
229456fc 6325 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6326 wait_lapic_expire(vcpu);
851ba692 6327 kvm_x86_ops->run(vcpu);
b6c7a5dc 6328
c77fb5fe
PB		 6329 /*
6330 * Do this here before restoring debug registers on the host. And
6331 * since we do this before handling the vmexit, a DR access vmexit
6332 * can (a) read the correct value of the debug registers, (b) set
6333 * KVM_DEBUGREG_WONT_EXIT again.
6334 */
6335 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6336 int i;
6337
6338 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6339 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6340 for (i = 0; i < KVM_NR_DB_REGS; i++)
6341 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6342 }
6343
24f1e32c
FW		 6344 /*
6345 * If the guest has used debug registers, at least dr7
6346 * will be disabled while returning to the host.
6347 * If we don't have active breakpoints in the host, we don't
6348 * care about the messed up debug address registers. But if
6349 * we have some of them active, restore the old state.
6350 */
59d8eb53 6351 if (hw_breakpoint_active())
24f1e32c 6352 hw_breakpoint_restore();
42dbaa5a 6353
886b470c
MT		 6354 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6355 native_read_tsc());
1d5f066e 6356
6b7e2d09 6357 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6358 smp_wmb();
a547c6db
YZ		 6359
6360 /* Interrupt is enabled by handle_external_intr() */
6361 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6362
6363 ++vcpu->stat.exits;
6364
6365 /*
6366 * We must have an instruction between local_irq_enable() and
6367 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6368 * the interrupt shadow. The stat.exits increment will do nicely.
6369 * But we need to prevent reordering, hence this barrier():
6370 */
6371 barrier();
6372
6373 kvm_guest_exit();
6374
6375 preempt_enable();
6376
f656ce01 6377 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6378
b6c7a5dc
HB		 6379 /*
6380 * Profile KVM exit RIPs:
6381 */
6382 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6383 unsigned long rip = kvm_rip_read(vcpu);
6384 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6385 }
6386
cc578287
ZA		 6387 if (unlikely(vcpu->arch.tsc_always_catchup))
6388 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6389
5cfb1d5a
MT		 6390 if (vcpu->arch.apic_attention)
6391 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6392
851ba692 6393 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6394 return r;
6395
6396cancel_injection:
6397 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6398 if (unlikely(vcpu->arch.apic_attention))
6399 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6400out:
6401 return r;
6402}
b6c7a5dc 6403
09cec754 6404
851ba692 6405static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6406{
6407 int r;
f656ce01 6408 struct kvm *kvm = vcpu->kvm;
d7690175 6409
f656ce01 6410 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6411
6412 r = 1;
6413 while (r > 0) {
af585b92
GN		 6414 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6415 !vcpu->arch.apf.halted)
851ba692 6416 r = vcpu_enter_guest(vcpu);
d7690175 6417 else {
f656ce01 6418 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6419 kvm_vcpu_block(vcpu);
f656ce01 6420 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6421 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6422 kvm_apic_accept_events(vcpu);
09cec754
GN		 6423 switch(vcpu->arch.mp_state) {
6424 case KVM_MP_STATE_HALTED:
6aef266c 6425 vcpu->arch.pv.pv_unhalted = false;
d7690175 6426 vcpu->arch.mp_state =
09cec754
GN		 6427 KVM_MP_STATE_RUNNABLE;
6428 case KVM_MP_STATE_RUNNABLE:
af585b92 6429 vcpu->arch.apf.halted = false;
09cec754 6430 break;
66450a21
JK		 6431 case KVM_MP_STATE_INIT_RECEIVED:
6432 break;
09cec754
GN		 6433 default:
6434 r = -EINTR;
6435 break;
6436 }
6437 }
d7690175
MT		 6438 }
6439
09cec754
GN		 6440 if (r <= 0)
6441 break;
6442
6443 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6444 if (kvm_cpu_has_pending_timer(vcpu))
6445 kvm_inject_pending_timer_irqs(vcpu);
6446
851ba692 6447 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6448 r = -EINTR;
851ba692 6449 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6450 ++vcpu->stat.request_irq_exits;
6451 }
af585b92
GN		 6452
6453 kvm_check_async_pf_completion(vcpu);
6454
09cec754
GN		 6455 if (signal_pending(current)) {
6456 r = -EINTR;
851ba692 6457 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6458 ++vcpu->stat.signal_exits;
6459 }
6460 if (need_resched()) {
f656ce01 6461 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6462 cond_resched();
f656ce01 6463 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6464 }
b6c7a5dc
HB		 6465 }
6466
f656ce01 6467 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6468
6469 return r;
6470}
6471
716d51ab
GN		 6472static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6473{
6474 int r;
6475 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6476 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6477 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6478 if (r != EMULATE_DONE)
6479 return 0;
6480 return 1;
6481}
6482
6483static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6484{
6485 BUG_ON(!vcpu->arch.pio.count);
6486
6487 return complete_emulated_io(vcpu);
6488}
6489
f78146b0
AK		 6490/*
6491 * Implements the following, as a state machine:
6492 *
6493 * read:
6494 * for each fragment
87da7e66
XG		 6495 * for each mmio piece in the fragment
6496 * write gpa, len
6497 * exit
6498 * copy data
f78146b0
AK		 6499 * execute insn
6500 *
6501 * write:
6502 * for each fragment
87da7e66
XG		 6503 * for each mmio piece in the fragment
6504 * write gpa, len
6505 * copy data
6506 * exit
f78146b0 6507 */
716d51ab 6508static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6509{
6510 struct kvm_run *run = vcpu->run;
f78146b0 6511 struct kvm_mmio_fragment *frag;
87da7e66 6512 unsigned len;
5287f194 6513
716d51ab 6514 BUG_ON(!vcpu->mmio_needed);
5287f194 6515
716d51ab 6516 /* Complete previous fragment */
87da7e66
XG		 6517 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6518 len = min(8u, frag->len);
716d51ab 6519 if (!vcpu->mmio_is_write)
87da7e66
XG		 6520 memcpy(frag->data, run->mmio.data, len);
6521
6522 if (frag->len <= 8) {
6523 /* Switch to the next fragment. */
6524 frag++;
6525 vcpu->mmio_cur_fragment++;
6526 } else {
6527 /* Go forward to the next mmio piece. */
6528 frag->data += len;
6529 frag->gpa += len;
6530 frag->len -= len;
6531 }
6532
a08d3b3b 6533 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6534 vcpu->mmio_needed = 0;
0912c977
PB		 6535
6536 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6537 if (vcpu->mmio_is_write)
716d51ab
GN		 6538 return 1;
6539 vcpu->mmio_read_completed = 1;
6540 return complete_emulated_io(vcpu);
6541 }
87da7e66 6542
716d51ab
GN		 6543 run->exit_reason = KVM_EXIT_MMIO;
6544 run->mmio.phys_addr = frag->gpa;
6545 if (vcpu->mmio_is_write)
87da7e66
XG		 6546 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6547 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6548 run->mmio.is_write = vcpu->mmio_is_write;
6549 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6550 return 0;
5287f194
AK		 6551}
6552
716d51ab 6553
b6c7a5dc
HB		 6554int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6555{
6556 int r;
6557 sigset_t sigsaved;
6558
e5c30142
AK		 6559 if (!tsk_used_math(current) && init_fpu(current))
6560 return -ENOMEM;
6561
ac9f6dc0
AK		 6562 if (vcpu->sigset_active)
6563 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6564
a4535290 6565 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6566 kvm_vcpu_block(vcpu);
66450a21 6567 kvm_apic_accept_events(vcpu);
d7690175 6568 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6569 r = -EAGAIN;
6570 goto out;
b6c7a5dc
HB		 6571 }
6572
b6c7a5dc 6573 /* re-sync apic's tpr */
eea1cff9
AP		 6574 if (!irqchip_in_kernel(vcpu->kvm)) {
6575 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6576 r = -EINVAL;
6577 goto out;
6578 }
6579 }
b6c7a5dc 6580
716d51ab
GN		 6581 if (unlikely(vcpu->arch.complete_userspace_io)) {
6582 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6583 vcpu->arch.complete_userspace_io = NULL;
6584 r = cui(vcpu);
6585 if (r <= 0)
6586 goto out;
6587 } else
6588 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6589
851ba692 6590 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6591
6592out:
f1d86e46 6593 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6594 if (vcpu->sigset_active)
6595 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6596
b6c7a5dc
HB		 6597 return r;
6598}
6599
6600int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6601{
7ae441ea
GN		 6602 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6603 /*
6604 * We are here if userspace calls get_regs() in the middle of
6605 * instruction emulation. Registers state needs to be copied
4a969980 6606 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6607 * that usually, but some bad designed PV devices (vmware
6608 * backdoor interface) need this to work
6609 */
dd856efa 6610 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6611 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6612 }
5fdbf976
MT		 6613 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6614 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6615 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6616 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6617 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6618 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6619 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6620 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6621#ifdef CONFIG_X86_64
5fdbf976
MT		 6622 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6623 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6624 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6625 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6626 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6627 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6628 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6629 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6630#endif
6631
5fdbf976 6632 regs->rip = kvm_rip_read(vcpu);
91586a3b 6633 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6634
b6c7a5dc
HB		 6635 return 0;
6636}
6637
6638int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6639{
7ae441ea
GN		 6640 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6641 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6642
5fdbf976
MT		 6643 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6644 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6645 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6646 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6647 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6648 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6649 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6650 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6651#ifdef CONFIG_X86_64
5fdbf976
MT		 6652 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6653 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6654 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6655 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6656 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6657 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6658 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6659 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6660#endif
6661
5fdbf976 6662 kvm_rip_write(vcpu, regs->rip);
91586a3b 6663 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6664
b4f14abd
JK		 6665 vcpu->arch.exception.pending = false;
6666
3842d135
AK		 6667 kvm_make_request(KVM_REQ_EVENT, vcpu);
6668
b6c7a5dc
HB		 6669 return 0;
6670}
6671
b6c7a5dc
HB		 6672void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6673{
6674 struct kvm_segment cs;
6675
3e6e0aab 6676 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6677 *db = cs.db;
6678 *l = cs.l;
6679}
6680EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6681
6682int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6683 struct kvm_sregs *sregs)
6684{
89a27f4d 6685 struct desc_ptr dt;
b6c7a5dc 6686
3e6e0aab
GT		 6687 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6688 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6689 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6690 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6691 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6692 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6693
3e6e0aab
GT		 6694 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6695 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6696
6697 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6698 sregs->idt.limit = dt.size;
6699 sregs->idt.base = dt.address;
b6c7a5dc 6700 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6701 sregs->gdt.limit = dt.size;
6702 sregs->gdt.base = dt.address;
b6c7a5dc 6703
4d4ec087 6704 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6705 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6706 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6707 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6708 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6709 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6710 sregs->apic_base = kvm_get_apic_base(vcpu);
6711
923c61bb 6712 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6713
36752c9b 6714 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6715 set_bit(vcpu->arch.interrupt.nr,
6716 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6717
b6c7a5dc
HB		 6718 return 0;
6719}
6720
62d9f0db
MT		 6721int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6722 struct kvm_mp_state *mp_state)
6723{
66450a21 6724 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6725 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6726 vcpu->arch.pv.pv_unhalted)
6727 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6728 else
6729 mp_state->mp_state = vcpu->arch.mp_state;
6730
62d9f0db
MT		 6731 return 0;
6732}
6733
6734int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6735 struct kvm_mp_state *mp_state)
6736{
66450a21
JK		 6737 if (!kvm_vcpu_has_lapic(vcpu) &&
6738 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6739 return -EINVAL;
6740
6741 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6742 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6743 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6744 } else
6745 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6746 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6747 return 0;
6748}
6749
7f3d35fd
KW		 6750int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6751 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6752{
9d74191a 6753 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6754 int ret;
e01c2426 6755
8ec4722d 6756 init_emulate_ctxt(vcpu);
c697518a 6757
7f3d35fd 6758 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6759 has_error_code, error_code);
c697518a 6760
c697518a 6761 if (ret)
19d04437 6762 return EMULATE_FAIL;
37817f29 6763
9d74191a
TY		 6764 kvm_rip_write(vcpu, ctxt->eip);
6765 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6766 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6767 return EMULATE_DONE;
37817f29
IE		 6768}
6769EXPORT_SYMBOL_GPL(kvm_task_switch);
6770
b6c7a5dc
HB		 6771int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6772 struct kvm_sregs *sregs)
6773{
58cb628d 6774 struct msr_data apic_base_msr;
b6c7a5dc 6775 int mmu_reset_needed = 0;
63f42e02 6776 int pending_vec, max_bits, idx;
89a27f4d 6777 struct desc_ptr dt;
b6c7a5dc 6778
6d1068b3
PM		 6779 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6780 return -EINVAL;
6781
89a27f4d
GN		 6782 dt.size = sregs->idt.limit;
6783 dt.address = sregs->idt.base;
b6c7a5dc 6784 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6785 dt.size = sregs->gdt.limit;
6786 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6787 kvm_x86_ops->set_gdt(vcpu, &dt);
6788
ad312c7c 6789 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6790 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6791 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6793
2d3ad1f4 6794 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6795
f6801dff 6796 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6797 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6798 apic_base_msr.data = sregs->apic_base;
6799 apic_base_msr.host_initiated = true;
6800 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6801
4d4ec087 6802 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6803 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6804 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6805
fc78f519 6806 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6807 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6808 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6809 kvm_update_cpuid(vcpu);
63f42e02
XG		 6810
6811 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6812 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6813 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6814 mmu_reset_needed = 1;
6815 }
63f42e02 6816 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6817
6818 if (mmu_reset_needed)
6819 kvm_mmu_reset_context(vcpu);
6820
a50abc3b 6821 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6822 pending_vec = find_first_bit(
6823 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6824 if (pending_vec < max_bits) {
66fd3f7f 6825 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6826 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6827 }
6828
3e6e0aab
GT		 6829 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6830 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6831 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6832 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6833 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6834 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6835
3e6e0aab
GT		 6836 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6837 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6838
5f0269f5
ME		 6839 update_cr8_intercept(vcpu);
6840
9c3e4aab 6841 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6842 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6843 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6844 !is_protmode(vcpu))
9c3e4aab
MT		 6845 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6846
3842d135
AK		 6847 kvm_make_request(KVM_REQ_EVENT, vcpu);
6848
b6c7a5dc
HB		 6849 return 0;
6850}
6851
d0bfb940
JK		 6852int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6853 struct kvm_guest_debug *dbg)
b6c7a5dc 6854{
355be0b9 6855 unsigned long rflags;
ae675ef0 6856 int i, r;
b6c7a5dc 6857
4f926bf2
JK		 6858 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6859 r = -EBUSY;
6860 if (vcpu->arch.exception.pending)
2122ff5e 6861 goto out;
4f926bf2
JK		 6862 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6863 kvm_queue_exception(vcpu, DB_VECTOR);
6864 else
6865 kvm_queue_exception(vcpu, BP_VECTOR);
6866 }
6867
91586a3b
JK		 6868 /*
6869 * Read rflags as long as potentially injected trace flags are still
6870 * filtered out.
6871 */
6872 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6873
6874 vcpu->guest_debug = dbg->control;
6875 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6876 vcpu->guest_debug = 0;
6877
6878 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6879 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6880 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6881 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6882 } else {
6883 for (i = 0; i < KVM_NR_DB_REGS; i++)
6884 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6885 }
c8639010 6886 kvm_update_dr7(vcpu);
ae675ef0 6887
f92653ee
JK		 6888 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6889 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6890 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6891
91586a3b
JK		 6892 /*
6893 * Trigger an rflags update that will inject or remove the trace
6894 * flags.
6895 */
6896 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6897
c8639010 6898 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6899
4f926bf2 6900 r = 0;
d0bfb940 6901
2122ff5e 6902out:
b6c7a5dc
HB		 6903
6904 return r;
6905}
6906
8b006791
ZX		 6907/*
6908 * Translate a guest virtual address to a guest physical address.
6909 */
6910int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6911 struct kvm_translation *tr)
6912{
6913 unsigned long vaddr = tr->linear_address;
6914 gpa_t gpa;
f656ce01 6915 int idx;
8b006791 6916
f656ce01 6917 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6918 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6919 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6920 tr->physical_address = gpa;
6921 tr->valid = gpa != UNMAPPED_GVA;
6922 tr->writeable = 1;
6923 tr->usermode = 0;
8b006791
ZX		 6924
6925 return 0;
6926}
6927
d0752060
HB		 6928int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6929{
98918833
SY		 6930 struct i387_fxsave_struct *fxsave =
6931 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6932
d0752060
HB		 6933 memcpy(fpu->fpr, fxsave->st_space, 128);
6934 fpu->fcw = fxsave->cwd;
6935 fpu->fsw = fxsave->swd;
6936 fpu->ftwx = fxsave->twd;
6937 fpu->last_opcode = fxsave->fop;
6938 fpu->last_ip = fxsave->rip;
6939 fpu->last_dp = fxsave->rdp;
6940 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6941
d0752060
HB		 6942 return 0;
6943}
6944
6945int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6946{
98918833
SY		 6947 struct i387_fxsave_struct *fxsave =
6948 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6949
d0752060
HB		 6950 memcpy(fxsave->st_space, fpu->fpr, 128);
6951 fxsave->cwd = fpu->fcw;
6952 fxsave->swd = fpu->fsw;
6953 fxsave->twd = fpu->ftwx;
6954 fxsave->fop = fpu->last_opcode;
6955 fxsave->rip = fpu->last_ip;
6956 fxsave->rdp = fpu->last_dp;
6957 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6958
d0752060
HB		 6959 return 0;
6960}
6961
10ab25cd 6962int fx_init(struct kvm_vcpu *vcpu)
d0752060 6963{
10ab25cd
JK		 6964 int err;
6965
6966 err = fpu_alloc(&vcpu->arch.guest_fpu);
6967 if (err)
6968 return err;
6969
98918833 6970 fpu_finit(&vcpu->arch.guest_fpu);
df1daba7
PB		 6971 if (cpu_has_xsaves)
6972 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
6973 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 6974
2acf923e
DC		 6975 /*
6976 * Ensure guest xcr0 is valid for loading
6977 */
6978 vcpu->arch.xcr0 = XSTATE_FP;
6979
ad312c7c 6980 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6981
6982 return 0;
d0752060
HB		 6983}
6984EXPORT_SYMBOL_GPL(fx_init);
6985
98918833
SY		 6986static void fx_free(struct kvm_vcpu *vcpu)
6987{
6988 fpu_free(&vcpu->arch.guest_fpu);
6989}
6990
d0752060
HB		 6991void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6992{
2608d7a1 6993 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6994 return;
6995
2acf923e
DC		 6996 /*
6997 * Restore all possible states in the guest,
6998 * and assume host would use all available bits.
6999 * Guest xcr0 would be loaded later.
7000 */
7001 kvm_put_guest_xcr0(vcpu);
d0752060 7002 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7003 __kernel_fpu_begin();
98918833 7004 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7005 trace_kvm_fpu(1);
d0752060 7006}
d0752060
HB		 7007
7008void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7009{
2acf923e
DC		 7010 kvm_put_guest_xcr0(vcpu);
7011
d0752060
HB		 7012 if (!vcpu->guest_fpu_loaded)
7013 return;
7014
7015 vcpu->guest_fpu_loaded = 0;
98918833 7016 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7017 __kernel_fpu_end();
f096ed85 7018 ++vcpu->stat.fpu_reload;
a8eeb04a 7019 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 7020 trace_kvm_fpu(0);
d0752060 7021}
e9b11c17
ZX		 7022
7023void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7024{
12f9a48f 7025 kvmclock_reset(vcpu);
7f1ea208 7026
f5f48ee1 7027 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7028 fx_free(vcpu);
e9b11c17
ZX		 7029 kvm_x86_ops->vcpu_free(vcpu);
7030}
7031
7032struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7033 unsigned int id)
7034{
6755bae8
ZA		 7035 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7036 printk_once(KERN_WARNING
7037 "kvm: SMP vm created on host with unstable TSC; "
7038 "guest TSC will not be reliable\n");
26e5215f
AK		 7039 return kvm_x86_ops->vcpu_create(kvm, id);
7040}
e9b11c17 7041
26e5215f
AK		 7042int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7043{
7044 int r;
e9b11c17 7045
0bed3b56 7046 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7047 r = vcpu_load(vcpu);
7048 if (r)
7049 return r;
57f252f2 7050 kvm_vcpu_reset(vcpu);
8a3c1a33 7051 kvm_mmu_setup(vcpu);
e9b11c17 7052 vcpu_put(vcpu);
e9b11c17 7053
26e5215f 7054 return r;
e9b11c17
ZX		 7055}
7056
42897d86
MT		 7057int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7058{
7059 int r;
8fe8ab46 7060 struct msr_data msr;
332967a3 7061 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 7062
7063 r = vcpu_load(vcpu);
7064 if (r)
7065 return r;
8fe8ab46
WA		 7066 msr.data = 0x0;
7067 msr.index = MSR_IA32_TSC;
7068 msr.host_initiated = true;
7069 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7070 vcpu_put(vcpu);
7071
332967a3
AJ		 7072 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7073 KVMCLOCK_SYNC_PERIOD);
7074
42897d86
MT		 7075 return r;
7076}
7077
d40ccc62 7078void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7079{
9fc77441 7080 int r;
344d9588
GN		 7081 vcpu->arch.apf.msr_val = 0;
7082
9fc77441
MT		 7083 r = vcpu_load(vcpu);
7084 BUG_ON(r);
e9b11c17
ZX		 7085 kvm_mmu_unload(vcpu);
7086 vcpu_put(vcpu);
7087
98918833 7088 fx_free(vcpu);
e9b11c17
ZX		 7089 kvm_x86_ops->vcpu_free(vcpu);
7090}
7091
66450a21 7092void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 7093{
7460fb4a
AK		 7094 atomic_set(&vcpu->arch.nmi_queued, 0);
7095 vcpu->arch.nmi_pending = 0;
448fa4a9 7096 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7097 kvm_clear_interrupt_queue(vcpu);
7098 kvm_clear_exception_queue(vcpu);
448fa4a9 7099
42dbaa5a 7100 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 7101 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7102 kvm_update_dr6(vcpu);
42dbaa5a 7103 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7104 kvm_update_dr7(vcpu);
42dbaa5a 7105
3842d135 7106 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7107 vcpu->arch.apf.msr_val = 0;
c9aaa895 7108 vcpu->arch.st.msr_val = 0;
3842d135 7109
12f9a48f
GC		 7110 kvmclock_reset(vcpu);
7111
af585b92
GN		 7112 kvm_clear_async_pf_completion_queue(vcpu);
7113 kvm_async_pf_hash_reset(vcpu);
7114 vcpu->arch.apf.halted = false;
3842d135 7115
f5132b01
GN		 7116 kvm_pmu_reset(vcpu);
7117
66f7b72e
JS		 7118 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7119 vcpu->arch.regs_avail = ~0;
7120 vcpu->arch.regs_dirty = ~0;
7121
57f252f2 7122 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7123}
7124
2b4a273b 7125void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7126{
7127 struct kvm_segment cs;
7128
7129 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7130 cs.selector = vector << 8;
7131 cs.base = vector << 12;
7132 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7133 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7134}
7135
13a34e06 7136int kvm_arch_hardware_enable(void)
e9b11c17 7137{
ca84d1a2
ZA		 7138 struct kvm *kvm;
7139 struct kvm_vcpu *vcpu;
7140 int i;
0dd6a6ed
ZA		 7141 int ret;
7142 u64 local_tsc;
7143 u64 max_tsc = 0;
7144 bool stable, backwards_tsc = false;
18863bdd
AK		 7145
7146 kvm_shared_msr_cpu_online();
13a34e06 7147 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7148 if (ret != 0)
7149 return ret;
7150
7151 local_tsc = native_read_tsc();
7152 stable = !check_tsc_unstable();
7153 list_for_each_entry(kvm, &vm_list, vm_list) {
7154 kvm_for_each_vcpu(i, vcpu, kvm) {
7155 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7156 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7157 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7158 backwards_tsc = true;
7159 if (vcpu->arch.last_host_tsc > max_tsc)
7160 max_tsc = vcpu->arch.last_host_tsc;
7161 }
7162 }
7163 }
7164
7165 /*
7166 * Sometimes, even reliable TSCs go backwards. This happens on
7167 * platforms that reset TSC during suspend or hibernate actions, but
7168 * maintain synchronization. We must compensate. Fortunately, we can
7169 * detect that condition here, which happens early in CPU bringup,
7170 * before any KVM threads can be running. Unfortunately, we can't
7171 * bring the TSCs fully up to date with real time, as we aren't yet far
7172 * enough into CPU bringup that we know how much real time has actually
7173 * elapsed; our helper function, get_kernel_ns() will be using boot
7174 * variables that haven't been updated yet.
7175 *
7176 * So we simply find the maximum observed TSC above, then record the
7177 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7178 * the adjustment will be applied. Note that we accumulate
7179 * adjustments, in case multiple suspend cycles happen before some VCPU
7180 * gets a chance to run again. In the event that no KVM threads get a
7181 * chance to run, we will miss the entire elapsed period, as we'll have
7182 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7183 * loose cycle time. This isn't too big a deal, since the loss will be
7184 * uniform across all VCPUs (not to mention the scenario is extremely
7185 * unlikely). It is possible that a second hibernate recovery happens
7186 * much faster than a first, causing the observed TSC here to be
7187 * smaller; this would require additional padding adjustment, which is
7188 * why we set last_host_tsc to the local tsc observed here.
7189 *
7190 * N.B. - this code below runs only on platforms with reliable TSC,
7191 * as that is the only way backwards_tsc is set above. Also note
7192 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7193 * have the same delta_cyc adjustment applied if backwards_tsc
7194 * is detected. Note further, this adjustment is only done once,
7195 * as we reset last_host_tsc on all VCPUs to stop this from being
7196 * called multiple times (one for each physical CPU bringup).
7197 *
4a969980 7198 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7199 * will be compensated by the logic in vcpu_load, which sets the TSC to
7200 * catchup mode. This will catchup all VCPUs to real time, but cannot
7201 * guarantee that they stay in perfect synchronization.
7202 */
7203 if (backwards_tsc) {
7204 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7205 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7206 list_for_each_entry(kvm, &vm_list, vm_list) {
7207 kvm_for_each_vcpu(i, vcpu, kvm) {
7208 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7209 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7210 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7211 }
7212
7213 /*
7214 * We have to disable TSC offset matching.. if you were
7215 * booting a VM while issuing an S4 host suspend....
7216 * you may have some problem. Solving this issue is
7217 * left as an exercise to the reader.
7218 */
7219 kvm->arch.last_tsc_nsec = 0;
7220 kvm->arch.last_tsc_write = 0;
7221 }
7222
7223 }
7224 return 0;
e9b11c17
ZX		 7225}
7226
13a34e06 7227void kvm_arch_hardware_disable(void)
e9b11c17 7228{
13a34e06
RK		 7229 kvm_x86_ops->hardware_disable();
7230 drop_user_return_notifiers();
e9b11c17
ZX		 7231}
7232
7233int kvm_arch_hardware_setup(void)
7234{
7235 return kvm_x86_ops->hardware_setup();
7236}
7237
7238void kvm_arch_hardware_unsetup(void)
7239{
7240 kvm_x86_ops->hardware_unsetup();
7241}
7242
7243void kvm_arch_check_processor_compat(void *rtn)
7244{
7245 kvm_x86_ops->check_processor_compatibility(rtn);
7246}
7247
3e515705
AK		 7248bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7249{
7250 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7251}
7252
54e9818f
GN		 7253struct static_key kvm_no_apic_vcpu __read_mostly;
7254
e9b11c17
ZX		 7255int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7256{
7257 struct page *page;
7258 struct kvm *kvm;
7259 int r;
7260
7261 BUG_ON(vcpu->kvm == NULL);
7262 kvm = vcpu->kvm;
7263
6aef266c 7264 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7265 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7266 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7267 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7268 else
a4535290 7269 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7270
7271 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7272 if (!page) {
7273 r = -ENOMEM;
7274 goto fail;
7275 }
ad312c7c 7276 vcpu->arch.pio_data = page_address(page);
e9b11c17 7277
cc578287 7278 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7279
e9b11c17
ZX		 7280 r = kvm_mmu_create(vcpu);
7281 if (r < 0)
7282 goto fail_free_pio_data;
7283
7284 if (irqchip_in_kernel(kvm)) {
7285 r = kvm_create_lapic(vcpu);
7286 if (r < 0)
7287 goto fail_mmu_destroy;
54e9818f
GN		 7288 } else
7289 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7290
890ca9ae
HY		 7291 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7292 GFP_KERNEL);
7293 if (!vcpu->arch.mce_banks) {
7294 r = -ENOMEM;
443c39bc 7295 goto fail_free_lapic;
890ca9ae
HY		 7296 }
7297 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7298
f1797359
WY		 7299 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7300 r = -ENOMEM;
f5f48ee1 7301 goto fail_free_mce_banks;
f1797359 7302 }
f5f48ee1 7303
66f7b72e
JS		 7304 r = fx_init(vcpu);
7305 if (r)
7306 goto fail_free_wbinvd_dirty_mask;
7307
ba904635 7308 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7309 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7310
7311 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7312 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7313
af585b92 7314 kvm_async_pf_hash_reset(vcpu);
f5132b01 7315 kvm_pmu_init(vcpu);
af585b92 7316
e9b11c17 7317 return 0;
66f7b72e
JS		 7318fail_free_wbinvd_dirty_mask:
7319 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7320fail_free_mce_banks:
7321 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7322fail_free_lapic:
7323 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7324fail_mmu_destroy:
7325 kvm_mmu_destroy(vcpu);
7326fail_free_pio_data:
ad312c7c 7327 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7328fail:
7329 return r;
7330}
7331
7332void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7333{
f656ce01
MT		 7334 int idx;
7335
f5132b01 7336 kvm_pmu_destroy(vcpu);
36cb93fd 7337 kfree(vcpu->arch.mce_banks);
e9b11c17 7338 kvm_free_lapic(vcpu);
f656ce01 7339 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7340 kvm_mmu_destroy(vcpu);
f656ce01 7341 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7342 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7343 if (!irqchip_in_kernel(vcpu->kvm))
7344 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7345}
d19a9cd2 7346
e790d9ef
RK		 7347void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7348{
ae97a3b8 7349 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7350}
7351
e08b9637 7352int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7353{
e08b9637
CO		 7354 if (type)
7355 return -EINVAL;
7356
6ef768fa 7357 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7358 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7359 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7360 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7361 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7362
5550af4d
SY		 7363 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7364 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7365 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7366 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7367 &kvm->arch.irq_sources_bitmap);
5550af4d 7368
038f8c11 7369 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7370 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7371 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7372
7373 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7374
7e44e449 7375 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7376 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7377
d89f5eff 7378 return 0;
d19a9cd2
ZX		 7379}
7380
7381static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7382{
9fc77441
MT		 7383 int r;
7384 r = vcpu_load(vcpu);
7385 BUG_ON(r);
d19a9cd2
ZX		 7386 kvm_mmu_unload(vcpu);
7387 vcpu_put(vcpu);
7388}
7389
7390static void kvm_free_vcpus(struct kvm *kvm)
7391{
7392 unsigned int i;
988a2cae 7393 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7394
7395 /*
7396 * Unpin any mmu pages first.
7397 */
af585b92
GN		 7398 kvm_for_each_vcpu(i, vcpu, kvm) {
7399 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7400 kvm_unload_vcpu_mmu(vcpu);
af585b92 7401 }
988a2cae
GN		 7402 kvm_for_each_vcpu(i, vcpu, kvm)
7403 kvm_arch_vcpu_free(vcpu);
7404
7405 mutex_lock(&kvm->lock);
7406 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7407 kvm->vcpus[i] = NULL;
d19a9cd2 7408
988a2cae
GN		 7409 atomic_set(&kvm->online_vcpus, 0);
7410 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7411}
7412
ad8ba2cd
SY		 7413void kvm_arch_sync_events(struct kvm *kvm)
7414{
332967a3 7415 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7416 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7417 kvm_free_all_assigned_devices(kvm);
aea924f6 7418 kvm_free_pit(kvm);
ad8ba2cd
SY		 7419}
7420
d19a9cd2
ZX		 7421void kvm_arch_destroy_vm(struct kvm *kvm)
7422{
27469d29
AH		 7423 if (current->mm == kvm->mm) {
7424 /*
7425 * Free memory regions allocated on behalf of userspace,
7426 * unless the the memory map has changed due to process exit
7427 * or fd copying.
7428 */
7429 struct kvm_userspace_memory_region mem;
7430 memset(&mem, 0, sizeof(mem));
7431 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7432 kvm_set_memory_region(kvm, &mem);
7433
7434 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7435 kvm_set_memory_region(kvm, &mem);
7436
7437 mem.slot = TSS_PRIVATE_MEMSLOT;
7438 kvm_set_memory_region(kvm, &mem);
7439 }
6eb55818 7440 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7441 kfree(kvm->arch.vpic);
7442 kfree(kvm->arch.vioapic);
d19a9cd2 7443 kvm_free_vcpus(kvm);
1e08ec4a 7444 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7445}
0de10343 7446
5587027c 7447void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7448 struct kvm_memory_slot *dont)
7449{
7450 int i;
7451
d89cc617
TY		 7452 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7453 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7454 kvm_kvfree(free->arch.rmap[i]);
7455 free->arch.rmap[i] = NULL;
77d11309 7456 }
d89cc617
TY		 7457 if (i == 0)
7458 continue;
7459
7460 if (!dont || free->arch.lpage_info[i - 1] !=
7461 dont->arch.lpage_info[i - 1]) {
7462 kvm_kvfree(free->arch.lpage_info[i - 1]);
7463 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7464 }
7465 }
7466}
7467
5587027c
AK		 7468int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7469 unsigned long npages)
db3fe4eb
TY		 7470{
7471 int i;
7472
d89cc617 7473 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7474 unsigned long ugfn;
7475 int lpages;
d89cc617 7476 int level = i + 1;
db3fe4eb
TY		 7477
7478 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7479 slot->base_gfn, level) + 1;
7480
d89cc617
TY		 7481 slot->arch.rmap[i] =
7482 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7483 if (!slot->arch.rmap[i])
77d11309 7484 goto out_free;
d89cc617
TY		 7485 if (i == 0)
7486 continue;
77d11309 7487
d89cc617
TY		 7488 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7489 sizeof(*slot->arch.lpage_info[i - 1]));
7490 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7491 goto out_free;
7492
7493 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7494 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7495 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7496 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7497 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7498 /*
7499 * If the gfn and userspace address are not aligned wrt each
7500 * other, or if explicitly asked to, disable large page
7501 * support for this slot
7502 */
7503 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7504 !kvm_largepages_enabled()) {
7505 unsigned long j;
7506
7507 for (j = 0; j < lpages; ++j)
d89cc617 7508 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7509 }
7510 }
7511
7512 return 0;
7513
7514out_free:
d89cc617
TY		 7515 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7516 kvm_kvfree(slot->arch.rmap[i]);
7517 slot->arch.rmap[i] = NULL;
7518 if (i == 0)
7519 continue;
7520
7521 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7522 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7523 }
7524 return -ENOMEM;
7525}
7526
e59dbe09
TY		 7527void kvm_arch_memslots_updated(struct kvm *kvm)
7528{
e6dff7d1
TY		 7529 /*
7530 * memslots->generation has been incremented.
7531 * mmio generation may have reached its maximum value.
7532 */
7533 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7534}
7535
f7784b8e
MT		 7536int kvm_arch_prepare_memory_region(struct kvm *kvm,
7537 struct kvm_memory_slot *memslot,
f7784b8e 7538 struct kvm_userspace_memory_region *mem,
7b6195a9 7539 enum kvm_mr_change change)
0de10343 7540{
7a905b14
TY		 7541 /*
7542 * Only private memory slots need to be mapped here since
7543 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7544 */
7b6195a9 7545 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7546 unsigned long userspace_addr;
604b38ac 7547
7a905b14
TY		 7548 /*
7549 * MAP_SHARED to prevent internal slot pages from being moved
7550 * by fork()/COW.
7551 */
7b6195a9 7552 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7553 PROT_READ | PROT_WRITE,
7554 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7555
7a905b14
TY		 7556 if (IS_ERR((void *)userspace_addr))
7557 return PTR_ERR((void *)userspace_addr);
604b38ac 7558
7a905b14 7559 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7560 }
7561
f7784b8e
MT		 7562 return 0;
7563}
7564
7565void kvm_arch_commit_memory_region(struct kvm *kvm,
7566 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7567 const struct kvm_memory_slot *old,
7568 enum kvm_mr_change change)
f7784b8e
MT		 7569{
7570
8482644a 7571 int nr_mmu_pages = 0;
f7784b8e 7572
8482644a 7573 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7574 int ret;
7575
8482644a
TY		 7576 ret = vm_munmap(old->userspace_addr,
7577 old->npages * PAGE_SIZE);
f7784b8e
MT		 7578 if (ret < 0)
7579 printk(KERN_WARNING
7580 "kvm_vm_ioctl_set_memory_region: "
7581 "failed to munmap memory\n");
7582 }
7583
48c0e4e9
XG		 7584 if (!kvm->arch.n_requested_mmu_pages)
7585 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7586
48c0e4e9 7587 if (nr_mmu_pages)
0de10343 7588 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7589 /*
7590 * Write protect all pages for dirty logging.
c126d94f
XG		 7591 *
7592 * All the sptes including the large sptes which point to this
7593 * slot are set to readonly. We can not create any new large
7594 * spte on this slot until the end of the logging.
7595 *
7596 * See the comments in fast_page_fault().
c972f3b1 7597 */
8482644a 7598 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7599 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7600}
1d737c8a 7601
2df72e9b 7602void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7603{
6ca18b69 7604 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7605}
7606
2df72e9b
MT		 7607void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7608 struct kvm_memory_slot *slot)
7609{
6ca18b69 7610 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7611}
7612
1d737c8a
ZX		 7613int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7614{
b6b8a145
JK		 7615 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7616 kvm_x86_ops->check_nested_events(vcpu, false);
7617
af585b92
GN		 7618 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7619 !vcpu->arch.apf.halted)
7620 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7621 || kvm_apic_has_events(vcpu)
6aef266c 7622 || vcpu->arch.pv.pv_unhalted
7460fb4a 7623 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7624 (kvm_arch_interrupt_allowed(vcpu) &&
7625 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7626}
5736199a 7627
b6d33834 7628int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7629{
b6d33834 7630 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7631}
78646121
GN		 7632
7633int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7634{
7635 return kvm_x86_ops->interrupt_allowed(vcpu);
7636}
229456fc 7637
82b32774 7638unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7639{
82b32774
NA		 7640 if (is_64_bit_mode(vcpu))
7641 return kvm_rip_read(vcpu);
7642 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7643 kvm_rip_read(vcpu));
7644}
7645EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7646
82b32774
NA		 7647bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7648{
7649 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7650}
7651EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7652
94fe45da
JK		 7653unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7654{
7655 unsigned long rflags;
7656
7657 rflags = kvm_x86_ops->get_rflags(vcpu);
7658 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7659 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7660 return rflags;
7661}
7662EXPORT_SYMBOL_GPL(kvm_get_rflags);
7663
6addfc42 7664static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7665{
7666 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7667 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7668 rflags |= X86_EFLAGS_TF;
94fe45da 7669 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7670}
7671
7672void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7673{
7674 __kvm_set_rflags(vcpu, rflags);
3842d135 7675 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7676}
7677EXPORT_SYMBOL_GPL(kvm_set_rflags);
7678
56028d08
GN		 7679void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7680{
7681 int r;
7682
fb67e14f 7683 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7684 work->wakeup_all)
56028d08
GN		 7685 return;
7686
7687 r = kvm_mmu_reload(vcpu);
7688 if (unlikely(r))
7689 return;
7690
fb67e14f
XG		 7691 if (!vcpu->arch.mmu.direct_map &&
7692 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7693 return;
7694
56028d08
GN		 7695 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7696}
7697
af585b92
GN		 7698static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7699{
7700 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7701}
7702
7703static inline u32 kvm_async_pf_next_probe(u32 key)
7704{
7705 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7706}
7707
7708static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7709{
7710 u32 key = kvm_async_pf_hash_fn(gfn);
7711
7712 while (vcpu->arch.apf.gfns[key] != ~0)
7713 key = kvm_async_pf_next_probe(key);
7714
7715 vcpu->arch.apf.gfns[key] = gfn;
7716}
7717
7718static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7719{
7720 int i;
7721 u32 key = kvm_async_pf_hash_fn(gfn);
7722
7723 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7724 (vcpu->arch.apf.gfns[key] != gfn &&
7725 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7726 key = kvm_async_pf_next_probe(key);
7727
7728 return key;
7729}
7730
7731bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7732{
7733 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7734}
7735
7736static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7737{
7738 u32 i, j, k;
7739
7740 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7741 while (true) {
7742 vcpu->arch.apf.gfns[i] = ~0;
7743 do {
7744 j = kvm_async_pf_next_probe(j);
7745 if (vcpu->arch.apf.gfns[j] == ~0)
7746 return;
7747 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7748 /*
7749 * k lies cyclically in ]i,j]
7750 * | i.k.j |
7751 * |....j i.k.| or |.k..j i...|
7752 */
7753 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7754 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7755 i = j;
7756 }
7757}
7758
7c90705b
GN		 7759static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7760{
7761
7762 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7763 sizeof(val));
7764}
7765
af585b92
GN		 7766void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7767 struct kvm_async_pf *work)
7768{
6389ee94
AK		 7769 struct x86_exception fault;
7770
7c90705b 7771 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7772 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7773
7774 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7775 (vcpu->arch.apf.send_user_only &&
7776 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7777 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7778 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7779 fault.vector = PF_VECTOR;
7780 fault.error_code_valid = true;
7781 fault.error_code = 0;
7782 fault.nested_page_fault = false;
7783 fault.address = work->arch.token;
7784 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7785 }
af585b92
GN		 7786}
7787
7788void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7789 struct kvm_async_pf *work)
7790{
6389ee94
AK		 7791 struct x86_exception fault;
7792
7c90705b 7793 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7794 if (work->wakeup_all)
7c90705b
GN		 7795 work->arch.token = ~0; /* broadcast wakeup */
7796 else
7797 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7798
7799 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7800 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7801 fault.vector = PF_VECTOR;
7802 fault.error_code_valid = true;
7803 fault.error_code = 0;
7804 fault.nested_page_fault = false;
7805 fault.address = work->arch.token;
7806 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7807 }
e6d53e3b 7808 vcpu->arch.apf.halted = false;
a4fa1635 7809 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7810}
7811
7812bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7813{
7814 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7815 return true;
7816 else
7817 return !kvm_event_needs_reinjection(vcpu) &&
7818 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7819}
7820
e0f0bbc5
AW		 7821void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7822{
7823 atomic_inc(&kvm->arch.noncoherent_dma_count);
7824}
7825EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7826
7827void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7828{
7829 atomic_dec(&kvm->arch.noncoherent_dma_count);
7830}
7831EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7832
7833bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7834{
7835 return atomic_read(&kvm->arch.noncoherent_dma_count);
7836}
7837EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7838
229456fc
MT		 7839EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7840EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7841EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7842EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7845EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7846EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux kernel - Deliverables
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