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KVM: introduce KVM_HVA_ERR_RO_BAD
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
d6aa1000
AK		 161int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
af585b92
GN		 163static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164{
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168}
169
18863bdd
AK		 170static void kvm_on_user_return(struct user_return_notifier *urn)
171{
172 unsigned slot;
18863bdd
AK		 173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 175 struct kvm_shared_msr_values *values;
18863bdd
AK		 176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
18863bdd
AK		 182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186}
187
2bf78fa7 188static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 189{
2bf78fa7 190 struct kvm_shared_msrs *smsr;
18863bdd
AK		 191 u64 value;
192
2bf78fa7
SY		 193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203}
204
205void kvm_define_shared_msr(unsigned slot, u32 msr)
206{
18863bdd
AK		 207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
18863bdd
AK		 212}
213EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215static void kvm_shared_msr_cpu_online(void)
216{
217 unsigned i;
18863bdd
AK		 218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 220 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 221}
222
d5696725 223void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
2bf78fa7 227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 228 return;
2bf78fa7
SY		 229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236}
237EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
3548bab5
AK		 239static void drop_user_return_notifiers(void *ignore)
240{
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245}
246
6866b83e
CO		 247u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248{
8a5a87d9 249 return vcpu->arch.apic_base;
6866b83e
CO		 250}
251EXPORT_SYMBOL_GPL(kvm_get_apic_base);
252
253void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
254{
255 /* TODO: reserve bits check */
8a5a87d9 256 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
7460fb4a
AK		 362 atomic_inc(&vcpu->arch.nmi_queued);
363 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
ad756a16
MJ		 525 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
526 return 1;
527
a03490ed 528 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 529
d170c419 530 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 531 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 532 kvm_async_pf_hash_reset(vcpu);
533 }
e5f3f027 534
aad82703
SY		 535 if ((cr0 ^ old_cr0) & update_bits)
536 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 537 return 0;
538}
2d3ad1f4 539EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 540
2d3ad1f4 541void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 542{
49a9b07e 543 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 546
2acf923e
DC		 547int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
548{
549 u64 xcr0;
550
551 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
552 if (index != XCR_XFEATURE_ENABLED_MASK)
553 return 1;
554 xcr0 = xcr;
555 if (kvm_x86_ops->get_cpl(vcpu) != 0)
556 return 1;
557 if (!(xcr0 & XSTATE_FP))
558 return 1;
559 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
560 return 1;
561 if (xcr0 & ~host_xcr0)
562 return 1;
563 vcpu->arch.xcr0 = xcr0;
564 vcpu->guest_xcr0_loaded = 0;
565 return 0;
566}
567
568int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
569{
570 if (__kvm_set_xcr(vcpu, index, xcr)) {
571 kvm_inject_gp(vcpu, 0);
572 return 1;
573 }
574 return 0;
575}
576EXPORT_SYMBOL_GPL(kvm_set_xcr);
577
a83b29c6 578int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 579{
fc78f519 580 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 581 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
582 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 583 if (cr4 & CR4_RESERVED_BITS)
584 return 1;
a03490ed 585
2acf923e
DC		 586 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
587 return 1;
588
c68b734f
YW		 589 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
590 return 1;
591
74dc2b4f
YW		 592 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
593 return 1;
594
a03490ed 595 if (is_long_mode(vcpu)) {
0f12244f
GN		 596 if (!(cr4 & X86_CR4_PAE))
597 return 1;
a2edf57f
AK		 598 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
599 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 600 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
601 kvm_read_cr3(vcpu)))
0f12244f
GN		 602 return 1;
603
ad756a16
MJ		 604 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
605 if (!guest_cpuid_has_pcid(vcpu))
606 return 1;
607
608 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
609 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
610 return 1;
611 }
612
5e1746d6 613 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 614 return 1;
a03490ed 615
ad756a16
MJ		 616 if (((cr4 ^ old_cr4) & pdptr_bits) ||
617 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 618 kvm_mmu_reset_context(vcpu);
0f12244f 619
2acf923e 620 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 621 kvm_update_cpuid(vcpu);
2acf923e 622
0f12244f
GN		 623 return 0;
624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 626
2390218b 627int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 628{
9f8fe504 629 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 630 kvm_mmu_sync_roots(vcpu);
d835dfec 631 kvm_mmu_flush_tlb(vcpu);
0f12244f 632 return 0;
d835dfec
AK		 633 }
634
a03490ed 635 if (is_long_mode(vcpu)) {
ad756a16
MJ		 636 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
637 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
638 return 1;
639 } else
640 if (cr3 & CR3_L_MODE_RESERVED_BITS)
641 return 1;
a03490ed
CO		 642 } else {
643 if (is_pae(vcpu)) {
0f12244f
GN		 644 if (cr3 & CR3_PAE_RESERVED_BITS)
645 return 1;
ff03a073
JR		 646 if (is_paging(vcpu) &&
647 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 648 return 1;
a03490ed
CO		 649 }
650 /*
651 * We don't check reserved bits in nonpae mode, because
652 * this isn't enforced, and VMware depends on this.
653 */
654 }
655
a03490ed
CO		 656 /*
657 * Does the new cr3 value map to physical memory? (Note, we
658 * catch an invalid cr3 even in real-mode, because it would
659 * cause trouble later on when we turn on paging anyway.)
660 *
661 * A real CPU would silently accept an invalid cr3 and would
662 * attempt to use it - with largely undefined (and often hard
663 * to debug) behavior on the guest side.
664 */
665 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 666 return 1;
667 vcpu->arch.cr3 = cr3;
aff48baa 668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 673
eea1cff9 674int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 675{
0f12244f
GN		 676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
a03490ed
CO		 678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
ad312c7c 681 vcpu->arch.cr8 = cr8;
0f12244f
GN		 682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 685
2d3ad1f4 686unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 687{
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
ad312c7c 691 return vcpu->arch.cr8;
a03490ed 692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 694
338dbc97 695static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 696{
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
338dbc97
GN		 704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
020df079
GN		 706 /* fall through */
707 case 6:
338dbc97
GN		 708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
020df079
GN		 710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
338dbc97
GN		 713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
020df079
GN		 715 /* fall through */
716 default: /* 7 */
338dbc97
GN		 717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
020df079
GN		 719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728}
338dbc97
GN		 729
730int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731{
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741}
020df079
GN		 742EXPORT_SYMBOL_GPL(kvm_set_dr);
743
338dbc97 744static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 745{
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
338dbc97 751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 752 return 1;
020df079
GN		 753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
338dbc97 758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 759 return 1;
020df079
GN		 760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770{
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776}
020df079
GN		 777EXPORT_SYMBOL_GPL(kvm_get_dr);
778
022cd0e8
AK		 779bool kvm_rdpmc(struct kvm_vcpu *vcpu)
780{
781 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
782 u64 data;
783 int err;
784
785 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
786 if (err)
787 return err;
788 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
789 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
790 return err;
791}
792EXPORT_SYMBOL_GPL(kvm_rdpmc);
793
043405e1
CO		 794/*
795 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
796 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
797 *
798 * This list is modified at module load time to reflect the
e3267cbb
GC		 799 * capabilities of the host cpu. This capabilities test skips MSRs that are
800 * kvm-specific. Those are put in the beginning of the list.
043405e1 801 */
e3267cbb 802
e115676e 803#define KVM_SAVE_MSRS_BEGIN 10
043405e1 804static u32 msrs_to_save[] = {
e3267cbb 805 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 806 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 807 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 808 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 809 MSR_KVM_PV_EOI_EN,
043405e1 810 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 811 MSR_STAR,
043405e1
CO		 812#ifdef CONFIG_X86_64
813 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
814#endif
e90aa41e 815 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 816};
817
818static unsigned num_msrs_to_save;
819
820static u32 emulated_msrs[] = {
a3e06bbe 821 MSR_IA32_TSCDEADLINE,
043405e1 822 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 823 MSR_IA32_MCG_STATUS,
824 MSR_IA32_MCG_CTL,
043405e1
CO		 825};
826
b69e8cae 827static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 828{
aad82703
SY		 829 u64 old_efer = vcpu->arch.efer;
830
b69e8cae
RJ		 831 if (efer & efer_reserved_bits)
832 return 1;
15c4a640
CO		 833
834 if (is_paging(vcpu)
b69e8cae
RJ		 835 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
836 return 1;
15c4a640 837
1b2fd70c
AG		 838 if (efer & EFER_FFXSR) {
839 struct kvm_cpuid_entry2 *feat;
840
841 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 842 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
843 return 1;
1b2fd70c
AG		 844 }
845
d8017474
AG		 846 if (efer & EFER_SVME) {
847 struct kvm_cpuid_entry2 *feat;
848
849 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 850 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
851 return 1;
d8017474
AG		 852 }
853
15c4a640 854 efer &= ~EFER_LMA;
f6801dff 855 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 856
a3d204e2
SY		 857 kvm_x86_ops->set_efer(vcpu, efer);
858
9645bb56 859 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 860
aad82703
SY		 861 /* Update reserved bits */
862 if ((efer ^ old_efer) & EFER_NX)
863 kvm_mmu_reset_context(vcpu);
864
b69e8cae 865 return 0;
15c4a640
CO		 866}
867
f2b4b7dd
JR		 868void kvm_enable_efer_bits(u64 mask)
869{
870 efer_reserved_bits &= ~mask;
871}
872EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
873
874
15c4a640
CO		 875/*
876 * Writes msr value into into the appropriate "register".
877 * Returns 0 on success, non-0 otherwise.
878 * Assumes vcpu_load() was already called.
879 */
880int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
881{
882 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
883}
884
313a3dc7
CO		 885/*
886 * Adapt set_msr() to msr_io()'s calling convention
887 */
888static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
889{
890 return kvm_set_msr(vcpu, index, *data);
891}
892
18068523
GOC		 893static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
894{
9ed3c444
AK		 895 int version;
896 int r;
50d0a0f9 897 struct pvclock_wall_clock wc;
923de3cf 898 struct timespec boot;
18068523
GOC		 899
900 if (!wall_clock)
901 return;
902
9ed3c444
AK		 903 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
904 if (r)
905 return;
906
907 if (version & 1)
908 ++version; /* first time write, random junk */
909
910 ++version;
18068523 911
18068523
GOC		 912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
913
50d0a0f9
GH		 914 /*
915 * The guest calculates current wall clock time by adding
34c238a1 916 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 917 * wall clock specified here. guest system time equals host
918 * system time for us, thus we must fill in host boot time here.
919 */
923de3cf 920 getboottime(&boot);
50d0a0f9 921
4b648665
BR		 922 if (kvm->arch.kvmclock_offset) {
923 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
924 boot = timespec_sub(boot, ts);
925 }
50d0a0f9
GH		 926 wc.sec = boot.tv_sec;
927 wc.nsec = boot.tv_nsec;
928 wc.version = version;
18068523
GOC		 929
930 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
931
932 version++;
933 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 934}
935
50d0a0f9
GH		 936static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
937{
938 uint32_t quotient, remainder;
939
940 /* Don't try to replace with do_div(), this one calculates
941 * "(dividend << 32) / divisor" */
942 __asm__ ( "divl %4"
943 : "=a" (quotient), "=d" (remainder)
944 : "0" (0), "1" (dividend), "r" (divisor) );
945 return quotient;
946}
947
5f4e3f88
ZA		 948static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
949 s8 *pshift, u32 *pmultiplier)
50d0a0f9 950{
5f4e3f88 951 uint64_t scaled64;
50d0a0f9
GH		 952 int32_t shift = 0;
953 uint64_t tps64;
954 uint32_t tps32;
955
5f4e3f88
ZA		 956 tps64 = base_khz * 1000LL;
957 scaled64 = scaled_khz * 1000LL;
50933623 958 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 959 tps64 >>= 1;
960 shift--;
961 }
962
963 tps32 = (uint32_t)tps64;
50933623
JK		 964 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
965 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 966 scaled64 >>= 1;
967 else
968 tps32 <<= 1;
50d0a0f9
GH		 969 shift++;
970 }
971
5f4e3f88
ZA		 972 *pshift = shift;
973 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 974
5f4e3f88
ZA		 975 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
976 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 977}
978
759379dd
ZA		 979static inline u64 get_kernel_ns(void)
980{
981 struct timespec ts;
982
983 WARN_ON(preemptible());
984 ktime_get_ts(&ts);
985 monotonic_to_bootbased(&ts);
986 return timespec_to_ns(&ts);
50d0a0f9
GH		 987}
988
c8076604 989static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 990unsigned long max_tsc_khz;
c8076604 991
cc578287 992static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 993{
cc578287
ZA		 994 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
995 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 996}
997
cc578287 998static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 999{
cc578287
ZA		 1000 u64 v = (u64)khz * (1000000 + ppm);
1001 do_div(v, 1000000);
1002 return v;
1e993611
JR		 1003}
1004
cc578287 1005static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1006{
cc578287
ZA		 1007 u32 thresh_lo, thresh_hi;
1008 int use_scaling = 0;
217fc9cf 1009
c285545f
ZA		 1010 /* Compute a scale to convert nanoseconds in TSC cycles */
1011 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1012 &vcpu->arch.virtual_tsc_shift,
1013 &vcpu->arch.virtual_tsc_mult);
1014 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1015
1016 /*
1017 * Compute the variation in TSC rate which is acceptable
1018 * within the range of tolerance and decide if the
1019 * rate being applied is within that bounds of the hardware
1020 * rate. If so, no scaling or compensation need be done.
1021 */
1022 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1023 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1024 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1025 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1026 use_scaling = 1;
1027 }
1028 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1029}
1030
1031static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1032{
e26101b1 1033 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1034 vcpu->arch.virtual_tsc_mult,
1035 vcpu->arch.virtual_tsc_shift);
e26101b1 1036 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1037 return tsc;
1038}
1039
99e3e30a
ZA		 1040void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1041{
1042 struct kvm *kvm = vcpu->kvm;
f38e098f 1043 u64 offset, ns, elapsed;
99e3e30a 1044 unsigned long flags;
02626b6a 1045 s64 usdiff;
99e3e30a 1046
038f8c11 1047 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1048 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1049 ns = get_kernel_ns();
f38e098f 1050 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1051
1052 /* n.b - signed multiplication and division required */
02626b6a 1053 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1054#ifdef CONFIG_X86_64
02626b6a 1055 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1056#else
1057 /* do_div() only does unsigned */
1058 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1059 : "=A"(usdiff)
1060 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1061#endif
02626b6a
MT		 1062 do_div(elapsed, 1000);
1063 usdiff -= elapsed;
1064 if (usdiff < 0)
1065 usdiff = -usdiff;
f38e098f
ZA		 1066
1067 /*
5d3cb0f6
ZA		 1068 * Special case: TSC write with a small delta (1 second) of virtual
1069 * cycle time against real time is interpreted as an attempt to
1070 * synchronize the CPU.
1071 *
1072 * For a reliable TSC, we can match TSC offsets, and for an unstable
1073 * TSC, we add elapsed time in this computation. We could let the
1074 * compensation code attempt to catch up if we fall behind, but
1075 * it's better to try to match offsets from the beginning.
1076 */
02626b6a 1077 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1078 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1079 if (!check_tsc_unstable()) {
e26101b1 1080 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1081 pr_debug("kvm: matched tsc offset for %llu\n", data);
1082 } else {
857e4099 1083 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1084 data += delta;
1085 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1086 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1087 }
e26101b1
ZA		 1088 } else {
1089 /*
1090 * We split periods of matched TSC writes into generations.
1091 * For each generation, we track the original measured
1092 * nanosecond time, offset, and write, so if TSCs are in
1093 * sync, we can match exact offset, and if not, we can match
4a969980 1094 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1095 *
1096 * These values are tracked in kvm->arch.cur_xxx variables.
1097 */
1098 kvm->arch.cur_tsc_generation++;
1099 kvm->arch.cur_tsc_nsec = ns;
1100 kvm->arch.cur_tsc_write = data;
1101 kvm->arch.cur_tsc_offset = offset;
1102 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1103 kvm->arch.cur_tsc_generation, data);
f38e098f 1104 }
e26101b1
ZA		 1105
1106 /*
1107 * We also track th most recent recorded KHZ, write and time to
1108 * allow the matching interval to be extended at each write.
1109 */
f38e098f
ZA		 1110 kvm->arch.last_tsc_nsec = ns;
1111 kvm->arch.last_tsc_write = data;
5d3cb0f6 1112 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1113
1114 /* Reset of TSC must disable overshoot protection below */
1115 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1116 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1117
1118 /* Keep track of which generation this VCPU has synchronized to */
1119 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1120 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1121 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1122
1123 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1124 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1125}
e26101b1 1126
99e3e30a
ZA		 1127EXPORT_SYMBOL_GPL(kvm_write_tsc);
1128
34c238a1 1129static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1130{
18068523
GOC		 1131 unsigned long flags;
1132 struct kvm_vcpu_arch *vcpu = &v->arch;
1133 void *shared_kaddr;
463656c0 1134 unsigned long this_tsc_khz;
1d5f066e
ZA		 1135 s64 kernel_ns, max_kernel_ns;
1136 u64 tsc_timestamp;
51d59c6b 1137 u8 pvclock_flags;
18068523 1138
18068523
GOC		 1139 /* Keep irq disabled to prevent changes to the clock */
1140 local_irq_save(flags);
d5c1785d 1141 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1142 kernel_ns = get_kernel_ns();
cc578287 1143 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1144 if (unlikely(this_tsc_khz == 0)) {
c285545f 1145 local_irq_restore(flags);
34c238a1 1146 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1147 return 1;
1148 }
18068523 1149
c285545f
ZA		 1150 /*
1151 * We may have to catch up the TSC to match elapsed wall clock
1152 * time for two reasons, even if kvmclock is used.
1153 * 1) CPU could have been running below the maximum TSC rate
1154 * 2) Broken TSC compensation resets the base at each VCPU
1155 * entry to avoid unknown leaps of TSC even when running
1156 * again on the same CPU. This may cause apparent elapsed
1157 * time to disappear, and the guest to stand still or run
1158 * very slowly.
1159 */
1160 if (vcpu->tsc_catchup) {
1161 u64 tsc = compute_guest_tsc(v, kernel_ns);
1162 if (tsc > tsc_timestamp) {
f1e2b260 1163 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1164 tsc_timestamp = tsc;
1165 }
50d0a0f9
GH		 1166 }
1167
18068523
GOC		 1168 local_irq_restore(flags);
1169
c285545f
ZA		 1170 if (!vcpu->time_page)
1171 return 0;
18068523 1172
1d5f066e
ZA		 1173 /*
1174 * Time as measured by the TSC may go backwards when resetting the base
1175 * tsc_timestamp. The reason for this is that the TSC resolution is
1176 * higher than the resolution of the other clock scales. Thus, many
1177 * possible measurments of the TSC correspond to one measurement of any
1178 * other clock, and so a spread of values is possible. This is not a
1179 * problem for the computation of the nanosecond clock; with TSC rates
1180 * around 1GHZ, there can only be a few cycles which correspond to one
1181 * nanosecond value, and any path through this code will inevitably
1182 * take longer than that. However, with the kernel_ns value itself,
1183 * the precision may be much lower, down to HZ granularity. If the
1184 * first sampling of TSC against kernel_ns ends in the low part of the
1185 * range, and the second in the high end of the range, we can get:
1186 *
1187 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1188 *
1189 * As the sampling errors potentially range in the thousands of cycles,
1190 * it is possible such a time value has already been observed by the
1191 * guest. To protect against this, we must compute the system time as
1192 * observed by the guest and ensure the new system time is greater.
1193 */
1194 max_kernel_ns = 0;
b183aa58 1195 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1196 max_kernel_ns = vcpu->last_guest_tsc -
1197 vcpu->hv_clock.tsc_timestamp;
1198 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1199 vcpu->hv_clock.tsc_to_system_mul,
1200 vcpu->hv_clock.tsc_shift);
1201 max_kernel_ns += vcpu->last_kernel_ns;
1202 }
afbcf7ab 1203
e48672fa 1204 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1205 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1206 &vcpu->hv_clock.tsc_shift,
1207 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1208 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1209 }
1210
1d5f066e
ZA		 1211 if (max_kernel_ns > kernel_ns)
1212 kernel_ns = max_kernel_ns;
1213
8cfdc000 1214 /* With all the info we got, fill in the values */
1d5f066e 1215 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1216 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1217 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1218 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b
MT		 1219
1220 pvclock_flags = 0;
1221 if (vcpu->pvclock_set_guest_stopped_request) {
1222 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1223 vcpu->pvclock_set_guest_stopped_request = false;
1224 }
1225
1226 vcpu->hv_clock.flags = pvclock_flags;
371bcf64 1227
18068523
GOC		 1228 /*
1229 * The interface expects us to write an even number signaling that the
1230 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1231 * state, we just increase by 2 at the end.
18068523 1232 */
50d0a0f9 1233 vcpu->hv_clock.version += 2;
18068523 1234
8fd75e12 1235 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523
GOC		 1236
1237 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1238 sizeof(vcpu->hv_clock));
18068523 1239
8fd75e12 1240 kunmap_atomic(shared_kaddr);
18068523
GOC		 1241
1242 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1243 return 0;
c8076604
GH		 1244}
1245
9ba075a6
AK		 1246static bool msr_mtrr_valid(unsigned msr)
1247{
1248 switch (msr) {
1249 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1250 case MSR_MTRRfix64K_00000:
1251 case MSR_MTRRfix16K_80000:
1252 case MSR_MTRRfix16K_A0000:
1253 case MSR_MTRRfix4K_C0000:
1254 case MSR_MTRRfix4K_C8000:
1255 case MSR_MTRRfix4K_D0000:
1256 case MSR_MTRRfix4K_D8000:
1257 case MSR_MTRRfix4K_E0000:
1258 case MSR_MTRRfix4K_E8000:
1259 case MSR_MTRRfix4K_F0000:
1260 case MSR_MTRRfix4K_F8000:
1261 case MSR_MTRRdefType:
1262 case MSR_IA32_CR_PAT:
1263 return true;
1264 case 0x2f8:
1265 return true;
1266 }
1267 return false;
1268}
1269
d6289b93
MT		 1270static bool valid_pat_type(unsigned t)
1271{
1272 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1273}
1274
1275static bool valid_mtrr_type(unsigned t)
1276{
1277 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1278}
1279
1280static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1281{
1282 int i;
1283
1284 if (!msr_mtrr_valid(msr))
1285 return false;
1286
1287 if (msr == MSR_IA32_CR_PAT) {
1288 for (i = 0; i < 8; i++)
1289 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1290 return false;
1291 return true;
1292 } else if (msr == MSR_MTRRdefType) {
1293 if (data & ~0xcff)
1294 return false;
1295 return valid_mtrr_type(data & 0xff);
1296 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1297 for (i = 0; i < 8 ; i++)
1298 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1299 return false;
1300 return true;
1301 }
1302
1303 /* variable MTRRs */
1304 return valid_mtrr_type(data & 0xff);
1305}
1306
9ba075a6
AK		 1307static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1308{
0bed3b56
SY		 1309 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1310
d6289b93 1311 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1312 return 1;
1313
0bed3b56
SY		 1314 if (msr == MSR_MTRRdefType) {
1315 vcpu->arch.mtrr_state.def_type = data;
1316 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1317 } else if (msr == MSR_MTRRfix64K_00000)
1318 p[0] = data;
1319 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1320 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1321 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1322 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1323 else if (msr == MSR_IA32_CR_PAT)
1324 vcpu->arch.pat = data;
1325 else { /* Variable MTRRs */
1326 int idx, is_mtrr_mask;
1327 u64 *pt;
1328
1329 idx = (msr - 0x200) / 2;
1330 is_mtrr_mask = msr - 0x200 - 2 * idx;
1331 if (!is_mtrr_mask)
1332 pt =
1333 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1334 else
1335 pt =
1336 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1337 *pt = data;
1338 }
1339
1340 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1341 return 0;
1342}
15c4a640 1343
890ca9ae 1344static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1345{
890ca9ae
HY		 1346 u64 mcg_cap = vcpu->arch.mcg_cap;
1347 unsigned bank_num = mcg_cap & 0xff;
1348
15c4a640 1349 switch (msr) {
15c4a640 1350 case MSR_IA32_MCG_STATUS:
890ca9ae 1351 vcpu->arch.mcg_status = data;
15c4a640 1352 break;
c7ac679c 1353 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1354 if (!(mcg_cap & MCG_CTL_P))
1355 return 1;
1356 if (data != 0 && data != ~(u64)0)
1357 return -1;
1358 vcpu->arch.mcg_ctl = data;
1359 break;
1360 default:
1361 if (msr >= MSR_IA32_MC0_CTL &&
1362 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1363 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1364 /* only 0 or all 1s can be written to IA32_MCi_CTL
1365 * some Linux kernels though clear bit 10 in bank 4 to
1366 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1367 * this to avoid an uncatched #GP in the guest
1368 */
890ca9ae 1369 if ((offset & 0x3) == 0 &&
114be429 1370 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1371 return -1;
1372 vcpu->arch.mce_banks[offset] = data;
1373 break;
1374 }
1375 return 1;
1376 }
1377 return 0;
1378}
1379
ffde22ac
ES		 1380static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1381{
1382 struct kvm *kvm = vcpu->kvm;
1383 int lm = is_long_mode(vcpu);
1384 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1385 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1386 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1387 : kvm->arch.xen_hvm_config.blob_size_32;
1388 u32 page_num = data & ~PAGE_MASK;
1389 u64 page_addr = data & PAGE_MASK;
1390 u8 *page;
1391 int r;
1392
1393 r = -E2BIG;
1394 if (page_num >= blob_size)
1395 goto out;
1396 r = -ENOMEM;
ff5c2c03
SL		 1397 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1398 if (IS_ERR(page)) {
1399 r = PTR_ERR(page);
ffde22ac 1400 goto out;
ff5c2c03 1401 }
ffde22ac
ES		 1402 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1403 goto out_free;
1404 r = 0;
1405out_free:
1406 kfree(page);
1407out:
1408 return r;
1409}
1410
55cd8e5a
GN		 1411static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1412{
1413 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1414}
1415
1416static bool kvm_hv_msr_partition_wide(u32 msr)
1417{
1418 bool r = false;
1419 switch (msr) {
1420 case HV_X64_MSR_GUEST_OS_ID:
1421 case HV_X64_MSR_HYPERCALL:
1422 r = true;
1423 break;
1424 }
1425
1426 return r;
1427}
1428
1429static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1430{
1431 struct kvm *kvm = vcpu->kvm;
1432
1433 switch (msr) {
1434 case HV_X64_MSR_GUEST_OS_ID:
1435 kvm->arch.hv_guest_os_id = data;
1436 /* setting guest os id to zero disables hypercall page */
1437 if (!kvm->arch.hv_guest_os_id)
1438 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1439 break;
1440 case HV_X64_MSR_HYPERCALL: {
1441 u64 gfn;
1442 unsigned long addr;
1443 u8 instructions[4];
1444
1445 /* if guest os id is not set hypercall should remain disabled */
1446 if (!kvm->arch.hv_guest_os_id)
1447 break;
1448 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1449 kvm->arch.hv_hypercall = data;
1450 break;
1451 }
1452 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1453 addr = gfn_to_hva(kvm, gfn);
1454 if (kvm_is_error_hva(addr))
1455 return 1;
1456 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1457 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1458 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1459 return 1;
1460 kvm->arch.hv_hypercall = data;
1461 break;
1462 }
1463 default:
a737f256
CD		 1464 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1465 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1466 return 1;
1467 }
1468 return 0;
1469}
1470
1471static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1472{
10388a07
GN		 1473 switch (msr) {
1474 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1475 unsigned long addr;
55cd8e5a 1476
10388a07
GN		 1477 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1478 vcpu->arch.hv_vapic = data;
1479 break;
1480 }
1481 addr = gfn_to_hva(vcpu->kvm, data >>
1482 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1483 if (kvm_is_error_hva(addr))
1484 return 1;
8b0cedff 1485 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1486 return 1;
1487 vcpu->arch.hv_vapic = data;
1488 break;
1489 }
1490 case HV_X64_MSR_EOI:
1491 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1492 case HV_X64_MSR_ICR:
1493 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1494 case HV_X64_MSR_TPR:
1495 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1496 default:
a737f256
CD		 1497 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1498 "data 0x%llx\n", msr, data);
10388a07
GN		 1499 return 1;
1500 }
1501
1502 return 0;
55cd8e5a
GN		 1503}
1504
344d9588
GN		 1505static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1506{
1507 gpa_t gpa = data & ~0x3f;
1508
4a969980 1509 /* Bits 2:5 are reserved, Should be zero */
6adba527 1510 if (data & 0x3c)
344d9588
GN		 1511 return 1;
1512
1513 vcpu->arch.apf.msr_val = data;
1514
1515 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1516 kvm_clear_async_pf_completion_queue(vcpu);
1517 kvm_async_pf_hash_reset(vcpu);
1518 return 0;
1519 }
1520
1521 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1522 return 1;
1523
6adba527 1524 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1525 kvm_async_pf_wakeup_all(vcpu);
1526 return 0;
1527}
1528
12f9a48f
GC		 1529static void kvmclock_reset(struct kvm_vcpu *vcpu)
1530{
1531 if (vcpu->arch.time_page) {
1532 kvm_release_page_dirty(vcpu->arch.time_page);
1533 vcpu->arch.time_page = NULL;
1534 }
1535}
1536
c9aaa895
GC		 1537static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1538{
1539 u64 delta;
1540
1541 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1542 return;
1543
1544 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1545 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1546 vcpu->arch.st.accum_steal = delta;
1547}
1548
1549static void record_steal_time(struct kvm_vcpu *vcpu)
1550{
1551 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1552 return;
1553
1554 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1555 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1556 return;
1557
1558 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1559 vcpu->arch.st.steal.version += 2;
1560 vcpu->arch.st.accum_steal = 0;
1561
1562 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1563 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1564}
1565
15c4a640
CO		 1566int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1567{
5753785f
GN		 1568 bool pr = false;
1569
15c4a640 1570 switch (msr) {
15c4a640 1571 case MSR_EFER:
b69e8cae 1572 return set_efer(vcpu, data);
8f1589d9
AP		 1573 case MSR_K7_HWCR:
1574 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1575 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1576 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1577 if (data != 0) {
a737f256
CD		 1578 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1579 data);
8f1589d9
AP		 1580 return 1;
1581 }
15c4a640 1582 break;
f7c6d140
AP		 1583 case MSR_FAM10H_MMIO_CONF_BASE:
1584 if (data != 0) {
a737f256
CD		 1585 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1586 "0x%llx\n", data);
f7c6d140
AP		 1587 return 1;
1588 }
15c4a640 1589 break;
c323c0e5 1590 case MSR_AMD64_NB_CFG:
c7ac679c 1591 break;
b5e2fec0
AG		 1592 case MSR_IA32_DEBUGCTLMSR:
1593 if (!data) {
1594 /* We support the non-activated case already */
1595 break;
1596 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1597 /* Values other than LBR and BTF are vendor-specific,
1598 thus reserved and should throw a #GP */
1599 return 1;
1600 }
a737f256
CD		 1601 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1602 __func__, data);
b5e2fec0 1603 break;
15c4a640
CO		 1604 case MSR_IA32_UCODE_REV:
1605 case MSR_IA32_UCODE_WRITE:
61a6bd67 1606 case MSR_VM_HSAVE_PA:
6098ca93 1607 case MSR_AMD64_PATCH_LOADER:
15c4a640 1608 break;
9ba075a6
AK		 1609 case 0x200 ... 0x2ff:
1610 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1611 case MSR_IA32_APICBASE:
1612 kvm_set_apic_base(vcpu, data);
1613 break;
0105d1a5
GN		 1614 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1615 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1616 case MSR_IA32_TSCDEADLINE:
1617 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1618 break;
15c4a640 1619 case MSR_IA32_MISC_ENABLE:
ad312c7c 1620 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1621 break;
11c6bffa 1622 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1623 case MSR_KVM_WALL_CLOCK:
1624 vcpu->kvm->arch.wall_clock = data;
1625 kvm_write_wall_clock(vcpu->kvm, data);
1626 break;
11c6bffa 1627 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1628 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1629 kvmclock_reset(vcpu);
18068523
GOC		 1630
1631 vcpu->arch.time = data;
c285545f 1632 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1633
1634 /* we verify if the enable bit is set... */
1635 if (!(data & 1))
1636 break;
1637
1638 /* ...but clean it before doing the actual write */
1639 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1640
18068523
GOC		 1641 vcpu->arch.time_page =
1642 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1643
32cad84f 1644 if (is_error_page(vcpu->arch.time_page))
18068523 1645 vcpu->arch.time_page = NULL;
32cad84f 1646
18068523
GOC		 1647 break;
1648 }
344d9588
GN		 1649 case MSR_KVM_ASYNC_PF_EN:
1650 if (kvm_pv_enable_async_pf(vcpu, data))
1651 return 1;
1652 break;
c9aaa895
GC		 1653 case MSR_KVM_STEAL_TIME:
1654
1655 if (unlikely(!sched_info_on()))
1656 return 1;
1657
1658 if (data & KVM_STEAL_RESERVED_MASK)
1659 return 1;
1660
1661 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1662 data & KVM_STEAL_VALID_BITS))
1663 return 1;
1664
1665 vcpu->arch.st.msr_val = data;
1666
1667 if (!(data & KVM_MSR_ENABLED))
1668 break;
1669
1670 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1671
1672 preempt_disable();
1673 accumulate_steal_time(vcpu);
1674 preempt_enable();
1675
1676 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1677
1678 break;
ae7a2a3f
MT		 1679 case MSR_KVM_PV_EOI_EN:
1680 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1681 return 1;
1682 break;
c9aaa895 1683
890ca9ae
HY		 1684 case MSR_IA32_MCG_CTL:
1685 case MSR_IA32_MCG_STATUS:
1686 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1687 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1688
1689 /* Performance counters are not protected by a CPUID bit,
1690 * so we should check all of them in the generic path for the sake of
1691 * cross vendor migration.
1692 * Writing a zero into the event select MSRs disables them,
1693 * which we perfectly emulate ;-). Any other value should be at least
1694 * reported, some guests depend on them.
1695 */
71db6023
AP		 1696 case MSR_K7_EVNTSEL0:
1697 case MSR_K7_EVNTSEL1:
1698 case MSR_K7_EVNTSEL2:
1699 case MSR_K7_EVNTSEL3:
1700 if (data != 0)
a737f256
CD		 1701 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1702 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1703 break;
1704 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1705 * so we ignore writes to make it happy.
1706 */
71db6023
AP		 1707 case MSR_K7_PERFCTR0:
1708 case MSR_K7_PERFCTR1:
1709 case MSR_K7_PERFCTR2:
1710 case MSR_K7_PERFCTR3:
a737f256
CD		 1711 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1712 "0x%x data 0x%llx\n", msr, data);
71db6023 1713 break;
5753785f
GN		 1714 case MSR_P6_PERFCTR0:
1715 case MSR_P6_PERFCTR1:
1716 pr = true;
1717 case MSR_P6_EVNTSEL0:
1718 case MSR_P6_EVNTSEL1:
1719 if (kvm_pmu_msr(vcpu, msr))
1720 return kvm_pmu_set_msr(vcpu, msr, data);
1721
1722 if (pr || data != 0)
a737f256
CD		 1723 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1724 "0x%x data 0x%llx\n", msr, data);
5753785f 1725 break;
84e0cefa
JS		 1726 case MSR_K7_CLK_CTL:
1727 /*
1728 * Ignore all writes to this no longer documented MSR.
1729 * Writes are only relevant for old K7 processors,
1730 * all pre-dating SVM, but a recommended workaround from
4a969980 1731 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 1732 * affected processor models on the command line, hence
1733 * the need to ignore the workaround.
1734 */
1735 break;
55cd8e5a
GN		 1736 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1737 if (kvm_hv_msr_partition_wide(msr)) {
1738 int r;
1739 mutex_lock(&vcpu->kvm->lock);
1740 r = set_msr_hyperv_pw(vcpu, msr, data);
1741 mutex_unlock(&vcpu->kvm->lock);
1742 return r;
1743 } else
1744 return set_msr_hyperv(vcpu, msr, data);
1745 break;
91c9c3ed 1746 case MSR_IA32_BBL_CR_CTL3:
1747 /* Drop writes to this legacy MSR -- see rdmsr
1748 * counterpart for further detail.
1749 */
a737f256 1750 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1751 break;
2b036c6b
BO		 1752 case MSR_AMD64_OSVW_ID_LENGTH:
1753 if (!guest_cpuid_has_osvw(vcpu))
1754 return 1;
1755 vcpu->arch.osvw.length = data;
1756 break;
1757 case MSR_AMD64_OSVW_STATUS:
1758 if (!guest_cpuid_has_osvw(vcpu))
1759 return 1;
1760 vcpu->arch.osvw.status = data;
1761 break;
15c4a640 1762 default:
ffde22ac
ES		 1763 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1764 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1765 if (kvm_pmu_msr(vcpu, msr))
1766 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1767 if (!ignore_msrs) {
a737f256
CD		 1768 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1769 msr, data);
ed85c068
AP		 1770 return 1;
1771 } else {
a737f256
CD		 1772 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1773 msr, data);
ed85c068
AP		 1774 break;
1775 }
15c4a640
CO		 1776 }
1777 return 0;
1778}
1779EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1780
1781
1782/*
1783 * Reads an msr value (of 'msr_index') into 'pdata'.
1784 * Returns 0 on success, non-0 otherwise.
1785 * Assumes vcpu_load() was already called.
1786 */
1787int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1788{
1789 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1790}
1791
9ba075a6
AK		 1792static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1793{
0bed3b56
SY		 1794 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1795
9ba075a6
AK		 1796 if (!msr_mtrr_valid(msr))
1797 return 1;
1798
0bed3b56
SY		 1799 if (msr == MSR_MTRRdefType)
1800 *pdata = vcpu->arch.mtrr_state.def_type +
1801 (vcpu->arch.mtrr_state.enabled << 10);
1802 else if (msr == MSR_MTRRfix64K_00000)
1803 *pdata = p[0];
1804 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1805 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1806 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1807 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1808 else if (msr == MSR_IA32_CR_PAT)
1809 *pdata = vcpu->arch.pat;
1810 else { /* Variable MTRRs */
1811 int idx, is_mtrr_mask;
1812 u64 *pt;
1813
1814 idx = (msr - 0x200) / 2;
1815 is_mtrr_mask = msr - 0x200 - 2 * idx;
1816 if (!is_mtrr_mask)
1817 pt =
1818 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1819 else
1820 pt =
1821 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1822 *pdata = *pt;
1823 }
1824
9ba075a6
AK		 1825 return 0;
1826}
1827
890ca9ae 1828static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1829{
1830 u64 data;
890ca9ae
HY		 1831 u64 mcg_cap = vcpu->arch.mcg_cap;
1832 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1833
1834 switch (msr) {
15c4a640
CO		 1835 case MSR_IA32_P5_MC_ADDR:
1836 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1837 data = 0;
1838 break;
15c4a640 1839 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1840 data = vcpu->arch.mcg_cap;
1841 break;
c7ac679c 1842 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1843 if (!(mcg_cap & MCG_CTL_P))
1844 return 1;
1845 data = vcpu->arch.mcg_ctl;
1846 break;
1847 case MSR_IA32_MCG_STATUS:
1848 data = vcpu->arch.mcg_status;
1849 break;
1850 default:
1851 if (msr >= MSR_IA32_MC0_CTL &&
1852 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1853 u32 offset = msr - MSR_IA32_MC0_CTL;
1854 data = vcpu->arch.mce_banks[offset];
1855 break;
1856 }
1857 return 1;
1858 }
1859 *pdata = data;
1860 return 0;
1861}
1862
55cd8e5a
GN		 1863static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1864{
1865 u64 data = 0;
1866 struct kvm *kvm = vcpu->kvm;
1867
1868 switch (msr) {
1869 case HV_X64_MSR_GUEST_OS_ID:
1870 data = kvm->arch.hv_guest_os_id;
1871 break;
1872 case HV_X64_MSR_HYPERCALL:
1873 data = kvm->arch.hv_hypercall;
1874 break;
1875 default:
a737f256 1876 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1877 return 1;
1878 }
1879
1880 *pdata = data;
1881 return 0;
1882}
1883
1884static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1885{
1886 u64 data = 0;
1887
1888 switch (msr) {
1889 case HV_X64_MSR_VP_INDEX: {
1890 int r;
1891 struct kvm_vcpu *v;
1892 kvm_for_each_vcpu(r, v, vcpu->kvm)
1893 if (v == vcpu)
1894 data = r;
1895 break;
1896 }
10388a07
GN		 1897 case HV_X64_MSR_EOI:
1898 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1899 case HV_X64_MSR_ICR:
1900 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1901 case HV_X64_MSR_TPR:
1902 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1903 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1904 data = vcpu->arch.hv_vapic;
1905 break;
55cd8e5a 1906 default:
a737f256 1907 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1908 return 1;
1909 }
1910 *pdata = data;
1911 return 0;
1912}
1913
890ca9ae
HY		 1914int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1915{
1916 u64 data;
1917
1918 switch (msr) {
890ca9ae 1919 case MSR_IA32_PLATFORM_ID:
15c4a640 1920 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1921 case MSR_IA32_DEBUGCTLMSR:
1922 case MSR_IA32_LASTBRANCHFROMIP:
1923 case MSR_IA32_LASTBRANCHTOIP:
1924 case MSR_IA32_LASTINTFROMIP:
1925 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1926 case MSR_K8_SYSCFG:
1927 case MSR_K7_HWCR:
61a6bd67 1928 case MSR_VM_HSAVE_PA:
9e699624 1929 case MSR_K7_EVNTSEL0:
1f3ee616 1930 case MSR_K7_PERFCTR0:
1fdbd48c 1931 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1932 case MSR_AMD64_NB_CFG:
f7c6d140 1933 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1934 data = 0;
1935 break;
5753785f
GN		 1936 case MSR_P6_PERFCTR0:
1937 case MSR_P6_PERFCTR1:
1938 case MSR_P6_EVNTSEL0:
1939 case MSR_P6_EVNTSEL1:
1940 if (kvm_pmu_msr(vcpu, msr))
1941 return kvm_pmu_get_msr(vcpu, msr, pdata);
1942 data = 0;
1943 break;
742bc670
MT		 1944 case MSR_IA32_UCODE_REV:
1945 data = 0x100000000ULL;
1946 break;
9ba075a6
AK		 1947 case MSR_MTRRcap:
1948 data = 0x500 | KVM_NR_VAR_MTRR;
1949 break;
1950 case 0x200 ... 0x2ff:
1951 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1952 case 0xcd: /* fsb frequency */
1953 data = 3;
1954 break;
7b914098
JS		 1955 /*
1956 * MSR_EBC_FREQUENCY_ID
1957 * Conservative value valid for even the basic CPU models.
1958 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1959 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1960 * and 266MHz for model 3, or 4. Set Core Clock
1961 * Frequency to System Bus Frequency Ratio to 1 (bits
1962 * 31:24) even though these are only valid for CPU
1963 * models > 2, however guests may end up dividing or
1964 * multiplying by zero otherwise.
1965 */
1966 case MSR_EBC_FREQUENCY_ID:
1967 data = 1 << 24;
1968 break;
15c4a640
CO		 1969 case MSR_IA32_APICBASE:
1970 data = kvm_get_apic_base(vcpu);
1971 break;
0105d1a5
GN		 1972 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1973 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1974 break;
a3e06bbe
LJ		 1975 case MSR_IA32_TSCDEADLINE:
1976 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1977 break;
15c4a640 1978 case MSR_IA32_MISC_ENABLE:
ad312c7c 1979 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1980 break;
847f0ad8
AG		 1981 case MSR_IA32_PERF_STATUS:
1982 /* TSC increment by tick */
1983 data = 1000ULL;
1984 /* CPU multiplier */
1985 data |= (((uint64_t)4ULL) << 40);
1986 break;
15c4a640 1987 case MSR_EFER:
f6801dff 1988 data = vcpu->arch.efer;
15c4a640 1989 break;
18068523 1990 case MSR_KVM_WALL_CLOCK:
11c6bffa 1991 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1992 data = vcpu->kvm->arch.wall_clock;
1993 break;
1994 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1995 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1996 data = vcpu->arch.time;
1997 break;
344d9588
GN		 1998 case MSR_KVM_ASYNC_PF_EN:
1999 data = vcpu->arch.apf.msr_val;
2000 break;
c9aaa895
GC		 2001 case MSR_KVM_STEAL_TIME:
2002 data = vcpu->arch.st.msr_val;
2003 break;
890ca9ae
HY		 2004 case MSR_IA32_P5_MC_ADDR:
2005 case MSR_IA32_P5_MC_TYPE:
2006 case MSR_IA32_MCG_CAP:
2007 case MSR_IA32_MCG_CTL:
2008 case MSR_IA32_MCG_STATUS:
2009 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2010 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2011 case MSR_K7_CLK_CTL:
2012 /*
2013 * Provide expected ramp-up count for K7. All other
2014 * are set to zero, indicating minimum divisors for
2015 * every field.
2016 *
2017 * This prevents guest kernels on AMD host with CPU
2018 * type 6, model 8 and higher from exploding due to
2019 * the rdmsr failing.
2020 */
2021 data = 0x20000000;
2022 break;
55cd8e5a
GN		 2023 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2024 if (kvm_hv_msr_partition_wide(msr)) {
2025 int r;
2026 mutex_lock(&vcpu->kvm->lock);
2027 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2028 mutex_unlock(&vcpu->kvm->lock);
2029 return r;
2030 } else
2031 return get_msr_hyperv(vcpu, msr, pdata);
2032 break;
91c9c3ed 2033 case MSR_IA32_BBL_CR_CTL3:
2034 /* This legacy MSR exists but isn't fully documented in current
2035 * silicon. It is however accessed by winxp in very narrow
2036 * scenarios where it sets bit #19, itself documented as
2037 * a "reserved" bit. Best effort attempt to source coherent
2038 * read data here should the balance of the register be
2039 * interpreted by the guest:
2040 *
2041 * L2 cache control register 3: 64GB range, 256KB size,
2042 * enabled, latency 0x1, configured
2043 */
2044 data = 0xbe702111;
2045 break;
2b036c6b
BO		 2046 case MSR_AMD64_OSVW_ID_LENGTH:
2047 if (!guest_cpuid_has_osvw(vcpu))
2048 return 1;
2049 data = vcpu->arch.osvw.length;
2050 break;
2051 case MSR_AMD64_OSVW_STATUS:
2052 if (!guest_cpuid_has_osvw(vcpu))
2053 return 1;
2054 data = vcpu->arch.osvw.status;
2055 break;
15c4a640 2056 default:
f5132b01
GN		 2057 if (kvm_pmu_msr(vcpu, msr))
2058 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2059 if (!ignore_msrs) {
a737f256 2060 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2061 return 1;
2062 } else {
a737f256 2063 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2064 data = 0;
2065 }
2066 break;
15c4a640
CO		 2067 }
2068 *pdata = data;
2069 return 0;
2070}
2071EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2072
313a3dc7
CO		 2073/*
2074 * Read or write a bunch of msrs. All parameters are kernel addresses.
2075 *
2076 * @return number of msrs set successfully.
2077 */
2078static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2079 struct kvm_msr_entry *entries,
2080 int (*do_msr)(struct kvm_vcpu *vcpu,
2081 unsigned index, u64 *data))
2082{
f656ce01 2083 int i, idx;
313a3dc7 2084
f656ce01 2085 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2086 for (i = 0; i < msrs->nmsrs; ++i)
2087 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2088 break;
f656ce01 2089 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2090
313a3dc7
CO		 2091 return i;
2092}
2093
2094/*
2095 * Read or write a bunch of msrs. Parameters are user addresses.
2096 *
2097 * @return number of msrs set successfully.
2098 */
2099static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2100 int (*do_msr)(struct kvm_vcpu *vcpu,
2101 unsigned index, u64 *data),
2102 int writeback)
2103{
2104 struct kvm_msrs msrs;
2105 struct kvm_msr_entry *entries;
2106 int r, n;
2107 unsigned size;
2108
2109 r = -EFAULT;
2110 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2111 goto out;
2112
2113 r = -E2BIG;
2114 if (msrs.nmsrs >= MAX_IO_MSRS)
2115 goto out;
2116
313a3dc7 2117 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2118 entries = memdup_user(user_msrs->entries, size);
2119 if (IS_ERR(entries)) {
2120 r = PTR_ERR(entries);
313a3dc7 2121 goto out;
ff5c2c03 2122 }
313a3dc7
CO		 2123
2124 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2125 if (r < 0)
2126 goto out_free;
2127
2128 r = -EFAULT;
2129 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2130 goto out_free;
2131
2132 r = n;
2133
2134out_free:
7a73c028 2135 kfree(entries);
313a3dc7
CO		 2136out:
2137 return r;
2138}
2139
018d00d2
ZX		 2140int kvm_dev_ioctl_check_extension(long ext)
2141{
2142 int r;
2143
2144 switch (ext) {
2145 case KVM_CAP_IRQCHIP:
2146 case KVM_CAP_HLT:
2147 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2148 case KVM_CAP_SET_TSS_ADDR:
07716717 2149 case KVM_CAP_EXT_CPUID:
c8076604 2150 case KVM_CAP_CLOCKSOURCE:
7837699f 2151 case KVM_CAP_PIT:
a28e4f5a 2152 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2153 case KVM_CAP_MP_STATE:
ed848624 2154 case KVM_CAP_SYNC_MMU:
a355c85c 2155 case KVM_CAP_USER_NMI:
52d939a0 2156 case KVM_CAP_REINJECT_CONTROL:
4925663a 2157 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2158 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2159 case KVM_CAP_IRQFD:
d34e6b17 2160 case KVM_CAP_IOEVENTFD:
c5ff41ce 2161 case KVM_CAP_PIT2:
e9f42757 2162 case KVM_CAP_PIT_STATE2:
b927a3ce 2163 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2164 case KVM_CAP_XEN_HVM:
afbcf7ab 2165 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2166 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2167 case KVM_CAP_HYPERV:
10388a07 2168 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2169 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2170 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2171 case KVM_CAP_DEBUGREGS:
d2be1651 2172 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2173 case KVM_CAP_XSAVE:
344d9588 2174 case KVM_CAP_ASYNC_PF:
92a1f12d 2175 case KVM_CAP_GET_TSC_KHZ:
07700a94 2176 case KVM_CAP_PCI_2_3:
1c0b28c2 2177 case KVM_CAP_KVMCLOCK_CTRL:
018d00d2
ZX		 2178 r = 1;
2179 break;
542472b5
LV		 2180 case KVM_CAP_COALESCED_MMIO:
2181 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2182 break;
774ead3a
AK		 2183 case KVM_CAP_VAPIC:
2184 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2185 break;
f725230a 2186 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2187 r = KVM_SOFT_MAX_VCPUS;
2188 break;
2189 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2190 r = KVM_MAX_VCPUS;
2191 break;
a988b910
AK		 2192 case KVM_CAP_NR_MEMSLOTS:
2193 r = KVM_MEMORY_SLOTS;
2194 break;
a68a6a72
MT		 2195 case KVM_CAP_PV_MMU: /* obsolete */
2196 r = 0;
2f333bcb 2197 break;
62c476c7 2198 case KVM_CAP_IOMMU:
a1b60c1c 2199 r = iommu_present(&pci_bus_type);
62c476c7 2200 break;
890ca9ae
HY		 2201 case KVM_CAP_MCE:
2202 r = KVM_MAX_MCE_BANKS;
2203 break;
2d5b5a66
SY		 2204 case KVM_CAP_XCRS:
2205 r = cpu_has_xsave;
2206 break;
92a1f12d
JR		 2207 case KVM_CAP_TSC_CONTROL:
2208 r = kvm_has_tsc_control;
2209 break;
4d25a066
JK		 2210 case KVM_CAP_TSC_DEADLINE_TIMER:
2211 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2212 break;
018d00d2
ZX		 2213 default:
2214 r = 0;
2215 break;
2216 }
2217 return r;
2218
2219}
2220
043405e1
CO		 2221long kvm_arch_dev_ioctl(struct file *filp,
2222 unsigned int ioctl, unsigned long arg)
2223{
2224 void __user *argp = (void __user *)arg;
2225 long r;
2226
2227 switch (ioctl) {
2228 case KVM_GET_MSR_INDEX_LIST: {
2229 struct kvm_msr_list __user *user_msr_list = argp;
2230 struct kvm_msr_list msr_list;
2231 unsigned n;
2232
2233 r = -EFAULT;
2234 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2235 goto out;
2236 n = msr_list.nmsrs;
2237 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2238 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2239 goto out;
2240 r = -E2BIG;
e125e7b6 2241 if (n < msr_list.nmsrs)
043405e1
CO		 2242 goto out;
2243 r = -EFAULT;
2244 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2245 num_msrs_to_save * sizeof(u32)))
2246 goto out;
e125e7b6 2247 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2248 &emulated_msrs,
2249 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2250 goto out;
2251 r = 0;
2252 break;
2253 }
674eea0f
AK		 2254 case KVM_GET_SUPPORTED_CPUID: {
2255 struct kvm_cpuid2 __user *cpuid_arg = argp;
2256 struct kvm_cpuid2 cpuid;
2257
2258 r = -EFAULT;
2259 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2260 goto out;
2261 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2262 cpuid_arg->entries);
674eea0f
AK		 2263 if (r)
2264 goto out;
2265
2266 r = -EFAULT;
2267 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2268 goto out;
2269 r = 0;
2270 break;
2271 }
890ca9ae
HY		 2272 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2273 u64 mce_cap;
2274
2275 mce_cap = KVM_MCE_CAP_SUPPORTED;
2276 r = -EFAULT;
2277 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2278 goto out;
2279 r = 0;
2280 break;
2281 }
043405e1
CO		 2282 default:
2283 r = -EINVAL;
2284 }
2285out:
2286 return r;
2287}
2288
f5f48ee1
SY		 2289static void wbinvd_ipi(void *garbage)
2290{
2291 wbinvd();
2292}
2293
2294static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2295{
2296 return vcpu->kvm->arch.iommu_domain &&
2297 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2298}
2299
313a3dc7
CO		 2300void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2301{
f5f48ee1
SY		 2302 /* Address WBINVD may be executed by guest */
2303 if (need_emulate_wbinvd(vcpu)) {
2304 if (kvm_x86_ops->has_wbinvd_exit())
2305 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2306 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2307 smp_call_function_single(vcpu->cpu,
2308 wbinvd_ipi, NULL, 1);
2309 }
2310
313a3dc7 2311 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2312
0dd6a6ed
ZA		 2313 /* Apply any externally detected TSC adjustments (due to suspend) */
2314 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2315 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2316 vcpu->arch.tsc_offset_adjustment = 0;
2317 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2318 }
8f6055cb 2319
48434c20 2320 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2321 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2322 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2323 if (tsc_delta < 0)
2324 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2325 if (check_tsc_unstable()) {
b183aa58
ZA		 2326 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2327 vcpu->arch.last_guest_tsc);
2328 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2329 vcpu->arch.tsc_catchup = 1;
c285545f 2330 }
1aa8ceef 2331 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2332 if (vcpu->cpu != cpu)
2333 kvm_migrate_timers(vcpu);
e48672fa 2334 vcpu->cpu = cpu;
6b7d7e76 2335 }
c9aaa895
GC		 2336
2337 accumulate_steal_time(vcpu);
2338 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2339}
2340
2341void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2342{
02daab21 2343 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2344 kvm_put_guest_fpu(vcpu);
6f526ec5 2345 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2346}
2347
313a3dc7
CO		 2348static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2349 struct kvm_lapic_state *s)
2350{
ad312c7c 2351 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2352
2353 return 0;
2354}
2355
2356static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2357 struct kvm_lapic_state *s)
2358{
64eb0620 2359 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2360 update_cr8_intercept(vcpu);
313a3dc7
CO		 2361
2362 return 0;
2363}
2364
f77bc6a4
ZX		 2365static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2366 struct kvm_interrupt *irq)
2367{
2368 if (irq->irq < 0 || irq->irq >= 256)
2369 return -EINVAL;
2370 if (irqchip_in_kernel(vcpu->kvm))
2371 return -ENXIO;
f77bc6a4 2372
66fd3f7f 2373 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2374 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2375
f77bc6a4
ZX		 2376 return 0;
2377}
2378
c4abb7c9
JK		 2379static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2380{
c4abb7c9 2381 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2382
2383 return 0;
2384}
2385
b209749f
AK		 2386static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2387 struct kvm_tpr_access_ctl *tac)
2388{
2389 if (tac->flags)
2390 return -EINVAL;
2391 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2392 return 0;
2393}
2394
890ca9ae
HY		 2395static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2396 u64 mcg_cap)
2397{
2398 int r;
2399 unsigned bank_num = mcg_cap & 0xff, bank;
2400
2401 r = -EINVAL;
a9e38c3e 2402 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2403 goto out;
2404 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2405 goto out;
2406 r = 0;
2407 vcpu->arch.mcg_cap = mcg_cap;
2408 /* Init IA32_MCG_CTL to all 1s */
2409 if (mcg_cap & MCG_CTL_P)
2410 vcpu->arch.mcg_ctl = ~(u64)0;
2411 /* Init IA32_MCi_CTL to all 1s */
2412 for (bank = 0; bank < bank_num; bank++)
2413 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2414out:
2415 return r;
2416}
2417
2418static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2419 struct kvm_x86_mce *mce)
2420{
2421 u64 mcg_cap = vcpu->arch.mcg_cap;
2422 unsigned bank_num = mcg_cap & 0xff;
2423 u64 *banks = vcpu->arch.mce_banks;
2424
2425 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2426 return -EINVAL;
2427 /*
2428 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2429 * reporting is disabled
2430 */
2431 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2432 vcpu->arch.mcg_ctl != ~(u64)0)
2433 return 0;
2434 banks += 4 * mce->bank;
2435 /*
2436 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2437 * reporting is disabled for the bank
2438 */
2439 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2440 return 0;
2441 if (mce->status & MCI_STATUS_UC) {
2442 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2443 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2444 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2445 return 0;
2446 }
2447 if (banks[1] & MCI_STATUS_VAL)
2448 mce->status |= MCI_STATUS_OVER;
2449 banks[2] = mce->addr;
2450 banks[3] = mce->misc;
2451 vcpu->arch.mcg_status = mce->mcg_status;
2452 banks[1] = mce->status;
2453 kvm_queue_exception(vcpu, MC_VECTOR);
2454 } else if (!(banks[1] & MCI_STATUS_VAL)
2455 || !(banks[1] & MCI_STATUS_UC)) {
2456 if (banks[1] & MCI_STATUS_VAL)
2457 mce->status |= MCI_STATUS_OVER;
2458 banks[2] = mce->addr;
2459 banks[3] = mce->misc;
2460 banks[1] = mce->status;
2461 } else
2462 banks[1] |= MCI_STATUS_OVER;
2463 return 0;
2464}
2465
3cfc3092
JK		 2466static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2467 struct kvm_vcpu_events *events)
2468{
7460fb4a 2469 process_nmi(vcpu);
03b82a30
JK		 2470 events->exception.injected =
2471 vcpu->arch.exception.pending &&
2472 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2473 events->exception.nr = vcpu->arch.exception.nr;
2474 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2475 events->exception.pad = 0;
3cfc3092
JK		 2476 events->exception.error_code = vcpu->arch.exception.error_code;
2477
03b82a30
JK		 2478 events->interrupt.injected =
2479 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2480 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2481 events->interrupt.soft = 0;
48005f64
JK		 2482 events->interrupt.shadow =
2483 kvm_x86_ops->get_interrupt_shadow(vcpu,
2484 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2485
2486 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2487 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2488 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2489 events->nmi.pad = 0;
3cfc3092
JK		 2490
2491 events->sipi_vector = vcpu->arch.sipi_vector;
2492
dab4b911 2493 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2494 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2495 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2496 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2497}
2498
2499static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2500 struct kvm_vcpu_events *events)
2501{
dab4b911 2502 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2503 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2504 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2505 return -EINVAL;
2506
7460fb4a 2507 process_nmi(vcpu);
3cfc3092
JK		 2508 vcpu->arch.exception.pending = events->exception.injected;
2509 vcpu->arch.exception.nr = events->exception.nr;
2510 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2511 vcpu->arch.exception.error_code = events->exception.error_code;
2512
2513 vcpu->arch.interrupt.pending = events->interrupt.injected;
2514 vcpu->arch.interrupt.nr = events->interrupt.nr;
2515 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2516 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2517 kvm_x86_ops->set_interrupt_shadow(vcpu,
2518 events->interrupt.shadow);
3cfc3092
JK		 2519
2520 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2521 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2522 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2523 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2524
dab4b911
JK		 2525 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2526 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2527
3842d135
AK		 2528 kvm_make_request(KVM_REQ_EVENT, vcpu);
2529
3cfc3092
JK		 2530 return 0;
2531}
2532
a1efbe77
JK		 2533static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2534 struct kvm_debugregs *dbgregs)
2535{
a1efbe77
JK		 2536 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2537 dbgregs->dr6 = vcpu->arch.dr6;
2538 dbgregs->dr7 = vcpu->arch.dr7;
2539 dbgregs->flags = 0;
97e69aa6 2540 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2541}
2542
2543static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2544 struct kvm_debugregs *dbgregs)
2545{
2546 if (dbgregs->flags)
2547 return -EINVAL;
2548
a1efbe77
JK		 2549 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2550 vcpu->arch.dr6 = dbgregs->dr6;
2551 vcpu->arch.dr7 = dbgregs->dr7;
2552
a1efbe77
JK		 2553 return 0;
2554}
2555
2d5b5a66
SY		 2556static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2557 struct kvm_xsave *guest_xsave)
2558{
2559 if (cpu_has_xsave)
2560 memcpy(guest_xsave->region,
2561 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2562 xstate_size);
2d5b5a66
SY		 2563 else {
2564 memcpy(guest_xsave->region,
2565 &vcpu->arch.guest_fpu.state->fxsave,
2566 sizeof(struct i387_fxsave_struct));
2567 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2568 XSTATE_FPSSE;
2569 }
2570}
2571
2572static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2573 struct kvm_xsave *guest_xsave)
2574{
2575 u64 xstate_bv =
2576 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2577
2578 if (cpu_has_xsave)
2579 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2580 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2581 else {
2582 if (xstate_bv & ~XSTATE_FPSSE)
2583 return -EINVAL;
2584 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2585 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2586 }
2587 return 0;
2588}
2589
2590static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2591 struct kvm_xcrs *guest_xcrs)
2592{
2593 if (!cpu_has_xsave) {
2594 guest_xcrs->nr_xcrs = 0;
2595 return;
2596 }
2597
2598 guest_xcrs->nr_xcrs = 1;
2599 guest_xcrs->flags = 0;
2600 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2601 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2602}
2603
2604static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2605 struct kvm_xcrs *guest_xcrs)
2606{
2607 int i, r = 0;
2608
2609 if (!cpu_has_xsave)
2610 return -EINVAL;
2611
2612 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2613 return -EINVAL;
2614
2615 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2616 /* Only support XCR0 currently */
2617 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2618 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2619 guest_xcrs->xcrs[0].value);
2620 break;
2621 }
2622 if (r)
2623 r = -EINVAL;
2624 return r;
2625}
2626
1c0b28c2
EM		 2627/*
2628 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2629 * stopped by the hypervisor. This function will be called from the host only.
2630 * EINVAL is returned when the host attempts to set the flag for a guest that
2631 * does not support pv clocks.
2632 */
2633static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2634{
1c0b28c2
EM		 2635 if (!vcpu->arch.time_page)
2636 return -EINVAL;
51d59c6b 2637 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2638 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2639 return 0;
2640}
2641
313a3dc7
CO		 2642long kvm_arch_vcpu_ioctl(struct file *filp,
2643 unsigned int ioctl, unsigned long arg)
2644{
2645 struct kvm_vcpu *vcpu = filp->private_data;
2646 void __user *argp = (void __user *)arg;
2647 int r;
d1ac91d8
AK		 2648 union {
2649 struct kvm_lapic_state *lapic;
2650 struct kvm_xsave *xsave;
2651 struct kvm_xcrs *xcrs;
2652 void *buffer;
2653 } u;
2654
2655 u.buffer = NULL;
313a3dc7
CO		 2656 switch (ioctl) {
2657 case KVM_GET_LAPIC: {
2204ae3c
MT		 2658 r = -EINVAL;
2659 if (!vcpu->arch.apic)
2660 goto out;
d1ac91d8 2661 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2662
b772ff36 2663 r = -ENOMEM;
d1ac91d8 2664 if (!u.lapic)
b772ff36 2665 goto out;
d1ac91d8 2666 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2667 if (r)
2668 goto out;
2669 r = -EFAULT;
d1ac91d8 2670 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2671 goto out;
2672 r = 0;
2673 break;
2674 }
2675 case KVM_SET_LAPIC: {
2204ae3c
MT		 2676 r = -EINVAL;
2677 if (!vcpu->arch.apic)
2678 goto out;
ff5c2c03
SL		 2679 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2680 if (IS_ERR(u.lapic)) {
2681 r = PTR_ERR(u.lapic);
313a3dc7 2682 goto out;
ff5c2c03
SL		 2683 }
2684
d1ac91d8 2685 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2686 if (r)
2687 goto out;
2688 r = 0;
2689 break;
2690 }
f77bc6a4
ZX		 2691 case KVM_INTERRUPT: {
2692 struct kvm_interrupt irq;
2693
2694 r = -EFAULT;
2695 if (copy_from_user(&irq, argp, sizeof irq))
2696 goto out;
2697 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2698 if (r)
2699 goto out;
2700 r = 0;
2701 break;
2702 }
c4abb7c9
JK		 2703 case KVM_NMI: {
2704 r = kvm_vcpu_ioctl_nmi(vcpu);
2705 if (r)
2706 goto out;
2707 r = 0;
2708 break;
2709 }
313a3dc7
CO		 2710 case KVM_SET_CPUID: {
2711 struct kvm_cpuid __user *cpuid_arg = argp;
2712 struct kvm_cpuid cpuid;
2713
2714 r = -EFAULT;
2715 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2716 goto out;
2717 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2718 if (r)
2719 goto out;
2720 break;
2721 }
07716717
DK		 2722 case KVM_SET_CPUID2: {
2723 struct kvm_cpuid2 __user *cpuid_arg = argp;
2724 struct kvm_cpuid2 cpuid;
2725
2726 r = -EFAULT;
2727 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2728 goto out;
2729 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2730 cpuid_arg->entries);
07716717
DK		 2731 if (r)
2732 goto out;
2733 break;
2734 }
2735 case KVM_GET_CPUID2: {
2736 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737 struct kvm_cpuid2 cpuid;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2741 goto out;
2742 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2743 cpuid_arg->entries);
07716717
DK		 2744 if (r)
2745 goto out;
2746 r = -EFAULT;
2747 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2748 goto out;
2749 r = 0;
2750 break;
2751 }
313a3dc7
CO		 2752 case KVM_GET_MSRS:
2753 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2754 break;
2755 case KVM_SET_MSRS:
2756 r = msr_io(vcpu, argp, do_set_msr, 0);
2757 break;
b209749f
AK		 2758 case KVM_TPR_ACCESS_REPORTING: {
2759 struct kvm_tpr_access_ctl tac;
2760
2761 r = -EFAULT;
2762 if (copy_from_user(&tac, argp, sizeof tac))
2763 goto out;
2764 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2765 if (r)
2766 goto out;
2767 r = -EFAULT;
2768 if (copy_to_user(argp, &tac, sizeof tac))
2769 goto out;
2770 r = 0;
2771 break;
2772 };
b93463aa
AK		 2773 case KVM_SET_VAPIC_ADDR: {
2774 struct kvm_vapic_addr va;
2775
2776 r = -EINVAL;
2777 if (!irqchip_in_kernel(vcpu->kvm))
2778 goto out;
2779 r = -EFAULT;
2780 if (copy_from_user(&va, argp, sizeof va))
2781 goto out;
2782 r = 0;
2783 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2784 break;
2785 }
890ca9ae
HY		 2786 case KVM_X86_SETUP_MCE: {
2787 u64 mcg_cap;
2788
2789 r = -EFAULT;
2790 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2791 goto out;
2792 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2793 break;
2794 }
2795 case KVM_X86_SET_MCE: {
2796 struct kvm_x86_mce mce;
2797
2798 r = -EFAULT;
2799 if (copy_from_user(&mce, argp, sizeof mce))
2800 goto out;
2801 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2802 break;
2803 }
3cfc3092
JK		 2804 case KVM_GET_VCPU_EVENTS: {
2805 struct kvm_vcpu_events events;
2806
2807 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2808
2809 r = -EFAULT;
2810 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2811 break;
2812 r = 0;
2813 break;
2814 }
2815 case KVM_SET_VCPU_EVENTS: {
2816 struct kvm_vcpu_events events;
2817
2818 r = -EFAULT;
2819 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2820 break;
2821
2822 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2823 break;
2824 }
a1efbe77
JK		 2825 case KVM_GET_DEBUGREGS: {
2826 struct kvm_debugregs dbgregs;
2827
2828 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2829
2830 r = -EFAULT;
2831 if (copy_to_user(argp, &dbgregs,
2832 sizeof(struct kvm_debugregs)))
2833 break;
2834 r = 0;
2835 break;
2836 }
2837 case KVM_SET_DEBUGREGS: {
2838 struct kvm_debugregs dbgregs;
2839
2840 r = -EFAULT;
2841 if (copy_from_user(&dbgregs, argp,
2842 sizeof(struct kvm_debugregs)))
2843 break;
2844
2845 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2846 break;
2847 }
2d5b5a66 2848 case KVM_GET_XSAVE: {
d1ac91d8 2849 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2850 r = -ENOMEM;
d1ac91d8 2851 if (!u.xsave)
2d5b5a66
SY		 2852 break;
2853
d1ac91d8 2854 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2855
2856 r = -EFAULT;
d1ac91d8 2857 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2858 break;
2859 r = 0;
2860 break;
2861 }
2862 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2863 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2864 if (IS_ERR(u.xsave)) {
2865 r = PTR_ERR(u.xsave);
2866 goto out;
2867 }
2d5b5a66 2868
d1ac91d8 2869 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2870 break;
2871 }
2872 case KVM_GET_XCRS: {
d1ac91d8 2873 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2874 r = -ENOMEM;
d1ac91d8 2875 if (!u.xcrs)
2d5b5a66
SY		 2876 break;
2877
d1ac91d8 2878 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2879
2880 r = -EFAULT;
d1ac91d8 2881 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2882 sizeof(struct kvm_xcrs)))
2883 break;
2884 r = 0;
2885 break;
2886 }
2887 case KVM_SET_XCRS: {
ff5c2c03
SL		 2888 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2889 if (IS_ERR(u.xcrs)) {
2890 r = PTR_ERR(u.xcrs);
2891 goto out;
2892 }
2d5b5a66 2893
d1ac91d8 2894 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2895 break;
2896 }
92a1f12d
JR		 2897 case KVM_SET_TSC_KHZ: {
2898 u32 user_tsc_khz;
2899
2900 r = -EINVAL;
92a1f12d
JR		 2901 user_tsc_khz = (u32)arg;
2902
2903 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2904 goto out;
2905
cc578287
ZA		 2906 if (user_tsc_khz == 0)
2907 user_tsc_khz = tsc_khz;
2908
2909 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2910
2911 r = 0;
2912 goto out;
2913 }
2914 case KVM_GET_TSC_KHZ: {
cc578287 2915 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2916 goto out;
2917 }
1c0b28c2
EM		 2918 case KVM_KVMCLOCK_CTRL: {
2919 r = kvm_set_guest_paused(vcpu);
2920 goto out;
2921 }
313a3dc7
CO		 2922 default:
2923 r = -EINVAL;
2924 }
2925out:
d1ac91d8 2926 kfree(u.buffer);
313a3dc7
CO		 2927 return r;
2928}
2929
5b1c1493
CO		 2930int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2931{
2932 return VM_FAULT_SIGBUS;
2933}
2934
1fe779f8
CO		 2935static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2936{
2937 int ret;
2938
2939 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2940 return -1;
2941 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2942 return ret;
2943}
2944
b927a3ce
SY		 2945static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2946 u64 ident_addr)
2947{
2948 kvm->arch.ept_identity_map_addr = ident_addr;
2949 return 0;
2950}
2951
1fe779f8
CO		 2952static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2953 u32 kvm_nr_mmu_pages)
2954{
2955 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2956 return -EINVAL;
2957
79fac95e 2958 mutex_lock(&kvm->slots_lock);
7c8a83b7 2959 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2960
2961 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2962 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2963
7c8a83b7 2964 spin_unlock(&kvm->mmu_lock);
79fac95e 2965 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2966 return 0;
2967}
2968
2969static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2970{
39de71ec 2971 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2972}
2973
1fe779f8
CO		 2974static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2975{
2976 int r;
2977
2978 r = 0;
2979 switch (chip->chip_id) {
2980 case KVM_IRQCHIP_PIC_MASTER:
2981 memcpy(&chip->chip.pic,
2982 &pic_irqchip(kvm)->pics[0],
2983 sizeof(struct kvm_pic_state));
2984 break;
2985 case KVM_IRQCHIP_PIC_SLAVE:
2986 memcpy(&chip->chip.pic,
2987 &pic_irqchip(kvm)->pics[1],
2988 sizeof(struct kvm_pic_state));
2989 break;
2990 case KVM_IRQCHIP_IOAPIC:
eba0226b 2991 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2992 break;
2993 default:
2994 r = -EINVAL;
2995 break;
2996 }
2997 return r;
2998}
2999
3000static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3001{
3002 int r;
3003
3004 r = 0;
3005 switch (chip->chip_id) {
3006 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3007 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3008 memcpy(&pic_irqchip(kvm)->pics[0],
3009 &chip->chip.pic,
3010 sizeof(struct kvm_pic_state));
f4f51050 3011 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3012 break;
3013 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3014 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3015 memcpy(&pic_irqchip(kvm)->pics[1],
3016 &chip->chip.pic,
3017 sizeof(struct kvm_pic_state));
f4f51050 3018 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3019 break;
3020 case KVM_IRQCHIP_IOAPIC:
eba0226b 3021 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3022 break;
3023 default:
3024 r = -EINVAL;
3025 break;
3026 }
3027 kvm_pic_update_irq(pic_irqchip(kvm));
3028 return r;
3029}
3030
e0f63cb9
SY		 3031static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3032{
3033 int r = 0;
3034
894a9c55 3035 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3036 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3037 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3038 return r;
3039}
3040
3041static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3042{
3043 int r = 0;
3044
894a9c55 3045 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3046 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3047 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3048 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3049 return r;
3050}
3051
3052static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3053{
3054 int r = 0;
3055
3056 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3057 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3058 sizeof(ps->channels));
3059 ps->flags = kvm->arch.vpit->pit_state.flags;
3060 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3061 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3062 return r;
3063}
3064
3065static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3066{
3067 int r = 0, start = 0;
3068 u32 prev_legacy, cur_legacy;
3069 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3070 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3071 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3072 if (!prev_legacy && cur_legacy)
3073 start = 1;
3074 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3075 sizeof(kvm->arch.vpit->pit_state.channels));
3076 kvm->arch.vpit->pit_state.flags = ps->flags;
3077 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3078 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3079 return r;
3080}
3081
52d939a0
MT		 3082static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3083 struct kvm_reinject_control *control)
3084{
3085 if (!kvm->arch.vpit)
3086 return -ENXIO;
894a9c55 3087 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3088 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3089 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3090 return 0;
3091}
3092
95d4c16c 3093/**
60c34612
TY		 3094 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3095 * @kvm: kvm instance
3096 * @log: slot id and address to which we copy the log
95d4c16c 3097 *
60c34612
TY		 3098 * We need to keep it in mind that VCPU threads can write to the bitmap
3099 * concurrently. So, to avoid losing data, we keep the following order for
3100 * each bit:
95d4c16c 3101 *
60c34612
TY		 3102 * 1. Take a snapshot of the bit and clear it if needed.
3103 * 2. Write protect the corresponding page.
3104 * 3. Flush TLB's if needed.
3105 * 4. Copy the snapshot to the userspace.
95d4c16c 3106 *
60c34612
TY		 3107 * Between 2 and 3, the guest may write to the page using the remaining TLB
3108 * entry. This is not a problem because the page will be reported dirty at
3109 * step 4 using the snapshot taken before and step 3 ensures that successive
3110 * writes will be logged for the next call.
5bb064dc 3111 */
60c34612 3112int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3113{
7850ac54 3114 int r;
5bb064dc 3115 struct kvm_memory_slot *memslot;
60c34612
TY		 3116 unsigned long n, i;
3117 unsigned long *dirty_bitmap;
3118 unsigned long *dirty_bitmap_buffer;
3119 bool is_dirty = false;
5bb064dc 3120
79fac95e 3121 mutex_lock(&kvm->slots_lock);
5bb064dc 3122
b050b015
MT		 3123 r = -EINVAL;
3124 if (log->slot >= KVM_MEMORY_SLOTS)
3125 goto out;
3126
28a37544 3127 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3128
3129 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3130 r = -ENOENT;
60c34612 3131 if (!dirty_bitmap)
b050b015
MT		 3132 goto out;
3133
87bf6e7d 3134 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3135
60c34612
TY		 3136 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3137 memset(dirty_bitmap_buffer, 0, n);
b050b015 3138
60c34612 3139 spin_lock(&kvm->mmu_lock);
b050b015 3140
60c34612
TY		 3141 for (i = 0; i < n / sizeof(long); i++) {
3142 unsigned long mask;
3143 gfn_t offset;
cdfca7b3 3144
60c34612
TY		 3145 if (!dirty_bitmap[i])
3146 continue;
b050b015 3147
60c34612 3148 is_dirty = true;
914ebccd 3149
60c34612
TY		 3150 mask = xchg(&dirty_bitmap[i], 0);
3151 dirty_bitmap_buffer[i] = mask;
edde99ce 3152
60c34612
TY		 3153 offset = i * BITS_PER_LONG;
3154 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3155 }
60c34612
TY		 3156 if (is_dirty)
3157 kvm_flush_remote_tlbs(kvm);
3158
3159 spin_unlock(&kvm->mmu_lock);
3160
3161 r = -EFAULT;
3162 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3163 goto out;
b050b015 3164
5bb064dc
ZX		 3165 r = 0;
3166out:
79fac95e 3167 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3168 return r;
3169}
3170
23d43cf9
CD		 3171int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3172{
3173 if (!irqchip_in_kernel(kvm))
3174 return -ENXIO;
3175
3176 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3177 irq_event->irq, irq_event->level);
3178 return 0;
3179}
3180
1fe779f8
CO		 3181long kvm_arch_vm_ioctl(struct file *filp,
3182 unsigned int ioctl, unsigned long arg)
3183{
3184 struct kvm *kvm = filp->private_data;
3185 void __user *argp = (void __user *)arg;
367e1319 3186 int r = -ENOTTY;
f0d66275
DH		 3187 /*
3188 * This union makes it completely explicit to gcc-3.x
3189 * that these two variables' stack usage should be
3190 * combined, not added together.
3191 */
3192 union {
3193 struct kvm_pit_state ps;
e9f42757 3194 struct kvm_pit_state2 ps2;
c5ff41ce 3195 struct kvm_pit_config pit_config;
f0d66275 3196 } u;
1fe779f8
CO		 3197
3198 switch (ioctl) {
3199 case KVM_SET_TSS_ADDR:
3200 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3201 if (r < 0)
3202 goto out;
3203 break;
b927a3ce
SY		 3204 case KVM_SET_IDENTITY_MAP_ADDR: {
3205 u64 ident_addr;
3206
3207 r = -EFAULT;
3208 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3209 goto out;
3210 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3211 if (r < 0)
3212 goto out;
3213 break;
3214 }
1fe779f8
CO		 3215 case KVM_SET_NR_MMU_PAGES:
3216 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3217 if (r)
3218 goto out;
3219 break;
3220 case KVM_GET_NR_MMU_PAGES:
3221 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3222 break;
3ddea128
MT		 3223 case KVM_CREATE_IRQCHIP: {
3224 struct kvm_pic *vpic;
3225
3226 mutex_lock(&kvm->lock);
3227 r = -EEXIST;
3228 if (kvm->arch.vpic)
3229 goto create_irqchip_unlock;
3e515705
AK		 3230 r = -EINVAL;
3231 if (atomic_read(&kvm->online_vcpus))
3232 goto create_irqchip_unlock;
1fe779f8 3233 r = -ENOMEM;
3ddea128
MT		 3234 vpic = kvm_create_pic(kvm);
3235 if (vpic) {
1fe779f8
CO		 3236 r = kvm_ioapic_init(kvm);
3237 if (r) {
175504cd 3238 mutex_lock(&kvm->slots_lock);
72bb2fcd 3239 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3240 &vpic->dev_master);
3241 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3242 &vpic->dev_slave);
3243 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3244 &vpic->dev_eclr);
175504cd 3245 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3246 kfree(vpic);
3247 goto create_irqchip_unlock;
1fe779f8
CO		 3248 }
3249 } else
3ddea128
MT		 3250 goto create_irqchip_unlock;
3251 smp_wmb();
3252 kvm->arch.vpic = vpic;
3253 smp_wmb();
399ec807
AK		 3254 r = kvm_setup_default_irq_routing(kvm);
3255 if (r) {
175504cd 3256 mutex_lock(&kvm->slots_lock);
3ddea128 3257 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3258 kvm_ioapic_destroy(kvm);
3259 kvm_destroy_pic(kvm);
3ddea128 3260 mutex_unlock(&kvm->irq_lock);
175504cd 3261 mutex_unlock(&kvm->slots_lock);
399ec807 3262 }
3ddea128
MT		 3263 create_irqchip_unlock:
3264 mutex_unlock(&kvm->lock);
1fe779f8 3265 break;
3ddea128 3266 }
7837699f 3267 case KVM_CREATE_PIT:
c5ff41ce
JK		 3268 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3269 goto create_pit;
3270 case KVM_CREATE_PIT2:
3271 r = -EFAULT;
3272 if (copy_from_user(&u.pit_config, argp,
3273 sizeof(struct kvm_pit_config)))
3274 goto out;
3275 create_pit:
79fac95e 3276 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3277 r = -EEXIST;
3278 if (kvm->arch.vpit)
3279 goto create_pit_unlock;
7837699f 3280 r = -ENOMEM;
c5ff41ce 3281 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3282 if (kvm->arch.vpit)
3283 r = 0;
269e05e4 3284 create_pit_unlock:
79fac95e 3285 mutex_unlock(&kvm->slots_lock);
7837699f 3286 break;
1fe779f8
CO		 3287 case KVM_GET_IRQCHIP: {
3288 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3289 struct kvm_irqchip *chip;
1fe779f8 3290
ff5c2c03
SL		 3291 chip = memdup_user(argp, sizeof(*chip));
3292 if (IS_ERR(chip)) {
3293 r = PTR_ERR(chip);
1fe779f8 3294 goto out;
ff5c2c03
SL		 3295 }
3296
1fe779f8
CO		 3297 r = -ENXIO;
3298 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3299 goto get_irqchip_out;
3300 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3301 if (r)
f0d66275 3302 goto get_irqchip_out;
1fe779f8 3303 r = -EFAULT;
f0d66275
DH		 3304 if (copy_to_user(argp, chip, sizeof *chip))
3305 goto get_irqchip_out;
1fe779f8 3306 r = 0;
f0d66275
DH		 3307 get_irqchip_out:
3308 kfree(chip);
3309 if (r)
3310 goto out;
1fe779f8
CO		 3311 break;
3312 }
3313 case KVM_SET_IRQCHIP: {
3314 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3315 struct kvm_irqchip *chip;
1fe779f8 3316
ff5c2c03
SL		 3317 chip = memdup_user(argp, sizeof(*chip));
3318 if (IS_ERR(chip)) {
3319 r = PTR_ERR(chip);
1fe779f8 3320 goto out;
ff5c2c03
SL		 3321 }
3322
1fe779f8
CO		 3323 r = -ENXIO;
3324 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3325 goto set_irqchip_out;
3326 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3327 if (r)
f0d66275 3328 goto set_irqchip_out;
1fe779f8 3329 r = 0;
f0d66275
DH		 3330 set_irqchip_out:
3331 kfree(chip);
3332 if (r)
3333 goto out;
1fe779f8
CO		 3334 break;
3335 }
e0f63cb9 3336 case KVM_GET_PIT: {
e0f63cb9 3337 r = -EFAULT;
f0d66275 3338 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3339 goto out;
3340 r = -ENXIO;
3341 if (!kvm->arch.vpit)
3342 goto out;
f0d66275 3343 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3344 if (r)
3345 goto out;
3346 r = -EFAULT;
f0d66275 3347 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3348 goto out;
3349 r = 0;
3350 break;
3351 }
3352 case KVM_SET_PIT: {
e0f63cb9 3353 r = -EFAULT;
f0d66275 3354 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3355 goto out;
3356 r = -ENXIO;
3357 if (!kvm->arch.vpit)
3358 goto out;
f0d66275 3359 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3360 if (r)
3361 goto out;
3362 r = 0;
3363 break;
3364 }
e9f42757
BK		 3365 case KVM_GET_PIT2: {
3366 r = -ENXIO;
3367 if (!kvm->arch.vpit)
3368 goto out;
3369 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3370 if (r)
3371 goto out;
3372 r = -EFAULT;
3373 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3374 goto out;
3375 r = 0;
3376 break;
3377 }
3378 case KVM_SET_PIT2: {
3379 r = -EFAULT;
3380 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3381 goto out;
3382 r = -ENXIO;
3383 if (!kvm->arch.vpit)
3384 goto out;
3385 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3386 if (r)
3387 goto out;
3388 r = 0;
3389 break;
3390 }
52d939a0
MT		 3391 case KVM_REINJECT_CONTROL: {
3392 struct kvm_reinject_control control;
3393 r = -EFAULT;
3394 if (copy_from_user(&control, argp, sizeof(control)))
3395 goto out;
3396 r = kvm_vm_ioctl_reinject(kvm, &control);
3397 if (r)
3398 goto out;
3399 r = 0;
3400 break;
3401 }
ffde22ac
ES		 3402 case KVM_XEN_HVM_CONFIG: {
3403 r = -EFAULT;
3404 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3405 sizeof(struct kvm_xen_hvm_config)))
3406 goto out;
3407 r = -EINVAL;
3408 if (kvm->arch.xen_hvm_config.flags)
3409 goto out;
3410 r = 0;
3411 break;
3412 }
afbcf7ab 3413 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3414 struct kvm_clock_data user_ns;
3415 u64 now_ns;
3416 s64 delta;
3417
3418 r = -EFAULT;
3419 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3420 goto out;
3421
3422 r = -EINVAL;
3423 if (user_ns.flags)
3424 goto out;
3425
3426 r = 0;
395c6b0a 3427 local_irq_disable();
759379dd 3428 now_ns = get_kernel_ns();
afbcf7ab 3429 delta = user_ns.clock - now_ns;
395c6b0a 3430 local_irq_enable();
afbcf7ab
GC		 3431 kvm->arch.kvmclock_offset = delta;
3432 break;
3433 }
3434 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3435 struct kvm_clock_data user_ns;
3436 u64 now_ns;
3437
395c6b0a 3438 local_irq_disable();
759379dd 3439 now_ns = get_kernel_ns();
afbcf7ab 3440 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3441 local_irq_enable();
afbcf7ab 3442 user_ns.flags = 0;
97e69aa6 3443 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3444
3445 r = -EFAULT;
3446 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3447 goto out;
3448 r = 0;
3449 break;
3450 }
3451
1fe779f8
CO		 3452 default:
3453 ;
3454 }
3455out:
3456 return r;
3457}
3458
a16b043c 3459static void kvm_init_msr_list(void)
043405e1
CO		 3460{
3461 u32 dummy[2];
3462 unsigned i, j;
3463
e3267cbb
GC		 3464 /* skip the first msrs in the list. KVM-specific */
3465 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3466 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3467 continue;
3468 if (j < i)
3469 msrs_to_save[j] = msrs_to_save[i];
3470 j++;
3471 }
3472 num_msrs_to_save = j;
3473}
3474
bda9020e
MT		 3475static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3476 const void *v)
bbd9b64e 3477{
70252a10
AK		 3478 int handled = 0;
3479 int n;
3480
3481 do {
3482 n = min(len, 8);
3483 if (!(vcpu->arch.apic &&
3484 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3485 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3486 break;
3487 handled += n;
3488 addr += n;
3489 len -= n;
3490 v += n;
3491 } while (len);
bbd9b64e 3492
70252a10 3493 return handled;
bbd9b64e
CO		 3494}
3495
bda9020e 3496static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3497{
70252a10
AK		 3498 int handled = 0;
3499 int n;
3500
3501 do {
3502 n = min(len, 8);
3503 if (!(vcpu->arch.apic &&
3504 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3505 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3506 break;
3507 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3508 handled += n;
3509 addr += n;
3510 len -= n;
3511 v += n;
3512 } while (len);
bbd9b64e 3513
70252a10 3514 return handled;
bbd9b64e
CO		 3515}
3516
2dafc6c2
GN		 3517static void kvm_set_segment(struct kvm_vcpu *vcpu,
3518 struct kvm_segment *var, int seg)
3519{
3520 kvm_x86_ops->set_segment(vcpu, var, seg);
3521}
3522
3523void kvm_get_segment(struct kvm_vcpu *vcpu,
3524 struct kvm_segment *var, int seg)
3525{
3526 kvm_x86_ops->get_segment(vcpu, var, seg);
3527}
3528
e459e322 3529gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3530{
3531 gpa_t t_gpa;
ab9ae313 3532 struct x86_exception exception;
02f59dc9
JR		 3533
3534 BUG_ON(!mmu_is_nested(vcpu));
3535
3536 /* NPT walks are always user-walks */
3537 access |= PFERR_USER_MASK;
ab9ae313 3538 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3539
3540 return t_gpa;
3541}
3542
ab9ae313
AK		 3543gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3544 struct x86_exception *exception)
1871c602
GN		 3545{
3546 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3547 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3548}
3549
ab9ae313
AK		 3550 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3551 struct x86_exception *exception)
1871c602
GN		 3552{
3553 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3554 access |= PFERR_FETCH_MASK;
ab9ae313 3555 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3556}
3557
ab9ae313
AK		 3558gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3559 struct x86_exception *exception)
1871c602
GN		 3560{
3561 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3562 access |= PFERR_WRITE_MASK;
ab9ae313 3563 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3564}
3565
3566/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3567gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3568 struct x86_exception *exception)
1871c602 3569{
ab9ae313 3570 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3571}
3572
3573static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3574 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3575 struct x86_exception *exception)
bbd9b64e
CO		 3576{
3577 void *data = val;
10589a46 3578 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3579
3580 while (bytes) {
14dfe855 3581 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3582 exception);
bbd9b64e 3583 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3584 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3585 int ret;
3586
bcc55cba 3587 if (gpa == UNMAPPED_GVA)
ab9ae313 3588 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3589 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3590 if (ret < 0) {
c3cd7ffa 3591 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3592 goto out;
3593 }
bbd9b64e 3594
77c2002e
IE		 3595 bytes -= toread;
3596 data += toread;
3597 addr += toread;
bbd9b64e 3598 }
10589a46 3599out:
10589a46 3600 return r;
bbd9b64e 3601}
77c2002e 3602
1871c602 3603/* used for instruction fetching */
0f65dd70
AK		 3604static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3605 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3606 struct x86_exception *exception)
1871c602 3607{
0f65dd70 3608 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3609 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3610
1871c602 3611 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3612 access | PFERR_FETCH_MASK,
3613 exception);
1871c602
GN		 3614}
3615
064aea77 3616int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3617 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3618 struct x86_exception *exception)
1871c602 3619{
0f65dd70 3620 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3621 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3622
1871c602 3623 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3624 exception);
1871c602 3625}
064aea77 3626EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3627
0f65dd70
AK		 3628static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3629 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3630 struct x86_exception *exception)
1871c602 3631{
0f65dd70 3632 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3633 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3634}
3635
6a4d7550 3636int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3637 gva_t addr, void *val,
2dafc6c2 3638 unsigned int bytes,
bcc55cba 3639 struct x86_exception *exception)
77c2002e 3640{
0f65dd70 3641 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3642 void *data = val;
3643 int r = X86EMUL_CONTINUE;
3644
3645 while (bytes) {
14dfe855
JR		 3646 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3647 PFERR_WRITE_MASK,
ab9ae313 3648 exception);
77c2002e
IE		 3649 unsigned offset = addr & (PAGE_SIZE-1);
3650 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3651 int ret;
3652
bcc55cba 3653 if (gpa == UNMAPPED_GVA)
ab9ae313 3654 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3655 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3656 if (ret < 0) {
c3cd7ffa 3657 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3658 goto out;
3659 }
3660
3661 bytes -= towrite;
3662 data += towrite;
3663 addr += towrite;
3664 }
3665out:
3666 return r;
3667}
6a4d7550 3668EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3669
af7cc7d1
XG		 3670static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3671 gpa_t *gpa, struct x86_exception *exception,
3672 bool write)
3673{
3674 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3675
bebb106a
XG		 3676 if (vcpu_match_mmio_gva(vcpu, gva) &&
3677 check_write_user_access(vcpu, write, access,
3678 vcpu->arch.access)) {
3679 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3680 (gva & (PAGE_SIZE - 1));
4f022648 3681 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3682 return 1;
3683 }
3684
af7cc7d1
XG		 3685 if (write)
3686 access |= PFERR_WRITE_MASK;
3687
3688 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3689
3690 if (*gpa == UNMAPPED_GVA)
3691 return -1;
3692
3693 /* For APIC access vmexit */
3694 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3695 return 1;
3696
4f022648
XG		 3697 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3698 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3699 return 1;
4f022648 3700 }
bebb106a 3701
af7cc7d1
XG		 3702 return 0;
3703}
3704
3200f405 3705int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3706 const void *val, int bytes)
bbd9b64e
CO		 3707{
3708 int ret;
3709
3710 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3711 if (ret < 0)
bbd9b64e 3712 return 0;
f57f2ef5 3713 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3714 return 1;
3715}
3716
77d197b2
XG		 3717struct read_write_emulator_ops {
3718 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3719 int bytes);
3720 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3721 void *val, int bytes);
3722 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3723 int bytes, void *val);
3724 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3725 void *val, int bytes);
3726 bool write;
3727};
3728
3729static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3730{
3731 if (vcpu->mmio_read_completed) {
77d197b2 3732 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3733 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3734 vcpu->mmio_read_completed = 0;
3735 return 1;
3736 }
3737
3738 return 0;
3739}
3740
3741static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3742 void *val, int bytes)
3743{
3744 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3745}
3746
3747static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3748 void *val, int bytes)
3749{
3750 return emulator_write_phys(vcpu, gpa, val, bytes);
3751}
3752
3753static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3754{
3755 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3756 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3757}
3758
3759static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3760 void *val, int bytes)
3761{
3762 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3763 return X86EMUL_IO_NEEDED;
3764}
3765
3766static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3767 void *val, int bytes)
3768{
f78146b0
AK		 3769 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3770
3771 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3772 return X86EMUL_CONTINUE;
3773}
3774
3775static struct read_write_emulator_ops read_emultor = {
3776 .read_write_prepare = read_prepare,
3777 .read_write_emulate = read_emulate,
3778 .read_write_mmio = vcpu_mmio_read,
3779 .read_write_exit_mmio = read_exit_mmio,
3780};
3781
3782static struct read_write_emulator_ops write_emultor = {
3783 .read_write_emulate = write_emulate,
3784 .read_write_mmio = write_mmio,
3785 .read_write_exit_mmio = write_exit_mmio,
3786 .write = true,
3787};
3788
22388a3c
XG		 3789static int emulator_read_write_onepage(unsigned long addr, void *val,
3790 unsigned int bytes,
3791 struct x86_exception *exception,
3792 struct kvm_vcpu *vcpu,
3793 struct read_write_emulator_ops *ops)
bbd9b64e 3794{
af7cc7d1
XG		 3795 gpa_t gpa;
3796 int handled, ret;
22388a3c 3797 bool write = ops->write;
f78146b0 3798 struct kvm_mmio_fragment *frag;
10589a46 3799
22388a3c 3800 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3801
af7cc7d1 3802 if (ret < 0)
bbd9b64e 3803 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3804
3805 /* For APIC access vmexit */
af7cc7d1 3806 if (ret)
bbd9b64e
CO		 3807 goto mmio;
3808
22388a3c 3809 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3810 return X86EMUL_CONTINUE;
3811
3812mmio:
3813 /*
3814 * Is this MMIO handled locally?
3815 */
22388a3c 3816 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3817 if (handled == bytes)
bbd9b64e 3818 return X86EMUL_CONTINUE;
bbd9b64e 3819
70252a10
AK		 3820 gpa += handled;
3821 bytes -= handled;
3822 val += handled;
3823
f78146b0
AK		 3824 while (bytes) {
3825 unsigned now = min(bytes, 8U);
bbd9b64e 3826
f78146b0
AK		 3827 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3828 frag->gpa = gpa;
3829 frag->data = val;
3830 frag->len = now;
3831
3832 gpa += now;
3833 val += now;
3834 bytes -= now;
3835 }
3836 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3837}
3838
22388a3c
XG		 3839int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3840 void *val, unsigned int bytes,
3841 struct x86_exception *exception,
3842 struct read_write_emulator_ops *ops)
bbd9b64e 3843{
0f65dd70 3844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3845 gpa_t gpa;
3846 int rc;
3847
3848 if (ops->read_write_prepare &&
3849 ops->read_write_prepare(vcpu, val, bytes))
3850 return X86EMUL_CONTINUE;
3851
3852 vcpu->mmio_nr_fragments = 0;
0f65dd70 3853
bbd9b64e
CO		 3854 /* Crossing a page boundary? */
3855 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3856 int now;
bbd9b64e
CO		 3857
3858 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3859 rc = emulator_read_write_onepage(addr, val, now, exception,
3860 vcpu, ops);
3861
bbd9b64e
CO		 3862 if (rc != X86EMUL_CONTINUE)
3863 return rc;
3864 addr += now;
3865 val += now;
3866 bytes -= now;
3867 }
22388a3c 3868
f78146b0
AK		 3869 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3870 vcpu, ops);
3871 if (rc != X86EMUL_CONTINUE)
3872 return rc;
3873
3874 if (!vcpu->mmio_nr_fragments)
3875 return rc;
3876
3877 gpa = vcpu->mmio_fragments[0].gpa;
3878
3879 vcpu->mmio_needed = 1;
3880 vcpu->mmio_cur_fragment = 0;
3881
3882 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3883 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3884 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3885 vcpu->run->mmio.phys_addr = gpa;
3886
3887 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3888}
3889
3890static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3891 unsigned long addr,
3892 void *val,
3893 unsigned int bytes,
3894 struct x86_exception *exception)
3895{
3896 return emulator_read_write(ctxt, addr, val, bytes,
3897 exception, &read_emultor);
3898}
3899
3900int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3901 unsigned long addr,
3902 const void *val,
3903 unsigned int bytes,
3904 struct x86_exception *exception)
3905{
3906 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3907 exception, &write_emultor);
bbd9b64e 3908}
bbd9b64e 3909
daea3e73
AK		 3910#define CMPXCHG_TYPE(t, ptr, old, new) \
3911 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3912
3913#ifdef CONFIG_X86_64
3914# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3915#else
3916# define CMPXCHG64(ptr, old, new) \
9749a6c0 3917 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3918#endif
3919
0f65dd70
AK		 3920static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3921 unsigned long addr,
bbd9b64e
CO		 3922 const void *old,
3923 const void *new,
3924 unsigned int bytes,
0f65dd70 3925 struct x86_exception *exception)
bbd9b64e 3926{
0f65dd70 3927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3928 gpa_t gpa;
3929 struct page *page;
3930 char *kaddr;
3931 bool exchanged;
2bacc55c 3932
daea3e73
AK		 3933 /* guests cmpxchg8b have to be emulated atomically */
3934 if (bytes > 8 || (bytes & (bytes - 1)))
3935 goto emul_write;
10589a46 3936
daea3e73 3937 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3938
daea3e73
AK		 3939 if (gpa == UNMAPPED_GVA ||
3940 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3941 goto emul_write;
2bacc55c 3942
daea3e73
AK		 3943 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3944 goto emul_write;
72dc67a6 3945
daea3e73 3946 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 3947 if (is_error_page(page))
c19b8bd6 3948 goto emul_write;
72dc67a6 3949
8fd75e12 3950 kaddr = kmap_atomic(page);
daea3e73
AK		 3951 kaddr += offset_in_page(gpa);
3952 switch (bytes) {
3953 case 1:
3954 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3955 break;
3956 case 2:
3957 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3958 break;
3959 case 4:
3960 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3961 break;
3962 case 8:
3963 exchanged = CMPXCHG64(kaddr, old, new);
3964 break;
3965 default:
3966 BUG();
2bacc55c 3967 }
8fd75e12 3968 kunmap_atomic(kaddr);
daea3e73
AK		 3969 kvm_release_page_dirty(page);
3970
3971 if (!exchanged)
3972 return X86EMUL_CMPXCHG_FAILED;
3973
f57f2ef5 3974 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3975
3976 return X86EMUL_CONTINUE;
4a5f48f6 3977
3200f405 3978emul_write:
daea3e73 3979 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3980
0f65dd70 3981 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3982}
3983
cf8f70bf
GN		 3984static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3985{
3986 /* TODO: String I/O for in kernel device */
3987 int r;
3988
3989 if (vcpu->arch.pio.in)
3990 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3991 vcpu->arch.pio.size, pd);
3992 else
3993 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3994 vcpu->arch.pio.port, vcpu->arch.pio.size,
3995 pd);
3996 return r;
3997}
3998
6f6fbe98
XG		 3999static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4000 unsigned short port, void *val,
4001 unsigned int count, bool in)
cf8f70bf 4002{
6f6fbe98 4003 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4004
4005 vcpu->arch.pio.port = port;
6f6fbe98 4006 vcpu->arch.pio.in = in;
7972995b 4007 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4008 vcpu->arch.pio.size = size;
4009
4010 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4011 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4012 return 1;
4013 }
4014
4015 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4016 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4017 vcpu->run->io.size = size;
4018 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4019 vcpu->run->io.count = count;
4020 vcpu->run->io.port = port;
4021
4022 return 0;
4023}
4024
6f6fbe98
XG		 4025static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4026 int size, unsigned short port, void *val,
4027 unsigned int count)
cf8f70bf 4028{
ca1d4a9e 4029 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4030 int ret;
ca1d4a9e 4031
6f6fbe98
XG		 4032 if (vcpu->arch.pio.count)
4033 goto data_avail;
cf8f70bf 4034
6f6fbe98
XG		 4035 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4036 if (ret) {
4037data_avail:
4038 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4039 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4040 return 1;
4041 }
4042
cf8f70bf
GN		 4043 return 0;
4044}
4045
6f6fbe98
XG		 4046static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4047 int size, unsigned short port,
4048 const void *val, unsigned int count)
4049{
4050 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4051
4052 memcpy(vcpu->arch.pio_data, val, size * count);
4053 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4054}
4055
bbd9b64e
CO		 4056static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4057{
4058 return kvm_x86_ops->get_segment_base(vcpu, seg);
4059}
4060
3cb16fe7 4061static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4062{
3cb16fe7 4063 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4064}
4065
f5f48ee1
SY		 4066int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4067{
4068 if (!need_emulate_wbinvd(vcpu))
4069 return X86EMUL_CONTINUE;
4070
4071 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4072 int cpu = get_cpu();
4073
4074 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4075 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4076 wbinvd_ipi, NULL, 1);
2eec7343 4077 put_cpu();
f5f48ee1 4078 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4079 } else
4080 wbinvd();
f5f48ee1
SY		 4081 return X86EMUL_CONTINUE;
4082}
4083EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4084
bcaf5cc5
AK		 4085static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4086{
4087 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4088}
4089
717746e3 4090int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4091{
717746e3 4092 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4093}
4094
717746e3 4095int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4096{
338dbc97 4097
717746e3 4098 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4099}
4100
52a46617 4101static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4102{
52a46617 4103 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4104}
4105
717746e3 4106static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4107{
717746e3 4108 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4109 unsigned long value;
4110
4111 switch (cr) {
4112 case 0:
4113 value = kvm_read_cr0(vcpu);
4114 break;
4115 case 2:
4116 value = vcpu->arch.cr2;
4117 break;
4118 case 3:
9f8fe504 4119 value = kvm_read_cr3(vcpu);
52a46617
GN		 4120 break;
4121 case 4:
4122 value = kvm_read_cr4(vcpu);
4123 break;
4124 case 8:
4125 value = kvm_get_cr8(vcpu);
4126 break;
4127 default:
a737f256 4128 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4129 return 0;
4130 }
4131
4132 return value;
4133}
4134
717746e3 4135static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4136{
717746e3 4137 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4138 int res = 0;
4139
52a46617
GN		 4140 switch (cr) {
4141 case 0:
49a9b07e 4142 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4143 break;
4144 case 2:
4145 vcpu->arch.cr2 = val;
4146 break;
4147 case 3:
2390218b 4148 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4149 break;
4150 case 4:
a83b29c6 4151 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4152 break;
4153 case 8:
eea1cff9 4154 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4155 break;
4156 default:
a737f256 4157 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4158 res = -1;
52a46617 4159 }
0f12244f
GN		 4160
4161 return res;
52a46617
GN		 4162}
4163
4cee4798
KW		 4164static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4165{
4166 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4167}
4168
717746e3 4169static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4170{
717746e3 4171 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4172}
4173
4bff1e86 4174static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4175{
4bff1e86 4176 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4177}
4178
4bff1e86 4179static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4180{
4bff1e86 4181 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4182}
4183
1ac9d0cf
AK		 4184static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4185{
4186 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4187}
4188
4189static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4190{
4191 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4192}
4193
4bff1e86
AK		 4194static unsigned long emulator_get_cached_segment_base(
4195 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4196{
4bff1e86 4197 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4198}
4199
1aa36616
AK		 4200static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4201 struct desc_struct *desc, u32 *base3,
4202 int seg)
2dafc6c2
GN		 4203{
4204 struct kvm_segment var;
4205
4bff1e86 4206 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4207 *selector = var.selector;
2dafc6c2
GN		 4208
4209 if (var.unusable)
4210 return false;
4211
4212 if (var.g)
4213 var.limit >>= 12;
4214 set_desc_limit(desc, var.limit);
4215 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4216#ifdef CONFIG_X86_64
4217 if (base3)
4218 *base3 = var.base >> 32;
4219#endif
2dafc6c2
GN		 4220 desc->type = var.type;
4221 desc->s = var.s;
4222 desc->dpl = var.dpl;
4223 desc->p = var.present;
4224 desc->avl = var.avl;
4225 desc->l = var.l;
4226 desc->d = var.db;
4227 desc->g = var.g;
4228
4229 return true;
4230}
4231
1aa36616
AK		 4232static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4233 struct desc_struct *desc, u32 base3,
4234 int seg)
2dafc6c2 4235{
4bff1e86 4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4237 struct kvm_segment var;
4238
1aa36616 4239 var.selector = selector;
2dafc6c2 4240 var.base = get_desc_base(desc);
5601d05b
GN		 4241#ifdef CONFIG_X86_64
4242 var.base |= ((u64)base3) << 32;
4243#endif
2dafc6c2
GN		 4244 var.limit = get_desc_limit(desc);
4245 if (desc->g)
4246 var.limit = (var.limit << 12) | 0xfff;
4247 var.type = desc->type;
4248 var.present = desc->p;
4249 var.dpl = desc->dpl;
4250 var.db = desc->d;
4251 var.s = desc->s;
4252 var.l = desc->l;
4253 var.g = desc->g;
4254 var.avl = desc->avl;
4255 var.present = desc->p;
4256 var.unusable = !var.present;
4257 var.padding = 0;
4258
4259 kvm_set_segment(vcpu, &var, seg);
4260 return;
4261}
4262
717746e3
AK		 4263static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4264 u32 msr_index, u64 *pdata)
4265{
4266 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4267}
4268
4269static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4270 u32 msr_index, u64 data)
4271{
4272 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4273}
4274
222d21aa
AK		 4275static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4276 u32 pmc, u64 *pdata)
4277{
4278 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4279}
4280
6c3287f7
AK		 4281static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4282{
4283 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4284}
4285
5037f6f3
AK		 4286static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4287{
4288 preempt_disable();
5197b808 4289 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4290 /*
4291 * CR0.TS may reference the host fpu state, not the guest fpu state,
4292 * so it may be clear at this point.
4293 */
4294 clts();
4295}
4296
4297static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4298{
4299 preempt_enable();
4300}
4301
2953538e 4302static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4303 struct x86_instruction_info *info,
c4f035c6
AK		 4304 enum x86_intercept_stage stage)
4305{
2953538e 4306 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4307}
4308
0017f93a 4309static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4310 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4311{
0017f93a 4312 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4313}
4314
14af3f3c 4315static struct x86_emulate_ops emulate_ops = {
1871c602 4316 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4317 .write_std = kvm_write_guest_virt_system,
1871c602 4318 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4319 .read_emulated = emulator_read_emulated,
4320 .write_emulated = emulator_write_emulated,
4321 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4322 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4323 .pio_in_emulated = emulator_pio_in_emulated,
4324 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4325 .get_segment = emulator_get_segment,
4326 .set_segment = emulator_set_segment,
5951c442 4327 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4328 .get_gdt = emulator_get_gdt,
160ce1f1 4329 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4330 .set_gdt = emulator_set_gdt,
4331 .set_idt = emulator_set_idt,
52a46617
GN		 4332 .get_cr = emulator_get_cr,
4333 .set_cr = emulator_set_cr,
4cee4798 4334 .set_rflags = emulator_set_rflags,
9c537244 4335 .cpl = emulator_get_cpl,
35aa5375
GN		 4336 .get_dr = emulator_get_dr,
4337 .set_dr = emulator_set_dr,
717746e3
AK		 4338 .set_msr = emulator_set_msr,
4339 .get_msr = emulator_get_msr,
222d21aa 4340 .read_pmc = emulator_read_pmc,
6c3287f7 4341 .halt = emulator_halt,
bcaf5cc5 4342 .wbinvd = emulator_wbinvd,
d6aa1000 4343 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4344 .get_fpu = emulator_get_fpu,
4345 .put_fpu = emulator_put_fpu,
c4f035c6 4346 .intercept = emulator_intercept,
bdb42f5a 4347 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4348};
4349
5fdbf976
MT		 4350static void cache_all_regs(struct kvm_vcpu *vcpu)
4351{
4352 kvm_register_read(vcpu, VCPU_REGS_RAX);
4353 kvm_register_read(vcpu, VCPU_REGS_RSP);
4354 kvm_register_read(vcpu, VCPU_REGS_RIP);
4355 vcpu->arch.regs_dirty = ~0;
4356}
4357
95cb2295
GN		 4358static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4359{
4360 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4361 /*
4362 * an sti; sti; sequence only disable interrupts for the first
4363 * instruction. So, if the last instruction, be it emulated or
4364 * not, left the system with the INT_STI flag enabled, it
4365 * means that the last instruction is an sti. We should not
4366 * leave the flag on in this case. The same goes for mov ss
4367 */
4368 if (!(int_shadow & mask))
4369 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4370}
4371
54b8486f
GN		 4372static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4373{
4374 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4375 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4376 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4377 else if (ctxt->exception.error_code_valid)
4378 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4379 ctxt->exception.error_code);
54b8486f 4380 else
da9cb575 4381 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4382}
4383
9dac77fa 4384static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4385 const unsigned long *regs)
4386{
9dac77fa
AK		 4387 memset(&ctxt->twobyte, 0,
4388 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4389 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4390
9dac77fa
AK		 4391 ctxt->fetch.start = 0;
4392 ctxt->fetch.end = 0;
4393 ctxt->io_read.pos = 0;
4394 ctxt->io_read.end = 0;
4395 ctxt->mem_read.pos = 0;
4396 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4397}
4398
8ec4722d
MG		 4399static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4400{
adf52235 4401 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4402 int cs_db, cs_l;
4403
2aab2c5b
GN		 4404 /*
4405 * TODO: fix emulate.c to use guest_read/write_register
4406 * instead of direct ->regs accesses, can save hundred cycles
4407 * on Intel for instructions that don't read/change RSP, for
4408 * for example.
4409 */
8ec4722d
MG		 4410 cache_all_regs(vcpu);
4411
4412 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4413
adf52235
TY		 4414 ctxt->eflags = kvm_get_rflags(vcpu);
4415 ctxt->eip = kvm_rip_read(vcpu);
4416 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4417 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4418 cs_l ? X86EMUL_MODE_PROT64 :
4419 cs_db ? X86EMUL_MODE_PROT32 :
4420 X86EMUL_MODE_PROT16;
4421 ctxt->guest_mode = is_guest_mode(vcpu);
4422
9dac77fa 4423 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4424 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4425}
4426
71f9833b 4427int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4428{
9d74191a 4429 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4430 int ret;
4431
4432 init_emulate_ctxt(vcpu);
4433
9dac77fa
AK		 4434 ctxt->op_bytes = 2;
4435 ctxt->ad_bytes = 2;
4436 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4437 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4438
4439 if (ret != X86EMUL_CONTINUE)
4440 return EMULATE_FAIL;
4441
9dac77fa
AK		 4442 ctxt->eip = ctxt->_eip;
4443 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4444 kvm_rip_write(vcpu, ctxt->eip);
4445 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4446
4447 if (irq == NMI_VECTOR)
7460fb4a 4448 vcpu->arch.nmi_pending = 0;
63995653
MG		 4449 else
4450 vcpu->arch.interrupt.pending = false;
4451
4452 return EMULATE_DONE;
4453}
4454EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4455
6d77dbfc
GN		 4456static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4457{
fc3a9157
JR		 4458 int r = EMULATE_DONE;
4459
6d77dbfc
GN		 4460 ++vcpu->stat.insn_emulation_fail;
4461 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4462 if (!is_guest_mode(vcpu)) {
4463 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4464 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4465 vcpu->run->internal.ndata = 0;
4466 r = EMULATE_FAIL;
4467 }
6d77dbfc 4468 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4469
4470 return r;
6d77dbfc
GN		 4471}
4472
a6f177ef
GN		 4473static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4474{
4475 gpa_t gpa;
8e3d9d06 4476 pfn_t pfn;
a6f177ef 4477
68be0803
GN		 4478 if (tdp_enabled)
4479 return false;
4480
a6f177ef
GN		 4481 /*
4482 * if emulation was due to access to shadowed page table
4a969980 4483 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4484 * guest to let CPU execute the instruction.
4485 */
4486 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4487 return true;
4488
4489 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4490
4491 if (gpa == UNMAPPED_GVA)
4492 return true; /* let cpu generate fault */
4493
8e3d9d06
XG		 4494 /*
4495 * Do not retry the unhandleable instruction if it faults on the
4496 * readonly host memory, otherwise it will goto a infinite loop:
4497 * retry instruction -> write #PF -> emulation fail -> retry
4498 * instruction -> ...
4499 */
4500 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4501 if (!is_error_pfn(pfn)) {
4502 kvm_release_pfn_clean(pfn);
a6f177ef 4503 return true;
8e3d9d06 4504 }
a6f177ef
GN		 4505
4506 return false;
4507}
4508
1cb3f3ae
XG		 4509static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4510 unsigned long cr2, int emulation_type)
4511{
4512 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4513 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4514
4515 last_retry_eip = vcpu->arch.last_retry_eip;
4516 last_retry_addr = vcpu->arch.last_retry_addr;
4517
4518 /*
4519 * If the emulation is caused by #PF and it is non-page_table
4520 * writing instruction, it means the VM-EXIT is caused by shadow
4521 * page protected, we can zap the shadow page and retry this
4522 * instruction directly.
4523 *
4524 * Note: if the guest uses a non-page-table modifying instruction
4525 * on the PDE that points to the instruction, then we will unmap
4526 * the instruction and go to an infinite loop. So, we cache the
4527 * last retried eip and the last fault address, if we meet the eip
4528 * and the address again, we can break out of the potential infinite
4529 * loop.
4530 */
4531 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4532
4533 if (!(emulation_type & EMULTYPE_RETRY))
4534 return false;
4535
4536 if (x86_page_table_writing_insn(ctxt))
4537 return false;
4538
4539 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4540 return false;
4541
4542 vcpu->arch.last_retry_eip = ctxt->eip;
4543 vcpu->arch.last_retry_addr = cr2;
4544
4545 if (!vcpu->arch.mmu.direct_map)
4546 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4547
4548 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4549
4550 return true;
4551}
4552
51d8b661
AP		 4553int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4554 unsigned long cr2,
dc25e89e
AP		 4555 int emulation_type,
4556 void *insn,
4557 int insn_len)
bbd9b64e 4558{
95cb2295 4559 int r;
9d74191a 4560 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4561 bool writeback = true;
bbd9b64e 4562
26eef70c 4563 kvm_clear_exception_queue(vcpu);
8d7d8102 4564
571008da 4565 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4566 init_emulate_ctxt(vcpu);
9d74191a
TY		 4567 ctxt->interruptibility = 0;
4568 ctxt->have_exception = false;
4569 ctxt->perm_ok = false;
bbd9b64e 4570
9d74191a 4571 ctxt->only_vendor_specific_insn
4005996e
AK		 4572 = emulation_type & EMULTYPE_TRAP_UD;
4573
9d74191a 4574 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4575
e46479f8 4576 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4577 ++vcpu->stat.insn_emulation;
1d2887e2 4578 if (r != EMULATION_OK) {
4005996e
AK		 4579 if (emulation_type & EMULTYPE_TRAP_UD)
4580 return EMULATE_FAIL;
a6f177ef 4581 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4582 return EMULATE_DONE;
6d77dbfc
GN		 4583 if (emulation_type & EMULTYPE_SKIP)
4584 return EMULATE_FAIL;
4585 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4586 }
4587 }
4588
ba8afb6b 4589 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4590 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4591 return EMULATE_DONE;
4592 }
4593
1cb3f3ae
XG		 4594 if (retry_instruction(ctxt, cr2, emulation_type))
4595 return EMULATE_DONE;
4596
7ae441ea 4597 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4598 changes registers values during IO operation */
7ae441ea
GN		 4599 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4600 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4601 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4602 }
4d2179e1 4603
5cd21917 4604restart:
9d74191a 4605 r = x86_emulate_insn(ctxt);
bbd9b64e 4606
775fde86
JR		 4607 if (r == EMULATION_INTERCEPTED)
4608 return EMULATE_DONE;
4609
d2ddd1c4 4610 if (r == EMULATION_FAILED) {
a6f177ef 4611 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4612 return EMULATE_DONE;
4613
6d77dbfc 4614 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4615 }
4616
9d74191a 4617 if (ctxt->have_exception) {
54b8486f 4618 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4619 r = EMULATE_DONE;
4620 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4621 if (!vcpu->arch.pio.in)
4622 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4623 else
4624 writeback = false;
e85d28f8 4625 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4626 } else if (vcpu->mmio_needed) {
4627 if (!vcpu->mmio_is_write)
4628 writeback = false;
e85d28f8 4629 r = EMULATE_DO_MMIO;
7ae441ea 4630 } else if (r == EMULATION_RESTART)
5cd21917 4631 goto restart;
d2ddd1c4
GN		 4632 else
4633 r = EMULATE_DONE;
f850e2e6 4634
7ae441ea 4635 if (writeback) {
9d74191a
TY		 4636 toggle_interruptibility(vcpu, ctxt->interruptibility);
4637 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4638 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4639 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4640 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4641 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4642 } else
4643 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4644
4645 return r;
de7d789a 4646}
51d8b661 4647EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4648
cf8f70bf 4649int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4650{
cf8f70bf 4651 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4652 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4653 size, port, &val, 1);
cf8f70bf 4654 /* do not return to emulator after return from userspace */
7972995b 4655 vcpu->arch.pio.count = 0;
de7d789a
CO		 4656 return ret;
4657}
cf8f70bf 4658EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4659
8cfdc000
ZA		 4660static void tsc_bad(void *info)
4661{
0a3aee0d 4662 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4663}
4664
4665static void tsc_khz_changed(void *data)
c8076604 4666{
8cfdc000
ZA		 4667 struct cpufreq_freqs *freq = data;
4668 unsigned long khz = 0;
4669
4670 if (data)
4671 khz = freq->new;
4672 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4673 khz = cpufreq_quick_get(raw_smp_processor_id());
4674 if (!khz)
4675 khz = tsc_khz;
0a3aee0d 4676 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4677}
4678
c8076604
GH		 4679static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4680 void *data)
4681{
4682 struct cpufreq_freqs *freq = data;
4683 struct kvm *kvm;
4684 struct kvm_vcpu *vcpu;
4685 int i, send_ipi = 0;
4686
8cfdc000
ZA		 4687 /*
4688 * We allow guests to temporarily run on slowing clocks,
4689 * provided we notify them after, or to run on accelerating
4690 * clocks, provided we notify them before. Thus time never
4691 * goes backwards.
4692 *
4693 * However, we have a problem. We can't atomically update
4694 * the frequency of a given CPU from this function; it is
4695 * merely a notifier, which can be called from any CPU.
4696 * Changing the TSC frequency at arbitrary points in time
4697 * requires a recomputation of local variables related to
4698 * the TSC for each VCPU. We must flag these local variables
4699 * to be updated and be sure the update takes place with the
4700 * new frequency before any guests proceed.
4701 *
4702 * Unfortunately, the combination of hotplug CPU and frequency
4703 * change creates an intractable locking scenario; the order
4704 * of when these callouts happen is undefined with respect to
4705 * CPU hotplug, and they can race with each other. As such,
4706 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4707 * undefined; you can actually have a CPU frequency change take
4708 * place in between the computation of X and the setting of the
4709 * variable. To protect against this problem, all updates of
4710 * the per_cpu tsc_khz variable are done in an interrupt
4711 * protected IPI, and all callers wishing to update the value
4712 * must wait for a synchronous IPI to complete (which is trivial
4713 * if the caller is on the CPU already). This establishes the
4714 * necessary total order on variable updates.
4715 *
4716 * Note that because a guest time update may take place
4717 * anytime after the setting of the VCPU's request bit, the
4718 * correct TSC value must be set before the request. However,
4719 * to ensure the update actually makes it to any guest which
4720 * starts running in hardware virtualization between the set
4721 * and the acquisition of the spinlock, we must also ping the
4722 * CPU after setting the request bit.
4723 *
4724 */
4725
c8076604
GH		 4726 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4727 return 0;
4728 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4729 return 0;
8cfdc000
ZA		 4730
4731 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4732
e935b837 4733 raw_spin_lock(&kvm_lock);
c8076604 4734 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4735 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4736 if (vcpu->cpu != freq->cpu)
4737 continue;
c285545f 4738 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4739 if (vcpu->cpu != smp_processor_id())
8cfdc000 4740 send_ipi = 1;
c8076604
GH		 4741 }
4742 }
e935b837 4743 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4744
4745 if (freq->old < freq->new && send_ipi) {
4746 /*
4747 * We upscale the frequency. Must make the guest
4748 * doesn't see old kvmclock values while running with
4749 * the new frequency, otherwise we risk the guest sees
4750 * time go backwards.
4751 *
4752 * In case we update the frequency for another cpu
4753 * (which might be in guest context) send an interrupt
4754 * to kick the cpu out of guest context. Next time
4755 * guest context is entered kvmclock will be updated,
4756 * so the guest will not see stale values.
4757 */
8cfdc000 4758 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4759 }
4760 return 0;
4761}
4762
4763static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4764 .notifier_call = kvmclock_cpufreq_notifier
4765};
4766
4767static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4768 unsigned long action, void *hcpu)
4769{
4770 unsigned int cpu = (unsigned long)hcpu;
4771
4772 switch (action) {
4773 case CPU_ONLINE:
4774 case CPU_DOWN_FAILED:
4775 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4776 break;
4777 case CPU_DOWN_PREPARE:
4778 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4779 break;
4780 }
4781 return NOTIFY_OK;
4782}
4783
4784static struct notifier_block kvmclock_cpu_notifier_block = {
4785 .notifier_call = kvmclock_cpu_notifier,
4786 .priority = -INT_MAX
c8076604
GH		 4787};
4788
b820cc0c
ZA		 4789static void kvm_timer_init(void)
4790{
4791 int cpu;
4792
c285545f 4793 max_tsc_khz = tsc_khz;
8cfdc000 4794 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4795 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4796#ifdef CONFIG_CPU_FREQ
4797 struct cpufreq_policy policy;
4798 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4799 cpu = get_cpu();
4800 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4801 if (policy.cpuinfo.max_freq)
4802 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4803 put_cpu();
c285545f 4804#endif
b820cc0c
ZA		 4805 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4806 CPUFREQ_TRANSITION_NOTIFIER);
4807 }
c285545f 4808 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4809 for_each_online_cpu(cpu)
4810 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4811}
4812
ff9d07a0
ZY		 4813static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4814
f5132b01 4815int kvm_is_in_guest(void)
ff9d07a0 4816{
086c9855 4817 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4818}
4819
4820static int kvm_is_user_mode(void)
4821{
4822 int user_mode = 3;
dcf46b94 4823
086c9855
AS		 4824 if (__this_cpu_read(current_vcpu))
4825 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4826
ff9d07a0
ZY		 4827 return user_mode != 0;
4828}
4829
4830static unsigned long kvm_get_guest_ip(void)
4831{
4832 unsigned long ip = 0;
dcf46b94 4833
086c9855
AS		 4834 if (__this_cpu_read(current_vcpu))
4835 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4836
ff9d07a0
ZY		 4837 return ip;
4838}
4839
4840static struct perf_guest_info_callbacks kvm_guest_cbs = {
4841 .is_in_guest = kvm_is_in_guest,
4842 .is_user_mode = kvm_is_user_mode,
4843 .get_guest_ip = kvm_get_guest_ip,
4844};
4845
4846void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4847{
086c9855 4848 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4849}
4850EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4851
4852void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4853{
086c9855 4854 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4855}
4856EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4857
ce88decf
XG		 4858static void kvm_set_mmio_spte_mask(void)
4859{
4860 u64 mask;
4861 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4862
4863 /*
4864 * Set the reserved bits and the present bit of an paging-structure
4865 * entry to generate page fault with PFER.RSV = 1.
4866 */
4867 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4868 mask |= 1ull;
4869
4870#ifdef CONFIG_X86_64
4871 /*
4872 * If reserved bit is not supported, clear the present bit to disable
4873 * mmio page fault.
4874 */
4875 if (maxphyaddr == 52)
4876 mask &= ~1ull;
4877#endif
4878
4879 kvm_mmu_set_mmio_spte_mask(mask);
4880}
4881
f8c16bba 4882int kvm_arch_init(void *opaque)
043405e1 4883{
b820cc0c 4884 int r;
f8c16bba
ZX		 4885 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4886
f8c16bba
ZX		 4887 if (kvm_x86_ops) {
4888 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4889 r = -EEXIST;
4890 goto out;
f8c16bba
ZX		 4891 }
4892
4893 if (!ops->cpu_has_kvm_support()) {
4894 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4895 r = -EOPNOTSUPP;
4896 goto out;
f8c16bba
ZX		 4897 }
4898 if (ops->disabled_by_bios()) {
4899 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4900 r = -EOPNOTSUPP;
4901 goto out;
f8c16bba
ZX		 4902 }
4903
97db56ce
AK		 4904 r = kvm_mmu_module_init();
4905 if (r)
4906 goto out;
4907
ce88decf 4908 kvm_set_mmio_spte_mask();
97db56ce
AK		 4909 kvm_init_msr_list();
4910
f8c16bba 4911 kvm_x86_ops = ops;
7b52345e 4912 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4913 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4914
b820cc0c 4915 kvm_timer_init();
c8076604 4916
ff9d07a0
ZY		 4917 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4918
2acf923e
DC		 4919 if (cpu_has_xsave)
4920 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4921
c5cc421b 4922 kvm_lapic_init();
f8c16bba 4923 return 0;
56c6d28a
ZX		 4924
4925out:
56c6d28a 4926 return r;
043405e1 4927}
8776e519 4928
f8c16bba
ZX		 4929void kvm_arch_exit(void)
4930{
ff9d07a0
ZY		 4931 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4932
888d256e
JK		 4933 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4934 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4935 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4936 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4937 kvm_x86_ops = NULL;
56c6d28a
ZX		 4938 kvm_mmu_module_exit();
4939}
f8c16bba 4940
8776e519
HB		 4941int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4942{
4943 ++vcpu->stat.halt_exits;
4944 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4945 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4946 return 1;
4947 } else {
4948 vcpu->run->exit_reason = KVM_EXIT_HLT;
4949 return 0;
4950 }
4951}
4952EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4953
55cd8e5a
GN		 4954int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4955{
4956 u64 param, ingpa, outgpa, ret;
4957 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4958 bool fast, longmode;
4959 int cs_db, cs_l;
4960
4961 /*
4962 * hypercall generates UD from non zero cpl and real mode
4963 * per HYPER-V spec
4964 */
3eeb3288 4965 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4966 kvm_queue_exception(vcpu, UD_VECTOR);
4967 return 0;
4968 }
4969
4970 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4971 longmode = is_long_mode(vcpu) && cs_l == 1;
4972
4973 if (!longmode) {
ccd46936
GN		 4974 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4975 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4976 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4977 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4978 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4979 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4980 }
4981#ifdef CONFIG_X86_64
4982 else {
4983 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4984 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4985 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4986 }
4987#endif
4988
4989 code = param & 0xffff;
4990 fast = (param >> 16) & 0x1;
4991 rep_cnt = (param >> 32) & 0xfff;
4992 rep_idx = (param >> 48) & 0xfff;
4993
4994 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4995
c25bc163
GN		 4996 switch (code) {
4997 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4998 kvm_vcpu_on_spin(vcpu);
4999 break;
5000 default:
5001 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5002 break;
5003 }
55cd8e5a
GN		 5004
5005 ret = res | (((u64)rep_done & 0xfff) << 32);
5006 if (longmode) {
5007 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5008 } else {
5009 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5010 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5011 }
5012
5013 return 1;
5014}
5015
8776e519
HB		 5016int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5017{
5018 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5019 int r = 1;
8776e519 5020
55cd8e5a
GN		 5021 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5022 return kvm_hv_hypercall(vcpu);
5023
5fdbf976
MT		 5024 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5025 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5026 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5027 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5028 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5029
229456fc 5030 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5031
8776e519
HB		 5032 if (!is_long_mode(vcpu)) {
5033 nr &= 0xFFFFFFFF;
5034 a0 &= 0xFFFFFFFF;
5035 a1 &= 0xFFFFFFFF;
5036 a2 &= 0xFFFFFFFF;
5037 a3 &= 0xFFFFFFFF;
5038 }
5039
07708c4a
JK		 5040 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5041 ret = -KVM_EPERM;
5042 goto out;
5043 }
5044
8776e519 5045 switch (nr) {
b93463aa
AK		 5046 case KVM_HC_VAPIC_POLL_IRQ:
5047 ret = 0;
5048 break;
8776e519
HB		 5049 default:
5050 ret = -KVM_ENOSYS;
5051 break;
5052 }
07708c4a 5053out:
5fdbf976 5054 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5055 ++vcpu->stat.hypercalls;
2f333bcb 5056 return r;
8776e519
HB		 5057}
5058EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5059
d6aa1000 5060int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5061{
d6aa1000 5062 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5063 char instruction[3];
5fdbf976 5064 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5065
8776e519
HB		 5066 /*
5067 * Blow out the MMU to ensure that no other VCPU has an active mapping
5068 * to ensure that the updated hypercall appears atomically across all
5069 * VCPUs.
5070 */
5071 kvm_mmu_zap_all(vcpu->kvm);
5072
8776e519 5073 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5074
9d74191a 5075 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5076}
5077
b6c7a5dc
HB		 5078/*
5079 * Check if userspace requested an interrupt window, and that the
5080 * interrupt window is open.
5081 *
5082 * No need to exit to userspace if we already have an interrupt queued.
5083 */
851ba692 5084static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5085{
8061823a 5086 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5087 vcpu->run->request_interrupt_window &&
5df56646 5088 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5089}
5090
851ba692 5091static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5092{
851ba692
AK		 5093 struct kvm_run *kvm_run = vcpu->run;
5094
91586a3b 5095 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5096 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5097 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5098 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5099 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5100 else
b6c7a5dc 5101 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5102 kvm_arch_interrupt_allowed(vcpu) &&
5103 !kvm_cpu_has_interrupt(vcpu) &&
5104 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5105}
5106
b93463aa
AK		 5107static void vapic_enter(struct kvm_vcpu *vcpu)
5108{
5109 struct kvm_lapic *apic = vcpu->arch.apic;
5110 struct page *page;
5111
5112 if (!apic || !apic->vapic_addr)
5113 return;
5114
5115 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5116
5117 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5118}
5119
5120static void vapic_exit(struct kvm_vcpu *vcpu)
5121{
5122 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5123 int idx;
b93463aa
AK		 5124
5125 if (!apic || !apic->vapic_addr)
5126 return;
5127
f656ce01 5128 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5129 kvm_release_page_dirty(apic->vapic_page);
5130 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5131 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5132}
5133
95ba8273
GN		 5134static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5135{
5136 int max_irr, tpr;
5137
5138 if (!kvm_x86_ops->update_cr8_intercept)
5139 return;
5140
88c808fd
AK		 5141 if (!vcpu->arch.apic)
5142 return;
5143
8db3baa2
GN		 5144 if (!vcpu->arch.apic->vapic_addr)
5145 max_irr = kvm_lapic_find_highest_irr(vcpu);
5146 else
5147 max_irr = -1;
95ba8273
GN		 5148
5149 if (max_irr != -1)
5150 max_irr >>= 4;
5151
5152 tpr = kvm_lapic_get_cr8(vcpu);
5153
5154 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5155}
5156
851ba692 5157static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5158{
5159 /* try to reinject previous events if any */
b59bb7bd 5160 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5161 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5162 vcpu->arch.exception.has_error_code,
5163 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5164 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5165 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5166 vcpu->arch.exception.error_code,
5167 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5168 return;
5169 }
5170
95ba8273
GN		 5171 if (vcpu->arch.nmi_injected) {
5172 kvm_x86_ops->set_nmi(vcpu);
5173 return;
5174 }
5175
5176 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5177 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5178 return;
5179 }
5180
5181 /* try to inject new event if pending */
5182 if (vcpu->arch.nmi_pending) {
5183 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5184 --vcpu->arch.nmi_pending;
95ba8273
GN		 5185 vcpu->arch.nmi_injected = true;
5186 kvm_x86_ops->set_nmi(vcpu);
5187 }
5188 } else if (kvm_cpu_has_interrupt(vcpu)) {
5189 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5190 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5191 false);
5192 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5193 }
5194 }
5195}
5196
2acf923e
DC		 5197static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5198{
5199 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5200 !vcpu->guest_xcr0_loaded) {
5201 /* kvm_set_xcr() also depends on this */
5202 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5203 vcpu->guest_xcr0_loaded = 1;
5204 }
5205}
5206
5207static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5208{
5209 if (vcpu->guest_xcr0_loaded) {
5210 if (vcpu->arch.xcr0 != host_xcr0)
5211 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5212 vcpu->guest_xcr0_loaded = 0;
5213 }
5214}
5215
7460fb4a
AK		 5216static void process_nmi(struct kvm_vcpu *vcpu)
5217{
5218 unsigned limit = 2;
5219
5220 /*
5221 * x86 is limited to one NMI running, and one NMI pending after it.
5222 * If an NMI is already in progress, limit further NMIs to just one.
5223 * Otherwise, allow two (and we'll inject the first one immediately).
5224 */
5225 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5226 limit = 1;
5227
5228 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5229 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5230 kvm_make_request(KVM_REQ_EVENT, vcpu);
5231}
5232
851ba692 5233static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5234{
5235 int r;
6a8b1d13 5236 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5237 vcpu->run->request_interrupt_window;
d6185f20 5238 bool req_immediate_exit = 0;
b6c7a5dc 5239
3e007509 5240 if (vcpu->requests) {
a8eeb04a 5241 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5242 kvm_mmu_unload(vcpu);
a8eeb04a 5243 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5244 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5245 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5246 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5247 if (unlikely(r))
5248 goto out;
5249 }
a8eeb04a 5250 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5251 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5252 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5253 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5254 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5255 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5256 r = 0;
5257 goto out;
5258 }
a8eeb04a 5259 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5260 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5261 r = 0;
5262 goto out;
5263 }
a8eeb04a 5264 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5265 vcpu->fpu_active = 0;
5266 kvm_x86_ops->fpu_deactivate(vcpu);
5267 }
af585b92
GN		 5268 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5269 /* Page is swapped out. Do synthetic halt */
5270 vcpu->arch.apf.halted = true;
5271 r = 1;
5272 goto out;
5273 }
c9aaa895
GC		 5274 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5275 record_steal_time(vcpu);
7460fb4a
AK		 5276 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5277 process_nmi(vcpu);
d6185f20
NHE		 5278 req_immediate_exit =
5279 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5280 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5281 kvm_handle_pmu_event(vcpu);
5282 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5283 kvm_deliver_pmi(vcpu);
2f52d58c 5284 }
b93463aa 5285
b463a6f7
AK		 5286 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5287 inject_pending_event(vcpu);
5288
5289 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5290 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5291 kvm_x86_ops->enable_nmi_window(vcpu);
5292 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5293 kvm_x86_ops->enable_irq_window(vcpu);
5294
5295 if (kvm_lapic_enabled(vcpu)) {
5296 update_cr8_intercept(vcpu);
5297 kvm_lapic_sync_to_vapic(vcpu);
5298 }
5299 }
5300
d8368af8
AK		 5301 r = kvm_mmu_reload(vcpu);
5302 if (unlikely(r)) {
d905c069 5303 goto cancel_injection;
d8368af8
AK		 5304 }
5305
b6c7a5dc
HB		 5306 preempt_disable();
5307
5308 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5309 if (vcpu->fpu_active)
5310 kvm_load_guest_fpu(vcpu);
2acf923e 5311 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5312
6b7e2d09
XG		 5313 vcpu->mode = IN_GUEST_MODE;
5314
5315 /* We should set ->mode before check ->requests,
5316 * see the comment in make_all_cpus_request.
5317 */
5318 smp_mb();
b6c7a5dc 5319
d94e1dc9 5320 local_irq_disable();
32f88400 5321
6b7e2d09 5322 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5323 || need_resched() || signal_pending(current)) {
6b7e2d09 5324 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5325 smp_wmb();
6c142801
AK		 5326 local_irq_enable();
5327 preempt_enable();
5328 r = 1;
d905c069 5329 goto cancel_injection;
6c142801
AK		 5330 }
5331
f656ce01 5332 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5333
d6185f20
NHE		 5334 if (req_immediate_exit)
5335 smp_send_reschedule(vcpu->cpu);
5336
b6c7a5dc
HB		 5337 kvm_guest_enter();
5338
42dbaa5a 5339 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5340 set_debugreg(0, 7);
5341 set_debugreg(vcpu->arch.eff_db[0], 0);
5342 set_debugreg(vcpu->arch.eff_db[1], 1);
5343 set_debugreg(vcpu->arch.eff_db[2], 2);
5344 set_debugreg(vcpu->arch.eff_db[3], 3);
5345 }
b6c7a5dc 5346
229456fc 5347 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5348 kvm_x86_ops->run(vcpu);
b6c7a5dc 5349
24f1e32c
FW		 5350 /*
5351 * If the guest has used debug registers, at least dr7
5352 * will be disabled while returning to the host.
5353 * If we don't have active breakpoints in the host, we don't
5354 * care about the messed up debug address registers. But if
5355 * we have some of them active, restore the old state.
5356 */
59d8eb53 5357 if (hw_breakpoint_active())
24f1e32c 5358 hw_breakpoint_restore();
42dbaa5a 5359
d5c1785d 5360 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5361
6b7e2d09 5362 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5363 smp_wmb();
b6c7a5dc
HB		 5364 local_irq_enable();
5365
5366 ++vcpu->stat.exits;
5367
5368 /*
5369 * We must have an instruction between local_irq_enable() and
5370 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5371 * the interrupt shadow. The stat.exits increment will do nicely.
5372 * But we need to prevent reordering, hence this barrier():
5373 */
5374 barrier();
5375
5376 kvm_guest_exit();
5377
5378 preempt_enable();
5379
f656ce01 5380 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5381
b6c7a5dc
HB		 5382 /*
5383 * Profile KVM exit RIPs:
5384 */
5385 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5386 unsigned long rip = kvm_rip_read(vcpu);
5387 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5388 }
5389
cc578287
ZA		 5390 if (unlikely(vcpu->arch.tsc_always_catchup))
5391 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5392
5cfb1d5a
MT		 5393 if (vcpu->arch.apic_attention)
5394 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5395
851ba692 5396 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5397 return r;
5398
5399cancel_injection:
5400 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5401 if (unlikely(vcpu->arch.apic_attention))
5402 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5403out:
5404 return r;
5405}
b6c7a5dc 5406
09cec754 5407
851ba692 5408static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5409{
5410 int r;
f656ce01 5411 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5412
5413 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5414 pr_debug("vcpu %d received sipi with vector # %x\n",
5415 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5416 kvm_lapic_reset(vcpu);
5f179287 5417 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5418 if (r)
5419 return r;
5420 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5421 }
5422
f656ce01 5423 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5424 vapic_enter(vcpu);
5425
5426 r = 1;
5427 while (r > 0) {
af585b92
GN		 5428 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5429 !vcpu->arch.apf.halted)
851ba692 5430 r = vcpu_enter_guest(vcpu);
d7690175 5431 else {
f656ce01 5432 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5433 kvm_vcpu_block(vcpu);
f656ce01 5434 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5435 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5436 {
5437 switch(vcpu->arch.mp_state) {
5438 case KVM_MP_STATE_HALTED:
d7690175 5439 vcpu->arch.mp_state =
09cec754
GN		 5440 KVM_MP_STATE_RUNNABLE;
5441 case KVM_MP_STATE_RUNNABLE:
af585b92 5442 vcpu->arch.apf.halted = false;
09cec754
GN		 5443 break;
5444 case KVM_MP_STATE_SIPI_RECEIVED:
5445 default:
5446 r = -EINTR;
5447 break;
5448 }
5449 }
d7690175
MT		 5450 }
5451
09cec754
GN		 5452 if (r <= 0)
5453 break;
5454
5455 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5456 if (kvm_cpu_has_pending_timer(vcpu))
5457 kvm_inject_pending_timer_irqs(vcpu);
5458
851ba692 5459 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5460 r = -EINTR;
851ba692 5461 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5462 ++vcpu->stat.request_irq_exits;
5463 }
af585b92
GN		 5464
5465 kvm_check_async_pf_completion(vcpu);
5466
09cec754
GN		 5467 if (signal_pending(current)) {
5468 r = -EINTR;
851ba692 5469 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5470 ++vcpu->stat.signal_exits;
5471 }
5472 if (need_resched()) {
f656ce01 5473 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5474 kvm_resched(vcpu);
f656ce01 5475 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5476 }
b6c7a5dc
HB		 5477 }
5478
f656ce01 5479 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5480
b93463aa
AK		 5481 vapic_exit(vcpu);
5482
b6c7a5dc
HB		 5483 return r;
5484}
5485
f78146b0
AK		 5486/*
5487 * Implements the following, as a state machine:
5488 *
5489 * read:
5490 * for each fragment
5491 * write gpa, len
5492 * exit
5493 * copy data
5494 * execute insn
5495 *
5496 * write:
5497 * for each fragment
5498 * write gpa, len
5499 * copy data
5500 * exit
5501 */
5287f194
AK		 5502static int complete_mmio(struct kvm_vcpu *vcpu)
5503{
5504 struct kvm_run *run = vcpu->run;
f78146b0 5505 struct kvm_mmio_fragment *frag;
5287f194
AK		 5506 int r;
5507
5508 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5509 return 1;
5510
5511 if (vcpu->mmio_needed) {
f78146b0
AK		 5512 /* Complete previous fragment */
5513 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
cef4dea0 5514 if (!vcpu->mmio_is_write)
f78146b0
AK		 5515 memcpy(frag->data, run->mmio.data, frag->len);
5516 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5517 vcpu->mmio_needed = 0;
5518 if (vcpu->mmio_is_write)
5519 return 1;
5520 vcpu->mmio_read_completed = 1;
5521 goto done;
cef4dea0 5522 }
f78146b0
AK		 5523 /* Initiate next fragment */
5524 ++frag;
5525 run->exit_reason = KVM_EXIT_MMIO;
5526 run->mmio.phys_addr = frag->gpa;
cef4dea0 5527 if (vcpu->mmio_is_write)
f78146b0
AK		 5528 memcpy(run->mmio.data, frag->data, frag->len);
5529 run->mmio.len = frag->len;
5530 run->mmio.is_write = vcpu->mmio_is_write;
5531 return 0;
5532
5287f194 5533 }
f78146b0 5534done:
5287f194
AK		 5535 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5536 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5537 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5538 if (r != EMULATE_DONE)
5539 return 0;
5540 return 1;
5541}
5542
b6c7a5dc
HB		 5543int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5544{
5545 int r;
5546 sigset_t sigsaved;
5547
e5c30142
AK		 5548 if (!tsk_used_math(current) && init_fpu(current))
5549 return -ENOMEM;
5550
ac9f6dc0
AK		 5551 if (vcpu->sigset_active)
5552 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5553
a4535290 5554 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5555 kvm_vcpu_block(vcpu);
d7690175 5556 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5557 r = -EAGAIN;
5558 goto out;
b6c7a5dc
HB		 5559 }
5560
b6c7a5dc 5561 /* re-sync apic's tpr */
eea1cff9
AP		 5562 if (!irqchip_in_kernel(vcpu->kvm)) {
5563 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5564 r = -EINVAL;
5565 goto out;
5566 }
5567 }
b6c7a5dc 5568
5287f194
AK		 5569 r = complete_mmio(vcpu);
5570 if (r <= 0)
5571 goto out;
5572
851ba692 5573 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5574
5575out:
f1d86e46 5576 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5577 if (vcpu->sigset_active)
5578 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5579
b6c7a5dc
HB		 5580 return r;
5581}
5582
5583int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5584{
7ae441ea
GN		 5585 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5586 /*
5587 * We are here if userspace calls get_regs() in the middle of
5588 * instruction emulation. Registers state needs to be copied
4a969980 5589 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5590 * that usually, but some bad designed PV devices (vmware
5591 * backdoor interface) need this to work
5592 */
9dac77fa
AK		 5593 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5594 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5595 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5596 }
5fdbf976
MT		 5597 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5598 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5599 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5600 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5601 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5602 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5603 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5604 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5605#ifdef CONFIG_X86_64
5fdbf976
MT		 5606 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5607 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5608 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5609 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5610 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5611 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5612 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5613 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5614#endif
5615
5fdbf976 5616 regs->rip = kvm_rip_read(vcpu);
91586a3b 5617 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5618
b6c7a5dc
HB		 5619 return 0;
5620}
5621
5622int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5623{
7ae441ea
GN		 5624 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5625 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5626
5fdbf976
MT		 5627 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5628 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5629 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5630 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5631 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5632 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5633 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5634 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5635#ifdef CONFIG_X86_64
5fdbf976
MT		 5636 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5637 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5638 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5639 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5640 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5641 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5642 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5643 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5644#endif
5645
5fdbf976 5646 kvm_rip_write(vcpu, regs->rip);
91586a3b 5647 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5648
b4f14abd
JK		 5649 vcpu->arch.exception.pending = false;
5650
3842d135
AK		 5651 kvm_make_request(KVM_REQ_EVENT, vcpu);
5652
b6c7a5dc
HB		 5653 return 0;
5654}
5655
b6c7a5dc
HB		 5656void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5657{
5658 struct kvm_segment cs;
5659
3e6e0aab 5660 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5661 *db = cs.db;
5662 *l = cs.l;
5663}
5664EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5665
5666int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5667 struct kvm_sregs *sregs)
5668{
89a27f4d 5669 struct desc_ptr dt;
b6c7a5dc 5670
3e6e0aab
GT		 5671 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5672 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5673 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5674 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5675 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5676 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5677
3e6e0aab
GT		 5678 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5679 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5680
5681 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5682 sregs->idt.limit = dt.size;
5683 sregs->idt.base = dt.address;
b6c7a5dc 5684 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5685 sregs->gdt.limit = dt.size;
5686 sregs->gdt.base = dt.address;
b6c7a5dc 5687
4d4ec087 5688 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5689 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5690 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5691 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5692 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5693 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5694 sregs->apic_base = kvm_get_apic_base(vcpu);
5695
923c61bb 5696 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5697
36752c9b 5698 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5699 set_bit(vcpu->arch.interrupt.nr,
5700 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5701
b6c7a5dc
HB		 5702 return 0;
5703}
5704
62d9f0db
MT		 5705int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5706 struct kvm_mp_state *mp_state)
5707{
62d9f0db 5708 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5709 return 0;
5710}
5711
5712int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5713 struct kvm_mp_state *mp_state)
5714{
62d9f0db 5715 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5716 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5717 return 0;
5718}
5719
7f3d35fd
KW		 5720int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5721 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5722{
9d74191a 5723 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5724 int ret;
e01c2426 5725
8ec4722d 5726 init_emulate_ctxt(vcpu);
c697518a 5727
7f3d35fd 5728 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5729 has_error_code, error_code);
c697518a 5730
c697518a 5731 if (ret)
19d04437 5732 return EMULATE_FAIL;
37817f29 5733
9dac77fa 5734 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5735 kvm_rip_write(vcpu, ctxt->eip);
5736 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5737 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5738 return EMULATE_DONE;
37817f29
IE		 5739}
5740EXPORT_SYMBOL_GPL(kvm_task_switch);
5741
b6c7a5dc
HB		 5742int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5743 struct kvm_sregs *sregs)
5744{
5745 int mmu_reset_needed = 0;
63f42e02 5746 int pending_vec, max_bits, idx;
89a27f4d 5747 struct desc_ptr dt;
b6c7a5dc 5748
89a27f4d
GN		 5749 dt.size = sregs->idt.limit;
5750 dt.address = sregs->idt.base;
b6c7a5dc 5751 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5752 dt.size = sregs->gdt.limit;
5753 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5754 kvm_x86_ops->set_gdt(vcpu, &dt);
5755
ad312c7c 5756 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5757 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5758 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5759 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5760
2d3ad1f4 5761 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5762
f6801dff 5763 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5764 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5765 kvm_set_apic_base(vcpu, sregs->apic_base);
5766
4d4ec087 5767 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5768 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5769 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5770
fc78f519 5771 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5772 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5773 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5774 kvm_update_cpuid(vcpu);
63f42e02
XG		 5775
5776 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5777 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5778 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5779 mmu_reset_needed = 1;
5780 }
63f42e02 5781 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5782
5783 if (mmu_reset_needed)
5784 kvm_mmu_reset_context(vcpu);
5785
923c61bb
GN		 5786 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5787 pending_vec = find_first_bit(
5788 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5789 if (pending_vec < max_bits) {
66fd3f7f 5790 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5791 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5792 }
5793
3e6e0aab
GT		 5794 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5795 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5796 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5797 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5798 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5799 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5800
3e6e0aab
GT		 5801 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5802 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5803
5f0269f5
ME		 5804 update_cr8_intercept(vcpu);
5805
9c3e4aab 5806 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5807 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5808 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5809 !is_protmode(vcpu))
9c3e4aab
MT		 5810 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5811
3842d135
AK		 5812 kvm_make_request(KVM_REQ_EVENT, vcpu);
5813
b6c7a5dc
HB		 5814 return 0;
5815}
5816
d0bfb940
JK		 5817int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5818 struct kvm_guest_debug *dbg)
b6c7a5dc 5819{
355be0b9 5820 unsigned long rflags;
ae675ef0 5821 int i, r;
b6c7a5dc 5822
4f926bf2
JK		 5823 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5824 r = -EBUSY;
5825 if (vcpu->arch.exception.pending)
2122ff5e 5826 goto out;
4f926bf2
JK		 5827 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5828 kvm_queue_exception(vcpu, DB_VECTOR);
5829 else
5830 kvm_queue_exception(vcpu, BP_VECTOR);
5831 }
5832
91586a3b
JK		 5833 /*
5834 * Read rflags as long as potentially injected trace flags are still
5835 * filtered out.
5836 */
5837 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5838
5839 vcpu->guest_debug = dbg->control;
5840 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5841 vcpu->guest_debug = 0;
5842
5843 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5844 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5845 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5846 vcpu->arch.switch_db_regs =
5847 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5848 } else {
5849 for (i = 0; i < KVM_NR_DB_REGS; i++)
5850 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5851 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5852 }
5853
f92653ee
JK		 5854 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5855 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5856 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5857
91586a3b
JK		 5858 /*
5859 * Trigger an rflags update that will inject or remove the trace
5860 * flags.
5861 */
5862 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5863
355be0b9 5864 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5865
4f926bf2 5866 r = 0;
d0bfb940 5867
2122ff5e 5868out:
b6c7a5dc
HB		 5869
5870 return r;
5871}
5872
8b006791
ZX		 5873/*
5874 * Translate a guest virtual address to a guest physical address.
5875 */
5876int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5877 struct kvm_translation *tr)
5878{
5879 unsigned long vaddr = tr->linear_address;
5880 gpa_t gpa;
f656ce01 5881 int idx;
8b006791 5882
f656ce01 5883 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5884 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5885 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5886 tr->physical_address = gpa;
5887 tr->valid = gpa != UNMAPPED_GVA;
5888 tr->writeable = 1;
5889 tr->usermode = 0;
8b006791
ZX		 5890
5891 return 0;
5892}
5893
d0752060
HB		 5894int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5895{
98918833
SY		 5896 struct i387_fxsave_struct *fxsave =
5897 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5898
d0752060
HB		 5899 memcpy(fpu->fpr, fxsave->st_space, 128);
5900 fpu->fcw = fxsave->cwd;
5901 fpu->fsw = fxsave->swd;
5902 fpu->ftwx = fxsave->twd;
5903 fpu->last_opcode = fxsave->fop;
5904 fpu->last_ip = fxsave->rip;
5905 fpu->last_dp = fxsave->rdp;
5906 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5907
d0752060
HB		 5908 return 0;
5909}
5910
5911int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5912{
98918833
SY		 5913 struct i387_fxsave_struct *fxsave =
5914 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5915
d0752060
HB		 5916 memcpy(fxsave->st_space, fpu->fpr, 128);
5917 fxsave->cwd = fpu->fcw;
5918 fxsave->swd = fpu->fsw;
5919 fxsave->twd = fpu->ftwx;
5920 fxsave->fop = fpu->last_opcode;
5921 fxsave->rip = fpu->last_ip;
5922 fxsave->rdp = fpu->last_dp;
5923 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5924
d0752060
HB		 5925 return 0;
5926}
5927
10ab25cd 5928int fx_init(struct kvm_vcpu *vcpu)
d0752060 5929{
10ab25cd
JK		 5930 int err;
5931
5932 err = fpu_alloc(&vcpu->arch.guest_fpu);
5933 if (err)
5934 return err;
5935
98918833 5936 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5937
2acf923e
DC		 5938 /*
5939 * Ensure guest xcr0 is valid for loading
5940 */
5941 vcpu->arch.xcr0 = XSTATE_FP;
5942
ad312c7c 5943 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5944
5945 return 0;
d0752060
HB		 5946}
5947EXPORT_SYMBOL_GPL(fx_init);
5948
98918833
SY		 5949static void fx_free(struct kvm_vcpu *vcpu)
5950{
5951 fpu_free(&vcpu->arch.guest_fpu);
5952}
5953
d0752060
HB		 5954void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5955{
2608d7a1 5956 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5957 return;
5958
2acf923e
DC		 5959 /*
5960 * Restore all possible states in the guest,
5961 * and assume host would use all available bits.
5962 * Guest xcr0 would be loaded later.
5963 */
5964 kvm_put_guest_xcr0(vcpu);
d0752060 5965 vcpu->guest_fpu_loaded = 1;
7cf30855 5966 unlazy_fpu(current);
98918833 5967 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5968 trace_kvm_fpu(1);
d0752060 5969}
d0752060
HB		 5970
5971void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5972{
2acf923e
DC		 5973 kvm_put_guest_xcr0(vcpu);
5974
d0752060
HB		 5975 if (!vcpu->guest_fpu_loaded)
5976 return;
5977
5978 vcpu->guest_fpu_loaded = 0;
98918833 5979 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5980 ++vcpu->stat.fpu_reload;
a8eeb04a 5981 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5982 trace_kvm_fpu(0);
d0752060 5983}
e9b11c17
ZX		 5984
5985void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5986{
12f9a48f 5987 kvmclock_reset(vcpu);
7f1ea208 5988
f5f48ee1 5989 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5990 fx_free(vcpu);
e9b11c17
ZX		 5991 kvm_x86_ops->vcpu_free(vcpu);
5992}
5993
5994struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5995 unsigned int id)
5996{
6755bae8
ZA		 5997 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5998 printk_once(KERN_WARNING
5999 "kvm: SMP vm created on host with unstable TSC; "
6000 "guest TSC will not be reliable\n");
26e5215f
AK		 6001 return kvm_x86_ops->vcpu_create(kvm, id);
6002}
e9b11c17 6003
26e5215f
AK		 6004int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6005{
6006 int r;
e9b11c17 6007
0bed3b56 6008 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6009 vcpu_load(vcpu);
6010 r = kvm_arch_vcpu_reset(vcpu);
6011 if (r == 0)
6012 r = kvm_mmu_setup(vcpu);
6013 vcpu_put(vcpu);
e9b11c17 6014
26e5215f 6015 return r;
e9b11c17
ZX		 6016}
6017
d40ccc62 6018void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6019{
344d9588
GN		 6020 vcpu->arch.apf.msr_val = 0;
6021
e9b11c17
ZX		 6022 vcpu_load(vcpu);
6023 kvm_mmu_unload(vcpu);
6024 vcpu_put(vcpu);
6025
98918833 6026 fx_free(vcpu);
e9b11c17
ZX		 6027 kvm_x86_ops->vcpu_free(vcpu);
6028}
6029
6030int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6031{
7460fb4a
AK		 6032 atomic_set(&vcpu->arch.nmi_queued, 0);
6033 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6034 vcpu->arch.nmi_injected = false;
6035
42dbaa5a
JK		 6036 vcpu->arch.switch_db_regs = 0;
6037 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6038 vcpu->arch.dr6 = DR6_FIXED_1;
6039 vcpu->arch.dr7 = DR7_FIXED_1;
6040
3842d135 6041 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6042 vcpu->arch.apf.msr_val = 0;
c9aaa895 6043 vcpu->arch.st.msr_val = 0;
3842d135 6044
12f9a48f
GC		 6045 kvmclock_reset(vcpu);
6046
af585b92
GN		 6047 kvm_clear_async_pf_completion_queue(vcpu);
6048 kvm_async_pf_hash_reset(vcpu);
6049 vcpu->arch.apf.halted = false;
3842d135 6050
f5132b01
GN		 6051 kvm_pmu_reset(vcpu);
6052
e9b11c17
ZX		 6053 return kvm_x86_ops->vcpu_reset(vcpu);
6054}
6055
10474ae8 6056int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6057{
ca84d1a2
ZA		 6058 struct kvm *kvm;
6059 struct kvm_vcpu *vcpu;
6060 int i;
0dd6a6ed
ZA		 6061 int ret;
6062 u64 local_tsc;
6063 u64 max_tsc = 0;
6064 bool stable, backwards_tsc = false;
18863bdd
AK		 6065
6066 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6067 ret = kvm_x86_ops->hardware_enable(garbage);
6068 if (ret != 0)
6069 return ret;
6070
6071 local_tsc = native_read_tsc();
6072 stable = !check_tsc_unstable();
6073 list_for_each_entry(kvm, &vm_list, vm_list) {
6074 kvm_for_each_vcpu(i, vcpu, kvm) {
6075 if (!stable && vcpu->cpu == smp_processor_id())
6076 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6077 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6078 backwards_tsc = true;
6079 if (vcpu->arch.last_host_tsc > max_tsc)
6080 max_tsc = vcpu->arch.last_host_tsc;
6081 }
6082 }
6083 }
6084
6085 /*
6086 * Sometimes, even reliable TSCs go backwards. This happens on
6087 * platforms that reset TSC during suspend or hibernate actions, but
6088 * maintain synchronization. We must compensate. Fortunately, we can
6089 * detect that condition here, which happens early in CPU bringup,
6090 * before any KVM threads can be running. Unfortunately, we can't
6091 * bring the TSCs fully up to date with real time, as we aren't yet far
6092 * enough into CPU bringup that we know how much real time has actually
6093 * elapsed; our helper function, get_kernel_ns() will be using boot
6094 * variables that haven't been updated yet.
6095 *
6096 * So we simply find the maximum observed TSC above, then record the
6097 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6098 * the adjustment will be applied. Note that we accumulate
6099 * adjustments, in case multiple suspend cycles happen before some VCPU
6100 * gets a chance to run again. In the event that no KVM threads get a
6101 * chance to run, we will miss the entire elapsed period, as we'll have
6102 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6103 * loose cycle time. This isn't too big a deal, since the loss will be
6104 * uniform across all VCPUs (not to mention the scenario is extremely
6105 * unlikely). It is possible that a second hibernate recovery happens
6106 * much faster than a first, causing the observed TSC here to be
6107 * smaller; this would require additional padding adjustment, which is
6108 * why we set last_host_tsc to the local tsc observed here.
6109 *
6110 * N.B. - this code below runs only on platforms with reliable TSC,
6111 * as that is the only way backwards_tsc is set above. Also note
6112 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6113 * have the same delta_cyc adjustment applied if backwards_tsc
6114 * is detected. Note further, this adjustment is only done once,
6115 * as we reset last_host_tsc on all VCPUs to stop this from being
6116 * called multiple times (one for each physical CPU bringup).
6117 *
4a969980 6118 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6119 * will be compensated by the logic in vcpu_load, which sets the TSC to
6120 * catchup mode. This will catchup all VCPUs to real time, but cannot
6121 * guarantee that they stay in perfect synchronization.
6122 */
6123 if (backwards_tsc) {
6124 u64 delta_cyc = max_tsc - local_tsc;
6125 list_for_each_entry(kvm, &vm_list, vm_list) {
6126 kvm_for_each_vcpu(i, vcpu, kvm) {
6127 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6128 vcpu->arch.last_host_tsc = local_tsc;
6129 }
6130
6131 /*
6132 * We have to disable TSC offset matching.. if you were
6133 * booting a VM while issuing an S4 host suspend....
6134 * you may have some problem. Solving this issue is
6135 * left as an exercise to the reader.
6136 */
6137 kvm->arch.last_tsc_nsec = 0;
6138 kvm->arch.last_tsc_write = 0;
6139 }
6140
6141 }
6142 return 0;
e9b11c17
ZX		 6143}
6144
6145void kvm_arch_hardware_disable(void *garbage)
6146{
6147 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6148 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6149}
6150
6151int kvm_arch_hardware_setup(void)
6152{
6153 return kvm_x86_ops->hardware_setup();
6154}
6155
6156void kvm_arch_hardware_unsetup(void)
6157{
6158 kvm_x86_ops->hardware_unsetup();
6159}
6160
6161void kvm_arch_check_processor_compat(void *rtn)
6162{
6163 kvm_x86_ops->check_processor_compatibility(rtn);
6164}
6165
3e515705
AK		 6166bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6167{
6168 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6169}
6170
54e9818f
GN		 6171struct static_key kvm_no_apic_vcpu __read_mostly;
6172
e9b11c17
ZX		 6173int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6174{
6175 struct page *page;
6176 struct kvm *kvm;
6177 int r;
6178
6179 BUG_ON(vcpu->kvm == NULL);
6180 kvm = vcpu->kvm;
6181
9aabc88f 6182 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6183 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6184 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6185 else
a4535290 6186 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6187
6188 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6189 if (!page) {
6190 r = -ENOMEM;
6191 goto fail;
6192 }
ad312c7c 6193 vcpu->arch.pio_data = page_address(page);
e9b11c17 6194
cc578287 6195 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6196
e9b11c17
ZX		 6197 r = kvm_mmu_create(vcpu);
6198 if (r < 0)
6199 goto fail_free_pio_data;
6200
6201 if (irqchip_in_kernel(kvm)) {
6202 r = kvm_create_lapic(vcpu);
6203 if (r < 0)
6204 goto fail_mmu_destroy;
54e9818f
GN		 6205 } else
6206 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6207
890ca9ae
HY		 6208 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6209 GFP_KERNEL);
6210 if (!vcpu->arch.mce_banks) {
6211 r = -ENOMEM;
443c39bc 6212 goto fail_free_lapic;
890ca9ae
HY		 6213 }
6214 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6215
f5f48ee1
SY		 6216 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6217 goto fail_free_mce_banks;
6218
af585b92 6219 kvm_async_pf_hash_reset(vcpu);
f5132b01 6220 kvm_pmu_init(vcpu);
af585b92 6221
e9b11c17 6222 return 0;
f5f48ee1
SY		 6223fail_free_mce_banks:
6224 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6225fail_free_lapic:
6226 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6227fail_mmu_destroy:
6228 kvm_mmu_destroy(vcpu);
6229fail_free_pio_data:
ad312c7c 6230 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6231fail:
6232 return r;
6233}
6234
6235void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6236{
f656ce01
MT		 6237 int idx;
6238
f5132b01 6239 kvm_pmu_destroy(vcpu);
36cb93fd 6240 kfree(vcpu->arch.mce_banks);
e9b11c17 6241 kvm_free_lapic(vcpu);
f656ce01 6242 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6243 kvm_mmu_destroy(vcpu);
f656ce01 6244 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6245 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6246 if (!irqchip_in_kernel(vcpu->kvm))
6247 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6248}
d19a9cd2 6249
e08b9637 6250int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6251{
e08b9637
CO		 6252 if (type)
6253 return -EINVAL;
6254
f05e70ac 6255 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6256 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6257
5550af4d
SY		 6258 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6259 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6260
038f8c11 6261 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6262
d89f5eff 6263 return 0;
d19a9cd2
ZX		 6264}
6265
6266static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6267{
6268 vcpu_load(vcpu);
6269 kvm_mmu_unload(vcpu);
6270 vcpu_put(vcpu);
6271}
6272
6273static void kvm_free_vcpus(struct kvm *kvm)
6274{
6275 unsigned int i;
988a2cae 6276 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6277
6278 /*
6279 * Unpin any mmu pages first.
6280 */
af585b92
GN		 6281 kvm_for_each_vcpu(i, vcpu, kvm) {
6282 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6283 kvm_unload_vcpu_mmu(vcpu);
af585b92 6284 }
988a2cae
GN		 6285 kvm_for_each_vcpu(i, vcpu, kvm)
6286 kvm_arch_vcpu_free(vcpu);
6287
6288 mutex_lock(&kvm->lock);
6289 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6290 kvm->vcpus[i] = NULL;
d19a9cd2 6291
988a2cae
GN		 6292 atomic_set(&kvm->online_vcpus, 0);
6293 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6294}
6295
ad8ba2cd
SY		 6296void kvm_arch_sync_events(struct kvm *kvm)
6297{
ba4cef31 6298 kvm_free_all_assigned_devices(kvm);
aea924f6 6299 kvm_free_pit(kvm);
ad8ba2cd
SY		 6300}
6301
d19a9cd2
ZX		 6302void kvm_arch_destroy_vm(struct kvm *kvm)
6303{
6eb55818 6304 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6305 kfree(kvm->arch.vpic);
6306 kfree(kvm->arch.vioapic);
d19a9cd2 6307 kvm_free_vcpus(kvm);
3d45830c
AK		 6308 if (kvm->arch.apic_access_page)
6309 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6310 if (kvm->arch.ept_identity_pagetable)
6311 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6312}
0de10343 6313
db3fe4eb
TY		 6314void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6315 struct kvm_memory_slot *dont)
6316{
6317 int i;
6318
d89cc617
TY		 6319 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6320 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6321 kvm_kvfree(free->arch.rmap[i]);
6322 free->arch.rmap[i] = NULL;
77d11309 6323 }
d89cc617
TY		 6324 if (i == 0)
6325 continue;
6326
6327 if (!dont || free->arch.lpage_info[i - 1] !=
6328 dont->arch.lpage_info[i - 1]) {
6329 kvm_kvfree(free->arch.lpage_info[i - 1]);
6330 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6331 }
6332 }
6333}
6334
6335int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6336{
6337 int i;
6338
d89cc617 6339 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6340 unsigned long ugfn;
6341 int lpages;
d89cc617 6342 int level = i + 1;
db3fe4eb
TY		 6343
6344 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6345 slot->base_gfn, level) + 1;
6346
d89cc617
TY		 6347 slot->arch.rmap[i] =
6348 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6349 if (!slot->arch.rmap[i])
77d11309 6350 goto out_free;
d89cc617
TY		 6351 if (i == 0)
6352 continue;
77d11309 6353
d89cc617
TY		 6354 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6355 sizeof(*slot->arch.lpage_info[i - 1]));
6356 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6357 goto out_free;
6358
6359 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6360 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6361 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6362 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6363 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6364 /*
6365 * If the gfn and userspace address are not aligned wrt each
6366 * other, or if explicitly asked to, disable large page
6367 * support for this slot
6368 */
6369 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6370 !kvm_largepages_enabled()) {
6371 unsigned long j;
6372
6373 for (j = 0; j < lpages; ++j)
d89cc617 6374 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6375 }
6376 }
6377
6378 return 0;
6379
6380out_free:
d89cc617
TY		 6381 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6382 kvm_kvfree(slot->arch.rmap[i]);
6383 slot->arch.rmap[i] = NULL;
6384 if (i == 0)
6385 continue;
6386
6387 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6388 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6389 }
6390 return -ENOMEM;
6391}
6392
f7784b8e
MT		 6393int kvm_arch_prepare_memory_region(struct kvm *kvm,
6394 struct kvm_memory_slot *memslot,
0de10343 6395 struct kvm_memory_slot old,
f7784b8e 6396 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6397 int user_alloc)
6398{
f7784b8e 6399 int npages = memslot->npages;
7ac77099
AK		 6400 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6401
6402 /* Prevent internal slot pages from being moved by fork()/COW. */
6403 if (memslot->id >= KVM_MEMORY_SLOTS)
6404 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6405
6406 /*To keep backward compatibility with older userspace,
4a969980 6407 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6408 */
6409 if (!user_alloc) {
aab2eb7a 6410 if (npages && !old.npages) {
604b38ac
AA		 6411 unsigned long userspace_addr;
6412
6be5ceb0 6413 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6414 npages * PAGE_SIZE,
6415 PROT_READ | PROT_WRITE,
7ac77099 6416 map_flags,
604b38ac 6417 0);
0de10343 6418
604b38ac
AA		 6419 if (IS_ERR((void *)userspace_addr))
6420 return PTR_ERR((void *)userspace_addr);
6421
604b38ac 6422 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6423 }
6424 }
6425
f7784b8e
MT		 6426
6427 return 0;
6428}
6429
6430void kvm_arch_commit_memory_region(struct kvm *kvm,
6431 struct kvm_userspace_memory_region *mem,
6432 struct kvm_memory_slot old,
6433 int user_alloc)
6434{
6435
48c0e4e9 6436 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6437
aab2eb7a 6438 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6439 int ret;
6440
bfce281c 6441 ret = vm_munmap(old.userspace_addr,
f7784b8e 6442 old.npages * PAGE_SIZE);
f7784b8e
MT		 6443 if (ret < 0)
6444 printk(KERN_WARNING
6445 "kvm_vm_ioctl_set_memory_region: "
6446 "failed to munmap memory\n");
6447 }
6448
48c0e4e9
XG		 6449 if (!kvm->arch.n_requested_mmu_pages)
6450 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6451
7c8a83b7 6452 spin_lock(&kvm->mmu_lock);
48c0e4e9 6453 if (nr_mmu_pages)
0de10343 6454 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6455 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6456 spin_unlock(&kvm->mmu_lock);
0de10343 6457}
1d737c8a 6458
34d4cb8f
MT		 6459void kvm_arch_flush_shadow(struct kvm *kvm)
6460{
6461 kvm_mmu_zap_all(kvm);
8986ecc0 6462 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6463}
6464
1d737c8a
ZX		 6465int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6466{
af585b92
GN		 6467 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6468 !vcpu->arch.apf.halted)
6469 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6470 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6471 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6472 (kvm_arch_interrupt_allowed(vcpu) &&
6473 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6474}
5736199a 6475
b6d33834 6476int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6477{
b6d33834 6478 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6479}
78646121
GN		 6480
6481int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6482{
6483 return kvm_x86_ops->interrupt_allowed(vcpu);
6484}
229456fc 6485
f92653ee
JK		 6486bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6487{
6488 unsigned long current_rip = kvm_rip_read(vcpu) +
6489 get_segment_base(vcpu, VCPU_SREG_CS);
6490
6491 return current_rip == linear_rip;
6492}
6493EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6494
94fe45da
JK		 6495unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6496{
6497 unsigned long rflags;
6498
6499 rflags = kvm_x86_ops->get_rflags(vcpu);
6500 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6501 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6502 return rflags;
6503}
6504EXPORT_SYMBOL_GPL(kvm_get_rflags);
6505
6506void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6507{
6508 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6509 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6510 rflags |= X86_EFLAGS_TF;
94fe45da 6511 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6512 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6513}
6514EXPORT_SYMBOL_GPL(kvm_set_rflags);
6515
56028d08
GN		 6516void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6517{
6518 int r;
6519
fb67e14f 6520 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6521 is_error_page(work->page))
56028d08
GN		 6522 return;
6523
6524 r = kvm_mmu_reload(vcpu);
6525 if (unlikely(r))
6526 return;
6527
fb67e14f
XG		 6528 if (!vcpu->arch.mmu.direct_map &&
6529 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6530 return;
6531
56028d08
GN		 6532 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6533}
6534
af585b92
GN		 6535static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6536{
6537 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6538}
6539
6540static inline u32 kvm_async_pf_next_probe(u32 key)
6541{
6542 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6543}
6544
6545static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6546{
6547 u32 key = kvm_async_pf_hash_fn(gfn);
6548
6549 while (vcpu->arch.apf.gfns[key] != ~0)
6550 key = kvm_async_pf_next_probe(key);
6551
6552 vcpu->arch.apf.gfns[key] = gfn;
6553}
6554
6555static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6556{
6557 int i;
6558 u32 key = kvm_async_pf_hash_fn(gfn);
6559
6560 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6561 (vcpu->arch.apf.gfns[key] != gfn &&
6562 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6563 key = kvm_async_pf_next_probe(key);
6564
6565 return key;
6566}
6567
6568bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6569{
6570 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6571}
6572
6573static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6574{
6575 u32 i, j, k;
6576
6577 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6578 while (true) {
6579 vcpu->arch.apf.gfns[i] = ~0;
6580 do {
6581 j = kvm_async_pf_next_probe(j);
6582 if (vcpu->arch.apf.gfns[j] == ~0)
6583 return;
6584 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6585 /*
6586 * k lies cyclically in ]i,j]
6587 * | i.k.j |
6588 * |....j i.k.| or |.k..j i...|
6589 */
6590 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6591 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6592 i = j;
6593 }
6594}
6595
7c90705b
GN		 6596static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6597{
6598
6599 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6600 sizeof(val));
6601}
6602
af585b92
GN		 6603void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6604 struct kvm_async_pf *work)
6605{
6389ee94
AK		 6606 struct x86_exception fault;
6607
7c90705b 6608 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6609 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6610
6611 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6612 (vcpu->arch.apf.send_user_only &&
6613 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6614 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6615 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6616 fault.vector = PF_VECTOR;
6617 fault.error_code_valid = true;
6618 fault.error_code = 0;
6619 fault.nested_page_fault = false;
6620 fault.address = work->arch.token;
6621 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6622 }
af585b92
GN		 6623}
6624
6625void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6626 struct kvm_async_pf *work)
6627{
6389ee94
AK		 6628 struct x86_exception fault;
6629
7c90705b
GN		 6630 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6631 if (is_error_page(work->page))
6632 work->arch.token = ~0; /* broadcast wakeup */
6633 else
6634 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6635
6636 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6637 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6638 fault.vector = PF_VECTOR;
6639 fault.error_code_valid = true;
6640 fault.error_code = 0;
6641 fault.nested_page_fault = false;
6642 fault.address = work->arch.token;
6643 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6644 }
e6d53e3b 6645 vcpu->arch.apf.halted = false;
a4fa1635 6646 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6647}
6648
6649bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6650{
6651 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6652 return true;
6653 else
6654 return !kvm_event_needs_reinjection(vcpu) &&
6655 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6656}
6657
229456fc
MT		 6658EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6659EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6660EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6661EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6662EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6663EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6664EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6665EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6666EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6667EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6668EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6669EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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