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KVM: enlarge number of possible CPUID leaves
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
5854dbca 76#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
18863bdd
AK		 158static void kvm_on_user_return(struct user_return_notifier *urn)
159{
160 unsigned slot;
18863bdd
AK		 161 struct kvm_shared_msrs *locals
162 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 163 struct kvm_shared_msr_values *values;
18863bdd
AK		 164
165 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 166 values = &locals->values[slot];
167 if (values->host != values->curr) {
168 wrmsrl(shared_msrs_global.msrs[slot], values->host);
169 values->curr = values->host;
18863bdd
AK		 170 }
171 }
172 locals->registered = false;
173 user_return_notifier_unregister(urn);
174}
175
2bf78fa7 176static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 177{
2bf78fa7 178 struct kvm_shared_msrs *smsr;
18863bdd
AK		 179 u64 value;
180
2bf78fa7
SY		 181 smsr = &__get_cpu_var(shared_msrs);
182 /* only read, and nobody should modify it at this time,
183 * so don't need lock */
184 if (slot >= shared_msrs_global.nr) {
185 printk(KERN_ERR "kvm: invalid MSR slot!");
186 return;
187 }
188 rdmsrl_safe(msr, &value);
189 smsr->values[slot].host = value;
190 smsr->values[slot].curr = value;
191}
192
193void kvm_define_shared_msr(unsigned slot, u32 msr)
194{
18863bdd
AK		 195 if (slot >= shared_msrs_global.nr)
196 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 197 shared_msrs_global.msrs[slot] = msr;
198 /* we need ensured the shared_msr_global have been updated */
199 smp_wmb();
18863bdd
AK		 200}
201EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
202
203static void kvm_shared_msr_cpu_online(void)
204{
205 unsigned i;
18863bdd
AK		 206
207 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 208 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 209}
210
d5696725 211void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 212{
213 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
214
2bf78fa7 215 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 216 return;
2bf78fa7
SY		 217 smsr->values[slot].curr = value;
218 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 219 if (!smsr->registered) {
220 smsr->urn.on_user_return = kvm_on_user_return;
221 user_return_notifier_register(&smsr->urn);
222 smsr->registered = true;
223 }
224}
225EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
226
3548bab5
AK		 227static void drop_user_return_notifiers(void *ignore)
228{
229 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
230
231 if (smsr->registered)
232 kvm_on_user_return(&smsr->urn);
233}
234
6866b83e
CO		 235u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
236{
237 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 238 return vcpu->arch.apic_base;
6866b83e 239 else
ad312c7c 240 return vcpu->arch.apic_base;
6866b83e
CO		 241}
242EXPORT_SYMBOL_GPL(kvm_get_apic_base);
243
244void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
245{
246 /* TODO: reserve bits check */
247 if (irqchip_in_kernel(vcpu->kvm))
248 kvm_lapic_set_base(vcpu, data);
249 else
ad312c7c 250 vcpu->arch.apic_base = data;
6866b83e
CO		 251}
252EXPORT_SYMBOL_GPL(kvm_set_apic_base);
253
3fd28fce
ED		 254#define EXCPT_BENIGN 0
255#define EXCPT_CONTRIBUTORY 1
256#define EXCPT_PF 2
257
258static int exception_class(int vector)
259{
260 switch (vector) {
261 case PF_VECTOR:
262 return EXCPT_PF;
263 case DE_VECTOR:
264 case TS_VECTOR:
265 case NP_VECTOR:
266 case SS_VECTOR:
267 case GP_VECTOR:
268 return EXCPT_CONTRIBUTORY;
269 default:
270 break;
271 }
272 return EXCPT_BENIGN;
273}
274
275static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 276 unsigned nr, bool has_error, u32 error_code,
277 bool reinject)
3fd28fce
ED		 278{
279 u32 prev_nr;
280 int class1, class2;
281
3842d135
AK		 282 kvm_make_request(KVM_REQ_EVENT, vcpu);
283
3fd28fce
ED		 284 if (!vcpu->arch.exception.pending) {
285 queue:
286 vcpu->arch.exception.pending = true;
287 vcpu->arch.exception.has_error_code = has_error;
288 vcpu->arch.exception.nr = nr;
289 vcpu->arch.exception.error_code = error_code;
3f0fd292 290 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 291 return;
292 }
293
294 /* to check exception */
295 prev_nr = vcpu->arch.exception.nr;
296 if (prev_nr == DF_VECTOR) {
297 /* triple fault -> shutdown */
a8eeb04a 298 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 299 return;
300 }
301 class1 = exception_class(prev_nr);
302 class2 = exception_class(nr);
303 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
304 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
305 /* generate double fault per SDM Table 5-5 */
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = true;
308 vcpu->arch.exception.nr = DF_VECTOR;
309 vcpu->arch.exception.error_code = 0;
310 } else
311 /* replace previous exception with a new one in a hope
312 that instruction re-execution will regenerate lost
313 exception */
314 goto queue;
315}
316
298101da
AK		 317void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
318{
ce7ddec4 319 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 320}
321EXPORT_SYMBOL_GPL(kvm_queue_exception);
322
ce7ddec4
JR		 323void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
325 kvm_multiple_exception(vcpu, nr, false, 0, true);
326}
327EXPORT_SYMBOL_GPL(kvm_requeue_exception);
328
8df25a32 329void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 330{
8df25a32
JR		 331 unsigned error_code = vcpu->arch.fault.error_code;
332
c3c91fee 333 ++vcpu->stat.pf_guest;
8df25a32 334 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 335 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
336}
337
d4f8cf66
JR		 338void kvm_propagate_fault(struct kvm_vcpu *vcpu)
339{
0959ffac 340 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 341 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
342 else
343 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 344
345 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 346}
347
3419ffc8
SY		 348void kvm_inject_nmi(struct kvm_vcpu *vcpu)
349{
3842d135 350 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 351 vcpu->arch.nmi_pending = 1;
352}
353EXPORT_SYMBOL_GPL(kvm_inject_nmi);
354
298101da
AK		 355void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
356{
ce7ddec4 357 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 358}
359EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
360
ce7ddec4
JR		 361void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
362{
363 kvm_multiple_exception(vcpu, nr, true, error_code, true);
364}
365EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
366
0a79b009
AK		 367/*
368 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
369 * a #GP and return false.
370 */
371bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 372{
0a79b009
AK		 373 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
374 return true;
375 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
376 return false;
298101da 377}
0a79b009 378EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 379
ec92fe44
JR		 380/*
381 * This function will be used to read from the physical memory of the currently
382 * running guest. The difference to kvm_read_guest_page is that this function
383 * can read from guest physical or from the guest's guest physical memory.
384 */
385int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
386 gfn_t ngfn, void *data, int offset, int len,
387 u32 access)
388{
389 gfn_t real_gfn;
390 gpa_t ngpa;
391
392 ngpa = gfn_to_gpa(ngfn);
393 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
394 if (real_gfn == UNMAPPED_GVA)
395 return -EFAULT;
396
397 real_gfn = gpa_to_gfn(real_gfn);
398
399 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
400}
401EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
402
3d06b8bf
JR		 403int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
404 void *data, int offset, int len, u32 access)
405{
406 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
407 data, offset, len, access);
408}
409
a03490ed
CO		 410/*
411 * Load the pae pdptrs. Return true is they are all valid.
412 */
ff03a073 413int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 414{
415 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
416 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
417 int i;
418 int ret;
ff03a073 419 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 420
ff03a073
JR		 421 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
422 offset * sizeof(u64), sizeof(pdpte),
423 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 424 if (ret < 0) {
425 ret = 0;
426 goto out;
427 }
428 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 429 if (is_present_gpte(pdpte[i]) &&
20c466b5 430 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 431 ret = 0;
432 goto out;
433 }
434 }
435 ret = 1;
436
ff03a073 437 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 438 __set_bit(VCPU_EXREG_PDPTR,
439 (unsigned long *)&vcpu->arch.regs_avail);
440 __set_bit(VCPU_EXREG_PDPTR,
441 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 442out:
a03490ed
CO		 443
444 return ret;
445}
cc4b6871 446EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 447
d835dfec
AK		 448static bool pdptrs_changed(struct kvm_vcpu *vcpu)
449{
ff03a073 450 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 451 bool changed = true;
3d06b8bf
JR		 452 int offset;
453 gfn_t gfn;
d835dfec
AK		 454 int r;
455
456 if (is_long_mode(vcpu) || !is_pae(vcpu))
457 return false;
458
6de4f3ad
AK		 459 if (!test_bit(VCPU_EXREG_PDPTR,
460 (unsigned long *)&vcpu->arch.regs_avail))
461 return true;
462
3d06b8bf
JR		 463 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
464 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
465 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
466 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 467 if (r < 0)
468 goto out;
ff03a073 469 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 470out:
d835dfec
AK		 471
472 return changed;
473}
474
49a9b07e 475int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 476{
aad82703
SY		 477 unsigned long old_cr0 = kvm_read_cr0(vcpu);
478 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
479 X86_CR0_CD | X86_CR0_NW;
480
f9a48e6a
AK		 481 cr0 |= X86_CR0_ET;
482
ab344828 483#ifdef CONFIG_X86_64
0f12244f
GN		 484 if (cr0 & 0xffffffff00000000UL)
485 return 1;
ab344828
GN		 486#endif
487
488 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 489
0f12244f
GN		 490 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
491 return 1;
a03490ed 492
0f12244f
GN		 493 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
494 return 1;
a03490ed
CO		 495
496 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
497#ifdef CONFIG_X86_64
f6801dff 498 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 499 int cs_db, cs_l;
500
0f12244f
GN		 501 if (!is_pae(vcpu))
502 return 1;
a03490ed 503 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 504 if (cs_l)
505 return 1;
a03490ed
CO		 506 } else
507#endif
ff03a073
JR		 508 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
509 vcpu->arch.cr3))
0f12244f 510 return 1;
a03490ed
CO		 511 }
512
513 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 514
aad82703
SY		 515 if ((cr0 ^ old_cr0) & update_bits)
516 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 517 return 0;
518}
2d3ad1f4 519EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 520
2d3ad1f4 521void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 522{
49a9b07e 523 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 524}
2d3ad1f4 525EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 526
2acf923e
DC		 527int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
528{
529 u64 xcr0;
530
531 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
532 if (index != XCR_XFEATURE_ENABLED_MASK)
533 return 1;
534 xcr0 = xcr;
535 if (kvm_x86_ops->get_cpl(vcpu) != 0)
536 return 1;
537 if (!(xcr0 & XSTATE_FP))
538 return 1;
539 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
540 return 1;
541 if (xcr0 & ~host_xcr0)
542 return 1;
543 vcpu->arch.xcr0 = xcr0;
544 vcpu->guest_xcr0_loaded = 0;
545 return 0;
546}
547
548int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
549{
550 if (__kvm_set_xcr(vcpu, index, xcr)) {
551 kvm_inject_gp(vcpu, 0);
552 return 1;
553 }
554 return 0;
555}
556EXPORT_SYMBOL_GPL(kvm_set_xcr);
557
558static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
559{
560 struct kvm_cpuid_entry2 *best;
561
562 best = kvm_find_cpuid_entry(vcpu, 1, 0);
563 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
564}
565
566static void update_cpuid(struct kvm_vcpu *vcpu)
567{
568 struct kvm_cpuid_entry2 *best;
569
570 best = kvm_find_cpuid_entry(vcpu, 1, 0);
571 if (!best)
572 return;
573
574 /* Update OSXSAVE bit */
575 if (cpu_has_xsave && best->function == 0x1) {
576 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
577 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
578 best->ecx |= bit(X86_FEATURE_OSXSAVE);
579 }
580}
581
a83b29c6 582int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 583{
fc78f519 584 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 585 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
586
0f12244f
GN		 587 if (cr4 & CR4_RESERVED_BITS)
588 return 1;
a03490ed 589
2acf923e
DC		 590 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
591 return 1;
592
a03490ed 593 if (is_long_mode(vcpu)) {
0f12244f
GN		 594 if (!(cr4 & X86_CR4_PAE))
595 return 1;
a2edf57f
AK		 596 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
597 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 598 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 599 return 1;
600
601 if (cr4 & X86_CR4_VMXE)
602 return 1;
a03490ed 603
a03490ed 604 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 605
aad82703
SY		 606 if ((cr4 ^ old_cr4) & pdptr_bits)
607 kvm_mmu_reset_context(vcpu);
0f12244f 608
2acf923e
DC		 609 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
610 update_cpuid(vcpu);
611
0f12244f
GN		 612 return 0;
613}
2d3ad1f4 614EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 615
2390218b 616int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 617{
ad312c7c 618 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 619 kvm_mmu_sync_roots(vcpu);
d835dfec 620 kvm_mmu_flush_tlb(vcpu);
0f12244f 621 return 0;
d835dfec
AK		 622 }
623
a03490ed 624 if (is_long_mode(vcpu)) {
0f12244f
GN		 625 if (cr3 & CR3_L_MODE_RESERVED_BITS)
626 return 1;
a03490ed
CO		 627 } else {
628 if (is_pae(vcpu)) {
0f12244f
GN		 629 if (cr3 & CR3_PAE_RESERVED_BITS)
630 return 1;
ff03a073
JR		 631 if (is_paging(vcpu) &&
632 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 633 return 1;
a03490ed
CO		 634 }
635 /*
636 * We don't check reserved bits in nonpae mode, because
637 * this isn't enforced, and VMware depends on this.
638 */
639 }
640
a03490ed
CO		 641 /*
642 * Does the new cr3 value map to physical memory? (Note, we
643 * catch an invalid cr3 even in real-mode, because it would
644 * cause trouble later on when we turn on paging anyway.)
645 *
646 * A real CPU would silently accept an invalid cr3 and would
647 * attempt to use it - with largely undefined (and often hard
648 * to debug) behavior on the guest side.
649 */
650 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 651 return 1;
652 vcpu->arch.cr3 = cr3;
653 vcpu->arch.mmu.new_cr3(vcpu);
654 return 0;
655}
2d3ad1f4 656EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 657
0f12244f 658int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 659{
0f12244f
GN		 660 if (cr8 & CR8_RESERVED_BITS)
661 return 1;
a03490ed
CO		 662 if (irqchip_in_kernel(vcpu->kvm))
663 kvm_lapic_set_tpr(vcpu, cr8);
664 else
ad312c7c 665 vcpu->arch.cr8 = cr8;
0f12244f
GN		 666 return 0;
667}
668
669void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
670{
671 if (__kvm_set_cr8(vcpu, cr8))
672 kvm_inject_gp(vcpu, 0);
a03490ed 673}
2d3ad1f4 674EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 675
2d3ad1f4 676unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 677{
678 if (irqchip_in_kernel(vcpu->kvm))
679 return kvm_lapic_get_cr8(vcpu);
680 else
ad312c7c 681 return vcpu->arch.cr8;
a03490ed 682}
2d3ad1f4 683EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 684
338dbc97 685static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 686{
687 switch (dr) {
688 case 0 ... 3:
689 vcpu->arch.db[dr] = val;
690 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
691 vcpu->arch.eff_db[dr] = val;
692 break;
693 case 4:
338dbc97
GN		 694 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
695 return 1; /* #UD */
020df079
GN		 696 /* fall through */
697 case 6:
338dbc97
GN		 698 if (val & 0xffffffff00000000ULL)
699 return -1; /* #GP */
020df079
GN		 700 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
701 break;
702 case 5:
338dbc97
GN		 703 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
704 return 1; /* #UD */
020df079
GN		 705 /* fall through */
706 default: /* 7 */
338dbc97
GN		 707 if (val & 0xffffffff00000000ULL)
708 return -1; /* #GP */
020df079
GN		 709 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
710 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
711 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
712 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
713 }
714 break;
715 }
716
717 return 0;
718}
338dbc97
GN		 719
720int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
721{
722 int res;
723
724 res = __kvm_set_dr(vcpu, dr, val);
725 if (res > 0)
726 kvm_queue_exception(vcpu, UD_VECTOR);
727 else if (res < 0)
728 kvm_inject_gp(vcpu, 0);
729
730 return res;
731}
020df079
GN		 732EXPORT_SYMBOL_GPL(kvm_set_dr);
733
338dbc97 734static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 735{
736 switch (dr) {
737 case 0 ... 3:
738 *val = vcpu->arch.db[dr];
739 break;
740 case 4:
338dbc97 741 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 742 return 1;
020df079
GN		 743 /* fall through */
744 case 6:
745 *val = vcpu->arch.dr6;
746 break;
747 case 5:
338dbc97 748 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 749 return 1;
020df079
GN		 750 /* fall through */
751 default: /* 7 */
752 *val = vcpu->arch.dr7;
753 break;
754 }
755
756 return 0;
757}
338dbc97
GN		 758
759int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
760{
761 if (_kvm_get_dr(vcpu, dr, val)) {
762 kvm_queue_exception(vcpu, UD_VECTOR);
763 return 1;
764 }
765 return 0;
766}
020df079
GN		 767EXPORT_SYMBOL_GPL(kvm_get_dr);
768
043405e1
CO		 769/*
770 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
771 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
772 *
773 * This list is modified at module load time to reflect the
e3267cbb
GC		 774 * capabilities of the host cpu. This capabilities test skips MSRs that are
775 * kvm-specific. Those are put in the beginning of the list.
043405e1 776 */
e3267cbb 777
11c6bffa 778#define KVM_SAVE_MSRS_BEGIN 7
043405e1 779static u32 msrs_to_save[] = {
e3267cbb 780 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 781 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 782 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 783 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 784 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 785 MSR_STAR,
043405e1
CO		 786#ifdef CONFIG_X86_64
787 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
788#endif
e90aa41e 789 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 790};
791
792static unsigned num_msrs_to_save;
793
794static u32 emulated_msrs[] = {
795 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 796 MSR_IA32_MCG_STATUS,
797 MSR_IA32_MCG_CTL,
043405e1
CO		 798};
799
b69e8cae 800static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 801{
aad82703
SY		 802 u64 old_efer = vcpu->arch.efer;
803
b69e8cae
RJ		 804 if (efer & efer_reserved_bits)
805 return 1;
15c4a640
CO		 806
807 if (is_paging(vcpu)
b69e8cae
RJ		 808 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
809 return 1;
15c4a640 810
1b2fd70c
AG		 811 if (efer & EFER_FFXSR) {
812 struct kvm_cpuid_entry2 *feat;
813
814 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 815 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
816 return 1;
1b2fd70c
AG		 817 }
818
d8017474
AG		 819 if (efer & EFER_SVME) {
820 struct kvm_cpuid_entry2 *feat;
821
822 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 823 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
824 return 1;
d8017474
AG		 825 }
826
15c4a640 827 efer &= ~EFER_LMA;
f6801dff 828 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 829
a3d204e2
SY		 830 kvm_x86_ops->set_efer(vcpu, efer);
831
9645bb56
AK		 832 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
833 kvm_mmu_reset_context(vcpu);
b69e8cae 834
aad82703
SY		 835 /* Update reserved bits */
836 if ((efer ^ old_efer) & EFER_NX)
837 kvm_mmu_reset_context(vcpu);
838
b69e8cae 839 return 0;
15c4a640
CO		 840}
841
f2b4b7dd
JR		 842void kvm_enable_efer_bits(u64 mask)
843{
844 efer_reserved_bits &= ~mask;
845}
846EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
847
848
15c4a640
CO		 849/*
850 * Writes msr value into into the appropriate "register".
851 * Returns 0 on success, non-0 otherwise.
852 * Assumes vcpu_load() was already called.
853 */
854int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
855{
856 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
857}
858
313a3dc7
CO		 859/*
860 * Adapt set_msr() to msr_io()'s calling convention
861 */
862static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
863{
864 return kvm_set_msr(vcpu, index, *data);
865}
866
18068523
GOC		 867static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
868{
9ed3c444
AK		 869 int version;
870 int r;
50d0a0f9 871 struct pvclock_wall_clock wc;
923de3cf 872 struct timespec boot;
18068523
GOC		 873
874 if (!wall_clock)
875 return;
876
9ed3c444
AK		 877 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
878 if (r)
879 return;
880
881 if (version & 1)
882 ++version; /* first time write, random junk */
883
884 ++version;
18068523 885
18068523
GOC		 886 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
887
50d0a0f9
GH		 888 /*
889 * The guest calculates current wall clock time by adding
34c238a1 890 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 891 * wall clock specified here. guest system time equals host
892 * system time for us, thus we must fill in host boot time here.
893 */
923de3cf 894 getboottime(&boot);
50d0a0f9
GH		 895
896 wc.sec = boot.tv_sec;
897 wc.nsec = boot.tv_nsec;
898 wc.version = version;
18068523
GOC		 899
900 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
901
902 version++;
903 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 904}
905
50d0a0f9
GH		 906static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
907{
908 uint32_t quotient, remainder;
909
910 /* Don't try to replace with do_div(), this one calculates
911 * "(dividend << 32) / divisor" */
912 __asm__ ( "divl %4"
913 : "=a" (quotient), "=d" (remainder)
914 : "0" (0), "1" (dividend), "r" (divisor) );
915 return quotient;
916}
917
5f4e3f88
ZA		 918static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
919 s8 *pshift, u32 *pmultiplier)
50d0a0f9 920{
5f4e3f88 921 uint64_t scaled64;
50d0a0f9
GH		 922 int32_t shift = 0;
923 uint64_t tps64;
924 uint32_t tps32;
925
5f4e3f88
ZA		 926 tps64 = base_khz * 1000LL;
927 scaled64 = scaled_khz * 1000LL;
50933623 928 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 929 tps64 >>= 1;
930 shift--;
931 }
932
933 tps32 = (uint32_t)tps64;
50933623
JK		 934 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
935 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 936 scaled64 >>= 1;
937 else
938 tps32 <<= 1;
50d0a0f9
GH		 939 shift++;
940 }
941
5f4e3f88
ZA		 942 *pshift = shift;
943 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 944
5f4e3f88
ZA		 945 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
946 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 947}
948
759379dd
ZA		 949static inline u64 get_kernel_ns(void)
950{
951 struct timespec ts;
952
953 WARN_ON(preemptible());
954 ktime_get_ts(&ts);
955 monotonic_to_bootbased(&ts);
956 return timespec_to_ns(&ts);
50d0a0f9
GH		 957}
958
c8076604 959static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 960unsigned long max_tsc_khz;
c8076604 961
8cfdc000
ZA		 962static inline int kvm_tsc_changes_freq(void)
963{
964 int cpu = get_cpu();
965 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
966 cpufreq_quick_get(cpu) != 0;
967 put_cpu();
968 return ret;
969}
970
759379dd
ZA		 971static inline u64 nsec_to_cycles(u64 nsec)
972{
217fc9cf
AK		 973 u64 ret;
974
759379dd
ZA		 975 WARN_ON(preemptible());
976 if (kvm_tsc_changes_freq())
977 printk_once(KERN_WARNING
978 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 979 ret = nsec * __get_cpu_var(cpu_tsc_khz);
980 do_div(ret, USEC_PER_SEC);
981 return ret;
759379dd
ZA		 982}
983
c285545f
ZA		 984static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
985{
986 /* Compute a scale to convert nanoseconds in TSC cycles */
987 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
988 &kvm->arch.virtual_tsc_shift,
989 &kvm->arch.virtual_tsc_mult);
990 kvm->arch.virtual_tsc_khz = this_tsc_khz;
991}
992
993static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
994{
995 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
996 vcpu->kvm->arch.virtual_tsc_mult,
997 vcpu->kvm->arch.virtual_tsc_shift);
998 tsc += vcpu->arch.last_tsc_write;
999 return tsc;
1000}
1001
99e3e30a
ZA		 1002void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1003{
1004 struct kvm *kvm = vcpu->kvm;
f38e098f 1005 u64 offset, ns, elapsed;
99e3e30a 1006 unsigned long flags;
46543ba4 1007 s64 sdiff;
99e3e30a
ZA		 1008
1009 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1010 offset = data - native_read_tsc();
759379dd 1011 ns = get_kernel_ns();
f38e098f 1012 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1013 sdiff = data - kvm->arch.last_tsc_write;
1014 if (sdiff < 0)
1015 sdiff = -sdiff;
f38e098f
ZA		 1016
1017 /*
46543ba4 1018 * Special case: close write to TSC within 5 seconds of
f38e098f 1019 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1020 * The 5 seconds is to accomodate host load / swapping as
1021 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1022 *
1023 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1024 * or make a best guest using elapsed value.
f38e098f 1025 */
46543ba4
ZA		 1026 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1027 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1028 if (!check_tsc_unstable()) {
1029 offset = kvm->arch.last_tsc_offset;
1030 pr_debug("kvm: matched tsc offset for %llu\n", data);
1031 } else {
759379dd
ZA		 1032 u64 delta = nsec_to_cycles(elapsed);
1033 offset += delta;
1034 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1035 }
1036 ns = kvm->arch.last_tsc_nsec;
1037 }
1038 kvm->arch.last_tsc_nsec = ns;
1039 kvm->arch.last_tsc_write = data;
1040 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1041 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1042 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1043
1044 /* Reset of TSC must disable overshoot protection below */
1045 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1046 vcpu->arch.last_tsc_write = data;
1047 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1048}
1049EXPORT_SYMBOL_GPL(kvm_write_tsc);
1050
34c238a1 1051static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1052{
18068523
GOC		 1053 unsigned long flags;
1054 struct kvm_vcpu_arch *vcpu = &v->arch;
1055 void *shared_kaddr;
463656c0 1056 unsigned long this_tsc_khz;
1d5f066e
ZA		 1057 s64 kernel_ns, max_kernel_ns;
1058 u64 tsc_timestamp;
18068523 1059
18068523
GOC		 1060 /* Keep irq disabled to prevent changes to the clock */
1061 local_irq_save(flags);
1d5f066e 1062 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1063 kernel_ns = get_kernel_ns();
8cfdc000 1064 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1065
8cfdc000 1066 if (unlikely(this_tsc_khz == 0)) {
c285545f 1067 local_irq_restore(flags);
34c238a1 1068 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1069 return 1;
1070 }
18068523 1071
c285545f
ZA		 1072 /*
1073 * We may have to catch up the TSC to match elapsed wall clock
1074 * time for two reasons, even if kvmclock is used.
1075 * 1) CPU could have been running below the maximum TSC rate
1076 * 2) Broken TSC compensation resets the base at each VCPU
1077 * entry to avoid unknown leaps of TSC even when running
1078 * again on the same CPU. This may cause apparent elapsed
1079 * time to disappear, and the guest to stand still or run
1080 * very slowly.
1081 */
1082 if (vcpu->tsc_catchup) {
1083 u64 tsc = compute_guest_tsc(v, kernel_ns);
1084 if (tsc > tsc_timestamp) {
1085 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1086 tsc_timestamp = tsc;
1087 }
50d0a0f9
GH		 1088 }
1089
18068523
GOC		 1090 local_irq_restore(flags);
1091
c285545f
ZA		 1092 if (!vcpu->time_page)
1093 return 0;
18068523 1094
1d5f066e
ZA		 1095 /*
1096 * Time as measured by the TSC may go backwards when resetting the base
1097 * tsc_timestamp. The reason for this is that the TSC resolution is
1098 * higher than the resolution of the other clock scales. Thus, many
1099 * possible measurments of the TSC correspond to one measurement of any
1100 * other clock, and so a spread of values is possible. This is not a
1101 * problem for the computation of the nanosecond clock; with TSC rates
1102 * around 1GHZ, there can only be a few cycles which correspond to one
1103 * nanosecond value, and any path through this code will inevitably
1104 * take longer than that. However, with the kernel_ns value itself,
1105 * the precision may be much lower, down to HZ granularity. If the
1106 * first sampling of TSC against kernel_ns ends in the low part of the
1107 * range, and the second in the high end of the range, we can get:
1108 *
1109 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1110 *
1111 * As the sampling errors potentially range in the thousands of cycles,
1112 * it is possible such a time value has already been observed by the
1113 * guest. To protect against this, we must compute the system time as
1114 * observed by the guest and ensure the new system time is greater.
1115 */
1116 max_kernel_ns = 0;
1117 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1118 max_kernel_ns = vcpu->last_guest_tsc -
1119 vcpu->hv_clock.tsc_timestamp;
1120 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1121 vcpu->hv_clock.tsc_to_system_mul,
1122 vcpu->hv_clock.tsc_shift);
1123 max_kernel_ns += vcpu->last_kernel_ns;
1124 }
afbcf7ab 1125
e48672fa 1126 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1127 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1128 &vcpu->hv_clock.tsc_shift,
1129 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1130 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1131 }
1132
1d5f066e
ZA		 1133 if (max_kernel_ns > kernel_ns)
1134 kernel_ns = max_kernel_ns;
1135
8cfdc000 1136 /* With all the info we got, fill in the values */
1d5f066e 1137 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1138 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1139 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1140 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1141 vcpu->hv_clock.flags = 0;
1142
18068523
GOC		 1143 /*
1144 * The interface expects us to write an even number signaling that the
1145 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1146 * state, we just increase by 2 at the end.
18068523 1147 */
50d0a0f9 1148 vcpu->hv_clock.version += 2;
18068523
GOC		 1149
1150 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1151
1152 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1153 sizeof(vcpu->hv_clock));
18068523
GOC		 1154
1155 kunmap_atomic(shared_kaddr, KM_USER0);
1156
1157 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1158 return 0;
c8076604
GH		 1159}
1160
9ba075a6
AK		 1161static bool msr_mtrr_valid(unsigned msr)
1162{
1163 switch (msr) {
1164 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1165 case MSR_MTRRfix64K_00000:
1166 case MSR_MTRRfix16K_80000:
1167 case MSR_MTRRfix16K_A0000:
1168 case MSR_MTRRfix4K_C0000:
1169 case MSR_MTRRfix4K_C8000:
1170 case MSR_MTRRfix4K_D0000:
1171 case MSR_MTRRfix4K_D8000:
1172 case MSR_MTRRfix4K_E0000:
1173 case MSR_MTRRfix4K_E8000:
1174 case MSR_MTRRfix4K_F0000:
1175 case MSR_MTRRfix4K_F8000:
1176 case MSR_MTRRdefType:
1177 case MSR_IA32_CR_PAT:
1178 return true;
1179 case 0x2f8:
1180 return true;
1181 }
1182 return false;
1183}
1184
d6289b93
MT		 1185static bool valid_pat_type(unsigned t)
1186{
1187 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1188}
1189
1190static bool valid_mtrr_type(unsigned t)
1191{
1192 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1193}
1194
1195static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1196{
1197 int i;
1198
1199 if (!msr_mtrr_valid(msr))
1200 return false;
1201
1202 if (msr == MSR_IA32_CR_PAT) {
1203 for (i = 0; i < 8; i++)
1204 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1205 return false;
1206 return true;
1207 } else if (msr == MSR_MTRRdefType) {
1208 if (data & ~0xcff)
1209 return false;
1210 return valid_mtrr_type(data & 0xff);
1211 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1212 for (i = 0; i < 8 ; i++)
1213 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1214 return false;
1215 return true;
1216 }
1217
1218 /* variable MTRRs */
1219 return valid_mtrr_type(data & 0xff);
1220}
1221
9ba075a6
AK		 1222static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1223{
0bed3b56
SY		 1224 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1225
d6289b93 1226 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1227 return 1;
1228
0bed3b56
SY		 1229 if (msr == MSR_MTRRdefType) {
1230 vcpu->arch.mtrr_state.def_type = data;
1231 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1232 } else if (msr == MSR_MTRRfix64K_00000)
1233 p[0] = data;
1234 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1235 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1236 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1237 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1238 else if (msr == MSR_IA32_CR_PAT)
1239 vcpu->arch.pat = data;
1240 else { /* Variable MTRRs */
1241 int idx, is_mtrr_mask;
1242 u64 *pt;
1243
1244 idx = (msr - 0x200) / 2;
1245 is_mtrr_mask = msr - 0x200 - 2 * idx;
1246 if (!is_mtrr_mask)
1247 pt =
1248 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1249 else
1250 pt =
1251 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1252 *pt = data;
1253 }
1254
1255 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1256 return 0;
1257}
15c4a640 1258
890ca9ae 1259static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1260{
890ca9ae
HY		 1261 u64 mcg_cap = vcpu->arch.mcg_cap;
1262 unsigned bank_num = mcg_cap & 0xff;
1263
15c4a640 1264 switch (msr) {
15c4a640 1265 case MSR_IA32_MCG_STATUS:
890ca9ae 1266 vcpu->arch.mcg_status = data;
15c4a640 1267 break;
c7ac679c 1268 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1269 if (!(mcg_cap & MCG_CTL_P))
1270 return 1;
1271 if (data != 0 && data != ~(u64)0)
1272 return -1;
1273 vcpu->arch.mcg_ctl = data;
1274 break;
1275 default:
1276 if (msr >= MSR_IA32_MC0_CTL &&
1277 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1278 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1279 /* only 0 or all 1s can be written to IA32_MCi_CTL
1280 * some Linux kernels though clear bit 10 in bank 4 to
1281 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1282 * this to avoid an uncatched #GP in the guest
1283 */
890ca9ae 1284 if ((offset & 0x3) == 0 &&
114be429 1285 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1286 return -1;
1287 vcpu->arch.mce_banks[offset] = data;
1288 break;
1289 }
1290 return 1;
1291 }
1292 return 0;
1293}
1294
ffde22ac
ES		 1295static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1296{
1297 struct kvm *kvm = vcpu->kvm;
1298 int lm = is_long_mode(vcpu);
1299 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1300 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1301 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1302 : kvm->arch.xen_hvm_config.blob_size_32;
1303 u32 page_num = data & ~PAGE_MASK;
1304 u64 page_addr = data & PAGE_MASK;
1305 u8 *page;
1306 int r;
1307
1308 r = -E2BIG;
1309 if (page_num >= blob_size)
1310 goto out;
1311 r = -ENOMEM;
1312 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1313 if (!page)
1314 goto out;
1315 r = -EFAULT;
1316 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1317 goto out_free;
1318 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1319 goto out_free;
1320 r = 0;
1321out_free:
1322 kfree(page);
1323out:
1324 return r;
1325}
1326
55cd8e5a
GN		 1327static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1328{
1329 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1330}
1331
1332static bool kvm_hv_msr_partition_wide(u32 msr)
1333{
1334 bool r = false;
1335 switch (msr) {
1336 case HV_X64_MSR_GUEST_OS_ID:
1337 case HV_X64_MSR_HYPERCALL:
1338 r = true;
1339 break;
1340 }
1341
1342 return r;
1343}
1344
1345static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1346{
1347 struct kvm *kvm = vcpu->kvm;
1348
1349 switch (msr) {
1350 case HV_X64_MSR_GUEST_OS_ID:
1351 kvm->arch.hv_guest_os_id = data;
1352 /* setting guest os id to zero disables hypercall page */
1353 if (!kvm->arch.hv_guest_os_id)
1354 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1355 break;
1356 case HV_X64_MSR_HYPERCALL: {
1357 u64 gfn;
1358 unsigned long addr;
1359 u8 instructions[4];
1360
1361 /* if guest os id is not set hypercall should remain disabled */
1362 if (!kvm->arch.hv_guest_os_id)
1363 break;
1364 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1365 kvm->arch.hv_hypercall = data;
1366 break;
1367 }
1368 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1369 addr = gfn_to_hva(kvm, gfn);
1370 if (kvm_is_error_hva(addr))
1371 return 1;
1372 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1373 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1374 if (copy_to_user((void __user *)addr, instructions, 4))
1375 return 1;
1376 kvm->arch.hv_hypercall = data;
1377 break;
1378 }
1379 default:
1380 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1381 "data 0x%llx\n", msr, data);
1382 return 1;
1383 }
1384 return 0;
1385}
1386
1387static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1388{
10388a07
GN		 1389 switch (msr) {
1390 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1391 unsigned long addr;
55cd8e5a 1392
10388a07
GN		 1393 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1394 vcpu->arch.hv_vapic = data;
1395 break;
1396 }
1397 addr = gfn_to_hva(vcpu->kvm, data >>
1398 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1399 if (kvm_is_error_hva(addr))
1400 return 1;
1401 if (clear_user((void __user *)addr, PAGE_SIZE))
1402 return 1;
1403 vcpu->arch.hv_vapic = data;
1404 break;
1405 }
1406 case HV_X64_MSR_EOI:
1407 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1408 case HV_X64_MSR_ICR:
1409 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1410 case HV_X64_MSR_TPR:
1411 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1412 default:
1413 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1414 "data 0x%llx\n", msr, data);
1415 return 1;
1416 }
1417
1418 return 0;
55cd8e5a
GN		 1419}
1420
15c4a640
CO		 1421int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1422{
1423 switch (msr) {
15c4a640 1424 case MSR_EFER:
b69e8cae 1425 return set_efer(vcpu, data);
8f1589d9
AP		 1426 case MSR_K7_HWCR:
1427 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1428 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1429 if (data != 0) {
1430 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1431 data);
1432 return 1;
1433 }
15c4a640 1434 break;
f7c6d140
AP		 1435 case MSR_FAM10H_MMIO_CONF_BASE:
1436 if (data != 0) {
1437 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1438 "0x%llx\n", data);
1439 return 1;
1440 }
15c4a640 1441 break;
c323c0e5 1442 case MSR_AMD64_NB_CFG:
c7ac679c 1443 break;
b5e2fec0
AG		 1444 case MSR_IA32_DEBUGCTLMSR:
1445 if (!data) {
1446 /* We support the non-activated case already */
1447 break;
1448 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1449 /* Values other than LBR and BTF are vendor-specific,
1450 thus reserved and should throw a #GP */
1451 return 1;
1452 }
1453 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1454 __func__, data);
1455 break;
15c4a640
CO		 1456 case MSR_IA32_UCODE_REV:
1457 case MSR_IA32_UCODE_WRITE:
61a6bd67 1458 case MSR_VM_HSAVE_PA:
6098ca93 1459 case MSR_AMD64_PATCH_LOADER:
15c4a640 1460 break;
9ba075a6
AK		 1461 case 0x200 ... 0x2ff:
1462 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1463 case MSR_IA32_APICBASE:
1464 kvm_set_apic_base(vcpu, data);
1465 break;
0105d1a5
GN		 1466 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1467 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1468 case MSR_IA32_MISC_ENABLE:
ad312c7c 1469 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1470 break;
11c6bffa 1471 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1472 case MSR_KVM_WALL_CLOCK:
1473 vcpu->kvm->arch.wall_clock = data;
1474 kvm_write_wall_clock(vcpu->kvm, data);
1475 break;
11c6bffa 1476 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1477 case MSR_KVM_SYSTEM_TIME: {
1478 if (vcpu->arch.time_page) {
1479 kvm_release_page_dirty(vcpu->arch.time_page);
1480 vcpu->arch.time_page = NULL;
1481 }
1482
1483 vcpu->arch.time = data;
c285545f 1484 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1485
1486 /* we verify if the enable bit is set... */
1487 if (!(data & 1))
1488 break;
1489
1490 /* ...but clean it before doing the actual write */
1491 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1492
18068523
GOC		 1493 vcpu->arch.time_page =
1494 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1495
1496 if (is_error_page(vcpu->arch.time_page)) {
1497 kvm_release_page_clean(vcpu->arch.time_page);
1498 vcpu->arch.time_page = NULL;
1499 }
18068523
GOC		 1500 break;
1501 }
890ca9ae
HY		 1502 case MSR_IA32_MCG_CTL:
1503 case MSR_IA32_MCG_STATUS:
1504 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1505 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1506
1507 /* Performance counters are not protected by a CPUID bit,
1508 * so we should check all of them in the generic path for the sake of
1509 * cross vendor migration.
1510 * Writing a zero into the event select MSRs disables them,
1511 * which we perfectly emulate ;-). Any other value should be at least
1512 * reported, some guests depend on them.
1513 */
1514 case MSR_P6_EVNTSEL0:
1515 case MSR_P6_EVNTSEL1:
1516 case MSR_K7_EVNTSEL0:
1517 case MSR_K7_EVNTSEL1:
1518 case MSR_K7_EVNTSEL2:
1519 case MSR_K7_EVNTSEL3:
1520 if (data != 0)
1521 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1522 "0x%x data 0x%llx\n", msr, data);
1523 break;
1524 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1525 * so we ignore writes to make it happy.
1526 */
1527 case MSR_P6_PERFCTR0:
1528 case MSR_P6_PERFCTR1:
1529 case MSR_K7_PERFCTR0:
1530 case MSR_K7_PERFCTR1:
1531 case MSR_K7_PERFCTR2:
1532 case MSR_K7_PERFCTR3:
1533 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1534 "0x%x data 0x%llx\n", msr, data);
1535 break;
84e0cefa
JS		 1536 case MSR_K7_CLK_CTL:
1537 /*
1538 * Ignore all writes to this no longer documented MSR.
1539 * Writes are only relevant for old K7 processors,
1540 * all pre-dating SVM, but a recommended workaround from
1541 * AMD for these chips. It is possible to speicify the
1542 * affected processor models on the command line, hence
1543 * the need to ignore the workaround.
1544 */
1545 break;
55cd8e5a
GN		 1546 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1547 if (kvm_hv_msr_partition_wide(msr)) {
1548 int r;
1549 mutex_lock(&vcpu->kvm->lock);
1550 r = set_msr_hyperv_pw(vcpu, msr, data);
1551 mutex_unlock(&vcpu->kvm->lock);
1552 return r;
1553 } else
1554 return set_msr_hyperv(vcpu, msr, data);
1555 break;
15c4a640 1556 default:
ffde22ac
ES		 1557 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1558 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1559 if (!ignore_msrs) {
1560 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1561 msr, data);
1562 return 1;
1563 } else {
1564 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1565 msr, data);
1566 break;
1567 }
15c4a640
CO		 1568 }
1569 return 0;
1570}
1571EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1572
1573
1574/*
1575 * Reads an msr value (of 'msr_index') into 'pdata'.
1576 * Returns 0 on success, non-0 otherwise.
1577 * Assumes vcpu_load() was already called.
1578 */
1579int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1580{
1581 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1582}
1583
9ba075a6
AK		 1584static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1585{
0bed3b56
SY		 1586 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1587
9ba075a6
AK		 1588 if (!msr_mtrr_valid(msr))
1589 return 1;
1590
0bed3b56
SY		 1591 if (msr == MSR_MTRRdefType)
1592 *pdata = vcpu->arch.mtrr_state.def_type +
1593 (vcpu->arch.mtrr_state.enabled << 10);
1594 else if (msr == MSR_MTRRfix64K_00000)
1595 *pdata = p[0];
1596 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1597 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1598 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1599 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1600 else if (msr == MSR_IA32_CR_PAT)
1601 *pdata = vcpu->arch.pat;
1602 else { /* Variable MTRRs */
1603 int idx, is_mtrr_mask;
1604 u64 *pt;
1605
1606 idx = (msr - 0x200) / 2;
1607 is_mtrr_mask = msr - 0x200 - 2 * idx;
1608 if (!is_mtrr_mask)
1609 pt =
1610 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1611 else
1612 pt =
1613 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1614 *pdata = *pt;
1615 }
1616
9ba075a6
AK		 1617 return 0;
1618}
1619
890ca9ae 1620static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1621{
1622 u64 data;
890ca9ae
HY		 1623 u64 mcg_cap = vcpu->arch.mcg_cap;
1624 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1625
1626 switch (msr) {
15c4a640
CO		 1627 case MSR_IA32_P5_MC_ADDR:
1628 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1629 data = 0;
1630 break;
15c4a640 1631 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1632 data = vcpu->arch.mcg_cap;
1633 break;
c7ac679c 1634 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1635 if (!(mcg_cap & MCG_CTL_P))
1636 return 1;
1637 data = vcpu->arch.mcg_ctl;
1638 break;
1639 case MSR_IA32_MCG_STATUS:
1640 data = vcpu->arch.mcg_status;
1641 break;
1642 default:
1643 if (msr >= MSR_IA32_MC0_CTL &&
1644 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1645 u32 offset = msr - MSR_IA32_MC0_CTL;
1646 data = vcpu->arch.mce_banks[offset];
1647 break;
1648 }
1649 return 1;
1650 }
1651 *pdata = data;
1652 return 0;
1653}
1654
55cd8e5a
GN		 1655static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1656{
1657 u64 data = 0;
1658 struct kvm *kvm = vcpu->kvm;
1659
1660 switch (msr) {
1661 case HV_X64_MSR_GUEST_OS_ID:
1662 data = kvm->arch.hv_guest_os_id;
1663 break;
1664 case HV_X64_MSR_HYPERCALL:
1665 data = kvm->arch.hv_hypercall;
1666 break;
1667 default:
1668 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1669 return 1;
1670 }
1671
1672 *pdata = data;
1673 return 0;
1674}
1675
1676static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1677{
1678 u64 data = 0;
1679
1680 switch (msr) {
1681 case HV_X64_MSR_VP_INDEX: {
1682 int r;
1683 struct kvm_vcpu *v;
1684 kvm_for_each_vcpu(r, v, vcpu->kvm)
1685 if (v == vcpu)
1686 data = r;
1687 break;
1688 }
10388a07
GN		 1689 case HV_X64_MSR_EOI:
1690 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1691 case HV_X64_MSR_ICR:
1692 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1693 case HV_X64_MSR_TPR:
1694 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1695 default:
1696 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1697 return 1;
1698 }
1699 *pdata = data;
1700 return 0;
1701}
1702
890ca9ae
HY		 1703int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1704{
1705 u64 data;
1706
1707 switch (msr) {
890ca9ae 1708 case MSR_IA32_PLATFORM_ID:
15c4a640 1709 case MSR_IA32_UCODE_REV:
15c4a640 1710 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1711 case MSR_IA32_DEBUGCTLMSR:
1712 case MSR_IA32_LASTBRANCHFROMIP:
1713 case MSR_IA32_LASTBRANCHTOIP:
1714 case MSR_IA32_LASTINTFROMIP:
1715 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1716 case MSR_K8_SYSCFG:
1717 case MSR_K7_HWCR:
61a6bd67 1718 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1719 case MSR_P6_PERFCTR0:
1720 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1721 case MSR_P6_EVNTSEL0:
1722 case MSR_P6_EVNTSEL1:
9e699624 1723 case MSR_K7_EVNTSEL0:
1f3ee616 1724 case MSR_K7_PERFCTR0:
1fdbd48c 1725 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1726 case MSR_AMD64_NB_CFG:
f7c6d140 1727 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1728 data = 0;
1729 break;
9ba075a6
AK		 1730 case MSR_MTRRcap:
1731 data = 0x500 | KVM_NR_VAR_MTRR;
1732 break;
1733 case 0x200 ... 0x2ff:
1734 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1735 case 0xcd: /* fsb frequency */
1736 data = 3;
1737 break;
7b914098
JS		 1738 /*
1739 * MSR_EBC_FREQUENCY_ID
1740 * Conservative value valid for even the basic CPU models.
1741 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1742 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1743 * and 266MHz for model 3, or 4. Set Core Clock
1744 * Frequency to System Bus Frequency Ratio to 1 (bits
1745 * 31:24) even though these are only valid for CPU
1746 * models > 2, however guests may end up dividing or
1747 * multiplying by zero otherwise.
1748 */
1749 case MSR_EBC_FREQUENCY_ID:
1750 data = 1 << 24;
1751 break;
15c4a640
CO		 1752 case MSR_IA32_APICBASE:
1753 data = kvm_get_apic_base(vcpu);
1754 break;
0105d1a5
GN		 1755 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1756 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1757 break;
15c4a640 1758 case MSR_IA32_MISC_ENABLE:
ad312c7c 1759 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1760 break;
847f0ad8
AG		 1761 case MSR_IA32_PERF_STATUS:
1762 /* TSC increment by tick */
1763 data = 1000ULL;
1764 /* CPU multiplier */
1765 data |= (((uint64_t)4ULL) << 40);
1766 break;
15c4a640 1767 case MSR_EFER:
f6801dff 1768 data = vcpu->arch.efer;
15c4a640 1769 break;
18068523 1770 case MSR_KVM_WALL_CLOCK:
11c6bffa 1771 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1772 data = vcpu->kvm->arch.wall_clock;
1773 break;
1774 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1775 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1776 data = vcpu->arch.time;
1777 break;
890ca9ae
HY		 1778 case MSR_IA32_P5_MC_ADDR:
1779 case MSR_IA32_P5_MC_TYPE:
1780 case MSR_IA32_MCG_CAP:
1781 case MSR_IA32_MCG_CTL:
1782 case MSR_IA32_MCG_STATUS:
1783 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1784 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1785 case MSR_K7_CLK_CTL:
1786 /*
1787 * Provide expected ramp-up count for K7. All other
1788 * are set to zero, indicating minimum divisors for
1789 * every field.
1790 *
1791 * This prevents guest kernels on AMD host with CPU
1792 * type 6, model 8 and higher from exploding due to
1793 * the rdmsr failing.
1794 */
1795 data = 0x20000000;
1796 break;
55cd8e5a
GN		 1797 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1798 if (kvm_hv_msr_partition_wide(msr)) {
1799 int r;
1800 mutex_lock(&vcpu->kvm->lock);
1801 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1802 mutex_unlock(&vcpu->kvm->lock);
1803 return r;
1804 } else
1805 return get_msr_hyperv(vcpu, msr, pdata);
1806 break;
15c4a640 1807 default:
ed85c068
AP		 1808 if (!ignore_msrs) {
1809 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1810 return 1;
1811 } else {
1812 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1813 data = 0;
1814 }
1815 break;
15c4a640
CO		 1816 }
1817 *pdata = data;
1818 return 0;
1819}
1820EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1821
313a3dc7
CO		 1822/*
1823 * Read or write a bunch of msrs. All parameters are kernel addresses.
1824 *
1825 * @return number of msrs set successfully.
1826 */
1827static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1828 struct kvm_msr_entry *entries,
1829 int (*do_msr)(struct kvm_vcpu *vcpu,
1830 unsigned index, u64 *data))
1831{
f656ce01 1832 int i, idx;
313a3dc7 1833
f656ce01 1834 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1835 for (i = 0; i < msrs->nmsrs; ++i)
1836 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1837 break;
f656ce01 1838 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1839
313a3dc7
CO		 1840 return i;
1841}
1842
1843/*
1844 * Read or write a bunch of msrs. Parameters are user addresses.
1845 *
1846 * @return number of msrs set successfully.
1847 */
1848static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1849 int (*do_msr)(struct kvm_vcpu *vcpu,
1850 unsigned index, u64 *data),
1851 int writeback)
1852{
1853 struct kvm_msrs msrs;
1854 struct kvm_msr_entry *entries;
1855 int r, n;
1856 unsigned size;
1857
1858 r = -EFAULT;
1859 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1860 goto out;
1861
1862 r = -E2BIG;
1863 if (msrs.nmsrs >= MAX_IO_MSRS)
1864 goto out;
1865
1866 r = -ENOMEM;
1867 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1868 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1869 if (!entries)
1870 goto out;
1871
1872 r = -EFAULT;
1873 if (copy_from_user(entries, user_msrs->entries, size))
1874 goto out_free;
1875
1876 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1877 if (r < 0)
1878 goto out_free;
1879
1880 r = -EFAULT;
1881 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1882 goto out_free;
1883
1884 r = n;
1885
1886out_free:
7a73c028 1887 kfree(entries);
313a3dc7
CO		 1888out:
1889 return r;
1890}
1891
018d00d2
ZX		 1892int kvm_dev_ioctl_check_extension(long ext)
1893{
1894 int r;
1895
1896 switch (ext) {
1897 case KVM_CAP_IRQCHIP:
1898 case KVM_CAP_HLT:
1899 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1900 case KVM_CAP_SET_TSS_ADDR:
07716717 1901 case KVM_CAP_EXT_CPUID:
c8076604 1902 case KVM_CAP_CLOCKSOURCE:
7837699f 1903 case KVM_CAP_PIT:
a28e4f5a 1904 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1905 case KVM_CAP_MP_STATE:
ed848624 1906 case KVM_CAP_SYNC_MMU:
52d939a0 1907 case KVM_CAP_REINJECT_CONTROL:
4925663a 1908 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1909 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1910 case KVM_CAP_IRQFD:
d34e6b17 1911 case KVM_CAP_IOEVENTFD:
c5ff41ce 1912 case KVM_CAP_PIT2:
e9f42757 1913 case KVM_CAP_PIT_STATE2:
b927a3ce 1914 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1915 case KVM_CAP_XEN_HVM:
afbcf7ab 1916 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1917 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1918 case KVM_CAP_HYPERV:
10388a07 1919 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1920 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1921 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1922 case KVM_CAP_DEBUGREGS:
d2be1651 1923 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1924 case KVM_CAP_XSAVE:
018d00d2
ZX		 1925 r = 1;
1926 break;
542472b5
LV		 1927 case KVM_CAP_COALESCED_MMIO:
1928 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1929 break;
774ead3a
AK		 1930 case KVM_CAP_VAPIC:
1931 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1932 break;
f725230a
AK		 1933 case KVM_CAP_NR_VCPUS:
1934 r = KVM_MAX_VCPUS;
1935 break;
a988b910
AK		 1936 case KVM_CAP_NR_MEMSLOTS:
1937 r = KVM_MEMORY_SLOTS;
1938 break;
a68a6a72
MT		 1939 case KVM_CAP_PV_MMU: /* obsolete */
1940 r = 0;
2f333bcb 1941 break;
62c476c7 1942 case KVM_CAP_IOMMU:
19de40a8 1943 r = iommu_found();
62c476c7 1944 break;
890ca9ae
HY		 1945 case KVM_CAP_MCE:
1946 r = KVM_MAX_MCE_BANKS;
1947 break;
2d5b5a66
SY		 1948 case KVM_CAP_XCRS:
1949 r = cpu_has_xsave;
1950 break;
018d00d2
ZX		 1951 default:
1952 r = 0;
1953 break;
1954 }
1955 return r;
1956
1957}
1958
043405e1
CO		 1959long kvm_arch_dev_ioctl(struct file *filp,
1960 unsigned int ioctl, unsigned long arg)
1961{
1962 void __user *argp = (void __user *)arg;
1963 long r;
1964
1965 switch (ioctl) {
1966 case KVM_GET_MSR_INDEX_LIST: {
1967 struct kvm_msr_list __user *user_msr_list = argp;
1968 struct kvm_msr_list msr_list;
1969 unsigned n;
1970
1971 r = -EFAULT;
1972 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1973 goto out;
1974 n = msr_list.nmsrs;
1975 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1976 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1977 goto out;
1978 r = -E2BIG;
e125e7b6 1979 if (n < msr_list.nmsrs)
043405e1
CO		 1980 goto out;
1981 r = -EFAULT;
1982 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1983 num_msrs_to_save * sizeof(u32)))
1984 goto out;
e125e7b6 1985 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1986 &emulated_msrs,
1987 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1988 goto out;
1989 r = 0;
1990 break;
1991 }
674eea0f
AK		 1992 case KVM_GET_SUPPORTED_CPUID: {
1993 struct kvm_cpuid2 __user *cpuid_arg = argp;
1994 struct kvm_cpuid2 cpuid;
1995
1996 r = -EFAULT;
1997 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1998 goto out;
1999 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2000 cpuid_arg->entries);
674eea0f
AK		 2001 if (r)
2002 goto out;
2003
2004 r = -EFAULT;
2005 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2006 goto out;
2007 r = 0;
2008 break;
2009 }
890ca9ae
HY		 2010 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2011 u64 mce_cap;
2012
2013 mce_cap = KVM_MCE_CAP_SUPPORTED;
2014 r = -EFAULT;
2015 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2016 goto out;
2017 r = 0;
2018 break;
2019 }
043405e1
CO		 2020 default:
2021 r = -EINVAL;
2022 }
2023out:
2024 return r;
2025}
2026
f5f48ee1
SY		 2027static void wbinvd_ipi(void *garbage)
2028{
2029 wbinvd();
2030}
2031
2032static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2033{
2034 return vcpu->kvm->arch.iommu_domain &&
2035 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2036}
2037
313a3dc7
CO		 2038void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2039{
f5f48ee1
SY		 2040 /* Address WBINVD may be executed by guest */
2041 if (need_emulate_wbinvd(vcpu)) {
2042 if (kvm_x86_ops->has_wbinvd_exit())
2043 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2044 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2045 smp_call_function_single(vcpu->cpu,
2046 wbinvd_ipi, NULL, 1);
2047 }
2048
313a3dc7 2049 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2050 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2051 /* Make sure TSC doesn't go backwards */
2052 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2053 native_read_tsc() - vcpu->arch.last_host_tsc;
2054 if (tsc_delta < 0)
2055 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2056 if (check_tsc_unstable()) {
e48672fa 2057 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2058 vcpu->arch.tsc_catchup = 1;
2059 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2060 }
2061 if (vcpu->cpu != cpu)
2062 kvm_migrate_timers(vcpu);
e48672fa 2063 vcpu->cpu = cpu;
6b7d7e76 2064 }
313a3dc7
CO		 2065}
2066
2067void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2068{
02daab21 2069 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2070 kvm_put_guest_fpu(vcpu);
e48672fa 2071 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2072}
2073
07716717 2074static int is_efer_nx(void)
313a3dc7 2075{
e286e86e 2076 unsigned long long efer = 0;
313a3dc7 2077
e286e86e 2078 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2079 return efer & EFER_NX;
2080}
2081
2082static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2083{
2084 int i;
2085 struct kvm_cpuid_entry2 *e, *entry;
2086
313a3dc7 2087 entry = NULL;
ad312c7c
ZX		 2088 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2089 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2090 if (e->function == 0x80000001) {
2091 entry = e;
2092 break;
2093 }
2094 }
07716717 2095 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2096 entry->edx &= ~(1 << 20);
2097 printk(KERN_INFO "kvm: guest NX capability removed\n");
2098 }
2099}
2100
07716717 2101/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2102static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2103 struct kvm_cpuid *cpuid,
2104 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2105{
2106 int r, i;
2107 struct kvm_cpuid_entry *cpuid_entries;
2108
2109 r = -E2BIG;
2110 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2111 goto out;
2112 r = -ENOMEM;
2113 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2114 if (!cpuid_entries)
2115 goto out;
2116 r = -EFAULT;
2117 if (copy_from_user(cpuid_entries, entries,
2118 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2119 goto out_free;
2120 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2121 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2122 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2123 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2124 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2125 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2126 vcpu->arch.cpuid_entries[i].index = 0;
2127 vcpu->arch.cpuid_entries[i].flags = 0;
2128 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2129 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2130 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2131 }
2132 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2133 cpuid_fix_nx_cap(vcpu);
2134 r = 0;
fc61b800 2135 kvm_apic_set_version(vcpu);
0e851880 2136 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2137 update_cpuid(vcpu);
07716717
DK		 2138
2139out_free:
2140 vfree(cpuid_entries);
2141out:
2142 return r;
2143}
2144
2145static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2146 struct kvm_cpuid2 *cpuid,
2147 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2148{
2149 int r;
2150
2151 r = -E2BIG;
2152 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2153 goto out;
2154 r = -EFAULT;
ad312c7c 2155 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2156 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2157 goto out;
ad312c7c 2158 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2159 kvm_apic_set_version(vcpu);
0e851880 2160 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2161 update_cpuid(vcpu);
313a3dc7
CO		 2162 return 0;
2163
2164out:
2165 return r;
2166}
2167
07716717 2168static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2169 struct kvm_cpuid2 *cpuid,
2170 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2171{
2172 int r;
2173
2174 r = -E2BIG;
ad312c7c 2175 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2176 goto out;
2177 r = -EFAULT;
ad312c7c 2178 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2179 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2180 goto out;
2181 return 0;
2182
2183out:
ad312c7c 2184 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2185 return r;
2186}
2187
07716717 2188static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2189 u32 index)
07716717
DK		 2190{
2191 entry->function = function;
2192 entry->index = index;
2193 cpuid_count(entry->function, entry->index,
19355475 2194 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2195 entry->flags = 0;
2196}
2197
7faa4ee1
AK		 2198#define F(x) bit(X86_FEATURE_##x)
2199
07716717
DK		 2200static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2201 u32 index, int *nent, int maxnent)
2202{
7faa4ee1 2203 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2204#ifdef CONFIG_X86_64
17cc3935
SY		 2205 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2206 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2207 unsigned f_lm = F(LM);
2208#else
17cc3935 2209 unsigned f_gbpages = 0;
7faa4ee1 2210 unsigned f_lm = 0;
07716717 2211#endif
4e47c7a6 2212 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2213
2214 /* cpuid 1.edx */
2215 const u32 kvm_supported_word0_x86_features =
2216 F(FPU) | F(VME) | F(DE) | F(PSE) |
2217 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2218 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2219 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2220 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2221 0 /* Reserved, DS, ACPI */ | F(MMX) |
2222 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2223 0 /* HTT, TM, Reserved, PBE */;
2224 /* cpuid 0x80000001.edx */
2225 const u32 kvm_supported_word1_x86_features =
2226 F(FPU) | F(VME) | F(DE) | F(PSE) |
2227 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2228 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2229 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2230 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2231 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2232 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2233 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2234 /* cpuid 1.ecx */
2235 const u32 kvm_supported_word4_x86_features =
6c3f6041 2236 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2237 0 /* DS-CPL, VMX, SMX, EST */ |
2238 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2239 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2240 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2241 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2242 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2243 F(F16C);
7faa4ee1 2244 /* cpuid 0x80000001.ecx */
07716717 2245 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2246 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2247 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2248 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2249 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2250
19355475 2251 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2252 get_cpu();
2253 do_cpuid_1_ent(entry, function, index);
2254 ++*nent;
2255
2256 switch (function) {
2257 case 0:
2acf923e 2258 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2259 break;
2260 case 1:
2261 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2262 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2263 /* we support x2apic emulation even if host does not support
2264 * it since we emulate x2apic in software */
2265 entry->ecx |= F(X2APIC);
07716717
DK		 2266 break;
2267 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2268 * may return different values. This forces us to get_cpu() before
2269 * issuing the first command, and also to emulate this annoying behavior
2270 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2271 case 2: {
2272 int t, times = entry->eax & 0xff;
2273
2274 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2275 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2276 for (t = 1; t < times && *nent < maxnent; ++t) {
2277 do_cpuid_1_ent(&entry[t], function, 0);
2278 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2279 ++*nent;
2280 }
2281 break;
2282 }
2283 /* function 4 and 0xb have additional index. */
2284 case 4: {
14af3f3c 2285 int i, cache_type;
07716717
DK		 2286
2287 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2288 /* read more entries until cache_type is zero */
14af3f3c
HH		 2289 for (i = 1; *nent < maxnent; ++i) {
2290 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2291 if (!cache_type)
2292 break;
14af3f3c
HH		 2293 do_cpuid_1_ent(&entry[i], function, i);
2294 entry[i].flags |=
07716717
DK		 2295 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2296 ++*nent;
2297 }
2298 break;
2299 }
2300 case 0xb: {
14af3f3c 2301 int i, level_type;
07716717
DK		 2302
2303 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2304 /* read more entries until level_type is zero */
14af3f3c 2305 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2306 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2307 if (!level_type)
2308 break;
14af3f3c
HH		 2309 do_cpuid_1_ent(&entry[i], function, i);
2310 entry[i].flags |=
07716717
DK		 2311 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2312 ++*nent;
2313 }
2314 break;
2315 }
2acf923e
DC		 2316 case 0xd: {
2317 int i;
2318
2319 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2320 for (i = 1; *nent < maxnent; ++i) {
2321 if (entry[i - 1].eax == 0 && i != 2)
2322 break;
2323 do_cpuid_1_ent(&entry[i], function, i);
2324 entry[i].flags |=
2325 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2326 ++*nent;
2327 }
2328 break;
2329 }
84478c82
GC		 2330 case KVM_CPUID_SIGNATURE: {
2331 char signature[12] = "KVMKVMKVM\0\0";
2332 u32 *sigptr = (u32 *)signature;
2333 entry->eax = 0;
2334 entry->ebx = sigptr[0];
2335 entry->ecx = sigptr[1];
2336 entry->edx = sigptr[2];
2337 break;
2338 }
2339 case KVM_CPUID_FEATURES:
2340 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2341 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2342 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2343 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2344 entry->ebx = 0;
2345 entry->ecx = 0;
2346 entry->edx = 0;
2347 break;
07716717
DK		 2348 case 0x80000000:
2349 entry->eax = min(entry->eax, 0x8000001a);
2350 break;
2351 case 0x80000001:
2352 entry->edx &= kvm_supported_word1_x86_features;
2353 entry->ecx &= kvm_supported_word6_x86_features;
2354 break;
2355 }
d4330ef2
JR		 2356
2357 kvm_x86_ops->set_supported_cpuid(function, entry);
2358
07716717
DK		 2359 put_cpu();
2360}
2361
7faa4ee1
AK		 2362#undef F
2363
674eea0f 2364static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2365 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2366{
2367 struct kvm_cpuid_entry2 *cpuid_entries;
2368 int limit, nent = 0, r = -E2BIG;
2369 u32 func;
2370
2371 if (cpuid->nent < 1)
2372 goto out;
6a544355
AK		 2373 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2374 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2375 r = -ENOMEM;
2376 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2377 if (!cpuid_entries)
2378 goto out;
2379
2380 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2381 limit = cpuid_entries[0].eax;
2382 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2383 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2384 &nent, cpuid->nent);
07716717
DK		 2385 r = -E2BIG;
2386 if (nent >= cpuid->nent)
2387 goto out_free;
2388
2389 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2390 limit = cpuid_entries[nent - 1].eax;
2391 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2392 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2393 &nent, cpuid->nent);
84478c82
GC		 2394
2395
2396
2397 r = -E2BIG;
2398 if (nent >= cpuid->nent)
2399 goto out_free;
2400
2401 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2402 cpuid->nent);
2403
2404 r = -E2BIG;
2405 if (nent >= cpuid->nent)
2406 goto out_free;
2407
2408 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2409 cpuid->nent);
2410
cb007648
MM		 2411 r = -E2BIG;
2412 if (nent >= cpuid->nent)
2413 goto out_free;
2414
07716717
DK		 2415 r = -EFAULT;
2416 if (copy_to_user(entries, cpuid_entries,
19355475 2417 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2418 goto out_free;
2419 cpuid->nent = nent;
2420 r = 0;
2421
2422out_free:
2423 vfree(cpuid_entries);
2424out:
2425 return r;
2426}
2427
313a3dc7
CO		 2428static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2429 struct kvm_lapic_state *s)
2430{
ad312c7c 2431 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2432
2433 return 0;
2434}
2435
2436static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2437 struct kvm_lapic_state *s)
2438{
ad312c7c 2439 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2440 kvm_apic_post_state_restore(vcpu);
cb142eb7 2441 update_cr8_intercept(vcpu);
313a3dc7
CO		 2442
2443 return 0;
2444}
2445
f77bc6a4
ZX		 2446static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2447 struct kvm_interrupt *irq)
2448{
2449 if (irq->irq < 0 || irq->irq >= 256)
2450 return -EINVAL;
2451 if (irqchip_in_kernel(vcpu->kvm))
2452 return -ENXIO;
f77bc6a4 2453
66fd3f7f 2454 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2455 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2456
f77bc6a4
ZX		 2457 return 0;
2458}
2459
c4abb7c9
JK		 2460static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2461{
c4abb7c9 2462 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2463
2464 return 0;
2465}
2466
b209749f
AK		 2467static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2468 struct kvm_tpr_access_ctl *tac)
2469{
2470 if (tac->flags)
2471 return -EINVAL;
2472 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2473 return 0;
2474}
2475
890ca9ae
HY		 2476static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2477 u64 mcg_cap)
2478{
2479 int r;
2480 unsigned bank_num = mcg_cap & 0xff, bank;
2481
2482 r = -EINVAL;
a9e38c3e 2483 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2484 goto out;
2485 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2486 goto out;
2487 r = 0;
2488 vcpu->arch.mcg_cap = mcg_cap;
2489 /* Init IA32_MCG_CTL to all 1s */
2490 if (mcg_cap & MCG_CTL_P)
2491 vcpu->arch.mcg_ctl = ~(u64)0;
2492 /* Init IA32_MCi_CTL to all 1s */
2493 for (bank = 0; bank < bank_num; bank++)
2494 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2495out:
2496 return r;
2497}
2498
2499static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2500 struct kvm_x86_mce *mce)
2501{
2502 u64 mcg_cap = vcpu->arch.mcg_cap;
2503 unsigned bank_num = mcg_cap & 0xff;
2504 u64 *banks = vcpu->arch.mce_banks;
2505
2506 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2507 return -EINVAL;
2508 /*
2509 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2510 * reporting is disabled
2511 */
2512 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2513 vcpu->arch.mcg_ctl != ~(u64)0)
2514 return 0;
2515 banks += 4 * mce->bank;
2516 /*
2517 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2518 * reporting is disabled for the bank
2519 */
2520 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2521 return 0;
2522 if (mce->status & MCI_STATUS_UC) {
2523 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2524 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2525 printk(KERN_DEBUG "kvm: set_mce: "
2526 "injects mce exception while "
2527 "previous one is in progress!\n");
a8eeb04a 2528 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2529 return 0;
2530 }
2531 if (banks[1] & MCI_STATUS_VAL)
2532 mce->status |= MCI_STATUS_OVER;
2533 banks[2] = mce->addr;
2534 banks[3] = mce->misc;
2535 vcpu->arch.mcg_status = mce->mcg_status;
2536 banks[1] = mce->status;
2537 kvm_queue_exception(vcpu, MC_VECTOR);
2538 } else if (!(banks[1] & MCI_STATUS_VAL)
2539 || !(banks[1] & MCI_STATUS_UC)) {
2540 if (banks[1] & MCI_STATUS_VAL)
2541 mce->status |= MCI_STATUS_OVER;
2542 banks[2] = mce->addr;
2543 banks[3] = mce->misc;
2544 banks[1] = mce->status;
2545 } else
2546 banks[1] |= MCI_STATUS_OVER;
2547 return 0;
2548}
2549
3cfc3092
JK		 2550static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2551 struct kvm_vcpu_events *events)
2552{
03b82a30
JK		 2553 events->exception.injected =
2554 vcpu->arch.exception.pending &&
2555 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2556 events->exception.nr = vcpu->arch.exception.nr;
2557 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2558 events->exception.pad = 0;
3cfc3092
JK		 2559 events->exception.error_code = vcpu->arch.exception.error_code;
2560
03b82a30
JK		 2561 events->interrupt.injected =
2562 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2563 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2564 events->interrupt.soft = 0;
48005f64
JK		 2565 events->interrupt.shadow =
2566 kvm_x86_ops->get_interrupt_shadow(vcpu,
2567 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2568
2569 events->nmi.injected = vcpu->arch.nmi_injected;
2570 events->nmi.pending = vcpu->arch.nmi_pending;
2571 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2572 events->nmi.pad = 0;
3cfc3092
JK		 2573
2574 events->sipi_vector = vcpu->arch.sipi_vector;
2575
dab4b911 2576 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2577 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2578 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2579 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2580}
2581
2582static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2583 struct kvm_vcpu_events *events)
2584{
dab4b911 2585 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2586 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2587 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2588 return -EINVAL;
2589
3cfc3092
JK		 2590 vcpu->arch.exception.pending = events->exception.injected;
2591 vcpu->arch.exception.nr = events->exception.nr;
2592 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2593 vcpu->arch.exception.error_code = events->exception.error_code;
2594
2595 vcpu->arch.interrupt.pending = events->interrupt.injected;
2596 vcpu->arch.interrupt.nr = events->interrupt.nr;
2597 vcpu->arch.interrupt.soft = events->interrupt.soft;
2598 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2599 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2600 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2601 kvm_x86_ops->set_interrupt_shadow(vcpu,
2602 events->interrupt.shadow);
3cfc3092
JK		 2603
2604 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2605 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2606 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2607 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2608
dab4b911
JK		 2609 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2610 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2611
3842d135
AK		 2612 kvm_make_request(KVM_REQ_EVENT, vcpu);
2613
3cfc3092
JK		 2614 return 0;
2615}
2616
a1efbe77
JK		 2617static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2618 struct kvm_debugregs *dbgregs)
2619{
a1efbe77
JK		 2620 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2621 dbgregs->dr6 = vcpu->arch.dr6;
2622 dbgregs->dr7 = vcpu->arch.dr7;
2623 dbgregs->flags = 0;
97e69aa6 2624 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2625}
2626
2627static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2628 struct kvm_debugregs *dbgregs)
2629{
2630 if (dbgregs->flags)
2631 return -EINVAL;
2632
a1efbe77
JK		 2633 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2634 vcpu->arch.dr6 = dbgregs->dr6;
2635 vcpu->arch.dr7 = dbgregs->dr7;
2636
a1efbe77
JK		 2637 return 0;
2638}
2639
2d5b5a66
SY		 2640static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2641 struct kvm_xsave *guest_xsave)
2642{
2643 if (cpu_has_xsave)
2644 memcpy(guest_xsave->region,
2645 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2646 xstate_size);
2d5b5a66
SY		 2647 else {
2648 memcpy(guest_xsave->region,
2649 &vcpu->arch.guest_fpu.state->fxsave,
2650 sizeof(struct i387_fxsave_struct));
2651 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2652 XSTATE_FPSSE;
2653 }
2654}
2655
2656static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2657 struct kvm_xsave *guest_xsave)
2658{
2659 u64 xstate_bv =
2660 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2661
2662 if (cpu_has_xsave)
2663 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2664 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2665 else {
2666 if (xstate_bv & ~XSTATE_FPSSE)
2667 return -EINVAL;
2668 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2669 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2670 }
2671 return 0;
2672}
2673
2674static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2675 struct kvm_xcrs *guest_xcrs)
2676{
2677 if (!cpu_has_xsave) {
2678 guest_xcrs->nr_xcrs = 0;
2679 return;
2680 }
2681
2682 guest_xcrs->nr_xcrs = 1;
2683 guest_xcrs->flags = 0;
2684 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2685 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2686}
2687
2688static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2689 struct kvm_xcrs *guest_xcrs)
2690{
2691 int i, r = 0;
2692
2693 if (!cpu_has_xsave)
2694 return -EINVAL;
2695
2696 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2697 return -EINVAL;
2698
2699 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2700 /* Only support XCR0 currently */
2701 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2702 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2703 guest_xcrs->xcrs[0].value);
2704 break;
2705 }
2706 if (r)
2707 r = -EINVAL;
2708 return r;
2709}
2710
313a3dc7
CO		 2711long kvm_arch_vcpu_ioctl(struct file *filp,
2712 unsigned int ioctl, unsigned long arg)
2713{
2714 struct kvm_vcpu *vcpu = filp->private_data;
2715 void __user *argp = (void __user *)arg;
2716 int r;
d1ac91d8
AK		 2717 union {
2718 struct kvm_lapic_state *lapic;
2719 struct kvm_xsave *xsave;
2720 struct kvm_xcrs *xcrs;
2721 void *buffer;
2722 } u;
2723
2724 u.buffer = NULL;
313a3dc7
CO		 2725 switch (ioctl) {
2726 case KVM_GET_LAPIC: {
2204ae3c
MT		 2727 r = -EINVAL;
2728 if (!vcpu->arch.apic)
2729 goto out;
d1ac91d8 2730 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2731
b772ff36 2732 r = -ENOMEM;
d1ac91d8 2733 if (!u.lapic)
b772ff36 2734 goto out;
d1ac91d8 2735 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2736 if (r)
2737 goto out;
2738 r = -EFAULT;
d1ac91d8 2739 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2740 goto out;
2741 r = 0;
2742 break;
2743 }
2744 case KVM_SET_LAPIC: {
2204ae3c
MT		 2745 r = -EINVAL;
2746 if (!vcpu->arch.apic)
2747 goto out;
d1ac91d8 2748 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2749 r = -ENOMEM;
d1ac91d8 2750 if (!u.lapic)
b772ff36 2751 goto out;
313a3dc7 2752 r = -EFAULT;
d1ac91d8 2753 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2754 goto out;
d1ac91d8 2755 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2756 if (r)
2757 goto out;
2758 r = 0;
2759 break;
2760 }
f77bc6a4
ZX		 2761 case KVM_INTERRUPT: {
2762 struct kvm_interrupt irq;
2763
2764 r = -EFAULT;
2765 if (copy_from_user(&irq, argp, sizeof irq))
2766 goto out;
2767 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2768 if (r)
2769 goto out;
2770 r = 0;
2771 break;
2772 }
c4abb7c9
JK		 2773 case KVM_NMI: {
2774 r = kvm_vcpu_ioctl_nmi(vcpu);
2775 if (r)
2776 goto out;
2777 r = 0;
2778 break;
2779 }
313a3dc7
CO		 2780 case KVM_SET_CPUID: {
2781 struct kvm_cpuid __user *cpuid_arg = argp;
2782 struct kvm_cpuid cpuid;
2783
2784 r = -EFAULT;
2785 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2786 goto out;
2787 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2788 if (r)
2789 goto out;
2790 break;
2791 }
07716717
DK		 2792 case KVM_SET_CPUID2: {
2793 struct kvm_cpuid2 __user *cpuid_arg = argp;
2794 struct kvm_cpuid2 cpuid;
2795
2796 r = -EFAULT;
2797 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2798 goto out;
2799 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2800 cpuid_arg->entries);
07716717
DK		 2801 if (r)
2802 goto out;
2803 break;
2804 }
2805 case KVM_GET_CPUID2: {
2806 struct kvm_cpuid2 __user *cpuid_arg = argp;
2807 struct kvm_cpuid2 cpuid;
2808
2809 r = -EFAULT;
2810 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2811 goto out;
2812 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2813 cpuid_arg->entries);
07716717
DK		 2814 if (r)
2815 goto out;
2816 r = -EFAULT;
2817 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2818 goto out;
2819 r = 0;
2820 break;
2821 }
313a3dc7
CO		 2822 case KVM_GET_MSRS:
2823 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2824 break;
2825 case KVM_SET_MSRS:
2826 r = msr_io(vcpu, argp, do_set_msr, 0);
2827 break;
b209749f
AK		 2828 case KVM_TPR_ACCESS_REPORTING: {
2829 struct kvm_tpr_access_ctl tac;
2830
2831 r = -EFAULT;
2832 if (copy_from_user(&tac, argp, sizeof tac))
2833 goto out;
2834 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2835 if (r)
2836 goto out;
2837 r = -EFAULT;
2838 if (copy_to_user(argp, &tac, sizeof tac))
2839 goto out;
2840 r = 0;
2841 break;
2842 };
b93463aa
AK		 2843 case KVM_SET_VAPIC_ADDR: {
2844 struct kvm_vapic_addr va;
2845
2846 r = -EINVAL;
2847 if (!irqchip_in_kernel(vcpu->kvm))
2848 goto out;
2849 r = -EFAULT;
2850 if (copy_from_user(&va, argp, sizeof va))
2851 goto out;
2852 r = 0;
2853 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2854 break;
2855 }
890ca9ae
HY		 2856 case KVM_X86_SETUP_MCE: {
2857 u64 mcg_cap;
2858
2859 r = -EFAULT;
2860 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2861 goto out;
2862 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2863 break;
2864 }
2865 case KVM_X86_SET_MCE: {
2866 struct kvm_x86_mce mce;
2867
2868 r = -EFAULT;
2869 if (copy_from_user(&mce, argp, sizeof mce))
2870 goto out;
2871 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2872 break;
2873 }
3cfc3092
JK		 2874 case KVM_GET_VCPU_EVENTS: {
2875 struct kvm_vcpu_events events;
2876
2877 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2878
2879 r = -EFAULT;
2880 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2881 break;
2882 r = 0;
2883 break;
2884 }
2885 case KVM_SET_VCPU_EVENTS: {
2886 struct kvm_vcpu_events events;
2887
2888 r = -EFAULT;
2889 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2890 break;
2891
2892 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2893 break;
2894 }
a1efbe77
JK		 2895 case KVM_GET_DEBUGREGS: {
2896 struct kvm_debugregs dbgregs;
2897
2898 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2899
2900 r = -EFAULT;
2901 if (copy_to_user(argp, &dbgregs,
2902 sizeof(struct kvm_debugregs)))
2903 break;
2904 r = 0;
2905 break;
2906 }
2907 case KVM_SET_DEBUGREGS: {
2908 struct kvm_debugregs dbgregs;
2909
2910 r = -EFAULT;
2911 if (copy_from_user(&dbgregs, argp,
2912 sizeof(struct kvm_debugregs)))
2913 break;
2914
2915 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2916 break;
2917 }
2d5b5a66 2918 case KVM_GET_XSAVE: {
d1ac91d8 2919 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2920 r = -ENOMEM;
d1ac91d8 2921 if (!u.xsave)
2d5b5a66
SY		 2922 break;
2923
d1ac91d8 2924 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2925
2926 r = -EFAULT;
d1ac91d8 2927 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2928 break;
2929 r = 0;
2930 break;
2931 }
2932 case KVM_SET_XSAVE: {
d1ac91d8 2933 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2934 r = -ENOMEM;
d1ac91d8 2935 if (!u.xsave)
2d5b5a66
SY		 2936 break;
2937
2938 r = -EFAULT;
d1ac91d8 2939 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2940 break;
2941
d1ac91d8 2942 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2943 break;
2944 }
2945 case KVM_GET_XCRS: {
d1ac91d8 2946 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2947 r = -ENOMEM;
d1ac91d8 2948 if (!u.xcrs)
2d5b5a66
SY		 2949 break;
2950
d1ac91d8 2951 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2952
2953 r = -EFAULT;
d1ac91d8 2954 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2955 sizeof(struct kvm_xcrs)))
2956 break;
2957 r = 0;
2958 break;
2959 }
2960 case KVM_SET_XCRS: {
d1ac91d8 2961 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2962 r = -ENOMEM;
d1ac91d8 2963 if (!u.xcrs)
2d5b5a66
SY		 2964 break;
2965
2966 r = -EFAULT;
d1ac91d8 2967 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2968 sizeof(struct kvm_xcrs)))
2969 break;
2970
d1ac91d8 2971 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2972 break;
2973 }
313a3dc7
CO		 2974 default:
2975 r = -EINVAL;
2976 }
2977out:
d1ac91d8 2978 kfree(u.buffer);
313a3dc7
CO		 2979 return r;
2980}
2981
1fe779f8
CO		 2982static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2983{
2984 int ret;
2985
2986 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2987 return -1;
2988 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2989 return ret;
2990}
2991
b927a3ce
SY		 2992static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2993 u64 ident_addr)
2994{
2995 kvm->arch.ept_identity_map_addr = ident_addr;
2996 return 0;
2997}
2998
1fe779f8
CO		 2999static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3000 u32 kvm_nr_mmu_pages)
3001{
3002 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3003 return -EINVAL;
3004
79fac95e 3005 mutex_lock(&kvm->slots_lock);
7c8a83b7 3006 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3007
3008 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3009 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3010
7c8a83b7 3011 spin_unlock(&kvm->mmu_lock);
79fac95e 3012 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3013 return 0;
3014}
3015
3016static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3017{
39de71ec 3018 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3019}
3020
1fe779f8
CO		 3021static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3022{
3023 int r;
3024
3025 r = 0;
3026 switch (chip->chip_id) {
3027 case KVM_IRQCHIP_PIC_MASTER:
3028 memcpy(&chip->chip.pic,
3029 &pic_irqchip(kvm)->pics[0],
3030 sizeof(struct kvm_pic_state));
3031 break;
3032 case KVM_IRQCHIP_PIC_SLAVE:
3033 memcpy(&chip->chip.pic,
3034 &pic_irqchip(kvm)->pics[1],
3035 sizeof(struct kvm_pic_state));
3036 break;
3037 case KVM_IRQCHIP_IOAPIC:
eba0226b 3038 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3039 break;
3040 default:
3041 r = -EINVAL;
3042 break;
3043 }
3044 return r;
3045}
3046
3047static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3048{
3049 int r;
3050
3051 r = 0;
3052 switch (chip->chip_id) {
3053 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3054 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3055 memcpy(&pic_irqchip(kvm)->pics[0],
3056 &chip->chip.pic,
3057 sizeof(struct kvm_pic_state));
f4f51050 3058 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3059 break;
3060 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3061 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3062 memcpy(&pic_irqchip(kvm)->pics[1],
3063 &chip->chip.pic,
3064 sizeof(struct kvm_pic_state));
f4f51050 3065 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3066 break;
3067 case KVM_IRQCHIP_IOAPIC:
eba0226b 3068 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3069 break;
3070 default:
3071 r = -EINVAL;
3072 break;
3073 }
3074 kvm_pic_update_irq(pic_irqchip(kvm));
3075 return r;
3076}
3077
e0f63cb9
SY		 3078static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3079{
3080 int r = 0;
3081
894a9c55 3082 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3083 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3084 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3085 return r;
3086}
3087
3088static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3089{
3090 int r = 0;
3091
894a9c55 3092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3093 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3094 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3095 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3096 return r;
3097}
3098
3099static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3100{
3101 int r = 0;
3102
3103 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3104 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3105 sizeof(ps->channels));
3106 ps->flags = kvm->arch.vpit->pit_state.flags;
3107 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3108 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3109 return r;
3110}
3111
3112static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3113{
3114 int r = 0, start = 0;
3115 u32 prev_legacy, cur_legacy;
3116 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3117 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3118 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3119 if (!prev_legacy && cur_legacy)
3120 start = 1;
3121 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3122 sizeof(kvm->arch.vpit->pit_state.channels));
3123 kvm->arch.vpit->pit_state.flags = ps->flags;
3124 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3125 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3126 return r;
3127}
3128
52d939a0
MT		 3129static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3130 struct kvm_reinject_control *control)
3131{
3132 if (!kvm->arch.vpit)
3133 return -ENXIO;
894a9c55 3134 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3135 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3136 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3137 return 0;
3138}
3139
5bb064dc
ZX		 3140/*
3141 * Get (and clear) the dirty memory log for a memory slot.
3142 */
3143int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3144 struct kvm_dirty_log *log)
3145{
87bf6e7d 3146 int r, i;
5bb064dc 3147 struct kvm_memory_slot *memslot;
87bf6e7d 3148 unsigned long n;
b050b015 3149 unsigned long is_dirty = 0;
5bb064dc 3150
79fac95e 3151 mutex_lock(&kvm->slots_lock);
5bb064dc 3152
b050b015
MT		 3153 r = -EINVAL;
3154 if (log->slot >= KVM_MEMORY_SLOTS)
3155 goto out;
3156
3157 memslot = &kvm->memslots->memslots[log->slot];
3158 r = -ENOENT;
3159 if (!memslot->dirty_bitmap)
3160 goto out;
3161
87bf6e7d 3162 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3163
b050b015
MT		 3164 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3165 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3166
3167 /* If nothing is dirty, don't bother messing with page tables. */
3168 if (is_dirty) {
b050b015 3169 struct kvm_memslots *slots, *old_slots;
914ebccd 3170 unsigned long *dirty_bitmap;
b050b015 3171
914ebccd
TY		 3172 r = -ENOMEM;
3173 dirty_bitmap = vmalloc(n);
3174 if (!dirty_bitmap)
3175 goto out;
3176 memset(dirty_bitmap, 0, n);
b050b015 3177
914ebccd
TY		 3178 r = -ENOMEM;
3179 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3180 if (!slots) {
3181 vfree(dirty_bitmap);
3182 goto out;
3183 }
b050b015
MT		 3184 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3185 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3186
3187 old_slots = kvm->memslots;
3188 rcu_assign_pointer(kvm->memslots, slots);
3189 synchronize_srcu_expedited(&kvm->srcu);
3190 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3191 kfree(old_slots);
914ebccd 3192
edde99ce
MT		 3193 spin_lock(&kvm->mmu_lock);
3194 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3195 spin_unlock(&kvm->mmu_lock);
3196
914ebccd
TY		 3197 r = -EFAULT;
3198 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3199 vfree(dirty_bitmap);
3200 goto out;
3201 }
3202 vfree(dirty_bitmap);
3203 } else {
3204 r = -EFAULT;
3205 if (clear_user(log->dirty_bitmap, n))
3206 goto out;
5bb064dc 3207 }
b050b015 3208
5bb064dc
ZX		 3209 r = 0;
3210out:
79fac95e 3211 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3212 return r;
3213}
3214
1fe779f8
CO		 3215long kvm_arch_vm_ioctl(struct file *filp,
3216 unsigned int ioctl, unsigned long arg)
3217{
3218 struct kvm *kvm = filp->private_data;
3219 void __user *argp = (void __user *)arg;
367e1319 3220 int r = -ENOTTY;
f0d66275
DH		 3221 /*
3222 * This union makes it completely explicit to gcc-3.x
3223 * that these two variables' stack usage should be
3224 * combined, not added together.
3225 */
3226 union {
3227 struct kvm_pit_state ps;
e9f42757 3228 struct kvm_pit_state2 ps2;
c5ff41ce 3229 struct kvm_pit_config pit_config;
f0d66275 3230 } u;
1fe779f8
CO		 3231
3232 switch (ioctl) {
3233 case KVM_SET_TSS_ADDR:
3234 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3235 if (r < 0)
3236 goto out;
3237 break;
b927a3ce
SY		 3238 case KVM_SET_IDENTITY_MAP_ADDR: {
3239 u64 ident_addr;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3243 goto out;
3244 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3245 if (r < 0)
3246 goto out;
3247 break;
3248 }
1fe779f8
CO		 3249 case KVM_SET_NR_MMU_PAGES:
3250 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3251 if (r)
3252 goto out;
3253 break;
3254 case KVM_GET_NR_MMU_PAGES:
3255 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3256 break;
3ddea128
MT		 3257 case KVM_CREATE_IRQCHIP: {
3258 struct kvm_pic *vpic;
3259
3260 mutex_lock(&kvm->lock);
3261 r = -EEXIST;
3262 if (kvm->arch.vpic)
3263 goto create_irqchip_unlock;
1fe779f8 3264 r = -ENOMEM;
3ddea128
MT		 3265 vpic = kvm_create_pic(kvm);
3266 if (vpic) {
1fe779f8
CO		 3267 r = kvm_ioapic_init(kvm);
3268 if (r) {
72bb2fcd
WY		 3269 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3270 &vpic->dev);
3ddea128
MT		 3271 kfree(vpic);
3272 goto create_irqchip_unlock;
1fe779f8
CO		 3273 }
3274 } else
3ddea128
MT		 3275 goto create_irqchip_unlock;
3276 smp_wmb();
3277 kvm->arch.vpic = vpic;
3278 smp_wmb();
399ec807
AK		 3279 r = kvm_setup_default_irq_routing(kvm);
3280 if (r) {
3ddea128 3281 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3282 kvm_ioapic_destroy(kvm);
3283 kvm_destroy_pic(kvm);
3ddea128 3284 mutex_unlock(&kvm->irq_lock);
399ec807 3285 }
3ddea128
MT		 3286 create_irqchip_unlock:
3287 mutex_unlock(&kvm->lock);
1fe779f8 3288 break;
3ddea128 3289 }
7837699f 3290 case KVM_CREATE_PIT:
c5ff41ce
JK		 3291 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3292 goto create_pit;
3293 case KVM_CREATE_PIT2:
3294 r = -EFAULT;
3295 if (copy_from_user(&u.pit_config, argp,
3296 sizeof(struct kvm_pit_config)))
3297 goto out;
3298 create_pit:
79fac95e 3299 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3300 r = -EEXIST;
3301 if (kvm->arch.vpit)
3302 goto create_pit_unlock;
7837699f 3303 r = -ENOMEM;
c5ff41ce 3304 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3305 if (kvm->arch.vpit)
3306 r = 0;
269e05e4 3307 create_pit_unlock:
79fac95e 3308 mutex_unlock(&kvm->slots_lock);
7837699f 3309 break;
4925663a 3310 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3311 case KVM_IRQ_LINE: {
3312 struct kvm_irq_level irq_event;
3313
3314 r = -EFAULT;
3315 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3316 goto out;
160d2f6c 3317 r = -ENXIO;
1fe779f8 3318 if (irqchip_in_kernel(kvm)) {
4925663a 3319 __s32 status;
4925663a
GN		 3320 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3321 irq_event.irq, irq_event.level);
4925663a 3322 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3323 r = -EFAULT;
4925663a
GN		 3324 irq_event.status = status;
3325 if (copy_to_user(argp, &irq_event,
3326 sizeof irq_event))
3327 goto out;
3328 }
1fe779f8
CO		 3329 r = 0;
3330 }
3331 break;
3332 }
3333 case KVM_GET_IRQCHIP: {
3334 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3335 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3336
f0d66275
DH		 3337 r = -ENOMEM;
3338 if (!chip)
1fe779f8 3339 goto out;
f0d66275
DH		 3340 r = -EFAULT;
3341 if (copy_from_user(chip, argp, sizeof *chip))
3342 goto get_irqchip_out;
1fe779f8
CO		 3343 r = -ENXIO;
3344 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3345 goto get_irqchip_out;
3346 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3347 if (r)
f0d66275 3348 goto get_irqchip_out;
1fe779f8 3349 r = -EFAULT;
f0d66275
DH		 3350 if (copy_to_user(argp, chip, sizeof *chip))
3351 goto get_irqchip_out;
1fe779f8 3352 r = 0;
f0d66275
DH		 3353 get_irqchip_out:
3354 kfree(chip);
3355 if (r)
3356 goto out;
1fe779f8
CO		 3357 break;
3358 }
3359 case KVM_SET_IRQCHIP: {
3360 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3361 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3362
f0d66275
DH		 3363 r = -ENOMEM;
3364 if (!chip)
1fe779f8 3365 goto out;
f0d66275
DH		 3366 r = -EFAULT;
3367 if (copy_from_user(chip, argp, sizeof *chip))
3368 goto set_irqchip_out;
1fe779f8
CO		 3369 r = -ENXIO;
3370 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3371 goto set_irqchip_out;
3372 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3373 if (r)
f0d66275 3374 goto set_irqchip_out;
1fe779f8 3375 r = 0;
f0d66275
DH		 3376 set_irqchip_out:
3377 kfree(chip);
3378 if (r)
3379 goto out;
1fe779f8
CO		 3380 break;
3381 }
e0f63cb9 3382 case KVM_GET_PIT: {
e0f63cb9 3383 r = -EFAULT;
f0d66275 3384 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3385 goto out;
3386 r = -ENXIO;
3387 if (!kvm->arch.vpit)
3388 goto out;
f0d66275 3389 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3390 if (r)
3391 goto out;
3392 r = -EFAULT;
f0d66275 3393 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3394 goto out;
3395 r = 0;
3396 break;
3397 }
3398 case KVM_SET_PIT: {
e0f63cb9 3399 r = -EFAULT;
f0d66275 3400 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3401 goto out;
3402 r = -ENXIO;
3403 if (!kvm->arch.vpit)
3404 goto out;
f0d66275 3405 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3406 if (r)
3407 goto out;
3408 r = 0;
3409 break;
3410 }
e9f42757
BK		 3411 case KVM_GET_PIT2: {
3412 r = -ENXIO;
3413 if (!kvm->arch.vpit)
3414 goto out;
3415 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3416 if (r)
3417 goto out;
3418 r = -EFAULT;
3419 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3420 goto out;
3421 r = 0;
3422 break;
3423 }
3424 case KVM_SET_PIT2: {
3425 r = -EFAULT;
3426 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3427 goto out;
3428 r = -ENXIO;
3429 if (!kvm->arch.vpit)
3430 goto out;
3431 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3432 if (r)
3433 goto out;
3434 r = 0;
3435 break;
3436 }
52d939a0
MT		 3437 case KVM_REINJECT_CONTROL: {
3438 struct kvm_reinject_control control;
3439 r = -EFAULT;
3440 if (copy_from_user(&control, argp, sizeof(control)))
3441 goto out;
3442 r = kvm_vm_ioctl_reinject(kvm, &control);
3443 if (r)
3444 goto out;
3445 r = 0;
3446 break;
3447 }
ffde22ac
ES		 3448 case KVM_XEN_HVM_CONFIG: {
3449 r = -EFAULT;
3450 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3451 sizeof(struct kvm_xen_hvm_config)))
3452 goto out;
3453 r = -EINVAL;
3454 if (kvm->arch.xen_hvm_config.flags)
3455 goto out;
3456 r = 0;
3457 break;
3458 }
afbcf7ab 3459 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3460 struct kvm_clock_data user_ns;
3461 u64 now_ns;
3462 s64 delta;
3463
3464 r = -EFAULT;
3465 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3466 goto out;
3467
3468 r = -EINVAL;
3469 if (user_ns.flags)
3470 goto out;
3471
3472 r = 0;
395c6b0a 3473 local_irq_disable();
759379dd 3474 now_ns = get_kernel_ns();
afbcf7ab 3475 delta = user_ns.clock - now_ns;
395c6b0a 3476 local_irq_enable();
afbcf7ab
GC		 3477 kvm->arch.kvmclock_offset = delta;
3478 break;
3479 }
3480 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3481 struct kvm_clock_data user_ns;
3482 u64 now_ns;
3483
395c6b0a 3484 local_irq_disable();
759379dd 3485 now_ns = get_kernel_ns();
afbcf7ab 3486 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3487 local_irq_enable();
afbcf7ab 3488 user_ns.flags = 0;
97e69aa6 3489 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3490
3491 r = -EFAULT;
3492 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3493 goto out;
3494 r = 0;
3495 break;
3496 }
3497
1fe779f8
CO		 3498 default:
3499 ;
3500 }
3501out:
3502 return r;
3503}
3504
a16b043c 3505static void kvm_init_msr_list(void)
043405e1
CO		 3506{
3507 u32 dummy[2];
3508 unsigned i, j;
3509
e3267cbb
GC		 3510 /* skip the first msrs in the list. KVM-specific */
3511 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3512 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3513 continue;
3514 if (j < i)
3515 msrs_to_save[j] = msrs_to_save[i];
3516 j++;
3517 }
3518 num_msrs_to_save = j;
3519}
3520
bda9020e
MT		 3521static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3522 const void *v)
bbd9b64e 3523{
bda9020e
MT		 3524 if (vcpu->arch.apic &&
3525 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3526 return 0;
bbd9b64e 3527
e93f8a0f 3528 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3529}
3530
bda9020e 3531static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3532{
bda9020e
MT		 3533 if (vcpu->arch.apic &&
3534 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3535 return 0;
bbd9b64e 3536
e93f8a0f 3537 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3538}
3539
2dafc6c2
GN		 3540static void kvm_set_segment(struct kvm_vcpu *vcpu,
3541 struct kvm_segment *var, int seg)
3542{
3543 kvm_x86_ops->set_segment(vcpu, var, seg);
3544}
3545
3546void kvm_get_segment(struct kvm_vcpu *vcpu,
3547 struct kvm_segment *var, int seg)
3548{
3549 kvm_x86_ops->get_segment(vcpu, var, seg);
3550}
3551
c30a358d
JR		 3552static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3553{
3554 return gpa;
3555}
3556
02f59dc9
JR		 3557static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3558{
3559 gpa_t t_gpa;
3560 u32 error;
3561
3562 BUG_ON(!mmu_is_nested(vcpu));
3563
3564 /* NPT walks are always user-walks */
3565 access |= PFERR_USER_MASK;
3566 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3567 if (t_gpa == UNMAPPED_GVA)
0959ffac 3568 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3569
3570 return t_gpa;
3571}
3572
1871c602
GN		 3573gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3574{
3575 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3576 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3577}
3578
3579 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3580{
3581 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3582 access |= PFERR_FETCH_MASK;
14dfe855 3583 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3584}
3585
3586gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3587{
3588 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3589 access |= PFERR_WRITE_MASK;
14dfe855 3590 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3591}
3592
3593/* uses this to access any guest's mapped memory without checking CPL */
3594gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3595{
14dfe855 3596 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3597}
3598
3599static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3600 struct kvm_vcpu *vcpu, u32 access,
3601 u32 *error)
bbd9b64e
CO		 3602{
3603 void *data = val;
10589a46 3604 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3605
3606 while (bytes) {
14dfe855
JR		 3607 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3608 error);
bbd9b64e 3609 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3610 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3611 int ret;
3612
10589a46
MT		 3613 if (gpa == UNMAPPED_GVA) {
3614 r = X86EMUL_PROPAGATE_FAULT;
3615 goto out;
3616 }
77c2002e 3617 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3618 if (ret < 0) {
c3cd7ffa 3619 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3620 goto out;
3621 }
bbd9b64e 3622
77c2002e
IE		 3623 bytes -= toread;
3624 data += toread;
3625 addr += toread;
bbd9b64e 3626 }
10589a46 3627out:
10589a46 3628 return r;
bbd9b64e 3629}
77c2002e 3630
1871c602
GN		 3631/* used for instruction fetching */
3632static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3633 struct kvm_vcpu *vcpu, u32 *error)
3634{
3635 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3636 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3637 access | PFERR_FETCH_MASK, error);
3638}
3639
3640static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3641 struct kvm_vcpu *vcpu, u32 *error)
3642{
3643 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3644 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3645 error);
3646}
3647
3648static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3649 struct kvm_vcpu *vcpu, u32 *error)
3650{
3651 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3652}
3653
7972995b 3654static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3655 unsigned int bytes,
7972995b 3656 struct kvm_vcpu *vcpu,
2dafc6c2 3657 u32 *error)
77c2002e
IE		 3658{
3659 void *data = val;
3660 int r = X86EMUL_CONTINUE;
3661
3662 while (bytes) {
14dfe855
JR		 3663 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3664 PFERR_WRITE_MASK,
3665 error);
77c2002e
IE		 3666 unsigned offset = addr & (PAGE_SIZE-1);
3667 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3668 int ret;
3669
3670 if (gpa == UNMAPPED_GVA) {
3671 r = X86EMUL_PROPAGATE_FAULT;
3672 goto out;
3673 }
3674 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3675 if (ret < 0) {
c3cd7ffa 3676 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3677 goto out;
3678 }
3679
3680 bytes -= towrite;
3681 data += towrite;
3682 addr += towrite;
3683 }
3684out:
3685 return r;
3686}
3687
bbd9b64e
CO		 3688static int emulator_read_emulated(unsigned long addr,
3689 void *val,
3690 unsigned int bytes,
8fe681e9 3691 unsigned int *error_code,
bbd9b64e
CO		 3692 struct kvm_vcpu *vcpu)
3693{
bbd9b64e
CO		 3694 gpa_t gpa;
3695
3696 if (vcpu->mmio_read_completed) {
3697 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3698 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3699 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3700 vcpu->mmio_read_completed = 0;
3701 return X86EMUL_CONTINUE;
3702 }
3703
8fe681e9 3704 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3705
8fe681e9 3706 if (gpa == UNMAPPED_GVA)
1871c602 3707 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3708
3709 /* For APIC access vmexit */
3710 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3711 goto mmio;
3712
1871c602 3713 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3714 == X86EMUL_CONTINUE)
bbd9b64e 3715 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3716
3717mmio:
3718 /*
3719 * Is this MMIO handled locally?
3720 */
aec51dc4
AK		 3721 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3722 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3723 return X86EMUL_CONTINUE;
3724 }
aec51dc4
AK		 3725
3726 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3727
3728 vcpu->mmio_needed = 1;
411c35b7
GN		 3729 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3730 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3731 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3732 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3733
c3cd7ffa 3734 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3735}
3736
3200f405 3737int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3738 const void *val, int bytes)
bbd9b64e
CO		 3739{
3740 int ret;
3741
3742 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3743 if (ret < 0)
bbd9b64e 3744 return 0;
ad218f85 3745 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3746 return 1;
3747}
3748
3749static int emulator_write_emulated_onepage(unsigned long addr,
3750 const void *val,
3751 unsigned int bytes,
8fe681e9 3752 unsigned int *error_code,
bbd9b64e
CO		 3753 struct kvm_vcpu *vcpu)
3754{
10589a46
MT		 3755 gpa_t gpa;
3756
8fe681e9 3757 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3758
8fe681e9 3759 if (gpa == UNMAPPED_GVA)
bbd9b64e 3760 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3761
3762 /* For APIC access vmexit */
3763 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3764 goto mmio;
3765
3766 if (emulator_write_phys(vcpu, gpa, val, bytes))
3767 return X86EMUL_CONTINUE;
3768
3769mmio:
aec51dc4 3770 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3771 /*
3772 * Is this MMIO handled locally?
3773 */
bda9020e 3774 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3775 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3776
3777 vcpu->mmio_needed = 1;
411c35b7
GN		 3778 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3779 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3780 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3781 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3782 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3783
3784 return X86EMUL_CONTINUE;
3785}
3786
3787int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3788 const void *val,
3789 unsigned int bytes,
8fe681e9 3790 unsigned int *error_code,
8f6abd06 3791 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3792{
3793 /* Crossing a page boundary? */
3794 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3795 int rc, now;
3796
3797 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3798 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3799 vcpu);
bbd9b64e
CO		 3800 if (rc != X86EMUL_CONTINUE)
3801 return rc;
3802 addr += now;
3803 val += now;
3804 bytes -= now;
3805 }
8fe681e9
GN		 3806 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3807 vcpu);
bbd9b64e 3808}
bbd9b64e 3809
daea3e73
AK		 3810#define CMPXCHG_TYPE(t, ptr, old, new) \
3811 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3812
3813#ifdef CONFIG_X86_64
3814# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3815#else
3816# define CMPXCHG64(ptr, old, new) \
9749a6c0 3817 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3818#endif
3819
bbd9b64e
CO		 3820static int emulator_cmpxchg_emulated(unsigned long addr,
3821 const void *old,
3822 const void *new,
3823 unsigned int bytes,
8fe681e9 3824 unsigned int *error_code,
bbd9b64e
CO		 3825 struct kvm_vcpu *vcpu)
3826{
daea3e73
AK		 3827 gpa_t gpa;
3828 struct page *page;
3829 char *kaddr;
3830 bool exchanged;
2bacc55c 3831
daea3e73
AK		 3832 /* guests cmpxchg8b have to be emulated atomically */
3833 if (bytes > 8 || (bytes & (bytes - 1)))
3834 goto emul_write;
10589a46 3835
daea3e73 3836 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3837
daea3e73
AK		 3838 if (gpa == UNMAPPED_GVA ||
3839 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3840 goto emul_write;
2bacc55c 3841
daea3e73
AK		 3842 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3843 goto emul_write;
72dc67a6 3844
daea3e73 3845 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3846 if (is_error_page(page)) {
3847 kvm_release_page_clean(page);
3848 goto emul_write;
3849 }
72dc67a6 3850
daea3e73
AK		 3851 kaddr = kmap_atomic(page, KM_USER0);
3852 kaddr += offset_in_page(gpa);
3853 switch (bytes) {
3854 case 1:
3855 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3856 break;
3857 case 2:
3858 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3859 break;
3860 case 4:
3861 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3862 break;
3863 case 8:
3864 exchanged = CMPXCHG64(kaddr, old, new);
3865 break;
3866 default:
3867 BUG();
2bacc55c 3868 }
daea3e73
AK		 3869 kunmap_atomic(kaddr, KM_USER0);
3870 kvm_release_page_dirty(page);
3871
3872 if (!exchanged)
3873 return X86EMUL_CMPXCHG_FAILED;
3874
8f6abd06
GN		 3875 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3876
3877 return X86EMUL_CONTINUE;
4a5f48f6 3878
3200f405 3879emul_write:
daea3e73 3880 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3881
8fe681e9 3882 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3883}
3884
cf8f70bf
GN		 3885static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3886{
3887 /* TODO: String I/O for in kernel device */
3888 int r;
3889
3890 if (vcpu->arch.pio.in)
3891 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3892 vcpu->arch.pio.size, pd);
3893 else
3894 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3895 vcpu->arch.pio.port, vcpu->arch.pio.size,
3896 pd);
3897 return r;
3898}
3899
3900
3901static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3902 unsigned int count, struct kvm_vcpu *vcpu)
3903{
7972995b 3904 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3905 goto data_avail;
3906
c41a15dd 3907 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3908
3909 vcpu->arch.pio.port = port;
3910 vcpu->arch.pio.in = 1;
7972995b 3911 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3912 vcpu->arch.pio.size = size;
3913
3914 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3915 data_avail:
3916 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3917 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3918 return 1;
3919 }
3920
3921 vcpu->run->exit_reason = KVM_EXIT_IO;
3922 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3923 vcpu->run->io.size = size;
3924 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3925 vcpu->run->io.count = count;
3926 vcpu->run->io.port = port;
3927
3928 return 0;
3929}
3930
3931static int emulator_pio_out_emulated(int size, unsigned short port,
3932 const void *val, unsigned int count,
3933 struct kvm_vcpu *vcpu)
3934{
c41a15dd 3935 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3936
3937 vcpu->arch.pio.port = port;
3938 vcpu->arch.pio.in = 0;
7972995b 3939 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3940 vcpu->arch.pio.size = size;
3941
3942 memcpy(vcpu->arch.pio_data, val, size * count);
3943
3944 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3945 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3946 return 1;
3947 }
3948
3949 vcpu->run->exit_reason = KVM_EXIT_IO;
3950 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3951 vcpu->run->io.size = size;
3952 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3953 vcpu->run->io.count = count;
3954 vcpu->run->io.port = port;
3955
3956 return 0;
3957}
3958
bbd9b64e
CO		 3959static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3960{
3961 return kvm_x86_ops->get_segment_base(vcpu, seg);
3962}
3963
3964int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3965{
a7052897 3966 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3967 return X86EMUL_CONTINUE;
3968}
3969
f5f48ee1
SY		 3970int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3971{
3972 if (!need_emulate_wbinvd(vcpu))
3973 return X86EMUL_CONTINUE;
3974
3975 if (kvm_x86_ops->has_wbinvd_exit()) {
453d9c57 3976 preempt_disable();
f5f48ee1
SY		 3977 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3978 wbinvd_ipi, NULL, 1);
453d9c57 3979 preempt_enable();
f5f48ee1
SY		 3980 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3981 }
3982 wbinvd();
3983 return X86EMUL_CONTINUE;
3984}
3985EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3986
bbd9b64e
CO		 3987int emulate_clts(struct kvm_vcpu *vcpu)
3988{
4d4ec087 3989 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3990 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3991 return X86EMUL_CONTINUE;
3992}
3993
35aa5375 3994int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3995{
338dbc97 3996 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3997}
3998
35aa5375 3999int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4000{
338dbc97
GN		 4001
4002 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4003}
4004
52a46617 4005static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4006{
52a46617 4007 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4008}
4009
52a46617 4010static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4011{
52a46617
GN		 4012 unsigned long value;
4013
4014 switch (cr) {
4015 case 0:
4016 value = kvm_read_cr0(vcpu);
4017 break;
4018 case 2:
4019 value = vcpu->arch.cr2;
4020 break;
4021 case 3:
4022 value = vcpu->arch.cr3;
4023 break;
4024 case 4:
4025 value = kvm_read_cr4(vcpu);
4026 break;
4027 case 8:
4028 value = kvm_get_cr8(vcpu);
4029 break;
4030 default:
4031 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4032 return 0;
4033 }
4034
4035 return value;
4036}
4037
0f12244f 4038static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4039{
0f12244f
GN		 4040 int res = 0;
4041
52a46617
GN		 4042 switch (cr) {
4043 case 0:
49a9b07e 4044 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4045 break;
4046 case 2:
4047 vcpu->arch.cr2 = val;
4048 break;
4049 case 3:
2390218b 4050 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4051 break;
4052 case 4:
a83b29c6 4053 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4054 break;
4055 case 8:
0f12244f 4056 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4057 break;
4058 default:
4059 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4060 res = -1;
52a46617 4061 }
0f12244f
GN		 4062
4063 return res;
52a46617
GN		 4064}
4065
9c537244
GN		 4066static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4067{
4068 return kvm_x86_ops->get_cpl(vcpu);
4069}
4070
2dafc6c2
GN		 4071static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4072{
4073 kvm_x86_ops->get_gdt(vcpu, dt);
4074}
4075
160ce1f1
MG		 4076static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4077{
4078 kvm_x86_ops->get_idt(vcpu, dt);
4079}
4080
5951c442
GN		 4081static unsigned long emulator_get_cached_segment_base(int seg,
4082 struct kvm_vcpu *vcpu)
4083{
4084 return get_segment_base(vcpu, seg);
4085}
4086
2dafc6c2
GN		 4087static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4088 struct kvm_vcpu *vcpu)
4089{
4090 struct kvm_segment var;
4091
4092 kvm_get_segment(vcpu, &var, seg);
4093
4094 if (var.unusable)
4095 return false;
4096
4097 if (var.g)
4098 var.limit >>= 12;
4099 set_desc_limit(desc, var.limit);
4100 set_desc_base(desc, (unsigned long)var.base);
4101 desc->type = var.type;
4102 desc->s = var.s;
4103 desc->dpl = var.dpl;
4104 desc->p = var.present;
4105 desc->avl = var.avl;
4106 desc->l = var.l;
4107 desc->d = var.db;
4108 desc->g = var.g;
4109
4110 return true;
4111}
4112
4113static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4114 struct kvm_vcpu *vcpu)
4115{
4116 struct kvm_segment var;
4117
4118 /* needed to preserve selector */
4119 kvm_get_segment(vcpu, &var, seg);
4120
4121 var.base = get_desc_base(desc);
4122 var.limit = get_desc_limit(desc);
4123 if (desc->g)
4124 var.limit = (var.limit << 12) | 0xfff;
4125 var.type = desc->type;
4126 var.present = desc->p;
4127 var.dpl = desc->dpl;
4128 var.db = desc->d;
4129 var.s = desc->s;
4130 var.l = desc->l;
4131 var.g = desc->g;
4132 var.avl = desc->avl;
4133 var.present = desc->p;
4134 var.unusable = !var.present;
4135 var.padding = 0;
4136
4137 kvm_set_segment(vcpu, &var, seg);
4138 return;
4139}
4140
4141static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4142{
4143 struct kvm_segment kvm_seg;
4144
4145 kvm_get_segment(vcpu, &kvm_seg, seg);
4146 return kvm_seg.selector;
4147}
4148
4149static void emulator_set_segment_selector(u16 sel, int seg,
4150 struct kvm_vcpu *vcpu)
4151{
4152 struct kvm_segment kvm_seg;
4153
4154 kvm_get_segment(vcpu, &kvm_seg, seg);
4155 kvm_seg.selector = sel;
4156 kvm_set_segment(vcpu, &kvm_seg, seg);
4157}
4158
14af3f3c 4159static struct x86_emulate_ops emulate_ops = {
1871c602 4160 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4161 .write_std = kvm_write_guest_virt_system,
1871c602 4162 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4163 .read_emulated = emulator_read_emulated,
4164 .write_emulated = emulator_write_emulated,
4165 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4166 .pio_in_emulated = emulator_pio_in_emulated,
4167 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4168 .get_cached_descriptor = emulator_get_cached_descriptor,
4169 .set_cached_descriptor = emulator_set_cached_descriptor,
4170 .get_segment_selector = emulator_get_segment_selector,
4171 .set_segment_selector = emulator_set_segment_selector,
5951c442 4172 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4173 .get_gdt = emulator_get_gdt,
160ce1f1 4174 .get_idt = emulator_get_idt,
52a46617
GN		 4175 .get_cr = emulator_get_cr,
4176 .set_cr = emulator_set_cr,
9c537244 4177 .cpl = emulator_get_cpl,
35aa5375
GN		 4178 .get_dr = emulator_get_dr,
4179 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4180 .set_msr = kvm_set_msr,
4181 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4182};
4183
5fdbf976
MT		 4184static void cache_all_regs(struct kvm_vcpu *vcpu)
4185{
4186 kvm_register_read(vcpu, VCPU_REGS_RAX);
4187 kvm_register_read(vcpu, VCPU_REGS_RSP);
4188 kvm_register_read(vcpu, VCPU_REGS_RIP);
4189 vcpu->arch.regs_dirty = ~0;
4190}
4191
95cb2295
GN		 4192static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4193{
4194 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4195 /*
4196 * an sti; sti; sequence only disable interrupts for the first
4197 * instruction. So, if the last instruction, be it emulated or
4198 * not, left the system with the INT_STI flag enabled, it
4199 * means that the last instruction is an sti. We should not
4200 * leave the flag on in this case. The same goes for mov ss
4201 */
4202 if (!(int_shadow & mask))
4203 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4204}
4205
54b8486f
GN		 4206static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4207{
4208 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4209 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4210 kvm_propagate_fault(vcpu);
54b8486f
GN		 4211 else if (ctxt->error_code_valid)
4212 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4213 else
4214 kvm_queue_exception(vcpu, ctxt->exception);
4215}
4216
8ec4722d
MG		 4217static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4218{
4219 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4220 int cs_db, cs_l;
4221
4222 cache_all_regs(vcpu);
4223
4224 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4225
4226 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4227 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4228 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4229 vcpu->arch.emulate_ctxt.mode =
4230 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4231 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4232 ? X86EMUL_MODE_VM86 : cs_l
4233 ? X86EMUL_MODE_PROT64 : cs_db
4234 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4235 memset(c, 0, sizeof(struct decode_cache));
4236 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4237}
4238
63995653
MG		 4239int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4240{
4241 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4242 int ret;
4243
4244 init_emulate_ctxt(vcpu);
4245
4246 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4247 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4248 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4249 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4250
4251 if (ret != X86EMUL_CONTINUE)
4252 return EMULATE_FAIL;
4253
4254 vcpu->arch.emulate_ctxt.eip = c->eip;
4255 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4256 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4257 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4258
4259 if (irq == NMI_VECTOR)
4260 vcpu->arch.nmi_pending = false;
4261 else
4262 vcpu->arch.interrupt.pending = false;
4263
4264 return EMULATE_DONE;
4265}
4266EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4267
6d77dbfc
GN		 4268static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4269{
6d77dbfc
GN		 4270 ++vcpu->stat.insn_emulation_fail;
4271 trace_kvm_emulate_insn_failed(vcpu);
4272 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4273 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4274 vcpu->run->internal.ndata = 0;
4275 kvm_queue_exception(vcpu, UD_VECTOR);
4276 return EMULATE_FAIL;
4277}
4278
a6f177ef
GN		 4279static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4280{
4281 gpa_t gpa;
4282
68be0803
GN		 4283 if (tdp_enabled)
4284 return false;
4285
a6f177ef
GN		 4286 /*
4287 * if emulation was due to access to shadowed page table
4288 * and it failed try to unshadow page and re-entetr the
4289 * guest to let CPU execute the instruction.
4290 */
4291 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4292 return true;
4293
4294 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4295
4296 if (gpa == UNMAPPED_GVA)
4297 return true; /* let cpu generate fault */
4298
4299 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4300 return true;
4301
4302 return false;
4303}
4304
bbd9b64e 4305int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4306 unsigned long cr2,
4307 u16 error_code,
571008da 4308 int emulation_type)
bbd9b64e 4309{
95cb2295 4310 int r;
4d2179e1 4311 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4312
26eef70c 4313 kvm_clear_exception_queue(vcpu);
ad312c7c 4314 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4315 /*
56e82318 4316 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4317 * instead of direct ->regs accesses, can save hundred cycles
4318 * on Intel for instructions that don't read/change RSP, for
4319 * for example.
4320 */
4321 cache_all_regs(vcpu);
bbd9b64e 4322
571008da 4323 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4324 init_emulate_ctxt(vcpu);
95cb2295 4325 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4326 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4327 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4328
9aabc88f 4329 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4330 if (r == X86EMUL_PROPAGATE_FAULT)
4331 goto done;
bbd9b64e 4332
e46479f8 4333 trace_kvm_emulate_insn_start(vcpu);
571008da 4334
0cb5762e
AP		 4335 /* Only allow emulation of specific instructions on #UD
4336 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4337 if (emulation_type & EMULTYPE_TRAP_UD) {
4338 if (!c->twobyte)
4339 return EMULATE_FAIL;
4340 switch (c->b) {
4341 case 0x01: /* VMMCALL */
4342 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4343 return EMULATE_FAIL;
4344 break;
4345 case 0x34: /* sysenter */
4346 case 0x35: /* sysexit */
4347 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4348 return EMULATE_FAIL;
4349 break;
4350 case 0x05: /* syscall */
4351 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4352 return EMULATE_FAIL;
4353 break;
4354 default:
4355 return EMULATE_FAIL;
4356 }
4357
4358 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4359 return EMULATE_FAIL;
4360 }
571008da 4361
f2b5756b 4362 ++vcpu->stat.insn_emulation;
bbd9b64e 4363 if (r) {
a6f177ef 4364 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4365 return EMULATE_DONE;
6d77dbfc
GN		 4366 if (emulation_type & EMULTYPE_SKIP)
4367 return EMULATE_FAIL;
4368 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4369 }
4370 }
4371
ba8afb6b
GN		 4372 if (emulation_type & EMULTYPE_SKIP) {
4373 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4374 return EMULATE_DONE;
4375 }
4376
4d2179e1
GN		 4377 /* this is needed for vmware backdor interface to work since it
4378 changes registers values during IO operation */
4379 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4380
5cd21917 4381restart:
9aabc88f 4382 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4383
d2ddd1c4 4384 if (r == EMULATION_FAILED) {
a6f177ef 4385 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4386 return EMULATE_DONE;
4387
6d77dbfc 4388 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4389 }
4390
d47f00a6 4391done:
54b8486f
GN		 4392 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4393 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4394 r = EMULATE_DONE;
4395 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4396 if (!vcpu->arch.pio.in)
4397 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4398 r = EMULATE_DO_MMIO;
4399 } else if (vcpu->mmio_needed) {
3457e419
GN		 4400 if (vcpu->mmio_is_write)
4401 vcpu->mmio_needed = 0;
e85d28f8 4402 r = EMULATE_DO_MMIO;
d2ddd1c4 4403 } else if (r == EMULATION_RESTART)
5cd21917 4404 goto restart;
d2ddd1c4
GN		 4405 else
4406 r = EMULATE_DONE;
f850e2e6 4407
e85d28f8
GN		 4408 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4409 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4410 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4411 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4412 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4413
4414 return r;
de7d789a 4415}
bbd9b64e 4416EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4417
cf8f70bf 4418int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4419{
cf8f70bf
GN		 4420 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4421 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4422 /* do not return to emulator after return from userspace */
7972995b 4423 vcpu->arch.pio.count = 0;
de7d789a
CO		 4424 return ret;
4425}
cf8f70bf 4426EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4427
8cfdc000
ZA		 4428static void tsc_bad(void *info)
4429{
4430 __get_cpu_var(cpu_tsc_khz) = 0;
4431}
4432
4433static void tsc_khz_changed(void *data)
c8076604 4434{
8cfdc000
ZA		 4435 struct cpufreq_freqs *freq = data;
4436 unsigned long khz = 0;
4437
4438 if (data)
4439 khz = freq->new;
4440 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4441 khz = cpufreq_quick_get(raw_smp_processor_id());
4442 if (!khz)
4443 khz = tsc_khz;
4444 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4445}
4446
c8076604
GH		 4447static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4448 void *data)
4449{
4450 struct cpufreq_freqs *freq = data;
4451 struct kvm *kvm;
4452 struct kvm_vcpu *vcpu;
4453 int i, send_ipi = 0;
4454
8cfdc000
ZA		 4455 /*
4456 * We allow guests to temporarily run on slowing clocks,
4457 * provided we notify them after, or to run on accelerating
4458 * clocks, provided we notify them before. Thus time never
4459 * goes backwards.
4460 *
4461 * However, we have a problem. We can't atomically update
4462 * the frequency of a given CPU from this function; it is
4463 * merely a notifier, which can be called from any CPU.
4464 * Changing the TSC frequency at arbitrary points in time
4465 * requires a recomputation of local variables related to
4466 * the TSC for each VCPU. We must flag these local variables
4467 * to be updated and be sure the update takes place with the
4468 * new frequency before any guests proceed.
4469 *
4470 * Unfortunately, the combination of hotplug CPU and frequency
4471 * change creates an intractable locking scenario; the order
4472 * of when these callouts happen is undefined with respect to
4473 * CPU hotplug, and they can race with each other. As such,
4474 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4475 * undefined; you can actually have a CPU frequency change take
4476 * place in between the computation of X and the setting of the
4477 * variable. To protect against this problem, all updates of
4478 * the per_cpu tsc_khz variable are done in an interrupt
4479 * protected IPI, and all callers wishing to update the value
4480 * must wait for a synchronous IPI to complete (which is trivial
4481 * if the caller is on the CPU already). This establishes the
4482 * necessary total order on variable updates.
4483 *
4484 * Note that because a guest time update may take place
4485 * anytime after the setting of the VCPU's request bit, the
4486 * correct TSC value must be set before the request. However,
4487 * to ensure the update actually makes it to any guest which
4488 * starts running in hardware virtualization between the set
4489 * and the acquisition of the spinlock, we must also ping the
4490 * CPU after setting the request bit.
4491 *
4492 */
4493
c8076604
GH		 4494 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4495 return 0;
4496 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4497 return 0;
8cfdc000
ZA		 4498
4499 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4500
4501 spin_lock(&kvm_lock);
4502 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4503 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4504 if (vcpu->cpu != freq->cpu)
4505 continue;
c285545f 4506 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4507 if (vcpu->cpu != smp_processor_id())
8cfdc000 4508 send_ipi = 1;
c8076604
GH		 4509 }
4510 }
4511 spin_unlock(&kvm_lock);
4512
4513 if (freq->old < freq->new && send_ipi) {
4514 /*
4515 * We upscale the frequency. Must make the guest
4516 * doesn't see old kvmclock values while running with
4517 * the new frequency, otherwise we risk the guest sees
4518 * time go backwards.
4519 *
4520 * In case we update the frequency for another cpu
4521 * (which might be in guest context) send an interrupt
4522 * to kick the cpu out of guest context. Next time
4523 * guest context is entered kvmclock will be updated,
4524 * so the guest will not see stale values.
4525 */
8cfdc000 4526 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4527 }
4528 return 0;
4529}
4530
4531static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4532 .notifier_call = kvmclock_cpufreq_notifier
4533};
4534
4535static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4536 unsigned long action, void *hcpu)
4537{
4538 unsigned int cpu = (unsigned long)hcpu;
4539
4540 switch (action) {
4541 case CPU_ONLINE:
4542 case CPU_DOWN_FAILED:
4543 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4544 break;
4545 case CPU_DOWN_PREPARE:
4546 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4547 break;
4548 }
4549 return NOTIFY_OK;
4550}
4551
4552static struct notifier_block kvmclock_cpu_notifier_block = {
4553 .notifier_call = kvmclock_cpu_notifier,
4554 .priority = -INT_MAX
c8076604
GH		 4555};
4556
b820cc0c
ZA		 4557static void kvm_timer_init(void)
4558{
4559 int cpu;
4560
c285545f 4561 max_tsc_khz = tsc_khz;
8cfdc000 4562 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4563 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4564#ifdef CONFIG_CPU_FREQ
4565 struct cpufreq_policy policy;
4566 memset(&policy, 0, sizeof(policy));
4567 cpufreq_get_policy(&policy, get_cpu());
4568 if (policy.cpuinfo.max_freq)
4569 max_tsc_khz = policy.cpuinfo.max_freq;
4570#endif
b820cc0c
ZA		 4571 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4572 CPUFREQ_TRANSITION_NOTIFIER);
4573 }
c285545f 4574 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4575 for_each_online_cpu(cpu)
4576 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4577}
4578
ff9d07a0
ZY		 4579static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4580
4581static int kvm_is_in_guest(void)
4582{
4583 return percpu_read(current_vcpu) != NULL;
4584}
4585
4586static int kvm_is_user_mode(void)
4587{
4588 int user_mode = 3;
dcf46b94 4589
ff9d07a0
ZY		 4590 if (percpu_read(current_vcpu))
4591 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4592
ff9d07a0
ZY		 4593 return user_mode != 0;
4594}
4595
4596static unsigned long kvm_get_guest_ip(void)
4597{
4598 unsigned long ip = 0;
dcf46b94 4599
ff9d07a0
ZY		 4600 if (percpu_read(current_vcpu))
4601 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4602
ff9d07a0
ZY		 4603 return ip;
4604}
4605
4606static struct perf_guest_info_callbacks kvm_guest_cbs = {
4607 .is_in_guest = kvm_is_in_guest,
4608 .is_user_mode = kvm_is_user_mode,
4609 .get_guest_ip = kvm_get_guest_ip,
4610};
4611
4612void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4613{
4614 percpu_write(current_vcpu, vcpu);
4615}
4616EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4617
4618void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4619{
4620 percpu_write(current_vcpu, NULL);
4621}
4622EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4623
f8c16bba 4624int kvm_arch_init(void *opaque)
043405e1 4625{
b820cc0c 4626 int r;
f8c16bba
ZX		 4627 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4628
f8c16bba
ZX		 4629 if (kvm_x86_ops) {
4630 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4631 r = -EEXIST;
4632 goto out;
f8c16bba
ZX		 4633 }
4634
4635 if (!ops->cpu_has_kvm_support()) {
4636 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4637 r = -EOPNOTSUPP;
4638 goto out;
f8c16bba
ZX		 4639 }
4640 if (ops->disabled_by_bios()) {
4641 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4642 r = -EOPNOTSUPP;
4643 goto out;
f8c16bba
ZX		 4644 }
4645
97db56ce
AK		 4646 r = kvm_mmu_module_init();
4647 if (r)
4648 goto out;
4649
4650 kvm_init_msr_list();
4651
f8c16bba 4652 kvm_x86_ops = ops;
56c6d28a 4653 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4654 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4655 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4656 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4657
b820cc0c 4658 kvm_timer_init();
c8076604 4659
ff9d07a0
ZY		 4660 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4661
2acf923e
DC		 4662 if (cpu_has_xsave)
4663 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4664
f8c16bba 4665 return 0;
56c6d28a
ZX		 4666
4667out:
56c6d28a 4668 return r;
043405e1 4669}
8776e519 4670
f8c16bba
ZX		 4671void kvm_arch_exit(void)
4672{
ff9d07a0
ZY		 4673 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4674
888d256e
JK		 4675 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4676 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4677 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4678 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4679 kvm_x86_ops = NULL;
56c6d28a
ZX		 4680 kvm_mmu_module_exit();
4681}
f8c16bba 4682
8776e519
HB		 4683int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4684{
4685 ++vcpu->stat.halt_exits;
4686 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4687 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4688 return 1;
4689 } else {
4690 vcpu->run->exit_reason = KVM_EXIT_HLT;
4691 return 0;
4692 }
4693}
4694EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4695
2f333bcb
MT		 4696static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4697 unsigned long a1)
4698{
4699 if (is_long_mode(vcpu))
4700 return a0;
4701 else
4702 return a0 | ((gpa_t)a1 << 32);
4703}
4704
55cd8e5a
GN		 4705int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4706{
4707 u64 param, ingpa, outgpa, ret;
4708 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4709 bool fast, longmode;
4710 int cs_db, cs_l;
4711
4712 /*
4713 * hypercall generates UD from non zero cpl and real mode
4714 * per HYPER-V spec
4715 */
3eeb3288 4716 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4717 kvm_queue_exception(vcpu, UD_VECTOR);
4718 return 0;
4719 }
4720
4721 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4722 longmode = is_long_mode(vcpu) && cs_l == 1;
4723
4724 if (!longmode) {
ccd46936
GN		 4725 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4726 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4727 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4728 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4729 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4730 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4731 }
4732#ifdef CONFIG_X86_64
4733 else {
4734 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4735 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4736 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4737 }
4738#endif
4739
4740 code = param & 0xffff;
4741 fast = (param >> 16) & 0x1;
4742 rep_cnt = (param >> 32) & 0xfff;
4743 rep_idx = (param >> 48) & 0xfff;
4744
4745 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4746
c25bc163
GN		 4747 switch (code) {
4748 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4749 kvm_vcpu_on_spin(vcpu);
4750 break;
4751 default:
4752 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4753 break;
4754 }
55cd8e5a
GN		 4755
4756 ret = res | (((u64)rep_done & 0xfff) << 32);
4757 if (longmode) {
4758 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4759 } else {
4760 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4761 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4762 }
4763
4764 return 1;
4765}
4766
8776e519
HB		 4767int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4768{
4769 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4770 int r = 1;
8776e519 4771
55cd8e5a
GN		 4772 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4773 return kvm_hv_hypercall(vcpu);
4774
5fdbf976
MT		 4775 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4776 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4777 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4778 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4779 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4780
229456fc 4781 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4782
8776e519
HB		 4783 if (!is_long_mode(vcpu)) {
4784 nr &= 0xFFFFFFFF;
4785 a0 &= 0xFFFFFFFF;
4786 a1 &= 0xFFFFFFFF;
4787 a2 &= 0xFFFFFFFF;
4788 a3 &= 0xFFFFFFFF;
4789 }
4790
07708c4a
JK		 4791 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4792 ret = -KVM_EPERM;
4793 goto out;
4794 }
4795
8776e519 4796 switch (nr) {
b93463aa
AK		 4797 case KVM_HC_VAPIC_POLL_IRQ:
4798 ret = 0;
4799 break;
2f333bcb
MT		 4800 case KVM_HC_MMU_OP:
4801 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4802 break;
8776e519
HB		 4803 default:
4804 ret = -KVM_ENOSYS;
4805 break;
4806 }
07708c4a 4807out:
5fdbf976 4808 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4809 ++vcpu->stat.hypercalls;
2f333bcb 4810 return r;
8776e519
HB		 4811}
4812EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4813
4814int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4815{
4816 char instruction[3];
5fdbf976 4817 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4818
8776e519
HB		 4819 /*
4820 * Blow out the MMU to ensure that no other VCPU has an active mapping
4821 * to ensure that the updated hypercall appears atomically across all
4822 * VCPUs.
4823 */
4824 kvm_mmu_zap_all(vcpu->kvm);
4825
8776e519 4826 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4827
8fe681e9 4828 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4829}
4830
8776e519
HB		 4831void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4832{
89a27f4d 4833 struct desc_ptr dt = { limit, base };
8776e519
HB		 4834
4835 kvm_x86_ops->set_gdt(vcpu, &dt);
4836}
4837
4838void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4839{
89a27f4d 4840 struct desc_ptr dt = { limit, base };
8776e519
HB		 4841
4842 kvm_x86_ops->set_idt(vcpu, &dt);
4843}
4844
07716717
DK		 4845static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4846{
ad312c7c
ZX		 4847 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4848 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4849
4850 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4851 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4852 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4853 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4854 if (ej->function == e->function) {
4855 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4856 return j;
4857 }
4858 }
4859 return 0; /* silence gcc, even though control never reaches here */
4860}
4861
4862/* find an entry with matching function, matching index (if needed), and that
4863 * should be read next (if it's stateful) */
4864static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4865 u32 function, u32 index)
4866{
4867 if (e->function != function)
4868 return 0;
4869 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4870 return 0;
4871 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4872 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4873 return 0;
4874 return 1;
4875}
4876
d8017474
AG		 4877struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4878 u32 function, u32 index)
8776e519
HB		 4879{
4880 int i;
d8017474 4881 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4882
ad312c7c 4883 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4884 struct kvm_cpuid_entry2 *e;
4885
ad312c7c 4886 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4887 if (is_matching_cpuid_entry(e, function, index)) {
4888 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4889 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4890 best = e;
4891 break;
4892 }
4893 /*
4894 * Both basic or both extended?
4895 */
4896 if (((e->function ^ function) & 0x80000000) == 0)
4897 if (!best || e->function > best->function)
4898 best = e;
4899 }
d8017474
AG		 4900 return best;
4901}
0e851880 4902EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4903
82725b20
DE		 4904int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4905{
4906 struct kvm_cpuid_entry2 *best;
4907
f7a71197
AK		 4908 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4909 if (!best || best->eax < 0x80000008)
4910 goto not_found;
82725b20
DE		 4911 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4912 if (best)
4913 return best->eax & 0xff;
f7a71197 4914not_found:
82725b20
DE		 4915 return 36;
4916}
4917
d8017474
AG		 4918void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4919{
4920 u32 function, index;
4921 struct kvm_cpuid_entry2 *best;
4922
4923 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4924 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4925 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4926 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4927 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4928 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4929 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4930 if (best) {
5fdbf976
MT		 4931 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4932 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4933 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4934 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4935 }
8776e519 4936 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4937 trace_kvm_cpuid(function,
4938 kvm_register_read(vcpu, VCPU_REGS_RAX),
4939 kvm_register_read(vcpu, VCPU_REGS_RBX),
4940 kvm_register_read(vcpu, VCPU_REGS_RCX),
4941 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4942}
4943EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4944
b6c7a5dc
HB		 4945/*
4946 * Check if userspace requested an interrupt window, and that the
4947 * interrupt window is open.
4948 *
4949 * No need to exit to userspace if we already have an interrupt queued.
4950 */
851ba692 4951static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4952{
8061823a 4953 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4954 vcpu->run->request_interrupt_window &&
5df56646 4955 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4956}
4957
851ba692 4958static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4959{
851ba692
AK		 4960 struct kvm_run *kvm_run = vcpu->run;
4961
91586a3b 4962 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4963 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4964 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4965 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4966 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4967 else
b6c7a5dc 4968 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4969 kvm_arch_interrupt_allowed(vcpu) &&
4970 !kvm_cpu_has_interrupt(vcpu) &&
4971 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4972}
4973
b93463aa
AK		 4974static void vapic_enter(struct kvm_vcpu *vcpu)
4975{
4976 struct kvm_lapic *apic = vcpu->arch.apic;
4977 struct page *page;
4978
4979 if (!apic || !apic->vapic_addr)
4980 return;
4981
4982 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4983
4984 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4985}
4986
4987static void vapic_exit(struct kvm_vcpu *vcpu)
4988{
4989 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4990 int idx;
b93463aa
AK		 4991
4992 if (!apic || !apic->vapic_addr)
4993 return;
4994
f656ce01 4995 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4996 kvm_release_page_dirty(apic->vapic_page);
4997 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4998 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4999}
5000
95ba8273
GN		 5001static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5002{
5003 int max_irr, tpr;
5004
5005 if (!kvm_x86_ops->update_cr8_intercept)
5006 return;
5007
88c808fd
AK		 5008 if (!vcpu->arch.apic)
5009 return;
5010
8db3baa2
GN		 5011 if (!vcpu->arch.apic->vapic_addr)
5012 max_irr = kvm_lapic_find_highest_irr(vcpu);
5013 else
5014 max_irr = -1;
95ba8273
GN		 5015
5016 if (max_irr != -1)
5017 max_irr >>= 4;
5018
5019 tpr = kvm_lapic_get_cr8(vcpu);
5020
5021 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5022}
5023
851ba692 5024static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5025{
5026 /* try to reinject previous events if any */
b59bb7bd 5027 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5028 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5029 vcpu->arch.exception.has_error_code,
5030 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5031 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5032 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5033 vcpu->arch.exception.error_code,
5034 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5035 return;
5036 }
5037
95ba8273
GN		 5038 if (vcpu->arch.nmi_injected) {
5039 kvm_x86_ops->set_nmi(vcpu);
5040 return;
5041 }
5042
5043 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5044 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5045 return;
5046 }
5047
5048 /* try to inject new event if pending */
5049 if (vcpu->arch.nmi_pending) {
5050 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5051 vcpu->arch.nmi_pending = false;
5052 vcpu->arch.nmi_injected = true;
5053 kvm_x86_ops->set_nmi(vcpu);
5054 }
5055 } else if (kvm_cpu_has_interrupt(vcpu)) {
5056 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5057 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5058 false);
5059 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5060 }
5061 }
5062}
5063
2acf923e
DC		 5064static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5065{
5066 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5067 !vcpu->guest_xcr0_loaded) {
5068 /* kvm_set_xcr() also depends on this */
5069 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5070 vcpu->guest_xcr0_loaded = 1;
5071 }
5072}
5073
5074static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5075{
5076 if (vcpu->guest_xcr0_loaded) {
5077 if (vcpu->arch.xcr0 != host_xcr0)
5078 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5079 vcpu->guest_xcr0_loaded = 0;
5080 }
5081}
5082
851ba692 5083static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5084{
5085 int r;
6a8b1d13 5086 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5087 vcpu->run->request_interrupt_window;
b6c7a5dc 5088
3e007509 5089 if (vcpu->requests) {
a8eeb04a 5090 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5091 kvm_mmu_unload(vcpu);
a8eeb04a 5092 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5093 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5094 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5095 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5096 if (unlikely(r))
5097 goto out;
5098 }
a8eeb04a 5099 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5100 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5101 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5102 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5103 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5104 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5105 r = 0;
5106 goto out;
5107 }
a8eeb04a 5108 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5109 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5110 r = 0;
5111 goto out;
5112 }
a8eeb04a 5113 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5114 vcpu->fpu_active = 0;
5115 kvm_x86_ops->fpu_deactivate(vcpu);
5116 }
2f52d58c 5117 }
b93463aa 5118
3e007509
AK		 5119 r = kvm_mmu_reload(vcpu);
5120 if (unlikely(r))
5121 goto out;
5122
b463a6f7
AK		 5123 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5124 inject_pending_event(vcpu);
5125
5126 /* enable NMI/IRQ window open exits if needed */
5127 if (vcpu->arch.nmi_pending)
5128 kvm_x86_ops->enable_nmi_window(vcpu);
5129 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5130 kvm_x86_ops->enable_irq_window(vcpu);
5131
5132 if (kvm_lapic_enabled(vcpu)) {
5133 update_cr8_intercept(vcpu);
5134 kvm_lapic_sync_to_vapic(vcpu);
5135 }
5136 }
5137
b6c7a5dc
HB		 5138 preempt_disable();
5139
5140 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5141 if (vcpu->fpu_active)
5142 kvm_load_guest_fpu(vcpu);
2acf923e 5143 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5144
d94e1dc9
AK		 5145 atomic_set(&vcpu->guest_mode, 1);
5146 smp_wmb();
b6c7a5dc 5147
d94e1dc9 5148 local_irq_disable();
32f88400 5149
d94e1dc9
AK		 5150 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5151 || need_resched() || signal_pending(current)) {
5152 atomic_set(&vcpu->guest_mode, 0);
5153 smp_wmb();
6c142801
AK		 5154 local_irq_enable();
5155 preempt_enable();
b463a6f7 5156 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5157 r = 1;
5158 goto out;
5159 }
5160
f656ce01 5161 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5162
b6c7a5dc
HB		 5163 kvm_guest_enter();
5164
42dbaa5a 5165 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5166 set_debugreg(0, 7);
5167 set_debugreg(vcpu->arch.eff_db[0], 0);
5168 set_debugreg(vcpu->arch.eff_db[1], 1);
5169 set_debugreg(vcpu->arch.eff_db[2], 2);
5170 set_debugreg(vcpu->arch.eff_db[3], 3);
5171 }
b6c7a5dc 5172
229456fc 5173 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5174 kvm_x86_ops->run(vcpu);
b6c7a5dc 5175
24f1e32c
FW		 5176 /*
5177 * If the guest has used debug registers, at least dr7
5178 * will be disabled while returning to the host.
5179 * If we don't have active breakpoints in the host, we don't
5180 * care about the messed up debug address registers. But if
5181 * we have some of them active, restore the old state.
5182 */
59d8eb53 5183 if (hw_breakpoint_active())
24f1e32c 5184 hw_breakpoint_restore();
42dbaa5a 5185
1d5f066e
ZA		 5186 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5187
d94e1dc9
AK		 5188 atomic_set(&vcpu->guest_mode, 0);
5189 smp_wmb();
b6c7a5dc
HB		 5190 local_irq_enable();
5191
5192 ++vcpu->stat.exits;
5193
5194 /*
5195 * We must have an instruction between local_irq_enable() and
5196 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5197 * the interrupt shadow. The stat.exits increment will do nicely.
5198 * But we need to prevent reordering, hence this barrier():
5199 */
5200 barrier();
5201
5202 kvm_guest_exit();
5203
5204 preempt_enable();
5205
f656ce01 5206 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5207
b6c7a5dc
HB		 5208 /*
5209 * Profile KVM exit RIPs:
5210 */
5211 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5212 unsigned long rip = kvm_rip_read(vcpu);
5213 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5214 }
5215
298101da 5216
b93463aa
AK		 5217 kvm_lapic_sync_from_vapic(vcpu);
5218
851ba692 5219 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5220out:
5221 return r;
5222}
b6c7a5dc 5223
09cec754 5224
851ba692 5225static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5226{
5227 int r;
f656ce01 5228 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5229
5230 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5231 pr_debug("vcpu %d received sipi with vector # %x\n",
5232 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5233 kvm_lapic_reset(vcpu);
5f179287 5234 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5235 if (r)
5236 return r;
5237 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5238 }
5239
f656ce01 5240 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5241 vapic_enter(vcpu);
5242
5243 r = 1;
5244 while (r > 0) {
af2152f5 5245 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5246 r = vcpu_enter_guest(vcpu);
d7690175 5247 else {
f656ce01 5248 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5249 kvm_vcpu_block(vcpu);
f656ce01 5250 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5251 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5252 {
5253 switch(vcpu->arch.mp_state) {
5254 case KVM_MP_STATE_HALTED:
d7690175 5255 vcpu->arch.mp_state =
09cec754
GN		 5256 KVM_MP_STATE_RUNNABLE;
5257 case KVM_MP_STATE_RUNNABLE:
5258 break;
5259 case KVM_MP_STATE_SIPI_RECEIVED:
5260 default:
5261 r = -EINTR;
5262 break;
5263 }
5264 }
d7690175
MT		 5265 }
5266
09cec754
GN		 5267 if (r <= 0)
5268 break;
5269
5270 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5271 if (kvm_cpu_has_pending_timer(vcpu))
5272 kvm_inject_pending_timer_irqs(vcpu);
5273
851ba692 5274 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5275 r = -EINTR;
851ba692 5276 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5277 ++vcpu->stat.request_irq_exits;
5278 }
5279 if (signal_pending(current)) {
5280 r = -EINTR;
851ba692 5281 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5282 ++vcpu->stat.signal_exits;
5283 }
5284 if (need_resched()) {
f656ce01 5285 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5286 kvm_resched(vcpu);
f656ce01 5287 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5288 }
b6c7a5dc
HB		 5289 }
5290
f656ce01 5291 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5292
b93463aa
AK		 5293 vapic_exit(vcpu);
5294
b6c7a5dc
HB		 5295 return r;
5296}
5297
5298int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5299{
5300 int r;
5301 sigset_t sigsaved;
5302
ac9f6dc0
AK		 5303 if (vcpu->sigset_active)
5304 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5305
a4535290 5306 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5307 kvm_vcpu_block(vcpu);
d7690175 5308 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5309 r = -EAGAIN;
5310 goto out;
b6c7a5dc
HB		 5311 }
5312
b6c7a5dc
HB		 5313 /* re-sync apic's tpr */
5314 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5315 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5316
d2ddd1c4 5317 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5318 if (vcpu->mmio_needed) {
5319 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5320 vcpu->mmio_read_completed = 1;
5321 vcpu->mmio_needed = 0;
b6c7a5dc 5322 }
f656ce01 5323 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5324 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5325 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5326 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5327 r = 0;
5328 goto out;
5329 }
5330 }
5fdbf976
MT		 5331 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5332 kvm_register_write(vcpu, VCPU_REGS_RAX,
5333 kvm_run->hypercall.ret);
b6c7a5dc 5334
851ba692 5335 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5336
5337out:
f1d86e46 5338 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5339 if (vcpu->sigset_active)
5340 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5341
b6c7a5dc
HB		 5342 return r;
5343}
5344
5345int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5346{
5fdbf976
MT		 5347 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5348 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5349 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5350 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5351 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5352 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5353 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5354 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5355#ifdef CONFIG_X86_64
5fdbf976
MT		 5356 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5357 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5358 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5359 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5360 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5361 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5362 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5363 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5364#endif
5365
5fdbf976 5366 regs->rip = kvm_rip_read(vcpu);
91586a3b 5367 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5368
b6c7a5dc
HB		 5369 return 0;
5370}
5371
5372int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5373{
5fdbf976
MT		 5374 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5375 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5376 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5377 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5378 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5379 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5380 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5381 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5382#ifdef CONFIG_X86_64
5fdbf976
MT		 5383 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5384 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5385 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5386 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5387 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5388 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5389 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5390 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5391#endif
5392
5fdbf976 5393 kvm_rip_write(vcpu, regs->rip);
91586a3b 5394 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5395
b4f14abd
JK		 5396 vcpu->arch.exception.pending = false;
5397
3842d135
AK		 5398 kvm_make_request(KVM_REQ_EVENT, vcpu);
5399
b6c7a5dc
HB		 5400 return 0;
5401}
5402
b6c7a5dc
HB		 5403void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5404{
5405 struct kvm_segment cs;
5406
3e6e0aab 5407 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5408 *db = cs.db;
5409 *l = cs.l;
5410}
5411EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5412
5413int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5414 struct kvm_sregs *sregs)
5415{
89a27f4d 5416 struct desc_ptr dt;
b6c7a5dc 5417
3e6e0aab
GT		 5418 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5419 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5420 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5421 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5422 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5423 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5424
3e6e0aab
GT		 5425 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5426 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5427
5428 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5429 sregs->idt.limit = dt.size;
5430 sregs->idt.base = dt.address;
b6c7a5dc 5431 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5432 sregs->gdt.limit = dt.size;
5433 sregs->gdt.base = dt.address;
b6c7a5dc 5434
4d4ec087 5435 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5436 sregs->cr2 = vcpu->arch.cr2;
5437 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5438 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5439 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5440 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5441 sregs->apic_base = kvm_get_apic_base(vcpu);
5442
923c61bb 5443 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5444
36752c9b 5445 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5446 set_bit(vcpu->arch.interrupt.nr,
5447 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5448
b6c7a5dc
HB		 5449 return 0;
5450}
5451
62d9f0db
MT		 5452int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5453 struct kvm_mp_state *mp_state)
5454{
62d9f0db 5455 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5456 return 0;
5457}
5458
5459int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5460 struct kvm_mp_state *mp_state)
5461{
62d9f0db 5462 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5463 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5464 return 0;
5465}
5466
e269fb21
JK		 5467int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5468 bool has_error_code, u32 error_code)
b6c7a5dc 5469{
4d2179e1 5470 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5471 int ret;
e01c2426 5472
8ec4722d 5473 init_emulate_ctxt(vcpu);
c697518a 5474
9aabc88f 5475 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5476 tss_selector, reason, has_error_code,
5477 error_code);
c697518a 5478
c697518a 5479 if (ret)
19d04437 5480 return EMULATE_FAIL;
37817f29 5481
4d2179e1 5482 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5483 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5484 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5485 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5486 return EMULATE_DONE;
37817f29
IE		 5487}
5488EXPORT_SYMBOL_GPL(kvm_task_switch);
5489
b6c7a5dc
HB		 5490int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5491 struct kvm_sregs *sregs)
5492{
5493 int mmu_reset_needed = 0;
923c61bb 5494 int pending_vec, max_bits;
89a27f4d 5495 struct desc_ptr dt;
b6c7a5dc 5496
89a27f4d
GN		 5497 dt.size = sregs->idt.limit;
5498 dt.address = sregs->idt.base;
b6c7a5dc 5499 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5500 dt.size = sregs->gdt.limit;
5501 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5502 kvm_x86_ops->set_gdt(vcpu, &dt);
5503
ad312c7c
ZX		 5504 vcpu->arch.cr2 = sregs->cr2;
5505 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5506 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5507
2d3ad1f4 5508 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5509
f6801dff 5510 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5511 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5512 kvm_set_apic_base(vcpu, sregs->apic_base);
5513
4d4ec087 5514 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5515 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5516 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5517
fc78f519 5518 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5519 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5520 if (sregs->cr4 & X86_CR4_OSXSAVE)
5521 update_cpuid(vcpu);
7c93be44 5522 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5523 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5524 mmu_reset_needed = 1;
5525 }
b6c7a5dc
HB		 5526
5527 if (mmu_reset_needed)
5528 kvm_mmu_reset_context(vcpu);
5529
923c61bb
GN		 5530 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5531 pending_vec = find_first_bit(
5532 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5533 if (pending_vec < max_bits) {
66fd3f7f 5534 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5535 pr_debug("Set back pending irq %d\n", pending_vec);
5536 if (irqchip_in_kernel(vcpu->kvm))
5537 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5538 }
5539
3e6e0aab
GT		 5540 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5541 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5542 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5543 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5544 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5545 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5546
3e6e0aab
GT		 5547 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5548 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5549
5f0269f5
ME		 5550 update_cr8_intercept(vcpu);
5551
9c3e4aab 5552 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5553 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5554 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5555 !is_protmode(vcpu))
9c3e4aab
MT		 5556 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5557
3842d135
AK		 5558 kvm_make_request(KVM_REQ_EVENT, vcpu);
5559
b6c7a5dc
HB		 5560 return 0;
5561}
5562
d0bfb940
JK		 5563int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5564 struct kvm_guest_debug *dbg)
b6c7a5dc 5565{
355be0b9 5566 unsigned long rflags;
ae675ef0 5567 int i, r;
b6c7a5dc 5568
4f926bf2
JK		 5569 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5570 r = -EBUSY;
5571 if (vcpu->arch.exception.pending)
2122ff5e 5572 goto out;
4f926bf2
JK		 5573 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5574 kvm_queue_exception(vcpu, DB_VECTOR);
5575 else
5576 kvm_queue_exception(vcpu, BP_VECTOR);
5577 }
5578
91586a3b
JK		 5579 /*
5580 * Read rflags as long as potentially injected trace flags are still
5581 * filtered out.
5582 */
5583 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5584
5585 vcpu->guest_debug = dbg->control;
5586 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5587 vcpu->guest_debug = 0;
5588
5589 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5590 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5591 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5592 vcpu->arch.switch_db_regs =
5593 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5594 } else {
5595 for (i = 0; i < KVM_NR_DB_REGS; i++)
5596 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5597 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5598 }
5599
f92653ee
JK		 5600 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5601 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5602 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5603
91586a3b
JK		 5604 /*
5605 * Trigger an rflags update that will inject or remove the trace
5606 * flags.
5607 */
5608 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5609
355be0b9 5610 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5611
4f926bf2 5612 r = 0;
d0bfb940 5613
2122ff5e 5614out:
b6c7a5dc
HB		 5615
5616 return r;
5617}
5618
8b006791
ZX		 5619/*
5620 * Translate a guest virtual address to a guest physical address.
5621 */
5622int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5623 struct kvm_translation *tr)
5624{
5625 unsigned long vaddr = tr->linear_address;
5626 gpa_t gpa;
f656ce01 5627 int idx;
8b006791 5628
f656ce01 5629 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5630 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5631 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5632 tr->physical_address = gpa;
5633 tr->valid = gpa != UNMAPPED_GVA;
5634 tr->writeable = 1;
5635 tr->usermode = 0;
8b006791
ZX		 5636
5637 return 0;
5638}
5639
d0752060
HB		 5640int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5641{
98918833
SY		 5642 struct i387_fxsave_struct *fxsave =
5643 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5644
d0752060
HB		 5645 memcpy(fpu->fpr, fxsave->st_space, 128);
5646 fpu->fcw = fxsave->cwd;
5647 fpu->fsw = fxsave->swd;
5648 fpu->ftwx = fxsave->twd;
5649 fpu->last_opcode = fxsave->fop;
5650 fpu->last_ip = fxsave->rip;
5651 fpu->last_dp = fxsave->rdp;
5652 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5653
d0752060
HB		 5654 return 0;
5655}
5656
5657int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5658{
98918833
SY		 5659 struct i387_fxsave_struct *fxsave =
5660 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5661
d0752060
HB		 5662 memcpy(fxsave->st_space, fpu->fpr, 128);
5663 fxsave->cwd = fpu->fcw;
5664 fxsave->swd = fpu->fsw;
5665 fxsave->twd = fpu->ftwx;
5666 fxsave->fop = fpu->last_opcode;
5667 fxsave->rip = fpu->last_ip;
5668 fxsave->rdp = fpu->last_dp;
5669 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5670
d0752060
HB		 5671 return 0;
5672}
5673
10ab25cd 5674int fx_init(struct kvm_vcpu *vcpu)
d0752060 5675{
10ab25cd
JK		 5676 int err;
5677
5678 err = fpu_alloc(&vcpu->arch.guest_fpu);
5679 if (err)
5680 return err;
5681
98918833 5682 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5683
2acf923e
DC		 5684 /*
5685 * Ensure guest xcr0 is valid for loading
5686 */
5687 vcpu->arch.xcr0 = XSTATE_FP;
5688
ad312c7c 5689 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5690
5691 return 0;
d0752060
HB		 5692}
5693EXPORT_SYMBOL_GPL(fx_init);
5694
98918833
SY		 5695static void fx_free(struct kvm_vcpu *vcpu)
5696{
5697 fpu_free(&vcpu->arch.guest_fpu);
5698}
5699
d0752060
HB		 5700void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5701{
2608d7a1 5702 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5703 return;
5704
2acf923e
DC		 5705 /*
5706 * Restore all possible states in the guest,
5707 * and assume host would use all available bits.
5708 * Guest xcr0 would be loaded later.
5709 */
5710 kvm_put_guest_xcr0(vcpu);
d0752060 5711 vcpu->guest_fpu_loaded = 1;
7cf30855 5712 unlazy_fpu(current);
98918833 5713 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5714 trace_kvm_fpu(1);
d0752060 5715}
d0752060
HB		 5716
5717void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5718{
2acf923e
DC		 5719 kvm_put_guest_xcr0(vcpu);
5720
d0752060
HB		 5721 if (!vcpu->guest_fpu_loaded)
5722 return;
5723
5724 vcpu->guest_fpu_loaded = 0;
98918833 5725 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5726 ++vcpu->stat.fpu_reload;
a8eeb04a 5727 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5728 trace_kvm_fpu(0);
d0752060 5729}
e9b11c17
ZX		 5730
5731void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5732{
7f1ea208
JR		 5733 if (vcpu->arch.time_page) {
5734 kvm_release_page_dirty(vcpu->arch.time_page);
5735 vcpu->arch.time_page = NULL;
5736 }
5737
f5f48ee1 5738 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5739 fx_free(vcpu);
e9b11c17
ZX		 5740 kvm_x86_ops->vcpu_free(vcpu);
5741}
5742
5743struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5744 unsigned int id)
5745{
6755bae8
ZA		 5746 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5747 printk_once(KERN_WARNING
5748 "kvm: SMP vm created on host with unstable TSC; "
5749 "guest TSC will not be reliable\n");
26e5215f
AK		 5750 return kvm_x86_ops->vcpu_create(kvm, id);
5751}
e9b11c17 5752
26e5215f
AK		 5753int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5754{
5755 int r;
e9b11c17 5756
0bed3b56 5757 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5758 vcpu_load(vcpu);
5759 r = kvm_arch_vcpu_reset(vcpu);
5760 if (r == 0)
5761 r = kvm_mmu_setup(vcpu);
5762 vcpu_put(vcpu);
5763 if (r < 0)
5764 goto free_vcpu;
5765
26e5215f 5766 return 0;
e9b11c17
ZX		 5767free_vcpu:
5768 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5769 return r;
e9b11c17
ZX		 5770}
5771
d40ccc62 5772void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5773{
5774 vcpu_load(vcpu);
5775 kvm_mmu_unload(vcpu);
5776 vcpu_put(vcpu);
5777
98918833 5778 fx_free(vcpu);
e9b11c17
ZX		 5779 kvm_x86_ops->vcpu_free(vcpu);
5780}
5781
5782int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5783{
448fa4a9
JK		 5784 vcpu->arch.nmi_pending = false;
5785 vcpu->arch.nmi_injected = false;
5786
42dbaa5a
JK		 5787 vcpu->arch.switch_db_regs = 0;
5788 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5789 vcpu->arch.dr6 = DR6_FIXED_1;
5790 vcpu->arch.dr7 = DR7_FIXED_1;
5791
3842d135
AK		 5792 kvm_make_request(KVM_REQ_EVENT, vcpu);
5793
e9b11c17
ZX		 5794 return kvm_x86_ops->vcpu_reset(vcpu);
5795}
5796
10474ae8 5797int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5798{
ca84d1a2
ZA		 5799 struct kvm *kvm;
5800 struct kvm_vcpu *vcpu;
5801 int i;
18863bdd
AK		 5802
5803 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5804 list_for_each_entry(kvm, &vm_list, vm_list)
5805 kvm_for_each_vcpu(i, vcpu, kvm)
5806 if (vcpu->cpu == smp_processor_id())
c285545f 5807 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5808 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5809}
5810
5811void kvm_arch_hardware_disable(void *garbage)
5812{
5813 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5814 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5815}
5816
5817int kvm_arch_hardware_setup(void)
5818{
5819 return kvm_x86_ops->hardware_setup();
5820}
5821
5822void kvm_arch_hardware_unsetup(void)
5823{
5824 kvm_x86_ops->hardware_unsetup();
5825}
5826
5827void kvm_arch_check_processor_compat(void *rtn)
5828{
5829 kvm_x86_ops->check_processor_compatibility(rtn);
5830}
5831
5832int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5833{
5834 struct page *page;
5835 struct kvm *kvm;
5836 int r;
5837
5838 BUG_ON(vcpu->kvm == NULL);
5839 kvm = vcpu->kvm;
5840
9aabc88f 5841 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5842 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5843 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5844 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5845 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5846 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5847 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5848 else
a4535290 5849 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5850
5851 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5852 if (!page) {
5853 r = -ENOMEM;
5854 goto fail;
5855 }
ad312c7c 5856 vcpu->arch.pio_data = page_address(page);
e9b11c17 5857
c285545f
ZA		 5858 if (!kvm->arch.virtual_tsc_khz)
5859 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5860
e9b11c17
ZX		 5861 r = kvm_mmu_create(vcpu);
5862 if (r < 0)
5863 goto fail_free_pio_data;
5864
5865 if (irqchip_in_kernel(kvm)) {
5866 r = kvm_create_lapic(vcpu);
5867 if (r < 0)
5868 goto fail_mmu_destroy;
5869 }
5870
890ca9ae
HY		 5871 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5872 GFP_KERNEL);
5873 if (!vcpu->arch.mce_banks) {
5874 r = -ENOMEM;
443c39bc 5875 goto fail_free_lapic;
890ca9ae
HY		 5876 }
5877 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5878
f5f48ee1
SY		 5879 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5880 goto fail_free_mce_banks;
5881
e9b11c17 5882 return 0;
f5f48ee1
SY		 5883fail_free_mce_banks:
5884 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5885fail_free_lapic:
5886 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5887fail_mmu_destroy:
5888 kvm_mmu_destroy(vcpu);
5889fail_free_pio_data:
ad312c7c 5890 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5891fail:
5892 return r;
5893}
5894
5895void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5896{
f656ce01
MT		 5897 int idx;
5898
36cb93fd 5899 kfree(vcpu->arch.mce_banks);
e9b11c17 5900 kvm_free_lapic(vcpu);
f656ce01 5901 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5902 kvm_mmu_destroy(vcpu);
f656ce01 5903 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5904 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5905}
d19a9cd2
ZX		 5906
5907struct kvm *kvm_arch_create_vm(void)
5908{
5909 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5910
5911 if (!kvm)
5912 return ERR_PTR(-ENOMEM);
5913
f05e70ac 5914 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5915 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5916
5550af4d
SY		 5917 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5918 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5919
99e3e30a 5920 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5921
d19a9cd2
ZX		 5922 return kvm;
5923}
5924
5925static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5926{
5927 vcpu_load(vcpu);
5928 kvm_mmu_unload(vcpu);
5929 vcpu_put(vcpu);
5930}
5931
5932static void kvm_free_vcpus(struct kvm *kvm)
5933{
5934 unsigned int i;
988a2cae 5935 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5936
5937 /*
5938 * Unpin any mmu pages first.
5939 */
988a2cae
GN		 5940 kvm_for_each_vcpu(i, vcpu, kvm)
5941 kvm_unload_vcpu_mmu(vcpu);
5942 kvm_for_each_vcpu(i, vcpu, kvm)
5943 kvm_arch_vcpu_free(vcpu);
5944
5945 mutex_lock(&kvm->lock);
5946 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5947 kvm->vcpus[i] = NULL;
d19a9cd2 5948
988a2cae
GN		 5949 atomic_set(&kvm->online_vcpus, 0);
5950 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5951}
5952
ad8ba2cd
SY		 5953void kvm_arch_sync_events(struct kvm *kvm)
5954{
ba4cef31 5955 kvm_free_all_assigned_devices(kvm);
aea924f6 5956 kvm_free_pit(kvm);
ad8ba2cd
SY		 5957}
5958
d19a9cd2
ZX		 5959void kvm_arch_destroy_vm(struct kvm *kvm)
5960{
6eb55818 5961 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5962 kfree(kvm->arch.vpic);
5963 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5964 kvm_free_vcpus(kvm);
5965 kvm_free_physmem(kvm);
3d45830c
AK		 5966 if (kvm->arch.apic_access_page)
5967 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5968 if (kvm->arch.ept_identity_pagetable)
5969 put_page(kvm->arch.ept_identity_pagetable);
64749204 5970 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5971 kfree(kvm);
5972}
0de10343 5973
f7784b8e
MT		 5974int kvm_arch_prepare_memory_region(struct kvm *kvm,
5975 struct kvm_memory_slot *memslot,
0de10343 5976 struct kvm_memory_slot old,
f7784b8e 5977 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5978 int user_alloc)
5979{
f7784b8e 5980 int npages = memslot->npages;
7ac77099
AK		 5981 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5982
5983 /* Prevent internal slot pages from being moved by fork()/COW. */
5984 if (memslot->id >= KVM_MEMORY_SLOTS)
5985 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5986
5987 /*To keep backward compatibility with older userspace,
5988 *x86 needs to hanlde !user_alloc case.
5989 */
5990 if (!user_alloc) {
5991 if (npages && !old.rmap) {
604b38ac
AA		 5992 unsigned long userspace_addr;
5993
72dc67a6 5994 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5995 userspace_addr = do_mmap(NULL, 0,
5996 npages * PAGE_SIZE,
5997 PROT_READ | PROT_WRITE,
7ac77099 5998 map_flags,
604b38ac 5999 0);
72dc67a6 6000 up_write(&current->mm->mmap_sem);
0de10343 6001
604b38ac
AA		 6002 if (IS_ERR((void *)userspace_addr))
6003 return PTR_ERR((void *)userspace_addr);
6004
604b38ac 6005 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6006 }
6007 }
6008
f7784b8e
MT		 6009
6010 return 0;
6011}
6012
6013void kvm_arch_commit_memory_region(struct kvm *kvm,
6014 struct kvm_userspace_memory_region *mem,
6015 struct kvm_memory_slot old,
6016 int user_alloc)
6017{
6018
6019 int npages = mem->memory_size >> PAGE_SHIFT;
6020
6021 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6022 int ret;
6023
6024 down_write(&current->mm->mmap_sem);
6025 ret = do_munmap(current->mm, old.userspace_addr,
6026 old.npages * PAGE_SIZE);
6027 up_write(&current->mm->mmap_sem);
6028 if (ret < 0)
6029 printk(KERN_WARNING
6030 "kvm_vm_ioctl_set_memory_region: "
6031 "failed to munmap memory\n");
6032 }
6033
7c8a83b7 6034 spin_lock(&kvm->mmu_lock);
f05e70ac 6035 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6036 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6037 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6038 }
6039
6040 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6041 spin_unlock(&kvm->mmu_lock);
0de10343 6042}
1d737c8a 6043
34d4cb8f
MT		 6044void kvm_arch_flush_shadow(struct kvm *kvm)
6045{
6046 kvm_mmu_zap_all(kvm);
8986ecc0 6047 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6048}
6049
1d737c8a
ZX		 6050int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6051{
a4535290 6052 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 6053 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6054 || vcpu->arch.nmi_pending ||
6055 (kvm_arch_interrupt_allowed(vcpu) &&
6056 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6057}
5736199a 6058
5736199a
ZX		 6059void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6060{
32f88400
MT		 6061 int me;
6062 int cpu = vcpu->cpu;
5736199a
ZX		 6063
6064 if (waitqueue_active(&vcpu->wq)) {
6065 wake_up_interruptible(&vcpu->wq);
6066 ++vcpu->stat.halt_wakeup;
6067 }
32f88400
MT		 6068
6069 me = get_cpu();
6070 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6071 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6072 smp_send_reschedule(cpu);
e9571ed5 6073 put_cpu();
5736199a 6074}
78646121
GN		 6075
6076int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6077{
6078 return kvm_x86_ops->interrupt_allowed(vcpu);
6079}
229456fc 6080
f92653ee
JK		 6081bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6082{
6083 unsigned long current_rip = kvm_rip_read(vcpu) +
6084 get_segment_base(vcpu, VCPU_SREG_CS);
6085
6086 return current_rip == linear_rip;
6087}
6088EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6089
94fe45da
JK		 6090unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6091{
6092 unsigned long rflags;
6093
6094 rflags = kvm_x86_ops->get_rflags(vcpu);
6095 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6096 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6097 return rflags;
6098}
6099EXPORT_SYMBOL_GPL(kvm_get_rflags);
6100
6101void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6102{
6103 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6104 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6105 rflags |= X86_EFLAGS_TF;
94fe45da 6106 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6107 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6108}
6109EXPORT_SYMBOL_GPL(kvm_set_rflags);
6110
229456fc
MT		 6111EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6112EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6113EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6114EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6115EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6116EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6117EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6118EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6119EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6120EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6121EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6122EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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