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KVM: x86: Use unlazy_fpu() for host FPU
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
7cf30855 55#include <asm/i387.h>
043405e1 56
313a3dc7 57#define MAX_IO_MSRS 256
a03490ed
CO		 58#define CR0_RESERVED_BITS \
59 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
60 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
61 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
62#define CR4_RESERVED_BITS \
63 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
64 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
65 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
66 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
67
68#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 69
70#define KVM_MAX_MCE_BANKS 32
71#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
72
50a37eb4
JR		 73/* EFER defaults:
74 * - enable syscall per default because its emulated by KVM
75 * - enable LME and LMA per default on 64 bit KVM
76 */
77#ifdef CONFIG_X86_64
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
79#else
80static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 87static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
88 struct kvm_cpuid_entry2 __user *entries);
89
97896d04 90struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 91EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 92
ed85c068
AP		 93int ignore_msrs = 0;
94module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
95
18863bdd
AK		 96#define KVM_NR_SHARED_MSRS 16
97
98struct kvm_shared_msrs_global {
99 int nr;
2bf78fa7 100 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 101};
102
103struct kvm_shared_msrs {
104 struct user_return_notifier urn;
105 bool registered;
2bf78fa7
SY		 106 struct kvm_shared_msr_values {
107 u64 host;
108 u64 curr;
109 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 110};
111
112static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
113static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
114
417bc304 115struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 116 { "pf_fixed", VCPU_STAT(pf_fixed) },
117 { "pf_guest", VCPU_STAT(pf_guest) },
118 { "tlb_flush", VCPU_STAT(tlb_flush) },
119 { "invlpg", VCPU_STAT(invlpg) },
120 { "exits", VCPU_STAT(exits) },
121 { "io_exits", VCPU_STAT(io_exits) },
122 { "mmio_exits", VCPU_STAT(mmio_exits) },
123 { "signal_exits", VCPU_STAT(signal_exits) },
124 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 125 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 126 { "halt_exits", VCPU_STAT(halt_exits) },
127 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 128 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 129 { "request_irq", VCPU_STAT(request_irq_exits) },
130 { "irq_exits", VCPU_STAT(irq_exits) },
131 { "host_state_reload", VCPU_STAT(host_state_reload) },
132 { "efer_reload", VCPU_STAT(efer_reload) },
133 { "fpu_reload", VCPU_STAT(fpu_reload) },
134 { "insn_emulation", VCPU_STAT(insn_emulation) },
135 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 136 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 137 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 138 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
139 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
140 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
141 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
142 { "mmu_flooded", VM_STAT(mmu_flooded) },
143 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 144 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 145 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 146 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 147 { "largepages", VM_STAT(lpages) },
417bc304
HB		 148 { NULL }
149};
150
18863bdd
AK		 151static void kvm_on_user_return(struct user_return_notifier *urn)
152{
153 unsigned slot;
18863bdd
AK		 154 struct kvm_shared_msrs *locals
155 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 156 struct kvm_shared_msr_values *values;
18863bdd
AK		 157
158 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 159 values = &locals->values[slot];
160 if (values->host != values->curr) {
161 wrmsrl(shared_msrs_global.msrs[slot], values->host);
162 values->curr = values->host;
18863bdd
AK		 163 }
164 }
165 locals->registered = false;
166 user_return_notifier_unregister(urn);
167}
168
2bf78fa7 169static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 170{
2bf78fa7 171 struct kvm_shared_msrs *smsr;
18863bdd
AK		 172 u64 value;
173
2bf78fa7
SY		 174 smsr = &__get_cpu_var(shared_msrs);
175 /* only read, and nobody should modify it at this time,
176 * so don't need lock */
177 if (slot >= shared_msrs_global.nr) {
178 printk(KERN_ERR "kvm: invalid MSR slot!");
179 return;
180 }
181 rdmsrl_safe(msr, &value);
182 smsr->values[slot].host = value;
183 smsr->values[slot].curr = value;
184}
185
186void kvm_define_shared_msr(unsigned slot, u32 msr)
187{
18863bdd
AK		 188 if (slot >= shared_msrs_global.nr)
189 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 190 shared_msrs_global.msrs[slot] = msr;
191 /* we need ensured the shared_msr_global have been updated */
192 smp_wmb();
18863bdd
AK		 193}
194EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
195
196static void kvm_shared_msr_cpu_online(void)
197{
198 unsigned i;
18863bdd
AK		 199
200 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 201 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 202}
203
d5696725 204void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 205{
206 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
207
2bf78fa7 208 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 209 return;
2bf78fa7
SY		 210 smsr->values[slot].curr = value;
211 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 212 if (!smsr->registered) {
213 smsr->urn.on_user_return = kvm_on_user_return;
214 user_return_notifier_register(&smsr->urn);
215 smsr->registered = true;
216 }
217}
218EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
219
3548bab5
AK		 220static void drop_user_return_notifiers(void *ignore)
221{
222 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
223
224 if (smsr->registered)
225 kvm_on_user_return(&smsr->urn);
226}
227
6866b83e
CO		 228u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
229{
230 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 231 return vcpu->arch.apic_base;
6866b83e 232 else
ad312c7c 233 return vcpu->arch.apic_base;
6866b83e
CO		 234}
235EXPORT_SYMBOL_GPL(kvm_get_apic_base);
236
237void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
238{
239 /* TODO: reserve bits check */
240 if (irqchip_in_kernel(vcpu->kvm))
241 kvm_lapic_set_base(vcpu, data);
242 else
ad312c7c 243 vcpu->arch.apic_base = data;
6866b83e
CO		 244}
245EXPORT_SYMBOL_GPL(kvm_set_apic_base);
246
3fd28fce
ED		 247#define EXCPT_BENIGN 0
248#define EXCPT_CONTRIBUTORY 1
249#define EXCPT_PF 2
250
251static int exception_class(int vector)
252{
253 switch (vector) {
254 case PF_VECTOR:
255 return EXCPT_PF;
256 case DE_VECTOR:
257 case TS_VECTOR:
258 case NP_VECTOR:
259 case SS_VECTOR:
260 case GP_VECTOR:
261 return EXCPT_CONTRIBUTORY;
262 default:
263 break;
264 }
265 return EXCPT_BENIGN;
266}
267
268static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 269 unsigned nr, bool has_error, u32 error_code,
270 bool reinject)
3fd28fce
ED		 271{
272 u32 prev_nr;
273 int class1, class2;
274
275 if (!vcpu->arch.exception.pending) {
276 queue:
277 vcpu->arch.exception.pending = true;
278 vcpu->arch.exception.has_error_code = has_error;
279 vcpu->arch.exception.nr = nr;
280 vcpu->arch.exception.error_code = error_code;
3f0fd292 281 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 282 return;
283 }
284
285 /* to check exception */
286 prev_nr = vcpu->arch.exception.nr;
287 if (prev_nr == DF_VECTOR) {
288 /* triple fault -> shutdown */
289 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
290 return;
291 }
292 class1 = exception_class(prev_nr);
293 class2 = exception_class(nr);
294 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
295 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
296 /* generate double fault per SDM Table 5-5 */
297 vcpu->arch.exception.pending = true;
298 vcpu->arch.exception.has_error_code = true;
299 vcpu->arch.exception.nr = DF_VECTOR;
300 vcpu->arch.exception.error_code = 0;
301 } else
302 /* replace previous exception with a new one in a hope
303 that instruction re-execution will regenerate lost
304 exception */
305 goto queue;
306}
307
298101da
AK		 308void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
309{
ce7ddec4 310 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 311}
312EXPORT_SYMBOL_GPL(kvm_queue_exception);
313
ce7ddec4
JR		 314void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
315{
316 kvm_multiple_exception(vcpu, nr, false, 0, true);
317}
318EXPORT_SYMBOL_GPL(kvm_requeue_exception);
319
c3c91fee
AK		 320void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
321 u32 error_code)
322{
323 ++vcpu->stat.pf_guest;
ad312c7c 324 vcpu->arch.cr2 = addr;
c3c91fee
AK		 325 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
326}
327
3419ffc8
SY		 328void kvm_inject_nmi(struct kvm_vcpu *vcpu)
329{
330 vcpu->arch.nmi_pending = 1;
331}
332EXPORT_SYMBOL_GPL(kvm_inject_nmi);
333
298101da
AK		 334void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
339
ce7ddec4
JR		 340void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
341{
342 kvm_multiple_exception(vcpu, nr, true, error_code, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
345
0a79b009
AK		 346/*
347 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
348 * a #GP and return false.
349 */
350bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 351{
0a79b009
AK		 352 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
353 return true;
354 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
355 return false;
298101da 356}
0a79b009 357EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 358
a03490ed
CO		 359/*
360 * Load the pae pdptrs. Return true is they are all valid.
361 */
362int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
363{
364 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
365 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
366 int i;
367 int ret;
ad312c7c 368 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 369
a03490ed
CO		 370 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
371 offset * sizeof(u64), sizeof(pdpte));
372 if (ret < 0) {
373 ret = 0;
374 goto out;
375 }
376 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 377 if (is_present_gpte(pdpte[i]) &&
20c466b5 378 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 379 ret = 0;
380 goto out;
381 }
382 }
383 ret = 1;
384
ad312c7c 385 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 386 __set_bit(VCPU_EXREG_PDPTR,
387 (unsigned long *)&vcpu->arch.regs_avail);
388 __set_bit(VCPU_EXREG_PDPTR,
389 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 390out:
a03490ed
CO		 391
392 return ret;
393}
cc4b6871 394EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 395
d835dfec
AK		 396static bool pdptrs_changed(struct kvm_vcpu *vcpu)
397{
ad312c7c 398 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 399 bool changed = true;
400 int r;
401
402 if (is_long_mode(vcpu) || !is_pae(vcpu))
403 return false;
404
6de4f3ad
AK		 405 if (!test_bit(VCPU_EXREG_PDPTR,
406 (unsigned long *)&vcpu->arch.regs_avail))
407 return true;
408
ad312c7c 409 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 410 if (r < 0)
411 goto out;
ad312c7c 412 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 413out:
d835dfec
AK		 414
415 return changed;
416}
417
0f12244f 418static int __kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 419{
aad82703
SY		 420 unsigned long old_cr0 = kvm_read_cr0(vcpu);
421 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
422 X86_CR0_CD | X86_CR0_NW;
423
f9a48e6a
AK		 424 cr0 |= X86_CR0_ET;
425
ab344828 426#ifdef CONFIG_X86_64
0f12244f
GN		 427 if (cr0 & 0xffffffff00000000UL)
428 return 1;
ab344828
GN		 429#endif
430
431 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 432
0f12244f
GN		 433 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
434 return 1;
a03490ed 435
0f12244f
GN		 436 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
437 return 1;
a03490ed
CO		 438
439 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
440#ifdef CONFIG_X86_64
f6801dff 441 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 442 int cs_db, cs_l;
443
0f12244f
GN		 444 if (!is_pae(vcpu))
445 return 1;
a03490ed 446 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 447 if (cs_l)
448 return 1;
a03490ed
CO		 449 } else
450#endif
0f12244f
GN		 451 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
452 return 1;
a03490ed
CO		 453 }
454
455 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 456
aad82703
SY		 457 if ((cr0 ^ old_cr0) & update_bits)
458 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 459 return 0;
460}
461
462void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
463{
464 if (__kvm_set_cr0(vcpu, cr0))
465 kvm_inject_gp(vcpu, 0);
a03490ed 466}
2d3ad1f4 467EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 468
2d3ad1f4 469void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 470{
f78e9176 471 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 472}
2d3ad1f4 473EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 474
0f12244f 475int __kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 476{
fc78f519 477 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 478 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
479
0f12244f
GN		 480 if (cr4 & CR4_RESERVED_BITS)
481 return 1;
a03490ed
CO		 482
483 if (is_long_mode(vcpu)) {
0f12244f
GN		 484 if (!(cr4 & X86_CR4_PAE))
485 return 1;
a2edf57f
AK		 486 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
487 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 488 && !load_pdptrs(vcpu, vcpu->arch.cr3))
489 return 1;
490
491 if (cr4 & X86_CR4_VMXE)
492 return 1;
a03490ed 493
a03490ed 494 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 495
aad82703
SY		 496 if ((cr4 ^ old_cr4) & pdptr_bits)
497 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 498
499 return 0;
500}
501
502void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
503{
504 if (__kvm_set_cr4(vcpu, cr4))
505 kvm_inject_gp(vcpu, 0);
a03490ed 506}
2d3ad1f4 507EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 508
0f12244f 509static int __kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 510{
ad312c7c 511 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 512 kvm_mmu_sync_roots(vcpu);
d835dfec 513 kvm_mmu_flush_tlb(vcpu);
0f12244f 514 return 0;
d835dfec
AK		 515 }
516
a03490ed 517 if (is_long_mode(vcpu)) {
0f12244f
GN		 518 if (cr3 & CR3_L_MODE_RESERVED_BITS)
519 return 1;
a03490ed
CO		 520 } else {
521 if (is_pae(vcpu)) {
0f12244f
GN		 522 if (cr3 & CR3_PAE_RESERVED_BITS)
523 return 1;
524 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
525 return 1;
a03490ed
CO		 526 }
527 /*
528 * We don't check reserved bits in nonpae mode, because
529 * this isn't enforced, and VMware depends on this.
530 */
531 }
532
a03490ed
CO		 533 /*
534 * Does the new cr3 value map to physical memory? (Note, we
535 * catch an invalid cr3 even in real-mode, because it would
536 * cause trouble later on when we turn on paging anyway.)
537 *
538 * A real CPU would silently accept an invalid cr3 and would
539 * attempt to use it - with largely undefined (and often hard
540 * to debug) behavior on the guest side.
541 */
542 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 543 return 1;
544 vcpu->arch.cr3 = cr3;
545 vcpu->arch.mmu.new_cr3(vcpu);
546 return 0;
547}
548
549void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
550{
551 if (__kvm_set_cr3(vcpu, cr3))
c1a5d4f9 552 kvm_inject_gp(vcpu, 0);
a03490ed 553}
2d3ad1f4 554EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 555
0f12244f 556int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 557{
0f12244f
GN		 558 if (cr8 & CR8_RESERVED_BITS)
559 return 1;
a03490ed
CO		 560 if (irqchip_in_kernel(vcpu->kvm))
561 kvm_lapic_set_tpr(vcpu, cr8);
562 else
ad312c7c 563 vcpu->arch.cr8 = cr8;
0f12244f
GN		 564 return 0;
565}
566
567void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
568{
569 if (__kvm_set_cr8(vcpu, cr8))
570 kvm_inject_gp(vcpu, 0);
a03490ed 571}
2d3ad1f4 572EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 573
2d3ad1f4 574unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 575{
576 if (irqchip_in_kernel(vcpu->kvm))
577 return kvm_lapic_get_cr8(vcpu);
578 else
ad312c7c 579 return vcpu->arch.cr8;
a03490ed 580}
2d3ad1f4 581EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 582
338dbc97 583static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 584{
585 switch (dr) {
586 case 0 ... 3:
587 vcpu->arch.db[dr] = val;
588 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
589 vcpu->arch.eff_db[dr] = val;
590 break;
591 case 4:
338dbc97
GN		 592 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
593 return 1; /* #UD */
020df079
GN		 594 /* fall through */
595 case 6:
338dbc97
GN		 596 if (val & 0xffffffff00000000ULL)
597 return -1; /* #GP */
020df079
GN		 598 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
599 break;
600 case 5:
338dbc97
GN		 601 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
602 return 1; /* #UD */
020df079
GN		 603 /* fall through */
604 default: /* 7 */
338dbc97
GN		 605 if (val & 0xffffffff00000000ULL)
606 return -1; /* #GP */
020df079
GN		 607 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
608 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
609 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
610 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
611 }
612 break;
613 }
614
615 return 0;
616}
338dbc97
GN		 617
618int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
619{
620 int res;
621
622 res = __kvm_set_dr(vcpu, dr, val);
623 if (res > 0)
624 kvm_queue_exception(vcpu, UD_VECTOR);
625 else if (res < 0)
626 kvm_inject_gp(vcpu, 0);
627
628 return res;
629}
020df079
GN		 630EXPORT_SYMBOL_GPL(kvm_set_dr);
631
338dbc97 632static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 633{
634 switch (dr) {
635 case 0 ... 3:
636 *val = vcpu->arch.db[dr];
637 break;
638 case 4:
338dbc97 639 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 640 return 1;
020df079
GN		 641 /* fall through */
642 case 6:
643 *val = vcpu->arch.dr6;
644 break;
645 case 5:
338dbc97 646 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 647 return 1;
020df079
GN		 648 /* fall through */
649 default: /* 7 */
650 *val = vcpu->arch.dr7;
651 break;
652 }
653
654 return 0;
655}
338dbc97
GN		 656
657int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
658{
659 if (_kvm_get_dr(vcpu, dr, val)) {
660 kvm_queue_exception(vcpu, UD_VECTOR);
661 return 1;
662 }
663 return 0;
664}
020df079
GN		 665EXPORT_SYMBOL_GPL(kvm_get_dr);
666
d8017474
AG		 667static inline u32 bit(int bitno)
668{
669 return 1 << (bitno & 31);
670}
671
043405e1
CO		 672/*
673 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
674 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
675 *
676 * This list is modified at module load time to reflect the
e3267cbb
GC		 677 * capabilities of the host cpu. This capabilities test skips MSRs that are
678 * kvm-specific. Those are put in the beginning of the list.
043405e1 679 */
e3267cbb 680
11c6bffa 681#define KVM_SAVE_MSRS_BEGIN 7
043405e1 682static u32 msrs_to_save[] = {
e3267cbb 683 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 684 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 685 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 686 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 687 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
688 MSR_K6_STAR,
689#ifdef CONFIG_X86_64
690 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
691#endif
e3267cbb 692 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 693};
694
695static unsigned num_msrs_to_save;
696
697static u32 emulated_msrs[] = {
698 MSR_IA32_MISC_ENABLE,
699};
700
b69e8cae 701static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 702{
aad82703
SY		 703 u64 old_efer = vcpu->arch.efer;
704
b69e8cae
RJ		 705 if (efer & efer_reserved_bits)
706 return 1;
15c4a640
CO		 707
708 if (is_paging(vcpu)
b69e8cae
RJ		 709 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
710 return 1;
15c4a640 711
1b2fd70c
AG		 712 if (efer & EFER_FFXSR) {
713 struct kvm_cpuid_entry2 *feat;
714
715 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 716 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
717 return 1;
1b2fd70c
AG		 718 }
719
d8017474
AG		 720 if (efer & EFER_SVME) {
721 struct kvm_cpuid_entry2 *feat;
722
723 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 724 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
725 return 1;
d8017474
AG		 726 }
727
15c4a640 728 efer &= ~EFER_LMA;
f6801dff 729 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 730
a3d204e2
SY		 731 kvm_x86_ops->set_efer(vcpu, efer);
732
9645bb56
AK		 733 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
734 kvm_mmu_reset_context(vcpu);
b69e8cae 735
aad82703
SY		 736 /* Update reserved bits */
737 if ((efer ^ old_efer) & EFER_NX)
738 kvm_mmu_reset_context(vcpu);
739
b69e8cae 740 return 0;
15c4a640
CO		 741}
742
f2b4b7dd
JR		 743void kvm_enable_efer_bits(u64 mask)
744{
745 efer_reserved_bits &= ~mask;
746}
747EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
748
749
15c4a640
CO		 750/*
751 * Writes msr value into into the appropriate "register".
752 * Returns 0 on success, non-0 otherwise.
753 * Assumes vcpu_load() was already called.
754 */
755int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
756{
757 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
758}
759
313a3dc7
CO		 760/*
761 * Adapt set_msr() to msr_io()'s calling convention
762 */
763static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
764{
765 return kvm_set_msr(vcpu, index, *data);
766}
767
18068523
GOC		 768static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
769{
9ed3c444
AK		 770 int version;
771 int r;
50d0a0f9 772 struct pvclock_wall_clock wc;
923de3cf 773 struct timespec boot;
18068523
GOC		 774
775 if (!wall_clock)
776 return;
777
9ed3c444
AK		 778 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
779 if (r)
780 return;
781
782 if (version & 1)
783 ++version; /* first time write, random junk */
784
785 ++version;
18068523 786
18068523
GOC		 787 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
788
50d0a0f9
GH		 789 /*
790 * The guest calculates current wall clock time by adding
791 * system time (updated by kvm_write_guest_time below) to the
792 * wall clock specified here. guest system time equals host
793 * system time for us, thus we must fill in host boot time here.
794 */
923de3cf 795 getboottime(&boot);
50d0a0f9
GH		 796
797 wc.sec = boot.tv_sec;
798 wc.nsec = boot.tv_nsec;
799 wc.version = version;
18068523
GOC		 800
801 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
802
803 version++;
804 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 805}
806
50d0a0f9
GH		 807static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
808{
809 uint32_t quotient, remainder;
810
811 /* Don't try to replace with do_div(), this one calculates
812 * "(dividend << 32) / divisor" */
813 __asm__ ( "divl %4"
814 : "=a" (quotient), "=d" (remainder)
815 : "0" (0), "1" (dividend), "r" (divisor) );
816 return quotient;
817}
818
819static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
820{
821 uint64_t nsecs = 1000000000LL;
822 int32_t shift = 0;
823 uint64_t tps64;
824 uint32_t tps32;
825
826 tps64 = tsc_khz * 1000LL;
827 while (tps64 > nsecs*2) {
828 tps64 >>= 1;
829 shift--;
830 }
831
832 tps32 = (uint32_t)tps64;
833 while (tps32 <= (uint32_t)nsecs) {
834 tps32 <<= 1;
835 shift++;
836 }
837
838 hv_clock->tsc_shift = shift;
839 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
840
841 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 842 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 843 hv_clock->tsc_to_system_mul);
844}
845
c8076604
GH		 846static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
847
18068523
GOC		 848static void kvm_write_guest_time(struct kvm_vcpu *v)
849{
850 struct timespec ts;
851 unsigned long flags;
852 struct kvm_vcpu_arch *vcpu = &v->arch;
853 void *shared_kaddr;
463656c0 854 unsigned long this_tsc_khz;
18068523
GOC		 855
856 if ((!vcpu->time_page))
857 return;
858
463656c0
AK		 859 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
860 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
861 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
862 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 863 }
463656c0 864 put_cpu_var(cpu_tsc_khz);
50d0a0f9 865
18068523
GOC		 866 /* Keep irq disabled to prevent changes to the clock */
867 local_irq_save(flags);
af24a4e4 868 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 869 ktime_get_ts(&ts);
923de3cf 870 monotonic_to_bootbased(&ts);
18068523
GOC		 871 local_irq_restore(flags);
872
873 /* With all the info we got, fill in the values */
874
875 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 876 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
877
371bcf64
GC		 878 vcpu->hv_clock.flags = 0;
879
18068523
GOC		 880 /*
881 * The interface expects us to write an even number signaling that the
882 * update is finished. Since the guest won't see the intermediate
50d0a0f9 883 * state, we just increase by 2 at the end.
18068523 884 */
50d0a0f9 885 vcpu->hv_clock.version += 2;
18068523
GOC		 886
887 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
888
889 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 890 sizeof(vcpu->hv_clock));
18068523
GOC		 891
892 kunmap_atomic(shared_kaddr, KM_USER0);
893
894 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
895}
896
c8076604
GH		 897static int kvm_request_guest_time_update(struct kvm_vcpu *v)
898{
899 struct kvm_vcpu_arch *vcpu = &v->arch;
900
901 if (!vcpu->time_page)
902 return 0;
903 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
904 return 1;
905}
906
9ba075a6
AK		 907static bool msr_mtrr_valid(unsigned msr)
908{
909 switch (msr) {
910 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
911 case MSR_MTRRfix64K_00000:
912 case MSR_MTRRfix16K_80000:
913 case MSR_MTRRfix16K_A0000:
914 case MSR_MTRRfix4K_C0000:
915 case MSR_MTRRfix4K_C8000:
916 case MSR_MTRRfix4K_D0000:
917 case MSR_MTRRfix4K_D8000:
918 case MSR_MTRRfix4K_E0000:
919 case MSR_MTRRfix4K_E8000:
920 case MSR_MTRRfix4K_F0000:
921 case MSR_MTRRfix4K_F8000:
922 case MSR_MTRRdefType:
923 case MSR_IA32_CR_PAT:
924 return true;
925 case 0x2f8:
926 return true;
927 }
928 return false;
929}
930
d6289b93
MT		 931static bool valid_pat_type(unsigned t)
932{
933 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
934}
935
936static bool valid_mtrr_type(unsigned t)
937{
938 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
939}
940
941static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
942{
943 int i;
944
945 if (!msr_mtrr_valid(msr))
946 return false;
947
948 if (msr == MSR_IA32_CR_PAT) {
949 for (i = 0; i < 8; i++)
950 if (!valid_pat_type((data >> (i * 8)) & 0xff))
951 return false;
952 return true;
953 } else if (msr == MSR_MTRRdefType) {
954 if (data & ~0xcff)
955 return false;
956 return valid_mtrr_type(data & 0xff);
957 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
958 for (i = 0; i < 8 ; i++)
959 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
960 return false;
961 return true;
962 }
963
964 /* variable MTRRs */
965 return valid_mtrr_type(data & 0xff);
966}
967
9ba075a6
AK		 968static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
969{
0bed3b56
SY		 970 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
971
d6289b93 972 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 973 return 1;
974
0bed3b56
SY		 975 if (msr == MSR_MTRRdefType) {
976 vcpu->arch.mtrr_state.def_type = data;
977 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
978 } else if (msr == MSR_MTRRfix64K_00000)
979 p[0] = data;
980 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
981 p[1 + msr - MSR_MTRRfix16K_80000] = data;
982 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
983 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
984 else if (msr == MSR_IA32_CR_PAT)
985 vcpu->arch.pat = data;
986 else { /* Variable MTRRs */
987 int idx, is_mtrr_mask;
988 u64 *pt;
989
990 idx = (msr - 0x200) / 2;
991 is_mtrr_mask = msr - 0x200 - 2 * idx;
992 if (!is_mtrr_mask)
993 pt =
994 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
995 else
996 pt =
997 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
998 *pt = data;
999 }
1000
1001 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1002 return 0;
1003}
15c4a640 1004
890ca9ae 1005static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1006{
890ca9ae
HY		 1007 u64 mcg_cap = vcpu->arch.mcg_cap;
1008 unsigned bank_num = mcg_cap & 0xff;
1009
15c4a640 1010 switch (msr) {
15c4a640 1011 case MSR_IA32_MCG_STATUS:
890ca9ae 1012 vcpu->arch.mcg_status = data;
15c4a640 1013 break;
c7ac679c 1014 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1015 if (!(mcg_cap & MCG_CTL_P))
1016 return 1;
1017 if (data != 0 && data != ~(u64)0)
1018 return -1;
1019 vcpu->arch.mcg_ctl = data;
1020 break;
1021 default:
1022 if (msr >= MSR_IA32_MC0_CTL &&
1023 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1024 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1025 /* only 0 or all 1s can be written to IA32_MCi_CTL
1026 * some Linux kernels though clear bit 10 in bank 4 to
1027 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1028 * this to avoid an uncatched #GP in the guest
1029 */
890ca9ae 1030 if ((offset & 0x3) == 0 &&
114be429 1031 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1032 return -1;
1033 vcpu->arch.mce_banks[offset] = data;
1034 break;
1035 }
1036 return 1;
1037 }
1038 return 0;
1039}
1040
ffde22ac
ES		 1041static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1042{
1043 struct kvm *kvm = vcpu->kvm;
1044 int lm = is_long_mode(vcpu);
1045 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1046 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1047 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1048 : kvm->arch.xen_hvm_config.blob_size_32;
1049 u32 page_num = data & ~PAGE_MASK;
1050 u64 page_addr = data & PAGE_MASK;
1051 u8 *page;
1052 int r;
1053
1054 r = -E2BIG;
1055 if (page_num >= blob_size)
1056 goto out;
1057 r = -ENOMEM;
1058 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1059 if (!page)
1060 goto out;
1061 r = -EFAULT;
1062 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1063 goto out_free;
1064 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1065 goto out_free;
1066 r = 0;
1067out_free:
1068 kfree(page);
1069out:
1070 return r;
1071}
1072
55cd8e5a
GN		 1073static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1074{
1075 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1076}
1077
1078static bool kvm_hv_msr_partition_wide(u32 msr)
1079{
1080 bool r = false;
1081 switch (msr) {
1082 case HV_X64_MSR_GUEST_OS_ID:
1083 case HV_X64_MSR_HYPERCALL:
1084 r = true;
1085 break;
1086 }
1087
1088 return r;
1089}
1090
1091static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1092{
1093 struct kvm *kvm = vcpu->kvm;
1094
1095 switch (msr) {
1096 case HV_X64_MSR_GUEST_OS_ID:
1097 kvm->arch.hv_guest_os_id = data;
1098 /* setting guest os id to zero disables hypercall page */
1099 if (!kvm->arch.hv_guest_os_id)
1100 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1101 break;
1102 case HV_X64_MSR_HYPERCALL: {
1103 u64 gfn;
1104 unsigned long addr;
1105 u8 instructions[4];
1106
1107 /* if guest os id is not set hypercall should remain disabled */
1108 if (!kvm->arch.hv_guest_os_id)
1109 break;
1110 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1111 kvm->arch.hv_hypercall = data;
1112 break;
1113 }
1114 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1115 addr = gfn_to_hva(kvm, gfn);
1116 if (kvm_is_error_hva(addr))
1117 return 1;
1118 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1119 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1120 if (copy_to_user((void __user *)addr, instructions, 4))
1121 return 1;
1122 kvm->arch.hv_hypercall = data;
1123 break;
1124 }
1125 default:
1126 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1127 "data 0x%llx\n", msr, data);
1128 return 1;
1129 }
1130 return 0;
1131}
1132
1133static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1134{
10388a07
GN		 1135 switch (msr) {
1136 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1137 unsigned long addr;
55cd8e5a 1138
10388a07
GN		 1139 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1140 vcpu->arch.hv_vapic = data;
1141 break;
1142 }
1143 addr = gfn_to_hva(vcpu->kvm, data >>
1144 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1145 if (kvm_is_error_hva(addr))
1146 return 1;
1147 if (clear_user((void __user *)addr, PAGE_SIZE))
1148 return 1;
1149 vcpu->arch.hv_vapic = data;
1150 break;
1151 }
1152 case HV_X64_MSR_EOI:
1153 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1154 case HV_X64_MSR_ICR:
1155 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1156 case HV_X64_MSR_TPR:
1157 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1158 default:
1159 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1160 "data 0x%llx\n", msr, data);
1161 return 1;
1162 }
1163
1164 return 0;
55cd8e5a
GN		 1165}
1166
15c4a640
CO		 1167int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1168{
1169 switch (msr) {
15c4a640 1170 case MSR_EFER:
b69e8cae 1171 return set_efer(vcpu, data);
8f1589d9
AP		 1172 case MSR_K7_HWCR:
1173 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1174 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1175 if (data != 0) {
1176 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1177 data);
1178 return 1;
1179 }
15c4a640 1180 break;
f7c6d140
AP		 1181 case MSR_FAM10H_MMIO_CONF_BASE:
1182 if (data != 0) {
1183 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1184 "0x%llx\n", data);
1185 return 1;
1186 }
15c4a640 1187 break;
c323c0e5 1188 case MSR_AMD64_NB_CFG:
c7ac679c 1189 break;
b5e2fec0
AG		 1190 case MSR_IA32_DEBUGCTLMSR:
1191 if (!data) {
1192 /* We support the non-activated case already */
1193 break;
1194 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1195 /* Values other than LBR and BTF are vendor-specific,
1196 thus reserved and should throw a #GP */
1197 return 1;
1198 }
1199 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1200 __func__, data);
1201 break;
15c4a640
CO		 1202 case MSR_IA32_UCODE_REV:
1203 case MSR_IA32_UCODE_WRITE:
61a6bd67 1204 case MSR_VM_HSAVE_PA:
6098ca93 1205 case MSR_AMD64_PATCH_LOADER:
15c4a640 1206 break;
9ba075a6
AK		 1207 case 0x200 ... 0x2ff:
1208 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1209 case MSR_IA32_APICBASE:
1210 kvm_set_apic_base(vcpu, data);
1211 break;
0105d1a5
GN		 1212 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1213 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1214 case MSR_IA32_MISC_ENABLE:
ad312c7c 1215 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1216 break;
11c6bffa 1217 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1218 case MSR_KVM_WALL_CLOCK:
1219 vcpu->kvm->arch.wall_clock = data;
1220 kvm_write_wall_clock(vcpu->kvm, data);
1221 break;
11c6bffa 1222 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1223 case MSR_KVM_SYSTEM_TIME: {
1224 if (vcpu->arch.time_page) {
1225 kvm_release_page_dirty(vcpu->arch.time_page);
1226 vcpu->arch.time_page = NULL;
1227 }
1228
1229 vcpu->arch.time = data;
1230
1231 /* we verify if the enable bit is set... */
1232 if (!(data & 1))
1233 break;
1234
1235 /* ...but clean it before doing the actual write */
1236 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1237
18068523
GOC		 1238 vcpu->arch.time_page =
1239 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1240
1241 if (is_error_page(vcpu->arch.time_page)) {
1242 kvm_release_page_clean(vcpu->arch.time_page);
1243 vcpu->arch.time_page = NULL;
1244 }
1245
c8076604 1246 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1247 break;
1248 }
890ca9ae
HY		 1249 case MSR_IA32_MCG_CTL:
1250 case MSR_IA32_MCG_STATUS:
1251 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1252 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1253
1254 /* Performance counters are not protected by a CPUID bit,
1255 * so we should check all of them in the generic path for the sake of
1256 * cross vendor migration.
1257 * Writing a zero into the event select MSRs disables them,
1258 * which we perfectly emulate ;-). Any other value should be at least
1259 * reported, some guests depend on them.
1260 */
1261 case MSR_P6_EVNTSEL0:
1262 case MSR_P6_EVNTSEL1:
1263 case MSR_K7_EVNTSEL0:
1264 case MSR_K7_EVNTSEL1:
1265 case MSR_K7_EVNTSEL2:
1266 case MSR_K7_EVNTSEL3:
1267 if (data != 0)
1268 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1269 "0x%x data 0x%llx\n", msr, data);
1270 break;
1271 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1272 * so we ignore writes to make it happy.
1273 */
1274 case MSR_P6_PERFCTR0:
1275 case MSR_P6_PERFCTR1:
1276 case MSR_K7_PERFCTR0:
1277 case MSR_K7_PERFCTR1:
1278 case MSR_K7_PERFCTR2:
1279 case MSR_K7_PERFCTR3:
1280 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1281 "0x%x data 0x%llx\n", msr, data);
1282 break;
55cd8e5a
GN		 1283 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1284 if (kvm_hv_msr_partition_wide(msr)) {
1285 int r;
1286 mutex_lock(&vcpu->kvm->lock);
1287 r = set_msr_hyperv_pw(vcpu, msr, data);
1288 mutex_unlock(&vcpu->kvm->lock);
1289 return r;
1290 } else
1291 return set_msr_hyperv(vcpu, msr, data);
1292 break;
15c4a640 1293 default:
ffde22ac
ES		 1294 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1295 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1296 if (!ignore_msrs) {
1297 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1298 msr, data);
1299 return 1;
1300 } else {
1301 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1302 msr, data);
1303 break;
1304 }
15c4a640
CO		 1305 }
1306 return 0;
1307}
1308EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1309
1310
1311/*
1312 * Reads an msr value (of 'msr_index') into 'pdata'.
1313 * Returns 0 on success, non-0 otherwise.
1314 * Assumes vcpu_load() was already called.
1315 */
1316int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1317{
1318 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1319}
1320
9ba075a6
AK		 1321static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1322{
0bed3b56
SY		 1323 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1324
9ba075a6
AK		 1325 if (!msr_mtrr_valid(msr))
1326 return 1;
1327
0bed3b56
SY		 1328 if (msr == MSR_MTRRdefType)
1329 *pdata = vcpu->arch.mtrr_state.def_type +
1330 (vcpu->arch.mtrr_state.enabled << 10);
1331 else if (msr == MSR_MTRRfix64K_00000)
1332 *pdata = p[0];
1333 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1334 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1335 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1336 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1337 else if (msr == MSR_IA32_CR_PAT)
1338 *pdata = vcpu->arch.pat;
1339 else { /* Variable MTRRs */
1340 int idx, is_mtrr_mask;
1341 u64 *pt;
1342
1343 idx = (msr - 0x200) / 2;
1344 is_mtrr_mask = msr - 0x200 - 2 * idx;
1345 if (!is_mtrr_mask)
1346 pt =
1347 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1348 else
1349 pt =
1350 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1351 *pdata = *pt;
1352 }
1353
9ba075a6
AK		 1354 return 0;
1355}
1356
890ca9ae 1357static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1358{
1359 u64 data;
890ca9ae
HY		 1360 u64 mcg_cap = vcpu->arch.mcg_cap;
1361 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1362
1363 switch (msr) {
15c4a640
CO		 1364 case MSR_IA32_P5_MC_ADDR:
1365 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1366 data = 0;
1367 break;
15c4a640 1368 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1369 data = vcpu->arch.mcg_cap;
1370 break;
c7ac679c 1371 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1372 if (!(mcg_cap & MCG_CTL_P))
1373 return 1;
1374 data = vcpu->arch.mcg_ctl;
1375 break;
1376 case MSR_IA32_MCG_STATUS:
1377 data = vcpu->arch.mcg_status;
1378 break;
1379 default:
1380 if (msr >= MSR_IA32_MC0_CTL &&
1381 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1382 u32 offset = msr - MSR_IA32_MC0_CTL;
1383 data = vcpu->arch.mce_banks[offset];
1384 break;
1385 }
1386 return 1;
1387 }
1388 *pdata = data;
1389 return 0;
1390}
1391
55cd8e5a
GN		 1392static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1393{
1394 u64 data = 0;
1395 struct kvm *kvm = vcpu->kvm;
1396
1397 switch (msr) {
1398 case HV_X64_MSR_GUEST_OS_ID:
1399 data = kvm->arch.hv_guest_os_id;
1400 break;
1401 case HV_X64_MSR_HYPERCALL:
1402 data = kvm->arch.hv_hypercall;
1403 break;
1404 default:
1405 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1406 return 1;
1407 }
1408
1409 *pdata = data;
1410 return 0;
1411}
1412
1413static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1414{
1415 u64 data = 0;
1416
1417 switch (msr) {
1418 case HV_X64_MSR_VP_INDEX: {
1419 int r;
1420 struct kvm_vcpu *v;
1421 kvm_for_each_vcpu(r, v, vcpu->kvm)
1422 if (v == vcpu)
1423 data = r;
1424 break;
1425 }
10388a07
GN		 1426 case HV_X64_MSR_EOI:
1427 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1428 case HV_X64_MSR_ICR:
1429 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1430 case HV_X64_MSR_TPR:
1431 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1432 default:
1433 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1434 return 1;
1435 }
1436 *pdata = data;
1437 return 0;
1438}
1439
890ca9ae
HY		 1440int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1441{
1442 u64 data;
1443
1444 switch (msr) {
890ca9ae 1445 case MSR_IA32_PLATFORM_ID:
15c4a640 1446 case MSR_IA32_UCODE_REV:
15c4a640 1447 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1448 case MSR_IA32_DEBUGCTLMSR:
1449 case MSR_IA32_LASTBRANCHFROMIP:
1450 case MSR_IA32_LASTBRANCHTOIP:
1451 case MSR_IA32_LASTINTFROMIP:
1452 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1453 case MSR_K8_SYSCFG:
1454 case MSR_K7_HWCR:
61a6bd67 1455 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1456 case MSR_P6_PERFCTR0:
1457 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1458 case MSR_P6_EVNTSEL0:
1459 case MSR_P6_EVNTSEL1:
9e699624 1460 case MSR_K7_EVNTSEL0:
1f3ee616 1461 case MSR_K7_PERFCTR0:
1fdbd48c 1462 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1463 case MSR_AMD64_NB_CFG:
f7c6d140 1464 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1465 data = 0;
1466 break;
9ba075a6
AK		 1467 case MSR_MTRRcap:
1468 data = 0x500 | KVM_NR_VAR_MTRR;
1469 break;
1470 case 0x200 ... 0x2ff:
1471 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1472 case 0xcd: /* fsb frequency */
1473 data = 3;
1474 break;
1475 case MSR_IA32_APICBASE:
1476 data = kvm_get_apic_base(vcpu);
1477 break;
0105d1a5
GN		 1478 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1479 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1480 break;
15c4a640 1481 case MSR_IA32_MISC_ENABLE:
ad312c7c 1482 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1483 break;
847f0ad8
AG		 1484 case MSR_IA32_PERF_STATUS:
1485 /* TSC increment by tick */
1486 data = 1000ULL;
1487 /* CPU multiplier */
1488 data |= (((uint64_t)4ULL) << 40);
1489 break;
15c4a640 1490 case MSR_EFER:
f6801dff 1491 data = vcpu->arch.efer;
15c4a640 1492 break;
18068523 1493 case MSR_KVM_WALL_CLOCK:
11c6bffa 1494 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1495 data = vcpu->kvm->arch.wall_clock;
1496 break;
1497 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1498 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1499 data = vcpu->arch.time;
1500 break;
890ca9ae
HY		 1501 case MSR_IA32_P5_MC_ADDR:
1502 case MSR_IA32_P5_MC_TYPE:
1503 case MSR_IA32_MCG_CAP:
1504 case MSR_IA32_MCG_CTL:
1505 case MSR_IA32_MCG_STATUS:
1506 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1507 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1508 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1509 if (kvm_hv_msr_partition_wide(msr)) {
1510 int r;
1511 mutex_lock(&vcpu->kvm->lock);
1512 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1513 mutex_unlock(&vcpu->kvm->lock);
1514 return r;
1515 } else
1516 return get_msr_hyperv(vcpu, msr, pdata);
1517 break;
15c4a640 1518 default:
ed85c068
AP		 1519 if (!ignore_msrs) {
1520 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1521 return 1;
1522 } else {
1523 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1524 data = 0;
1525 }
1526 break;
15c4a640
CO		 1527 }
1528 *pdata = data;
1529 return 0;
1530}
1531EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1532
313a3dc7
CO		 1533/*
1534 * Read or write a bunch of msrs. All parameters are kernel addresses.
1535 *
1536 * @return number of msrs set successfully.
1537 */
1538static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1539 struct kvm_msr_entry *entries,
1540 int (*do_msr)(struct kvm_vcpu *vcpu,
1541 unsigned index, u64 *data))
1542{
f656ce01 1543 int i, idx;
313a3dc7 1544
f656ce01 1545 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1546 for (i = 0; i < msrs->nmsrs; ++i)
1547 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1548 break;
f656ce01 1549 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1550
313a3dc7
CO		 1551 return i;
1552}
1553
1554/*
1555 * Read or write a bunch of msrs. Parameters are user addresses.
1556 *
1557 * @return number of msrs set successfully.
1558 */
1559static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1560 int (*do_msr)(struct kvm_vcpu *vcpu,
1561 unsigned index, u64 *data),
1562 int writeback)
1563{
1564 struct kvm_msrs msrs;
1565 struct kvm_msr_entry *entries;
1566 int r, n;
1567 unsigned size;
1568
1569 r = -EFAULT;
1570 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1571 goto out;
1572
1573 r = -E2BIG;
1574 if (msrs.nmsrs >= MAX_IO_MSRS)
1575 goto out;
1576
1577 r = -ENOMEM;
1578 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1579 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1580 if (!entries)
1581 goto out;
1582
1583 r = -EFAULT;
1584 if (copy_from_user(entries, user_msrs->entries, size))
1585 goto out_free;
1586
1587 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1588 if (r < 0)
1589 goto out_free;
1590
1591 r = -EFAULT;
1592 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1593 goto out_free;
1594
1595 r = n;
1596
1597out_free:
7a73c028 1598 kfree(entries);
313a3dc7
CO		 1599out:
1600 return r;
1601}
1602
018d00d2
ZX		 1603int kvm_dev_ioctl_check_extension(long ext)
1604{
1605 int r;
1606
1607 switch (ext) {
1608 case KVM_CAP_IRQCHIP:
1609 case KVM_CAP_HLT:
1610 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1611 case KVM_CAP_SET_TSS_ADDR:
07716717 1612 case KVM_CAP_EXT_CPUID:
c8076604 1613 case KVM_CAP_CLOCKSOURCE:
7837699f 1614 case KVM_CAP_PIT:
a28e4f5a 1615 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1616 case KVM_CAP_MP_STATE:
ed848624 1617 case KVM_CAP_SYNC_MMU:
52d939a0 1618 case KVM_CAP_REINJECT_CONTROL:
4925663a 1619 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1620 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1621 case KVM_CAP_IRQFD:
d34e6b17 1622 case KVM_CAP_IOEVENTFD:
c5ff41ce 1623 case KVM_CAP_PIT2:
e9f42757 1624 case KVM_CAP_PIT_STATE2:
b927a3ce 1625 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1626 case KVM_CAP_XEN_HVM:
afbcf7ab 1627 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1628 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1629 case KVM_CAP_HYPERV:
10388a07 1630 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1631 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1632 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1633 case KVM_CAP_DEBUGREGS:
d2be1651 1634 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1635 r = 1;
1636 break;
542472b5
LV		 1637 case KVM_CAP_COALESCED_MMIO:
1638 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1639 break;
774ead3a
AK		 1640 case KVM_CAP_VAPIC:
1641 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1642 break;
f725230a
AK		 1643 case KVM_CAP_NR_VCPUS:
1644 r = KVM_MAX_VCPUS;
1645 break;
a988b910
AK		 1646 case KVM_CAP_NR_MEMSLOTS:
1647 r = KVM_MEMORY_SLOTS;
1648 break;
a68a6a72
MT		 1649 case KVM_CAP_PV_MMU: /* obsolete */
1650 r = 0;
2f333bcb 1651 break;
62c476c7 1652 case KVM_CAP_IOMMU:
19de40a8 1653 r = iommu_found();
62c476c7 1654 break;
890ca9ae
HY		 1655 case KVM_CAP_MCE:
1656 r = KVM_MAX_MCE_BANKS;
1657 break;
018d00d2
ZX		 1658 default:
1659 r = 0;
1660 break;
1661 }
1662 return r;
1663
1664}
1665
043405e1
CO		 1666long kvm_arch_dev_ioctl(struct file *filp,
1667 unsigned int ioctl, unsigned long arg)
1668{
1669 void __user *argp = (void __user *)arg;
1670 long r;
1671
1672 switch (ioctl) {
1673 case KVM_GET_MSR_INDEX_LIST: {
1674 struct kvm_msr_list __user *user_msr_list = argp;
1675 struct kvm_msr_list msr_list;
1676 unsigned n;
1677
1678 r = -EFAULT;
1679 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1680 goto out;
1681 n = msr_list.nmsrs;
1682 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1683 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1684 goto out;
1685 r = -E2BIG;
e125e7b6 1686 if (n < msr_list.nmsrs)
043405e1
CO		 1687 goto out;
1688 r = -EFAULT;
1689 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1690 num_msrs_to_save * sizeof(u32)))
1691 goto out;
e125e7b6 1692 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1693 &emulated_msrs,
1694 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1695 goto out;
1696 r = 0;
1697 break;
1698 }
674eea0f
AK		 1699 case KVM_GET_SUPPORTED_CPUID: {
1700 struct kvm_cpuid2 __user *cpuid_arg = argp;
1701 struct kvm_cpuid2 cpuid;
1702
1703 r = -EFAULT;
1704 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1705 goto out;
1706 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1707 cpuid_arg->entries);
674eea0f
AK		 1708 if (r)
1709 goto out;
1710
1711 r = -EFAULT;
1712 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1713 goto out;
1714 r = 0;
1715 break;
1716 }
890ca9ae
HY		 1717 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1718 u64 mce_cap;
1719
1720 mce_cap = KVM_MCE_CAP_SUPPORTED;
1721 r = -EFAULT;
1722 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1723 goto out;
1724 r = 0;
1725 break;
1726 }
043405e1
CO		 1727 default:
1728 r = -EINVAL;
1729 }
1730out:
1731 return r;
1732}
1733
313a3dc7
CO		 1734void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1735{
1736 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1737 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1738 unsigned long khz = cpufreq_quick_get(cpu);
1739 if (!khz)
1740 khz = tsc_khz;
1741 per_cpu(cpu_tsc_khz, cpu) = khz;
1742 }
c8076604 1743 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1744}
1745
1746void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1747{
02daab21 1748 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1749 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1750}
1751
07716717 1752static int is_efer_nx(void)
313a3dc7 1753{
e286e86e 1754 unsigned long long efer = 0;
313a3dc7 1755
e286e86e 1756 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1757 return efer & EFER_NX;
1758}
1759
1760static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1761{
1762 int i;
1763 struct kvm_cpuid_entry2 *e, *entry;
1764
313a3dc7 1765 entry = NULL;
ad312c7c
ZX		 1766 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1767 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1768 if (e->function == 0x80000001) {
1769 entry = e;
1770 break;
1771 }
1772 }
07716717 1773 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1774 entry->edx &= ~(1 << 20);
1775 printk(KERN_INFO "kvm: guest NX capability removed\n");
1776 }
1777}
1778
07716717 1779/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1780static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1781 struct kvm_cpuid *cpuid,
1782 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1783{
1784 int r, i;
1785 struct kvm_cpuid_entry *cpuid_entries;
1786
1787 r = -E2BIG;
1788 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1789 goto out;
1790 r = -ENOMEM;
1791 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1792 if (!cpuid_entries)
1793 goto out;
1794 r = -EFAULT;
1795 if (copy_from_user(cpuid_entries, entries,
1796 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1797 goto out_free;
1798 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1799 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1800 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1801 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1802 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1803 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1804 vcpu->arch.cpuid_entries[i].index = 0;
1805 vcpu->arch.cpuid_entries[i].flags = 0;
1806 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1807 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1808 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1809 }
1810 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1811 cpuid_fix_nx_cap(vcpu);
1812 r = 0;
fc61b800 1813 kvm_apic_set_version(vcpu);
0e851880 1814 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1815
1816out_free:
1817 vfree(cpuid_entries);
1818out:
1819 return r;
1820}
1821
1822static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1823 struct kvm_cpuid2 *cpuid,
1824 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1825{
1826 int r;
1827
1828 r = -E2BIG;
1829 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1830 goto out;
1831 r = -EFAULT;
ad312c7c 1832 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1833 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1834 goto out;
ad312c7c 1835 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1836 kvm_apic_set_version(vcpu);
0e851880 1837 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1838 return 0;
1839
1840out:
1841 return r;
1842}
1843
07716717 1844static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1845 struct kvm_cpuid2 *cpuid,
1846 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1847{
1848 int r;
1849
1850 r = -E2BIG;
ad312c7c 1851 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1852 goto out;
1853 r = -EFAULT;
ad312c7c 1854 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1855 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1856 goto out;
1857 return 0;
1858
1859out:
ad312c7c 1860 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1861 return r;
1862}
1863
07716717 1864static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1865 u32 index)
07716717
DK		 1866{
1867 entry->function = function;
1868 entry->index = index;
1869 cpuid_count(entry->function, entry->index,
19355475 1870 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1871 entry->flags = 0;
1872}
1873
7faa4ee1
AK		 1874#define F(x) bit(X86_FEATURE_##x)
1875
07716717
DK		 1876static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1877 u32 index, int *nent, int maxnent)
1878{
7faa4ee1 1879 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1880#ifdef CONFIG_X86_64
17cc3935
SY		 1881 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1882 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1883 unsigned f_lm = F(LM);
1884#else
17cc3935 1885 unsigned f_gbpages = 0;
7faa4ee1 1886 unsigned f_lm = 0;
07716717 1887#endif
4e47c7a6 1888 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1889
1890 /* cpuid 1.edx */
1891 const u32 kvm_supported_word0_x86_features =
1892 F(FPU) | F(VME) | F(DE) | F(PSE) |
1893 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1894 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1895 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1896 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1897 0 /* Reserved, DS, ACPI */ | F(MMX) |
1898 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1899 0 /* HTT, TM, Reserved, PBE */;
1900 /* cpuid 0x80000001.edx */
1901 const u32 kvm_supported_word1_x86_features =
1902 F(FPU) | F(VME) | F(DE) | F(PSE) |
1903 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1904 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1905 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1906 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1907 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1908 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1909 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1910 /* cpuid 1.ecx */
1911 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1912 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1913 0 /* DS-CPL, VMX, SMX, EST */ |
1914 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1915 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1916 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1917 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1918 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1919 /* cpuid 0x80000001.ecx */
07716717 1920 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1921 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1922 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1923 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1924 0 /* SKINIT */ | 0 /* WDT */;
07716717 1925
19355475 1926 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1927 get_cpu();
1928 do_cpuid_1_ent(entry, function, index);
1929 ++*nent;
1930
1931 switch (function) {
1932 case 0:
1933 entry->eax = min(entry->eax, (u32)0xb);
1934 break;
1935 case 1:
1936 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1937 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1938 /* we support x2apic emulation even if host does not support
1939 * it since we emulate x2apic in software */
1940 entry->ecx |= F(X2APIC);
07716717
DK		 1941 break;
1942 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1943 * may return different values. This forces us to get_cpu() before
1944 * issuing the first command, and also to emulate this annoying behavior
1945 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1946 case 2: {
1947 int t, times = entry->eax & 0xff;
1948
1949 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1950 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1951 for (t = 1; t < times && *nent < maxnent; ++t) {
1952 do_cpuid_1_ent(&entry[t], function, 0);
1953 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1954 ++*nent;
1955 }
1956 break;
1957 }
1958 /* function 4 and 0xb have additional index. */
1959 case 4: {
14af3f3c 1960 int i, cache_type;
07716717
DK		 1961
1962 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1963 /* read more entries until cache_type is zero */
14af3f3c
HH		 1964 for (i = 1; *nent < maxnent; ++i) {
1965 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1966 if (!cache_type)
1967 break;
14af3f3c
HH		 1968 do_cpuid_1_ent(&entry[i], function, i);
1969 entry[i].flags |=
07716717
DK		 1970 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1971 ++*nent;
1972 }
1973 break;
1974 }
1975 case 0xb: {
14af3f3c 1976 int i, level_type;
07716717
DK		 1977
1978 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1979 /* read more entries until level_type is zero */
14af3f3c 1980 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1981 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1982 if (!level_type)
1983 break;
14af3f3c
HH		 1984 do_cpuid_1_ent(&entry[i], function, i);
1985 entry[i].flags |=
07716717
DK		 1986 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1987 ++*nent;
1988 }
1989 break;
1990 }
84478c82
GC		 1991 case KVM_CPUID_SIGNATURE: {
1992 char signature[12] = "KVMKVMKVM\0\0";
1993 u32 *sigptr = (u32 *)signature;
1994 entry->eax = 0;
1995 entry->ebx = sigptr[0];
1996 entry->ecx = sigptr[1];
1997 entry->edx = sigptr[2];
1998 break;
1999 }
2000 case KVM_CPUID_FEATURES:
2001 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2002 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2003 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2004 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2005 entry->ebx = 0;
2006 entry->ecx = 0;
2007 entry->edx = 0;
2008 break;
07716717
DK		 2009 case 0x80000000:
2010 entry->eax = min(entry->eax, 0x8000001a);
2011 break;
2012 case 0x80000001:
2013 entry->edx &= kvm_supported_word1_x86_features;
2014 entry->ecx &= kvm_supported_word6_x86_features;
2015 break;
2016 }
d4330ef2
JR		 2017
2018 kvm_x86_ops->set_supported_cpuid(function, entry);
2019
07716717
DK		 2020 put_cpu();
2021}
2022
7faa4ee1
AK		 2023#undef F
2024
674eea0f 2025static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2026 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2027{
2028 struct kvm_cpuid_entry2 *cpuid_entries;
2029 int limit, nent = 0, r = -E2BIG;
2030 u32 func;
2031
2032 if (cpuid->nent < 1)
2033 goto out;
6a544355
AK		 2034 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2035 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2036 r = -ENOMEM;
2037 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2038 if (!cpuid_entries)
2039 goto out;
2040
2041 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2042 limit = cpuid_entries[0].eax;
2043 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2044 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2045 &nent, cpuid->nent);
07716717
DK		 2046 r = -E2BIG;
2047 if (nent >= cpuid->nent)
2048 goto out_free;
2049
2050 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2051 limit = cpuid_entries[nent - 1].eax;
2052 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2053 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2054 &nent, cpuid->nent);
84478c82
GC		 2055
2056
2057
2058 r = -E2BIG;
2059 if (nent >= cpuid->nent)
2060 goto out_free;
2061
2062 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2063 cpuid->nent);
2064
2065 r = -E2BIG;
2066 if (nent >= cpuid->nent)
2067 goto out_free;
2068
2069 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2070 cpuid->nent);
2071
cb007648
MM		 2072 r = -E2BIG;
2073 if (nent >= cpuid->nent)
2074 goto out_free;
2075
07716717
DK		 2076 r = -EFAULT;
2077 if (copy_to_user(entries, cpuid_entries,
19355475 2078 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2079 goto out_free;
2080 cpuid->nent = nent;
2081 r = 0;
2082
2083out_free:
2084 vfree(cpuid_entries);
2085out:
2086 return r;
2087}
2088
313a3dc7
CO		 2089static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2090 struct kvm_lapic_state *s)
2091{
ad312c7c 2092 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2093
2094 return 0;
2095}
2096
2097static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2098 struct kvm_lapic_state *s)
2099{
ad312c7c 2100 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2101 kvm_apic_post_state_restore(vcpu);
cb142eb7 2102 update_cr8_intercept(vcpu);
313a3dc7
CO		 2103
2104 return 0;
2105}
2106
f77bc6a4
ZX		 2107static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2108 struct kvm_interrupt *irq)
2109{
2110 if (irq->irq < 0 || irq->irq >= 256)
2111 return -EINVAL;
2112 if (irqchip_in_kernel(vcpu->kvm))
2113 return -ENXIO;
f77bc6a4 2114
66fd3f7f 2115 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2116
f77bc6a4
ZX		 2117 return 0;
2118}
2119
c4abb7c9
JK		 2120static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2121{
c4abb7c9 2122 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2123
2124 return 0;
2125}
2126
b209749f
AK		 2127static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2128 struct kvm_tpr_access_ctl *tac)
2129{
2130 if (tac->flags)
2131 return -EINVAL;
2132 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2133 return 0;
2134}
2135
890ca9ae
HY		 2136static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2137 u64 mcg_cap)
2138{
2139 int r;
2140 unsigned bank_num = mcg_cap & 0xff, bank;
2141
2142 r = -EINVAL;
a9e38c3e 2143 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2144 goto out;
2145 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2146 goto out;
2147 r = 0;
2148 vcpu->arch.mcg_cap = mcg_cap;
2149 /* Init IA32_MCG_CTL to all 1s */
2150 if (mcg_cap & MCG_CTL_P)
2151 vcpu->arch.mcg_ctl = ~(u64)0;
2152 /* Init IA32_MCi_CTL to all 1s */
2153 for (bank = 0; bank < bank_num; bank++)
2154 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2155out:
2156 return r;
2157}
2158
2159static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2160 struct kvm_x86_mce *mce)
2161{
2162 u64 mcg_cap = vcpu->arch.mcg_cap;
2163 unsigned bank_num = mcg_cap & 0xff;
2164 u64 *banks = vcpu->arch.mce_banks;
2165
2166 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2167 return -EINVAL;
2168 /*
2169 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2170 * reporting is disabled
2171 */
2172 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2173 vcpu->arch.mcg_ctl != ~(u64)0)
2174 return 0;
2175 banks += 4 * mce->bank;
2176 /*
2177 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2178 * reporting is disabled for the bank
2179 */
2180 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2181 return 0;
2182 if (mce->status & MCI_STATUS_UC) {
2183 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2184 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2185 printk(KERN_DEBUG "kvm: set_mce: "
2186 "injects mce exception while "
2187 "previous one is in progress!\n");
2188 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2189 return 0;
2190 }
2191 if (banks[1] & MCI_STATUS_VAL)
2192 mce->status |= MCI_STATUS_OVER;
2193 banks[2] = mce->addr;
2194 banks[3] = mce->misc;
2195 vcpu->arch.mcg_status = mce->mcg_status;
2196 banks[1] = mce->status;
2197 kvm_queue_exception(vcpu, MC_VECTOR);
2198 } else if (!(banks[1] & MCI_STATUS_VAL)
2199 || !(banks[1] & MCI_STATUS_UC)) {
2200 if (banks[1] & MCI_STATUS_VAL)
2201 mce->status |= MCI_STATUS_OVER;
2202 banks[2] = mce->addr;
2203 banks[3] = mce->misc;
2204 banks[1] = mce->status;
2205 } else
2206 banks[1] |= MCI_STATUS_OVER;
2207 return 0;
2208}
2209
3cfc3092
JK		 2210static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2211 struct kvm_vcpu_events *events)
2212{
03b82a30
JK		 2213 events->exception.injected =
2214 vcpu->arch.exception.pending &&
2215 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2216 events->exception.nr = vcpu->arch.exception.nr;
2217 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2218 events->exception.error_code = vcpu->arch.exception.error_code;
2219
03b82a30
JK		 2220 events->interrupt.injected =
2221 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2222 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2223 events->interrupt.soft = 0;
48005f64
JK		 2224 events->interrupt.shadow =
2225 kvm_x86_ops->get_interrupt_shadow(vcpu,
2226 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2227
2228 events->nmi.injected = vcpu->arch.nmi_injected;
2229 events->nmi.pending = vcpu->arch.nmi_pending;
2230 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2231
2232 events->sipi_vector = vcpu->arch.sipi_vector;
2233
dab4b911 2234 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2235 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2236 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2237}
2238
2239static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2240 struct kvm_vcpu_events *events)
2241{
dab4b911 2242 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2243 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2244 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2245 return -EINVAL;
2246
3cfc3092
JK		 2247 vcpu->arch.exception.pending = events->exception.injected;
2248 vcpu->arch.exception.nr = events->exception.nr;
2249 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2250 vcpu->arch.exception.error_code = events->exception.error_code;
2251
2252 vcpu->arch.interrupt.pending = events->interrupt.injected;
2253 vcpu->arch.interrupt.nr = events->interrupt.nr;
2254 vcpu->arch.interrupt.soft = events->interrupt.soft;
2255 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2256 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2257 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2258 kvm_x86_ops->set_interrupt_shadow(vcpu,
2259 events->interrupt.shadow);
3cfc3092
JK		 2260
2261 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2262 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2263 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2264 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2265
dab4b911
JK		 2266 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2267 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2268
3cfc3092
JK		 2269 return 0;
2270}
2271
a1efbe77
JK		 2272static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2273 struct kvm_debugregs *dbgregs)
2274{
a1efbe77
JK		 2275 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2276 dbgregs->dr6 = vcpu->arch.dr6;
2277 dbgregs->dr7 = vcpu->arch.dr7;
2278 dbgregs->flags = 0;
a1efbe77
JK		 2279}
2280
2281static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2282 struct kvm_debugregs *dbgregs)
2283{
2284 if (dbgregs->flags)
2285 return -EINVAL;
2286
a1efbe77
JK		 2287 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2288 vcpu->arch.dr6 = dbgregs->dr6;
2289 vcpu->arch.dr7 = dbgregs->dr7;
2290
a1efbe77
JK		 2291 return 0;
2292}
2293
313a3dc7
CO		 2294long kvm_arch_vcpu_ioctl(struct file *filp,
2295 unsigned int ioctl, unsigned long arg)
2296{
2297 struct kvm_vcpu *vcpu = filp->private_data;
2298 void __user *argp = (void __user *)arg;
2299 int r;
b772ff36 2300 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2301
2302 switch (ioctl) {
2303 case KVM_GET_LAPIC: {
2204ae3c
MT		 2304 r = -EINVAL;
2305 if (!vcpu->arch.apic)
2306 goto out;
b772ff36 2307 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2308
b772ff36
DH		 2309 r = -ENOMEM;
2310 if (!lapic)
2311 goto out;
2312 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2313 if (r)
2314 goto out;
2315 r = -EFAULT;
b772ff36 2316 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2317 goto out;
2318 r = 0;
2319 break;
2320 }
2321 case KVM_SET_LAPIC: {
2204ae3c
MT		 2322 r = -EINVAL;
2323 if (!vcpu->arch.apic)
2324 goto out;
b772ff36
DH		 2325 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2326 r = -ENOMEM;
2327 if (!lapic)
2328 goto out;
313a3dc7 2329 r = -EFAULT;
b772ff36 2330 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2331 goto out;
b772ff36 2332 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2333 if (r)
2334 goto out;
2335 r = 0;
2336 break;
2337 }
f77bc6a4
ZX		 2338 case KVM_INTERRUPT: {
2339 struct kvm_interrupt irq;
2340
2341 r = -EFAULT;
2342 if (copy_from_user(&irq, argp, sizeof irq))
2343 goto out;
2344 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2345 if (r)
2346 goto out;
2347 r = 0;
2348 break;
2349 }
c4abb7c9
JK		 2350 case KVM_NMI: {
2351 r = kvm_vcpu_ioctl_nmi(vcpu);
2352 if (r)
2353 goto out;
2354 r = 0;
2355 break;
2356 }
313a3dc7
CO		 2357 case KVM_SET_CPUID: {
2358 struct kvm_cpuid __user *cpuid_arg = argp;
2359 struct kvm_cpuid cpuid;
2360
2361 r = -EFAULT;
2362 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2363 goto out;
2364 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2365 if (r)
2366 goto out;
2367 break;
2368 }
07716717
DK		 2369 case KVM_SET_CPUID2: {
2370 struct kvm_cpuid2 __user *cpuid_arg = argp;
2371 struct kvm_cpuid2 cpuid;
2372
2373 r = -EFAULT;
2374 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2375 goto out;
2376 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2377 cpuid_arg->entries);
07716717
DK		 2378 if (r)
2379 goto out;
2380 break;
2381 }
2382 case KVM_GET_CPUID2: {
2383 struct kvm_cpuid2 __user *cpuid_arg = argp;
2384 struct kvm_cpuid2 cpuid;
2385
2386 r = -EFAULT;
2387 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2388 goto out;
2389 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2390 cpuid_arg->entries);
07716717
DK		 2391 if (r)
2392 goto out;
2393 r = -EFAULT;
2394 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2395 goto out;
2396 r = 0;
2397 break;
2398 }
313a3dc7
CO		 2399 case KVM_GET_MSRS:
2400 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2401 break;
2402 case KVM_SET_MSRS:
2403 r = msr_io(vcpu, argp, do_set_msr, 0);
2404 break;
b209749f
AK		 2405 case KVM_TPR_ACCESS_REPORTING: {
2406 struct kvm_tpr_access_ctl tac;
2407
2408 r = -EFAULT;
2409 if (copy_from_user(&tac, argp, sizeof tac))
2410 goto out;
2411 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2412 if (r)
2413 goto out;
2414 r = -EFAULT;
2415 if (copy_to_user(argp, &tac, sizeof tac))
2416 goto out;
2417 r = 0;
2418 break;
2419 };
b93463aa
AK		 2420 case KVM_SET_VAPIC_ADDR: {
2421 struct kvm_vapic_addr va;
2422
2423 r = -EINVAL;
2424 if (!irqchip_in_kernel(vcpu->kvm))
2425 goto out;
2426 r = -EFAULT;
2427 if (copy_from_user(&va, argp, sizeof va))
2428 goto out;
2429 r = 0;
2430 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2431 break;
2432 }
890ca9ae
HY		 2433 case KVM_X86_SETUP_MCE: {
2434 u64 mcg_cap;
2435
2436 r = -EFAULT;
2437 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2438 goto out;
2439 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2440 break;
2441 }
2442 case KVM_X86_SET_MCE: {
2443 struct kvm_x86_mce mce;
2444
2445 r = -EFAULT;
2446 if (copy_from_user(&mce, argp, sizeof mce))
2447 goto out;
2448 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2449 break;
2450 }
3cfc3092
JK		 2451 case KVM_GET_VCPU_EVENTS: {
2452 struct kvm_vcpu_events events;
2453
2454 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2455
2456 r = -EFAULT;
2457 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2458 break;
2459 r = 0;
2460 break;
2461 }
2462 case KVM_SET_VCPU_EVENTS: {
2463 struct kvm_vcpu_events events;
2464
2465 r = -EFAULT;
2466 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2467 break;
2468
2469 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2470 break;
2471 }
a1efbe77
JK		 2472 case KVM_GET_DEBUGREGS: {
2473 struct kvm_debugregs dbgregs;
2474
2475 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2476
2477 r = -EFAULT;
2478 if (copy_to_user(argp, &dbgregs,
2479 sizeof(struct kvm_debugregs)))
2480 break;
2481 r = 0;
2482 break;
2483 }
2484 case KVM_SET_DEBUGREGS: {
2485 struct kvm_debugregs dbgregs;
2486
2487 r = -EFAULT;
2488 if (copy_from_user(&dbgregs, argp,
2489 sizeof(struct kvm_debugregs)))
2490 break;
2491
2492 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2493 break;
2494 }
313a3dc7
CO		 2495 default:
2496 r = -EINVAL;
2497 }
2498out:
7a6ce84c 2499 kfree(lapic);
313a3dc7
CO		 2500 return r;
2501}
2502
1fe779f8
CO		 2503static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2504{
2505 int ret;
2506
2507 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2508 return -1;
2509 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2510 return ret;
2511}
2512
b927a3ce
SY		 2513static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2514 u64 ident_addr)
2515{
2516 kvm->arch.ept_identity_map_addr = ident_addr;
2517 return 0;
2518}
2519
1fe779f8
CO		 2520static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2521 u32 kvm_nr_mmu_pages)
2522{
2523 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2524 return -EINVAL;
2525
79fac95e 2526 mutex_lock(&kvm->slots_lock);
7c8a83b7 2527 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2528
2529 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2530 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2531
7c8a83b7 2532 spin_unlock(&kvm->mmu_lock);
79fac95e 2533 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2534 return 0;
2535}
2536
2537static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2538{
f05e70ac 2539 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2540}
2541
a983fb23
MT		 2542gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2543{
2544 int i;
2545 struct kvm_mem_alias *alias;
2546 struct kvm_mem_aliases *aliases;
2547
90d83dc3 2548 aliases = kvm_aliases(kvm);
a983fb23
MT		 2549
2550 for (i = 0; i < aliases->naliases; ++i) {
2551 alias = &aliases->aliases[i];
2552 if (alias->flags & KVM_ALIAS_INVALID)
2553 continue;
2554 if (gfn >= alias->base_gfn
2555 && gfn < alias->base_gfn + alias->npages)
2556 return alias->target_gfn + gfn - alias->base_gfn;
2557 }
2558 return gfn;
2559}
2560
e9f85cde
ZX		 2561gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2562{
2563 int i;
2564 struct kvm_mem_alias *alias;
a983fb23
MT		 2565 struct kvm_mem_aliases *aliases;
2566
90d83dc3 2567 aliases = kvm_aliases(kvm);
e9f85cde 2568
fef9cce0
MT		 2569 for (i = 0; i < aliases->naliases; ++i) {
2570 alias = &aliases->aliases[i];
e9f85cde
ZX		 2571 if (gfn >= alias->base_gfn
2572 && gfn < alias->base_gfn + alias->npages)
2573 return alias->target_gfn + gfn - alias->base_gfn;
2574 }
2575 return gfn;
2576}
2577
1fe779f8
CO		 2578/*
2579 * Set a new alias region. Aliases map a portion of physical memory into
2580 * another portion. This is useful for memory windows, for example the PC
2581 * VGA region.
2582 */
2583static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2584 struct kvm_memory_alias *alias)
2585{
2586 int r, n;
2587 struct kvm_mem_alias *p;
a983fb23 2588 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2589
2590 r = -EINVAL;
2591 /* General sanity checks */
2592 if (alias->memory_size & (PAGE_SIZE - 1))
2593 goto out;
2594 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2595 goto out;
2596 if (alias->slot >= KVM_ALIAS_SLOTS)
2597 goto out;
2598 if (alias->guest_phys_addr + alias->memory_size
2599 < alias->guest_phys_addr)
2600 goto out;
2601 if (alias->target_phys_addr + alias->memory_size
2602 < alias->target_phys_addr)
2603 goto out;
2604
a983fb23
MT		 2605 r = -ENOMEM;
2606 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2607 if (!aliases)
2608 goto out;
2609
79fac95e 2610 mutex_lock(&kvm->slots_lock);
1fe779f8 2611
a983fb23
MT		 2612 /* invalidate any gfn reference in case of deletion/shrinking */
2613 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2614 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2615 old_aliases = kvm->arch.aliases;
2616 rcu_assign_pointer(kvm->arch.aliases, aliases);
2617 synchronize_srcu_expedited(&kvm->srcu);
2618 kvm_mmu_zap_all(kvm);
2619 kfree(old_aliases);
2620
2621 r = -ENOMEM;
2622 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2623 if (!aliases)
2624 goto out_unlock;
2625
2626 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2627
2628 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2629 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2630 p->npages = alias->memory_size >> PAGE_SHIFT;
2631 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2632 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2633
2634 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2635 if (aliases->aliases[n - 1].npages)
1fe779f8 2636 break;
fef9cce0 2637 aliases->naliases = n;
1fe779f8 2638
a983fb23
MT		 2639 old_aliases = kvm->arch.aliases;
2640 rcu_assign_pointer(kvm->arch.aliases, aliases);
2641 synchronize_srcu_expedited(&kvm->srcu);
2642 kfree(old_aliases);
2643 r = 0;
1fe779f8 2644
a983fb23 2645out_unlock:
79fac95e 2646 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2647out:
2648 return r;
2649}
2650
2651static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2652{
2653 int r;
2654
2655 r = 0;
2656 switch (chip->chip_id) {
2657 case KVM_IRQCHIP_PIC_MASTER:
2658 memcpy(&chip->chip.pic,
2659 &pic_irqchip(kvm)->pics[0],
2660 sizeof(struct kvm_pic_state));
2661 break;
2662 case KVM_IRQCHIP_PIC_SLAVE:
2663 memcpy(&chip->chip.pic,
2664 &pic_irqchip(kvm)->pics[1],
2665 sizeof(struct kvm_pic_state));
2666 break;
2667 case KVM_IRQCHIP_IOAPIC:
eba0226b 2668 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2669 break;
2670 default:
2671 r = -EINVAL;
2672 break;
2673 }
2674 return r;
2675}
2676
2677static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2678{
2679 int r;
2680
2681 r = 0;
2682 switch (chip->chip_id) {
2683 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2684 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2685 memcpy(&pic_irqchip(kvm)->pics[0],
2686 &chip->chip.pic,
2687 sizeof(struct kvm_pic_state));
fa8273e9 2688 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2689 break;
2690 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2691 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2692 memcpy(&pic_irqchip(kvm)->pics[1],
2693 &chip->chip.pic,
2694 sizeof(struct kvm_pic_state));
fa8273e9 2695 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2696 break;
2697 case KVM_IRQCHIP_IOAPIC:
eba0226b 2698 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2699 break;
2700 default:
2701 r = -EINVAL;
2702 break;
2703 }
2704 kvm_pic_update_irq(pic_irqchip(kvm));
2705 return r;
2706}
2707
e0f63cb9
SY		 2708static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2709{
2710 int r = 0;
2711
894a9c55 2712 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2713 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2714 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2715 return r;
2716}
2717
2718static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2719{
2720 int r = 0;
2721
894a9c55 2722 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2723 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2724 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2725 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2726 return r;
2727}
2728
2729static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2730{
2731 int r = 0;
2732
2733 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2734 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2735 sizeof(ps->channels));
2736 ps->flags = kvm->arch.vpit->pit_state.flags;
2737 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2738 return r;
2739}
2740
2741static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2742{
2743 int r = 0, start = 0;
2744 u32 prev_legacy, cur_legacy;
2745 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2746 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2747 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2748 if (!prev_legacy && cur_legacy)
2749 start = 1;
2750 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2751 sizeof(kvm->arch.vpit->pit_state.channels));
2752 kvm->arch.vpit->pit_state.flags = ps->flags;
2753 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2754 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2755 return r;
2756}
2757
52d939a0
MT		 2758static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2759 struct kvm_reinject_control *control)
2760{
2761 if (!kvm->arch.vpit)
2762 return -ENXIO;
894a9c55 2763 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2764 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2765 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2766 return 0;
2767}
2768
5bb064dc
ZX		 2769/*
2770 * Get (and clear) the dirty memory log for a memory slot.
2771 */
2772int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2773 struct kvm_dirty_log *log)
2774{
87bf6e7d 2775 int r, i;
5bb064dc 2776 struct kvm_memory_slot *memslot;
87bf6e7d 2777 unsigned long n;
b050b015 2778 unsigned long is_dirty = 0;
5bb064dc 2779
79fac95e 2780 mutex_lock(&kvm->slots_lock);
5bb064dc 2781
b050b015
MT		 2782 r = -EINVAL;
2783 if (log->slot >= KVM_MEMORY_SLOTS)
2784 goto out;
2785
2786 memslot = &kvm->memslots->memslots[log->slot];
2787 r = -ENOENT;
2788 if (!memslot->dirty_bitmap)
2789 goto out;
2790
87bf6e7d 2791 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2792
b050b015
MT		 2793 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2794 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2795
2796 /* If nothing is dirty, don't bother messing with page tables. */
2797 if (is_dirty) {
b050b015 2798 struct kvm_memslots *slots, *old_slots;
914ebccd 2799 unsigned long *dirty_bitmap;
b050b015 2800
7c8a83b7 2801 spin_lock(&kvm->mmu_lock);
5bb064dc 2802 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2803 spin_unlock(&kvm->mmu_lock);
b050b015 2804
914ebccd
TY		 2805 r = -ENOMEM;
2806 dirty_bitmap = vmalloc(n);
2807 if (!dirty_bitmap)
2808 goto out;
2809 memset(dirty_bitmap, 0, n);
b050b015 2810
914ebccd
TY		 2811 r = -ENOMEM;
2812 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2813 if (!slots) {
2814 vfree(dirty_bitmap);
2815 goto out;
2816 }
b050b015
MT		 2817 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2818 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2819
2820 old_slots = kvm->memslots;
2821 rcu_assign_pointer(kvm->memslots, slots);
2822 synchronize_srcu_expedited(&kvm->srcu);
2823 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2824 kfree(old_slots);
914ebccd
TY		 2825
2826 r = -EFAULT;
2827 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2828 vfree(dirty_bitmap);
2829 goto out;
2830 }
2831 vfree(dirty_bitmap);
2832 } else {
2833 r = -EFAULT;
2834 if (clear_user(log->dirty_bitmap, n))
2835 goto out;
5bb064dc 2836 }
b050b015 2837
5bb064dc
ZX		 2838 r = 0;
2839out:
79fac95e 2840 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2841 return r;
2842}
2843
1fe779f8
CO		 2844long kvm_arch_vm_ioctl(struct file *filp,
2845 unsigned int ioctl, unsigned long arg)
2846{
2847 struct kvm *kvm = filp->private_data;
2848 void __user *argp = (void __user *)arg;
367e1319 2849 int r = -ENOTTY;
f0d66275
DH		 2850 /*
2851 * This union makes it completely explicit to gcc-3.x
2852 * that these two variables' stack usage should be
2853 * combined, not added together.
2854 */
2855 union {
2856 struct kvm_pit_state ps;
e9f42757 2857 struct kvm_pit_state2 ps2;
f0d66275 2858 struct kvm_memory_alias alias;
c5ff41ce 2859 struct kvm_pit_config pit_config;
f0d66275 2860 } u;
1fe779f8
CO		 2861
2862 switch (ioctl) {
2863 case KVM_SET_TSS_ADDR:
2864 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2865 if (r < 0)
2866 goto out;
2867 break;
b927a3ce
SY		 2868 case KVM_SET_IDENTITY_MAP_ADDR: {
2869 u64 ident_addr;
2870
2871 r = -EFAULT;
2872 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2873 goto out;
2874 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2875 if (r < 0)
2876 goto out;
2877 break;
2878 }
1fe779f8
CO		 2879 case KVM_SET_MEMORY_REGION: {
2880 struct kvm_memory_region kvm_mem;
2881 struct kvm_userspace_memory_region kvm_userspace_mem;
2882
2883 r = -EFAULT;
2884 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2885 goto out;
2886 kvm_userspace_mem.slot = kvm_mem.slot;
2887 kvm_userspace_mem.flags = kvm_mem.flags;
2888 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2889 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2890 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2891 if (r)
2892 goto out;
2893 break;
2894 }
2895 case KVM_SET_NR_MMU_PAGES:
2896 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2897 if (r)
2898 goto out;
2899 break;
2900 case KVM_GET_NR_MMU_PAGES:
2901 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2902 break;
f0d66275 2903 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2904 r = -EFAULT;
f0d66275 2905 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2906 goto out;
f0d66275 2907 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2908 if (r)
2909 goto out;
2910 break;
3ddea128
MT		 2911 case KVM_CREATE_IRQCHIP: {
2912 struct kvm_pic *vpic;
2913
2914 mutex_lock(&kvm->lock);
2915 r = -EEXIST;
2916 if (kvm->arch.vpic)
2917 goto create_irqchip_unlock;
1fe779f8 2918 r = -ENOMEM;
3ddea128
MT		 2919 vpic = kvm_create_pic(kvm);
2920 if (vpic) {
1fe779f8
CO		 2921 r = kvm_ioapic_init(kvm);
2922 if (r) {
72bb2fcd
WY		 2923 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2924 &vpic->dev);
3ddea128
MT		 2925 kfree(vpic);
2926 goto create_irqchip_unlock;
1fe779f8
CO		 2927 }
2928 } else
3ddea128
MT		 2929 goto create_irqchip_unlock;
2930 smp_wmb();
2931 kvm->arch.vpic = vpic;
2932 smp_wmb();
399ec807
AK		 2933 r = kvm_setup_default_irq_routing(kvm);
2934 if (r) {
3ddea128 2935 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2936 kvm_ioapic_destroy(kvm);
2937 kvm_destroy_pic(kvm);
3ddea128 2938 mutex_unlock(&kvm->irq_lock);
399ec807 2939 }
3ddea128
MT		 2940 create_irqchip_unlock:
2941 mutex_unlock(&kvm->lock);
1fe779f8 2942 break;
3ddea128 2943 }
7837699f 2944 case KVM_CREATE_PIT:
c5ff41ce
JK		 2945 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2946 goto create_pit;
2947 case KVM_CREATE_PIT2:
2948 r = -EFAULT;
2949 if (copy_from_user(&u.pit_config, argp,
2950 sizeof(struct kvm_pit_config)))
2951 goto out;
2952 create_pit:
79fac95e 2953 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2954 r = -EEXIST;
2955 if (kvm->arch.vpit)
2956 goto create_pit_unlock;
7837699f 2957 r = -ENOMEM;
c5ff41ce 2958 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2959 if (kvm->arch.vpit)
2960 r = 0;
269e05e4 2961 create_pit_unlock:
79fac95e 2962 mutex_unlock(&kvm->slots_lock);
7837699f 2963 break;
4925663a 2964 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2965 case KVM_IRQ_LINE: {
2966 struct kvm_irq_level irq_event;
2967
2968 r = -EFAULT;
2969 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2970 goto out;
160d2f6c 2971 r = -ENXIO;
1fe779f8 2972 if (irqchip_in_kernel(kvm)) {
4925663a 2973 __s32 status;
4925663a
GN		 2974 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2975 irq_event.irq, irq_event.level);
4925663a 2976 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2977 r = -EFAULT;
4925663a
GN		 2978 irq_event.status = status;
2979 if (copy_to_user(argp, &irq_event,
2980 sizeof irq_event))
2981 goto out;
2982 }
1fe779f8
CO		 2983 r = 0;
2984 }
2985 break;
2986 }
2987 case KVM_GET_IRQCHIP: {
2988 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2989 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2990
f0d66275
DH		 2991 r = -ENOMEM;
2992 if (!chip)
1fe779f8 2993 goto out;
f0d66275
DH		 2994 r = -EFAULT;
2995 if (copy_from_user(chip, argp, sizeof *chip))
2996 goto get_irqchip_out;
1fe779f8
CO		 2997 r = -ENXIO;
2998 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2999 goto get_irqchip_out;
3000 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3001 if (r)
f0d66275 3002 goto get_irqchip_out;
1fe779f8 3003 r = -EFAULT;
f0d66275
DH		 3004 if (copy_to_user(argp, chip, sizeof *chip))
3005 goto get_irqchip_out;
1fe779f8 3006 r = 0;
f0d66275
DH		 3007 get_irqchip_out:
3008 kfree(chip);
3009 if (r)
3010 goto out;
1fe779f8
CO		 3011 break;
3012 }
3013 case KVM_SET_IRQCHIP: {
3014 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3015 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3016
f0d66275
DH		 3017 r = -ENOMEM;
3018 if (!chip)
1fe779f8 3019 goto out;
f0d66275
DH		 3020 r = -EFAULT;
3021 if (copy_from_user(chip, argp, sizeof *chip))
3022 goto set_irqchip_out;
1fe779f8
CO		 3023 r = -ENXIO;
3024 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3025 goto set_irqchip_out;
3026 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3027 if (r)
f0d66275 3028 goto set_irqchip_out;
1fe779f8 3029 r = 0;
f0d66275
DH		 3030 set_irqchip_out:
3031 kfree(chip);
3032 if (r)
3033 goto out;
1fe779f8
CO		 3034 break;
3035 }
e0f63cb9 3036 case KVM_GET_PIT: {
e0f63cb9 3037 r = -EFAULT;
f0d66275 3038 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3039 goto out;
3040 r = -ENXIO;
3041 if (!kvm->arch.vpit)
3042 goto out;
f0d66275 3043 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3044 if (r)
3045 goto out;
3046 r = -EFAULT;
f0d66275 3047 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3048 goto out;
3049 r = 0;
3050 break;
3051 }
3052 case KVM_SET_PIT: {
e0f63cb9 3053 r = -EFAULT;
f0d66275 3054 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3055 goto out;
3056 r = -ENXIO;
3057 if (!kvm->arch.vpit)
3058 goto out;
f0d66275 3059 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3060 if (r)
3061 goto out;
3062 r = 0;
3063 break;
3064 }
e9f42757
BK		 3065 case KVM_GET_PIT2: {
3066 r = -ENXIO;
3067 if (!kvm->arch.vpit)
3068 goto out;
3069 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3070 if (r)
3071 goto out;
3072 r = -EFAULT;
3073 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3074 goto out;
3075 r = 0;
3076 break;
3077 }
3078 case KVM_SET_PIT2: {
3079 r = -EFAULT;
3080 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3081 goto out;
3082 r = -ENXIO;
3083 if (!kvm->arch.vpit)
3084 goto out;
3085 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3086 if (r)
3087 goto out;
3088 r = 0;
3089 break;
3090 }
52d939a0
MT		 3091 case KVM_REINJECT_CONTROL: {
3092 struct kvm_reinject_control control;
3093 r = -EFAULT;
3094 if (copy_from_user(&control, argp, sizeof(control)))
3095 goto out;
3096 r = kvm_vm_ioctl_reinject(kvm, &control);
3097 if (r)
3098 goto out;
3099 r = 0;
3100 break;
3101 }
ffde22ac
ES		 3102 case KVM_XEN_HVM_CONFIG: {
3103 r = -EFAULT;
3104 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3105 sizeof(struct kvm_xen_hvm_config)))
3106 goto out;
3107 r = -EINVAL;
3108 if (kvm->arch.xen_hvm_config.flags)
3109 goto out;
3110 r = 0;
3111 break;
3112 }
afbcf7ab
GC		 3113 case KVM_SET_CLOCK: {
3114 struct timespec now;
3115 struct kvm_clock_data user_ns;
3116 u64 now_ns;
3117 s64 delta;
3118
3119 r = -EFAULT;
3120 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3121 goto out;
3122
3123 r = -EINVAL;
3124 if (user_ns.flags)
3125 goto out;
3126
3127 r = 0;
3128 ktime_get_ts(&now);
3129 now_ns = timespec_to_ns(&now);
3130 delta = user_ns.clock - now_ns;
3131 kvm->arch.kvmclock_offset = delta;
3132 break;
3133 }
3134 case KVM_GET_CLOCK: {
3135 struct timespec now;
3136 struct kvm_clock_data user_ns;
3137 u64 now_ns;
3138
3139 ktime_get_ts(&now);
3140 now_ns = timespec_to_ns(&now);
3141 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3142 user_ns.flags = 0;
3143
3144 r = -EFAULT;
3145 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3146 goto out;
3147 r = 0;
3148 break;
3149 }
3150
1fe779f8
CO		 3151 default:
3152 ;
3153 }
3154out:
3155 return r;
3156}
3157
a16b043c 3158static void kvm_init_msr_list(void)
043405e1
CO		 3159{
3160 u32 dummy[2];
3161 unsigned i, j;
3162
e3267cbb
GC		 3163 /* skip the first msrs in the list. KVM-specific */
3164 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3165 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3166 continue;
3167 if (j < i)
3168 msrs_to_save[j] = msrs_to_save[i];
3169 j++;
3170 }
3171 num_msrs_to_save = j;
3172}
3173
bda9020e
MT		 3174static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3175 const void *v)
bbd9b64e 3176{
bda9020e
MT		 3177 if (vcpu->arch.apic &&
3178 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3179 return 0;
bbd9b64e 3180
e93f8a0f 3181 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3182}
3183
bda9020e 3184static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3185{
bda9020e
MT		 3186 if (vcpu->arch.apic &&
3187 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3188 return 0;
bbd9b64e 3189
e93f8a0f 3190 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3191}
3192
2dafc6c2
GN		 3193static void kvm_set_segment(struct kvm_vcpu *vcpu,
3194 struct kvm_segment *var, int seg)
3195{
3196 kvm_x86_ops->set_segment(vcpu, var, seg);
3197}
3198
3199void kvm_get_segment(struct kvm_vcpu *vcpu,
3200 struct kvm_segment *var, int seg)
3201{
3202 kvm_x86_ops->get_segment(vcpu, var, seg);
3203}
3204
1871c602
GN		 3205gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3206{
3207 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3208 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3209}
3210
3211 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3212{
3213 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3214 access |= PFERR_FETCH_MASK;
3215 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3216}
3217
3218gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3219{
3220 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3221 access |= PFERR_WRITE_MASK;
3222 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3223}
3224
3225/* uses this to access any guest's mapped memory without checking CPL */
3226gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3227{
3228 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3229}
3230
3231static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3232 struct kvm_vcpu *vcpu, u32 access,
3233 u32 *error)
bbd9b64e
CO		 3234{
3235 void *data = val;
10589a46 3236 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3237
3238 while (bytes) {
1871c602 3239 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3240 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3241 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3242 int ret;
3243
10589a46
MT		 3244 if (gpa == UNMAPPED_GVA) {
3245 r = X86EMUL_PROPAGATE_FAULT;
3246 goto out;
3247 }
77c2002e 3248 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3249 if (ret < 0) {
c3cd7ffa 3250 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3251 goto out;
3252 }
bbd9b64e 3253
77c2002e
IE		 3254 bytes -= toread;
3255 data += toread;
3256 addr += toread;
bbd9b64e 3257 }
10589a46 3258out:
10589a46 3259 return r;
bbd9b64e 3260}
77c2002e 3261
1871c602
GN		 3262/* used for instruction fetching */
3263static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3264 struct kvm_vcpu *vcpu, u32 *error)
3265{
3266 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3267 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3268 access | PFERR_FETCH_MASK, error);
3269}
3270
3271static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3272 struct kvm_vcpu *vcpu, u32 *error)
3273{
3274 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3275 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3276 error);
3277}
3278
3279static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3280 struct kvm_vcpu *vcpu, u32 *error)
3281{
3282 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3283}
3284
7972995b 3285static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3286 unsigned int bytes,
7972995b 3287 struct kvm_vcpu *vcpu,
2dafc6c2 3288 u32 *error)
77c2002e
IE		 3289{
3290 void *data = val;
3291 int r = X86EMUL_CONTINUE;
3292
3293 while (bytes) {
7972995b
GN		 3294 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3295 PFERR_WRITE_MASK, error);
77c2002e
IE		 3296 unsigned offset = addr & (PAGE_SIZE-1);
3297 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3298 int ret;
3299
3300 if (gpa == UNMAPPED_GVA) {
3301 r = X86EMUL_PROPAGATE_FAULT;
3302 goto out;
3303 }
3304 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3305 if (ret < 0) {
c3cd7ffa 3306 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3307 goto out;
3308 }
3309
3310 bytes -= towrite;
3311 data += towrite;
3312 addr += towrite;
3313 }
3314out:
3315 return r;
3316}
3317
bbd9b64e
CO		 3318static int emulator_read_emulated(unsigned long addr,
3319 void *val,
3320 unsigned int bytes,
8fe681e9 3321 unsigned int *error_code,
bbd9b64e
CO		 3322 struct kvm_vcpu *vcpu)
3323{
bbd9b64e
CO		 3324 gpa_t gpa;
3325
3326 if (vcpu->mmio_read_completed) {
3327 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3328 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3329 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3330 vcpu->mmio_read_completed = 0;
3331 return X86EMUL_CONTINUE;
3332 }
3333
8fe681e9 3334 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3335
8fe681e9 3336 if (gpa == UNMAPPED_GVA)
1871c602 3337 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3338
3339 /* For APIC access vmexit */
3340 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3341 goto mmio;
3342
1871c602 3343 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3344 == X86EMUL_CONTINUE)
bbd9b64e 3345 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3346
3347mmio:
3348 /*
3349 * Is this MMIO handled locally?
3350 */
aec51dc4
AK		 3351 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3352 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3353 return X86EMUL_CONTINUE;
3354 }
aec51dc4
AK		 3355
3356 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3357
3358 vcpu->mmio_needed = 1;
411c35b7
GN		 3359 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3360 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3361 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3362 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3363
c3cd7ffa 3364 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3365}
3366
3200f405 3367int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3368 const void *val, int bytes)
bbd9b64e
CO		 3369{
3370 int ret;
3371
3372 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3373 if (ret < 0)
bbd9b64e 3374 return 0;
ad218f85 3375 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3376 return 1;
3377}
3378
3379static int emulator_write_emulated_onepage(unsigned long addr,
3380 const void *val,
3381 unsigned int bytes,
8fe681e9 3382 unsigned int *error_code,
bbd9b64e
CO		 3383 struct kvm_vcpu *vcpu)
3384{
10589a46
MT		 3385 gpa_t gpa;
3386
8fe681e9 3387 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3388
8fe681e9 3389 if (gpa == UNMAPPED_GVA)
bbd9b64e 3390 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3391
3392 /* For APIC access vmexit */
3393 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3394 goto mmio;
3395
3396 if (emulator_write_phys(vcpu, gpa, val, bytes))
3397 return X86EMUL_CONTINUE;
3398
3399mmio:
aec51dc4 3400 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3401 /*
3402 * Is this MMIO handled locally?
3403 */
bda9020e 3404 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3405 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3406
3407 vcpu->mmio_needed = 1;
411c35b7
GN		 3408 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3409 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3410 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3411 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3412 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3413
3414 return X86EMUL_CONTINUE;
3415}
3416
3417int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3418 const void *val,
3419 unsigned int bytes,
8fe681e9 3420 unsigned int *error_code,
8f6abd06 3421 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3422{
3423 /* Crossing a page boundary? */
3424 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3425 int rc, now;
3426
3427 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3428 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3429 vcpu);
bbd9b64e
CO		 3430 if (rc != X86EMUL_CONTINUE)
3431 return rc;
3432 addr += now;
3433 val += now;
3434 bytes -= now;
3435 }
8fe681e9
GN		 3436 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3437 vcpu);
bbd9b64e 3438}
bbd9b64e 3439
daea3e73
AK		 3440#define CMPXCHG_TYPE(t, ptr, old, new) \
3441 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3442
3443#ifdef CONFIG_X86_64
3444# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3445#else
3446# define CMPXCHG64(ptr, old, new) \
9749a6c0 3447 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3448#endif
3449
bbd9b64e
CO		 3450static int emulator_cmpxchg_emulated(unsigned long addr,
3451 const void *old,
3452 const void *new,
3453 unsigned int bytes,
8fe681e9 3454 unsigned int *error_code,
bbd9b64e
CO		 3455 struct kvm_vcpu *vcpu)
3456{
daea3e73
AK		 3457 gpa_t gpa;
3458 struct page *page;
3459 char *kaddr;
3460 bool exchanged;
2bacc55c 3461
daea3e73
AK		 3462 /* guests cmpxchg8b have to be emulated atomically */
3463 if (bytes > 8 || (bytes & (bytes - 1)))
3464 goto emul_write;
10589a46 3465
daea3e73 3466 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3467
daea3e73
AK		 3468 if (gpa == UNMAPPED_GVA ||
3469 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3470 goto emul_write;
2bacc55c 3471
daea3e73
AK		 3472 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3473 goto emul_write;
72dc67a6 3474
daea3e73 3475 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3476
daea3e73
AK		 3477 kaddr = kmap_atomic(page, KM_USER0);
3478 kaddr += offset_in_page(gpa);
3479 switch (bytes) {
3480 case 1:
3481 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3482 break;
3483 case 2:
3484 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3485 break;
3486 case 4:
3487 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3488 break;
3489 case 8:
3490 exchanged = CMPXCHG64(kaddr, old, new);
3491 break;
3492 default:
3493 BUG();
2bacc55c 3494 }
daea3e73
AK		 3495 kunmap_atomic(kaddr, KM_USER0);
3496 kvm_release_page_dirty(page);
3497
3498 if (!exchanged)
3499 return X86EMUL_CMPXCHG_FAILED;
3500
8f6abd06
GN		 3501 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3502
3503 return X86EMUL_CONTINUE;
4a5f48f6 3504
3200f405 3505emul_write:
daea3e73 3506 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3507
8fe681e9 3508 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3509}
3510
cf8f70bf
GN		 3511static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3512{
3513 /* TODO: String I/O for in kernel device */
3514 int r;
3515
3516 if (vcpu->arch.pio.in)
3517 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3518 vcpu->arch.pio.size, pd);
3519 else
3520 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3521 vcpu->arch.pio.port, vcpu->arch.pio.size,
3522 pd);
3523 return r;
3524}
3525
3526
3527static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3528 unsigned int count, struct kvm_vcpu *vcpu)
3529{
7972995b 3530 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3531 goto data_avail;
3532
3533 trace_kvm_pio(1, port, size, 1);
3534
3535 vcpu->arch.pio.port = port;
3536 vcpu->arch.pio.in = 1;
7972995b 3537 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3538 vcpu->arch.pio.size = size;
3539
3540 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3541 data_avail:
3542 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3543 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3544 return 1;
3545 }
3546
3547 vcpu->run->exit_reason = KVM_EXIT_IO;
3548 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3549 vcpu->run->io.size = size;
3550 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3551 vcpu->run->io.count = count;
3552 vcpu->run->io.port = port;
3553
3554 return 0;
3555}
3556
3557static int emulator_pio_out_emulated(int size, unsigned short port,
3558 const void *val, unsigned int count,
3559 struct kvm_vcpu *vcpu)
3560{
3561 trace_kvm_pio(0, port, size, 1);
3562
3563 vcpu->arch.pio.port = port;
3564 vcpu->arch.pio.in = 0;
7972995b 3565 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3566 vcpu->arch.pio.size = size;
3567
3568 memcpy(vcpu->arch.pio_data, val, size * count);
3569
3570 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3571 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3572 return 1;
3573 }
3574
3575 vcpu->run->exit_reason = KVM_EXIT_IO;
3576 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3577 vcpu->run->io.size = size;
3578 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3579 vcpu->run->io.count = count;
3580 vcpu->run->io.port = port;
3581
3582 return 0;
3583}
3584
bbd9b64e
CO		 3585static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3586{
3587 return kvm_x86_ops->get_segment_base(vcpu, seg);
3588}
3589
3590int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3591{
a7052897 3592 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3593 return X86EMUL_CONTINUE;
3594}
3595
3596int emulate_clts(struct kvm_vcpu *vcpu)
3597{
4d4ec087 3598 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3599 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3600 return X86EMUL_CONTINUE;
3601}
3602
35aa5375 3603int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3604{
338dbc97 3605 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3606}
3607
35aa5375 3608int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3609{
338dbc97
GN		 3610
3611 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3612}
3613
52a46617 3614static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3615{
52a46617 3616 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3617}
3618
52a46617 3619static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3620{
52a46617
GN		 3621 unsigned long value;
3622
3623 switch (cr) {
3624 case 0:
3625 value = kvm_read_cr0(vcpu);
3626 break;
3627 case 2:
3628 value = vcpu->arch.cr2;
3629 break;
3630 case 3:
3631 value = vcpu->arch.cr3;
3632 break;
3633 case 4:
3634 value = kvm_read_cr4(vcpu);
3635 break;
3636 case 8:
3637 value = kvm_get_cr8(vcpu);
3638 break;
3639 default:
3640 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3641 return 0;
3642 }
3643
3644 return value;
3645}
3646
0f12244f 3647static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3648{
0f12244f
GN		 3649 int res = 0;
3650
52a46617
GN		 3651 switch (cr) {
3652 case 0:
0f12244f 3653 res = __kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3654 break;
3655 case 2:
3656 vcpu->arch.cr2 = val;
3657 break;
3658 case 3:
0f12244f 3659 res = __kvm_set_cr3(vcpu, val);
52a46617
GN		 3660 break;
3661 case 4:
0f12244f 3662 res = __kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3663 break;
3664 case 8:
0f12244f 3665 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3666 break;
3667 default:
3668 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3669 res = -1;
52a46617 3670 }
0f12244f
GN		 3671
3672 return res;
52a46617
GN		 3673}
3674
9c537244
GN		 3675static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3676{
3677 return kvm_x86_ops->get_cpl(vcpu);
3678}
3679
2dafc6c2
GN		 3680static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3681{
3682 kvm_x86_ops->get_gdt(vcpu, dt);
3683}
3684
5951c442
GN		 3685static unsigned long emulator_get_cached_segment_base(int seg,
3686 struct kvm_vcpu *vcpu)
3687{
3688 return get_segment_base(vcpu, seg);
3689}
3690
2dafc6c2
GN		 3691static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3692 struct kvm_vcpu *vcpu)
3693{
3694 struct kvm_segment var;
3695
3696 kvm_get_segment(vcpu, &var, seg);
3697
3698 if (var.unusable)
3699 return false;
3700
3701 if (var.g)
3702 var.limit >>= 12;
3703 set_desc_limit(desc, var.limit);
3704 set_desc_base(desc, (unsigned long)var.base);
3705 desc->type = var.type;
3706 desc->s = var.s;
3707 desc->dpl = var.dpl;
3708 desc->p = var.present;
3709 desc->avl = var.avl;
3710 desc->l = var.l;
3711 desc->d = var.db;
3712 desc->g = var.g;
3713
3714 return true;
3715}
3716
3717static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3718 struct kvm_vcpu *vcpu)
3719{
3720 struct kvm_segment var;
3721
3722 /* needed to preserve selector */
3723 kvm_get_segment(vcpu, &var, seg);
3724
3725 var.base = get_desc_base(desc);
3726 var.limit = get_desc_limit(desc);
3727 if (desc->g)
3728 var.limit = (var.limit << 12) | 0xfff;
3729 var.type = desc->type;
3730 var.present = desc->p;
3731 var.dpl = desc->dpl;
3732 var.db = desc->d;
3733 var.s = desc->s;
3734 var.l = desc->l;
3735 var.g = desc->g;
3736 var.avl = desc->avl;
3737 var.present = desc->p;
3738 var.unusable = !var.present;
3739 var.padding = 0;
3740
3741 kvm_set_segment(vcpu, &var, seg);
3742 return;
3743}
3744
3745static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3746{
3747 struct kvm_segment kvm_seg;
3748
3749 kvm_get_segment(vcpu, &kvm_seg, seg);
3750 return kvm_seg.selector;
3751}
3752
3753static void emulator_set_segment_selector(u16 sel, int seg,
3754 struct kvm_vcpu *vcpu)
3755{
3756 struct kvm_segment kvm_seg;
3757
3758 kvm_get_segment(vcpu, &kvm_seg, seg);
3759 kvm_seg.selector = sel;
3760 kvm_set_segment(vcpu, &kvm_seg, seg);
3761}
3762
14af3f3c 3763static struct x86_emulate_ops emulate_ops = {
1871c602 3764 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3765 .write_std = kvm_write_guest_virt_system,
1871c602 3766 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3767 .read_emulated = emulator_read_emulated,
3768 .write_emulated = emulator_write_emulated,
3769 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3770 .pio_in_emulated = emulator_pio_in_emulated,
3771 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3772 .get_cached_descriptor = emulator_get_cached_descriptor,
3773 .set_cached_descriptor = emulator_set_cached_descriptor,
3774 .get_segment_selector = emulator_get_segment_selector,
3775 .set_segment_selector = emulator_set_segment_selector,
5951c442 3776 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3777 .get_gdt = emulator_get_gdt,
52a46617
GN		 3778 .get_cr = emulator_get_cr,
3779 .set_cr = emulator_set_cr,
9c537244 3780 .cpl = emulator_get_cpl,
35aa5375
GN		 3781 .get_dr = emulator_get_dr,
3782 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3783 .set_msr = kvm_set_msr,
3784 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3785};
3786
5fdbf976
MT		 3787static void cache_all_regs(struct kvm_vcpu *vcpu)
3788{
3789 kvm_register_read(vcpu, VCPU_REGS_RAX);
3790 kvm_register_read(vcpu, VCPU_REGS_RSP);
3791 kvm_register_read(vcpu, VCPU_REGS_RIP);
3792 vcpu->arch.regs_dirty = ~0;
3793}
3794
95cb2295
GN		 3795static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3796{
3797 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3798 /*
3799 * an sti; sti; sequence only disable interrupts for the first
3800 * instruction. So, if the last instruction, be it emulated or
3801 * not, left the system with the INT_STI flag enabled, it
3802 * means that the last instruction is an sti. We should not
3803 * leave the flag on in this case. The same goes for mov ss
3804 */
3805 if (!(int_shadow & mask))
3806 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3807}
3808
54b8486f
GN		 3809static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3810{
3811 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3812 if (ctxt->exception == PF_VECTOR)
3813 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3814 else if (ctxt->error_code_valid)
3815 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3816 else
3817 kvm_queue_exception(vcpu, ctxt->exception);
3818}
3819
6d77dbfc
GN		 3820static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3821{
6d77dbfc
GN		 3822 ++vcpu->stat.insn_emulation_fail;
3823 trace_kvm_emulate_insn_failed(vcpu);
3824 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3825 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3826 vcpu->run->internal.ndata = 0;
3827 kvm_queue_exception(vcpu, UD_VECTOR);
3828 return EMULATE_FAIL;
3829}
3830
bbd9b64e 3831int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3832 unsigned long cr2,
3833 u16 error_code,
571008da 3834 int emulation_type)
bbd9b64e 3835{
95cb2295 3836 int r;
4d2179e1 3837 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3838
26eef70c 3839 kvm_clear_exception_queue(vcpu);
ad312c7c 3840 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3841 /*
56e82318 3842 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3843 * instead of direct ->regs accesses, can save hundred cycles
3844 * on Intel for instructions that don't read/change RSP, for
3845 * for example.
3846 */
3847 cache_all_regs(vcpu);
bbd9b64e 3848
571008da 3849 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3850 int cs_db, cs_l;
3851 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3852
ad312c7c 3853 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3854 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3855 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3856 vcpu->arch.emulate_ctxt.mode =
a0044755 3857 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3858 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3859 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3860 ? X86EMUL_MODE_PROT64 : cs_db
3861 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3862 memset(c, 0, sizeof(struct decode_cache));
3863 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3864 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 3865 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 3866
ad312c7c 3867 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3868 trace_kvm_emulate_insn_start(vcpu);
571008da 3869
0cb5762e
AP		 3870 /* Only allow emulation of specific instructions on #UD
3871 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 3872 if (emulation_type & EMULTYPE_TRAP_UD) {
3873 if (!c->twobyte)
3874 return EMULATE_FAIL;
3875 switch (c->b) {
3876 case 0x01: /* VMMCALL */
3877 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3878 return EMULATE_FAIL;
3879 break;
3880 case 0x34: /* sysenter */
3881 case 0x35: /* sysexit */
3882 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3883 return EMULATE_FAIL;
3884 break;
3885 case 0x05: /* syscall */
3886 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3887 return EMULATE_FAIL;
3888 break;
3889 default:
3890 return EMULATE_FAIL;
3891 }
3892
3893 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3894 return EMULATE_FAIL;
3895 }
571008da 3896
f2b5756b 3897 ++vcpu->stat.insn_emulation;
bbd9b64e
CO		 3898 if (r) {
3899 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3900 return EMULATE_DONE;
6d77dbfc
GN		 3901 if (emulation_type & EMULTYPE_SKIP)
3902 return EMULATE_FAIL;
3903 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3904 }
3905 }
3906
ba8afb6b
GN		 3907 if (emulation_type & EMULTYPE_SKIP) {
3908 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3909 return EMULATE_DONE;
3910 }
3911
4d2179e1
GN		 3912 /* this is needed for vmware backdor interface to work since it
3913 changes registers values during IO operation */
3914 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
3915
5cd21917 3916restart:
ad312c7c 3917 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 3918
c3cd7ffa
GN		 3919 if (r) { /* emulation failed */
3920 /*
3921 * if emulation was due to access to shadowed page table
3922 * and it failed try to unshadow page and re-entetr the
3923 * guest to let CPU execute the instruction.
3924 */
3925 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3926 return EMULATE_DONE;
3927
6d77dbfc 3928 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3929 }
3930
95cb2295 3931 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 3932 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 3933 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 3934 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 3935
54b8486f
GN		 3936 if (vcpu->arch.emulate_ctxt.exception >= 0) {
3937 inject_emulated_exception(vcpu);
3938 return EMULATE_DONE;
3939 }
3940
3457e419
GN		 3941 if (vcpu->arch.pio.count) {
3942 if (!vcpu->arch.pio.in)
3943 vcpu->arch.pio.count = 0;
3944 return EMULATE_DO_MMIO;
3945 }
3946
3947 if (vcpu->mmio_needed) {
3948 if (vcpu->mmio_is_write)
3949 vcpu->mmio_needed = 0;
3950 return EMULATE_DO_MMIO;
3951 }
3952
5cd21917
GN		 3953 if (vcpu->arch.emulate_ctxt.restart)
3954 goto restart;
f850e2e6 3955
bbd9b64e 3956 return EMULATE_DONE;
de7d789a 3957}
bbd9b64e 3958EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 3959
cf8f70bf 3960int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 3961{
cf8f70bf
GN		 3962 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3963 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3964 /* do not return to emulator after return from userspace */
7972995b 3965 vcpu->arch.pio.count = 0;
de7d789a
CO		 3966 return ret;
3967}
cf8f70bf 3968EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 3969
c8076604
GH		 3970static void bounce_off(void *info)
3971{
3972 /* nothing */
3973}
3974
c8076604
GH		 3975static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3976 void *data)
3977{
3978 struct cpufreq_freqs *freq = data;
3979 struct kvm *kvm;
3980 struct kvm_vcpu *vcpu;
3981 int i, send_ipi = 0;
3982
c8076604
GH		 3983 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3984 return 0;
3985 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3986 return 0;
0cca7907 3987 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3988
3989 spin_lock(&kvm_lock);
3990 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3991 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3992 if (vcpu->cpu != freq->cpu)
3993 continue;
3994 if (!kvm_request_guest_time_update(vcpu))
3995 continue;
3996 if (vcpu->cpu != smp_processor_id())
3997 send_ipi++;
3998 }
3999 }
4000 spin_unlock(&kvm_lock);
4001
4002 if (freq->old < freq->new && send_ipi) {
4003 /*
4004 * We upscale the frequency. Must make the guest
4005 * doesn't see old kvmclock values while running with
4006 * the new frequency, otherwise we risk the guest sees
4007 * time go backwards.
4008 *
4009 * In case we update the frequency for another cpu
4010 * (which might be in guest context) send an interrupt
4011 * to kick the cpu out of guest context. Next time
4012 * guest context is entered kvmclock will be updated,
4013 * so the guest will not see stale values.
4014 */
4015 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4016 }
4017 return 0;
4018}
4019
4020static struct notifier_block kvmclock_cpufreq_notifier_block = {
4021 .notifier_call = kvmclock_cpufreq_notifier
4022};
4023
b820cc0c
ZA		 4024static void kvm_timer_init(void)
4025{
4026 int cpu;
4027
b820cc0c 4028 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4029 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4030 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4031 for_each_online_cpu(cpu) {
4032 unsigned long khz = cpufreq_get(cpu);
4033 if (!khz)
4034 khz = tsc_khz;
4035 per_cpu(cpu_tsc_khz, cpu) = khz;
4036 }
0cca7907
ZA		 4037 } else {
4038 for_each_possible_cpu(cpu)
4039 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4040 }
4041}
4042
ff9d07a0
ZY		 4043static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4044
4045static int kvm_is_in_guest(void)
4046{
4047 return percpu_read(current_vcpu) != NULL;
4048}
4049
4050static int kvm_is_user_mode(void)
4051{
4052 int user_mode = 3;
dcf46b94 4053
ff9d07a0
ZY		 4054 if (percpu_read(current_vcpu))
4055 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4056
ff9d07a0
ZY		 4057 return user_mode != 0;
4058}
4059
4060static unsigned long kvm_get_guest_ip(void)
4061{
4062 unsigned long ip = 0;
dcf46b94 4063
ff9d07a0
ZY		 4064 if (percpu_read(current_vcpu))
4065 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4066
ff9d07a0
ZY		 4067 return ip;
4068}
4069
4070static struct perf_guest_info_callbacks kvm_guest_cbs = {
4071 .is_in_guest = kvm_is_in_guest,
4072 .is_user_mode = kvm_is_user_mode,
4073 .get_guest_ip = kvm_get_guest_ip,
4074};
4075
4076void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4077{
4078 percpu_write(current_vcpu, vcpu);
4079}
4080EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4081
4082void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4083{
4084 percpu_write(current_vcpu, NULL);
4085}
4086EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4087
f8c16bba 4088int kvm_arch_init(void *opaque)
043405e1 4089{
b820cc0c 4090 int r;
f8c16bba
ZX		 4091 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4092
f8c16bba
ZX		 4093 if (kvm_x86_ops) {
4094 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4095 r = -EEXIST;
4096 goto out;
f8c16bba
ZX		 4097 }
4098
4099 if (!ops->cpu_has_kvm_support()) {
4100 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4101 r = -EOPNOTSUPP;
4102 goto out;
f8c16bba
ZX		 4103 }
4104 if (ops->disabled_by_bios()) {
4105 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4106 r = -EOPNOTSUPP;
4107 goto out;
f8c16bba
ZX		 4108 }
4109
97db56ce
AK		 4110 r = kvm_mmu_module_init();
4111 if (r)
4112 goto out;
4113
4114 kvm_init_msr_list();
4115
f8c16bba 4116 kvm_x86_ops = ops;
56c6d28a 4117 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4118 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4119 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4120 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4121
b820cc0c 4122 kvm_timer_init();
c8076604 4123
ff9d07a0
ZY		 4124 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4125
f8c16bba 4126 return 0;
56c6d28a
ZX		 4127
4128out:
56c6d28a 4129 return r;
043405e1 4130}
8776e519 4131
f8c16bba
ZX		 4132void kvm_arch_exit(void)
4133{
ff9d07a0
ZY		 4134 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4135
888d256e
JK		 4136 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4137 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4138 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4139 kvm_x86_ops = NULL;
56c6d28a
ZX		 4140 kvm_mmu_module_exit();
4141}
f8c16bba 4142
8776e519
HB		 4143int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4144{
4145 ++vcpu->stat.halt_exits;
4146 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4147 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4148 return 1;
4149 } else {
4150 vcpu->run->exit_reason = KVM_EXIT_HLT;
4151 return 0;
4152 }
4153}
4154EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4155
2f333bcb
MT		 4156static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4157 unsigned long a1)
4158{
4159 if (is_long_mode(vcpu))
4160 return a0;
4161 else
4162 return a0 | ((gpa_t)a1 << 32);
4163}
4164
55cd8e5a
GN		 4165int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4166{
4167 u64 param, ingpa, outgpa, ret;
4168 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4169 bool fast, longmode;
4170 int cs_db, cs_l;
4171
4172 /*
4173 * hypercall generates UD from non zero cpl and real mode
4174 * per HYPER-V spec
4175 */
3eeb3288 4176 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4177 kvm_queue_exception(vcpu, UD_VECTOR);
4178 return 0;
4179 }
4180
4181 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4182 longmode = is_long_mode(vcpu) && cs_l == 1;
4183
4184 if (!longmode) {
ccd46936
GN		 4185 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4186 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4187 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4188 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4189 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4190 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4191 }
4192#ifdef CONFIG_X86_64
4193 else {
4194 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4195 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4196 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4197 }
4198#endif
4199
4200 code = param & 0xffff;
4201 fast = (param >> 16) & 0x1;
4202 rep_cnt = (param >> 32) & 0xfff;
4203 rep_idx = (param >> 48) & 0xfff;
4204
4205 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4206
c25bc163
GN		 4207 switch (code) {
4208 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4209 kvm_vcpu_on_spin(vcpu);
4210 break;
4211 default:
4212 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4213 break;
4214 }
55cd8e5a
GN		 4215
4216 ret = res | (((u64)rep_done & 0xfff) << 32);
4217 if (longmode) {
4218 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4219 } else {
4220 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4221 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4222 }
4223
4224 return 1;
4225}
4226
8776e519
HB		 4227int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4228{
4229 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4230 int r = 1;
8776e519 4231
55cd8e5a
GN		 4232 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4233 return kvm_hv_hypercall(vcpu);
4234
5fdbf976
MT		 4235 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4236 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4237 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4238 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4239 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4240
229456fc 4241 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4242
8776e519
HB		 4243 if (!is_long_mode(vcpu)) {
4244 nr &= 0xFFFFFFFF;
4245 a0 &= 0xFFFFFFFF;
4246 a1 &= 0xFFFFFFFF;
4247 a2 &= 0xFFFFFFFF;
4248 a3 &= 0xFFFFFFFF;
4249 }
4250
07708c4a
JK		 4251 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4252 ret = -KVM_EPERM;
4253 goto out;
4254 }
4255
8776e519 4256 switch (nr) {
b93463aa
AK		 4257 case KVM_HC_VAPIC_POLL_IRQ:
4258 ret = 0;
4259 break;
2f333bcb
MT		 4260 case KVM_HC_MMU_OP:
4261 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4262 break;
8776e519
HB		 4263 default:
4264 ret = -KVM_ENOSYS;
4265 break;
4266 }
07708c4a 4267out:
5fdbf976 4268 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4269 ++vcpu->stat.hypercalls;
2f333bcb 4270 return r;
8776e519
HB		 4271}
4272EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4273
4274int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4275{
4276 char instruction[3];
5fdbf976 4277 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4278
8776e519
HB		 4279 /*
4280 * Blow out the MMU to ensure that no other VCPU has an active mapping
4281 * to ensure that the updated hypercall appears atomically across all
4282 * VCPUs.
4283 */
4284 kvm_mmu_zap_all(vcpu->kvm);
4285
8776e519 4286 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4287
8fe681e9 4288 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4289}
4290
8776e519
HB		 4291void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4292{
89a27f4d 4293 struct desc_ptr dt = { limit, base };
8776e519
HB		 4294
4295 kvm_x86_ops->set_gdt(vcpu, &dt);
4296}
4297
4298void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4299{
89a27f4d 4300 struct desc_ptr dt = { limit, base };
8776e519
HB		 4301
4302 kvm_x86_ops->set_idt(vcpu, &dt);
4303}
4304
07716717
DK		 4305static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4306{
ad312c7c
ZX		 4307 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4308 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4309
4310 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4311 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4312 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4313 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4314 if (ej->function == e->function) {
4315 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4316 return j;
4317 }
4318 }
4319 return 0; /* silence gcc, even though control never reaches here */
4320}
4321
4322/* find an entry with matching function, matching index (if needed), and that
4323 * should be read next (if it's stateful) */
4324static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4325 u32 function, u32 index)
4326{
4327 if (e->function != function)
4328 return 0;
4329 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4330 return 0;
4331 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4332 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4333 return 0;
4334 return 1;
4335}
4336
d8017474
AG		 4337struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4338 u32 function, u32 index)
8776e519
HB		 4339{
4340 int i;
d8017474 4341 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4342
ad312c7c 4343 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4344 struct kvm_cpuid_entry2 *e;
4345
ad312c7c 4346 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4347 if (is_matching_cpuid_entry(e, function, index)) {
4348 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4349 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4350 best = e;
4351 break;
4352 }
4353 /*
4354 * Both basic or both extended?
4355 */
4356 if (((e->function ^ function) & 0x80000000) == 0)
4357 if (!best || e->function > best->function)
4358 best = e;
4359 }
d8017474
AG		 4360 return best;
4361}
0e851880 4362EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4363
82725b20
DE		 4364int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4365{
4366 struct kvm_cpuid_entry2 *best;
4367
f7a71197
AK		 4368 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4369 if (!best || best->eax < 0x80000008)
4370 goto not_found;
82725b20
DE		 4371 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4372 if (best)
4373 return best->eax & 0xff;
f7a71197 4374not_found:
82725b20
DE		 4375 return 36;
4376}
4377
d8017474
AG		 4378void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4379{
4380 u32 function, index;
4381 struct kvm_cpuid_entry2 *best;
4382
4383 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4384 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4385 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4386 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4387 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4388 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4389 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4390 if (best) {
5fdbf976
MT		 4391 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4392 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4393 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4394 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4395 }
8776e519 4396 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4397 trace_kvm_cpuid(function,
4398 kvm_register_read(vcpu, VCPU_REGS_RAX),
4399 kvm_register_read(vcpu, VCPU_REGS_RBX),
4400 kvm_register_read(vcpu, VCPU_REGS_RCX),
4401 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4402}
4403EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4404
b6c7a5dc
HB		 4405/*
4406 * Check if userspace requested an interrupt window, and that the
4407 * interrupt window is open.
4408 *
4409 * No need to exit to userspace if we already have an interrupt queued.
4410 */
851ba692 4411static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4412{
8061823a 4413 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4414 vcpu->run->request_interrupt_window &&
5df56646 4415 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4416}
4417
851ba692 4418static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4419{
851ba692
AK		 4420 struct kvm_run *kvm_run = vcpu->run;
4421
91586a3b 4422 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4423 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4424 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4425 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4426 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4427 else
b6c7a5dc 4428 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4429 kvm_arch_interrupt_allowed(vcpu) &&
4430 !kvm_cpu_has_interrupt(vcpu) &&
4431 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4432}
4433
b93463aa
AK		 4434static void vapic_enter(struct kvm_vcpu *vcpu)
4435{
4436 struct kvm_lapic *apic = vcpu->arch.apic;
4437 struct page *page;
4438
4439 if (!apic || !apic->vapic_addr)
4440 return;
4441
4442 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4443
4444 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4445}
4446
4447static void vapic_exit(struct kvm_vcpu *vcpu)
4448{
4449 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4450 int idx;
b93463aa
AK		 4451
4452 if (!apic || !apic->vapic_addr)
4453 return;
4454
f656ce01 4455 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4456 kvm_release_page_dirty(apic->vapic_page);
4457 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4458 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4459}
4460
95ba8273
GN		 4461static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4462{
4463 int max_irr, tpr;
4464
4465 if (!kvm_x86_ops->update_cr8_intercept)
4466 return;
4467
88c808fd
AK		 4468 if (!vcpu->arch.apic)
4469 return;
4470
8db3baa2
GN		 4471 if (!vcpu->arch.apic->vapic_addr)
4472 max_irr = kvm_lapic_find_highest_irr(vcpu);
4473 else
4474 max_irr = -1;
95ba8273
GN		 4475
4476 if (max_irr != -1)
4477 max_irr >>= 4;
4478
4479 tpr = kvm_lapic_get_cr8(vcpu);
4480
4481 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4482}
4483
851ba692 4484static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4485{
4486 /* try to reinject previous events if any */
b59bb7bd 4487 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4488 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4489 vcpu->arch.exception.has_error_code,
4490 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4491 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4492 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4493 vcpu->arch.exception.error_code,
4494 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4495 return;
4496 }
4497
95ba8273
GN		 4498 if (vcpu->arch.nmi_injected) {
4499 kvm_x86_ops->set_nmi(vcpu);
4500 return;
4501 }
4502
4503 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4504 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4505 return;
4506 }
4507
4508 /* try to inject new event if pending */
4509 if (vcpu->arch.nmi_pending) {
4510 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4511 vcpu->arch.nmi_pending = false;
4512 vcpu->arch.nmi_injected = true;
4513 kvm_x86_ops->set_nmi(vcpu);
4514 }
4515 } else if (kvm_cpu_has_interrupt(vcpu)) {
4516 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4517 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4518 false);
4519 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4520 }
4521 }
4522}
4523
851ba692 4524static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4525{
4526 int r;
6a8b1d13 4527 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4528 vcpu->run->request_interrupt_window;
b6c7a5dc 4529
2e53d63a
MT		 4530 if (vcpu->requests)
4531 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4532 kvm_mmu_unload(vcpu);
4533
b6c7a5dc
HB		 4534 r = kvm_mmu_reload(vcpu);
4535 if (unlikely(r))
4536 goto out;
4537
2f52d58c
AK		 4538 if (vcpu->requests) {
4539 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4540 __kvm_migrate_timers(vcpu);
c8076604
GH		 4541 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4542 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4543 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4544 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4545 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4546 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4547 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4548 &vcpu->requests)) {
851ba692 4549 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4550 r = 0;
4551 goto out;
4552 }
71c4dfaf 4553 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4554 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4555 r = 0;
4556 goto out;
4557 }
02daab21
AK		 4558 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4559 vcpu->fpu_active = 0;
4560 kvm_x86_ops->fpu_deactivate(vcpu);
4561 }
2f52d58c 4562 }
b93463aa 4563
b6c7a5dc
HB		 4564 preempt_disable();
4565
4566 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4567 if (vcpu->fpu_active)
4568 kvm_load_guest_fpu(vcpu);
b6c7a5dc 4569
d94e1dc9
AK		 4570 atomic_set(&vcpu->guest_mode, 1);
4571 smp_wmb();
b6c7a5dc 4572
d94e1dc9 4573 local_irq_disable();
32f88400 4574
d94e1dc9
AK		 4575 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4576 || need_resched() || signal_pending(current)) {
4577 atomic_set(&vcpu->guest_mode, 0);
4578 smp_wmb();
6c142801
AK		 4579 local_irq_enable();
4580 preempt_enable();
4581 r = 1;
4582 goto out;
4583 }
4584
851ba692 4585 inject_pending_event(vcpu);
b6c7a5dc 4586
6a8b1d13
GN		 4587 /* enable NMI/IRQ window open exits if needed */
4588 if (vcpu->arch.nmi_pending)
4589 kvm_x86_ops->enable_nmi_window(vcpu);
4590 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4591 kvm_x86_ops->enable_irq_window(vcpu);
4592
95ba8273 4593 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4594 update_cr8_intercept(vcpu);
4595 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4596 }
b93463aa 4597
f656ce01 4598 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4599
b6c7a5dc
HB		 4600 kvm_guest_enter();
4601
42dbaa5a 4602 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4603 set_debugreg(0, 7);
4604 set_debugreg(vcpu->arch.eff_db[0], 0);
4605 set_debugreg(vcpu->arch.eff_db[1], 1);
4606 set_debugreg(vcpu->arch.eff_db[2], 2);
4607 set_debugreg(vcpu->arch.eff_db[3], 3);
4608 }
b6c7a5dc 4609
229456fc 4610 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4611 kvm_x86_ops->run(vcpu);
b6c7a5dc 4612
24f1e32c
FW		 4613 /*
4614 * If the guest has used debug registers, at least dr7
4615 * will be disabled while returning to the host.
4616 * If we don't have active breakpoints in the host, we don't
4617 * care about the messed up debug address registers. But if
4618 * we have some of them active, restore the old state.
4619 */
59d8eb53 4620 if (hw_breakpoint_active())
24f1e32c 4621 hw_breakpoint_restore();
42dbaa5a 4622
d94e1dc9
AK		 4623 atomic_set(&vcpu->guest_mode, 0);
4624 smp_wmb();
b6c7a5dc
HB		 4625 local_irq_enable();
4626
4627 ++vcpu->stat.exits;
4628
4629 /*
4630 * We must have an instruction between local_irq_enable() and
4631 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4632 * the interrupt shadow. The stat.exits increment will do nicely.
4633 * But we need to prevent reordering, hence this barrier():
4634 */
4635 barrier();
4636
4637 kvm_guest_exit();
4638
4639 preempt_enable();
4640
f656ce01 4641 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4642
b6c7a5dc
HB		 4643 /*
4644 * Profile KVM exit RIPs:
4645 */
4646 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4647 unsigned long rip = kvm_rip_read(vcpu);
4648 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4649 }
4650
298101da 4651
b93463aa
AK		 4652 kvm_lapic_sync_from_vapic(vcpu);
4653
851ba692 4654 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4655out:
4656 return r;
4657}
b6c7a5dc 4658
09cec754 4659
851ba692 4660static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4661{
4662 int r;
f656ce01 4663 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4664
4665 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4666 pr_debug("vcpu %d received sipi with vector # %x\n",
4667 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4668 kvm_lapic_reset(vcpu);
5f179287 4669 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4670 if (r)
4671 return r;
4672 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4673 }
4674
f656ce01 4675 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4676 vapic_enter(vcpu);
4677
4678 r = 1;
4679 while (r > 0) {
af2152f5 4680 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4681 r = vcpu_enter_guest(vcpu);
d7690175 4682 else {
f656ce01 4683 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4684 kvm_vcpu_block(vcpu);
f656ce01 4685 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4686 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4687 {
4688 switch(vcpu->arch.mp_state) {
4689 case KVM_MP_STATE_HALTED:
d7690175 4690 vcpu->arch.mp_state =
09cec754
GN		 4691 KVM_MP_STATE_RUNNABLE;
4692 case KVM_MP_STATE_RUNNABLE:
4693 break;
4694 case KVM_MP_STATE_SIPI_RECEIVED:
4695 default:
4696 r = -EINTR;
4697 break;
4698 }
4699 }
d7690175
MT		 4700 }
4701
09cec754
GN		 4702 if (r <= 0)
4703 break;
4704
4705 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4706 if (kvm_cpu_has_pending_timer(vcpu))
4707 kvm_inject_pending_timer_irqs(vcpu);
4708
851ba692 4709 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4710 r = -EINTR;
851ba692 4711 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4712 ++vcpu->stat.request_irq_exits;
4713 }
4714 if (signal_pending(current)) {
4715 r = -EINTR;
851ba692 4716 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4717 ++vcpu->stat.signal_exits;
4718 }
4719 if (need_resched()) {
f656ce01 4720 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4721 kvm_resched(vcpu);
f656ce01 4722 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4723 }
b6c7a5dc
HB		 4724 }
4725
f656ce01 4726 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4727
b93463aa
AK		 4728 vapic_exit(vcpu);
4729
b6c7a5dc
HB		 4730 return r;
4731}
4732
4733int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4734{
4735 int r;
4736 sigset_t sigsaved;
4737
ac9f6dc0
AK		 4738 if (vcpu->sigset_active)
4739 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4740
a4535290 4741 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4742 kvm_vcpu_block(vcpu);
d7690175 4743 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4744 r = -EAGAIN;
4745 goto out;
b6c7a5dc
HB		 4746 }
4747
b6c7a5dc
HB		 4748 /* re-sync apic's tpr */
4749 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4750 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4751
92bf9748
GN		 4752 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4753 vcpu->arch.emulate_ctxt.restart) {
4754 if (vcpu->mmio_needed) {
4755 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4756 vcpu->mmio_read_completed = 1;
4757 vcpu->mmio_needed = 0;
b6c7a5dc 4758 }
f656ce01 4759 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4760 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4761 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4762 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4763 r = 0;
4764 goto out;
4765 }
4766 }
5fdbf976
MT		 4767 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4768 kvm_register_write(vcpu, VCPU_REGS_RAX,
4769 kvm_run->hypercall.ret);
b6c7a5dc 4770
851ba692 4771 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4772
4773out:
f1d86e46 4774 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4775 if (vcpu->sigset_active)
4776 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4777
b6c7a5dc
HB		 4778 return r;
4779}
4780
4781int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4782{
5fdbf976
MT		 4783 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4784 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4785 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4786 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4787 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4788 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4789 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4790 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4791#ifdef CONFIG_X86_64
5fdbf976
MT		 4792 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4793 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4794 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4795 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4796 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4797 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4798 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4799 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4800#endif
4801
5fdbf976 4802 regs->rip = kvm_rip_read(vcpu);
91586a3b 4803 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 4804
b6c7a5dc
HB		 4805 return 0;
4806}
4807
4808int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4809{
5fdbf976
MT		 4810 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4811 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4812 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4813 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4814 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4815 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4816 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4817 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4818#ifdef CONFIG_X86_64
5fdbf976
MT		 4819 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4820 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4821 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4822 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4823 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4824 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4825 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4826 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4827#endif
4828
5fdbf976 4829 kvm_rip_write(vcpu, regs->rip);
91586a3b 4830 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4831
b4f14abd
JK		 4832 vcpu->arch.exception.pending = false;
4833
b6c7a5dc
HB		 4834 return 0;
4835}
4836
b6c7a5dc
HB		 4837void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4838{
4839 struct kvm_segment cs;
4840
3e6e0aab 4841 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4842 *db = cs.db;
4843 *l = cs.l;
4844}
4845EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4846
4847int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4848 struct kvm_sregs *sregs)
4849{
89a27f4d 4850 struct desc_ptr dt;
b6c7a5dc 4851
3e6e0aab
GT		 4852 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4853 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4854 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4855 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4856 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4857 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4858
3e6e0aab
GT		 4859 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4860 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4861
4862 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4863 sregs->idt.limit = dt.size;
4864 sregs->idt.base = dt.address;
b6c7a5dc 4865 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4866 sregs->gdt.limit = dt.size;
4867 sregs->gdt.base = dt.address;
b6c7a5dc 4868
4d4ec087 4869 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4870 sregs->cr2 = vcpu->arch.cr2;
4871 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4872 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4873 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4874 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4875 sregs->apic_base = kvm_get_apic_base(vcpu);
4876
923c61bb 4877 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4878
36752c9b 4879 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4880 set_bit(vcpu->arch.interrupt.nr,
4881 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4882
b6c7a5dc
HB		 4883 return 0;
4884}
4885
62d9f0db
MT		 4886int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4887 struct kvm_mp_state *mp_state)
4888{
62d9f0db 4889 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 4890 return 0;
4891}
4892
4893int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4894 struct kvm_mp_state *mp_state)
4895{
62d9f0db 4896 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 4897 return 0;
4898}
4899
e269fb21
JK		 4900int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4901 bool has_error_code, u32 error_code)
b6c7a5dc 4902{
4d2179e1 4903 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 4904 int cs_db, cs_l, ret;
4905 cache_all_regs(vcpu);
37817f29 4906
ceffb459 4907 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 4908
ceffb459
GN		 4909 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4910 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4911 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4912 vcpu->arch.emulate_ctxt.mode =
4913 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4914 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4915 ? X86EMUL_MODE_VM86 : cs_l
4916 ? X86EMUL_MODE_PROT64 : cs_db
4917 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 4918 memset(c, 0, sizeof(struct decode_cache));
4919 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 4920
ceffb459 4921 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4922 tss_selector, reason, has_error_code,
4923 error_code);
c697518a 4924
c697518a 4925 if (ret)
19d04437 4926 return EMULATE_FAIL;
37817f29 4927
4d2179e1 4928 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4929 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 4930 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4931 return EMULATE_DONE;
37817f29
IE		 4932}
4933EXPORT_SYMBOL_GPL(kvm_task_switch);
4934
b6c7a5dc
HB		 4935int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4936 struct kvm_sregs *sregs)
4937{
4938 int mmu_reset_needed = 0;
923c61bb 4939 int pending_vec, max_bits;
89a27f4d 4940 struct desc_ptr dt;
b6c7a5dc 4941
89a27f4d
GN		 4942 dt.size = sregs->idt.limit;
4943 dt.address = sregs->idt.base;
b6c7a5dc 4944 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4945 dt.size = sregs->gdt.limit;
4946 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4947 kvm_x86_ops->set_gdt(vcpu, &dt);
4948
ad312c7c
ZX		 4949 vcpu->arch.cr2 = sregs->cr2;
4950 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4951 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4952
2d3ad1f4 4953 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4954
f6801dff 4955 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4956 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4957 kvm_set_apic_base(vcpu, sregs->apic_base);
4958
4d4ec087 4959 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4960 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4961 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4962
fc78f519 4963 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4964 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4965 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4966 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4967 mmu_reset_needed = 1;
4968 }
b6c7a5dc
HB		 4969
4970 if (mmu_reset_needed)
4971 kvm_mmu_reset_context(vcpu);
4972
923c61bb
GN		 4973 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4974 pending_vec = find_first_bit(
4975 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4976 if (pending_vec < max_bits) {
66fd3f7f 4977 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4978 pr_debug("Set back pending irq %d\n", pending_vec);
4979 if (irqchip_in_kernel(vcpu->kvm))
4980 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4981 }
4982
3e6e0aab
GT		 4983 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4984 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4985 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4986 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4987 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4988 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4989
3e6e0aab
GT		 4990 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4991 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4992
5f0269f5
ME		 4993 update_cr8_intercept(vcpu);
4994
9c3e4aab 4995 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4996 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4997 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4998 !is_protmode(vcpu))
9c3e4aab
MT		 4999 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5000
b6c7a5dc
HB		 5001 return 0;
5002}
5003
d0bfb940
JK		 5004int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5005 struct kvm_guest_debug *dbg)
b6c7a5dc 5006{
355be0b9 5007 unsigned long rflags;
ae675ef0 5008 int i, r;
b6c7a5dc 5009
4f926bf2
JK		 5010 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5011 r = -EBUSY;
5012 if (vcpu->arch.exception.pending)
2122ff5e 5013 goto out;
4f926bf2
JK		 5014 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5015 kvm_queue_exception(vcpu, DB_VECTOR);
5016 else
5017 kvm_queue_exception(vcpu, BP_VECTOR);
5018 }
5019
91586a3b
JK		 5020 /*
5021 * Read rflags as long as potentially injected trace flags are still
5022 * filtered out.
5023 */
5024 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5025
5026 vcpu->guest_debug = dbg->control;
5027 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5028 vcpu->guest_debug = 0;
5029
5030 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5031 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5032 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5033 vcpu->arch.switch_db_regs =
5034 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5035 } else {
5036 for (i = 0; i < KVM_NR_DB_REGS; i++)
5037 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5038 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5039 }
5040
f92653ee
JK		 5041 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5042 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5043 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5044
91586a3b
JK		 5045 /*
5046 * Trigger an rflags update that will inject or remove the trace
5047 * flags.
5048 */
5049 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5050
355be0b9 5051 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5052
4f926bf2 5053 r = 0;
d0bfb940 5054
2122ff5e 5055out:
b6c7a5dc
HB		 5056
5057 return r;
5058}
5059
d0752060
HB		 5060/*
5061 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5062 * we have asm/x86/processor.h
5063 */
5064struct fxsave {
5065 u16 cwd;
5066 u16 swd;
5067 u16 twd;
5068 u16 fop;
5069 u64 rip;
5070 u64 rdp;
5071 u32 mxcsr;
5072 u32 mxcsr_mask;
5073 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5074#ifdef CONFIG_X86_64
5075 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5076#else
5077 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5078#endif
5079};
5080
8b006791
ZX		 5081/*
5082 * Translate a guest virtual address to a guest physical address.
5083 */
5084int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5085 struct kvm_translation *tr)
5086{
5087 unsigned long vaddr = tr->linear_address;
5088 gpa_t gpa;
f656ce01 5089 int idx;
8b006791 5090
f656ce01 5091 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5092 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5093 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5094 tr->physical_address = gpa;
5095 tr->valid = gpa != UNMAPPED_GVA;
5096 tr->writeable = 1;
5097 tr->usermode = 0;
8b006791
ZX		 5098
5099 return 0;
5100}
5101
d0752060
HB		 5102int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5103{
ad312c7c 5104 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060 5105
d0752060
HB		 5106 memcpy(fpu->fpr, fxsave->st_space, 128);
5107 fpu->fcw = fxsave->cwd;
5108 fpu->fsw = fxsave->swd;
5109 fpu->ftwx = fxsave->twd;
5110 fpu->last_opcode = fxsave->fop;
5111 fpu->last_ip = fxsave->rip;
5112 fpu->last_dp = fxsave->rdp;
5113 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5114
d0752060
HB		 5115 return 0;
5116}
5117
5118int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5119{
ad312c7c 5120 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060 5121
d0752060
HB		 5122 memcpy(fxsave->st_space, fpu->fpr, 128);
5123 fxsave->cwd = fpu->fcw;
5124 fxsave->swd = fpu->fsw;
5125 fxsave->twd = fpu->ftwx;
5126 fxsave->fop = fpu->last_opcode;
5127 fxsave->rip = fpu->last_ip;
5128 fxsave->rdp = fpu->last_dp;
5129 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5130
d0752060
HB		 5131 return 0;
5132}
5133
5134void fx_init(struct kvm_vcpu *vcpu)
5135{
5136 unsigned after_mxcsr_mask;
5137
5138 /* Initialize guest FPU by resetting ours and saving into guest's */
5139 preempt_disable();
d6e88aec
AK		 5140 kvm_fx_finit();
5141 kvm_fx_save(&vcpu->arch.guest_fx_image);
d0752060
HB		 5142 preempt_enable();
5143
ad312c7c 5144 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5145 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5146 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5147 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5148 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5149}
5150EXPORT_SYMBOL_GPL(fx_init);
5151
5152void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5153{
2608d7a1 5154 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5155 return;
5156
5157 vcpu->guest_fpu_loaded = 1;
7cf30855 5158 unlazy_fpu(current);
d6e88aec 5159 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5160 trace_kvm_fpu(1);
d0752060 5161}
d0752060
HB		 5162
5163void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5164{
5165 if (!vcpu->guest_fpu_loaded)
5166 return;
5167
5168 vcpu->guest_fpu_loaded = 0;
d6e88aec 5169 kvm_fx_save(&vcpu->arch.guest_fx_image);
f096ed85 5170 ++vcpu->stat.fpu_reload;
02daab21 5171 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5172 trace_kvm_fpu(0);
d0752060 5173}
e9b11c17
ZX		 5174
5175void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5176{
7f1ea208
JR		 5177 if (vcpu->arch.time_page) {
5178 kvm_release_page_dirty(vcpu->arch.time_page);
5179 vcpu->arch.time_page = NULL;
5180 }
5181
e9b11c17
ZX		 5182 kvm_x86_ops->vcpu_free(vcpu);
5183}
5184
5185struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5186 unsigned int id)
5187{
26e5215f
AK		 5188 return kvm_x86_ops->vcpu_create(kvm, id);
5189}
e9b11c17 5190
26e5215f
AK		 5191int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5192{
5193 int r;
e9b11c17 5194
0bed3b56 5195 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5196 vcpu_load(vcpu);
5197 r = kvm_arch_vcpu_reset(vcpu);
5198 if (r == 0)
5199 r = kvm_mmu_setup(vcpu);
5200 vcpu_put(vcpu);
5201 if (r < 0)
5202 goto free_vcpu;
5203
26e5215f 5204 return 0;
e9b11c17
ZX		 5205free_vcpu:
5206 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5207 return r;
e9b11c17
ZX		 5208}
5209
d40ccc62 5210void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5211{
5212 vcpu_load(vcpu);
5213 kvm_mmu_unload(vcpu);
5214 vcpu_put(vcpu);
5215
5216 kvm_x86_ops->vcpu_free(vcpu);
5217}
5218
5219int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5220{
448fa4a9
JK		 5221 vcpu->arch.nmi_pending = false;
5222 vcpu->arch.nmi_injected = false;
5223
42dbaa5a
JK		 5224 vcpu->arch.switch_db_regs = 0;
5225 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5226 vcpu->arch.dr6 = DR6_FIXED_1;
5227 vcpu->arch.dr7 = DR7_FIXED_1;
5228
e9b11c17
ZX		 5229 return kvm_x86_ops->vcpu_reset(vcpu);
5230}
5231
10474ae8 5232int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5233{
0cca7907
ZA		 5234 /*
5235 * Since this may be called from a hotplug notifcation,
5236 * we can't get the CPU frequency directly.
5237 */
5238 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5239 int cpu = raw_smp_processor_id();
5240 per_cpu(cpu_tsc_khz, cpu) = 0;
5241 }
18863bdd
AK		 5242
5243 kvm_shared_msr_cpu_online();
5244
10474ae8 5245 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5246}
5247
5248void kvm_arch_hardware_disable(void *garbage)
5249{
5250 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5251 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5252}
5253
5254int kvm_arch_hardware_setup(void)
5255{
5256 return kvm_x86_ops->hardware_setup();
5257}
5258
5259void kvm_arch_hardware_unsetup(void)
5260{
5261 kvm_x86_ops->hardware_unsetup();
5262}
5263
5264void kvm_arch_check_processor_compat(void *rtn)
5265{
5266 kvm_x86_ops->check_processor_compatibility(rtn);
5267}
5268
5269int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5270{
5271 struct page *page;
5272 struct kvm *kvm;
5273 int r;
5274
5275 BUG_ON(vcpu->kvm == NULL);
5276 kvm = vcpu->kvm;
5277
ad312c7c 5278 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5279 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5280 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5281 else
a4535290 5282 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5283
5284 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5285 if (!page) {
5286 r = -ENOMEM;
5287 goto fail;
5288 }
ad312c7c 5289 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5290
5291 r = kvm_mmu_create(vcpu);
5292 if (r < 0)
5293 goto fail_free_pio_data;
5294
5295 if (irqchip_in_kernel(kvm)) {
5296 r = kvm_create_lapic(vcpu);
5297 if (r < 0)
5298 goto fail_mmu_destroy;
5299 }
5300
890ca9ae
HY		 5301 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5302 GFP_KERNEL);
5303 if (!vcpu->arch.mce_banks) {
5304 r = -ENOMEM;
443c39bc 5305 goto fail_free_lapic;
890ca9ae
HY		 5306 }
5307 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5308
e9b11c17 5309 return 0;
443c39bc
WY		 5310fail_free_lapic:
5311 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5312fail_mmu_destroy:
5313 kvm_mmu_destroy(vcpu);
5314fail_free_pio_data:
ad312c7c 5315 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5316fail:
5317 return r;
5318}
5319
5320void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5321{
f656ce01
MT		 5322 int idx;
5323
36cb93fd 5324 kfree(vcpu->arch.mce_banks);
e9b11c17 5325 kvm_free_lapic(vcpu);
f656ce01 5326 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5327 kvm_mmu_destroy(vcpu);
f656ce01 5328 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5329 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5330}
d19a9cd2
ZX		 5331
5332struct kvm *kvm_arch_create_vm(void)
5333{
5334 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5335
5336 if (!kvm)
5337 return ERR_PTR(-ENOMEM);
5338
fef9cce0
MT		 5339 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5340 if (!kvm->arch.aliases) {
5341 kfree(kvm);
5342 return ERR_PTR(-ENOMEM);
5343 }
5344
f05e70ac 5345 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5346 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5347
5550af4d
SY		 5348 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5349 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5350
53f658b3
MT		 5351 rdtscll(kvm->arch.vm_init_tsc);
5352
d19a9cd2
ZX		 5353 return kvm;
5354}
5355
5356static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5357{
5358 vcpu_load(vcpu);
5359 kvm_mmu_unload(vcpu);
5360 vcpu_put(vcpu);
5361}
5362
5363static void kvm_free_vcpus(struct kvm *kvm)
5364{
5365 unsigned int i;
988a2cae 5366 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5367
5368 /*
5369 * Unpin any mmu pages first.
5370 */
988a2cae
GN		 5371 kvm_for_each_vcpu(i, vcpu, kvm)
5372 kvm_unload_vcpu_mmu(vcpu);
5373 kvm_for_each_vcpu(i, vcpu, kvm)
5374 kvm_arch_vcpu_free(vcpu);
5375
5376 mutex_lock(&kvm->lock);
5377 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5378 kvm->vcpus[i] = NULL;
d19a9cd2 5379
988a2cae
GN		 5380 atomic_set(&kvm->online_vcpus, 0);
5381 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5382}
5383
ad8ba2cd
SY		 5384void kvm_arch_sync_events(struct kvm *kvm)
5385{
ba4cef31 5386 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5387}
5388
d19a9cd2
ZX		 5389void kvm_arch_destroy_vm(struct kvm *kvm)
5390{
6eb55818 5391 kvm_iommu_unmap_guest(kvm);
7837699f 5392 kvm_free_pit(kvm);
d7deeeb0
ZX		 5393 kfree(kvm->arch.vpic);
5394 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5395 kvm_free_vcpus(kvm);
5396 kvm_free_physmem(kvm);
3d45830c
AK		 5397 if (kvm->arch.apic_access_page)
5398 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5399 if (kvm->arch.ept_identity_pagetable)
5400 put_page(kvm->arch.ept_identity_pagetable);
64749204 5401 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5402 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5403 kfree(kvm);
5404}
0de10343 5405
f7784b8e
MT		 5406int kvm_arch_prepare_memory_region(struct kvm *kvm,
5407 struct kvm_memory_slot *memslot,
0de10343 5408 struct kvm_memory_slot old,
f7784b8e 5409 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5410 int user_alloc)
5411{
f7784b8e 5412 int npages = memslot->npages;
0de10343
ZX		 5413
5414 /*To keep backward compatibility with older userspace,
5415 *x86 needs to hanlde !user_alloc case.
5416 */
5417 if (!user_alloc) {
5418 if (npages && !old.rmap) {
604b38ac
AA		 5419 unsigned long userspace_addr;
5420
72dc67a6 5421 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5422 userspace_addr = do_mmap(NULL, 0,
5423 npages * PAGE_SIZE,
5424 PROT_READ | PROT_WRITE,
acee3c04 5425 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5426 0);
72dc67a6 5427 up_write(&current->mm->mmap_sem);
0de10343 5428
604b38ac
AA		 5429 if (IS_ERR((void *)userspace_addr))
5430 return PTR_ERR((void *)userspace_addr);
5431
604b38ac 5432 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5433 }
5434 }
5435
f7784b8e
MT		 5436
5437 return 0;
5438}
5439
5440void kvm_arch_commit_memory_region(struct kvm *kvm,
5441 struct kvm_userspace_memory_region *mem,
5442 struct kvm_memory_slot old,
5443 int user_alloc)
5444{
5445
5446 int npages = mem->memory_size >> PAGE_SHIFT;
5447
5448 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5449 int ret;
5450
5451 down_write(&current->mm->mmap_sem);
5452 ret = do_munmap(current->mm, old.userspace_addr,
5453 old.npages * PAGE_SIZE);
5454 up_write(&current->mm->mmap_sem);
5455 if (ret < 0)
5456 printk(KERN_WARNING
5457 "kvm_vm_ioctl_set_memory_region: "
5458 "failed to munmap memory\n");
5459 }
5460
7c8a83b7 5461 spin_lock(&kvm->mmu_lock);
f05e70ac 5462 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5463 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5464 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5465 }
5466
5467 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5468 spin_unlock(&kvm->mmu_lock);
0de10343 5469}
1d737c8a 5470
34d4cb8f
MT		 5471void kvm_arch_flush_shadow(struct kvm *kvm)
5472{
5473 kvm_mmu_zap_all(kvm);
8986ecc0 5474 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5475}
5476
1d737c8a
ZX		 5477int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5478{
a4535290 5479 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5480 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5481 || vcpu->arch.nmi_pending ||
5482 (kvm_arch_interrupt_allowed(vcpu) &&
5483 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5484}
5736199a 5485
5736199a
ZX		 5486void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5487{
32f88400
MT		 5488 int me;
5489 int cpu = vcpu->cpu;
5736199a
ZX		 5490
5491 if (waitqueue_active(&vcpu->wq)) {
5492 wake_up_interruptible(&vcpu->wq);
5493 ++vcpu->stat.halt_wakeup;
5494 }
32f88400
MT		 5495
5496 me = get_cpu();
5497 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5498 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5499 smp_send_reschedule(cpu);
e9571ed5 5500 put_cpu();
5736199a 5501}
78646121
GN		 5502
5503int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5504{
5505 return kvm_x86_ops->interrupt_allowed(vcpu);
5506}
229456fc 5507
f92653ee
JK		 5508bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5509{
5510 unsigned long current_rip = kvm_rip_read(vcpu) +
5511 get_segment_base(vcpu, VCPU_SREG_CS);
5512
5513 return current_rip == linear_rip;
5514}
5515EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5516
94fe45da
JK		 5517unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5518{
5519 unsigned long rflags;
5520
5521 rflags = kvm_x86_ops->get_rflags(vcpu);
5522 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5523 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5524 return rflags;
5525}
5526EXPORT_SYMBOL_GPL(kvm_get_rflags);
5527
5528void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5529{
5530 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5531 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5532 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5533 kvm_x86_ops->set_rflags(vcpu, rflags);
5534}
5535EXPORT_SYMBOL_GPL(kvm_set_rflags);
5536
229456fc
MT		 5537EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5538EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5539EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5540EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5541EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5542EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5543EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5544EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5545EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5546EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5547EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5548EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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