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x86: kvm: rate-limit global clock updates
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
afcbf13f 655 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 656 return 1;
657
a03490ed 658 if (is_long_mode(vcpu)) {
0f12244f
GN		 659 if (!(cr4 & X86_CR4_PAE))
660 return 1;
a2edf57f
AK		 661 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
662 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 663 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
664 kvm_read_cr3(vcpu)))
0f12244f
GN		 665 return 1;
666
ad756a16
MJ		 667 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
668 if (!guest_cpuid_has_pcid(vcpu))
669 return 1;
670
671 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
672 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
673 return 1;
674 }
675
5e1746d6 676 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 677 return 1;
a03490ed 678
ad756a16
MJ		 679 if (((cr4 ^ old_cr4) & pdptr_bits) ||
680 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 681 kvm_mmu_reset_context(vcpu);
0f12244f 682
2acf923e 683 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 684 kvm_update_cpuid(vcpu);
2acf923e 685
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 689
2390218b 690int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 691{
9f8fe504 692 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 693 kvm_mmu_sync_roots(vcpu);
d835dfec 694 kvm_mmu_flush_tlb(vcpu);
0f12244f 695 return 0;
d835dfec
AK		 696 }
697
a03490ed 698 if (is_long_mode(vcpu)) {
471842ec 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 700 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
701 return 1;
702 } else
703 if (cr3 & CR3_L_MODE_RESERVED_BITS)
704 return 1;
a03490ed
CO		 705 } else {
706 if (is_pae(vcpu)) {
0f12244f
GN		 707 if (cr3 & CR3_PAE_RESERVED_BITS)
708 return 1;
ff03a073
JR		 709 if (is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 711 return 1;
a03490ed
CO		 712 }
713 /*
714 * We don't check reserved bits in nonpae mode, because
715 * this isn't enforced, and VMware depends on this.
716 */
717 }
718
0f12244f 719 vcpu->arch.cr3 = cr3;
aff48baa 720 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 721 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 722 return 0;
723}
2d3ad1f4 724EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 725
eea1cff9 726int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 727{
0f12244f
GN		 728 if (cr8 & CR8_RESERVED_BITS)
729 return 1;
a03490ed
CO		 730 if (irqchip_in_kernel(vcpu->kvm))
731 kvm_lapic_set_tpr(vcpu, cr8);
732 else
ad312c7c 733 vcpu->arch.cr8 = cr8;
0f12244f
GN		 734 return 0;
735}
2d3ad1f4 736EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 737
2d3ad1f4 738unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 739{
740 if (irqchip_in_kernel(vcpu->kvm))
741 return kvm_lapic_get_cr8(vcpu);
742 else
ad312c7c 743 return vcpu->arch.cr8;
a03490ed 744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 746
73aaf249
JK		 747static void kvm_update_dr6(struct kvm_vcpu *vcpu)
748{
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
751}
752
c8639010
JK		 753static void kvm_update_dr7(struct kvm_vcpu *vcpu)
754{
755 unsigned long dr7;
756
757 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
758 dr7 = vcpu->arch.guest_debug_dr7;
759 else
760 dr7 = vcpu->arch.dr7;
761 kvm_x86_ops->set_dr7(vcpu, dr7);
762 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
763}
764
338dbc97 765static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 766{
767 switch (dr) {
768 case 0 ... 3:
769 vcpu->arch.db[dr] = val;
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 vcpu->arch.eff_db[dr] = val;
772 break;
773 case 4:
338dbc97
GN		 774 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
775 return 1; /* #UD */
020df079
GN		 776 /* fall through */
777 case 6:
338dbc97
GN		 778 if (val & 0xffffffff00000000ULL)
779 return -1; /* #GP */
020df079 780 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 781 kvm_update_dr6(vcpu);
020df079
GN		 782 break;
783 case 5:
338dbc97
GN		 784 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
785 return 1; /* #UD */
020df079
GN		 786 /* fall through */
787 default: /* 7 */
338dbc97
GN		 788 if (val & 0xffffffff00000000ULL)
789 return -1; /* #GP */
020df079 790 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 791 kvm_update_dr7(vcpu);
020df079
GN		 792 break;
793 }
794
795 return 0;
796}
338dbc97
GN		 797
798int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
799{
800 int res;
801
802 res = __kvm_set_dr(vcpu, dr, val);
803 if (res > 0)
804 kvm_queue_exception(vcpu, UD_VECTOR);
805 else if (res < 0)
806 kvm_inject_gp(vcpu, 0);
807
808 return res;
809}
020df079
GN		 810EXPORT_SYMBOL_GPL(kvm_set_dr);
811
338dbc97 812static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 813{
814 switch (dr) {
815 case 0 ... 3:
816 *val = vcpu->arch.db[dr];
817 break;
818 case 4:
338dbc97 819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 820 return 1;
020df079
GN		 821 /* fall through */
822 case 6:
73aaf249
JK		 823 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
824 *val = vcpu->arch.dr6;
825 else
826 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 827 break;
828 case 5:
338dbc97 829 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 830 return 1;
020df079
GN		 831 /* fall through */
832 default: /* 7 */
833 *val = vcpu->arch.dr7;
834 break;
835 }
836
837 return 0;
838}
338dbc97
GN		 839
840int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
841{
842 if (_kvm_get_dr(vcpu, dr, val)) {
843 kvm_queue_exception(vcpu, UD_VECTOR);
844 return 1;
845 }
846 return 0;
847}
020df079
GN		 848EXPORT_SYMBOL_GPL(kvm_get_dr);
849
022cd0e8
AK		 850bool kvm_rdpmc(struct kvm_vcpu *vcpu)
851{
852 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
853 u64 data;
854 int err;
855
856 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
857 if (err)
858 return err;
859 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
860 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
861 return err;
862}
863EXPORT_SYMBOL_GPL(kvm_rdpmc);
864
043405e1
CO		 865/*
866 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
867 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
868 *
869 * This list is modified at module load time to reflect the
e3267cbb
GC		 870 * capabilities of the host cpu. This capabilities test skips MSRs that are
871 * kvm-specific. Those are put in the beginning of the list.
043405e1 872 */
e3267cbb 873
e984097b 874#define KVM_SAVE_MSRS_BEGIN 12
043405e1 875static u32 msrs_to_save[] = {
e3267cbb 876 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 877 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 878 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 879 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 880 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 881 MSR_KVM_PV_EOI_EN,
043405e1 882 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 883 MSR_STAR,
043405e1
CO		 884#ifdef CONFIG_X86_64
885 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
886#endif
b3897a49 887 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 888 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 889};
890
891static unsigned num_msrs_to_save;
892
f1d24831 893static const u32 emulated_msrs[] = {
ba904635 894 MSR_IA32_TSC_ADJUST,
a3e06bbe 895 MSR_IA32_TSCDEADLINE,
043405e1 896 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 897 MSR_IA32_MCG_STATUS,
898 MSR_IA32_MCG_CTL,
043405e1
CO		 899};
900
384bb783 901bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 902{
b69e8cae 903 if (efer & efer_reserved_bits)
384bb783 904 return false;
15c4a640 905
1b2fd70c
AG		 906 if (efer & EFER_FFXSR) {
907 struct kvm_cpuid_entry2 *feat;
908
909 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 910 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 911 return false;
1b2fd70c
AG		 912 }
913
d8017474
AG		 914 if (efer & EFER_SVME) {
915 struct kvm_cpuid_entry2 *feat;
916
917 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 918 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 919 return false;
d8017474
AG		 920 }
921
384bb783
JK		 922 return true;
923}
924EXPORT_SYMBOL_GPL(kvm_valid_efer);
925
926static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
927{
928 u64 old_efer = vcpu->arch.efer;
929
930 if (!kvm_valid_efer(vcpu, efer))
931 return 1;
932
933 if (is_paging(vcpu)
934 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
935 return 1;
936
15c4a640 937 efer &= ~EFER_LMA;
f6801dff 938 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 939
a3d204e2
SY		 940 kvm_x86_ops->set_efer(vcpu, efer);
941
aad82703
SY		 942 /* Update reserved bits */
943 if ((efer ^ old_efer) & EFER_NX)
944 kvm_mmu_reset_context(vcpu);
945
b69e8cae 946 return 0;
15c4a640
CO		 947}
948
f2b4b7dd
JR		 949void kvm_enable_efer_bits(u64 mask)
950{
951 efer_reserved_bits &= ~mask;
952}
953EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
954
955
15c4a640
CO		 956/*
957 * Writes msr value into into the appropriate "register".
958 * Returns 0 on success, non-0 otherwise.
959 * Assumes vcpu_load() was already called.
960 */
8fe8ab46 961int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 962{
8fe8ab46 963 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 964}
965
313a3dc7
CO		 966/*
967 * Adapt set_msr() to msr_io()'s calling convention
968 */
969static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
970{
8fe8ab46
WA		 971 struct msr_data msr;
972
973 msr.data = *data;
974 msr.index = index;
975 msr.host_initiated = true;
976 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 977}
978
16e8d74d
MT		 979#ifdef CONFIG_X86_64
980struct pvclock_gtod_data {
981 seqcount_t seq;
982
983 struct { /* extract of a clocksource struct */
984 int vclock_mode;
985 cycle_t cycle_last;
986 cycle_t mask;
987 u32 mult;
988 u32 shift;
989 } clock;
990
991 /* open coded 'struct timespec' */
992 u64 monotonic_time_snsec;
993 time_t monotonic_time_sec;
994};
995
996static struct pvclock_gtod_data pvclock_gtod_data;
997
998static void update_pvclock_gtod(struct timekeeper *tk)
999{
1000 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1001
1002 write_seqcount_begin(&vdata->seq);
1003
1004 /* copy pvclock gtod data */
1005 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1006 vdata->clock.cycle_last = tk->clock->cycle_last;
1007 vdata->clock.mask = tk->clock->mask;
1008 vdata->clock.mult = tk->mult;
1009 vdata->clock.shift = tk->shift;
1010
1011 vdata->monotonic_time_sec = tk->xtime_sec
1012 + tk->wall_to_monotonic.tv_sec;
1013 vdata->monotonic_time_snsec = tk->xtime_nsec
1014 + (tk->wall_to_monotonic.tv_nsec
1015 << tk->shift);
1016 while (vdata->monotonic_time_snsec >=
1017 (((u64)NSEC_PER_SEC) << tk->shift)) {
1018 vdata->monotonic_time_snsec -=
1019 ((u64)NSEC_PER_SEC) << tk->shift;
1020 vdata->monotonic_time_sec++;
1021 }
1022
1023 write_seqcount_end(&vdata->seq);
1024}
1025#endif
1026
1027
18068523
GOC		 1028static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1029{
9ed3c444
AK		 1030 int version;
1031 int r;
50d0a0f9 1032 struct pvclock_wall_clock wc;
923de3cf 1033 struct timespec boot;
18068523
GOC		 1034
1035 if (!wall_clock)
1036 return;
1037
9ed3c444
AK		 1038 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1039 if (r)
1040 return;
1041
1042 if (version & 1)
1043 ++version; /* first time write, random junk */
1044
1045 ++version;
18068523 1046
18068523
GOC		 1047 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1048
50d0a0f9
GH		 1049 /*
1050 * The guest calculates current wall clock time by adding
34c238a1 1051 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1052 * wall clock specified here. guest system time equals host
1053 * system time for us, thus we must fill in host boot time here.
1054 */
923de3cf 1055 getboottime(&boot);
50d0a0f9 1056
4b648665
BR		 1057 if (kvm->arch.kvmclock_offset) {
1058 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1059 boot = timespec_sub(boot, ts);
1060 }
50d0a0f9
GH		 1061 wc.sec = boot.tv_sec;
1062 wc.nsec = boot.tv_nsec;
1063 wc.version = version;
18068523
GOC		 1064
1065 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1066
1067 version++;
1068 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1069}
1070
50d0a0f9
GH		 1071static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1072{
1073 uint32_t quotient, remainder;
1074
1075 /* Don't try to replace with do_div(), this one calculates
1076 * "(dividend << 32) / divisor" */
1077 __asm__ ( "divl %4"
1078 : "=a" (quotient), "=d" (remainder)
1079 : "0" (0), "1" (dividend), "r" (divisor) );
1080 return quotient;
1081}
1082
5f4e3f88
ZA		 1083static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1084 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1085{
5f4e3f88 1086 uint64_t scaled64;
50d0a0f9
GH		 1087 int32_t shift = 0;
1088 uint64_t tps64;
1089 uint32_t tps32;
1090
5f4e3f88
ZA		 1091 tps64 = base_khz * 1000LL;
1092 scaled64 = scaled_khz * 1000LL;
50933623 1093 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1094 tps64 >>= 1;
1095 shift--;
1096 }
1097
1098 tps32 = (uint32_t)tps64;
50933623
JK		 1099 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1100 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1101 scaled64 >>= 1;
1102 else
1103 tps32 <<= 1;
50d0a0f9
GH		 1104 shift++;
1105 }
1106
5f4e3f88
ZA		 1107 *pshift = shift;
1108 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1109
5f4e3f88
ZA		 1110 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1111 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1112}
1113
759379dd
ZA		 1114static inline u64 get_kernel_ns(void)
1115{
1116 struct timespec ts;
1117
1118 WARN_ON(preemptible());
1119 ktime_get_ts(&ts);
1120 monotonic_to_bootbased(&ts);
1121 return timespec_to_ns(&ts);
50d0a0f9
GH		 1122}
1123
d828199e 1124#ifdef CONFIG_X86_64
16e8d74d 1125static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1126#endif
16e8d74d 1127
c8076604 1128static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1129unsigned long max_tsc_khz;
c8076604 1130
cc578287 1131static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1132{
cc578287
ZA		 1133 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1134 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1135}
1136
cc578287 1137static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1138{
cc578287
ZA		 1139 u64 v = (u64)khz * (1000000 + ppm);
1140 do_div(v, 1000000);
1141 return v;
1e993611
JR		 1142}
1143
cc578287 1144static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1145{
cc578287
ZA		 1146 u32 thresh_lo, thresh_hi;
1147 int use_scaling = 0;
217fc9cf 1148
03ba32ca
MT		 1149 /* tsc_khz can be zero if TSC calibration fails */
1150 if (this_tsc_khz == 0)
1151 return;
1152
c285545f
ZA		 1153 /* Compute a scale to convert nanoseconds in TSC cycles */
1154 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1155 &vcpu->arch.virtual_tsc_shift,
1156 &vcpu->arch.virtual_tsc_mult);
1157 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1158
1159 /*
1160 * Compute the variation in TSC rate which is acceptable
1161 * within the range of tolerance and decide if the
1162 * rate being applied is within that bounds of the hardware
1163 * rate. If so, no scaling or compensation need be done.
1164 */
1165 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1166 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1167 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1168 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1169 use_scaling = 1;
1170 }
1171 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1172}
1173
1174static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1175{
e26101b1 1176 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1177 vcpu->arch.virtual_tsc_mult,
1178 vcpu->arch.virtual_tsc_shift);
e26101b1 1179 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1180 return tsc;
1181}
1182
b48aa97e
MT		 1183void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1184{
1185#ifdef CONFIG_X86_64
1186 bool vcpus_matched;
1187 bool do_request = false;
1188 struct kvm_arch *ka = &vcpu->kvm->arch;
1189 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1190
1191 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1192 atomic_read(&vcpu->kvm->online_vcpus));
1193
1194 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1195 if (!ka->use_master_clock)
1196 do_request = 1;
1197
1198 if (!vcpus_matched && ka->use_master_clock)
1199 do_request = 1;
1200
1201 if (do_request)
1202 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1203
1204 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1205 atomic_read(&vcpu->kvm->online_vcpus),
1206 ka->use_master_clock, gtod->clock.vclock_mode);
1207#endif
1208}
1209
ba904635
WA		 1210static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1211{
1212 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1213 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1214}
1215
8fe8ab46 1216void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1217{
1218 struct kvm *kvm = vcpu->kvm;
f38e098f 1219 u64 offset, ns, elapsed;
99e3e30a 1220 unsigned long flags;
02626b6a 1221 s64 usdiff;
b48aa97e 1222 bool matched;
8fe8ab46 1223 u64 data = msr->data;
99e3e30a 1224
038f8c11 1225 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1226 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1227 ns = get_kernel_ns();
f38e098f 1228 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1229
03ba32ca 1230 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1231 int faulted = 0;
1232
03ba32ca
MT		 1233 /* n.b - signed multiplication and division required */
1234 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1235#ifdef CONFIG_X86_64
03ba32ca 1236 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1237#else
03ba32ca 1238 /* do_div() only does unsigned */
8915aa27
MT		 1239 asm("1: idivl %[divisor]\n"
1240 "2: xor %%edx, %%edx\n"
1241 " movl $0, %[faulted]\n"
1242 "3:\n"
1243 ".section .fixup,\"ax\"\n"
1244 "4: movl $1, %[faulted]\n"
1245 " jmp 3b\n"
1246 ".previous\n"
1247
1248 _ASM_EXTABLE(1b, 4b)
1249
1250 : "=A"(usdiff), [faulted] "=r" (faulted)
1251 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1252
5d3cb0f6 1253#endif
03ba32ca
MT		 1254 do_div(elapsed, 1000);
1255 usdiff -= elapsed;
1256 if (usdiff < 0)
1257 usdiff = -usdiff;
8915aa27
MT		 1258
1259 /* idivl overflow => difference is larger than USEC_PER_SEC */
1260 if (faulted)
1261 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1262 } else
1263 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1264
1265 /*
5d3cb0f6
ZA		 1266 * Special case: TSC write with a small delta (1 second) of virtual
1267 * cycle time against real time is interpreted as an attempt to
1268 * synchronize the CPU.
1269 *
1270 * For a reliable TSC, we can match TSC offsets, and for an unstable
1271 * TSC, we add elapsed time in this computation. We could let the
1272 * compensation code attempt to catch up if we fall behind, but
1273 * it's better to try to match offsets from the beginning.
1274 */
02626b6a 1275 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1276 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1277 if (!check_tsc_unstable()) {
e26101b1 1278 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1279 pr_debug("kvm: matched tsc offset for %llu\n", data);
1280 } else {
857e4099 1281 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1282 data += delta;
1283 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1284 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1285 }
b48aa97e 1286 matched = true;
e26101b1
ZA		 1287 } else {
1288 /*
1289 * We split periods of matched TSC writes into generations.
1290 * For each generation, we track the original measured
1291 * nanosecond time, offset, and write, so if TSCs are in
1292 * sync, we can match exact offset, and if not, we can match
4a969980 1293 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1294 *
1295 * These values are tracked in kvm->arch.cur_xxx variables.
1296 */
1297 kvm->arch.cur_tsc_generation++;
1298 kvm->arch.cur_tsc_nsec = ns;
1299 kvm->arch.cur_tsc_write = data;
1300 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1301 matched = false;
e26101b1
ZA		 1302 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1303 kvm->arch.cur_tsc_generation, data);
f38e098f 1304 }
e26101b1
ZA		 1305
1306 /*
1307 * We also track th most recent recorded KHZ, write and time to
1308 * allow the matching interval to be extended at each write.
1309 */
f38e098f
ZA		 1310 kvm->arch.last_tsc_nsec = ns;
1311 kvm->arch.last_tsc_write = data;
5d3cb0f6 1312 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1313
b183aa58 1314 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1315
1316 /* Keep track of which generation this VCPU has synchronized to */
1317 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1318 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1319 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1320
ba904635
WA		 1321 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1322 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1323 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1324 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1325
1326 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1327 if (matched)
1328 kvm->arch.nr_vcpus_matched_tsc++;
1329 else
1330 kvm->arch.nr_vcpus_matched_tsc = 0;
1331
1332 kvm_track_tsc_matching(vcpu);
1333 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1334}
e26101b1 1335
99e3e30a
ZA		 1336EXPORT_SYMBOL_GPL(kvm_write_tsc);
1337
d828199e
MT		 1338#ifdef CONFIG_X86_64
1339
1340static cycle_t read_tsc(void)
1341{
1342 cycle_t ret;
1343 u64 last;
1344
1345 /*
1346 * Empirically, a fence (of type that depends on the CPU)
1347 * before rdtsc is enough to ensure that rdtsc is ordered
1348 * with respect to loads. The various CPU manuals are unclear
1349 * as to whether rdtsc can be reordered with later loads,
1350 * but no one has ever seen it happen.
1351 */
1352 rdtsc_barrier();
1353 ret = (cycle_t)vget_cycles();
1354
1355 last = pvclock_gtod_data.clock.cycle_last;
1356
1357 if (likely(ret >= last))
1358 return ret;
1359
1360 /*
1361 * GCC likes to generate cmov here, but this branch is extremely
1362 * predictable (it's just a funciton of time and the likely is
1363 * very likely) and there's a data dependence, so force GCC
1364 * to generate a branch instead. I don't barrier() because
1365 * we don't actually need a barrier, and if this function
1366 * ever gets inlined it will generate worse code.
1367 */
1368 asm volatile ("");
1369 return last;
1370}
1371
1372static inline u64 vgettsc(cycle_t *cycle_now)
1373{
1374 long v;
1375 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1376
1377 *cycle_now = read_tsc();
1378
1379 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1380 return v * gtod->clock.mult;
1381}
1382
1383static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1384{
1385 unsigned long seq;
1386 u64 ns;
1387 int mode;
1388 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1389
1390 ts->tv_nsec = 0;
1391 do {
1392 seq = read_seqcount_begin(&gtod->seq);
1393 mode = gtod->clock.vclock_mode;
1394 ts->tv_sec = gtod->monotonic_time_sec;
1395 ns = gtod->monotonic_time_snsec;
1396 ns += vgettsc(cycle_now);
1397 ns >>= gtod->clock.shift;
1398 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1399 timespec_add_ns(ts, ns);
1400
1401 return mode;
1402}
1403
1404/* returns true if host is using tsc clocksource */
1405static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1406{
1407 struct timespec ts;
1408
1409 /* checked again under seqlock below */
1410 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1411 return false;
1412
1413 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1414 return false;
1415
1416 monotonic_to_bootbased(&ts);
1417 *kernel_ns = timespec_to_ns(&ts);
1418
1419 return true;
1420}
1421#endif
1422
1423/*
1424 *
b48aa97e
MT		 1425 * Assuming a stable TSC across physical CPUS, and a stable TSC
1426 * across virtual CPUs, the following condition is possible.
1427 * Each numbered line represents an event visible to both
d828199e
MT		 1428 * CPUs at the next numbered event.
1429 *
1430 * "timespecX" represents host monotonic time. "tscX" represents
1431 * RDTSC value.
1432 *
1433 * VCPU0 on CPU0 | VCPU1 on CPU1
1434 *
1435 * 1. read timespec0,tsc0
1436 * 2. | timespec1 = timespec0 + N
1437 * | tsc1 = tsc0 + M
1438 * 3. transition to guest | transition to guest
1439 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1440 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1441 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1442 *
1443 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1444 *
1445 * - ret0 < ret1
1446 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1447 * ...
1448 * - 0 < N - M => M < N
1449 *
1450 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1451 * always the case (the difference between two distinct xtime instances
1452 * might be smaller then the difference between corresponding TSC reads,
1453 * when updating guest vcpus pvclock areas).
1454 *
1455 * To avoid that problem, do not allow visibility of distinct
1456 * system_timestamp/tsc_timestamp values simultaneously: use a master
1457 * copy of host monotonic time values. Update that master copy
1458 * in lockstep.
1459 *
b48aa97e 1460 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1461 *
1462 */
1463
1464static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1465{
1466#ifdef CONFIG_X86_64
1467 struct kvm_arch *ka = &kvm->arch;
1468 int vclock_mode;
b48aa97e
MT		 1469 bool host_tsc_clocksource, vcpus_matched;
1470
1471 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1472 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1473
1474 /*
1475 * If the host uses TSC clock, then passthrough TSC as stable
1476 * to the guest.
1477 */
b48aa97e 1478 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1479 &ka->master_kernel_ns,
1480 &ka->master_cycle_now);
1481
b48aa97e
MT		 1482 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1483
d828199e
MT		 1484 if (ka->use_master_clock)
1485 atomic_set(&kvm_guest_has_master_clock, 1);
1486
1487 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1488 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1489 vcpus_matched);
d828199e
MT		 1490#endif
1491}
1492
2e762ff7
MT		 1493static void kvm_gen_update_masterclock(struct kvm *kvm)
1494{
1495#ifdef CONFIG_X86_64
1496 int i;
1497 struct kvm_vcpu *vcpu;
1498 struct kvm_arch *ka = &kvm->arch;
1499
1500 spin_lock(&ka->pvclock_gtod_sync_lock);
1501 kvm_make_mclock_inprogress_request(kvm);
1502 /* no guest entries from this point */
1503 pvclock_update_vm_gtod_copy(kvm);
1504
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1507
1508 /* guest entries allowed */
1509 kvm_for_each_vcpu(i, vcpu, kvm)
1510 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1511
1512 spin_unlock(&ka->pvclock_gtod_sync_lock);
1513#endif
1514}
1515
34c238a1 1516static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1517{
d828199e 1518 unsigned long flags, this_tsc_khz;
18068523 1519 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1520 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1521 s64 kernel_ns;
d828199e 1522 u64 tsc_timestamp, host_tsc;
0b79459b 1523 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1524 u8 pvclock_flags;
d828199e
MT		 1525 bool use_master_clock;
1526
1527 kernel_ns = 0;
1528 host_tsc = 0;
18068523 1529
d828199e
MT		 1530 /*
1531 * If the host uses TSC clock, then passthrough TSC as stable
1532 * to the guest.
1533 */
1534 spin_lock(&ka->pvclock_gtod_sync_lock);
1535 use_master_clock = ka->use_master_clock;
1536 if (use_master_clock) {
1537 host_tsc = ka->master_cycle_now;
1538 kernel_ns = ka->master_kernel_ns;
1539 }
1540 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1541
1542 /* Keep irq disabled to prevent changes to the clock */
1543 local_irq_save(flags);
1544 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1545 if (unlikely(this_tsc_khz == 0)) {
1546 local_irq_restore(flags);
1547 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1548 return 1;
1549 }
d828199e
MT		 1550 if (!use_master_clock) {
1551 host_tsc = native_read_tsc();
1552 kernel_ns = get_kernel_ns();
1553 }
1554
1555 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1556
c285545f
ZA		 1557 /*
1558 * We may have to catch up the TSC to match elapsed wall clock
1559 * time for two reasons, even if kvmclock is used.
1560 * 1) CPU could have been running below the maximum TSC rate
1561 * 2) Broken TSC compensation resets the base at each VCPU
1562 * entry to avoid unknown leaps of TSC even when running
1563 * again on the same CPU. This may cause apparent elapsed
1564 * time to disappear, and the guest to stand still or run
1565 * very slowly.
1566 */
1567 if (vcpu->tsc_catchup) {
1568 u64 tsc = compute_guest_tsc(v, kernel_ns);
1569 if (tsc > tsc_timestamp) {
f1e2b260 1570 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1571 tsc_timestamp = tsc;
1572 }
50d0a0f9
GH		 1573 }
1574
18068523
GOC		 1575 local_irq_restore(flags);
1576
0b79459b 1577 if (!vcpu->pv_time_enabled)
c285545f 1578 return 0;
18068523 1579
e48672fa 1580 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1581 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1582 &vcpu->hv_clock.tsc_shift,
1583 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1584 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1585 }
1586
1587 /* With all the info we got, fill in the values */
1d5f066e 1588 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1589 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1590 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1591
18068523
GOC		 1592 /*
1593 * The interface expects us to write an even number signaling that the
1594 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1595 * state, we just increase by 2 at the end.
18068523 1596 */
50d0a0f9 1597 vcpu->hv_clock.version += 2;
18068523 1598
0b79459b
AH		 1599 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1600 &guest_hv_clock, sizeof(guest_hv_clock))))
1601 return 0;
78c0337a
MT		 1602
1603 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1604 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1605
1606 if (vcpu->pvclock_set_guest_stopped_request) {
1607 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1608 vcpu->pvclock_set_guest_stopped_request = false;
1609 }
1610
d828199e
MT		 1611 /* If the host uses TSC clocksource, then it is stable */
1612 if (use_master_clock)
1613 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1614
78c0337a
MT		 1615 vcpu->hv_clock.flags = pvclock_flags;
1616
0b79459b
AH		 1617 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1618 &vcpu->hv_clock,
1619 sizeof(vcpu->hv_clock));
8cfdc000 1620 return 0;
c8076604
GH		 1621}
1622
0061d53d
MT		 1623/*
1624 * kvmclock updates which are isolated to a given vcpu, such as
1625 * vcpu->cpu migration, should not allow system_timestamp from
1626 * the rest of the vcpus to remain static. Otherwise ntp frequency
1627 * correction applies to one vcpu's system_timestamp but not
1628 * the others.
1629 *
1630 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1631 * We need to rate-limit these requests though, as they can
1632 * considerably slow guests that have a large number of vcpus.
1633 * The time for a remote vcpu to update its kvmclock is bound
1634 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1635 */
1636
7e44e449
AJ		 1637#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1638
1639static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1640{
1641 int i;
7e44e449
AJ		 1642 struct delayed_work *dwork = to_delayed_work(work);
1643 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1644 kvmclock_update_work);
1645 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1646 struct kvm_vcpu *vcpu;
1647
1648 kvm_for_each_vcpu(i, vcpu, kvm) {
1649 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1650 kvm_vcpu_kick(vcpu);
1651 }
1652}
1653
7e44e449
AJ		 1654static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1655{
1656 struct kvm *kvm = v->kvm;
1657
1658 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1659 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1660 KVMCLOCK_UPDATE_DELAY);
1661}
1662
9ba075a6
AK		 1663static bool msr_mtrr_valid(unsigned msr)
1664{
1665 switch (msr) {
1666 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1667 case MSR_MTRRfix64K_00000:
1668 case MSR_MTRRfix16K_80000:
1669 case MSR_MTRRfix16K_A0000:
1670 case MSR_MTRRfix4K_C0000:
1671 case MSR_MTRRfix4K_C8000:
1672 case MSR_MTRRfix4K_D0000:
1673 case MSR_MTRRfix4K_D8000:
1674 case MSR_MTRRfix4K_E0000:
1675 case MSR_MTRRfix4K_E8000:
1676 case MSR_MTRRfix4K_F0000:
1677 case MSR_MTRRfix4K_F8000:
1678 case MSR_MTRRdefType:
1679 case MSR_IA32_CR_PAT:
1680 return true;
1681 case 0x2f8:
1682 return true;
1683 }
1684 return false;
1685}
1686
d6289b93
MT		 1687static bool valid_pat_type(unsigned t)
1688{
1689 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1690}
1691
1692static bool valid_mtrr_type(unsigned t)
1693{
1694 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1695}
1696
1697static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1698{
1699 int i;
1700
1701 if (!msr_mtrr_valid(msr))
1702 return false;
1703
1704 if (msr == MSR_IA32_CR_PAT) {
1705 for (i = 0; i < 8; i++)
1706 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1707 return false;
1708 return true;
1709 } else if (msr == MSR_MTRRdefType) {
1710 if (data & ~0xcff)
1711 return false;
1712 return valid_mtrr_type(data & 0xff);
1713 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1714 for (i = 0; i < 8 ; i++)
1715 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1716 return false;
1717 return true;
1718 }
1719
1720 /* variable MTRRs */
1721 return valid_mtrr_type(data & 0xff);
1722}
1723
9ba075a6
AK		 1724static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1725{
0bed3b56
SY		 1726 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1727
d6289b93 1728 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1729 return 1;
1730
0bed3b56
SY		 1731 if (msr == MSR_MTRRdefType) {
1732 vcpu->arch.mtrr_state.def_type = data;
1733 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1734 } else if (msr == MSR_MTRRfix64K_00000)
1735 p[0] = data;
1736 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1737 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1738 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1739 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1740 else if (msr == MSR_IA32_CR_PAT)
1741 vcpu->arch.pat = data;
1742 else { /* Variable MTRRs */
1743 int idx, is_mtrr_mask;
1744 u64 *pt;
1745
1746 idx = (msr - 0x200) / 2;
1747 is_mtrr_mask = msr - 0x200 - 2 * idx;
1748 if (!is_mtrr_mask)
1749 pt =
1750 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1751 else
1752 pt =
1753 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1754 *pt = data;
1755 }
1756
1757 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1758 return 0;
1759}
15c4a640 1760
890ca9ae 1761static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1762{
890ca9ae
HY		 1763 u64 mcg_cap = vcpu->arch.mcg_cap;
1764 unsigned bank_num = mcg_cap & 0xff;
1765
15c4a640 1766 switch (msr) {
15c4a640 1767 case MSR_IA32_MCG_STATUS:
890ca9ae 1768 vcpu->arch.mcg_status = data;
15c4a640 1769 break;
c7ac679c 1770 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1771 if (!(mcg_cap & MCG_CTL_P))
1772 return 1;
1773 if (data != 0 && data != ~(u64)0)
1774 return -1;
1775 vcpu->arch.mcg_ctl = data;
1776 break;
1777 default:
1778 if (msr >= MSR_IA32_MC0_CTL &&
1779 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1780 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1781 /* only 0 or all 1s can be written to IA32_MCi_CTL
1782 * some Linux kernels though clear bit 10 in bank 4 to
1783 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1784 * this to avoid an uncatched #GP in the guest
1785 */
890ca9ae 1786 if ((offset & 0x3) == 0 &&
114be429 1787 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1788 return -1;
1789 vcpu->arch.mce_banks[offset] = data;
1790 break;
1791 }
1792 return 1;
1793 }
1794 return 0;
1795}
1796
ffde22ac
ES		 1797static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1798{
1799 struct kvm *kvm = vcpu->kvm;
1800 int lm = is_long_mode(vcpu);
1801 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1802 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1803 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1804 : kvm->arch.xen_hvm_config.blob_size_32;
1805 u32 page_num = data & ~PAGE_MASK;
1806 u64 page_addr = data & PAGE_MASK;
1807 u8 *page;
1808 int r;
1809
1810 r = -E2BIG;
1811 if (page_num >= blob_size)
1812 goto out;
1813 r = -ENOMEM;
ff5c2c03
SL		 1814 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1815 if (IS_ERR(page)) {
1816 r = PTR_ERR(page);
ffde22ac 1817 goto out;
ff5c2c03 1818 }
ffde22ac
ES		 1819 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1820 goto out_free;
1821 r = 0;
1822out_free:
1823 kfree(page);
1824out:
1825 return r;
1826}
1827
55cd8e5a
GN		 1828static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1829{
1830 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1831}
1832
1833static bool kvm_hv_msr_partition_wide(u32 msr)
1834{
1835 bool r = false;
1836 switch (msr) {
1837 case HV_X64_MSR_GUEST_OS_ID:
1838 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1839 case HV_X64_MSR_REFERENCE_TSC:
1840 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1841 r = true;
1842 break;
1843 }
1844
1845 return r;
1846}
1847
1848static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1849{
1850 struct kvm *kvm = vcpu->kvm;
1851
1852 switch (msr) {
1853 case HV_X64_MSR_GUEST_OS_ID:
1854 kvm->arch.hv_guest_os_id = data;
1855 /* setting guest os id to zero disables hypercall page */
1856 if (!kvm->arch.hv_guest_os_id)
1857 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1858 break;
1859 case HV_X64_MSR_HYPERCALL: {
1860 u64 gfn;
1861 unsigned long addr;
1862 u8 instructions[4];
1863
1864 /* if guest os id is not set hypercall should remain disabled */
1865 if (!kvm->arch.hv_guest_os_id)
1866 break;
1867 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1868 kvm->arch.hv_hypercall = data;
1869 break;
1870 }
1871 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1872 addr = gfn_to_hva(kvm, gfn);
1873 if (kvm_is_error_hva(addr))
1874 return 1;
1875 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1876 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1877 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1878 return 1;
1879 kvm->arch.hv_hypercall = data;
b94b64c9 1880 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1881 break;
1882 }
e984097b
VR		 1883 case HV_X64_MSR_REFERENCE_TSC: {
1884 u64 gfn;
1885 HV_REFERENCE_TSC_PAGE tsc_ref;
1886 memset(&tsc_ref, 0, sizeof(tsc_ref));
1887 kvm->arch.hv_tsc_page = data;
1888 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1889 break;
1890 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1891 if (kvm_write_guest(kvm, data,
1892 &tsc_ref, sizeof(tsc_ref)))
1893 return 1;
1894 mark_page_dirty(kvm, gfn);
1895 break;
1896 }
55cd8e5a 1897 default:
a737f256
CD		 1898 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1899 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1900 return 1;
1901 }
1902 return 0;
1903}
1904
1905static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1906{
10388a07
GN		 1907 switch (msr) {
1908 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1909 u64 gfn;
10388a07 1910 unsigned long addr;
55cd8e5a 1911
10388a07
GN		 1912 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1913 vcpu->arch.hv_vapic = data;
1914 break;
1915 }
b3af1e88
VR		 1916 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1917 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1918 if (kvm_is_error_hva(addr))
1919 return 1;
8b0cedff 1920 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1921 return 1;
1922 vcpu->arch.hv_vapic = data;
b3af1e88 1923 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1924 break;
1925 }
1926 case HV_X64_MSR_EOI:
1927 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1928 case HV_X64_MSR_ICR:
1929 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1930 case HV_X64_MSR_TPR:
1931 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1932 default:
a737f256
CD		 1933 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1934 "data 0x%llx\n", msr, data);
10388a07
GN		 1935 return 1;
1936 }
1937
1938 return 0;
55cd8e5a
GN		 1939}
1940
344d9588
GN		 1941static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1942{
1943 gpa_t gpa = data & ~0x3f;
1944
4a969980 1945 /* Bits 2:5 are reserved, Should be zero */
6adba527 1946 if (data & 0x3c)
344d9588
GN		 1947 return 1;
1948
1949 vcpu->arch.apf.msr_val = data;
1950
1951 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1952 kvm_clear_async_pf_completion_queue(vcpu);
1953 kvm_async_pf_hash_reset(vcpu);
1954 return 0;
1955 }
1956
8f964525
AH		 1957 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1958 sizeof(u32)))
344d9588
GN		 1959 return 1;
1960
6adba527 1961 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1962 kvm_async_pf_wakeup_all(vcpu);
1963 return 0;
1964}
1965
12f9a48f
GC		 1966static void kvmclock_reset(struct kvm_vcpu *vcpu)
1967{
0b79459b 1968 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1969}
1970
c9aaa895
GC		 1971static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1972{
1973 u64 delta;
1974
1975 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1976 return;
1977
1978 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1979 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1980 vcpu->arch.st.accum_steal = delta;
1981}
1982
1983static void record_steal_time(struct kvm_vcpu *vcpu)
1984{
1985 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1986 return;
1987
1988 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1989 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1990 return;
1991
1992 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1993 vcpu->arch.st.steal.version += 2;
1994 vcpu->arch.st.accum_steal = 0;
1995
1996 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1997 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1998}
1999
8fe8ab46 2000int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2001{
5753785f 2002 bool pr = false;
8fe8ab46
WA		 2003 u32 msr = msr_info->index;
2004 u64 data = msr_info->data;
5753785f 2005
15c4a640 2006 switch (msr) {
2e32b719
BP		 2007 case MSR_AMD64_NB_CFG:
2008 case MSR_IA32_UCODE_REV:
2009 case MSR_IA32_UCODE_WRITE:
2010 case MSR_VM_HSAVE_PA:
2011 case MSR_AMD64_PATCH_LOADER:
2012 case MSR_AMD64_BU_CFG2:
2013 break;
2014
15c4a640 2015 case MSR_EFER:
b69e8cae 2016 return set_efer(vcpu, data);
8f1589d9
AP		 2017 case MSR_K7_HWCR:
2018 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2019 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2020 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2021 if (data != 0) {
a737f256
CD		 2022 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2023 data);
8f1589d9
AP		 2024 return 1;
2025 }
15c4a640 2026 break;
f7c6d140
AP		 2027 case MSR_FAM10H_MMIO_CONF_BASE:
2028 if (data != 0) {
a737f256
CD		 2029 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2030 "0x%llx\n", data);
f7c6d140
AP		 2031 return 1;
2032 }
15c4a640 2033 break;
b5e2fec0
AG		 2034 case MSR_IA32_DEBUGCTLMSR:
2035 if (!data) {
2036 /* We support the non-activated case already */
2037 break;
2038 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2039 /* Values other than LBR and BTF are vendor-specific,
2040 thus reserved and should throw a #GP */
2041 return 1;
2042 }
a737f256
CD		 2043 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2044 __func__, data);
b5e2fec0 2045 break;
9ba075a6
AK		 2046 case 0x200 ... 0x2ff:
2047 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2048 case MSR_IA32_APICBASE:
58cb628d 2049 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2050 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2051 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2052 case MSR_IA32_TSCDEADLINE:
2053 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2054 break;
ba904635
WA		 2055 case MSR_IA32_TSC_ADJUST:
2056 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2057 if (!msr_info->host_initiated) {
2058 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2059 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2060 }
2061 vcpu->arch.ia32_tsc_adjust_msr = data;
2062 }
2063 break;
15c4a640 2064 case MSR_IA32_MISC_ENABLE:
ad312c7c 2065 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2066 break;
11c6bffa 2067 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2068 case MSR_KVM_WALL_CLOCK:
2069 vcpu->kvm->arch.wall_clock = data;
2070 kvm_write_wall_clock(vcpu->kvm, data);
2071 break;
11c6bffa 2072 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2073 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2074 u64 gpa_offset;
12f9a48f 2075 kvmclock_reset(vcpu);
18068523
GOC		 2076
2077 vcpu->arch.time = data;
0061d53d 2078 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2079
2080 /* we verify if the enable bit is set... */
2081 if (!(data & 1))
2082 break;
2083
0b79459b 2084 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2085
0b79459b 2086 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2087 &vcpu->arch.pv_time, data & ~1ULL,
2088 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2089 vcpu->arch.pv_time_enabled = false;
2090 else
2091 vcpu->arch.pv_time_enabled = true;
32cad84f 2092
18068523
GOC		 2093 break;
2094 }
344d9588
GN		 2095 case MSR_KVM_ASYNC_PF_EN:
2096 if (kvm_pv_enable_async_pf(vcpu, data))
2097 return 1;
2098 break;
c9aaa895
GC		 2099 case MSR_KVM_STEAL_TIME:
2100
2101 if (unlikely(!sched_info_on()))
2102 return 1;
2103
2104 if (data & KVM_STEAL_RESERVED_MASK)
2105 return 1;
2106
2107 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2108 data & KVM_STEAL_VALID_BITS,
2109 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2110 return 1;
2111
2112 vcpu->arch.st.msr_val = data;
2113
2114 if (!(data & KVM_MSR_ENABLED))
2115 break;
2116
2117 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2118
2119 preempt_disable();
2120 accumulate_steal_time(vcpu);
2121 preempt_enable();
2122
2123 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2124
2125 break;
ae7a2a3f
MT		 2126 case MSR_KVM_PV_EOI_EN:
2127 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2128 return 1;
2129 break;
c9aaa895 2130
890ca9ae
HY		 2131 case MSR_IA32_MCG_CTL:
2132 case MSR_IA32_MCG_STATUS:
2133 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2134 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2135
2136 /* Performance counters are not protected by a CPUID bit,
2137 * so we should check all of them in the generic path for the sake of
2138 * cross vendor migration.
2139 * Writing a zero into the event select MSRs disables them,
2140 * which we perfectly emulate ;-). Any other value should be at least
2141 * reported, some guests depend on them.
2142 */
71db6023
AP		 2143 case MSR_K7_EVNTSEL0:
2144 case MSR_K7_EVNTSEL1:
2145 case MSR_K7_EVNTSEL2:
2146 case MSR_K7_EVNTSEL3:
2147 if (data != 0)
a737f256
CD		 2148 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2149 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2150 break;
2151 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2152 * so we ignore writes to make it happy.
2153 */
71db6023
AP		 2154 case MSR_K7_PERFCTR0:
2155 case MSR_K7_PERFCTR1:
2156 case MSR_K7_PERFCTR2:
2157 case MSR_K7_PERFCTR3:
a737f256
CD		 2158 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2159 "0x%x data 0x%llx\n", msr, data);
71db6023 2160 break;
5753785f
GN		 2161 case MSR_P6_PERFCTR0:
2162 case MSR_P6_PERFCTR1:
2163 pr = true;
2164 case MSR_P6_EVNTSEL0:
2165 case MSR_P6_EVNTSEL1:
2166 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2167 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2168
2169 if (pr || data != 0)
a737f256
CD		 2170 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2171 "0x%x data 0x%llx\n", msr, data);
5753785f 2172 break;
84e0cefa
JS		 2173 case MSR_K7_CLK_CTL:
2174 /*
2175 * Ignore all writes to this no longer documented MSR.
2176 * Writes are only relevant for old K7 processors,
2177 * all pre-dating SVM, but a recommended workaround from
4a969980 2178 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2179 * affected processor models on the command line, hence
2180 * the need to ignore the workaround.
2181 */
2182 break;
55cd8e5a
GN		 2183 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2184 if (kvm_hv_msr_partition_wide(msr)) {
2185 int r;
2186 mutex_lock(&vcpu->kvm->lock);
2187 r = set_msr_hyperv_pw(vcpu, msr, data);
2188 mutex_unlock(&vcpu->kvm->lock);
2189 return r;
2190 } else
2191 return set_msr_hyperv(vcpu, msr, data);
2192 break;
91c9c3ed 2193 case MSR_IA32_BBL_CR_CTL3:
2194 /* Drop writes to this legacy MSR -- see rdmsr
2195 * counterpart for further detail.
2196 */
a737f256 2197 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2198 break;
2b036c6b
BO		 2199 case MSR_AMD64_OSVW_ID_LENGTH:
2200 if (!guest_cpuid_has_osvw(vcpu))
2201 return 1;
2202 vcpu->arch.osvw.length = data;
2203 break;
2204 case MSR_AMD64_OSVW_STATUS:
2205 if (!guest_cpuid_has_osvw(vcpu))
2206 return 1;
2207 vcpu->arch.osvw.status = data;
2208 break;
15c4a640 2209 default:
ffde22ac
ES		 2210 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2211 return xen_hvm_config(vcpu, data);
f5132b01 2212 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2213 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2214 if (!ignore_msrs) {
a737f256
CD		 2215 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2216 msr, data);
ed85c068
AP		 2217 return 1;
2218 } else {
a737f256
CD		 2219 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2220 msr, data);
ed85c068
AP		 2221 break;
2222 }
15c4a640
CO		 2223 }
2224 return 0;
2225}
2226EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2227
2228
2229/*
2230 * Reads an msr value (of 'msr_index') into 'pdata'.
2231 * Returns 0 on success, non-0 otherwise.
2232 * Assumes vcpu_load() was already called.
2233 */
2234int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2235{
2236 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2237}
2238
9ba075a6
AK		 2239static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2240{
0bed3b56
SY		 2241 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2242
9ba075a6
AK		 2243 if (!msr_mtrr_valid(msr))
2244 return 1;
2245
0bed3b56
SY		 2246 if (msr == MSR_MTRRdefType)
2247 *pdata = vcpu->arch.mtrr_state.def_type +
2248 (vcpu->arch.mtrr_state.enabled << 10);
2249 else if (msr == MSR_MTRRfix64K_00000)
2250 *pdata = p[0];
2251 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2252 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2253 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2254 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2255 else if (msr == MSR_IA32_CR_PAT)
2256 *pdata = vcpu->arch.pat;
2257 else { /* Variable MTRRs */
2258 int idx, is_mtrr_mask;
2259 u64 *pt;
2260
2261 idx = (msr - 0x200) / 2;
2262 is_mtrr_mask = msr - 0x200 - 2 * idx;
2263 if (!is_mtrr_mask)
2264 pt =
2265 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2266 else
2267 pt =
2268 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2269 *pdata = *pt;
2270 }
2271
9ba075a6
AK		 2272 return 0;
2273}
2274
890ca9ae 2275static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2276{
2277 u64 data;
890ca9ae
HY		 2278 u64 mcg_cap = vcpu->arch.mcg_cap;
2279 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2280
2281 switch (msr) {
15c4a640
CO		 2282 case MSR_IA32_P5_MC_ADDR:
2283 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2284 data = 0;
2285 break;
15c4a640 2286 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2287 data = vcpu->arch.mcg_cap;
2288 break;
c7ac679c 2289 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2290 if (!(mcg_cap & MCG_CTL_P))
2291 return 1;
2292 data = vcpu->arch.mcg_ctl;
2293 break;
2294 case MSR_IA32_MCG_STATUS:
2295 data = vcpu->arch.mcg_status;
2296 break;
2297 default:
2298 if (msr >= MSR_IA32_MC0_CTL &&
2299 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2300 u32 offset = msr - MSR_IA32_MC0_CTL;
2301 data = vcpu->arch.mce_banks[offset];
2302 break;
2303 }
2304 return 1;
2305 }
2306 *pdata = data;
2307 return 0;
2308}
2309
55cd8e5a
GN		 2310static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2311{
2312 u64 data = 0;
2313 struct kvm *kvm = vcpu->kvm;
2314
2315 switch (msr) {
2316 case HV_X64_MSR_GUEST_OS_ID:
2317 data = kvm->arch.hv_guest_os_id;
2318 break;
2319 case HV_X64_MSR_HYPERCALL:
2320 data = kvm->arch.hv_hypercall;
2321 break;
e984097b
VR		 2322 case HV_X64_MSR_TIME_REF_COUNT: {
2323 data =
2324 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2325 break;
2326 }
2327 case HV_X64_MSR_REFERENCE_TSC:
2328 data = kvm->arch.hv_tsc_page;
2329 break;
55cd8e5a 2330 default:
a737f256 2331 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2332 return 1;
2333 }
2334
2335 *pdata = data;
2336 return 0;
2337}
2338
2339static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2340{
2341 u64 data = 0;
2342
2343 switch (msr) {
2344 case HV_X64_MSR_VP_INDEX: {
2345 int r;
2346 struct kvm_vcpu *v;
684851a1
TY		 2347 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2348 if (v == vcpu) {
55cd8e5a 2349 data = r;
684851a1
TY		 2350 break;
2351 }
2352 }
55cd8e5a
GN		 2353 break;
2354 }
10388a07
GN		 2355 case HV_X64_MSR_EOI:
2356 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2357 case HV_X64_MSR_ICR:
2358 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2359 case HV_X64_MSR_TPR:
2360 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2361 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2362 data = vcpu->arch.hv_vapic;
2363 break;
55cd8e5a 2364 default:
a737f256 2365 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2366 return 1;
2367 }
2368 *pdata = data;
2369 return 0;
2370}
2371
890ca9ae
HY		 2372int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2373{
2374 u64 data;
2375
2376 switch (msr) {
890ca9ae 2377 case MSR_IA32_PLATFORM_ID:
15c4a640 2378 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2379 case MSR_IA32_DEBUGCTLMSR:
2380 case MSR_IA32_LASTBRANCHFROMIP:
2381 case MSR_IA32_LASTBRANCHTOIP:
2382 case MSR_IA32_LASTINTFROMIP:
2383 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2384 case MSR_K8_SYSCFG:
2385 case MSR_K7_HWCR:
61a6bd67 2386 case MSR_VM_HSAVE_PA:
9e699624 2387 case MSR_K7_EVNTSEL0:
1f3ee616 2388 case MSR_K7_PERFCTR0:
1fdbd48c 2389 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2390 case MSR_AMD64_NB_CFG:
f7c6d140 2391 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2392 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2393 data = 0;
2394 break;
5753785f
GN		 2395 case MSR_P6_PERFCTR0:
2396 case MSR_P6_PERFCTR1:
2397 case MSR_P6_EVNTSEL0:
2398 case MSR_P6_EVNTSEL1:
2399 if (kvm_pmu_msr(vcpu, msr))
2400 return kvm_pmu_get_msr(vcpu, msr, pdata);
2401 data = 0;
2402 break;
742bc670
MT		 2403 case MSR_IA32_UCODE_REV:
2404 data = 0x100000000ULL;
2405 break;
9ba075a6
AK		 2406 case MSR_MTRRcap:
2407 data = 0x500 | KVM_NR_VAR_MTRR;
2408 break;
2409 case 0x200 ... 0x2ff:
2410 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2411 case 0xcd: /* fsb frequency */
2412 data = 3;
2413 break;
7b914098
JS		 2414 /*
2415 * MSR_EBC_FREQUENCY_ID
2416 * Conservative value valid for even the basic CPU models.
2417 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2418 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2419 * and 266MHz for model 3, or 4. Set Core Clock
2420 * Frequency to System Bus Frequency Ratio to 1 (bits
2421 * 31:24) even though these are only valid for CPU
2422 * models > 2, however guests may end up dividing or
2423 * multiplying by zero otherwise.
2424 */
2425 case MSR_EBC_FREQUENCY_ID:
2426 data = 1 << 24;
2427 break;
15c4a640
CO		 2428 case MSR_IA32_APICBASE:
2429 data = kvm_get_apic_base(vcpu);
2430 break;
0105d1a5
GN		 2431 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2432 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2433 break;
a3e06bbe
LJ		 2434 case MSR_IA32_TSCDEADLINE:
2435 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2436 break;
ba904635
WA		 2437 case MSR_IA32_TSC_ADJUST:
2438 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2439 break;
15c4a640 2440 case MSR_IA32_MISC_ENABLE:
ad312c7c 2441 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2442 break;
847f0ad8
AG		 2443 case MSR_IA32_PERF_STATUS:
2444 /* TSC increment by tick */
2445 data = 1000ULL;
2446 /* CPU multiplier */
2447 data |= (((uint64_t)4ULL) << 40);
2448 break;
15c4a640 2449 case MSR_EFER:
f6801dff 2450 data = vcpu->arch.efer;
15c4a640 2451 break;
18068523 2452 case MSR_KVM_WALL_CLOCK:
11c6bffa 2453 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2454 data = vcpu->kvm->arch.wall_clock;
2455 break;
2456 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2457 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2458 data = vcpu->arch.time;
2459 break;
344d9588
GN		 2460 case MSR_KVM_ASYNC_PF_EN:
2461 data = vcpu->arch.apf.msr_val;
2462 break;
c9aaa895
GC		 2463 case MSR_KVM_STEAL_TIME:
2464 data = vcpu->arch.st.msr_val;
2465 break;
1d92128f
MT		 2466 case MSR_KVM_PV_EOI_EN:
2467 data = vcpu->arch.pv_eoi.msr_val;
2468 break;
890ca9ae
HY		 2469 case MSR_IA32_P5_MC_ADDR:
2470 case MSR_IA32_P5_MC_TYPE:
2471 case MSR_IA32_MCG_CAP:
2472 case MSR_IA32_MCG_CTL:
2473 case MSR_IA32_MCG_STATUS:
2474 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2475 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2476 case MSR_K7_CLK_CTL:
2477 /*
2478 * Provide expected ramp-up count for K7. All other
2479 * are set to zero, indicating minimum divisors for
2480 * every field.
2481 *
2482 * This prevents guest kernels on AMD host with CPU
2483 * type 6, model 8 and higher from exploding due to
2484 * the rdmsr failing.
2485 */
2486 data = 0x20000000;
2487 break;
55cd8e5a
GN		 2488 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2489 if (kvm_hv_msr_partition_wide(msr)) {
2490 int r;
2491 mutex_lock(&vcpu->kvm->lock);
2492 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2493 mutex_unlock(&vcpu->kvm->lock);
2494 return r;
2495 } else
2496 return get_msr_hyperv(vcpu, msr, pdata);
2497 break;
91c9c3ed 2498 case MSR_IA32_BBL_CR_CTL3:
2499 /* This legacy MSR exists but isn't fully documented in current
2500 * silicon. It is however accessed by winxp in very narrow
2501 * scenarios where it sets bit #19, itself documented as
2502 * a "reserved" bit. Best effort attempt to source coherent
2503 * read data here should the balance of the register be
2504 * interpreted by the guest:
2505 *
2506 * L2 cache control register 3: 64GB range, 256KB size,
2507 * enabled, latency 0x1, configured
2508 */
2509 data = 0xbe702111;
2510 break;
2b036c6b
BO		 2511 case MSR_AMD64_OSVW_ID_LENGTH:
2512 if (!guest_cpuid_has_osvw(vcpu))
2513 return 1;
2514 data = vcpu->arch.osvw.length;
2515 break;
2516 case MSR_AMD64_OSVW_STATUS:
2517 if (!guest_cpuid_has_osvw(vcpu))
2518 return 1;
2519 data = vcpu->arch.osvw.status;
2520 break;
15c4a640 2521 default:
f5132b01
GN		 2522 if (kvm_pmu_msr(vcpu, msr))
2523 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2524 if (!ignore_msrs) {
a737f256 2525 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2526 return 1;
2527 } else {
a737f256 2528 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2529 data = 0;
2530 }
2531 break;
15c4a640
CO		 2532 }
2533 *pdata = data;
2534 return 0;
2535}
2536EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2537
313a3dc7
CO		 2538/*
2539 * Read or write a bunch of msrs. All parameters are kernel addresses.
2540 *
2541 * @return number of msrs set successfully.
2542 */
2543static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2544 struct kvm_msr_entry *entries,
2545 int (*do_msr)(struct kvm_vcpu *vcpu,
2546 unsigned index, u64 *data))
2547{
f656ce01 2548 int i, idx;
313a3dc7 2549
f656ce01 2550 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2551 for (i = 0; i < msrs->nmsrs; ++i)
2552 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2553 break;
f656ce01 2554 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2555
313a3dc7
CO		 2556 return i;
2557}
2558
2559/*
2560 * Read or write a bunch of msrs. Parameters are user addresses.
2561 *
2562 * @return number of msrs set successfully.
2563 */
2564static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2565 int (*do_msr)(struct kvm_vcpu *vcpu,
2566 unsigned index, u64 *data),
2567 int writeback)
2568{
2569 struct kvm_msrs msrs;
2570 struct kvm_msr_entry *entries;
2571 int r, n;
2572 unsigned size;
2573
2574 r = -EFAULT;
2575 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2576 goto out;
2577
2578 r = -E2BIG;
2579 if (msrs.nmsrs >= MAX_IO_MSRS)
2580 goto out;
2581
313a3dc7 2582 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2583 entries = memdup_user(user_msrs->entries, size);
2584 if (IS_ERR(entries)) {
2585 r = PTR_ERR(entries);
313a3dc7 2586 goto out;
ff5c2c03 2587 }
313a3dc7
CO		 2588
2589 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2590 if (r < 0)
2591 goto out_free;
2592
2593 r = -EFAULT;
2594 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2595 goto out_free;
2596
2597 r = n;
2598
2599out_free:
7a73c028 2600 kfree(entries);
313a3dc7
CO		 2601out:
2602 return r;
2603}
2604
018d00d2
ZX		 2605int kvm_dev_ioctl_check_extension(long ext)
2606{
2607 int r;
2608
2609 switch (ext) {
2610 case KVM_CAP_IRQCHIP:
2611 case KVM_CAP_HLT:
2612 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2613 case KVM_CAP_SET_TSS_ADDR:
07716717 2614 case KVM_CAP_EXT_CPUID:
9c15bb1d 2615 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2616 case KVM_CAP_CLOCKSOURCE:
7837699f 2617 case KVM_CAP_PIT:
a28e4f5a 2618 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2619 case KVM_CAP_MP_STATE:
ed848624 2620 case KVM_CAP_SYNC_MMU:
a355c85c 2621 case KVM_CAP_USER_NMI:
52d939a0 2622 case KVM_CAP_REINJECT_CONTROL:
4925663a 2623 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2624 case KVM_CAP_IRQFD:
d34e6b17 2625 case KVM_CAP_IOEVENTFD:
c5ff41ce 2626 case KVM_CAP_PIT2:
e9f42757 2627 case KVM_CAP_PIT_STATE2:
b927a3ce 2628 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2629 case KVM_CAP_XEN_HVM:
afbcf7ab 2630 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2631 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2632 case KVM_CAP_HYPERV:
10388a07 2633 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2634 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2635 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2636 case KVM_CAP_DEBUGREGS:
d2be1651 2637 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2638 case KVM_CAP_XSAVE:
344d9588 2639 case KVM_CAP_ASYNC_PF:
92a1f12d 2640 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2641 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2642 case KVM_CAP_READONLY_MEM:
5f66b620 2643 case KVM_CAP_HYPERV_TIME:
2a5bab10
AW		 2644#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2645 case KVM_CAP_ASSIGN_DEV_IRQ:
2646 case KVM_CAP_PCI_2_3:
2647#endif
018d00d2
ZX		 2648 r = 1;
2649 break;
542472b5
LV		 2650 case KVM_CAP_COALESCED_MMIO:
2651 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2652 break;
774ead3a
AK		 2653 case KVM_CAP_VAPIC:
2654 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2655 break;
f725230a 2656 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2657 r = KVM_SOFT_MAX_VCPUS;
2658 break;
2659 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2660 r = KVM_MAX_VCPUS;
2661 break;
a988b910 2662 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2663 r = KVM_USER_MEM_SLOTS;
a988b910 2664 break;
a68a6a72
MT		 2665 case KVM_CAP_PV_MMU: /* obsolete */
2666 r = 0;
2f333bcb 2667 break;
4cee4b72 2668#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2669 case KVM_CAP_IOMMU:
a1b60c1c 2670 r = iommu_present(&pci_bus_type);
62c476c7 2671 break;
4cee4b72 2672#endif
890ca9ae
HY		 2673 case KVM_CAP_MCE:
2674 r = KVM_MAX_MCE_BANKS;
2675 break;
2d5b5a66
SY		 2676 case KVM_CAP_XCRS:
2677 r = cpu_has_xsave;
2678 break;
92a1f12d
JR		 2679 case KVM_CAP_TSC_CONTROL:
2680 r = kvm_has_tsc_control;
2681 break;
4d25a066
JK		 2682 case KVM_CAP_TSC_DEADLINE_TIMER:
2683 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2684 break;
018d00d2
ZX		 2685 default:
2686 r = 0;
2687 break;
2688 }
2689 return r;
2690
2691}
2692
043405e1
CO		 2693long kvm_arch_dev_ioctl(struct file *filp,
2694 unsigned int ioctl, unsigned long arg)
2695{
2696 void __user *argp = (void __user *)arg;
2697 long r;
2698
2699 switch (ioctl) {
2700 case KVM_GET_MSR_INDEX_LIST: {
2701 struct kvm_msr_list __user *user_msr_list = argp;
2702 struct kvm_msr_list msr_list;
2703 unsigned n;
2704
2705 r = -EFAULT;
2706 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2707 goto out;
2708 n = msr_list.nmsrs;
2709 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2710 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2711 goto out;
2712 r = -E2BIG;
e125e7b6 2713 if (n < msr_list.nmsrs)
043405e1
CO		 2714 goto out;
2715 r = -EFAULT;
2716 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2717 num_msrs_to_save * sizeof(u32)))
2718 goto out;
e125e7b6 2719 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2720 &emulated_msrs,
2721 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2722 goto out;
2723 r = 0;
2724 break;
2725 }
9c15bb1d
BP		 2726 case KVM_GET_SUPPORTED_CPUID:
2727 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2728 struct kvm_cpuid2 __user *cpuid_arg = argp;
2729 struct kvm_cpuid2 cpuid;
2730
2731 r = -EFAULT;
2732 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2733 goto out;
9c15bb1d
BP		 2734
2735 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2736 ioctl);
674eea0f
AK		 2737 if (r)
2738 goto out;
2739
2740 r = -EFAULT;
2741 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2742 goto out;
2743 r = 0;
2744 break;
2745 }
890ca9ae
HY		 2746 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2747 u64 mce_cap;
2748
2749 mce_cap = KVM_MCE_CAP_SUPPORTED;
2750 r = -EFAULT;
2751 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2752 goto out;
2753 r = 0;
2754 break;
2755 }
043405e1
CO		 2756 default:
2757 r = -EINVAL;
2758 }
2759out:
2760 return r;
2761}
2762
f5f48ee1
SY		 2763static void wbinvd_ipi(void *garbage)
2764{
2765 wbinvd();
2766}
2767
2768static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2769{
e0f0bbc5 2770 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2771}
2772
313a3dc7
CO		 2773void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2774{
f5f48ee1
SY		 2775 /* Address WBINVD may be executed by guest */
2776 if (need_emulate_wbinvd(vcpu)) {
2777 if (kvm_x86_ops->has_wbinvd_exit())
2778 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2779 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2780 smp_call_function_single(vcpu->cpu,
2781 wbinvd_ipi, NULL, 1);
2782 }
2783
313a3dc7 2784 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2785
0dd6a6ed
ZA		 2786 /* Apply any externally detected TSC adjustments (due to suspend) */
2787 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2788 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2789 vcpu->arch.tsc_offset_adjustment = 0;
2790 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2791 }
8f6055cb 2792
48434c20 2793 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2794 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2795 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2796 if (tsc_delta < 0)
2797 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2798 if (check_tsc_unstable()) {
b183aa58
ZA		 2799 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2800 vcpu->arch.last_guest_tsc);
2801 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2802 vcpu->arch.tsc_catchup = 1;
c285545f 2803 }
d98d07ca
MT		 2804 /*
2805 * On a host with synchronized TSC, there is no need to update
2806 * kvmclock on vcpu->cpu migration
2807 */
2808 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2809 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2810 if (vcpu->cpu != cpu)
2811 kvm_migrate_timers(vcpu);
e48672fa 2812 vcpu->cpu = cpu;
6b7d7e76 2813 }
c9aaa895
GC		 2814
2815 accumulate_steal_time(vcpu);
2816 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2817}
2818
2819void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2820{
02daab21 2821 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2822 kvm_put_guest_fpu(vcpu);
6f526ec5 2823 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2824}
2825
313a3dc7
CO		 2826static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2827 struct kvm_lapic_state *s)
2828{
5a71785d 2829 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2830 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2831
2832 return 0;
2833}
2834
2835static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2836 struct kvm_lapic_state *s)
2837{
64eb0620 2838 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2839 update_cr8_intercept(vcpu);
313a3dc7
CO		 2840
2841 return 0;
2842}
2843
f77bc6a4
ZX		 2844static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2845 struct kvm_interrupt *irq)
2846{
02cdb50f 2847 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2848 return -EINVAL;
2849 if (irqchip_in_kernel(vcpu->kvm))
2850 return -ENXIO;
f77bc6a4 2851
66fd3f7f 2852 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2853 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2854
f77bc6a4
ZX		 2855 return 0;
2856}
2857
c4abb7c9
JK		 2858static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2859{
c4abb7c9 2860 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2861
2862 return 0;
2863}
2864
b209749f
AK		 2865static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2866 struct kvm_tpr_access_ctl *tac)
2867{
2868 if (tac->flags)
2869 return -EINVAL;
2870 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2871 return 0;
2872}
2873
890ca9ae
HY		 2874static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2875 u64 mcg_cap)
2876{
2877 int r;
2878 unsigned bank_num = mcg_cap & 0xff, bank;
2879
2880 r = -EINVAL;
a9e38c3e 2881 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2882 goto out;
2883 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2884 goto out;
2885 r = 0;
2886 vcpu->arch.mcg_cap = mcg_cap;
2887 /* Init IA32_MCG_CTL to all 1s */
2888 if (mcg_cap & MCG_CTL_P)
2889 vcpu->arch.mcg_ctl = ~(u64)0;
2890 /* Init IA32_MCi_CTL to all 1s */
2891 for (bank = 0; bank < bank_num; bank++)
2892 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2893out:
2894 return r;
2895}
2896
2897static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2898 struct kvm_x86_mce *mce)
2899{
2900 u64 mcg_cap = vcpu->arch.mcg_cap;
2901 unsigned bank_num = mcg_cap & 0xff;
2902 u64 *banks = vcpu->arch.mce_banks;
2903
2904 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2905 return -EINVAL;
2906 /*
2907 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2908 * reporting is disabled
2909 */
2910 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2911 vcpu->arch.mcg_ctl != ~(u64)0)
2912 return 0;
2913 banks += 4 * mce->bank;
2914 /*
2915 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2916 * reporting is disabled for the bank
2917 */
2918 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2919 return 0;
2920 if (mce->status & MCI_STATUS_UC) {
2921 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2922 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2923 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2924 return 0;
2925 }
2926 if (banks[1] & MCI_STATUS_VAL)
2927 mce->status |= MCI_STATUS_OVER;
2928 banks[2] = mce->addr;
2929 banks[3] = mce->misc;
2930 vcpu->arch.mcg_status = mce->mcg_status;
2931 banks[1] = mce->status;
2932 kvm_queue_exception(vcpu, MC_VECTOR);
2933 } else if (!(banks[1] & MCI_STATUS_VAL)
2934 || !(banks[1] & MCI_STATUS_UC)) {
2935 if (banks[1] & MCI_STATUS_VAL)
2936 mce->status |= MCI_STATUS_OVER;
2937 banks[2] = mce->addr;
2938 banks[3] = mce->misc;
2939 banks[1] = mce->status;
2940 } else
2941 banks[1] |= MCI_STATUS_OVER;
2942 return 0;
2943}
2944
3cfc3092
JK		 2945static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2946 struct kvm_vcpu_events *events)
2947{
7460fb4a 2948 process_nmi(vcpu);
03b82a30
JK		 2949 events->exception.injected =
2950 vcpu->arch.exception.pending &&
2951 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2952 events->exception.nr = vcpu->arch.exception.nr;
2953 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2954 events->exception.pad = 0;
3cfc3092
JK		 2955 events->exception.error_code = vcpu->arch.exception.error_code;
2956
03b82a30
JK		 2957 events->interrupt.injected =
2958 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2959 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2960 events->interrupt.soft = 0;
48005f64
JK		 2961 events->interrupt.shadow =
2962 kvm_x86_ops->get_interrupt_shadow(vcpu,
2963 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2964
2965 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2966 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2967 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2968 events->nmi.pad = 0;
3cfc3092 2969
66450a21 2970 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2971
dab4b911 2972 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2973 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2974 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2975}
2976
2977static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2978 struct kvm_vcpu_events *events)
2979{
dab4b911 2980 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2981 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2982 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2983 return -EINVAL;
2984
7460fb4a 2985 process_nmi(vcpu);
3cfc3092
JK		 2986 vcpu->arch.exception.pending = events->exception.injected;
2987 vcpu->arch.exception.nr = events->exception.nr;
2988 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2989 vcpu->arch.exception.error_code = events->exception.error_code;
2990
2991 vcpu->arch.interrupt.pending = events->interrupt.injected;
2992 vcpu->arch.interrupt.nr = events->interrupt.nr;
2993 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2994 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2995 kvm_x86_ops->set_interrupt_shadow(vcpu,
2996 events->interrupt.shadow);
3cfc3092
JK		 2997
2998 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2999 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3000 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3001 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3002
66450a21
JK		 3003 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3004 kvm_vcpu_has_lapic(vcpu))
3005 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3006
3842d135
AK		 3007 kvm_make_request(KVM_REQ_EVENT, vcpu);
3008
3cfc3092
JK		 3009 return 0;
3010}
3011
a1efbe77
JK		 3012static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3013 struct kvm_debugregs *dbgregs)
3014{
73aaf249
JK		 3015 unsigned long val;
3016
a1efbe77 3017 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3018 _kvm_get_dr(vcpu, 6, &val);
3019 dbgregs->dr6 = val;
a1efbe77
JK		 3020 dbgregs->dr7 = vcpu->arch.dr7;
3021 dbgregs->flags = 0;
97e69aa6 3022 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3023}
3024
3025static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3026 struct kvm_debugregs *dbgregs)
3027{
3028 if (dbgregs->flags)
3029 return -EINVAL;
3030
a1efbe77
JK		 3031 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3032 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3033 kvm_update_dr6(vcpu);
a1efbe77 3034 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3035 kvm_update_dr7(vcpu);
a1efbe77 3036
a1efbe77
JK		 3037 return 0;
3038}
3039
2d5b5a66
SY		 3040static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3041 struct kvm_xsave *guest_xsave)
3042{
4344ee98 3043 if (cpu_has_xsave) {
2d5b5a66
SY		 3044 memcpy(guest_xsave->region,
3045 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3046 vcpu->arch.guest_xstate_size);
3047 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3048 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3049 } else {
2d5b5a66
SY		 3050 memcpy(guest_xsave->region,
3051 &vcpu->arch.guest_fpu.state->fxsave,
3052 sizeof(struct i387_fxsave_struct));
3053 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3054 XSTATE_FPSSE;
3055 }
3056}
3057
3058static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3059 struct kvm_xsave *guest_xsave)
3060{
3061 u64 xstate_bv =
3062 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3063
d7876f1b
PB		 3064 if (cpu_has_xsave) {
3065 /*
3066 * Here we allow setting states that are not present in
3067 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3068 * with old userspace.
3069 */
3070 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3071 return -EINVAL;
3072 if (xstate_bv & ~host_xcr0)
3073 return -EINVAL;
2d5b5a66 3074 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3075 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3076 } else {
2d5b5a66
SY		 3077 if (xstate_bv & ~XSTATE_FPSSE)
3078 return -EINVAL;
3079 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3080 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3081 }
3082 return 0;
3083}
3084
3085static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3086 struct kvm_xcrs *guest_xcrs)
3087{
3088 if (!cpu_has_xsave) {
3089 guest_xcrs->nr_xcrs = 0;
3090 return;
3091 }
3092
3093 guest_xcrs->nr_xcrs = 1;
3094 guest_xcrs->flags = 0;
3095 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3096 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3097}
3098
3099static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3100 struct kvm_xcrs *guest_xcrs)
3101{
3102 int i, r = 0;
3103
3104 if (!cpu_has_xsave)
3105 return -EINVAL;
3106
3107 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3108 return -EINVAL;
3109
3110 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3111 /* Only support XCR0 currently */
c67a04cb 3112 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3113 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3114 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3115 break;
3116 }
3117 if (r)
3118 r = -EINVAL;
3119 return r;
3120}
3121
1c0b28c2
EM		 3122/*
3123 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3124 * stopped by the hypervisor. This function will be called from the host only.
3125 * EINVAL is returned when the host attempts to set the flag for a guest that
3126 * does not support pv clocks.
3127 */
3128static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3129{
0b79459b 3130 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3131 return -EINVAL;
51d59c6b 3132 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3133 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3134 return 0;
3135}
3136
313a3dc7
CO		 3137long kvm_arch_vcpu_ioctl(struct file *filp,
3138 unsigned int ioctl, unsigned long arg)
3139{
3140 struct kvm_vcpu *vcpu = filp->private_data;
3141 void __user *argp = (void __user *)arg;
3142 int r;
d1ac91d8
AK		 3143 union {
3144 struct kvm_lapic_state *lapic;
3145 struct kvm_xsave *xsave;
3146 struct kvm_xcrs *xcrs;
3147 void *buffer;
3148 } u;
3149
3150 u.buffer = NULL;
313a3dc7
CO		 3151 switch (ioctl) {
3152 case KVM_GET_LAPIC: {
2204ae3c
MT		 3153 r = -EINVAL;
3154 if (!vcpu->arch.apic)
3155 goto out;
d1ac91d8 3156 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3157
b772ff36 3158 r = -ENOMEM;
d1ac91d8 3159 if (!u.lapic)
b772ff36 3160 goto out;
d1ac91d8 3161 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3162 if (r)
3163 goto out;
3164 r = -EFAULT;
d1ac91d8 3165 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3166 goto out;
3167 r = 0;
3168 break;
3169 }
3170 case KVM_SET_LAPIC: {
2204ae3c
MT		 3171 r = -EINVAL;
3172 if (!vcpu->arch.apic)
3173 goto out;
ff5c2c03 3174 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3175 if (IS_ERR(u.lapic))
3176 return PTR_ERR(u.lapic);
ff5c2c03 3177
d1ac91d8 3178 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3179 break;
3180 }
f77bc6a4
ZX		 3181 case KVM_INTERRUPT: {
3182 struct kvm_interrupt irq;
3183
3184 r = -EFAULT;
3185 if (copy_from_user(&irq, argp, sizeof irq))
3186 goto out;
3187 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3188 break;
3189 }
c4abb7c9
JK		 3190 case KVM_NMI: {
3191 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3192 break;
3193 }
313a3dc7
CO		 3194 case KVM_SET_CPUID: {
3195 struct kvm_cpuid __user *cpuid_arg = argp;
3196 struct kvm_cpuid cpuid;
3197
3198 r = -EFAULT;
3199 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3200 goto out;
3201 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3202 break;
3203 }
07716717
DK		 3204 case KVM_SET_CPUID2: {
3205 struct kvm_cpuid2 __user *cpuid_arg = argp;
3206 struct kvm_cpuid2 cpuid;
3207
3208 r = -EFAULT;
3209 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3210 goto out;
3211 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3212 cpuid_arg->entries);
07716717
DK		 3213 break;
3214 }
3215 case KVM_GET_CPUID2: {
3216 struct kvm_cpuid2 __user *cpuid_arg = argp;
3217 struct kvm_cpuid2 cpuid;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3221 goto out;
3222 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3223 cpuid_arg->entries);
07716717
DK		 3224 if (r)
3225 goto out;
3226 r = -EFAULT;
3227 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3228 goto out;
3229 r = 0;
3230 break;
3231 }
313a3dc7
CO		 3232 case KVM_GET_MSRS:
3233 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3234 break;
3235 case KVM_SET_MSRS:
3236 r = msr_io(vcpu, argp, do_set_msr, 0);
3237 break;
b209749f
AK		 3238 case KVM_TPR_ACCESS_REPORTING: {
3239 struct kvm_tpr_access_ctl tac;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&tac, argp, sizeof tac))
3243 goto out;
3244 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3245 if (r)
3246 goto out;
3247 r = -EFAULT;
3248 if (copy_to_user(argp, &tac, sizeof tac))
3249 goto out;
3250 r = 0;
3251 break;
3252 };
b93463aa
AK		 3253 case KVM_SET_VAPIC_ADDR: {
3254 struct kvm_vapic_addr va;
3255
3256 r = -EINVAL;
3257 if (!irqchip_in_kernel(vcpu->kvm))
3258 goto out;
3259 r = -EFAULT;
3260 if (copy_from_user(&va, argp, sizeof va))
3261 goto out;
fda4e2e8 3262 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3263 break;
3264 }
890ca9ae
HY		 3265 case KVM_X86_SETUP_MCE: {
3266 u64 mcg_cap;
3267
3268 r = -EFAULT;
3269 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3270 goto out;
3271 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3272 break;
3273 }
3274 case KVM_X86_SET_MCE: {
3275 struct kvm_x86_mce mce;
3276
3277 r = -EFAULT;
3278 if (copy_from_user(&mce, argp, sizeof mce))
3279 goto out;
3280 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3281 break;
3282 }
3cfc3092
JK		 3283 case KVM_GET_VCPU_EVENTS: {
3284 struct kvm_vcpu_events events;
3285
3286 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3287
3288 r = -EFAULT;
3289 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3290 break;
3291 r = 0;
3292 break;
3293 }
3294 case KVM_SET_VCPU_EVENTS: {
3295 struct kvm_vcpu_events events;
3296
3297 r = -EFAULT;
3298 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3299 break;
3300
3301 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3302 break;
3303 }
a1efbe77
JK		 3304 case KVM_GET_DEBUGREGS: {
3305 struct kvm_debugregs dbgregs;
3306
3307 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3308
3309 r = -EFAULT;
3310 if (copy_to_user(argp, &dbgregs,
3311 sizeof(struct kvm_debugregs)))
3312 break;
3313 r = 0;
3314 break;
3315 }
3316 case KVM_SET_DEBUGREGS: {
3317 struct kvm_debugregs dbgregs;
3318
3319 r = -EFAULT;
3320 if (copy_from_user(&dbgregs, argp,
3321 sizeof(struct kvm_debugregs)))
3322 break;
3323
3324 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3325 break;
3326 }
2d5b5a66 3327 case KVM_GET_XSAVE: {
d1ac91d8 3328 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3329 r = -ENOMEM;
d1ac91d8 3330 if (!u.xsave)
2d5b5a66
SY		 3331 break;
3332
d1ac91d8 3333 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3334
3335 r = -EFAULT;
d1ac91d8 3336 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3337 break;
3338 r = 0;
3339 break;
3340 }
3341 case KVM_SET_XSAVE: {
ff5c2c03 3342 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3343 if (IS_ERR(u.xsave))
3344 return PTR_ERR(u.xsave);
2d5b5a66 3345
d1ac91d8 3346 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3347 break;
3348 }
3349 case KVM_GET_XCRS: {
d1ac91d8 3350 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3351 r = -ENOMEM;
d1ac91d8 3352 if (!u.xcrs)
2d5b5a66
SY		 3353 break;
3354
d1ac91d8 3355 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3356
3357 r = -EFAULT;
d1ac91d8 3358 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3359 sizeof(struct kvm_xcrs)))
3360 break;
3361 r = 0;
3362 break;
3363 }
3364 case KVM_SET_XCRS: {
ff5c2c03 3365 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3366 if (IS_ERR(u.xcrs))
3367 return PTR_ERR(u.xcrs);
2d5b5a66 3368
d1ac91d8 3369 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3370 break;
3371 }
92a1f12d
JR		 3372 case KVM_SET_TSC_KHZ: {
3373 u32 user_tsc_khz;
3374
3375 r = -EINVAL;
92a1f12d
JR		 3376 user_tsc_khz = (u32)arg;
3377
3378 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3379 goto out;
3380
cc578287
ZA		 3381 if (user_tsc_khz == 0)
3382 user_tsc_khz = tsc_khz;
3383
3384 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3385
3386 r = 0;
3387 goto out;
3388 }
3389 case KVM_GET_TSC_KHZ: {
cc578287 3390 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3391 goto out;
3392 }
1c0b28c2
EM		 3393 case KVM_KVMCLOCK_CTRL: {
3394 r = kvm_set_guest_paused(vcpu);
3395 goto out;
3396 }
313a3dc7
CO		 3397 default:
3398 r = -EINVAL;
3399 }
3400out:
d1ac91d8 3401 kfree(u.buffer);
313a3dc7
CO		 3402 return r;
3403}
3404
5b1c1493
CO		 3405int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3406{
3407 return VM_FAULT_SIGBUS;
3408}
3409
1fe779f8
CO		 3410static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3411{
3412 int ret;
3413
3414 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3415 return -EINVAL;
1fe779f8
CO		 3416 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3417 return ret;
3418}
3419
b927a3ce
SY		 3420static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3421 u64 ident_addr)
3422{
3423 kvm->arch.ept_identity_map_addr = ident_addr;
3424 return 0;
3425}
3426
1fe779f8
CO		 3427static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3428 u32 kvm_nr_mmu_pages)
3429{
3430 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3431 return -EINVAL;
3432
79fac95e 3433 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3434
3435 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3436 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3437
79fac95e 3438 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3439 return 0;
3440}
3441
3442static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3443{
39de71ec 3444 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3445}
3446
1fe779f8
CO		 3447static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3448{
3449 int r;
3450
3451 r = 0;
3452 switch (chip->chip_id) {
3453 case KVM_IRQCHIP_PIC_MASTER:
3454 memcpy(&chip->chip.pic,
3455 &pic_irqchip(kvm)->pics[0],
3456 sizeof(struct kvm_pic_state));
3457 break;
3458 case KVM_IRQCHIP_PIC_SLAVE:
3459 memcpy(&chip->chip.pic,
3460 &pic_irqchip(kvm)->pics[1],
3461 sizeof(struct kvm_pic_state));
3462 break;
3463 case KVM_IRQCHIP_IOAPIC:
eba0226b 3464 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3465 break;
3466 default:
3467 r = -EINVAL;
3468 break;
3469 }
3470 return r;
3471}
3472
3473static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3474{
3475 int r;
3476
3477 r = 0;
3478 switch (chip->chip_id) {
3479 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3480 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3481 memcpy(&pic_irqchip(kvm)->pics[0],
3482 &chip->chip.pic,
3483 sizeof(struct kvm_pic_state));
f4f51050 3484 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3485 break;
3486 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3487 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3488 memcpy(&pic_irqchip(kvm)->pics[1],
3489 &chip->chip.pic,
3490 sizeof(struct kvm_pic_state));
f4f51050 3491 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3492 break;
3493 case KVM_IRQCHIP_IOAPIC:
eba0226b 3494 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3495 break;
3496 default:
3497 r = -EINVAL;
3498 break;
3499 }
3500 kvm_pic_update_irq(pic_irqchip(kvm));
3501 return r;
3502}
3503
e0f63cb9
SY		 3504static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3505{
3506 int r = 0;
3507
894a9c55 3508 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3509 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3510 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3511 return r;
3512}
3513
3514static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3515{
3516 int r = 0;
3517
894a9c55 3518 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3519 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3520 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3521 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3522 return r;
3523}
3524
3525static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3526{
3527 int r = 0;
3528
3529 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3530 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3531 sizeof(ps->channels));
3532 ps->flags = kvm->arch.vpit->pit_state.flags;
3533 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3534 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3535 return r;
3536}
3537
3538static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3539{
3540 int r = 0, start = 0;
3541 u32 prev_legacy, cur_legacy;
3542 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3543 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3544 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3545 if (!prev_legacy && cur_legacy)
3546 start = 1;
3547 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3548 sizeof(kvm->arch.vpit->pit_state.channels));
3549 kvm->arch.vpit->pit_state.flags = ps->flags;
3550 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3551 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3552 return r;
3553}
3554
52d939a0
MT		 3555static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3556 struct kvm_reinject_control *control)
3557{
3558 if (!kvm->arch.vpit)
3559 return -ENXIO;
894a9c55 3560 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3561 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3562 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3563 return 0;
3564}
3565
95d4c16c 3566/**
60c34612
TY		 3567 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3568 * @kvm: kvm instance
3569 * @log: slot id and address to which we copy the log
95d4c16c 3570 *
60c34612
TY		 3571 * We need to keep it in mind that VCPU threads can write to the bitmap
3572 * concurrently. So, to avoid losing data, we keep the following order for
3573 * each bit:
95d4c16c 3574 *
60c34612
TY		 3575 * 1. Take a snapshot of the bit and clear it if needed.
3576 * 2. Write protect the corresponding page.
3577 * 3. Flush TLB's if needed.
3578 * 4. Copy the snapshot to the userspace.
95d4c16c 3579 *
60c34612
TY		 3580 * Between 2 and 3, the guest may write to the page using the remaining TLB
3581 * entry. This is not a problem because the page will be reported dirty at
3582 * step 4 using the snapshot taken before and step 3 ensures that successive
3583 * writes will be logged for the next call.
5bb064dc 3584 */
60c34612 3585int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3586{
7850ac54 3587 int r;
5bb064dc 3588 struct kvm_memory_slot *memslot;
60c34612
TY		 3589 unsigned long n, i;
3590 unsigned long *dirty_bitmap;
3591 unsigned long *dirty_bitmap_buffer;
3592 bool is_dirty = false;
5bb064dc 3593
79fac95e 3594 mutex_lock(&kvm->slots_lock);
5bb064dc 3595
b050b015 3596 r = -EINVAL;
bbacc0c1 3597 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3598 goto out;
3599
28a37544 3600 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3601
3602 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3603 r = -ENOENT;
60c34612 3604 if (!dirty_bitmap)
b050b015
MT		 3605 goto out;
3606
87bf6e7d 3607 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3608
60c34612
TY		 3609 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3610 memset(dirty_bitmap_buffer, 0, n);
b050b015 3611
60c34612 3612 spin_lock(&kvm->mmu_lock);
b050b015 3613
60c34612
TY		 3614 for (i = 0; i < n / sizeof(long); i++) {
3615 unsigned long mask;
3616 gfn_t offset;
cdfca7b3 3617
60c34612
TY		 3618 if (!dirty_bitmap[i])
3619 continue;
b050b015 3620
60c34612 3621 is_dirty = true;
914ebccd 3622
60c34612
TY		 3623 mask = xchg(&dirty_bitmap[i], 0);
3624 dirty_bitmap_buffer[i] = mask;
edde99ce 3625
60c34612
TY		 3626 offset = i * BITS_PER_LONG;
3627 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3628 }
60c34612
TY		 3629 if (is_dirty)
3630 kvm_flush_remote_tlbs(kvm);
3631
3632 spin_unlock(&kvm->mmu_lock);
3633
3634 r = -EFAULT;
3635 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3636 goto out;
b050b015 3637
5bb064dc
ZX		 3638 r = 0;
3639out:
79fac95e 3640 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3641 return r;
3642}
3643
aa2fbe6d
YZ		 3644int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3645 bool line_status)
23d43cf9
CD		 3646{
3647 if (!irqchip_in_kernel(kvm))
3648 return -ENXIO;
3649
3650 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3651 irq_event->irq, irq_event->level,
3652 line_status);
23d43cf9
CD		 3653 return 0;
3654}
3655
1fe779f8
CO		 3656long kvm_arch_vm_ioctl(struct file *filp,
3657 unsigned int ioctl, unsigned long arg)
3658{
3659 struct kvm *kvm = filp->private_data;
3660 void __user *argp = (void __user *)arg;
367e1319 3661 int r = -ENOTTY;
f0d66275
DH		 3662 /*
3663 * This union makes it completely explicit to gcc-3.x
3664 * that these two variables' stack usage should be
3665 * combined, not added together.
3666 */
3667 union {
3668 struct kvm_pit_state ps;
e9f42757 3669 struct kvm_pit_state2 ps2;
c5ff41ce 3670 struct kvm_pit_config pit_config;
f0d66275 3671 } u;
1fe779f8
CO		 3672
3673 switch (ioctl) {
3674 case KVM_SET_TSS_ADDR:
3675 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3676 break;
b927a3ce
SY		 3677 case KVM_SET_IDENTITY_MAP_ADDR: {
3678 u64 ident_addr;
3679
3680 r = -EFAULT;
3681 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3682 goto out;
3683 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3684 break;
3685 }
1fe779f8
CO		 3686 case KVM_SET_NR_MMU_PAGES:
3687 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3688 break;
3689 case KVM_GET_NR_MMU_PAGES:
3690 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3691 break;
3ddea128
MT		 3692 case KVM_CREATE_IRQCHIP: {
3693 struct kvm_pic *vpic;
3694
3695 mutex_lock(&kvm->lock);
3696 r = -EEXIST;
3697 if (kvm->arch.vpic)
3698 goto create_irqchip_unlock;
3e515705
AK		 3699 r = -EINVAL;
3700 if (atomic_read(&kvm->online_vcpus))
3701 goto create_irqchip_unlock;
1fe779f8 3702 r = -ENOMEM;
3ddea128
MT		 3703 vpic = kvm_create_pic(kvm);
3704 if (vpic) {
1fe779f8
CO		 3705 r = kvm_ioapic_init(kvm);
3706 if (r) {
175504cd 3707 mutex_lock(&kvm->slots_lock);
72bb2fcd 3708 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3709 &vpic->dev_master);
3710 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3711 &vpic->dev_slave);
3712 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3713 &vpic->dev_eclr);
175504cd 3714 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3715 kfree(vpic);
3716 goto create_irqchip_unlock;
1fe779f8
CO		 3717 }
3718 } else
3ddea128
MT		 3719 goto create_irqchip_unlock;
3720 smp_wmb();
3721 kvm->arch.vpic = vpic;
3722 smp_wmb();
399ec807
AK		 3723 r = kvm_setup_default_irq_routing(kvm);
3724 if (r) {
175504cd 3725 mutex_lock(&kvm->slots_lock);
3ddea128 3726 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3727 kvm_ioapic_destroy(kvm);
3728 kvm_destroy_pic(kvm);
3ddea128 3729 mutex_unlock(&kvm->irq_lock);
175504cd 3730 mutex_unlock(&kvm->slots_lock);
399ec807 3731 }
3ddea128
MT		 3732 create_irqchip_unlock:
3733 mutex_unlock(&kvm->lock);
1fe779f8 3734 break;
3ddea128 3735 }
7837699f 3736 case KVM_CREATE_PIT:
c5ff41ce
JK		 3737 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3738 goto create_pit;
3739 case KVM_CREATE_PIT2:
3740 r = -EFAULT;
3741 if (copy_from_user(&u.pit_config, argp,
3742 sizeof(struct kvm_pit_config)))
3743 goto out;
3744 create_pit:
79fac95e 3745 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3746 r = -EEXIST;
3747 if (kvm->arch.vpit)
3748 goto create_pit_unlock;
7837699f 3749 r = -ENOMEM;
c5ff41ce 3750 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3751 if (kvm->arch.vpit)
3752 r = 0;
269e05e4 3753 create_pit_unlock:
79fac95e 3754 mutex_unlock(&kvm->slots_lock);
7837699f 3755 break;
1fe779f8
CO		 3756 case KVM_GET_IRQCHIP: {
3757 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3758 struct kvm_irqchip *chip;
1fe779f8 3759
ff5c2c03
SL		 3760 chip = memdup_user(argp, sizeof(*chip));
3761 if (IS_ERR(chip)) {
3762 r = PTR_ERR(chip);
1fe779f8 3763 goto out;
ff5c2c03
SL		 3764 }
3765
1fe779f8
CO		 3766 r = -ENXIO;
3767 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3768 goto get_irqchip_out;
3769 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3770 if (r)
f0d66275 3771 goto get_irqchip_out;
1fe779f8 3772 r = -EFAULT;
f0d66275
DH		 3773 if (copy_to_user(argp, chip, sizeof *chip))
3774 goto get_irqchip_out;
1fe779f8 3775 r = 0;
f0d66275
DH		 3776 get_irqchip_out:
3777 kfree(chip);
1fe779f8
CO		 3778 break;
3779 }
3780 case KVM_SET_IRQCHIP: {
3781 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3782 struct kvm_irqchip *chip;
1fe779f8 3783
ff5c2c03
SL		 3784 chip = memdup_user(argp, sizeof(*chip));
3785 if (IS_ERR(chip)) {
3786 r = PTR_ERR(chip);
1fe779f8 3787 goto out;
ff5c2c03
SL		 3788 }
3789
1fe779f8
CO		 3790 r = -ENXIO;
3791 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3792 goto set_irqchip_out;
3793 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3794 if (r)
f0d66275 3795 goto set_irqchip_out;
1fe779f8 3796 r = 0;
f0d66275
DH		 3797 set_irqchip_out:
3798 kfree(chip);
1fe779f8
CO		 3799 break;
3800 }
e0f63cb9 3801 case KVM_GET_PIT: {
e0f63cb9 3802 r = -EFAULT;
f0d66275 3803 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3804 goto out;
3805 r = -ENXIO;
3806 if (!kvm->arch.vpit)
3807 goto out;
f0d66275 3808 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3809 if (r)
3810 goto out;
3811 r = -EFAULT;
f0d66275 3812 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3813 goto out;
3814 r = 0;
3815 break;
3816 }
3817 case KVM_SET_PIT: {
e0f63cb9 3818 r = -EFAULT;
f0d66275 3819 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3820 goto out;
3821 r = -ENXIO;
3822 if (!kvm->arch.vpit)
3823 goto out;
f0d66275 3824 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3825 break;
3826 }
e9f42757
BK		 3827 case KVM_GET_PIT2: {
3828 r = -ENXIO;
3829 if (!kvm->arch.vpit)
3830 goto out;
3831 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3832 if (r)
3833 goto out;
3834 r = -EFAULT;
3835 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3836 goto out;
3837 r = 0;
3838 break;
3839 }
3840 case KVM_SET_PIT2: {
3841 r = -EFAULT;
3842 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3843 goto out;
3844 r = -ENXIO;
3845 if (!kvm->arch.vpit)
3846 goto out;
3847 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3848 break;
3849 }
52d939a0
MT		 3850 case KVM_REINJECT_CONTROL: {
3851 struct kvm_reinject_control control;
3852 r = -EFAULT;
3853 if (copy_from_user(&control, argp, sizeof(control)))
3854 goto out;
3855 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3856 break;
3857 }
ffde22ac
ES		 3858 case KVM_XEN_HVM_CONFIG: {
3859 r = -EFAULT;
3860 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3861 sizeof(struct kvm_xen_hvm_config)))
3862 goto out;
3863 r = -EINVAL;
3864 if (kvm->arch.xen_hvm_config.flags)
3865 goto out;
3866 r = 0;
3867 break;
3868 }
afbcf7ab 3869 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3870 struct kvm_clock_data user_ns;
3871 u64 now_ns;
3872 s64 delta;
3873
3874 r = -EFAULT;
3875 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3876 goto out;
3877
3878 r = -EINVAL;
3879 if (user_ns.flags)
3880 goto out;
3881
3882 r = 0;
395c6b0a 3883 local_irq_disable();
759379dd 3884 now_ns = get_kernel_ns();
afbcf7ab 3885 delta = user_ns.clock - now_ns;
395c6b0a 3886 local_irq_enable();
afbcf7ab 3887 kvm->arch.kvmclock_offset = delta;
2e762ff7 3888 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3889 break;
3890 }
3891 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3892 struct kvm_clock_data user_ns;
3893 u64 now_ns;
3894
395c6b0a 3895 local_irq_disable();
759379dd 3896 now_ns = get_kernel_ns();
afbcf7ab 3897 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3898 local_irq_enable();
afbcf7ab 3899 user_ns.flags = 0;
97e69aa6 3900 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3901
3902 r = -EFAULT;
3903 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3904 goto out;
3905 r = 0;
3906 break;
3907 }
3908
1fe779f8
CO		 3909 default:
3910 ;
3911 }
3912out:
3913 return r;
3914}
3915
a16b043c 3916static void kvm_init_msr_list(void)
043405e1
CO		 3917{
3918 u32 dummy[2];
3919 unsigned i, j;
3920
e3267cbb
GC		 3921 /* skip the first msrs in the list. KVM-specific */
3922 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3923 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3924 continue;
3925 if (j < i)
3926 msrs_to_save[j] = msrs_to_save[i];
3927 j++;
3928 }
3929 num_msrs_to_save = j;
3930}
3931
bda9020e
MT		 3932static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3933 const void *v)
bbd9b64e 3934{
70252a10
AK		 3935 int handled = 0;
3936 int n;
3937
3938 do {
3939 n = min(len, 8);
3940 if (!(vcpu->arch.apic &&
3941 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3942 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3943 break;
3944 handled += n;
3945 addr += n;
3946 len -= n;
3947 v += n;
3948 } while (len);
bbd9b64e 3949
70252a10 3950 return handled;
bbd9b64e
CO		 3951}
3952
bda9020e 3953static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3954{
70252a10
AK		 3955 int handled = 0;
3956 int n;
3957
3958 do {
3959 n = min(len, 8);
3960 if (!(vcpu->arch.apic &&
3961 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3962 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3963 break;
3964 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3965 handled += n;
3966 addr += n;
3967 len -= n;
3968 v += n;
3969 } while (len);
bbd9b64e 3970
70252a10 3971 return handled;
bbd9b64e
CO		 3972}
3973
2dafc6c2
GN		 3974static void kvm_set_segment(struct kvm_vcpu *vcpu,
3975 struct kvm_segment *var, int seg)
3976{
3977 kvm_x86_ops->set_segment(vcpu, var, seg);
3978}
3979
3980void kvm_get_segment(struct kvm_vcpu *vcpu,
3981 struct kvm_segment *var, int seg)
3982{
3983 kvm_x86_ops->get_segment(vcpu, var, seg);
3984}
3985
e459e322 3986gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3987{
3988 gpa_t t_gpa;
ab9ae313 3989 struct x86_exception exception;
02f59dc9
JR		 3990
3991 BUG_ON(!mmu_is_nested(vcpu));
3992
3993 /* NPT walks are always user-walks */
3994 access |= PFERR_USER_MASK;
ab9ae313 3995 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3996
3997 return t_gpa;
3998}
3999
ab9ae313
AK		 4000gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4001 struct x86_exception *exception)
1871c602
GN		 4002{
4003 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4004 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4005}
4006
ab9ae313
AK		 4007 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4008 struct x86_exception *exception)
1871c602
GN		 4009{
4010 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4011 access |= PFERR_FETCH_MASK;
ab9ae313 4012 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4013}
4014
ab9ae313
AK		 4015gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4016 struct x86_exception *exception)
1871c602
GN		 4017{
4018 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4019 access |= PFERR_WRITE_MASK;
ab9ae313 4020 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4021}
4022
4023/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4024gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4025 struct x86_exception *exception)
1871c602 4026{
ab9ae313 4027 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4028}
4029
4030static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4031 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4032 struct x86_exception *exception)
bbd9b64e
CO		 4033{
4034 void *data = val;
10589a46 4035 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4036
4037 while (bytes) {
14dfe855 4038 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4039 exception);
bbd9b64e 4040 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4041 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4042 int ret;
4043
bcc55cba 4044 if (gpa == UNMAPPED_GVA)
ab9ae313 4045 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4046 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4047 if (ret < 0) {
c3cd7ffa 4048 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4049 goto out;
4050 }
bbd9b64e 4051
77c2002e
IE		 4052 bytes -= toread;
4053 data += toread;
4054 addr += toread;
bbd9b64e 4055 }
10589a46 4056out:
10589a46 4057 return r;
bbd9b64e 4058}
77c2002e 4059
1871c602 4060/* used for instruction fetching */
0f65dd70
AK		 4061static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4062 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4063 struct x86_exception *exception)
1871c602 4064{
0f65dd70 4065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4066 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4067
1871c602 4068 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4069 access | PFERR_FETCH_MASK,
4070 exception);
1871c602
GN		 4071}
4072
064aea77 4073int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4074 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4075 struct x86_exception *exception)
1871c602 4076{
0f65dd70 4077 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4078 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4079
1871c602 4080 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4081 exception);
1871c602 4082}
064aea77 4083EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4084
0f65dd70
AK		 4085static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4086 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4087 struct x86_exception *exception)
1871c602 4088{
0f65dd70 4089 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4090 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4091}
4092
6a4d7550 4093int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4094 gva_t addr, void *val,
2dafc6c2 4095 unsigned int bytes,
bcc55cba 4096 struct x86_exception *exception)
77c2002e 4097{
0f65dd70 4098 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4099 void *data = val;
4100 int r = X86EMUL_CONTINUE;
4101
4102 while (bytes) {
14dfe855
JR		 4103 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4104 PFERR_WRITE_MASK,
ab9ae313 4105 exception);
77c2002e
IE		 4106 unsigned offset = addr & (PAGE_SIZE-1);
4107 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4108 int ret;
4109
bcc55cba 4110 if (gpa == UNMAPPED_GVA)
ab9ae313 4111 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4112 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4113 if (ret < 0) {
c3cd7ffa 4114 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4115 goto out;
4116 }
4117
4118 bytes -= towrite;
4119 data += towrite;
4120 addr += towrite;
4121 }
4122out:
4123 return r;
4124}
6a4d7550 4125EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4126
af7cc7d1
XG		 4127static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4128 gpa_t *gpa, struct x86_exception *exception,
4129 bool write)
4130{
97d64b78
AK		 4131 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4132 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4133
97d64b78
AK		 4134 if (vcpu_match_mmio_gva(vcpu, gva)
4135 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4136 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4137 (gva & (PAGE_SIZE - 1));
4f022648 4138 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4139 return 1;
4140 }
4141
af7cc7d1
XG		 4142 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4143
4144 if (*gpa == UNMAPPED_GVA)
4145 return -1;
4146
4147 /* For APIC access vmexit */
4148 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4149 return 1;
4150
4f022648
XG		 4151 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4152 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4153 return 1;
4f022648 4154 }
bebb106a 4155
af7cc7d1
XG		 4156 return 0;
4157}
4158
3200f405 4159int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4160 const void *val, int bytes)
bbd9b64e
CO		 4161{
4162 int ret;
4163
4164 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4165 if (ret < 0)
bbd9b64e 4166 return 0;
f57f2ef5 4167 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4168 return 1;
4169}
4170
77d197b2
XG		 4171struct read_write_emulator_ops {
4172 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4173 int bytes);
4174 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4175 void *val, int bytes);
4176 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4177 int bytes, void *val);
4178 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4179 void *val, int bytes);
4180 bool write;
4181};
4182
4183static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4184{
4185 if (vcpu->mmio_read_completed) {
77d197b2 4186 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4187 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4188 vcpu->mmio_read_completed = 0;
4189 return 1;
4190 }
4191
4192 return 0;
4193}
4194
4195static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4196 void *val, int bytes)
4197{
4198 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4199}
4200
4201static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4202 void *val, int bytes)
4203{
4204 return emulator_write_phys(vcpu, gpa, val, bytes);
4205}
4206
4207static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4208{
4209 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4210 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4211}
4212
4213static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4214 void *val, int bytes)
4215{
4216 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4217 return X86EMUL_IO_NEEDED;
4218}
4219
4220static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4221 void *val, int bytes)
4222{
f78146b0
AK		 4223 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4224
87da7e66 4225 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4226 return X86EMUL_CONTINUE;
4227}
4228
0fbe9b0b 4229static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4230 .read_write_prepare = read_prepare,
4231 .read_write_emulate = read_emulate,
4232 .read_write_mmio = vcpu_mmio_read,
4233 .read_write_exit_mmio = read_exit_mmio,
4234};
4235
0fbe9b0b 4236static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4237 .read_write_emulate = write_emulate,
4238 .read_write_mmio = write_mmio,
4239 .read_write_exit_mmio = write_exit_mmio,
4240 .write = true,
4241};
4242
22388a3c
XG		 4243static int emulator_read_write_onepage(unsigned long addr, void *val,
4244 unsigned int bytes,
4245 struct x86_exception *exception,
4246 struct kvm_vcpu *vcpu,
0fbe9b0b 4247 const struct read_write_emulator_ops *ops)
bbd9b64e 4248{
af7cc7d1
XG		 4249 gpa_t gpa;
4250 int handled, ret;
22388a3c 4251 bool write = ops->write;
f78146b0 4252 struct kvm_mmio_fragment *frag;
10589a46 4253
22388a3c 4254 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4255
af7cc7d1 4256 if (ret < 0)
bbd9b64e 4257 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4258
4259 /* For APIC access vmexit */
af7cc7d1 4260 if (ret)
bbd9b64e
CO		 4261 goto mmio;
4262
22388a3c 4263 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4264 return X86EMUL_CONTINUE;
4265
4266mmio:
4267 /*
4268 * Is this MMIO handled locally?
4269 */
22388a3c 4270 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4271 if (handled == bytes)
bbd9b64e 4272 return X86EMUL_CONTINUE;
bbd9b64e 4273
70252a10
AK		 4274 gpa += handled;
4275 bytes -= handled;
4276 val += handled;
4277
87da7e66
XG		 4278 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4279 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4280 frag->gpa = gpa;
4281 frag->data = val;
4282 frag->len = bytes;
f78146b0 4283 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4284}
4285
22388a3c
XG		 4286int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4287 void *val, unsigned int bytes,
4288 struct x86_exception *exception,
0fbe9b0b 4289 const struct read_write_emulator_ops *ops)
bbd9b64e 4290{
0f65dd70 4291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4292 gpa_t gpa;
4293 int rc;
4294
4295 if (ops->read_write_prepare &&
4296 ops->read_write_prepare(vcpu, val, bytes))
4297 return X86EMUL_CONTINUE;
4298
4299 vcpu->mmio_nr_fragments = 0;
0f65dd70 4300
bbd9b64e
CO		 4301 /* Crossing a page boundary? */
4302 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4303 int now;
bbd9b64e
CO		 4304
4305 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4306 rc = emulator_read_write_onepage(addr, val, now, exception,
4307 vcpu, ops);
4308
bbd9b64e
CO		 4309 if (rc != X86EMUL_CONTINUE)
4310 return rc;
4311 addr += now;
4312 val += now;
4313 bytes -= now;
4314 }
22388a3c 4315
f78146b0
AK		 4316 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4317 vcpu, ops);
4318 if (rc != X86EMUL_CONTINUE)
4319 return rc;
4320
4321 if (!vcpu->mmio_nr_fragments)
4322 return rc;
4323
4324 gpa = vcpu->mmio_fragments[0].gpa;
4325
4326 vcpu->mmio_needed = 1;
4327 vcpu->mmio_cur_fragment = 0;
4328
87da7e66 4329 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4330 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4331 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4332 vcpu->run->mmio.phys_addr = gpa;
4333
4334 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4335}
4336
4337static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4338 unsigned long addr,
4339 void *val,
4340 unsigned int bytes,
4341 struct x86_exception *exception)
4342{
4343 return emulator_read_write(ctxt, addr, val, bytes,
4344 exception, &read_emultor);
4345}
4346
4347int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4348 unsigned long addr,
4349 const void *val,
4350 unsigned int bytes,
4351 struct x86_exception *exception)
4352{
4353 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4354 exception, &write_emultor);
bbd9b64e 4355}
bbd9b64e 4356
daea3e73
AK		 4357#define CMPXCHG_TYPE(t, ptr, old, new) \
4358 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4359
4360#ifdef CONFIG_X86_64
4361# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4362#else
4363# define CMPXCHG64(ptr, old, new) \
9749a6c0 4364 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4365#endif
4366
0f65dd70
AK		 4367static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4368 unsigned long addr,
bbd9b64e
CO		 4369 const void *old,
4370 const void *new,
4371 unsigned int bytes,
0f65dd70 4372 struct x86_exception *exception)
bbd9b64e 4373{
0f65dd70 4374 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4375 gpa_t gpa;
4376 struct page *page;
4377 char *kaddr;
4378 bool exchanged;
2bacc55c 4379
daea3e73
AK		 4380 /* guests cmpxchg8b have to be emulated atomically */
4381 if (bytes > 8 || (bytes & (bytes - 1)))
4382 goto emul_write;
10589a46 4383
daea3e73 4384 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4385
daea3e73
AK		 4386 if (gpa == UNMAPPED_GVA ||
4387 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4388 goto emul_write;
2bacc55c 4389
daea3e73
AK		 4390 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4391 goto emul_write;
72dc67a6 4392
daea3e73 4393 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4394 if (is_error_page(page))
c19b8bd6 4395 goto emul_write;
72dc67a6 4396
8fd75e12 4397 kaddr = kmap_atomic(page);
daea3e73
AK		 4398 kaddr += offset_in_page(gpa);
4399 switch (bytes) {
4400 case 1:
4401 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4402 break;
4403 case 2:
4404 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4405 break;
4406 case 4:
4407 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4408 break;
4409 case 8:
4410 exchanged = CMPXCHG64(kaddr, old, new);
4411 break;
4412 default:
4413 BUG();
2bacc55c 4414 }
8fd75e12 4415 kunmap_atomic(kaddr);
daea3e73
AK		 4416 kvm_release_page_dirty(page);
4417
4418 if (!exchanged)
4419 return X86EMUL_CMPXCHG_FAILED;
4420
d3714010 4421 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4422 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4423
4424 return X86EMUL_CONTINUE;
4a5f48f6 4425
3200f405 4426emul_write:
daea3e73 4427 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4428
0f65dd70 4429 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4430}
4431
cf8f70bf
GN		 4432static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4433{
4434 /* TODO: String I/O for in kernel device */
4435 int r;
4436
4437 if (vcpu->arch.pio.in)
4438 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4439 vcpu->arch.pio.size, pd);
4440 else
4441 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4442 vcpu->arch.pio.port, vcpu->arch.pio.size,
4443 pd);
4444 return r;
4445}
4446
6f6fbe98
XG		 4447static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4448 unsigned short port, void *val,
4449 unsigned int count, bool in)
cf8f70bf 4450{
6f6fbe98 4451 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4452
4453 vcpu->arch.pio.port = port;
6f6fbe98 4454 vcpu->arch.pio.in = in;
7972995b 4455 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4456 vcpu->arch.pio.size = size;
4457
4458 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4459 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4460 return 1;
4461 }
4462
4463 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4464 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4465 vcpu->run->io.size = size;
4466 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4467 vcpu->run->io.count = count;
4468 vcpu->run->io.port = port;
4469
4470 return 0;
4471}
4472
6f6fbe98
XG		 4473static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4474 int size, unsigned short port, void *val,
4475 unsigned int count)
cf8f70bf 4476{
ca1d4a9e 4477 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4478 int ret;
ca1d4a9e 4479
6f6fbe98
XG		 4480 if (vcpu->arch.pio.count)
4481 goto data_avail;
cf8f70bf 4482
6f6fbe98
XG		 4483 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4484 if (ret) {
4485data_avail:
4486 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4487 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4488 return 1;
4489 }
4490
cf8f70bf
GN		 4491 return 0;
4492}
4493
6f6fbe98
XG		 4494static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4495 int size, unsigned short port,
4496 const void *val, unsigned int count)
4497{
4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4499
4500 memcpy(vcpu->arch.pio_data, val, size * count);
4501 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4502}
4503
bbd9b64e
CO		 4504static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4505{
4506 return kvm_x86_ops->get_segment_base(vcpu, seg);
4507}
4508
3cb16fe7 4509static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4510{
3cb16fe7 4511 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4512}
4513
f5f48ee1
SY		 4514int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4515{
4516 if (!need_emulate_wbinvd(vcpu))
4517 return X86EMUL_CONTINUE;
4518
4519 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4520 int cpu = get_cpu();
4521
4522 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4523 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4524 wbinvd_ipi, NULL, 1);
2eec7343 4525 put_cpu();
f5f48ee1 4526 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4527 } else
4528 wbinvd();
f5f48ee1
SY		 4529 return X86EMUL_CONTINUE;
4530}
4531EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4532
bcaf5cc5
AK		 4533static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4534{
4535 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4536}
4537
717746e3 4538int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4539{
717746e3 4540 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4541}
4542
717746e3 4543int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4544{
338dbc97 4545
717746e3 4546 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4547}
4548
52a46617 4549static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4550{
52a46617 4551 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4552}
4553
717746e3 4554static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4555{
717746e3 4556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4557 unsigned long value;
4558
4559 switch (cr) {
4560 case 0:
4561 value = kvm_read_cr0(vcpu);
4562 break;
4563 case 2:
4564 value = vcpu->arch.cr2;
4565 break;
4566 case 3:
9f8fe504 4567 value = kvm_read_cr3(vcpu);
52a46617
GN		 4568 break;
4569 case 4:
4570 value = kvm_read_cr4(vcpu);
4571 break;
4572 case 8:
4573 value = kvm_get_cr8(vcpu);
4574 break;
4575 default:
a737f256 4576 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4577 return 0;
4578 }
4579
4580 return value;
4581}
4582
717746e3 4583static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4584{
717746e3 4585 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4586 int res = 0;
4587
52a46617
GN		 4588 switch (cr) {
4589 case 0:
49a9b07e 4590 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4591 break;
4592 case 2:
4593 vcpu->arch.cr2 = val;
4594 break;
4595 case 3:
2390218b 4596 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4597 break;
4598 case 4:
a83b29c6 4599 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4600 break;
4601 case 8:
eea1cff9 4602 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4603 break;
4604 default:
a737f256 4605 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4606 res = -1;
52a46617 4607 }
0f12244f
GN		 4608
4609 return res;
52a46617
GN		 4610}
4611
4cee4798
KW		 4612static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4613{
4614 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4615}
4616
717746e3 4617static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4618{
717746e3 4619 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4620}
4621
4bff1e86 4622static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4623{
4bff1e86 4624 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4625}
4626
4bff1e86 4627static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4628{
4bff1e86 4629 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4630}
4631
1ac9d0cf
AK		 4632static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4633{
4634 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4635}
4636
4637static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4638{
4639 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4640}
4641
4bff1e86
AK		 4642static unsigned long emulator_get_cached_segment_base(
4643 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4644{
4bff1e86 4645 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4646}
4647
1aa36616
AK		 4648static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4649 struct desc_struct *desc, u32 *base3,
4650 int seg)
2dafc6c2
GN		 4651{
4652 struct kvm_segment var;
4653
4bff1e86 4654 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4655 *selector = var.selector;
2dafc6c2 4656
378a8b09
GN		 4657 if (var.unusable) {
4658 memset(desc, 0, sizeof(*desc));
2dafc6c2 4659 return false;
378a8b09 4660 }
2dafc6c2
GN		 4661
4662 if (var.g)
4663 var.limit >>= 12;
4664 set_desc_limit(desc, var.limit);
4665 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4666#ifdef CONFIG_X86_64
4667 if (base3)
4668 *base3 = var.base >> 32;
4669#endif
2dafc6c2
GN		 4670 desc->type = var.type;
4671 desc->s = var.s;
4672 desc->dpl = var.dpl;
4673 desc->p = var.present;
4674 desc->avl = var.avl;
4675 desc->l = var.l;
4676 desc->d = var.db;
4677 desc->g = var.g;
4678
4679 return true;
4680}
4681
1aa36616
AK		 4682static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4683 struct desc_struct *desc, u32 base3,
4684 int seg)
2dafc6c2 4685{
4bff1e86 4686 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4687 struct kvm_segment var;
4688
1aa36616 4689 var.selector = selector;
2dafc6c2 4690 var.base = get_desc_base(desc);
5601d05b
GN		 4691#ifdef CONFIG_X86_64
4692 var.base |= ((u64)base3) << 32;
4693#endif
2dafc6c2
GN		 4694 var.limit = get_desc_limit(desc);
4695 if (desc->g)
4696 var.limit = (var.limit << 12) | 0xfff;
4697 var.type = desc->type;
4698 var.present = desc->p;
4699 var.dpl = desc->dpl;
4700 var.db = desc->d;
4701 var.s = desc->s;
4702 var.l = desc->l;
4703 var.g = desc->g;
4704 var.avl = desc->avl;
4705 var.present = desc->p;
4706 var.unusable = !var.present;
4707 var.padding = 0;
4708
4709 kvm_set_segment(vcpu, &var, seg);
4710 return;
4711}
4712
717746e3
AK		 4713static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4714 u32 msr_index, u64 *pdata)
4715{
4716 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4717}
4718
4719static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4720 u32 msr_index, u64 data)
4721{
8fe8ab46
WA		 4722 struct msr_data msr;
4723
4724 msr.data = data;
4725 msr.index = msr_index;
4726 msr.host_initiated = false;
4727 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4728}
4729
222d21aa
AK		 4730static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4731 u32 pmc, u64 *pdata)
4732{
4733 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4734}
4735
6c3287f7
AK		 4736static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4737{
4738 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4739}
4740
5037f6f3
AK		 4741static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4742{
4743 preempt_disable();
5197b808 4744 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4745 /*
4746 * CR0.TS may reference the host fpu state, not the guest fpu state,
4747 * so it may be clear at this point.
4748 */
4749 clts();
4750}
4751
4752static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4753{
4754 preempt_enable();
4755}
4756
2953538e 4757static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4758 struct x86_instruction_info *info,
c4f035c6
AK		 4759 enum x86_intercept_stage stage)
4760{
2953538e 4761 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4762}
4763
0017f93a 4764static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4765 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4766{
0017f93a 4767 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4768}
4769
dd856efa
AK		 4770static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4771{
4772 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4773}
4774
4775static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4776{
4777 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4778}
4779
0225fb50 4780static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4781 .read_gpr = emulator_read_gpr,
4782 .write_gpr = emulator_write_gpr,
1871c602 4783 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4784 .write_std = kvm_write_guest_virt_system,
1871c602 4785 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4786 .read_emulated = emulator_read_emulated,
4787 .write_emulated = emulator_write_emulated,
4788 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4789 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4790 .pio_in_emulated = emulator_pio_in_emulated,
4791 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4792 .get_segment = emulator_get_segment,
4793 .set_segment = emulator_set_segment,
5951c442 4794 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4795 .get_gdt = emulator_get_gdt,
160ce1f1 4796 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4797 .set_gdt = emulator_set_gdt,
4798 .set_idt = emulator_set_idt,
52a46617
GN		 4799 .get_cr = emulator_get_cr,
4800 .set_cr = emulator_set_cr,
4cee4798 4801 .set_rflags = emulator_set_rflags,
9c537244 4802 .cpl = emulator_get_cpl,
35aa5375
GN		 4803 .get_dr = emulator_get_dr,
4804 .set_dr = emulator_set_dr,
717746e3
AK		 4805 .set_msr = emulator_set_msr,
4806 .get_msr = emulator_get_msr,
222d21aa 4807 .read_pmc = emulator_read_pmc,
6c3287f7 4808 .halt = emulator_halt,
bcaf5cc5 4809 .wbinvd = emulator_wbinvd,
d6aa1000 4810 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4811 .get_fpu = emulator_get_fpu,
4812 .put_fpu = emulator_put_fpu,
c4f035c6 4813 .intercept = emulator_intercept,
bdb42f5a 4814 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4815};
4816
95cb2295
GN		 4817static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4818{
4819 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4820 /*
4821 * an sti; sti; sequence only disable interrupts for the first
4822 * instruction. So, if the last instruction, be it emulated or
4823 * not, left the system with the INT_STI flag enabled, it
4824 * means that the last instruction is an sti. We should not
4825 * leave the flag on in this case. The same goes for mov ss
4826 */
4827 if (!(int_shadow & mask))
4828 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4829}
4830
54b8486f
GN		 4831static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4832{
4833 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4834 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4835 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4836 else if (ctxt->exception.error_code_valid)
4837 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4838 ctxt->exception.error_code);
54b8486f 4839 else
da9cb575 4840 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4841}
4842
dd856efa 4843static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4844{
1ce19dc1
BP		 4845 memset(&ctxt->opcode_len, 0,
4846 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4847
9dac77fa
AK		 4848 ctxt->fetch.start = 0;
4849 ctxt->fetch.end = 0;
4850 ctxt->io_read.pos = 0;
4851 ctxt->io_read.end = 0;
4852 ctxt->mem_read.pos = 0;
4853 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4854}
4855
8ec4722d
MG		 4856static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4857{
adf52235 4858 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4859 int cs_db, cs_l;
4860
8ec4722d
MG		 4861 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4862
adf52235
TY		 4863 ctxt->eflags = kvm_get_rflags(vcpu);
4864 ctxt->eip = kvm_rip_read(vcpu);
4865 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4866 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4867 cs_l ? X86EMUL_MODE_PROT64 :
4868 cs_db ? X86EMUL_MODE_PROT32 :
4869 X86EMUL_MODE_PROT16;
4870 ctxt->guest_mode = is_guest_mode(vcpu);
4871
dd856efa 4872 init_decode_cache(ctxt);
7ae441ea 4873 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4874}
4875
71f9833b 4876int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4877{
9d74191a 4878 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4879 int ret;
4880
4881 init_emulate_ctxt(vcpu);
4882
9dac77fa
AK		 4883 ctxt->op_bytes = 2;
4884 ctxt->ad_bytes = 2;
4885 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4886 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4887
4888 if (ret != X86EMUL_CONTINUE)
4889 return EMULATE_FAIL;
4890
9dac77fa 4891 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4892 kvm_rip_write(vcpu, ctxt->eip);
4893 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4894
4895 if (irq == NMI_VECTOR)
7460fb4a 4896 vcpu->arch.nmi_pending = 0;
63995653
MG		 4897 else
4898 vcpu->arch.interrupt.pending = false;
4899
4900 return EMULATE_DONE;
4901}
4902EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4903
6d77dbfc
GN		 4904static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4905{
fc3a9157
JR		 4906 int r = EMULATE_DONE;
4907
6d77dbfc
GN		 4908 ++vcpu->stat.insn_emulation_fail;
4909 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4910 if (!is_guest_mode(vcpu)) {
4911 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4912 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4913 vcpu->run->internal.ndata = 0;
4914 r = EMULATE_FAIL;
4915 }
6d77dbfc 4916 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4917
4918 return r;
6d77dbfc
GN		 4919}
4920
93c05d3e 4921static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4922 bool write_fault_to_shadow_pgtable,
4923 int emulation_type)
a6f177ef 4924{
95b3cf69 4925 gpa_t gpa = cr2;
8e3d9d06 4926 pfn_t pfn;
a6f177ef 4927
991eebf9
GN		 4928 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4929 return false;
4930
95b3cf69
XG		 4931 if (!vcpu->arch.mmu.direct_map) {
4932 /*
4933 * Write permission should be allowed since only
4934 * write access need to be emulated.
4935 */
4936 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4937
95b3cf69
XG		 4938 /*
4939 * If the mapping is invalid in guest, let cpu retry
4940 * it to generate fault.
4941 */
4942 if (gpa == UNMAPPED_GVA)
4943 return true;
4944 }
a6f177ef 4945
8e3d9d06
XG		 4946 /*
4947 * Do not retry the unhandleable instruction if it faults on the
4948 * readonly host memory, otherwise it will goto a infinite loop:
4949 * retry instruction -> write #PF -> emulation fail -> retry
4950 * instruction -> ...
4951 */
4952 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4953
4954 /*
4955 * If the instruction failed on the error pfn, it can not be fixed,
4956 * report the error to userspace.
4957 */
4958 if (is_error_noslot_pfn(pfn))
4959 return false;
4960
4961 kvm_release_pfn_clean(pfn);
4962
4963 /* The instructions are well-emulated on direct mmu. */
4964 if (vcpu->arch.mmu.direct_map) {
4965 unsigned int indirect_shadow_pages;
4966
4967 spin_lock(&vcpu->kvm->mmu_lock);
4968 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4969 spin_unlock(&vcpu->kvm->mmu_lock);
4970
4971 if (indirect_shadow_pages)
4972 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4973
a6f177ef 4974 return true;
8e3d9d06 4975 }
a6f177ef 4976
95b3cf69
XG		 4977 /*
4978 * if emulation was due to access to shadowed page table
4979 * and it failed try to unshadow page and re-enter the
4980 * guest to let CPU execute the instruction.
4981 */
4982 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4983
4984 /*
4985 * If the access faults on its page table, it can not
4986 * be fixed by unprotecting shadow page and it should
4987 * be reported to userspace.
4988 */
4989 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4990}
4991
1cb3f3ae
XG		 4992static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4993 unsigned long cr2, int emulation_type)
4994{
4995 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4996 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4997
4998 last_retry_eip = vcpu->arch.last_retry_eip;
4999 last_retry_addr = vcpu->arch.last_retry_addr;
5000
5001 /*
5002 * If the emulation is caused by #PF and it is non-page_table
5003 * writing instruction, it means the VM-EXIT is caused by shadow
5004 * page protected, we can zap the shadow page and retry this
5005 * instruction directly.
5006 *
5007 * Note: if the guest uses a non-page-table modifying instruction
5008 * on the PDE that points to the instruction, then we will unmap
5009 * the instruction and go to an infinite loop. So, we cache the
5010 * last retried eip and the last fault address, if we meet the eip
5011 * and the address again, we can break out of the potential infinite
5012 * loop.
5013 */
5014 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5015
5016 if (!(emulation_type & EMULTYPE_RETRY))
5017 return false;
5018
5019 if (x86_page_table_writing_insn(ctxt))
5020 return false;
5021
5022 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5023 return false;
5024
5025 vcpu->arch.last_retry_eip = ctxt->eip;
5026 vcpu->arch.last_retry_addr = cr2;
5027
5028 if (!vcpu->arch.mmu.direct_map)
5029 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5030
22368028 5031 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5032
5033 return true;
5034}
5035
716d51ab
GN		 5036static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5037static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5038
4a1e10d5
PB		 5039static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5040 unsigned long *db)
5041{
5042 u32 dr6 = 0;
5043 int i;
5044 u32 enable, rwlen;
5045
5046 enable = dr7;
5047 rwlen = dr7 >> 16;
5048 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5049 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5050 dr6 |= (1 << i);
5051 return dr6;
5052}
5053
663f4c61
PB		 5054static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5055{
5056 struct kvm_run *kvm_run = vcpu->run;
5057
5058 /*
5059 * Use the "raw" value to see if TF was passed to the processor.
5060 * Note that the new value of the flags has not been saved yet.
5061 *
5062 * This is correct even for TF set by the guest, because "the
5063 * processor will not generate this exception after the instruction
5064 * that sets the TF flag".
5065 */
5066 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5067
5068 if (unlikely(rflags & X86_EFLAGS_TF)) {
5069 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5070 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5071 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5072 kvm_run->debug.arch.exception = DB_VECTOR;
5073 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5074 *r = EMULATE_USER_EXIT;
5075 } else {
5076 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5077 /*
5078 * "Certain debug exceptions may clear bit 0-3. The
5079 * remaining contents of the DR6 register are never
5080 * cleared by the processor".
5081 */
5082 vcpu->arch.dr6 &= ~15;
5083 vcpu->arch.dr6 |= DR6_BS;
5084 kvm_queue_exception(vcpu, DB_VECTOR);
5085 }
5086 }
5087}
5088
4a1e10d5
PB		 5089static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5090{
5091 struct kvm_run *kvm_run = vcpu->run;
5092 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5093 u32 dr6 = 0;
5094
5095 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5096 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5097 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5098 vcpu->arch.guest_debug_dr7,
5099 vcpu->arch.eff_db);
5100
5101 if (dr6 != 0) {
5102 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5103 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5104 get_segment_base(vcpu, VCPU_SREG_CS);
5105
5106 kvm_run->debug.arch.exception = DB_VECTOR;
5107 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5108 *r = EMULATE_USER_EXIT;
5109 return true;
5110 }
5111 }
5112
5113 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5114 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5115 vcpu->arch.dr7,
5116 vcpu->arch.db);
5117
5118 if (dr6 != 0) {
5119 vcpu->arch.dr6 &= ~15;
5120 vcpu->arch.dr6 |= dr6;
5121 kvm_queue_exception(vcpu, DB_VECTOR);
5122 *r = EMULATE_DONE;
5123 return true;
5124 }
5125 }
5126
5127 return false;
5128}
5129
51d8b661
AP		 5130int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5131 unsigned long cr2,
dc25e89e
AP		 5132 int emulation_type,
5133 void *insn,
5134 int insn_len)
bbd9b64e 5135{
95cb2295 5136 int r;
9d74191a 5137 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5138 bool writeback = true;
93c05d3e 5139 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5140
93c05d3e
XG		 5141 /*
5142 * Clear write_fault_to_shadow_pgtable here to ensure it is
5143 * never reused.
5144 */
5145 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5146 kvm_clear_exception_queue(vcpu);
8d7d8102 5147
571008da 5148 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5149 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5150
5151 /*
5152 * We will reenter on the same instruction since
5153 * we do not set complete_userspace_io. This does not
5154 * handle watchpoints yet, those would be handled in
5155 * the emulate_ops.
5156 */
5157 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5158 return r;
5159
9d74191a
TY		 5160 ctxt->interruptibility = 0;
5161 ctxt->have_exception = false;
5162 ctxt->perm_ok = false;
bbd9b64e 5163
b51e974f 5164 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5165
9d74191a 5166 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5167
e46479f8 5168 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5169 ++vcpu->stat.insn_emulation;
1d2887e2 5170 if (r != EMULATION_OK) {
4005996e
AK		 5171 if (emulation_type & EMULTYPE_TRAP_UD)
5172 return EMULATE_FAIL;
991eebf9
GN		 5173 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5174 emulation_type))
bbd9b64e 5175 return EMULATE_DONE;
6d77dbfc
GN		 5176 if (emulation_type & EMULTYPE_SKIP)
5177 return EMULATE_FAIL;
5178 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5179 }
5180 }
5181
ba8afb6b 5182 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5183 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5184 return EMULATE_DONE;
5185 }
5186
1cb3f3ae
XG		 5187 if (retry_instruction(ctxt, cr2, emulation_type))
5188 return EMULATE_DONE;
5189
7ae441ea 5190 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5191 changes registers values during IO operation */
7ae441ea
GN		 5192 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5193 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5194 emulator_invalidate_register_cache(ctxt);
7ae441ea 5195 }
4d2179e1 5196
5cd21917 5197restart:
9d74191a 5198 r = x86_emulate_insn(ctxt);
bbd9b64e 5199
775fde86
JR		 5200 if (r == EMULATION_INTERCEPTED)
5201 return EMULATE_DONE;
5202
d2ddd1c4 5203 if (r == EMULATION_FAILED) {
991eebf9
GN		 5204 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5205 emulation_type))
c3cd7ffa
GN		 5206 return EMULATE_DONE;
5207
6d77dbfc 5208 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5209 }
5210
9d74191a 5211 if (ctxt->have_exception) {
54b8486f 5212 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5213 r = EMULATE_DONE;
5214 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5215 if (!vcpu->arch.pio.in) {
5216 /* FIXME: return into emulator if single-stepping. */
3457e419 5217 vcpu->arch.pio.count = 0;
0912c977 5218 } else {
7ae441ea 5219 writeback = false;
716d51ab
GN		 5220 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5221 }
ac0a48c3 5222 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5223 } else if (vcpu->mmio_needed) {
5224 if (!vcpu->mmio_is_write)
5225 writeback = false;
ac0a48c3 5226 r = EMULATE_USER_EXIT;
716d51ab 5227 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5228 } else if (r == EMULATION_RESTART)
5cd21917 5229 goto restart;
d2ddd1c4
GN		 5230 else
5231 r = EMULATE_DONE;
f850e2e6 5232
7ae441ea 5233 if (writeback) {
9d74191a 5234 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5235 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5236 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5237 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5238 if (r == EMULATE_DONE)
5239 kvm_vcpu_check_singlestep(vcpu, &r);
5240 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5241 } else
5242 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5243
5244 return r;
de7d789a 5245}
51d8b661 5246EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5247
cf8f70bf 5248int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5249{
cf8f70bf 5250 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5251 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5252 size, port, &val, 1);
cf8f70bf 5253 /* do not return to emulator after return from userspace */
7972995b 5254 vcpu->arch.pio.count = 0;
de7d789a
CO		 5255 return ret;
5256}
cf8f70bf 5257EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5258
8cfdc000
ZA		 5259static void tsc_bad(void *info)
5260{
0a3aee0d 5261 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5262}
5263
5264static void tsc_khz_changed(void *data)
c8076604 5265{
8cfdc000
ZA		 5266 struct cpufreq_freqs *freq = data;
5267 unsigned long khz = 0;
5268
5269 if (data)
5270 khz = freq->new;
5271 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5272 khz = cpufreq_quick_get(raw_smp_processor_id());
5273 if (!khz)
5274 khz = tsc_khz;
0a3aee0d 5275 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5276}
5277
c8076604
GH		 5278static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5279 void *data)
5280{
5281 struct cpufreq_freqs *freq = data;
5282 struct kvm *kvm;
5283 struct kvm_vcpu *vcpu;
5284 int i, send_ipi = 0;
5285
8cfdc000
ZA		 5286 /*
5287 * We allow guests to temporarily run on slowing clocks,
5288 * provided we notify them after, or to run on accelerating
5289 * clocks, provided we notify them before. Thus time never
5290 * goes backwards.
5291 *
5292 * However, we have a problem. We can't atomically update
5293 * the frequency of a given CPU from this function; it is
5294 * merely a notifier, which can be called from any CPU.
5295 * Changing the TSC frequency at arbitrary points in time
5296 * requires a recomputation of local variables related to
5297 * the TSC for each VCPU. We must flag these local variables
5298 * to be updated and be sure the update takes place with the
5299 * new frequency before any guests proceed.
5300 *
5301 * Unfortunately, the combination of hotplug CPU and frequency
5302 * change creates an intractable locking scenario; the order
5303 * of when these callouts happen is undefined with respect to
5304 * CPU hotplug, and they can race with each other. As such,
5305 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5306 * undefined; you can actually have a CPU frequency change take
5307 * place in between the computation of X and the setting of the
5308 * variable. To protect against this problem, all updates of
5309 * the per_cpu tsc_khz variable are done in an interrupt
5310 * protected IPI, and all callers wishing to update the value
5311 * must wait for a synchronous IPI to complete (which is trivial
5312 * if the caller is on the CPU already). This establishes the
5313 * necessary total order on variable updates.
5314 *
5315 * Note that because a guest time update may take place
5316 * anytime after the setting of the VCPU's request bit, the
5317 * correct TSC value must be set before the request. However,
5318 * to ensure the update actually makes it to any guest which
5319 * starts running in hardware virtualization between the set
5320 * and the acquisition of the spinlock, we must also ping the
5321 * CPU after setting the request bit.
5322 *
5323 */
5324
c8076604
GH		 5325 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5326 return 0;
5327 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5328 return 0;
8cfdc000
ZA		 5329
5330 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5331
2f303b74 5332 spin_lock(&kvm_lock);
c8076604 5333 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5334 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5335 if (vcpu->cpu != freq->cpu)
5336 continue;
c285545f 5337 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5338 if (vcpu->cpu != smp_processor_id())
8cfdc000 5339 send_ipi = 1;
c8076604
GH		 5340 }
5341 }
2f303b74 5342 spin_unlock(&kvm_lock);
c8076604
GH		 5343
5344 if (freq->old < freq->new && send_ipi) {
5345 /*
5346 * We upscale the frequency. Must make the guest
5347 * doesn't see old kvmclock values while running with
5348 * the new frequency, otherwise we risk the guest sees
5349 * time go backwards.
5350 *
5351 * In case we update the frequency for another cpu
5352 * (which might be in guest context) send an interrupt
5353 * to kick the cpu out of guest context. Next time
5354 * guest context is entered kvmclock will be updated,
5355 * so the guest will not see stale values.
5356 */
8cfdc000 5357 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5358 }
5359 return 0;
5360}
5361
5362static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5363 .notifier_call = kvmclock_cpufreq_notifier
5364};
5365
5366static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5367 unsigned long action, void *hcpu)
5368{
5369 unsigned int cpu = (unsigned long)hcpu;
5370
5371 switch (action) {
5372 case CPU_ONLINE:
5373 case CPU_DOWN_FAILED:
5374 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5375 break;
5376 case CPU_DOWN_PREPARE:
5377 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5378 break;
5379 }
5380 return NOTIFY_OK;
5381}
5382
5383static struct notifier_block kvmclock_cpu_notifier_block = {
5384 .notifier_call = kvmclock_cpu_notifier,
5385 .priority = -INT_MAX
c8076604
GH		 5386};
5387
b820cc0c
ZA		 5388static void kvm_timer_init(void)
5389{
5390 int cpu;
5391
c285545f 5392 max_tsc_khz = tsc_khz;
8cfdc000 5393 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5394 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5395#ifdef CONFIG_CPU_FREQ
5396 struct cpufreq_policy policy;
5397 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5398 cpu = get_cpu();
5399 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5400 if (policy.cpuinfo.max_freq)
5401 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5402 put_cpu();
c285545f 5403#endif
b820cc0c
ZA		 5404 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5405 CPUFREQ_TRANSITION_NOTIFIER);
5406 }
c285545f 5407 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5408 for_each_online_cpu(cpu)
5409 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5410}
5411
ff9d07a0
ZY		 5412static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5413
f5132b01 5414int kvm_is_in_guest(void)
ff9d07a0 5415{
086c9855 5416 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5417}
5418
5419static int kvm_is_user_mode(void)
5420{
5421 int user_mode = 3;
dcf46b94 5422
086c9855
AS		 5423 if (__this_cpu_read(current_vcpu))
5424 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5425
ff9d07a0
ZY		 5426 return user_mode != 0;
5427}
5428
5429static unsigned long kvm_get_guest_ip(void)
5430{
5431 unsigned long ip = 0;
dcf46b94 5432
086c9855
AS		 5433 if (__this_cpu_read(current_vcpu))
5434 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5435
ff9d07a0
ZY		 5436 return ip;
5437}
5438
5439static struct perf_guest_info_callbacks kvm_guest_cbs = {
5440 .is_in_guest = kvm_is_in_guest,
5441 .is_user_mode = kvm_is_user_mode,
5442 .get_guest_ip = kvm_get_guest_ip,
5443};
5444
5445void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5446{
086c9855 5447 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5448}
5449EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5450
5451void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5452{
086c9855 5453 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5454}
5455EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5456
ce88decf
XG		 5457static void kvm_set_mmio_spte_mask(void)
5458{
5459 u64 mask;
5460 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5461
5462 /*
5463 * Set the reserved bits and the present bit of an paging-structure
5464 * entry to generate page fault with PFER.RSV = 1.
5465 */
885032b9
XG		 5466 /* Mask the reserved physical address bits. */
5467 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5468
5469 /* Bit 62 is always reserved for 32bit host. */
5470 mask |= 0x3ull << 62;
5471
5472 /* Set the present bit. */
ce88decf
XG		 5473 mask |= 1ull;
5474
5475#ifdef CONFIG_X86_64
5476 /*
5477 * If reserved bit is not supported, clear the present bit to disable
5478 * mmio page fault.
5479 */
5480 if (maxphyaddr == 52)
5481 mask &= ~1ull;
5482#endif
5483
5484 kvm_mmu_set_mmio_spte_mask(mask);
5485}
5486
16e8d74d
MT		 5487#ifdef CONFIG_X86_64
5488static void pvclock_gtod_update_fn(struct work_struct *work)
5489{
d828199e
MT		 5490 struct kvm *kvm;
5491
5492 struct kvm_vcpu *vcpu;
5493 int i;
5494
2f303b74 5495 spin_lock(&kvm_lock);
d828199e
MT		 5496 list_for_each_entry(kvm, &vm_list, vm_list)
5497 kvm_for_each_vcpu(i, vcpu, kvm)
5498 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5499 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5500 spin_unlock(&kvm_lock);
16e8d74d
MT		 5501}
5502
5503static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5504
5505/*
5506 * Notification about pvclock gtod data update.
5507 */
5508static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5509 void *priv)
5510{
5511 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5512 struct timekeeper *tk = priv;
5513
5514 update_pvclock_gtod(tk);
5515
5516 /* disable master clock if host does not trust, or does not
5517 * use, TSC clocksource
5518 */
5519 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5520 atomic_read(&kvm_guest_has_master_clock) != 0)
5521 queue_work(system_long_wq, &pvclock_gtod_work);
5522
5523 return 0;
5524}
5525
5526static struct notifier_block pvclock_gtod_notifier = {
5527 .notifier_call = pvclock_gtod_notify,
5528};
5529#endif
5530
f8c16bba 5531int kvm_arch_init(void *opaque)
043405e1 5532{
b820cc0c 5533 int r;
6b61edf7 5534 struct kvm_x86_ops *ops = opaque;
f8c16bba 5535
f8c16bba
ZX		 5536 if (kvm_x86_ops) {
5537 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5538 r = -EEXIST;
5539 goto out;
f8c16bba
ZX		 5540 }
5541
5542 if (!ops->cpu_has_kvm_support()) {
5543 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5544 r = -EOPNOTSUPP;
5545 goto out;
f8c16bba
ZX		 5546 }
5547 if (ops->disabled_by_bios()) {
5548 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5549 r = -EOPNOTSUPP;
5550 goto out;
f8c16bba
ZX		 5551 }
5552
013f6a5d
MT		 5553 r = -ENOMEM;
5554 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5555 if (!shared_msrs) {
5556 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5557 goto out;
5558 }
5559
97db56ce
AK		 5560 r = kvm_mmu_module_init();
5561 if (r)
013f6a5d 5562 goto out_free_percpu;
97db56ce 5563
ce88decf 5564 kvm_set_mmio_spte_mask();
97db56ce
AK		 5565 kvm_init_msr_list();
5566
f8c16bba 5567 kvm_x86_ops = ops;
7b52345e 5568 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5569 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5570
b820cc0c 5571 kvm_timer_init();
c8076604 5572
ff9d07a0
ZY		 5573 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5574
2acf923e
DC		 5575 if (cpu_has_xsave)
5576 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5577
c5cc421b 5578 kvm_lapic_init();
16e8d74d
MT		 5579#ifdef CONFIG_X86_64
5580 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5581#endif
5582
f8c16bba 5583 return 0;
56c6d28a 5584
013f6a5d
MT		 5585out_free_percpu:
5586 free_percpu(shared_msrs);
56c6d28a 5587out:
56c6d28a 5588 return r;
043405e1 5589}
8776e519 5590
f8c16bba
ZX		 5591void kvm_arch_exit(void)
5592{
ff9d07a0
ZY		 5593 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5594
888d256e
JK		 5595 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5596 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5597 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5598 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5599#ifdef CONFIG_X86_64
5600 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5601#endif
f8c16bba 5602 kvm_x86_ops = NULL;
56c6d28a 5603 kvm_mmu_module_exit();
013f6a5d 5604 free_percpu(shared_msrs);
56c6d28a 5605}
f8c16bba 5606
8776e519
HB		 5607int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5608{
5609 ++vcpu->stat.halt_exits;
5610 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5611 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5612 return 1;
5613 } else {
5614 vcpu->run->exit_reason = KVM_EXIT_HLT;
5615 return 0;
5616 }
5617}
5618EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5619
55cd8e5a
GN		 5620int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5621{
5622 u64 param, ingpa, outgpa, ret;
5623 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5624 bool fast, longmode;
5625 int cs_db, cs_l;
5626
5627 /*
5628 * hypercall generates UD from non zero cpl and real mode
5629 * per HYPER-V spec
5630 */
3eeb3288 5631 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5632 kvm_queue_exception(vcpu, UD_VECTOR);
5633 return 0;
5634 }
5635
5636 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5637 longmode = is_long_mode(vcpu) && cs_l == 1;
5638
5639 if (!longmode) {
ccd46936
GN		 5640 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5641 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5642 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5643 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5644 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5645 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5646 }
5647#ifdef CONFIG_X86_64
5648 else {
5649 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5650 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5651 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5652 }
5653#endif
5654
5655 code = param & 0xffff;
5656 fast = (param >> 16) & 0x1;
5657 rep_cnt = (param >> 32) & 0xfff;
5658 rep_idx = (param >> 48) & 0xfff;
5659
5660 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5661
c25bc163
GN		 5662 switch (code) {
5663 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5664 kvm_vcpu_on_spin(vcpu);
5665 break;
5666 default:
5667 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5668 break;
5669 }
55cd8e5a
GN		 5670
5671 ret = res | (((u64)rep_done & 0xfff) << 32);
5672 if (longmode) {
5673 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5674 } else {
5675 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5676 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5677 }
5678
5679 return 1;
5680}
5681
6aef266c
SV		 5682/*
5683 * kvm_pv_kick_cpu_op: Kick a vcpu.
5684 *
5685 * @apicid - apicid of vcpu to be kicked.
5686 */
5687static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5688{
24d2166b 5689 struct kvm_lapic_irq lapic_irq;
6aef266c 5690
24d2166b
R		 5691 lapic_irq.shorthand = 0;
5692 lapic_irq.dest_mode = 0;
5693 lapic_irq.dest_id = apicid;
6aef266c 5694
24d2166b
R		 5695 lapic_irq.delivery_mode = APIC_DM_REMRD;
5696 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5697}
5698
8776e519
HB		 5699int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5700{
5701 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5702 int r = 1;
8776e519 5703
55cd8e5a
GN		 5704 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5705 return kvm_hv_hypercall(vcpu);
5706
5fdbf976
MT		 5707 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5708 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5709 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5710 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5711 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5712
229456fc 5713 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5714
8776e519
HB		 5715 if (!is_long_mode(vcpu)) {
5716 nr &= 0xFFFFFFFF;
5717 a0 &= 0xFFFFFFFF;
5718 a1 &= 0xFFFFFFFF;
5719 a2 &= 0xFFFFFFFF;
5720 a3 &= 0xFFFFFFFF;
5721 }
5722
07708c4a
JK		 5723 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5724 ret = -KVM_EPERM;
5725 goto out;
5726 }
5727
8776e519 5728 switch (nr) {
b93463aa
AK		 5729 case KVM_HC_VAPIC_POLL_IRQ:
5730 ret = 0;
5731 break;
6aef266c
SV		 5732 case KVM_HC_KICK_CPU:
5733 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5734 ret = 0;
5735 break;
8776e519
HB		 5736 default:
5737 ret = -KVM_ENOSYS;
5738 break;
5739 }
07708c4a 5740out:
5fdbf976 5741 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5742 ++vcpu->stat.hypercalls;
2f333bcb 5743 return r;
8776e519
HB		 5744}
5745EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5746
b6785def 5747static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5748{
d6aa1000 5749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5750 char instruction[3];
5fdbf976 5751 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5752
8776e519 5753 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5754
9d74191a 5755 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5756}
5757
b6c7a5dc
HB		 5758/*
5759 * Check if userspace requested an interrupt window, and that the
5760 * interrupt window is open.
5761 *
5762 * No need to exit to userspace if we already have an interrupt queued.
5763 */
851ba692 5764static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5765{
8061823a 5766 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5767 vcpu->run->request_interrupt_window &&
5df56646 5768 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5769}
5770
851ba692 5771static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5772{
851ba692
AK		 5773 struct kvm_run *kvm_run = vcpu->run;
5774
91586a3b 5775 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5776 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5777 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5778 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5779 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5780 else
b6c7a5dc 5781 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5782 kvm_arch_interrupt_allowed(vcpu) &&
5783 !kvm_cpu_has_interrupt(vcpu) &&
5784 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5785}
5786
95ba8273
GN		 5787static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5788{
5789 int max_irr, tpr;
5790
5791 if (!kvm_x86_ops->update_cr8_intercept)
5792 return;
5793
88c808fd
AK		 5794 if (!vcpu->arch.apic)
5795 return;
5796
8db3baa2
GN		 5797 if (!vcpu->arch.apic->vapic_addr)
5798 max_irr = kvm_lapic_find_highest_irr(vcpu);
5799 else
5800 max_irr = -1;
95ba8273
GN		 5801
5802 if (max_irr != -1)
5803 max_irr >>= 4;
5804
5805 tpr = kvm_lapic_get_cr8(vcpu);
5806
5807 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5808}
5809
851ba692 5810static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5811{
5812 /* try to reinject previous events if any */
b59bb7bd 5813 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5814 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5815 vcpu->arch.exception.has_error_code,
5816 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5817 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5818 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5819 vcpu->arch.exception.error_code,
5820 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5821 return;
5822 }
5823
95ba8273
GN		 5824 if (vcpu->arch.nmi_injected) {
5825 kvm_x86_ops->set_nmi(vcpu);
5826 return;
5827 }
5828
5829 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5830 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5831 return;
5832 }
5833
5834 /* try to inject new event if pending */
5835 if (vcpu->arch.nmi_pending) {
5836 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5837 --vcpu->arch.nmi_pending;
95ba8273
GN		 5838 vcpu->arch.nmi_injected = true;
5839 kvm_x86_ops->set_nmi(vcpu);
5840 }
c7c9c56c 5841 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5842 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5843 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5844 false);
5845 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5846 }
5847 }
5848}
5849
7460fb4a
AK		 5850static void process_nmi(struct kvm_vcpu *vcpu)
5851{
5852 unsigned limit = 2;
5853
5854 /*
5855 * x86 is limited to one NMI running, and one NMI pending after it.
5856 * If an NMI is already in progress, limit further NMIs to just one.
5857 * Otherwise, allow two (and we'll inject the first one immediately).
5858 */
5859 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5860 limit = 1;
5861
5862 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5863 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5864 kvm_make_request(KVM_REQ_EVENT, vcpu);
5865}
5866
3d81bc7e 5867static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5868{
5869 u64 eoi_exit_bitmap[4];
cf9e65b7 5870 u32 tmr[8];
c7c9c56c 5871
3d81bc7e
YZ		 5872 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5873 return;
c7c9c56c
YZ		 5874
5875 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5876 memset(tmr, 0, 32);
c7c9c56c 5877
cf9e65b7 5878 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5879 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5880 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5881}
5882
9357d939
TY		 5883/*
5884 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5885 * exiting to the userspace. Otherwise, the value will be returned to the
5886 * userspace.
5887 */
851ba692 5888static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5889{
5890 int r;
6a8b1d13 5891 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5892 vcpu->run->request_interrupt_window;
730dca42 5893 bool req_immediate_exit = false;
b6c7a5dc 5894
3e007509 5895 if (vcpu->requests) {
a8eeb04a 5896 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5897 kvm_mmu_unload(vcpu);
a8eeb04a 5898 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5899 __kvm_migrate_timers(vcpu);
d828199e
MT		 5900 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5901 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5902 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5903 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5904 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5905 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5906 if (unlikely(r))
5907 goto out;
5908 }
a8eeb04a 5909 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5910 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5911 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5912 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5913 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5914 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5915 r = 0;
5916 goto out;
5917 }
a8eeb04a 5918 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5919 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5920 r = 0;
5921 goto out;
5922 }
a8eeb04a 5923 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5924 vcpu->fpu_active = 0;
5925 kvm_x86_ops->fpu_deactivate(vcpu);
5926 }
af585b92
GN		 5927 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5928 /* Page is swapped out. Do synthetic halt */
5929 vcpu->arch.apf.halted = true;
5930 r = 1;
5931 goto out;
5932 }
c9aaa895
GC		 5933 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5934 record_steal_time(vcpu);
7460fb4a
AK		 5935 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5936 process_nmi(vcpu);
f5132b01
GN		 5937 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5938 kvm_handle_pmu_event(vcpu);
5939 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5940 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5941 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5942 vcpu_scan_ioapic(vcpu);
2f52d58c 5943 }
b93463aa 5944
b463a6f7 5945 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5946 kvm_apic_accept_events(vcpu);
5947 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5948 r = 1;
5949 goto out;
5950 }
5951
b463a6f7
AK		 5952 inject_pending_event(vcpu);
5953
5954 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5955 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5956 req_immediate_exit =
5957 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5958 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5959 req_immediate_exit =
5960 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5961
5962 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5963 /*
5964 * Update architecture specific hints for APIC
5965 * virtual interrupt delivery.
5966 */
5967 if (kvm_x86_ops->hwapic_irr_update)
5968 kvm_x86_ops->hwapic_irr_update(vcpu,
5969 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5970 update_cr8_intercept(vcpu);
5971 kvm_lapic_sync_to_vapic(vcpu);
5972 }
5973 }
5974
d8368af8
AK		 5975 r = kvm_mmu_reload(vcpu);
5976 if (unlikely(r)) {
d905c069 5977 goto cancel_injection;
d8368af8
AK		 5978 }
5979
b6c7a5dc
HB		 5980 preempt_disable();
5981
5982 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5983 if (vcpu->fpu_active)
5984 kvm_load_guest_fpu(vcpu);
2acf923e 5985 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5986
6b7e2d09
XG		 5987 vcpu->mode = IN_GUEST_MODE;
5988
01b71917
MT		 5989 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5990
6b7e2d09
XG		 5991 /* We should set ->mode before check ->requests,
5992 * see the comment in make_all_cpus_request.
5993 */
01b71917 5994 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5995
d94e1dc9 5996 local_irq_disable();
32f88400 5997
6b7e2d09 5998 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5999 || need_resched() || signal_pending(current)) {
6b7e2d09 6000 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6001 smp_wmb();
6c142801
AK		 6002 local_irq_enable();
6003 preempt_enable();
01b71917 6004 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6005 r = 1;
d905c069 6006 goto cancel_injection;
6c142801
AK		 6007 }
6008
d6185f20
NHE		 6009 if (req_immediate_exit)
6010 smp_send_reschedule(vcpu->cpu);
6011
b6c7a5dc
HB		 6012 kvm_guest_enter();
6013
42dbaa5a 6014 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6015 set_debugreg(0, 7);
6016 set_debugreg(vcpu->arch.eff_db[0], 0);
6017 set_debugreg(vcpu->arch.eff_db[1], 1);
6018 set_debugreg(vcpu->arch.eff_db[2], 2);
6019 set_debugreg(vcpu->arch.eff_db[3], 3);
6020 }
b6c7a5dc 6021
229456fc 6022 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6023 kvm_x86_ops->run(vcpu);
b6c7a5dc 6024
24f1e32c
FW		 6025 /*
6026 * If the guest has used debug registers, at least dr7
6027 * will be disabled while returning to the host.
6028 * If we don't have active breakpoints in the host, we don't
6029 * care about the messed up debug address registers. But if
6030 * we have some of them active, restore the old state.
6031 */
59d8eb53 6032 if (hw_breakpoint_active())
24f1e32c 6033 hw_breakpoint_restore();
42dbaa5a 6034
886b470c
MT		 6035 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6036 native_read_tsc());
1d5f066e 6037
6b7e2d09 6038 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6039 smp_wmb();
a547c6db
YZ		 6040
6041 /* Interrupt is enabled by handle_external_intr() */
6042 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6043
6044 ++vcpu->stat.exits;
6045
6046 /*
6047 * We must have an instruction between local_irq_enable() and
6048 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6049 * the interrupt shadow. The stat.exits increment will do nicely.
6050 * But we need to prevent reordering, hence this barrier():
6051 */
6052 barrier();
6053
6054 kvm_guest_exit();
6055
6056 preempt_enable();
6057
f656ce01 6058 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6059
b6c7a5dc
HB		 6060 /*
6061 * Profile KVM exit RIPs:
6062 */
6063 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6064 unsigned long rip = kvm_rip_read(vcpu);
6065 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6066 }
6067
cc578287
ZA		 6068 if (unlikely(vcpu->arch.tsc_always_catchup))
6069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6070
5cfb1d5a
MT		 6071 if (vcpu->arch.apic_attention)
6072 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6073
851ba692 6074 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6075 return r;
6076
6077cancel_injection:
6078 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6079 if (unlikely(vcpu->arch.apic_attention))
6080 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6081out:
6082 return r;
6083}
b6c7a5dc 6084
09cec754 6085
851ba692 6086static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6087{
6088 int r;
f656ce01 6089 struct kvm *kvm = vcpu->kvm;
d7690175 6090
f656ce01 6091 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6092
6093 r = 1;
6094 while (r > 0) {
af585b92
GN		 6095 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6096 !vcpu->arch.apf.halted)
851ba692 6097 r = vcpu_enter_guest(vcpu);
d7690175 6098 else {
f656ce01 6099 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6100 kvm_vcpu_block(vcpu);
f656ce01 6101 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6102 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6103 kvm_apic_accept_events(vcpu);
09cec754
GN		 6104 switch(vcpu->arch.mp_state) {
6105 case KVM_MP_STATE_HALTED:
6aef266c 6106 vcpu->arch.pv.pv_unhalted = false;
d7690175 6107 vcpu->arch.mp_state =
09cec754
GN		 6108 KVM_MP_STATE_RUNNABLE;
6109 case KVM_MP_STATE_RUNNABLE:
af585b92 6110 vcpu->arch.apf.halted = false;
09cec754 6111 break;
66450a21
JK		 6112 case KVM_MP_STATE_INIT_RECEIVED:
6113 break;
09cec754
GN		 6114 default:
6115 r = -EINTR;
6116 break;
6117 }
6118 }
d7690175
MT		 6119 }
6120
09cec754
GN		 6121 if (r <= 0)
6122 break;
6123
6124 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6125 if (kvm_cpu_has_pending_timer(vcpu))
6126 kvm_inject_pending_timer_irqs(vcpu);
6127
851ba692 6128 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6129 r = -EINTR;
851ba692 6130 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6131 ++vcpu->stat.request_irq_exits;
6132 }
af585b92
GN		 6133
6134 kvm_check_async_pf_completion(vcpu);
6135
09cec754
GN		 6136 if (signal_pending(current)) {
6137 r = -EINTR;
851ba692 6138 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6139 ++vcpu->stat.signal_exits;
6140 }
6141 if (need_resched()) {
f656ce01 6142 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6143 cond_resched();
f656ce01 6144 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6145 }
b6c7a5dc
HB		 6146 }
6147
f656ce01 6148 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6149
6150 return r;
6151}
6152
716d51ab
GN		 6153static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6154{
6155 int r;
6156 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6157 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6158 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6159 if (r != EMULATE_DONE)
6160 return 0;
6161 return 1;
6162}
6163
6164static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6165{
6166 BUG_ON(!vcpu->arch.pio.count);
6167
6168 return complete_emulated_io(vcpu);
6169}
6170
f78146b0
AK		 6171/*
6172 * Implements the following, as a state machine:
6173 *
6174 * read:
6175 * for each fragment
87da7e66
XG		 6176 * for each mmio piece in the fragment
6177 * write gpa, len
6178 * exit
6179 * copy data
f78146b0
AK		 6180 * execute insn
6181 *
6182 * write:
6183 * for each fragment
87da7e66
XG		 6184 * for each mmio piece in the fragment
6185 * write gpa, len
6186 * copy data
6187 * exit
f78146b0 6188 */
716d51ab 6189static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6190{
6191 struct kvm_run *run = vcpu->run;
f78146b0 6192 struct kvm_mmio_fragment *frag;
87da7e66 6193 unsigned len;
5287f194 6194
716d51ab 6195 BUG_ON(!vcpu->mmio_needed);
5287f194 6196
716d51ab 6197 /* Complete previous fragment */
87da7e66
XG		 6198 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6199 len = min(8u, frag->len);
716d51ab 6200 if (!vcpu->mmio_is_write)
87da7e66
XG		 6201 memcpy(frag->data, run->mmio.data, len);
6202
6203 if (frag->len <= 8) {
6204 /* Switch to the next fragment. */
6205 frag++;
6206 vcpu->mmio_cur_fragment++;
6207 } else {
6208 /* Go forward to the next mmio piece. */
6209 frag->data += len;
6210 frag->gpa += len;
6211 frag->len -= len;
6212 }
6213
716d51ab
GN		 6214 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6215 vcpu->mmio_needed = 0;
0912c977
PB		 6216
6217 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6218 if (vcpu->mmio_is_write)
716d51ab
GN		 6219 return 1;
6220 vcpu->mmio_read_completed = 1;
6221 return complete_emulated_io(vcpu);
6222 }
87da7e66 6223
716d51ab
GN		 6224 run->exit_reason = KVM_EXIT_MMIO;
6225 run->mmio.phys_addr = frag->gpa;
6226 if (vcpu->mmio_is_write)
87da7e66
XG		 6227 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6228 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6229 run->mmio.is_write = vcpu->mmio_is_write;
6230 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6231 return 0;
5287f194
AK		 6232}
6233
716d51ab 6234
b6c7a5dc
HB		 6235int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6236{
6237 int r;
6238 sigset_t sigsaved;
6239
e5c30142
AK		 6240 if (!tsk_used_math(current) && init_fpu(current))
6241 return -ENOMEM;
6242
ac9f6dc0
AK		 6243 if (vcpu->sigset_active)
6244 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6245
a4535290 6246 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6247 kvm_vcpu_block(vcpu);
66450a21 6248 kvm_apic_accept_events(vcpu);
d7690175 6249 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6250 r = -EAGAIN;
6251 goto out;
b6c7a5dc
HB		 6252 }
6253
b6c7a5dc 6254 /* re-sync apic's tpr */
eea1cff9
AP		 6255 if (!irqchip_in_kernel(vcpu->kvm)) {
6256 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6257 r = -EINVAL;
6258 goto out;
6259 }
6260 }
b6c7a5dc 6261
716d51ab
GN		 6262 if (unlikely(vcpu->arch.complete_userspace_io)) {
6263 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6264 vcpu->arch.complete_userspace_io = NULL;
6265 r = cui(vcpu);
6266 if (r <= 0)
6267 goto out;
6268 } else
6269 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6270
851ba692 6271 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6272
6273out:
f1d86e46 6274 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6275 if (vcpu->sigset_active)
6276 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6277
b6c7a5dc
HB		 6278 return r;
6279}
6280
6281int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6282{
7ae441ea
GN		 6283 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6284 /*
6285 * We are here if userspace calls get_regs() in the middle of
6286 * instruction emulation. Registers state needs to be copied
4a969980 6287 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6288 * that usually, but some bad designed PV devices (vmware
6289 * backdoor interface) need this to work
6290 */
dd856efa 6291 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6292 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6293 }
5fdbf976
MT		 6294 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6295 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6296 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6297 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6298 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6299 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6300 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6301 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6302#ifdef CONFIG_X86_64
5fdbf976
MT		 6303 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6304 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6305 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6306 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6307 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6308 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6309 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6310 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6311#endif
6312
5fdbf976 6313 regs->rip = kvm_rip_read(vcpu);
91586a3b 6314 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6315
b6c7a5dc
HB		 6316 return 0;
6317}
6318
6319int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6320{
7ae441ea
GN		 6321 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6322 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6323
5fdbf976
MT		 6324 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6325 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6326 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6327 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6328 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6329 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6330 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6331 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6332#ifdef CONFIG_X86_64
5fdbf976
MT		 6333 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6334 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6335 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6336 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6337 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6338 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6339 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6340 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6341#endif
6342
5fdbf976 6343 kvm_rip_write(vcpu, regs->rip);
91586a3b 6344 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6345
b4f14abd
JK		 6346 vcpu->arch.exception.pending = false;
6347
3842d135
AK		 6348 kvm_make_request(KVM_REQ_EVENT, vcpu);
6349
b6c7a5dc
HB		 6350 return 0;
6351}
6352
b6c7a5dc
HB		 6353void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6354{
6355 struct kvm_segment cs;
6356
3e6e0aab 6357 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6358 *db = cs.db;
6359 *l = cs.l;
6360}
6361EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6362
6363int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6364 struct kvm_sregs *sregs)
6365{
89a27f4d 6366 struct desc_ptr dt;
b6c7a5dc 6367
3e6e0aab
GT		 6368 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6369 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6370 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6371 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6372 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6373 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6374
3e6e0aab
GT		 6375 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6376 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6377
6378 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6379 sregs->idt.limit = dt.size;
6380 sregs->idt.base = dt.address;
b6c7a5dc 6381 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6382 sregs->gdt.limit = dt.size;
6383 sregs->gdt.base = dt.address;
b6c7a5dc 6384
4d4ec087 6385 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6386 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6387 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6388 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6389 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6390 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6391 sregs->apic_base = kvm_get_apic_base(vcpu);
6392
923c61bb 6393 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6394
36752c9b 6395 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6396 set_bit(vcpu->arch.interrupt.nr,
6397 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6398
b6c7a5dc
HB		 6399 return 0;
6400}
6401
62d9f0db
MT		 6402int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6403 struct kvm_mp_state *mp_state)
6404{
66450a21 6405 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6406 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6407 vcpu->arch.pv.pv_unhalted)
6408 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6409 else
6410 mp_state->mp_state = vcpu->arch.mp_state;
6411
62d9f0db
MT		 6412 return 0;
6413}
6414
6415int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6416 struct kvm_mp_state *mp_state)
6417{
66450a21
JK		 6418 if (!kvm_vcpu_has_lapic(vcpu) &&
6419 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6420 return -EINVAL;
6421
6422 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6423 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6424 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6425 } else
6426 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6427 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6428 return 0;
6429}
6430
7f3d35fd
KW		 6431int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6432 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6433{
9d74191a 6434 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6435 int ret;
e01c2426 6436
8ec4722d 6437 init_emulate_ctxt(vcpu);
c697518a 6438
7f3d35fd 6439 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6440 has_error_code, error_code);
c697518a 6441
c697518a 6442 if (ret)
19d04437 6443 return EMULATE_FAIL;
37817f29 6444
9d74191a
TY		 6445 kvm_rip_write(vcpu, ctxt->eip);
6446 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6447 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6448 return EMULATE_DONE;
37817f29
IE		 6449}
6450EXPORT_SYMBOL_GPL(kvm_task_switch);
6451
b6c7a5dc
HB		 6452int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6453 struct kvm_sregs *sregs)
6454{
58cb628d 6455 struct msr_data apic_base_msr;
b6c7a5dc 6456 int mmu_reset_needed = 0;
63f42e02 6457 int pending_vec, max_bits, idx;
89a27f4d 6458 struct desc_ptr dt;
b6c7a5dc 6459
6d1068b3
PM		 6460 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6461 return -EINVAL;
6462
89a27f4d
GN		 6463 dt.size = sregs->idt.limit;
6464 dt.address = sregs->idt.base;
b6c7a5dc 6465 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6466 dt.size = sregs->gdt.limit;
6467 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6468 kvm_x86_ops->set_gdt(vcpu, &dt);
6469
ad312c7c 6470 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6471 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6472 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6473 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6474
2d3ad1f4 6475 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6476
f6801dff 6477 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6478 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6479 apic_base_msr.data = sregs->apic_base;
6480 apic_base_msr.host_initiated = true;
6481 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6482
4d4ec087 6483 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6484 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6485 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6486
fc78f519 6487 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6488 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6489 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6490 kvm_update_cpuid(vcpu);
63f42e02
XG		 6491
6492 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6493 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6494 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6495 mmu_reset_needed = 1;
6496 }
63f42e02 6497 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6498
6499 if (mmu_reset_needed)
6500 kvm_mmu_reset_context(vcpu);
6501
a50abc3b 6502 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6503 pending_vec = find_first_bit(
6504 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6505 if (pending_vec < max_bits) {
66fd3f7f 6506 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6507 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6508 }
6509
3e6e0aab
GT		 6510 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6511 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6512 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6513 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6514 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6515 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6516
3e6e0aab
GT		 6517 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6518 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6519
5f0269f5
ME		 6520 update_cr8_intercept(vcpu);
6521
9c3e4aab 6522 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6523 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6524 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6525 !is_protmode(vcpu))
9c3e4aab
MT		 6526 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6527
3842d135
AK		 6528 kvm_make_request(KVM_REQ_EVENT, vcpu);
6529
b6c7a5dc
HB		 6530 return 0;
6531}
6532
d0bfb940
JK		 6533int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6534 struct kvm_guest_debug *dbg)
b6c7a5dc 6535{
355be0b9 6536 unsigned long rflags;
ae675ef0 6537 int i, r;
b6c7a5dc 6538
4f926bf2
JK		 6539 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6540 r = -EBUSY;
6541 if (vcpu->arch.exception.pending)
2122ff5e 6542 goto out;
4f926bf2
JK		 6543 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6544 kvm_queue_exception(vcpu, DB_VECTOR);
6545 else
6546 kvm_queue_exception(vcpu, BP_VECTOR);
6547 }
6548
91586a3b
JK		 6549 /*
6550 * Read rflags as long as potentially injected trace flags are still
6551 * filtered out.
6552 */
6553 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6554
6555 vcpu->guest_debug = dbg->control;
6556 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6557 vcpu->guest_debug = 0;
6558
6559 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6560 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6561 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6562 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6563 } else {
6564 for (i = 0; i < KVM_NR_DB_REGS; i++)
6565 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6566 }
c8639010 6567 kvm_update_dr7(vcpu);
ae675ef0 6568
f92653ee
JK		 6569 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6570 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6571 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6572
91586a3b
JK		 6573 /*
6574 * Trigger an rflags update that will inject or remove the trace
6575 * flags.
6576 */
6577 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6578
c8639010 6579 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6580
4f926bf2 6581 r = 0;
d0bfb940 6582
2122ff5e 6583out:
b6c7a5dc
HB		 6584
6585 return r;
6586}
6587
8b006791
ZX		 6588/*
6589 * Translate a guest virtual address to a guest physical address.
6590 */
6591int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6592 struct kvm_translation *tr)
6593{
6594 unsigned long vaddr = tr->linear_address;
6595 gpa_t gpa;
f656ce01 6596 int idx;
8b006791 6597
f656ce01 6598 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6599 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6600 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6601 tr->physical_address = gpa;
6602 tr->valid = gpa != UNMAPPED_GVA;
6603 tr->writeable = 1;
6604 tr->usermode = 0;
8b006791
ZX		 6605
6606 return 0;
6607}
6608
d0752060
HB		 6609int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6610{
98918833
SY		 6611 struct i387_fxsave_struct *fxsave =
6612 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6613
d0752060
HB		 6614 memcpy(fpu->fpr, fxsave->st_space, 128);
6615 fpu->fcw = fxsave->cwd;
6616 fpu->fsw = fxsave->swd;
6617 fpu->ftwx = fxsave->twd;
6618 fpu->last_opcode = fxsave->fop;
6619 fpu->last_ip = fxsave->rip;
6620 fpu->last_dp = fxsave->rdp;
6621 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6622
d0752060
HB		 6623 return 0;
6624}
6625
6626int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6627{
98918833
SY		 6628 struct i387_fxsave_struct *fxsave =
6629 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6630
d0752060
HB		 6631 memcpy(fxsave->st_space, fpu->fpr, 128);
6632 fxsave->cwd = fpu->fcw;
6633 fxsave->swd = fpu->fsw;
6634 fxsave->twd = fpu->ftwx;
6635 fxsave->fop = fpu->last_opcode;
6636 fxsave->rip = fpu->last_ip;
6637 fxsave->rdp = fpu->last_dp;
6638 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6639
d0752060
HB		 6640 return 0;
6641}
6642
10ab25cd 6643int fx_init(struct kvm_vcpu *vcpu)
d0752060 6644{
10ab25cd
JK		 6645 int err;
6646
6647 err = fpu_alloc(&vcpu->arch.guest_fpu);
6648 if (err)
6649 return err;
6650
98918833 6651 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6652
2acf923e
DC		 6653 /*
6654 * Ensure guest xcr0 is valid for loading
6655 */
6656 vcpu->arch.xcr0 = XSTATE_FP;
6657
ad312c7c 6658 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6659
6660 return 0;
d0752060
HB		 6661}
6662EXPORT_SYMBOL_GPL(fx_init);
6663
98918833
SY		 6664static void fx_free(struct kvm_vcpu *vcpu)
6665{
6666 fpu_free(&vcpu->arch.guest_fpu);
6667}
6668
d0752060
HB		 6669void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6670{
2608d7a1 6671 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6672 return;
6673
2acf923e
DC		 6674 /*
6675 * Restore all possible states in the guest,
6676 * and assume host would use all available bits.
6677 * Guest xcr0 would be loaded later.
6678 */
6679 kvm_put_guest_xcr0(vcpu);
d0752060 6680 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6681 __kernel_fpu_begin();
98918833 6682 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6683 trace_kvm_fpu(1);
d0752060 6684}
d0752060
HB		 6685
6686void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6687{
2acf923e
DC		 6688 kvm_put_guest_xcr0(vcpu);
6689
d0752060
HB		 6690 if (!vcpu->guest_fpu_loaded)
6691 return;
6692
6693 vcpu->guest_fpu_loaded = 0;
98918833 6694 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6695 __kernel_fpu_end();
f096ed85 6696 ++vcpu->stat.fpu_reload;
a8eeb04a 6697 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6698 trace_kvm_fpu(0);
d0752060 6699}
e9b11c17
ZX		 6700
6701void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6702{
12f9a48f 6703 kvmclock_reset(vcpu);
7f1ea208 6704
f5f48ee1 6705 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6706 fx_free(vcpu);
e9b11c17
ZX		 6707 kvm_x86_ops->vcpu_free(vcpu);
6708}
6709
6710struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6711 unsigned int id)
6712{
6755bae8
ZA		 6713 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6714 printk_once(KERN_WARNING
6715 "kvm: SMP vm created on host with unstable TSC; "
6716 "guest TSC will not be reliable\n");
26e5215f
AK		 6717 return kvm_x86_ops->vcpu_create(kvm, id);
6718}
e9b11c17 6719
26e5215f
AK		 6720int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6721{
6722 int r;
e9b11c17 6723
0bed3b56 6724 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6725 r = vcpu_load(vcpu);
6726 if (r)
6727 return r;
57f252f2 6728 kvm_vcpu_reset(vcpu);
8a3c1a33 6729 kvm_mmu_setup(vcpu);
e9b11c17 6730 vcpu_put(vcpu);
e9b11c17 6731
26e5215f 6732 return r;
e9b11c17
ZX		 6733}
6734
42897d86
MT		 6735int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6736{
6737 int r;
8fe8ab46 6738 struct msr_data msr;
42897d86
MT		 6739
6740 r = vcpu_load(vcpu);
6741 if (r)
6742 return r;
8fe8ab46
WA		 6743 msr.data = 0x0;
6744 msr.index = MSR_IA32_TSC;
6745 msr.host_initiated = true;
6746 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6747 vcpu_put(vcpu);
6748
6749 return r;
6750}
6751
d40ccc62 6752void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6753{
9fc77441 6754 int r;
344d9588
GN		 6755 vcpu->arch.apf.msr_val = 0;
6756
9fc77441
MT		 6757 r = vcpu_load(vcpu);
6758 BUG_ON(r);
e9b11c17
ZX		 6759 kvm_mmu_unload(vcpu);
6760 vcpu_put(vcpu);
6761
98918833 6762 fx_free(vcpu);
e9b11c17
ZX		 6763 kvm_x86_ops->vcpu_free(vcpu);
6764}
6765
66450a21 6766void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6767{
7460fb4a
AK		 6768 atomic_set(&vcpu->arch.nmi_queued, 0);
6769 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6770 vcpu->arch.nmi_injected = false;
6771
42dbaa5a
JK		 6772 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6773 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6774 kvm_update_dr6(vcpu);
42dbaa5a 6775 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6776 kvm_update_dr7(vcpu);
42dbaa5a 6777
3842d135 6778 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6779 vcpu->arch.apf.msr_val = 0;
c9aaa895 6780 vcpu->arch.st.msr_val = 0;
3842d135 6781
12f9a48f
GC		 6782 kvmclock_reset(vcpu);
6783
af585b92
GN		 6784 kvm_clear_async_pf_completion_queue(vcpu);
6785 kvm_async_pf_hash_reset(vcpu);
6786 vcpu->arch.apf.halted = false;
3842d135 6787
f5132b01
GN		 6788 kvm_pmu_reset(vcpu);
6789
66f7b72e
JS		 6790 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6791 vcpu->arch.regs_avail = ~0;
6792 vcpu->arch.regs_dirty = ~0;
6793
57f252f2 6794 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6795}
6796
66450a21
JK		 6797void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6798{
6799 struct kvm_segment cs;
6800
6801 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6802 cs.selector = vector << 8;
6803 cs.base = vector << 12;
6804 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6805 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6806}
6807
10474ae8 6808int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6809{
ca84d1a2
ZA		 6810 struct kvm *kvm;
6811 struct kvm_vcpu *vcpu;
6812 int i;
0dd6a6ed
ZA		 6813 int ret;
6814 u64 local_tsc;
6815 u64 max_tsc = 0;
6816 bool stable, backwards_tsc = false;
18863bdd
AK		 6817
6818 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6819 ret = kvm_x86_ops->hardware_enable(garbage);
6820 if (ret != 0)
6821 return ret;
6822
6823 local_tsc = native_read_tsc();
6824 stable = !check_tsc_unstable();
6825 list_for_each_entry(kvm, &vm_list, vm_list) {
6826 kvm_for_each_vcpu(i, vcpu, kvm) {
6827 if (!stable && vcpu->cpu == smp_processor_id())
6828 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6829 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6830 backwards_tsc = true;
6831 if (vcpu->arch.last_host_tsc > max_tsc)
6832 max_tsc = vcpu->arch.last_host_tsc;
6833 }
6834 }
6835 }
6836
6837 /*
6838 * Sometimes, even reliable TSCs go backwards. This happens on
6839 * platforms that reset TSC during suspend or hibernate actions, but
6840 * maintain synchronization. We must compensate. Fortunately, we can
6841 * detect that condition here, which happens early in CPU bringup,
6842 * before any KVM threads can be running. Unfortunately, we can't
6843 * bring the TSCs fully up to date with real time, as we aren't yet far
6844 * enough into CPU bringup that we know how much real time has actually
6845 * elapsed; our helper function, get_kernel_ns() will be using boot
6846 * variables that haven't been updated yet.
6847 *
6848 * So we simply find the maximum observed TSC above, then record the
6849 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6850 * the adjustment will be applied. Note that we accumulate
6851 * adjustments, in case multiple suspend cycles happen before some VCPU
6852 * gets a chance to run again. In the event that no KVM threads get a
6853 * chance to run, we will miss the entire elapsed period, as we'll have
6854 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6855 * loose cycle time. This isn't too big a deal, since the loss will be
6856 * uniform across all VCPUs (not to mention the scenario is extremely
6857 * unlikely). It is possible that a second hibernate recovery happens
6858 * much faster than a first, causing the observed TSC here to be
6859 * smaller; this would require additional padding adjustment, which is
6860 * why we set last_host_tsc to the local tsc observed here.
6861 *
6862 * N.B. - this code below runs only on platforms with reliable TSC,
6863 * as that is the only way backwards_tsc is set above. Also note
6864 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6865 * have the same delta_cyc adjustment applied if backwards_tsc
6866 * is detected. Note further, this adjustment is only done once,
6867 * as we reset last_host_tsc on all VCPUs to stop this from being
6868 * called multiple times (one for each physical CPU bringup).
6869 *
4a969980 6870 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6871 * will be compensated by the logic in vcpu_load, which sets the TSC to
6872 * catchup mode. This will catchup all VCPUs to real time, but cannot
6873 * guarantee that they stay in perfect synchronization.
6874 */
6875 if (backwards_tsc) {
6876 u64 delta_cyc = max_tsc - local_tsc;
6877 list_for_each_entry(kvm, &vm_list, vm_list) {
6878 kvm_for_each_vcpu(i, vcpu, kvm) {
6879 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6880 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6881 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6882 &vcpu->requests);
0dd6a6ed
ZA		 6883 }
6884
6885 /*
6886 * We have to disable TSC offset matching.. if you were
6887 * booting a VM while issuing an S4 host suspend....
6888 * you may have some problem. Solving this issue is
6889 * left as an exercise to the reader.
6890 */
6891 kvm->arch.last_tsc_nsec = 0;
6892 kvm->arch.last_tsc_write = 0;
6893 }
6894
6895 }
6896 return 0;
e9b11c17
ZX		 6897}
6898
6899void kvm_arch_hardware_disable(void *garbage)
6900{
6901 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6902 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6903}
6904
6905int kvm_arch_hardware_setup(void)
6906{
6907 return kvm_x86_ops->hardware_setup();
6908}
6909
6910void kvm_arch_hardware_unsetup(void)
6911{
6912 kvm_x86_ops->hardware_unsetup();
6913}
6914
6915void kvm_arch_check_processor_compat(void *rtn)
6916{
6917 kvm_x86_ops->check_processor_compatibility(rtn);
6918}
6919
3e515705
AK		 6920bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6921{
6922 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6923}
6924
54e9818f
GN		 6925struct static_key kvm_no_apic_vcpu __read_mostly;
6926
e9b11c17
ZX		 6927int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6928{
6929 struct page *page;
6930 struct kvm *kvm;
6931 int r;
6932
6933 BUG_ON(vcpu->kvm == NULL);
6934 kvm = vcpu->kvm;
6935
6aef266c 6936 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6937 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6938 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6939 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6940 else
a4535290 6941 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6942
6943 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6944 if (!page) {
6945 r = -ENOMEM;
6946 goto fail;
6947 }
ad312c7c 6948 vcpu->arch.pio_data = page_address(page);
e9b11c17 6949
cc578287 6950 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6951
e9b11c17
ZX		 6952 r = kvm_mmu_create(vcpu);
6953 if (r < 0)
6954 goto fail_free_pio_data;
6955
6956 if (irqchip_in_kernel(kvm)) {
6957 r = kvm_create_lapic(vcpu);
6958 if (r < 0)
6959 goto fail_mmu_destroy;
54e9818f
GN		 6960 } else
6961 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6962
890ca9ae
HY		 6963 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6964 GFP_KERNEL);
6965 if (!vcpu->arch.mce_banks) {
6966 r = -ENOMEM;
443c39bc 6967 goto fail_free_lapic;
890ca9ae
HY		 6968 }
6969 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6970
f1797359
WY		 6971 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6972 r = -ENOMEM;
f5f48ee1 6973 goto fail_free_mce_banks;
f1797359 6974 }
f5f48ee1 6975
66f7b72e
JS		 6976 r = fx_init(vcpu);
6977 if (r)
6978 goto fail_free_wbinvd_dirty_mask;
6979
ba904635 6980 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6981 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6982
6983 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6984 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6985
af585b92 6986 kvm_async_pf_hash_reset(vcpu);
f5132b01 6987 kvm_pmu_init(vcpu);
af585b92 6988
e9b11c17 6989 return 0;
66f7b72e
JS		 6990fail_free_wbinvd_dirty_mask:
6991 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6992fail_free_mce_banks:
6993 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6994fail_free_lapic:
6995 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6996fail_mmu_destroy:
6997 kvm_mmu_destroy(vcpu);
6998fail_free_pio_data:
ad312c7c 6999 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7000fail:
7001 return r;
7002}
7003
7004void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7005{
f656ce01
MT		 7006 int idx;
7007
f5132b01 7008 kvm_pmu_destroy(vcpu);
36cb93fd 7009 kfree(vcpu->arch.mce_banks);
e9b11c17 7010 kvm_free_lapic(vcpu);
f656ce01 7011 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7012 kvm_mmu_destroy(vcpu);
f656ce01 7013 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7014 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7015 if (!irqchip_in_kernel(vcpu->kvm))
7016 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7017}
d19a9cd2 7018
e08b9637 7019int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7020{
e08b9637
CO		 7021 if (type)
7022 return -EINVAL;
7023
f05e70ac 7024 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7025 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7026 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7027 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7028
5550af4d
SY		 7029 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7030 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7031 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7032 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7033 &kvm->arch.irq_sources_bitmap);
5550af4d 7034
038f8c11 7035 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7036 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7037 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7038
7039 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7040
7e44e449
AJ		 7041 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7042
d89f5eff 7043 return 0;
d19a9cd2
ZX		 7044}
7045
7046static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7047{
9fc77441
MT		 7048 int r;
7049 r = vcpu_load(vcpu);
7050 BUG_ON(r);
d19a9cd2
ZX		 7051 kvm_mmu_unload(vcpu);
7052 vcpu_put(vcpu);
7053}
7054
7055static void kvm_free_vcpus(struct kvm *kvm)
7056{
7057 unsigned int i;
988a2cae 7058 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7059
7060 /*
7061 * Unpin any mmu pages first.
7062 */
af585b92
GN		 7063 kvm_for_each_vcpu(i, vcpu, kvm) {
7064 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7065 kvm_unload_vcpu_mmu(vcpu);
af585b92 7066 }
988a2cae
GN		 7067 kvm_for_each_vcpu(i, vcpu, kvm)
7068 kvm_arch_vcpu_free(vcpu);
7069
7070 mutex_lock(&kvm->lock);
7071 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7072 kvm->vcpus[i] = NULL;
d19a9cd2 7073
988a2cae
GN		 7074 atomic_set(&kvm->online_vcpus, 0);
7075 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7076}
7077
ad8ba2cd
SY		 7078void kvm_arch_sync_events(struct kvm *kvm)
7079{
7e44e449 7080 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7081 kvm_free_all_assigned_devices(kvm);
aea924f6 7082 kvm_free_pit(kvm);
ad8ba2cd
SY		 7083}
7084
d19a9cd2
ZX		 7085void kvm_arch_destroy_vm(struct kvm *kvm)
7086{
27469d29
AH		 7087 if (current->mm == kvm->mm) {
7088 /*
7089 * Free memory regions allocated on behalf of userspace,
7090 * unless the the memory map has changed due to process exit
7091 * or fd copying.
7092 */
7093 struct kvm_userspace_memory_region mem;
7094 memset(&mem, 0, sizeof(mem));
7095 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7096 kvm_set_memory_region(kvm, &mem);
7097
7098 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7099 kvm_set_memory_region(kvm, &mem);
7100
7101 mem.slot = TSS_PRIVATE_MEMSLOT;
7102 kvm_set_memory_region(kvm, &mem);
7103 }
6eb55818 7104 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7105 kfree(kvm->arch.vpic);
7106 kfree(kvm->arch.vioapic);
d19a9cd2 7107 kvm_free_vcpus(kvm);
3d45830c
AK		 7108 if (kvm->arch.apic_access_page)
7109 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7110 if (kvm->arch.ept_identity_pagetable)
7111 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7112 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7113}
0de10343 7114
5587027c 7115void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7116 struct kvm_memory_slot *dont)
7117{
7118 int i;
7119
d89cc617
TY		 7120 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7121 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7122 kvm_kvfree(free->arch.rmap[i]);
7123 free->arch.rmap[i] = NULL;
77d11309 7124 }
d89cc617
TY		 7125 if (i == 0)
7126 continue;
7127
7128 if (!dont || free->arch.lpage_info[i - 1] !=
7129 dont->arch.lpage_info[i - 1]) {
7130 kvm_kvfree(free->arch.lpage_info[i - 1]);
7131 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7132 }
7133 }
7134}
7135
5587027c
AK		 7136int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7137 unsigned long npages)
db3fe4eb
TY		 7138{
7139 int i;
7140
d89cc617 7141 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7142 unsigned long ugfn;
7143 int lpages;
d89cc617 7144 int level = i + 1;
db3fe4eb
TY		 7145
7146 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7147 slot->base_gfn, level) + 1;
7148
d89cc617
TY		 7149 slot->arch.rmap[i] =
7150 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7151 if (!slot->arch.rmap[i])
77d11309 7152 goto out_free;
d89cc617
TY		 7153 if (i == 0)
7154 continue;
77d11309 7155
d89cc617
TY		 7156 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7157 sizeof(*slot->arch.lpage_info[i - 1]));
7158 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7159 goto out_free;
7160
7161 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7162 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7163 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7164 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7165 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7166 /*
7167 * If the gfn and userspace address are not aligned wrt each
7168 * other, or if explicitly asked to, disable large page
7169 * support for this slot
7170 */
7171 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7172 !kvm_largepages_enabled()) {
7173 unsigned long j;
7174
7175 for (j = 0; j < lpages; ++j)
d89cc617 7176 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7177 }
7178 }
7179
7180 return 0;
7181
7182out_free:
d89cc617
TY		 7183 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7184 kvm_kvfree(slot->arch.rmap[i]);
7185 slot->arch.rmap[i] = NULL;
7186 if (i == 0)
7187 continue;
7188
7189 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7190 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7191 }
7192 return -ENOMEM;
7193}
7194
e59dbe09
TY		 7195void kvm_arch_memslots_updated(struct kvm *kvm)
7196{
e6dff7d1
TY		 7197 /*
7198 * memslots->generation has been incremented.
7199 * mmio generation may have reached its maximum value.
7200 */
7201 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7202}
7203
f7784b8e
MT		 7204int kvm_arch_prepare_memory_region(struct kvm *kvm,
7205 struct kvm_memory_slot *memslot,
f7784b8e 7206 struct kvm_userspace_memory_region *mem,
7b6195a9 7207 enum kvm_mr_change change)
0de10343 7208{
7a905b14
TY		 7209 /*
7210 * Only private memory slots need to be mapped here since
7211 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7212 */
7b6195a9 7213 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7214 unsigned long userspace_addr;
604b38ac 7215
7a905b14
TY		 7216 /*
7217 * MAP_SHARED to prevent internal slot pages from being moved
7218 * by fork()/COW.
7219 */
7b6195a9 7220 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7221 PROT_READ | PROT_WRITE,
7222 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7223
7a905b14
TY		 7224 if (IS_ERR((void *)userspace_addr))
7225 return PTR_ERR((void *)userspace_addr);
604b38ac 7226
7a905b14 7227 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7228 }
7229
f7784b8e
MT		 7230 return 0;
7231}
7232
7233void kvm_arch_commit_memory_region(struct kvm *kvm,
7234 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7235 const struct kvm_memory_slot *old,
7236 enum kvm_mr_change change)
f7784b8e
MT		 7237{
7238
8482644a 7239 int nr_mmu_pages = 0;
f7784b8e 7240
8482644a 7241 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7242 int ret;
7243
8482644a
TY		 7244 ret = vm_munmap(old->userspace_addr,
7245 old->npages * PAGE_SIZE);
f7784b8e
MT		 7246 if (ret < 0)
7247 printk(KERN_WARNING
7248 "kvm_vm_ioctl_set_memory_region: "
7249 "failed to munmap memory\n");
7250 }
7251
48c0e4e9
XG		 7252 if (!kvm->arch.n_requested_mmu_pages)
7253 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7254
48c0e4e9 7255 if (nr_mmu_pages)
0de10343 7256 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7257 /*
7258 * Write protect all pages for dirty logging.
7259 * Existing largepage mappings are destroyed here and new ones will
7260 * not be created until the end of the logging.
7261 */
8482644a 7262 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7263 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7264}
1d737c8a 7265
2df72e9b 7266void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7267{
6ca18b69 7268 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7269}
7270
2df72e9b
MT		 7271void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7272 struct kvm_memory_slot *slot)
7273{
6ca18b69 7274 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7275}
7276
1d737c8a
ZX		 7277int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7278{
af585b92
GN		 7279 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7280 !vcpu->arch.apf.halted)
7281 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7282 || kvm_apic_has_events(vcpu)
6aef266c 7283 || vcpu->arch.pv.pv_unhalted
7460fb4a 7284 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7285 (kvm_arch_interrupt_allowed(vcpu) &&
7286 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7287}
5736199a 7288
b6d33834 7289int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7290{
b6d33834 7291 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7292}
78646121
GN		 7293
7294int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7295{
7296 return kvm_x86_ops->interrupt_allowed(vcpu);
7297}
229456fc 7298
f92653ee
JK		 7299bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7300{
7301 unsigned long current_rip = kvm_rip_read(vcpu) +
7302 get_segment_base(vcpu, VCPU_SREG_CS);
7303
7304 return current_rip == linear_rip;
7305}
7306EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7307
94fe45da
JK		 7308unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7309{
7310 unsigned long rflags;
7311
7312 rflags = kvm_x86_ops->get_rflags(vcpu);
7313 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7314 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7315 return rflags;
7316}
7317EXPORT_SYMBOL_GPL(kvm_get_rflags);
7318
7319void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7320{
7321 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7322 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7323 rflags |= X86_EFLAGS_TF;
94fe45da 7324 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7325 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7326}
7327EXPORT_SYMBOL_GPL(kvm_set_rflags);
7328
56028d08
GN		 7329void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7330{
7331 int r;
7332
fb67e14f 7333 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7334 work->wakeup_all)
56028d08
GN		 7335 return;
7336
7337 r = kvm_mmu_reload(vcpu);
7338 if (unlikely(r))
7339 return;
7340
fb67e14f
XG		 7341 if (!vcpu->arch.mmu.direct_map &&
7342 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7343 return;
7344
56028d08
GN		 7345 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7346}
7347
af585b92
GN		 7348static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7349{
7350 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7351}
7352
7353static inline u32 kvm_async_pf_next_probe(u32 key)
7354{
7355 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7356}
7357
7358static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7359{
7360 u32 key = kvm_async_pf_hash_fn(gfn);
7361
7362 while (vcpu->arch.apf.gfns[key] != ~0)
7363 key = kvm_async_pf_next_probe(key);
7364
7365 vcpu->arch.apf.gfns[key] = gfn;
7366}
7367
7368static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7369{
7370 int i;
7371 u32 key = kvm_async_pf_hash_fn(gfn);
7372
7373 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7374 (vcpu->arch.apf.gfns[key] != gfn &&
7375 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7376 key = kvm_async_pf_next_probe(key);
7377
7378 return key;
7379}
7380
7381bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7382{
7383 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7384}
7385
7386static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7387{
7388 u32 i, j, k;
7389
7390 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7391 while (true) {
7392 vcpu->arch.apf.gfns[i] = ~0;
7393 do {
7394 j = kvm_async_pf_next_probe(j);
7395 if (vcpu->arch.apf.gfns[j] == ~0)
7396 return;
7397 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7398 /*
7399 * k lies cyclically in ]i,j]
7400 * | i.k.j |
7401 * |....j i.k.| or |.k..j i...|
7402 */
7403 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7404 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7405 i = j;
7406 }
7407}
7408
7c90705b
GN		 7409static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7410{
7411
7412 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7413 sizeof(val));
7414}
7415
af585b92
GN		 7416void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7417 struct kvm_async_pf *work)
7418{
6389ee94
AK		 7419 struct x86_exception fault;
7420
7c90705b 7421 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7422 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7423
7424 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7425 (vcpu->arch.apf.send_user_only &&
7426 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7427 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7428 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7429 fault.vector = PF_VECTOR;
7430 fault.error_code_valid = true;
7431 fault.error_code = 0;
7432 fault.nested_page_fault = false;
7433 fault.address = work->arch.token;
7434 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7435 }
af585b92
GN		 7436}
7437
7438void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7439 struct kvm_async_pf *work)
7440{
6389ee94
AK		 7441 struct x86_exception fault;
7442
7c90705b 7443 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7444 if (work->wakeup_all)
7c90705b
GN		 7445 work->arch.token = ~0; /* broadcast wakeup */
7446 else
7447 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7448
7449 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7450 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7451 fault.vector = PF_VECTOR;
7452 fault.error_code_valid = true;
7453 fault.error_code = 0;
7454 fault.nested_page_fault = false;
7455 fault.address = work->arch.token;
7456 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7457 }
e6d53e3b 7458 vcpu->arch.apf.halted = false;
a4fa1635 7459 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7460}
7461
7462bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7463{
7464 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7465 return true;
7466 else
7467 return !kvm_event_needs_reinjection(vcpu) &&
7468 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7469}
7470
e0f0bbc5
AW		 7471void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7472{
7473 atomic_inc(&kvm->arch.noncoherent_dma_count);
7474}
7475EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7476
7477void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7478{
7479 atomic_dec(&kvm->arch.noncoherent_dma_count);
7480}
7481EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7482
7483bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7484{
7485 return atomic_read(&kvm->arch.noncoherent_dma_count);
7486}
7487EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7488
229456fc
MT		 7489EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7490EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7491EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7492EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7493EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7494EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7495EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7496EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7497EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7498EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7499EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7500EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7501EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux kernel - Deliverables
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