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kvm: x86: emulate monitor and mwait instructions as nop
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
97ec8c06
FW		 655 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
656 return 1;
657
afcbf13f 658 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 659 return 1;
660
a03490ed 661 if (is_long_mode(vcpu)) {
0f12244f
GN		 662 if (!(cr4 & X86_CR4_PAE))
663 return 1;
a2edf57f
AK		 664 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
665 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 666 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
667 kvm_read_cr3(vcpu)))
0f12244f
GN		 668 return 1;
669
ad756a16
MJ		 670 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
671 if (!guest_cpuid_has_pcid(vcpu))
672 return 1;
673
674 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
675 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
676 return 1;
677 }
678
5e1746d6 679 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 680 return 1;
a03490ed 681
ad756a16
MJ		 682 if (((cr4 ^ old_cr4) & pdptr_bits) ||
683 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 684 kvm_mmu_reset_context(vcpu);
0f12244f 685
97ec8c06
FW		 686 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
687 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
688
2acf923e 689 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 690 kvm_update_cpuid(vcpu);
2acf923e 691
0f12244f
GN		 692 return 0;
693}
2d3ad1f4 694EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 695
2390218b 696int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 697{
9f8fe504 698 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 699 kvm_mmu_sync_roots(vcpu);
d835dfec 700 kvm_mmu_flush_tlb(vcpu);
0f12244f 701 return 0;
d835dfec
AK		 702 }
703
346874c9
NA		 704 if (is_long_mode(vcpu) && (cr3 & CR3_L_MODE_RESERVED_BITS))
705 return 1;
706 if (is_pae(vcpu) && is_paging(vcpu) &&
707 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
708 return 1;
a03490ed 709
0f12244f 710 vcpu->arch.cr3 = cr3;
aff48baa 711 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 712 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 713 return 0;
714}
2d3ad1f4 715EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 716
eea1cff9 717int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 718{
0f12244f
GN		 719 if (cr8 & CR8_RESERVED_BITS)
720 return 1;
a03490ed
CO		 721 if (irqchip_in_kernel(vcpu->kvm))
722 kvm_lapic_set_tpr(vcpu, cr8);
723 else
ad312c7c 724 vcpu->arch.cr8 = cr8;
0f12244f
GN		 725 return 0;
726}
2d3ad1f4 727EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 728
2d3ad1f4 729unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 730{
731 if (irqchip_in_kernel(vcpu->kvm))
732 return kvm_lapic_get_cr8(vcpu);
733 else
ad312c7c 734 return vcpu->arch.cr8;
a03490ed 735}
2d3ad1f4 736EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 737
73aaf249
JK		 738static void kvm_update_dr6(struct kvm_vcpu *vcpu)
739{
740 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
741 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
742}
743
c8639010
JK		 744static void kvm_update_dr7(struct kvm_vcpu *vcpu)
745{
746 unsigned long dr7;
747
748 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
749 dr7 = vcpu->arch.guest_debug_dr7;
750 else
751 dr7 = vcpu->arch.dr7;
752 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 753 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
754 if (dr7 & DR7_BP_EN_MASK)
755 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 756}
757
338dbc97 758static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 759{
760 switch (dr) {
761 case 0 ... 3:
762 vcpu->arch.db[dr] = val;
763 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
764 vcpu->arch.eff_db[dr] = val;
765 break;
766 case 4:
338dbc97
GN		 767 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
768 return 1; /* #UD */
020df079
GN		 769 /* fall through */
770 case 6:
338dbc97
GN		 771 if (val & 0xffffffff00000000ULL)
772 return -1; /* #GP */
020df079 773 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 774 kvm_update_dr6(vcpu);
020df079
GN		 775 break;
776 case 5:
338dbc97
GN		 777 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
778 return 1; /* #UD */
020df079
GN		 779 /* fall through */
780 default: /* 7 */
338dbc97
GN		 781 if (val & 0xffffffff00000000ULL)
782 return -1; /* #GP */
020df079 783 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 784 kvm_update_dr7(vcpu);
020df079
GN		 785 break;
786 }
787
788 return 0;
789}
338dbc97
GN		 790
791int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
792{
793 int res;
794
795 res = __kvm_set_dr(vcpu, dr, val);
796 if (res > 0)
797 kvm_queue_exception(vcpu, UD_VECTOR);
798 else if (res < 0)
799 kvm_inject_gp(vcpu, 0);
800
801 return res;
802}
020df079
GN		 803EXPORT_SYMBOL_GPL(kvm_set_dr);
804
338dbc97 805static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 806{
807 switch (dr) {
808 case 0 ... 3:
809 *val = vcpu->arch.db[dr];
810 break;
811 case 4:
338dbc97 812 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 813 return 1;
020df079
GN		 814 /* fall through */
815 case 6:
73aaf249
JK		 816 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
817 *val = vcpu->arch.dr6;
818 else
819 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 820 break;
821 case 5:
338dbc97 822 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 823 return 1;
020df079
GN		 824 /* fall through */
825 default: /* 7 */
826 *val = vcpu->arch.dr7;
827 break;
828 }
829
830 return 0;
831}
338dbc97
GN		 832
833int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
834{
835 if (_kvm_get_dr(vcpu, dr, val)) {
836 kvm_queue_exception(vcpu, UD_VECTOR);
837 return 1;
838 }
839 return 0;
840}
020df079
GN		 841EXPORT_SYMBOL_GPL(kvm_get_dr);
842
022cd0e8
AK		 843bool kvm_rdpmc(struct kvm_vcpu *vcpu)
844{
845 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
846 u64 data;
847 int err;
848
849 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
850 if (err)
851 return err;
852 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
853 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
854 return err;
855}
856EXPORT_SYMBOL_GPL(kvm_rdpmc);
857
043405e1
CO		 858/*
859 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
860 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
861 *
862 * This list is modified at module load time to reflect the
e3267cbb
GC		 863 * capabilities of the host cpu. This capabilities test skips MSRs that are
864 * kvm-specific. Those are put in the beginning of the list.
043405e1 865 */
e3267cbb 866
e984097b 867#define KVM_SAVE_MSRS_BEGIN 12
043405e1 868static u32 msrs_to_save[] = {
e3267cbb 869 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 870 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 871 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 872 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 873 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 874 MSR_KVM_PV_EOI_EN,
043405e1 875 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 876 MSR_STAR,
043405e1
CO		 877#ifdef CONFIG_X86_64
878 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
879#endif
b3897a49 880 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 881 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 882};
883
884static unsigned num_msrs_to_save;
885
f1d24831 886static const u32 emulated_msrs[] = {
ba904635 887 MSR_IA32_TSC_ADJUST,
a3e06bbe 888 MSR_IA32_TSCDEADLINE,
043405e1 889 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 890 MSR_IA32_MCG_STATUS,
891 MSR_IA32_MCG_CTL,
043405e1
CO		 892};
893
384bb783 894bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 895{
b69e8cae 896 if (efer & efer_reserved_bits)
384bb783 897 return false;
15c4a640 898
1b2fd70c
AG		 899 if (efer & EFER_FFXSR) {
900 struct kvm_cpuid_entry2 *feat;
901
902 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 903 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 904 return false;
1b2fd70c
AG		 905 }
906
d8017474
AG		 907 if (efer & EFER_SVME) {
908 struct kvm_cpuid_entry2 *feat;
909
910 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 911 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 912 return false;
d8017474
AG		 913 }
914
384bb783
JK		 915 return true;
916}
917EXPORT_SYMBOL_GPL(kvm_valid_efer);
918
919static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
920{
921 u64 old_efer = vcpu->arch.efer;
922
923 if (!kvm_valid_efer(vcpu, efer))
924 return 1;
925
926 if (is_paging(vcpu)
927 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
928 return 1;
929
15c4a640 930 efer &= ~EFER_LMA;
f6801dff 931 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 932
a3d204e2
SY		 933 kvm_x86_ops->set_efer(vcpu, efer);
934
aad82703
SY		 935 /* Update reserved bits */
936 if ((efer ^ old_efer) & EFER_NX)
937 kvm_mmu_reset_context(vcpu);
938
b69e8cae 939 return 0;
15c4a640
CO		 940}
941
f2b4b7dd
JR		 942void kvm_enable_efer_bits(u64 mask)
943{
944 efer_reserved_bits &= ~mask;
945}
946EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
947
948
15c4a640
CO		 949/*
950 * Writes msr value into into the appropriate "register".
951 * Returns 0 on success, non-0 otherwise.
952 * Assumes vcpu_load() was already called.
953 */
8fe8ab46 954int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 955{
8fe8ab46 956 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 957}
958
313a3dc7
CO		 959/*
960 * Adapt set_msr() to msr_io()'s calling convention
961 */
962static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
963{
8fe8ab46
WA		 964 struct msr_data msr;
965
966 msr.data = *data;
967 msr.index = index;
968 msr.host_initiated = true;
969 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 970}
971
16e8d74d
MT		 972#ifdef CONFIG_X86_64
973struct pvclock_gtod_data {
974 seqcount_t seq;
975
976 struct { /* extract of a clocksource struct */
977 int vclock_mode;
978 cycle_t cycle_last;
979 cycle_t mask;
980 u32 mult;
981 u32 shift;
982 } clock;
983
984 /* open coded 'struct timespec' */
985 u64 monotonic_time_snsec;
986 time_t monotonic_time_sec;
987};
988
989static struct pvclock_gtod_data pvclock_gtod_data;
990
991static void update_pvclock_gtod(struct timekeeper *tk)
992{
993 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
994
995 write_seqcount_begin(&vdata->seq);
996
997 /* copy pvclock gtod data */
998 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
999 vdata->clock.cycle_last = tk->clock->cycle_last;
1000 vdata->clock.mask = tk->clock->mask;
1001 vdata->clock.mult = tk->mult;
1002 vdata->clock.shift = tk->shift;
1003
1004 vdata->monotonic_time_sec = tk->xtime_sec
1005 + tk->wall_to_monotonic.tv_sec;
1006 vdata->monotonic_time_snsec = tk->xtime_nsec
1007 + (tk->wall_to_monotonic.tv_nsec
1008 << tk->shift);
1009 while (vdata->monotonic_time_snsec >=
1010 (((u64)NSEC_PER_SEC) << tk->shift)) {
1011 vdata->monotonic_time_snsec -=
1012 ((u64)NSEC_PER_SEC) << tk->shift;
1013 vdata->monotonic_time_sec++;
1014 }
1015
1016 write_seqcount_end(&vdata->seq);
1017}
1018#endif
1019
1020
18068523
GOC		 1021static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1022{
9ed3c444
AK		 1023 int version;
1024 int r;
50d0a0f9 1025 struct pvclock_wall_clock wc;
923de3cf 1026 struct timespec boot;
18068523
GOC		 1027
1028 if (!wall_clock)
1029 return;
1030
9ed3c444
AK		 1031 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1032 if (r)
1033 return;
1034
1035 if (version & 1)
1036 ++version; /* first time write, random junk */
1037
1038 ++version;
18068523 1039
18068523
GOC		 1040 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1041
50d0a0f9
GH		 1042 /*
1043 * The guest calculates current wall clock time by adding
34c238a1 1044 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1045 * wall clock specified here. guest system time equals host
1046 * system time for us, thus we must fill in host boot time here.
1047 */
923de3cf 1048 getboottime(&boot);
50d0a0f9 1049
4b648665
BR		 1050 if (kvm->arch.kvmclock_offset) {
1051 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1052 boot = timespec_sub(boot, ts);
1053 }
50d0a0f9
GH		 1054 wc.sec = boot.tv_sec;
1055 wc.nsec = boot.tv_nsec;
1056 wc.version = version;
18068523
GOC		 1057
1058 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1059
1060 version++;
1061 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1062}
1063
50d0a0f9
GH		 1064static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1065{
1066 uint32_t quotient, remainder;
1067
1068 /* Don't try to replace with do_div(), this one calculates
1069 * "(dividend << 32) / divisor" */
1070 __asm__ ( "divl %4"
1071 : "=a" (quotient), "=d" (remainder)
1072 : "0" (0), "1" (dividend), "r" (divisor) );
1073 return quotient;
1074}
1075
5f4e3f88
ZA		 1076static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1077 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1078{
5f4e3f88 1079 uint64_t scaled64;
50d0a0f9
GH		 1080 int32_t shift = 0;
1081 uint64_t tps64;
1082 uint32_t tps32;
1083
5f4e3f88
ZA		 1084 tps64 = base_khz * 1000LL;
1085 scaled64 = scaled_khz * 1000LL;
50933623 1086 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1087 tps64 >>= 1;
1088 shift--;
1089 }
1090
1091 tps32 = (uint32_t)tps64;
50933623
JK		 1092 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1093 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1094 scaled64 >>= 1;
1095 else
1096 tps32 <<= 1;
50d0a0f9
GH		 1097 shift++;
1098 }
1099
5f4e3f88
ZA		 1100 *pshift = shift;
1101 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1102
5f4e3f88
ZA		 1103 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1104 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1105}
1106
759379dd
ZA		 1107static inline u64 get_kernel_ns(void)
1108{
1109 struct timespec ts;
1110
759379dd
ZA		 1111 ktime_get_ts(&ts);
1112 monotonic_to_bootbased(&ts);
1113 return timespec_to_ns(&ts);
50d0a0f9
GH		 1114}
1115
d828199e 1116#ifdef CONFIG_X86_64
16e8d74d 1117static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1118#endif
16e8d74d 1119
c8076604 1120static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1121unsigned long max_tsc_khz;
c8076604 1122
cc578287 1123static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1124{
cc578287
ZA		 1125 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1126 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1127}
1128
cc578287 1129static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1130{
cc578287
ZA		 1131 u64 v = (u64)khz * (1000000 + ppm);
1132 do_div(v, 1000000);
1133 return v;
1e993611
JR		 1134}
1135
cc578287 1136static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1137{
cc578287
ZA		 1138 u32 thresh_lo, thresh_hi;
1139 int use_scaling = 0;
217fc9cf 1140
03ba32ca
MT		 1141 /* tsc_khz can be zero if TSC calibration fails */
1142 if (this_tsc_khz == 0)
1143 return;
1144
c285545f
ZA		 1145 /* Compute a scale to convert nanoseconds in TSC cycles */
1146 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1147 &vcpu->arch.virtual_tsc_shift,
1148 &vcpu->arch.virtual_tsc_mult);
1149 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1150
1151 /*
1152 * Compute the variation in TSC rate which is acceptable
1153 * within the range of tolerance and decide if the
1154 * rate being applied is within that bounds of the hardware
1155 * rate. If so, no scaling or compensation need be done.
1156 */
1157 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1158 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1159 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1160 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1161 use_scaling = 1;
1162 }
1163 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1164}
1165
1166static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1167{
e26101b1 1168 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1169 vcpu->arch.virtual_tsc_mult,
1170 vcpu->arch.virtual_tsc_shift);
e26101b1 1171 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1172 return tsc;
1173}
1174
b48aa97e
MT		 1175void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1176{
1177#ifdef CONFIG_X86_64
1178 bool vcpus_matched;
1179 bool do_request = false;
1180 struct kvm_arch *ka = &vcpu->kvm->arch;
1181 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1182
1183 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1184 atomic_read(&vcpu->kvm->online_vcpus));
1185
1186 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1187 if (!ka->use_master_clock)
1188 do_request = 1;
1189
1190 if (!vcpus_matched && ka->use_master_clock)
1191 do_request = 1;
1192
1193 if (do_request)
1194 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1195
1196 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1197 atomic_read(&vcpu->kvm->online_vcpus),
1198 ka->use_master_clock, gtod->clock.vclock_mode);
1199#endif
1200}
1201
ba904635
WA		 1202static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1203{
1204 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1205 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1206}
1207
8fe8ab46 1208void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1209{
1210 struct kvm *kvm = vcpu->kvm;
f38e098f 1211 u64 offset, ns, elapsed;
99e3e30a 1212 unsigned long flags;
02626b6a 1213 s64 usdiff;
b48aa97e 1214 bool matched;
8fe8ab46 1215 u64 data = msr->data;
99e3e30a 1216
038f8c11 1217 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1218 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1219 ns = get_kernel_ns();
f38e098f 1220 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1221
03ba32ca 1222 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1223 int faulted = 0;
1224
03ba32ca
MT		 1225 /* n.b - signed multiplication and division required */
1226 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1227#ifdef CONFIG_X86_64
03ba32ca 1228 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1229#else
03ba32ca 1230 /* do_div() only does unsigned */
8915aa27
MT		 1231 asm("1: idivl %[divisor]\n"
1232 "2: xor %%edx, %%edx\n"
1233 " movl $0, %[faulted]\n"
1234 "3:\n"
1235 ".section .fixup,\"ax\"\n"
1236 "4: movl $1, %[faulted]\n"
1237 " jmp 3b\n"
1238 ".previous\n"
1239
1240 _ASM_EXTABLE(1b, 4b)
1241
1242 : "=A"(usdiff), [faulted] "=r" (faulted)
1243 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1244
5d3cb0f6 1245#endif
03ba32ca
MT		 1246 do_div(elapsed, 1000);
1247 usdiff -= elapsed;
1248 if (usdiff < 0)
1249 usdiff = -usdiff;
8915aa27
MT		 1250
1251 /* idivl overflow => difference is larger than USEC_PER_SEC */
1252 if (faulted)
1253 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1254 } else
1255 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1256
1257 /*
5d3cb0f6
ZA		 1258 * Special case: TSC write with a small delta (1 second) of virtual
1259 * cycle time against real time is interpreted as an attempt to
1260 * synchronize the CPU.
1261 *
1262 * For a reliable TSC, we can match TSC offsets, and for an unstable
1263 * TSC, we add elapsed time in this computation. We could let the
1264 * compensation code attempt to catch up if we fall behind, but
1265 * it's better to try to match offsets from the beginning.
1266 */
02626b6a 1267 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1268 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1269 if (!check_tsc_unstable()) {
e26101b1 1270 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1271 pr_debug("kvm: matched tsc offset for %llu\n", data);
1272 } else {
857e4099 1273 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1274 data += delta;
1275 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1276 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1277 }
b48aa97e 1278 matched = true;
e26101b1
ZA		 1279 } else {
1280 /*
1281 * We split periods of matched TSC writes into generations.
1282 * For each generation, we track the original measured
1283 * nanosecond time, offset, and write, so if TSCs are in
1284 * sync, we can match exact offset, and if not, we can match
4a969980 1285 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1286 *
1287 * These values are tracked in kvm->arch.cur_xxx variables.
1288 */
1289 kvm->arch.cur_tsc_generation++;
1290 kvm->arch.cur_tsc_nsec = ns;
1291 kvm->arch.cur_tsc_write = data;
1292 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1293 matched = false;
e26101b1
ZA		 1294 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1295 kvm->arch.cur_tsc_generation, data);
f38e098f 1296 }
e26101b1
ZA		 1297
1298 /*
1299 * We also track th most recent recorded KHZ, write and time to
1300 * allow the matching interval to be extended at each write.
1301 */
f38e098f
ZA		 1302 kvm->arch.last_tsc_nsec = ns;
1303 kvm->arch.last_tsc_write = data;
5d3cb0f6 1304 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1305
b183aa58 1306 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1307
1308 /* Keep track of which generation this VCPU has synchronized to */
1309 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1310 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1311 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1312
ba904635
WA		 1313 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1314 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1315 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1316 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1317
1318 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1319 if (matched)
1320 kvm->arch.nr_vcpus_matched_tsc++;
1321 else
1322 kvm->arch.nr_vcpus_matched_tsc = 0;
1323
1324 kvm_track_tsc_matching(vcpu);
1325 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1326}
e26101b1 1327
99e3e30a
ZA		 1328EXPORT_SYMBOL_GPL(kvm_write_tsc);
1329
d828199e
MT		 1330#ifdef CONFIG_X86_64
1331
1332static cycle_t read_tsc(void)
1333{
1334 cycle_t ret;
1335 u64 last;
1336
1337 /*
1338 * Empirically, a fence (of type that depends on the CPU)
1339 * before rdtsc is enough to ensure that rdtsc is ordered
1340 * with respect to loads. The various CPU manuals are unclear
1341 * as to whether rdtsc can be reordered with later loads,
1342 * but no one has ever seen it happen.
1343 */
1344 rdtsc_barrier();
1345 ret = (cycle_t)vget_cycles();
1346
1347 last = pvclock_gtod_data.clock.cycle_last;
1348
1349 if (likely(ret >= last))
1350 return ret;
1351
1352 /*
1353 * GCC likes to generate cmov here, but this branch is extremely
1354 * predictable (it's just a funciton of time and the likely is
1355 * very likely) and there's a data dependence, so force GCC
1356 * to generate a branch instead. I don't barrier() because
1357 * we don't actually need a barrier, and if this function
1358 * ever gets inlined it will generate worse code.
1359 */
1360 asm volatile ("");
1361 return last;
1362}
1363
1364static inline u64 vgettsc(cycle_t *cycle_now)
1365{
1366 long v;
1367 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1368
1369 *cycle_now = read_tsc();
1370
1371 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1372 return v * gtod->clock.mult;
1373}
1374
1375static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1376{
1377 unsigned long seq;
1378 u64 ns;
1379 int mode;
1380 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1381
1382 ts->tv_nsec = 0;
1383 do {
1384 seq = read_seqcount_begin(&gtod->seq);
1385 mode = gtod->clock.vclock_mode;
1386 ts->tv_sec = gtod->monotonic_time_sec;
1387 ns = gtod->monotonic_time_snsec;
1388 ns += vgettsc(cycle_now);
1389 ns >>= gtod->clock.shift;
1390 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1391 timespec_add_ns(ts, ns);
1392
1393 return mode;
1394}
1395
1396/* returns true if host is using tsc clocksource */
1397static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1398{
1399 struct timespec ts;
1400
1401 /* checked again under seqlock below */
1402 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1403 return false;
1404
1405 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1406 return false;
1407
1408 monotonic_to_bootbased(&ts);
1409 *kernel_ns = timespec_to_ns(&ts);
1410
1411 return true;
1412}
1413#endif
1414
1415/*
1416 *
b48aa97e
MT		 1417 * Assuming a stable TSC across physical CPUS, and a stable TSC
1418 * across virtual CPUs, the following condition is possible.
1419 * Each numbered line represents an event visible to both
d828199e
MT		 1420 * CPUs at the next numbered event.
1421 *
1422 * "timespecX" represents host monotonic time. "tscX" represents
1423 * RDTSC value.
1424 *
1425 * VCPU0 on CPU0 | VCPU1 on CPU1
1426 *
1427 * 1. read timespec0,tsc0
1428 * 2. | timespec1 = timespec0 + N
1429 * | tsc1 = tsc0 + M
1430 * 3. transition to guest | transition to guest
1431 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1432 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1433 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1434 *
1435 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1436 *
1437 * - ret0 < ret1
1438 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1439 * ...
1440 * - 0 < N - M => M < N
1441 *
1442 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1443 * always the case (the difference between two distinct xtime instances
1444 * might be smaller then the difference between corresponding TSC reads,
1445 * when updating guest vcpus pvclock areas).
1446 *
1447 * To avoid that problem, do not allow visibility of distinct
1448 * system_timestamp/tsc_timestamp values simultaneously: use a master
1449 * copy of host monotonic time values. Update that master copy
1450 * in lockstep.
1451 *
b48aa97e 1452 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1453 *
1454 */
1455
1456static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1457{
1458#ifdef CONFIG_X86_64
1459 struct kvm_arch *ka = &kvm->arch;
1460 int vclock_mode;
b48aa97e
MT		 1461 bool host_tsc_clocksource, vcpus_matched;
1462
1463 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1464 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1465
1466 /*
1467 * If the host uses TSC clock, then passthrough TSC as stable
1468 * to the guest.
1469 */
b48aa97e 1470 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1471 &ka->master_kernel_ns,
1472 &ka->master_cycle_now);
1473
b48aa97e
MT		 1474 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1475
d828199e
MT		 1476 if (ka->use_master_clock)
1477 atomic_set(&kvm_guest_has_master_clock, 1);
1478
1479 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1480 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1481 vcpus_matched);
d828199e
MT		 1482#endif
1483}
1484
2e762ff7
MT		 1485static void kvm_gen_update_masterclock(struct kvm *kvm)
1486{
1487#ifdef CONFIG_X86_64
1488 int i;
1489 struct kvm_vcpu *vcpu;
1490 struct kvm_arch *ka = &kvm->arch;
1491
1492 spin_lock(&ka->pvclock_gtod_sync_lock);
1493 kvm_make_mclock_inprogress_request(kvm);
1494 /* no guest entries from this point */
1495 pvclock_update_vm_gtod_copy(kvm);
1496
1497 kvm_for_each_vcpu(i, vcpu, kvm)
1498 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1499
1500 /* guest entries allowed */
1501 kvm_for_each_vcpu(i, vcpu, kvm)
1502 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1503
1504 spin_unlock(&ka->pvclock_gtod_sync_lock);
1505#endif
1506}
1507
34c238a1 1508static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1509{
d828199e 1510 unsigned long flags, this_tsc_khz;
18068523 1511 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1512 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1513 s64 kernel_ns;
d828199e 1514 u64 tsc_timestamp, host_tsc;
0b79459b 1515 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1516 u8 pvclock_flags;
d828199e
MT		 1517 bool use_master_clock;
1518
1519 kernel_ns = 0;
1520 host_tsc = 0;
18068523 1521
d828199e
MT		 1522 /*
1523 * If the host uses TSC clock, then passthrough TSC as stable
1524 * to the guest.
1525 */
1526 spin_lock(&ka->pvclock_gtod_sync_lock);
1527 use_master_clock = ka->use_master_clock;
1528 if (use_master_clock) {
1529 host_tsc = ka->master_cycle_now;
1530 kernel_ns = ka->master_kernel_ns;
1531 }
1532 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1533
1534 /* Keep irq disabled to prevent changes to the clock */
1535 local_irq_save(flags);
1536 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1537 if (unlikely(this_tsc_khz == 0)) {
1538 local_irq_restore(flags);
1539 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1540 return 1;
1541 }
d828199e
MT		 1542 if (!use_master_clock) {
1543 host_tsc = native_read_tsc();
1544 kernel_ns = get_kernel_ns();
1545 }
1546
1547 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1548
c285545f
ZA		 1549 /*
1550 * We may have to catch up the TSC to match elapsed wall clock
1551 * time for two reasons, even if kvmclock is used.
1552 * 1) CPU could have been running below the maximum TSC rate
1553 * 2) Broken TSC compensation resets the base at each VCPU
1554 * entry to avoid unknown leaps of TSC even when running
1555 * again on the same CPU. This may cause apparent elapsed
1556 * time to disappear, and the guest to stand still or run
1557 * very slowly.
1558 */
1559 if (vcpu->tsc_catchup) {
1560 u64 tsc = compute_guest_tsc(v, kernel_ns);
1561 if (tsc > tsc_timestamp) {
f1e2b260 1562 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1563 tsc_timestamp = tsc;
1564 }
50d0a0f9
GH		 1565 }
1566
18068523
GOC		 1567 local_irq_restore(flags);
1568
0b79459b 1569 if (!vcpu->pv_time_enabled)
c285545f 1570 return 0;
18068523 1571
e48672fa 1572 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1573 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1574 &vcpu->hv_clock.tsc_shift,
1575 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1576 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1577 }
1578
1579 /* With all the info we got, fill in the values */
1d5f066e 1580 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1581 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1582 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1583
18068523
GOC		 1584 /*
1585 * The interface expects us to write an even number signaling that the
1586 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1587 * state, we just increase by 2 at the end.
18068523 1588 */
50d0a0f9 1589 vcpu->hv_clock.version += 2;
18068523 1590
0b79459b
AH		 1591 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1592 &guest_hv_clock, sizeof(guest_hv_clock))))
1593 return 0;
78c0337a
MT		 1594
1595 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1596 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1597
1598 if (vcpu->pvclock_set_guest_stopped_request) {
1599 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1600 vcpu->pvclock_set_guest_stopped_request = false;
1601 }
1602
d828199e
MT		 1603 /* If the host uses TSC clocksource, then it is stable */
1604 if (use_master_clock)
1605 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1606
78c0337a
MT		 1607 vcpu->hv_clock.flags = pvclock_flags;
1608
0b79459b
AH		 1609 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1610 &vcpu->hv_clock,
1611 sizeof(vcpu->hv_clock));
8cfdc000 1612 return 0;
c8076604
GH		 1613}
1614
0061d53d
MT		 1615/*
1616 * kvmclock updates which are isolated to a given vcpu, such as
1617 * vcpu->cpu migration, should not allow system_timestamp from
1618 * the rest of the vcpus to remain static. Otherwise ntp frequency
1619 * correction applies to one vcpu's system_timestamp but not
1620 * the others.
1621 *
1622 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1623 * We need to rate-limit these requests though, as they can
1624 * considerably slow guests that have a large number of vcpus.
1625 * The time for a remote vcpu to update its kvmclock is bound
1626 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1627 */
1628
7e44e449
AJ		 1629#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1630
1631static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1632{
1633 int i;
7e44e449
AJ		 1634 struct delayed_work *dwork = to_delayed_work(work);
1635 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1636 kvmclock_update_work);
1637 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1638 struct kvm_vcpu *vcpu;
1639
1640 kvm_for_each_vcpu(i, vcpu, kvm) {
1641 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1642 kvm_vcpu_kick(vcpu);
1643 }
1644}
1645
7e44e449
AJ		 1646static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1647{
1648 struct kvm *kvm = v->kvm;
1649
1650 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1651 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1652 KVMCLOCK_UPDATE_DELAY);
1653}
1654
332967a3
AJ		 1655#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1656
1657static void kvmclock_sync_fn(struct work_struct *work)
1658{
1659 struct delayed_work *dwork = to_delayed_work(work);
1660 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1661 kvmclock_sync_work);
1662 struct kvm *kvm = container_of(ka, struct kvm, arch);
1663
1664 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1665 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1666 KVMCLOCK_SYNC_PERIOD);
1667}
1668
9ba075a6
AK		 1669static bool msr_mtrr_valid(unsigned msr)
1670{
1671 switch (msr) {
1672 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1673 case MSR_MTRRfix64K_00000:
1674 case MSR_MTRRfix16K_80000:
1675 case MSR_MTRRfix16K_A0000:
1676 case MSR_MTRRfix4K_C0000:
1677 case MSR_MTRRfix4K_C8000:
1678 case MSR_MTRRfix4K_D0000:
1679 case MSR_MTRRfix4K_D8000:
1680 case MSR_MTRRfix4K_E0000:
1681 case MSR_MTRRfix4K_E8000:
1682 case MSR_MTRRfix4K_F0000:
1683 case MSR_MTRRfix4K_F8000:
1684 case MSR_MTRRdefType:
1685 case MSR_IA32_CR_PAT:
1686 return true;
1687 case 0x2f8:
1688 return true;
1689 }
1690 return false;
1691}
1692
d6289b93
MT		 1693static bool valid_pat_type(unsigned t)
1694{
1695 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1696}
1697
1698static bool valid_mtrr_type(unsigned t)
1699{
1700 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1701}
1702
1703static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1704{
1705 int i;
1706
1707 if (!msr_mtrr_valid(msr))
1708 return false;
1709
1710 if (msr == MSR_IA32_CR_PAT) {
1711 for (i = 0; i < 8; i++)
1712 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1713 return false;
1714 return true;
1715 } else if (msr == MSR_MTRRdefType) {
1716 if (data & ~0xcff)
1717 return false;
1718 return valid_mtrr_type(data & 0xff);
1719 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1720 for (i = 0; i < 8 ; i++)
1721 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1722 return false;
1723 return true;
1724 }
1725
1726 /* variable MTRRs */
1727 return valid_mtrr_type(data & 0xff);
1728}
1729
9ba075a6
AK		 1730static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1731{
0bed3b56
SY		 1732 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1733
d6289b93 1734 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1735 return 1;
1736
0bed3b56
SY		 1737 if (msr == MSR_MTRRdefType) {
1738 vcpu->arch.mtrr_state.def_type = data;
1739 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1740 } else if (msr == MSR_MTRRfix64K_00000)
1741 p[0] = data;
1742 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1743 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1744 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1745 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1746 else if (msr == MSR_IA32_CR_PAT)
1747 vcpu->arch.pat = data;
1748 else { /* Variable MTRRs */
1749 int idx, is_mtrr_mask;
1750 u64 *pt;
1751
1752 idx = (msr - 0x200) / 2;
1753 is_mtrr_mask = msr - 0x200 - 2 * idx;
1754 if (!is_mtrr_mask)
1755 pt =
1756 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1757 else
1758 pt =
1759 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1760 *pt = data;
1761 }
1762
1763 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1764 return 0;
1765}
15c4a640 1766
890ca9ae 1767static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1768{
890ca9ae
HY		 1769 u64 mcg_cap = vcpu->arch.mcg_cap;
1770 unsigned bank_num = mcg_cap & 0xff;
1771
15c4a640 1772 switch (msr) {
15c4a640 1773 case MSR_IA32_MCG_STATUS:
890ca9ae 1774 vcpu->arch.mcg_status = data;
15c4a640 1775 break;
c7ac679c 1776 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1777 if (!(mcg_cap & MCG_CTL_P))
1778 return 1;
1779 if (data != 0 && data != ~(u64)0)
1780 return -1;
1781 vcpu->arch.mcg_ctl = data;
1782 break;
1783 default:
1784 if (msr >= MSR_IA32_MC0_CTL &&
1785 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1786 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1787 /* only 0 or all 1s can be written to IA32_MCi_CTL
1788 * some Linux kernels though clear bit 10 in bank 4 to
1789 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1790 * this to avoid an uncatched #GP in the guest
1791 */
890ca9ae 1792 if ((offset & 0x3) == 0 &&
114be429 1793 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1794 return -1;
1795 vcpu->arch.mce_banks[offset] = data;
1796 break;
1797 }
1798 return 1;
1799 }
1800 return 0;
1801}
1802
ffde22ac
ES		 1803static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1804{
1805 struct kvm *kvm = vcpu->kvm;
1806 int lm = is_long_mode(vcpu);
1807 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1808 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1809 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1810 : kvm->arch.xen_hvm_config.blob_size_32;
1811 u32 page_num = data & ~PAGE_MASK;
1812 u64 page_addr = data & PAGE_MASK;
1813 u8 *page;
1814 int r;
1815
1816 r = -E2BIG;
1817 if (page_num >= blob_size)
1818 goto out;
1819 r = -ENOMEM;
ff5c2c03
SL		 1820 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1821 if (IS_ERR(page)) {
1822 r = PTR_ERR(page);
ffde22ac 1823 goto out;
ff5c2c03 1824 }
ffde22ac
ES		 1825 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1826 goto out_free;
1827 r = 0;
1828out_free:
1829 kfree(page);
1830out:
1831 return r;
1832}
1833
55cd8e5a
GN		 1834static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1835{
1836 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1837}
1838
1839static bool kvm_hv_msr_partition_wide(u32 msr)
1840{
1841 bool r = false;
1842 switch (msr) {
1843 case HV_X64_MSR_GUEST_OS_ID:
1844 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1845 case HV_X64_MSR_REFERENCE_TSC:
1846 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1847 r = true;
1848 break;
1849 }
1850
1851 return r;
1852}
1853
1854static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1855{
1856 struct kvm *kvm = vcpu->kvm;
1857
1858 switch (msr) {
1859 case HV_X64_MSR_GUEST_OS_ID:
1860 kvm->arch.hv_guest_os_id = data;
1861 /* setting guest os id to zero disables hypercall page */
1862 if (!kvm->arch.hv_guest_os_id)
1863 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1864 break;
1865 case HV_X64_MSR_HYPERCALL: {
1866 u64 gfn;
1867 unsigned long addr;
1868 u8 instructions[4];
1869
1870 /* if guest os id is not set hypercall should remain disabled */
1871 if (!kvm->arch.hv_guest_os_id)
1872 break;
1873 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1874 kvm->arch.hv_hypercall = data;
1875 break;
1876 }
1877 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1878 addr = gfn_to_hva(kvm, gfn);
1879 if (kvm_is_error_hva(addr))
1880 return 1;
1881 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1882 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1883 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1884 return 1;
1885 kvm->arch.hv_hypercall = data;
b94b64c9 1886 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1887 break;
1888 }
e984097b
VR		 1889 case HV_X64_MSR_REFERENCE_TSC: {
1890 u64 gfn;
1891 HV_REFERENCE_TSC_PAGE tsc_ref;
1892 memset(&tsc_ref, 0, sizeof(tsc_ref));
1893 kvm->arch.hv_tsc_page = data;
1894 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1895 break;
1896 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1897 if (kvm_write_guest(kvm, data,
1898 &tsc_ref, sizeof(tsc_ref)))
1899 return 1;
1900 mark_page_dirty(kvm, gfn);
1901 break;
1902 }
55cd8e5a 1903 default:
a737f256
CD		 1904 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1905 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1906 return 1;
1907 }
1908 return 0;
1909}
1910
1911static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1912{
10388a07
GN		 1913 switch (msr) {
1914 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1915 u64 gfn;
10388a07 1916 unsigned long addr;
55cd8e5a 1917
10388a07
GN		 1918 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1919 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1920 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1921 return 1;
10388a07
GN		 1922 break;
1923 }
b3af1e88
VR		 1924 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1925 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1926 if (kvm_is_error_hva(addr))
1927 return 1;
8b0cedff 1928 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1929 return 1;
1930 vcpu->arch.hv_vapic = data;
b3af1e88 1931 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1932 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1933 return 1;
10388a07
GN		 1934 break;
1935 }
1936 case HV_X64_MSR_EOI:
1937 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1938 case HV_X64_MSR_ICR:
1939 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1940 case HV_X64_MSR_TPR:
1941 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1942 default:
a737f256
CD		 1943 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1944 "data 0x%llx\n", msr, data);
10388a07
GN		 1945 return 1;
1946 }
1947
1948 return 0;
55cd8e5a
GN		 1949}
1950
344d9588
GN		 1951static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1952{
1953 gpa_t gpa = data & ~0x3f;
1954
4a969980 1955 /* Bits 2:5 are reserved, Should be zero */
6adba527 1956 if (data & 0x3c)
344d9588
GN		 1957 return 1;
1958
1959 vcpu->arch.apf.msr_val = data;
1960
1961 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1962 kvm_clear_async_pf_completion_queue(vcpu);
1963 kvm_async_pf_hash_reset(vcpu);
1964 return 0;
1965 }
1966
8f964525
AH		 1967 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1968 sizeof(u32)))
344d9588
GN		 1969 return 1;
1970
6adba527 1971 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1972 kvm_async_pf_wakeup_all(vcpu);
1973 return 0;
1974}
1975
12f9a48f
GC		 1976static void kvmclock_reset(struct kvm_vcpu *vcpu)
1977{
0b79459b 1978 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1979}
1980
c9aaa895
GC		 1981static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1982{
1983 u64 delta;
1984
1985 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1986 return;
1987
1988 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1989 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1990 vcpu->arch.st.accum_steal = delta;
1991}
1992
1993static void record_steal_time(struct kvm_vcpu *vcpu)
1994{
1995 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1996 return;
1997
1998 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1999 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2000 return;
2001
2002 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2003 vcpu->arch.st.steal.version += 2;
2004 vcpu->arch.st.accum_steal = 0;
2005
2006 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2007 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2008}
2009
8fe8ab46 2010int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2011{
5753785f 2012 bool pr = false;
8fe8ab46
WA		 2013 u32 msr = msr_info->index;
2014 u64 data = msr_info->data;
5753785f 2015
15c4a640 2016 switch (msr) {
2e32b719
BP		 2017 case MSR_AMD64_NB_CFG:
2018 case MSR_IA32_UCODE_REV:
2019 case MSR_IA32_UCODE_WRITE:
2020 case MSR_VM_HSAVE_PA:
2021 case MSR_AMD64_PATCH_LOADER:
2022 case MSR_AMD64_BU_CFG2:
2023 break;
2024
15c4a640 2025 case MSR_EFER:
b69e8cae 2026 return set_efer(vcpu, data);
8f1589d9
AP		 2027 case MSR_K7_HWCR:
2028 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2029 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2030 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2031 if (data != 0) {
a737f256
CD		 2032 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2033 data);
8f1589d9
AP		 2034 return 1;
2035 }
15c4a640 2036 break;
f7c6d140
AP		 2037 case MSR_FAM10H_MMIO_CONF_BASE:
2038 if (data != 0) {
a737f256
CD		 2039 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2040 "0x%llx\n", data);
f7c6d140
AP		 2041 return 1;
2042 }
15c4a640 2043 break;
b5e2fec0
AG		 2044 case MSR_IA32_DEBUGCTLMSR:
2045 if (!data) {
2046 /* We support the non-activated case already */
2047 break;
2048 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2049 /* Values other than LBR and BTF are vendor-specific,
2050 thus reserved and should throw a #GP */
2051 return 1;
2052 }
a737f256
CD		 2053 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2054 __func__, data);
b5e2fec0 2055 break;
9ba075a6
AK		 2056 case 0x200 ... 0x2ff:
2057 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2058 case MSR_IA32_APICBASE:
58cb628d 2059 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2060 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2061 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2062 case MSR_IA32_TSCDEADLINE:
2063 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2064 break;
ba904635
WA		 2065 case MSR_IA32_TSC_ADJUST:
2066 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2067 if (!msr_info->host_initiated) {
2068 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2069 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2070 }
2071 vcpu->arch.ia32_tsc_adjust_msr = data;
2072 }
2073 break;
15c4a640 2074 case MSR_IA32_MISC_ENABLE:
ad312c7c 2075 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2076 break;
11c6bffa 2077 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2078 case MSR_KVM_WALL_CLOCK:
2079 vcpu->kvm->arch.wall_clock = data;
2080 kvm_write_wall_clock(vcpu->kvm, data);
2081 break;
11c6bffa 2082 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2083 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2084 u64 gpa_offset;
12f9a48f 2085 kvmclock_reset(vcpu);
18068523
GOC		 2086
2087 vcpu->arch.time = data;
0061d53d 2088 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2089
2090 /* we verify if the enable bit is set... */
2091 if (!(data & 1))
2092 break;
2093
0b79459b 2094 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2095
0b79459b 2096 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2097 &vcpu->arch.pv_time, data & ~1ULL,
2098 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2099 vcpu->arch.pv_time_enabled = false;
2100 else
2101 vcpu->arch.pv_time_enabled = true;
32cad84f 2102
18068523
GOC		 2103 break;
2104 }
344d9588
GN		 2105 case MSR_KVM_ASYNC_PF_EN:
2106 if (kvm_pv_enable_async_pf(vcpu, data))
2107 return 1;
2108 break;
c9aaa895
GC		 2109 case MSR_KVM_STEAL_TIME:
2110
2111 if (unlikely(!sched_info_on()))
2112 return 1;
2113
2114 if (data & KVM_STEAL_RESERVED_MASK)
2115 return 1;
2116
2117 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2118 data & KVM_STEAL_VALID_BITS,
2119 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2120 return 1;
2121
2122 vcpu->arch.st.msr_val = data;
2123
2124 if (!(data & KVM_MSR_ENABLED))
2125 break;
2126
2127 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2128
2129 preempt_disable();
2130 accumulate_steal_time(vcpu);
2131 preempt_enable();
2132
2133 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2134
2135 break;
ae7a2a3f
MT		 2136 case MSR_KVM_PV_EOI_EN:
2137 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2138 return 1;
2139 break;
c9aaa895 2140
890ca9ae
HY		 2141 case MSR_IA32_MCG_CTL:
2142 case MSR_IA32_MCG_STATUS:
2143 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2144 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2145
2146 /* Performance counters are not protected by a CPUID bit,
2147 * so we should check all of them in the generic path for the sake of
2148 * cross vendor migration.
2149 * Writing a zero into the event select MSRs disables them,
2150 * which we perfectly emulate ;-). Any other value should be at least
2151 * reported, some guests depend on them.
2152 */
71db6023
AP		 2153 case MSR_K7_EVNTSEL0:
2154 case MSR_K7_EVNTSEL1:
2155 case MSR_K7_EVNTSEL2:
2156 case MSR_K7_EVNTSEL3:
2157 if (data != 0)
a737f256
CD		 2158 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2159 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2160 break;
2161 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2162 * so we ignore writes to make it happy.
2163 */
71db6023
AP		 2164 case MSR_K7_PERFCTR0:
2165 case MSR_K7_PERFCTR1:
2166 case MSR_K7_PERFCTR2:
2167 case MSR_K7_PERFCTR3:
a737f256
CD		 2168 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2169 "0x%x data 0x%llx\n", msr, data);
71db6023 2170 break;
5753785f
GN		 2171 case MSR_P6_PERFCTR0:
2172 case MSR_P6_PERFCTR1:
2173 pr = true;
2174 case MSR_P6_EVNTSEL0:
2175 case MSR_P6_EVNTSEL1:
2176 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2177 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2178
2179 if (pr || data != 0)
a737f256
CD		 2180 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2181 "0x%x data 0x%llx\n", msr, data);
5753785f 2182 break;
84e0cefa
JS		 2183 case MSR_K7_CLK_CTL:
2184 /*
2185 * Ignore all writes to this no longer documented MSR.
2186 * Writes are only relevant for old K7 processors,
2187 * all pre-dating SVM, but a recommended workaround from
4a969980 2188 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2189 * affected processor models on the command line, hence
2190 * the need to ignore the workaround.
2191 */
2192 break;
55cd8e5a
GN		 2193 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2194 if (kvm_hv_msr_partition_wide(msr)) {
2195 int r;
2196 mutex_lock(&vcpu->kvm->lock);
2197 r = set_msr_hyperv_pw(vcpu, msr, data);
2198 mutex_unlock(&vcpu->kvm->lock);
2199 return r;
2200 } else
2201 return set_msr_hyperv(vcpu, msr, data);
2202 break;
91c9c3ed 2203 case MSR_IA32_BBL_CR_CTL3:
2204 /* Drop writes to this legacy MSR -- see rdmsr
2205 * counterpart for further detail.
2206 */
a737f256 2207 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2208 break;
2b036c6b
BO		 2209 case MSR_AMD64_OSVW_ID_LENGTH:
2210 if (!guest_cpuid_has_osvw(vcpu))
2211 return 1;
2212 vcpu->arch.osvw.length = data;
2213 break;
2214 case MSR_AMD64_OSVW_STATUS:
2215 if (!guest_cpuid_has_osvw(vcpu))
2216 return 1;
2217 vcpu->arch.osvw.status = data;
2218 break;
15c4a640 2219 default:
ffde22ac
ES		 2220 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2221 return xen_hvm_config(vcpu, data);
f5132b01 2222 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2223 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2224 if (!ignore_msrs) {
a737f256
CD		 2225 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2226 msr, data);
ed85c068
AP		 2227 return 1;
2228 } else {
a737f256
CD		 2229 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2230 msr, data);
ed85c068
AP		 2231 break;
2232 }
15c4a640
CO		 2233 }
2234 return 0;
2235}
2236EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2237
2238
2239/*
2240 * Reads an msr value (of 'msr_index') into 'pdata'.
2241 * Returns 0 on success, non-0 otherwise.
2242 * Assumes vcpu_load() was already called.
2243 */
2244int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2245{
2246 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2247}
2248
9ba075a6
AK		 2249static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2250{
0bed3b56
SY		 2251 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2252
9ba075a6
AK		 2253 if (!msr_mtrr_valid(msr))
2254 return 1;
2255
0bed3b56
SY		 2256 if (msr == MSR_MTRRdefType)
2257 *pdata = vcpu->arch.mtrr_state.def_type +
2258 (vcpu->arch.mtrr_state.enabled << 10);
2259 else if (msr == MSR_MTRRfix64K_00000)
2260 *pdata = p[0];
2261 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2262 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2263 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2264 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2265 else if (msr == MSR_IA32_CR_PAT)
2266 *pdata = vcpu->arch.pat;
2267 else { /* Variable MTRRs */
2268 int idx, is_mtrr_mask;
2269 u64 *pt;
2270
2271 idx = (msr - 0x200) / 2;
2272 is_mtrr_mask = msr - 0x200 - 2 * idx;
2273 if (!is_mtrr_mask)
2274 pt =
2275 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2276 else
2277 pt =
2278 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2279 *pdata = *pt;
2280 }
2281
9ba075a6
AK		 2282 return 0;
2283}
2284
890ca9ae 2285static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2286{
2287 u64 data;
890ca9ae
HY		 2288 u64 mcg_cap = vcpu->arch.mcg_cap;
2289 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2290
2291 switch (msr) {
15c4a640
CO		 2292 case MSR_IA32_P5_MC_ADDR:
2293 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2294 data = 0;
2295 break;
15c4a640 2296 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2297 data = vcpu->arch.mcg_cap;
2298 break;
c7ac679c 2299 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2300 if (!(mcg_cap & MCG_CTL_P))
2301 return 1;
2302 data = vcpu->arch.mcg_ctl;
2303 break;
2304 case MSR_IA32_MCG_STATUS:
2305 data = vcpu->arch.mcg_status;
2306 break;
2307 default:
2308 if (msr >= MSR_IA32_MC0_CTL &&
2309 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2310 u32 offset = msr - MSR_IA32_MC0_CTL;
2311 data = vcpu->arch.mce_banks[offset];
2312 break;
2313 }
2314 return 1;
2315 }
2316 *pdata = data;
2317 return 0;
2318}
2319
55cd8e5a
GN		 2320static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2321{
2322 u64 data = 0;
2323 struct kvm *kvm = vcpu->kvm;
2324
2325 switch (msr) {
2326 case HV_X64_MSR_GUEST_OS_ID:
2327 data = kvm->arch.hv_guest_os_id;
2328 break;
2329 case HV_X64_MSR_HYPERCALL:
2330 data = kvm->arch.hv_hypercall;
2331 break;
e984097b
VR		 2332 case HV_X64_MSR_TIME_REF_COUNT: {
2333 data =
2334 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2335 break;
2336 }
2337 case HV_X64_MSR_REFERENCE_TSC:
2338 data = kvm->arch.hv_tsc_page;
2339 break;
55cd8e5a 2340 default:
a737f256 2341 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2342 return 1;
2343 }
2344
2345 *pdata = data;
2346 return 0;
2347}
2348
2349static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2350{
2351 u64 data = 0;
2352
2353 switch (msr) {
2354 case HV_X64_MSR_VP_INDEX: {
2355 int r;
2356 struct kvm_vcpu *v;
684851a1
TY		 2357 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2358 if (v == vcpu) {
55cd8e5a 2359 data = r;
684851a1
TY		 2360 break;
2361 }
2362 }
55cd8e5a
GN		 2363 break;
2364 }
10388a07
GN		 2365 case HV_X64_MSR_EOI:
2366 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2367 case HV_X64_MSR_ICR:
2368 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2369 case HV_X64_MSR_TPR:
2370 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2371 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2372 data = vcpu->arch.hv_vapic;
2373 break;
55cd8e5a 2374 default:
a737f256 2375 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2376 return 1;
2377 }
2378 *pdata = data;
2379 return 0;
2380}
2381
890ca9ae
HY		 2382int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2383{
2384 u64 data;
2385
2386 switch (msr) {
890ca9ae 2387 case MSR_IA32_PLATFORM_ID:
15c4a640 2388 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2389 case MSR_IA32_DEBUGCTLMSR:
2390 case MSR_IA32_LASTBRANCHFROMIP:
2391 case MSR_IA32_LASTBRANCHTOIP:
2392 case MSR_IA32_LASTINTFROMIP:
2393 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2394 case MSR_K8_SYSCFG:
2395 case MSR_K7_HWCR:
61a6bd67 2396 case MSR_VM_HSAVE_PA:
9e699624 2397 case MSR_K7_EVNTSEL0:
1f3ee616 2398 case MSR_K7_PERFCTR0:
1fdbd48c 2399 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2400 case MSR_AMD64_NB_CFG:
f7c6d140 2401 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2402 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2403 data = 0;
2404 break;
5753785f
GN		 2405 case MSR_P6_PERFCTR0:
2406 case MSR_P6_PERFCTR1:
2407 case MSR_P6_EVNTSEL0:
2408 case MSR_P6_EVNTSEL1:
2409 if (kvm_pmu_msr(vcpu, msr))
2410 return kvm_pmu_get_msr(vcpu, msr, pdata);
2411 data = 0;
2412 break;
742bc670
MT		 2413 case MSR_IA32_UCODE_REV:
2414 data = 0x100000000ULL;
2415 break;
9ba075a6
AK		 2416 case MSR_MTRRcap:
2417 data = 0x500 | KVM_NR_VAR_MTRR;
2418 break;
2419 case 0x200 ... 0x2ff:
2420 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2421 case 0xcd: /* fsb frequency */
2422 data = 3;
2423 break;
7b914098
JS		 2424 /*
2425 * MSR_EBC_FREQUENCY_ID
2426 * Conservative value valid for even the basic CPU models.
2427 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2428 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2429 * and 266MHz for model 3, or 4. Set Core Clock
2430 * Frequency to System Bus Frequency Ratio to 1 (bits
2431 * 31:24) even though these are only valid for CPU
2432 * models > 2, however guests may end up dividing or
2433 * multiplying by zero otherwise.
2434 */
2435 case MSR_EBC_FREQUENCY_ID:
2436 data = 1 << 24;
2437 break;
15c4a640
CO		 2438 case MSR_IA32_APICBASE:
2439 data = kvm_get_apic_base(vcpu);
2440 break;
0105d1a5
GN		 2441 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2442 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2443 break;
a3e06bbe
LJ		 2444 case MSR_IA32_TSCDEADLINE:
2445 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2446 break;
ba904635
WA		 2447 case MSR_IA32_TSC_ADJUST:
2448 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2449 break;
15c4a640 2450 case MSR_IA32_MISC_ENABLE:
ad312c7c 2451 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2452 break;
847f0ad8
AG		 2453 case MSR_IA32_PERF_STATUS:
2454 /* TSC increment by tick */
2455 data = 1000ULL;
2456 /* CPU multiplier */
2457 data |= (((uint64_t)4ULL) << 40);
2458 break;
15c4a640 2459 case MSR_EFER:
f6801dff 2460 data = vcpu->arch.efer;
15c4a640 2461 break;
18068523 2462 case MSR_KVM_WALL_CLOCK:
11c6bffa 2463 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2464 data = vcpu->kvm->arch.wall_clock;
2465 break;
2466 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2467 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2468 data = vcpu->arch.time;
2469 break;
344d9588
GN		 2470 case MSR_KVM_ASYNC_PF_EN:
2471 data = vcpu->arch.apf.msr_val;
2472 break;
c9aaa895
GC		 2473 case MSR_KVM_STEAL_TIME:
2474 data = vcpu->arch.st.msr_val;
2475 break;
1d92128f
MT		 2476 case MSR_KVM_PV_EOI_EN:
2477 data = vcpu->arch.pv_eoi.msr_val;
2478 break;
890ca9ae
HY		 2479 case MSR_IA32_P5_MC_ADDR:
2480 case MSR_IA32_P5_MC_TYPE:
2481 case MSR_IA32_MCG_CAP:
2482 case MSR_IA32_MCG_CTL:
2483 case MSR_IA32_MCG_STATUS:
2484 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2485 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2486 case MSR_K7_CLK_CTL:
2487 /*
2488 * Provide expected ramp-up count for K7. All other
2489 * are set to zero, indicating minimum divisors for
2490 * every field.
2491 *
2492 * This prevents guest kernels on AMD host with CPU
2493 * type 6, model 8 and higher from exploding due to
2494 * the rdmsr failing.
2495 */
2496 data = 0x20000000;
2497 break;
55cd8e5a
GN		 2498 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2499 if (kvm_hv_msr_partition_wide(msr)) {
2500 int r;
2501 mutex_lock(&vcpu->kvm->lock);
2502 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2503 mutex_unlock(&vcpu->kvm->lock);
2504 return r;
2505 } else
2506 return get_msr_hyperv(vcpu, msr, pdata);
2507 break;
91c9c3ed 2508 case MSR_IA32_BBL_CR_CTL3:
2509 /* This legacy MSR exists but isn't fully documented in current
2510 * silicon. It is however accessed by winxp in very narrow
2511 * scenarios where it sets bit #19, itself documented as
2512 * a "reserved" bit. Best effort attempt to source coherent
2513 * read data here should the balance of the register be
2514 * interpreted by the guest:
2515 *
2516 * L2 cache control register 3: 64GB range, 256KB size,
2517 * enabled, latency 0x1, configured
2518 */
2519 data = 0xbe702111;
2520 break;
2b036c6b
BO		 2521 case MSR_AMD64_OSVW_ID_LENGTH:
2522 if (!guest_cpuid_has_osvw(vcpu))
2523 return 1;
2524 data = vcpu->arch.osvw.length;
2525 break;
2526 case MSR_AMD64_OSVW_STATUS:
2527 if (!guest_cpuid_has_osvw(vcpu))
2528 return 1;
2529 data = vcpu->arch.osvw.status;
2530 break;
15c4a640 2531 default:
f5132b01
GN		 2532 if (kvm_pmu_msr(vcpu, msr))
2533 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2534 if (!ignore_msrs) {
a737f256 2535 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2536 return 1;
2537 } else {
a737f256 2538 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2539 data = 0;
2540 }
2541 break;
15c4a640
CO		 2542 }
2543 *pdata = data;
2544 return 0;
2545}
2546EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2547
313a3dc7
CO		 2548/*
2549 * Read or write a bunch of msrs. All parameters are kernel addresses.
2550 *
2551 * @return number of msrs set successfully.
2552 */
2553static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2554 struct kvm_msr_entry *entries,
2555 int (*do_msr)(struct kvm_vcpu *vcpu,
2556 unsigned index, u64 *data))
2557{
f656ce01 2558 int i, idx;
313a3dc7 2559
f656ce01 2560 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2561 for (i = 0; i < msrs->nmsrs; ++i)
2562 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2563 break;
f656ce01 2564 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2565
313a3dc7
CO		 2566 return i;
2567}
2568
2569/*
2570 * Read or write a bunch of msrs. Parameters are user addresses.
2571 *
2572 * @return number of msrs set successfully.
2573 */
2574static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2575 int (*do_msr)(struct kvm_vcpu *vcpu,
2576 unsigned index, u64 *data),
2577 int writeback)
2578{
2579 struct kvm_msrs msrs;
2580 struct kvm_msr_entry *entries;
2581 int r, n;
2582 unsigned size;
2583
2584 r = -EFAULT;
2585 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2586 goto out;
2587
2588 r = -E2BIG;
2589 if (msrs.nmsrs >= MAX_IO_MSRS)
2590 goto out;
2591
313a3dc7 2592 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2593 entries = memdup_user(user_msrs->entries, size);
2594 if (IS_ERR(entries)) {
2595 r = PTR_ERR(entries);
313a3dc7 2596 goto out;
ff5c2c03 2597 }
313a3dc7
CO		 2598
2599 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2600 if (r < 0)
2601 goto out_free;
2602
2603 r = -EFAULT;
2604 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2605 goto out_free;
2606
2607 r = n;
2608
2609out_free:
7a73c028 2610 kfree(entries);
313a3dc7
CO		 2611out:
2612 return r;
2613}
2614
018d00d2
ZX		 2615int kvm_dev_ioctl_check_extension(long ext)
2616{
2617 int r;
2618
2619 switch (ext) {
2620 case KVM_CAP_IRQCHIP:
2621 case KVM_CAP_HLT:
2622 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2623 case KVM_CAP_SET_TSS_ADDR:
07716717 2624 case KVM_CAP_EXT_CPUID:
9c15bb1d 2625 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2626 case KVM_CAP_CLOCKSOURCE:
7837699f 2627 case KVM_CAP_PIT:
a28e4f5a 2628 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2629 case KVM_CAP_MP_STATE:
ed848624 2630 case KVM_CAP_SYNC_MMU:
a355c85c 2631 case KVM_CAP_USER_NMI:
52d939a0 2632 case KVM_CAP_REINJECT_CONTROL:
4925663a 2633 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2634 case KVM_CAP_IRQFD:
d34e6b17 2635 case KVM_CAP_IOEVENTFD:
f848a5a8 2636 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2637 case KVM_CAP_PIT2:
e9f42757 2638 case KVM_CAP_PIT_STATE2:
b927a3ce 2639 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2640 case KVM_CAP_XEN_HVM:
afbcf7ab 2641 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2642 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2643 case KVM_CAP_HYPERV:
10388a07 2644 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2645 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2646 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2647 case KVM_CAP_DEBUGREGS:
d2be1651 2648 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2649 case KVM_CAP_XSAVE:
344d9588 2650 case KVM_CAP_ASYNC_PF:
92a1f12d 2651 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2652 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2653 case KVM_CAP_READONLY_MEM:
5f66b620 2654 case KVM_CAP_HYPERV_TIME:
100943c5 2655 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2656#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2657 case KVM_CAP_ASSIGN_DEV_IRQ:
2658 case KVM_CAP_PCI_2_3:
2659#endif
018d00d2
ZX		 2660 r = 1;
2661 break;
542472b5
LV		 2662 case KVM_CAP_COALESCED_MMIO:
2663 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2664 break;
774ead3a
AK		 2665 case KVM_CAP_VAPIC:
2666 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2667 break;
f725230a 2668 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2669 r = KVM_SOFT_MAX_VCPUS;
2670 break;
2671 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2672 r = KVM_MAX_VCPUS;
2673 break;
a988b910 2674 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2675 r = KVM_USER_MEM_SLOTS;
a988b910 2676 break;
a68a6a72
MT		 2677 case KVM_CAP_PV_MMU: /* obsolete */
2678 r = 0;
2f333bcb 2679 break;
4cee4b72 2680#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2681 case KVM_CAP_IOMMU:
a1b60c1c 2682 r = iommu_present(&pci_bus_type);
62c476c7 2683 break;
4cee4b72 2684#endif
890ca9ae
HY		 2685 case KVM_CAP_MCE:
2686 r = KVM_MAX_MCE_BANKS;
2687 break;
2d5b5a66
SY		 2688 case KVM_CAP_XCRS:
2689 r = cpu_has_xsave;
2690 break;
92a1f12d
JR		 2691 case KVM_CAP_TSC_CONTROL:
2692 r = kvm_has_tsc_control;
2693 break;
4d25a066
JK		 2694 case KVM_CAP_TSC_DEADLINE_TIMER:
2695 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2696 break;
018d00d2
ZX		 2697 default:
2698 r = 0;
2699 break;
2700 }
2701 return r;
2702
2703}
2704
043405e1
CO		 2705long kvm_arch_dev_ioctl(struct file *filp,
2706 unsigned int ioctl, unsigned long arg)
2707{
2708 void __user *argp = (void __user *)arg;
2709 long r;
2710
2711 switch (ioctl) {
2712 case KVM_GET_MSR_INDEX_LIST: {
2713 struct kvm_msr_list __user *user_msr_list = argp;
2714 struct kvm_msr_list msr_list;
2715 unsigned n;
2716
2717 r = -EFAULT;
2718 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2719 goto out;
2720 n = msr_list.nmsrs;
2721 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2722 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2723 goto out;
2724 r = -E2BIG;
e125e7b6 2725 if (n < msr_list.nmsrs)
043405e1
CO		 2726 goto out;
2727 r = -EFAULT;
2728 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2729 num_msrs_to_save * sizeof(u32)))
2730 goto out;
e125e7b6 2731 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2732 &emulated_msrs,
2733 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2734 goto out;
2735 r = 0;
2736 break;
2737 }
9c15bb1d
BP		 2738 case KVM_GET_SUPPORTED_CPUID:
2739 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2740 struct kvm_cpuid2 __user *cpuid_arg = argp;
2741 struct kvm_cpuid2 cpuid;
2742
2743 r = -EFAULT;
2744 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2745 goto out;
9c15bb1d
BP		 2746
2747 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2748 ioctl);
674eea0f
AK		 2749 if (r)
2750 goto out;
2751
2752 r = -EFAULT;
2753 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2754 goto out;
2755 r = 0;
2756 break;
2757 }
890ca9ae
HY		 2758 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2759 u64 mce_cap;
2760
2761 mce_cap = KVM_MCE_CAP_SUPPORTED;
2762 r = -EFAULT;
2763 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2764 goto out;
2765 r = 0;
2766 break;
2767 }
043405e1
CO		 2768 default:
2769 r = -EINVAL;
2770 }
2771out:
2772 return r;
2773}
2774
f5f48ee1
SY		 2775static void wbinvd_ipi(void *garbage)
2776{
2777 wbinvd();
2778}
2779
2780static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2781{
e0f0bbc5 2782 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2783}
2784
313a3dc7
CO		 2785void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2786{
f5f48ee1
SY		 2787 /* Address WBINVD may be executed by guest */
2788 if (need_emulate_wbinvd(vcpu)) {
2789 if (kvm_x86_ops->has_wbinvd_exit())
2790 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2791 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2792 smp_call_function_single(vcpu->cpu,
2793 wbinvd_ipi, NULL, 1);
2794 }
2795
313a3dc7 2796 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2797
0dd6a6ed
ZA		 2798 /* Apply any externally detected TSC adjustments (due to suspend) */
2799 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2800 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2801 vcpu->arch.tsc_offset_adjustment = 0;
2802 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2803 }
8f6055cb 2804
48434c20 2805 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2806 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2807 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2808 if (tsc_delta < 0)
2809 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2810 if (check_tsc_unstable()) {
b183aa58
ZA		 2811 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2812 vcpu->arch.last_guest_tsc);
2813 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2814 vcpu->arch.tsc_catchup = 1;
c285545f 2815 }
d98d07ca
MT		 2816 /*
2817 * On a host with synchronized TSC, there is no need to update
2818 * kvmclock on vcpu->cpu migration
2819 */
2820 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2821 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2822 if (vcpu->cpu != cpu)
2823 kvm_migrate_timers(vcpu);
e48672fa 2824 vcpu->cpu = cpu;
6b7d7e76 2825 }
c9aaa895
GC		 2826
2827 accumulate_steal_time(vcpu);
2828 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2829}
2830
2831void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2832{
02daab21 2833 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2834 kvm_put_guest_fpu(vcpu);
6f526ec5 2835 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2836}
2837
313a3dc7
CO		 2838static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2839 struct kvm_lapic_state *s)
2840{
5a71785d 2841 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2842 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2843
2844 return 0;
2845}
2846
2847static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2848 struct kvm_lapic_state *s)
2849{
64eb0620 2850 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2851 update_cr8_intercept(vcpu);
313a3dc7
CO		 2852
2853 return 0;
2854}
2855
f77bc6a4
ZX		 2856static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2857 struct kvm_interrupt *irq)
2858{
02cdb50f 2859 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2860 return -EINVAL;
2861 if (irqchip_in_kernel(vcpu->kvm))
2862 return -ENXIO;
f77bc6a4 2863
66fd3f7f 2864 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2865 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2866
f77bc6a4
ZX		 2867 return 0;
2868}
2869
c4abb7c9
JK		 2870static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2871{
c4abb7c9 2872 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2873
2874 return 0;
2875}
2876
b209749f
AK		 2877static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2878 struct kvm_tpr_access_ctl *tac)
2879{
2880 if (tac->flags)
2881 return -EINVAL;
2882 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2883 return 0;
2884}
2885
890ca9ae
HY		 2886static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2887 u64 mcg_cap)
2888{
2889 int r;
2890 unsigned bank_num = mcg_cap & 0xff, bank;
2891
2892 r = -EINVAL;
a9e38c3e 2893 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2894 goto out;
2895 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2896 goto out;
2897 r = 0;
2898 vcpu->arch.mcg_cap = mcg_cap;
2899 /* Init IA32_MCG_CTL to all 1s */
2900 if (mcg_cap & MCG_CTL_P)
2901 vcpu->arch.mcg_ctl = ~(u64)0;
2902 /* Init IA32_MCi_CTL to all 1s */
2903 for (bank = 0; bank < bank_num; bank++)
2904 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2905out:
2906 return r;
2907}
2908
2909static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2910 struct kvm_x86_mce *mce)
2911{
2912 u64 mcg_cap = vcpu->arch.mcg_cap;
2913 unsigned bank_num = mcg_cap & 0xff;
2914 u64 *banks = vcpu->arch.mce_banks;
2915
2916 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2917 return -EINVAL;
2918 /*
2919 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2920 * reporting is disabled
2921 */
2922 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2923 vcpu->arch.mcg_ctl != ~(u64)0)
2924 return 0;
2925 banks += 4 * mce->bank;
2926 /*
2927 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2928 * reporting is disabled for the bank
2929 */
2930 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2931 return 0;
2932 if (mce->status & MCI_STATUS_UC) {
2933 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2934 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2935 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2936 return 0;
2937 }
2938 if (banks[1] & MCI_STATUS_VAL)
2939 mce->status |= MCI_STATUS_OVER;
2940 banks[2] = mce->addr;
2941 banks[3] = mce->misc;
2942 vcpu->arch.mcg_status = mce->mcg_status;
2943 banks[1] = mce->status;
2944 kvm_queue_exception(vcpu, MC_VECTOR);
2945 } else if (!(banks[1] & MCI_STATUS_VAL)
2946 || !(banks[1] & MCI_STATUS_UC)) {
2947 if (banks[1] & MCI_STATUS_VAL)
2948 mce->status |= MCI_STATUS_OVER;
2949 banks[2] = mce->addr;
2950 banks[3] = mce->misc;
2951 banks[1] = mce->status;
2952 } else
2953 banks[1] |= MCI_STATUS_OVER;
2954 return 0;
2955}
2956
3cfc3092
JK		 2957static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2958 struct kvm_vcpu_events *events)
2959{
7460fb4a 2960 process_nmi(vcpu);
03b82a30
JK		 2961 events->exception.injected =
2962 vcpu->arch.exception.pending &&
2963 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2964 events->exception.nr = vcpu->arch.exception.nr;
2965 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2966 events->exception.pad = 0;
3cfc3092
JK		 2967 events->exception.error_code = vcpu->arch.exception.error_code;
2968
03b82a30
JK		 2969 events->interrupt.injected =
2970 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2971 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2972 events->interrupt.soft = 0;
48005f64
JK		 2973 events->interrupt.shadow =
2974 kvm_x86_ops->get_interrupt_shadow(vcpu,
2975 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2976
2977 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2978 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2979 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2980 events->nmi.pad = 0;
3cfc3092 2981
66450a21 2982 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2983
dab4b911 2984 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2985 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2986 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2987}
2988
2989static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2990 struct kvm_vcpu_events *events)
2991{
dab4b911 2992 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2993 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2994 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2995 return -EINVAL;
2996
7460fb4a 2997 process_nmi(vcpu);
3cfc3092
JK		 2998 vcpu->arch.exception.pending = events->exception.injected;
2999 vcpu->arch.exception.nr = events->exception.nr;
3000 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3001 vcpu->arch.exception.error_code = events->exception.error_code;
3002
3003 vcpu->arch.interrupt.pending = events->interrupt.injected;
3004 vcpu->arch.interrupt.nr = events->interrupt.nr;
3005 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3006 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3007 kvm_x86_ops->set_interrupt_shadow(vcpu,
3008 events->interrupt.shadow);
3cfc3092
JK		 3009
3010 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3011 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3012 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3013 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3014
66450a21
JK		 3015 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3016 kvm_vcpu_has_lapic(vcpu))
3017 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3018
3842d135
AK		 3019 kvm_make_request(KVM_REQ_EVENT, vcpu);
3020
3cfc3092
JK		 3021 return 0;
3022}
3023
a1efbe77
JK		 3024static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3025 struct kvm_debugregs *dbgregs)
3026{
73aaf249
JK		 3027 unsigned long val;
3028
a1efbe77 3029 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3030 _kvm_get_dr(vcpu, 6, &val);
3031 dbgregs->dr6 = val;
a1efbe77
JK		 3032 dbgregs->dr7 = vcpu->arch.dr7;
3033 dbgregs->flags = 0;
97e69aa6 3034 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3035}
3036
3037static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3038 struct kvm_debugregs *dbgregs)
3039{
3040 if (dbgregs->flags)
3041 return -EINVAL;
3042
a1efbe77
JK		 3043 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3044 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3045 kvm_update_dr6(vcpu);
a1efbe77 3046 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3047 kvm_update_dr7(vcpu);
a1efbe77 3048
a1efbe77
JK		 3049 return 0;
3050}
3051
2d5b5a66
SY		 3052static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3053 struct kvm_xsave *guest_xsave)
3054{
4344ee98 3055 if (cpu_has_xsave) {
2d5b5a66
SY		 3056 memcpy(guest_xsave->region,
3057 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3058 vcpu->arch.guest_xstate_size);
3059 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3060 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3061 } else {
2d5b5a66
SY		 3062 memcpy(guest_xsave->region,
3063 &vcpu->arch.guest_fpu.state->fxsave,
3064 sizeof(struct i387_fxsave_struct));
3065 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3066 XSTATE_FPSSE;
3067 }
3068}
3069
3070static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3071 struct kvm_xsave *guest_xsave)
3072{
3073 u64 xstate_bv =
3074 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3075
d7876f1b
PB		 3076 if (cpu_has_xsave) {
3077 /*
3078 * Here we allow setting states that are not present in
3079 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3080 * with old userspace.
3081 */
4ff41732 3082 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3083 return -EINVAL;
2d5b5a66 3084 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3085 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3086 } else {
2d5b5a66
SY		 3087 if (xstate_bv & ~XSTATE_FPSSE)
3088 return -EINVAL;
3089 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3090 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3091 }
3092 return 0;
3093}
3094
3095static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3096 struct kvm_xcrs *guest_xcrs)
3097{
3098 if (!cpu_has_xsave) {
3099 guest_xcrs->nr_xcrs = 0;
3100 return;
3101 }
3102
3103 guest_xcrs->nr_xcrs = 1;
3104 guest_xcrs->flags = 0;
3105 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3106 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3107}
3108
3109static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3110 struct kvm_xcrs *guest_xcrs)
3111{
3112 int i, r = 0;
3113
3114 if (!cpu_has_xsave)
3115 return -EINVAL;
3116
3117 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3118 return -EINVAL;
3119
3120 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3121 /* Only support XCR0 currently */
c67a04cb 3122 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3123 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3124 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3125 break;
3126 }
3127 if (r)
3128 r = -EINVAL;
3129 return r;
3130}
3131
1c0b28c2
EM		 3132/*
3133 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3134 * stopped by the hypervisor. This function will be called from the host only.
3135 * EINVAL is returned when the host attempts to set the flag for a guest that
3136 * does not support pv clocks.
3137 */
3138static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3139{
0b79459b 3140 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3141 return -EINVAL;
51d59c6b 3142 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3143 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3144 return 0;
3145}
3146
313a3dc7
CO		 3147long kvm_arch_vcpu_ioctl(struct file *filp,
3148 unsigned int ioctl, unsigned long arg)
3149{
3150 struct kvm_vcpu *vcpu = filp->private_data;
3151 void __user *argp = (void __user *)arg;
3152 int r;
d1ac91d8
AK		 3153 union {
3154 struct kvm_lapic_state *lapic;
3155 struct kvm_xsave *xsave;
3156 struct kvm_xcrs *xcrs;
3157 void *buffer;
3158 } u;
3159
3160 u.buffer = NULL;
313a3dc7
CO		 3161 switch (ioctl) {
3162 case KVM_GET_LAPIC: {
2204ae3c
MT		 3163 r = -EINVAL;
3164 if (!vcpu->arch.apic)
3165 goto out;
d1ac91d8 3166 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3167
b772ff36 3168 r = -ENOMEM;
d1ac91d8 3169 if (!u.lapic)
b772ff36 3170 goto out;
d1ac91d8 3171 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3172 if (r)
3173 goto out;
3174 r = -EFAULT;
d1ac91d8 3175 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3176 goto out;
3177 r = 0;
3178 break;
3179 }
3180 case KVM_SET_LAPIC: {
2204ae3c
MT		 3181 r = -EINVAL;
3182 if (!vcpu->arch.apic)
3183 goto out;
ff5c2c03 3184 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3185 if (IS_ERR(u.lapic))
3186 return PTR_ERR(u.lapic);
ff5c2c03 3187
d1ac91d8 3188 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3189 break;
3190 }
f77bc6a4
ZX		 3191 case KVM_INTERRUPT: {
3192 struct kvm_interrupt irq;
3193
3194 r = -EFAULT;
3195 if (copy_from_user(&irq, argp, sizeof irq))
3196 goto out;
3197 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3198 break;
3199 }
c4abb7c9
JK		 3200 case KVM_NMI: {
3201 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3202 break;
3203 }
313a3dc7
CO		 3204 case KVM_SET_CPUID: {
3205 struct kvm_cpuid __user *cpuid_arg = argp;
3206 struct kvm_cpuid cpuid;
3207
3208 r = -EFAULT;
3209 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3210 goto out;
3211 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3212 break;
3213 }
07716717
DK		 3214 case KVM_SET_CPUID2: {
3215 struct kvm_cpuid2 __user *cpuid_arg = argp;
3216 struct kvm_cpuid2 cpuid;
3217
3218 r = -EFAULT;
3219 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3220 goto out;
3221 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3222 cpuid_arg->entries);
07716717
DK		 3223 break;
3224 }
3225 case KVM_GET_CPUID2: {
3226 struct kvm_cpuid2 __user *cpuid_arg = argp;
3227 struct kvm_cpuid2 cpuid;
3228
3229 r = -EFAULT;
3230 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3231 goto out;
3232 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3233 cpuid_arg->entries);
07716717
DK		 3234 if (r)
3235 goto out;
3236 r = -EFAULT;
3237 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3238 goto out;
3239 r = 0;
3240 break;
3241 }
313a3dc7
CO		 3242 case KVM_GET_MSRS:
3243 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3244 break;
3245 case KVM_SET_MSRS:
3246 r = msr_io(vcpu, argp, do_set_msr, 0);
3247 break;
b209749f
AK		 3248 case KVM_TPR_ACCESS_REPORTING: {
3249 struct kvm_tpr_access_ctl tac;
3250
3251 r = -EFAULT;
3252 if (copy_from_user(&tac, argp, sizeof tac))
3253 goto out;
3254 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3255 if (r)
3256 goto out;
3257 r = -EFAULT;
3258 if (copy_to_user(argp, &tac, sizeof tac))
3259 goto out;
3260 r = 0;
3261 break;
3262 };
b93463aa
AK		 3263 case KVM_SET_VAPIC_ADDR: {
3264 struct kvm_vapic_addr va;
3265
3266 r = -EINVAL;
3267 if (!irqchip_in_kernel(vcpu->kvm))
3268 goto out;
3269 r = -EFAULT;
3270 if (copy_from_user(&va, argp, sizeof va))
3271 goto out;
fda4e2e8 3272 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3273 break;
3274 }
890ca9ae
HY		 3275 case KVM_X86_SETUP_MCE: {
3276 u64 mcg_cap;
3277
3278 r = -EFAULT;
3279 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3280 goto out;
3281 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3282 break;
3283 }
3284 case KVM_X86_SET_MCE: {
3285 struct kvm_x86_mce mce;
3286
3287 r = -EFAULT;
3288 if (copy_from_user(&mce, argp, sizeof mce))
3289 goto out;
3290 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3291 break;
3292 }
3cfc3092
JK		 3293 case KVM_GET_VCPU_EVENTS: {
3294 struct kvm_vcpu_events events;
3295
3296 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3297
3298 r = -EFAULT;
3299 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3300 break;
3301 r = 0;
3302 break;
3303 }
3304 case KVM_SET_VCPU_EVENTS: {
3305 struct kvm_vcpu_events events;
3306
3307 r = -EFAULT;
3308 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3309 break;
3310
3311 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3312 break;
3313 }
a1efbe77
JK		 3314 case KVM_GET_DEBUGREGS: {
3315 struct kvm_debugregs dbgregs;
3316
3317 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3318
3319 r = -EFAULT;
3320 if (copy_to_user(argp, &dbgregs,
3321 sizeof(struct kvm_debugregs)))
3322 break;
3323 r = 0;
3324 break;
3325 }
3326 case KVM_SET_DEBUGREGS: {
3327 struct kvm_debugregs dbgregs;
3328
3329 r = -EFAULT;
3330 if (copy_from_user(&dbgregs, argp,
3331 sizeof(struct kvm_debugregs)))
3332 break;
3333
3334 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3335 break;
3336 }
2d5b5a66 3337 case KVM_GET_XSAVE: {
d1ac91d8 3338 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3339 r = -ENOMEM;
d1ac91d8 3340 if (!u.xsave)
2d5b5a66
SY		 3341 break;
3342
d1ac91d8 3343 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3344
3345 r = -EFAULT;
d1ac91d8 3346 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3347 break;
3348 r = 0;
3349 break;
3350 }
3351 case KVM_SET_XSAVE: {
ff5c2c03 3352 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3353 if (IS_ERR(u.xsave))
3354 return PTR_ERR(u.xsave);
2d5b5a66 3355
d1ac91d8 3356 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3357 break;
3358 }
3359 case KVM_GET_XCRS: {
d1ac91d8 3360 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3361 r = -ENOMEM;
d1ac91d8 3362 if (!u.xcrs)
2d5b5a66
SY		 3363 break;
3364
d1ac91d8 3365 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3366
3367 r = -EFAULT;
d1ac91d8 3368 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3369 sizeof(struct kvm_xcrs)))
3370 break;
3371 r = 0;
3372 break;
3373 }
3374 case KVM_SET_XCRS: {
ff5c2c03 3375 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3376 if (IS_ERR(u.xcrs))
3377 return PTR_ERR(u.xcrs);
2d5b5a66 3378
d1ac91d8 3379 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3380 break;
3381 }
92a1f12d
JR		 3382 case KVM_SET_TSC_KHZ: {
3383 u32 user_tsc_khz;
3384
3385 r = -EINVAL;
92a1f12d
JR		 3386 user_tsc_khz = (u32)arg;
3387
3388 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3389 goto out;
3390
cc578287
ZA		 3391 if (user_tsc_khz == 0)
3392 user_tsc_khz = tsc_khz;
3393
3394 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3395
3396 r = 0;
3397 goto out;
3398 }
3399 case KVM_GET_TSC_KHZ: {
cc578287 3400 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3401 goto out;
3402 }
1c0b28c2
EM		 3403 case KVM_KVMCLOCK_CTRL: {
3404 r = kvm_set_guest_paused(vcpu);
3405 goto out;
3406 }
313a3dc7
CO		 3407 default:
3408 r = -EINVAL;
3409 }
3410out:
d1ac91d8 3411 kfree(u.buffer);
313a3dc7
CO		 3412 return r;
3413}
3414
5b1c1493
CO		 3415int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3416{
3417 return VM_FAULT_SIGBUS;
3418}
3419
1fe779f8
CO		 3420static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3421{
3422 int ret;
3423
3424 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3425 return -EINVAL;
1fe779f8
CO		 3426 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3427 return ret;
3428}
3429
b927a3ce
SY		 3430static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3431 u64 ident_addr)
3432{
3433 kvm->arch.ept_identity_map_addr = ident_addr;
3434 return 0;
3435}
3436
1fe779f8
CO		 3437static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3438 u32 kvm_nr_mmu_pages)
3439{
3440 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3441 return -EINVAL;
3442
79fac95e 3443 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3444
3445 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3446 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3447
79fac95e 3448 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3449 return 0;
3450}
3451
3452static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3453{
39de71ec 3454 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3455}
3456
1fe779f8
CO		 3457static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3458{
3459 int r;
3460
3461 r = 0;
3462 switch (chip->chip_id) {
3463 case KVM_IRQCHIP_PIC_MASTER:
3464 memcpy(&chip->chip.pic,
3465 &pic_irqchip(kvm)->pics[0],
3466 sizeof(struct kvm_pic_state));
3467 break;
3468 case KVM_IRQCHIP_PIC_SLAVE:
3469 memcpy(&chip->chip.pic,
3470 &pic_irqchip(kvm)->pics[1],
3471 sizeof(struct kvm_pic_state));
3472 break;
3473 case KVM_IRQCHIP_IOAPIC:
eba0226b 3474 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3475 break;
3476 default:
3477 r = -EINVAL;
3478 break;
3479 }
3480 return r;
3481}
3482
3483static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3484{
3485 int r;
3486
3487 r = 0;
3488 switch (chip->chip_id) {
3489 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3490 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3491 memcpy(&pic_irqchip(kvm)->pics[0],
3492 &chip->chip.pic,
3493 sizeof(struct kvm_pic_state));
f4f51050 3494 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3495 break;
3496 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3497 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3498 memcpy(&pic_irqchip(kvm)->pics[1],
3499 &chip->chip.pic,
3500 sizeof(struct kvm_pic_state));
f4f51050 3501 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3502 break;
3503 case KVM_IRQCHIP_IOAPIC:
eba0226b 3504 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3505 break;
3506 default:
3507 r = -EINVAL;
3508 break;
3509 }
3510 kvm_pic_update_irq(pic_irqchip(kvm));
3511 return r;
3512}
3513
e0f63cb9
SY		 3514static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3515{
3516 int r = 0;
3517
894a9c55 3518 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3519 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3520 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3521 return r;
3522}
3523
3524static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3525{
3526 int r = 0;
3527
894a9c55 3528 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3529 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3530 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3531 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3532 return r;
3533}
3534
3535static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3536{
3537 int r = 0;
3538
3539 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3540 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3541 sizeof(ps->channels));
3542 ps->flags = kvm->arch.vpit->pit_state.flags;
3543 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3544 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3545 return r;
3546}
3547
3548static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3549{
3550 int r = 0, start = 0;
3551 u32 prev_legacy, cur_legacy;
3552 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3553 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3554 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3555 if (!prev_legacy && cur_legacy)
3556 start = 1;
3557 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3558 sizeof(kvm->arch.vpit->pit_state.channels));
3559 kvm->arch.vpit->pit_state.flags = ps->flags;
3560 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3561 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3562 return r;
3563}
3564
52d939a0
MT		 3565static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3566 struct kvm_reinject_control *control)
3567{
3568 if (!kvm->arch.vpit)
3569 return -ENXIO;
894a9c55 3570 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3571 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3572 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3573 return 0;
3574}
3575
95d4c16c 3576/**
60c34612
TY		 3577 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3578 * @kvm: kvm instance
3579 * @log: slot id and address to which we copy the log
95d4c16c 3580 *
60c34612
TY		 3581 * We need to keep it in mind that VCPU threads can write to the bitmap
3582 * concurrently. So, to avoid losing data, we keep the following order for
3583 * each bit:
95d4c16c 3584 *
60c34612
TY		 3585 * 1. Take a snapshot of the bit and clear it if needed.
3586 * 2. Write protect the corresponding page.
3587 * 3. Flush TLB's if needed.
3588 * 4. Copy the snapshot to the userspace.
95d4c16c 3589 *
60c34612
TY		 3590 * Between 2 and 3, the guest may write to the page using the remaining TLB
3591 * entry. This is not a problem because the page will be reported dirty at
3592 * step 4 using the snapshot taken before and step 3 ensures that successive
3593 * writes will be logged for the next call.
5bb064dc 3594 */
60c34612 3595int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3596{
7850ac54 3597 int r;
5bb064dc 3598 struct kvm_memory_slot *memslot;
60c34612
TY		 3599 unsigned long n, i;
3600 unsigned long *dirty_bitmap;
3601 unsigned long *dirty_bitmap_buffer;
3602 bool is_dirty = false;
5bb064dc 3603
79fac95e 3604 mutex_lock(&kvm->slots_lock);
5bb064dc 3605
b050b015 3606 r = -EINVAL;
bbacc0c1 3607 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3608 goto out;
3609
28a37544 3610 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3611
3612 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3613 r = -ENOENT;
60c34612 3614 if (!dirty_bitmap)
b050b015
MT		 3615 goto out;
3616
87bf6e7d 3617 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3618
60c34612
TY		 3619 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3620 memset(dirty_bitmap_buffer, 0, n);
b050b015 3621
60c34612 3622 spin_lock(&kvm->mmu_lock);
b050b015 3623
60c34612
TY		 3624 for (i = 0; i < n / sizeof(long); i++) {
3625 unsigned long mask;
3626 gfn_t offset;
cdfca7b3 3627
60c34612
TY		 3628 if (!dirty_bitmap[i])
3629 continue;
b050b015 3630
60c34612 3631 is_dirty = true;
914ebccd 3632
60c34612
TY		 3633 mask = xchg(&dirty_bitmap[i], 0);
3634 dirty_bitmap_buffer[i] = mask;
edde99ce 3635
60c34612
TY		 3636 offset = i * BITS_PER_LONG;
3637 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3638 }
60c34612
TY		 3639
3640 spin_unlock(&kvm->mmu_lock);
3641
198c74f4
XG		 3642 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3643 lockdep_assert_held(&kvm->slots_lock);
3644
3645 /*
3646 * All the TLBs can be flushed out of mmu lock, see the comments in
3647 * kvm_mmu_slot_remove_write_access().
3648 */
3649 if (is_dirty)
3650 kvm_flush_remote_tlbs(kvm);
3651
60c34612
TY		 3652 r = -EFAULT;
3653 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3654 goto out;
b050b015 3655
5bb064dc
ZX		 3656 r = 0;
3657out:
79fac95e 3658 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3659 return r;
3660}
3661
aa2fbe6d
YZ		 3662int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3663 bool line_status)
23d43cf9
CD		 3664{
3665 if (!irqchip_in_kernel(kvm))
3666 return -ENXIO;
3667
3668 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3669 irq_event->irq, irq_event->level,
3670 line_status);
23d43cf9
CD		 3671 return 0;
3672}
3673
1fe779f8
CO		 3674long kvm_arch_vm_ioctl(struct file *filp,
3675 unsigned int ioctl, unsigned long arg)
3676{
3677 struct kvm *kvm = filp->private_data;
3678 void __user *argp = (void __user *)arg;
367e1319 3679 int r = -ENOTTY;
f0d66275
DH		 3680 /*
3681 * This union makes it completely explicit to gcc-3.x
3682 * that these two variables' stack usage should be
3683 * combined, not added together.
3684 */
3685 union {
3686 struct kvm_pit_state ps;
e9f42757 3687 struct kvm_pit_state2 ps2;
c5ff41ce 3688 struct kvm_pit_config pit_config;
f0d66275 3689 } u;
1fe779f8
CO		 3690
3691 switch (ioctl) {
3692 case KVM_SET_TSS_ADDR:
3693 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3694 break;
b927a3ce
SY		 3695 case KVM_SET_IDENTITY_MAP_ADDR: {
3696 u64 ident_addr;
3697
3698 r = -EFAULT;
3699 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3700 goto out;
3701 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3702 break;
3703 }
1fe779f8
CO		 3704 case KVM_SET_NR_MMU_PAGES:
3705 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3706 break;
3707 case KVM_GET_NR_MMU_PAGES:
3708 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3709 break;
3ddea128
MT		 3710 case KVM_CREATE_IRQCHIP: {
3711 struct kvm_pic *vpic;
3712
3713 mutex_lock(&kvm->lock);
3714 r = -EEXIST;
3715 if (kvm->arch.vpic)
3716 goto create_irqchip_unlock;
3e515705
AK		 3717 r = -EINVAL;
3718 if (atomic_read(&kvm->online_vcpus))
3719 goto create_irqchip_unlock;
1fe779f8 3720 r = -ENOMEM;
3ddea128
MT		 3721 vpic = kvm_create_pic(kvm);
3722 if (vpic) {
1fe779f8
CO		 3723 r = kvm_ioapic_init(kvm);
3724 if (r) {
175504cd 3725 mutex_lock(&kvm->slots_lock);
72bb2fcd 3726 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3727 &vpic->dev_master);
3728 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3729 &vpic->dev_slave);
3730 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3731 &vpic->dev_eclr);
175504cd 3732 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3733 kfree(vpic);
3734 goto create_irqchip_unlock;
1fe779f8
CO		 3735 }
3736 } else
3ddea128
MT		 3737 goto create_irqchip_unlock;
3738 smp_wmb();
3739 kvm->arch.vpic = vpic;
3740 smp_wmb();
399ec807
AK		 3741 r = kvm_setup_default_irq_routing(kvm);
3742 if (r) {
175504cd 3743 mutex_lock(&kvm->slots_lock);
3ddea128 3744 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3745 kvm_ioapic_destroy(kvm);
3746 kvm_destroy_pic(kvm);
3ddea128 3747 mutex_unlock(&kvm->irq_lock);
175504cd 3748 mutex_unlock(&kvm->slots_lock);
399ec807 3749 }
3ddea128
MT		 3750 create_irqchip_unlock:
3751 mutex_unlock(&kvm->lock);
1fe779f8 3752 break;
3ddea128 3753 }
7837699f 3754 case KVM_CREATE_PIT:
c5ff41ce
JK		 3755 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3756 goto create_pit;
3757 case KVM_CREATE_PIT2:
3758 r = -EFAULT;
3759 if (copy_from_user(&u.pit_config, argp,
3760 sizeof(struct kvm_pit_config)))
3761 goto out;
3762 create_pit:
79fac95e 3763 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3764 r = -EEXIST;
3765 if (kvm->arch.vpit)
3766 goto create_pit_unlock;
7837699f 3767 r = -ENOMEM;
c5ff41ce 3768 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3769 if (kvm->arch.vpit)
3770 r = 0;
269e05e4 3771 create_pit_unlock:
79fac95e 3772 mutex_unlock(&kvm->slots_lock);
7837699f 3773 break;
1fe779f8
CO		 3774 case KVM_GET_IRQCHIP: {
3775 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3776 struct kvm_irqchip *chip;
1fe779f8 3777
ff5c2c03
SL		 3778 chip = memdup_user(argp, sizeof(*chip));
3779 if (IS_ERR(chip)) {
3780 r = PTR_ERR(chip);
1fe779f8 3781 goto out;
ff5c2c03
SL		 3782 }
3783
1fe779f8
CO		 3784 r = -ENXIO;
3785 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3786 goto get_irqchip_out;
3787 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3788 if (r)
f0d66275 3789 goto get_irqchip_out;
1fe779f8 3790 r = -EFAULT;
f0d66275
DH		 3791 if (copy_to_user(argp, chip, sizeof *chip))
3792 goto get_irqchip_out;
1fe779f8 3793 r = 0;
f0d66275
DH		 3794 get_irqchip_out:
3795 kfree(chip);
1fe779f8
CO		 3796 break;
3797 }
3798 case KVM_SET_IRQCHIP: {
3799 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3800 struct kvm_irqchip *chip;
1fe779f8 3801
ff5c2c03
SL		 3802 chip = memdup_user(argp, sizeof(*chip));
3803 if (IS_ERR(chip)) {
3804 r = PTR_ERR(chip);
1fe779f8 3805 goto out;
ff5c2c03
SL		 3806 }
3807
1fe779f8
CO		 3808 r = -ENXIO;
3809 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3810 goto set_irqchip_out;
3811 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3812 if (r)
f0d66275 3813 goto set_irqchip_out;
1fe779f8 3814 r = 0;
f0d66275
DH		 3815 set_irqchip_out:
3816 kfree(chip);
1fe779f8
CO		 3817 break;
3818 }
e0f63cb9 3819 case KVM_GET_PIT: {
e0f63cb9 3820 r = -EFAULT;
f0d66275 3821 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3822 goto out;
3823 r = -ENXIO;
3824 if (!kvm->arch.vpit)
3825 goto out;
f0d66275 3826 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3827 if (r)
3828 goto out;
3829 r = -EFAULT;
f0d66275 3830 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3831 goto out;
3832 r = 0;
3833 break;
3834 }
3835 case KVM_SET_PIT: {
e0f63cb9 3836 r = -EFAULT;
f0d66275 3837 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3838 goto out;
3839 r = -ENXIO;
3840 if (!kvm->arch.vpit)
3841 goto out;
f0d66275 3842 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3843 break;
3844 }
e9f42757
BK		 3845 case KVM_GET_PIT2: {
3846 r = -ENXIO;
3847 if (!kvm->arch.vpit)
3848 goto out;
3849 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3850 if (r)
3851 goto out;
3852 r = -EFAULT;
3853 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3854 goto out;
3855 r = 0;
3856 break;
3857 }
3858 case KVM_SET_PIT2: {
3859 r = -EFAULT;
3860 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3861 goto out;
3862 r = -ENXIO;
3863 if (!kvm->arch.vpit)
3864 goto out;
3865 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3866 break;
3867 }
52d939a0
MT		 3868 case KVM_REINJECT_CONTROL: {
3869 struct kvm_reinject_control control;
3870 r = -EFAULT;
3871 if (copy_from_user(&control, argp, sizeof(control)))
3872 goto out;
3873 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3874 break;
3875 }
ffde22ac
ES		 3876 case KVM_XEN_HVM_CONFIG: {
3877 r = -EFAULT;
3878 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3879 sizeof(struct kvm_xen_hvm_config)))
3880 goto out;
3881 r = -EINVAL;
3882 if (kvm->arch.xen_hvm_config.flags)
3883 goto out;
3884 r = 0;
3885 break;
3886 }
afbcf7ab 3887 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3888 struct kvm_clock_data user_ns;
3889 u64 now_ns;
3890 s64 delta;
3891
3892 r = -EFAULT;
3893 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3894 goto out;
3895
3896 r = -EINVAL;
3897 if (user_ns.flags)
3898 goto out;
3899
3900 r = 0;
395c6b0a 3901 local_irq_disable();
759379dd 3902 now_ns = get_kernel_ns();
afbcf7ab 3903 delta = user_ns.clock - now_ns;
395c6b0a 3904 local_irq_enable();
afbcf7ab 3905 kvm->arch.kvmclock_offset = delta;
2e762ff7 3906 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3907 break;
3908 }
3909 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3910 struct kvm_clock_data user_ns;
3911 u64 now_ns;
3912
395c6b0a 3913 local_irq_disable();
759379dd 3914 now_ns = get_kernel_ns();
afbcf7ab 3915 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3916 local_irq_enable();
afbcf7ab 3917 user_ns.flags = 0;
97e69aa6 3918 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3919
3920 r = -EFAULT;
3921 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3922 goto out;
3923 r = 0;
3924 break;
3925 }
3926
1fe779f8
CO		 3927 default:
3928 ;
3929 }
3930out:
3931 return r;
3932}
3933
a16b043c 3934static void kvm_init_msr_list(void)
043405e1
CO		 3935{
3936 u32 dummy[2];
3937 unsigned i, j;
3938
e3267cbb
GC		 3939 /* skip the first msrs in the list. KVM-specific */
3940 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3941 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3942 continue;
93c4adc7
PB		 3943
3944 /*
3945 * Even MSRs that are valid in the host may not be exposed
3946 * to the guests in some cases. We could work around this
3947 * in VMX with the generic MSR save/load machinery, but it
3948 * is not really worthwhile since it will really only
3949 * happen with nested virtualization.
3950 */
3951 switch (msrs_to_save[i]) {
3952 case MSR_IA32_BNDCFGS:
3953 if (!kvm_x86_ops->mpx_supported())
3954 continue;
3955 break;
3956 default:
3957 break;
3958 }
3959
043405e1
CO		 3960 if (j < i)
3961 msrs_to_save[j] = msrs_to_save[i];
3962 j++;
3963 }
3964 num_msrs_to_save = j;
3965}
3966
bda9020e
MT		 3967static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3968 const void *v)
bbd9b64e 3969{
70252a10
AK		 3970 int handled = 0;
3971 int n;
3972
3973 do {
3974 n = min(len, 8);
3975 if (!(vcpu->arch.apic &&
3976 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3977 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3978 break;
3979 handled += n;
3980 addr += n;
3981 len -= n;
3982 v += n;
3983 } while (len);
bbd9b64e 3984
70252a10 3985 return handled;
bbd9b64e
CO		 3986}
3987
bda9020e 3988static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3989{
70252a10
AK		 3990 int handled = 0;
3991 int n;
3992
3993 do {
3994 n = min(len, 8);
3995 if (!(vcpu->arch.apic &&
3996 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3997 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3998 break;
3999 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4000 handled += n;
4001 addr += n;
4002 len -= n;
4003 v += n;
4004 } while (len);
bbd9b64e 4005
70252a10 4006 return handled;
bbd9b64e
CO		 4007}
4008
2dafc6c2
GN		 4009static void kvm_set_segment(struct kvm_vcpu *vcpu,
4010 struct kvm_segment *var, int seg)
4011{
4012 kvm_x86_ops->set_segment(vcpu, var, seg);
4013}
4014
4015void kvm_get_segment(struct kvm_vcpu *vcpu,
4016 struct kvm_segment *var, int seg)
4017{
4018 kvm_x86_ops->get_segment(vcpu, var, seg);
4019}
4020
e459e322 4021gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4022{
4023 gpa_t t_gpa;
ab9ae313 4024 struct x86_exception exception;
02f59dc9
JR		 4025
4026 BUG_ON(!mmu_is_nested(vcpu));
4027
4028 /* NPT walks are always user-walks */
4029 access |= PFERR_USER_MASK;
ab9ae313 4030 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4031
4032 return t_gpa;
4033}
4034
ab9ae313
AK		 4035gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4036 struct x86_exception *exception)
1871c602
GN		 4037{
4038 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4039 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4040}
4041
ab9ae313
AK		 4042 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4043 struct x86_exception *exception)
1871c602
GN		 4044{
4045 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4046 access |= PFERR_FETCH_MASK;
ab9ae313 4047 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4048}
4049
ab9ae313
AK		 4050gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4051 struct x86_exception *exception)
1871c602
GN		 4052{
4053 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4054 access |= PFERR_WRITE_MASK;
ab9ae313 4055 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4056}
4057
4058/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4059gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4060 struct x86_exception *exception)
1871c602 4061{
ab9ae313 4062 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4063}
4064
4065static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4066 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4067 struct x86_exception *exception)
bbd9b64e
CO		 4068{
4069 void *data = val;
10589a46 4070 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4071
4072 while (bytes) {
14dfe855 4073 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4074 exception);
bbd9b64e 4075 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4076 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4077 int ret;
4078
bcc55cba 4079 if (gpa == UNMAPPED_GVA)
ab9ae313 4080 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4081 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4082 if (ret < 0) {
c3cd7ffa 4083 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4084 goto out;
4085 }
bbd9b64e 4086
77c2002e
IE		 4087 bytes -= toread;
4088 data += toread;
4089 addr += toread;
bbd9b64e 4090 }
10589a46 4091out:
10589a46 4092 return r;
bbd9b64e 4093}
77c2002e 4094
1871c602 4095/* used for instruction fetching */
0f65dd70
AK		 4096static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4097 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4098 struct x86_exception *exception)
1871c602 4099{
0f65dd70 4100 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4101 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4102
1871c602 4103 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4104 access | PFERR_FETCH_MASK,
4105 exception);
1871c602
GN		 4106}
4107
064aea77 4108int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4109 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4110 struct x86_exception *exception)
1871c602 4111{
0f65dd70 4112 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4113 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4114
1871c602 4115 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4116 exception);
1871c602 4117}
064aea77 4118EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4119
0f65dd70
AK		 4120static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4121 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4122 struct x86_exception *exception)
1871c602 4123{
0f65dd70 4124 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4125 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4126}
4127
6a4d7550 4128int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4129 gva_t addr, void *val,
2dafc6c2 4130 unsigned int bytes,
bcc55cba 4131 struct x86_exception *exception)
77c2002e 4132{
0f65dd70 4133 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4134 void *data = val;
4135 int r = X86EMUL_CONTINUE;
4136
4137 while (bytes) {
14dfe855
JR		 4138 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4139 PFERR_WRITE_MASK,
ab9ae313 4140 exception);
77c2002e
IE		 4141 unsigned offset = addr & (PAGE_SIZE-1);
4142 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4143 int ret;
4144
bcc55cba 4145 if (gpa == UNMAPPED_GVA)
ab9ae313 4146 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4147 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4148 if (ret < 0) {
c3cd7ffa 4149 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4150 goto out;
4151 }
4152
4153 bytes -= towrite;
4154 data += towrite;
4155 addr += towrite;
4156 }
4157out:
4158 return r;
4159}
6a4d7550 4160EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4161
af7cc7d1
XG		 4162static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4163 gpa_t *gpa, struct x86_exception *exception,
4164 bool write)
4165{
97d64b78
AK		 4166 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4167 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4168
97d64b78 4169 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4170 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4171 vcpu->arch.access, access)) {
bebb106a
XG		 4172 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4173 (gva & (PAGE_SIZE - 1));
4f022648 4174 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4175 return 1;
4176 }
4177
af7cc7d1
XG		 4178 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4179
4180 if (*gpa == UNMAPPED_GVA)
4181 return -1;
4182
4183 /* For APIC access vmexit */
4184 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4185 return 1;
4186
4f022648
XG		 4187 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4188 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4189 return 1;
4f022648 4190 }
bebb106a 4191
af7cc7d1
XG		 4192 return 0;
4193}
4194
3200f405 4195int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4196 const void *val, int bytes)
bbd9b64e
CO		 4197{
4198 int ret;
4199
4200 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4201 if (ret < 0)
bbd9b64e 4202 return 0;
f57f2ef5 4203 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4204 return 1;
4205}
4206
77d197b2
XG		 4207struct read_write_emulator_ops {
4208 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4209 int bytes);
4210 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4211 void *val, int bytes);
4212 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4213 int bytes, void *val);
4214 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4215 void *val, int bytes);
4216 bool write;
4217};
4218
4219static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4220{
4221 if (vcpu->mmio_read_completed) {
77d197b2 4222 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4223 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4224 vcpu->mmio_read_completed = 0;
4225 return 1;
4226 }
4227
4228 return 0;
4229}
4230
4231static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4232 void *val, int bytes)
4233{
4234 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4235}
4236
4237static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4238 void *val, int bytes)
4239{
4240 return emulator_write_phys(vcpu, gpa, val, bytes);
4241}
4242
4243static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4244{
4245 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4246 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4247}
4248
4249static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4250 void *val, int bytes)
4251{
4252 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4253 return X86EMUL_IO_NEEDED;
4254}
4255
4256static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4257 void *val, int bytes)
4258{
f78146b0
AK		 4259 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4260
87da7e66 4261 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4262 return X86EMUL_CONTINUE;
4263}
4264
0fbe9b0b 4265static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4266 .read_write_prepare = read_prepare,
4267 .read_write_emulate = read_emulate,
4268 .read_write_mmio = vcpu_mmio_read,
4269 .read_write_exit_mmio = read_exit_mmio,
4270};
4271
0fbe9b0b 4272static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4273 .read_write_emulate = write_emulate,
4274 .read_write_mmio = write_mmio,
4275 .read_write_exit_mmio = write_exit_mmio,
4276 .write = true,
4277};
4278
22388a3c
XG		 4279static int emulator_read_write_onepage(unsigned long addr, void *val,
4280 unsigned int bytes,
4281 struct x86_exception *exception,
4282 struct kvm_vcpu *vcpu,
0fbe9b0b 4283 const struct read_write_emulator_ops *ops)
bbd9b64e 4284{
af7cc7d1
XG		 4285 gpa_t gpa;
4286 int handled, ret;
22388a3c 4287 bool write = ops->write;
f78146b0 4288 struct kvm_mmio_fragment *frag;
10589a46 4289
22388a3c 4290 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4291
af7cc7d1 4292 if (ret < 0)
bbd9b64e 4293 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4294
4295 /* For APIC access vmexit */
af7cc7d1 4296 if (ret)
bbd9b64e
CO		 4297 goto mmio;
4298
22388a3c 4299 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4300 return X86EMUL_CONTINUE;
4301
4302mmio:
4303 /*
4304 * Is this MMIO handled locally?
4305 */
22388a3c 4306 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4307 if (handled == bytes)
bbd9b64e 4308 return X86EMUL_CONTINUE;
bbd9b64e 4309
70252a10
AK		 4310 gpa += handled;
4311 bytes -= handled;
4312 val += handled;
4313
87da7e66
XG		 4314 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4315 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4316 frag->gpa = gpa;
4317 frag->data = val;
4318 frag->len = bytes;
f78146b0 4319 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4320}
4321
22388a3c
XG		 4322int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4323 void *val, unsigned int bytes,
4324 struct x86_exception *exception,
0fbe9b0b 4325 const struct read_write_emulator_ops *ops)
bbd9b64e 4326{
0f65dd70 4327 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4328 gpa_t gpa;
4329 int rc;
4330
4331 if (ops->read_write_prepare &&
4332 ops->read_write_prepare(vcpu, val, bytes))
4333 return X86EMUL_CONTINUE;
4334
4335 vcpu->mmio_nr_fragments = 0;
0f65dd70 4336
bbd9b64e
CO		 4337 /* Crossing a page boundary? */
4338 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4339 int now;
bbd9b64e
CO		 4340
4341 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4342 rc = emulator_read_write_onepage(addr, val, now, exception,
4343 vcpu, ops);
4344
bbd9b64e
CO		 4345 if (rc != X86EMUL_CONTINUE)
4346 return rc;
4347 addr += now;
4348 val += now;
4349 bytes -= now;
4350 }
22388a3c 4351
f78146b0
AK		 4352 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4353 vcpu, ops);
4354 if (rc != X86EMUL_CONTINUE)
4355 return rc;
4356
4357 if (!vcpu->mmio_nr_fragments)
4358 return rc;
4359
4360 gpa = vcpu->mmio_fragments[0].gpa;
4361
4362 vcpu->mmio_needed = 1;
4363 vcpu->mmio_cur_fragment = 0;
4364
87da7e66 4365 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4366 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4367 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4368 vcpu->run->mmio.phys_addr = gpa;
4369
4370 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4371}
4372
4373static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4374 unsigned long addr,
4375 void *val,
4376 unsigned int bytes,
4377 struct x86_exception *exception)
4378{
4379 return emulator_read_write(ctxt, addr, val, bytes,
4380 exception, &read_emultor);
4381}
4382
4383int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4384 unsigned long addr,
4385 const void *val,
4386 unsigned int bytes,
4387 struct x86_exception *exception)
4388{
4389 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4390 exception, &write_emultor);
bbd9b64e 4391}
bbd9b64e 4392
daea3e73
AK		 4393#define CMPXCHG_TYPE(t, ptr, old, new) \
4394 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4395
4396#ifdef CONFIG_X86_64
4397# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4398#else
4399# define CMPXCHG64(ptr, old, new) \
9749a6c0 4400 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4401#endif
4402
0f65dd70
AK		 4403static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4404 unsigned long addr,
bbd9b64e
CO		 4405 const void *old,
4406 const void *new,
4407 unsigned int bytes,
0f65dd70 4408 struct x86_exception *exception)
bbd9b64e 4409{
0f65dd70 4410 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4411 gpa_t gpa;
4412 struct page *page;
4413 char *kaddr;
4414 bool exchanged;
2bacc55c 4415
daea3e73
AK		 4416 /* guests cmpxchg8b have to be emulated atomically */
4417 if (bytes > 8 || (bytes & (bytes - 1)))
4418 goto emul_write;
10589a46 4419
daea3e73 4420 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4421
daea3e73
AK		 4422 if (gpa == UNMAPPED_GVA ||
4423 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4424 goto emul_write;
2bacc55c 4425
daea3e73
AK		 4426 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4427 goto emul_write;
72dc67a6 4428
daea3e73 4429 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4430 if (is_error_page(page))
c19b8bd6 4431 goto emul_write;
72dc67a6 4432
8fd75e12 4433 kaddr = kmap_atomic(page);
daea3e73
AK		 4434 kaddr += offset_in_page(gpa);
4435 switch (bytes) {
4436 case 1:
4437 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4438 break;
4439 case 2:
4440 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4441 break;
4442 case 4:
4443 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4444 break;
4445 case 8:
4446 exchanged = CMPXCHG64(kaddr, old, new);
4447 break;
4448 default:
4449 BUG();
2bacc55c 4450 }
8fd75e12 4451 kunmap_atomic(kaddr);
daea3e73
AK		 4452 kvm_release_page_dirty(page);
4453
4454 if (!exchanged)
4455 return X86EMUL_CMPXCHG_FAILED;
4456
d3714010 4457 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4458 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4459
4460 return X86EMUL_CONTINUE;
4a5f48f6 4461
3200f405 4462emul_write:
daea3e73 4463 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4464
0f65dd70 4465 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4466}
4467
cf8f70bf
GN		 4468static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4469{
4470 /* TODO: String I/O for in kernel device */
4471 int r;
4472
4473 if (vcpu->arch.pio.in)
4474 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4475 vcpu->arch.pio.size, pd);
4476 else
4477 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4478 vcpu->arch.pio.port, vcpu->arch.pio.size,
4479 pd);
4480 return r;
4481}
4482
6f6fbe98
XG		 4483static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4484 unsigned short port, void *val,
4485 unsigned int count, bool in)
cf8f70bf 4486{
cf8f70bf 4487 vcpu->arch.pio.port = port;
6f6fbe98 4488 vcpu->arch.pio.in = in;
7972995b 4489 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4490 vcpu->arch.pio.size = size;
4491
4492 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4493 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4494 return 1;
4495 }
4496
4497 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4498 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4499 vcpu->run->io.size = size;
4500 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4501 vcpu->run->io.count = count;
4502 vcpu->run->io.port = port;
4503
4504 return 0;
4505}
4506
6f6fbe98
XG		 4507static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4508 int size, unsigned short port, void *val,
4509 unsigned int count)
cf8f70bf 4510{
ca1d4a9e 4511 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4512 int ret;
ca1d4a9e 4513
6f6fbe98
XG		 4514 if (vcpu->arch.pio.count)
4515 goto data_avail;
cf8f70bf 4516
6f6fbe98
XG		 4517 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4518 if (ret) {
4519data_avail:
4520 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4521 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4522 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4523 return 1;
4524 }
4525
cf8f70bf
GN		 4526 return 0;
4527}
4528
6f6fbe98
XG		 4529static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4530 int size, unsigned short port,
4531 const void *val, unsigned int count)
4532{
4533 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4534
4535 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4536 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4537 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4538}
4539
bbd9b64e
CO		 4540static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4541{
4542 return kvm_x86_ops->get_segment_base(vcpu, seg);
4543}
4544
3cb16fe7 4545static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4546{
3cb16fe7 4547 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4548}
4549
f5f48ee1
SY		 4550int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4551{
4552 if (!need_emulate_wbinvd(vcpu))
4553 return X86EMUL_CONTINUE;
4554
4555 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4556 int cpu = get_cpu();
4557
4558 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4559 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4560 wbinvd_ipi, NULL, 1);
2eec7343 4561 put_cpu();
f5f48ee1 4562 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4563 } else
4564 wbinvd();
f5f48ee1
SY		 4565 return X86EMUL_CONTINUE;
4566}
4567EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4568
bcaf5cc5
AK		 4569static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4570{
4571 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4572}
4573
717746e3 4574int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4575{
717746e3 4576 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4577}
4578
717746e3 4579int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4580{
338dbc97 4581
717746e3 4582 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4583}
4584
52a46617 4585static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4586{
52a46617 4587 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4588}
4589
717746e3 4590static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4591{
717746e3 4592 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4593 unsigned long value;
4594
4595 switch (cr) {
4596 case 0:
4597 value = kvm_read_cr0(vcpu);
4598 break;
4599 case 2:
4600 value = vcpu->arch.cr2;
4601 break;
4602 case 3:
9f8fe504 4603 value = kvm_read_cr3(vcpu);
52a46617
GN		 4604 break;
4605 case 4:
4606 value = kvm_read_cr4(vcpu);
4607 break;
4608 case 8:
4609 value = kvm_get_cr8(vcpu);
4610 break;
4611 default:
a737f256 4612 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4613 return 0;
4614 }
4615
4616 return value;
4617}
4618
717746e3 4619static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4620{
717746e3 4621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4622 int res = 0;
4623
52a46617
GN		 4624 switch (cr) {
4625 case 0:
49a9b07e 4626 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4627 break;
4628 case 2:
4629 vcpu->arch.cr2 = val;
4630 break;
4631 case 3:
2390218b 4632 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4633 break;
4634 case 4:
a83b29c6 4635 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4636 break;
4637 case 8:
eea1cff9 4638 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4639 break;
4640 default:
a737f256 4641 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4642 res = -1;
52a46617 4643 }
0f12244f
GN		 4644
4645 return res;
52a46617
GN		 4646}
4647
4cee4798
KW		 4648static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4649{
4650 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4651}
4652
717746e3 4653static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4654{
717746e3 4655 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4656}
4657
4bff1e86 4658static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4659{
4bff1e86 4660 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4661}
4662
4bff1e86 4663static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4664{
4bff1e86 4665 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4666}
4667
1ac9d0cf
AK		 4668static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4669{
4670 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4671}
4672
4673static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4674{
4675 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4676}
4677
4bff1e86
AK		 4678static unsigned long emulator_get_cached_segment_base(
4679 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4680{
4bff1e86 4681 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4682}
4683
1aa36616
AK		 4684static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4685 struct desc_struct *desc, u32 *base3,
4686 int seg)
2dafc6c2
GN		 4687{
4688 struct kvm_segment var;
4689
4bff1e86 4690 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4691 *selector = var.selector;
2dafc6c2 4692
378a8b09
GN		 4693 if (var.unusable) {
4694 memset(desc, 0, sizeof(*desc));
2dafc6c2 4695 return false;
378a8b09 4696 }
2dafc6c2
GN		 4697
4698 if (var.g)
4699 var.limit >>= 12;
4700 set_desc_limit(desc, var.limit);
4701 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4702#ifdef CONFIG_X86_64
4703 if (base3)
4704 *base3 = var.base >> 32;
4705#endif
2dafc6c2
GN		 4706 desc->type = var.type;
4707 desc->s = var.s;
4708 desc->dpl = var.dpl;
4709 desc->p = var.present;
4710 desc->avl = var.avl;
4711 desc->l = var.l;
4712 desc->d = var.db;
4713 desc->g = var.g;
4714
4715 return true;
4716}
4717
1aa36616
AK		 4718static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4719 struct desc_struct *desc, u32 base3,
4720 int seg)
2dafc6c2 4721{
4bff1e86 4722 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4723 struct kvm_segment var;
4724
1aa36616 4725 var.selector = selector;
2dafc6c2 4726 var.base = get_desc_base(desc);
5601d05b
GN		 4727#ifdef CONFIG_X86_64
4728 var.base |= ((u64)base3) << 32;
4729#endif
2dafc6c2
GN		 4730 var.limit = get_desc_limit(desc);
4731 if (desc->g)
4732 var.limit = (var.limit << 12) | 0xfff;
4733 var.type = desc->type;
4734 var.present = desc->p;
4735 var.dpl = desc->dpl;
4736 var.db = desc->d;
4737 var.s = desc->s;
4738 var.l = desc->l;
4739 var.g = desc->g;
4740 var.avl = desc->avl;
4741 var.present = desc->p;
4742 var.unusable = !var.present;
4743 var.padding = 0;
4744
4745 kvm_set_segment(vcpu, &var, seg);
4746 return;
4747}
4748
717746e3
AK		 4749static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4750 u32 msr_index, u64 *pdata)
4751{
4752 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4753}
4754
4755static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4756 u32 msr_index, u64 data)
4757{
8fe8ab46
WA		 4758 struct msr_data msr;
4759
4760 msr.data = data;
4761 msr.index = msr_index;
4762 msr.host_initiated = false;
4763 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4764}
4765
222d21aa
AK		 4766static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4767 u32 pmc, u64 *pdata)
4768{
4769 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4770}
4771
6c3287f7
AK		 4772static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4773{
4774 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4775}
4776
5037f6f3
AK		 4777static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4778{
4779 preempt_disable();
5197b808 4780 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4781 /*
4782 * CR0.TS may reference the host fpu state, not the guest fpu state,
4783 * so it may be clear at this point.
4784 */
4785 clts();
4786}
4787
4788static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4789{
4790 preempt_enable();
4791}
4792
2953538e 4793static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4794 struct x86_instruction_info *info,
c4f035c6
AK		 4795 enum x86_intercept_stage stage)
4796{
2953538e 4797 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4798}
4799
0017f93a 4800static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4801 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4802{
0017f93a 4803 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4804}
4805
dd856efa
AK		 4806static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4807{
4808 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4809}
4810
4811static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4812{
4813 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4814}
4815
0225fb50 4816static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4817 .read_gpr = emulator_read_gpr,
4818 .write_gpr = emulator_write_gpr,
1871c602 4819 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4820 .write_std = kvm_write_guest_virt_system,
1871c602 4821 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4822 .read_emulated = emulator_read_emulated,
4823 .write_emulated = emulator_write_emulated,
4824 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4825 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4826 .pio_in_emulated = emulator_pio_in_emulated,
4827 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4828 .get_segment = emulator_get_segment,
4829 .set_segment = emulator_set_segment,
5951c442 4830 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4831 .get_gdt = emulator_get_gdt,
160ce1f1 4832 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4833 .set_gdt = emulator_set_gdt,
4834 .set_idt = emulator_set_idt,
52a46617
GN		 4835 .get_cr = emulator_get_cr,
4836 .set_cr = emulator_set_cr,
4cee4798 4837 .set_rflags = emulator_set_rflags,
9c537244 4838 .cpl = emulator_get_cpl,
35aa5375
GN		 4839 .get_dr = emulator_get_dr,
4840 .set_dr = emulator_set_dr,
717746e3
AK		 4841 .set_msr = emulator_set_msr,
4842 .get_msr = emulator_get_msr,
222d21aa 4843 .read_pmc = emulator_read_pmc,
6c3287f7 4844 .halt = emulator_halt,
bcaf5cc5 4845 .wbinvd = emulator_wbinvd,
d6aa1000 4846 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4847 .get_fpu = emulator_get_fpu,
4848 .put_fpu = emulator_put_fpu,
c4f035c6 4849 .intercept = emulator_intercept,
bdb42f5a 4850 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4851};
4852
95cb2295
GN		 4853static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4854{
4855 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4856 /*
4857 * an sti; sti; sequence only disable interrupts for the first
4858 * instruction. So, if the last instruction, be it emulated or
4859 * not, left the system with the INT_STI flag enabled, it
4860 * means that the last instruction is an sti. We should not
4861 * leave the flag on in this case. The same goes for mov ss
4862 */
4863 if (!(int_shadow & mask))
4864 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4865}
4866
54b8486f
GN		 4867static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4868{
4869 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4870 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4871 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4872 else if (ctxt->exception.error_code_valid)
4873 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4874 ctxt->exception.error_code);
54b8486f 4875 else
da9cb575 4876 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4877}
4878
dd856efa 4879static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4880{
1ce19dc1
BP		 4881 memset(&ctxt->opcode_len, 0,
4882 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4883
9dac77fa
AK		 4884 ctxt->fetch.start = 0;
4885 ctxt->fetch.end = 0;
4886 ctxt->io_read.pos = 0;
4887 ctxt->io_read.end = 0;
4888 ctxt->mem_read.pos = 0;
4889 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4890}
4891
8ec4722d
MG		 4892static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4893{
adf52235 4894 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4895 int cs_db, cs_l;
4896
8ec4722d
MG		 4897 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4898
adf52235
TY		 4899 ctxt->eflags = kvm_get_rflags(vcpu);
4900 ctxt->eip = kvm_rip_read(vcpu);
4901 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4902 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4903 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4904 cs_db ? X86EMUL_MODE_PROT32 :
4905 X86EMUL_MODE_PROT16;
4906 ctxt->guest_mode = is_guest_mode(vcpu);
4907
dd856efa 4908 init_decode_cache(ctxt);
7ae441ea 4909 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4910}
4911
71f9833b 4912int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4913{
9d74191a 4914 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4915 int ret;
4916
4917 init_emulate_ctxt(vcpu);
4918
9dac77fa
AK		 4919 ctxt->op_bytes = 2;
4920 ctxt->ad_bytes = 2;
4921 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4922 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4923
4924 if (ret != X86EMUL_CONTINUE)
4925 return EMULATE_FAIL;
4926
9dac77fa 4927 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4928 kvm_rip_write(vcpu, ctxt->eip);
4929 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4930
4931 if (irq == NMI_VECTOR)
7460fb4a 4932 vcpu->arch.nmi_pending = 0;
63995653
MG		 4933 else
4934 vcpu->arch.interrupt.pending = false;
4935
4936 return EMULATE_DONE;
4937}
4938EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4939
6d77dbfc
GN		 4940static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4941{
fc3a9157
JR		 4942 int r = EMULATE_DONE;
4943
6d77dbfc
GN		 4944 ++vcpu->stat.insn_emulation_fail;
4945 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4946 if (!is_guest_mode(vcpu)) {
4947 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4948 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4949 vcpu->run->internal.ndata = 0;
4950 r = EMULATE_FAIL;
4951 }
6d77dbfc 4952 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4953
4954 return r;
6d77dbfc
GN		 4955}
4956
93c05d3e 4957static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4958 bool write_fault_to_shadow_pgtable,
4959 int emulation_type)
a6f177ef 4960{
95b3cf69 4961 gpa_t gpa = cr2;
8e3d9d06 4962 pfn_t pfn;
a6f177ef 4963
991eebf9
GN		 4964 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4965 return false;
4966
95b3cf69
XG		 4967 if (!vcpu->arch.mmu.direct_map) {
4968 /*
4969 * Write permission should be allowed since only
4970 * write access need to be emulated.
4971 */
4972 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4973
95b3cf69
XG		 4974 /*
4975 * If the mapping is invalid in guest, let cpu retry
4976 * it to generate fault.
4977 */
4978 if (gpa == UNMAPPED_GVA)
4979 return true;
4980 }
a6f177ef 4981
8e3d9d06
XG		 4982 /*
4983 * Do not retry the unhandleable instruction if it faults on the
4984 * readonly host memory, otherwise it will goto a infinite loop:
4985 * retry instruction -> write #PF -> emulation fail -> retry
4986 * instruction -> ...
4987 */
4988 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4989
4990 /*
4991 * If the instruction failed on the error pfn, it can not be fixed,
4992 * report the error to userspace.
4993 */
4994 if (is_error_noslot_pfn(pfn))
4995 return false;
4996
4997 kvm_release_pfn_clean(pfn);
4998
4999 /* The instructions are well-emulated on direct mmu. */
5000 if (vcpu->arch.mmu.direct_map) {
5001 unsigned int indirect_shadow_pages;
5002
5003 spin_lock(&vcpu->kvm->mmu_lock);
5004 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5005 spin_unlock(&vcpu->kvm->mmu_lock);
5006
5007 if (indirect_shadow_pages)
5008 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5009
a6f177ef 5010 return true;
8e3d9d06 5011 }
a6f177ef 5012
95b3cf69
XG		 5013 /*
5014 * if emulation was due to access to shadowed page table
5015 * and it failed try to unshadow page and re-enter the
5016 * guest to let CPU execute the instruction.
5017 */
5018 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5019
5020 /*
5021 * If the access faults on its page table, it can not
5022 * be fixed by unprotecting shadow page and it should
5023 * be reported to userspace.
5024 */
5025 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5026}
5027
1cb3f3ae
XG		 5028static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5029 unsigned long cr2, int emulation_type)
5030{
5031 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5032 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5033
5034 last_retry_eip = vcpu->arch.last_retry_eip;
5035 last_retry_addr = vcpu->arch.last_retry_addr;
5036
5037 /*
5038 * If the emulation is caused by #PF and it is non-page_table
5039 * writing instruction, it means the VM-EXIT is caused by shadow
5040 * page protected, we can zap the shadow page and retry this
5041 * instruction directly.
5042 *
5043 * Note: if the guest uses a non-page-table modifying instruction
5044 * on the PDE that points to the instruction, then we will unmap
5045 * the instruction and go to an infinite loop. So, we cache the
5046 * last retried eip and the last fault address, if we meet the eip
5047 * and the address again, we can break out of the potential infinite
5048 * loop.
5049 */
5050 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5051
5052 if (!(emulation_type & EMULTYPE_RETRY))
5053 return false;
5054
5055 if (x86_page_table_writing_insn(ctxt))
5056 return false;
5057
5058 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5059 return false;
5060
5061 vcpu->arch.last_retry_eip = ctxt->eip;
5062 vcpu->arch.last_retry_addr = cr2;
5063
5064 if (!vcpu->arch.mmu.direct_map)
5065 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5066
22368028 5067 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5068
5069 return true;
5070}
5071
716d51ab
GN		 5072static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5073static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5074
4a1e10d5
PB		 5075static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5076 unsigned long *db)
5077{
5078 u32 dr6 = 0;
5079 int i;
5080 u32 enable, rwlen;
5081
5082 enable = dr7;
5083 rwlen = dr7 >> 16;
5084 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5085 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5086 dr6 |= (1 << i);
5087 return dr6;
5088}
5089
663f4c61
PB		 5090static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5091{
5092 struct kvm_run *kvm_run = vcpu->run;
5093
5094 /*
5095 * Use the "raw" value to see if TF was passed to the processor.
5096 * Note that the new value of the flags has not been saved yet.
5097 *
5098 * This is correct even for TF set by the guest, because "the
5099 * processor will not generate this exception after the instruction
5100 * that sets the TF flag".
5101 */
5102 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5103
5104 if (unlikely(rflags & X86_EFLAGS_TF)) {
5105 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5106 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5107 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5108 kvm_run->debug.arch.exception = DB_VECTOR;
5109 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5110 *r = EMULATE_USER_EXIT;
5111 } else {
5112 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5113 /*
5114 * "Certain debug exceptions may clear bit 0-3. The
5115 * remaining contents of the DR6 register are never
5116 * cleared by the processor".
5117 */
5118 vcpu->arch.dr6 &= ~15;
5119 vcpu->arch.dr6 |= DR6_BS;
5120 kvm_queue_exception(vcpu, DB_VECTOR);
5121 }
5122 }
5123}
5124
4a1e10d5
PB		 5125static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5126{
5127 struct kvm_run *kvm_run = vcpu->run;
5128 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5129 u32 dr6 = 0;
5130
5131 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5132 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5133 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5134 vcpu->arch.guest_debug_dr7,
5135 vcpu->arch.eff_db);
5136
5137 if (dr6 != 0) {
5138 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5139 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5140 get_segment_base(vcpu, VCPU_SREG_CS);
5141
5142 kvm_run->debug.arch.exception = DB_VECTOR;
5143 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5144 *r = EMULATE_USER_EXIT;
5145 return true;
5146 }
5147 }
5148
5149 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5150 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5151 vcpu->arch.dr7,
5152 vcpu->arch.db);
5153
5154 if (dr6 != 0) {
5155 vcpu->arch.dr6 &= ~15;
5156 vcpu->arch.dr6 |= dr6;
5157 kvm_queue_exception(vcpu, DB_VECTOR);
5158 *r = EMULATE_DONE;
5159 return true;
5160 }
5161 }
5162
5163 return false;
5164}
5165
51d8b661
AP		 5166int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5167 unsigned long cr2,
dc25e89e
AP		 5168 int emulation_type,
5169 void *insn,
5170 int insn_len)
bbd9b64e 5171{
95cb2295 5172 int r;
9d74191a 5173 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5174 bool writeback = true;
93c05d3e 5175 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5176
93c05d3e
XG		 5177 /*
5178 * Clear write_fault_to_shadow_pgtable here to ensure it is
5179 * never reused.
5180 */
5181 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5182 kvm_clear_exception_queue(vcpu);
8d7d8102 5183
571008da 5184 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5185 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5186
5187 /*
5188 * We will reenter on the same instruction since
5189 * we do not set complete_userspace_io. This does not
5190 * handle watchpoints yet, those would be handled in
5191 * the emulate_ops.
5192 */
5193 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5194 return r;
5195
9d74191a
TY		 5196 ctxt->interruptibility = 0;
5197 ctxt->have_exception = false;
5198 ctxt->perm_ok = false;
bbd9b64e 5199
b51e974f 5200 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5201
9d74191a 5202 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5203
e46479f8 5204 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5205 ++vcpu->stat.insn_emulation;
1d2887e2 5206 if (r != EMULATION_OK) {
4005996e
AK		 5207 if (emulation_type & EMULTYPE_TRAP_UD)
5208 return EMULATE_FAIL;
991eebf9
GN		 5209 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5210 emulation_type))
bbd9b64e 5211 return EMULATE_DONE;
6d77dbfc
GN		 5212 if (emulation_type & EMULTYPE_SKIP)
5213 return EMULATE_FAIL;
5214 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5215 }
5216 }
5217
ba8afb6b 5218 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5219 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5220 return EMULATE_DONE;
5221 }
5222
1cb3f3ae
XG		 5223 if (retry_instruction(ctxt, cr2, emulation_type))
5224 return EMULATE_DONE;
5225
7ae441ea 5226 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5227 changes registers values during IO operation */
7ae441ea
GN		 5228 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5229 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5230 emulator_invalidate_register_cache(ctxt);
7ae441ea 5231 }
4d2179e1 5232
5cd21917 5233restart:
9d74191a 5234 r = x86_emulate_insn(ctxt);
bbd9b64e 5235
775fde86
JR		 5236 if (r == EMULATION_INTERCEPTED)
5237 return EMULATE_DONE;
5238
d2ddd1c4 5239 if (r == EMULATION_FAILED) {
991eebf9
GN		 5240 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5241 emulation_type))
c3cd7ffa
GN		 5242 return EMULATE_DONE;
5243
6d77dbfc 5244 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5245 }
5246
9d74191a 5247 if (ctxt->have_exception) {
54b8486f 5248 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5249 r = EMULATE_DONE;
5250 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5251 if (!vcpu->arch.pio.in) {
5252 /* FIXME: return into emulator if single-stepping. */
3457e419 5253 vcpu->arch.pio.count = 0;
0912c977 5254 } else {
7ae441ea 5255 writeback = false;
716d51ab
GN		 5256 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5257 }
ac0a48c3 5258 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5259 } else if (vcpu->mmio_needed) {
5260 if (!vcpu->mmio_is_write)
5261 writeback = false;
ac0a48c3 5262 r = EMULATE_USER_EXIT;
716d51ab 5263 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5264 } else if (r == EMULATION_RESTART)
5cd21917 5265 goto restart;
d2ddd1c4
GN		 5266 else
5267 r = EMULATE_DONE;
f850e2e6 5268
7ae441ea 5269 if (writeback) {
9d74191a 5270 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5271 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5272 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5273 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5274 if (r == EMULATE_DONE)
5275 kvm_vcpu_check_singlestep(vcpu, &r);
5276 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5277 } else
5278 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5279
5280 return r;
de7d789a 5281}
51d8b661 5282EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5283
cf8f70bf 5284int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5285{
cf8f70bf 5286 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5287 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5288 size, port, &val, 1);
cf8f70bf 5289 /* do not return to emulator after return from userspace */
7972995b 5290 vcpu->arch.pio.count = 0;
de7d789a
CO		 5291 return ret;
5292}
cf8f70bf 5293EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5294
8cfdc000
ZA		 5295static void tsc_bad(void *info)
5296{
0a3aee0d 5297 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5298}
5299
5300static void tsc_khz_changed(void *data)
c8076604 5301{
8cfdc000
ZA		 5302 struct cpufreq_freqs *freq = data;
5303 unsigned long khz = 0;
5304
5305 if (data)
5306 khz = freq->new;
5307 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5308 khz = cpufreq_quick_get(raw_smp_processor_id());
5309 if (!khz)
5310 khz = tsc_khz;
0a3aee0d 5311 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5312}
5313
c8076604
GH		 5314static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5315 void *data)
5316{
5317 struct cpufreq_freqs *freq = data;
5318 struct kvm *kvm;
5319 struct kvm_vcpu *vcpu;
5320 int i, send_ipi = 0;
5321
8cfdc000
ZA		 5322 /*
5323 * We allow guests to temporarily run on slowing clocks,
5324 * provided we notify them after, or to run on accelerating
5325 * clocks, provided we notify them before. Thus time never
5326 * goes backwards.
5327 *
5328 * However, we have a problem. We can't atomically update
5329 * the frequency of a given CPU from this function; it is
5330 * merely a notifier, which can be called from any CPU.
5331 * Changing the TSC frequency at arbitrary points in time
5332 * requires a recomputation of local variables related to
5333 * the TSC for each VCPU. We must flag these local variables
5334 * to be updated and be sure the update takes place with the
5335 * new frequency before any guests proceed.
5336 *
5337 * Unfortunately, the combination of hotplug CPU and frequency
5338 * change creates an intractable locking scenario; the order
5339 * of when these callouts happen is undefined with respect to
5340 * CPU hotplug, and they can race with each other. As such,
5341 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5342 * undefined; you can actually have a CPU frequency change take
5343 * place in between the computation of X and the setting of the
5344 * variable. To protect against this problem, all updates of
5345 * the per_cpu tsc_khz variable are done in an interrupt
5346 * protected IPI, and all callers wishing to update the value
5347 * must wait for a synchronous IPI to complete (which is trivial
5348 * if the caller is on the CPU already). This establishes the
5349 * necessary total order on variable updates.
5350 *
5351 * Note that because a guest time update may take place
5352 * anytime after the setting of the VCPU's request bit, the
5353 * correct TSC value must be set before the request. However,
5354 * to ensure the update actually makes it to any guest which
5355 * starts running in hardware virtualization between the set
5356 * and the acquisition of the spinlock, we must also ping the
5357 * CPU after setting the request bit.
5358 *
5359 */
5360
c8076604
GH		 5361 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5362 return 0;
5363 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5364 return 0;
8cfdc000
ZA		 5365
5366 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5367
2f303b74 5368 spin_lock(&kvm_lock);
c8076604 5369 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5370 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5371 if (vcpu->cpu != freq->cpu)
5372 continue;
c285545f 5373 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5374 if (vcpu->cpu != smp_processor_id())
8cfdc000 5375 send_ipi = 1;
c8076604
GH		 5376 }
5377 }
2f303b74 5378 spin_unlock(&kvm_lock);
c8076604
GH		 5379
5380 if (freq->old < freq->new && send_ipi) {
5381 /*
5382 * We upscale the frequency. Must make the guest
5383 * doesn't see old kvmclock values while running with
5384 * the new frequency, otherwise we risk the guest sees
5385 * time go backwards.
5386 *
5387 * In case we update the frequency for another cpu
5388 * (which might be in guest context) send an interrupt
5389 * to kick the cpu out of guest context. Next time
5390 * guest context is entered kvmclock will be updated,
5391 * so the guest will not see stale values.
5392 */
8cfdc000 5393 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5394 }
5395 return 0;
5396}
5397
5398static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5399 .notifier_call = kvmclock_cpufreq_notifier
5400};
5401
5402static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5403 unsigned long action, void *hcpu)
5404{
5405 unsigned int cpu = (unsigned long)hcpu;
5406
5407 switch (action) {
5408 case CPU_ONLINE:
5409 case CPU_DOWN_FAILED:
5410 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5411 break;
5412 case CPU_DOWN_PREPARE:
5413 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5414 break;
5415 }
5416 return NOTIFY_OK;
5417}
5418
5419static struct notifier_block kvmclock_cpu_notifier_block = {
5420 .notifier_call = kvmclock_cpu_notifier,
5421 .priority = -INT_MAX
c8076604
GH		 5422};
5423
b820cc0c
ZA		 5424static void kvm_timer_init(void)
5425{
5426 int cpu;
5427
c285545f 5428 max_tsc_khz = tsc_khz;
460dd42e
SB		 5429
5430 cpu_notifier_register_begin();
b820cc0c 5431 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5432#ifdef CONFIG_CPU_FREQ
5433 struct cpufreq_policy policy;
5434 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5435 cpu = get_cpu();
5436 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5437 if (policy.cpuinfo.max_freq)
5438 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5439 put_cpu();
c285545f 5440#endif
b820cc0c
ZA		 5441 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5442 CPUFREQ_TRANSITION_NOTIFIER);
5443 }
c285545f 5444 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5445 for_each_online_cpu(cpu)
5446 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5447
5448 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5449 cpu_notifier_register_done();
5450
b820cc0c
ZA		 5451}
5452
ff9d07a0
ZY		 5453static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5454
f5132b01 5455int kvm_is_in_guest(void)
ff9d07a0 5456{
086c9855 5457 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5458}
5459
5460static int kvm_is_user_mode(void)
5461{
5462 int user_mode = 3;
dcf46b94 5463
086c9855
AS		 5464 if (__this_cpu_read(current_vcpu))
5465 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5466
ff9d07a0
ZY		 5467 return user_mode != 0;
5468}
5469
5470static unsigned long kvm_get_guest_ip(void)
5471{
5472 unsigned long ip = 0;
dcf46b94 5473
086c9855
AS		 5474 if (__this_cpu_read(current_vcpu))
5475 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5476
ff9d07a0
ZY		 5477 return ip;
5478}
5479
5480static struct perf_guest_info_callbacks kvm_guest_cbs = {
5481 .is_in_guest = kvm_is_in_guest,
5482 .is_user_mode = kvm_is_user_mode,
5483 .get_guest_ip = kvm_get_guest_ip,
5484};
5485
5486void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5487{
086c9855 5488 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5489}
5490EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5491
5492void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5493{
086c9855 5494 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5495}
5496EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5497
ce88decf
XG		 5498static void kvm_set_mmio_spte_mask(void)
5499{
5500 u64 mask;
5501 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5502
5503 /*
5504 * Set the reserved bits and the present bit of an paging-structure
5505 * entry to generate page fault with PFER.RSV = 1.
5506 */
885032b9
XG		 5507 /* Mask the reserved physical address bits. */
5508 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5509
5510 /* Bit 62 is always reserved for 32bit host. */
5511 mask |= 0x3ull << 62;
5512
5513 /* Set the present bit. */
ce88decf
XG		 5514 mask |= 1ull;
5515
5516#ifdef CONFIG_X86_64
5517 /*
5518 * If reserved bit is not supported, clear the present bit to disable
5519 * mmio page fault.
5520 */
5521 if (maxphyaddr == 52)
5522 mask &= ~1ull;
5523#endif
5524
5525 kvm_mmu_set_mmio_spte_mask(mask);
5526}
5527
16e8d74d
MT		 5528#ifdef CONFIG_X86_64
5529static void pvclock_gtod_update_fn(struct work_struct *work)
5530{
d828199e
MT		 5531 struct kvm *kvm;
5532
5533 struct kvm_vcpu *vcpu;
5534 int i;
5535
2f303b74 5536 spin_lock(&kvm_lock);
d828199e
MT		 5537 list_for_each_entry(kvm, &vm_list, vm_list)
5538 kvm_for_each_vcpu(i, vcpu, kvm)
5539 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5540 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5541 spin_unlock(&kvm_lock);
16e8d74d
MT		 5542}
5543
5544static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5545
5546/*
5547 * Notification about pvclock gtod data update.
5548 */
5549static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5550 void *priv)
5551{
5552 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5553 struct timekeeper *tk = priv;
5554
5555 update_pvclock_gtod(tk);
5556
5557 /* disable master clock if host does not trust, or does not
5558 * use, TSC clocksource
5559 */
5560 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5561 atomic_read(&kvm_guest_has_master_clock) != 0)
5562 queue_work(system_long_wq, &pvclock_gtod_work);
5563
5564 return 0;
5565}
5566
5567static struct notifier_block pvclock_gtod_notifier = {
5568 .notifier_call = pvclock_gtod_notify,
5569};
5570#endif
5571
f8c16bba 5572int kvm_arch_init(void *opaque)
043405e1 5573{
b820cc0c 5574 int r;
6b61edf7 5575 struct kvm_x86_ops *ops = opaque;
f8c16bba 5576
f8c16bba
ZX		 5577 if (kvm_x86_ops) {
5578 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5579 r = -EEXIST;
5580 goto out;
f8c16bba
ZX		 5581 }
5582
5583 if (!ops->cpu_has_kvm_support()) {
5584 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5585 r = -EOPNOTSUPP;
5586 goto out;
f8c16bba
ZX		 5587 }
5588 if (ops->disabled_by_bios()) {
5589 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5590 r = -EOPNOTSUPP;
5591 goto out;
f8c16bba
ZX		 5592 }
5593
013f6a5d
MT		 5594 r = -ENOMEM;
5595 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5596 if (!shared_msrs) {
5597 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5598 goto out;
5599 }
5600
97db56ce
AK		 5601 r = kvm_mmu_module_init();
5602 if (r)
013f6a5d 5603 goto out_free_percpu;
97db56ce 5604
ce88decf 5605 kvm_set_mmio_spte_mask();
97db56ce 5606
f8c16bba 5607 kvm_x86_ops = ops;
920c8377
PB		 5608 kvm_init_msr_list();
5609
7b52345e 5610 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5611 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5612
b820cc0c 5613 kvm_timer_init();
c8076604 5614
ff9d07a0
ZY		 5615 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5616
2acf923e
DC		 5617 if (cpu_has_xsave)
5618 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5619
c5cc421b 5620 kvm_lapic_init();
16e8d74d
MT		 5621#ifdef CONFIG_X86_64
5622 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5623#endif
5624
f8c16bba 5625 return 0;
56c6d28a 5626
013f6a5d
MT		 5627out_free_percpu:
5628 free_percpu(shared_msrs);
56c6d28a 5629out:
56c6d28a 5630 return r;
043405e1 5631}
8776e519 5632
f8c16bba
ZX		 5633void kvm_arch_exit(void)
5634{
ff9d07a0
ZY		 5635 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5636
888d256e
JK		 5637 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5638 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5639 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5640 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5641#ifdef CONFIG_X86_64
5642 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5643#endif
f8c16bba 5644 kvm_x86_ops = NULL;
56c6d28a 5645 kvm_mmu_module_exit();
013f6a5d 5646 free_percpu(shared_msrs);
56c6d28a 5647}
f8c16bba 5648
8776e519
HB		 5649int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5650{
5651 ++vcpu->stat.halt_exits;
5652 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5653 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5654 return 1;
5655 } else {
5656 vcpu->run->exit_reason = KVM_EXIT_HLT;
5657 return 0;
5658 }
5659}
5660EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5661
55cd8e5a
GN		 5662int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5663{
5664 u64 param, ingpa, outgpa, ret;
5665 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5666 bool fast, longmode;
5667 int cs_db, cs_l;
5668
5669 /*
5670 * hypercall generates UD from non zero cpl and real mode
5671 * per HYPER-V spec
5672 */
3eeb3288 5673 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5674 kvm_queue_exception(vcpu, UD_VECTOR);
5675 return 0;
5676 }
5677
5678 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5679 longmode = is_long_mode(vcpu) && cs_l == 1;
5680
5681 if (!longmode) {
ccd46936
GN		 5682 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5683 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5684 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5685 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5686 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5687 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5688 }
5689#ifdef CONFIG_X86_64
5690 else {
5691 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5692 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5693 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5694 }
5695#endif
5696
5697 code = param & 0xffff;
5698 fast = (param >> 16) & 0x1;
5699 rep_cnt = (param >> 32) & 0xfff;
5700 rep_idx = (param >> 48) & 0xfff;
5701
5702 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5703
c25bc163
GN		 5704 switch (code) {
5705 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5706 kvm_vcpu_on_spin(vcpu);
5707 break;
5708 default:
5709 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5710 break;
5711 }
55cd8e5a
GN		 5712
5713 ret = res | (((u64)rep_done & 0xfff) << 32);
5714 if (longmode) {
5715 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5716 } else {
5717 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5718 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5719 }
5720
5721 return 1;
5722}
5723
6aef266c
SV		 5724/*
5725 * kvm_pv_kick_cpu_op: Kick a vcpu.
5726 *
5727 * @apicid - apicid of vcpu to be kicked.
5728 */
5729static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5730{
24d2166b 5731 struct kvm_lapic_irq lapic_irq;
6aef266c 5732
24d2166b
R		 5733 lapic_irq.shorthand = 0;
5734 lapic_irq.dest_mode = 0;
5735 lapic_irq.dest_id = apicid;
6aef266c 5736
24d2166b
R		 5737 lapic_irq.delivery_mode = APIC_DM_REMRD;
5738 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5739}
5740
8776e519
HB		 5741int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5742{
5743 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5744 int r = 1;
8776e519 5745
55cd8e5a
GN		 5746 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5747 return kvm_hv_hypercall(vcpu);
5748
5fdbf976
MT		 5749 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5750 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5751 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5752 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5753 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5754
229456fc 5755 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5756
8776e519
HB		 5757 if (!is_long_mode(vcpu)) {
5758 nr &= 0xFFFFFFFF;
5759 a0 &= 0xFFFFFFFF;
5760 a1 &= 0xFFFFFFFF;
5761 a2 &= 0xFFFFFFFF;
5762 a3 &= 0xFFFFFFFF;
5763 }
5764
07708c4a
JK		 5765 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5766 ret = -KVM_EPERM;
5767 goto out;
5768 }
5769
8776e519 5770 switch (nr) {
b93463aa
AK		 5771 case KVM_HC_VAPIC_POLL_IRQ:
5772 ret = 0;
5773 break;
6aef266c
SV		 5774 case KVM_HC_KICK_CPU:
5775 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5776 ret = 0;
5777 break;
8776e519
HB		 5778 default:
5779 ret = -KVM_ENOSYS;
5780 break;
5781 }
07708c4a 5782out:
5fdbf976 5783 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5784 ++vcpu->stat.hypercalls;
2f333bcb 5785 return r;
8776e519
HB		 5786}
5787EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5788
b6785def 5789static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5790{
d6aa1000 5791 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5792 char instruction[3];
5fdbf976 5793 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5794
8776e519 5795 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5796
9d74191a 5797 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5798}
5799
b6c7a5dc
HB		 5800/*
5801 * Check if userspace requested an interrupt window, and that the
5802 * interrupt window is open.
5803 *
5804 * No need to exit to userspace if we already have an interrupt queued.
5805 */
851ba692 5806static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5807{
8061823a 5808 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5809 vcpu->run->request_interrupt_window &&
5df56646 5810 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5811}
5812
851ba692 5813static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5814{
851ba692
AK		 5815 struct kvm_run *kvm_run = vcpu->run;
5816
91586a3b 5817 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5818 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5819 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5820 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5821 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5822 else
b6c7a5dc 5823 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5824 kvm_arch_interrupt_allowed(vcpu) &&
5825 !kvm_cpu_has_interrupt(vcpu) &&
5826 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5827}
5828
95ba8273
GN		 5829static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5830{
5831 int max_irr, tpr;
5832
5833 if (!kvm_x86_ops->update_cr8_intercept)
5834 return;
5835
88c808fd
AK		 5836 if (!vcpu->arch.apic)
5837 return;
5838
8db3baa2
GN		 5839 if (!vcpu->arch.apic->vapic_addr)
5840 max_irr = kvm_lapic_find_highest_irr(vcpu);
5841 else
5842 max_irr = -1;
95ba8273
GN		 5843
5844 if (max_irr != -1)
5845 max_irr >>= 4;
5846
5847 tpr = kvm_lapic_get_cr8(vcpu);
5848
5849 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5850}
5851
b6b8a145 5852static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5853{
b6b8a145
JK		 5854 int r;
5855
95ba8273 5856 /* try to reinject previous events if any */
b59bb7bd 5857 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5858 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5859 vcpu->arch.exception.has_error_code,
5860 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5861 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5862 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5863 vcpu->arch.exception.error_code,
5864 vcpu->arch.exception.reinject);
b6b8a145 5865 return 0;
b59bb7bd
GN		 5866 }
5867
95ba8273
GN		 5868 if (vcpu->arch.nmi_injected) {
5869 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5870 return 0;
95ba8273
GN		 5871 }
5872
5873 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5874 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5875 return 0;
5876 }
5877
5878 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5879 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5880 if (r != 0)
5881 return r;
95ba8273
GN		 5882 }
5883
5884 /* try to inject new event if pending */
5885 if (vcpu->arch.nmi_pending) {
5886 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5887 --vcpu->arch.nmi_pending;
95ba8273
GN		 5888 vcpu->arch.nmi_injected = true;
5889 kvm_x86_ops->set_nmi(vcpu);
5890 }
c7c9c56c 5891 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5892 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5893 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5894 false);
5895 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5896 }
5897 }
b6b8a145 5898 return 0;
95ba8273
GN		 5899}
5900
7460fb4a
AK		 5901static void process_nmi(struct kvm_vcpu *vcpu)
5902{
5903 unsigned limit = 2;
5904
5905 /*
5906 * x86 is limited to one NMI running, and one NMI pending after it.
5907 * If an NMI is already in progress, limit further NMIs to just one.
5908 * Otherwise, allow two (and we'll inject the first one immediately).
5909 */
5910 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5911 limit = 1;
5912
5913 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5914 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5915 kvm_make_request(KVM_REQ_EVENT, vcpu);
5916}
5917
3d81bc7e 5918static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5919{
5920 u64 eoi_exit_bitmap[4];
cf9e65b7 5921 u32 tmr[8];
c7c9c56c 5922
3d81bc7e
YZ		 5923 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5924 return;
c7c9c56c
YZ		 5925
5926 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5927 memset(tmr, 0, 32);
c7c9c56c 5928
cf9e65b7 5929 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5930 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5931 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5932}
5933
9357d939
TY		 5934/*
5935 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5936 * exiting to the userspace. Otherwise, the value will be returned to the
5937 * userspace.
5938 */
851ba692 5939static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5940{
5941 int r;
6a8b1d13 5942 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5943 vcpu->run->request_interrupt_window;
730dca42 5944 bool req_immediate_exit = false;
b6c7a5dc 5945
3e007509 5946 if (vcpu->requests) {
a8eeb04a 5947 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5948 kvm_mmu_unload(vcpu);
a8eeb04a 5949 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5950 __kvm_migrate_timers(vcpu);
d828199e
MT		 5951 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5952 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5953 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5954 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5955 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5956 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5957 if (unlikely(r))
5958 goto out;
5959 }
a8eeb04a 5960 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5961 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5962 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5963 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5964 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5965 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5966 r = 0;
5967 goto out;
5968 }
a8eeb04a 5969 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5970 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5971 r = 0;
5972 goto out;
5973 }
a8eeb04a 5974 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5975 vcpu->fpu_active = 0;
5976 kvm_x86_ops->fpu_deactivate(vcpu);
5977 }
af585b92
GN		 5978 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5979 /* Page is swapped out. Do synthetic halt */
5980 vcpu->arch.apf.halted = true;
5981 r = 1;
5982 goto out;
5983 }
c9aaa895
GC		 5984 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5985 record_steal_time(vcpu);
7460fb4a
AK		 5986 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5987 process_nmi(vcpu);
f5132b01
GN		 5988 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5989 kvm_handle_pmu_event(vcpu);
5990 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5991 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5992 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5993 vcpu_scan_ioapic(vcpu);
2f52d58c 5994 }
b93463aa 5995
b463a6f7 5996 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5997 kvm_apic_accept_events(vcpu);
5998 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5999 r = 1;
6000 goto out;
6001 }
6002
b6b8a145
JK		 6003 if (inject_pending_event(vcpu, req_int_win) != 0)
6004 req_immediate_exit = true;
b463a6f7 6005 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6006 else if (vcpu->arch.nmi_pending)
c9a7953f 6007 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6008 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6009 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6010
6011 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6012 /*
6013 * Update architecture specific hints for APIC
6014 * virtual interrupt delivery.
6015 */
6016 if (kvm_x86_ops->hwapic_irr_update)
6017 kvm_x86_ops->hwapic_irr_update(vcpu,
6018 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6019 update_cr8_intercept(vcpu);
6020 kvm_lapic_sync_to_vapic(vcpu);
6021 }
6022 }
6023
d8368af8
AK		 6024 r = kvm_mmu_reload(vcpu);
6025 if (unlikely(r)) {
d905c069 6026 goto cancel_injection;
d8368af8
AK		 6027 }
6028
b6c7a5dc
HB		 6029 preempt_disable();
6030
6031 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6032 if (vcpu->fpu_active)
6033 kvm_load_guest_fpu(vcpu);
2acf923e 6034 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6035
6b7e2d09
XG		 6036 vcpu->mode = IN_GUEST_MODE;
6037
01b71917
MT		 6038 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6039
6b7e2d09
XG		 6040 /* We should set ->mode before check ->requests,
6041 * see the comment in make_all_cpus_request.
6042 */
01b71917 6043 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6044
d94e1dc9 6045 local_irq_disable();
32f88400 6046
6b7e2d09 6047 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6048 || need_resched() || signal_pending(current)) {
6b7e2d09 6049 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6050 smp_wmb();
6c142801
AK		 6051 local_irq_enable();
6052 preempt_enable();
01b71917 6053 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6054 r = 1;
d905c069 6055 goto cancel_injection;
6c142801
AK		 6056 }
6057
d6185f20
NHE		 6058 if (req_immediate_exit)
6059 smp_send_reschedule(vcpu->cpu);
6060
b6c7a5dc
HB		 6061 kvm_guest_enter();
6062
42dbaa5a 6063 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6064 set_debugreg(0, 7);
6065 set_debugreg(vcpu->arch.eff_db[0], 0);
6066 set_debugreg(vcpu->arch.eff_db[1], 1);
6067 set_debugreg(vcpu->arch.eff_db[2], 2);
6068 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6069 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6070 }
b6c7a5dc 6071
229456fc 6072 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6073 kvm_x86_ops->run(vcpu);
b6c7a5dc 6074
c77fb5fe
PB		 6075 /*
6076 * Do this here before restoring debug registers on the host. And
6077 * since we do this before handling the vmexit, a DR access vmexit
6078 * can (a) read the correct value of the debug registers, (b) set
6079 * KVM_DEBUGREG_WONT_EXIT again.
6080 */
6081 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6082 int i;
6083
6084 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6085 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6086 for (i = 0; i < KVM_NR_DB_REGS; i++)
6087 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6088 }
6089
24f1e32c
FW		 6090 /*
6091 * If the guest has used debug registers, at least dr7
6092 * will be disabled while returning to the host.
6093 * If we don't have active breakpoints in the host, we don't
6094 * care about the messed up debug address registers. But if
6095 * we have some of them active, restore the old state.
6096 */
59d8eb53 6097 if (hw_breakpoint_active())
24f1e32c 6098 hw_breakpoint_restore();
42dbaa5a 6099
886b470c
MT		 6100 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6101 native_read_tsc());
1d5f066e 6102
6b7e2d09 6103 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6104 smp_wmb();
a547c6db
YZ		 6105
6106 /* Interrupt is enabled by handle_external_intr() */
6107 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6108
6109 ++vcpu->stat.exits;
6110
6111 /*
6112 * We must have an instruction between local_irq_enable() and
6113 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6114 * the interrupt shadow. The stat.exits increment will do nicely.
6115 * But we need to prevent reordering, hence this barrier():
6116 */
6117 barrier();
6118
6119 kvm_guest_exit();
6120
6121 preempt_enable();
6122
f656ce01 6123 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6124
b6c7a5dc
HB		 6125 /*
6126 * Profile KVM exit RIPs:
6127 */
6128 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6129 unsigned long rip = kvm_rip_read(vcpu);
6130 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6131 }
6132
cc578287
ZA		 6133 if (unlikely(vcpu->arch.tsc_always_catchup))
6134 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6135
5cfb1d5a
MT		 6136 if (vcpu->arch.apic_attention)
6137 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6138
851ba692 6139 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6140 return r;
6141
6142cancel_injection:
6143 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6144 if (unlikely(vcpu->arch.apic_attention))
6145 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6146out:
6147 return r;
6148}
b6c7a5dc 6149
09cec754 6150
851ba692 6151static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6152{
6153 int r;
f656ce01 6154 struct kvm *kvm = vcpu->kvm;
d7690175 6155
f656ce01 6156 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6157
6158 r = 1;
6159 while (r > 0) {
af585b92
GN		 6160 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6161 !vcpu->arch.apf.halted)
851ba692 6162 r = vcpu_enter_guest(vcpu);
d7690175 6163 else {
f656ce01 6164 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6165 kvm_vcpu_block(vcpu);
f656ce01 6166 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6167 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6168 kvm_apic_accept_events(vcpu);
09cec754
GN		 6169 switch(vcpu->arch.mp_state) {
6170 case KVM_MP_STATE_HALTED:
6aef266c 6171 vcpu->arch.pv.pv_unhalted = false;
d7690175 6172 vcpu->arch.mp_state =
09cec754
GN		 6173 KVM_MP_STATE_RUNNABLE;
6174 case KVM_MP_STATE_RUNNABLE:
af585b92 6175 vcpu->arch.apf.halted = false;
09cec754 6176 break;
66450a21
JK		 6177 case KVM_MP_STATE_INIT_RECEIVED:
6178 break;
09cec754
GN		 6179 default:
6180 r = -EINTR;
6181 break;
6182 }
6183 }
d7690175
MT		 6184 }
6185
09cec754
GN		 6186 if (r <= 0)
6187 break;
6188
6189 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6190 if (kvm_cpu_has_pending_timer(vcpu))
6191 kvm_inject_pending_timer_irqs(vcpu);
6192
851ba692 6193 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6194 r = -EINTR;
851ba692 6195 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6196 ++vcpu->stat.request_irq_exits;
6197 }
af585b92
GN		 6198
6199 kvm_check_async_pf_completion(vcpu);
6200
09cec754
GN		 6201 if (signal_pending(current)) {
6202 r = -EINTR;
851ba692 6203 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6204 ++vcpu->stat.signal_exits;
6205 }
6206 if (need_resched()) {
f656ce01 6207 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6208 cond_resched();
f656ce01 6209 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6210 }
b6c7a5dc
HB		 6211 }
6212
f656ce01 6213 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6214
6215 return r;
6216}
6217
716d51ab
GN		 6218static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6219{
6220 int r;
6221 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6222 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6223 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6224 if (r != EMULATE_DONE)
6225 return 0;
6226 return 1;
6227}
6228
6229static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6230{
6231 BUG_ON(!vcpu->arch.pio.count);
6232
6233 return complete_emulated_io(vcpu);
6234}
6235
f78146b0
AK		 6236/*
6237 * Implements the following, as a state machine:
6238 *
6239 * read:
6240 * for each fragment
87da7e66
XG		 6241 * for each mmio piece in the fragment
6242 * write gpa, len
6243 * exit
6244 * copy data
f78146b0
AK		 6245 * execute insn
6246 *
6247 * write:
6248 * for each fragment
87da7e66
XG		 6249 * for each mmio piece in the fragment
6250 * write gpa, len
6251 * copy data
6252 * exit
f78146b0 6253 */
716d51ab 6254static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6255{
6256 struct kvm_run *run = vcpu->run;
f78146b0 6257 struct kvm_mmio_fragment *frag;
87da7e66 6258 unsigned len;
5287f194 6259
716d51ab 6260 BUG_ON(!vcpu->mmio_needed);
5287f194 6261
716d51ab 6262 /* Complete previous fragment */
87da7e66
XG		 6263 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6264 len = min(8u, frag->len);
716d51ab 6265 if (!vcpu->mmio_is_write)
87da7e66
XG		 6266 memcpy(frag->data, run->mmio.data, len);
6267
6268 if (frag->len <= 8) {
6269 /* Switch to the next fragment. */
6270 frag++;
6271 vcpu->mmio_cur_fragment++;
6272 } else {
6273 /* Go forward to the next mmio piece. */
6274 frag->data += len;
6275 frag->gpa += len;
6276 frag->len -= len;
6277 }
6278
a08d3b3b 6279 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6280 vcpu->mmio_needed = 0;
0912c977
PB		 6281
6282 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6283 if (vcpu->mmio_is_write)
716d51ab
GN		 6284 return 1;
6285 vcpu->mmio_read_completed = 1;
6286 return complete_emulated_io(vcpu);
6287 }
87da7e66 6288
716d51ab
GN		 6289 run->exit_reason = KVM_EXIT_MMIO;
6290 run->mmio.phys_addr = frag->gpa;
6291 if (vcpu->mmio_is_write)
87da7e66
XG		 6292 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6293 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6294 run->mmio.is_write = vcpu->mmio_is_write;
6295 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6296 return 0;
5287f194
AK		 6297}
6298
716d51ab 6299
b6c7a5dc
HB		 6300int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6301{
6302 int r;
6303 sigset_t sigsaved;
6304
e5c30142
AK		 6305 if (!tsk_used_math(current) && init_fpu(current))
6306 return -ENOMEM;
6307
ac9f6dc0
AK		 6308 if (vcpu->sigset_active)
6309 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6310
a4535290 6311 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6312 kvm_vcpu_block(vcpu);
66450a21 6313 kvm_apic_accept_events(vcpu);
d7690175 6314 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6315 r = -EAGAIN;
6316 goto out;
b6c7a5dc
HB		 6317 }
6318
b6c7a5dc 6319 /* re-sync apic's tpr */
eea1cff9
AP		 6320 if (!irqchip_in_kernel(vcpu->kvm)) {
6321 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6322 r = -EINVAL;
6323 goto out;
6324 }
6325 }
b6c7a5dc 6326
716d51ab
GN		 6327 if (unlikely(vcpu->arch.complete_userspace_io)) {
6328 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6329 vcpu->arch.complete_userspace_io = NULL;
6330 r = cui(vcpu);
6331 if (r <= 0)
6332 goto out;
6333 } else
6334 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6335
851ba692 6336 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6337
6338out:
f1d86e46 6339 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6340 if (vcpu->sigset_active)
6341 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6342
b6c7a5dc
HB		 6343 return r;
6344}
6345
6346int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6347{
7ae441ea
GN		 6348 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6349 /*
6350 * We are here if userspace calls get_regs() in the middle of
6351 * instruction emulation. Registers state needs to be copied
4a969980 6352 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6353 * that usually, but some bad designed PV devices (vmware
6354 * backdoor interface) need this to work
6355 */
dd856efa 6356 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6357 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6358 }
5fdbf976
MT		 6359 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6360 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6361 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6362 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6363 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6364 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6365 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6366 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6367#ifdef CONFIG_X86_64
5fdbf976
MT		 6368 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6369 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6370 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6371 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6372 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6373 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6374 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6375 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6376#endif
6377
5fdbf976 6378 regs->rip = kvm_rip_read(vcpu);
91586a3b 6379 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6380
b6c7a5dc
HB		 6381 return 0;
6382}
6383
6384int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6385{
7ae441ea
GN		 6386 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6387 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6388
5fdbf976
MT		 6389 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6390 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6391 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6392 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6393 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6394 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6395 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6396 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6397#ifdef CONFIG_X86_64
5fdbf976
MT		 6398 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6399 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6400 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6401 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6402 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6403 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6404 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6405 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6406#endif
6407
5fdbf976 6408 kvm_rip_write(vcpu, regs->rip);
91586a3b 6409 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6410
b4f14abd
JK		 6411 vcpu->arch.exception.pending = false;
6412
3842d135
AK		 6413 kvm_make_request(KVM_REQ_EVENT, vcpu);
6414
b6c7a5dc
HB		 6415 return 0;
6416}
6417
b6c7a5dc
HB		 6418void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6419{
6420 struct kvm_segment cs;
6421
3e6e0aab 6422 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6423 *db = cs.db;
6424 *l = cs.l;
6425}
6426EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6427
6428int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6429 struct kvm_sregs *sregs)
6430{
89a27f4d 6431 struct desc_ptr dt;
b6c7a5dc 6432
3e6e0aab
GT		 6433 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6434 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6435 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6436 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6437 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6438 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6439
3e6e0aab
GT		 6440 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6441 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6442
6443 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6444 sregs->idt.limit = dt.size;
6445 sregs->idt.base = dt.address;
b6c7a5dc 6446 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6447 sregs->gdt.limit = dt.size;
6448 sregs->gdt.base = dt.address;
b6c7a5dc 6449
4d4ec087 6450 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6451 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6452 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6453 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6454 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6455 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6456 sregs->apic_base = kvm_get_apic_base(vcpu);
6457
923c61bb 6458 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6459
36752c9b 6460 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6461 set_bit(vcpu->arch.interrupt.nr,
6462 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6463
b6c7a5dc
HB		 6464 return 0;
6465}
6466
62d9f0db
MT		 6467int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6468 struct kvm_mp_state *mp_state)
6469{
66450a21 6470 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6471 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6472 vcpu->arch.pv.pv_unhalted)
6473 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6474 else
6475 mp_state->mp_state = vcpu->arch.mp_state;
6476
62d9f0db
MT		 6477 return 0;
6478}
6479
6480int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6481 struct kvm_mp_state *mp_state)
6482{
66450a21
JK		 6483 if (!kvm_vcpu_has_lapic(vcpu) &&
6484 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6485 return -EINVAL;
6486
6487 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6488 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6489 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6490 } else
6491 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6492 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6493 return 0;
6494}
6495
7f3d35fd
KW		 6496int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6497 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6498{
9d74191a 6499 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6500 int ret;
e01c2426 6501
8ec4722d 6502 init_emulate_ctxt(vcpu);
c697518a 6503
7f3d35fd 6504 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6505 has_error_code, error_code);
c697518a 6506
c697518a 6507 if (ret)
19d04437 6508 return EMULATE_FAIL;
37817f29 6509
9d74191a
TY		 6510 kvm_rip_write(vcpu, ctxt->eip);
6511 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6512 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6513 return EMULATE_DONE;
37817f29
IE		 6514}
6515EXPORT_SYMBOL_GPL(kvm_task_switch);
6516
b6c7a5dc
HB		 6517int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6518 struct kvm_sregs *sregs)
6519{
58cb628d 6520 struct msr_data apic_base_msr;
b6c7a5dc 6521 int mmu_reset_needed = 0;
63f42e02 6522 int pending_vec, max_bits, idx;
89a27f4d 6523 struct desc_ptr dt;
b6c7a5dc 6524
6d1068b3
PM		 6525 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6526 return -EINVAL;
6527
89a27f4d
GN		 6528 dt.size = sregs->idt.limit;
6529 dt.address = sregs->idt.base;
b6c7a5dc 6530 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6531 dt.size = sregs->gdt.limit;
6532 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6533 kvm_x86_ops->set_gdt(vcpu, &dt);
6534
ad312c7c 6535 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6536 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6537 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6538 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6539
2d3ad1f4 6540 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6541
f6801dff 6542 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6543 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6544 apic_base_msr.data = sregs->apic_base;
6545 apic_base_msr.host_initiated = true;
6546 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6547
4d4ec087 6548 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6549 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6550 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6551
fc78f519 6552 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6553 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6554 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6555 kvm_update_cpuid(vcpu);
63f42e02
XG		 6556
6557 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6558 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6559 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6560 mmu_reset_needed = 1;
6561 }
63f42e02 6562 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6563
6564 if (mmu_reset_needed)
6565 kvm_mmu_reset_context(vcpu);
6566
a50abc3b 6567 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6568 pending_vec = find_first_bit(
6569 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6570 if (pending_vec < max_bits) {
66fd3f7f 6571 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6572 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6573 }
6574
3e6e0aab
GT		 6575 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6576 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6577 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6578 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6579 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6580 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6581
3e6e0aab
GT		 6582 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6583 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6584
5f0269f5
ME		 6585 update_cr8_intercept(vcpu);
6586
9c3e4aab 6587 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6588 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6589 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6590 !is_protmode(vcpu))
9c3e4aab
MT		 6591 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6592
3842d135
AK		 6593 kvm_make_request(KVM_REQ_EVENT, vcpu);
6594
b6c7a5dc
HB		 6595 return 0;
6596}
6597
d0bfb940
JK		 6598int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6599 struct kvm_guest_debug *dbg)
b6c7a5dc 6600{
355be0b9 6601 unsigned long rflags;
ae675ef0 6602 int i, r;
b6c7a5dc 6603
4f926bf2
JK		 6604 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6605 r = -EBUSY;
6606 if (vcpu->arch.exception.pending)
2122ff5e 6607 goto out;
4f926bf2
JK		 6608 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6609 kvm_queue_exception(vcpu, DB_VECTOR);
6610 else
6611 kvm_queue_exception(vcpu, BP_VECTOR);
6612 }
6613
91586a3b
JK		 6614 /*
6615 * Read rflags as long as potentially injected trace flags are still
6616 * filtered out.
6617 */
6618 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6619
6620 vcpu->guest_debug = dbg->control;
6621 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6622 vcpu->guest_debug = 0;
6623
6624 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6625 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6626 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6627 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6628 } else {
6629 for (i = 0; i < KVM_NR_DB_REGS; i++)
6630 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6631 }
c8639010 6632 kvm_update_dr7(vcpu);
ae675ef0 6633
f92653ee
JK		 6634 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6635 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6636 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6637
91586a3b
JK		 6638 /*
6639 * Trigger an rflags update that will inject or remove the trace
6640 * flags.
6641 */
6642 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6643
c8639010 6644 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6645
4f926bf2 6646 r = 0;
d0bfb940 6647
2122ff5e 6648out:
b6c7a5dc
HB		 6649
6650 return r;
6651}
6652
8b006791
ZX		 6653/*
6654 * Translate a guest virtual address to a guest physical address.
6655 */
6656int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6657 struct kvm_translation *tr)
6658{
6659 unsigned long vaddr = tr->linear_address;
6660 gpa_t gpa;
f656ce01 6661 int idx;
8b006791 6662
f656ce01 6663 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6664 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6665 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6666 tr->physical_address = gpa;
6667 tr->valid = gpa != UNMAPPED_GVA;
6668 tr->writeable = 1;
6669 tr->usermode = 0;
8b006791
ZX		 6670
6671 return 0;
6672}
6673
d0752060
HB		 6674int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6675{
98918833
SY		 6676 struct i387_fxsave_struct *fxsave =
6677 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6678
d0752060
HB		 6679 memcpy(fpu->fpr, fxsave->st_space, 128);
6680 fpu->fcw = fxsave->cwd;
6681 fpu->fsw = fxsave->swd;
6682 fpu->ftwx = fxsave->twd;
6683 fpu->last_opcode = fxsave->fop;
6684 fpu->last_ip = fxsave->rip;
6685 fpu->last_dp = fxsave->rdp;
6686 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6687
d0752060
HB		 6688 return 0;
6689}
6690
6691int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6692{
98918833
SY		 6693 struct i387_fxsave_struct *fxsave =
6694 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6695
d0752060
HB		 6696 memcpy(fxsave->st_space, fpu->fpr, 128);
6697 fxsave->cwd = fpu->fcw;
6698 fxsave->swd = fpu->fsw;
6699 fxsave->twd = fpu->ftwx;
6700 fxsave->fop = fpu->last_opcode;
6701 fxsave->rip = fpu->last_ip;
6702 fxsave->rdp = fpu->last_dp;
6703 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6704
d0752060
HB		 6705 return 0;
6706}
6707
10ab25cd 6708int fx_init(struct kvm_vcpu *vcpu)
d0752060 6709{
10ab25cd
JK		 6710 int err;
6711
6712 err = fpu_alloc(&vcpu->arch.guest_fpu);
6713 if (err)
6714 return err;
6715
98918833 6716 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6717
2acf923e
DC		 6718 /*
6719 * Ensure guest xcr0 is valid for loading
6720 */
6721 vcpu->arch.xcr0 = XSTATE_FP;
6722
ad312c7c 6723 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6724
6725 return 0;
d0752060
HB		 6726}
6727EXPORT_SYMBOL_GPL(fx_init);
6728
98918833
SY		 6729static void fx_free(struct kvm_vcpu *vcpu)
6730{
6731 fpu_free(&vcpu->arch.guest_fpu);
6732}
6733
d0752060
HB		 6734void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6735{
2608d7a1 6736 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6737 return;
6738
2acf923e
DC		 6739 /*
6740 * Restore all possible states in the guest,
6741 * and assume host would use all available bits.
6742 * Guest xcr0 would be loaded later.
6743 */
6744 kvm_put_guest_xcr0(vcpu);
d0752060 6745 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6746 __kernel_fpu_begin();
98918833 6747 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6748 trace_kvm_fpu(1);
d0752060 6749}
d0752060
HB		 6750
6751void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6752{
2acf923e
DC		 6753 kvm_put_guest_xcr0(vcpu);
6754
d0752060
HB		 6755 if (!vcpu->guest_fpu_loaded)
6756 return;
6757
6758 vcpu->guest_fpu_loaded = 0;
98918833 6759 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6760 __kernel_fpu_end();
f096ed85 6761 ++vcpu->stat.fpu_reload;
a8eeb04a 6762 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6763 trace_kvm_fpu(0);
d0752060 6764}
e9b11c17
ZX		 6765
6766void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6767{
12f9a48f 6768 kvmclock_reset(vcpu);
7f1ea208 6769
f5f48ee1 6770 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6771 fx_free(vcpu);
e9b11c17
ZX		 6772 kvm_x86_ops->vcpu_free(vcpu);
6773}
6774
6775struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6776 unsigned int id)
6777{
6755bae8
ZA		 6778 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6779 printk_once(KERN_WARNING
6780 "kvm: SMP vm created on host with unstable TSC; "
6781 "guest TSC will not be reliable\n");
26e5215f
AK		 6782 return kvm_x86_ops->vcpu_create(kvm, id);
6783}
e9b11c17 6784
26e5215f
AK		 6785int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6786{
6787 int r;
e9b11c17 6788
0bed3b56 6789 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6790 r = vcpu_load(vcpu);
6791 if (r)
6792 return r;
57f252f2 6793 kvm_vcpu_reset(vcpu);
8a3c1a33 6794 kvm_mmu_setup(vcpu);
e9b11c17 6795 vcpu_put(vcpu);
e9b11c17 6796
26e5215f 6797 return r;
e9b11c17
ZX		 6798}
6799
42897d86
MT		 6800int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6801{
6802 int r;
8fe8ab46 6803 struct msr_data msr;
332967a3 6804 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6805
6806 r = vcpu_load(vcpu);
6807 if (r)
6808 return r;
8fe8ab46
WA		 6809 msr.data = 0x0;
6810 msr.index = MSR_IA32_TSC;
6811 msr.host_initiated = true;
6812 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6813 vcpu_put(vcpu);
6814
332967a3
AJ		 6815 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6816 KVMCLOCK_SYNC_PERIOD);
6817
42897d86
MT		 6818 return r;
6819}
6820
d40ccc62 6821void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6822{
9fc77441 6823 int r;
344d9588
GN		 6824 vcpu->arch.apf.msr_val = 0;
6825
9fc77441
MT		 6826 r = vcpu_load(vcpu);
6827 BUG_ON(r);
e9b11c17
ZX		 6828 kvm_mmu_unload(vcpu);
6829 vcpu_put(vcpu);
6830
98918833 6831 fx_free(vcpu);
e9b11c17
ZX		 6832 kvm_x86_ops->vcpu_free(vcpu);
6833}
6834
66450a21 6835void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6836{
7460fb4a
AK		 6837 atomic_set(&vcpu->arch.nmi_queued, 0);
6838 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6839 vcpu->arch.nmi_injected = false;
6840
42dbaa5a
JK		 6841 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6842 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6843 kvm_update_dr6(vcpu);
42dbaa5a 6844 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6845 kvm_update_dr7(vcpu);
42dbaa5a 6846
3842d135 6847 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6848 vcpu->arch.apf.msr_val = 0;
c9aaa895 6849 vcpu->arch.st.msr_val = 0;
3842d135 6850
12f9a48f
GC		 6851 kvmclock_reset(vcpu);
6852
af585b92
GN		 6853 kvm_clear_async_pf_completion_queue(vcpu);
6854 kvm_async_pf_hash_reset(vcpu);
6855 vcpu->arch.apf.halted = false;
3842d135 6856
f5132b01
GN		 6857 kvm_pmu_reset(vcpu);
6858
66f7b72e
JS		 6859 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6860 vcpu->arch.regs_avail = ~0;
6861 vcpu->arch.regs_dirty = ~0;
6862
57f252f2 6863 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6864}
6865
66450a21
JK		 6866void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6867{
6868 struct kvm_segment cs;
6869
6870 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6871 cs.selector = vector << 8;
6872 cs.base = vector << 12;
6873 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6874 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6875}
6876
10474ae8 6877int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6878{
ca84d1a2
ZA		 6879 struct kvm *kvm;
6880 struct kvm_vcpu *vcpu;
6881 int i;
0dd6a6ed
ZA		 6882 int ret;
6883 u64 local_tsc;
6884 u64 max_tsc = 0;
6885 bool stable, backwards_tsc = false;
18863bdd
AK		 6886
6887 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6888 ret = kvm_x86_ops->hardware_enable(garbage);
6889 if (ret != 0)
6890 return ret;
6891
6892 local_tsc = native_read_tsc();
6893 stable = !check_tsc_unstable();
6894 list_for_each_entry(kvm, &vm_list, vm_list) {
6895 kvm_for_each_vcpu(i, vcpu, kvm) {
6896 if (!stable && vcpu->cpu == smp_processor_id())
6897 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6898 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6899 backwards_tsc = true;
6900 if (vcpu->arch.last_host_tsc > max_tsc)
6901 max_tsc = vcpu->arch.last_host_tsc;
6902 }
6903 }
6904 }
6905
6906 /*
6907 * Sometimes, even reliable TSCs go backwards. This happens on
6908 * platforms that reset TSC during suspend or hibernate actions, but
6909 * maintain synchronization. We must compensate. Fortunately, we can
6910 * detect that condition here, which happens early in CPU bringup,
6911 * before any KVM threads can be running. Unfortunately, we can't
6912 * bring the TSCs fully up to date with real time, as we aren't yet far
6913 * enough into CPU bringup that we know how much real time has actually
6914 * elapsed; our helper function, get_kernel_ns() will be using boot
6915 * variables that haven't been updated yet.
6916 *
6917 * So we simply find the maximum observed TSC above, then record the
6918 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6919 * the adjustment will be applied. Note that we accumulate
6920 * adjustments, in case multiple suspend cycles happen before some VCPU
6921 * gets a chance to run again. In the event that no KVM threads get a
6922 * chance to run, we will miss the entire elapsed period, as we'll have
6923 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6924 * loose cycle time. This isn't too big a deal, since the loss will be
6925 * uniform across all VCPUs (not to mention the scenario is extremely
6926 * unlikely). It is possible that a second hibernate recovery happens
6927 * much faster than a first, causing the observed TSC here to be
6928 * smaller; this would require additional padding adjustment, which is
6929 * why we set last_host_tsc to the local tsc observed here.
6930 *
6931 * N.B. - this code below runs only on platforms with reliable TSC,
6932 * as that is the only way backwards_tsc is set above. Also note
6933 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6934 * have the same delta_cyc adjustment applied if backwards_tsc
6935 * is detected. Note further, this adjustment is only done once,
6936 * as we reset last_host_tsc on all VCPUs to stop this from being
6937 * called multiple times (one for each physical CPU bringup).
6938 *
4a969980 6939 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6940 * will be compensated by the logic in vcpu_load, which sets the TSC to
6941 * catchup mode. This will catchup all VCPUs to real time, but cannot
6942 * guarantee that they stay in perfect synchronization.
6943 */
6944 if (backwards_tsc) {
6945 u64 delta_cyc = max_tsc - local_tsc;
6946 list_for_each_entry(kvm, &vm_list, vm_list) {
6947 kvm_for_each_vcpu(i, vcpu, kvm) {
6948 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6949 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6950 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6951 &vcpu->requests);
0dd6a6ed
ZA		 6952 }
6953
6954 /*
6955 * We have to disable TSC offset matching.. if you were
6956 * booting a VM while issuing an S4 host suspend....
6957 * you may have some problem. Solving this issue is
6958 * left as an exercise to the reader.
6959 */
6960 kvm->arch.last_tsc_nsec = 0;
6961 kvm->arch.last_tsc_write = 0;
6962 }
6963
6964 }
6965 return 0;
e9b11c17
ZX		 6966}
6967
6968void kvm_arch_hardware_disable(void *garbage)
6969{
6970 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6971 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6972}
6973
6974int kvm_arch_hardware_setup(void)
6975{
6976 return kvm_x86_ops->hardware_setup();
6977}
6978
6979void kvm_arch_hardware_unsetup(void)
6980{
6981 kvm_x86_ops->hardware_unsetup();
6982}
6983
6984void kvm_arch_check_processor_compat(void *rtn)
6985{
6986 kvm_x86_ops->check_processor_compatibility(rtn);
6987}
6988
3e515705
AK		 6989bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6990{
6991 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6992}
6993
54e9818f
GN		 6994struct static_key kvm_no_apic_vcpu __read_mostly;
6995
e9b11c17
ZX		 6996int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6997{
6998 struct page *page;
6999 struct kvm *kvm;
7000 int r;
7001
7002 BUG_ON(vcpu->kvm == NULL);
7003 kvm = vcpu->kvm;
7004
6aef266c 7005 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7006 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7007 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7008 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7009 else
a4535290 7010 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7011
7012 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7013 if (!page) {
7014 r = -ENOMEM;
7015 goto fail;
7016 }
ad312c7c 7017 vcpu->arch.pio_data = page_address(page);
e9b11c17 7018
cc578287 7019 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7020
e9b11c17
ZX		 7021 r = kvm_mmu_create(vcpu);
7022 if (r < 0)
7023 goto fail_free_pio_data;
7024
7025 if (irqchip_in_kernel(kvm)) {
7026 r = kvm_create_lapic(vcpu);
7027 if (r < 0)
7028 goto fail_mmu_destroy;
54e9818f
GN		 7029 } else
7030 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7031
890ca9ae
HY		 7032 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7033 GFP_KERNEL);
7034 if (!vcpu->arch.mce_banks) {
7035 r = -ENOMEM;
443c39bc 7036 goto fail_free_lapic;
890ca9ae
HY		 7037 }
7038 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7039
f1797359
WY		 7040 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7041 r = -ENOMEM;
f5f48ee1 7042 goto fail_free_mce_banks;
f1797359 7043 }
f5f48ee1 7044
66f7b72e
JS		 7045 r = fx_init(vcpu);
7046 if (r)
7047 goto fail_free_wbinvd_dirty_mask;
7048
ba904635 7049 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7050 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7051
7052 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7053 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7054
af585b92 7055 kvm_async_pf_hash_reset(vcpu);
f5132b01 7056 kvm_pmu_init(vcpu);
af585b92 7057
e9b11c17 7058 return 0;
66f7b72e
JS		 7059fail_free_wbinvd_dirty_mask:
7060 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7061fail_free_mce_banks:
7062 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7063fail_free_lapic:
7064 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7065fail_mmu_destroy:
7066 kvm_mmu_destroy(vcpu);
7067fail_free_pio_data:
ad312c7c 7068 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7069fail:
7070 return r;
7071}
7072
7073void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7074{
f656ce01
MT		 7075 int idx;
7076
f5132b01 7077 kvm_pmu_destroy(vcpu);
36cb93fd 7078 kfree(vcpu->arch.mce_banks);
e9b11c17 7079 kvm_free_lapic(vcpu);
f656ce01 7080 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7081 kvm_mmu_destroy(vcpu);
f656ce01 7082 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7083 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7084 if (!irqchip_in_kernel(vcpu->kvm))
7085 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7086}
d19a9cd2 7087
e08b9637 7088int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7089{
e08b9637
CO		 7090 if (type)
7091 return -EINVAL;
7092
f05e70ac 7093 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7094 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7095 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7096 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7097
5550af4d
SY		 7098 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7099 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7100 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7101 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7102 &kvm->arch.irq_sources_bitmap);
5550af4d 7103
038f8c11 7104 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7105 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7106 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7107
7108 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7109
7e44e449 7110 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7111 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7112
d89f5eff 7113 return 0;
d19a9cd2
ZX		 7114}
7115
7116static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7117{
9fc77441
MT		 7118 int r;
7119 r = vcpu_load(vcpu);
7120 BUG_ON(r);
d19a9cd2
ZX		 7121 kvm_mmu_unload(vcpu);
7122 vcpu_put(vcpu);
7123}
7124
7125static void kvm_free_vcpus(struct kvm *kvm)
7126{
7127 unsigned int i;
988a2cae 7128 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7129
7130 /*
7131 * Unpin any mmu pages first.
7132 */
af585b92
GN		 7133 kvm_for_each_vcpu(i, vcpu, kvm) {
7134 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7135 kvm_unload_vcpu_mmu(vcpu);
af585b92 7136 }
988a2cae
GN		 7137 kvm_for_each_vcpu(i, vcpu, kvm)
7138 kvm_arch_vcpu_free(vcpu);
7139
7140 mutex_lock(&kvm->lock);
7141 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7142 kvm->vcpus[i] = NULL;
d19a9cd2 7143
988a2cae
GN		 7144 atomic_set(&kvm->online_vcpus, 0);
7145 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7146}
7147
ad8ba2cd
SY		 7148void kvm_arch_sync_events(struct kvm *kvm)
7149{
332967a3 7150 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7151 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7152 kvm_free_all_assigned_devices(kvm);
aea924f6 7153 kvm_free_pit(kvm);
ad8ba2cd
SY		 7154}
7155
d19a9cd2
ZX		 7156void kvm_arch_destroy_vm(struct kvm *kvm)
7157{
27469d29
AH		 7158 if (current->mm == kvm->mm) {
7159 /*
7160 * Free memory regions allocated on behalf of userspace,
7161 * unless the the memory map has changed due to process exit
7162 * or fd copying.
7163 */
7164 struct kvm_userspace_memory_region mem;
7165 memset(&mem, 0, sizeof(mem));
7166 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7167 kvm_set_memory_region(kvm, &mem);
7168
7169 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7170 kvm_set_memory_region(kvm, &mem);
7171
7172 mem.slot = TSS_PRIVATE_MEMSLOT;
7173 kvm_set_memory_region(kvm, &mem);
7174 }
6eb55818 7175 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7176 kfree(kvm->arch.vpic);
7177 kfree(kvm->arch.vioapic);
d19a9cd2 7178 kvm_free_vcpus(kvm);
3d45830c
AK		 7179 if (kvm->arch.apic_access_page)
7180 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7181 if (kvm->arch.ept_identity_pagetable)
7182 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7183 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7184}
0de10343 7185
5587027c 7186void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7187 struct kvm_memory_slot *dont)
7188{
7189 int i;
7190
d89cc617
TY		 7191 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7192 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7193 kvm_kvfree(free->arch.rmap[i]);
7194 free->arch.rmap[i] = NULL;
77d11309 7195 }
d89cc617
TY		 7196 if (i == 0)
7197 continue;
7198
7199 if (!dont || free->arch.lpage_info[i - 1] !=
7200 dont->arch.lpage_info[i - 1]) {
7201 kvm_kvfree(free->arch.lpage_info[i - 1]);
7202 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7203 }
7204 }
7205}
7206
5587027c
AK		 7207int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7208 unsigned long npages)
db3fe4eb
TY		 7209{
7210 int i;
7211
d89cc617 7212 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7213 unsigned long ugfn;
7214 int lpages;
d89cc617 7215 int level = i + 1;
db3fe4eb
TY		 7216
7217 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7218 slot->base_gfn, level) + 1;
7219
d89cc617
TY		 7220 slot->arch.rmap[i] =
7221 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7222 if (!slot->arch.rmap[i])
77d11309 7223 goto out_free;
d89cc617
TY		 7224 if (i == 0)
7225 continue;
77d11309 7226
d89cc617
TY		 7227 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7228 sizeof(*slot->arch.lpage_info[i - 1]));
7229 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7230 goto out_free;
7231
7232 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7233 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7234 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7235 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7236 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7237 /*
7238 * If the gfn and userspace address are not aligned wrt each
7239 * other, or if explicitly asked to, disable large page
7240 * support for this slot
7241 */
7242 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7243 !kvm_largepages_enabled()) {
7244 unsigned long j;
7245
7246 for (j = 0; j < lpages; ++j)
d89cc617 7247 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7248 }
7249 }
7250
7251 return 0;
7252
7253out_free:
d89cc617
TY		 7254 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7255 kvm_kvfree(slot->arch.rmap[i]);
7256 slot->arch.rmap[i] = NULL;
7257 if (i == 0)
7258 continue;
7259
7260 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7261 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7262 }
7263 return -ENOMEM;
7264}
7265
e59dbe09
TY		 7266void kvm_arch_memslots_updated(struct kvm *kvm)
7267{
e6dff7d1
TY		 7268 /*
7269 * memslots->generation has been incremented.
7270 * mmio generation may have reached its maximum value.
7271 */
7272 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7273}
7274
f7784b8e
MT		 7275int kvm_arch_prepare_memory_region(struct kvm *kvm,
7276 struct kvm_memory_slot *memslot,
f7784b8e 7277 struct kvm_userspace_memory_region *mem,
7b6195a9 7278 enum kvm_mr_change change)
0de10343 7279{
7a905b14
TY		 7280 /*
7281 * Only private memory slots need to be mapped here since
7282 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7283 */
7b6195a9 7284 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7285 unsigned long userspace_addr;
604b38ac 7286
7a905b14
TY		 7287 /*
7288 * MAP_SHARED to prevent internal slot pages from being moved
7289 * by fork()/COW.
7290 */
7b6195a9 7291 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7292 PROT_READ | PROT_WRITE,
7293 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7294
7a905b14
TY		 7295 if (IS_ERR((void *)userspace_addr))
7296 return PTR_ERR((void *)userspace_addr);
604b38ac 7297
7a905b14 7298 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7299 }
7300
f7784b8e
MT		 7301 return 0;
7302}
7303
7304void kvm_arch_commit_memory_region(struct kvm *kvm,
7305 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7306 const struct kvm_memory_slot *old,
7307 enum kvm_mr_change change)
f7784b8e
MT		 7308{
7309
8482644a 7310 int nr_mmu_pages = 0;
f7784b8e 7311
8482644a 7312 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7313 int ret;
7314
8482644a
TY		 7315 ret = vm_munmap(old->userspace_addr,
7316 old->npages * PAGE_SIZE);
f7784b8e
MT		 7317 if (ret < 0)
7318 printk(KERN_WARNING
7319 "kvm_vm_ioctl_set_memory_region: "
7320 "failed to munmap memory\n");
7321 }
7322
48c0e4e9
XG		 7323 if (!kvm->arch.n_requested_mmu_pages)
7324 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7325
48c0e4e9 7326 if (nr_mmu_pages)
0de10343 7327 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7328 /*
7329 * Write protect all pages for dirty logging.
c126d94f
XG		 7330 *
7331 * All the sptes including the large sptes which point to this
7332 * slot are set to readonly. We can not create any new large
7333 * spte on this slot until the end of the logging.
7334 *
7335 * See the comments in fast_page_fault().
c972f3b1 7336 */
8482644a 7337 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7338 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7339}
1d737c8a 7340
2df72e9b 7341void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7342{
6ca18b69 7343 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7344}
7345
2df72e9b
MT		 7346void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7347 struct kvm_memory_slot *slot)
7348{
6ca18b69 7349 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7350}
7351
1d737c8a
ZX		 7352int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7353{
b6b8a145
JK		 7354 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7355 kvm_x86_ops->check_nested_events(vcpu, false);
7356
af585b92
GN		 7357 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7358 !vcpu->arch.apf.halted)
7359 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7360 || kvm_apic_has_events(vcpu)
6aef266c 7361 || vcpu->arch.pv.pv_unhalted
7460fb4a 7362 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7363 (kvm_arch_interrupt_allowed(vcpu) &&
7364 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7365}
5736199a 7366
b6d33834 7367int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7368{
b6d33834 7369 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7370}
78646121
GN		 7371
7372int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7373{
7374 return kvm_x86_ops->interrupt_allowed(vcpu);
7375}
229456fc 7376
f92653ee
JK		 7377bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7378{
7379 unsigned long current_rip = kvm_rip_read(vcpu) +
7380 get_segment_base(vcpu, VCPU_SREG_CS);
7381
7382 return current_rip == linear_rip;
7383}
7384EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7385
94fe45da
JK		 7386unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7387{
7388 unsigned long rflags;
7389
7390 rflags = kvm_x86_ops->get_rflags(vcpu);
7391 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7392 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7393 return rflags;
7394}
7395EXPORT_SYMBOL_GPL(kvm_get_rflags);
7396
7397void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7398{
7399 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7400 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7401 rflags |= X86_EFLAGS_TF;
94fe45da 7402 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7403 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7404}
7405EXPORT_SYMBOL_GPL(kvm_set_rflags);
7406
56028d08
GN		 7407void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7408{
7409 int r;
7410
fb67e14f 7411 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7412 work->wakeup_all)
56028d08
GN		 7413 return;
7414
7415 r = kvm_mmu_reload(vcpu);
7416 if (unlikely(r))
7417 return;
7418
fb67e14f
XG		 7419 if (!vcpu->arch.mmu.direct_map &&
7420 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7421 return;
7422
56028d08
GN		 7423 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7424}
7425
af585b92
GN		 7426static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7427{
7428 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7429}
7430
7431static inline u32 kvm_async_pf_next_probe(u32 key)
7432{
7433 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7434}
7435
7436static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7437{
7438 u32 key = kvm_async_pf_hash_fn(gfn);
7439
7440 while (vcpu->arch.apf.gfns[key] != ~0)
7441 key = kvm_async_pf_next_probe(key);
7442
7443 vcpu->arch.apf.gfns[key] = gfn;
7444}
7445
7446static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7447{
7448 int i;
7449 u32 key = kvm_async_pf_hash_fn(gfn);
7450
7451 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7452 (vcpu->arch.apf.gfns[key] != gfn &&
7453 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7454 key = kvm_async_pf_next_probe(key);
7455
7456 return key;
7457}
7458
7459bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7460{
7461 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7462}
7463
7464static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7465{
7466 u32 i, j, k;
7467
7468 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7469 while (true) {
7470 vcpu->arch.apf.gfns[i] = ~0;
7471 do {
7472 j = kvm_async_pf_next_probe(j);
7473 if (vcpu->arch.apf.gfns[j] == ~0)
7474 return;
7475 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7476 /*
7477 * k lies cyclically in ]i,j]
7478 * | i.k.j |
7479 * |....j i.k.| or |.k..j i...|
7480 */
7481 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7482 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7483 i = j;
7484 }
7485}
7486
7c90705b
GN		 7487static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7488{
7489
7490 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7491 sizeof(val));
7492}
7493
af585b92
GN		 7494void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7495 struct kvm_async_pf *work)
7496{
6389ee94
AK		 7497 struct x86_exception fault;
7498
7c90705b 7499 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7500 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7501
7502 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7503 (vcpu->arch.apf.send_user_only &&
7504 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7505 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7506 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7507 fault.vector = PF_VECTOR;
7508 fault.error_code_valid = true;
7509 fault.error_code = 0;
7510 fault.nested_page_fault = false;
7511 fault.address = work->arch.token;
7512 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7513 }
af585b92
GN		 7514}
7515
7516void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7517 struct kvm_async_pf *work)
7518{
6389ee94
AK		 7519 struct x86_exception fault;
7520
7c90705b 7521 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7522 if (work->wakeup_all)
7c90705b
GN		 7523 work->arch.token = ~0; /* broadcast wakeup */
7524 else
7525 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7526
7527 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7528 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7529 fault.vector = PF_VECTOR;
7530 fault.error_code_valid = true;
7531 fault.error_code = 0;
7532 fault.nested_page_fault = false;
7533 fault.address = work->arch.token;
7534 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7535 }
e6d53e3b 7536 vcpu->arch.apf.halted = false;
a4fa1635 7537 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7538}
7539
7540bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7541{
7542 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7543 return true;
7544 else
7545 return !kvm_event_needs_reinjection(vcpu) &&
7546 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7547}
7548
e0f0bbc5
AW		 7549void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7550{
7551 atomic_inc(&kvm->arch.noncoherent_dma_count);
7552}
7553EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7554
7555void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7556{
7557 atomic_dec(&kvm->arch.noncoherent_dma_count);
7558}
7559EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7560
7561bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7562{
7563 return atomic_read(&kvm->arch.noncoherent_dma_count);
7564}
7565EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7566
229456fc
MT		 7567EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7568EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7569EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7570EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7571EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7572EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7573EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7574EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7575EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7576EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7577EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7578EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7579EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux kernel - Deliverables
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