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KVM: x86 emulator: implement 'ret far' instruction (opcode 0xcb)
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
0bed3b56 43#include <asm/mtrr.h>
043405e1 44
313a3dc7 45#define MAX_IO_MSRS 256
a03490ed
CO		 46#define CR0_RESERVED_BITS \
47 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
48 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
49 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
50#define CR4_RESERVED_BITS \
51 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
52 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
53 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
54 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
55
56#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 57/* EFER defaults:
58 * - enable syscall per default because its emulated by KVM
59 * - enable LME and LMA per default on 64 bit KVM
60 */
61#ifdef CONFIG_X86_64
62static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
63#else
64static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
65#endif
313a3dc7 66
ba1389b7
AK		 67#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
68#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 69
674eea0f
AK		 70static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
71 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 72struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
73 u32 function, u32 index);
674eea0f 74
97896d04 75struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 76EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 77
417bc304 78struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 79 { "pf_fixed", VCPU_STAT(pf_fixed) },
80 { "pf_guest", VCPU_STAT(pf_guest) },
81 { "tlb_flush", VCPU_STAT(tlb_flush) },
82 { "invlpg", VCPU_STAT(invlpg) },
83 { "exits", VCPU_STAT(exits) },
84 { "io_exits", VCPU_STAT(io_exits) },
85 { "mmio_exits", VCPU_STAT(mmio_exits) },
86 { "signal_exits", VCPU_STAT(signal_exits) },
87 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 88 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 89 { "halt_exits", VCPU_STAT(halt_exits) },
90 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 91 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 92 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 93 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 94 { "irq_exits", VCPU_STAT(irq_exits) },
95 { "host_state_reload", VCPU_STAT(host_state_reload) },
96 { "efer_reload", VCPU_STAT(efer_reload) },
97 { "fpu_reload", VCPU_STAT(fpu_reload) },
98 { "insn_emulation", VCPU_STAT(insn_emulation) },
99 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 100 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 101 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 102 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
103 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
104 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
105 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
106 { "mmu_flooded", VM_STAT(mmu_flooded) },
107 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 108 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 109 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 110 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 111 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 112 { "largepages", VM_STAT(lpages) },
417bc304
HB		 113 { NULL }
114};
115
5fb76f9b
CO		 116unsigned long segment_base(u16 selector)
117{
118 struct descriptor_table gdt;
a5f61300 119 struct desc_struct *d;
5fb76f9b
CO		 120 unsigned long table_base;
121 unsigned long v;
122
123 if (selector == 0)
124 return 0;
125
126 asm("sgdt %0" : "=m"(gdt));
127 table_base = gdt.base;
128
129 if (selector & 4) { /* from ldt */
130 u16 ldt_selector;
131
132 asm("sldt %0" : "=g"(ldt_selector));
133 table_base = segment_base(ldt_selector);
134 }
a5f61300
AK		 135 d = (struct desc_struct *)(table_base + (selector & ~7));
136 v = d->base0 | ((unsigned long)d->base1 << 16) |
137 ((unsigned long)d->base2 << 24);
5fb76f9b 138#ifdef CONFIG_X86_64
a5f61300
AK		 139 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
140 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 141#endif
142 return v;
143}
144EXPORT_SYMBOL_GPL(segment_base);
145
6866b83e
CO		 146u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
147{
148 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 149 return vcpu->arch.apic_base;
6866b83e 150 else
ad312c7c 151 return vcpu->arch.apic_base;
6866b83e
CO		 152}
153EXPORT_SYMBOL_GPL(kvm_get_apic_base);
154
155void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
156{
157 /* TODO: reserve bits check */
158 if (irqchip_in_kernel(vcpu->kvm))
159 kvm_lapic_set_base(vcpu, data);
160 else
ad312c7c 161 vcpu->arch.apic_base = data;
6866b83e
CO		 162}
163EXPORT_SYMBOL_GPL(kvm_set_apic_base);
164
298101da
AK		 165void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
166{
ad312c7c
ZX		 167 WARN_ON(vcpu->arch.exception.pending);
168 vcpu->arch.exception.pending = true;
169 vcpu->arch.exception.has_error_code = false;
170 vcpu->arch.exception.nr = nr;
298101da
AK		 171}
172EXPORT_SYMBOL_GPL(kvm_queue_exception);
173
c3c91fee
AK		 174void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
175 u32 error_code)
176{
177 ++vcpu->stat.pf_guest;
d8017474 178
71c4dfaf
JR		 179 if (vcpu->arch.exception.pending) {
180 if (vcpu->arch.exception.nr == PF_VECTOR) {
181 printk(KERN_DEBUG "kvm: inject_page_fault:"
182 " double fault 0x%lx\n", addr);
183 vcpu->arch.exception.nr = DF_VECTOR;
184 vcpu->arch.exception.error_code = 0;
185 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
186 /* triple fault -> shutdown */
187 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
188 }
c3c91fee
AK		 189 return;
190 }
ad312c7c 191 vcpu->arch.cr2 = addr;
c3c91fee
AK		 192 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
193}
194
3419ffc8
SY		 195void kvm_inject_nmi(struct kvm_vcpu *vcpu)
196{
197 vcpu->arch.nmi_pending = 1;
198}
199EXPORT_SYMBOL_GPL(kvm_inject_nmi);
200
298101da
AK		 201void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
202{
ad312c7c
ZX		 203 WARN_ON(vcpu->arch.exception.pending);
204 vcpu->arch.exception.pending = true;
205 vcpu->arch.exception.has_error_code = true;
206 vcpu->arch.exception.nr = nr;
207 vcpu->arch.exception.error_code = error_code;
298101da
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
210
211static void __queue_exception(struct kvm_vcpu *vcpu)
212{
ad312c7c
ZX		 213 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
214 vcpu->arch.exception.has_error_code,
215 vcpu->arch.exception.error_code);
298101da
AK		 216}
217
a03490ed
CO		 218/*
219 * Load the pae pdptrs. Return true is they are all valid.
220 */
221int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
222{
223 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
224 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
225 int i;
226 int ret;
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 228
a03490ed
CO		 229 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
230 offset * sizeof(u64), sizeof(pdpte));
231 if (ret < 0) {
232 ret = 0;
233 goto out;
234 }
235 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
236 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
237 ret = 0;
238 goto out;
239 }
240 }
241 ret = 1;
242
ad312c7c 243 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 244out:
a03490ed
CO		 245
246 return ret;
247}
cc4b6871 248EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 249
d835dfec
AK		 250static bool pdptrs_changed(struct kvm_vcpu *vcpu)
251{
ad312c7c 252 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 253 bool changed = true;
254 int r;
255
256 if (is_long_mode(vcpu) || !is_pae(vcpu))
257 return false;
258
ad312c7c 259 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 260 if (r < 0)
261 goto out;
ad312c7c 262 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 263out:
d835dfec
AK		 264
265 return changed;
266}
267
2d3ad1f4 268void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 269{
270 if (cr0 & CR0_RESERVED_BITS) {
271 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 272 cr0, vcpu->arch.cr0);
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276
277 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
278 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 279 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 280 return;
281 }
282
283 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
284 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
285 "and a clear PE flag\n");
c1a5d4f9 286 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 287 return;
288 }
289
290 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
291#ifdef CONFIG_X86_64
ad312c7c 292 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 293 int cs_db, cs_l;
294
295 if (!is_pae(vcpu)) {
296 printk(KERN_DEBUG "set_cr0: #GP, start paging "
297 "in long mode while PAE is disabled\n");
c1a5d4f9 298 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 299 return;
300 }
301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
302 if (cs_l) {
303 printk(KERN_DEBUG "set_cr0: #GP, start paging "
304 "in long mode while CS.L == 1\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307
308 }
309 } else
310#endif
ad312c7c 311 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 312 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
313 "reserved bits\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317
318 }
319
320 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 321 vcpu->arch.cr0 = cr0;
a03490ed 322
6cffe8ca 323 kvm_mmu_sync_global(vcpu);
a03490ed 324 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 325 return;
326}
2d3ad1f4 327EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 328
2d3ad1f4 329void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 330{
2d3ad1f4 331 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 332 KVMTRACE_1D(LMSW, vcpu,
333 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
334 handler);
a03490ed 335}
2d3ad1f4 336EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 337
2d3ad1f4 338void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 339{
340 if (cr4 & CR4_RESERVED_BITS) {
341 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 342 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 343 return;
344 }
345
346 if (is_long_mode(vcpu)) {
347 if (!(cr4 & X86_CR4_PAE)) {
348 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
349 "in long mode\n");
c1a5d4f9 350 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 351 return;
352 }
353 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 354 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 355 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359
360 if (cr4 & X86_CR4_VMXE) {
361 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 366 vcpu->arch.cr4 = cr4;
2f0b3d60 367 vcpu->arch.mmu.base_role.cr4_pge = !!(cr4 & X86_CR4_PGE);
6cffe8ca 368 kvm_mmu_sync_global(vcpu);
a03490ed 369 kvm_mmu_reset_context(vcpu);
a03490ed 370}
2d3ad1f4 371EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 372
2d3ad1f4 373void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 374{
ad312c7c 375 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 376 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 377 kvm_mmu_flush_tlb(vcpu);
378 return;
379 }
380
a03490ed
CO		 381 if (is_long_mode(vcpu)) {
382 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
383 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 384 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 385 return;
386 }
387 } else {
388 if (is_pae(vcpu)) {
389 if (cr3 & CR3_PAE_RESERVED_BITS) {
390 printk(KERN_DEBUG
391 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 392 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 393 return;
394 }
395 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
396 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
397 "reserved bits\n");
c1a5d4f9 398 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 399 return;
400 }
401 }
402 /*
403 * We don't check reserved bits in nonpae mode, because
404 * this isn't enforced, and VMware depends on this.
405 */
406 }
407
a03490ed
CO		 408 /*
409 * Does the new cr3 value map to physical memory? (Note, we
410 * catch an invalid cr3 even in real-mode, because it would
411 * cause trouble later on when we turn on paging anyway.)
412 *
413 * A real CPU would silently accept an invalid cr3 and would
414 * attempt to use it - with largely undefined (and often hard
415 * to debug) behavior on the guest side.
416 */
417 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 418 kvm_inject_gp(vcpu, 0);
a03490ed 419 else {
ad312c7c
ZX		 420 vcpu->arch.cr3 = cr3;
421 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 422 }
a03490ed 423}
2d3ad1f4 424EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 425
2d3ad1f4 426void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 427{
428 if (cr8 & CR8_RESERVED_BITS) {
429 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 430 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 431 return;
432 }
433 if (irqchip_in_kernel(vcpu->kvm))
434 kvm_lapic_set_tpr(vcpu, cr8);
435 else
ad312c7c 436 vcpu->arch.cr8 = cr8;
a03490ed 437}
2d3ad1f4 438EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 439
2d3ad1f4 440unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 441{
442 if (irqchip_in_kernel(vcpu->kvm))
443 return kvm_lapic_get_cr8(vcpu);
444 else
ad312c7c 445 return vcpu->arch.cr8;
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 448
d8017474
AG		 449static inline u32 bit(int bitno)
450{
451 return 1 << (bitno & 31);
452}
453
043405e1
CO		 454/*
455 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
456 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
457 *
458 * This list is modified at module load time to reflect the
459 * capabilities of the host cpu.
460 */
461static u32 msrs_to_save[] = {
462 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
463 MSR_K6_STAR,
464#ifdef CONFIG_X86_64
465 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
466#endif
18068523 467 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 468 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 469};
470
471static unsigned num_msrs_to_save;
472
473static u32 emulated_msrs[] = {
474 MSR_IA32_MISC_ENABLE,
475};
476
15c4a640
CO		 477static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
478{
f2b4b7dd 479 if (efer & efer_reserved_bits) {
15c4a640
CO		 480 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
481 efer);
c1a5d4f9 482 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 483 return;
484 }
485
486 if (is_paging(vcpu)
ad312c7c 487 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 488 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 490 return;
491 }
492
d8017474
AG		 493 if (efer & EFER_SVME) {
494 struct kvm_cpuid_entry2 *feat;
495
496 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
497 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
498 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
499 kvm_inject_gp(vcpu, 0);
500 return;
501 }
502 }
503
15c4a640
CO		 504 kvm_x86_ops->set_efer(vcpu, efer);
505
506 efer &= ~EFER_LMA;
ad312c7c 507 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 508
ad312c7c 509 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 510}
511
f2b4b7dd
JR		 512void kvm_enable_efer_bits(u64 mask)
513{
514 efer_reserved_bits &= ~mask;
515}
516EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
517
518
15c4a640
CO		 519/*
520 * Writes msr value into into the appropriate "register".
521 * Returns 0 on success, non-0 otherwise.
522 * Assumes vcpu_load() was already called.
523 */
524int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
525{
526 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
527}
528
313a3dc7
CO		 529/*
530 * Adapt set_msr() to msr_io()'s calling convention
531 */
532static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
533{
534 return kvm_set_msr(vcpu, index, *data);
535}
536
18068523
GOC		 537static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
538{
539 static int version;
50d0a0f9
GH		 540 struct pvclock_wall_clock wc;
541 struct timespec now, sys, boot;
18068523
GOC		 542
543 if (!wall_clock)
544 return;
545
546 version++;
547
18068523
GOC		 548 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
549
50d0a0f9
GH		 550 /*
551 * The guest calculates current wall clock time by adding
552 * system time (updated by kvm_write_guest_time below) to the
553 * wall clock specified here. guest system time equals host
554 * system time for us, thus we must fill in host boot time here.
555 */
556 now = current_kernel_time();
557 ktime_get_ts(&sys);
558 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
559
560 wc.sec = boot.tv_sec;
561 wc.nsec = boot.tv_nsec;
562 wc.version = version;
18068523
GOC		 563
564 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
565
566 version++;
567 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 568}
569
50d0a0f9
GH		 570static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
571{
572 uint32_t quotient, remainder;
573
574 /* Don't try to replace with do_div(), this one calculates
575 * "(dividend << 32) / divisor" */
576 __asm__ ( "divl %4"
577 : "=a" (quotient), "=d" (remainder)
578 : "0" (0), "1" (dividend), "r" (divisor) );
579 return quotient;
580}
581
582static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
583{
584 uint64_t nsecs = 1000000000LL;
585 int32_t shift = 0;
586 uint64_t tps64;
587 uint32_t tps32;
588
589 tps64 = tsc_khz * 1000LL;
590 while (tps64 > nsecs*2) {
591 tps64 >>= 1;
592 shift--;
593 }
594
595 tps32 = (uint32_t)tps64;
596 while (tps32 <= (uint32_t)nsecs) {
597 tps32 <<= 1;
598 shift++;
599 }
600
601 hv_clock->tsc_shift = shift;
602 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
603
604 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 605 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 606 hv_clock->tsc_to_system_mul);
607}
608
18068523
GOC		 609static void kvm_write_guest_time(struct kvm_vcpu *v)
610{
611 struct timespec ts;
612 unsigned long flags;
613 struct kvm_vcpu_arch *vcpu = &v->arch;
614 void *shared_kaddr;
615
616 if ((!vcpu->time_page))
617 return;
618
50d0a0f9
GH		 619 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
620 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
621 vcpu->hv_clock_tsc_khz = tsc_khz;
622 }
623
18068523
GOC		 624 /* Keep irq disabled to prevent changes to the clock */
625 local_irq_save(flags);
626 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
627 &vcpu->hv_clock.tsc_timestamp);
628 ktime_get_ts(&ts);
629 local_irq_restore(flags);
630
631 /* With all the info we got, fill in the values */
632
633 vcpu->hv_clock.system_time = ts.tv_nsec +
634 (NSEC_PER_SEC * (u64)ts.tv_sec);
635 /*
636 * The interface expects us to write an even number signaling that the
637 * update is finished. Since the guest won't see the intermediate
50d0a0f9 638 * state, we just increase by 2 at the end.
18068523 639 */
50d0a0f9 640 vcpu->hv_clock.version += 2;
18068523
GOC		 641
642 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
643
644 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 645 sizeof(vcpu->hv_clock));
18068523
GOC		 646
647 kunmap_atomic(shared_kaddr, KM_USER0);
648
649 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
650}
651
9ba075a6
AK		 652static bool msr_mtrr_valid(unsigned msr)
653{
654 switch (msr) {
655 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
656 case MSR_MTRRfix64K_00000:
657 case MSR_MTRRfix16K_80000:
658 case MSR_MTRRfix16K_A0000:
659 case MSR_MTRRfix4K_C0000:
660 case MSR_MTRRfix4K_C8000:
661 case MSR_MTRRfix4K_D0000:
662 case MSR_MTRRfix4K_D8000:
663 case MSR_MTRRfix4K_E0000:
664 case MSR_MTRRfix4K_E8000:
665 case MSR_MTRRfix4K_F0000:
666 case MSR_MTRRfix4K_F8000:
667 case MSR_MTRRdefType:
668 case MSR_IA32_CR_PAT:
669 return true;
670 case 0x2f8:
671 return true;
672 }
673 return false;
674}
675
676static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
677{
0bed3b56
SY		 678 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
679
9ba075a6
AK		 680 if (!msr_mtrr_valid(msr))
681 return 1;
682
0bed3b56
SY		 683 if (msr == MSR_MTRRdefType) {
684 vcpu->arch.mtrr_state.def_type = data;
685 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
686 } else if (msr == MSR_MTRRfix64K_00000)
687 p[0] = data;
688 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
689 p[1 + msr - MSR_MTRRfix16K_80000] = data;
690 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
691 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
692 else if (msr == MSR_IA32_CR_PAT)
693 vcpu->arch.pat = data;
694 else { /* Variable MTRRs */
695 int idx, is_mtrr_mask;
696 u64 *pt;
697
698 idx = (msr - 0x200) / 2;
699 is_mtrr_mask = msr - 0x200 - 2 * idx;
700 if (!is_mtrr_mask)
701 pt =
702 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
703 else
704 pt =
705 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
706 *pt = data;
707 }
708
709 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 710 return 0;
711}
15c4a640
CO		 712
713int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
714{
715 switch (msr) {
15c4a640
CO		 716 case MSR_EFER:
717 set_efer(vcpu, data);
718 break;
15c4a640
CO		 719 case MSR_IA32_MC0_STATUS:
720 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 721 __func__, data);
15c4a640
CO		 722 break;
723 case MSR_IA32_MCG_STATUS:
724 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 725 __func__, data);
15c4a640 726 break;
c7ac679c
JR		 727 case MSR_IA32_MCG_CTL:
728 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 729 __func__, data);
c7ac679c 730 break;
b5e2fec0
AG		 731 case MSR_IA32_DEBUGCTLMSR:
732 if (!data) {
733 /* We support the non-activated case already */
734 break;
735 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
736 /* Values other than LBR and BTF are vendor-specific,
737 thus reserved and should throw a #GP */
738 return 1;
739 }
740 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
741 __func__, data);
742 break;
15c4a640
CO		 743 case MSR_IA32_UCODE_REV:
744 case MSR_IA32_UCODE_WRITE:
61a6bd67 745 case MSR_VM_HSAVE_PA:
15c4a640 746 break;
9ba075a6
AK		 747 case 0x200 ... 0x2ff:
748 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 749 case MSR_IA32_APICBASE:
750 kvm_set_apic_base(vcpu, data);
751 break;
752 case MSR_IA32_MISC_ENABLE:
ad312c7c 753 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 754 break;
18068523
GOC		 755 case MSR_KVM_WALL_CLOCK:
756 vcpu->kvm->arch.wall_clock = data;
757 kvm_write_wall_clock(vcpu->kvm, data);
758 break;
759 case MSR_KVM_SYSTEM_TIME: {
760 if (vcpu->arch.time_page) {
761 kvm_release_page_dirty(vcpu->arch.time_page);
762 vcpu->arch.time_page = NULL;
763 }
764
765 vcpu->arch.time = data;
766
767 /* we verify if the enable bit is set... */
768 if (!(data & 1))
769 break;
770
771 /* ...but clean it before doing the actual write */
772 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
773
18068523
GOC		 774 vcpu->arch.time_page =
775 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 776
777 if (is_error_page(vcpu->arch.time_page)) {
778 kvm_release_page_clean(vcpu->arch.time_page);
779 vcpu->arch.time_page = NULL;
780 }
781
782 kvm_write_guest_time(vcpu);
783 break;
784 }
15c4a640 785 default:
565f1fbd 786 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 787 return 1;
788 }
789 return 0;
790}
791EXPORT_SYMBOL_GPL(kvm_set_msr_common);
792
793
794/*
795 * Reads an msr value (of 'msr_index') into 'pdata'.
796 * Returns 0 on success, non-0 otherwise.
797 * Assumes vcpu_load() was already called.
798 */
799int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
800{
801 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
802}
803
9ba075a6
AK		 804static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
805{
0bed3b56
SY		 806 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
807
9ba075a6
AK		 808 if (!msr_mtrr_valid(msr))
809 return 1;
810
0bed3b56
SY		 811 if (msr == MSR_MTRRdefType)
812 *pdata = vcpu->arch.mtrr_state.def_type +
813 (vcpu->arch.mtrr_state.enabled << 10);
814 else if (msr == MSR_MTRRfix64K_00000)
815 *pdata = p[0];
816 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
817 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
818 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
819 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
820 else if (msr == MSR_IA32_CR_PAT)
821 *pdata = vcpu->arch.pat;
822 else { /* Variable MTRRs */
823 int idx, is_mtrr_mask;
824 u64 *pt;
825
826 idx = (msr - 0x200) / 2;
827 is_mtrr_mask = msr - 0x200 - 2 * idx;
828 if (!is_mtrr_mask)
829 pt =
830 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
831 else
832 pt =
833 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
834 *pdata = *pt;
835 }
836
9ba075a6
AK		 837 return 0;
838}
839
15c4a640
CO		 840int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
841{
842 u64 data;
843
844 switch (msr) {
845 case 0xc0010010: /* SYSCFG */
846 case 0xc0010015: /* HWCR */
847 case MSR_IA32_PLATFORM_ID:
848 case MSR_IA32_P5_MC_ADDR:
849 case MSR_IA32_P5_MC_TYPE:
850 case MSR_IA32_MC0_CTL:
851 case MSR_IA32_MCG_STATUS:
852 case MSR_IA32_MCG_CAP:
c7ac679c 853 case MSR_IA32_MCG_CTL:
15c4a640
CO		 854 case MSR_IA32_MC0_MISC:
855 case MSR_IA32_MC0_MISC+4:
856 case MSR_IA32_MC0_MISC+8:
857 case MSR_IA32_MC0_MISC+12:
858 case MSR_IA32_MC0_MISC+16:
a89c1ad2 859 case MSR_IA32_MC0_MISC+20:
15c4a640 860 case MSR_IA32_UCODE_REV:
15c4a640 861 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 862 case MSR_IA32_DEBUGCTLMSR:
863 case MSR_IA32_LASTBRANCHFROMIP:
864 case MSR_IA32_LASTBRANCHTOIP:
865 case MSR_IA32_LASTINTFROMIP:
866 case MSR_IA32_LASTINTTOIP:
61a6bd67 867 case MSR_VM_HSAVE_PA:
15c4a640
CO		 868 data = 0;
869 break;
9ba075a6
AK		 870 case MSR_MTRRcap:
871 data = 0x500 | KVM_NR_VAR_MTRR;
872 break;
873 case 0x200 ... 0x2ff:
874 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 875 case 0xcd: /* fsb frequency */
876 data = 3;
877 break;
878 case MSR_IA32_APICBASE:
879 data = kvm_get_apic_base(vcpu);
880 break;
881 case MSR_IA32_MISC_ENABLE:
ad312c7c 882 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 883 break;
847f0ad8
AG		 884 case MSR_IA32_PERF_STATUS:
885 /* TSC increment by tick */
886 data = 1000ULL;
887 /* CPU multiplier */
888 data |= (((uint64_t)4ULL) << 40);
889 break;
15c4a640 890 case MSR_EFER:
ad312c7c 891 data = vcpu->arch.shadow_efer;
15c4a640 892 break;
18068523
GOC		 893 case MSR_KVM_WALL_CLOCK:
894 data = vcpu->kvm->arch.wall_clock;
895 break;
896 case MSR_KVM_SYSTEM_TIME:
897 data = vcpu->arch.time;
898 break;
15c4a640
CO		 899 default:
900 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
901 return 1;
902 }
903 *pdata = data;
904 return 0;
905}
906EXPORT_SYMBOL_GPL(kvm_get_msr_common);
907
313a3dc7
CO		 908/*
909 * Read or write a bunch of msrs. All parameters are kernel addresses.
910 *
911 * @return number of msrs set successfully.
912 */
913static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
914 struct kvm_msr_entry *entries,
915 int (*do_msr)(struct kvm_vcpu *vcpu,
916 unsigned index, u64 *data))
917{
918 int i;
919
920 vcpu_load(vcpu);
921
3200f405 922 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 923 for (i = 0; i < msrs->nmsrs; ++i)
924 if (do_msr(vcpu, entries[i].index, &entries[i].data))
925 break;
3200f405 926 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 927
928 vcpu_put(vcpu);
929
930 return i;
931}
932
933/*
934 * Read or write a bunch of msrs. Parameters are user addresses.
935 *
936 * @return number of msrs set successfully.
937 */
938static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
939 int (*do_msr)(struct kvm_vcpu *vcpu,
940 unsigned index, u64 *data),
941 int writeback)
942{
943 struct kvm_msrs msrs;
944 struct kvm_msr_entry *entries;
945 int r, n;
946 unsigned size;
947
948 r = -EFAULT;
949 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
950 goto out;
951
952 r = -E2BIG;
953 if (msrs.nmsrs >= MAX_IO_MSRS)
954 goto out;
955
956 r = -ENOMEM;
957 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
958 entries = vmalloc(size);
959 if (!entries)
960 goto out;
961
962 r = -EFAULT;
963 if (copy_from_user(entries, user_msrs->entries, size))
964 goto out_free;
965
966 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
967 if (r < 0)
968 goto out_free;
969
970 r = -EFAULT;
971 if (writeback && copy_to_user(user_msrs->entries, entries, size))
972 goto out_free;
973
974 r = n;
975
976out_free:
977 vfree(entries);
978out:
979 return r;
980}
981
018d00d2
ZX		 982int kvm_dev_ioctl_check_extension(long ext)
983{
984 int r;
985
986 switch (ext) {
987 case KVM_CAP_IRQCHIP:
988 case KVM_CAP_HLT:
989 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 990 case KVM_CAP_SET_TSS_ADDR:
07716717 991 case KVM_CAP_EXT_CPUID:
7837699f 992 case KVM_CAP_PIT:
a28e4f5a 993 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 994 case KVM_CAP_MP_STATE:
ed848624 995 case KVM_CAP_SYNC_MMU:
52d939a0 996 case KVM_CAP_REINJECT_CONTROL:
018d00d2
ZX		 997 r = 1;
998 break;
542472b5
LV		 999 case KVM_CAP_COALESCED_MMIO:
1000 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1001 break;
774ead3a
AK		 1002 case KVM_CAP_VAPIC:
1003 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1004 break;
f725230a
AK		 1005 case KVM_CAP_NR_VCPUS:
1006 r = KVM_MAX_VCPUS;
1007 break;
a988b910
AK		 1008 case KVM_CAP_NR_MEMSLOTS:
1009 r = KVM_MEMORY_SLOTS;
1010 break;
2f333bcb
MT		 1011 case KVM_CAP_PV_MMU:
1012 r = !tdp_enabled;
1013 break;
62c476c7 1014 case KVM_CAP_IOMMU:
19de40a8 1015 r = iommu_found();
62c476c7 1016 break;
abe6655d
MT		 1017 case KVM_CAP_CLOCKSOURCE:
1018 r = boot_cpu_has(X86_FEATURE_CONSTANT_TSC);
1019 break;
018d00d2
ZX		 1020 default:
1021 r = 0;
1022 break;
1023 }
1024 return r;
1025
1026}
1027
043405e1
CO		 1028long kvm_arch_dev_ioctl(struct file *filp,
1029 unsigned int ioctl, unsigned long arg)
1030{
1031 void __user *argp = (void __user *)arg;
1032 long r;
1033
1034 switch (ioctl) {
1035 case KVM_GET_MSR_INDEX_LIST: {
1036 struct kvm_msr_list __user *user_msr_list = argp;
1037 struct kvm_msr_list msr_list;
1038 unsigned n;
1039
1040 r = -EFAULT;
1041 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1042 goto out;
1043 n = msr_list.nmsrs;
1044 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1045 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1046 goto out;
1047 r = -E2BIG;
1048 if (n < num_msrs_to_save)
1049 goto out;
1050 r = -EFAULT;
1051 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1052 num_msrs_to_save * sizeof(u32)))
1053 goto out;
1054 if (copy_to_user(user_msr_list->indices
1055 + num_msrs_to_save * sizeof(u32),
1056 &emulated_msrs,
1057 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1058 goto out;
1059 r = 0;
1060 break;
1061 }
674eea0f
AK		 1062 case KVM_GET_SUPPORTED_CPUID: {
1063 struct kvm_cpuid2 __user *cpuid_arg = argp;
1064 struct kvm_cpuid2 cpuid;
1065
1066 r = -EFAULT;
1067 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1068 goto out;
1069 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1070 cpuid_arg->entries);
1071 if (r)
1072 goto out;
1073
1074 r = -EFAULT;
1075 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1076 goto out;
1077 r = 0;
1078 break;
1079 }
043405e1
CO		 1080 default:
1081 r = -EINVAL;
1082 }
1083out:
1084 return r;
1085}
1086
313a3dc7
CO		 1087void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1088{
1089 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1090 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1091}
1092
1093void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1094{
1095 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1096 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1097}
1098
07716717 1099static int is_efer_nx(void)
313a3dc7
CO		 1100{
1101 u64 efer;
313a3dc7
CO		 1102
1103 rdmsrl(MSR_EFER, efer);
07716717
DK		 1104 return efer & EFER_NX;
1105}
1106
1107static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1108{
1109 int i;
1110 struct kvm_cpuid_entry2 *e, *entry;
1111
313a3dc7 1112 entry = NULL;
ad312c7c
ZX		 1113 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1114 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1115 if (e->function == 0x80000001) {
1116 entry = e;
1117 break;
1118 }
1119 }
07716717 1120 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1121 entry->edx &= ~(1 << 20);
1122 printk(KERN_INFO "kvm: guest NX capability removed\n");
1123 }
1124}
1125
07716717 1126/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1127static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1128 struct kvm_cpuid *cpuid,
1129 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1130{
1131 int r, i;
1132 struct kvm_cpuid_entry *cpuid_entries;
1133
1134 r = -E2BIG;
1135 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1136 goto out;
1137 r = -ENOMEM;
1138 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1139 if (!cpuid_entries)
1140 goto out;
1141 r = -EFAULT;
1142 if (copy_from_user(cpuid_entries, entries,
1143 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1144 goto out_free;
1145 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1146 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1147 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1148 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1149 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1150 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1151 vcpu->arch.cpuid_entries[i].index = 0;
1152 vcpu->arch.cpuid_entries[i].flags = 0;
1153 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1154 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1155 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1156 }
1157 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1158 cpuid_fix_nx_cap(vcpu);
1159 r = 0;
1160
1161out_free:
1162 vfree(cpuid_entries);
1163out:
1164 return r;
1165}
1166
1167static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1168 struct kvm_cpuid2 *cpuid,
1169 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1170{
1171 int r;
1172
1173 r = -E2BIG;
1174 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1175 goto out;
1176 r = -EFAULT;
ad312c7c 1177 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1178 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1179 goto out;
ad312c7c 1180 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1181 return 0;
1182
1183out:
1184 return r;
1185}
1186
07716717
DK		 1187static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1188 struct kvm_cpuid2 *cpuid,
1189 struct kvm_cpuid_entry2 __user *entries)
1190{
1191 int r;
1192
1193 r = -E2BIG;
ad312c7c 1194 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1195 goto out;
1196 r = -EFAULT;
ad312c7c
ZX		 1197 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1198 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1199 goto out;
1200 return 0;
1201
1202out:
ad312c7c 1203 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1204 return r;
1205}
1206
07716717
DK		 1207static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1208 u32 index)
1209{
1210 entry->function = function;
1211 entry->index = index;
1212 cpuid_count(entry->function, entry->index,
1213 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1214 entry->flags = 0;
1215}
1216
1217static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1218 u32 index, int *nent, int maxnent)
1219{
1220 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1221 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1222 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1223 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1224 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1225 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1226 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1227 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1228 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1229 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1230 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1231 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1232 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1233 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1234 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1235 bit(X86_FEATURE_PGE) |
1236 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1237 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1238 bit(X86_FEATURE_SYSCALL) |
1239 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1240#ifdef CONFIG_X86_64
1241 bit(X86_FEATURE_LM) |
1242#endif
1243 bit(X86_FEATURE_MMXEXT) |
1244 bit(X86_FEATURE_3DNOWEXT) |
1245 bit(X86_FEATURE_3DNOW);
1246 const u32 kvm_supported_word3_x86_features =
1247 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1248 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1249 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1250 bit(X86_FEATURE_SVM);
07716717
DK		 1251
1252 /* all func 2 cpuid_count() should be called on the same cpu */
1253 get_cpu();
1254 do_cpuid_1_ent(entry, function, index);
1255 ++*nent;
1256
1257 switch (function) {
1258 case 0:
1259 entry->eax = min(entry->eax, (u32)0xb);
1260 break;
1261 case 1:
1262 entry->edx &= kvm_supported_word0_x86_features;
1263 entry->ecx &= kvm_supported_word3_x86_features;
1264 break;
1265 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1266 * may return different values. This forces us to get_cpu() before
1267 * issuing the first command, and also to emulate this annoying behavior
1268 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1269 case 2: {
1270 int t, times = entry->eax & 0xff;
1271
1272 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1273 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1274 for (t = 1; t < times && *nent < maxnent; ++t) {
1275 do_cpuid_1_ent(&entry[t], function, 0);
1276 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1277 ++*nent;
1278 }
1279 break;
1280 }
1281 /* function 4 and 0xb have additional index. */
1282 case 4: {
14af3f3c 1283 int i, cache_type;
07716717
DK		 1284
1285 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1286 /* read more entries until cache_type is zero */
14af3f3c
HH		 1287 for (i = 1; *nent < maxnent; ++i) {
1288 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1289 if (!cache_type)
1290 break;
14af3f3c
HH		 1291 do_cpuid_1_ent(&entry[i], function, i);
1292 entry[i].flags |=
07716717
DK		 1293 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1294 ++*nent;
1295 }
1296 break;
1297 }
1298 case 0xb: {
14af3f3c 1299 int i, level_type;
07716717
DK		 1300
1301 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1302 /* read more entries until level_type is zero */
14af3f3c 1303 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1304 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1305 if (!level_type)
1306 break;
14af3f3c
HH		 1307 do_cpuid_1_ent(&entry[i], function, i);
1308 entry[i].flags |=
07716717
DK		 1309 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1310 ++*nent;
1311 }
1312 break;
1313 }
1314 case 0x80000000:
1315 entry->eax = min(entry->eax, 0x8000001a);
1316 break;
1317 case 0x80000001:
1318 entry->edx &= kvm_supported_word1_x86_features;
1319 entry->ecx &= kvm_supported_word6_x86_features;
1320 break;
1321 }
1322 put_cpu();
1323}
1324
674eea0f 1325static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1326 struct kvm_cpuid_entry2 __user *entries)
1327{
1328 struct kvm_cpuid_entry2 *cpuid_entries;
1329 int limit, nent = 0, r = -E2BIG;
1330 u32 func;
1331
1332 if (cpuid->nent < 1)
1333 goto out;
1334 r = -ENOMEM;
1335 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1336 if (!cpuid_entries)
1337 goto out;
1338
1339 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1340 limit = cpuid_entries[0].eax;
1341 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1342 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1343 &nent, cpuid->nent);
1344 r = -E2BIG;
1345 if (nent >= cpuid->nent)
1346 goto out_free;
1347
1348 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1349 limit = cpuid_entries[nent - 1].eax;
1350 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1351 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1352 &nent, cpuid->nent);
1353 r = -EFAULT;
1354 if (copy_to_user(entries, cpuid_entries,
1355 nent * sizeof(struct kvm_cpuid_entry2)))
1356 goto out_free;
1357 cpuid->nent = nent;
1358 r = 0;
1359
1360out_free:
1361 vfree(cpuid_entries);
1362out:
1363 return r;
1364}
1365
313a3dc7
CO		 1366static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1367 struct kvm_lapic_state *s)
1368{
1369 vcpu_load(vcpu);
ad312c7c 1370 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1371 vcpu_put(vcpu);
1372
1373 return 0;
1374}
1375
1376static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1377 struct kvm_lapic_state *s)
1378{
1379 vcpu_load(vcpu);
ad312c7c 1380 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1381 kvm_apic_post_state_restore(vcpu);
1382 vcpu_put(vcpu);
1383
1384 return 0;
1385}
1386
f77bc6a4
ZX		 1387static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1388 struct kvm_interrupt *irq)
1389{
1390 if (irq->irq < 0 || irq->irq >= 256)
1391 return -EINVAL;
1392 if (irqchip_in_kernel(vcpu->kvm))
1393 return -ENXIO;
1394 vcpu_load(vcpu);
1395
ad312c7c
ZX		 1396 set_bit(irq->irq, vcpu->arch.irq_pending);
1397 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1398
1399 vcpu_put(vcpu);
1400
1401 return 0;
1402}
1403
c4abb7c9
JK		 1404static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1405{
1406 vcpu_load(vcpu);
1407 kvm_inject_nmi(vcpu);
1408 vcpu_put(vcpu);
1409
1410 return 0;
1411}
1412
b209749f
AK		 1413static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1414 struct kvm_tpr_access_ctl *tac)
1415{
1416 if (tac->flags)
1417 return -EINVAL;
1418 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1419 return 0;
1420}
1421
313a3dc7
CO		 1422long kvm_arch_vcpu_ioctl(struct file *filp,
1423 unsigned int ioctl, unsigned long arg)
1424{
1425 struct kvm_vcpu *vcpu = filp->private_data;
1426 void __user *argp = (void __user *)arg;
1427 int r;
b772ff36 1428 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1429
1430 switch (ioctl) {
1431 case KVM_GET_LAPIC: {
b772ff36 1432 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1433
b772ff36
DH		 1434 r = -ENOMEM;
1435 if (!lapic)
1436 goto out;
1437 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1438 if (r)
1439 goto out;
1440 r = -EFAULT;
b772ff36 1441 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1442 goto out;
1443 r = 0;
1444 break;
1445 }
1446 case KVM_SET_LAPIC: {
b772ff36
DH		 1447 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1448 r = -ENOMEM;
1449 if (!lapic)
1450 goto out;
313a3dc7 1451 r = -EFAULT;
b772ff36 1452 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1453 goto out;
b772ff36 1454 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1455 if (r)
1456 goto out;
1457 r = 0;
1458 break;
1459 }
f77bc6a4
ZX		 1460 case KVM_INTERRUPT: {
1461 struct kvm_interrupt irq;
1462
1463 r = -EFAULT;
1464 if (copy_from_user(&irq, argp, sizeof irq))
1465 goto out;
1466 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1467 if (r)
1468 goto out;
1469 r = 0;
1470 break;
1471 }
c4abb7c9
JK		 1472 case KVM_NMI: {
1473 r = kvm_vcpu_ioctl_nmi(vcpu);
1474 if (r)
1475 goto out;
1476 r = 0;
1477 break;
1478 }
313a3dc7
CO		 1479 case KVM_SET_CPUID: {
1480 struct kvm_cpuid __user *cpuid_arg = argp;
1481 struct kvm_cpuid cpuid;
1482
1483 r = -EFAULT;
1484 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1485 goto out;
1486 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1487 if (r)
1488 goto out;
1489 break;
1490 }
07716717
DK		 1491 case KVM_SET_CPUID2: {
1492 struct kvm_cpuid2 __user *cpuid_arg = argp;
1493 struct kvm_cpuid2 cpuid;
1494
1495 r = -EFAULT;
1496 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1497 goto out;
1498 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1499 cpuid_arg->entries);
1500 if (r)
1501 goto out;
1502 break;
1503 }
1504 case KVM_GET_CPUID2: {
1505 struct kvm_cpuid2 __user *cpuid_arg = argp;
1506 struct kvm_cpuid2 cpuid;
1507
1508 r = -EFAULT;
1509 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1510 goto out;
1511 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1512 cpuid_arg->entries);
1513 if (r)
1514 goto out;
1515 r = -EFAULT;
1516 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1517 goto out;
1518 r = 0;
1519 break;
1520 }
313a3dc7
CO		 1521 case KVM_GET_MSRS:
1522 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1523 break;
1524 case KVM_SET_MSRS:
1525 r = msr_io(vcpu, argp, do_set_msr, 0);
1526 break;
b209749f
AK		 1527 case KVM_TPR_ACCESS_REPORTING: {
1528 struct kvm_tpr_access_ctl tac;
1529
1530 r = -EFAULT;
1531 if (copy_from_user(&tac, argp, sizeof tac))
1532 goto out;
1533 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1534 if (r)
1535 goto out;
1536 r = -EFAULT;
1537 if (copy_to_user(argp, &tac, sizeof tac))
1538 goto out;
1539 r = 0;
1540 break;
1541 };
b93463aa
AK		 1542 case KVM_SET_VAPIC_ADDR: {
1543 struct kvm_vapic_addr va;
1544
1545 r = -EINVAL;
1546 if (!irqchip_in_kernel(vcpu->kvm))
1547 goto out;
1548 r = -EFAULT;
1549 if (copy_from_user(&va, argp, sizeof va))
1550 goto out;
1551 r = 0;
1552 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1553 break;
1554 }
313a3dc7
CO		 1555 default:
1556 r = -EINVAL;
1557 }
1558out:
b772ff36
DH		 1559 if (lapic)
1560 kfree(lapic);
313a3dc7
CO		 1561 return r;
1562}
1563
1fe779f8
CO		 1564static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1565{
1566 int ret;
1567
1568 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1569 return -1;
1570 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1571 return ret;
1572}
1573
1574static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1575 u32 kvm_nr_mmu_pages)
1576{
1577 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1578 return -EINVAL;
1579
72dc67a6 1580 down_write(&kvm->slots_lock);
1fe779f8
CO		 1581
1582 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1583 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1584
72dc67a6 1585 up_write(&kvm->slots_lock);
1fe779f8
CO		 1586 return 0;
1587}
1588
1589static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1590{
f05e70ac 1591 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1592}
1593
e9f85cde
ZX		 1594gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1595{
1596 int i;
1597 struct kvm_mem_alias *alias;
1598
d69fb81f
ZX		 1599 for (i = 0; i < kvm->arch.naliases; ++i) {
1600 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1601 if (gfn >= alias->base_gfn
1602 && gfn < alias->base_gfn + alias->npages)
1603 return alias->target_gfn + gfn - alias->base_gfn;
1604 }
1605 return gfn;
1606}
1607
1fe779f8
CO		 1608/*
1609 * Set a new alias region. Aliases map a portion of physical memory into
1610 * another portion. This is useful for memory windows, for example the PC
1611 * VGA region.
1612 */
1613static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1614 struct kvm_memory_alias *alias)
1615{
1616 int r, n;
1617 struct kvm_mem_alias *p;
1618
1619 r = -EINVAL;
1620 /* General sanity checks */
1621 if (alias->memory_size & (PAGE_SIZE - 1))
1622 goto out;
1623 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1624 goto out;
1625 if (alias->slot >= KVM_ALIAS_SLOTS)
1626 goto out;
1627 if (alias->guest_phys_addr + alias->memory_size
1628 < alias->guest_phys_addr)
1629 goto out;
1630 if (alias->target_phys_addr + alias->memory_size
1631 < alias->target_phys_addr)
1632 goto out;
1633
72dc67a6 1634 down_write(&kvm->slots_lock);
a1708ce8 1635 spin_lock(&kvm->mmu_lock);
1fe779f8 1636
d69fb81f 1637 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1638 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1639 p->npages = alias->memory_size >> PAGE_SHIFT;
1640 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1641
1642 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1643 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1644 break;
d69fb81f 1645 kvm->arch.naliases = n;
1fe779f8 1646
a1708ce8 1647 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1648 kvm_mmu_zap_all(kvm);
1649
72dc67a6 1650 up_write(&kvm->slots_lock);
1fe779f8
CO		 1651
1652 return 0;
1653
1654out:
1655 return r;
1656}
1657
1658static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1659{
1660 int r;
1661
1662 r = 0;
1663 switch (chip->chip_id) {
1664 case KVM_IRQCHIP_PIC_MASTER:
1665 memcpy(&chip->chip.pic,
1666 &pic_irqchip(kvm)->pics[0],
1667 sizeof(struct kvm_pic_state));
1668 break;
1669 case KVM_IRQCHIP_PIC_SLAVE:
1670 memcpy(&chip->chip.pic,
1671 &pic_irqchip(kvm)->pics[1],
1672 sizeof(struct kvm_pic_state));
1673 break;
1674 case KVM_IRQCHIP_IOAPIC:
1675 memcpy(&chip->chip.ioapic,
1676 ioapic_irqchip(kvm),
1677 sizeof(struct kvm_ioapic_state));
1678 break;
1679 default:
1680 r = -EINVAL;
1681 break;
1682 }
1683 return r;
1684}
1685
1686static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1687{
1688 int r;
1689
1690 r = 0;
1691 switch (chip->chip_id) {
1692 case KVM_IRQCHIP_PIC_MASTER:
1693 memcpy(&pic_irqchip(kvm)->pics[0],
1694 &chip->chip.pic,
1695 sizeof(struct kvm_pic_state));
1696 break;
1697 case KVM_IRQCHIP_PIC_SLAVE:
1698 memcpy(&pic_irqchip(kvm)->pics[1],
1699 &chip->chip.pic,
1700 sizeof(struct kvm_pic_state));
1701 break;
1702 case KVM_IRQCHIP_IOAPIC:
1703 memcpy(ioapic_irqchip(kvm),
1704 &chip->chip.ioapic,
1705 sizeof(struct kvm_ioapic_state));
1706 break;
1707 default:
1708 r = -EINVAL;
1709 break;
1710 }
1711 kvm_pic_update_irq(pic_irqchip(kvm));
1712 return r;
1713}
1714
e0f63cb9
SY		 1715static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1716{
1717 int r = 0;
1718
1719 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1720 return r;
1721}
1722
1723static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1724{
1725 int r = 0;
1726
1727 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1728 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1729 return r;
1730}
1731
52d939a0
MT		 1732static int kvm_vm_ioctl_reinject(struct kvm *kvm,
1733 struct kvm_reinject_control *control)
1734{
1735 if (!kvm->arch.vpit)
1736 return -ENXIO;
1737 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
1738 return 0;
1739}
1740
5bb064dc
ZX		 1741/*
1742 * Get (and clear) the dirty memory log for a memory slot.
1743 */
1744int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1745 struct kvm_dirty_log *log)
1746{
1747 int r;
1748 int n;
1749 struct kvm_memory_slot *memslot;
1750 int is_dirty = 0;
1751
72dc67a6 1752 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1753
1754 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1755 if (r)
1756 goto out;
1757
1758 /* If nothing is dirty, don't bother messing with page tables. */
1759 if (is_dirty) {
1760 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1761 kvm_flush_remote_tlbs(kvm);
1762 memslot = &kvm->memslots[log->slot];
1763 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1764 memset(memslot->dirty_bitmap, 0, n);
1765 }
1766 r = 0;
1767out:
72dc67a6 1768 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1769 return r;
1770}
1771
1fe779f8
CO		 1772long kvm_arch_vm_ioctl(struct file *filp,
1773 unsigned int ioctl, unsigned long arg)
1774{
1775 struct kvm *kvm = filp->private_data;
1776 void __user *argp = (void __user *)arg;
1777 int r = -EINVAL;
f0d66275
DH		 1778 /*
1779 * This union makes it completely explicit to gcc-3.x
1780 * that these two variables' stack usage should be
1781 * combined, not added together.
1782 */
1783 union {
1784 struct kvm_pit_state ps;
1785 struct kvm_memory_alias alias;
1786 } u;
1fe779f8
CO		 1787
1788 switch (ioctl) {
1789 case KVM_SET_TSS_ADDR:
1790 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1791 if (r < 0)
1792 goto out;
1793 break;
1794 case KVM_SET_MEMORY_REGION: {
1795 struct kvm_memory_region kvm_mem;
1796 struct kvm_userspace_memory_region kvm_userspace_mem;
1797
1798 r = -EFAULT;
1799 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1800 goto out;
1801 kvm_userspace_mem.slot = kvm_mem.slot;
1802 kvm_userspace_mem.flags = kvm_mem.flags;
1803 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1804 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1805 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1806 if (r)
1807 goto out;
1808 break;
1809 }
1810 case KVM_SET_NR_MMU_PAGES:
1811 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1812 if (r)
1813 goto out;
1814 break;
1815 case KVM_GET_NR_MMU_PAGES:
1816 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1817 break;
f0d66275 1818 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1819 r = -EFAULT;
f0d66275 1820 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1821 goto out;
f0d66275 1822 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1823 if (r)
1824 goto out;
1825 break;
1fe779f8
CO		 1826 case KVM_CREATE_IRQCHIP:
1827 r = -ENOMEM;
d7deeeb0
ZX		 1828 kvm->arch.vpic = kvm_create_pic(kvm);
1829 if (kvm->arch.vpic) {
1fe779f8
CO		 1830 r = kvm_ioapic_init(kvm);
1831 if (r) {
d7deeeb0
ZX		 1832 kfree(kvm->arch.vpic);
1833 kvm->arch.vpic = NULL;
1fe779f8
CO		 1834 goto out;
1835 }
1836 } else
1837 goto out;
1838 break;
7837699f
SY		 1839 case KVM_CREATE_PIT:
1840 r = -ENOMEM;
1841 kvm->arch.vpit = kvm_create_pit(kvm);
1842 if (kvm->arch.vpit)
1843 r = 0;
1844 break;
1fe779f8
CO		 1845 case KVM_IRQ_LINE: {
1846 struct kvm_irq_level irq_event;
1847
1848 r = -EFAULT;
1849 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1850 goto out;
1851 if (irqchip_in_kernel(kvm)) {
1852 mutex_lock(&kvm->lock);
5550af4d
SY		 1853 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1854 irq_event.irq, irq_event.level);
1fe779f8
CO		 1855 mutex_unlock(&kvm->lock);
1856 r = 0;
1857 }
1858 break;
1859 }
1860 case KVM_GET_IRQCHIP: {
1861 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1862 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1863
f0d66275
DH		 1864 r = -ENOMEM;
1865 if (!chip)
1fe779f8 1866 goto out;
f0d66275
DH		 1867 r = -EFAULT;
1868 if (copy_from_user(chip, argp, sizeof *chip))
1869 goto get_irqchip_out;
1fe779f8
CO		 1870 r = -ENXIO;
1871 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1872 goto get_irqchip_out;
1873 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1874 if (r)
f0d66275 1875 goto get_irqchip_out;
1fe779f8 1876 r = -EFAULT;
f0d66275
DH		 1877 if (copy_to_user(argp, chip, sizeof *chip))
1878 goto get_irqchip_out;
1fe779f8 1879 r = 0;
f0d66275
DH		 1880 get_irqchip_out:
1881 kfree(chip);
1882 if (r)
1883 goto out;
1fe779f8
CO		 1884 break;
1885 }
1886 case KVM_SET_IRQCHIP: {
1887 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1888 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1889
f0d66275
DH		 1890 r = -ENOMEM;
1891 if (!chip)
1fe779f8 1892 goto out;
f0d66275
DH		 1893 r = -EFAULT;
1894 if (copy_from_user(chip, argp, sizeof *chip))
1895 goto set_irqchip_out;
1fe779f8
CO		 1896 r = -ENXIO;
1897 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1898 goto set_irqchip_out;
1899 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1900 if (r)
f0d66275 1901 goto set_irqchip_out;
1fe779f8 1902 r = 0;
f0d66275
DH		 1903 set_irqchip_out:
1904 kfree(chip);
1905 if (r)
1906 goto out;
1fe779f8
CO		 1907 break;
1908 }
e0f63cb9 1909 case KVM_GET_PIT: {
e0f63cb9 1910 r = -EFAULT;
f0d66275 1911 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1912 goto out;
1913 r = -ENXIO;
1914 if (!kvm->arch.vpit)
1915 goto out;
f0d66275 1916 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1917 if (r)
1918 goto out;
1919 r = -EFAULT;
f0d66275 1920 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1921 goto out;
1922 r = 0;
1923 break;
1924 }
1925 case KVM_SET_PIT: {
e0f63cb9 1926 r = -EFAULT;
f0d66275 1927 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1928 goto out;
1929 r = -ENXIO;
1930 if (!kvm->arch.vpit)
1931 goto out;
f0d66275 1932 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1933 if (r)
1934 goto out;
1935 r = 0;
1936 break;
1937 }
52d939a0
MT		 1938 case KVM_REINJECT_CONTROL: {
1939 struct kvm_reinject_control control;
1940 r = -EFAULT;
1941 if (copy_from_user(&control, argp, sizeof(control)))
1942 goto out;
1943 r = kvm_vm_ioctl_reinject(kvm, &control);
1944 if (r)
1945 goto out;
1946 r = 0;
1947 break;
1948 }
1fe779f8
CO		 1949 default:
1950 ;
1951 }
1952out:
1953 return r;
1954}
1955
a16b043c 1956static void kvm_init_msr_list(void)
043405e1
CO		 1957{
1958 u32 dummy[2];
1959 unsigned i, j;
1960
1961 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1962 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1963 continue;
1964 if (j < i)
1965 msrs_to_save[j] = msrs_to_save[i];
1966 j++;
1967 }
1968 num_msrs_to_save = j;
1969}
1970
bbd9b64e
CO		 1971/*
1972 * Only apic need an MMIO device hook, so shortcut now..
1973 */
1974static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1975 gpa_t addr, int len,
1976 int is_write)
bbd9b64e
CO		 1977{
1978 struct kvm_io_device *dev;
1979
ad312c7c
ZX		 1980 if (vcpu->arch.apic) {
1981 dev = &vcpu->arch.apic->dev;
92760499 1982 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1983 return dev;
1984 }
1985 return NULL;
1986}
1987
1988
1989static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1990 gpa_t addr, int len,
1991 int is_write)
bbd9b64e
CO		 1992{
1993 struct kvm_io_device *dev;
1994
92760499 1995 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1996 if (dev == NULL)
92760499
LV		 1997 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1998 is_write);
bbd9b64e
CO		 1999 return dev;
2000}
2001
77c2002e
IE		 2002int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2003 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2004{
2005 void *data = val;
10589a46 2006 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2007
2008 while (bytes) {
ad312c7c 2009 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2010 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2011 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2012 int ret;
2013
10589a46
MT		 2014 if (gpa == UNMAPPED_GVA) {
2015 r = X86EMUL_PROPAGATE_FAULT;
2016 goto out;
2017 }
77c2002e 2018 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2019 if (ret < 0) {
2020 r = X86EMUL_UNHANDLEABLE;
2021 goto out;
2022 }
bbd9b64e 2023
77c2002e
IE		 2024 bytes -= toread;
2025 data += toread;
2026 addr += toread;
bbd9b64e 2027 }
10589a46 2028out:
10589a46 2029 return r;
bbd9b64e 2030}
77c2002e
IE		 2031
2032int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2033 struct kvm_vcpu *vcpu)
2034{
2035 void *data = val;
2036 int r = X86EMUL_CONTINUE;
2037
2038 while (bytes) {
2039 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2040 unsigned offset = addr & (PAGE_SIZE-1);
2041 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2042 int ret;
2043
2044 if (gpa == UNMAPPED_GVA) {
2045 r = X86EMUL_PROPAGATE_FAULT;
2046 goto out;
2047 }
2048 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2049 if (ret < 0) {
2050 r = X86EMUL_UNHANDLEABLE;
2051 goto out;
2052 }
2053
2054 bytes -= towrite;
2055 data += towrite;
2056 addr += towrite;
2057 }
2058out:
2059 return r;
2060}
2061
bbd9b64e 2062
bbd9b64e
CO		 2063static int emulator_read_emulated(unsigned long addr,
2064 void *val,
2065 unsigned int bytes,
2066 struct kvm_vcpu *vcpu)
2067{
2068 struct kvm_io_device *mmio_dev;
2069 gpa_t gpa;
2070
2071 if (vcpu->mmio_read_completed) {
2072 memcpy(val, vcpu->mmio_data, bytes);
2073 vcpu->mmio_read_completed = 0;
2074 return X86EMUL_CONTINUE;
2075 }
2076
ad312c7c 2077 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2078
2079 /* For APIC access vmexit */
2080 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2081 goto mmio;
2082
77c2002e
IE		 2083 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2084 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2085 return X86EMUL_CONTINUE;
2086 if (gpa == UNMAPPED_GVA)
2087 return X86EMUL_PROPAGATE_FAULT;
2088
2089mmio:
2090 /*
2091 * Is this MMIO handled locally?
2092 */
10589a46 2093 mutex_lock(&vcpu->kvm->lock);
92760499 2094 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2095 if (mmio_dev) {
2096 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2097 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2098 return X86EMUL_CONTINUE;
2099 }
10589a46 2100 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2101
2102 vcpu->mmio_needed = 1;
2103 vcpu->mmio_phys_addr = gpa;
2104 vcpu->mmio_size = bytes;
2105 vcpu->mmio_is_write = 0;
2106
2107 return X86EMUL_UNHANDLEABLE;
2108}
2109
3200f405 2110int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2111 const void *val, int bytes)
bbd9b64e
CO		 2112{
2113 int ret;
2114
2115 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2116 if (ret < 0)
bbd9b64e 2117 return 0;
ad218f85 2118 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2119 return 1;
2120}
2121
2122static int emulator_write_emulated_onepage(unsigned long addr,
2123 const void *val,
2124 unsigned int bytes,
2125 struct kvm_vcpu *vcpu)
2126{
2127 struct kvm_io_device *mmio_dev;
10589a46
MT		 2128 gpa_t gpa;
2129
10589a46 2130 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2131
2132 if (gpa == UNMAPPED_GVA) {
c3c91fee 2133 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2134 return X86EMUL_PROPAGATE_FAULT;
2135 }
2136
2137 /* For APIC access vmexit */
2138 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2139 goto mmio;
2140
2141 if (emulator_write_phys(vcpu, gpa, val, bytes))
2142 return X86EMUL_CONTINUE;
2143
2144mmio:
2145 /*
2146 * Is this MMIO handled locally?
2147 */
10589a46 2148 mutex_lock(&vcpu->kvm->lock);
92760499 2149 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2150 if (mmio_dev) {
2151 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2152 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2153 return X86EMUL_CONTINUE;
2154 }
10589a46 2155 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2156
2157 vcpu->mmio_needed = 1;
2158 vcpu->mmio_phys_addr = gpa;
2159 vcpu->mmio_size = bytes;
2160 vcpu->mmio_is_write = 1;
2161 memcpy(vcpu->mmio_data, val, bytes);
2162
2163 return X86EMUL_CONTINUE;
2164}
2165
2166int emulator_write_emulated(unsigned long addr,
2167 const void *val,
2168 unsigned int bytes,
2169 struct kvm_vcpu *vcpu)
2170{
2171 /* Crossing a page boundary? */
2172 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2173 int rc, now;
2174
2175 now = -addr & ~PAGE_MASK;
2176 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2177 if (rc != X86EMUL_CONTINUE)
2178 return rc;
2179 addr += now;
2180 val += now;
2181 bytes -= now;
2182 }
2183 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2184}
2185EXPORT_SYMBOL_GPL(emulator_write_emulated);
2186
2187static int emulator_cmpxchg_emulated(unsigned long addr,
2188 const void *old,
2189 const void *new,
2190 unsigned int bytes,
2191 struct kvm_vcpu *vcpu)
2192{
2193 static int reported;
2194
2195 if (!reported) {
2196 reported = 1;
2197 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2198 }
2bacc55c
MT		 2199#ifndef CONFIG_X86_64
2200 /* guests cmpxchg8b have to be emulated atomically */
2201 if (bytes == 8) {
10589a46 2202 gpa_t gpa;
2bacc55c 2203 struct page *page;
c0b49b0d 2204 char *kaddr;
2bacc55c
MT		 2205 u64 val;
2206
10589a46
MT		 2207 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2208
2bacc55c
MT		 2209 if (gpa == UNMAPPED_GVA ||
2210 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2211 goto emul_write;
2212
2213 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2214 goto emul_write;
2215
2216 val = *(u64 *)new;
72dc67a6 2217
2bacc55c 2218 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2219
c0b49b0d
AM		 2220 kaddr = kmap_atomic(page, KM_USER0);
2221 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2222 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2223 kvm_release_page_dirty(page);
2224 }
3200f405 2225emul_write:
2bacc55c
MT		 2226#endif
2227
bbd9b64e
CO		 2228 return emulator_write_emulated(addr, new, bytes, vcpu);
2229}
2230
2231static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2232{
2233 return kvm_x86_ops->get_segment_base(vcpu, seg);
2234}
2235
2236int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2237{
a7052897 2238 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2239 return X86EMUL_CONTINUE;
2240}
2241
2242int emulate_clts(struct kvm_vcpu *vcpu)
2243{
54e445ca 2244 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2245 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2246 return X86EMUL_CONTINUE;
2247}
2248
2249int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2250{
2251 struct kvm_vcpu *vcpu = ctxt->vcpu;
2252
2253 switch (dr) {
2254 case 0 ... 3:
2255 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2256 return X86EMUL_CONTINUE;
2257 default:
b8688d51 2258 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2259 return X86EMUL_UNHANDLEABLE;
2260 }
2261}
2262
2263int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2264{
2265 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2266 int exception;
2267
2268 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2269 if (exception) {
2270 /* FIXME: better handling */
2271 return X86EMUL_UNHANDLEABLE;
2272 }
2273 return X86EMUL_CONTINUE;
2274}
2275
2276void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2277{
bbd9b64e 2278 u8 opcodes[4];
5fdbf976 2279 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2280 unsigned long rip_linear;
2281
f76c710d 2282 if (!printk_ratelimit())
bbd9b64e
CO		 2283 return;
2284
25be4608
GC		 2285 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2286
77c2002e 2287 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2288
2289 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2290 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2291}
2292EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2293
14af3f3c 2294static struct x86_emulate_ops emulate_ops = {
77c2002e 2295 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2296 .read_emulated = emulator_read_emulated,
2297 .write_emulated = emulator_write_emulated,
2298 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2299};
2300
5fdbf976
MT		 2301static void cache_all_regs(struct kvm_vcpu *vcpu)
2302{
2303 kvm_register_read(vcpu, VCPU_REGS_RAX);
2304 kvm_register_read(vcpu, VCPU_REGS_RSP);
2305 kvm_register_read(vcpu, VCPU_REGS_RIP);
2306 vcpu->arch.regs_dirty = ~0;
2307}
2308
bbd9b64e
CO		 2309int emulate_instruction(struct kvm_vcpu *vcpu,
2310 struct kvm_run *run,
2311 unsigned long cr2,
2312 u16 error_code,
571008da 2313 int emulation_type)
bbd9b64e
CO		 2314{
2315 int r;
571008da 2316 struct decode_cache *c;
bbd9b64e 2317
26eef70c 2318 kvm_clear_exception_queue(vcpu);
ad312c7c 2319 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2320 /*
2321 * TODO: fix x86_emulate.c to use guest_read/write_register
2322 * instead of direct ->regs accesses, can save hundred cycles
2323 * on Intel for instructions that don't read/change RSP, for
2324 * for example.
2325 */
2326 cache_all_regs(vcpu);
bbd9b64e
CO		 2327
2328 vcpu->mmio_is_write = 0;
ad312c7c 2329 vcpu->arch.pio.string = 0;
bbd9b64e 2330
571008da 2331 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2332 int cs_db, cs_l;
2333 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2334
ad312c7c
ZX		 2335 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2336 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2337 vcpu->arch.emulate_ctxt.mode =
2338 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2339 ? X86EMUL_MODE_REAL : cs_l
2340 ? X86EMUL_MODE_PROT64 : cs_db
2341 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2342
ad312c7c 2343 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2344
2345 /* Reject the instructions other than VMCALL/VMMCALL when
2346 * try to emulate invalid opcode */
2347 c = &vcpu->arch.emulate_ctxt.decode;
2348 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2349 (!(c->twobyte && c->b == 0x01 &&
2350 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2351 c->modrm_mod == 3 && c->modrm_rm == 1)))
2352 return EMULATE_FAIL;
2353
f2b5756b 2354 ++vcpu->stat.insn_emulation;
bbd9b64e 2355 if (r) {
f2b5756b 2356 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2357 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2358 return EMULATE_DONE;
2359 return EMULATE_FAIL;
2360 }
2361 }
2362
ad312c7c 2363 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2364
ad312c7c 2365 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2366 return EMULATE_DO_MMIO;
2367
2368 if ((r || vcpu->mmio_is_write) && run) {
2369 run->exit_reason = KVM_EXIT_MMIO;
2370 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2371 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2372 run->mmio.len = vcpu->mmio_size;
2373 run->mmio.is_write = vcpu->mmio_is_write;
2374 }
2375
2376 if (r) {
2377 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2378 return EMULATE_DONE;
2379 if (!vcpu->mmio_needed) {
2380 kvm_report_emulation_failure(vcpu, "mmio");
2381 return EMULATE_FAIL;
2382 }
2383 return EMULATE_DO_MMIO;
2384 }
2385
ad312c7c 2386 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2387
2388 if (vcpu->mmio_is_write) {
2389 vcpu->mmio_needed = 0;
2390 return EMULATE_DO_MMIO;
2391 }
2392
2393 return EMULATE_DONE;
2394}
2395EXPORT_SYMBOL_GPL(emulate_instruction);
2396
de7d789a
CO		 2397static int pio_copy_data(struct kvm_vcpu *vcpu)
2398{
ad312c7c 2399 void *p = vcpu->arch.pio_data;
0f346074 2400 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2401 unsigned bytes;
0f346074 2402 int ret;
de7d789a 2403
ad312c7c
ZX		 2404 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2405 if (vcpu->arch.pio.in)
0f346074 2406 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2407 else
0f346074
IE		 2408 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2409 return ret;
de7d789a
CO		 2410}
2411
2412int complete_pio(struct kvm_vcpu *vcpu)
2413{
ad312c7c 2414 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2415 long delta;
2416 int r;
5fdbf976 2417 unsigned long val;
de7d789a
CO		 2418
2419 if (!io->string) {
5fdbf976
MT		 2420 if (io->in) {
2421 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2422 memcpy(&val, vcpu->arch.pio_data, io->size);
2423 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2424 }
de7d789a
CO		 2425 } else {
2426 if (io->in) {
2427 r = pio_copy_data(vcpu);
5fdbf976 2428 if (r)
de7d789a 2429 return r;
de7d789a
CO		 2430 }
2431
2432 delta = 1;
2433 if (io->rep) {
2434 delta *= io->cur_count;
2435 /*
2436 * The size of the register should really depend on
2437 * current address size.
2438 */
5fdbf976
MT		 2439 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2440 val -= delta;
2441 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2442 }
2443 if (io->down)
2444 delta = -delta;
2445 delta *= io->size;
5fdbf976
MT		 2446 if (io->in) {
2447 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2448 val += delta;
2449 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2450 } else {
2451 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2452 val += delta;
2453 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2454 }
de7d789a
CO		 2455 }
2456
de7d789a
CO		 2457 io->count -= io->cur_count;
2458 io->cur_count = 0;
2459
2460 return 0;
2461}
2462
2463static void kernel_pio(struct kvm_io_device *pio_dev,
2464 struct kvm_vcpu *vcpu,
2465 void *pd)
2466{
2467 /* TODO: String I/O for in kernel device */
2468
2469 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2470 if (vcpu->arch.pio.in)
2471 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2472 vcpu->arch.pio.size,
de7d789a
CO		 2473 pd);
2474 else
ad312c7c
ZX		 2475 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2476 vcpu->arch.pio.size,
de7d789a
CO		 2477 pd);
2478 mutex_unlock(&vcpu->kvm->lock);
2479}
2480
2481static void pio_string_write(struct kvm_io_device *pio_dev,
2482 struct kvm_vcpu *vcpu)
2483{
ad312c7c
ZX		 2484 struct kvm_pio_request *io = &vcpu->arch.pio;
2485 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2486 int i;
2487
2488 mutex_lock(&vcpu->kvm->lock);
2489 for (i = 0; i < io->cur_count; i++) {
2490 kvm_iodevice_write(pio_dev, io->port,
2491 io->size,
2492 pd);
2493 pd += io->size;
2494 }
2495 mutex_unlock(&vcpu->kvm->lock);
2496}
2497
2498static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2499 gpa_t addr, int len,
2500 int is_write)
de7d789a 2501{
92760499 2502 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2503}
2504
2505int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2506 int size, unsigned port)
2507{
2508 struct kvm_io_device *pio_dev;
5fdbf976 2509 unsigned long val;
de7d789a
CO		 2510
2511 vcpu->run->exit_reason = KVM_EXIT_IO;
2512 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2513 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2514 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2515 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2516 vcpu->run->io.port = vcpu->arch.pio.port = port;
2517 vcpu->arch.pio.in = in;
2518 vcpu->arch.pio.string = 0;
2519 vcpu->arch.pio.down = 0;
ad312c7c 2520 vcpu->arch.pio.rep = 0;
de7d789a 2521
2714d1d3
FEL		 2522 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2523 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2524 handler);
2525 else
2526 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2527 handler);
2528
5fdbf976
MT		 2529 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2530 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2531
92760499 2532 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2533 if (pio_dev) {
ad312c7c 2534 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2535 complete_pio(vcpu);
2536 return 1;
2537 }
2538 return 0;
2539}
2540EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2541
2542int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2543 int size, unsigned long count, int down,
2544 gva_t address, int rep, unsigned port)
2545{
2546 unsigned now, in_page;
0f346074 2547 int ret = 0;
de7d789a
CO		 2548 struct kvm_io_device *pio_dev;
2549
2550 vcpu->run->exit_reason = KVM_EXIT_IO;
2551 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2552 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2553 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2554 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2555 vcpu->run->io.port = vcpu->arch.pio.port = port;
2556 vcpu->arch.pio.in = in;
2557 vcpu->arch.pio.string = 1;
2558 vcpu->arch.pio.down = down;
ad312c7c 2559 vcpu->arch.pio.rep = rep;
de7d789a 2560
2714d1d3
FEL		 2561 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2562 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2563 handler);
2564 else
2565 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2566 handler);
2567
de7d789a
CO		 2568 if (!count) {
2569 kvm_x86_ops->skip_emulated_instruction(vcpu);
2570 return 1;
2571 }
2572
2573 if (!down)
2574 in_page = PAGE_SIZE - offset_in_page(address);
2575 else
2576 in_page = offset_in_page(address) + size;
2577 now = min(count, (unsigned long)in_page / size);
0f346074 2578 if (!now)
de7d789a 2579 now = 1;
de7d789a
CO		 2580 if (down) {
2581 /*
2582 * String I/O in reverse. Yuck. Kill the guest, fix later.
2583 */
2584 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2585 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2586 return 1;
2587 }
2588 vcpu->run->io.count = now;
ad312c7c 2589 vcpu->arch.pio.cur_count = now;
de7d789a 2590
ad312c7c 2591 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2592 kvm_x86_ops->skip_emulated_instruction(vcpu);
2593
0f346074 2594 vcpu->arch.pio.guest_gva = address;
de7d789a 2595
92760499
LV		 2596 pio_dev = vcpu_find_pio_dev(vcpu, port,
2597 vcpu->arch.pio.cur_count,
2598 !vcpu->arch.pio.in);
ad312c7c 2599 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2600 /* string PIO write */
2601 ret = pio_copy_data(vcpu);
0f346074
IE		 2602 if (ret == X86EMUL_PROPAGATE_FAULT) {
2603 kvm_inject_gp(vcpu, 0);
2604 return 1;
2605 }
2606 if (ret == 0 && pio_dev) {
de7d789a
CO		 2607 pio_string_write(pio_dev, vcpu);
2608 complete_pio(vcpu);
ad312c7c 2609 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2610 ret = 1;
2611 }
2612 } else if (pio_dev)
2613 pr_unimpl(vcpu, "no string pio read support yet, "
2614 "port %x size %d count %ld\n",
2615 port, size, count);
2616
2617 return ret;
2618}
2619EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2620
f8c16bba 2621int kvm_arch_init(void *opaque)
043405e1 2622{
56c6d28a 2623 int r;
f8c16bba
ZX		 2624 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2625
f8c16bba
ZX		 2626 if (kvm_x86_ops) {
2627 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2628 r = -EEXIST;
2629 goto out;
f8c16bba
ZX		 2630 }
2631
2632 if (!ops->cpu_has_kvm_support()) {
2633 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2634 r = -EOPNOTSUPP;
2635 goto out;
f8c16bba
ZX		 2636 }
2637 if (ops->disabled_by_bios()) {
2638 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2639 r = -EOPNOTSUPP;
2640 goto out;
f8c16bba
ZX		 2641 }
2642
97db56ce
AK		 2643 r = kvm_mmu_module_init();
2644 if (r)
2645 goto out;
2646
2647 kvm_init_msr_list();
2648
f8c16bba 2649 kvm_x86_ops = ops;
56c6d28a 2650 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2651 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2652 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2653 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
f8c16bba 2654 return 0;
56c6d28a
ZX		 2655
2656out:
56c6d28a 2657 return r;
043405e1 2658}
8776e519 2659
f8c16bba
ZX		 2660void kvm_arch_exit(void)
2661{
2662 kvm_x86_ops = NULL;
56c6d28a
ZX		 2663 kvm_mmu_module_exit();
2664}
f8c16bba 2665
8776e519
HB		 2666int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2667{
2668 ++vcpu->stat.halt_exits;
2714d1d3 2669 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2670 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2671 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2672 return 1;
2673 } else {
2674 vcpu->run->exit_reason = KVM_EXIT_HLT;
2675 return 0;
2676 }
2677}
2678EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2679
2f333bcb
MT		 2680static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2681 unsigned long a1)
2682{
2683 if (is_long_mode(vcpu))
2684 return a0;
2685 else
2686 return a0 | ((gpa_t)a1 << 32);
2687}
2688
8776e519
HB		 2689int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2690{
2691 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2692 int r = 1;
8776e519 2693
5fdbf976
MT		 2694 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2695 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2696 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2697 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2698 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2699
2714d1d3
FEL		 2700 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2701
8776e519
HB		 2702 if (!is_long_mode(vcpu)) {
2703 nr &= 0xFFFFFFFF;
2704 a0 &= 0xFFFFFFFF;
2705 a1 &= 0xFFFFFFFF;
2706 a2 &= 0xFFFFFFFF;
2707 a3 &= 0xFFFFFFFF;
2708 }
2709
2710 switch (nr) {
b93463aa
AK		 2711 case KVM_HC_VAPIC_POLL_IRQ:
2712 ret = 0;
2713 break;
2f333bcb
MT		 2714 case KVM_HC_MMU_OP:
2715 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2716 break;
8776e519
HB		 2717 default:
2718 ret = -KVM_ENOSYS;
2719 break;
2720 }
5fdbf976 2721 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2722 ++vcpu->stat.hypercalls;
2f333bcb 2723 return r;
8776e519
HB		 2724}
2725EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2726
2727int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2728{
2729 char instruction[3];
2730 int ret = 0;
5fdbf976 2731 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2732
8776e519
HB		 2733
2734 /*
2735 * Blow out the MMU to ensure that no other VCPU has an active mapping
2736 * to ensure that the updated hypercall appears atomically across all
2737 * VCPUs.
2738 */
2739 kvm_mmu_zap_all(vcpu->kvm);
2740
8776e519 2741 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2742 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2743 != X86EMUL_CONTINUE)
2744 ret = -EFAULT;
2745
8776e519
HB		 2746 return ret;
2747}
2748
2749static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2750{
2751 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2752}
2753
2754void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2755{
2756 struct descriptor_table dt = { limit, base };
2757
2758 kvm_x86_ops->set_gdt(vcpu, &dt);
2759}
2760
2761void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2762{
2763 struct descriptor_table dt = { limit, base };
2764
2765 kvm_x86_ops->set_idt(vcpu, &dt);
2766}
2767
2768void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2769 unsigned long *rflags)
2770{
2d3ad1f4 2771 kvm_lmsw(vcpu, msw);
8776e519
HB		 2772 *rflags = kvm_x86_ops->get_rflags(vcpu);
2773}
2774
2775unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2776{
54e445ca
JR		 2777 unsigned long value;
2778
8776e519
HB		 2779 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2780 switch (cr) {
2781 case 0:
54e445ca
JR		 2782 value = vcpu->arch.cr0;
2783 break;
8776e519 2784 case 2:
54e445ca
JR		 2785 value = vcpu->arch.cr2;
2786 break;
8776e519 2787 case 3:
54e445ca
JR		 2788 value = vcpu->arch.cr3;
2789 break;
8776e519 2790 case 4:
54e445ca
JR		 2791 value = vcpu->arch.cr4;
2792 break;
152ff9be 2793 case 8:
54e445ca
JR		 2794 value = kvm_get_cr8(vcpu);
2795 break;
8776e519 2796 default:
b8688d51 2797 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2798 return 0;
2799 }
54e445ca
JR		 2800 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2801 (u32)((u64)value >> 32), handler);
2802
2803 return value;
8776e519
HB		 2804}
2805
2806void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2807 unsigned long *rflags)
2808{
54e445ca
JR		 2809 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2810 (u32)((u64)val >> 32), handler);
2811
8776e519
HB		 2812 switch (cr) {
2813 case 0:
2d3ad1f4 2814 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2815 *rflags = kvm_x86_ops->get_rflags(vcpu);
2816 break;
2817 case 2:
ad312c7c 2818 vcpu->arch.cr2 = val;
8776e519
HB		 2819 break;
2820 case 3:
2d3ad1f4 2821 kvm_set_cr3(vcpu, val);
8776e519
HB		 2822 break;
2823 case 4:
2d3ad1f4 2824 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2825 break;
152ff9be 2826 case 8:
2d3ad1f4 2827 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2828 break;
8776e519 2829 default:
b8688d51 2830 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2831 }
2832}
2833
07716717
DK		 2834static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2835{
ad312c7c
ZX		 2836 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2837 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2838
2839 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2840 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2841 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2842 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2843 if (ej->function == e->function) {
2844 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2845 return j;
2846 }
2847 }
2848 return 0; /* silence gcc, even though control never reaches here */
2849}
2850
2851/* find an entry with matching function, matching index (if needed), and that
2852 * should be read next (if it's stateful) */
2853static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2854 u32 function, u32 index)
2855{
2856 if (e->function != function)
2857 return 0;
2858 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2859 return 0;
2860 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2861 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2862 return 0;
2863 return 1;
2864}
2865
d8017474
AG		 2866struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2867 u32 function, u32 index)
8776e519
HB		 2868{
2869 int i;
d8017474 2870 struct kvm_cpuid_entry2 *best = NULL;
8776e519 2871
ad312c7c 2872 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 2873 struct kvm_cpuid_entry2 *e;
2874
ad312c7c 2875 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2876 if (is_matching_cpuid_entry(e, function, index)) {
2877 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2878 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2879 best = e;
2880 break;
2881 }
2882 /*
2883 * Both basic or both extended?
2884 */
2885 if (((e->function ^ function) & 0x80000000) == 0)
2886 if (!best || e->function > best->function)
2887 best = e;
2888 }
d8017474
AG		 2889
2890 return best;
2891}
2892
2893void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2894{
2895 u32 function, index;
2896 struct kvm_cpuid_entry2 *best;
2897
2898 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2899 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2900 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2901 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2902 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2903 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
2904 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 2905 if (best) {
5fdbf976
MT		 2906 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2907 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2908 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2909 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2910 }
8776e519 2911 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2912 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2913 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2914 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2915 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2916 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2917}
2918EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2919
b6c7a5dc
HB		 2920/*
2921 * Check if userspace requested an interrupt window, and that the
2922 * interrupt window is open.
2923 *
2924 * No need to exit to userspace if we already have an interrupt queued.
2925 */
2926static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2927 struct kvm_run *kvm_run)
2928{
ad312c7c 2929 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2930 kvm_run->request_interrupt_window &&
ad312c7c 2931 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2932 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2933}
2934
2935static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2936 struct kvm_run *kvm_run)
2937{
2938 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2939 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 2940 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 2941 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2942 kvm_run->ready_for_interrupt_injection = 1;
4531220b 2943 else
b6c7a5dc 2944 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2945 (vcpu->arch.interrupt_window_open &&
2946 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2947}
2948
b93463aa
AK		 2949static void vapic_enter(struct kvm_vcpu *vcpu)
2950{
2951 struct kvm_lapic *apic = vcpu->arch.apic;
2952 struct page *page;
2953
2954 if (!apic || !apic->vapic_addr)
2955 return;
2956
2957 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 2958
2959 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2960}
2961
2962static void vapic_exit(struct kvm_vcpu *vcpu)
2963{
2964 struct kvm_lapic *apic = vcpu->arch.apic;
2965
2966 if (!apic || !apic->vapic_addr)
2967 return;
2968
f8b78fa3 2969 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2970 kvm_release_page_dirty(apic->vapic_page);
2971 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2972 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2973}
2974
d7690175 2975static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 2976{
2977 int r;
2978
2e53d63a
MT		 2979 if (vcpu->requests)
2980 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2981 kvm_mmu_unload(vcpu);
2982
b6c7a5dc
HB		 2983 r = kvm_mmu_reload(vcpu);
2984 if (unlikely(r))
2985 goto out;
2986
2f52d58c
AK		 2987 if (vcpu->requests) {
2988 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2989 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 2990 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
2991 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 2992 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2993 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2994 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2995 &vcpu->requests)) {
2996 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2997 r = 0;
2998 goto out;
2999 }
71c4dfaf
JR		 3000 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3001 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3002 r = 0;
3003 goto out;
3004 }
2f52d58c 3005 }
b93463aa 3006
06e05645 3007 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 3008 kvm_inject_pending_timer_irqs(vcpu);
3009
3010 preempt_disable();
3011
3012 kvm_x86_ops->prepare_guest_switch(vcpu);
3013 kvm_load_guest_fpu(vcpu);
3014
3015 local_irq_disable();
3016
d7690175 3017 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3018 local_irq_enable();
3019 preempt_enable();
3020 r = 1;
3021 goto out;
3022 }
3023
e9571ed5
MT		 3024 vcpu->guest_mode = 1;
3025 /*
3026 * Make sure that guest_mode assignment won't happen after
3027 * testing the pending IRQ vector bitmap.
3028 */
3029 smp_wmb();
3030
ad312c7c 3031 if (vcpu->arch.exception.pending)
298101da
AK		 3032 __queue_exception(vcpu);
3033 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3034 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3035 else
b6c7a5dc
HB		 3036 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3037
b93463aa
AK		 3038 kvm_lapic_sync_to_vapic(vcpu);
3039
3200f405
MT		 3040 up_read(&vcpu->kvm->slots_lock);
3041
b6c7a5dc
HB		 3042 kvm_guest_enter();
3043
42dbaa5a
JK		 3044 get_debugreg(vcpu->arch.host_dr6, 6);
3045 get_debugreg(vcpu->arch.host_dr7, 7);
3046 if (unlikely(vcpu->arch.switch_db_regs)) {
3047 get_debugreg(vcpu->arch.host_db[0], 0);
3048 get_debugreg(vcpu->arch.host_db[1], 1);
3049 get_debugreg(vcpu->arch.host_db[2], 2);
3050 get_debugreg(vcpu->arch.host_db[3], 3);
3051
3052 set_debugreg(0, 7);
3053 set_debugreg(vcpu->arch.eff_db[0], 0);
3054 set_debugreg(vcpu->arch.eff_db[1], 1);
3055 set_debugreg(vcpu->arch.eff_db[2], 2);
3056 set_debugreg(vcpu->arch.eff_db[3], 3);
3057 }
b6c7a5dc 3058
2714d1d3 3059 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3060 kvm_x86_ops->run(vcpu, kvm_run);
3061
42dbaa5a
JK		 3062 if (unlikely(vcpu->arch.switch_db_regs)) {
3063 set_debugreg(0, 7);
3064 set_debugreg(vcpu->arch.host_db[0], 0);
3065 set_debugreg(vcpu->arch.host_db[1], 1);
3066 set_debugreg(vcpu->arch.host_db[2], 2);
3067 set_debugreg(vcpu->arch.host_db[3], 3);
3068 }
3069 set_debugreg(vcpu->arch.host_dr6, 6);
3070 set_debugreg(vcpu->arch.host_dr7, 7);
3071
b6c7a5dc
HB		 3072 vcpu->guest_mode = 0;
3073 local_irq_enable();
3074
3075 ++vcpu->stat.exits;
3076
3077 /*
3078 * We must have an instruction between local_irq_enable() and
3079 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3080 * the interrupt shadow. The stat.exits increment will do nicely.
3081 * But we need to prevent reordering, hence this barrier():
3082 */
3083 barrier();
3084
3085 kvm_guest_exit();
3086
3087 preempt_enable();
3088
3200f405
MT		 3089 down_read(&vcpu->kvm->slots_lock);
3090
b6c7a5dc
HB		 3091 /*
3092 * Profile KVM exit RIPs:
3093 */
3094 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3095 unsigned long rip = kvm_rip_read(vcpu);
3096 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3097 }
3098
ad312c7c
ZX		 3099 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3100 vcpu->arch.exception.pending = false;
298101da 3101
b93463aa
AK		 3102 kvm_lapic_sync_from_vapic(vcpu);
3103
b6c7a5dc 3104 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3105out:
3106 return r;
3107}
b6c7a5dc 3108
d7690175
MT		 3109static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3110{
3111 int r;
3112
3113 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3114 pr_debug("vcpu %d received sipi with vector # %x\n",
3115 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3116 kvm_lapic_reset(vcpu);
5f179287 3117 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3118 if (r)
3119 return r;
3120 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3121 }
3122
d7690175
MT		 3123 down_read(&vcpu->kvm->slots_lock);
3124 vapic_enter(vcpu);
3125
3126 r = 1;
3127 while (r > 0) {
af2152f5 3128 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3129 r = vcpu_enter_guest(vcpu, kvm_run);
3130 else {
3131 up_read(&vcpu->kvm->slots_lock);
3132 kvm_vcpu_block(vcpu);
3133 down_read(&vcpu->kvm->slots_lock);
3134 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3135 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3136 vcpu->arch.mp_state =
3137 KVM_MP_STATE_RUNNABLE;
3138 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3139 r = -EINTR;
3140 }
3141
3142 if (r > 0) {
3143 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3144 r = -EINTR;
3145 kvm_run->exit_reason = KVM_EXIT_INTR;
3146 ++vcpu->stat.request_irq_exits;
3147 }
3148 if (signal_pending(current)) {
3149 r = -EINTR;
3150 kvm_run->exit_reason = KVM_EXIT_INTR;
3151 ++vcpu->stat.signal_exits;
3152 }
3153 if (need_resched()) {
3154 up_read(&vcpu->kvm->slots_lock);
3155 kvm_resched(vcpu);
3156 down_read(&vcpu->kvm->slots_lock);
3157 }
3158 }
b6c7a5dc
HB		 3159 }
3160
d7690175 3161 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3162 post_kvm_run_save(vcpu, kvm_run);
3163
b93463aa
AK		 3164 vapic_exit(vcpu);
3165
b6c7a5dc
HB		 3166 return r;
3167}
3168
3169int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3170{
3171 int r;
3172 sigset_t sigsaved;
3173
3174 vcpu_load(vcpu);
3175
ac9f6dc0
AK		 3176 if (vcpu->sigset_active)
3177 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3178
a4535290 3179 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3180 kvm_vcpu_block(vcpu);
d7690175 3181 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3182 r = -EAGAIN;
3183 goto out;
b6c7a5dc
HB		 3184 }
3185
b6c7a5dc
HB		 3186 /* re-sync apic's tpr */
3187 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3188 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3189
ad312c7c 3190 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3191 r = complete_pio(vcpu);
3192 if (r)
3193 goto out;
3194 }
3195#if CONFIG_HAS_IOMEM
3196 if (vcpu->mmio_needed) {
3197 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3198 vcpu->mmio_read_completed = 1;
3199 vcpu->mmio_needed = 0;
3200f405
MT		 3200
3201 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3202 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3203 vcpu->arch.mmio_fault_cr2, 0,
3204 EMULTYPE_NO_DECODE);
3200f405 3205 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3206 if (r == EMULATE_DO_MMIO) {
3207 /*
3208 * Read-modify-write. Back to userspace.
3209 */
3210 r = 0;
3211 goto out;
3212 }
3213 }
3214#endif
5fdbf976
MT		 3215 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3216 kvm_register_write(vcpu, VCPU_REGS_RAX,
3217 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3218
3219 r = __vcpu_run(vcpu, kvm_run);
3220
3221out:
3222 if (vcpu->sigset_active)
3223 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3224
3225 vcpu_put(vcpu);
3226 return r;
3227}
3228
3229int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3230{
3231 vcpu_load(vcpu);
3232
5fdbf976
MT		 3233 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3234 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3235 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3236 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3237 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3238 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3239 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3240 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3241#ifdef CONFIG_X86_64
5fdbf976
MT		 3242 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3243 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3244 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3245 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3246 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3247 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3248 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3249 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3250#endif
3251
5fdbf976 3252 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3253 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3254
3255 /*
3256 * Don't leak debug flags in case they were set for guest debugging
3257 */
d0bfb940 3258 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3259 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3260
3261 vcpu_put(vcpu);
3262
3263 return 0;
3264}
3265
3266int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3267{
3268 vcpu_load(vcpu);
3269
5fdbf976
MT		 3270 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3271 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3272 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3273 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3274 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3275 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3276 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3277 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3278#ifdef CONFIG_X86_64
5fdbf976
MT		 3279 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3280 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3281 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3282 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3283 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3284 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3285 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3286 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3287
b6c7a5dc
HB		 3288#endif
3289
5fdbf976 3290 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3291 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3292
b6c7a5dc 3293
b4f14abd
JK		 3294 vcpu->arch.exception.pending = false;
3295
b6c7a5dc
HB		 3296 vcpu_put(vcpu);
3297
3298 return 0;
3299}
3300
3e6e0aab
GT		 3301void kvm_get_segment(struct kvm_vcpu *vcpu,
3302 struct kvm_segment *var, int seg)
b6c7a5dc 3303{
14af3f3c 3304 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3305}
3306
3307void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3308{
3309 struct kvm_segment cs;
3310
3e6e0aab 3311 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3312 *db = cs.db;
3313 *l = cs.l;
3314}
3315EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3316
3317int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3318 struct kvm_sregs *sregs)
3319{
3320 struct descriptor_table dt;
3321 int pending_vec;
3322
3323 vcpu_load(vcpu);
3324
3e6e0aab
GT		 3325 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3326 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3327 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3328 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3329 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3330 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3331
3e6e0aab
GT		 3332 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3333 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3334
3335 kvm_x86_ops->get_idt(vcpu, &dt);
3336 sregs->idt.limit = dt.limit;
3337 sregs->idt.base = dt.base;
3338 kvm_x86_ops->get_gdt(vcpu, &dt);
3339 sregs->gdt.limit = dt.limit;
3340 sregs->gdt.base = dt.base;
3341
3342 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3343 sregs->cr0 = vcpu->arch.cr0;
3344 sregs->cr2 = vcpu->arch.cr2;
3345 sregs->cr3 = vcpu->arch.cr3;
3346 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3347 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3348 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3349 sregs->apic_base = kvm_get_apic_base(vcpu);
3350
3351 if (irqchip_in_kernel(vcpu->kvm)) {
3352 memset(sregs->interrupt_bitmap, 0,
3353 sizeof sregs->interrupt_bitmap);
3354 pending_vec = kvm_x86_ops->get_irq(vcpu);
3355 if (pending_vec >= 0)
3356 set_bit(pending_vec,
3357 (unsigned long *)sregs->interrupt_bitmap);
3358 } else
ad312c7c 3359 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3360 sizeof sregs->interrupt_bitmap);
3361
3362 vcpu_put(vcpu);
3363
3364 return 0;
3365}
3366
62d9f0db
MT		 3367int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3368 struct kvm_mp_state *mp_state)
3369{
3370 vcpu_load(vcpu);
3371 mp_state->mp_state = vcpu->arch.mp_state;
3372 vcpu_put(vcpu);
3373 return 0;
3374}
3375
3376int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3377 struct kvm_mp_state *mp_state)
3378{
3379 vcpu_load(vcpu);
3380 vcpu->arch.mp_state = mp_state->mp_state;
3381 vcpu_put(vcpu);
3382 return 0;
3383}
3384
3e6e0aab 3385static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3386 struct kvm_segment *var, int seg)
3387{
14af3f3c 3388 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3389}
3390
37817f29
IE		 3391static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3392 struct kvm_segment *kvm_desct)
3393{
3394 kvm_desct->base = seg_desc->base0;
3395 kvm_desct->base |= seg_desc->base1 << 16;
3396 kvm_desct->base |= seg_desc->base2 << 24;
3397 kvm_desct->limit = seg_desc->limit0;
3398 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3399 if (seg_desc->g) {
3400 kvm_desct->limit <<= 12;
3401 kvm_desct->limit |= 0xfff;
3402 }
37817f29
IE		 3403 kvm_desct->selector = selector;
3404 kvm_desct->type = seg_desc->type;
3405 kvm_desct->present = seg_desc->p;
3406 kvm_desct->dpl = seg_desc->dpl;
3407 kvm_desct->db = seg_desc->d;
3408 kvm_desct->s = seg_desc->s;
3409 kvm_desct->l = seg_desc->l;
3410 kvm_desct->g = seg_desc->g;
3411 kvm_desct->avl = seg_desc->avl;
3412 if (!selector)
3413 kvm_desct->unusable = 1;
3414 else
3415 kvm_desct->unusable = 0;
3416 kvm_desct->padding = 0;
3417}
3418
b8222ad2
AS		 3419static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3420 u16 selector,
3421 struct descriptor_table *dtable)
37817f29
IE		 3422{
3423 if (selector & 1 << 2) {
3424 struct kvm_segment kvm_seg;
3425
3e6e0aab 3426 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3427
3428 if (kvm_seg.unusable)
3429 dtable->limit = 0;
3430 else
3431 dtable->limit = kvm_seg.limit;
3432 dtable->base = kvm_seg.base;
3433 }
3434 else
3435 kvm_x86_ops->get_gdt(vcpu, dtable);
3436}
3437
3438/* allowed just for 8 bytes segments */
3439static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3440 struct desc_struct *seg_desc)
3441{
98899aa0 3442 gpa_t gpa;
37817f29
IE		 3443 struct descriptor_table dtable;
3444 u16 index = selector >> 3;
3445
b8222ad2 3446 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3447
3448 if (dtable.limit < index * 8 + 7) {
3449 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3450 return 1;
3451 }
98899aa0
MT		 3452 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3453 gpa += index * 8;
3454 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3455}
3456
3457/* allowed just for 8 bytes segments */
3458static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3459 struct desc_struct *seg_desc)
3460{
98899aa0 3461 gpa_t gpa;
37817f29
IE		 3462 struct descriptor_table dtable;
3463 u16 index = selector >> 3;
3464
b8222ad2 3465 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3466
3467 if (dtable.limit < index * 8 + 7)
3468 return 1;
98899aa0
MT		 3469 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3470 gpa += index * 8;
3471 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3472}
3473
3474static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3475 struct desc_struct *seg_desc)
3476{
3477 u32 base_addr;
3478
3479 base_addr = seg_desc->base0;
3480 base_addr |= (seg_desc->base1 << 16);
3481 base_addr |= (seg_desc->base2 << 24);
3482
98899aa0 3483 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3484}
3485
37817f29
IE		 3486static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3487{
3488 struct kvm_segment kvm_seg;
3489
3e6e0aab 3490 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3491 return kvm_seg.selector;
3492}
3493
3494static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3495 u16 selector,
3496 struct kvm_segment *kvm_seg)
3497{
3498 struct desc_struct seg_desc;
3499
3500 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3501 return 1;
3502 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3503 return 0;
3504}
3505
2259e3a7 3506static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3507{
3508 struct kvm_segment segvar = {
3509 .base = selector << 4,
3510 .limit = 0xffff,
3511 .selector = selector,
3512 .type = 3,
3513 .present = 1,
3514 .dpl = 3,
3515 .db = 0,
3516 .s = 1,
3517 .l = 0,
3518 .g = 0,
3519 .avl = 0,
3520 .unusable = 0,
3521 };
3522 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3523 return 0;
3524}
3525
3e6e0aab
GT		 3526int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3527 int type_bits, int seg)
37817f29
IE		 3528{
3529 struct kvm_segment kvm_seg;
3530
f4bbd9aa
AK		 3531 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3532 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3533 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3534 return 1;
3535 kvm_seg.type |= type_bits;
3536
3537 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3538 seg != VCPU_SREG_LDTR)
3539 if (!kvm_seg.s)
3540 kvm_seg.unusable = 1;
3541
3e6e0aab 3542 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3543 return 0;
3544}
3545
3546static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3547 struct tss_segment_32 *tss)
3548{
3549 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3550 tss->eip = kvm_rip_read(vcpu);
37817f29 3551 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3552 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3553 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3554 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3555 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3556 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3557 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3558 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3559 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3560 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3561 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3562 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3563 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3564 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3565 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3566 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3567 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3568}
3569
3570static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3571 struct tss_segment_32 *tss)
3572{
3573 kvm_set_cr3(vcpu, tss->cr3);
3574
5fdbf976 3575 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3576 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3577
5fdbf976
MT		 3578 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3579 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3580 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3581 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3582 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3583 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3584 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3585 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3586
3e6e0aab 3587 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3588 return 1;
3589
3e6e0aab 3590 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3591 return 1;
3592
3e6e0aab 3593 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3594 return 1;
3595
3e6e0aab 3596 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3597 return 1;
3598
3e6e0aab 3599 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3600 return 1;
3601
3e6e0aab 3602 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3603 return 1;
3604
3e6e0aab 3605 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3606 return 1;
3607 return 0;
3608}
3609
3610static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3611 struct tss_segment_16 *tss)
3612{
5fdbf976 3613 tss->ip = kvm_rip_read(vcpu);
37817f29 3614 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3615 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3616 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3617 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3618 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3619 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3620 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3621 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3622 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3623
3624 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3625 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3626 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3627 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3628 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3629 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3630}
3631
3632static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3633 struct tss_segment_16 *tss)
3634{
5fdbf976 3635 kvm_rip_write(vcpu, tss->ip);
37817f29 3636 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3637 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3638 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3639 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3640 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3641 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3642 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3643 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3644 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3645
3e6e0aab 3646 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3647 return 1;
3648
3e6e0aab 3649 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3650 return 1;
3651
3e6e0aab 3652 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3653 return 1;
3654
3e6e0aab 3655 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3656 return 1;
3657
3e6e0aab 3658 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3659 return 1;
3660 return 0;
3661}
3662
8b2cf73c 3663static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3664 u32 old_tss_base,
37817f29
IE		 3665 struct desc_struct *nseg_desc)
3666{
3667 struct tss_segment_16 tss_segment_16;
3668 int ret = 0;
3669
34198bf8
MT		 3670 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3671 sizeof tss_segment_16))
37817f29
IE		 3672 goto out;
3673
3674 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3675
34198bf8
MT		 3676 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3677 sizeof tss_segment_16))
37817f29 3678 goto out;
34198bf8
MT		 3679
3680 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3681 &tss_segment_16, sizeof tss_segment_16))
3682 goto out;
3683
37817f29
IE		 3684 if (load_state_from_tss16(vcpu, &tss_segment_16))
3685 goto out;
3686
3687 ret = 1;
3688out:
3689 return ret;
3690}
3691
8b2cf73c 3692static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3693 u32 old_tss_base,
37817f29
IE		 3694 struct desc_struct *nseg_desc)
3695{
3696 struct tss_segment_32 tss_segment_32;
3697 int ret = 0;
3698
34198bf8
MT		 3699 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3700 sizeof tss_segment_32))
37817f29
IE		 3701 goto out;
3702
3703 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3704
34198bf8
MT		 3705 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3706 sizeof tss_segment_32))
3707 goto out;
3708
3709 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3710 &tss_segment_32, sizeof tss_segment_32))
37817f29 3711 goto out;
34198bf8 3712
37817f29
IE		 3713 if (load_state_from_tss32(vcpu, &tss_segment_32))
3714 goto out;
3715
3716 ret = 1;
3717out:
3718 return ret;
3719}
3720
3721int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3722{
3723 struct kvm_segment tr_seg;
3724 struct desc_struct cseg_desc;
3725 struct desc_struct nseg_desc;
3726 int ret = 0;
34198bf8
MT		 3727 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3728 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3729
34198bf8 3730 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3731
34198bf8
MT		 3732 /* FIXME: Handle errors. Failure to read either TSS or their
3733 * descriptors should generate a pagefault.
3734 */
37817f29
IE		 3735 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3736 goto out;
3737
34198bf8 3738 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3739 goto out;
3740
37817f29
IE		 3741 if (reason != TASK_SWITCH_IRET) {
3742 int cpl;
3743
3744 cpl = kvm_x86_ops->get_cpl(vcpu);
3745 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3746 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3747 return 1;
3748 }
3749 }
3750
3751 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3752 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3753 return 1;
3754 }
3755
3756 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3757 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3758 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3759 }
3760
3761 if (reason == TASK_SWITCH_IRET) {
3762 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3763 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3764 }
3765
3766 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3767
3768 if (nseg_desc.type & 8)
34198bf8 3769 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3770 &nseg_desc);
3771 else
34198bf8 3772 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3773 &nseg_desc);
3774
3775 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3776 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3777 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3778 }
3779
3780 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3781 nseg_desc.type |= (1 << 1);
37817f29
IE		 3782 save_guest_segment_descriptor(vcpu, tss_selector,
3783 &nseg_desc);
3784 }
3785
3786 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3787 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3788 tr_seg.type = 11;
3e6e0aab 3789 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3790out:
37817f29
IE		 3791 return ret;
3792}
3793EXPORT_SYMBOL_GPL(kvm_task_switch);
3794
b6c7a5dc
HB		 3795int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3796 struct kvm_sregs *sregs)
3797{
3798 int mmu_reset_needed = 0;
3799 int i, pending_vec, max_bits;
3800 struct descriptor_table dt;
3801
3802 vcpu_load(vcpu);
3803
3804 dt.limit = sregs->idt.limit;
3805 dt.base = sregs->idt.base;
3806 kvm_x86_ops->set_idt(vcpu, &dt);
3807 dt.limit = sregs->gdt.limit;
3808 dt.base = sregs->gdt.base;
3809 kvm_x86_ops->set_gdt(vcpu, &dt);
3810
ad312c7c
ZX		 3811 vcpu->arch.cr2 = sregs->cr2;
3812 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3813 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3814
2d3ad1f4 3815 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3816
ad312c7c 3817 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3818 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3819 kvm_set_apic_base(vcpu, sregs->apic_base);
3820
3821 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3822
ad312c7c 3823 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3824 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3825 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3826
ad312c7c 3827 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3828 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3829 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3830 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3831
3832 if (mmu_reset_needed)
3833 kvm_mmu_reset_context(vcpu);
3834
3835 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3836 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3837 sizeof vcpu->arch.irq_pending);
3838 vcpu->arch.irq_summary = 0;
3839 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3840 if (vcpu->arch.irq_pending[i])
3841 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3842 } else {
3843 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3844 pending_vec = find_first_bit(
3845 (const unsigned long *)sregs->interrupt_bitmap,
3846 max_bits);
3847 /* Only pending external irq is handled here */
3848 if (pending_vec < max_bits) {
3849 kvm_x86_ops->set_irq(vcpu, pending_vec);
3850 pr_debug("Set back pending irq %d\n",
3851 pending_vec);
3852 }
e4825800 3853 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3854 }
3855
3e6e0aab
GT		 3856 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3857 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3858 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3859 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3860 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3861 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3862
3e6e0aab
GT		 3863 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3864 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3865
9c3e4aab
MT		 3866 /* Older userspace won't unhalt the vcpu on reset. */
3867 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3868 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3869 !(vcpu->arch.cr0 & X86_CR0_PE))
3870 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3871
b6c7a5dc
HB		 3872 vcpu_put(vcpu);
3873
3874 return 0;
3875}
3876
d0bfb940
JK		 3877int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
3878 struct kvm_guest_debug *dbg)
b6c7a5dc 3879{
ae675ef0 3880 int i, r;
b6c7a5dc
HB		 3881
3882 vcpu_load(vcpu);
3883
ae675ef0
JK		 3884 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
3885 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
3886 for (i = 0; i < KVM_NR_DB_REGS; ++i)
3887 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
3888 vcpu->arch.switch_db_regs =
3889 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
3890 } else {
3891 for (i = 0; i < KVM_NR_DB_REGS; i++)
3892 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
3893 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
3894 }
3895
b6c7a5dc
HB		 3896 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3897
d0bfb940
JK		 3898 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
3899 kvm_queue_exception(vcpu, DB_VECTOR);
3900 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
3901 kvm_queue_exception(vcpu, BP_VECTOR);
3902
b6c7a5dc
HB		 3903 vcpu_put(vcpu);
3904
3905 return r;
3906}
3907
d0752060
HB		 3908/*
3909 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3910 * we have asm/x86/processor.h
3911 */
3912struct fxsave {
3913 u16 cwd;
3914 u16 swd;
3915 u16 twd;
3916 u16 fop;
3917 u64 rip;
3918 u64 rdp;
3919 u32 mxcsr;
3920 u32 mxcsr_mask;
3921 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3922#ifdef CONFIG_X86_64
3923 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3924#else
3925 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3926#endif
3927};
3928
8b006791
ZX		 3929/*
3930 * Translate a guest virtual address to a guest physical address.
3931 */
3932int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3933 struct kvm_translation *tr)
3934{
3935 unsigned long vaddr = tr->linear_address;
3936 gpa_t gpa;
3937
3938 vcpu_load(vcpu);
72dc67a6 3939 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3940 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3941 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3942 tr->physical_address = gpa;
3943 tr->valid = gpa != UNMAPPED_GVA;
3944 tr->writeable = 1;
3945 tr->usermode = 0;
8b006791
ZX		 3946 vcpu_put(vcpu);
3947
3948 return 0;
3949}
3950
d0752060
HB		 3951int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3952{
ad312c7c 3953 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3954
3955 vcpu_load(vcpu);
3956
3957 memcpy(fpu->fpr, fxsave->st_space, 128);
3958 fpu->fcw = fxsave->cwd;
3959 fpu->fsw = fxsave->swd;
3960 fpu->ftwx = fxsave->twd;
3961 fpu->last_opcode = fxsave->fop;
3962 fpu->last_ip = fxsave->rip;
3963 fpu->last_dp = fxsave->rdp;
3964 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3965
3966 vcpu_put(vcpu);
3967
3968 return 0;
3969}
3970
3971int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3972{
ad312c7c 3973 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3974
3975 vcpu_load(vcpu);
3976
3977 memcpy(fxsave->st_space, fpu->fpr, 128);
3978 fxsave->cwd = fpu->fcw;
3979 fxsave->swd = fpu->fsw;
3980 fxsave->twd = fpu->ftwx;
3981 fxsave->fop = fpu->last_opcode;
3982 fxsave->rip = fpu->last_ip;
3983 fxsave->rdp = fpu->last_dp;
3984 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3985
3986 vcpu_put(vcpu);
3987
3988 return 0;
3989}
3990
3991void fx_init(struct kvm_vcpu *vcpu)
3992{
3993 unsigned after_mxcsr_mask;
3994
bc1a34f1
AA		 3995 /*
3996 * Touch the fpu the first time in non atomic context as if
3997 * this is the first fpu instruction the exception handler
3998 * will fire before the instruction returns and it'll have to
3999 * allocate ram with GFP_KERNEL.
4000 */
4001 if (!used_math())
d6e88aec 4002 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4003
d0752060
HB		 4004 /* Initialize guest FPU by resetting ours and saving into guest's */
4005 preempt_disable();
d6e88aec
AK		 4006 kvm_fx_save(&vcpu->arch.host_fx_image);
4007 kvm_fx_finit();
4008 kvm_fx_save(&vcpu->arch.guest_fx_image);
4009 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4010 preempt_enable();
4011
ad312c7c 4012 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4013 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4014 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4015 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4016 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4017}
4018EXPORT_SYMBOL_GPL(fx_init);
4019
4020void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4021{
4022 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4023 return;
4024
4025 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4026 kvm_fx_save(&vcpu->arch.host_fx_image);
4027 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4028}
4029EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4030
4031void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4032{
4033 if (!vcpu->guest_fpu_loaded)
4034 return;
4035
4036 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4037 kvm_fx_save(&vcpu->arch.guest_fx_image);
4038 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4039 ++vcpu->stat.fpu_reload;
d0752060
HB		 4040}
4041EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4042
4043void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4044{
4045 kvm_x86_ops->vcpu_free(vcpu);
4046}
4047
4048struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4049 unsigned int id)
4050{
26e5215f
AK		 4051 return kvm_x86_ops->vcpu_create(kvm, id);
4052}
e9b11c17 4053
26e5215f
AK		 4054int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4055{
4056 int r;
e9b11c17
ZX		 4057
4058 /* We do fxsave: this must be aligned. */
ad312c7c 4059 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4060
0bed3b56 4061 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4062 vcpu_load(vcpu);
4063 r = kvm_arch_vcpu_reset(vcpu);
4064 if (r == 0)
4065 r = kvm_mmu_setup(vcpu);
4066 vcpu_put(vcpu);
4067 if (r < 0)
4068 goto free_vcpu;
4069
26e5215f 4070 return 0;
e9b11c17
ZX		 4071free_vcpu:
4072 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4073 return r;
e9b11c17
ZX		 4074}
4075
d40ccc62 4076void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4077{
4078 vcpu_load(vcpu);
4079 kvm_mmu_unload(vcpu);
4080 vcpu_put(vcpu);
4081
4082 kvm_x86_ops->vcpu_free(vcpu);
4083}
4084
4085int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4086{
448fa4a9
JK		 4087 vcpu->arch.nmi_pending = false;
4088 vcpu->arch.nmi_injected = false;
4089
42dbaa5a
JK		 4090 vcpu->arch.switch_db_regs = 0;
4091 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4092 vcpu->arch.dr6 = DR6_FIXED_1;
4093 vcpu->arch.dr7 = DR7_FIXED_1;
4094
e9b11c17
ZX		 4095 return kvm_x86_ops->vcpu_reset(vcpu);
4096}
4097
4098void kvm_arch_hardware_enable(void *garbage)
4099{
4100 kvm_x86_ops->hardware_enable(garbage);
4101}
4102
4103void kvm_arch_hardware_disable(void *garbage)
4104{
4105 kvm_x86_ops->hardware_disable(garbage);
4106}
4107
4108int kvm_arch_hardware_setup(void)
4109{
4110 return kvm_x86_ops->hardware_setup();
4111}
4112
4113void kvm_arch_hardware_unsetup(void)
4114{
4115 kvm_x86_ops->hardware_unsetup();
4116}
4117
4118void kvm_arch_check_processor_compat(void *rtn)
4119{
4120 kvm_x86_ops->check_processor_compatibility(rtn);
4121}
4122
4123int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4124{
4125 struct page *page;
4126 struct kvm *kvm;
4127 int r;
4128
4129 BUG_ON(vcpu->kvm == NULL);
4130 kvm = vcpu->kvm;
4131
ad312c7c 4132 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4133 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4134 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4135 else
a4535290 4136 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4137
4138 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4139 if (!page) {
4140 r = -ENOMEM;
4141 goto fail;
4142 }
ad312c7c 4143 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4144
4145 r = kvm_mmu_create(vcpu);
4146 if (r < 0)
4147 goto fail_free_pio_data;
4148
4149 if (irqchip_in_kernel(kvm)) {
4150 r = kvm_create_lapic(vcpu);
4151 if (r < 0)
4152 goto fail_mmu_destroy;
4153 }
4154
4155 return 0;
4156
4157fail_mmu_destroy:
4158 kvm_mmu_destroy(vcpu);
4159fail_free_pio_data:
ad312c7c 4160 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4161fail:
4162 return r;
4163}
4164
4165void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4166{
4167 kvm_free_lapic(vcpu);
3200f405 4168 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4169 kvm_mmu_destroy(vcpu);
3200f405 4170 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4171 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4172}
d19a9cd2
ZX		 4173
4174struct kvm *kvm_arch_create_vm(void)
4175{
4176 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4177
4178 if (!kvm)
4179 return ERR_PTR(-ENOMEM);
4180
f05e70ac 4181 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4182 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4183 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4184
5550af4d
SY		 4185 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4186 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4187
53f658b3
MT		 4188 rdtscll(kvm->arch.vm_init_tsc);
4189
d19a9cd2
ZX		 4190 return kvm;
4191}
4192
4193static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4194{
4195 vcpu_load(vcpu);
4196 kvm_mmu_unload(vcpu);
4197 vcpu_put(vcpu);
4198}
4199
4200static void kvm_free_vcpus(struct kvm *kvm)
4201{
4202 unsigned int i;
4203
4204 /*
4205 * Unpin any mmu pages first.
4206 */
4207 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4208 if (kvm->vcpus[i])
4209 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4210 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4211 if (kvm->vcpus[i]) {
4212 kvm_arch_vcpu_free(kvm->vcpus[i]);
4213 kvm->vcpus[i] = NULL;
4214 }
4215 }
4216
4217}
4218
ad8ba2cd
SY		 4219void kvm_arch_sync_events(struct kvm *kvm)
4220{
ba4cef31 4221 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4222}
4223
d19a9cd2
ZX		 4224void kvm_arch_destroy_vm(struct kvm *kvm)
4225{
6eb55818 4226 kvm_iommu_unmap_guest(kvm);
7837699f 4227 kvm_free_pit(kvm);
d7deeeb0
ZX		 4228 kfree(kvm->arch.vpic);
4229 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4230 kvm_free_vcpus(kvm);
4231 kvm_free_physmem(kvm);
3d45830c
AK		 4232 if (kvm->arch.apic_access_page)
4233 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4234 if (kvm->arch.ept_identity_pagetable)
4235 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4236 kfree(kvm);
4237}
0de10343
ZX		 4238
4239int kvm_arch_set_memory_region(struct kvm *kvm,
4240 struct kvm_userspace_memory_region *mem,
4241 struct kvm_memory_slot old,
4242 int user_alloc)
4243{
4244 int npages = mem->memory_size >> PAGE_SHIFT;
4245 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4246
4247 /*To keep backward compatibility with older userspace,
4248 *x86 needs to hanlde !user_alloc case.
4249 */
4250 if (!user_alloc) {
4251 if (npages && !old.rmap) {
604b38ac
AA		 4252 unsigned long userspace_addr;
4253
72dc67a6 4254 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4255 userspace_addr = do_mmap(NULL, 0,
4256 npages * PAGE_SIZE,
4257 PROT_READ | PROT_WRITE,
acee3c04 4258 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4259 0);
72dc67a6 4260 up_write(&current->mm->mmap_sem);
0de10343 4261
604b38ac
AA		 4262 if (IS_ERR((void *)userspace_addr))
4263 return PTR_ERR((void *)userspace_addr);
4264
4265 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4266 spin_lock(&kvm->mmu_lock);
4267 memslot->userspace_addr = userspace_addr;
4268 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4269 } else {
4270 if (!old.user_alloc && old.rmap) {
4271 int ret;
4272
72dc67a6 4273 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4274 ret = do_munmap(current->mm, old.userspace_addr,
4275 old.npages * PAGE_SIZE);
72dc67a6 4276 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4277 if (ret < 0)
4278 printk(KERN_WARNING
4279 "kvm_vm_ioctl_set_memory_region: "
4280 "failed to munmap memory\n");
4281 }
4282 }
4283 }
4284
f05e70ac 4285 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4286 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4287 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4288 }
4289
4290 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4291 kvm_flush_remote_tlbs(kvm);
4292
4293 return 0;
4294}
1d737c8a 4295
34d4cb8f
MT		 4296void kvm_arch_flush_shadow(struct kvm *kvm)
4297{
4298 kvm_mmu_zap_all(kvm);
4299}
4300
1d737c8a
ZX		 4301int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4302{
a4535290 4303 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4304 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4305 || vcpu->arch.nmi_pending;
1d737c8a 4306}
5736199a
ZX		 4307
4308static void vcpu_kick_intr(void *info)
4309{
4310#ifdef DEBUG
4311 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4312 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4313#endif
4314}
4315
4316void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4317{
4318 int ipi_pcpu = vcpu->cpu;
e9571ed5 4319 int cpu = get_cpu();
5736199a
ZX		 4320
4321 if (waitqueue_active(&vcpu->wq)) {
4322 wake_up_interruptible(&vcpu->wq);
4323 ++vcpu->stat.halt_wakeup;
4324 }
e9571ed5
MT		 4325 /*
4326 * We may be called synchronously with irqs disabled in guest mode,
4327 * So need not to call smp_call_function_single() in that case.
4328 */
4329 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4330 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4331 put_cpu();
5736199a 4332}
Linux kernel - Deliverables
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