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KVM: remove useless write to vcpu->hv_clock.tsc_timestamp
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261{
262 /* TODO: reserve bits check */
8a5a87d9 263 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 264}
265EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266
e3ba45b8
GL		 267asmlinkage void kvm_spurious_fault(void)
268{
269 /* Fault while not rebooting. We want the trace. */
270 BUG();
271}
272EXPORT_SYMBOL_GPL(kvm_spurious_fault);
273
3fd28fce
ED		 274#define EXCPT_BENIGN 0
275#define EXCPT_CONTRIBUTORY 1
276#define EXCPT_PF 2
277
278static int exception_class(int vector)
279{
280 switch (vector) {
281 case PF_VECTOR:
282 return EXCPT_PF;
283 case DE_VECTOR:
284 case TS_VECTOR:
285 case NP_VECTOR:
286 case SS_VECTOR:
287 case GP_VECTOR:
288 return EXCPT_CONTRIBUTORY;
289 default:
290 break;
291 }
292 return EXCPT_BENIGN;
293}
294
295static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 296 unsigned nr, bool has_error, u32 error_code,
297 bool reinject)
3fd28fce
ED		 298{
299 u32 prev_nr;
300 int class1, class2;
301
3842d135
AK		 302 kvm_make_request(KVM_REQ_EVENT, vcpu);
303
3fd28fce
ED		 304 if (!vcpu->arch.exception.pending) {
305 queue:
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = has_error;
308 vcpu->arch.exception.nr = nr;
309 vcpu->arch.exception.error_code = error_code;
3f0fd292 310 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 311 return;
312 }
313
314 /* to check exception */
315 prev_nr = vcpu->arch.exception.nr;
316 if (prev_nr == DF_VECTOR) {
317 /* triple fault -> shutdown */
a8eeb04a 318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 319 return;
320 }
321 class1 = exception_class(prev_nr);
322 class2 = exception_class(nr);
323 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325 /* generate double fault per SDM Table 5-5 */
326 vcpu->arch.exception.pending = true;
327 vcpu->arch.exception.has_error_code = true;
328 vcpu->arch.exception.nr = DF_VECTOR;
329 vcpu->arch.exception.error_code = 0;
330 } else
331 /* replace previous exception with a new one in a hope
332 that instruction re-execution will regenerate lost
333 exception */
334 goto queue;
335}
336
298101da
AK		 337void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
338{
ce7ddec4 339 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 340}
341EXPORT_SYMBOL_GPL(kvm_queue_exception);
342
ce7ddec4
JR		 343void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344{
345 kvm_multiple_exception(vcpu, nr, false, 0, true);
346}
347EXPORT_SYMBOL_GPL(kvm_requeue_exception);
348
db8fcefa 349void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 350{
db8fcefa
AP		 351 if (err)
352 kvm_inject_gp(vcpu, 0);
353 else
354 kvm_x86_ops->skip_emulated_instruction(vcpu);
355}
356EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 357
6389ee94 358void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 359{
360 ++vcpu->stat.pf_guest;
6389ee94
AK		 361 vcpu->arch.cr2 = fault->address;
362 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 363}
27d6c865 364EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 365
6389ee94 366void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 367{
6389ee94
AK		 368 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 370 else
6389ee94 371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 372}
373
3419ffc8
SY		 374void kvm_inject_nmi(struct kvm_vcpu *vcpu)
375{
7460fb4a
AK		 376 atomic_inc(&vcpu->arch.nmi_queued);
377 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 378}
379EXPORT_SYMBOL_GPL(kvm_inject_nmi);
380
298101da
AK		 381void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
382{
ce7ddec4 383 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 384}
385EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
386
ce7ddec4
JR		 387void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388{
389 kvm_multiple_exception(vcpu, nr, true, error_code, true);
390}
391EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
392
0a79b009
AK		 393/*
394 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
395 * a #GP and return false.
396 */
397bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 398{
0a79b009
AK		 399 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
400 return true;
401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
402 return false;
298101da 403}
0a79b009 404EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 405
ec92fe44
JR		 406/*
407 * This function will be used to read from the physical memory of the currently
408 * running guest. The difference to kvm_read_guest_page is that this function
409 * can read from guest physical or from the guest's guest physical memory.
410 */
411int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412 gfn_t ngfn, void *data, int offset, int len,
413 u32 access)
414{
415 gfn_t real_gfn;
416 gpa_t ngpa;
417
418 ngpa = gfn_to_gpa(ngfn);
419 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420 if (real_gfn == UNMAPPED_GVA)
421 return -EFAULT;
422
423 real_gfn = gpa_to_gfn(real_gfn);
424
425 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
426}
427EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
428
3d06b8bf
JR		 429int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430 void *data, int offset, int len, u32 access)
431{
432 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433 data, offset, len, access);
434}
435
a03490ed
CO		 436/*
437 * Load the pae pdptrs. Return true is they are all valid.
438 */
ff03a073 439int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 440{
441 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
443 int i;
444 int ret;
ff03a073 445 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 446
ff03a073
JR		 447 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448 offset * sizeof(u64), sizeof(pdpte),
449 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 450 if (ret < 0) {
451 ret = 0;
452 goto out;
453 }
454 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 455 if (is_present_gpte(pdpte[i]) &&
20c466b5 456 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 457 ret = 0;
458 goto out;
459 }
460 }
461 ret = 1;
462
ff03a073 463 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 464 __set_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail);
466 __set_bit(VCPU_EXREG_PDPTR,
467 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 468out:
a03490ed
CO		 469
470 return ret;
471}
cc4b6871 472EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 473
d835dfec
AK		 474static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475{
ff03a073 476 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 477 bool changed = true;
3d06b8bf
JR		 478 int offset;
479 gfn_t gfn;
d835dfec
AK		 480 int r;
481
482 if (is_long_mode(vcpu) || !is_pae(vcpu))
483 return false;
484
6de4f3ad
AK		 485 if (!test_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail))
487 return true;
488
9f8fe504
AK		 489 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 491 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 493 if (r < 0)
494 goto out;
ff03a073 495 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 496out:
d835dfec
AK		 497
498 return changed;
499}
500
49a9b07e 501int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 502{
aad82703
SY		 503 unsigned long old_cr0 = kvm_read_cr0(vcpu);
504 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505 X86_CR0_CD | X86_CR0_NW;
506
f9a48e6a
AK		 507 cr0 |= X86_CR0_ET;
508
ab344828 509#ifdef CONFIG_X86_64
0f12244f
GN		 510 if (cr0 & 0xffffffff00000000UL)
511 return 1;
ab344828
GN		 512#endif
513
514 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
517 return 1;
a03490ed 518
0f12244f
GN		 519 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
520 return 1;
a03490ed
CO		 521
522 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
523#ifdef CONFIG_X86_64
f6801dff 524 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 525 int cs_db, cs_l;
526
0f12244f
GN		 527 if (!is_pae(vcpu))
528 return 1;
a03490ed 529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 530 if (cs_l)
531 return 1;
a03490ed
CO		 532 } else
533#endif
ff03a073 534 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 535 kvm_read_cr3(vcpu)))
0f12244f 536 return 1;
a03490ed
CO		 537 }
538
ad756a16
MJ		 539 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
540 return 1;
541
a03490ed 542 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 543
d170c419 544 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 545 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 546 kvm_async_pf_hash_reset(vcpu);
547 }
e5f3f027 548
aad82703
SY		 549 if ((cr0 ^ old_cr0) & update_bits)
550 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 551 return 0;
552}
2d3ad1f4 553EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 554
2d3ad1f4 555void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 556{
49a9b07e 557 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 558}
2d3ad1f4 559EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 560
42bdf991
MT		 561static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
562{
563 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564 !vcpu->guest_xcr0_loaded) {
565 /* kvm_set_xcr() also depends on this */
566 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567 vcpu->guest_xcr0_loaded = 1;
568 }
569}
570
571static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
572{
573 if (vcpu->guest_xcr0_loaded) {
574 if (vcpu->arch.xcr0 != host_xcr0)
575 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576 vcpu->guest_xcr0_loaded = 0;
577 }
578}
579
2acf923e
DC		 580int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581{
582 u64 xcr0;
46c34cb0 583 u64 valid_bits;
2acf923e
DC		 584
585 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
586 if (index != XCR_XFEATURE_ENABLED_MASK)
587 return 1;
588 xcr0 = xcr;
2acf923e
DC		 589 if (!(xcr0 & XSTATE_FP))
590 return 1;
591 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
592 return 1;
46c34cb0
PB		 593
594 /*
595 * Do not allow the guest to set bits that we do not support
596 * saving. However, xcr0 bit 0 is always set, even if the
597 * emulated CPU does not support XSAVE (see fx_init).
598 */
599 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
600 if (xcr0 & ~valid_bits)
2acf923e 601 return 1;
46c34cb0 602
42bdf991 603 kvm_put_guest_xcr0(vcpu);
2acf923e 604 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 605 return 0;
606}
607
608int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
609{
764bcbc5
Z		 610 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
611 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 612 kvm_inject_gp(vcpu, 0);
613 return 1;
614 }
615 return 0;
616}
617EXPORT_SYMBOL_GPL(kvm_set_xcr);
618
a83b29c6 619int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 620{
fc78f519 621 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 622 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
623 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 624 if (cr4 & CR4_RESERVED_BITS)
625 return 1;
a03490ed 626
2acf923e
DC		 627 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
628 return 1;
629
c68b734f
YW		 630 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
631 return 1;
632
afcbf13f 633 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 634 return 1;
635
a03490ed 636 if (is_long_mode(vcpu)) {
0f12244f
GN		 637 if (!(cr4 & X86_CR4_PAE))
638 return 1;
a2edf57f
AK		 639 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
640 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 641 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
642 kvm_read_cr3(vcpu)))
0f12244f
GN		 643 return 1;
644
ad756a16
MJ		 645 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
646 if (!guest_cpuid_has_pcid(vcpu))
647 return 1;
648
649 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
650 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
651 return 1;
652 }
653
5e1746d6 654 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 655 return 1;
a03490ed 656
ad756a16
MJ		 657 if (((cr4 ^ old_cr4) & pdptr_bits) ||
658 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 659 kvm_mmu_reset_context(vcpu);
0f12244f 660
2acf923e 661 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 662 kvm_update_cpuid(vcpu);
2acf923e 663
0f12244f
GN		 664 return 0;
665}
2d3ad1f4 666EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 667
2390218b 668int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 669{
9f8fe504 670 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 671 kvm_mmu_sync_roots(vcpu);
d835dfec 672 kvm_mmu_flush_tlb(vcpu);
0f12244f 673 return 0;
d835dfec
AK		 674 }
675
a03490ed 676 if (is_long_mode(vcpu)) {
471842ec 677 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 678 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
679 return 1;
680 } else
681 if (cr3 & CR3_L_MODE_RESERVED_BITS)
682 return 1;
a03490ed
CO		 683 } else {
684 if (is_pae(vcpu)) {
0f12244f
GN		 685 if (cr3 & CR3_PAE_RESERVED_BITS)
686 return 1;
ff03a073
JR		 687 if (is_paging(vcpu) &&
688 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 689 return 1;
a03490ed
CO		 690 }
691 /*
692 * We don't check reserved bits in nonpae mode, because
693 * this isn't enforced, and VMware depends on this.
694 */
695 }
696
0f12244f 697 vcpu->arch.cr3 = cr3;
aff48baa 698 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 699 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 703
eea1cff9 704int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 705{
0f12244f
GN		 706 if (cr8 & CR8_RESERVED_BITS)
707 return 1;
a03490ed
CO		 708 if (irqchip_in_kernel(vcpu->kvm))
709 kvm_lapic_set_tpr(vcpu, cr8);
710 else
ad312c7c 711 vcpu->arch.cr8 = cr8;
0f12244f
GN		 712 return 0;
713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 715
2d3ad1f4 716unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 717{
718 if (irqchip_in_kernel(vcpu->kvm))
719 return kvm_lapic_get_cr8(vcpu);
720 else
ad312c7c 721 return vcpu->arch.cr8;
a03490ed 722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 724
c8639010
JK		 725static void kvm_update_dr7(struct kvm_vcpu *vcpu)
726{
727 unsigned long dr7;
728
729 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730 dr7 = vcpu->arch.guest_debug_dr7;
731 else
732 dr7 = vcpu->arch.dr7;
733 kvm_x86_ops->set_dr7(vcpu, dr7);
734 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
735}
736
338dbc97 737static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 738{
739 switch (dr) {
740 case 0 ... 3:
741 vcpu->arch.db[dr] = val;
742 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743 vcpu->arch.eff_db[dr] = val;
744 break;
745 case 4:
338dbc97
GN		 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747 return 1; /* #UD */
020df079
GN		 748 /* fall through */
749 case 6:
338dbc97
GN		 750 if (val & 0xffffffff00000000ULL)
751 return -1; /* #GP */
020df079
GN		 752 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
753 break;
754 case 5:
338dbc97
GN		 755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
756 return 1; /* #UD */
020df079
GN		 757 /* fall through */
758 default: /* 7 */
338dbc97
GN		 759 if (val & 0xffffffff00000000ULL)
760 return -1; /* #GP */
020df079 761 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 762 kvm_update_dr7(vcpu);
020df079
GN		 763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
770{
771 int res;
772
773 res = __kvm_set_dr(vcpu, dr, val);
774 if (res > 0)
775 kvm_queue_exception(vcpu, UD_VECTOR);
776 else if (res < 0)
777 kvm_inject_gp(vcpu, 0);
778
779 return res;
780}
020df079
GN		 781EXPORT_SYMBOL_GPL(kvm_set_dr);
782
338dbc97 783static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 784{
785 switch (dr) {
786 case 0 ... 3:
787 *val = vcpu->arch.db[dr];
788 break;
789 case 4:
338dbc97 790 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 791 return 1;
020df079
GN		 792 /* fall through */
793 case 6:
794 *val = vcpu->arch.dr6;
795 break;
796 case 5:
338dbc97 797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 798 return 1;
020df079
GN		 799 /* fall through */
800 default: /* 7 */
801 *val = vcpu->arch.dr7;
802 break;
803 }
804
805 return 0;
806}
338dbc97
GN		 807
808int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809{
810 if (_kvm_get_dr(vcpu, dr, val)) {
811 kvm_queue_exception(vcpu, UD_VECTOR);
812 return 1;
813 }
814 return 0;
815}
020df079
GN		 816EXPORT_SYMBOL_GPL(kvm_get_dr);
817
022cd0e8
AK		 818bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819{
820 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
821 u64 data;
822 int err;
823
824 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
825 if (err)
826 return err;
827 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
829 return err;
830}
831EXPORT_SYMBOL_GPL(kvm_rdpmc);
832
043405e1
CO		 833/*
834 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836 *
837 * This list is modified at module load time to reflect the
e3267cbb
GC		 838 * capabilities of the host cpu. This capabilities test skips MSRs that are
839 * kvm-specific. Those are put in the beginning of the list.
043405e1 840 */
e3267cbb 841
439793d4 842#define KVM_SAVE_MSRS_BEGIN 10
043405e1 843static u32 msrs_to_save[] = {
e3267cbb 844 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 845 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 846 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 847 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 848 MSR_KVM_PV_EOI_EN,
043405e1 849 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 850 MSR_STAR,
043405e1
CO		 851#ifdef CONFIG_X86_64
852 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
853#endif
b3897a49
NHE		 854 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
855 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 856};
857
858static unsigned num_msrs_to_save;
859
f1d24831 860static const u32 emulated_msrs[] = {
ba904635 861 MSR_IA32_TSC_ADJUST,
a3e06bbe 862 MSR_IA32_TSCDEADLINE,
043405e1 863 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 864 MSR_IA32_MCG_STATUS,
865 MSR_IA32_MCG_CTL,
043405e1
CO		 866};
867
384bb783 868bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 869{
b69e8cae 870 if (efer & efer_reserved_bits)
384bb783 871 return false;
15c4a640 872
1b2fd70c
AG		 873 if (efer & EFER_FFXSR) {
874 struct kvm_cpuid_entry2 *feat;
875
876 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 877 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 878 return false;
1b2fd70c
AG		 879 }
880
d8017474
AG		 881 if (efer & EFER_SVME) {
882 struct kvm_cpuid_entry2 *feat;
883
884 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 885 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 886 return false;
d8017474
AG		 887 }
888
384bb783
JK		 889 return true;
890}
891EXPORT_SYMBOL_GPL(kvm_valid_efer);
892
893static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
894{
895 u64 old_efer = vcpu->arch.efer;
896
897 if (!kvm_valid_efer(vcpu, efer))
898 return 1;
899
900 if (is_paging(vcpu)
901 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
902 return 1;
903
15c4a640 904 efer &= ~EFER_LMA;
f6801dff 905 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 906
a3d204e2
SY		 907 kvm_x86_ops->set_efer(vcpu, efer);
908
aad82703
SY		 909 /* Update reserved bits */
910 if ((efer ^ old_efer) & EFER_NX)
911 kvm_mmu_reset_context(vcpu);
912
b69e8cae 913 return 0;
15c4a640
CO		 914}
915
f2b4b7dd
JR		 916void kvm_enable_efer_bits(u64 mask)
917{
918 efer_reserved_bits &= ~mask;
919}
920EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
921
922
15c4a640
CO		 923/*
924 * Writes msr value into into the appropriate "register".
925 * Returns 0 on success, non-0 otherwise.
926 * Assumes vcpu_load() was already called.
927 */
8fe8ab46 928int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 929{
8fe8ab46 930 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 931}
932
313a3dc7
CO		 933/*
934 * Adapt set_msr() to msr_io()'s calling convention
935 */
936static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
937{
8fe8ab46
WA		 938 struct msr_data msr;
939
940 msr.data = *data;
941 msr.index = index;
942 msr.host_initiated = true;
943 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 944}
945
16e8d74d
MT		 946#ifdef CONFIG_X86_64
947struct pvclock_gtod_data {
948 seqcount_t seq;
949
950 struct { /* extract of a clocksource struct */
951 int vclock_mode;
952 cycle_t cycle_last;
953 cycle_t mask;
954 u32 mult;
955 u32 shift;
956 } clock;
957
958 /* open coded 'struct timespec' */
959 u64 monotonic_time_snsec;
960 time_t monotonic_time_sec;
961};
962
963static struct pvclock_gtod_data pvclock_gtod_data;
964
965static void update_pvclock_gtod(struct timekeeper *tk)
966{
967 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
968
969 write_seqcount_begin(&vdata->seq);
970
971 /* copy pvclock gtod data */
972 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
973 vdata->clock.cycle_last = tk->clock->cycle_last;
974 vdata->clock.mask = tk->clock->mask;
975 vdata->clock.mult = tk->mult;
976 vdata->clock.shift = tk->shift;
977
978 vdata->monotonic_time_sec = tk->xtime_sec
979 + tk->wall_to_monotonic.tv_sec;
980 vdata->monotonic_time_snsec = tk->xtime_nsec
981 + (tk->wall_to_monotonic.tv_nsec
982 << tk->shift);
983 while (vdata->monotonic_time_snsec >=
984 (((u64)NSEC_PER_SEC) << tk->shift)) {
985 vdata->monotonic_time_snsec -=
986 ((u64)NSEC_PER_SEC) << tk->shift;
987 vdata->monotonic_time_sec++;
988 }
989
990 write_seqcount_end(&vdata->seq);
991}
992#endif
993
994
18068523
GOC		 995static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
996{
9ed3c444
AK		 997 int version;
998 int r;
50d0a0f9 999 struct pvclock_wall_clock wc;
923de3cf 1000 struct timespec boot;
18068523
GOC		 1001
1002 if (!wall_clock)
1003 return;
1004
9ed3c444
AK		 1005 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1006 if (r)
1007 return;
1008
1009 if (version & 1)
1010 ++version; /* first time write, random junk */
1011
1012 ++version;
18068523 1013
18068523
GOC		 1014 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1015
50d0a0f9
GH		 1016 /*
1017 * The guest calculates current wall clock time by adding
34c238a1 1018 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1019 * wall clock specified here. guest system time equals host
1020 * system time for us, thus we must fill in host boot time here.
1021 */
923de3cf 1022 getboottime(&boot);
50d0a0f9 1023
4b648665
BR		 1024 if (kvm->arch.kvmclock_offset) {
1025 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1026 boot = timespec_sub(boot, ts);
1027 }
50d0a0f9
GH		 1028 wc.sec = boot.tv_sec;
1029 wc.nsec = boot.tv_nsec;
1030 wc.version = version;
18068523
GOC		 1031
1032 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1033
1034 version++;
1035 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1036}
1037
50d0a0f9
GH		 1038static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1039{
1040 uint32_t quotient, remainder;
1041
1042 /* Don't try to replace with do_div(), this one calculates
1043 * "(dividend << 32) / divisor" */
1044 __asm__ ( "divl %4"
1045 : "=a" (quotient), "=d" (remainder)
1046 : "0" (0), "1" (dividend), "r" (divisor) );
1047 return quotient;
1048}
1049
5f4e3f88
ZA		 1050static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1051 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1052{
5f4e3f88 1053 uint64_t scaled64;
50d0a0f9
GH		 1054 int32_t shift = 0;
1055 uint64_t tps64;
1056 uint32_t tps32;
1057
5f4e3f88
ZA		 1058 tps64 = base_khz * 1000LL;
1059 scaled64 = scaled_khz * 1000LL;
50933623 1060 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1061 tps64 >>= 1;
1062 shift--;
1063 }
1064
1065 tps32 = (uint32_t)tps64;
50933623
JK		 1066 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1067 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1068 scaled64 >>= 1;
1069 else
1070 tps32 <<= 1;
50d0a0f9
GH		 1071 shift++;
1072 }
1073
5f4e3f88
ZA		 1074 *pshift = shift;
1075 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1076
5f4e3f88
ZA		 1077 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1078 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1079}
1080
759379dd
ZA		 1081static inline u64 get_kernel_ns(void)
1082{
1083 struct timespec ts;
1084
1085 WARN_ON(preemptible());
1086 ktime_get_ts(&ts);
1087 monotonic_to_bootbased(&ts);
1088 return timespec_to_ns(&ts);
50d0a0f9
GH		 1089}
1090
d828199e 1091#ifdef CONFIG_X86_64
16e8d74d 1092static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1093#endif
16e8d74d 1094
c8076604 1095static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1096unsigned long max_tsc_khz;
c8076604 1097
cc578287 1098static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1099{
cc578287
ZA		 1100 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1101 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1102}
1103
cc578287 1104static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1105{
cc578287
ZA		 1106 u64 v = (u64)khz * (1000000 + ppm);
1107 do_div(v, 1000000);
1108 return v;
1e993611
JR		 1109}
1110
cc578287 1111static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1112{
cc578287
ZA		 1113 u32 thresh_lo, thresh_hi;
1114 int use_scaling = 0;
217fc9cf 1115
03ba32ca
MT		 1116 /* tsc_khz can be zero if TSC calibration fails */
1117 if (this_tsc_khz == 0)
1118 return;
1119
c285545f
ZA		 1120 /* Compute a scale to convert nanoseconds in TSC cycles */
1121 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1122 &vcpu->arch.virtual_tsc_shift,
1123 &vcpu->arch.virtual_tsc_mult);
1124 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1125
1126 /*
1127 * Compute the variation in TSC rate which is acceptable
1128 * within the range of tolerance and decide if the
1129 * rate being applied is within that bounds of the hardware
1130 * rate. If so, no scaling or compensation need be done.
1131 */
1132 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1133 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1134 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1135 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1136 use_scaling = 1;
1137 }
1138 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1139}
1140
1141static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1142{
e26101b1 1143 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1144 vcpu->arch.virtual_tsc_mult,
1145 vcpu->arch.virtual_tsc_shift);
e26101b1 1146 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1147 return tsc;
1148}
1149
b48aa97e
MT		 1150void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1151{
1152#ifdef CONFIG_X86_64
1153 bool vcpus_matched;
1154 bool do_request = false;
1155 struct kvm_arch *ka = &vcpu->kvm->arch;
1156 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1157
1158 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1159 atomic_read(&vcpu->kvm->online_vcpus));
1160
1161 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1162 if (!ka->use_master_clock)
1163 do_request = 1;
1164
1165 if (!vcpus_matched && ka->use_master_clock)
1166 do_request = 1;
1167
1168 if (do_request)
1169 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1170
1171 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1172 atomic_read(&vcpu->kvm->online_vcpus),
1173 ka->use_master_clock, gtod->clock.vclock_mode);
1174#endif
1175}
1176
ba904635
WA		 1177static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1178{
1179 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1180 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1181}
1182
8fe8ab46 1183void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1184{
1185 struct kvm *kvm = vcpu->kvm;
f38e098f 1186 u64 offset, ns, elapsed;
99e3e30a 1187 unsigned long flags;
02626b6a 1188 s64 usdiff;
b48aa97e 1189 bool matched;
8fe8ab46 1190 u64 data = msr->data;
99e3e30a 1191
038f8c11 1192 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1193 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1194 ns = get_kernel_ns();
f38e098f 1195 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1196
03ba32ca 1197 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1198 int faulted = 0;
1199
03ba32ca
MT		 1200 /* n.b - signed multiplication and division required */
1201 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1202#ifdef CONFIG_X86_64
03ba32ca 1203 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1204#else
03ba32ca 1205 /* do_div() only does unsigned */
8915aa27
MT		 1206 asm("1: idivl %[divisor]\n"
1207 "2: xor %%edx, %%edx\n"
1208 " movl $0, %[faulted]\n"
1209 "3:\n"
1210 ".section .fixup,\"ax\"\n"
1211 "4: movl $1, %[faulted]\n"
1212 " jmp 3b\n"
1213 ".previous\n"
1214
1215 _ASM_EXTABLE(1b, 4b)
1216
1217 : "=A"(usdiff), [faulted] "=r" (faulted)
1218 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1219
5d3cb0f6 1220#endif
03ba32ca
MT		 1221 do_div(elapsed, 1000);
1222 usdiff -= elapsed;
1223 if (usdiff < 0)
1224 usdiff = -usdiff;
8915aa27
MT		 1225
1226 /* idivl overflow => difference is larger than USEC_PER_SEC */
1227 if (faulted)
1228 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1229 } else
1230 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1231
1232 /*
5d3cb0f6
ZA		 1233 * Special case: TSC write with a small delta (1 second) of virtual
1234 * cycle time against real time is interpreted as an attempt to
1235 * synchronize the CPU.
1236 *
1237 * For a reliable TSC, we can match TSC offsets, and for an unstable
1238 * TSC, we add elapsed time in this computation. We could let the
1239 * compensation code attempt to catch up if we fall behind, but
1240 * it's better to try to match offsets from the beginning.
1241 */
02626b6a 1242 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1243 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1244 if (!check_tsc_unstable()) {
e26101b1 1245 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1246 pr_debug("kvm: matched tsc offset for %llu\n", data);
1247 } else {
857e4099 1248 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1249 data += delta;
1250 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1251 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1252 }
b48aa97e 1253 matched = true;
e26101b1
ZA		 1254 } else {
1255 /*
1256 * We split periods of matched TSC writes into generations.
1257 * For each generation, we track the original measured
1258 * nanosecond time, offset, and write, so if TSCs are in
1259 * sync, we can match exact offset, and if not, we can match
4a969980 1260 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1261 *
1262 * These values are tracked in kvm->arch.cur_xxx variables.
1263 */
1264 kvm->arch.cur_tsc_generation++;
1265 kvm->arch.cur_tsc_nsec = ns;
1266 kvm->arch.cur_tsc_write = data;
1267 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1268 matched = false;
e26101b1
ZA		 1269 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1270 kvm->arch.cur_tsc_generation, data);
f38e098f 1271 }
e26101b1
ZA		 1272
1273 /*
1274 * We also track th most recent recorded KHZ, write and time to
1275 * allow the matching interval to be extended at each write.
1276 */
f38e098f
ZA		 1277 kvm->arch.last_tsc_nsec = ns;
1278 kvm->arch.last_tsc_write = data;
5d3cb0f6 1279 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1280
b183aa58 1281 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1282
1283 /* Keep track of which generation this VCPU has synchronized to */
1284 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1285 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1286 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1287
ba904635
WA		 1288 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1289 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1290 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1291 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1292
1293 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1294 if (matched)
1295 kvm->arch.nr_vcpus_matched_tsc++;
1296 else
1297 kvm->arch.nr_vcpus_matched_tsc = 0;
1298
1299 kvm_track_tsc_matching(vcpu);
1300 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1301}
e26101b1 1302
99e3e30a
ZA		 1303EXPORT_SYMBOL_GPL(kvm_write_tsc);
1304
d828199e
MT		 1305#ifdef CONFIG_X86_64
1306
1307static cycle_t read_tsc(void)
1308{
1309 cycle_t ret;
1310 u64 last;
1311
1312 /*
1313 * Empirically, a fence (of type that depends on the CPU)
1314 * before rdtsc is enough to ensure that rdtsc is ordered
1315 * with respect to loads. The various CPU manuals are unclear
1316 * as to whether rdtsc can be reordered with later loads,
1317 * but no one has ever seen it happen.
1318 */
1319 rdtsc_barrier();
1320 ret = (cycle_t)vget_cycles();
1321
1322 last = pvclock_gtod_data.clock.cycle_last;
1323
1324 if (likely(ret >= last))
1325 return ret;
1326
1327 /*
1328 * GCC likes to generate cmov here, but this branch is extremely
1329 * predictable (it's just a funciton of time and the likely is
1330 * very likely) and there's a data dependence, so force GCC
1331 * to generate a branch instead. I don't barrier() because
1332 * we don't actually need a barrier, and if this function
1333 * ever gets inlined it will generate worse code.
1334 */
1335 asm volatile ("");
1336 return last;
1337}
1338
1339static inline u64 vgettsc(cycle_t *cycle_now)
1340{
1341 long v;
1342 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1343
1344 *cycle_now = read_tsc();
1345
1346 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1347 return v * gtod->clock.mult;
1348}
1349
1350static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1351{
1352 unsigned long seq;
1353 u64 ns;
1354 int mode;
1355 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1356
1357 ts->tv_nsec = 0;
1358 do {
1359 seq = read_seqcount_begin(&gtod->seq);
1360 mode = gtod->clock.vclock_mode;
1361 ts->tv_sec = gtod->monotonic_time_sec;
1362 ns = gtod->monotonic_time_snsec;
1363 ns += vgettsc(cycle_now);
1364 ns >>= gtod->clock.shift;
1365 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1366 timespec_add_ns(ts, ns);
1367
1368 return mode;
1369}
1370
1371/* returns true if host is using tsc clocksource */
1372static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1373{
1374 struct timespec ts;
1375
1376 /* checked again under seqlock below */
1377 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1378 return false;
1379
1380 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1381 return false;
1382
1383 monotonic_to_bootbased(&ts);
1384 *kernel_ns = timespec_to_ns(&ts);
1385
1386 return true;
1387}
1388#endif
1389
1390/*
1391 *
b48aa97e
MT		 1392 * Assuming a stable TSC across physical CPUS, and a stable TSC
1393 * across virtual CPUs, the following condition is possible.
1394 * Each numbered line represents an event visible to both
d828199e
MT		 1395 * CPUs at the next numbered event.
1396 *
1397 * "timespecX" represents host monotonic time. "tscX" represents
1398 * RDTSC value.
1399 *
1400 * VCPU0 on CPU0 | VCPU1 on CPU1
1401 *
1402 * 1. read timespec0,tsc0
1403 * 2. | timespec1 = timespec0 + N
1404 * | tsc1 = tsc0 + M
1405 * 3. transition to guest | transition to guest
1406 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1407 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1408 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1409 *
1410 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1411 *
1412 * - ret0 < ret1
1413 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1414 * ...
1415 * - 0 < N - M => M < N
1416 *
1417 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1418 * always the case (the difference between two distinct xtime instances
1419 * might be smaller then the difference between corresponding TSC reads,
1420 * when updating guest vcpus pvclock areas).
1421 *
1422 * To avoid that problem, do not allow visibility of distinct
1423 * system_timestamp/tsc_timestamp values simultaneously: use a master
1424 * copy of host monotonic time values. Update that master copy
1425 * in lockstep.
1426 *
b48aa97e 1427 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1428 *
1429 */
1430
1431static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1432{
1433#ifdef CONFIG_X86_64
1434 struct kvm_arch *ka = &kvm->arch;
1435 int vclock_mode;
b48aa97e
MT		 1436 bool host_tsc_clocksource, vcpus_matched;
1437
1438 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1439 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1440
1441 /*
1442 * If the host uses TSC clock, then passthrough TSC as stable
1443 * to the guest.
1444 */
b48aa97e 1445 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1446 &ka->master_kernel_ns,
1447 &ka->master_cycle_now);
1448
b48aa97e
MT		 1449 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1450
d828199e
MT		 1451 if (ka->use_master_clock)
1452 atomic_set(&kvm_guest_has_master_clock, 1);
1453
1454 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1455 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1456 vcpus_matched);
d828199e
MT		 1457#endif
1458}
1459
2e762ff7
MT		 1460static void kvm_gen_update_masterclock(struct kvm *kvm)
1461{
1462#ifdef CONFIG_X86_64
1463 int i;
1464 struct kvm_vcpu *vcpu;
1465 struct kvm_arch *ka = &kvm->arch;
1466
1467 spin_lock(&ka->pvclock_gtod_sync_lock);
1468 kvm_make_mclock_inprogress_request(kvm);
1469 /* no guest entries from this point */
1470 pvclock_update_vm_gtod_copy(kvm);
1471
1472 kvm_for_each_vcpu(i, vcpu, kvm)
1473 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1474
1475 /* guest entries allowed */
1476 kvm_for_each_vcpu(i, vcpu, kvm)
1477 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1478
1479 spin_unlock(&ka->pvclock_gtod_sync_lock);
1480#endif
1481}
1482
34c238a1 1483static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1484{
d828199e 1485 unsigned long flags, this_tsc_khz;
18068523 1486 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1487 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1488 s64 kernel_ns;
d828199e 1489 u64 tsc_timestamp, host_tsc;
0b79459b 1490 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1491 u8 pvclock_flags;
d828199e
MT		 1492 bool use_master_clock;
1493
1494 kernel_ns = 0;
1495 host_tsc = 0;
18068523 1496
d828199e
MT		 1497 /*
1498 * If the host uses TSC clock, then passthrough TSC as stable
1499 * to the guest.
1500 */
1501 spin_lock(&ka->pvclock_gtod_sync_lock);
1502 use_master_clock = ka->use_master_clock;
1503 if (use_master_clock) {
1504 host_tsc = ka->master_cycle_now;
1505 kernel_ns = ka->master_kernel_ns;
1506 }
1507 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1508
1509 /* Keep irq disabled to prevent changes to the clock */
1510 local_irq_save(flags);
1511 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1512 if (unlikely(this_tsc_khz == 0)) {
1513 local_irq_restore(flags);
1514 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1515 return 1;
1516 }
d828199e
MT		 1517 if (!use_master_clock) {
1518 host_tsc = native_read_tsc();
1519 kernel_ns = get_kernel_ns();
1520 }
1521
1522 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1523
c285545f
ZA		 1524 /*
1525 * We may have to catch up the TSC to match elapsed wall clock
1526 * time for two reasons, even if kvmclock is used.
1527 * 1) CPU could have been running below the maximum TSC rate
1528 * 2) Broken TSC compensation resets the base at each VCPU
1529 * entry to avoid unknown leaps of TSC even when running
1530 * again on the same CPU. This may cause apparent elapsed
1531 * time to disappear, and the guest to stand still or run
1532 * very slowly.
1533 */
1534 if (vcpu->tsc_catchup) {
1535 u64 tsc = compute_guest_tsc(v, kernel_ns);
1536 if (tsc > tsc_timestamp) {
f1e2b260 1537 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1538 tsc_timestamp = tsc;
1539 }
50d0a0f9
GH		 1540 }
1541
18068523
GOC		 1542 local_irq_restore(flags);
1543
0b79459b 1544 if (!vcpu->pv_time_enabled)
c285545f 1545 return 0;
18068523 1546
e48672fa 1547 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1548 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1549 &vcpu->hv_clock.tsc_shift,
1550 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1551 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1552 }
1553
1554 /* With all the info we got, fill in the values */
1d5f066e 1555 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1556 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1557 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1558 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1559
18068523
GOC		 1560 /*
1561 * The interface expects us to write an even number signaling that the
1562 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1563 * state, we just increase by 2 at the end.
18068523 1564 */
50d0a0f9 1565 vcpu->hv_clock.version += 2;
18068523 1566
0b79459b
AH		 1567 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1568 &guest_hv_clock, sizeof(guest_hv_clock))))
1569 return 0;
78c0337a
MT		 1570
1571 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1572 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1573
1574 if (vcpu->pvclock_set_guest_stopped_request) {
1575 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1576 vcpu->pvclock_set_guest_stopped_request = false;
1577 }
1578
d828199e
MT		 1579 /* If the host uses TSC clocksource, then it is stable */
1580 if (use_master_clock)
1581 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1582
78c0337a
MT		 1583 vcpu->hv_clock.flags = pvclock_flags;
1584
0b79459b
AH		 1585 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1586 &vcpu->hv_clock,
1587 sizeof(vcpu->hv_clock));
8cfdc000 1588 return 0;
c8076604
GH		 1589}
1590
0061d53d
MT		 1591/*
1592 * kvmclock updates which are isolated to a given vcpu, such as
1593 * vcpu->cpu migration, should not allow system_timestamp from
1594 * the rest of the vcpus to remain static. Otherwise ntp frequency
1595 * correction applies to one vcpu's system_timestamp but not
1596 * the others.
1597 *
1598 * So in those cases, request a kvmclock update for all vcpus.
1599 * The worst case for a remote vcpu to update its kvmclock
1600 * is then bounded by maximum nohz sleep latency.
1601 */
1602
1603static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1604{
1605 int i;
1606 struct kvm *kvm = v->kvm;
1607 struct kvm_vcpu *vcpu;
1608
1609 kvm_for_each_vcpu(i, vcpu, kvm) {
1610 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1611 kvm_vcpu_kick(vcpu);
1612 }
1613}
1614
9ba075a6
AK		 1615static bool msr_mtrr_valid(unsigned msr)
1616{
1617 switch (msr) {
1618 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1619 case MSR_MTRRfix64K_00000:
1620 case MSR_MTRRfix16K_80000:
1621 case MSR_MTRRfix16K_A0000:
1622 case MSR_MTRRfix4K_C0000:
1623 case MSR_MTRRfix4K_C8000:
1624 case MSR_MTRRfix4K_D0000:
1625 case MSR_MTRRfix4K_D8000:
1626 case MSR_MTRRfix4K_E0000:
1627 case MSR_MTRRfix4K_E8000:
1628 case MSR_MTRRfix4K_F0000:
1629 case MSR_MTRRfix4K_F8000:
1630 case MSR_MTRRdefType:
1631 case MSR_IA32_CR_PAT:
1632 return true;
1633 case 0x2f8:
1634 return true;
1635 }
1636 return false;
1637}
1638
d6289b93
MT		 1639static bool valid_pat_type(unsigned t)
1640{
1641 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1642}
1643
1644static bool valid_mtrr_type(unsigned t)
1645{
1646 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1647}
1648
1649static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1650{
1651 int i;
1652
1653 if (!msr_mtrr_valid(msr))
1654 return false;
1655
1656 if (msr == MSR_IA32_CR_PAT) {
1657 for (i = 0; i < 8; i++)
1658 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1659 return false;
1660 return true;
1661 } else if (msr == MSR_MTRRdefType) {
1662 if (data & ~0xcff)
1663 return false;
1664 return valid_mtrr_type(data & 0xff);
1665 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1666 for (i = 0; i < 8 ; i++)
1667 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1668 return false;
1669 return true;
1670 }
1671
1672 /* variable MTRRs */
1673 return valid_mtrr_type(data & 0xff);
1674}
1675
9ba075a6
AK		 1676static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1677{
0bed3b56
SY		 1678 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1679
d6289b93 1680 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1681 return 1;
1682
0bed3b56
SY		 1683 if (msr == MSR_MTRRdefType) {
1684 vcpu->arch.mtrr_state.def_type = data;
1685 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1686 } else if (msr == MSR_MTRRfix64K_00000)
1687 p[0] = data;
1688 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1689 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1690 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1691 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1692 else if (msr == MSR_IA32_CR_PAT)
1693 vcpu->arch.pat = data;
1694 else { /* Variable MTRRs */
1695 int idx, is_mtrr_mask;
1696 u64 *pt;
1697
1698 idx = (msr - 0x200) / 2;
1699 is_mtrr_mask = msr - 0x200 - 2 * idx;
1700 if (!is_mtrr_mask)
1701 pt =
1702 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1703 else
1704 pt =
1705 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1706 *pt = data;
1707 }
1708
1709 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1710 return 0;
1711}
15c4a640 1712
890ca9ae 1713static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1714{
890ca9ae
HY		 1715 u64 mcg_cap = vcpu->arch.mcg_cap;
1716 unsigned bank_num = mcg_cap & 0xff;
1717
15c4a640 1718 switch (msr) {
15c4a640 1719 case MSR_IA32_MCG_STATUS:
890ca9ae 1720 vcpu->arch.mcg_status = data;
15c4a640 1721 break;
c7ac679c 1722 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1723 if (!(mcg_cap & MCG_CTL_P))
1724 return 1;
1725 if (data != 0 && data != ~(u64)0)
1726 return -1;
1727 vcpu->arch.mcg_ctl = data;
1728 break;
1729 default:
1730 if (msr >= MSR_IA32_MC0_CTL &&
1731 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1732 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1733 /* only 0 or all 1s can be written to IA32_MCi_CTL
1734 * some Linux kernels though clear bit 10 in bank 4 to
1735 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1736 * this to avoid an uncatched #GP in the guest
1737 */
890ca9ae 1738 if ((offset & 0x3) == 0 &&
114be429 1739 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1740 return -1;
1741 vcpu->arch.mce_banks[offset] = data;
1742 break;
1743 }
1744 return 1;
1745 }
1746 return 0;
1747}
1748
ffde22ac
ES		 1749static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1750{
1751 struct kvm *kvm = vcpu->kvm;
1752 int lm = is_long_mode(vcpu);
1753 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1754 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1755 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1756 : kvm->arch.xen_hvm_config.blob_size_32;
1757 u32 page_num = data & ~PAGE_MASK;
1758 u64 page_addr = data & PAGE_MASK;
1759 u8 *page;
1760 int r;
1761
1762 r = -E2BIG;
1763 if (page_num >= blob_size)
1764 goto out;
1765 r = -ENOMEM;
ff5c2c03
SL		 1766 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1767 if (IS_ERR(page)) {
1768 r = PTR_ERR(page);
ffde22ac 1769 goto out;
ff5c2c03 1770 }
ffde22ac
ES		 1771 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1772 goto out_free;
1773 r = 0;
1774out_free:
1775 kfree(page);
1776out:
1777 return r;
1778}
1779
55cd8e5a
GN		 1780static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1781{
1782 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1783}
1784
1785static bool kvm_hv_msr_partition_wide(u32 msr)
1786{
1787 bool r = false;
1788 switch (msr) {
1789 case HV_X64_MSR_GUEST_OS_ID:
1790 case HV_X64_MSR_HYPERCALL:
1791 r = true;
1792 break;
1793 }
1794
1795 return r;
1796}
1797
1798static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1799{
1800 struct kvm *kvm = vcpu->kvm;
1801
1802 switch (msr) {
1803 case HV_X64_MSR_GUEST_OS_ID:
1804 kvm->arch.hv_guest_os_id = data;
1805 /* setting guest os id to zero disables hypercall page */
1806 if (!kvm->arch.hv_guest_os_id)
1807 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1808 break;
1809 case HV_X64_MSR_HYPERCALL: {
1810 u64 gfn;
1811 unsigned long addr;
1812 u8 instructions[4];
1813
1814 /* if guest os id is not set hypercall should remain disabled */
1815 if (!kvm->arch.hv_guest_os_id)
1816 break;
1817 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1818 kvm->arch.hv_hypercall = data;
1819 break;
1820 }
1821 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1822 addr = gfn_to_hva(kvm, gfn);
1823 if (kvm_is_error_hva(addr))
1824 return 1;
1825 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1826 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1827 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1828 return 1;
1829 kvm->arch.hv_hypercall = data;
1830 break;
1831 }
1832 default:
a737f256
CD		 1833 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1834 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1835 return 1;
1836 }
1837 return 0;
1838}
1839
1840static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1841{
10388a07
GN		 1842 switch (msr) {
1843 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1844 unsigned long addr;
55cd8e5a 1845
10388a07
GN		 1846 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1847 vcpu->arch.hv_vapic = data;
1848 break;
1849 }
1850 addr = gfn_to_hva(vcpu->kvm, data >>
1851 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1852 if (kvm_is_error_hva(addr))
1853 return 1;
8b0cedff 1854 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1855 return 1;
1856 vcpu->arch.hv_vapic = data;
1857 break;
1858 }
1859 case HV_X64_MSR_EOI:
1860 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1861 case HV_X64_MSR_ICR:
1862 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1863 case HV_X64_MSR_TPR:
1864 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1865 default:
a737f256
CD		 1866 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1867 "data 0x%llx\n", msr, data);
10388a07
GN		 1868 return 1;
1869 }
1870
1871 return 0;
55cd8e5a
GN		 1872}
1873
344d9588
GN		 1874static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1875{
1876 gpa_t gpa = data & ~0x3f;
1877
4a969980 1878 /* Bits 2:5 are reserved, Should be zero */
6adba527 1879 if (data & 0x3c)
344d9588
GN		 1880 return 1;
1881
1882 vcpu->arch.apf.msr_val = data;
1883
1884 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1885 kvm_clear_async_pf_completion_queue(vcpu);
1886 kvm_async_pf_hash_reset(vcpu);
1887 return 0;
1888 }
1889
8f964525
AH		 1890 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1891 sizeof(u32)))
344d9588
GN		 1892 return 1;
1893
6adba527 1894 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1895 kvm_async_pf_wakeup_all(vcpu);
1896 return 0;
1897}
1898
12f9a48f
GC		 1899static void kvmclock_reset(struct kvm_vcpu *vcpu)
1900{
0b79459b 1901 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1902}
1903
c9aaa895
GC		 1904static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1905{
1906 u64 delta;
1907
1908 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1909 return;
1910
1911 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1912 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1913 vcpu->arch.st.accum_steal = delta;
1914}
1915
1916static void record_steal_time(struct kvm_vcpu *vcpu)
1917{
1918 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1919 return;
1920
1921 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1922 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1923 return;
1924
1925 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1926 vcpu->arch.st.steal.version += 2;
1927 vcpu->arch.st.accum_steal = 0;
1928
1929 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1930 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1931}
1932
8fe8ab46 1933int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1934{
5753785f 1935 bool pr = false;
8fe8ab46
WA		 1936 u32 msr = msr_info->index;
1937 u64 data = msr_info->data;
5753785f 1938
15c4a640 1939 switch (msr) {
2e32b719
BP		 1940 case MSR_AMD64_NB_CFG:
1941 case MSR_IA32_UCODE_REV:
1942 case MSR_IA32_UCODE_WRITE:
1943 case MSR_VM_HSAVE_PA:
1944 case MSR_AMD64_PATCH_LOADER:
1945 case MSR_AMD64_BU_CFG2:
1946 break;
1947
15c4a640 1948 case MSR_EFER:
b69e8cae 1949 return set_efer(vcpu, data);
8f1589d9
AP		 1950 case MSR_K7_HWCR:
1951 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1952 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1953 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1954 if (data != 0) {
a737f256
CD		 1955 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1956 data);
8f1589d9
AP		 1957 return 1;
1958 }
15c4a640 1959 break;
f7c6d140
AP		 1960 case MSR_FAM10H_MMIO_CONF_BASE:
1961 if (data != 0) {
a737f256
CD		 1962 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1963 "0x%llx\n", data);
f7c6d140
AP		 1964 return 1;
1965 }
15c4a640 1966 break;
b5e2fec0
AG		 1967 case MSR_IA32_DEBUGCTLMSR:
1968 if (!data) {
1969 /* We support the non-activated case already */
1970 break;
1971 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1972 /* Values other than LBR and BTF are vendor-specific,
1973 thus reserved and should throw a #GP */
1974 return 1;
1975 }
a737f256
CD		 1976 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1977 __func__, data);
b5e2fec0 1978 break;
9ba075a6
AK		 1979 case 0x200 ... 0x2ff:
1980 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1981 case MSR_IA32_APICBASE:
1982 kvm_set_apic_base(vcpu, data);
1983 break;
0105d1a5
GN		 1984 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1985 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1986 case MSR_IA32_TSCDEADLINE:
1987 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1988 break;
ba904635
WA		 1989 case MSR_IA32_TSC_ADJUST:
1990 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1991 if (!msr_info->host_initiated) {
1992 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1993 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1994 }
1995 vcpu->arch.ia32_tsc_adjust_msr = data;
1996 }
1997 break;
15c4a640 1998 case MSR_IA32_MISC_ENABLE:
ad312c7c 1999 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2000 break;
11c6bffa 2001 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2002 case MSR_KVM_WALL_CLOCK:
2003 vcpu->kvm->arch.wall_clock = data;
2004 kvm_write_wall_clock(vcpu->kvm, data);
2005 break;
11c6bffa 2006 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2007 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2008 u64 gpa_offset;
12f9a48f 2009 kvmclock_reset(vcpu);
18068523
GOC		 2010
2011 vcpu->arch.time = data;
0061d53d 2012 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2013
2014 /* we verify if the enable bit is set... */
2015 if (!(data & 1))
2016 break;
2017
0b79459b 2018 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2019
0b79459b 2020 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2021 &vcpu->arch.pv_time, data & ~1ULL,
2022 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2023 vcpu->arch.pv_time_enabled = false;
2024 else
2025 vcpu->arch.pv_time_enabled = true;
32cad84f 2026
18068523
GOC		 2027 break;
2028 }
344d9588
GN		 2029 case MSR_KVM_ASYNC_PF_EN:
2030 if (kvm_pv_enable_async_pf(vcpu, data))
2031 return 1;
2032 break;
c9aaa895
GC		 2033 case MSR_KVM_STEAL_TIME:
2034
2035 if (unlikely(!sched_info_on()))
2036 return 1;
2037
2038 if (data & KVM_STEAL_RESERVED_MASK)
2039 return 1;
2040
2041 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2042 data & KVM_STEAL_VALID_BITS,
2043 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2044 return 1;
2045
2046 vcpu->arch.st.msr_val = data;
2047
2048 if (!(data & KVM_MSR_ENABLED))
2049 break;
2050
2051 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2052
2053 preempt_disable();
2054 accumulate_steal_time(vcpu);
2055 preempt_enable();
2056
2057 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2058
2059 break;
ae7a2a3f
MT		 2060 case MSR_KVM_PV_EOI_EN:
2061 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2062 return 1;
2063 break;
c9aaa895 2064
890ca9ae
HY		 2065 case MSR_IA32_MCG_CTL:
2066 case MSR_IA32_MCG_STATUS:
2067 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2068 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2069
2070 /* Performance counters are not protected by a CPUID bit,
2071 * so we should check all of them in the generic path for the sake of
2072 * cross vendor migration.
2073 * Writing a zero into the event select MSRs disables them,
2074 * which we perfectly emulate ;-). Any other value should be at least
2075 * reported, some guests depend on them.
2076 */
71db6023
AP		 2077 case MSR_K7_EVNTSEL0:
2078 case MSR_K7_EVNTSEL1:
2079 case MSR_K7_EVNTSEL2:
2080 case MSR_K7_EVNTSEL3:
2081 if (data != 0)
a737f256
CD		 2082 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2083 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2084 break;
2085 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2086 * so we ignore writes to make it happy.
2087 */
71db6023
AP		 2088 case MSR_K7_PERFCTR0:
2089 case MSR_K7_PERFCTR1:
2090 case MSR_K7_PERFCTR2:
2091 case MSR_K7_PERFCTR3:
a737f256
CD		 2092 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2093 "0x%x data 0x%llx\n", msr, data);
71db6023 2094 break;
5753785f
GN		 2095 case MSR_P6_PERFCTR0:
2096 case MSR_P6_PERFCTR1:
2097 pr = true;
2098 case MSR_P6_EVNTSEL0:
2099 case MSR_P6_EVNTSEL1:
2100 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2101 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2102
2103 if (pr || data != 0)
a737f256
CD		 2104 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2105 "0x%x data 0x%llx\n", msr, data);
5753785f 2106 break;
84e0cefa
JS		 2107 case MSR_K7_CLK_CTL:
2108 /*
2109 * Ignore all writes to this no longer documented MSR.
2110 * Writes are only relevant for old K7 processors,
2111 * all pre-dating SVM, but a recommended workaround from
4a969980 2112 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2113 * affected processor models on the command line, hence
2114 * the need to ignore the workaround.
2115 */
2116 break;
55cd8e5a
GN		 2117 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2118 if (kvm_hv_msr_partition_wide(msr)) {
2119 int r;
2120 mutex_lock(&vcpu->kvm->lock);
2121 r = set_msr_hyperv_pw(vcpu, msr, data);
2122 mutex_unlock(&vcpu->kvm->lock);
2123 return r;
2124 } else
2125 return set_msr_hyperv(vcpu, msr, data);
2126 break;
91c9c3ed 2127 case MSR_IA32_BBL_CR_CTL3:
2128 /* Drop writes to this legacy MSR -- see rdmsr
2129 * counterpart for further detail.
2130 */
a737f256 2131 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2132 break;
2b036c6b
BO		 2133 case MSR_AMD64_OSVW_ID_LENGTH:
2134 if (!guest_cpuid_has_osvw(vcpu))
2135 return 1;
2136 vcpu->arch.osvw.length = data;
2137 break;
2138 case MSR_AMD64_OSVW_STATUS:
2139 if (!guest_cpuid_has_osvw(vcpu))
2140 return 1;
2141 vcpu->arch.osvw.status = data;
2142 break;
15c4a640 2143 default:
ffde22ac
ES		 2144 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2145 return xen_hvm_config(vcpu, data);
f5132b01 2146 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2147 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2148 if (!ignore_msrs) {
a737f256
CD		 2149 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2150 msr, data);
ed85c068
AP		 2151 return 1;
2152 } else {
a737f256
CD		 2153 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2154 msr, data);
ed85c068
AP		 2155 break;
2156 }
15c4a640
CO		 2157 }
2158 return 0;
2159}
2160EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2161
2162
2163/*
2164 * Reads an msr value (of 'msr_index') into 'pdata'.
2165 * Returns 0 on success, non-0 otherwise.
2166 * Assumes vcpu_load() was already called.
2167 */
2168int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2169{
2170 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2171}
2172
9ba075a6
AK		 2173static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2174{
0bed3b56
SY		 2175 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2176
9ba075a6
AK		 2177 if (!msr_mtrr_valid(msr))
2178 return 1;
2179
0bed3b56
SY		 2180 if (msr == MSR_MTRRdefType)
2181 *pdata = vcpu->arch.mtrr_state.def_type +
2182 (vcpu->arch.mtrr_state.enabled << 10);
2183 else if (msr == MSR_MTRRfix64K_00000)
2184 *pdata = p[0];
2185 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2186 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2187 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2188 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2189 else if (msr == MSR_IA32_CR_PAT)
2190 *pdata = vcpu->arch.pat;
2191 else { /* Variable MTRRs */
2192 int idx, is_mtrr_mask;
2193 u64 *pt;
2194
2195 idx = (msr - 0x200) / 2;
2196 is_mtrr_mask = msr - 0x200 - 2 * idx;
2197 if (!is_mtrr_mask)
2198 pt =
2199 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2200 else
2201 pt =
2202 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2203 *pdata = *pt;
2204 }
2205
9ba075a6
AK		 2206 return 0;
2207}
2208
890ca9ae 2209static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2210{
2211 u64 data;
890ca9ae
HY		 2212 u64 mcg_cap = vcpu->arch.mcg_cap;
2213 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2214
2215 switch (msr) {
15c4a640
CO		 2216 case MSR_IA32_P5_MC_ADDR:
2217 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2218 data = 0;
2219 break;
15c4a640 2220 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2221 data = vcpu->arch.mcg_cap;
2222 break;
c7ac679c 2223 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2224 if (!(mcg_cap & MCG_CTL_P))
2225 return 1;
2226 data = vcpu->arch.mcg_ctl;
2227 break;
2228 case MSR_IA32_MCG_STATUS:
2229 data = vcpu->arch.mcg_status;
2230 break;
2231 default:
2232 if (msr >= MSR_IA32_MC0_CTL &&
2233 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2234 u32 offset = msr - MSR_IA32_MC0_CTL;
2235 data = vcpu->arch.mce_banks[offset];
2236 break;
2237 }
2238 return 1;
2239 }
2240 *pdata = data;
2241 return 0;
2242}
2243
55cd8e5a
GN		 2244static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2245{
2246 u64 data = 0;
2247 struct kvm *kvm = vcpu->kvm;
2248
2249 switch (msr) {
2250 case HV_X64_MSR_GUEST_OS_ID:
2251 data = kvm->arch.hv_guest_os_id;
2252 break;
2253 case HV_X64_MSR_HYPERCALL:
2254 data = kvm->arch.hv_hypercall;
2255 break;
2256 default:
a737f256 2257 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2258 return 1;
2259 }
2260
2261 *pdata = data;
2262 return 0;
2263}
2264
2265static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2266{
2267 u64 data = 0;
2268
2269 switch (msr) {
2270 case HV_X64_MSR_VP_INDEX: {
2271 int r;
2272 struct kvm_vcpu *v;
2273 kvm_for_each_vcpu(r, v, vcpu->kvm)
2274 if (v == vcpu)
2275 data = r;
2276 break;
2277 }
10388a07
GN		 2278 case HV_X64_MSR_EOI:
2279 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2280 case HV_X64_MSR_ICR:
2281 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2282 case HV_X64_MSR_TPR:
2283 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2284 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2285 data = vcpu->arch.hv_vapic;
2286 break;
55cd8e5a 2287 default:
a737f256 2288 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2289 return 1;
2290 }
2291 *pdata = data;
2292 return 0;
2293}
2294
890ca9ae
HY		 2295int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2296{
2297 u64 data;
2298
2299 switch (msr) {
890ca9ae 2300 case MSR_IA32_PLATFORM_ID:
15c4a640 2301 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2302 case MSR_IA32_DEBUGCTLMSR:
2303 case MSR_IA32_LASTBRANCHFROMIP:
2304 case MSR_IA32_LASTBRANCHTOIP:
2305 case MSR_IA32_LASTINTFROMIP:
2306 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2307 case MSR_K8_SYSCFG:
2308 case MSR_K7_HWCR:
61a6bd67 2309 case MSR_VM_HSAVE_PA:
9e699624 2310 case MSR_K7_EVNTSEL0:
1f3ee616 2311 case MSR_K7_PERFCTR0:
1fdbd48c 2312 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2313 case MSR_AMD64_NB_CFG:
f7c6d140 2314 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2315 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2316 data = 0;
2317 break;
5753785f
GN		 2318 case MSR_P6_PERFCTR0:
2319 case MSR_P6_PERFCTR1:
2320 case MSR_P6_EVNTSEL0:
2321 case MSR_P6_EVNTSEL1:
2322 if (kvm_pmu_msr(vcpu, msr))
2323 return kvm_pmu_get_msr(vcpu, msr, pdata);
2324 data = 0;
2325 break;
742bc670
MT		 2326 case MSR_IA32_UCODE_REV:
2327 data = 0x100000000ULL;
2328 break;
9ba075a6
AK		 2329 case MSR_MTRRcap:
2330 data = 0x500 | KVM_NR_VAR_MTRR;
2331 break;
2332 case 0x200 ... 0x2ff:
2333 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2334 case 0xcd: /* fsb frequency */
2335 data = 3;
2336 break;
7b914098
JS		 2337 /*
2338 * MSR_EBC_FREQUENCY_ID
2339 * Conservative value valid for even the basic CPU models.
2340 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2341 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2342 * and 266MHz for model 3, or 4. Set Core Clock
2343 * Frequency to System Bus Frequency Ratio to 1 (bits
2344 * 31:24) even though these are only valid for CPU
2345 * models > 2, however guests may end up dividing or
2346 * multiplying by zero otherwise.
2347 */
2348 case MSR_EBC_FREQUENCY_ID:
2349 data = 1 << 24;
2350 break;
15c4a640
CO		 2351 case MSR_IA32_APICBASE:
2352 data = kvm_get_apic_base(vcpu);
2353 break;
0105d1a5
GN		 2354 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2355 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2356 break;
a3e06bbe
LJ		 2357 case MSR_IA32_TSCDEADLINE:
2358 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2359 break;
ba904635
WA		 2360 case MSR_IA32_TSC_ADJUST:
2361 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2362 break;
15c4a640 2363 case MSR_IA32_MISC_ENABLE:
ad312c7c 2364 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2365 break;
847f0ad8
AG		 2366 case MSR_IA32_PERF_STATUS:
2367 /* TSC increment by tick */
2368 data = 1000ULL;
2369 /* CPU multiplier */
2370 data |= (((uint64_t)4ULL) << 40);
2371 break;
15c4a640 2372 case MSR_EFER:
f6801dff 2373 data = vcpu->arch.efer;
15c4a640 2374 break;
18068523 2375 case MSR_KVM_WALL_CLOCK:
11c6bffa 2376 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2377 data = vcpu->kvm->arch.wall_clock;
2378 break;
2379 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2380 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2381 data = vcpu->arch.time;
2382 break;
344d9588
GN		 2383 case MSR_KVM_ASYNC_PF_EN:
2384 data = vcpu->arch.apf.msr_val;
2385 break;
c9aaa895
GC		 2386 case MSR_KVM_STEAL_TIME:
2387 data = vcpu->arch.st.msr_val;
2388 break;
1d92128f
MT		 2389 case MSR_KVM_PV_EOI_EN:
2390 data = vcpu->arch.pv_eoi.msr_val;
2391 break;
890ca9ae
HY		 2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
2394 case MSR_IA32_MCG_CAP:
2395 case MSR_IA32_MCG_CTL:
2396 case MSR_IA32_MCG_STATUS:
2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2398 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2399 case MSR_K7_CLK_CTL:
2400 /*
2401 * Provide expected ramp-up count for K7. All other
2402 * are set to zero, indicating minimum divisors for
2403 * every field.
2404 *
2405 * This prevents guest kernels on AMD host with CPU
2406 * type 6, model 8 and higher from exploding due to
2407 * the rdmsr failing.
2408 */
2409 data = 0x20000000;
2410 break;
55cd8e5a
GN		 2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2412 if (kvm_hv_msr_partition_wide(msr)) {
2413 int r;
2414 mutex_lock(&vcpu->kvm->lock);
2415 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2416 mutex_unlock(&vcpu->kvm->lock);
2417 return r;
2418 } else
2419 return get_msr_hyperv(vcpu, msr, pdata);
2420 break;
91c9c3ed 2421 case MSR_IA32_BBL_CR_CTL3:
2422 /* This legacy MSR exists but isn't fully documented in current
2423 * silicon. It is however accessed by winxp in very narrow
2424 * scenarios where it sets bit #19, itself documented as
2425 * a "reserved" bit. Best effort attempt to source coherent
2426 * read data here should the balance of the register be
2427 * interpreted by the guest:
2428 *
2429 * L2 cache control register 3: 64GB range, 256KB size,
2430 * enabled, latency 0x1, configured
2431 */
2432 data = 0xbe702111;
2433 break;
2b036c6b
BO		 2434 case MSR_AMD64_OSVW_ID_LENGTH:
2435 if (!guest_cpuid_has_osvw(vcpu))
2436 return 1;
2437 data = vcpu->arch.osvw.length;
2438 break;
2439 case MSR_AMD64_OSVW_STATUS:
2440 if (!guest_cpuid_has_osvw(vcpu))
2441 return 1;
2442 data = vcpu->arch.osvw.status;
2443 break;
15c4a640 2444 default:
f5132b01
GN		 2445 if (kvm_pmu_msr(vcpu, msr))
2446 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2447 if (!ignore_msrs) {
a737f256 2448 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2449 return 1;
2450 } else {
a737f256 2451 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2452 data = 0;
2453 }
2454 break;
15c4a640
CO		 2455 }
2456 *pdata = data;
2457 return 0;
2458}
2459EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2460
313a3dc7
CO		 2461/*
2462 * Read or write a bunch of msrs. All parameters are kernel addresses.
2463 *
2464 * @return number of msrs set successfully.
2465 */
2466static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2467 struct kvm_msr_entry *entries,
2468 int (*do_msr)(struct kvm_vcpu *vcpu,
2469 unsigned index, u64 *data))
2470{
f656ce01 2471 int i, idx;
313a3dc7 2472
f656ce01 2473 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2474 for (i = 0; i < msrs->nmsrs; ++i)
2475 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2476 break;
f656ce01 2477 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2478
313a3dc7
CO		 2479 return i;
2480}
2481
2482/*
2483 * Read or write a bunch of msrs. Parameters are user addresses.
2484 *
2485 * @return number of msrs set successfully.
2486 */
2487static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2488 int (*do_msr)(struct kvm_vcpu *vcpu,
2489 unsigned index, u64 *data),
2490 int writeback)
2491{
2492 struct kvm_msrs msrs;
2493 struct kvm_msr_entry *entries;
2494 int r, n;
2495 unsigned size;
2496
2497 r = -EFAULT;
2498 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2499 goto out;
2500
2501 r = -E2BIG;
2502 if (msrs.nmsrs >= MAX_IO_MSRS)
2503 goto out;
2504
313a3dc7 2505 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2506 entries = memdup_user(user_msrs->entries, size);
2507 if (IS_ERR(entries)) {
2508 r = PTR_ERR(entries);
313a3dc7 2509 goto out;
ff5c2c03 2510 }
313a3dc7
CO		 2511
2512 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2513 if (r < 0)
2514 goto out_free;
2515
2516 r = -EFAULT;
2517 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2518 goto out_free;
2519
2520 r = n;
2521
2522out_free:
7a73c028 2523 kfree(entries);
313a3dc7
CO		 2524out:
2525 return r;
2526}
2527
018d00d2
ZX		 2528int kvm_dev_ioctl_check_extension(long ext)
2529{
2530 int r;
2531
2532 switch (ext) {
2533 case KVM_CAP_IRQCHIP:
2534 case KVM_CAP_HLT:
2535 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2536 case KVM_CAP_SET_TSS_ADDR:
07716717 2537 case KVM_CAP_EXT_CPUID:
9c15bb1d 2538 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2539 case KVM_CAP_CLOCKSOURCE:
7837699f 2540 case KVM_CAP_PIT:
a28e4f5a 2541 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2542 case KVM_CAP_MP_STATE:
ed848624 2543 case KVM_CAP_SYNC_MMU:
a355c85c 2544 case KVM_CAP_USER_NMI:
52d939a0 2545 case KVM_CAP_REINJECT_CONTROL:
4925663a 2546 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2547 case KVM_CAP_IRQFD:
d34e6b17 2548 case KVM_CAP_IOEVENTFD:
c5ff41ce 2549 case KVM_CAP_PIT2:
e9f42757 2550 case KVM_CAP_PIT_STATE2:
b927a3ce 2551 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2552 case KVM_CAP_XEN_HVM:
afbcf7ab 2553 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2554 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2555 case KVM_CAP_HYPERV:
10388a07 2556 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2557 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2558 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2559 case KVM_CAP_DEBUGREGS:
d2be1651 2560 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2561 case KVM_CAP_XSAVE:
344d9588 2562 case KVM_CAP_ASYNC_PF:
92a1f12d 2563 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2564 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2565 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2566#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2567 case KVM_CAP_ASSIGN_DEV_IRQ:
2568 case KVM_CAP_PCI_2_3:
2569#endif
018d00d2
ZX		 2570 r = 1;
2571 break;
542472b5
LV		 2572 case KVM_CAP_COALESCED_MMIO:
2573 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2574 break;
774ead3a
AK		 2575 case KVM_CAP_VAPIC:
2576 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2577 break;
f725230a 2578 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2579 r = KVM_SOFT_MAX_VCPUS;
2580 break;
2581 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2582 r = KVM_MAX_VCPUS;
2583 break;
a988b910 2584 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2585 r = KVM_USER_MEM_SLOTS;
a988b910 2586 break;
a68a6a72
MT		 2587 case KVM_CAP_PV_MMU: /* obsolete */
2588 r = 0;
2f333bcb 2589 break;
4cee4b72 2590#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2591 case KVM_CAP_IOMMU:
a1b60c1c 2592 r = iommu_present(&pci_bus_type);
62c476c7 2593 break;
4cee4b72 2594#endif
890ca9ae
HY		 2595 case KVM_CAP_MCE:
2596 r = KVM_MAX_MCE_BANKS;
2597 break;
2d5b5a66
SY		 2598 case KVM_CAP_XCRS:
2599 r = cpu_has_xsave;
2600 break;
92a1f12d
JR		 2601 case KVM_CAP_TSC_CONTROL:
2602 r = kvm_has_tsc_control;
2603 break;
4d25a066
JK		 2604 case KVM_CAP_TSC_DEADLINE_TIMER:
2605 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2606 break;
018d00d2
ZX		 2607 default:
2608 r = 0;
2609 break;
2610 }
2611 return r;
2612
2613}
2614
043405e1
CO		 2615long kvm_arch_dev_ioctl(struct file *filp,
2616 unsigned int ioctl, unsigned long arg)
2617{
2618 void __user *argp = (void __user *)arg;
2619 long r;
2620
2621 switch (ioctl) {
2622 case KVM_GET_MSR_INDEX_LIST: {
2623 struct kvm_msr_list __user *user_msr_list = argp;
2624 struct kvm_msr_list msr_list;
2625 unsigned n;
2626
2627 r = -EFAULT;
2628 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2629 goto out;
2630 n = msr_list.nmsrs;
2631 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2632 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2633 goto out;
2634 r = -E2BIG;
e125e7b6 2635 if (n < msr_list.nmsrs)
043405e1
CO		 2636 goto out;
2637 r = -EFAULT;
2638 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2639 num_msrs_to_save * sizeof(u32)))
2640 goto out;
e125e7b6 2641 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2642 &emulated_msrs,
2643 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2644 goto out;
2645 r = 0;
2646 break;
2647 }
9c15bb1d
BP		 2648 case KVM_GET_SUPPORTED_CPUID:
2649 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2650 struct kvm_cpuid2 __user *cpuid_arg = argp;
2651 struct kvm_cpuid2 cpuid;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2655 goto out;
9c15bb1d
BP		 2656
2657 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2658 ioctl);
674eea0f
AK		 2659 if (r)
2660 goto out;
2661
2662 r = -EFAULT;
2663 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2664 goto out;
2665 r = 0;
2666 break;
2667 }
890ca9ae
HY		 2668 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2669 u64 mce_cap;
2670
2671 mce_cap = KVM_MCE_CAP_SUPPORTED;
2672 r = -EFAULT;
2673 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2674 goto out;
2675 r = 0;
2676 break;
2677 }
043405e1
CO		 2678 default:
2679 r = -EINVAL;
2680 }
2681out:
2682 return r;
2683}
2684
f5f48ee1
SY		 2685static void wbinvd_ipi(void *garbage)
2686{
2687 wbinvd();
2688}
2689
2690static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2691{
e0f0bbc5 2692 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2693}
2694
313a3dc7
CO		 2695void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2696{
f5f48ee1
SY		 2697 /* Address WBINVD may be executed by guest */
2698 if (need_emulate_wbinvd(vcpu)) {
2699 if (kvm_x86_ops->has_wbinvd_exit())
2700 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2701 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2702 smp_call_function_single(vcpu->cpu,
2703 wbinvd_ipi, NULL, 1);
2704 }
2705
313a3dc7 2706 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2707
0dd6a6ed
ZA		 2708 /* Apply any externally detected TSC adjustments (due to suspend) */
2709 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2710 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2711 vcpu->arch.tsc_offset_adjustment = 0;
2712 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2713 }
8f6055cb 2714
48434c20 2715 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2716 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2717 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2718 if (tsc_delta < 0)
2719 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2720 if (check_tsc_unstable()) {
b183aa58
ZA		 2721 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2722 vcpu->arch.last_guest_tsc);
2723 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2724 vcpu->arch.tsc_catchup = 1;
c285545f 2725 }
d98d07ca
MT		 2726 /*
2727 * On a host with synchronized TSC, there is no need to update
2728 * kvmclock on vcpu->cpu migration
2729 */
2730 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2731 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2732 if (vcpu->cpu != cpu)
2733 kvm_migrate_timers(vcpu);
e48672fa 2734 vcpu->cpu = cpu;
6b7d7e76 2735 }
c9aaa895
GC		 2736
2737 accumulate_steal_time(vcpu);
2738 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2739}
2740
2741void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2742{
02daab21 2743 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2744 kvm_put_guest_fpu(vcpu);
6f526ec5 2745 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2746}
2747
313a3dc7
CO		 2748static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2749 struct kvm_lapic_state *s)
2750{
5a71785d 2751 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2752 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2753
2754 return 0;
2755}
2756
2757static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2758 struct kvm_lapic_state *s)
2759{
64eb0620 2760 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2761 update_cr8_intercept(vcpu);
313a3dc7
CO		 2762
2763 return 0;
2764}
2765
f77bc6a4
ZX		 2766static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2767 struct kvm_interrupt *irq)
2768{
02cdb50f 2769 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2770 return -EINVAL;
2771 if (irqchip_in_kernel(vcpu->kvm))
2772 return -ENXIO;
f77bc6a4 2773
66fd3f7f 2774 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2775 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2776
f77bc6a4
ZX		 2777 return 0;
2778}
2779
c4abb7c9
JK		 2780static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2781{
c4abb7c9 2782 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2783
2784 return 0;
2785}
2786
b209749f
AK		 2787static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2788 struct kvm_tpr_access_ctl *tac)
2789{
2790 if (tac->flags)
2791 return -EINVAL;
2792 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2793 return 0;
2794}
2795
890ca9ae
HY		 2796static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2797 u64 mcg_cap)
2798{
2799 int r;
2800 unsigned bank_num = mcg_cap & 0xff, bank;
2801
2802 r = -EINVAL;
a9e38c3e 2803 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2804 goto out;
2805 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2806 goto out;
2807 r = 0;
2808 vcpu->arch.mcg_cap = mcg_cap;
2809 /* Init IA32_MCG_CTL to all 1s */
2810 if (mcg_cap & MCG_CTL_P)
2811 vcpu->arch.mcg_ctl = ~(u64)0;
2812 /* Init IA32_MCi_CTL to all 1s */
2813 for (bank = 0; bank < bank_num; bank++)
2814 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2815out:
2816 return r;
2817}
2818
2819static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2820 struct kvm_x86_mce *mce)
2821{
2822 u64 mcg_cap = vcpu->arch.mcg_cap;
2823 unsigned bank_num = mcg_cap & 0xff;
2824 u64 *banks = vcpu->arch.mce_banks;
2825
2826 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2827 return -EINVAL;
2828 /*
2829 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2830 * reporting is disabled
2831 */
2832 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2833 vcpu->arch.mcg_ctl != ~(u64)0)
2834 return 0;
2835 banks += 4 * mce->bank;
2836 /*
2837 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2838 * reporting is disabled for the bank
2839 */
2840 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2841 return 0;
2842 if (mce->status & MCI_STATUS_UC) {
2843 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2844 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2845 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2846 return 0;
2847 }
2848 if (banks[1] & MCI_STATUS_VAL)
2849 mce->status |= MCI_STATUS_OVER;
2850 banks[2] = mce->addr;
2851 banks[3] = mce->misc;
2852 vcpu->arch.mcg_status = mce->mcg_status;
2853 banks[1] = mce->status;
2854 kvm_queue_exception(vcpu, MC_VECTOR);
2855 } else if (!(banks[1] & MCI_STATUS_VAL)
2856 || !(banks[1] & MCI_STATUS_UC)) {
2857 if (banks[1] & MCI_STATUS_VAL)
2858 mce->status |= MCI_STATUS_OVER;
2859 banks[2] = mce->addr;
2860 banks[3] = mce->misc;
2861 banks[1] = mce->status;
2862 } else
2863 banks[1] |= MCI_STATUS_OVER;
2864 return 0;
2865}
2866
3cfc3092
JK		 2867static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2868 struct kvm_vcpu_events *events)
2869{
7460fb4a 2870 process_nmi(vcpu);
03b82a30
JK		 2871 events->exception.injected =
2872 vcpu->arch.exception.pending &&
2873 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2874 events->exception.nr = vcpu->arch.exception.nr;
2875 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2876 events->exception.pad = 0;
3cfc3092
JK		 2877 events->exception.error_code = vcpu->arch.exception.error_code;
2878
03b82a30
JK		 2879 events->interrupt.injected =
2880 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2881 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2882 events->interrupt.soft = 0;
48005f64
JK		 2883 events->interrupt.shadow =
2884 kvm_x86_ops->get_interrupt_shadow(vcpu,
2885 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2886
2887 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2888 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2889 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2890 events->nmi.pad = 0;
3cfc3092 2891
66450a21 2892 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2893
dab4b911 2894 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2895 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2896 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2897}
2898
2899static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2900 struct kvm_vcpu_events *events)
2901{
dab4b911 2902 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2903 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2904 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2905 return -EINVAL;
2906
7460fb4a 2907 process_nmi(vcpu);
3cfc3092
JK		 2908 vcpu->arch.exception.pending = events->exception.injected;
2909 vcpu->arch.exception.nr = events->exception.nr;
2910 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2911 vcpu->arch.exception.error_code = events->exception.error_code;
2912
2913 vcpu->arch.interrupt.pending = events->interrupt.injected;
2914 vcpu->arch.interrupt.nr = events->interrupt.nr;
2915 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2916 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2917 kvm_x86_ops->set_interrupt_shadow(vcpu,
2918 events->interrupt.shadow);
3cfc3092
JK		 2919
2920 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2921 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2922 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2923 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2924
66450a21
JK		 2925 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2926 kvm_vcpu_has_lapic(vcpu))
2927 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2928
3842d135
AK		 2929 kvm_make_request(KVM_REQ_EVENT, vcpu);
2930
3cfc3092
JK		 2931 return 0;
2932}
2933
a1efbe77
JK		 2934static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2935 struct kvm_debugregs *dbgregs)
2936{
a1efbe77
JK		 2937 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2938 dbgregs->dr6 = vcpu->arch.dr6;
2939 dbgregs->dr7 = vcpu->arch.dr7;
2940 dbgregs->flags = 0;
97e69aa6 2941 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2942}
2943
2944static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2945 struct kvm_debugregs *dbgregs)
2946{
2947 if (dbgregs->flags)
2948 return -EINVAL;
2949
a1efbe77
JK		 2950 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2951 vcpu->arch.dr6 = dbgregs->dr6;
2952 vcpu->arch.dr7 = dbgregs->dr7;
2953
a1efbe77
JK		 2954 return 0;
2955}
2956
2d5b5a66
SY		 2957static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2958 struct kvm_xsave *guest_xsave)
2959{
4344ee98 2960 if (cpu_has_xsave) {
2d5b5a66
SY		 2961 memcpy(guest_xsave->region,
2962 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 2963 vcpu->arch.guest_xstate_size);
2964 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
2965 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
2966 } else {
2d5b5a66
SY		 2967 memcpy(guest_xsave->region,
2968 &vcpu->arch.guest_fpu.state->fxsave,
2969 sizeof(struct i387_fxsave_struct));
2970 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2971 XSTATE_FPSSE;
2972 }
2973}
2974
2975static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2976 struct kvm_xsave *guest_xsave)
2977{
2978 u64 xstate_bv =
2979 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2980
d7876f1b
PB		 2981 if (cpu_has_xsave) {
2982 /*
2983 * Here we allow setting states that are not present in
2984 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
2985 * with old userspace.
2986 */
2987 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
2988 return -EINVAL;
2989 if (xstate_bv & ~host_xcr0)
2990 return -EINVAL;
2d5b5a66 2991 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 2992 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 2993 } else {
2d5b5a66
SY		 2994 if (xstate_bv & ~XSTATE_FPSSE)
2995 return -EINVAL;
2996 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2997 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2998 }
2999 return 0;
3000}
3001
3002static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3003 struct kvm_xcrs *guest_xcrs)
3004{
3005 if (!cpu_has_xsave) {
3006 guest_xcrs->nr_xcrs = 0;
3007 return;
3008 }
3009
3010 guest_xcrs->nr_xcrs = 1;
3011 guest_xcrs->flags = 0;
3012 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3013 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3014}
3015
3016static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3017 struct kvm_xcrs *guest_xcrs)
3018{
3019 int i, r = 0;
3020
3021 if (!cpu_has_xsave)
3022 return -EINVAL;
3023
3024 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3025 return -EINVAL;
3026
3027 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3028 /* Only support XCR0 currently */
c67a04cb 3029 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3030 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3031 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3032 break;
3033 }
3034 if (r)
3035 r = -EINVAL;
3036 return r;
3037}
3038
1c0b28c2
EM		 3039/*
3040 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3041 * stopped by the hypervisor. This function will be called from the host only.
3042 * EINVAL is returned when the host attempts to set the flag for a guest that
3043 * does not support pv clocks.
3044 */
3045static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3046{
0b79459b 3047 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3048 return -EINVAL;
51d59c6b 3049 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3050 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3051 return 0;
3052}
3053
313a3dc7
CO		 3054long kvm_arch_vcpu_ioctl(struct file *filp,
3055 unsigned int ioctl, unsigned long arg)
3056{
3057 struct kvm_vcpu *vcpu = filp->private_data;
3058 void __user *argp = (void __user *)arg;
3059 int r;
d1ac91d8
AK		 3060 union {
3061 struct kvm_lapic_state *lapic;
3062 struct kvm_xsave *xsave;
3063 struct kvm_xcrs *xcrs;
3064 void *buffer;
3065 } u;
3066
3067 u.buffer = NULL;
313a3dc7
CO		 3068 switch (ioctl) {
3069 case KVM_GET_LAPIC: {
2204ae3c
MT		 3070 r = -EINVAL;
3071 if (!vcpu->arch.apic)
3072 goto out;
d1ac91d8 3073 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3074
b772ff36 3075 r = -ENOMEM;
d1ac91d8 3076 if (!u.lapic)
b772ff36 3077 goto out;
d1ac91d8 3078 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3079 if (r)
3080 goto out;
3081 r = -EFAULT;
d1ac91d8 3082 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3083 goto out;
3084 r = 0;
3085 break;
3086 }
3087 case KVM_SET_LAPIC: {
2204ae3c
MT		 3088 r = -EINVAL;
3089 if (!vcpu->arch.apic)
3090 goto out;
ff5c2c03 3091 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3092 if (IS_ERR(u.lapic))
3093 return PTR_ERR(u.lapic);
ff5c2c03 3094
d1ac91d8 3095 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3096 break;
3097 }
f77bc6a4
ZX		 3098 case KVM_INTERRUPT: {
3099 struct kvm_interrupt irq;
3100
3101 r = -EFAULT;
3102 if (copy_from_user(&irq, argp, sizeof irq))
3103 goto out;
3104 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3105 break;
3106 }
c4abb7c9
JK		 3107 case KVM_NMI: {
3108 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3109 break;
3110 }
313a3dc7
CO		 3111 case KVM_SET_CPUID: {
3112 struct kvm_cpuid __user *cpuid_arg = argp;
3113 struct kvm_cpuid cpuid;
3114
3115 r = -EFAULT;
3116 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3117 goto out;
3118 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3119 break;
3120 }
07716717
DK		 3121 case KVM_SET_CPUID2: {
3122 struct kvm_cpuid2 __user *cpuid_arg = argp;
3123 struct kvm_cpuid2 cpuid;
3124
3125 r = -EFAULT;
3126 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3127 goto out;
3128 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3129 cpuid_arg->entries);
07716717
DK		 3130 break;
3131 }
3132 case KVM_GET_CPUID2: {
3133 struct kvm_cpuid2 __user *cpuid_arg = argp;
3134 struct kvm_cpuid2 cpuid;
3135
3136 r = -EFAULT;
3137 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3138 goto out;
3139 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3140 cpuid_arg->entries);
07716717
DK		 3141 if (r)
3142 goto out;
3143 r = -EFAULT;
3144 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3145 goto out;
3146 r = 0;
3147 break;
3148 }
313a3dc7
CO		 3149 case KVM_GET_MSRS:
3150 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3151 break;
3152 case KVM_SET_MSRS:
3153 r = msr_io(vcpu, argp, do_set_msr, 0);
3154 break;
b209749f
AK		 3155 case KVM_TPR_ACCESS_REPORTING: {
3156 struct kvm_tpr_access_ctl tac;
3157
3158 r = -EFAULT;
3159 if (copy_from_user(&tac, argp, sizeof tac))
3160 goto out;
3161 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3162 if (r)
3163 goto out;
3164 r = -EFAULT;
3165 if (copy_to_user(argp, &tac, sizeof tac))
3166 goto out;
3167 r = 0;
3168 break;
3169 };
b93463aa
AK		 3170 case KVM_SET_VAPIC_ADDR: {
3171 struct kvm_vapic_addr va;
3172
3173 r = -EINVAL;
3174 if (!irqchip_in_kernel(vcpu->kvm))
3175 goto out;
3176 r = -EFAULT;
3177 if (copy_from_user(&va, argp, sizeof va))
3178 goto out;
3179 r = 0;
3180 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3181 break;
3182 }
890ca9ae
HY		 3183 case KVM_X86_SETUP_MCE: {
3184 u64 mcg_cap;
3185
3186 r = -EFAULT;
3187 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3188 goto out;
3189 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3190 break;
3191 }
3192 case KVM_X86_SET_MCE: {
3193 struct kvm_x86_mce mce;
3194
3195 r = -EFAULT;
3196 if (copy_from_user(&mce, argp, sizeof mce))
3197 goto out;
3198 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3199 break;
3200 }
3cfc3092
JK		 3201 case KVM_GET_VCPU_EVENTS: {
3202 struct kvm_vcpu_events events;
3203
3204 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3205
3206 r = -EFAULT;
3207 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3208 break;
3209 r = 0;
3210 break;
3211 }
3212 case KVM_SET_VCPU_EVENTS: {
3213 struct kvm_vcpu_events events;
3214
3215 r = -EFAULT;
3216 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3217 break;
3218
3219 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3220 break;
3221 }
a1efbe77
JK		 3222 case KVM_GET_DEBUGREGS: {
3223 struct kvm_debugregs dbgregs;
3224
3225 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3226
3227 r = -EFAULT;
3228 if (copy_to_user(argp, &dbgregs,
3229 sizeof(struct kvm_debugregs)))
3230 break;
3231 r = 0;
3232 break;
3233 }
3234 case KVM_SET_DEBUGREGS: {
3235 struct kvm_debugregs dbgregs;
3236
3237 r = -EFAULT;
3238 if (copy_from_user(&dbgregs, argp,
3239 sizeof(struct kvm_debugregs)))
3240 break;
3241
3242 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3243 break;
3244 }
2d5b5a66 3245 case KVM_GET_XSAVE: {
d1ac91d8 3246 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3247 r = -ENOMEM;
d1ac91d8 3248 if (!u.xsave)
2d5b5a66
SY		 3249 break;
3250
d1ac91d8 3251 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3252
3253 r = -EFAULT;
d1ac91d8 3254 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3255 break;
3256 r = 0;
3257 break;
3258 }
3259 case KVM_SET_XSAVE: {
ff5c2c03 3260 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3261 if (IS_ERR(u.xsave))
3262 return PTR_ERR(u.xsave);
2d5b5a66 3263
d1ac91d8 3264 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3265 break;
3266 }
3267 case KVM_GET_XCRS: {
d1ac91d8 3268 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3269 r = -ENOMEM;
d1ac91d8 3270 if (!u.xcrs)
2d5b5a66
SY		 3271 break;
3272
d1ac91d8 3273 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3274
3275 r = -EFAULT;
d1ac91d8 3276 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3277 sizeof(struct kvm_xcrs)))
3278 break;
3279 r = 0;
3280 break;
3281 }
3282 case KVM_SET_XCRS: {
ff5c2c03 3283 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3284 if (IS_ERR(u.xcrs))
3285 return PTR_ERR(u.xcrs);
2d5b5a66 3286
d1ac91d8 3287 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3288 break;
3289 }
92a1f12d
JR		 3290 case KVM_SET_TSC_KHZ: {
3291 u32 user_tsc_khz;
3292
3293 r = -EINVAL;
92a1f12d
JR		 3294 user_tsc_khz = (u32)arg;
3295
3296 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3297 goto out;
3298
cc578287
ZA		 3299 if (user_tsc_khz == 0)
3300 user_tsc_khz = tsc_khz;
3301
3302 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3303
3304 r = 0;
3305 goto out;
3306 }
3307 case KVM_GET_TSC_KHZ: {
cc578287 3308 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3309 goto out;
3310 }
1c0b28c2
EM		 3311 case KVM_KVMCLOCK_CTRL: {
3312 r = kvm_set_guest_paused(vcpu);
3313 goto out;
3314 }
313a3dc7
CO		 3315 default:
3316 r = -EINVAL;
3317 }
3318out:
d1ac91d8 3319 kfree(u.buffer);
313a3dc7
CO		 3320 return r;
3321}
3322
5b1c1493
CO		 3323int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3324{
3325 return VM_FAULT_SIGBUS;
3326}
3327
1fe779f8
CO		 3328static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3329{
3330 int ret;
3331
3332 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3333 return -EINVAL;
1fe779f8
CO		 3334 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3335 return ret;
3336}
3337
b927a3ce
SY		 3338static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3339 u64 ident_addr)
3340{
3341 kvm->arch.ept_identity_map_addr = ident_addr;
3342 return 0;
3343}
3344
1fe779f8
CO		 3345static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3346 u32 kvm_nr_mmu_pages)
3347{
3348 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3349 return -EINVAL;
3350
79fac95e 3351 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3352
3353 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3354 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3355
79fac95e 3356 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3357 return 0;
3358}
3359
3360static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3361{
39de71ec 3362 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3363}
3364
1fe779f8
CO		 3365static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3366{
3367 int r;
3368
3369 r = 0;
3370 switch (chip->chip_id) {
3371 case KVM_IRQCHIP_PIC_MASTER:
3372 memcpy(&chip->chip.pic,
3373 &pic_irqchip(kvm)->pics[0],
3374 sizeof(struct kvm_pic_state));
3375 break;
3376 case KVM_IRQCHIP_PIC_SLAVE:
3377 memcpy(&chip->chip.pic,
3378 &pic_irqchip(kvm)->pics[1],
3379 sizeof(struct kvm_pic_state));
3380 break;
3381 case KVM_IRQCHIP_IOAPIC:
eba0226b 3382 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3383 break;
3384 default:
3385 r = -EINVAL;
3386 break;
3387 }
3388 return r;
3389}
3390
3391static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3392{
3393 int r;
3394
3395 r = 0;
3396 switch (chip->chip_id) {
3397 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3398 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3399 memcpy(&pic_irqchip(kvm)->pics[0],
3400 &chip->chip.pic,
3401 sizeof(struct kvm_pic_state));
f4f51050 3402 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3403 break;
3404 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3405 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3406 memcpy(&pic_irqchip(kvm)->pics[1],
3407 &chip->chip.pic,
3408 sizeof(struct kvm_pic_state));
f4f51050 3409 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3410 break;
3411 case KVM_IRQCHIP_IOAPIC:
eba0226b 3412 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3413 break;
3414 default:
3415 r = -EINVAL;
3416 break;
3417 }
3418 kvm_pic_update_irq(pic_irqchip(kvm));
3419 return r;
3420}
3421
e0f63cb9
SY		 3422static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3423{
3424 int r = 0;
3425
894a9c55 3426 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3427 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3428 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3429 return r;
3430}
3431
3432static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3433{
3434 int r = 0;
3435
894a9c55 3436 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3437 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3438 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3439 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3440 return r;
3441}
3442
3443static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3444{
3445 int r = 0;
3446
3447 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3448 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3449 sizeof(ps->channels));
3450 ps->flags = kvm->arch.vpit->pit_state.flags;
3451 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3452 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3453 return r;
3454}
3455
3456static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3457{
3458 int r = 0, start = 0;
3459 u32 prev_legacy, cur_legacy;
3460 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3461 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3462 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3463 if (!prev_legacy && cur_legacy)
3464 start = 1;
3465 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3466 sizeof(kvm->arch.vpit->pit_state.channels));
3467 kvm->arch.vpit->pit_state.flags = ps->flags;
3468 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3469 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3470 return r;
3471}
3472
52d939a0
MT		 3473static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3474 struct kvm_reinject_control *control)
3475{
3476 if (!kvm->arch.vpit)
3477 return -ENXIO;
894a9c55 3478 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3479 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3480 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3481 return 0;
3482}
3483
95d4c16c 3484/**
60c34612
TY		 3485 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3486 * @kvm: kvm instance
3487 * @log: slot id and address to which we copy the log
95d4c16c 3488 *
60c34612
TY		 3489 * We need to keep it in mind that VCPU threads can write to the bitmap
3490 * concurrently. So, to avoid losing data, we keep the following order for
3491 * each bit:
95d4c16c 3492 *
60c34612
TY		 3493 * 1. Take a snapshot of the bit and clear it if needed.
3494 * 2. Write protect the corresponding page.
3495 * 3. Flush TLB's if needed.
3496 * 4. Copy the snapshot to the userspace.
95d4c16c 3497 *
60c34612
TY		 3498 * Between 2 and 3, the guest may write to the page using the remaining TLB
3499 * entry. This is not a problem because the page will be reported dirty at
3500 * step 4 using the snapshot taken before and step 3 ensures that successive
3501 * writes will be logged for the next call.
5bb064dc 3502 */
60c34612 3503int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3504{
7850ac54 3505 int r;
5bb064dc 3506 struct kvm_memory_slot *memslot;
60c34612
TY		 3507 unsigned long n, i;
3508 unsigned long *dirty_bitmap;
3509 unsigned long *dirty_bitmap_buffer;
3510 bool is_dirty = false;
5bb064dc 3511
79fac95e 3512 mutex_lock(&kvm->slots_lock);
5bb064dc 3513
b050b015 3514 r = -EINVAL;
bbacc0c1 3515 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3516 goto out;
3517
28a37544 3518 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3519
3520 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3521 r = -ENOENT;
60c34612 3522 if (!dirty_bitmap)
b050b015
MT		 3523 goto out;
3524
87bf6e7d 3525 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3526
60c34612
TY		 3527 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3528 memset(dirty_bitmap_buffer, 0, n);
b050b015 3529
60c34612 3530 spin_lock(&kvm->mmu_lock);
b050b015 3531
60c34612
TY		 3532 for (i = 0; i < n / sizeof(long); i++) {
3533 unsigned long mask;
3534 gfn_t offset;
cdfca7b3 3535
60c34612
TY		 3536 if (!dirty_bitmap[i])
3537 continue;
b050b015 3538
60c34612 3539 is_dirty = true;
914ebccd 3540
60c34612
TY		 3541 mask = xchg(&dirty_bitmap[i], 0);
3542 dirty_bitmap_buffer[i] = mask;
edde99ce 3543
60c34612
TY		 3544 offset = i * BITS_PER_LONG;
3545 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3546 }
60c34612
TY		 3547 if (is_dirty)
3548 kvm_flush_remote_tlbs(kvm);
3549
3550 spin_unlock(&kvm->mmu_lock);
3551
3552 r = -EFAULT;
3553 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3554 goto out;
b050b015 3555
5bb064dc
ZX		 3556 r = 0;
3557out:
79fac95e 3558 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3559 return r;
3560}
3561
aa2fbe6d
YZ		 3562int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3563 bool line_status)
23d43cf9
CD		 3564{
3565 if (!irqchip_in_kernel(kvm))
3566 return -ENXIO;
3567
3568 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3569 irq_event->irq, irq_event->level,
3570 line_status);
23d43cf9
CD		 3571 return 0;
3572}
3573
1fe779f8
CO		 3574long kvm_arch_vm_ioctl(struct file *filp,
3575 unsigned int ioctl, unsigned long arg)
3576{
3577 struct kvm *kvm = filp->private_data;
3578 void __user *argp = (void __user *)arg;
367e1319 3579 int r = -ENOTTY;
f0d66275
DH		 3580 /*
3581 * This union makes it completely explicit to gcc-3.x
3582 * that these two variables' stack usage should be
3583 * combined, not added together.
3584 */
3585 union {
3586 struct kvm_pit_state ps;
e9f42757 3587 struct kvm_pit_state2 ps2;
c5ff41ce 3588 struct kvm_pit_config pit_config;
f0d66275 3589 } u;
1fe779f8
CO		 3590
3591 switch (ioctl) {
3592 case KVM_SET_TSS_ADDR:
3593 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3594 break;
b927a3ce
SY		 3595 case KVM_SET_IDENTITY_MAP_ADDR: {
3596 u64 ident_addr;
3597
3598 r = -EFAULT;
3599 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3600 goto out;
3601 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3602 break;
3603 }
1fe779f8
CO		 3604 case KVM_SET_NR_MMU_PAGES:
3605 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3606 break;
3607 case KVM_GET_NR_MMU_PAGES:
3608 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3609 break;
3ddea128
MT		 3610 case KVM_CREATE_IRQCHIP: {
3611 struct kvm_pic *vpic;
3612
3613 mutex_lock(&kvm->lock);
3614 r = -EEXIST;
3615 if (kvm->arch.vpic)
3616 goto create_irqchip_unlock;
3e515705
AK		 3617 r = -EINVAL;
3618 if (atomic_read(&kvm->online_vcpus))
3619 goto create_irqchip_unlock;
1fe779f8 3620 r = -ENOMEM;
3ddea128
MT		 3621 vpic = kvm_create_pic(kvm);
3622 if (vpic) {
1fe779f8
CO		 3623 r = kvm_ioapic_init(kvm);
3624 if (r) {
175504cd 3625 mutex_lock(&kvm->slots_lock);
72bb2fcd 3626 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3627 &vpic->dev_master);
3628 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3629 &vpic->dev_slave);
3630 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3631 &vpic->dev_eclr);
175504cd 3632 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3633 kfree(vpic);
3634 goto create_irqchip_unlock;
1fe779f8
CO		 3635 }
3636 } else
3ddea128
MT		 3637 goto create_irqchip_unlock;
3638 smp_wmb();
3639 kvm->arch.vpic = vpic;
3640 smp_wmb();
399ec807
AK		 3641 r = kvm_setup_default_irq_routing(kvm);
3642 if (r) {
175504cd 3643 mutex_lock(&kvm->slots_lock);
3ddea128 3644 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3645 kvm_ioapic_destroy(kvm);
3646 kvm_destroy_pic(kvm);
3ddea128 3647 mutex_unlock(&kvm->irq_lock);
175504cd 3648 mutex_unlock(&kvm->slots_lock);
399ec807 3649 }
3ddea128
MT		 3650 create_irqchip_unlock:
3651 mutex_unlock(&kvm->lock);
1fe779f8 3652 break;
3ddea128 3653 }
7837699f 3654 case KVM_CREATE_PIT:
c5ff41ce
JK		 3655 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3656 goto create_pit;
3657 case KVM_CREATE_PIT2:
3658 r = -EFAULT;
3659 if (copy_from_user(&u.pit_config, argp,
3660 sizeof(struct kvm_pit_config)))
3661 goto out;
3662 create_pit:
79fac95e 3663 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3664 r = -EEXIST;
3665 if (kvm->arch.vpit)
3666 goto create_pit_unlock;
7837699f 3667 r = -ENOMEM;
c5ff41ce 3668 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3669 if (kvm->arch.vpit)
3670 r = 0;
269e05e4 3671 create_pit_unlock:
79fac95e 3672 mutex_unlock(&kvm->slots_lock);
7837699f 3673 break;
1fe779f8
CO		 3674 case KVM_GET_IRQCHIP: {
3675 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3676 struct kvm_irqchip *chip;
1fe779f8 3677
ff5c2c03
SL		 3678 chip = memdup_user(argp, sizeof(*chip));
3679 if (IS_ERR(chip)) {
3680 r = PTR_ERR(chip);
1fe779f8 3681 goto out;
ff5c2c03
SL		 3682 }
3683
1fe779f8
CO		 3684 r = -ENXIO;
3685 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3686 goto get_irqchip_out;
3687 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3688 if (r)
f0d66275 3689 goto get_irqchip_out;
1fe779f8 3690 r = -EFAULT;
f0d66275
DH		 3691 if (copy_to_user(argp, chip, sizeof *chip))
3692 goto get_irqchip_out;
1fe779f8 3693 r = 0;
f0d66275
DH		 3694 get_irqchip_out:
3695 kfree(chip);
1fe779f8
CO		 3696 break;
3697 }
3698 case KVM_SET_IRQCHIP: {
3699 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3700 struct kvm_irqchip *chip;
1fe779f8 3701
ff5c2c03
SL		 3702 chip = memdup_user(argp, sizeof(*chip));
3703 if (IS_ERR(chip)) {
3704 r = PTR_ERR(chip);
1fe779f8 3705 goto out;
ff5c2c03
SL		 3706 }
3707
1fe779f8
CO		 3708 r = -ENXIO;
3709 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3710 goto set_irqchip_out;
3711 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3712 if (r)
f0d66275 3713 goto set_irqchip_out;
1fe779f8 3714 r = 0;
f0d66275
DH		 3715 set_irqchip_out:
3716 kfree(chip);
1fe779f8
CO		 3717 break;
3718 }
e0f63cb9 3719 case KVM_GET_PIT: {
e0f63cb9 3720 r = -EFAULT;
f0d66275 3721 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3722 goto out;
3723 r = -ENXIO;
3724 if (!kvm->arch.vpit)
3725 goto out;
f0d66275 3726 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3727 if (r)
3728 goto out;
3729 r = -EFAULT;
f0d66275 3730 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3731 goto out;
3732 r = 0;
3733 break;
3734 }
3735 case KVM_SET_PIT: {
e0f63cb9 3736 r = -EFAULT;
f0d66275 3737 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3738 goto out;
3739 r = -ENXIO;
3740 if (!kvm->arch.vpit)
3741 goto out;
f0d66275 3742 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3743 break;
3744 }
e9f42757
BK		 3745 case KVM_GET_PIT2: {
3746 r = -ENXIO;
3747 if (!kvm->arch.vpit)
3748 goto out;
3749 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3750 if (r)
3751 goto out;
3752 r = -EFAULT;
3753 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3754 goto out;
3755 r = 0;
3756 break;
3757 }
3758 case KVM_SET_PIT2: {
3759 r = -EFAULT;
3760 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3761 goto out;
3762 r = -ENXIO;
3763 if (!kvm->arch.vpit)
3764 goto out;
3765 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3766 break;
3767 }
52d939a0
MT		 3768 case KVM_REINJECT_CONTROL: {
3769 struct kvm_reinject_control control;
3770 r = -EFAULT;
3771 if (copy_from_user(&control, argp, sizeof(control)))
3772 goto out;
3773 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3774 break;
3775 }
ffde22ac
ES		 3776 case KVM_XEN_HVM_CONFIG: {
3777 r = -EFAULT;
3778 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3779 sizeof(struct kvm_xen_hvm_config)))
3780 goto out;
3781 r = -EINVAL;
3782 if (kvm->arch.xen_hvm_config.flags)
3783 goto out;
3784 r = 0;
3785 break;
3786 }
afbcf7ab 3787 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3788 struct kvm_clock_data user_ns;
3789 u64 now_ns;
3790 s64 delta;
3791
3792 r = -EFAULT;
3793 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3794 goto out;
3795
3796 r = -EINVAL;
3797 if (user_ns.flags)
3798 goto out;
3799
3800 r = 0;
395c6b0a 3801 local_irq_disable();
759379dd 3802 now_ns = get_kernel_ns();
afbcf7ab 3803 delta = user_ns.clock - now_ns;
395c6b0a 3804 local_irq_enable();
afbcf7ab 3805 kvm->arch.kvmclock_offset = delta;
2e762ff7 3806 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3807 break;
3808 }
3809 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3810 struct kvm_clock_data user_ns;
3811 u64 now_ns;
3812
395c6b0a 3813 local_irq_disable();
759379dd 3814 now_ns = get_kernel_ns();
afbcf7ab 3815 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3816 local_irq_enable();
afbcf7ab 3817 user_ns.flags = 0;
97e69aa6 3818 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3819
3820 r = -EFAULT;
3821 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3822 goto out;
3823 r = 0;
3824 break;
3825 }
3826
1fe779f8
CO		 3827 default:
3828 ;
3829 }
3830out:
3831 return r;
3832}
3833
a16b043c 3834static void kvm_init_msr_list(void)
043405e1
CO		 3835{
3836 u32 dummy[2];
3837 unsigned i, j;
3838
e3267cbb
GC		 3839 /* skip the first msrs in the list. KVM-specific */
3840 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3841 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3842 continue;
3843 if (j < i)
3844 msrs_to_save[j] = msrs_to_save[i];
3845 j++;
3846 }
3847 num_msrs_to_save = j;
3848}
3849
bda9020e
MT		 3850static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3851 const void *v)
bbd9b64e 3852{
70252a10
AK		 3853 int handled = 0;
3854 int n;
3855
3856 do {
3857 n = min(len, 8);
3858 if (!(vcpu->arch.apic &&
3859 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3860 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3861 break;
3862 handled += n;
3863 addr += n;
3864 len -= n;
3865 v += n;
3866 } while (len);
bbd9b64e 3867
70252a10 3868 return handled;
bbd9b64e
CO		 3869}
3870
bda9020e 3871static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3872{
70252a10
AK		 3873 int handled = 0;
3874 int n;
3875
3876 do {
3877 n = min(len, 8);
3878 if (!(vcpu->arch.apic &&
3879 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3880 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3881 break;
3882 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3883 handled += n;
3884 addr += n;
3885 len -= n;
3886 v += n;
3887 } while (len);
bbd9b64e 3888
70252a10 3889 return handled;
bbd9b64e
CO		 3890}
3891
2dafc6c2
GN		 3892static void kvm_set_segment(struct kvm_vcpu *vcpu,
3893 struct kvm_segment *var, int seg)
3894{
3895 kvm_x86_ops->set_segment(vcpu, var, seg);
3896}
3897
3898void kvm_get_segment(struct kvm_vcpu *vcpu,
3899 struct kvm_segment *var, int seg)
3900{
3901 kvm_x86_ops->get_segment(vcpu, var, seg);
3902}
3903
e459e322 3904gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3905{
3906 gpa_t t_gpa;
ab9ae313 3907 struct x86_exception exception;
02f59dc9
JR		 3908
3909 BUG_ON(!mmu_is_nested(vcpu));
3910
3911 /* NPT walks are always user-walks */
3912 access |= PFERR_USER_MASK;
ab9ae313 3913 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3914
3915 return t_gpa;
3916}
3917
ab9ae313
AK		 3918gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3919 struct x86_exception *exception)
1871c602
GN		 3920{
3921 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3922 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3923}
3924
ab9ae313
AK		 3925 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3926 struct x86_exception *exception)
1871c602
GN		 3927{
3928 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3929 access |= PFERR_FETCH_MASK;
ab9ae313 3930 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3931}
3932
ab9ae313
AK		 3933gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3934 struct x86_exception *exception)
1871c602
GN		 3935{
3936 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3937 access |= PFERR_WRITE_MASK;
ab9ae313 3938 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3939}
3940
3941/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3942gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3943 struct x86_exception *exception)
1871c602 3944{
ab9ae313 3945 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3946}
3947
3948static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3949 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3950 struct x86_exception *exception)
bbd9b64e
CO		 3951{
3952 void *data = val;
10589a46 3953 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3954
3955 while (bytes) {
14dfe855 3956 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3957 exception);
bbd9b64e 3958 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3959 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3960 int ret;
3961
bcc55cba 3962 if (gpa == UNMAPPED_GVA)
ab9ae313 3963 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3964 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3965 if (ret < 0) {
c3cd7ffa 3966 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3967 goto out;
3968 }
bbd9b64e 3969
77c2002e
IE		 3970 bytes -= toread;
3971 data += toread;
3972 addr += toread;
bbd9b64e 3973 }
10589a46 3974out:
10589a46 3975 return r;
bbd9b64e 3976}
77c2002e 3977
1871c602 3978/* used for instruction fetching */
0f65dd70
AK		 3979static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3980 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3981 struct x86_exception *exception)
1871c602 3982{
0f65dd70 3983 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3984 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3985
1871c602 3986 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3987 access | PFERR_FETCH_MASK,
3988 exception);
1871c602
GN		 3989}
3990
064aea77 3991int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3992 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3993 struct x86_exception *exception)
1871c602 3994{
0f65dd70 3995 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3996 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3997
1871c602 3998 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3999 exception);
1871c602 4000}
064aea77 4001EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4002
0f65dd70
AK		 4003static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4004 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4005 struct x86_exception *exception)
1871c602 4006{
0f65dd70 4007 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4008 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4009}
4010
6a4d7550 4011int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4012 gva_t addr, void *val,
2dafc6c2 4013 unsigned int bytes,
bcc55cba 4014 struct x86_exception *exception)
77c2002e 4015{
0f65dd70 4016 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4017 void *data = val;
4018 int r = X86EMUL_CONTINUE;
4019
4020 while (bytes) {
14dfe855
JR		 4021 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4022 PFERR_WRITE_MASK,
ab9ae313 4023 exception);
77c2002e
IE		 4024 unsigned offset = addr & (PAGE_SIZE-1);
4025 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4026 int ret;
4027
bcc55cba 4028 if (gpa == UNMAPPED_GVA)
ab9ae313 4029 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4030 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4031 if (ret < 0) {
c3cd7ffa 4032 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4033 goto out;
4034 }
4035
4036 bytes -= towrite;
4037 data += towrite;
4038 addr += towrite;
4039 }
4040out:
4041 return r;
4042}
6a4d7550 4043EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4044
af7cc7d1
XG		 4045static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4046 gpa_t *gpa, struct x86_exception *exception,
4047 bool write)
4048{
97d64b78
AK		 4049 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4050 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4051
97d64b78
AK		 4052 if (vcpu_match_mmio_gva(vcpu, gva)
4053 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4054 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4055 (gva & (PAGE_SIZE - 1));
4f022648 4056 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4057 return 1;
4058 }
4059
af7cc7d1
XG		 4060 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4061
4062 if (*gpa == UNMAPPED_GVA)
4063 return -1;
4064
4065 /* For APIC access vmexit */
4066 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4067 return 1;
4068
4f022648
XG		 4069 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4070 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4071 return 1;
4f022648 4072 }
bebb106a 4073
af7cc7d1
XG		 4074 return 0;
4075}
4076
3200f405 4077int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4078 const void *val, int bytes)
bbd9b64e
CO		 4079{
4080 int ret;
4081
4082 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4083 if (ret < 0)
bbd9b64e 4084 return 0;
f57f2ef5 4085 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4086 return 1;
4087}
4088
77d197b2
XG		 4089struct read_write_emulator_ops {
4090 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4091 int bytes);
4092 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4093 void *val, int bytes);
4094 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4095 int bytes, void *val);
4096 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4097 void *val, int bytes);
4098 bool write;
4099};
4100
4101static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4102{
4103 if (vcpu->mmio_read_completed) {
77d197b2 4104 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4105 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4106 vcpu->mmio_read_completed = 0;
4107 return 1;
4108 }
4109
4110 return 0;
4111}
4112
4113static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4114 void *val, int bytes)
4115{
4116 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4117}
4118
4119static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4120 void *val, int bytes)
4121{
4122 return emulator_write_phys(vcpu, gpa, val, bytes);
4123}
4124
4125static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4126{
4127 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4128 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4129}
4130
4131static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4132 void *val, int bytes)
4133{
4134 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4135 return X86EMUL_IO_NEEDED;
4136}
4137
4138static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4139 void *val, int bytes)
4140{
f78146b0
AK		 4141 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4142
87da7e66 4143 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4144 return X86EMUL_CONTINUE;
4145}
4146
0fbe9b0b 4147static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4148 .read_write_prepare = read_prepare,
4149 .read_write_emulate = read_emulate,
4150 .read_write_mmio = vcpu_mmio_read,
4151 .read_write_exit_mmio = read_exit_mmio,
4152};
4153
0fbe9b0b 4154static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4155 .read_write_emulate = write_emulate,
4156 .read_write_mmio = write_mmio,
4157 .read_write_exit_mmio = write_exit_mmio,
4158 .write = true,
4159};
4160
22388a3c
XG		 4161static int emulator_read_write_onepage(unsigned long addr, void *val,
4162 unsigned int bytes,
4163 struct x86_exception *exception,
4164 struct kvm_vcpu *vcpu,
0fbe9b0b 4165 const struct read_write_emulator_ops *ops)
bbd9b64e 4166{
af7cc7d1
XG		 4167 gpa_t gpa;
4168 int handled, ret;
22388a3c 4169 bool write = ops->write;
f78146b0 4170 struct kvm_mmio_fragment *frag;
10589a46 4171
22388a3c 4172 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4173
af7cc7d1 4174 if (ret < 0)
bbd9b64e 4175 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4176
4177 /* For APIC access vmexit */
af7cc7d1 4178 if (ret)
bbd9b64e
CO		 4179 goto mmio;
4180
22388a3c 4181 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4182 return X86EMUL_CONTINUE;
4183
4184mmio:
4185 /*
4186 * Is this MMIO handled locally?
4187 */
22388a3c 4188 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4189 if (handled == bytes)
bbd9b64e 4190 return X86EMUL_CONTINUE;
bbd9b64e 4191
70252a10
AK		 4192 gpa += handled;
4193 bytes -= handled;
4194 val += handled;
4195
87da7e66
XG		 4196 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4197 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4198 frag->gpa = gpa;
4199 frag->data = val;
4200 frag->len = bytes;
f78146b0 4201 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4202}
4203
22388a3c
XG		 4204int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4205 void *val, unsigned int bytes,
4206 struct x86_exception *exception,
0fbe9b0b 4207 const struct read_write_emulator_ops *ops)
bbd9b64e 4208{
0f65dd70 4209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4210 gpa_t gpa;
4211 int rc;
4212
4213 if (ops->read_write_prepare &&
4214 ops->read_write_prepare(vcpu, val, bytes))
4215 return X86EMUL_CONTINUE;
4216
4217 vcpu->mmio_nr_fragments = 0;
0f65dd70 4218
bbd9b64e
CO		 4219 /* Crossing a page boundary? */
4220 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4221 int now;
bbd9b64e
CO		 4222
4223 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4224 rc = emulator_read_write_onepage(addr, val, now, exception,
4225 vcpu, ops);
4226
bbd9b64e
CO		 4227 if (rc != X86EMUL_CONTINUE)
4228 return rc;
4229 addr += now;
4230 val += now;
4231 bytes -= now;
4232 }
22388a3c 4233
f78146b0
AK		 4234 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4235 vcpu, ops);
4236 if (rc != X86EMUL_CONTINUE)
4237 return rc;
4238
4239 if (!vcpu->mmio_nr_fragments)
4240 return rc;
4241
4242 gpa = vcpu->mmio_fragments[0].gpa;
4243
4244 vcpu->mmio_needed = 1;
4245 vcpu->mmio_cur_fragment = 0;
4246
87da7e66 4247 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4248 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4249 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4250 vcpu->run->mmio.phys_addr = gpa;
4251
4252 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4253}
4254
4255static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4256 unsigned long addr,
4257 void *val,
4258 unsigned int bytes,
4259 struct x86_exception *exception)
4260{
4261 return emulator_read_write(ctxt, addr, val, bytes,
4262 exception, &read_emultor);
4263}
4264
4265int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4266 unsigned long addr,
4267 const void *val,
4268 unsigned int bytes,
4269 struct x86_exception *exception)
4270{
4271 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4272 exception, &write_emultor);
bbd9b64e 4273}
bbd9b64e 4274
daea3e73
AK		 4275#define CMPXCHG_TYPE(t, ptr, old, new) \
4276 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4277
4278#ifdef CONFIG_X86_64
4279# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4280#else
4281# define CMPXCHG64(ptr, old, new) \
9749a6c0 4282 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4283#endif
4284
0f65dd70
AK		 4285static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4286 unsigned long addr,
bbd9b64e
CO		 4287 const void *old,
4288 const void *new,
4289 unsigned int bytes,
0f65dd70 4290 struct x86_exception *exception)
bbd9b64e 4291{
0f65dd70 4292 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4293 gpa_t gpa;
4294 struct page *page;
4295 char *kaddr;
4296 bool exchanged;
2bacc55c 4297
daea3e73
AK		 4298 /* guests cmpxchg8b have to be emulated atomically */
4299 if (bytes > 8 || (bytes & (bytes - 1)))
4300 goto emul_write;
10589a46 4301
daea3e73 4302 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4303
daea3e73
AK		 4304 if (gpa == UNMAPPED_GVA ||
4305 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4306 goto emul_write;
2bacc55c 4307
daea3e73
AK		 4308 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4309 goto emul_write;
72dc67a6 4310
daea3e73 4311 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4312 if (is_error_page(page))
c19b8bd6 4313 goto emul_write;
72dc67a6 4314
8fd75e12 4315 kaddr = kmap_atomic(page);
daea3e73
AK		 4316 kaddr += offset_in_page(gpa);
4317 switch (bytes) {
4318 case 1:
4319 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4320 break;
4321 case 2:
4322 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4323 break;
4324 case 4:
4325 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4326 break;
4327 case 8:
4328 exchanged = CMPXCHG64(kaddr, old, new);
4329 break;
4330 default:
4331 BUG();
2bacc55c 4332 }
8fd75e12 4333 kunmap_atomic(kaddr);
daea3e73
AK		 4334 kvm_release_page_dirty(page);
4335
4336 if (!exchanged)
4337 return X86EMUL_CMPXCHG_FAILED;
4338
f57f2ef5 4339 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4340
4341 return X86EMUL_CONTINUE;
4a5f48f6 4342
3200f405 4343emul_write:
daea3e73 4344 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4345
0f65dd70 4346 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4347}
4348
cf8f70bf
GN		 4349static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4350{
4351 /* TODO: String I/O for in kernel device */
4352 int r;
4353
4354 if (vcpu->arch.pio.in)
4355 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4356 vcpu->arch.pio.size, pd);
4357 else
4358 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4359 vcpu->arch.pio.port, vcpu->arch.pio.size,
4360 pd);
4361 return r;
4362}
4363
6f6fbe98
XG		 4364static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4365 unsigned short port, void *val,
4366 unsigned int count, bool in)
cf8f70bf 4367{
6f6fbe98 4368 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4369
4370 vcpu->arch.pio.port = port;
6f6fbe98 4371 vcpu->arch.pio.in = in;
7972995b 4372 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4373 vcpu->arch.pio.size = size;
4374
4375 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4376 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4377 return 1;
4378 }
4379
4380 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4381 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4382 vcpu->run->io.size = size;
4383 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4384 vcpu->run->io.count = count;
4385 vcpu->run->io.port = port;
4386
4387 return 0;
4388}
4389
6f6fbe98
XG		 4390static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4391 int size, unsigned short port, void *val,
4392 unsigned int count)
cf8f70bf 4393{
ca1d4a9e 4394 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4395 int ret;
ca1d4a9e 4396
6f6fbe98
XG		 4397 if (vcpu->arch.pio.count)
4398 goto data_avail;
cf8f70bf 4399
6f6fbe98
XG		 4400 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4401 if (ret) {
4402data_avail:
4403 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4404 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4405 return 1;
4406 }
4407
cf8f70bf
GN		 4408 return 0;
4409}
4410
6f6fbe98
XG		 4411static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4412 int size, unsigned short port,
4413 const void *val, unsigned int count)
4414{
4415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4416
4417 memcpy(vcpu->arch.pio_data, val, size * count);
4418 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4419}
4420
bbd9b64e
CO		 4421static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4422{
4423 return kvm_x86_ops->get_segment_base(vcpu, seg);
4424}
4425
3cb16fe7 4426static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4427{
3cb16fe7 4428 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4429}
4430
f5f48ee1
SY		 4431int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4432{
4433 if (!need_emulate_wbinvd(vcpu))
4434 return X86EMUL_CONTINUE;
4435
4436 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4437 int cpu = get_cpu();
4438
4439 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4440 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4441 wbinvd_ipi, NULL, 1);
2eec7343 4442 put_cpu();
f5f48ee1 4443 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4444 } else
4445 wbinvd();
f5f48ee1
SY		 4446 return X86EMUL_CONTINUE;
4447}
4448EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4449
bcaf5cc5
AK		 4450static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4451{
4452 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4453}
4454
717746e3 4455int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4456{
717746e3 4457 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4458}
4459
717746e3 4460int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4461{
338dbc97 4462
717746e3 4463 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4464}
4465
52a46617 4466static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4467{
52a46617 4468 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4469}
4470
717746e3 4471static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4472{
717746e3 4473 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4474 unsigned long value;
4475
4476 switch (cr) {
4477 case 0:
4478 value = kvm_read_cr0(vcpu);
4479 break;
4480 case 2:
4481 value = vcpu->arch.cr2;
4482 break;
4483 case 3:
9f8fe504 4484 value = kvm_read_cr3(vcpu);
52a46617
GN		 4485 break;
4486 case 4:
4487 value = kvm_read_cr4(vcpu);
4488 break;
4489 case 8:
4490 value = kvm_get_cr8(vcpu);
4491 break;
4492 default:
a737f256 4493 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4494 return 0;
4495 }
4496
4497 return value;
4498}
4499
717746e3 4500static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4501{
717746e3 4502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4503 int res = 0;
4504
52a46617
GN		 4505 switch (cr) {
4506 case 0:
49a9b07e 4507 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4508 break;
4509 case 2:
4510 vcpu->arch.cr2 = val;
4511 break;
4512 case 3:
2390218b 4513 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4514 break;
4515 case 4:
a83b29c6 4516 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4517 break;
4518 case 8:
eea1cff9 4519 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4520 break;
4521 default:
a737f256 4522 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4523 res = -1;
52a46617 4524 }
0f12244f
GN		 4525
4526 return res;
52a46617
GN		 4527}
4528
4cee4798
KW		 4529static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4530{
4531 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4532}
4533
717746e3 4534static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4535{
717746e3 4536 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4537}
4538
4bff1e86 4539static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4540{
4bff1e86 4541 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4542}
4543
4bff1e86 4544static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4545{
4bff1e86 4546 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4547}
4548
1ac9d0cf
AK		 4549static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4550{
4551 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4552}
4553
4554static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4555{
4556 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4557}
4558
4bff1e86
AK		 4559static unsigned long emulator_get_cached_segment_base(
4560 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4561{
4bff1e86 4562 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4563}
4564
1aa36616
AK		 4565static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4566 struct desc_struct *desc, u32 *base3,
4567 int seg)
2dafc6c2
GN		 4568{
4569 struct kvm_segment var;
4570
4bff1e86 4571 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4572 *selector = var.selector;
2dafc6c2 4573
378a8b09
GN		 4574 if (var.unusable) {
4575 memset(desc, 0, sizeof(*desc));
2dafc6c2 4576 return false;
378a8b09 4577 }
2dafc6c2
GN		 4578
4579 if (var.g)
4580 var.limit >>= 12;
4581 set_desc_limit(desc, var.limit);
4582 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4583#ifdef CONFIG_X86_64
4584 if (base3)
4585 *base3 = var.base >> 32;
4586#endif
2dafc6c2
GN		 4587 desc->type = var.type;
4588 desc->s = var.s;
4589 desc->dpl = var.dpl;
4590 desc->p = var.present;
4591 desc->avl = var.avl;
4592 desc->l = var.l;
4593 desc->d = var.db;
4594 desc->g = var.g;
4595
4596 return true;
4597}
4598
1aa36616
AK		 4599static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4600 struct desc_struct *desc, u32 base3,
4601 int seg)
2dafc6c2 4602{
4bff1e86 4603 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4604 struct kvm_segment var;
4605
1aa36616 4606 var.selector = selector;
2dafc6c2 4607 var.base = get_desc_base(desc);
5601d05b
GN		 4608#ifdef CONFIG_X86_64
4609 var.base |= ((u64)base3) << 32;
4610#endif
2dafc6c2
GN		 4611 var.limit = get_desc_limit(desc);
4612 if (desc->g)
4613 var.limit = (var.limit << 12) | 0xfff;
4614 var.type = desc->type;
4615 var.present = desc->p;
4616 var.dpl = desc->dpl;
4617 var.db = desc->d;
4618 var.s = desc->s;
4619 var.l = desc->l;
4620 var.g = desc->g;
4621 var.avl = desc->avl;
4622 var.present = desc->p;
4623 var.unusable = !var.present;
4624 var.padding = 0;
4625
4626 kvm_set_segment(vcpu, &var, seg);
4627 return;
4628}
4629
717746e3
AK		 4630static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4631 u32 msr_index, u64 *pdata)
4632{
4633 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4634}
4635
4636static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4637 u32 msr_index, u64 data)
4638{
8fe8ab46
WA		 4639 struct msr_data msr;
4640
4641 msr.data = data;
4642 msr.index = msr_index;
4643 msr.host_initiated = false;
4644 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4645}
4646
222d21aa
AK		 4647static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4648 u32 pmc, u64 *pdata)
4649{
4650 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4651}
4652
6c3287f7
AK		 4653static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4654{
4655 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4656}
4657
5037f6f3
AK		 4658static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4659{
4660 preempt_disable();
5197b808 4661 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4662 /*
4663 * CR0.TS may reference the host fpu state, not the guest fpu state,
4664 * so it may be clear at this point.
4665 */
4666 clts();
4667}
4668
4669static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4670{
4671 preempt_enable();
4672}
4673
2953538e 4674static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4675 struct x86_instruction_info *info,
c4f035c6
AK		 4676 enum x86_intercept_stage stage)
4677{
2953538e 4678 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4679}
4680
0017f93a 4681static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4682 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4683{
0017f93a 4684 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4685}
4686
dd856efa
AK		 4687static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4688{
4689 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4690}
4691
4692static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4693{
4694 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4695}
4696
0225fb50 4697static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4698 .read_gpr = emulator_read_gpr,
4699 .write_gpr = emulator_write_gpr,
1871c602 4700 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4701 .write_std = kvm_write_guest_virt_system,
1871c602 4702 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4703 .read_emulated = emulator_read_emulated,
4704 .write_emulated = emulator_write_emulated,
4705 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4706 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4707 .pio_in_emulated = emulator_pio_in_emulated,
4708 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4709 .get_segment = emulator_get_segment,
4710 .set_segment = emulator_set_segment,
5951c442 4711 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4712 .get_gdt = emulator_get_gdt,
160ce1f1 4713 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4714 .set_gdt = emulator_set_gdt,
4715 .set_idt = emulator_set_idt,
52a46617
GN		 4716 .get_cr = emulator_get_cr,
4717 .set_cr = emulator_set_cr,
4cee4798 4718 .set_rflags = emulator_set_rflags,
9c537244 4719 .cpl = emulator_get_cpl,
35aa5375
GN		 4720 .get_dr = emulator_get_dr,
4721 .set_dr = emulator_set_dr,
717746e3
AK		 4722 .set_msr = emulator_set_msr,
4723 .get_msr = emulator_get_msr,
222d21aa 4724 .read_pmc = emulator_read_pmc,
6c3287f7 4725 .halt = emulator_halt,
bcaf5cc5 4726 .wbinvd = emulator_wbinvd,
d6aa1000 4727 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4728 .get_fpu = emulator_get_fpu,
4729 .put_fpu = emulator_put_fpu,
c4f035c6 4730 .intercept = emulator_intercept,
bdb42f5a 4731 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4732};
4733
95cb2295
GN		 4734static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4735{
4736 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4737 /*
4738 * an sti; sti; sequence only disable interrupts for the first
4739 * instruction. So, if the last instruction, be it emulated or
4740 * not, left the system with the INT_STI flag enabled, it
4741 * means that the last instruction is an sti. We should not
4742 * leave the flag on in this case. The same goes for mov ss
4743 */
4744 if (!(int_shadow & mask))
4745 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4746}
4747
54b8486f
GN		 4748static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4749{
4750 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4751 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4752 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4753 else if (ctxt->exception.error_code_valid)
4754 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4755 ctxt->exception.error_code);
54b8486f 4756 else
da9cb575 4757 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4758}
4759
dd856efa 4760static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4761{
1ce19dc1
BP		 4762 memset(&ctxt->opcode_len, 0,
4763 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4764
9dac77fa
AK		 4765 ctxt->fetch.start = 0;
4766 ctxt->fetch.end = 0;
4767 ctxt->io_read.pos = 0;
4768 ctxt->io_read.end = 0;
4769 ctxt->mem_read.pos = 0;
4770 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4771}
4772
8ec4722d
MG		 4773static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4774{
adf52235 4775 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4776 int cs_db, cs_l;
4777
8ec4722d
MG		 4778 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4779
adf52235
TY		 4780 ctxt->eflags = kvm_get_rflags(vcpu);
4781 ctxt->eip = kvm_rip_read(vcpu);
4782 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4783 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4784 cs_l ? X86EMUL_MODE_PROT64 :
4785 cs_db ? X86EMUL_MODE_PROT32 :
4786 X86EMUL_MODE_PROT16;
4787 ctxt->guest_mode = is_guest_mode(vcpu);
4788
dd856efa 4789 init_decode_cache(ctxt);
7ae441ea 4790 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4791}
4792
71f9833b 4793int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4794{
9d74191a 4795 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4796 int ret;
4797
4798 init_emulate_ctxt(vcpu);
4799
9dac77fa
AK		 4800 ctxt->op_bytes = 2;
4801 ctxt->ad_bytes = 2;
4802 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4803 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4804
4805 if (ret != X86EMUL_CONTINUE)
4806 return EMULATE_FAIL;
4807
9dac77fa 4808 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4809 kvm_rip_write(vcpu, ctxt->eip);
4810 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4811
4812 if (irq == NMI_VECTOR)
7460fb4a 4813 vcpu->arch.nmi_pending = 0;
63995653
MG		 4814 else
4815 vcpu->arch.interrupt.pending = false;
4816
4817 return EMULATE_DONE;
4818}
4819EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4820
6d77dbfc
GN		 4821static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4822{
fc3a9157
JR		 4823 int r = EMULATE_DONE;
4824
6d77dbfc
GN		 4825 ++vcpu->stat.insn_emulation_fail;
4826 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4827 if (!is_guest_mode(vcpu)) {
4828 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4829 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4830 vcpu->run->internal.ndata = 0;
4831 r = EMULATE_FAIL;
4832 }
6d77dbfc 4833 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4834
4835 return r;
6d77dbfc
GN		 4836}
4837
93c05d3e 4838static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4839 bool write_fault_to_shadow_pgtable,
4840 int emulation_type)
a6f177ef 4841{
95b3cf69 4842 gpa_t gpa = cr2;
8e3d9d06 4843 pfn_t pfn;
a6f177ef 4844
991eebf9
GN		 4845 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4846 return false;
4847
95b3cf69
XG		 4848 if (!vcpu->arch.mmu.direct_map) {
4849 /*
4850 * Write permission should be allowed since only
4851 * write access need to be emulated.
4852 */
4853 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4854
95b3cf69
XG		 4855 /*
4856 * If the mapping is invalid in guest, let cpu retry
4857 * it to generate fault.
4858 */
4859 if (gpa == UNMAPPED_GVA)
4860 return true;
4861 }
a6f177ef 4862
8e3d9d06
XG		 4863 /*
4864 * Do not retry the unhandleable instruction if it faults on the
4865 * readonly host memory, otherwise it will goto a infinite loop:
4866 * retry instruction -> write #PF -> emulation fail -> retry
4867 * instruction -> ...
4868 */
4869 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4870
4871 /*
4872 * If the instruction failed on the error pfn, it can not be fixed,
4873 * report the error to userspace.
4874 */
4875 if (is_error_noslot_pfn(pfn))
4876 return false;
4877
4878 kvm_release_pfn_clean(pfn);
4879
4880 /* The instructions are well-emulated on direct mmu. */
4881 if (vcpu->arch.mmu.direct_map) {
4882 unsigned int indirect_shadow_pages;
4883
4884 spin_lock(&vcpu->kvm->mmu_lock);
4885 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4886 spin_unlock(&vcpu->kvm->mmu_lock);
4887
4888 if (indirect_shadow_pages)
4889 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4890
a6f177ef 4891 return true;
8e3d9d06 4892 }
a6f177ef 4893
95b3cf69
XG		 4894 /*
4895 * if emulation was due to access to shadowed page table
4896 * and it failed try to unshadow page and re-enter the
4897 * guest to let CPU execute the instruction.
4898 */
4899 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4900
4901 /*
4902 * If the access faults on its page table, it can not
4903 * be fixed by unprotecting shadow page and it should
4904 * be reported to userspace.
4905 */
4906 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4907}
4908
1cb3f3ae
XG		 4909static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4910 unsigned long cr2, int emulation_type)
4911{
4912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4913 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4914
4915 last_retry_eip = vcpu->arch.last_retry_eip;
4916 last_retry_addr = vcpu->arch.last_retry_addr;
4917
4918 /*
4919 * If the emulation is caused by #PF and it is non-page_table
4920 * writing instruction, it means the VM-EXIT is caused by shadow
4921 * page protected, we can zap the shadow page and retry this
4922 * instruction directly.
4923 *
4924 * Note: if the guest uses a non-page-table modifying instruction
4925 * on the PDE that points to the instruction, then we will unmap
4926 * the instruction and go to an infinite loop. So, we cache the
4927 * last retried eip and the last fault address, if we meet the eip
4928 * and the address again, we can break out of the potential infinite
4929 * loop.
4930 */
4931 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4932
4933 if (!(emulation_type & EMULTYPE_RETRY))
4934 return false;
4935
4936 if (x86_page_table_writing_insn(ctxt))
4937 return false;
4938
4939 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4940 return false;
4941
4942 vcpu->arch.last_retry_eip = ctxt->eip;
4943 vcpu->arch.last_retry_addr = cr2;
4944
4945 if (!vcpu->arch.mmu.direct_map)
4946 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4947
22368028 4948 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4949
4950 return true;
4951}
4952
716d51ab
GN		 4953static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4954static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4955
4a1e10d5
PB		 4956static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4957 unsigned long *db)
4958{
4959 u32 dr6 = 0;
4960 int i;
4961 u32 enable, rwlen;
4962
4963 enable = dr7;
4964 rwlen = dr7 >> 16;
4965 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4966 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4967 dr6 |= (1 << i);
4968 return dr6;
4969}
4970
663f4c61
PB		 4971static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
4972{
4973 struct kvm_run *kvm_run = vcpu->run;
4974
4975 /*
4976 * Use the "raw" value to see if TF was passed to the processor.
4977 * Note that the new value of the flags has not been saved yet.
4978 *
4979 * This is correct even for TF set by the guest, because "the
4980 * processor will not generate this exception after the instruction
4981 * that sets the TF flag".
4982 */
4983 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
4984
4985 if (unlikely(rflags & X86_EFLAGS_TF)) {
4986 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4987 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
4988 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
4989 kvm_run->debug.arch.exception = DB_VECTOR;
4990 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4991 *r = EMULATE_USER_EXIT;
4992 } else {
4993 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
4994 /*
4995 * "Certain debug exceptions may clear bit 0-3. The
4996 * remaining contents of the DR6 register are never
4997 * cleared by the processor".
4998 */
4999 vcpu->arch.dr6 &= ~15;
5000 vcpu->arch.dr6 |= DR6_BS;
5001 kvm_queue_exception(vcpu, DB_VECTOR);
5002 }
5003 }
5004}
5005
4a1e10d5
PB		 5006static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5007{
5008 struct kvm_run *kvm_run = vcpu->run;
5009 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5010 u32 dr6 = 0;
5011
5012 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5013 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5014 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5015 vcpu->arch.guest_debug_dr7,
5016 vcpu->arch.eff_db);
5017
5018 if (dr6 != 0) {
5019 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5020 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5021 get_segment_base(vcpu, VCPU_SREG_CS);
5022
5023 kvm_run->debug.arch.exception = DB_VECTOR;
5024 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5025 *r = EMULATE_USER_EXIT;
5026 return true;
5027 }
5028 }
5029
5030 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5031 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5032 vcpu->arch.dr7,
5033 vcpu->arch.db);
5034
5035 if (dr6 != 0) {
5036 vcpu->arch.dr6 &= ~15;
5037 vcpu->arch.dr6 |= dr6;
5038 kvm_queue_exception(vcpu, DB_VECTOR);
5039 *r = EMULATE_DONE;
5040 return true;
5041 }
5042 }
5043
5044 return false;
5045}
5046
51d8b661
AP		 5047int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5048 unsigned long cr2,
dc25e89e
AP		 5049 int emulation_type,
5050 void *insn,
5051 int insn_len)
bbd9b64e 5052{
95cb2295 5053 int r;
9d74191a 5054 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5055 bool writeback = true;
93c05d3e 5056 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5057
93c05d3e
XG		 5058 /*
5059 * Clear write_fault_to_shadow_pgtable here to ensure it is
5060 * never reused.
5061 */
5062 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5063 kvm_clear_exception_queue(vcpu);
8d7d8102 5064
571008da 5065 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5066 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5067
5068 /*
5069 * We will reenter on the same instruction since
5070 * we do not set complete_userspace_io. This does not
5071 * handle watchpoints yet, those would be handled in
5072 * the emulate_ops.
5073 */
5074 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5075 return r;
5076
9d74191a
TY		 5077 ctxt->interruptibility = 0;
5078 ctxt->have_exception = false;
5079 ctxt->perm_ok = false;
bbd9b64e 5080
b51e974f 5081 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5082
9d74191a 5083 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5084
e46479f8 5085 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5086 ++vcpu->stat.insn_emulation;
1d2887e2 5087 if (r != EMULATION_OK) {
4005996e
AK		 5088 if (emulation_type & EMULTYPE_TRAP_UD)
5089 return EMULATE_FAIL;
991eebf9
GN		 5090 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5091 emulation_type))
bbd9b64e 5092 return EMULATE_DONE;
6d77dbfc
GN		 5093 if (emulation_type & EMULTYPE_SKIP)
5094 return EMULATE_FAIL;
5095 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5096 }
5097 }
5098
ba8afb6b 5099 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5100 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5101 return EMULATE_DONE;
5102 }
5103
1cb3f3ae
XG		 5104 if (retry_instruction(ctxt, cr2, emulation_type))
5105 return EMULATE_DONE;
5106
7ae441ea 5107 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5108 changes registers values during IO operation */
7ae441ea
GN		 5109 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5110 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5111 emulator_invalidate_register_cache(ctxt);
7ae441ea 5112 }
4d2179e1 5113
5cd21917 5114restart:
9d74191a 5115 r = x86_emulate_insn(ctxt);
bbd9b64e 5116
775fde86
JR		 5117 if (r == EMULATION_INTERCEPTED)
5118 return EMULATE_DONE;
5119
d2ddd1c4 5120 if (r == EMULATION_FAILED) {
991eebf9
GN		 5121 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5122 emulation_type))
c3cd7ffa
GN		 5123 return EMULATE_DONE;
5124
6d77dbfc 5125 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5126 }
5127
9d74191a 5128 if (ctxt->have_exception) {
54b8486f 5129 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5130 r = EMULATE_DONE;
5131 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5132 if (!vcpu->arch.pio.in) {
5133 /* FIXME: return into emulator if single-stepping. */
3457e419 5134 vcpu->arch.pio.count = 0;
0912c977 5135 } else {
7ae441ea 5136 writeback = false;
716d51ab
GN		 5137 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5138 }
ac0a48c3 5139 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5140 } else if (vcpu->mmio_needed) {
5141 if (!vcpu->mmio_is_write)
5142 writeback = false;
ac0a48c3 5143 r = EMULATE_USER_EXIT;
716d51ab 5144 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5145 } else if (r == EMULATION_RESTART)
5cd21917 5146 goto restart;
d2ddd1c4
GN		 5147 else
5148 r = EMULATE_DONE;
f850e2e6 5149
7ae441ea 5150 if (writeback) {
9d74191a 5151 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5152 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5153 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5154 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5155 if (r == EMULATE_DONE)
5156 kvm_vcpu_check_singlestep(vcpu, &r);
5157 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5158 } else
5159 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5160
5161 return r;
de7d789a 5162}
51d8b661 5163EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5164
cf8f70bf 5165int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5166{
cf8f70bf 5167 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5168 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5169 size, port, &val, 1);
cf8f70bf 5170 /* do not return to emulator after return from userspace */
7972995b 5171 vcpu->arch.pio.count = 0;
de7d789a
CO		 5172 return ret;
5173}
cf8f70bf 5174EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5175
8cfdc000
ZA		 5176static void tsc_bad(void *info)
5177{
0a3aee0d 5178 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5179}
5180
5181static void tsc_khz_changed(void *data)
c8076604 5182{
8cfdc000
ZA		 5183 struct cpufreq_freqs *freq = data;
5184 unsigned long khz = 0;
5185
5186 if (data)
5187 khz = freq->new;
5188 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5189 khz = cpufreq_quick_get(raw_smp_processor_id());
5190 if (!khz)
5191 khz = tsc_khz;
0a3aee0d 5192 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5193}
5194
c8076604
GH		 5195static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5196 void *data)
5197{
5198 struct cpufreq_freqs *freq = data;
5199 struct kvm *kvm;
5200 struct kvm_vcpu *vcpu;
5201 int i, send_ipi = 0;
5202
8cfdc000
ZA		 5203 /*
5204 * We allow guests to temporarily run on slowing clocks,
5205 * provided we notify them after, or to run on accelerating
5206 * clocks, provided we notify them before. Thus time never
5207 * goes backwards.
5208 *
5209 * However, we have a problem. We can't atomically update
5210 * the frequency of a given CPU from this function; it is
5211 * merely a notifier, which can be called from any CPU.
5212 * Changing the TSC frequency at arbitrary points in time
5213 * requires a recomputation of local variables related to
5214 * the TSC for each VCPU. We must flag these local variables
5215 * to be updated and be sure the update takes place with the
5216 * new frequency before any guests proceed.
5217 *
5218 * Unfortunately, the combination of hotplug CPU and frequency
5219 * change creates an intractable locking scenario; the order
5220 * of when these callouts happen is undefined with respect to
5221 * CPU hotplug, and they can race with each other. As such,
5222 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5223 * undefined; you can actually have a CPU frequency change take
5224 * place in between the computation of X and the setting of the
5225 * variable. To protect against this problem, all updates of
5226 * the per_cpu tsc_khz variable are done in an interrupt
5227 * protected IPI, and all callers wishing to update the value
5228 * must wait for a synchronous IPI to complete (which is trivial
5229 * if the caller is on the CPU already). This establishes the
5230 * necessary total order on variable updates.
5231 *
5232 * Note that because a guest time update may take place
5233 * anytime after the setting of the VCPU's request bit, the
5234 * correct TSC value must be set before the request. However,
5235 * to ensure the update actually makes it to any guest which
5236 * starts running in hardware virtualization between the set
5237 * and the acquisition of the spinlock, we must also ping the
5238 * CPU after setting the request bit.
5239 *
5240 */
5241
c8076604
GH		 5242 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5243 return 0;
5244 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5245 return 0;
8cfdc000
ZA		 5246
5247 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5248
2f303b74 5249 spin_lock(&kvm_lock);
c8076604 5250 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5251 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5252 if (vcpu->cpu != freq->cpu)
5253 continue;
c285545f 5254 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5255 if (vcpu->cpu != smp_processor_id())
8cfdc000 5256 send_ipi = 1;
c8076604
GH		 5257 }
5258 }
2f303b74 5259 spin_unlock(&kvm_lock);
c8076604
GH		 5260
5261 if (freq->old < freq->new && send_ipi) {
5262 /*
5263 * We upscale the frequency. Must make the guest
5264 * doesn't see old kvmclock values while running with
5265 * the new frequency, otherwise we risk the guest sees
5266 * time go backwards.
5267 *
5268 * In case we update the frequency for another cpu
5269 * (which might be in guest context) send an interrupt
5270 * to kick the cpu out of guest context. Next time
5271 * guest context is entered kvmclock will be updated,
5272 * so the guest will not see stale values.
5273 */
8cfdc000 5274 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5275 }
5276 return 0;
5277}
5278
5279static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5280 .notifier_call = kvmclock_cpufreq_notifier
5281};
5282
5283static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5284 unsigned long action, void *hcpu)
5285{
5286 unsigned int cpu = (unsigned long)hcpu;
5287
5288 switch (action) {
5289 case CPU_ONLINE:
5290 case CPU_DOWN_FAILED:
5291 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5292 break;
5293 case CPU_DOWN_PREPARE:
5294 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5295 break;
5296 }
5297 return NOTIFY_OK;
5298}
5299
5300static struct notifier_block kvmclock_cpu_notifier_block = {
5301 .notifier_call = kvmclock_cpu_notifier,
5302 .priority = -INT_MAX
c8076604
GH		 5303};
5304
b820cc0c
ZA		 5305static void kvm_timer_init(void)
5306{
5307 int cpu;
5308
c285545f 5309 max_tsc_khz = tsc_khz;
8cfdc000 5310 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5311 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5312#ifdef CONFIG_CPU_FREQ
5313 struct cpufreq_policy policy;
5314 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5315 cpu = get_cpu();
5316 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5317 if (policy.cpuinfo.max_freq)
5318 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5319 put_cpu();
c285545f 5320#endif
b820cc0c
ZA		 5321 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5322 CPUFREQ_TRANSITION_NOTIFIER);
5323 }
c285545f 5324 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5325 for_each_online_cpu(cpu)
5326 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5327}
5328
ff9d07a0
ZY		 5329static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5330
f5132b01 5331int kvm_is_in_guest(void)
ff9d07a0 5332{
086c9855 5333 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5334}
5335
5336static int kvm_is_user_mode(void)
5337{
5338 int user_mode = 3;
dcf46b94 5339
086c9855
AS		 5340 if (__this_cpu_read(current_vcpu))
5341 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5342
ff9d07a0
ZY		 5343 return user_mode != 0;
5344}
5345
5346static unsigned long kvm_get_guest_ip(void)
5347{
5348 unsigned long ip = 0;
dcf46b94 5349
086c9855
AS		 5350 if (__this_cpu_read(current_vcpu))
5351 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5352
ff9d07a0
ZY		 5353 return ip;
5354}
5355
5356static struct perf_guest_info_callbacks kvm_guest_cbs = {
5357 .is_in_guest = kvm_is_in_guest,
5358 .is_user_mode = kvm_is_user_mode,
5359 .get_guest_ip = kvm_get_guest_ip,
5360};
5361
5362void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5363{
086c9855 5364 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5365}
5366EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5367
5368void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5369{
086c9855 5370 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5371}
5372EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5373
ce88decf
XG		 5374static void kvm_set_mmio_spte_mask(void)
5375{
5376 u64 mask;
5377 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5378
5379 /*
5380 * Set the reserved bits and the present bit of an paging-structure
5381 * entry to generate page fault with PFER.RSV = 1.
5382 */
885032b9
XG		 5383 /* Mask the reserved physical address bits. */
5384 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5385
5386 /* Bit 62 is always reserved for 32bit host. */
5387 mask |= 0x3ull << 62;
5388
5389 /* Set the present bit. */
ce88decf
XG		 5390 mask |= 1ull;
5391
5392#ifdef CONFIG_X86_64
5393 /*
5394 * If reserved bit is not supported, clear the present bit to disable
5395 * mmio page fault.
5396 */
5397 if (maxphyaddr == 52)
5398 mask &= ~1ull;
5399#endif
5400
5401 kvm_mmu_set_mmio_spte_mask(mask);
5402}
5403
16e8d74d
MT		 5404#ifdef CONFIG_X86_64
5405static void pvclock_gtod_update_fn(struct work_struct *work)
5406{
d828199e
MT		 5407 struct kvm *kvm;
5408
5409 struct kvm_vcpu *vcpu;
5410 int i;
5411
2f303b74 5412 spin_lock(&kvm_lock);
d828199e
MT		 5413 list_for_each_entry(kvm, &vm_list, vm_list)
5414 kvm_for_each_vcpu(i, vcpu, kvm)
5415 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5416 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5417 spin_unlock(&kvm_lock);
16e8d74d
MT		 5418}
5419
5420static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5421
5422/*
5423 * Notification about pvclock gtod data update.
5424 */
5425static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5426 void *priv)
5427{
5428 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5429 struct timekeeper *tk = priv;
5430
5431 update_pvclock_gtod(tk);
5432
5433 /* disable master clock if host does not trust, or does not
5434 * use, TSC clocksource
5435 */
5436 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5437 atomic_read(&kvm_guest_has_master_clock) != 0)
5438 queue_work(system_long_wq, &pvclock_gtod_work);
5439
5440 return 0;
5441}
5442
5443static struct notifier_block pvclock_gtod_notifier = {
5444 .notifier_call = pvclock_gtod_notify,
5445};
5446#endif
5447
f8c16bba 5448int kvm_arch_init(void *opaque)
043405e1 5449{
b820cc0c 5450 int r;
6b61edf7 5451 struct kvm_x86_ops *ops = opaque;
f8c16bba 5452
f8c16bba
ZX		 5453 if (kvm_x86_ops) {
5454 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5455 r = -EEXIST;
5456 goto out;
f8c16bba
ZX		 5457 }
5458
5459 if (!ops->cpu_has_kvm_support()) {
5460 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5461 r = -EOPNOTSUPP;
5462 goto out;
f8c16bba
ZX		 5463 }
5464 if (ops->disabled_by_bios()) {
5465 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5466 r = -EOPNOTSUPP;
5467 goto out;
f8c16bba
ZX		 5468 }
5469
013f6a5d
MT		 5470 r = -ENOMEM;
5471 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5472 if (!shared_msrs) {
5473 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5474 goto out;
5475 }
5476
97db56ce
AK		 5477 r = kvm_mmu_module_init();
5478 if (r)
013f6a5d 5479 goto out_free_percpu;
97db56ce 5480
ce88decf 5481 kvm_set_mmio_spte_mask();
97db56ce
AK		 5482 kvm_init_msr_list();
5483
f8c16bba 5484 kvm_x86_ops = ops;
7b52345e 5485 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5486 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5487
b820cc0c 5488 kvm_timer_init();
c8076604 5489
ff9d07a0
ZY		 5490 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5491
2acf923e
DC		 5492 if (cpu_has_xsave)
5493 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5494
c5cc421b 5495 kvm_lapic_init();
16e8d74d
MT		 5496#ifdef CONFIG_X86_64
5497 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5498#endif
5499
f8c16bba 5500 return 0;
56c6d28a 5501
013f6a5d
MT		 5502out_free_percpu:
5503 free_percpu(shared_msrs);
56c6d28a 5504out:
56c6d28a 5505 return r;
043405e1 5506}
8776e519 5507
f8c16bba
ZX		 5508void kvm_arch_exit(void)
5509{
ff9d07a0
ZY		 5510 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5511
888d256e
JK		 5512 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5513 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5514 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5515 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5516#ifdef CONFIG_X86_64
5517 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5518#endif
f8c16bba 5519 kvm_x86_ops = NULL;
56c6d28a 5520 kvm_mmu_module_exit();
013f6a5d 5521 free_percpu(shared_msrs);
56c6d28a 5522}
f8c16bba 5523
8776e519
HB		 5524int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5525{
5526 ++vcpu->stat.halt_exits;
5527 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5528 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5529 return 1;
5530 } else {
5531 vcpu->run->exit_reason = KVM_EXIT_HLT;
5532 return 0;
5533 }
5534}
5535EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5536
55cd8e5a
GN		 5537int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5538{
5539 u64 param, ingpa, outgpa, ret;
5540 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5541 bool fast, longmode;
5542 int cs_db, cs_l;
5543
5544 /*
5545 * hypercall generates UD from non zero cpl and real mode
5546 * per HYPER-V spec
5547 */
3eeb3288 5548 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5549 kvm_queue_exception(vcpu, UD_VECTOR);
5550 return 0;
5551 }
5552
5553 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5554 longmode = is_long_mode(vcpu) && cs_l == 1;
5555
5556 if (!longmode) {
ccd46936
GN		 5557 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5558 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5559 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5560 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5561 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5562 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5563 }
5564#ifdef CONFIG_X86_64
5565 else {
5566 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5567 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5568 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5569 }
5570#endif
5571
5572 code = param & 0xffff;
5573 fast = (param >> 16) & 0x1;
5574 rep_cnt = (param >> 32) & 0xfff;
5575 rep_idx = (param >> 48) & 0xfff;
5576
5577 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5578
c25bc163
GN		 5579 switch (code) {
5580 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5581 kvm_vcpu_on_spin(vcpu);
5582 break;
5583 default:
5584 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5585 break;
5586 }
55cd8e5a
GN		 5587
5588 ret = res | (((u64)rep_done & 0xfff) << 32);
5589 if (longmode) {
5590 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5591 } else {
5592 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5593 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5594 }
5595
5596 return 1;
5597}
5598
6aef266c
SV		 5599/*
5600 * kvm_pv_kick_cpu_op: Kick a vcpu.
5601 *
5602 * @apicid - apicid of vcpu to be kicked.
5603 */
5604static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5605{
24d2166b 5606 struct kvm_lapic_irq lapic_irq;
6aef266c 5607
24d2166b
R		 5608 lapic_irq.shorthand = 0;
5609 lapic_irq.dest_mode = 0;
5610 lapic_irq.dest_id = apicid;
6aef266c 5611
24d2166b
R		 5612 lapic_irq.delivery_mode = APIC_DM_REMRD;
5613 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5614}
5615
8776e519
HB		 5616int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5617{
5618 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5619 int r = 1;
8776e519 5620
55cd8e5a
GN		 5621 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5622 return kvm_hv_hypercall(vcpu);
5623
5fdbf976
MT		 5624 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5625 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5626 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5627 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5628 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5629
229456fc 5630 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5631
8776e519
HB		 5632 if (!is_long_mode(vcpu)) {
5633 nr &= 0xFFFFFFFF;
5634 a0 &= 0xFFFFFFFF;
5635 a1 &= 0xFFFFFFFF;
5636 a2 &= 0xFFFFFFFF;
5637 a3 &= 0xFFFFFFFF;
5638 }
5639
07708c4a
JK		 5640 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5641 ret = -KVM_EPERM;
5642 goto out;
5643 }
5644
8776e519 5645 switch (nr) {
b93463aa
AK		 5646 case KVM_HC_VAPIC_POLL_IRQ:
5647 ret = 0;
5648 break;
6aef266c
SV		 5649 case KVM_HC_KICK_CPU:
5650 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5651 ret = 0;
5652 break;
8776e519
HB		 5653 default:
5654 ret = -KVM_ENOSYS;
5655 break;
5656 }
07708c4a 5657out:
5fdbf976 5658 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5659 ++vcpu->stat.hypercalls;
2f333bcb 5660 return r;
8776e519
HB		 5661}
5662EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5663
b6785def 5664static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5665{
d6aa1000 5666 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5667 char instruction[3];
5fdbf976 5668 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5669
8776e519 5670 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5671
9d74191a 5672 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5673}
5674
b6c7a5dc
HB		 5675/*
5676 * Check if userspace requested an interrupt window, and that the
5677 * interrupt window is open.
5678 *
5679 * No need to exit to userspace if we already have an interrupt queued.
5680 */
851ba692 5681static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5682{
8061823a 5683 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5684 vcpu->run->request_interrupt_window &&
5df56646 5685 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5686}
5687
851ba692 5688static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5689{
851ba692
AK		 5690 struct kvm_run *kvm_run = vcpu->run;
5691
91586a3b 5692 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5693 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5694 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5695 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5696 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5697 else
b6c7a5dc 5698 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5699 kvm_arch_interrupt_allowed(vcpu) &&
5700 !kvm_cpu_has_interrupt(vcpu) &&
5701 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5702}
5703
4484141a 5704static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5705{
5706 struct kvm_lapic *apic = vcpu->arch.apic;
5707 struct page *page;
5708
5709 if (!apic || !apic->vapic_addr)
4484141a 5710 return 0;
b93463aa
AK		 5711
5712 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5713 if (is_error_page(page))
5714 return -EFAULT;
72dc67a6
IE		 5715
5716 vcpu->arch.apic->vapic_page = page;
4484141a 5717 return 0;
b93463aa
AK		 5718}
5719
5720static void vapic_exit(struct kvm_vcpu *vcpu)
5721{
5722 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5723 int idx;
b93463aa
AK		 5724
5725 if (!apic || !apic->vapic_addr)
5726 return;
5727
f656ce01 5728 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5729 kvm_release_page_dirty(apic->vapic_page);
5730 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5731 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5732}
5733
95ba8273
GN		 5734static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5735{
5736 int max_irr, tpr;
5737
5738 if (!kvm_x86_ops->update_cr8_intercept)
5739 return;
5740
88c808fd
AK		 5741 if (!vcpu->arch.apic)
5742 return;
5743
8db3baa2
GN		 5744 if (!vcpu->arch.apic->vapic_addr)
5745 max_irr = kvm_lapic_find_highest_irr(vcpu);
5746 else
5747 max_irr = -1;
95ba8273
GN		 5748
5749 if (max_irr != -1)
5750 max_irr >>= 4;
5751
5752 tpr = kvm_lapic_get_cr8(vcpu);
5753
5754 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5755}
5756
851ba692 5757static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5758{
5759 /* try to reinject previous events if any */
b59bb7bd 5760 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5761 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5762 vcpu->arch.exception.has_error_code,
5763 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5764 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5765 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5766 vcpu->arch.exception.error_code,
5767 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5768 return;
5769 }
5770
95ba8273
GN		 5771 if (vcpu->arch.nmi_injected) {
5772 kvm_x86_ops->set_nmi(vcpu);
5773 return;
5774 }
5775
5776 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5777 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5778 return;
5779 }
5780
5781 /* try to inject new event if pending */
5782 if (vcpu->arch.nmi_pending) {
5783 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5784 --vcpu->arch.nmi_pending;
95ba8273
GN		 5785 vcpu->arch.nmi_injected = true;
5786 kvm_x86_ops->set_nmi(vcpu);
5787 }
c7c9c56c 5788 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5789 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5790 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5791 false);
5792 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5793 }
5794 }
5795}
5796
7460fb4a
AK		 5797static void process_nmi(struct kvm_vcpu *vcpu)
5798{
5799 unsigned limit = 2;
5800
5801 /*
5802 * x86 is limited to one NMI running, and one NMI pending after it.
5803 * If an NMI is already in progress, limit further NMIs to just one.
5804 * Otherwise, allow two (and we'll inject the first one immediately).
5805 */
5806 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5807 limit = 1;
5808
5809 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5810 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5811 kvm_make_request(KVM_REQ_EVENT, vcpu);
5812}
5813
3d81bc7e 5814static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5815{
5816 u64 eoi_exit_bitmap[4];
cf9e65b7 5817 u32 tmr[8];
c7c9c56c 5818
3d81bc7e
YZ		 5819 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5820 return;
c7c9c56c
YZ		 5821
5822 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5823 memset(tmr, 0, 32);
c7c9c56c 5824
cf9e65b7 5825 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5826 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5827 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5828}
5829
9357d939
TY		 5830/*
5831 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5832 * exiting to the userspace. Otherwise, the value will be returned to the
5833 * userspace.
5834 */
851ba692 5835static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5836{
5837 int r;
6a8b1d13 5838 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5839 vcpu->run->request_interrupt_window;
730dca42 5840 bool req_immediate_exit = false;
b6c7a5dc 5841
3e007509 5842 if (vcpu->requests) {
a8eeb04a 5843 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5844 kvm_mmu_unload(vcpu);
a8eeb04a 5845 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5846 __kvm_migrate_timers(vcpu);
d828199e
MT		 5847 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5848 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5849 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5850 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5851 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5852 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5853 if (unlikely(r))
5854 goto out;
5855 }
a8eeb04a 5856 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5857 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5858 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5859 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5860 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5861 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5862 r = 0;
5863 goto out;
5864 }
a8eeb04a 5865 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5866 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5867 r = 0;
5868 goto out;
5869 }
a8eeb04a 5870 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5871 vcpu->fpu_active = 0;
5872 kvm_x86_ops->fpu_deactivate(vcpu);
5873 }
af585b92
GN		 5874 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5875 /* Page is swapped out. Do synthetic halt */
5876 vcpu->arch.apf.halted = true;
5877 r = 1;
5878 goto out;
5879 }
c9aaa895
GC		 5880 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5881 record_steal_time(vcpu);
7460fb4a
AK		 5882 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5883 process_nmi(vcpu);
f5132b01
GN		 5884 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5885 kvm_handle_pmu_event(vcpu);
5886 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5887 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5888 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5889 vcpu_scan_ioapic(vcpu);
2f52d58c 5890 }
b93463aa 5891
b463a6f7 5892 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5893 kvm_apic_accept_events(vcpu);
5894 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5895 r = 1;
5896 goto out;
5897 }
5898
b463a6f7
AK		 5899 inject_pending_event(vcpu);
5900
5901 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5902 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5903 req_immediate_exit =
5904 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5905 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5906 req_immediate_exit =
5907 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5908
5909 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5910 /*
5911 * Update architecture specific hints for APIC
5912 * virtual interrupt delivery.
5913 */
5914 if (kvm_x86_ops->hwapic_irr_update)
5915 kvm_x86_ops->hwapic_irr_update(vcpu,
5916 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5917 update_cr8_intercept(vcpu);
5918 kvm_lapic_sync_to_vapic(vcpu);
5919 }
5920 }
5921
d8368af8
AK		 5922 r = kvm_mmu_reload(vcpu);
5923 if (unlikely(r)) {
d905c069 5924 goto cancel_injection;
d8368af8
AK		 5925 }
5926
b6c7a5dc
HB		 5927 preempt_disable();
5928
5929 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5930 if (vcpu->fpu_active)
5931 kvm_load_guest_fpu(vcpu);
2acf923e 5932 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5933
6b7e2d09
XG		 5934 vcpu->mode = IN_GUEST_MODE;
5935
01b71917
MT		 5936 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5937
6b7e2d09
XG		 5938 /* We should set ->mode before check ->requests,
5939 * see the comment in make_all_cpus_request.
5940 */
01b71917 5941 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5942
d94e1dc9 5943 local_irq_disable();
32f88400 5944
6b7e2d09 5945 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5946 || need_resched() || signal_pending(current)) {
6b7e2d09 5947 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5948 smp_wmb();
6c142801
AK		 5949 local_irq_enable();
5950 preempt_enable();
01b71917 5951 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5952 r = 1;
d905c069 5953 goto cancel_injection;
6c142801
AK		 5954 }
5955
d6185f20
NHE		 5956 if (req_immediate_exit)
5957 smp_send_reschedule(vcpu->cpu);
5958
b6c7a5dc
HB		 5959 kvm_guest_enter();
5960
42dbaa5a 5961 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5962 set_debugreg(0, 7);
5963 set_debugreg(vcpu->arch.eff_db[0], 0);
5964 set_debugreg(vcpu->arch.eff_db[1], 1);
5965 set_debugreg(vcpu->arch.eff_db[2], 2);
5966 set_debugreg(vcpu->arch.eff_db[3], 3);
5967 }
b6c7a5dc 5968
229456fc 5969 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5970 kvm_x86_ops->run(vcpu);
b6c7a5dc 5971
24f1e32c
FW		 5972 /*
5973 * If the guest has used debug registers, at least dr7
5974 * will be disabled while returning to the host.
5975 * If we don't have active breakpoints in the host, we don't
5976 * care about the messed up debug address registers. But if
5977 * we have some of them active, restore the old state.
5978 */
59d8eb53 5979 if (hw_breakpoint_active())
24f1e32c 5980 hw_breakpoint_restore();
42dbaa5a 5981
886b470c
MT		 5982 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5983 native_read_tsc());
1d5f066e 5984
6b7e2d09 5985 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5986 smp_wmb();
a547c6db
YZ		 5987
5988 /* Interrupt is enabled by handle_external_intr() */
5989 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 5990
5991 ++vcpu->stat.exits;
5992
5993 /*
5994 * We must have an instruction between local_irq_enable() and
5995 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5996 * the interrupt shadow. The stat.exits increment will do nicely.
5997 * But we need to prevent reordering, hence this barrier():
5998 */
5999 barrier();
6000
6001 kvm_guest_exit();
6002
6003 preempt_enable();
6004
f656ce01 6005 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6006
b6c7a5dc
HB		 6007 /*
6008 * Profile KVM exit RIPs:
6009 */
6010 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6011 unsigned long rip = kvm_rip_read(vcpu);
6012 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6013 }
6014
cc578287
ZA		 6015 if (unlikely(vcpu->arch.tsc_always_catchup))
6016 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6017
5cfb1d5a
MT		 6018 if (vcpu->arch.apic_attention)
6019 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6020
851ba692 6021 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6022 return r;
6023
6024cancel_injection:
6025 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6026 if (unlikely(vcpu->arch.apic_attention))
6027 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6028out:
6029 return r;
6030}
b6c7a5dc 6031
09cec754 6032
851ba692 6033static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6034{
6035 int r;
f656ce01 6036 struct kvm *kvm = vcpu->kvm;
d7690175 6037
f656ce01 6038 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 6039 r = vapic_enter(vcpu);
6040 if (r) {
6041 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6042 return r;
6043 }
d7690175
MT		 6044
6045 r = 1;
6046 while (r > 0) {
af585b92
GN		 6047 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6048 !vcpu->arch.apf.halted)
851ba692 6049 r = vcpu_enter_guest(vcpu);
d7690175 6050 else {
f656ce01 6051 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6052 kvm_vcpu_block(vcpu);
f656ce01 6053 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6054 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6055 kvm_apic_accept_events(vcpu);
09cec754
GN		 6056 switch(vcpu->arch.mp_state) {
6057 case KVM_MP_STATE_HALTED:
6aef266c 6058 vcpu->arch.pv.pv_unhalted = false;
d7690175 6059 vcpu->arch.mp_state =
09cec754
GN		 6060 KVM_MP_STATE_RUNNABLE;
6061 case KVM_MP_STATE_RUNNABLE:
af585b92 6062 vcpu->arch.apf.halted = false;
09cec754 6063 break;
66450a21
JK		 6064 case KVM_MP_STATE_INIT_RECEIVED:
6065 break;
09cec754
GN		 6066 default:
6067 r = -EINTR;
6068 break;
6069 }
6070 }
d7690175
MT		 6071 }
6072
09cec754
GN		 6073 if (r <= 0)
6074 break;
6075
6076 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6077 if (kvm_cpu_has_pending_timer(vcpu))
6078 kvm_inject_pending_timer_irqs(vcpu);
6079
851ba692 6080 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6081 r = -EINTR;
851ba692 6082 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6083 ++vcpu->stat.request_irq_exits;
6084 }
af585b92
GN		 6085
6086 kvm_check_async_pf_completion(vcpu);
6087
09cec754
GN		 6088 if (signal_pending(current)) {
6089 r = -EINTR;
851ba692 6090 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6091 ++vcpu->stat.signal_exits;
6092 }
6093 if (need_resched()) {
f656ce01 6094 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6095 cond_resched();
f656ce01 6096 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6097 }
b6c7a5dc
HB		 6098 }
6099
f656ce01 6100 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 6101
b93463aa
AK		 6102 vapic_exit(vcpu);
6103
b6c7a5dc
HB		 6104 return r;
6105}
6106
716d51ab
GN		 6107static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6108{
6109 int r;
6110 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6111 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6112 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6113 if (r != EMULATE_DONE)
6114 return 0;
6115 return 1;
6116}
6117
6118static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6119{
6120 BUG_ON(!vcpu->arch.pio.count);
6121
6122 return complete_emulated_io(vcpu);
6123}
6124
f78146b0
AK		 6125/*
6126 * Implements the following, as a state machine:
6127 *
6128 * read:
6129 * for each fragment
87da7e66
XG		 6130 * for each mmio piece in the fragment
6131 * write gpa, len
6132 * exit
6133 * copy data
f78146b0
AK		 6134 * execute insn
6135 *
6136 * write:
6137 * for each fragment
87da7e66
XG		 6138 * for each mmio piece in the fragment
6139 * write gpa, len
6140 * copy data
6141 * exit
f78146b0 6142 */
716d51ab 6143static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6144{
6145 struct kvm_run *run = vcpu->run;
f78146b0 6146 struct kvm_mmio_fragment *frag;
87da7e66 6147 unsigned len;
5287f194 6148
716d51ab 6149 BUG_ON(!vcpu->mmio_needed);
5287f194 6150
716d51ab 6151 /* Complete previous fragment */
87da7e66
XG		 6152 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6153 len = min(8u, frag->len);
716d51ab 6154 if (!vcpu->mmio_is_write)
87da7e66
XG		 6155 memcpy(frag->data, run->mmio.data, len);
6156
6157 if (frag->len <= 8) {
6158 /* Switch to the next fragment. */
6159 frag++;
6160 vcpu->mmio_cur_fragment++;
6161 } else {
6162 /* Go forward to the next mmio piece. */
6163 frag->data += len;
6164 frag->gpa += len;
6165 frag->len -= len;
6166 }
6167
716d51ab
GN		 6168 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6169 vcpu->mmio_needed = 0;
0912c977
PB		 6170
6171 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6172 if (vcpu->mmio_is_write)
716d51ab
GN		 6173 return 1;
6174 vcpu->mmio_read_completed = 1;
6175 return complete_emulated_io(vcpu);
6176 }
87da7e66 6177
716d51ab
GN		 6178 run->exit_reason = KVM_EXIT_MMIO;
6179 run->mmio.phys_addr = frag->gpa;
6180 if (vcpu->mmio_is_write)
87da7e66
XG		 6181 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6182 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6183 run->mmio.is_write = vcpu->mmio_is_write;
6184 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6185 return 0;
5287f194
AK		 6186}
6187
716d51ab 6188
b6c7a5dc
HB		 6189int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6190{
6191 int r;
6192 sigset_t sigsaved;
6193
e5c30142
AK		 6194 if (!tsk_used_math(current) && init_fpu(current))
6195 return -ENOMEM;
6196
ac9f6dc0
AK		 6197 if (vcpu->sigset_active)
6198 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6199
a4535290 6200 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6201 kvm_vcpu_block(vcpu);
66450a21 6202 kvm_apic_accept_events(vcpu);
d7690175 6203 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6204 r = -EAGAIN;
6205 goto out;
b6c7a5dc
HB		 6206 }
6207
b6c7a5dc 6208 /* re-sync apic's tpr */
eea1cff9
AP		 6209 if (!irqchip_in_kernel(vcpu->kvm)) {
6210 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6211 r = -EINVAL;
6212 goto out;
6213 }
6214 }
b6c7a5dc 6215
716d51ab
GN		 6216 if (unlikely(vcpu->arch.complete_userspace_io)) {
6217 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6218 vcpu->arch.complete_userspace_io = NULL;
6219 r = cui(vcpu);
6220 if (r <= 0)
6221 goto out;
6222 } else
6223 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6224
851ba692 6225 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6226
6227out:
f1d86e46 6228 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6229 if (vcpu->sigset_active)
6230 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6231
b6c7a5dc
HB		 6232 return r;
6233}
6234
6235int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6236{
7ae441ea
GN		 6237 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6238 /*
6239 * We are here if userspace calls get_regs() in the middle of
6240 * instruction emulation. Registers state needs to be copied
4a969980 6241 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6242 * that usually, but some bad designed PV devices (vmware
6243 * backdoor interface) need this to work
6244 */
dd856efa 6245 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6246 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6247 }
5fdbf976
MT		 6248 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6249 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6250 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6251 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6252 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6253 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6254 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6255 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6256#ifdef CONFIG_X86_64
5fdbf976
MT		 6257 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6258 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6259 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6260 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6261 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6262 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6263 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6264 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6265#endif
6266
5fdbf976 6267 regs->rip = kvm_rip_read(vcpu);
91586a3b 6268 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6269
b6c7a5dc
HB		 6270 return 0;
6271}
6272
6273int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6274{
7ae441ea
GN		 6275 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6276 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6277
5fdbf976
MT		 6278 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6279 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6280 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6281 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6282 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6283 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6284 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6285 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6286#ifdef CONFIG_X86_64
5fdbf976
MT		 6287 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6288 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6289 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6290 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6291 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6292 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6293 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6294 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6295#endif
6296
5fdbf976 6297 kvm_rip_write(vcpu, regs->rip);
91586a3b 6298 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6299
b4f14abd
JK		 6300 vcpu->arch.exception.pending = false;
6301
3842d135
AK		 6302 kvm_make_request(KVM_REQ_EVENT, vcpu);
6303
b6c7a5dc
HB		 6304 return 0;
6305}
6306
b6c7a5dc
HB		 6307void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6308{
6309 struct kvm_segment cs;
6310
3e6e0aab 6311 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6312 *db = cs.db;
6313 *l = cs.l;
6314}
6315EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6316
6317int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6318 struct kvm_sregs *sregs)
6319{
89a27f4d 6320 struct desc_ptr dt;
b6c7a5dc 6321
3e6e0aab
GT		 6322 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6323 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6324 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6325 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6326 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6327 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6328
3e6e0aab
GT		 6329 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6330 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6331
6332 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6333 sregs->idt.limit = dt.size;
6334 sregs->idt.base = dt.address;
b6c7a5dc 6335 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6336 sregs->gdt.limit = dt.size;
6337 sregs->gdt.base = dt.address;
b6c7a5dc 6338
4d4ec087 6339 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6340 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6341 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6342 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6343 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6344 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6345 sregs->apic_base = kvm_get_apic_base(vcpu);
6346
923c61bb 6347 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6348
36752c9b 6349 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6350 set_bit(vcpu->arch.interrupt.nr,
6351 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6352
b6c7a5dc
HB		 6353 return 0;
6354}
6355
62d9f0db
MT		 6356int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6357 struct kvm_mp_state *mp_state)
6358{
66450a21 6359 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6360 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6361 vcpu->arch.pv.pv_unhalted)
6362 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6363 else
6364 mp_state->mp_state = vcpu->arch.mp_state;
6365
62d9f0db
MT		 6366 return 0;
6367}
6368
6369int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6370 struct kvm_mp_state *mp_state)
6371{
66450a21
JK		 6372 if (!kvm_vcpu_has_lapic(vcpu) &&
6373 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6374 return -EINVAL;
6375
6376 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6377 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6378 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6379 } else
6380 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6381 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6382 return 0;
6383}
6384
7f3d35fd
KW		 6385int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6386 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6387{
9d74191a 6388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6389 int ret;
e01c2426 6390
8ec4722d 6391 init_emulate_ctxt(vcpu);
c697518a 6392
7f3d35fd 6393 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6394 has_error_code, error_code);
c697518a 6395
c697518a 6396 if (ret)
19d04437 6397 return EMULATE_FAIL;
37817f29 6398
9d74191a
TY		 6399 kvm_rip_write(vcpu, ctxt->eip);
6400 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6401 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6402 return EMULATE_DONE;
37817f29
IE		 6403}
6404EXPORT_SYMBOL_GPL(kvm_task_switch);
6405
b6c7a5dc
HB		 6406int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6407 struct kvm_sregs *sregs)
6408{
6409 int mmu_reset_needed = 0;
63f42e02 6410 int pending_vec, max_bits, idx;
89a27f4d 6411 struct desc_ptr dt;
b6c7a5dc 6412
6d1068b3
PM		 6413 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6414 return -EINVAL;
6415
89a27f4d
GN		 6416 dt.size = sregs->idt.limit;
6417 dt.address = sregs->idt.base;
b6c7a5dc 6418 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6419 dt.size = sregs->gdt.limit;
6420 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6421 kvm_x86_ops->set_gdt(vcpu, &dt);
6422
ad312c7c 6423 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6424 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6425 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6426 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6427
2d3ad1f4 6428 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6429
f6801dff 6430 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6431 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6432 kvm_set_apic_base(vcpu, sregs->apic_base);
6433
4d4ec087 6434 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6435 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6436 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6437
fc78f519 6438 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6439 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6440 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6441 kvm_update_cpuid(vcpu);
63f42e02
XG		 6442
6443 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6444 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6445 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6446 mmu_reset_needed = 1;
6447 }
63f42e02 6448 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6449
6450 if (mmu_reset_needed)
6451 kvm_mmu_reset_context(vcpu);
6452
a50abc3b 6453 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6454 pending_vec = find_first_bit(
6455 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6456 if (pending_vec < max_bits) {
66fd3f7f 6457 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6458 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6459 }
6460
3e6e0aab
GT		 6461 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6462 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6463 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6464 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6465 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6466 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6467
3e6e0aab
GT		 6468 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6469 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6470
5f0269f5
ME		 6471 update_cr8_intercept(vcpu);
6472
9c3e4aab 6473 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6474 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6475 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6476 !is_protmode(vcpu))
9c3e4aab
MT		 6477 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6478
3842d135
AK		 6479 kvm_make_request(KVM_REQ_EVENT, vcpu);
6480
b6c7a5dc
HB		 6481 return 0;
6482}
6483
d0bfb940
JK		 6484int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6485 struct kvm_guest_debug *dbg)
b6c7a5dc 6486{
355be0b9 6487 unsigned long rflags;
ae675ef0 6488 int i, r;
b6c7a5dc 6489
4f926bf2
JK		 6490 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6491 r = -EBUSY;
6492 if (vcpu->arch.exception.pending)
2122ff5e 6493 goto out;
4f926bf2
JK		 6494 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6495 kvm_queue_exception(vcpu, DB_VECTOR);
6496 else
6497 kvm_queue_exception(vcpu, BP_VECTOR);
6498 }
6499
91586a3b
JK		 6500 /*
6501 * Read rflags as long as potentially injected trace flags are still
6502 * filtered out.
6503 */
6504 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6505
6506 vcpu->guest_debug = dbg->control;
6507 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6508 vcpu->guest_debug = 0;
6509
6510 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6511 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6512 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6513 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6514 } else {
6515 for (i = 0; i < KVM_NR_DB_REGS; i++)
6516 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6517 }
c8639010 6518 kvm_update_dr7(vcpu);
ae675ef0 6519
f92653ee
JK		 6520 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6521 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6522 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6523
91586a3b
JK		 6524 /*
6525 * Trigger an rflags update that will inject or remove the trace
6526 * flags.
6527 */
6528 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6529
c8639010 6530 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6531
4f926bf2 6532 r = 0;
d0bfb940 6533
2122ff5e 6534out:
b6c7a5dc
HB		 6535
6536 return r;
6537}
6538
8b006791
ZX		 6539/*
6540 * Translate a guest virtual address to a guest physical address.
6541 */
6542int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6543 struct kvm_translation *tr)
6544{
6545 unsigned long vaddr = tr->linear_address;
6546 gpa_t gpa;
f656ce01 6547 int idx;
8b006791 6548
f656ce01 6549 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6550 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6551 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6552 tr->physical_address = gpa;
6553 tr->valid = gpa != UNMAPPED_GVA;
6554 tr->writeable = 1;
6555 tr->usermode = 0;
8b006791
ZX		 6556
6557 return 0;
6558}
6559
d0752060
HB		 6560int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6561{
98918833
SY		 6562 struct i387_fxsave_struct *fxsave =
6563 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6564
d0752060
HB		 6565 memcpy(fpu->fpr, fxsave->st_space, 128);
6566 fpu->fcw = fxsave->cwd;
6567 fpu->fsw = fxsave->swd;
6568 fpu->ftwx = fxsave->twd;
6569 fpu->last_opcode = fxsave->fop;
6570 fpu->last_ip = fxsave->rip;
6571 fpu->last_dp = fxsave->rdp;
6572 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6573
d0752060
HB		 6574 return 0;
6575}
6576
6577int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6578{
98918833
SY		 6579 struct i387_fxsave_struct *fxsave =
6580 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6581
d0752060
HB		 6582 memcpy(fxsave->st_space, fpu->fpr, 128);
6583 fxsave->cwd = fpu->fcw;
6584 fxsave->swd = fpu->fsw;
6585 fxsave->twd = fpu->ftwx;
6586 fxsave->fop = fpu->last_opcode;
6587 fxsave->rip = fpu->last_ip;
6588 fxsave->rdp = fpu->last_dp;
6589 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6590
d0752060
HB		 6591 return 0;
6592}
6593
10ab25cd 6594int fx_init(struct kvm_vcpu *vcpu)
d0752060 6595{
10ab25cd
JK		 6596 int err;
6597
6598 err = fpu_alloc(&vcpu->arch.guest_fpu);
6599 if (err)
6600 return err;
6601
98918833 6602 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6603
2acf923e
DC		 6604 /*
6605 * Ensure guest xcr0 is valid for loading
6606 */
6607 vcpu->arch.xcr0 = XSTATE_FP;
6608
ad312c7c 6609 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6610
6611 return 0;
d0752060
HB		 6612}
6613EXPORT_SYMBOL_GPL(fx_init);
6614
98918833
SY		 6615static void fx_free(struct kvm_vcpu *vcpu)
6616{
6617 fpu_free(&vcpu->arch.guest_fpu);
6618}
6619
d0752060
HB		 6620void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6621{
2608d7a1 6622 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6623 return;
6624
2acf923e
DC		 6625 /*
6626 * Restore all possible states in the guest,
6627 * and assume host would use all available bits.
6628 * Guest xcr0 would be loaded later.
6629 */
6630 kvm_put_guest_xcr0(vcpu);
d0752060 6631 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6632 __kernel_fpu_begin();
98918833 6633 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6634 trace_kvm_fpu(1);
d0752060 6635}
d0752060
HB		 6636
6637void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6638{
2acf923e
DC		 6639 kvm_put_guest_xcr0(vcpu);
6640
d0752060
HB		 6641 if (!vcpu->guest_fpu_loaded)
6642 return;
6643
6644 vcpu->guest_fpu_loaded = 0;
98918833 6645 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6646 __kernel_fpu_end();
f096ed85 6647 ++vcpu->stat.fpu_reload;
a8eeb04a 6648 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6649 trace_kvm_fpu(0);
d0752060 6650}
e9b11c17
ZX		 6651
6652void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6653{
12f9a48f 6654 kvmclock_reset(vcpu);
7f1ea208 6655
f5f48ee1 6656 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6657 fx_free(vcpu);
e9b11c17
ZX		 6658 kvm_x86_ops->vcpu_free(vcpu);
6659}
6660
6661struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6662 unsigned int id)
6663{
6755bae8
ZA		 6664 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6665 printk_once(KERN_WARNING
6666 "kvm: SMP vm created on host with unstable TSC; "
6667 "guest TSC will not be reliable\n");
26e5215f
AK		 6668 return kvm_x86_ops->vcpu_create(kvm, id);
6669}
e9b11c17 6670
26e5215f
AK		 6671int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6672{
6673 int r;
e9b11c17 6674
0bed3b56 6675 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6676 r = vcpu_load(vcpu);
6677 if (r)
6678 return r;
57f252f2 6679 kvm_vcpu_reset(vcpu);
8a3c1a33 6680 kvm_mmu_setup(vcpu);
e9b11c17 6681 vcpu_put(vcpu);
e9b11c17 6682
26e5215f 6683 return r;
e9b11c17
ZX		 6684}
6685
42897d86
MT		 6686int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6687{
6688 int r;
8fe8ab46 6689 struct msr_data msr;
42897d86
MT		 6690
6691 r = vcpu_load(vcpu);
6692 if (r)
6693 return r;
8fe8ab46
WA		 6694 msr.data = 0x0;
6695 msr.index = MSR_IA32_TSC;
6696 msr.host_initiated = true;
6697 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6698 vcpu_put(vcpu);
6699
6700 return r;
6701}
6702
d40ccc62 6703void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6704{
9fc77441 6705 int r;
344d9588
GN		 6706 vcpu->arch.apf.msr_val = 0;
6707
9fc77441
MT		 6708 r = vcpu_load(vcpu);
6709 BUG_ON(r);
e9b11c17
ZX		 6710 kvm_mmu_unload(vcpu);
6711 vcpu_put(vcpu);
6712
98918833 6713 fx_free(vcpu);
e9b11c17
ZX		 6714 kvm_x86_ops->vcpu_free(vcpu);
6715}
6716
66450a21 6717void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6718{
7460fb4a
AK		 6719 atomic_set(&vcpu->arch.nmi_queued, 0);
6720 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6721 vcpu->arch.nmi_injected = false;
6722
42dbaa5a
JK		 6723 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6724 vcpu->arch.dr6 = DR6_FIXED_1;
6725 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6726 kvm_update_dr7(vcpu);
42dbaa5a 6727
3842d135 6728 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6729 vcpu->arch.apf.msr_val = 0;
c9aaa895 6730 vcpu->arch.st.msr_val = 0;
3842d135 6731
12f9a48f
GC		 6732 kvmclock_reset(vcpu);
6733
af585b92
GN		 6734 kvm_clear_async_pf_completion_queue(vcpu);
6735 kvm_async_pf_hash_reset(vcpu);
6736 vcpu->arch.apf.halted = false;
3842d135 6737
f5132b01
GN		 6738 kvm_pmu_reset(vcpu);
6739
66f7b72e
JS		 6740 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6741 vcpu->arch.regs_avail = ~0;
6742 vcpu->arch.regs_dirty = ~0;
6743
57f252f2 6744 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6745}
6746
66450a21
JK		 6747void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6748{
6749 struct kvm_segment cs;
6750
6751 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6752 cs.selector = vector << 8;
6753 cs.base = vector << 12;
6754 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6755 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6756}
6757
10474ae8 6758int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6759{
ca84d1a2
ZA		 6760 struct kvm *kvm;
6761 struct kvm_vcpu *vcpu;
6762 int i;
0dd6a6ed
ZA		 6763 int ret;
6764 u64 local_tsc;
6765 u64 max_tsc = 0;
6766 bool stable, backwards_tsc = false;
18863bdd
AK		 6767
6768 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6769 ret = kvm_x86_ops->hardware_enable(garbage);
6770 if (ret != 0)
6771 return ret;
6772
6773 local_tsc = native_read_tsc();
6774 stable = !check_tsc_unstable();
6775 list_for_each_entry(kvm, &vm_list, vm_list) {
6776 kvm_for_each_vcpu(i, vcpu, kvm) {
6777 if (!stable && vcpu->cpu == smp_processor_id())
6778 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6779 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6780 backwards_tsc = true;
6781 if (vcpu->arch.last_host_tsc > max_tsc)
6782 max_tsc = vcpu->arch.last_host_tsc;
6783 }
6784 }
6785 }
6786
6787 /*
6788 * Sometimes, even reliable TSCs go backwards. This happens on
6789 * platforms that reset TSC during suspend or hibernate actions, but
6790 * maintain synchronization. We must compensate. Fortunately, we can
6791 * detect that condition here, which happens early in CPU bringup,
6792 * before any KVM threads can be running. Unfortunately, we can't
6793 * bring the TSCs fully up to date with real time, as we aren't yet far
6794 * enough into CPU bringup that we know how much real time has actually
6795 * elapsed; our helper function, get_kernel_ns() will be using boot
6796 * variables that haven't been updated yet.
6797 *
6798 * So we simply find the maximum observed TSC above, then record the
6799 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6800 * the adjustment will be applied. Note that we accumulate
6801 * adjustments, in case multiple suspend cycles happen before some VCPU
6802 * gets a chance to run again. In the event that no KVM threads get a
6803 * chance to run, we will miss the entire elapsed period, as we'll have
6804 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6805 * loose cycle time. This isn't too big a deal, since the loss will be
6806 * uniform across all VCPUs (not to mention the scenario is extremely
6807 * unlikely). It is possible that a second hibernate recovery happens
6808 * much faster than a first, causing the observed TSC here to be
6809 * smaller; this would require additional padding adjustment, which is
6810 * why we set last_host_tsc to the local tsc observed here.
6811 *
6812 * N.B. - this code below runs only on platforms with reliable TSC,
6813 * as that is the only way backwards_tsc is set above. Also note
6814 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6815 * have the same delta_cyc adjustment applied if backwards_tsc
6816 * is detected. Note further, this adjustment is only done once,
6817 * as we reset last_host_tsc on all VCPUs to stop this from being
6818 * called multiple times (one for each physical CPU bringup).
6819 *
4a969980 6820 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6821 * will be compensated by the logic in vcpu_load, which sets the TSC to
6822 * catchup mode. This will catchup all VCPUs to real time, but cannot
6823 * guarantee that they stay in perfect synchronization.
6824 */
6825 if (backwards_tsc) {
6826 u64 delta_cyc = max_tsc - local_tsc;
6827 list_for_each_entry(kvm, &vm_list, vm_list) {
6828 kvm_for_each_vcpu(i, vcpu, kvm) {
6829 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6830 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6831 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6832 &vcpu->requests);
0dd6a6ed
ZA		 6833 }
6834
6835 /*
6836 * We have to disable TSC offset matching.. if you were
6837 * booting a VM while issuing an S4 host suspend....
6838 * you may have some problem. Solving this issue is
6839 * left as an exercise to the reader.
6840 */
6841 kvm->arch.last_tsc_nsec = 0;
6842 kvm->arch.last_tsc_write = 0;
6843 }
6844
6845 }
6846 return 0;
e9b11c17
ZX		 6847}
6848
6849void kvm_arch_hardware_disable(void *garbage)
6850{
6851 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6852 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6853}
6854
6855int kvm_arch_hardware_setup(void)
6856{
6857 return kvm_x86_ops->hardware_setup();
6858}
6859
6860void kvm_arch_hardware_unsetup(void)
6861{
6862 kvm_x86_ops->hardware_unsetup();
6863}
6864
6865void kvm_arch_check_processor_compat(void *rtn)
6866{
6867 kvm_x86_ops->check_processor_compatibility(rtn);
6868}
6869
3e515705
AK		 6870bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6871{
6872 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6873}
6874
54e9818f
GN		 6875struct static_key kvm_no_apic_vcpu __read_mostly;
6876
e9b11c17
ZX		 6877int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6878{
6879 struct page *page;
6880 struct kvm *kvm;
6881 int r;
6882
6883 BUG_ON(vcpu->kvm == NULL);
6884 kvm = vcpu->kvm;
6885
6aef266c 6886 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6887 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6888 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6889 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6890 else
a4535290 6891 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6892
6893 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6894 if (!page) {
6895 r = -ENOMEM;
6896 goto fail;
6897 }
ad312c7c 6898 vcpu->arch.pio_data = page_address(page);
e9b11c17 6899
cc578287 6900 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6901
e9b11c17
ZX		 6902 r = kvm_mmu_create(vcpu);
6903 if (r < 0)
6904 goto fail_free_pio_data;
6905
6906 if (irqchip_in_kernel(kvm)) {
6907 r = kvm_create_lapic(vcpu);
6908 if (r < 0)
6909 goto fail_mmu_destroy;
54e9818f
GN		 6910 } else
6911 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6912
890ca9ae
HY		 6913 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6914 GFP_KERNEL);
6915 if (!vcpu->arch.mce_banks) {
6916 r = -ENOMEM;
443c39bc 6917 goto fail_free_lapic;
890ca9ae
HY		 6918 }
6919 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6920
f1797359
WY		 6921 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6922 r = -ENOMEM;
f5f48ee1 6923 goto fail_free_mce_banks;
f1797359 6924 }
f5f48ee1 6925
66f7b72e
JS		 6926 r = fx_init(vcpu);
6927 if (r)
6928 goto fail_free_wbinvd_dirty_mask;
6929
ba904635 6930 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6931 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6932
6933 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6934 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6935
af585b92 6936 kvm_async_pf_hash_reset(vcpu);
f5132b01 6937 kvm_pmu_init(vcpu);
af585b92 6938
e9b11c17 6939 return 0;
66f7b72e
JS		 6940fail_free_wbinvd_dirty_mask:
6941 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6942fail_free_mce_banks:
6943 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6944fail_free_lapic:
6945 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6946fail_mmu_destroy:
6947 kvm_mmu_destroy(vcpu);
6948fail_free_pio_data:
ad312c7c 6949 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6950fail:
6951 return r;
6952}
6953
6954void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6955{
f656ce01
MT		 6956 int idx;
6957
f5132b01 6958 kvm_pmu_destroy(vcpu);
36cb93fd 6959 kfree(vcpu->arch.mce_banks);
e9b11c17 6960 kvm_free_lapic(vcpu);
f656ce01 6961 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6962 kvm_mmu_destroy(vcpu);
f656ce01 6963 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6964 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6965 if (!irqchip_in_kernel(vcpu->kvm))
6966 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6967}
d19a9cd2 6968
e08b9637 6969int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6970{
e08b9637
CO		 6971 if (type)
6972 return -EINVAL;
6973
f05e70ac 6974 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 6975 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 6976 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 6977 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 6978
5550af4d
SY		 6979 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6980 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6981 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6982 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6983 &kvm->arch.irq_sources_bitmap);
5550af4d 6984
038f8c11 6985 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6986 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6987 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6988
6989 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6990
d89f5eff 6991 return 0;
d19a9cd2
ZX		 6992}
6993
6994static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6995{
9fc77441
MT		 6996 int r;
6997 r = vcpu_load(vcpu);
6998 BUG_ON(r);
d19a9cd2
ZX		 6999 kvm_mmu_unload(vcpu);
7000 vcpu_put(vcpu);
7001}
7002
7003static void kvm_free_vcpus(struct kvm *kvm)
7004{
7005 unsigned int i;
988a2cae 7006 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7007
7008 /*
7009 * Unpin any mmu pages first.
7010 */
af585b92
GN		 7011 kvm_for_each_vcpu(i, vcpu, kvm) {
7012 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7013 kvm_unload_vcpu_mmu(vcpu);
af585b92 7014 }
988a2cae
GN		 7015 kvm_for_each_vcpu(i, vcpu, kvm)
7016 kvm_arch_vcpu_free(vcpu);
7017
7018 mutex_lock(&kvm->lock);
7019 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7020 kvm->vcpus[i] = NULL;
d19a9cd2 7021
988a2cae
GN		 7022 atomic_set(&kvm->online_vcpus, 0);
7023 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7024}
7025
ad8ba2cd
SY		 7026void kvm_arch_sync_events(struct kvm *kvm)
7027{
ba4cef31 7028 kvm_free_all_assigned_devices(kvm);
aea924f6 7029 kvm_free_pit(kvm);
ad8ba2cd
SY		 7030}
7031
d19a9cd2
ZX		 7032void kvm_arch_destroy_vm(struct kvm *kvm)
7033{
27469d29
AH		 7034 if (current->mm == kvm->mm) {
7035 /*
7036 * Free memory regions allocated on behalf of userspace,
7037 * unless the the memory map has changed due to process exit
7038 * or fd copying.
7039 */
7040 struct kvm_userspace_memory_region mem;
7041 memset(&mem, 0, sizeof(mem));
7042 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7043 kvm_set_memory_region(kvm, &mem);
7044
7045 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7046 kvm_set_memory_region(kvm, &mem);
7047
7048 mem.slot = TSS_PRIVATE_MEMSLOT;
7049 kvm_set_memory_region(kvm, &mem);
7050 }
6eb55818 7051 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7052 kfree(kvm->arch.vpic);
7053 kfree(kvm->arch.vioapic);
d19a9cd2 7054 kvm_free_vcpus(kvm);
3d45830c
AK		 7055 if (kvm->arch.apic_access_page)
7056 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7057 if (kvm->arch.ept_identity_pagetable)
7058 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7059 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7060}
0de10343 7061
5587027c 7062void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7063 struct kvm_memory_slot *dont)
7064{
7065 int i;
7066
d89cc617
TY		 7067 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7068 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7069 kvm_kvfree(free->arch.rmap[i]);
7070 free->arch.rmap[i] = NULL;
77d11309 7071 }
d89cc617
TY		 7072 if (i == 0)
7073 continue;
7074
7075 if (!dont || free->arch.lpage_info[i - 1] !=
7076 dont->arch.lpage_info[i - 1]) {
7077 kvm_kvfree(free->arch.lpage_info[i - 1]);
7078 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7079 }
7080 }
7081}
7082
5587027c
AK		 7083int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7084 unsigned long npages)
db3fe4eb
TY		 7085{
7086 int i;
7087
d89cc617 7088 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7089 unsigned long ugfn;
7090 int lpages;
d89cc617 7091 int level = i + 1;
db3fe4eb
TY		 7092
7093 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7094 slot->base_gfn, level) + 1;
7095
d89cc617
TY		 7096 slot->arch.rmap[i] =
7097 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7098 if (!slot->arch.rmap[i])
77d11309 7099 goto out_free;
d89cc617
TY		 7100 if (i == 0)
7101 continue;
77d11309 7102
d89cc617
TY		 7103 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7104 sizeof(*slot->arch.lpage_info[i - 1]));
7105 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7106 goto out_free;
7107
7108 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7109 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7110 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7111 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7112 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7113 /*
7114 * If the gfn and userspace address are not aligned wrt each
7115 * other, or if explicitly asked to, disable large page
7116 * support for this slot
7117 */
7118 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7119 !kvm_largepages_enabled()) {
7120 unsigned long j;
7121
7122 for (j = 0; j < lpages; ++j)
d89cc617 7123 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7124 }
7125 }
7126
7127 return 0;
7128
7129out_free:
d89cc617
TY		 7130 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7131 kvm_kvfree(slot->arch.rmap[i]);
7132 slot->arch.rmap[i] = NULL;
7133 if (i == 0)
7134 continue;
7135
7136 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7137 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7138 }
7139 return -ENOMEM;
7140}
7141
e59dbe09
TY		 7142void kvm_arch_memslots_updated(struct kvm *kvm)
7143{
e6dff7d1
TY		 7144 /*
7145 * memslots->generation has been incremented.
7146 * mmio generation may have reached its maximum value.
7147 */
7148 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7149}
7150
f7784b8e
MT		 7151int kvm_arch_prepare_memory_region(struct kvm *kvm,
7152 struct kvm_memory_slot *memslot,
f7784b8e 7153 struct kvm_userspace_memory_region *mem,
7b6195a9 7154 enum kvm_mr_change change)
0de10343 7155{
7a905b14
TY		 7156 /*
7157 * Only private memory slots need to be mapped here since
7158 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7159 */
7b6195a9 7160 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7161 unsigned long userspace_addr;
604b38ac 7162
7a905b14
TY		 7163 /*
7164 * MAP_SHARED to prevent internal slot pages from being moved
7165 * by fork()/COW.
7166 */
7b6195a9 7167 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7168 PROT_READ | PROT_WRITE,
7169 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7170
7a905b14
TY		 7171 if (IS_ERR((void *)userspace_addr))
7172 return PTR_ERR((void *)userspace_addr);
604b38ac 7173
7a905b14 7174 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7175 }
7176
f7784b8e
MT		 7177 return 0;
7178}
7179
7180void kvm_arch_commit_memory_region(struct kvm *kvm,
7181 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7182 const struct kvm_memory_slot *old,
7183 enum kvm_mr_change change)
f7784b8e
MT		 7184{
7185
8482644a 7186 int nr_mmu_pages = 0;
f7784b8e 7187
8482644a 7188 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7189 int ret;
7190
8482644a
TY		 7191 ret = vm_munmap(old->userspace_addr,
7192 old->npages * PAGE_SIZE);
f7784b8e
MT		 7193 if (ret < 0)
7194 printk(KERN_WARNING
7195 "kvm_vm_ioctl_set_memory_region: "
7196 "failed to munmap memory\n");
7197 }
7198
48c0e4e9
XG		 7199 if (!kvm->arch.n_requested_mmu_pages)
7200 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7201
48c0e4e9 7202 if (nr_mmu_pages)
0de10343 7203 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7204 /*
7205 * Write protect all pages for dirty logging.
7206 * Existing largepage mappings are destroyed here and new ones will
7207 * not be created until the end of the logging.
7208 */
8482644a 7209 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7210 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7211}
1d737c8a 7212
2df72e9b 7213void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7214{
6ca18b69 7215 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7216}
7217
2df72e9b
MT		 7218void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7219 struct kvm_memory_slot *slot)
7220{
6ca18b69 7221 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7222}
7223
1d737c8a
ZX		 7224int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7225{
af585b92
GN		 7226 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7227 !vcpu->arch.apf.halted)
7228 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7229 || kvm_apic_has_events(vcpu)
6aef266c 7230 || vcpu->arch.pv.pv_unhalted
7460fb4a 7231 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7232 (kvm_arch_interrupt_allowed(vcpu) &&
7233 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7234}
5736199a 7235
b6d33834 7236int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7237{
b6d33834 7238 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7239}
78646121
GN		 7240
7241int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7242{
7243 return kvm_x86_ops->interrupt_allowed(vcpu);
7244}
229456fc 7245
f92653ee
JK		 7246bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7247{
7248 unsigned long current_rip = kvm_rip_read(vcpu) +
7249 get_segment_base(vcpu, VCPU_SREG_CS);
7250
7251 return current_rip == linear_rip;
7252}
7253EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7254
94fe45da
JK		 7255unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7256{
7257 unsigned long rflags;
7258
7259 rflags = kvm_x86_ops->get_rflags(vcpu);
7260 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7261 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7262 return rflags;
7263}
7264EXPORT_SYMBOL_GPL(kvm_get_rflags);
7265
7266void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7267{
7268 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7269 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7270 rflags |= X86_EFLAGS_TF;
94fe45da 7271 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7272 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7273}
7274EXPORT_SYMBOL_GPL(kvm_set_rflags);
7275
56028d08
GN		 7276void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7277{
7278 int r;
7279
fb67e14f 7280 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7281 work->wakeup_all)
56028d08
GN		 7282 return;
7283
7284 r = kvm_mmu_reload(vcpu);
7285 if (unlikely(r))
7286 return;
7287
fb67e14f
XG		 7288 if (!vcpu->arch.mmu.direct_map &&
7289 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7290 return;
7291
56028d08
GN		 7292 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7293}
7294
af585b92
GN		 7295static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7296{
7297 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7298}
7299
7300static inline u32 kvm_async_pf_next_probe(u32 key)
7301{
7302 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7303}
7304
7305static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7306{
7307 u32 key = kvm_async_pf_hash_fn(gfn);
7308
7309 while (vcpu->arch.apf.gfns[key] != ~0)
7310 key = kvm_async_pf_next_probe(key);
7311
7312 vcpu->arch.apf.gfns[key] = gfn;
7313}
7314
7315static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7316{
7317 int i;
7318 u32 key = kvm_async_pf_hash_fn(gfn);
7319
7320 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7321 (vcpu->arch.apf.gfns[key] != gfn &&
7322 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7323 key = kvm_async_pf_next_probe(key);
7324
7325 return key;
7326}
7327
7328bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7329{
7330 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7331}
7332
7333static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7334{
7335 u32 i, j, k;
7336
7337 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7338 while (true) {
7339 vcpu->arch.apf.gfns[i] = ~0;
7340 do {
7341 j = kvm_async_pf_next_probe(j);
7342 if (vcpu->arch.apf.gfns[j] == ~0)
7343 return;
7344 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7345 /*
7346 * k lies cyclically in ]i,j]
7347 * | i.k.j |
7348 * |....j i.k.| or |.k..j i...|
7349 */
7350 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7351 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7352 i = j;
7353 }
7354}
7355
7c90705b
GN		 7356static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7357{
7358
7359 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7360 sizeof(val));
7361}
7362
af585b92
GN		 7363void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7364 struct kvm_async_pf *work)
7365{
6389ee94
AK		 7366 struct x86_exception fault;
7367
7c90705b 7368 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7369 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7370
7371 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7372 (vcpu->arch.apf.send_user_only &&
7373 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7374 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7375 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7376 fault.vector = PF_VECTOR;
7377 fault.error_code_valid = true;
7378 fault.error_code = 0;
7379 fault.nested_page_fault = false;
7380 fault.address = work->arch.token;
7381 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7382 }
af585b92
GN		 7383}
7384
7385void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7386 struct kvm_async_pf *work)
7387{
6389ee94
AK		 7388 struct x86_exception fault;
7389
7c90705b 7390 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7391 if (work->wakeup_all)
7c90705b
GN		 7392 work->arch.token = ~0; /* broadcast wakeup */
7393 else
7394 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7395
7396 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7397 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7398 fault.vector = PF_VECTOR;
7399 fault.error_code_valid = true;
7400 fault.error_code = 0;
7401 fault.nested_page_fault = false;
7402 fault.address = work->arch.token;
7403 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7404 }
e6d53e3b 7405 vcpu->arch.apf.halted = false;
a4fa1635 7406 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7407}
7408
7409bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7410{
7411 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7412 return true;
7413 else
7414 return !kvm_event_needs_reinjection(vcpu) &&
7415 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7416}
7417
e0f0bbc5
AW		 7418void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7419{
7420 atomic_inc(&kvm->arch.noncoherent_dma_count);
7421}
7422EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7423
7424void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7425{
7426 atomic_dec(&kvm->arch.noncoherent_dma_count);
7427}
7428EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7429
7430bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7431{
7432 return atomic_read(&kvm->arch.noncoherent_dma_count);
7433}
7434EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7435
229456fc
MT		 7436EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7437EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7441EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7442EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux kernel - Deliverables
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