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Linux 3.19-rc3
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
92a1f12d
JR		 102bool kvm_has_tsc_control;
103EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104u32 kvm_max_guest_tsc_khz;
105EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
cc578287
ZA		 107/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108static u32 tsc_tolerance_ppm = 250;
109module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
16a96021
MT		 111static bool backwards_tsc_observed = false;
112
18863bdd
AK		 113#define KVM_NR_SHARED_MSRS 16
114
115struct kvm_shared_msrs_global {
116 int nr;
2bf78fa7 117 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120struct kvm_shared_msrs {
121 struct user_return_notifier urn;
122 bool registered;
2bf78fa7
SY		 123 struct kvm_shared_msr_values {
124 u64 host;
125 u64 curr;
126 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 127};
128
129static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 130static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 131
417bc304 132struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 133 { "pf_fixed", VCPU_STAT(pf_fixed) },
134 { "pf_guest", VCPU_STAT(pf_guest) },
135 { "tlb_flush", VCPU_STAT(tlb_flush) },
136 { "invlpg", VCPU_STAT(invlpg) },
137 { "exits", VCPU_STAT(exits) },
138 { "io_exits", VCPU_STAT(io_exits) },
139 { "mmio_exits", VCPU_STAT(mmio_exits) },
140 { "signal_exits", VCPU_STAT(signal_exits) },
141 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 142 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 143 { "halt_exits", VCPU_STAT(halt_exits) },
144 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 145 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 146 { "request_irq", VCPU_STAT(request_irq_exits) },
147 { "irq_exits", VCPU_STAT(irq_exits) },
148 { "host_state_reload", VCPU_STAT(host_state_reload) },
149 { "efer_reload", VCPU_STAT(efer_reload) },
150 { "fpu_reload", VCPU_STAT(fpu_reload) },
151 { "insn_emulation", VCPU_STAT(insn_emulation) },
152 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 153 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 154 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 155 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
156 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
157 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
158 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
159 { "mmu_flooded", VM_STAT(mmu_flooded) },
160 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 161 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 162 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 163 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 164 { "largepages", VM_STAT(lpages) },
417bc304
HB		 165 { NULL }
166};
167
2acf923e
DC		 168u64 __read_mostly host_xcr0;
169
b6785def 170static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 171
af585b92
GN		 172static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
173{
174 int i;
175 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
176 vcpu->arch.apf.gfns[i] = ~0;
177}
178
18863bdd
AK		 179static void kvm_on_user_return(struct user_return_notifier *urn)
180{
181 unsigned slot;
18863bdd
AK		 182 struct kvm_shared_msrs *locals
183 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 184 struct kvm_shared_msr_values *values;
18863bdd
AK		 185
186 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 187 values = &locals->values[slot];
188 if (values->host != values->curr) {
189 wrmsrl(shared_msrs_global.msrs[slot], values->host);
190 values->curr = values->host;
18863bdd
AK		 191 }
192 }
193 locals->registered = false;
194 user_return_notifier_unregister(urn);
195}
196
2bf78fa7 197static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 198{
18863bdd 199 u64 value;
013f6a5d
MT		 200 unsigned int cpu = smp_processor_id();
201 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 202
2bf78fa7
SY		 203 /* only read, and nobody should modify it at this time,
204 * so don't need lock */
205 if (slot >= shared_msrs_global.nr) {
206 printk(KERN_ERR "kvm: invalid MSR slot!");
207 return;
208 }
209 rdmsrl_safe(msr, &value);
210 smsr->values[slot].host = value;
211 smsr->values[slot].curr = value;
212}
213
214void kvm_define_shared_msr(unsigned slot, u32 msr)
215{
0123be42 216 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 217 if (slot >= shared_msrs_global.nr)
218 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 219 shared_msrs_global.msrs[slot] = msr;
220 /* we need ensured the shared_msr_global have been updated */
221 smp_wmb();
18863bdd
AK		 222}
223EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
224
225static void kvm_shared_msr_cpu_online(void)
226{
227 unsigned i;
18863bdd
AK		 228
229 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 230 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 231}
232
8b3c3104 233int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 234{
013f6a5d
MT		 235 unsigned int cpu = smp_processor_id();
236 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 237 int err;
18863bdd 238
2bf78fa7 239 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 240 return 0;
2bf78fa7 241 smsr->values[slot].curr = value;
8b3c3104
AH		 242 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
243 if (err)
244 return 1;
245
18863bdd
AK		 246 if (!smsr->registered) {
247 smsr->urn.on_user_return = kvm_on_user_return;
248 user_return_notifier_register(&smsr->urn);
249 smsr->registered = true;
250 }
8b3c3104 251 return 0;
18863bdd
AK		 252}
253EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
254
13a34e06 255static void drop_user_return_notifiers(void)
3548bab5 256{
013f6a5d
MT		 257 unsigned int cpu = smp_processor_id();
258 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 259
260 if (smsr->registered)
261 kvm_on_user_return(&smsr->urn);
262}
263
6866b83e
CO		 264u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
265{
8a5a87d9 266 return vcpu->arch.apic_base;
6866b83e
CO		 267}
268EXPORT_SYMBOL_GPL(kvm_get_apic_base);
269
58cb628d
JK		 270int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
271{
272 u64 old_state = vcpu->arch.apic_base &
273 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
274 u64 new_state = msr_info->data &
275 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
276 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
277 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
278
279 if (!msr_info->host_initiated &&
280 ((msr_info->data & reserved_bits) != 0 ||
281 new_state == X2APIC_ENABLE ||
282 (new_state == MSR_IA32_APICBASE_ENABLE &&
283 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
284 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
285 old_state == 0)))
286 return 1;
287
288 kvm_lapic_set_base(vcpu, msr_info->data);
289 return 0;
6866b83e
CO		 290}
291EXPORT_SYMBOL_GPL(kvm_set_apic_base);
292
2605fc21 293asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 294{
295 /* Fault while not rebooting. We want the trace. */
296 BUG();
297}
298EXPORT_SYMBOL_GPL(kvm_spurious_fault);
299
3fd28fce
ED		 300#define EXCPT_BENIGN 0
301#define EXCPT_CONTRIBUTORY 1
302#define EXCPT_PF 2
303
304static int exception_class(int vector)
305{
306 switch (vector) {
307 case PF_VECTOR:
308 return EXCPT_PF;
309 case DE_VECTOR:
310 case TS_VECTOR:
311 case NP_VECTOR:
312 case SS_VECTOR:
313 case GP_VECTOR:
314 return EXCPT_CONTRIBUTORY;
315 default:
316 break;
317 }
318 return EXCPT_BENIGN;
319}
320
d6e8c854
NA		 321#define EXCPT_FAULT 0
322#define EXCPT_TRAP 1
323#define EXCPT_ABORT 2
324#define EXCPT_INTERRUPT 3
325
326static int exception_type(int vector)
327{
328 unsigned int mask;
329
330 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
331 return EXCPT_INTERRUPT;
332
333 mask = 1 << vector;
334
335 /* #DB is trap, as instruction watchpoints are handled elsewhere */
336 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
337 return EXCPT_TRAP;
338
339 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
340 return EXCPT_ABORT;
341
342 /* Reserved exceptions will result in fault */
343 return EXCPT_FAULT;
344}
345
3fd28fce 346static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 347 unsigned nr, bool has_error, u32 error_code,
348 bool reinject)
3fd28fce
ED		 349{
350 u32 prev_nr;
351 int class1, class2;
352
3842d135
AK		 353 kvm_make_request(KVM_REQ_EVENT, vcpu);
354
3fd28fce
ED		 355 if (!vcpu->arch.exception.pending) {
356 queue:
3ffb2468
NA		 357 if (has_error && !is_protmode(vcpu))
358 has_error = false;
3fd28fce
ED		 359 vcpu->arch.exception.pending = true;
360 vcpu->arch.exception.has_error_code = has_error;
361 vcpu->arch.exception.nr = nr;
362 vcpu->arch.exception.error_code = error_code;
3f0fd292 363 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 364 return;
365 }
366
367 /* to check exception */
368 prev_nr = vcpu->arch.exception.nr;
369 if (prev_nr == DF_VECTOR) {
370 /* triple fault -> shutdown */
a8eeb04a 371 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 372 return;
373 }
374 class1 = exception_class(prev_nr);
375 class2 = exception_class(nr);
376 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
377 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
378 /* generate double fault per SDM Table 5-5 */
379 vcpu->arch.exception.pending = true;
380 vcpu->arch.exception.has_error_code = true;
381 vcpu->arch.exception.nr = DF_VECTOR;
382 vcpu->arch.exception.error_code = 0;
383 } else
384 /* replace previous exception with a new one in a hope
385 that instruction re-execution will regenerate lost
386 exception */
387 goto queue;
388}
389
298101da
AK		 390void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
391{
ce7ddec4 392 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 393}
394EXPORT_SYMBOL_GPL(kvm_queue_exception);
395
ce7ddec4
JR		 396void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
397{
398 kvm_multiple_exception(vcpu, nr, false, 0, true);
399}
400EXPORT_SYMBOL_GPL(kvm_requeue_exception);
401
db8fcefa 402void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 403{
db8fcefa
AP		 404 if (err)
405 kvm_inject_gp(vcpu, 0);
406 else
407 kvm_x86_ops->skip_emulated_instruction(vcpu);
408}
409EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 410
6389ee94 411void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 412{
413 ++vcpu->stat.pf_guest;
6389ee94
AK		 414 vcpu->arch.cr2 = fault->address;
415 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 416}
27d6c865 417EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 418
ef54bcfe 419static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 420{
6389ee94
AK		 421 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
422 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 423 else
6389ee94 424 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 425
426 return fault->nested_page_fault;
d4f8cf66
JR		 427}
428
3419ffc8
SY		 429void kvm_inject_nmi(struct kvm_vcpu *vcpu)
430{
7460fb4a
AK		 431 atomic_inc(&vcpu->arch.nmi_queued);
432 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 433}
434EXPORT_SYMBOL_GPL(kvm_inject_nmi);
435
298101da
AK		 436void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
437{
ce7ddec4 438 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 439}
440EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
441
ce7ddec4
JR		 442void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
443{
444 kvm_multiple_exception(vcpu, nr, true, error_code, true);
445}
446EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
447
0a79b009
AK		 448/*
449 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
450 * a #GP and return false.
451 */
452bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 453{
0a79b009
AK		 454 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
455 return true;
456 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
457 return false;
298101da 458}
0a79b009 459EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 460
16f8a6f9
NA		 461bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
462{
463 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
464 return true;
465
466 kvm_queue_exception(vcpu, UD_VECTOR);
467 return false;
468}
469EXPORT_SYMBOL_GPL(kvm_require_dr);
470
ec92fe44
JR		 471/*
472 * This function will be used to read from the physical memory of the currently
473 * running guest. The difference to kvm_read_guest_page is that this function
474 * can read from guest physical or from the guest's guest physical memory.
475 */
476int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
477 gfn_t ngfn, void *data, int offset, int len,
478 u32 access)
479{
54987b7a 480 struct x86_exception exception;
ec92fe44
JR		 481 gfn_t real_gfn;
482 gpa_t ngpa;
483
484 ngpa = gfn_to_gpa(ngfn);
54987b7a 485 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 486 if (real_gfn == UNMAPPED_GVA)
487 return -EFAULT;
488
489 real_gfn = gpa_to_gfn(real_gfn);
490
491 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
492}
493EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
494
3d06b8bf
JR		 495int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
496 void *data, int offset, int len, u32 access)
497{
498 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
499 data, offset, len, access);
500}
501
a03490ed
CO		 502/*
503 * Load the pae pdptrs. Return true is they are all valid.
504 */
ff03a073 505int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 506{
507 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
508 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
509 int i;
510 int ret;
ff03a073 511 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 512
ff03a073
JR		 513 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
514 offset * sizeof(u64), sizeof(pdpte),
515 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 516 if (ret < 0) {
517 ret = 0;
518 goto out;
519 }
520 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 521 if (is_present_gpte(pdpte[i]) &&
20c466b5 522 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 523 ret = 0;
524 goto out;
525 }
526 }
527 ret = 1;
528
ff03a073 529 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 530 __set_bit(VCPU_EXREG_PDPTR,
531 (unsigned long *)&vcpu->arch.regs_avail);
532 __set_bit(VCPU_EXREG_PDPTR,
533 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 534out:
a03490ed
CO		 535
536 return ret;
537}
cc4b6871 538EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 539
d835dfec
AK		 540static bool pdptrs_changed(struct kvm_vcpu *vcpu)
541{
ff03a073 542 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 543 bool changed = true;
3d06b8bf
JR		 544 int offset;
545 gfn_t gfn;
d835dfec
AK		 546 int r;
547
548 if (is_long_mode(vcpu) || !is_pae(vcpu))
549 return false;
550
6de4f3ad
AK		 551 if (!test_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_avail))
553 return true;
554
9f8fe504
AK		 555 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
556 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 557 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
558 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 559 if (r < 0)
560 goto out;
ff03a073 561 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 562out:
d835dfec
AK		 563
564 return changed;
565}
566
49a9b07e 567int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 568{
aad82703
SY		 569 unsigned long old_cr0 = kvm_read_cr0(vcpu);
570 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
571 X86_CR0_CD | X86_CR0_NW;
572
f9a48e6a
AK		 573 cr0 |= X86_CR0_ET;
574
ab344828 575#ifdef CONFIG_X86_64
0f12244f
GN		 576 if (cr0 & 0xffffffff00000000UL)
577 return 1;
ab344828
GN		 578#endif
579
580 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 581
0f12244f
GN		 582 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
583 return 1;
a03490ed 584
0f12244f
GN		 585 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
586 return 1;
a03490ed
CO		 587
588 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
589#ifdef CONFIG_X86_64
f6801dff 590 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 591 int cs_db, cs_l;
592
0f12244f
GN		 593 if (!is_pae(vcpu))
594 return 1;
a03490ed 595 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 596 if (cs_l)
597 return 1;
a03490ed
CO		 598 } else
599#endif
ff03a073 600 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 601 kvm_read_cr3(vcpu)))
0f12244f 602 return 1;
a03490ed
CO		 603 }
604
ad756a16
MJ		 605 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
606 return 1;
607
a03490ed 608 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 609
d170c419 610 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 611 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 612 kvm_async_pf_hash_reset(vcpu);
613 }
e5f3f027 614
aad82703
SY		 615 if ((cr0 ^ old_cr0) & update_bits)
616 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 617 return 0;
618}
2d3ad1f4 619EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 620
2d3ad1f4 621void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 622{
49a9b07e 623 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 626
42bdf991
MT		 627static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
628{
629 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
630 !vcpu->guest_xcr0_loaded) {
631 /* kvm_set_xcr() also depends on this */
632 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
633 vcpu->guest_xcr0_loaded = 1;
634 }
635}
636
637static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
638{
639 if (vcpu->guest_xcr0_loaded) {
640 if (vcpu->arch.xcr0 != host_xcr0)
641 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
642 vcpu->guest_xcr0_loaded = 0;
643 }
644}
645
2acf923e
DC		 646int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
647{
56c103ec
LJ		 648 u64 xcr0 = xcr;
649 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 650 u64 valid_bits;
2acf923e
DC		 651
652 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
653 if (index != XCR_XFEATURE_ENABLED_MASK)
654 return 1;
2acf923e
DC		 655 if (!(xcr0 & XSTATE_FP))
656 return 1;
657 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
658 return 1;
46c34cb0
PB		 659
660 /*
661 * Do not allow the guest to set bits that we do not support
662 * saving. However, xcr0 bit 0 is always set, even if the
663 * emulated CPU does not support XSAVE (see fx_init).
664 */
665 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
666 if (xcr0 & ~valid_bits)
2acf923e 667 return 1;
46c34cb0 668
390bd528
LJ		 669 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
670 return 1;
671
612263b3
CP		 672 if (xcr0 & XSTATE_AVX512) {
673 if (!(xcr0 & XSTATE_YMM))
674 return 1;
675 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
676 return 1;
677 }
42bdf991 678 kvm_put_guest_xcr0(vcpu);
2acf923e 679 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 680
681 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
682 kvm_update_cpuid(vcpu);
2acf923e
DC		 683 return 0;
684}
685
686int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
687{
764bcbc5
Z		 688 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
689 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 690 kvm_inject_gp(vcpu, 0);
691 return 1;
692 }
693 return 0;
694}
695EXPORT_SYMBOL_GPL(kvm_set_xcr);
696
a83b29c6 697int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 698{
fc78f519 699 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 700 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
701 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 702 if (cr4 & CR4_RESERVED_BITS)
703 return 1;
a03490ed 704
2acf923e
DC		 705 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
706 return 1;
707
c68b734f
YW		 708 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
709 return 1;
710
97ec8c06
FW		 711 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
712 return 1;
713
afcbf13f 714 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 715 return 1;
716
a03490ed 717 if (is_long_mode(vcpu)) {
0f12244f
GN		 718 if (!(cr4 & X86_CR4_PAE))
719 return 1;
a2edf57f
AK		 720 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
721 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 722 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
723 kvm_read_cr3(vcpu)))
0f12244f
GN		 724 return 1;
725
ad756a16
MJ		 726 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
727 if (!guest_cpuid_has_pcid(vcpu))
728 return 1;
729
730 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
731 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
732 return 1;
733 }
734
5e1746d6 735 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 736 return 1;
a03490ed 737
ad756a16
MJ		 738 if (((cr4 ^ old_cr4) & pdptr_bits) ||
739 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 740 kvm_mmu_reset_context(vcpu);
0f12244f 741
97ec8c06
FW		 742 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
743 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
744
2acf923e 745 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 746 kvm_update_cpuid(vcpu);
2acf923e 747
0f12244f
GN		 748 return 0;
749}
2d3ad1f4 750EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 751
2390218b 752int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 753{
ac146235 754#ifdef CONFIG_X86_64
9d88fca7 755 cr3 &= ~CR3_PCID_INVD;
ac146235 756#endif
9d88fca7 757
9f8fe504 758 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 759 kvm_mmu_sync_roots(vcpu);
77c3913b 760 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 761 return 0;
d835dfec
AK		 762 }
763
a03490ed 764 if (is_long_mode(vcpu)) {
d9f89b88
JK		 765 if (cr3 & CR3_L_MODE_RESERVED_BITS)
766 return 1;
767 } else if (is_pae(vcpu) && is_paging(vcpu) &&
768 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 769 return 1;
a03490ed 770
0f12244f 771 vcpu->arch.cr3 = cr3;
aff48baa 772 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 773 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 774 return 0;
775}
2d3ad1f4 776EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 777
eea1cff9 778int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 779{
0f12244f
GN		 780 if (cr8 & CR8_RESERVED_BITS)
781 return 1;
a03490ed
CO		 782 if (irqchip_in_kernel(vcpu->kvm))
783 kvm_lapic_set_tpr(vcpu, cr8);
784 else
ad312c7c 785 vcpu->arch.cr8 = cr8;
0f12244f
GN		 786 return 0;
787}
2d3ad1f4 788EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 789
2d3ad1f4 790unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 791{
792 if (irqchip_in_kernel(vcpu->kvm))
793 return kvm_lapic_get_cr8(vcpu);
794 else
ad312c7c 795 return vcpu->arch.cr8;
a03490ed 796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 798
73aaf249
JK		 799static void kvm_update_dr6(struct kvm_vcpu *vcpu)
800{
801 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
802 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
803}
804
c8639010
JK		 805static void kvm_update_dr7(struct kvm_vcpu *vcpu)
806{
807 unsigned long dr7;
808
809 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
810 dr7 = vcpu->arch.guest_debug_dr7;
811 else
812 dr7 = vcpu->arch.dr7;
813 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 814 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
815 if (dr7 & DR7_BP_EN_MASK)
816 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 817}
818
6f43ed01
NA		 819static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
820{
821 u64 fixed = DR6_FIXED_1;
822
823 if (!guest_cpuid_has_rtm(vcpu))
824 fixed |= DR6_RTM;
825 return fixed;
826}
827
338dbc97 828static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 829{
830 switch (dr) {
831 case 0 ... 3:
832 vcpu->arch.db[dr] = val;
833 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
834 vcpu->arch.eff_db[dr] = val;
835 break;
836 case 4:
020df079
GN		 837 /* fall through */
838 case 6:
338dbc97
GN		 839 if (val & 0xffffffff00000000ULL)
840 return -1; /* #GP */
6f43ed01 841 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 842 kvm_update_dr6(vcpu);
020df079
GN		 843 break;
844 case 5:
020df079
GN		 845 /* fall through */
846 default: /* 7 */
338dbc97
GN		 847 if (val & 0xffffffff00000000ULL)
848 return -1; /* #GP */
020df079 849 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 850 kvm_update_dr7(vcpu);
020df079
GN		 851 break;
852 }
853
854 return 0;
855}
338dbc97
GN		 856
857int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
858{
16f8a6f9 859 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 860 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 861 return 1;
862 }
863 return 0;
338dbc97 864}
020df079
GN		 865EXPORT_SYMBOL_GPL(kvm_set_dr);
866
16f8a6f9 867int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 868{
869 switch (dr) {
870 case 0 ... 3:
871 *val = vcpu->arch.db[dr];
872 break;
873 case 4:
020df079
GN		 874 /* fall through */
875 case 6:
73aaf249
JK		 876 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
877 *val = vcpu->arch.dr6;
878 else
879 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 880 break;
881 case 5:
020df079
GN		 882 /* fall through */
883 default: /* 7 */
884 *val = vcpu->arch.dr7;
885 break;
886 }
338dbc97
GN		 887 return 0;
888}
020df079
GN		 889EXPORT_SYMBOL_GPL(kvm_get_dr);
890
022cd0e8
AK		 891bool kvm_rdpmc(struct kvm_vcpu *vcpu)
892{
893 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
894 u64 data;
895 int err;
896
897 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
898 if (err)
899 return err;
900 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
901 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
902 return err;
903}
904EXPORT_SYMBOL_GPL(kvm_rdpmc);
905
043405e1
CO		 906/*
907 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
908 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
909 *
910 * This list is modified at module load time to reflect the
e3267cbb
GC		 911 * capabilities of the host cpu. This capabilities test skips MSRs that are
912 * kvm-specific. Those are put in the beginning of the list.
043405e1 913 */
e3267cbb 914
e984097b 915#define KVM_SAVE_MSRS_BEGIN 12
043405e1 916static u32 msrs_to_save[] = {
e3267cbb 917 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 918 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 919 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 920 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 921 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 922 MSR_KVM_PV_EOI_EN,
043405e1 923 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 924 MSR_STAR,
043405e1
CO		 925#ifdef CONFIG_X86_64
926 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
927#endif
b3897a49 928 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 929 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 930};
931
932static unsigned num_msrs_to_save;
933
f1d24831 934static const u32 emulated_msrs[] = {
ba904635 935 MSR_IA32_TSC_ADJUST,
a3e06bbe 936 MSR_IA32_TSCDEADLINE,
043405e1 937 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 938 MSR_IA32_MCG_STATUS,
939 MSR_IA32_MCG_CTL,
043405e1
CO		 940};
941
384bb783 942bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 943{
b69e8cae 944 if (efer & efer_reserved_bits)
384bb783 945 return false;
15c4a640 946
1b2fd70c
AG		 947 if (efer & EFER_FFXSR) {
948 struct kvm_cpuid_entry2 *feat;
949
950 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 951 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 952 return false;
1b2fd70c
AG		 953 }
954
d8017474
AG		 955 if (efer & EFER_SVME) {
956 struct kvm_cpuid_entry2 *feat;
957
958 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 959 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 960 return false;
d8017474
AG		 961 }
962
384bb783
JK		 963 return true;
964}
965EXPORT_SYMBOL_GPL(kvm_valid_efer);
966
967static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
968{
969 u64 old_efer = vcpu->arch.efer;
970
971 if (!kvm_valid_efer(vcpu, efer))
972 return 1;
973
974 if (is_paging(vcpu)
975 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
976 return 1;
977
15c4a640 978 efer &= ~EFER_LMA;
f6801dff 979 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 980
a3d204e2
SY		 981 kvm_x86_ops->set_efer(vcpu, efer);
982
aad82703
SY		 983 /* Update reserved bits */
984 if ((efer ^ old_efer) & EFER_NX)
985 kvm_mmu_reset_context(vcpu);
986
b69e8cae 987 return 0;
15c4a640
CO		 988}
989
f2b4b7dd
JR		 990void kvm_enable_efer_bits(u64 mask)
991{
992 efer_reserved_bits &= ~mask;
993}
994EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
995
15c4a640
CO		 996/*
997 * Writes msr value into into the appropriate "register".
998 * Returns 0 on success, non-0 otherwise.
999 * Assumes vcpu_load() was already called.
1000 */
8fe8ab46 1001int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1002{
854e8bb1
NA		 1003 switch (msr->index) {
1004 case MSR_FS_BASE:
1005 case MSR_GS_BASE:
1006 case MSR_KERNEL_GS_BASE:
1007 case MSR_CSTAR:
1008 case MSR_LSTAR:
1009 if (is_noncanonical_address(msr->data))
1010 return 1;
1011 break;
1012 case MSR_IA32_SYSENTER_EIP:
1013 case MSR_IA32_SYSENTER_ESP:
1014 /*
1015 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1016 * non-canonical address is written on Intel but not on
1017 * AMD (which ignores the top 32-bits, because it does
1018 * not implement 64-bit SYSENTER).
1019 *
1020 * 64-bit code should hence be able to write a non-canonical
1021 * value on AMD. Making the address canonical ensures that
1022 * vmentry does not fail on Intel after writing a non-canonical
1023 * value, and that something deterministic happens if the guest
1024 * invokes 64-bit SYSENTER.
1025 */
1026 msr->data = get_canonical(msr->data);
1027 }
8fe8ab46 1028 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1029}
854e8bb1 1030EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1031
313a3dc7
CO		 1032/*
1033 * Adapt set_msr() to msr_io()'s calling convention
1034 */
1035static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1036{
8fe8ab46
WA		 1037 struct msr_data msr;
1038
1039 msr.data = *data;
1040 msr.index = index;
1041 msr.host_initiated = true;
1042 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1043}
1044
16e8d74d
MT		 1045#ifdef CONFIG_X86_64
1046struct pvclock_gtod_data {
1047 seqcount_t seq;
1048
1049 struct { /* extract of a clocksource struct */
1050 int vclock_mode;
1051 cycle_t cycle_last;
1052 cycle_t mask;
1053 u32 mult;
1054 u32 shift;
1055 } clock;
1056
cbcf2dd3
TG		 1057 u64 boot_ns;
1058 u64 nsec_base;
16e8d74d
MT		 1059};
1060
1061static struct pvclock_gtod_data pvclock_gtod_data;
1062
1063static void update_pvclock_gtod(struct timekeeper *tk)
1064{
1065 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1066 u64 boot_ns;
1067
d28ede83 1068 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1069
1070 write_seqcount_begin(&vdata->seq);
1071
1072 /* copy pvclock gtod data */
d28ede83
TG		 1073 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1074 vdata->clock.cycle_last = tk->tkr.cycle_last;
1075 vdata->clock.mask = tk->tkr.mask;
1076 vdata->clock.mult = tk->tkr.mult;
1077 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1078
cbcf2dd3 1079 vdata->boot_ns = boot_ns;
d28ede83 1080 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1081
1082 write_seqcount_end(&vdata->seq);
1083}
1084#endif
1085
1086
18068523
GOC		 1087static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1088{
9ed3c444
AK		 1089 int version;
1090 int r;
50d0a0f9 1091 struct pvclock_wall_clock wc;
923de3cf 1092 struct timespec boot;
18068523
GOC		 1093
1094 if (!wall_clock)
1095 return;
1096
9ed3c444
AK		 1097 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1098 if (r)
1099 return;
1100
1101 if (version & 1)
1102 ++version; /* first time write, random junk */
1103
1104 ++version;
18068523 1105
18068523
GOC		 1106 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1107
50d0a0f9
GH		 1108 /*
1109 * The guest calculates current wall clock time by adding
34c238a1 1110 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1111 * wall clock specified here. guest system time equals host
1112 * system time for us, thus we must fill in host boot time here.
1113 */
923de3cf 1114 getboottime(&boot);
50d0a0f9 1115
4b648665
BR		 1116 if (kvm->arch.kvmclock_offset) {
1117 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1118 boot = timespec_sub(boot, ts);
1119 }
50d0a0f9
GH		 1120 wc.sec = boot.tv_sec;
1121 wc.nsec = boot.tv_nsec;
1122 wc.version = version;
18068523
GOC		 1123
1124 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1125
1126 version++;
1127 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1128}
1129
50d0a0f9
GH		 1130static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1131{
1132 uint32_t quotient, remainder;
1133
1134 /* Don't try to replace with do_div(), this one calculates
1135 * "(dividend << 32) / divisor" */
1136 __asm__ ( "divl %4"
1137 : "=a" (quotient), "=d" (remainder)
1138 : "0" (0), "1" (dividend), "r" (divisor) );
1139 return quotient;
1140}
1141
5f4e3f88
ZA		 1142static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1143 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1144{
5f4e3f88 1145 uint64_t scaled64;
50d0a0f9
GH		 1146 int32_t shift = 0;
1147 uint64_t tps64;
1148 uint32_t tps32;
1149
5f4e3f88
ZA		 1150 tps64 = base_khz * 1000LL;
1151 scaled64 = scaled_khz * 1000LL;
50933623 1152 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1153 tps64 >>= 1;
1154 shift--;
1155 }
1156
1157 tps32 = (uint32_t)tps64;
50933623
JK		 1158 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1159 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1160 scaled64 >>= 1;
1161 else
1162 tps32 <<= 1;
50d0a0f9
GH		 1163 shift++;
1164 }
1165
5f4e3f88
ZA		 1166 *pshift = shift;
1167 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1168
5f4e3f88
ZA		 1169 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1170 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1171}
1172
759379dd
ZA		 1173static inline u64 get_kernel_ns(void)
1174{
bb0b5812 1175 return ktime_get_boot_ns();
50d0a0f9
GH		 1176}
1177
d828199e 1178#ifdef CONFIG_X86_64
16e8d74d 1179static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1180#endif
16e8d74d 1181
c8076604 1182static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1183unsigned long max_tsc_khz;
c8076604 1184
cc578287 1185static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1186{
cc578287
ZA		 1187 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1188 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1189}
1190
cc578287 1191static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1192{
cc578287
ZA		 1193 u64 v = (u64)khz * (1000000 + ppm);
1194 do_div(v, 1000000);
1195 return v;
1e993611
JR		 1196}
1197
cc578287 1198static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1199{
cc578287
ZA		 1200 u32 thresh_lo, thresh_hi;
1201 int use_scaling = 0;
217fc9cf 1202
03ba32ca
MT		 1203 /* tsc_khz can be zero if TSC calibration fails */
1204 if (this_tsc_khz == 0)
1205 return;
1206
c285545f
ZA		 1207 /* Compute a scale to convert nanoseconds in TSC cycles */
1208 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1209 &vcpu->arch.virtual_tsc_shift,
1210 &vcpu->arch.virtual_tsc_mult);
1211 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1212
1213 /*
1214 * Compute the variation in TSC rate which is acceptable
1215 * within the range of tolerance and decide if the
1216 * rate being applied is within that bounds of the hardware
1217 * rate. If so, no scaling or compensation need be done.
1218 */
1219 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1220 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1221 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1222 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1223 use_scaling = 1;
1224 }
1225 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1226}
1227
1228static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1229{
e26101b1 1230 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1231 vcpu->arch.virtual_tsc_mult,
1232 vcpu->arch.virtual_tsc_shift);
e26101b1 1233 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1234 return tsc;
1235}
1236
b48aa97e
MT		 1237void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1238{
1239#ifdef CONFIG_X86_64
1240 bool vcpus_matched;
b48aa97e
MT		 1241 struct kvm_arch *ka = &vcpu->kvm->arch;
1242 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1243
1244 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1245 atomic_read(&vcpu->kvm->online_vcpus));
1246
7f187922
MT		 1247 /*
1248 * Once the masterclock is enabled, always perform request in
1249 * order to update it.
1250 *
1251 * In order to enable masterclock, the host clocksource must be TSC
1252 * and the vcpus need to have matched TSCs. When that happens,
1253 * perform request to enable masterclock.
1254 */
1255 if (ka->use_master_clock ||
1256 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1257 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1258
1259 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1260 atomic_read(&vcpu->kvm->online_vcpus),
1261 ka->use_master_clock, gtod->clock.vclock_mode);
1262#endif
1263}
1264
ba904635
WA		 1265static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1266{
1267 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1268 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1269}
1270
8fe8ab46 1271void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1272{
1273 struct kvm *kvm = vcpu->kvm;
f38e098f 1274 u64 offset, ns, elapsed;
99e3e30a 1275 unsigned long flags;
02626b6a 1276 s64 usdiff;
b48aa97e 1277 bool matched;
0d3da0d2 1278 bool already_matched;
8fe8ab46 1279 u64 data = msr->data;
99e3e30a 1280
038f8c11 1281 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1282 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1283 ns = get_kernel_ns();
f38e098f 1284 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1285
03ba32ca 1286 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1287 int faulted = 0;
1288
03ba32ca
MT		 1289 /* n.b - signed multiplication and division required */
1290 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1291#ifdef CONFIG_X86_64
03ba32ca 1292 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1293#else
03ba32ca 1294 /* do_div() only does unsigned */
8915aa27
MT		 1295 asm("1: idivl %[divisor]\n"
1296 "2: xor %%edx, %%edx\n"
1297 " movl $0, %[faulted]\n"
1298 "3:\n"
1299 ".section .fixup,\"ax\"\n"
1300 "4: movl $1, %[faulted]\n"
1301 " jmp 3b\n"
1302 ".previous\n"
1303
1304 _ASM_EXTABLE(1b, 4b)
1305
1306 : "=A"(usdiff), [faulted] "=r" (faulted)
1307 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1308
5d3cb0f6 1309#endif
03ba32ca
MT		 1310 do_div(elapsed, 1000);
1311 usdiff -= elapsed;
1312 if (usdiff < 0)
1313 usdiff = -usdiff;
8915aa27
MT		 1314
1315 /* idivl overflow => difference is larger than USEC_PER_SEC */
1316 if (faulted)
1317 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1318 } else
1319 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1320
1321 /*
5d3cb0f6
ZA		 1322 * Special case: TSC write with a small delta (1 second) of virtual
1323 * cycle time against real time is interpreted as an attempt to
1324 * synchronize the CPU.
1325 *
1326 * For a reliable TSC, we can match TSC offsets, and for an unstable
1327 * TSC, we add elapsed time in this computation. We could let the
1328 * compensation code attempt to catch up if we fall behind, but
1329 * it's better to try to match offsets from the beginning.
1330 */
02626b6a 1331 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1332 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1333 if (!check_tsc_unstable()) {
e26101b1 1334 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1335 pr_debug("kvm: matched tsc offset for %llu\n", data);
1336 } else {
857e4099 1337 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1338 data += delta;
1339 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1340 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1341 }
b48aa97e 1342 matched = true;
0d3da0d2 1343 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1344 } else {
1345 /*
1346 * We split periods of matched TSC writes into generations.
1347 * For each generation, we track the original measured
1348 * nanosecond time, offset, and write, so if TSCs are in
1349 * sync, we can match exact offset, and if not, we can match
4a969980 1350 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1351 *
1352 * These values are tracked in kvm->arch.cur_xxx variables.
1353 */
1354 kvm->arch.cur_tsc_generation++;
1355 kvm->arch.cur_tsc_nsec = ns;
1356 kvm->arch.cur_tsc_write = data;
1357 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1358 matched = false;
0d3da0d2 1359 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1360 kvm->arch.cur_tsc_generation, data);
f38e098f 1361 }
e26101b1
ZA		 1362
1363 /*
1364 * We also track th most recent recorded KHZ, write and time to
1365 * allow the matching interval to be extended at each write.
1366 */
f38e098f
ZA		 1367 kvm->arch.last_tsc_nsec = ns;
1368 kvm->arch.last_tsc_write = data;
5d3cb0f6 1369 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1370
b183aa58 1371 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1372
1373 /* Keep track of which generation this VCPU has synchronized to */
1374 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1375 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1376 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1377
ba904635
WA		 1378 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1379 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1380 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1381 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1382
1383 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1384 if (!matched) {
b48aa97e 1385 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1386 } else if (!already_matched) {
1387 kvm->arch.nr_vcpus_matched_tsc++;
1388 }
b48aa97e
MT		 1389
1390 kvm_track_tsc_matching(vcpu);
1391 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1392}
e26101b1 1393
99e3e30a
ZA		 1394EXPORT_SYMBOL_GPL(kvm_write_tsc);
1395
d828199e
MT		 1396#ifdef CONFIG_X86_64
1397
1398static cycle_t read_tsc(void)
1399{
1400 cycle_t ret;
1401 u64 last;
1402
1403 /*
1404 * Empirically, a fence (of type that depends on the CPU)
1405 * before rdtsc is enough to ensure that rdtsc is ordered
1406 * with respect to loads. The various CPU manuals are unclear
1407 * as to whether rdtsc can be reordered with later loads,
1408 * but no one has ever seen it happen.
1409 */
1410 rdtsc_barrier();
1411 ret = (cycle_t)vget_cycles();
1412
1413 last = pvclock_gtod_data.clock.cycle_last;
1414
1415 if (likely(ret >= last))
1416 return ret;
1417
1418 /*
1419 * GCC likes to generate cmov here, but this branch is extremely
1420 * predictable (it's just a funciton of time and the likely is
1421 * very likely) and there's a data dependence, so force GCC
1422 * to generate a branch instead. I don't barrier() because
1423 * we don't actually need a barrier, and if this function
1424 * ever gets inlined it will generate worse code.
1425 */
1426 asm volatile ("");
1427 return last;
1428}
1429
1430static inline u64 vgettsc(cycle_t *cycle_now)
1431{
1432 long v;
1433 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1434
1435 *cycle_now = read_tsc();
1436
1437 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1438 return v * gtod->clock.mult;
1439}
1440
cbcf2dd3 1441static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1442{
cbcf2dd3 1443 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1444 unsigned long seq;
d828199e 1445 int mode;
cbcf2dd3 1446 u64 ns;
d828199e 1447
d828199e
MT		 1448 do {
1449 seq = read_seqcount_begin(&gtod->seq);
1450 mode = gtod->clock.vclock_mode;
cbcf2dd3 1451 ns = gtod->nsec_base;
d828199e
MT		 1452 ns += vgettsc(cycle_now);
1453 ns >>= gtod->clock.shift;
cbcf2dd3 1454 ns += gtod->boot_ns;
d828199e 1455 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1456 *t = ns;
d828199e
MT		 1457
1458 return mode;
1459}
1460
1461/* returns true if host is using tsc clocksource */
1462static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1463{
d828199e
MT		 1464 /* checked again under seqlock below */
1465 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1466 return false;
1467
cbcf2dd3 1468 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1469}
1470#endif
1471
1472/*
1473 *
b48aa97e
MT		 1474 * Assuming a stable TSC across physical CPUS, and a stable TSC
1475 * across virtual CPUs, the following condition is possible.
1476 * Each numbered line represents an event visible to both
d828199e
MT		 1477 * CPUs at the next numbered event.
1478 *
1479 * "timespecX" represents host monotonic time. "tscX" represents
1480 * RDTSC value.
1481 *
1482 * VCPU0 on CPU0 | VCPU1 on CPU1
1483 *
1484 * 1. read timespec0,tsc0
1485 * 2. | timespec1 = timespec0 + N
1486 * | tsc1 = tsc0 + M
1487 * 3. transition to guest | transition to guest
1488 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1489 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1490 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1491 *
1492 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1493 *
1494 * - ret0 < ret1
1495 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1496 * ...
1497 * - 0 < N - M => M < N
1498 *
1499 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1500 * always the case (the difference between two distinct xtime instances
1501 * might be smaller then the difference between corresponding TSC reads,
1502 * when updating guest vcpus pvclock areas).
1503 *
1504 * To avoid that problem, do not allow visibility of distinct
1505 * system_timestamp/tsc_timestamp values simultaneously: use a master
1506 * copy of host monotonic time values. Update that master copy
1507 * in lockstep.
1508 *
b48aa97e 1509 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1510 *
1511 */
1512
1513static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1514{
1515#ifdef CONFIG_X86_64
1516 struct kvm_arch *ka = &kvm->arch;
1517 int vclock_mode;
b48aa97e
MT		 1518 bool host_tsc_clocksource, vcpus_matched;
1519
1520 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1521 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1522
1523 /*
1524 * If the host uses TSC clock, then passthrough TSC as stable
1525 * to the guest.
1526 */
b48aa97e 1527 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1528 &ka->master_kernel_ns,
1529 &ka->master_cycle_now);
1530
16a96021
MT		 1531 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1532 && !backwards_tsc_observed;
b48aa97e 1533
d828199e
MT		 1534 if (ka->use_master_clock)
1535 atomic_set(&kvm_guest_has_master_clock, 1);
1536
1537 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1538 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1539 vcpus_matched);
d828199e
MT		 1540#endif
1541}
1542
2e762ff7
MT		 1543static void kvm_gen_update_masterclock(struct kvm *kvm)
1544{
1545#ifdef CONFIG_X86_64
1546 int i;
1547 struct kvm_vcpu *vcpu;
1548 struct kvm_arch *ka = &kvm->arch;
1549
1550 spin_lock(&ka->pvclock_gtod_sync_lock);
1551 kvm_make_mclock_inprogress_request(kvm);
1552 /* no guest entries from this point */
1553 pvclock_update_vm_gtod_copy(kvm);
1554
1555 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1556 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1557
1558 /* guest entries allowed */
1559 kvm_for_each_vcpu(i, vcpu, kvm)
1560 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1561
1562 spin_unlock(&ka->pvclock_gtod_sync_lock);
1563#endif
1564}
1565
34c238a1 1566static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1567{
d828199e 1568 unsigned long flags, this_tsc_khz;
18068523 1569 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1570 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1571 s64 kernel_ns;
d828199e 1572 u64 tsc_timestamp, host_tsc;
0b79459b 1573 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1574 u8 pvclock_flags;
d828199e
MT		 1575 bool use_master_clock;
1576
1577 kernel_ns = 0;
1578 host_tsc = 0;
18068523 1579
d828199e
MT		 1580 /*
1581 * If the host uses TSC clock, then passthrough TSC as stable
1582 * to the guest.
1583 */
1584 spin_lock(&ka->pvclock_gtod_sync_lock);
1585 use_master_clock = ka->use_master_clock;
1586 if (use_master_clock) {
1587 host_tsc = ka->master_cycle_now;
1588 kernel_ns = ka->master_kernel_ns;
1589 }
1590 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1591
1592 /* Keep irq disabled to prevent changes to the clock */
1593 local_irq_save(flags);
89cbc767 1594 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1595 if (unlikely(this_tsc_khz == 0)) {
1596 local_irq_restore(flags);
1597 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1598 return 1;
1599 }
d828199e
MT		 1600 if (!use_master_clock) {
1601 host_tsc = native_read_tsc();
1602 kernel_ns = get_kernel_ns();
1603 }
1604
1605 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1606
c285545f
ZA		 1607 /*
1608 * We may have to catch up the TSC to match elapsed wall clock
1609 * time for two reasons, even if kvmclock is used.
1610 * 1) CPU could have been running below the maximum TSC rate
1611 * 2) Broken TSC compensation resets the base at each VCPU
1612 * entry to avoid unknown leaps of TSC even when running
1613 * again on the same CPU. This may cause apparent elapsed
1614 * time to disappear, and the guest to stand still or run
1615 * very slowly.
1616 */
1617 if (vcpu->tsc_catchup) {
1618 u64 tsc = compute_guest_tsc(v, kernel_ns);
1619 if (tsc > tsc_timestamp) {
f1e2b260 1620 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1621 tsc_timestamp = tsc;
1622 }
50d0a0f9
GH		 1623 }
1624
18068523
GOC		 1625 local_irq_restore(flags);
1626
0b79459b 1627 if (!vcpu->pv_time_enabled)
c285545f 1628 return 0;
18068523 1629
e48672fa 1630 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1631 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1632 &vcpu->hv_clock.tsc_shift,
1633 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1634 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1635 }
1636
1637 /* With all the info we got, fill in the values */
1d5f066e 1638 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1639 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1640 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1641
09a0c3f1
OH		 1642 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1643 &guest_hv_clock, sizeof(guest_hv_clock))))
1644 return 0;
1645
18068523
GOC		 1646 /*
1647 * The interface expects us to write an even number signaling that the
1648 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1649 * state, we just increase by 2 at the end.
18068523 1650 */
09a0c3f1 1651 vcpu->hv_clock.version = guest_hv_clock.version + 2;
78c0337a
MT		 1652
1653 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1654 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1655
1656 if (vcpu->pvclock_set_guest_stopped_request) {
1657 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1658 vcpu->pvclock_set_guest_stopped_request = false;
1659 }
1660
d828199e
MT		 1661 /* If the host uses TSC clocksource, then it is stable */
1662 if (use_master_clock)
1663 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1664
78c0337a
MT		 1665 vcpu->hv_clock.flags = pvclock_flags;
1666
ce1a5e60
DM		 1667 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1668
0b79459b
AH		 1669 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1670 &vcpu->hv_clock,
1671 sizeof(vcpu->hv_clock));
8cfdc000 1672 return 0;
c8076604
GH		 1673}
1674
0061d53d
MT		 1675/*
1676 * kvmclock updates which are isolated to a given vcpu, such as
1677 * vcpu->cpu migration, should not allow system_timestamp from
1678 * the rest of the vcpus to remain static. Otherwise ntp frequency
1679 * correction applies to one vcpu's system_timestamp but not
1680 * the others.
1681 *
1682 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1683 * We need to rate-limit these requests though, as they can
1684 * considerably slow guests that have a large number of vcpus.
1685 * The time for a remote vcpu to update its kvmclock is bound
1686 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1687 */
1688
7e44e449
AJ		 1689#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1690
1691static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1692{
1693 int i;
7e44e449
AJ		 1694 struct delayed_work *dwork = to_delayed_work(work);
1695 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1696 kvmclock_update_work);
1697 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1698 struct kvm_vcpu *vcpu;
1699
1700 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1701 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1702 kvm_vcpu_kick(vcpu);
1703 }
1704}
1705
7e44e449
AJ		 1706static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1707{
1708 struct kvm *kvm = v->kvm;
1709
105b21bb 1710 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1711 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1712 KVMCLOCK_UPDATE_DELAY);
1713}
1714
332967a3
AJ		 1715#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1716
1717static void kvmclock_sync_fn(struct work_struct *work)
1718{
1719 struct delayed_work *dwork = to_delayed_work(work);
1720 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1721 kvmclock_sync_work);
1722 struct kvm *kvm = container_of(ka, struct kvm, arch);
1723
1724 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1725 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1726 KVMCLOCK_SYNC_PERIOD);
1727}
1728
9ba075a6
AK		 1729static bool msr_mtrr_valid(unsigned msr)
1730{
1731 switch (msr) {
1732 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1733 case MSR_MTRRfix64K_00000:
1734 case MSR_MTRRfix16K_80000:
1735 case MSR_MTRRfix16K_A0000:
1736 case MSR_MTRRfix4K_C0000:
1737 case MSR_MTRRfix4K_C8000:
1738 case MSR_MTRRfix4K_D0000:
1739 case MSR_MTRRfix4K_D8000:
1740 case MSR_MTRRfix4K_E0000:
1741 case MSR_MTRRfix4K_E8000:
1742 case MSR_MTRRfix4K_F0000:
1743 case MSR_MTRRfix4K_F8000:
1744 case MSR_MTRRdefType:
1745 case MSR_IA32_CR_PAT:
1746 return true;
1747 case 0x2f8:
1748 return true;
1749 }
1750 return false;
1751}
1752
d6289b93
MT		 1753static bool valid_pat_type(unsigned t)
1754{
1755 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1756}
1757
1758static bool valid_mtrr_type(unsigned t)
1759{
1760 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1761}
1762
4566654b 1763bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1764{
1765 int i;
fd275235 1766 u64 mask;
d6289b93
MT		 1767
1768 if (!msr_mtrr_valid(msr))
1769 return false;
1770
1771 if (msr == MSR_IA32_CR_PAT) {
1772 for (i = 0; i < 8; i++)
1773 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1774 return false;
1775 return true;
1776 } else if (msr == MSR_MTRRdefType) {
1777 if (data & ~0xcff)
1778 return false;
1779 return valid_mtrr_type(data & 0xff);
1780 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1781 for (i = 0; i < 8 ; i++)
1782 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1783 return false;
1784 return true;
1785 }
1786
1787 /* variable MTRRs */
adfb5d27
WL		 1788 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1789
fd275235 1790 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1791 if ((msr & 1) == 0) {
adfb5d27 1792 /* MTRR base */
d7a2a246
WL		 1793 if (!valid_mtrr_type(data & 0xff))
1794 return false;
1795 mask |= 0xf00;
1796 } else
1797 /* MTRR mask */
1798 mask |= 0x7ff;
1799 if (data & mask) {
1800 kvm_inject_gp(vcpu, 0);
1801 return false;
1802 }
1803
adfb5d27 1804 return true;
d6289b93 1805}
4566654b 1806EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1807
9ba075a6
AK		 1808static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1809{
0bed3b56
SY		 1810 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1811
4566654b 1812 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1813 return 1;
1814
0bed3b56
SY		 1815 if (msr == MSR_MTRRdefType) {
1816 vcpu->arch.mtrr_state.def_type = data;
1817 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1818 } else if (msr == MSR_MTRRfix64K_00000)
1819 p[0] = data;
1820 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1821 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1822 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1823 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1824 else if (msr == MSR_IA32_CR_PAT)
1825 vcpu->arch.pat = data;
1826 else { /* Variable MTRRs */
1827 int idx, is_mtrr_mask;
1828 u64 *pt;
1829
1830 idx = (msr - 0x200) / 2;
1831 is_mtrr_mask = msr - 0x200 - 2 * idx;
1832 if (!is_mtrr_mask)
1833 pt =
1834 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1835 else
1836 pt =
1837 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1838 *pt = data;
1839 }
1840
1841 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1842 return 0;
1843}
15c4a640 1844
890ca9ae 1845static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1846{
890ca9ae
HY		 1847 u64 mcg_cap = vcpu->arch.mcg_cap;
1848 unsigned bank_num = mcg_cap & 0xff;
1849
15c4a640 1850 switch (msr) {
15c4a640 1851 case MSR_IA32_MCG_STATUS:
890ca9ae 1852 vcpu->arch.mcg_status = data;
15c4a640 1853 break;
c7ac679c 1854 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1855 if (!(mcg_cap & MCG_CTL_P))
1856 return 1;
1857 if (data != 0 && data != ~(u64)0)
1858 return -1;
1859 vcpu->arch.mcg_ctl = data;
1860 break;
1861 default:
1862 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1863 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1864 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1865 /* only 0 or all 1s can be written to IA32_MCi_CTL
1866 * some Linux kernels though clear bit 10 in bank 4 to
1867 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1868 * this to avoid an uncatched #GP in the guest
1869 */
890ca9ae 1870 if ((offset & 0x3) == 0 &&
114be429 1871 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1872 return -1;
1873 vcpu->arch.mce_banks[offset] = data;
1874 break;
1875 }
1876 return 1;
1877 }
1878 return 0;
1879}
1880
ffde22ac
ES		 1881static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1882{
1883 struct kvm *kvm = vcpu->kvm;
1884 int lm = is_long_mode(vcpu);
1885 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1886 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1887 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1888 : kvm->arch.xen_hvm_config.blob_size_32;
1889 u32 page_num = data & ~PAGE_MASK;
1890 u64 page_addr = data & PAGE_MASK;
1891 u8 *page;
1892 int r;
1893
1894 r = -E2BIG;
1895 if (page_num >= blob_size)
1896 goto out;
1897 r = -ENOMEM;
ff5c2c03
SL		 1898 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1899 if (IS_ERR(page)) {
1900 r = PTR_ERR(page);
ffde22ac 1901 goto out;
ff5c2c03 1902 }
ffde22ac
ES		 1903 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1904 goto out_free;
1905 r = 0;
1906out_free:
1907 kfree(page);
1908out:
1909 return r;
1910}
1911
55cd8e5a
GN		 1912static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1913{
1914 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1915}
1916
1917static bool kvm_hv_msr_partition_wide(u32 msr)
1918{
1919 bool r = false;
1920 switch (msr) {
1921 case HV_X64_MSR_GUEST_OS_ID:
1922 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1923 case HV_X64_MSR_REFERENCE_TSC:
1924 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1925 r = true;
1926 break;
1927 }
1928
1929 return r;
1930}
1931
1932static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1933{
1934 struct kvm *kvm = vcpu->kvm;
1935
1936 switch (msr) {
1937 case HV_X64_MSR_GUEST_OS_ID:
1938 kvm->arch.hv_guest_os_id = data;
1939 /* setting guest os id to zero disables hypercall page */
1940 if (!kvm->arch.hv_guest_os_id)
1941 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1942 break;
1943 case HV_X64_MSR_HYPERCALL: {
1944 u64 gfn;
1945 unsigned long addr;
1946 u8 instructions[4];
1947
1948 /* if guest os id is not set hypercall should remain disabled */
1949 if (!kvm->arch.hv_guest_os_id)
1950 break;
1951 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1952 kvm->arch.hv_hypercall = data;
1953 break;
1954 }
1955 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1956 addr = gfn_to_hva(kvm, gfn);
1957 if (kvm_is_error_hva(addr))
1958 return 1;
1959 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1960 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1961 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1962 return 1;
1963 kvm->arch.hv_hypercall = data;
b94b64c9 1964 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1965 break;
1966 }
e984097b
VR		 1967 case HV_X64_MSR_REFERENCE_TSC: {
1968 u64 gfn;
1969 HV_REFERENCE_TSC_PAGE tsc_ref;
1970 memset(&tsc_ref, 0, sizeof(tsc_ref));
1971 kvm->arch.hv_tsc_page = data;
1972 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1973 break;
1974 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1975 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1976 &tsc_ref, sizeof(tsc_ref)))
1977 return 1;
1978 mark_page_dirty(kvm, gfn);
1979 break;
1980 }
55cd8e5a 1981 default:
a737f256
CD		 1982 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1983 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1984 return 1;
1985 }
1986 return 0;
1987}
1988
1989static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1990{
10388a07
GN		 1991 switch (msr) {
1992 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1993 u64 gfn;
10388a07 1994 unsigned long addr;
55cd8e5a 1995
10388a07
GN		 1996 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1997 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1998 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1999 return 1;
10388a07
GN		 2000 break;
2001 }
b3af1e88
VR		 2002 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2003 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2004 if (kvm_is_error_hva(addr))
2005 return 1;
8b0cedff 2006 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2007 return 1;
2008 vcpu->arch.hv_vapic = data;
b3af1e88 2009 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2010 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2011 return 1;
10388a07
GN		 2012 break;
2013 }
2014 case HV_X64_MSR_EOI:
2015 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2016 case HV_X64_MSR_ICR:
2017 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2018 case HV_X64_MSR_TPR:
2019 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2020 default:
a737f256
CD		 2021 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2022 "data 0x%llx\n", msr, data);
10388a07
GN		 2023 return 1;
2024 }
2025
2026 return 0;
55cd8e5a
GN		 2027}
2028
344d9588
GN		 2029static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2030{
2031 gpa_t gpa = data & ~0x3f;
2032
4a969980 2033 /* Bits 2:5 are reserved, Should be zero */
6adba527 2034 if (data & 0x3c)
344d9588
GN		 2035 return 1;
2036
2037 vcpu->arch.apf.msr_val = data;
2038
2039 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2040 kvm_clear_async_pf_completion_queue(vcpu);
2041 kvm_async_pf_hash_reset(vcpu);
2042 return 0;
2043 }
2044
8f964525
AH		 2045 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2046 sizeof(u32)))
344d9588
GN		 2047 return 1;
2048
6adba527 2049 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2050 kvm_async_pf_wakeup_all(vcpu);
2051 return 0;
2052}
2053
12f9a48f
GC		 2054static void kvmclock_reset(struct kvm_vcpu *vcpu)
2055{
0b79459b 2056 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2057}
2058
c9aaa895
GC		 2059static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2060{
2061 u64 delta;
2062
2063 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2064 return;
2065
2066 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2067 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2068 vcpu->arch.st.accum_steal = delta;
2069}
2070
2071static void record_steal_time(struct kvm_vcpu *vcpu)
2072{
2073 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2074 return;
2075
2076 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2077 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2078 return;
2079
2080 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2081 vcpu->arch.st.steal.version += 2;
2082 vcpu->arch.st.accum_steal = 0;
2083
2084 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2085 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2086}
2087
8fe8ab46 2088int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2089{
5753785f 2090 bool pr = false;
8fe8ab46
WA		 2091 u32 msr = msr_info->index;
2092 u64 data = msr_info->data;
5753785f 2093
15c4a640 2094 switch (msr) {
2e32b719
BP		 2095 case MSR_AMD64_NB_CFG:
2096 case MSR_IA32_UCODE_REV:
2097 case MSR_IA32_UCODE_WRITE:
2098 case MSR_VM_HSAVE_PA:
2099 case MSR_AMD64_PATCH_LOADER:
2100 case MSR_AMD64_BU_CFG2:
2101 break;
2102
15c4a640 2103 case MSR_EFER:
b69e8cae 2104 return set_efer(vcpu, data);
8f1589d9
AP		 2105 case MSR_K7_HWCR:
2106 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2107 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2108 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2109 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2110 if (data != 0) {
a737f256
CD		 2111 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2112 data);
8f1589d9
AP		 2113 return 1;
2114 }
15c4a640 2115 break;
f7c6d140
AP		 2116 case MSR_FAM10H_MMIO_CONF_BASE:
2117 if (data != 0) {
a737f256
CD		 2118 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2119 "0x%llx\n", data);
f7c6d140
AP		 2120 return 1;
2121 }
15c4a640 2122 break;
b5e2fec0
AG		 2123 case MSR_IA32_DEBUGCTLMSR:
2124 if (!data) {
2125 /* We support the non-activated case already */
2126 break;
2127 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2128 /* Values other than LBR and BTF are vendor-specific,
2129 thus reserved and should throw a #GP */
2130 return 1;
2131 }
a737f256
CD		 2132 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2133 __func__, data);
b5e2fec0 2134 break;
9ba075a6
AK		 2135 case 0x200 ... 0x2ff:
2136 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2137 case MSR_IA32_APICBASE:
58cb628d 2138 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2139 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2140 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2141 case MSR_IA32_TSCDEADLINE:
2142 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2143 break;
ba904635
WA		 2144 case MSR_IA32_TSC_ADJUST:
2145 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2146 if (!msr_info->host_initiated) {
d913b904 2147 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2148 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2149 }
2150 vcpu->arch.ia32_tsc_adjust_msr = data;
2151 }
2152 break;
15c4a640 2153 case MSR_IA32_MISC_ENABLE:
ad312c7c 2154 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2155 break;
11c6bffa 2156 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2157 case MSR_KVM_WALL_CLOCK:
2158 vcpu->kvm->arch.wall_clock = data;
2159 kvm_write_wall_clock(vcpu->kvm, data);
2160 break;
11c6bffa 2161 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2162 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2163 u64 gpa_offset;
12f9a48f 2164 kvmclock_reset(vcpu);
18068523
GOC		 2165
2166 vcpu->arch.time = data;
0061d53d 2167 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2168
2169 /* we verify if the enable bit is set... */
2170 if (!(data & 1))
2171 break;
2172
0b79459b 2173 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2174
0b79459b 2175 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2176 &vcpu->arch.pv_time, data & ~1ULL,
2177 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2178 vcpu->arch.pv_time_enabled = false;
2179 else
2180 vcpu->arch.pv_time_enabled = true;
32cad84f 2181
18068523
GOC		 2182 break;
2183 }
344d9588
GN		 2184 case MSR_KVM_ASYNC_PF_EN:
2185 if (kvm_pv_enable_async_pf(vcpu, data))
2186 return 1;
2187 break;
c9aaa895
GC		 2188 case MSR_KVM_STEAL_TIME:
2189
2190 if (unlikely(!sched_info_on()))
2191 return 1;
2192
2193 if (data & KVM_STEAL_RESERVED_MASK)
2194 return 1;
2195
2196 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2197 data & KVM_STEAL_VALID_BITS,
2198 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2199 return 1;
2200
2201 vcpu->arch.st.msr_val = data;
2202
2203 if (!(data & KVM_MSR_ENABLED))
2204 break;
2205
2206 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2207
2208 preempt_disable();
2209 accumulate_steal_time(vcpu);
2210 preempt_enable();
2211
2212 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2213
2214 break;
ae7a2a3f
MT		 2215 case MSR_KVM_PV_EOI_EN:
2216 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2217 return 1;
2218 break;
c9aaa895 2219
890ca9ae
HY		 2220 case MSR_IA32_MCG_CTL:
2221 case MSR_IA32_MCG_STATUS:
81760dcc 2222 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2223 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2224
2225 /* Performance counters are not protected by a CPUID bit,
2226 * so we should check all of them in the generic path for the sake of
2227 * cross vendor migration.
2228 * Writing a zero into the event select MSRs disables them,
2229 * which we perfectly emulate ;-). Any other value should be at least
2230 * reported, some guests depend on them.
2231 */
71db6023
AP		 2232 case MSR_K7_EVNTSEL0:
2233 case MSR_K7_EVNTSEL1:
2234 case MSR_K7_EVNTSEL2:
2235 case MSR_K7_EVNTSEL3:
2236 if (data != 0)
a737f256
CD		 2237 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2238 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2239 break;
2240 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2241 * so we ignore writes to make it happy.
2242 */
71db6023
AP		 2243 case MSR_K7_PERFCTR0:
2244 case MSR_K7_PERFCTR1:
2245 case MSR_K7_PERFCTR2:
2246 case MSR_K7_PERFCTR3:
a737f256
CD		 2247 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2248 "0x%x data 0x%llx\n", msr, data);
71db6023 2249 break;
5753785f
GN		 2250 case MSR_P6_PERFCTR0:
2251 case MSR_P6_PERFCTR1:
2252 pr = true;
2253 case MSR_P6_EVNTSEL0:
2254 case MSR_P6_EVNTSEL1:
2255 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2256 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2257
2258 if (pr || data != 0)
a737f256
CD		 2259 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2260 "0x%x data 0x%llx\n", msr, data);
5753785f 2261 break;
84e0cefa
JS		 2262 case MSR_K7_CLK_CTL:
2263 /*
2264 * Ignore all writes to this no longer documented MSR.
2265 * Writes are only relevant for old K7 processors,
2266 * all pre-dating SVM, but a recommended workaround from
4a969980 2267 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2268 * affected processor models on the command line, hence
2269 * the need to ignore the workaround.
2270 */
2271 break;
55cd8e5a
GN		 2272 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2273 if (kvm_hv_msr_partition_wide(msr)) {
2274 int r;
2275 mutex_lock(&vcpu->kvm->lock);
2276 r = set_msr_hyperv_pw(vcpu, msr, data);
2277 mutex_unlock(&vcpu->kvm->lock);
2278 return r;
2279 } else
2280 return set_msr_hyperv(vcpu, msr, data);
2281 break;
91c9c3ed 2282 case MSR_IA32_BBL_CR_CTL3:
2283 /* Drop writes to this legacy MSR -- see rdmsr
2284 * counterpart for further detail.
2285 */
a737f256 2286 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2287 break;
2b036c6b
BO		 2288 case MSR_AMD64_OSVW_ID_LENGTH:
2289 if (!guest_cpuid_has_osvw(vcpu))
2290 return 1;
2291 vcpu->arch.osvw.length = data;
2292 break;
2293 case MSR_AMD64_OSVW_STATUS:
2294 if (!guest_cpuid_has_osvw(vcpu))
2295 return 1;
2296 vcpu->arch.osvw.status = data;
2297 break;
15c4a640 2298 default:
ffde22ac
ES		 2299 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2300 return xen_hvm_config(vcpu, data);
f5132b01 2301 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2302 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2303 if (!ignore_msrs) {
a737f256
CD		 2304 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2305 msr, data);
ed85c068
AP		 2306 return 1;
2307 } else {
a737f256
CD		 2308 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2309 msr, data);
ed85c068
AP		 2310 break;
2311 }
15c4a640
CO		 2312 }
2313 return 0;
2314}
2315EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2316
2317
2318/*
2319 * Reads an msr value (of 'msr_index') into 'pdata'.
2320 * Returns 0 on success, non-0 otherwise.
2321 * Assumes vcpu_load() was already called.
2322 */
2323int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2324{
2325 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2326}
2327
9ba075a6
AK		 2328static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2329{
0bed3b56
SY		 2330 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2331
9ba075a6
AK		 2332 if (!msr_mtrr_valid(msr))
2333 return 1;
2334
0bed3b56
SY		 2335 if (msr == MSR_MTRRdefType)
2336 *pdata = vcpu->arch.mtrr_state.def_type +
2337 (vcpu->arch.mtrr_state.enabled << 10);
2338 else if (msr == MSR_MTRRfix64K_00000)
2339 *pdata = p[0];
2340 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2341 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2342 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2343 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2344 else if (msr == MSR_IA32_CR_PAT)
2345 *pdata = vcpu->arch.pat;
2346 else { /* Variable MTRRs */
2347 int idx, is_mtrr_mask;
2348 u64 *pt;
2349
2350 idx = (msr - 0x200) / 2;
2351 is_mtrr_mask = msr - 0x200 - 2 * idx;
2352 if (!is_mtrr_mask)
2353 pt =
2354 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2355 else
2356 pt =
2357 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2358 *pdata = *pt;
2359 }
2360
9ba075a6
AK		 2361 return 0;
2362}
2363
890ca9ae 2364static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2365{
2366 u64 data;
890ca9ae
HY		 2367 u64 mcg_cap = vcpu->arch.mcg_cap;
2368 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2369
2370 switch (msr) {
15c4a640
CO		 2371 case MSR_IA32_P5_MC_ADDR:
2372 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2373 data = 0;
2374 break;
15c4a640 2375 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2376 data = vcpu->arch.mcg_cap;
2377 break;
c7ac679c 2378 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2379 if (!(mcg_cap & MCG_CTL_P))
2380 return 1;
2381 data = vcpu->arch.mcg_ctl;
2382 break;
2383 case MSR_IA32_MCG_STATUS:
2384 data = vcpu->arch.mcg_status;
2385 break;
2386 default:
2387 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2388 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2389 u32 offset = msr - MSR_IA32_MC0_CTL;
2390 data = vcpu->arch.mce_banks[offset];
2391 break;
2392 }
2393 return 1;
2394 }
2395 *pdata = data;
2396 return 0;
2397}
2398
55cd8e5a
GN		 2399static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2400{
2401 u64 data = 0;
2402 struct kvm *kvm = vcpu->kvm;
2403
2404 switch (msr) {
2405 case HV_X64_MSR_GUEST_OS_ID:
2406 data = kvm->arch.hv_guest_os_id;
2407 break;
2408 case HV_X64_MSR_HYPERCALL:
2409 data = kvm->arch.hv_hypercall;
2410 break;
e984097b
VR		 2411 case HV_X64_MSR_TIME_REF_COUNT: {
2412 data =
2413 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2414 break;
2415 }
2416 case HV_X64_MSR_REFERENCE_TSC:
2417 data = kvm->arch.hv_tsc_page;
2418 break;
55cd8e5a 2419 default:
a737f256 2420 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2421 return 1;
2422 }
2423
2424 *pdata = data;
2425 return 0;
2426}
2427
2428static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2429{
2430 u64 data = 0;
2431
2432 switch (msr) {
2433 case HV_X64_MSR_VP_INDEX: {
2434 int r;
2435 struct kvm_vcpu *v;
684851a1
TY		 2436 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2437 if (v == vcpu) {
55cd8e5a 2438 data = r;
684851a1
TY		 2439 break;
2440 }
2441 }
55cd8e5a
GN		 2442 break;
2443 }
10388a07
GN		 2444 case HV_X64_MSR_EOI:
2445 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2446 case HV_X64_MSR_ICR:
2447 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2448 case HV_X64_MSR_TPR:
2449 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2450 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2451 data = vcpu->arch.hv_vapic;
2452 break;
55cd8e5a 2453 default:
a737f256 2454 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2455 return 1;
2456 }
2457 *pdata = data;
2458 return 0;
2459}
2460
890ca9ae
HY		 2461int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2462{
2463 u64 data;
2464
2465 switch (msr) {
890ca9ae 2466 case MSR_IA32_PLATFORM_ID:
15c4a640 2467 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2468 case MSR_IA32_DEBUGCTLMSR:
2469 case MSR_IA32_LASTBRANCHFROMIP:
2470 case MSR_IA32_LASTBRANCHTOIP:
2471 case MSR_IA32_LASTINTFROMIP:
2472 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2473 case MSR_K8_SYSCFG:
2474 case MSR_K7_HWCR:
61a6bd67 2475 case MSR_VM_HSAVE_PA:
9e699624 2476 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2477 case MSR_K7_EVNTSEL1:
2478 case MSR_K7_EVNTSEL2:
2479 case MSR_K7_EVNTSEL3:
1f3ee616 2480 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2481 case MSR_K7_PERFCTR1:
2482 case MSR_K7_PERFCTR2:
2483 case MSR_K7_PERFCTR3:
1fdbd48c 2484 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2485 case MSR_AMD64_NB_CFG:
f7c6d140 2486 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2487 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2488 data = 0;
2489 break;
5753785f
GN		 2490 case MSR_P6_PERFCTR0:
2491 case MSR_P6_PERFCTR1:
2492 case MSR_P6_EVNTSEL0:
2493 case MSR_P6_EVNTSEL1:
2494 if (kvm_pmu_msr(vcpu, msr))
2495 return kvm_pmu_get_msr(vcpu, msr, pdata);
2496 data = 0;
2497 break;
742bc670
MT		 2498 case MSR_IA32_UCODE_REV:
2499 data = 0x100000000ULL;
2500 break;
9ba075a6
AK		 2501 case MSR_MTRRcap:
2502 data = 0x500 | KVM_NR_VAR_MTRR;
2503 break;
2504 case 0x200 ... 0x2ff:
2505 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2506 case 0xcd: /* fsb frequency */
2507 data = 3;
2508 break;
7b914098
JS		 2509 /*
2510 * MSR_EBC_FREQUENCY_ID
2511 * Conservative value valid for even the basic CPU models.
2512 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2513 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2514 * and 266MHz for model 3, or 4. Set Core Clock
2515 * Frequency to System Bus Frequency Ratio to 1 (bits
2516 * 31:24) even though these are only valid for CPU
2517 * models > 2, however guests may end up dividing or
2518 * multiplying by zero otherwise.
2519 */
2520 case MSR_EBC_FREQUENCY_ID:
2521 data = 1 << 24;
2522 break;
15c4a640
CO		 2523 case MSR_IA32_APICBASE:
2524 data = kvm_get_apic_base(vcpu);
2525 break;
0105d1a5
GN		 2526 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2527 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2528 break;
a3e06bbe
LJ		 2529 case MSR_IA32_TSCDEADLINE:
2530 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2531 break;
ba904635
WA		 2532 case MSR_IA32_TSC_ADJUST:
2533 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2534 break;
15c4a640 2535 case MSR_IA32_MISC_ENABLE:
ad312c7c 2536 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2537 break;
847f0ad8
AG		 2538 case MSR_IA32_PERF_STATUS:
2539 /* TSC increment by tick */
2540 data = 1000ULL;
2541 /* CPU multiplier */
2542 data |= (((uint64_t)4ULL) << 40);
2543 break;
15c4a640 2544 case MSR_EFER:
f6801dff 2545 data = vcpu->arch.efer;
15c4a640 2546 break;
18068523 2547 case MSR_KVM_WALL_CLOCK:
11c6bffa 2548 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2549 data = vcpu->kvm->arch.wall_clock;
2550 break;
2551 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2552 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2553 data = vcpu->arch.time;
2554 break;
344d9588
GN		 2555 case MSR_KVM_ASYNC_PF_EN:
2556 data = vcpu->arch.apf.msr_val;
2557 break;
c9aaa895
GC		 2558 case MSR_KVM_STEAL_TIME:
2559 data = vcpu->arch.st.msr_val;
2560 break;
1d92128f
MT		 2561 case MSR_KVM_PV_EOI_EN:
2562 data = vcpu->arch.pv_eoi.msr_val;
2563 break;
890ca9ae
HY		 2564 case MSR_IA32_P5_MC_ADDR:
2565 case MSR_IA32_P5_MC_TYPE:
2566 case MSR_IA32_MCG_CAP:
2567 case MSR_IA32_MCG_CTL:
2568 case MSR_IA32_MCG_STATUS:
81760dcc 2569 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2570 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2571 case MSR_K7_CLK_CTL:
2572 /*
2573 * Provide expected ramp-up count for K7. All other
2574 * are set to zero, indicating minimum divisors for
2575 * every field.
2576 *
2577 * This prevents guest kernels on AMD host with CPU
2578 * type 6, model 8 and higher from exploding due to
2579 * the rdmsr failing.
2580 */
2581 data = 0x20000000;
2582 break;
55cd8e5a
GN		 2583 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2584 if (kvm_hv_msr_partition_wide(msr)) {
2585 int r;
2586 mutex_lock(&vcpu->kvm->lock);
2587 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2588 mutex_unlock(&vcpu->kvm->lock);
2589 return r;
2590 } else
2591 return get_msr_hyperv(vcpu, msr, pdata);
2592 break;
91c9c3ed 2593 case MSR_IA32_BBL_CR_CTL3:
2594 /* This legacy MSR exists but isn't fully documented in current
2595 * silicon. It is however accessed by winxp in very narrow
2596 * scenarios where it sets bit #19, itself documented as
2597 * a "reserved" bit. Best effort attempt to source coherent
2598 * read data here should the balance of the register be
2599 * interpreted by the guest:
2600 *
2601 * L2 cache control register 3: 64GB range, 256KB size,
2602 * enabled, latency 0x1, configured
2603 */
2604 data = 0xbe702111;
2605 break;
2b036c6b
BO		 2606 case MSR_AMD64_OSVW_ID_LENGTH:
2607 if (!guest_cpuid_has_osvw(vcpu))
2608 return 1;
2609 data = vcpu->arch.osvw.length;
2610 break;
2611 case MSR_AMD64_OSVW_STATUS:
2612 if (!guest_cpuid_has_osvw(vcpu))
2613 return 1;
2614 data = vcpu->arch.osvw.status;
2615 break;
15c4a640 2616 default:
f5132b01
GN		 2617 if (kvm_pmu_msr(vcpu, msr))
2618 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2619 if (!ignore_msrs) {
a737f256 2620 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2621 return 1;
2622 } else {
a737f256 2623 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2624 data = 0;
2625 }
2626 break;
15c4a640
CO		 2627 }
2628 *pdata = data;
2629 return 0;
2630}
2631EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2632
313a3dc7
CO		 2633/*
2634 * Read or write a bunch of msrs. All parameters are kernel addresses.
2635 *
2636 * @return number of msrs set successfully.
2637 */
2638static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2639 struct kvm_msr_entry *entries,
2640 int (*do_msr)(struct kvm_vcpu *vcpu,
2641 unsigned index, u64 *data))
2642{
f656ce01 2643 int i, idx;
313a3dc7 2644
f656ce01 2645 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2646 for (i = 0; i < msrs->nmsrs; ++i)
2647 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2648 break;
f656ce01 2649 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2650
313a3dc7
CO		 2651 return i;
2652}
2653
2654/*
2655 * Read or write a bunch of msrs. Parameters are user addresses.
2656 *
2657 * @return number of msrs set successfully.
2658 */
2659static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2660 int (*do_msr)(struct kvm_vcpu *vcpu,
2661 unsigned index, u64 *data),
2662 int writeback)
2663{
2664 struct kvm_msrs msrs;
2665 struct kvm_msr_entry *entries;
2666 int r, n;
2667 unsigned size;
2668
2669 r = -EFAULT;
2670 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2671 goto out;
2672
2673 r = -E2BIG;
2674 if (msrs.nmsrs >= MAX_IO_MSRS)
2675 goto out;
2676
313a3dc7 2677 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2678 entries = memdup_user(user_msrs->entries, size);
2679 if (IS_ERR(entries)) {
2680 r = PTR_ERR(entries);
313a3dc7 2681 goto out;
ff5c2c03 2682 }
313a3dc7
CO		 2683
2684 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2685 if (r < 0)
2686 goto out_free;
2687
2688 r = -EFAULT;
2689 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2690 goto out_free;
2691
2692 r = n;
2693
2694out_free:
7a73c028 2695 kfree(entries);
313a3dc7
CO		 2696out:
2697 return r;
2698}
2699
784aa3d7 2700int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2701{
2702 int r;
2703
2704 switch (ext) {
2705 case KVM_CAP_IRQCHIP:
2706 case KVM_CAP_HLT:
2707 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2708 case KVM_CAP_SET_TSS_ADDR:
07716717 2709 case KVM_CAP_EXT_CPUID:
9c15bb1d 2710 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2711 case KVM_CAP_CLOCKSOURCE:
7837699f 2712 case KVM_CAP_PIT:
a28e4f5a 2713 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2714 case KVM_CAP_MP_STATE:
ed848624 2715 case KVM_CAP_SYNC_MMU:
a355c85c 2716 case KVM_CAP_USER_NMI:
52d939a0 2717 case KVM_CAP_REINJECT_CONTROL:
4925663a 2718 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2719 case KVM_CAP_IRQFD:
d34e6b17 2720 case KVM_CAP_IOEVENTFD:
f848a5a8 2721 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2722 case KVM_CAP_PIT2:
e9f42757 2723 case KVM_CAP_PIT_STATE2:
b927a3ce 2724 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2725 case KVM_CAP_XEN_HVM:
afbcf7ab 2726 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2727 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2728 case KVM_CAP_HYPERV:
10388a07 2729 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2730 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2731 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2732 case KVM_CAP_DEBUGREGS:
d2be1651 2733 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2734 case KVM_CAP_XSAVE:
344d9588 2735 case KVM_CAP_ASYNC_PF:
92a1f12d 2736 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2737 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2738 case KVM_CAP_READONLY_MEM:
5f66b620 2739 case KVM_CAP_HYPERV_TIME:
100943c5 2740 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2741#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2742 case KVM_CAP_ASSIGN_DEV_IRQ:
2743 case KVM_CAP_PCI_2_3:
2744#endif
018d00d2
ZX		 2745 r = 1;
2746 break;
542472b5
LV		 2747 case KVM_CAP_COALESCED_MMIO:
2748 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2749 break;
774ead3a
AK		 2750 case KVM_CAP_VAPIC:
2751 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2752 break;
f725230a 2753 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2754 r = KVM_SOFT_MAX_VCPUS;
2755 break;
2756 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2757 r = KVM_MAX_VCPUS;
2758 break;
a988b910 2759 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2760 r = KVM_USER_MEM_SLOTS;
a988b910 2761 break;
a68a6a72
MT		 2762 case KVM_CAP_PV_MMU: /* obsolete */
2763 r = 0;
2f333bcb 2764 break;
4cee4b72 2765#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2766 case KVM_CAP_IOMMU:
a1b60c1c 2767 r = iommu_present(&pci_bus_type);
62c476c7 2768 break;
4cee4b72 2769#endif
890ca9ae
HY		 2770 case KVM_CAP_MCE:
2771 r = KVM_MAX_MCE_BANKS;
2772 break;
2d5b5a66
SY		 2773 case KVM_CAP_XCRS:
2774 r = cpu_has_xsave;
2775 break;
92a1f12d
JR		 2776 case KVM_CAP_TSC_CONTROL:
2777 r = kvm_has_tsc_control;
2778 break;
4d25a066
JK		 2779 case KVM_CAP_TSC_DEADLINE_TIMER:
2780 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2781 break;
018d00d2
ZX		 2782 default:
2783 r = 0;
2784 break;
2785 }
2786 return r;
2787
2788}
2789
043405e1
CO		 2790long kvm_arch_dev_ioctl(struct file *filp,
2791 unsigned int ioctl, unsigned long arg)
2792{
2793 void __user *argp = (void __user *)arg;
2794 long r;
2795
2796 switch (ioctl) {
2797 case KVM_GET_MSR_INDEX_LIST: {
2798 struct kvm_msr_list __user *user_msr_list = argp;
2799 struct kvm_msr_list msr_list;
2800 unsigned n;
2801
2802 r = -EFAULT;
2803 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2804 goto out;
2805 n = msr_list.nmsrs;
2806 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2807 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2808 goto out;
2809 r = -E2BIG;
e125e7b6 2810 if (n < msr_list.nmsrs)
043405e1
CO		 2811 goto out;
2812 r = -EFAULT;
2813 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2814 num_msrs_to_save * sizeof(u32)))
2815 goto out;
e125e7b6 2816 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2817 &emulated_msrs,
2818 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2819 goto out;
2820 r = 0;
2821 break;
2822 }
9c15bb1d
BP		 2823 case KVM_GET_SUPPORTED_CPUID:
2824 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2825 struct kvm_cpuid2 __user *cpuid_arg = argp;
2826 struct kvm_cpuid2 cpuid;
2827
2828 r = -EFAULT;
2829 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2830 goto out;
9c15bb1d
BP		 2831
2832 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2833 ioctl);
674eea0f
AK		 2834 if (r)
2835 goto out;
2836
2837 r = -EFAULT;
2838 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2839 goto out;
2840 r = 0;
2841 break;
2842 }
890ca9ae
HY		 2843 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2844 u64 mce_cap;
2845
2846 mce_cap = KVM_MCE_CAP_SUPPORTED;
2847 r = -EFAULT;
2848 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2849 goto out;
2850 r = 0;
2851 break;
2852 }
043405e1
CO		 2853 default:
2854 r = -EINVAL;
2855 }
2856out:
2857 return r;
2858}
2859
f5f48ee1
SY		 2860static void wbinvd_ipi(void *garbage)
2861{
2862 wbinvd();
2863}
2864
2865static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2866{
e0f0bbc5 2867 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2868}
2869
313a3dc7
CO		 2870void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2871{
f5f48ee1
SY		 2872 /* Address WBINVD may be executed by guest */
2873 if (need_emulate_wbinvd(vcpu)) {
2874 if (kvm_x86_ops->has_wbinvd_exit())
2875 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2876 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2877 smp_call_function_single(vcpu->cpu,
2878 wbinvd_ipi, NULL, 1);
2879 }
2880
313a3dc7 2881 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2882
0dd6a6ed
ZA		 2883 /* Apply any externally detected TSC adjustments (due to suspend) */
2884 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2885 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2886 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2888 }
8f6055cb 2889
48434c20 2890 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2891 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2892 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2893 if (tsc_delta < 0)
2894 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2895 if (check_tsc_unstable()) {
b183aa58
ZA		 2896 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2897 vcpu->arch.last_guest_tsc);
2898 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2899 vcpu->arch.tsc_catchup = 1;
c285545f 2900 }
d98d07ca
MT		 2901 /*
2902 * On a host with synchronized TSC, there is no need to update
2903 * kvmclock on vcpu->cpu migration
2904 */
2905 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2906 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2907 if (vcpu->cpu != cpu)
2908 kvm_migrate_timers(vcpu);
e48672fa 2909 vcpu->cpu = cpu;
6b7d7e76 2910 }
c9aaa895
GC		 2911
2912 accumulate_steal_time(vcpu);
2913 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2914}
2915
2916void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2917{
02daab21 2918 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2919 kvm_put_guest_fpu(vcpu);
6f526ec5 2920 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2921}
2922
313a3dc7
CO		 2923static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2924 struct kvm_lapic_state *s)
2925{
5a71785d 2926 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2927 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2928
2929 return 0;
2930}
2931
2932static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2933 struct kvm_lapic_state *s)
2934{
64eb0620 2935 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2936 update_cr8_intercept(vcpu);
313a3dc7
CO		 2937
2938 return 0;
2939}
2940
f77bc6a4
ZX		 2941static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2942 struct kvm_interrupt *irq)
2943{
02cdb50f 2944 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2945 return -EINVAL;
2946 if (irqchip_in_kernel(vcpu->kvm))
2947 return -ENXIO;
f77bc6a4 2948
66fd3f7f 2949 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2950 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2951
f77bc6a4
ZX		 2952 return 0;
2953}
2954
c4abb7c9
JK		 2955static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2956{
c4abb7c9 2957 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2958
2959 return 0;
2960}
2961
b209749f
AK		 2962static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2963 struct kvm_tpr_access_ctl *tac)
2964{
2965 if (tac->flags)
2966 return -EINVAL;
2967 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2968 return 0;
2969}
2970
890ca9ae
HY		 2971static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2972 u64 mcg_cap)
2973{
2974 int r;
2975 unsigned bank_num = mcg_cap & 0xff, bank;
2976
2977 r = -EINVAL;
a9e38c3e 2978 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2979 goto out;
2980 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2981 goto out;
2982 r = 0;
2983 vcpu->arch.mcg_cap = mcg_cap;
2984 /* Init IA32_MCG_CTL to all 1s */
2985 if (mcg_cap & MCG_CTL_P)
2986 vcpu->arch.mcg_ctl = ~(u64)0;
2987 /* Init IA32_MCi_CTL to all 1s */
2988 for (bank = 0; bank < bank_num; bank++)
2989 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2990out:
2991 return r;
2992}
2993
2994static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2995 struct kvm_x86_mce *mce)
2996{
2997 u64 mcg_cap = vcpu->arch.mcg_cap;
2998 unsigned bank_num = mcg_cap & 0xff;
2999 u64 *banks = vcpu->arch.mce_banks;
3000
3001 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3002 return -EINVAL;
3003 /*
3004 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3005 * reporting is disabled
3006 */
3007 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3008 vcpu->arch.mcg_ctl != ~(u64)0)
3009 return 0;
3010 banks += 4 * mce->bank;
3011 /*
3012 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3013 * reporting is disabled for the bank
3014 */
3015 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3016 return 0;
3017 if (mce->status & MCI_STATUS_UC) {
3018 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3019 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3020 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3021 return 0;
3022 }
3023 if (banks[1] & MCI_STATUS_VAL)
3024 mce->status |= MCI_STATUS_OVER;
3025 banks[2] = mce->addr;
3026 banks[3] = mce->misc;
3027 vcpu->arch.mcg_status = mce->mcg_status;
3028 banks[1] = mce->status;
3029 kvm_queue_exception(vcpu, MC_VECTOR);
3030 } else if (!(banks[1] & MCI_STATUS_VAL)
3031 || !(banks[1] & MCI_STATUS_UC)) {
3032 if (banks[1] & MCI_STATUS_VAL)
3033 mce->status |= MCI_STATUS_OVER;
3034 banks[2] = mce->addr;
3035 banks[3] = mce->misc;
3036 banks[1] = mce->status;
3037 } else
3038 banks[1] |= MCI_STATUS_OVER;
3039 return 0;
3040}
3041
3cfc3092
JK		 3042static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3043 struct kvm_vcpu_events *events)
3044{
7460fb4a 3045 process_nmi(vcpu);
03b82a30
JK		 3046 events->exception.injected =
3047 vcpu->arch.exception.pending &&
3048 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3049 events->exception.nr = vcpu->arch.exception.nr;
3050 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3051 events->exception.pad = 0;
3cfc3092
JK		 3052 events->exception.error_code = vcpu->arch.exception.error_code;
3053
03b82a30
JK		 3054 events->interrupt.injected =
3055 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3056 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3057 events->interrupt.soft = 0;
37ccdcbe 3058 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3059
3060 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3061 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3062 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3063 events->nmi.pad = 0;
3cfc3092 3064
66450a21 3065 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3066
dab4b911 3067 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3068 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3069 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3070}
3071
3072static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3073 struct kvm_vcpu_events *events)
3074{
dab4b911 3075 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3076 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3077 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3078 return -EINVAL;
3079
7460fb4a 3080 process_nmi(vcpu);
3cfc3092
JK		 3081 vcpu->arch.exception.pending = events->exception.injected;
3082 vcpu->arch.exception.nr = events->exception.nr;
3083 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3084 vcpu->arch.exception.error_code = events->exception.error_code;
3085
3086 vcpu->arch.interrupt.pending = events->interrupt.injected;
3087 vcpu->arch.interrupt.nr = events->interrupt.nr;
3088 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3089 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3090 kvm_x86_ops->set_interrupt_shadow(vcpu,
3091 events->interrupt.shadow);
3cfc3092
JK		 3092
3093 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3094 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3095 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3096 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3097
66450a21
JK		 3098 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3099 kvm_vcpu_has_lapic(vcpu))
3100 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3101
3842d135
AK		 3102 kvm_make_request(KVM_REQ_EVENT, vcpu);
3103
3cfc3092
JK		 3104 return 0;
3105}
3106
a1efbe77
JK		 3107static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3108 struct kvm_debugregs *dbgregs)
3109{
73aaf249
JK		 3110 unsigned long val;
3111
a1efbe77 3112 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3113 kvm_get_dr(vcpu, 6, &val);
73aaf249 3114 dbgregs->dr6 = val;
a1efbe77
JK		 3115 dbgregs->dr7 = vcpu->arch.dr7;
3116 dbgregs->flags = 0;
97e69aa6 3117 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3118}
3119
3120static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3121 struct kvm_debugregs *dbgregs)
3122{
3123 if (dbgregs->flags)
3124 return -EINVAL;
3125
a1efbe77
JK		 3126 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3127 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3128 kvm_update_dr6(vcpu);
a1efbe77 3129 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3130 kvm_update_dr7(vcpu);
a1efbe77 3131
a1efbe77
JK		 3132 return 0;
3133}
3134
df1daba7
PB		 3135#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3136
3137static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3138{
3139 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3140 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3141 u64 valid;
3142
3143 /*
3144 * Copy legacy XSAVE area, to avoid complications with CPUID
3145 * leaves 0 and 1 in the loop below.
3146 */
3147 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3148
3149 /* Set XSTATE_BV */
3150 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3151
3152 /*
3153 * Copy each region from the possibly compacted offset to the
3154 * non-compacted offset.
3155 */
3156 valid = xstate_bv & ~XSTATE_FPSSE;
3157 while (valid) {
3158 u64 feature = valid & -valid;
3159 int index = fls64(feature) - 1;
3160 void *src = get_xsave_addr(xsave, feature);
3161
3162 if (src) {
3163 u32 size, offset, ecx, edx;
3164 cpuid_count(XSTATE_CPUID, index,
3165 &size, &offset, &ecx, &edx);
3166 memcpy(dest + offset, src, size);
3167 }
3168
3169 valid -= feature;
3170 }
3171}
3172
3173static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3174{
3175 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3176 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3177 u64 valid;
3178
3179 /*
3180 * Copy legacy XSAVE area, to avoid complications with CPUID
3181 * leaves 0 and 1 in the loop below.
3182 */
3183 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3184
3185 /* Set XSTATE_BV and possibly XCOMP_BV. */
3186 xsave->xsave_hdr.xstate_bv = xstate_bv;
3187 if (cpu_has_xsaves)
3188 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3189
3190 /*
3191 * Copy each region from the non-compacted offset to the
3192 * possibly compacted offset.
3193 */
3194 valid = xstate_bv & ~XSTATE_FPSSE;
3195 while (valid) {
3196 u64 feature = valid & -valid;
3197 int index = fls64(feature) - 1;
3198 void *dest = get_xsave_addr(xsave, feature);
3199
3200 if (dest) {
3201 u32 size, offset, ecx, edx;
3202 cpuid_count(XSTATE_CPUID, index,
3203 &size, &offset, &ecx, &edx);
3204 memcpy(dest, src + offset, size);
3205 } else
3206 WARN_ON_ONCE(1);
3207
3208 valid -= feature;
3209 }
3210}
3211
2d5b5a66
SY		 3212static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3213 struct kvm_xsave *guest_xsave)
3214{
4344ee98 3215 if (cpu_has_xsave) {
df1daba7
PB		 3216 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3217 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3218 } else {
2d5b5a66
SY		 3219 memcpy(guest_xsave->region,
3220 &vcpu->arch.guest_fpu.state->fxsave,
3221 sizeof(struct i387_fxsave_struct));
3222 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3223 XSTATE_FPSSE;
3224 }
3225}
3226
3227static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3228 struct kvm_xsave *guest_xsave)
3229{
3230 u64 xstate_bv =
3231 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3232
d7876f1b
PB		 3233 if (cpu_has_xsave) {
3234 /*
3235 * Here we allow setting states that are not present in
3236 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3237 * with old userspace.
3238 */
4ff41732 3239 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3240 return -EINVAL;
df1daba7 3241 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3242 } else {
2d5b5a66
SY		 3243 if (xstate_bv & ~XSTATE_FPSSE)
3244 return -EINVAL;
3245 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3246 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3247 }
3248 return 0;
3249}
3250
3251static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3252 struct kvm_xcrs *guest_xcrs)
3253{
3254 if (!cpu_has_xsave) {
3255 guest_xcrs->nr_xcrs = 0;
3256 return;
3257 }
3258
3259 guest_xcrs->nr_xcrs = 1;
3260 guest_xcrs->flags = 0;
3261 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3262 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3263}
3264
3265static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3266 struct kvm_xcrs *guest_xcrs)
3267{
3268 int i, r = 0;
3269
3270 if (!cpu_has_xsave)
3271 return -EINVAL;
3272
3273 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3274 return -EINVAL;
3275
3276 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3277 /* Only support XCR0 currently */
c67a04cb 3278 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3279 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3280 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3281 break;
3282 }
3283 if (r)
3284 r = -EINVAL;
3285 return r;
3286}
3287
1c0b28c2
EM		 3288/*
3289 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3290 * stopped by the hypervisor. This function will be called from the host only.
3291 * EINVAL is returned when the host attempts to set the flag for a guest that
3292 * does not support pv clocks.
3293 */
3294static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3295{
0b79459b 3296 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3297 return -EINVAL;
51d59c6b 3298 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3299 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3300 return 0;
3301}
3302
313a3dc7
CO		 3303long kvm_arch_vcpu_ioctl(struct file *filp,
3304 unsigned int ioctl, unsigned long arg)
3305{
3306 struct kvm_vcpu *vcpu = filp->private_data;
3307 void __user *argp = (void __user *)arg;
3308 int r;
d1ac91d8
AK		 3309 union {
3310 struct kvm_lapic_state *lapic;
3311 struct kvm_xsave *xsave;
3312 struct kvm_xcrs *xcrs;
3313 void *buffer;
3314 } u;
3315
3316 u.buffer = NULL;
313a3dc7
CO		 3317 switch (ioctl) {
3318 case KVM_GET_LAPIC: {
2204ae3c
MT		 3319 r = -EINVAL;
3320 if (!vcpu->arch.apic)
3321 goto out;
d1ac91d8 3322 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3323
b772ff36 3324 r = -ENOMEM;
d1ac91d8 3325 if (!u.lapic)
b772ff36 3326 goto out;
d1ac91d8 3327 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3328 if (r)
3329 goto out;
3330 r = -EFAULT;
d1ac91d8 3331 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3332 goto out;
3333 r = 0;
3334 break;
3335 }
3336 case KVM_SET_LAPIC: {
2204ae3c
MT		 3337 r = -EINVAL;
3338 if (!vcpu->arch.apic)
3339 goto out;
ff5c2c03 3340 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3341 if (IS_ERR(u.lapic))
3342 return PTR_ERR(u.lapic);
ff5c2c03 3343
d1ac91d8 3344 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3345 break;
3346 }
f77bc6a4
ZX		 3347 case KVM_INTERRUPT: {
3348 struct kvm_interrupt irq;
3349
3350 r = -EFAULT;
3351 if (copy_from_user(&irq, argp, sizeof irq))
3352 goto out;
3353 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3354 break;
3355 }
c4abb7c9
JK		 3356 case KVM_NMI: {
3357 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3358 break;
3359 }
313a3dc7
CO		 3360 case KVM_SET_CPUID: {
3361 struct kvm_cpuid __user *cpuid_arg = argp;
3362 struct kvm_cpuid cpuid;
3363
3364 r = -EFAULT;
3365 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3366 goto out;
3367 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3368 break;
3369 }
07716717
DK		 3370 case KVM_SET_CPUID2: {
3371 struct kvm_cpuid2 __user *cpuid_arg = argp;
3372 struct kvm_cpuid2 cpuid;
3373
3374 r = -EFAULT;
3375 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3376 goto out;
3377 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3378 cpuid_arg->entries);
07716717
DK		 3379 break;
3380 }
3381 case KVM_GET_CPUID2: {
3382 struct kvm_cpuid2 __user *cpuid_arg = argp;
3383 struct kvm_cpuid2 cpuid;
3384
3385 r = -EFAULT;
3386 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3387 goto out;
3388 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3389 cpuid_arg->entries);
07716717
DK		 3390 if (r)
3391 goto out;
3392 r = -EFAULT;
3393 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3394 goto out;
3395 r = 0;
3396 break;
3397 }
313a3dc7
CO		 3398 case KVM_GET_MSRS:
3399 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3400 break;
3401 case KVM_SET_MSRS:
3402 r = msr_io(vcpu, argp, do_set_msr, 0);
3403 break;
b209749f
AK		 3404 case KVM_TPR_ACCESS_REPORTING: {
3405 struct kvm_tpr_access_ctl tac;
3406
3407 r = -EFAULT;
3408 if (copy_from_user(&tac, argp, sizeof tac))
3409 goto out;
3410 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3411 if (r)
3412 goto out;
3413 r = -EFAULT;
3414 if (copy_to_user(argp, &tac, sizeof tac))
3415 goto out;
3416 r = 0;
3417 break;
3418 };
b93463aa
AK		 3419 case KVM_SET_VAPIC_ADDR: {
3420 struct kvm_vapic_addr va;
3421
3422 r = -EINVAL;
3423 if (!irqchip_in_kernel(vcpu->kvm))
3424 goto out;
3425 r = -EFAULT;
3426 if (copy_from_user(&va, argp, sizeof va))
3427 goto out;
fda4e2e8 3428 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3429 break;
3430 }
890ca9ae
HY		 3431 case KVM_X86_SETUP_MCE: {
3432 u64 mcg_cap;
3433
3434 r = -EFAULT;
3435 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3436 goto out;
3437 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3438 break;
3439 }
3440 case KVM_X86_SET_MCE: {
3441 struct kvm_x86_mce mce;
3442
3443 r = -EFAULT;
3444 if (copy_from_user(&mce, argp, sizeof mce))
3445 goto out;
3446 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3447 break;
3448 }
3cfc3092
JK		 3449 case KVM_GET_VCPU_EVENTS: {
3450 struct kvm_vcpu_events events;
3451
3452 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3453
3454 r = -EFAULT;
3455 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3456 break;
3457 r = 0;
3458 break;
3459 }
3460 case KVM_SET_VCPU_EVENTS: {
3461 struct kvm_vcpu_events events;
3462
3463 r = -EFAULT;
3464 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3465 break;
3466
3467 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3468 break;
3469 }
a1efbe77
JK		 3470 case KVM_GET_DEBUGREGS: {
3471 struct kvm_debugregs dbgregs;
3472
3473 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3474
3475 r = -EFAULT;
3476 if (copy_to_user(argp, &dbgregs,
3477 sizeof(struct kvm_debugregs)))
3478 break;
3479 r = 0;
3480 break;
3481 }
3482 case KVM_SET_DEBUGREGS: {
3483 struct kvm_debugregs dbgregs;
3484
3485 r = -EFAULT;
3486 if (copy_from_user(&dbgregs, argp,
3487 sizeof(struct kvm_debugregs)))
3488 break;
3489
3490 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3491 break;
3492 }
2d5b5a66 3493 case KVM_GET_XSAVE: {
d1ac91d8 3494 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3495 r = -ENOMEM;
d1ac91d8 3496 if (!u.xsave)
2d5b5a66
SY		 3497 break;
3498
d1ac91d8 3499 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3500
3501 r = -EFAULT;
d1ac91d8 3502 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3503 break;
3504 r = 0;
3505 break;
3506 }
3507 case KVM_SET_XSAVE: {
ff5c2c03 3508 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3509 if (IS_ERR(u.xsave))
3510 return PTR_ERR(u.xsave);
2d5b5a66 3511
d1ac91d8 3512 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3513 break;
3514 }
3515 case KVM_GET_XCRS: {
d1ac91d8 3516 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3517 r = -ENOMEM;
d1ac91d8 3518 if (!u.xcrs)
2d5b5a66
SY		 3519 break;
3520
d1ac91d8 3521 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3522
3523 r = -EFAULT;
d1ac91d8 3524 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3525 sizeof(struct kvm_xcrs)))
3526 break;
3527 r = 0;
3528 break;
3529 }
3530 case KVM_SET_XCRS: {
ff5c2c03 3531 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3532 if (IS_ERR(u.xcrs))
3533 return PTR_ERR(u.xcrs);
2d5b5a66 3534
d1ac91d8 3535 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3536 break;
3537 }
92a1f12d
JR		 3538 case KVM_SET_TSC_KHZ: {
3539 u32 user_tsc_khz;
3540
3541 r = -EINVAL;
92a1f12d
JR		 3542 user_tsc_khz = (u32)arg;
3543
3544 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3545 goto out;
3546
cc578287
ZA		 3547 if (user_tsc_khz == 0)
3548 user_tsc_khz = tsc_khz;
3549
3550 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3551
3552 r = 0;
3553 goto out;
3554 }
3555 case KVM_GET_TSC_KHZ: {
cc578287 3556 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3557 goto out;
3558 }
1c0b28c2
EM		 3559 case KVM_KVMCLOCK_CTRL: {
3560 r = kvm_set_guest_paused(vcpu);
3561 goto out;
3562 }
313a3dc7
CO		 3563 default:
3564 r = -EINVAL;
3565 }
3566out:
d1ac91d8 3567 kfree(u.buffer);
313a3dc7
CO		 3568 return r;
3569}
3570
5b1c1493
CO		 3571int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3572{
3573 return VM_FAULT_SIGBUS;
3574}
3575
1fe779f8
CO		 3576static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3577{
3578 int ret;
3579
3580 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3581 return -EINVAL;
1fe779f8
CO		 3582 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3583 return ret;
3584}
3585
b927a3ce
SY		 3586static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3587 u64 ident_addr)
3588{
3589 kvm->arch.ept_identity_map_addr = ident_addr;
3590 return 0;
3591}
3592
1fe779f8
CO		 3593static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3594 u32 kvm_nr_mmu_pages)
3595{
3596 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3597 return -EINVAL;
3598
79fac95e 3599 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3600
3601 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3602 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3603
79fac95e 3604 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3605 return 0;
3606}
3607
3608static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3609{
39de71ec 3610 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3611}
3612
1fe779f8
CO		 3613static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3614{
3615 int r;
3616
3617 r = 0;
3618 switch (chip->chip_id) {
3619 case KVM_IRQCHIP_PIC_MASTER:
3620 memcpy(&chip->chip.pic,
3621 &pic_irqchip(kvm)->pics[0],
3622 sizeof(struct kvm_pic_state));
3623 break;
3624 case KVM_IRQCHIP_PIC_SLAVE:
3625 memcpy(&chip->chip.pic,
3626 &pic_irqchip(kvm)->pics[1],
3627 sizeof(struct kvm_pic_state));
3628 break;
3629 case KVM_IRQCHIP_IOAPIC:
eba0226b 3630 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3631 break;
3632 default:
3633 r = -EINVAL;
3634 break;
3635 }
3636 return r;
3637}
3638
3639static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3640{
3641 int r;
3642
3643 r = 0;
3644 switch (chip->chip_id) {
3645 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3646 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3647 memcpy(&pic_irqchip(kvm)->pics[0],
3648 &chip->chip.pic,
3649 sizeof(struct kvm_pic_state));
f4f51050 3650 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3651 break;
3652 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3653 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3654 memcpy(&pic_irqchip(kvm)->pics[1],
3655 &chip->chip.pic,
3656 sizeof(struct kvm_pic_state));
f4f51050 3657 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3658 break;
3659 case KVM_IRQCHIP_IOAPIC:
eba0226b 3660 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3661 break;
3662 default:
3663 r = -EINVAL;
3664 break;
3665 }
3666 kvm_pic_update_irq(pic_irqchip(kvm));
3667 return r;
3668}
3669
e0f63cb9
SY		 3670static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3671{
3672 int r = 0;
3673
894a9c55 3674 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3675 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3676 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3677 return r;
3678}
3679
3680static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3681{
3682 int r = 0;
3683
894a9c55 3684 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3685 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3686 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3687 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3688 return r;
3689}
3690
3691static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3692{
3693 int r = 0;
3694
3695 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3696 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3697 sizeof(ps->channels));
3698 ps->flags = kvm->arch.vpit->pit_state.flags;
3699 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3700 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3701 return r;
3702}
3703
3704static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3705{
3706 int r = 0, start = 0;
3707 u32 prev_legacy, cur_legacy;
3708 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3709 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3710 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3711 if (!prev_legacy && cur_legacy)
3712 start = 1;
3713 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3714 sizeof(kvm->arch.vpit->pit_state.channels));
3715 kvm->arch.vpit->pit_state.flags = ps->flags;
3716 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3717 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3718 return r;
3719}
3720
52d939a0
MT		 3721static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3722 struct kvm_reinject_control *control)
3723{
3724 if (!kvm->arch.vpit)
3725 return -ENXIO;
894a9c55 3726 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3727 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3728 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3729 return 0;
3730}
3731
95d4c16c 3732/**
60c34612
TY		 3733 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3734 * @kvm: kvm instance
3735 * @log: slot id and address to which we copy the log
95d4c16c 3736 *
60c34612
TY		 3737 * We need to keep it in mind that VCPU threads can write to the bitmap
3738 * concurrently. So, to avoid losing data, we keep the following order for
3739 * each bit:
95d4c16c 3740 *
60c34612
TY		 3741 * 1. Take a snapshot of the bit and clear it if needed.
3742 * 2. Write protect the corresponding page.
3743 * 3. Flush TLB's if needed.
3744 * 4. Copy the snapshot to the userspace.
95d4c16c 3745 *
60c34612
TY		 3746 * Between 2 and 3, the guest may write to the page using the remaining TLB
3747 * entry. This is not a problem because the page will be reported dirty at
3748 * step 4 using the snapshot taken before and step 3 ensures that successive
3749 * writes will be logged for the next call.
5bb064dc 3750 */
60c34612 3751int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3752{
7850ac54 3753 int r;
5bb064dc 3754 struct kvm_memory_slot *memslot;
60c34612
TY		 3755 unsigned long n, i;
3756 unsigned long *dirty_bitmap;
3757 unsigned long *dirty_bitmap_buffer;
3758 bool is_dirty = false;
5bb064dc 3759
79fac95e 3760 mutex_lock(&kvm->slots_lock);
5bb064dc 3761
b050b015 3762 r = -EINVAL;
bbacc0c1 3763 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3764 goto out;
3765
28a37544 3766 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3767
3768 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3769 r = -ENOENT;
60c34612 3770 if (!dirty_bitmap)
b050b015
MT		 3771 goto out;
3772
87bf6e7d 3773 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3774
60c34612
TY		 3775 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3776 memset(dirty_bitmap_buffer, 0, n);
b050b015 3777
60c34612 3778 spin_lock(&kvm->mmu_lock);
b050b015 3779
60c34612
TY		 3780 for (i = 0; i < n / sizeof(long); i++) {
3781 unsigned long mask;
3782 gfn_t offset;
cdfca7b3 3783
60c34612
TY		 3784 if (!dirty_bitmap[i])
3785 continue;
b050b015 3786
60c34612 3787 is_dirty = true;
914ebccd 3788
60c34612
TY		 3789 mask = xchg(&dirty_bitmap[i], 0);
3790 dirty_bitmap_buffer[i] = mask;
edde99ce 3791
60c34612
TY		 3792 offset = i * BITS_PER_LONG;
3793 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3794 }
60c34612
TY		 3795
3796 spin_unlock(&kvm->mmu_lock);
3797
198c74f4
XG		 3798 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3799 lockdep_assert_held(&kvm->slots_lock);
3800
3801 /*
3802 * All the TLBs can be flushed out of mmu lock, see the comments in
3803 * kvm_mmu_slot_remove_write_access().
3804 */
3805 if (is_dirty)
3806 kvm_flush_remote_tlbs(kvm);
3807
60c34612
TY		 3808 r = -EFAULT;
3809 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3810 goto out;
b050b015 3811
5bb064dc
ZX		 3812 r = 0;
3813out:
79fac95e 3814 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3815 return r;
3816}
3817
aa2fbe6d
YZ		 3818int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3819 bool line_status)
23d43cf9
CD		 3820{
3821 if (!irqchip_in_kernel(kvm))
3822 return -ENXIO;
3823
3824 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3825 irq_event->irq, irq_event->level,
3826 line_status);
23d43cf9
CD		 3827 return 0;
3828}
3829
1fe779f8
CO		 3830long kvm_arch_vm_ioctl(struct file *filp,
3831 unsigned int ioctl, unsigned long arg)
3832{
3833 struct kvm *kvm = filp->private_data;
3834 void __user *argp = (void __user *)arg;
367e1319 3835 int r = -ENOTTY;
f0d66275
DH		 3836 /*
3837 * This union makes it completely explicit to gcc-3.x
3838 * that these two variables' stack usage should be
3839 * combined, not added together.
3840 */
3841 union {
3842 struct kvm_pit_state ps;
e9f42757 3843 struct kvm_pit_state2 ps2;
c5ff41ce 3844 struct kvm_pit_config pit_config;
f0d66275 3845 } u;
1fe779f8
CO		 3846
3847 switch (ioctl) {
3848 case KVM_SET_TSS_ADDR:
3849 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3850 break;
b927a3ce
SY		 3851 case KVM_SET_IDENTITY_MAP_ADDR: {
3852 u64 ident_addr;
3853
3854 r = -EFAULT;
3855 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3856 goto out;
3857 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3858 break;
3859 }
1fe779f8
CO		 3860 case KVM_SET_NR_MMU_PAGES:
3861 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3862 break;
3863 case KVM_GET_NR_MMU_PAGES:
3864 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3865 break;
3ddea128
MT		 3866 case KVM_CREATE_IRQCHIP: {
3867 struct kvm_pic *vpic;
3868
3869 mutex_lock(&kvm->lock);
3870 r = -EEXIST;
3871 if (kvm->arch.vpic)
3872 goto create_irqchip_unlock;
3e515705
AK		 3873 r = -EINVAL;
3874 if (atomic_read(&kvm->online_vcpus))
3875 goto create_irqchip_unlock;
1fe779f8 3876 r = -ENOMEM;
3ddea128
MT		 3877 vpic = kvm_create_pic(kvm);
3878 if (vpic) {
1fe779f8
CO		 3879 r = kvm_ioapic_init(kvm);
3880 if (r) {
175504cd 3881 mutex_lock(&kvm->slots_lock);
72bb2fcd 3882 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3883 &vpic->dev_master);
3884 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3885 &vpic->dev_slave);
3886 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3887 &vpic->dev_eclr);
175504cd 3888 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3889 kfree(vpic);
3890 goto create_irqchip_unlock;
1fe779f8
CO		 3891 }
3892 } else
3ddea128
MT		 3893 goto create_irqchip_unlock;
3894 smp_wmb();
3895 kvm->arch.vpic = vpic;
3896 smp_wmb();
399ec807
AK		 3897 r = kvm_setup_default_irq_routing(kvm);
3898 if (r) {
175504cd 3899 mutex_lock(&kvm->slots_lock);
3ddea128 3900 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3901 kvm_ioapic_destroy(kvm);
3902 kvm_destroy_pic(kvm);
3ddea128 3903 mutex_unlock(&kvm->irq_lock);
175504cd 3904 mutex_unlock(&kvm->slots_lock);
399ec807 3905 }
3ddea128
MT		 3906 create_irqchip_unlock:
3907 mutex_unlock(&kvm->lock);
1fe779f8 3908 break;
3ddea128 3909 }
7837699f 3910 case KVM_CREATE_PIT:
c5ff41ce
JK		 3911 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3912 goto create_pit;
3913 case KVM_CREATE_PIT2:
3914 r = -EFAULT;
3915 if (copy_from_user(&u.pit_config, argp,
3916 sizeof(struct kvm_pit_config)))
3917 goto out;
3918 create_pit:
79fac95e 3919 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3920 r = -EEXIST;
3921 if (kvm->arch.vpit)
3922 goto create_pit_unlock;
7837699f 3923 r = -ENOMEM;
c5ff41ce 3924 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3925 if (kvm->arch.vpit)
3926 r = 0;
269e05e4 3927 create_pit_unlock:
79fac95e 3928 mutex_unlock(&kvm->slots_lock);
7837699f 3929 break;
1fe779f8
CO		 3930 case KVM_GET_IRQCHIP: {
3931 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3932 struct kvm_irqchip *chip;
1fe779f8 3933
ff5c2c03
SL		 3934 chip = memdup_user(argp, sizeof(*chip));
3935 if (IS_ERR(chip)) {
3936 r = PTR_ERR(chip);
1fe779f8 3937 goto out;
ff5c2c03
SL		 3938 }
3939
1fe779f8
CO		 3940 r = -ENXIO;
3941 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3942 goto get_irqchip_out;
3943 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3944 if (r)
f0d66275 3945 goto get_irqchip_out;
1fe779f8 3946 r = -EFAULT;
f0d66275
DH		 3947 if (copy_to_user(argp, chip, sizeof *chip))
3948 goto get_irqchip_out;
1fe779f8 3949 r = 0;
f0d66275
DH		 3950 get_irqchip_out:
3951 kfree(chip);
1fe779f8
CO		 3952 break;
3953 }
3954 case KVM_SET_IRQCHIP: {
3955 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3956 struct kvm_irqchip *chip;
1fe779f8 3957
ff5c2c03
SL		 3958 chip = memdup_user(argp, sizeof(*chip));
3959 if (IS_ERR(chip)) {
3960 r = PTR_ERR(chip);
1fe779f8 3961 goto out;
ff5c2c03
SL		 3962 }
3963
1fe779f8
CO		 3964 r = -ENXIO;
3965 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3966 goto set_irqchip_out;
3967 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3968 if (r)
f0d66275 3969 goto set_irqchip_out;
1fe779f8 3970 r = 0;
f0d66275
DH		 3971 set_irqchip_out:
3972 kfree(chip);
1fe779f8
CO		 3973 break;
3974 }
e0f63cb9 3975 case KVM_GET_PIT: {
e0f63cb9 3976 r = -EFAULT;
f0d66275 3977 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3978 goto out;
3979 r = -ENXIO;
3980 if (!kvm->arch.vpit)
3981 goto out;
f0d66275 3982 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3983 if (r)
3984 goto out;
3985 r = -EFAULT;
f0d66275 3986 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3987 goto out;
3988 r = 0;
3989 break;
3990 }
3991 case KVM_SET_PIT: {
e0f63cb9 3992 r = -EFAULT;
f0d66275 3993 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3994 goto out;
3995 r = -ENXIO;
3996 if (!kvm->arch.vpit)
3997 goto out;
f0d66275 3998 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3999 break;
4000 }
e9f42757
BK		 4001 case KVM_GET_PIT2: {
4002 r = -ENXIO;
4003 if (!kvm->arch.vpit)
4004 goto out;
4005 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4006 if (r)
4007 goto out;
4008 r = -EFAULT;
4009 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4010 goto out;
4011 r = 0;
4012 break;
4013 }
4014 case KVM_SET_PIT2: {
4015 r = -EFAULT;
4016 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4017 goto out;
4018 r = -ENXIO;
4019 if (!kvm->arch.vpit)
4020 goto out;
4021 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4022 break;
4023 }
52d939a0
MT		 4024 case KVM_REINJECT_CONTROL: {
4025 struct kvm_reinject_control control;
4026 r = -EFAULT;
4027 if (copy_from_user(&control, argp, sizeof(control)))
4028 goto out;
4029 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4030 break;
4031 }
ffde22ac
ES		 4032 case KVM_XEN_HVM_CONFIG: {
4033 r = -EFAULT;
4034 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4035 sizeof(struct kvm_xen_hvm_config)))
4036 goto out;
4037 r = -EINVAL;
4038 if (kvm->arch.xen_hvm_config.flags)
4039 goto out;
4040 r = 0;
4041 break;
4042 }
afbcf7ab 4043 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4044 struct kvm_clock_data user_ns;
4045 u64 now_ns;
4046 s64 delta;
4047
4048 r = -EFAULT;
4049 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4050 goto out;
4051
4052 r = -EINVAL;
4053 if (user_ns.flags)
4054 goto out;
4055
4056 r = 0;
395c6b0a 4057 local_irq_disable();
759379dd 4058 now_ns = get_kernel_ns();
afbcf7ab 4059 delta = user_ns.clock - now_ns;
395c6b0a 4060 local_irq_enable();
afbcf7ab 4061 kvm->arch.kvmclock_offset = delta;
2e762ff7 4062 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4063 break;
4064 }
4065 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4066 struct kvm_clock_data user_ns;
4067 u64 now_ns;
4068
395c6b0a 4069 local_irq_disable();
759379dd 4070 now_ns = get_kernel_ns();
afbcf7ab 4071 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4072 local_irq_enable();
afbcf7ab 4073 user_ns.flags = 0;
97e69aa6 4074 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4075
4076 r = -EFAULT;
4077 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4078 goto out;
4079 r = 0;
4080 break;
4081 }
4082
1fe779f8 4083 default:
c274e03a 4084 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4085 }
4086out:
4087 return r;
4088}
4089
a16b043c 4090static void kvm_init_msr_list(void)
043405e1
CO		 4091{
4092 u32 dummy[2];
4093 unsigned i, j;
4094
e3267cbb
GC		 4095 /* skip the first msrs in the list. KVM-specific */
4096 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4097 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4098 continue;
93c4adc7
PB		 4099
4100 /*
4101 * Even MSRs that are valid in the host may not be exposed
4102 * to the guests in some cases. We could work around this
4103 * in VMX with the generic MSR save/load machinery, but it
4104 * is not really worthwhile since it will really only
4105 * happen with nested virtualization.
4106 */
4107 switch (msrs_to_save[i]) {
4108 case MSR_IA32_BNDCFGS:
4109 if (!kvm_x86_ops->mpx_supported())
4110 continue;
4111 break;
4112 default:
4113 break;
4114 }
4115
043405e1
CO		 4116 if (j < i)
4117 msrs_to_save[j] = msrs_to_save[i];
4118 j++;
4119 }
4120 num_msrs_to_save = j;
4121}
4122
bda9020e
MT		 4123static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4124 const void *v)
bbd9b64e 4125{
70252a10
AK		 4126 int handled = 0;
4127 int n;
4128
4129 do {
4130 n = min(len, 8);
4131 if (!(vcpu->arch.apic &&
4132 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4133 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4134 break;
4135 handled += n;
4136 addr += n;
4137 len -= n;
4138 v += n;
4139 } while (len);
bbd9b64e 4140
70252a10 4141 return handled;
bbd9b64e
CO		 4142}
4143
bda9020e 4144static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4145{
70252a10
AK		 4146 int handled = 0;
4147 int n;
4148
4149 do {
4150 n = min(len, 8);
4151 if (!(vcpu->arch.apic &&
4152 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4153 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4154 break;
4155 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4156 handled += n;
4157 addr += n;
4158 len -= n;
4159 v += n;
4160 } while (len);
bbd9b64e 4161
70252a10 4162 return handled;
bbd9b64e
CO		 4163}
4164
2dafc6c2
GN		 4165static void kvm_set_segment(struct kvm_vcpu *vcpu,
4166 struct kvm_segment *var, int seg)
4167{
4168 kvm_x86_ops->set_segment(vcpu, var, seg);
4169}
4170
4171void kvm_get_segment(struct kvm_vcpu *vcpu,
4172 struct kvm_segment *var, int seg)
4173{
4174 kvm_x86_ops->get_segment(vcpu, var, seg);
4175}
4176
54987b7a
PB		 4177gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4178 struct x86_exception *exception)
02f59dc9
JR		 4179{
4180 gpa_t t_gpa;
02f59dc9
JR		 4181
4182 BUG_ON(!mmu_is_nested(vcpu));
4183
4184 /* NPT walks are always user-walks */
4185 access |= PFERR_USER_MASK;
54987b7a 4186 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4187
4188 return t_gpa;
4189}
4190
ab9ae313
AK		 4191gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4192 struct x86_exception *exception)
1871c602
GN		 4193{
4194 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4195 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4196}
4197
ab9ae313
AK		 4198 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4199 struct x86_exception *exception)
1871c602
GN		 4200{
4201 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4202 access |= PFERR_FETCH_MASK;
ab9ae313 4203 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4204}
4205
ab9ae313
AK		 4206gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4207 struct x86_exception *exception)
1871c602
GN		 4208{
4209 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4210 access |= PFERR_WRITE_MASK;
ab9ae313 4211 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4212}
4213
4214/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4215gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4216 struct x86_exception *exception)
1871c602 4217{
ab9ae313 4218 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4219}
4220
4221static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4222 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4223 struct x86_exception *exception)
bbd9b64e
CO		 4224{
4225 void *data = val;
10589a46 4226 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4227
4228 while (bytes) {
14dfe855 4229 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4230 exception);
bbd9b64e 4231 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4232 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4233 int ret;
4234
bcc55cba 4235 if (gpa == UNMAPPED_GVA)
ab9ae313 4236 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4237 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4238 offset, toread);
10589a46 4239 if (ret < 0) {
c3cd7ffa 4240 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4241 goto out;
4242 }
bbd9b64e 4243
77c2002e
IE		 4244 bytes -= toread;
4245 data += toread;
4246 addr += toread;
bbd9b64e 4247 }
10589a46 4248out:
10589a46 4249 return r;
bbd9b64e 4250}
77c2002e 4251
1871c602 4252/* used for instruction fetching */
0f65dd70
AK		 4253static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4254 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4255 struct x86_exception *exception)
1871c602 4256{
0f65dd70 4257 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4258 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4259 unsigned offset;
4260 int ret;
0f65dd70 4261
44583cba
PB		 4262 /* Inline kvm_read_guest_virt_helper for speed. */
4263 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4264 exception);
4265 if (unlikely(gpa == UNMAPPED_GVA))
4266 return X86EMUL_PROPAGATE_FAULT;
4267
4268 offset = addr & (PAGE_SIZE-1);
4269 if (WARN_ON(offset + bytes > PAGE_SIZE))
4270 bytes = (unsigned)PAGE_SIZE - offset;
4271 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4272 offset, bytes);
4273 if (unlikely(ret < 0))
4274 return X86EMUL_IO_NEEDED;
4275
4276 return X86EMUL_CONTINUE;
1871c602
GN		 4277}
4278
064aea77 4279int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4280 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4281 struct x86_exception *exception)
1871c602 4282{
0f65dd70 4283 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4284 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4285
1871c602 4286 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4287 exception);
1871c602 4288}
064aea77 4289EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4290
0f65dd70
AK		 4291static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4292 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4293 struct x86_exception *exception)
1871c602 4294{
0f65dd70 4295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4296 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4297}
4298
6a4d7550 4299int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4300 gva_t addr, void *val,
2dafc6c2 4301 unsigned int bytes,
bcc55cba 4302 struct x86_exception *exception)
77c2002e 4303{
0f65dd70 4304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4305 void *data = val;
4306 int r = X86EMUL_CONTINUE;
4307
4308 while (bytes) {
14dfe855
JR		 4309 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4310 PFERR_WRITE_MASK,
ab9ae313 4311 exception);
77c2002e
IE		 4312 unsigned offset = addr & (PAGE_SIZE-1);
4313 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4314 int ret;
4315
bcc55cba 4316 if (gpa == UNMAPPED_GVA)
ab9ae313 4317 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4318 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4319 if (ret < 0) {
c3cd7ffa 4320 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4321 goto out;
4322 }
4323
4324 bytes -= towrite;
4325 data += towrite;
4326 addr += towrite;
4327 }
4328out:
4329 return r;
4330}
6a4d7550 4331EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4332
af7cc7d1
XG		 4333static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4334 gpa_t *gpa, struct x86_exception *exception,
4335 bool write)
4336{
97d64b78
AK		 4337 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4338 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4339
97d64b78 4340 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4341 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4342 vcpu->arch.access, access)) {
bebb106a
XG		 4343 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4344 (gva & (PAGE_SIZE - 1));
4f022648 4345 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4346 return 1;
4347 }
4348
af7cc7d1
XG		 4349 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4350
4351 if (*gpa == UNMAPPED_GVA)
4352 return -1;
4353
4354 /* For APIC access vmexit */
4355 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4356 return 1;
4357
4f022648
XG		 4358 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4359 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4360 return 1;
4f022648 4361 }
bebb106a 4362
af7cc7d1
XG		 4363 return 0;
4364}
4365
3200f405 4366int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4367 const void *val, int bytes)
bbd9b64e
CO		 4368{
4369 int ret;
4370
4371 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4372 if (ret < 0)
bbd9b64e 4373 return 0;
f57f2ef5 4374 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4375 return 1;
4376}
4377
77d197b2
XG		 4378struct read_write_emulator_ops {
4379 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4380 int bytes);
4381 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4382 void *val, int bytes);
4383 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4384 int bytes, void *val);
4385 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4386 void *val, int bytes);
4387 bool write;
4388};
4389
4390static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4391{
4392 if (vcpu->mmio_read_completed) {
77d197b2 4393 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4394 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4395 vcpu->mmio_read_completed = 0;
4396 return 1;
4397 }
4398
4399 return 0;
4400}
4401
4402static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4403 void *val, int bytes)
4404{
4405 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4406}
4407
4408static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4409 void *val, int bytes)
4410{
4411 return emulator_write_phys(vcpu, gpa, val, bytes);
4412}
4413
4414static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4415{
4416 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4417 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4418}
4419
4420static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 void *val, int bytes)
4422{
4423 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4424 return X86EMUL_IO_NEEDED;
4425}
4426
4427static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4428 void *val, int bytes)
4429{
f78146b0
AK		 4430 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4431
87da7e66 4432 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4433 return X86EMUL_CONTINUE;
4434}
4435
0fbe9b0b 4436static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4437 .read_write_prepare = read_prepare,
4438 .read_write_emulate = read_emulate,
4439 .read_write_mmio = vcpu_mmio_read,
4440 .read_write_exit_mmio = read_exit_mmio,
4441};
4442
0fbe9b0b 4443static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4444 .read_write_emulate = write_emulate,
4445 .read_write_mmio = write_mmio,
4446 .read_write_exit_mmio = write_exit_mmio,
4447 .write = true,
4448};
4449
22388a3c
XG		 4450static int emulator_read_write_onepage(unsigned long addr, void *val,
4451 unsigned int bytes,
4452 struct x86_exception *exception,
4453 struct kvm_vcpu *vcpu,
0fbe9b0b 4454 const struct read_write_emulator_ops *ops)
bbd9b64e 4455{
af7cc7d1
XG		 4456 gpa_t gpa;
4457 int handled, ret;
22388a3c 4458 bool write = ops->write;
f78146b0 4459 struct kvm_mmio_fragment *frag;
10589a46 4460
22388a3c 4461 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4462
af7cc7d1 4463 if (ret < 0)
bbd9b64e 4464 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4465
4466 /* For APIC access vmexit */
af7cc7d1 4467 if (ret)
bbd9b64e
CO		 4468 goto mmio;
4469
22388a3c 4470 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4471 return X86EMUL_CONTINUE;
4472
4473mmio:
4474 /*
4475 * Is this MMIO handled locally?
4476 */
22388a3c 4477 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4478 if (handled == bytes)
bbd9b64e 4479 return X86EMUL_CONTINUE;
bbd9b64e 4480
70252a10
AK		 4481 gpa += handled;
4482 bytes -= handled;
4483 val += handled;
4484
87da7e66
XG		 4485 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4486 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4487 frag->gpa = gpa;
4488 frag->data = val;
4489 frag->len = bytes;
f78146b0 4490 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4491}
4492
22388a3c
XG		 4493int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4494 void *val, unsigned int bytes,
4495 struct x86_exception *exception,
0fbe9b0b 4496 const struct read_write_emulator_ops *ops)
bbd9b64e 4497{
0f65dd70 4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4499 gpa_t gpa;
4500 int rc;
4501
4502 if (ops->read_write_prepare &&
4503 ops->read_write_prepare(vcpu, val, bytes))
4504 return X86EMUL_CONTINUE;
4505
4506 vcpu->mmio_nr_fragments = 0;
0f65dd70 4507
bbd9b64e
CO		 4508 /* Crossing a page boundary? */
4509 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4510 int now;
bbd9b64e
CO		 4511
4512 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4513 rc = emulator_read_write_onepage(addr, val, now, exception,
4514 vcpu, ops);
4515
bbd9b64e
CO		 4516 if (rc != X86EMUL_CONTINUE)
4517 return rc;
4518 addr += now;
4519 val += now;
4520 bytes -= now;
4521 }
22388a3c 4522
f78146b0
AK		 4523 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4524 vcpu, ops);
4525 if (rc != X86EMUL_CONTINUE)
4526 return rc;
4527
4528 if (!vcpu->mmio_nr_fragments)
4529 return rc;
4530
4531 gpa = vcpu->mmio_fragments[0].gpa;
4532
4533 vcpu->mmio_needed = 1;
4534 vcpu->mmio_cur_fragment = 0;
4535
87da7e66 4536 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4537 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4538 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4539 vcpu->run->mmio.phys_addr = gpa;
4540
4541 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4542}
4543
4544static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4545 unsigned long addr,
4546 void *val,
4547 unsigned int bytes,
4548 struct x86_exception *exception)
4549{
4550 return emulator_read_write(ctxt, addr, val, bytes,
4551 exception, &read_emultor);
4552}
4553
4554int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4555 unsigned long addr,
4556 const void *val,
4557 unsigned int bytes,
4558 struct x86_exception *exception)
4559{
4560 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4561 exception, &write_emultor);
bbd9b64e 4562}
bbd9b64e 4563
daea3e73
AK		 4564#define CMPXCHG_TYPE(t, ptr, old, new) \
4565 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4566
4567#ifdef CONFIG_X86_64
4568# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4569#else
4570# define CMPXCHG64(ptr, old, new) \
9749a6c0 4571 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4572#endif
4573
0f65dd70
AK		 4574static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4575 unsigned long addr,
bbd9b64e
CO		 4576 const void *old,
4577 const void *new,
4578 unsigned int bytes,
0f65dd70 4579 struct x86_exception *exception)
bbd9b64e 4580{
0f65dd70 4581 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4582 gpa_t gpa;
4583 struct page *page;
4584 char *kaddr;
4585 bool exchanged;
2bacc55c 4586
daea3e73
AK		 4587 /* guests cmpxchg8b have to be emulated atomically */
4588 if (bytes > 8 || (bytes & (bytes - 1)))
4589 goto emul_write;
10589a46 4590
daea3e73 4591 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4592
daea3e73
AK		 4593 if (gpa == UNMAPPED_GVA ||
4594 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4595 goto emul_write;
2bacc55c 4596
daea3e73
AK		 4597 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4598 goto emul_write;
72dc67a6 4599
daea3e73 4600 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4601 if (is_error_page(page))
c19b8bd6 4602 goto emul_write;
72dc67a6 4603
8fd75e12 4604 kaddr = kmap_atomic(page);
daea3e73
AK		 4605 kaddr += offset_in_page(gpa);
4606 switch (bytes) {
4607 case 1:
4608 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4609 break;
4610 case 2:
4611 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4612 break;
4613 case 4:
4614 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4615 break;
4616 case 8:
4617 exchanged = CMPXCHG64(kaddr, old, new);
4618 break;
4619 default:
4620 BUG();
2bacc55c 4621 }
8fd75e12 4622 kunmap_atomic(kaddr);
daea3e73
AK		 4623 kvm_release_page_dirty(page);
4624
4625 if (!exchanged)
4626 return X86EMUL_CMPXCHG_FAILED;
4627
d3714010 4628 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4629 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4630
4631 return X86EMUL_CONTINUE;
4a5f48f6 4632
3200f405 4633emul_write:
daea3e73 4634 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4635
0f65dd70 4636 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4637}
4638
cf8f70bf
GN		 4639static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4640{
4641 /* TODO: String I/O for in kernel device */
4642 int r;
4643
4644 if (vcpu->arch.pio.in)
4645 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4646 vcpu->arch.pio.size, pd);
4647 else
4648 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4649 vcpu->arch.pio.port, vcpu->arch.pio.size,
4650 pd);
4651 return r;
4652}
4653
6f6fbe98
XG		 4654static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4655 unsigned short port, void *val,
4656 unsigned int count, bool in)
cf8f70bf 4657{
cf8f70bf 4658 vcpu->arch.pio.port = port;
6f6fbe98 4659 vcpu->arch.pio.in = in;
7972995b 4660 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4661 vcpu->arch.pio.size = size;
4662
4663 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4664 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4665 return 1;
4666 }
4667
4668 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4669 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4670 vcpu->run->io.size = size;
4671 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4672 vcpu->run->io.count = count;
4673 vcpu->run->io.port = port;
4674
4675 return 0;
4676}
4677
6f6fbe98
XG		 4678static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4679 int size, unsigned short port, void *val,
4680 unsigned int count)
cf8f70bf 4681{
ca1d4a9e 4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4683 int ret;
ca1d4a9e 4684
6f6fbe98
XG		 4685 if (vcpu->arch.pio.count)
4686 goto data_avail;
cf8f70bf 4687
6f6fbe98
XG		 4688 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4689 if (ret) {
4690data_avail:
4691 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4692 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4693 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4694 return 1;
4695 }
4696
cf8f70bf
GN		 4697 return 0;
4698}
4699
6f6fbe98
XG		 4700static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4701 int size, unsigned short port,
4702 const void *val, unsigned int count)
4703{
4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4705
4706 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4707 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4708 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4709}
4710
bbd9b64e
CO		 4711static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4712{
4713 return kvm_x86_ops->get_segment_base(vcpu, seg);
4714}
4715
3cb16fe7 4716static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4717{
3cb16fe7 4718 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4719}
4720
f5f48ee1
SY		 4721int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4722{
4723 if (!need_emulate_wbinvd(vcpu))
4724 return X86EMUL_CONTINUE;
4725
4726 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4727 int cpu = get_cpu();
4728
4729 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4730 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4731 wbinvd_ipi, NULL, 1);
2eec7343 4732 put_cpu();
f5f48ee1 4733 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4734 } else
4735 wbinvd();
f5f48ee1
SY		 4736 return X86EMUL_CONTINUE;
4737}
4738EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4739
bcaf5cc5
AK		 4740static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4741{
4742 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4743}
4744
717746e3 4745int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4746{
16f8a6f9 4747 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4748}
4749
717746e3 4750int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4751{
338dbc97 4752
717746e3 4753 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4754}
4755
52a46617 4756static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4757{
52a46617 4758 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4759}
4760
717746e3 4761static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4762{
717746e3 4763 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4764 unsigned long value;
4765
4766 switch (cr) {
4767 case 0:
4768 value = kvm_read_cr0(vcpu);
4769 break;
4770 case 2:
4771 value = vcpu->arch.cr2;
4772 break;
4773 case 3:
9f8fe504 4774 value = kvm_read_cr3(vcpu);
52a46617
GN		 4775 break;
4776 case 4:
4777 value = kvm_read_cr4(vcpu);
4778 break;
4779 case 8:
4780 value = kvm_get_cr8(vcpu);
4781 break;
4782 default:
a737f256 4783 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4784 return 0;
4785 }
4786
4787 return value;
4788}
4789
717746e3 4790static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4791{
717746e3 4792 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4793 int res = 0;
4794
52a46617
GN		 4795 switch (cr) {
4796 case 0:
49a9b07e 4797 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4798 break;
4799 case 2:
4800 vcpu->arch.cr2 = val;
4801 break;
4802 case 3:
2390218b 4803 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4804 break;
4805 case 4:
a83b29c6 4806 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4807 break;
4808 case 8:
eea1cff9 4809 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4810 break;
4811 default:
a737f256 4812 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4813 res = -1;
52a46617 4814 }
0f12244f
GN		 4815
4816 return res;
52a46617
GN		 4817}
4818
717746e3 4819static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4820{
717746e3 4821 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4822}
4823
4bff1e86 4824static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4825{
4bff1e86 4826 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4827}
4828
4bff1e86 4829static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4830{
4bff1e86 4831 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4832}
4833
1ac9d0cf
AK		 4834static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4835{
4836 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4837}
4838
4839static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4840{
4841 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4842}
4843
4bff1e86
AK		 4844static unsigned long emulator_get_cached_segment_base(
4845 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4846{
4bff1e86 4847 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4848}
4849
1aa36616
AK		 4850static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4851 struct desc_struct *desc, u32 *base3,
4852 int seg)
2dafc6c2
GN		 4853{
4854 struct kvm_segment var;
4855
4bff1e86 4856 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4857 *selector = var.selector;
2dafc6c2 4858
378a8b09
GN		 4859 if (var.unusable) {
4860 memset(desc, 0, sizeof(*desc));
2dafc6c2 4861 return false;
378a8b09 4862 }
2dafc6c2
GN		 4863
4864 if (var.g)
4865 var.limit >>= 12;
4866 set_desc_limit(desc, var.limit);
4867 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4868#ifdef CONFIG_X86_64
4869 if (base3)
4870 *base3 = var.base >> 32;
4871#endif
2dafc6c2
GN		 4872 desc->type = var.type;
4873 desc->s = var.s;
4874 desc->dpl = var.dpl;
4875 desc->p = var.present;
4876 desc->avl = var.avl;
4877 desc->l = var.l;
4878 desc->d = var.db;
4879 desc->g = var.g;
4880
4881 return true;
4882}
4883
1aa36616
AK		 4884static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4885 struct desc_struct *desc, u32 base3,
4886 int seg)
2dafc6c2 4887{
4bff1e86 4888 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4889 struct kvm_segment var;
4890
1aa36616 4891 var.selector = selector;
2dafc6c2 4892 var.base = get_desc_base(desc);
5601d05b
GN		 4893#ifdef CONFIG_X86_64
4894 var.base |= ((u64)base3) << 32;
4895#endif
2dafc6c2
GN		 4896 var.limit = get_desc_limit(desc);
4897 if (desc->g)
4898 var.limit = (var.limit << 12) | 0xfff;
4899 var.type = desc->type;
2dafc6c2
GN		 4900 var.dpl = desc->dpl;
4901 var.db = desc->d;
4902 var.s = desc->s;
4903 var.l = desc->l;
4904 var.g = desc->g;
4905 var.avl = desc->avl;
4906 var.present = desc->p;
4907 var.unusable = !var.present;
4908 var.padding = 0;
4909
4910 kvm_set_segment(vcpu, &var, seg);
4911 return;
4912}
4913
717746e3
AK		 4914static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4915 u32 msr_index, u64 *pdata)
4916{
4917 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4918}
4919
4920static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4921 u32 msr_index, u64 data)
4922{
8fe8ab46
WA		 4923 struct msr_data msr;
4924
4925 msr.data = data;
4926 msr.index = msr_index;
4927 msr.host_initiated = false;
4928 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4929}
4930
67f4d428
NA		 4931static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4932 u32 pmc)
4933{
4934 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4935}
4936
222d21aa
AK		 4937static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4938 u32 pmc, u64 *pdata)
4939{
4940 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4941}
4942
6c3287f7
AK		 4943static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4944{
4945 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4946}
4947
5037f6f3
AK		 4948static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4949{
4950 preempt_disable();
5197b808 4951 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4952 /*
4953 * CR0.TS may reference the host fpu state, not the guest fpu state,
4954 * so it may be clear at this point.
4955 */
4956 clts();
4957}
4958
4959static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4960{
4961 preempt_enable();
4962}
4963
2953538e 4964static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4965 struct x86_instruction_info *info,
c4f035c6
AK		 4966 enum x86_intercept_stage stage)
4967{
2953538e 4968 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4969}
4970
0017f93a 4971static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4972 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4973{
0017f93a 4974 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4975}
4976
dd856efa
AK		 4977static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4978{
4979 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4980}
4981
4982static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4983{
4984 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4985}
4986
0225fb50 4987static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4988 .read_gpr = emulator_read_gpr,
4989 .write_gpr = emulator_write_gpr,
1871c602 4990 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4991 .write_std = kvm_write_guest_virt_system,
1871c602 4992 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4993 .read_emulated = emulator_read_emulated,
4994 .write_emulated = emulator_write_emulated,
4995 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4996 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4997 .pio_in_emulated = emulator_pio_in_emulated,
4998 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4999 .get_segment = emulator_get_segment,
5000 .set_segment = emulator_set_segment,
5951c442 5001 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5002 .get_gdt = emulator_get_gdt,
160ce1f1 5003 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5004 .set_gdt = emulator_set_gdt,
5005 .set_idt = emulator_set_idt,
52a46617
GN		 5006 .get_cr = emulator_get_cr,
5007 .set_cr = emulator_set_cr,
9c537244 5008 .cpl = emulator_get_cpl,
35aa5375
GN		 5009 .get_dr = emulator_get_dr,
5010 .set_dr = emulator_set_dr,
717746e3
AK		 5011 .set_msr = emulator_set_msr,
5012 .get_msr = emulator_get_msr,
67f4d428 5013 .check_pmc = emulator_check_pmc,
222d21aa 5014 .read_pmc = emulator_read_pmc,
6c3287f7 5015 .halt = emulator_halt,
bcaf5cc5 5016 .wbinvd = emulator_wbinvd,
d6aa1000 5017 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5018 .get_fpu = emulator_get_fpu,
5019 .put_fpu = emulator_put_fpu,
c4f035c6 5020 .intercept = emulator_intercept,
bdb42f5a 5021 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 5022};
5023
95cb2295
GN		 5024static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5025{
37ccdcbe 5026 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5027 /*
5028 * an sti; sti; sequence only disable interrupts for the first
5029 * instruction. So, if the last instruction, be it emulated or
5030 * not, left the system with the INT_STI flag enabled, it
5031 * means that the last instruction is an sti. We should not
5032 * leave the flag on in this case. The same goes for mov ss
5033 */
37ccdcbe
PB		 5034 if (int_shadow & mask)
5035 mask = 0;
6addfc42 5036 if (unlikely(int_shadow || mask)) {
95cb2295 5037 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5038 if (!mask)
5039 kvm_make_request(KVM_REQ_EVENT, vcpu);
5040 }
95cb2295
GN		 5041}
5042
ef54bcfe 5043static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5044{
5045 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5046 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5047 return kvm_propagate_fault(vcpu, &ctxt->exception);
5048
5049 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5050 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5051 ctxt->exception.error_code);
54b8486f 5052 else
da9cb575 5053 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5054 return false;
54b8486f
GN		 5055}
5056
8ec4722d
MG		 5057static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5058{
adf52235 5059 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5060 int cs_db, cs_l;
5061
8ec4722d
MG		 5062 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5063
adf52235
TY		 5064 ctxt->eflags = kvm_get_rflags(vcpu);
5065 ctxt->eip = kvm_rip_read(vcpu);
5066 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5067 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5068 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5069 cs_db ? X86EMUL_MODE_PROT32 :
5070 X86EMUL_MODE_PROT16;
5071 ctxt->guest_mode = is_guest_mode(vcpu);
5072
dd856efa 5073 init_decode_cache(ctxt);
7ae441ea 5074 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5075}
5076
71f9833b 5077int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5078{
9d74191a 5079 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5080 int ret;
5081
5082 init_emulate_ctxt(vcpu);
5083
9dac77fa
AK		 5084 ctxt->op_bytes = 2;
5085 ctxt->ad_bytes = 2;
5086 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5087 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5088
5089 if (ret != X86EMUL_CONTINUE)
5090 return EMULATE_FAIL;
5091
9dac77fa 5092 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5093 kvm_rip_write(vcpu, ctxt->eip);
5094 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5095
5096 if (irq == NMI_VECTOR)
7460fb4a 5097 vcpu->arch.nmi_pending = 0;
63995653
MG		 5098 else
5099 vcpu->arch.interrupt.pending = false;
5100
5101 return EMULATE_DONE;
5102}
5103EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5104
6d77dbfc
GN		 5105static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5106{
fc3a9157
JR		 5107 int r = EMULATE_DONE;
5108
6d77dbfc
GN		 5109 ++vcpu->stat.insn_emulation_fail;
5110 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5111 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5112 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5113 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5114 vcpu->run->internal.ndata = 0;
5115 r = EMULATE_FAIL;
5116 }
6d77dbfc 5117 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5118
5119 return r;
6d77dbfc
GN		 5120}
5121
93c05d3e 5122static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5123 bool write_fault_to_shadow_pgtable,
5124 int emulation_type)
a6f177ef 5125{
95b3cf69 5126 gpa_t gpa = cr2;
8e3d9d06 5127 pfn_t pfn;
a6f177ef 5128
991eebf9
GN		 5129 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5130 return false;
5131
95b3cf69
XG		 5132 if (!vcpu->arch.mmu.direct_map) {
5133 /*
5134 * Write permission should be allowed since only
5135 * write access need to be emulated.
5136 */
5137 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5138
95b3cf69
XG		 5139 /*
5140 * If the mapping is invalid in guest, let cpu retry
5141 * it to generate fault.
5142 */
5143 if (gpa == UNMAPPED_GVA)
5144 return true;
5145 }
a6f177ef 5146
8e3d9d06
XG		 5147 /*
5148 * Do not retry the unhandleable instruction if it faults on the
5149 * readonly host memory, otherwise it will goto a infinite loop:
5150 * retry instruction -> write #PF -> emulation fail -> retry
5151 * instruction -> ...
5152 */
5153 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5154
5155 /*
5156 * If the instruction failed on the error pfn, it can not be fixed,
5157 * report the error to userspace.
5158 */
5159 if (is_error_noslot_pfn(pfn))
5160 return false;
5161
5162 kvm_release_pfn_clean(pfn);
5163
5164 /* The instructions are well-emulated on direct mmu. */
5165 if (vcpu->arch.mmu.direct_map) {
5166 unsigned int indirect_shadow_pages;
5167
5168 spin_lock(&vcpu->kvm->mmu_lock);
5169 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5170 spin_unlock(&vcpu->kvm->mmu_lock);
5171
5172 if (indirect_shadow_pages)
5173 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5174
a6f177ef 5175 return true;
8e3d9d06 5176 }
a6f177ef 5177
95b3cf69
XG		 5178 /*
5179 * if emulation was due to access to shadowed page table
5180 * and it failed try to unshadow page and re-enter the
5181 * guest to let CPU execute the instruction.
5182 */
5183 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5184
5185 /*
5186 * If the access faults on its page table, it can not
5187 * be fixed by unprotecting shadow page and it should
5188 * be reported to userspace.
5189 */
5190 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5191}
5192
1cb3f3ae
XG		 5193static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5194 unsigned long cr2, int emulation_type)
5195{
5196 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5197 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5198
5199 last_retry_eip = vcpu->arch.last_retry_eip;
5200 last_retry_addr = vcpu->arch.last_retry_addr;
5201
5202 /*
5203 * If the emulation is caused by #PF and it is non-page_table
5204 * writing instruction, it means the VM-EXIT is caused by shadow
5205 * page protected, we can zap the shadow page and retry this
5206 * instruction directly.
5207 *
5208 * Note: if the guest uses a non-page-table modifying instruction
5209 * on the PDE that points to the instruction, then we will unmap
5210 * the instruction and go to an infinite loop. So, we cache the
5211 * last retried eip and the last fault address, if we meet the eip
5212 * and the address again, we can break out of the potential infinite
5213 * loop.
5214 */
5215 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5216
5217 if (!(emulation_type & EMULTYPE_RETRY))
5218 return false;
5219
5220 if (x86_page_table_writing_insn(ctxt))
5221 return false;
5222
5223 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5224 return false;
5225
5226 vcpu->arch.last_retry_eip = ctxt->eip;
5227 vcpu->arch.last_retry_addr = cr2;
5228
5229 if (!vcpu->arch.mmu.direct_map)
5230 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5231
22368028 5232 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5233
5234 return true;
5235}
5236
716d51ab
GN		 5237static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5238static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5239
4a1e10d5
PB		 5240static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5241 unsigned long *db)
5242{
5243 u32 dr6 = 0;
5244 int i;
5245 u32 enable, rwlen;
5246
5247 enable = dr7;
5248 rwlen = dr7 >> 16;
5249 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5250 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5251 dr6 |= (1 << i);
5252 return dr6;
5253}
5254
6addfc42 5255static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5256{
5257 struct kvm_run *kvm_run = vcpu->run;
5258
5259 /*
6addfc42
PB		 5260 * rflags is the old, "raw" value of the flags. The new value has
5261 * not been saved yet.
663f4c61
PB		 5262 *
5263 * This is correct even for TF set by the guest, because "the
5264 * processor will not generate this exception after the instruction
5265 * that sets the TF flag".
5266 */
663f4c61
PB		 5267 if (unlikely(rflags & X86_EFLAGS_TF)) {
5268 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5269 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5270 DR6_RTM;
663f4c61
PB		 5271 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5272 kvm_run->debug.arch.exception = DB_VECTOR;
5273 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5274 *r = EMULATE_USER_EXIT;
5275 } else {
5276 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5277 /*
5278 * "Certain debug exceptions may clear bit 0-3. The
5279 * remaining contents of the DR6 register are never
5280 * cleared by the processor".
5281 */
5282 vcpu->arch.dr6 &= ~15;
6f43ed01 5283 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5284 kvm_queue_exception(vcpu, DB_VECTOR);
5285 }
5286 }
5287}
5288
4a1e10d5
PB		 5289static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5290{
4a1e10d5
PB		 5291 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5292 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5293 struct kvm_run *kvm_run = vcpu->run;
5294 unsigned long eip = kvm_get_linear_rip(vcpu);
5295 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5296 vcpu->arch.guest_debug_dr7,
5297 vcpu->arch.eff_db);
5298
5299 if (dr6 != 0) {
6f43ed01 5300 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5301 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5302 kvm_run->debug.arch.exception = DB_VECTOR;
5303 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5304 *r = EMULATE_USER_EXIT;
5305 return true;
5306 }
5307 }
5308
4161a569
NA		 5309 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5310 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5311 unsigned long eip = kvm_get_linear_rip(vcpu);
5312 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5313 vcpu->arch.dr7,
5314 vcpu->arch.db);
5315
5316 if (dr6 != 0) {
5317 vcpu->arch.dr6 &= ~15;
6f43ed01 5318 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5319 kvm_queue_exception(vcpu, DB_VECTOR);
5320 *r = EMULATE_DONE;
5321 return true;
5322 }
5323 }
5324
5325 return false;
5326}
5327
51d8b661
AP		 5328int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5329 unsigned long cr2,
dc25e89e
AP		 5330 int emulation_type,
5331 void *insn,
5332 int insn_len)
bbd9b64e 5333{
95cb2295 5334 int r;
9d74191a 5335 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5336 bool writeback = true;
93c05d3e 5337 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5338
93c05d3e
XG		 5339 /*
5340 * Clear write_fault_to_shadow_pgtable here to ensure it is
5341 * never reused.
5342 */
5343 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5344 kvm_clear_exception_queue(vcpu);
8d7d8102 5345
571008da 5346 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5347 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5348
5349 /*
5350 * We will reenter on the same instruction since
5351 * we do not set complete_userspace_io. This does not
5352 * handle watchpoints yet, those would be handled in
5353 * the emulate_ops.
5354 */
5355 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5356 return r;
5357
9d74191a
TY		 5358 ctxt->interruptibility = 0;
5359 ctxt->have_exception = false;
e0ad0b47 5360 ctxt->exception.vector = -1;
9d74191a 5361 ctxt->perm_ok = false;
bbd9b64e 5362
b51e974f 5363 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5364
9d74191a 5365 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5366
e46479f8 5367 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5368 ++vcpu->stat.insn_emulation;
1d2887e2 5369 if (r != EMULATION_OK) {
4005996e
AK		 5370 if (emulation_type & EMULTYPE_TRAP_UD)
5371 return EMULATE_FAIL;
991eebf9
GN		 5372 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5373 emulation_type))
bbd9b64e 5374 return EMULATE_DONE;
6d77dbfc
GN		 5375 if (emulation_type & EMULTYPE_SKIP)
5376 return EMULATE_FAIL;
5377 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5378 }
5379 }
5380
ba8afb6b 5381 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5382 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5383 if (ctxt->eflags & X86_EFLAGS_RF)
5384 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5385 return EMULATE_DONE;
5386 }
5387
1cb3f3ae
XG		 5388 if (retry_instruction(ctxt, cr2, emulation_type))
5389 return EMULATE_DONE;
5390
7ae441ea 5391 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5392 changes registers values during IO operation */
7ae441ea
GN		 5393 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5394 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5395 emulator_invalidate_register_cache(ctxt);
7ae441ea 5396 }
4d2179e1 5397
5cd21917 5398restart:
9d74191a 5399 r = x86_emulate_insn(ctxt);
bbd9b64e 5400
775fde86
JR		 5401 if (r == EMULATION_INTERCEPTED)
5402 return EMULATE_DONE;
5403
d2ddd1c4 5404 if (r == EMULATION_FAILED) {
991eebf9
GN		 5405 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5406 emulation_type))
c3cd7ffa
GN		 5407 return EMULATE_DONE;
5408
6d77dbfc 5409 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5410 }
5411
9d74191a 5412 if (ctxt->have_exception) {
d2ddd1c4 5413 r = EMULATE_DONE;
ef54bcfe
PB		 5414 if (inject_emulated_exception(vcpu))
5415 return r;
d2ddd1c4 5416 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5417 if (!vcpu->arch.pio.in) {
5418 /* FIXME: return into emulator if single-stepping. */
3457e419 5419 vcpu->arch.pio.count = 0;
0912c977 5420 } else {
7ae441ea 5421 writeback = false;
716d51ab
GN		 5422 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5423 }
ac0a48c3 5424 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5425 } else if (vcpu->mmio_needed) {
5426 if (!vcpu->mmio_is_write)
5427 writeback = false;
ac0a48c3 5428 r = EMULATE_USER_EXIT;
716d51ab 5429 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5430 } else if (r == EMULATION_RESTART)
5cd21917 5431 goto restart;
d2ddd1c4
GN		 5432 else
5433 r = EMULATE_DONE;
f850e2e6 5434
7ae441ea 5435 if (writeback) {
6addfc42 5436 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5437 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5438 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5439 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5440 if (r == EMULATE_DONE)
6addfc42 5441 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5442 if (!ctxt->have_exception ||
5443 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5444 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5445
5446 /*
5447 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5448 * do nothing, and it will be requested again as soon as
5449 * the shadow expires. But we still need to check here,
5450 * because POPF has no interrupt shadow.
5451 */
5452 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5453 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5454 } else
5455 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5456
5457 return r;
de7d789a 5458}
51d8b661 5459EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5460
cf8f70bf 5461int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5462{
cf8f70bf 5463 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5464 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5465 size, port, &val, 1);
cf8f70bf 5466 /* do not return to emulator after return from userspace */
7972995b 5467 vcpu->arch.pio.count = 0;
de7d789a
CO		 5468 return ret;
5469}
cf8f70bf 5470EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5471
8cfdc000
ZA		 5472static void tsc_bad(void *info)
5473{
0a3aee0d 5474 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5475}
5476
5477static void tsc_khz_changed(void *data)
c8076604 5478{
8cfdc000
ZA		 5479 struct cpufreq_freqs *freq = data;
5480 unsigned long khz = 0;
5481
5482 if (data)
5483 khz = freq->new;
5484 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5485 khz = cpufreq_quick_get(raw_smp_processor_id());
5486 if (!khz)
5487 khz = tsc_khz;
0a3aee0d 5488 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5489}
5490
c8076604
GH		 5491static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5492 void *data)
5493{
5494 struct cpufreq_freqs *freq = data;
5495 struct kvm *kvm;
5496 struct kvm_vcpu *vcpu;
5497 int i, send_ipi = 0;
5498
8cfdc000
ZA		 5499 /*
5500 * We allow guests to temporarily run on slowing clocks,
5501 * provided we notify them after, or to run on accelerating
5502 * clocks, provided we notify them before. Thus time never
5503 * goes backwards.
5504 *
5505 * However, we have a problem. We can't atomically update
5506 * the frequency of a given CPU from this function; it is
5507 * merely a notifier, which can be called from any CPU.
5508 * Changing the TSC frequency at arbitrary points in time
5509 * requires a recomputation of local variables related to
5510 * the TSC for each VCPU. We must flag these local variables
5511 * to be updated and be sure the update takes place with the
5512 * new frequency before any guests proceed.
5513 *
5514 * Unfortunately, the combination of hotplug CPU and frequency
5515 * change creates an intractable locking scenario; the order
5516 * of when these callouts happen is undefined with respect to
5517 * CPU hotplug, and they can race with each other. As such,
5518 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5519 * undefined; you can actually have a CPU frequency change take
5520 * place in between the computation of X and the setting of the
5521 * variable. To protect against this problem, all updates of
5522 * the per_cpu tsc_khz variable are done in an interrupt
5523 * protected IPI, and all callers wishing to update the value
5524 * must wait for a synchronous IPI to complete (which is trivial
5525 * if the caller is on the CPU already). This establishes the
5526 * necessary total order on variable updates.
5527 *
5528 * Note that because a guest time update may take place
5529 * anytime after the setting of the VCPU's request bit, the
5530 * correct TSC value must be set before the request. However,
5531 * to ensure the update actually makes it to any guest which
5532 * starts running in hardware virtualization between the set
5533 * and the acquisition of the spinlock, we must also ping the
5534 * CPU after setting the request bit.
5535 *
5536 */
5537
c8076604
GH		 5538 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5539 return 0;
5540 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5541 return 0;
8cfdc000
ZA		 5542
5543 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5544
2f303b74 5545 spin_lock(&kvm_lock);
c8076604 5546 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5547 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5548 if (vcpu->cpu != freq->cpu)
5549 continue;
c285545f 5550 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5551 if (vcpu->cpu != smp_processor_id())
8cfdc000 5552 send_ipi = 1;
c8076604
GH		 5553 }
5554 }
2f303b74 5555 spin_unlock(&kvm_lock);
c8076604
GH		 5556
5557 if (freq->old < freq->new && send_ipi) {
5558 /*
5559 * We upscale the frequency. Must make the guest
5560 * doesn't see old kvmclock values while running with
5561 * the new frequency, otherwise we risk the guest sees
5562 * time go backwards.
5563 *
5564 * In case we update the frequency for another cpu
5565 * (which might be in guest context) send an interrupt
5566 * to kick the cpu out of guest context. Next time
5567 * guest context is entered kvmclock will be updated,
5568 * so the guest will not see stale values.
5569 */
8cfdc000 5570 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5571 }
5572 return 0;
5573}
5574
5575static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5576 .notifier_call = kvmclock_cpufreq_notifier
5577};
5578
5579static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5580 unsigned long action, void *hcpu)
5581{
5582 unsigned int cpu = (unsigned long)hcpu;
5583
5584 switch (action) {
5585 case CPU_ONLINE:
5586 case CPU_DOWN_FAILED:
5587 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5588 break;
5589 case CPU_DOWN_PREPARE:
5590 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5591 break;
5592 }
5593 return NOTIFY_OK;
5594}
5595
5596static struct notifier_block kvmclock_cpu_notifier_block = {
5597 .notifier_call = kvmclock_cpu_notifier,
5598 .priority = -INT_MAX
c8076604
GH		 5599};
5600
b820cc0c
ZA		 5601static void kvm_timer_init(void)
5602{
5603 int cpu;
5604
c285545f 5605 max_tsc_khz = tsc_khz;
460dd42e
SB		 5606
5607 cpu_notifier_register_begin();
b820cc0c 5608 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5609#ifdef CONFIG_CPU_FREQ
5610 struct cpufreq_policy policy;
5611 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5612 cpu = get_cpu();
5613 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5614 if (policy.cpuinfo.max_freq)
5615 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5616 put_cpu();
c285545f 5617#endif
b820cc0c
ZA		 5618 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5619 CPUFREQ_TRANSITION_NOTIFIER);
5620 }
c285545f 5621 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5622 for_each_online_cpu(cpu)
5623 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5624
5625 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5626 cpu_notifier_register_done();
5627
b820cc0c
ZA		 5628}
5629
ff9d07a0
ZY		 5630static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5631
f5132b01 5632int kvm_is_in_guest(void)
ff9d07a0 5633{
086c9855 5634 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5635}
5636
5637static int kvm_is_user_mode(void)
5638{
5639 int user_mode = 3;
dcf46b94 5640
086c9855
AS		 5641 if (__this_cpu_read(current_vcpu))
5642 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5643
ff9d07a0
ZY		 5644 return user_mode != 0;
5645}
5646
5647static unsigned long kvm_get_guest_ip(void)
5648{
5649 unsigned long ip = 0;
dcf46b94 5650
086c9855
AS		 5651 if (__this_cpu_read(current_vcpu))
5652 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5653
ff9d07a0
ZY		 5654 return ip;
5655}
5656
5657static struct perf_guest_info_callbacks kvm_guest_cbs = {
5658 .is_in_guest = kvm_is_in_guest,
5659 .is_user_mode = kvm_is_user_mode,
5660 .get_guest_ip = kvm_get_guest_ip,
5661};
5662
5663void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5664{
086c9855 5665 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5666}
5667EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5668
5669void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5670{
086c9855 5671 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5672}
5673EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5674
ce88decf
XG		 5675static void kvm_set_mmio_spte_mask(void)
5676{
5677 u64 mask;
5678 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5679
5680 /*
5681 * Set the reserved bits and the present bit of an paging-structure
5682 * entry to generate page fault with PFER.RSV = 1.
5683 */
885032b9 5684 /* Mask the reserved physical address bits. */
d1431483 5685 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5686
5687 /* Bit 62 is always reserved for 32bit host. */
5688 mask |= 0x3ull << 62;
5689
5690 /* Set the present bit. */
ce88decf
XG		 5691 mask |= 1ull;
5692
5693#ifdef CONFIG_X86_64
5694 /*
5695 * If reserved bit is not supported, clear the present bit to disable
5696 * mmio page fault.
5697 */
5698 if (maxphyaddr == 52)
5699 mask &= ~1ull;
5700#endif
5701
5702 kvm_mmu_set_mmio_spte_mask(mask);
5703}
5704
16e8d74d
MT		 5705#ifdef CONFIG_X86_64
5706static void pvclock_gtod_update_fn(struct work_struct *work)
5707{
d828199e
MT		 5708 struct kvm *kvm;
5709
5710 struct kvm_vcpu *vcpu;
5711 int i;
5712
2f303b74 5713 spin_lock(&kvm_lock);
d828199e
MT		 5714 list_for_each_entry(kvm, &vm_list, vm_list)
5715 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5716 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5717 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5718 spin_unlock(&kvm_lock);
16e8d74d
MT		 5719}
5720
5721static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5722
5723/*
5724 * Notification about pvclock gtod data update.
5725 */
5726static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5727 void *priv)
5728{
5729 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5730 struct timekeeper *tk = priv;
5731
5732 update_pvclock_gtod(tk);
5733
5734 /* disable master clock if host does not trust, or does not
5735 * use, TSC clocksource
5736 */
5737 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5738 atomic_read(&kvm_guest_has_master_clock) != 0)
5739 queue_work(system_long_wq, &pvclock_gtod_work);
5740
5741 return 0;
5742}
5743
5744static struct notifier_block pvclock_gtod_notifier = {
5745 .notifier_call = pvclock_gtod_notify,
5746};
5747#endif
5748
f8c16bba 5749int kvm_arch_init(void *opaque)
043405e1 5750{
b820cc0c 5751 int r;
6b61edf7 5752 struct kvm_x86_ops *ops = opaque;
f8c16bba 5753
f8c16bba
ZX		 5754 if (kvm_x86_ops) {
5755 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5756 r = -EEXIST;
5757 goto out;
f8c16bba
ZX		 5758 }
5759
5760 if (!ops->cpu_has_kvm_support()) {
5761 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5762 r = -EOPNOTSUPP;
5763 goto out;
f8c16bba
ZX		 5764 }
5765 if (ops->disabled_by_bios()) {
5766 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5767 r = -EOPNOTSUPP;
5768 goto out;
f8c16bba
ZX		 5769 }
5770
013f6a5d
MT		 5771 r = -ENOMEM;
5772 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5773 if (!shared_msrs) {
5774 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5775 goto out;
5776 }
5777
97db56ce
AK		 5778 r = kvm_mmu_module_init();
5779 if (r)
013f6a5d 5780 goto out_free_percpu;
97db56ce 5781
ce88decf 5782 kvm_set_mmio_spte_mask();
97db56ce 5783
f8c16bba 5784 kvm_x86_ops = ops;
920c8377
PB		 5785 kvm_init_msr_list();
5786
7b52345e 5787 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5788 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5789
b820cc0c 5790 kvm_timer_init();
c8076604 5791
ff9d07a0
ZY		 5792 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5793
2acf923e
DC		 5794 if (cpu_has_xsave)
5795 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5796
c5cc421b 5797 kvm_lapic_init();
16e8d74d
MT		 5798#ifdef CONFIG_X86_64
5799 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5800#endif
5801
f8c16bba 5802 return 0;
56c6d28a 5803
013f6a5d
MT		 5804out_free_percpu:
5805 free_percpu(shared_msrs);
56c6d28a 5806out:
56c6d28a 5807 return r;
043405e1 5808}
8776e519 5809
f8c16bba
ZX		 5810void kvm_arch_exit(void)
5811{
ff9d07a0
ZY		 5812 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5813
888d256e
JK		 5814 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5815 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5816 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5817 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5818#ifdef CONFIG_X86_64
5819 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5820#endif
f8c16bba 5821 kvm_x86_ops = NULL;
56c6d28a 5822 kvm_mmu_module_exit();
013f6a5d 5823 free_percpu(shared_msrs);
56c6d28a 5824}
f8c16bba 5825
8776e519
HB		 5826int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5827{
5828 ++vcpu->stat.halt_exits;
5829 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5830 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5831 return 1;
5832 } else {
5833 vcpu->run->exit_reason = KVM_EXIT_HLT;
5834 return 0;
5835 }
5836}
5837EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5838
55cd8e5a
GN		 5839int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5840{
5841 u64 param, ingpa, outgpa, ret;
5842 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5843 bool fast, longmode;
55cd8e5a
GN		 5844
5845 /*
5846 * hypercall generates UD from non zero cpl and real mode
5847 * per HYPER-V spec
5848 */
3eeb3288 5849 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5850 kvm_queue_exception(vcpu, UD_VECTOR);
5851 return 0;
5852 }
5853
a449c7aa 5854 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5855
5856 if (!longmode) {
ccd46936
GN		 5857 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5858 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5859 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5860 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5861 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5862 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5863 }
5864#ifdef CONFIG_X86_64
5865 else {
5866 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5867 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5868 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5869 }
5870#endif
5871
5872 code = param & 0xffff;
5873 fast = (param >> 16) & 0x1;
5874 rep_cnt = (param >> 32) & 0xfff;
5875 rep_idx = (param >> 48) & 0xfff;
5876
5877 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5878
c25bc163
GN		 5879 switch (code) {
5880 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5881 kvm_vcpu_on_spin(vcpu);
5882 break;
5883 default:
5884 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5885 break;
5886 }
55cd8e5a
GN		 5887
5888 ret = res | (((u64)rep_done & 0xfff) << 32);
5889 if (longmode) {
5890 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5891 } else {
5892 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5893 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5894 }
5895
5896 return 1;
5897}
5898
6aef266c
SV		 5899/*
5900 * kvm_pv_kick_cpu_op: Kick a vcpu.
5901 *
5902 * @apicid - apicid of vcpu to be kicked.
5903 */
5904static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5905{
24d2166b 5906 struct kvm_lapic_irq lapic_irq;
6aef266c 5907
24d2166b
R		 5908 lapic_irq.shorthand = 0;
5909 lapic_irq.dest_mode = 0;
5910 lapic_irq.dest_id = apicid;
6aef266c 5911
24d2166b
R		 5912 lapic_irq.delivery_mode = APIC_DM_REMRD;
5913 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5914}
5915
8776e519
HB		 5916int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5917{
5918 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5919 int op_64_bit, r = 1;
8776e519 5920
55cd8e5a
GN		 5921 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5922 return kvm_hv_hypercall(vcpu);
5923
5fdbf976
MT		 5924 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5925 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5926 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5927 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5928 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5929
229456fc 5930 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5931
a449c7aa
NA		 5932 op_64_bit = is_64_bit_mode(vcpu);
5933 if (!op_64_bit) {
8776e519
HB		 5934 nr &= 0xFFFFFFFF;
5935 a0 &= 0xFFFFFFFF;
5936 a1 &= 0xFFFFFFFF;
5937 a2 &= 0xFFFFFFFF;
5938 a3 &= 0xFFFFFFFF;
5939 }
5940
07708c4a
JK		 5941 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5942 ret = -KVM_EPERM;
5943 goto out;
5944 }
5945
8776e519 5946 switch (nr) {
b93463aa
AK		 5947 case KVM_HC_VAPIC_POLL_IRQ:
5948 ret = 0;
5949 break;
6aef266c
SV		 5950 case KVM_HC_KICK_CPU:
5951 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5952 ret = 0;
5953 break;
8776e519
HB		 5954 default:
5955 ret = -KVM_ENOSYS;
5956 break;
5957 }
07708c4a 5958out:
a449c7aa
NA		 5959 if (!op_64_bit)
5960 ret = (u32)ret;
5fdbf976 5961 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5962 ++vcpu->stat.hypercalls;
2f333bcb 5963 return r;
8776e519
HB		 5964}
5965EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5966
b6785def 5967static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5968{
d6aa1000 5969 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5970 char instruction[3];
5fdbf976 5971 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5972
8776e519 5973 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5974
9d74191a 5975 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5976}
5977
b6c7a5dc
HB		 5978/*
5979 * Check if userspace requested an interrupt window, and that the
5980 * interrupt window is open.
5981 *
5982 * No need to exit to userspace if we already have an interrupt queued.
5983 */
851ba692 5984static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5985{
8061823a 5986 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5987 vcpu->run->request_interrupt_window &&
5df56646 5988 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5989}
5990
851ba692 5991static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5992{
851ba692
AK		 5993 struct kvm_run *kvm_run = vcpu->run;
5994
91586a3b 5995 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5996 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5997 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5998 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5999 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6000 else
b6c7a5dc 6001 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6002 kvm_arch_interrupt_allowed(vcpu) &&
6003 !kvm_cpu_has_interrupt(vcpu) &&
6004 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6005}
6006
95ba8273
GN		 6007static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6008{
6009 int max_irr, tpr;
6010
6011 if (!kvm_x86_ops->update_cr8_intercept)
6012 return;
6013
88c808fd
AK		 6014 if (!vcpu->arch.apic)
6015 return;
6016
8db3baa2
GN		 6017 if (!vcpu->arch.apic->vapic_addr)
6018 max_irr = kvm_lapic_find_highest_irr(vcpu);
6019 else
6020 max_irr = -1;
95ba8273
GN		 6021
6022 if (max_irr != -1)
6023 max_irr >>= 4;
6024
6025 tpr = kvm_lapic_get_cr8(vcpu);
6026
6027 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6028}
6029
b6b8a145 6030static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6031{
b6b8a145
JK		 6032 int r;
6033
95ba8273 6034 /* try to reinject previous events if any */
b59bb7bd 6035 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6036 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6037 vcpu->arch.exception.has_error_code,
6038 vcpu->arch.exception.error_code);
d6e8c854
NA		 6039
6040 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6041 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6042 X86_EFLAGS_RF);
6043
6bdf0662
NA		 6044 if (vcpu->arch.exception.nr == DB_VECTOR &&
6045 (vcpu->arch.dr7 & DR7_GD)) {
6046 vcpu->arch.dr7 &= ~DR7_GD;
6047 kvm_update_dr7(vcpu);
6048 }
6049
b59bb7bd
GN		 6050 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6051 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6052 vcpu->arch.exception.error_code,
6053 vcpu->arch.exception.reinject);
b6b8a145 6054 return 0;
b59bb7bd
GN		 6055 }
6056
95ba8273
GN		 6057 if (vcpu->arch.nmi_injected) {
6058 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6059 return 0;
95ba8273
GN		 6060 }
6061
6062 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6063 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6064 return 0;
6065 }
6066
6067 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6068 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6069 if (r != 0)
6070 return r;
95ba8273
GN		 6071 }
6072
6073 /* try to inject new event if pending */
6074 if (vcpu->arch.nmi_pending) {
6075 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6076 --vcpu->arch.nmi_pending;
95ba8273
GN		 6077 vcpu->arch.nmi_injected = true;
6078 kvm_x86_ops->set_nmi(vcpu);
6079 }
c7c9c56c 6080 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6081 /*
6082 * Because interrupts can be injected asynchronously, we are
6083 * calling check_nested_events again here to avoid a race condition.
6084 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6085 * proposal and current concerns. Perhaps we should be setting
6086 * KVM_REQ_EVENT only on certain events and not unconditionally?
6087 */
6088 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6089 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6090 if (r != 0)
6091 return r;
6092 }
95ba8273 6093 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6094 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6095 false);
6096 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6097 }
6098 }
b6b8a145 6099 return 0;
95ba8273
GN		 6100}
6101
7460fb4a
AK		 6102static void process_nmi(struct kvm_vcpu *vcpu)
6103{
6104 unsigned limit = 2;
6105
6106 /*
6107 * x86 is limited to one NMI running, and one NMI pending after it.
6108 * If an NMI is already in progress, limit further NMIs to just one.
6109 * Otherwise, allow two (and we'll inject the first one immediately).
6110 */
6111 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6112 limit = 1;
6113
6114 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6115 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6116 kvm_make_request(KVM_REQ_EVENT, vcpu);
6117}
6118
3d81bc7e 6119static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6120{
6121 u64 eoi_exit_bitmap[4];
cf9e65b7 6122 u32 tmr[8];
c7c9c56c 6123
3d81bc7e
YZ		 6124 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6125 return;
c7c9c56c
YZ		 6126
6127 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6128 memset(tmr, 0, 32);
c7c9c56c 6129
cf9e65b7 6130 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6131 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6132 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6133}
6134
a70656b6
RK		 6135static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6136{
6137 ++vcpu->stat.tlb_flush;
6138 kvm_x86_ops->tlb_flush(vcpu);
6139}
6140
4256f43f
TC		 6141void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6142{
c24ae0dc
TC		 6143 struct page *page = NULL;
6144
f439ed27
PB		 6145 if (!irqchip_in_kernel(vcpu->kvm))
6146 return;
6147
4256f43f
TC		 6148 if (!kvm_x86_ops->set_apic_access_page_addr)
6149 return;
6150
c24ae0dc
TC		 6151 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6152 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6153
6154 /*
6155 * Do not pin apic access page in memory, the MMU notifier
6156 * will call us again if it is migrated or swapped out.
6157 */
6158 put_page(page);
4256f43f
TC		 6159}
6160EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6161
fe71557a
TC		 6162void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6163 unsigned long address)
6164{
c24ae0dc
TC		 6165 /*
6166 * The physical address of apic access page is stored in the VMCS.
6167 * Update it when it becomes invalid.
6168 */
6169 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6170 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6171}
6172
9357d939
TY		 6173/*
6174 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6175 * exiting to the userspace. Otherwise, the value will be returned to the
6176 * userspace.
6177 */
851ba692 6178static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6179{
6180 int r;
6a8b1d13 6181 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6182 vcpu->run->request_interrupt_window;
730dca42 6183 bool req_immediate_exit = false;
b6c7a5dc 6184
3e007509 6185 if (vcpu->requests) {
a8eeb04a 6186 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6187 kvm_mmu_unload(vcpu);
a8eeb04a 6188 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6189 __kvm_migrate_timers(vcpu);
d828199e
MT		 6190 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6191 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6192 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6193 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6194 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6195 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6196 if (unlikely(r))
6197 goto out;
6198 }
a8eeb04a 6199 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6200 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6201 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6202 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6203 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6204 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6205 r = 0;
6206 goto out;
6207 }
a8eeb04a 6208 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6209 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6210 r = 0;
6211 goto out;
6212 }
a8eeb04a 6213 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6214 vcpu->fpu_active = 0;
6215 kvm_x86_ops->fpu_deactivate(vcpu);
6216 }
af585b92
GN		 6217 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6218 /* Page is swapped out. Do synthetic halt */
6219 vcpu->arch.apf.halted = true;
6220 r = 1;
6221 goto out;
6222 }
c9aaa895
GC		 6223 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6224 record_steal_time(vcpu);
7460fb4a
AK		 6225 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6226 process_nmi(vcpu);
f5132b01
GN		 6227 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6228 kvm_handle_pmu_event(vcpu);
6229 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6230 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6231 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6232 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6233 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6234 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6235 }
b93463aa 6236
b463a6f7 6237 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6238 kvm_apic_accept_events(vcpu);
6239 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6240 r = 1;
6241 goto out;
6242 }
6243
b6b8a145
JK		 6244 if (inject_pending_event(vcpu, req_int_win) != 0)
6245 req_immediate_exit = true;
b463a6f7 6246 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6247 else if (vcpu->arch.nmi_pending)
c9a7953f 6248 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6249 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6250 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6251
6252 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6253 /*
6254 * Update architecture specific hints for APIC
6255 * virtual interrupt delivery.
6256 */
6257 if (kvm_x86_ops->hwapic_irr_update)
6258 kvm_x86_ops->hwapic_irr_update(vcpu,
6259 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6260 update_cr8_intercept(vcpu);
6261 kvm_lapic_sync_to_vapic(vcpu);
6262 }
6263 }
6264
d8368af8
AK		 6265 r = kvm_mmu_reload(vcpu);
6266 if (unlikely(r)) {
d905c069 6267 goto cancel_injection;
d8368af8
AK		 6268 }
6269
b6c7a5dc
HB		 6270 preempt_disable();
6271
6272 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6273 if (vcpu->fpu_active)
6274 kvm_load_guest_fpu(vcpu);
2acf923e 6275 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6276
6b7e2d09
XG		 6277 vcpu->mode = IN_GUEST_MODE;
6278
01b71917
MT		 6279 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6280
6b7e2d09
XG		 6281 /* We should set ->mode before check ->requests,
6282 * see the comment in make_all_cpus_request.
6283 */
01b71917 6284 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6285
d94e1dc9 6286 local_irq_disable();
32f88400 6287
6b7e2d09 6288 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6289 || need_resched() || signal_pending(current)) {
6b7e2d09 6290 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6291 smp_wmb();
6c142801
AK		 6292 local_irq_enable();
6293 preempt_enable();
01b71917 6294 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6295 r = 1;
d905c069 6296 goto cancel_injection;
6c142801
AK		 6297 }
6298
d6185f20
NHE		 6299 if (req_immediate_exit)
6300 smp_send_reschedule(vcpu->cpu);
6301
b6c7a5dc
HB		 6302 kvm_guest_enter();
6303
42dbaa5a 6304 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6305 set_debugreg(0, 7);
6306 set_debugreg(vcpu->arch.eff_db[0], 0);
6307 set_debugreg(vcpu->arch.eff_db[1], 1);
6308 set_debugreg(vcpu->arch.eff_db[2], 2);
6309 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6310 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6311 }
b6c7a5dc 6312
229456fc 6313 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6314 kvm_x86_ops->run(vcpu);
b6c7a5dc 6315
c77fb5fe
PB		 6316 /*
6317 * Do this here before restoring debug registers on the host. And
6318 * since we do this before handling the vmexit, a DR access vmexit
6319 * can (a) read the correct value of the debug registers, (b) set
6320 * KVM_DEBUGREG_WONT_EXIT again.
6321 */
6322 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6323 int i;
6324
6325 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6326 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6327 for (i = 0; i < KVM_NR_DB_REGS; i++)
6328 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6329 }
6330
24f1e32c
FW		 6331 /*
6332 * If the guest has used debug registers, at least dr7
6333 * will be disabled while returning to the host.
6334 * If we don't have active breakpoints in the host, we don't
6335 * care about the messed up debug address registers. But if
6336 * we have some of them active, restore the old state.
6337 */
59d8eb53 6338 if (hw_breakpoint_active())
24f1e32c 6339 hw_breakpoint_restore();
42dbaa5a 6340
886b470c
MT		 6341 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6342 native_read_tsc());
1d5f066e 6343
6b7e2d09 6344 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6345 smp_wmb();
a547c6db
YZ		 6346
6347 /* Interrupt is enabled by handle_external_intr() */
6348 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6349
6350 ++vcpu->stat.exits;
6351
6352 /*
6353 * We must have an instruction between local_irq_enable() and
6354 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6355 * the interrupt shadow. The stat.exits increment will do nicely.
6356 * But we need to prevent reordering, hence this barrier():
6357 */
6358 barrier();
6359
6360 kvm_guest_exit();
6361
6362 preempt_enable();
6363
f656ce01 6364 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6365
b6c7a5dc
HB		 6366 /*
6367 * Profile KVM exit RIPs:
6368 */
6369 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6370 unsigned long rip = kvm_rip_read(vcpu);
6371 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6372 }
6373
cc578287
ZA		 6374 if (unlikely(vcpu->arch.tsc_always_catchup))
6375 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6376
5cfb1d5a
MT		 6377 if (vcpu->arch.apic_attention)
6378 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6379
851ba692 6380 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6381 return r;
6382
6383cancel_injection:
6384 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6385 if (unlikely(vcpu->arch.apic_attention))
6386 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6387out:
6388 return r;
6389}
b6c7a5dc 6390
09cec754 6391
851ba692 6392static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6393{
6394 int r;
f656ce01 6395 struct kvm *kvm = vcpu->kvm;
d7690175 6396
f656ce01 6397 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6398
6399 r = 1;
6400 while (r > 0) {
af585b92
GN		 6401 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6402 !vcpu->arch.apf.halted)
851ba692 6403 r = vcpu_enter_guest(vcpu);
d7690175 6404 else {
f656ce01 6405 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6406 kvm_vcpu_block(vcpu);
f656ce01 6407 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6408 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6409 kvm_apic_accept_events(vcpu);
09cec754
GN		 6410 switch(vcpu->arch.mp_state) {
6411 case KVM_MP_STATE_HALTED:
6aef266c 6412 vcpu->arch.pv.pv_unhalted = false;
d7690175 6413 vcpu->arch.mp_state =
09cec754
GN		 6414 KVM_MP_STATE_RUNNABLE;
6415 case KVM_MP_STATE_RUNNABLE:
af585b92 6416 vcpu->arch.apf.halted = false;
09cec754 6417 break;
66450a21
JK		 6418 case KVM_MP_STATE_INIT_RECEIVED:
6419 break;
09cec754
GN		 6420 default:
6421 r = -EINTR;
6422 break;
6423 }
6424 }
d7690175
MT		 6425 }
6426
09cec754
GN		 6427 if (r <= 0)
6428 break;
6429
6430 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6431 if (kvm_cpu_has_pending_timer(vcpu))
6432 kvm_inject_pending_timer_irqs(vcpu);
6433
851ba692 6434 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6435 r = -EINTR;
851ba692 6436 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6437 ++vcpu->stat.request_irq_exits;
6438 }
af585b92
GN		 6439
6440 kvm_check_async_pf_completion(vcpu);
6441
09cec754
GN		 6442 if (signal_pending(current)) {
6443 r = -EINTR;
851ba692 6444 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6445 ++vcpu->stat.signal_exits;
6446 }
6447 if (need_resched()) {
f656ce01 6448 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6449 cond_resched();
f656ce01 6450 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6451 }
b6c7a5dc
HB		 6452 }
6453
f656ce01 6454 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6455
6456 return r;
6457}
6458
716d51ab
GN		 6459static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6460{
6461 int r;
6462 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6463 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6464 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6465 if (r != EMULATE_DONE)
6466 return 0;
6467 return 1;
6468}
6469
6470static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6471{
6472 BUG_ON(!vcpu->arch.pio.count);
6473
6474 return complete_emulated_io(vcpu);
6475}
6476
f78146b0
AK		 6477/*
6478 * Implements the following, as a state machine:
6479 *
6480 * read:
6481 * for each fragment
87da7e66
XG		 6482 * for each mmio piece in the fragment
6483 * write gpa, len
6484 * exit
6485 * copy data
f78146b0
AK		 6486 * execute insn
6487 *
6488 * write:
6489 * for each fragment
87da7e66
XG		 6490 * for each mmio piece in the fragment
6491 * write gpa, len
6492 * copy data
6493 * exit
f78146b0 6494 */
716d51ab 6495static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6496{
6497 struct kvm_run *run = vcpu->run;
f78146b0 6498 struct kvm_mmio_fragment *frag;
87da7e66 6499 unsigned len;
5287f194 6500
716d51ab 6501 BUG_ON(!vcpu->mmio_needed);
5287f194 6502
716d51ab 6503 /* Complete previous fragment */
87da7e66
XG		 6504 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6505 len = min(8u, frag->len);
716d51ab 6506 if (!vcpu->mmio_is_write)
87da7e66
XG		 6507 memcpy(frag->data, run->mmio.data, len);
6508
6509 if (frag->len <= 8) {
6510 /* Switch to the next fragment. */
6511 frag++;
6512 vcpu->mmio_cur_fragment++;
6513 } else {
6514 /* Go forward to the next mmio piece. */
6515 frag->data += len;
6516 frag->gpa += len;
6517 frag->len -= len;
6518 }
6519
a08d3b3b 6520 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6521 vcpu->mmio_needed = 0;
0912c977
PB		 6522
6523 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6524 if (vcpu->mmio_is_write)
716d51ab
GN		 6525 return 1;
6526 vcpu->mmio_read_completed = 1;
6527 return complete_emulated_io(vcpu);
6528 }
87da7e66 6529
716d51ab
GN		 6530 run->exit_reason = KVM_EXIT_MMIO;
6531 run->mmio.phys_addr = frag->gpa;
6532 if (vcpu->mmio_is_write)
87da7e66
XG		 6533 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6534 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6535 run->mmio.is_write = vcpu->mmio_is_write;
6536 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6537 return 0;
5287f194
AK		 6538}
6539
716d51ab 6540
b6c7a5dc
HB		 6541int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6542{
6543 int r;
6544 sigset_t sigsaved;
6545
e5c30142
AK		 6546 if (!tsk_used_math(current) && init_fpu(current))
6547 return -ENOMEM;
6548
ac9f6dc0
AK		 6549 if (vcpu->sigset_active)
6550 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6551
a4535290 6552 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6553 kvm_vcpu_block(vcpu);
66450a21 6554 kvm_apic_accept_events(vcpu);
d7690175 6555 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6556 r = -EAGAIN;
6557 goto out;
b6c7a5dc
HB		 6558 }
6559
b6c7a5dc 6560 /* re-sync apic's tpr */
eea1cff9
AP		 6561 if (!irqchip_in_kernel(vcpu->kvm)) {
6562 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6563 r = -EINVAL;
6564 goto out;
6565 }
6566 }
b6c7a5dc 6567
716d51ab
GN		 6568 if (unlikely(vcpu->arch.complete_userspace_io)) {
6569 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6570 vcpu->arch.complete_userspace_io = NULL;
6571 r = cui(vcpu);
6572 if (r <= 0)
6573 goto out;
6574 } else
6575 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6576
851ba692 6577 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6578
6579out:
f1d86e46 6580 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6581 if (vcpu->sigset_active)
6582 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6583
b6c7a5dc
HB		 6584 return r;
6585}
6586
6587int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6588{
7ae441ea
GN		 6589 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6590 /*
6591 * We are here if userspace calls get_regs() in the middle of
6592 * instruction emulation. Registers state needs to be copied
4a969980 6593 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6594 * that usually, but some bad designed PV devices (vmware
6595 * backdoor interface) need this to work
6596 */
dd856efa 6597 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6598 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6599 }
5fdbf976
MT		 6600 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6601 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6602 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6603 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6604 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6605 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6606 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6607 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6608#ifdef CONFIG_X86_64
5fdbf976
MT		 6609 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6610 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6611 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6612 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6613 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6614 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6615 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6616 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6617#endif
6618
5fdbf976 6619 regs->rip = kvm_rip_read(vcpu);
91586a3b 6620 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6621
b6c7a5dc
HB		 6622 return 0;
6623}
6624
6625int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6626{
7ae441ea
GN		 6627 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6628 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6629
5fdbf976
MT		 6630 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6631 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6632 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6633 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6634 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6635 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6636 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6637 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6638#ifdef CONFIG_X86_64
5fdbf976
MT		 6639 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6640 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6641 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6642 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6643 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6644 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6645 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6646 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6647#endif
6648
5fdbf976 6649 kvm_rip_write(vcpu, regs->rip);
91586a3b 6650 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6651
b4f14abd
JK		 6652 vcpu->arch.exception.pending = false;
6653
3842d135
AK		 6654 kvm_make_request(KVM_REQ_EVENT, vcpu);
6655
b6c7a5dc
HB		 6656 return 0;
6657}
6658
b6c7a5dc
HB		 6659void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6660{
6661 struct kvm_segment cs;
6662
3e6e0aab 6663 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6664 *db = cs.db;
6665 *l = cs.l;
6666}
6667EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6668
6669int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6670 struct kvm_sregs *sregs)
6671{
89a27f4d 6672 struct desc_ptr dt;
b6c7a5dc 6673
3e6e0aab
GT		 6674 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6675 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6676 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6677 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6678 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6679 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6680
3e6e0aab
GT		 6681 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6682 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6683
6684 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6685 sregs->idt.limit = dt.size;
6686 sregs->idt.base = dt.address;
b6c7a5dc 6687 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6688 sregs->gdt.limit = dt.size;
6689 sregs->gdt.base = dt.address;
b6c7a5dc 6690
4d4ec087 6691 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6692 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6693 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6694 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6695 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6696 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6697 sregs->apic_base = kvm_get_apic_base(vcpu);
6698
923c61bb 6699 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6700
36752c9b 6701 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6702 set_bit(vcpu->arch.interrupt.nr,
6703 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6704
b6c7a5dc
HB		 6705 return 0;
6706}
6707
62d9f0db
MT		 6708int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6709 struct kvm_mp_state *mp_state)
6710{
66450a21 6711 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6712 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6713 vcpu->arch.pv.pv_unhalted)
6714 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6715 else
6716 mp_state->mp_state = vcpu->arch.mp_state;
6717
62d9f0db
MT		 6718 return 0;
6719}
6720
6721int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6722 struct kvm_mp_state *mp_state)
6723{
66450a21
JK		 6724 if (!kvm_vcpu_has_lapic(vcpu) &&
6725 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6726 return -EINVAL;
6727
6728 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6729 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6730 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6731 } else
6732 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6733 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6734 return 0;
6735}
6736
7f3d35fd
KW		 6737int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6738 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6739{
9d74191a 6740 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6741 int ret;
e01c2426 6742
8ec4722d 6743 init_emulate_ctxt(vcpu);
c697518a 6744
7f3d35fd 6745 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6746 has_error_code, error_code);
c697518a 6747
c697518a 6748 if (ret)
19d04437 6749 return EMULATE_FAIL;
37817f29 6750
9d74191a
TY		 6751 kvm_rip_write(vcpu, ctxt->eip);
6752 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6753 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6754 return EMULATE_DONE;
37817f29
IE		 6755}
6756EXPORT_SYMBOL_GPL(kvm_task_switch);
6757
b6c7a5dc
HB		 6758int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6759 struct kvm_sregs *sregs)
6760{
58cb628d 6761 struct msr_data apic_base_msr;
b6c7a5dc 6762 int mmu_reset_needed = 0;
63f42e02 6763 int pending_vec, max_bits, idx;
89a27f4d 6764 struct desc_ptr dt;
b6c7a5dc 6765
6d1068b3
PM		 6766 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6767 return -EINVAL;
6768
89a27f4d
GN		 6769 dt.size = sregs->idt.limit;
6770 dt.address = sregs->idt.base;
b6c7a5dc 6771 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6772 dt.size = sregs->gdt.limit;
6773 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6774 kvm_x86_ops->set_gdt(vcpu, &dt);
6775
ad312c7c 6776 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6777 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6778 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6779 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6780
2d3ad1f4 6781 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6782
f6801dff 6783 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6784 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6785 apic_base_msr.data = sregs->apic_base;
6786 apic_base_msr.host_initiated = true;
6787 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6788
4d4ec087 6789 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6790 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6791 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6792
fc78f519 6793 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6794 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6795 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6796 kvm_update_cpuid(vcpu);
63f42e02
XG		 6797
6798 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6799 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6800 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6801 mmu_reset_needed = 1;
6802 }
63f42e02 6803 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6804
6805 if (mmu_reset_needed)
6806 kvm_mmu_reset_context(vcpu);
6807
a50abc3b 6808 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6809 pending_vec = find_first_bit(
6810 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6811 if (pending_vec < max_bits) {
66fd3f7f 6812 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6813 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6814 }
6815
3e6e0aab
GT		 6816 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6817 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6818 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6819 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6820 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6821 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6822
3e6e0aab
GT		 6823 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6824 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6825
5f0269f5
ME		 6826 update_cr8_intercept(vcpu);
6827
9c3e4aab 6828 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6829 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6830 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6831 !is_protmode(vcpu))
9c3e4aab
MT		 6832 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6833
3842d135
AK		 6834 kvm_make_request(KVM_REQ_EVENT, vcpu);
6835
b6c7a5dc
HB		 6836 return 0;
6837}
6838
d0bfb940
JK		 6839int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6840 struct kvm_guest_debug *dbg)
b6c7a5dc 6841{
355be0b9 6842 unsigned long rflags;
ae675ef0 6843 int i, r;
b6c7a5dc 6844
4f926bf2
JK		 6845 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6846 r = -EBUSY;
6847 if (vcpu->arch.exception.pending)
2122ff5e 6848 goto out;
4f926bf2
JK		 6849 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6850 kvm_queue_exception(vcpu, DB_VECTOR);
6851 else
6852 kvm_queue_exception(vcpu, BP_VECTOR);
6853 }
6854
91586a3b
JK		 6855 /*
6856 * Read rflags as long as potentially injected trace flags are still
6857 * filtered out.
6858 */
6859 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6860
6861 vcpu->guest_debug = dbg->control;
6862 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6863 vcpu->guest_debug = 0;
6864
6865 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6866 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6867 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6868 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6869 } else {
6870 for (i = 0; i < KVM_NR_DB_REGS; i++)
6871 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6872 }
c8639010 6873 kvm_update_dr7(vcpu);
ae675ef0 6874
f92653ee
JK		 6875 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6876 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6877 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6878
91586a3b
JK		 6879 /*
6880 * Trigger an rflags update that will inject or remove the trace
6881 * flags.
6882 */
6883 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6884
c8639010 6885 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6886
4f926bf2 6887 r = 0;
d0bfb940 6888
2122ff5e 6889out:
b6c7a5dc
HB		 6890
6891 return r;
6892}
6893
8b006791
ZX		 6894/*
6895 * Translate a guest virtual address to a guest physical address.
6896 */
6897int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6898 struct kvm_translation *tr)
6899{
6900 unsigned long vaddr = tr->linear_address;
6901 gpa_t gpa;
f656ce01 6902 int idx;
8b006791 6903
f656ce01 6904 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6905 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6906 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6907 tr->physical_address = gpa;
6908 tr->valid = gpa != UNMAPPED_GVA;
6909 tr->writeable = 1;
6910 tr->usermode = 0;
8b006791
ZX		 6911
6912 return 0;
6913}
6914
d0752060
HB		 6915int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6916{
98918833
SY		 6917 struct i387_fxsave_struct *fxsave =
6918 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6919
d0752060
HB		 6920 memcpy(fpu->fpr, fxsave->st_space, 128);
6921 fpu->fcw = fxsave->cwd;
6922 fpu->fsw = fxsave->swd;
6923 fpu->ftwx = fxsave->twd;
6924 fpu->last_opcode = fxsave->fop;
6925 fpu->last_ip = fxsave->rip;
6926 fpu->last_dp = fxsave->rdp;
6927 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6928
d0752060
HB		 6929 return 0;
6930}
6931
6932int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6933{
98918833
SY		 6934 struct i387_fxsave_struct *fxsave =
6935 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6936
d0752060
HB		 6937 memcpy(fxsave->st_space, fpu->fpr, 128);
6938 fxsave->cwd = fpu->fcw;
6939 fxsave->swd = fpu->fsw;
6940 fxsave->twd = fpu->ftwx;
6941 fxsave->fop = fpu->last_opcode;
6942 fxsave->rip = fpu->last_ip;
6943 fxsave->rdp = fpu->last_dp;
6944 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6945
d0752060
HB		 6946 return 0;
6947}
6948
10ab25cd 6949int fx_init(struct kvm_vcpu *vcpu)
d0752060 6950{
10ab25cd
JK		 6951 int err;
6952
6953 err = fpu_alloc(&vcpu->arch.guest_fpu);
6954 if (err)
6955 return err;
6956
98918833 6957 fpu_finit(&vcpu->arch.guest_fpu);
df1daba7
PB		 6958 if (cpu_has_xsaves)
6959 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
6960 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 6961
2acf923e
DC		 6962 /*
6963 * Ensure guest xcr0 is valid for loading
6964 */
6965 vcpu->arch.xcr0 = XSTATE_FP;
6966
ad312c7c 6967 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6968
6969 return 0;
d0752060
HB		 6970}
6971EXPORT_SYMBOL_GPL(fx_init);
6972
98918833
SY		 6973static void fx_free(struct kvm_vcpu *vcpu)
6974{
6975 fpu_free(&vcpu->arch.guest_fpu);
6976}
6977
d0752060
HB		 6978void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6979{
2608d7a1 6980 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6981 return;
6982
2acf923e
DC		 6983 /*
6984 * Restore all possible states in the guest,
6985 * and assume host would use all available bits.
6986 * Guest xcr0 would be loaded later.
6987 */
6988 kvm_put_guest_xcr0(vcpu);
d0752060 6989 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6990 __kernel_fpu_begin();
98918833 6991 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6992 trace_kvm_fpu(1);
d0752060 6993}
d0752060
HB		 6994
6995void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6996{
2acf923e
DC		 6997 kvm_put_guest_xcr0(vcpu);
6998
d0752060
HB		 6999 if (!vcpu->guest_fpu_loaded)
7000 return;
7001
7002 vcpu->guest_fpu_loaded = 0;
98918833 7003 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7004 __kernel_fpu_end();
f096ed85 7005 ++vcpu->stat.fpu_reload;
a8eeb04a 7006 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 7007 trace_kvm_fpu(0);
d0752060 7008}
e9b11c17
ZX		 7009
7010void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7011{
12f9a48f 7012 kvmclock_reset(vcpu);
7f1ea208 7013
f5f48ee1 7014 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7015 fx_free(vcpu);
e9b11c17
ZX		 7016 kvm_x86_ops->vcpu_free(vcpu);
7017}
7018
7019struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7020 unsigned int id)
7021{
6755bae8
ZA		 7022 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7023 printk_once(KERN_WARNING
7024 "kvm: SMP vm created on host with unstable TSC; "
7025 "guest TSC will not be reliable\n");
26e5215f
AK		 7026 return kvm_x86_ops->vcpu_create(kvm, id);
7027}
e9b11c17 7028
26e5215f
AK		 7029int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7030{
7031 int r;
e9b11c17 7032
0bed3b56 7033 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7034 r = vcpu_load(vcpu);
7035 if (r)
7036 return r;
57f252f2 7037 kvm_vcpu_reset(vcpu);
8a3c1a33 7038 kvm_mmu_setup(vcpu);
e9b11c17 7039 vcpu_put(vcpu);
e9b11c17 7040
26e5215f 7041 return r;
e9b11c17
ZX		 7042}
7043
42897d86
MT		 7044int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7045{
7046 int r;
8fe8ab46 7047 struct msr_data msr;
332967a3 7048 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 7049
7050 r = vcpu_load(vcpu);
7051 if (r)
7052 return r;
8fe8ab46
WA		 7053 msr.data = 0x0;
7054 msr.index = MSR_IA32_TSC;
7055 msr.host_initiated = true;
7056 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7057 vcpu_put(vcpu);
7058
332967a3
AJ		 7059 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7060 KVMCLOCK_SYNC_PERIOD);
7061
42897d86
MT		 7062 return r;
7063}
7064
d40ccc62 7065void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7066{
9fc77441 7067 int r;
344d9588
GN		 7068 vcpu->arch.apf.msr_val = 0;
7069
9fc77441
MT		 7070 r = vcpu_load(vcpu);
7071 BUG_ON(r);
e9b11c17
ZX		 7072 kvm_mmu_unload(vcpu);
7073 vcpu_put(vcpu);
7074
98918833 7075 fx_free(vcpu);
e9b11c17
ZX		 7076 kvm_x86_ops->vcpu_free(vcpu);
7077}
7078
66450a21 7079void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 7080{
7460fb4a
AK		 7081 atomic_set(&vcpu->arch.nmi_queued, 0);
7082 vcpu->arch.nmi_pending = 0;
448fa4a9 7083 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7084 kvm_clear_interrupt_queue(vcpu);
7085 kvm_clear_exception_queue(vcpu);
448fa4a9 7086
42dbaa5a 7087 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 7088 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7089 kvm_update_dr6(vcpu);
42dbaa5a 7090 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7091 kvm_update_dr7(vcpu);
42dbaa5a 7092
3842d135 7093 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7094 vcpu->arch.apf.msr_val = 0;
c9aaa895 7095 vcpu->arch.st.msr_val = 0;
3842d135 7096
12f9a48f
GC		 7097 kvmclock_reset(vcpu);
7098
af585b92
GN		 7099 kvm_clear_async_pf_completion_queue(vcpu);
7100 kvm_async_pf_hash_reset(vcpu);
7101 vcpu->arch.apf.halted = false;
3842d135 7102
f5132b01
GN		 7103 kvm_pmu_reset(vcpu);
7104
66f7b72e
JS		 7105 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7106 vcpu->arch.regs_avail = ~0;
7107 vcpu->arch.regs_dirty = ~0;
7108
57f252f2 7109 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7110}
7111
2b4a273b 7112void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7113{
7114 struct kvm_segment cs;
7115
7116 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7117 cs.selector = vector << 8;
7118 cs.base = vector << 12;
7119 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7120 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7121}
7122
13a34e06 7123int kvm_arch_hardware_enable(void)
e9b11c17 7124{
ca84d1a2
ZA		 7125 struct kvm *kvm;
7126 struct kvm_vcpu *vcpu;
7127 int i;
0dd6a6ed
ZA		 7128 int ret;
7129 u64 local_tsc;
7130 u64 max_tsc = 0;
7131 bool stable, backwards_tsc = false;
18863bdd
AK		 7132
7133 kvm_shared_msr_cpu_online();
13a34e06 7134 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7135 if (ret != 0)
7136 return ret;
7137
7138 local_tsc = native_read_tsc();
7139 stable = !check_tsc_unstable();
7140 list_for_each_entry(kvm, &vm_list, vm_list) {
7141 kvm_for_each_vcpu(i, vcpu, kvm) {
7142 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7143 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7144 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7145 backwards_tsc = true;
7146 if (vcpu->arch.last_host_tsc > max_tsc)
7147 max_tsc = vcpu->arch.last_host_tsc;
7148 }
7149 }
7150 }
7151
7152 /*
7153 * Sometimes, even reliable TSCs go backwards. This happens on
7154 * platforms that reset TSC during suspend or hibernate actions, but
7155 * maintain synchronization. We must compensate. Fortunately, we can
7156 * detect that condition here, which happens early in CPU bringup,
7157 * before any KVM threads can be running. Unfortunately, we can't
7158 * bring the TSCs fully up to date with real time, as we aren't yet far
7159 * enough into CPU bringup that we know how much real time has actually
7160 * elapsed; our helper function, get_kernel_ns() will be using boot
7161 * variables that haven't been updated yet.
7162 *
7163 * So we simply find the maximum observed TSC above, then record the
7164 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7165 * the adjustment will be applied. Note that we accumulate
7166 * adjustments, in case multiple suspend cycles happen before some VCPU
7167 * gets a chance to run again. In the event that no KVM threads get a
7168 * chance to run, we will miss the entire elapsed period, as we'll have
7169 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7170 * loose cycle time. This isn't too big a deal, since the loss will be
7171 * uniform across all VCPUs (not to mention the scenario is extremely
7172 * unlikely). It is possible that a second hibernate recovery happens
7173 * much faster than a first, causing the observed TSC here to be
7174 * smaller; this would require additional padding adjustment, which is
7175 * why we set last_host_tsc to the local tsc observed here.
7176 *
7177 * N.B. - this code below runs only on platforms with reliable TSC,
7178 * as that is the only way backwards_tsc is set above. Also note
7179 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7180 * have the same delta_cyc adjustment applied if backwards_tsc
7181 * is detected. Note further, this adjustment is only done once,
7182 * as we reset last_host_tsc on all VCPUs to stop this from being
7183 * called multiple times (one for each physical CPU bringup).
7184 *
4a969980 7185 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7186 * will be compensated by the logic in vcpu_load, which sets the TSC to
7187 * catchup mode. This will catchup all VCPUs to real time, but cannot
7188 * guarantee that they stay in perfect synchronization.
7189 */
7190 if (backwards_tsc) {
7191 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7192 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7193 list_for_each_entry(kvm, &vm_list, vm_list) {
7194 kvm_for_each_vcpu(i, vcpu, kvm) {
7195 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7196 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7197 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7198 }
7199
7200 /*
7201 * We have to disable TSC offset matching.. if you were
7202 * booting a VM while issuing an S4 host suspend....
7203 * you may have some problem. Solving this issue is
7204 * left as an exercise to the reader.
7205 */
7206 kvm->arch.last_tsc_nsec = 0;
7207 kvm->arch.last_tsc_write = 0;
7208 }
7209
7210 }
7211 return 0;
e9b11c17
ZX		 7212}
7213
13a34e06 7214void kvm_arch_hardware_disable(void)
e9b11c17 7215{
13a34e06
RK		 7216 kvm_x86_ops->hardware_disable();
7217 drop_user_return_notifiers();
e9b11c17
ZX		 7218}
7219
7220int kvm_arch_hardware_setup(void)
7221{
7222 return kvm_x86_ops->hardware_setup();
7223}
7224
7225void kvm_arch_hardware_unsetup(void)
7226{
7227 kvm_x86_ops->hardware_unsetup();
7228}
7229
7230void kvm_arch_check_processor_compat(void *rtn)
7231{
7232 kvm_x86_ops->check_processor_compatibility(rtn);
7233}
7234
3e515705
AK		 7235bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7236{
7237 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7238}
7239
54e9818f
GN		 7240struct static_key kvm_no_apic_vcpu __read_mostly;
7241
e9b11c17
ZX		 7242int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7243{
7244 struct page *page;
7245 struct kvm *kvm;
7246 int r;
7247
7248 BUG_ON(vcpu->kvm == NULL);
7249 kvm = vcpu->kvm;
7250
6aef266c 7251 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7252 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7253 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7254 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7255 else
a4535290 7256 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7257
7258 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7259 if (!page) {
7260 r = -ENOMEM;
7261 goto fail;
7262 }
ad312c7c 7263 vcpu->arch.pio_data = page_address(page);
e9b11c17 7264
cc578287 7265 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7266
e9b11c17
ZX		 7267 r = kvm_mmu_create(vcpu);
7268 if (r < 0)
7269 goto fail_free_pio_data;
7270
7271 if (irqchip_in_kernel(kvm)) {
7272 r = kvm_create_lapic(vcpu);
7273 if (r < 0)
7274 goto fail_mmu_destroy;
54e9818f
GN		 7275 } else
7276 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7277
890ca9ae
HY		 7278 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7279 GFP_KERNEL);
7280 if (!vcpu->arch.mce_banks) {
7281 r = -ENOMEM;
443c39bc 7282 goto fail_free_lapic;
890ca9ae
HY		 7283 }
7284 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7285
f1797359
WY		 7286 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7287 r = -ENOMEM;
f5f48ee1 7288 goto fail_free_mce_banks;
f1797359 7289 }
f5f48ee1 7290
66f7b72e
JS		 7291 r = fx_init(vcpu);
7292 if (r)
7293 goto fail_free_wbinvd_dirty_mask;
7294
ba904635 7295 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7296 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7297
7298 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7299 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7300
af585b92 7301 kvm_async_pf_hash_reset(vcpu);
f5132b01 7302 kvm_pmu_init(vcpu);
af585b92 7303
e9b11c17 7304 return 0;
66f7b72e
JS		 7305fail_free_wbinvd_dirty_mask:
7306 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7307fail_free_mce_banks:
7308 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7309fail_free_lapic:
7310 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7311fail_mmu_destroy:
7312 kvm_mmu_destroy(vcpu);
7313fail_free_pio_data:
ad312c7c 7314 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7315fail:
7316 return r;
7317}
7318
7319void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7320{
f656ce01
MT		 7321 int idx;
7322
f5132b01 7323 kvm_pmu_destroy(vcpu);
36cb93fd 7324 kfree(vcpu->arch.mce_banks);
e9b11c17 7325 kvm_free_lapic(vcpu);
f656ce01 7326 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7327 kvm_mmu_destroy(vcpu);
f656ce01 7328 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7329 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7330 if (!irqchip_in_kernel(vcpu->kvm))
7331 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7332}
d19a9cd2 7333
e790d9ef
RK		 7334void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7335{
ae97a3b8 7336 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7337}
7338
e08b9637 7339int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7340{
e08b9637
CO		 7341 if (type)
7342 return -EINVAL;
7343
6ef768fa 7344 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7345 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7346 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7347 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7348 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7349
5550af4d
SY		 7350 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7351 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7352 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7353 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7354 &kvm->arch.irq_sources_bitmap);
5550af4d 7355
038f8c11 7356 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7357 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7358 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7359
7360 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7361
7e44e449 7362 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7363 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7364
d89f5eff 7365 return 0;
d19a9cd2
ZX		 7366}
7367
7368static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7369{
9fc77441
MT		 7370 int r;
7371 r = vcpu_load(vcpu);
7372 BUG_ON(r);
d19a9cd2
ZX		 7373 kvm_mmu_unload(vcpu);
7374 vcpu_put(vcpu);
7375}
7376
7377static void kvm_free_vcpus(struct kvm *kvm)
7378{
7379 unsigned int i;
988a2cae 7380 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7381
7382 /*
7383 * Unpin any mmu pages first.
7384 */
af585b92
GN		 7385 kvm_for_each_vcpu(i, vcpu, kvm) {
7386 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7387 kvm_unload_vcpu_mmu(vcpu);
af585b92 7388 }
988a2cae
GN		 7389 kvm_for_each_vcpu(i, vcpu, kvm)
7390 kvm_arch_vcpu_free(vcpu);
7391
7392 mutex_lock(&kvm->lock);
7393 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7394 kvm->vcpus[i] = NULL;
d19a9cd2 7395
988a2cae
GN		 7396 atomic_set(&kvm->online_vcpus, 0);
7397 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7398}
7399
ad8ba2cd
SY		 7400void kvm_arch_sync_events(struct kvm *kvm)
7401{
332967a3 7402 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7403 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7404 kvm_free_all_assigned_devices(kvm);
aea924f6 7405 kvm_free_pit(kvm);
ad8ba2cd
SY		 7406}
7407
d19a9cd2
ZX		 7408void kvm_arch_destroy_vm(struct kvm *kvm)
7409{
27469d29
AH		 7410 if (current->mm == kvm->mm) {
7411 /*
7412 * Free memory regions allocated on behalf of userspace,
7413 * unless the the memory map has changed due to process exit
7414 * or fd copying.
7415 */
7416 struct kvm_userspace_memory_region mem;
7417 memset(&mem, 0, sizeof(mem));
7418 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7419 kvm_set_memory_region(kvm, &mem);
7420
7421 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7422 kvm_set_memory_region(kvm, &mem);
7423
7424 mem.slot = TSS_PRIVATE_MEMSLOT;
7425 kvm_set_memory_region(kvm, &mem);
7426 }
6eb55818 7427 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7428 kfree(kvm->arch.vpic);
7429 kfree(kvm->arch.vioapic);
d19a9cd2 7430 kvm_free_vcpus(kvm);
1e08ec4a 7431 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7432}
0de10343 7433
5587027c 7434void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7435 struct kvm_memory_slot *dont)
7436{
7437 int i;
7438
d89cc617
TY		 7439 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7440 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7441 kvm_kvfree(free->arch.rmap[i]);
7442 free->arch.rmap[i] = NULL;
77d11309 7443 }
d89cc617
TY		 7444 if (i == 0)
7445 continue;
7446
7447 if (!dont || free->arch.lpage_info[i - 1] !=
7448 dont->arch.lpage_info[i - 1]) {
7449 kvm_kvfree(free->arch.lpage_info[i - 1]);
7450 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7451 }
7452 }
7453}
7454
5587027c
AK		 7455int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7456 unsigned long npages)
db3fe4eb
TY		 7457{
7458 int i;
7459
d89cc617 7460 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7461 unsigned long ugfn;
7462 int lpages;
d89cc617 7463 int level = i + 1;
db3fe4eb
TY		 7464
7465 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7466 slot->base_gfn, level) + 1;
7467
d89cc617
TY		 7468 slot->arch.rmap[i] =
7469 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7470 if (!slot->arch.rmap[i])
77d11309 7471 goto out_free;
d89cc617
TY		 7472 if (i == 0)
7473 continue;
77d11309 7474
d89cc617
TY		 7475 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7476 sizeof(*slot->arch.lpage_info[i - 1]));
7477 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7478 goto out_free;
7479
7480 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7481 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7482 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7483 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7484 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7485 /*
7486 * If the gfn and userspace address are not aligned wrt each
7487 * other, or if explicitly asked to, disable large page
7488 * support for this slot
7489 */
7490 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7491 !kvm_largepages_enabled()) {
7492 unsigned long j;
7493
7494 for (j = 0; j < lpages; ++j)
d89cc617 7495 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7496 }
7497 }
7498
7499 return 0;
7500
7501out_free:
d89cc617
TY		 7502 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7503 kvm_kvfree(slot->arch.rmap[i]);
7504 slot->arch.rmap[i] = NULL;
7505 if (i == 0)
7506 continue;
7507
7508 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7509 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7510 }
7511 return -ENOMEM;
7512}
7513
e59dbe09
TY		 7514void kvm_arch_memslots_updated(struct kvm *kvm)
7515{
e6dff7d1
TY		 7516 /*
7517 * memslots->generation has been incremented.
7518 * mmio generation may have reached its maximum value.
7519 */
7520 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7521}
7522
f7784b8e
MT		 7523int kvm_arch_prepare_memory_region(struct kvm *kvm,
7524 struct kvm_memory_slot *memslot,
f7784b8e 7525 struct kvm_userspace_memory_region *mem,
7b6195a9 7526 enum kvm_mr_change change)
0de10343 7527{
7a905b14
TY		 7528 /*
7529 * Only private memory slots need to be mapped here since
7530 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7531 */
7b6195a9 7532 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7533 unsigned long userspace_addr;
604b38ac 7534
7a905b14
TY		 7535 /*
7536 * MAP_SHARED to prevent internal slot pages from being moved
7537 * by fork()/COW.
7538 */
7b6195a9 7539 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7540 PROT_READ | PROT_WRITE,
7541 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7542
7a905b14
TY		 7543 if (IS_ERR((void *)userspace_addr))
7544 return PTR_ERR((void *)userspace_addr);
604b38ac 7545
7a905b14 7546 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7547 }
7548
f7784b8e
MT		 7549 return 0;
7550}
7551
7552void kvm_arch_commit_memory_region(struct kvm *kvm,
7553 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7554 const struct kvm_memory_slot *old,
7555 enum kvm_mr_change change)
f7784b8e
MT		 7556{
7557
8482644a 7558 int nr_mmu_pages = 0;
f7784b8e 7559
8482644a 7560 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7561 int ret;
7562
8482644a
TY		 7563 ret = vm_munmap(old->userspace_addr,
7564 old->npages * PAGE_SIZE);
f7784b8e
MT		 7565 if (ret < 0)
7566 printk(KERN_WARNING
7567 "kvm_vm_ioctl_set_memory_region: "
7568 "failed to munmap memory\n");
7569 }
7570
48c0e4e9
XG		 7571 if (!kvm->arch.n_requested_mmu_pages)
7572 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7573
48c0e4e9 7574 if (nr_mmu_pages)
0de10343 7575 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7576 /*
7577 * Write protect all pages for dirty logging.
c126d94f
XG		 7578 *
7579 * All the sptes including the large sptes which point to this
7580 * slot are set to readonly. We can not create any new large
7581 * spte on this slot until the end of the logging.
7582 *
7583 * See the comments in fast_page_fault().
c972f3b1 7584 */
8482644a 7585 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7586 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7587}
1d737c8a 7588
2df72e9b 7589void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7590{
6ca18b69 7591 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7592}
7593
2df72e9b
MT		 7594void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7595 struct kvm_memory_slot *slot)
7596{
6ca18b69 7597 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7598}
7599
1d737c8a
ZX		 7600int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7601{
b6b8a145
JK		 7602 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7603 kvm_x86_ops->check_nested_events(vcpu, false);
7604
af585b92
GN		 7605 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7606 !vcpu->arch.apf.halted)
7607 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7608 || kvm_apic_has_events(vcpu)
6aef266c 7609 || vcpu->arch.pv.pv_unhalted
7460fb4a 7610 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7611 (kvm_arch_interrupt_allowed(vcpu) &&
7612 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7613}
5736199a 7614
b6d33834 7615int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7616{
b6d33834 7617 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7618}
78646121
GN		 7619
7620int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7621{
7622 return kvm_x86_ops->interrupt_allowed(vcpu);
7623}
229456fc 7624
82b32774 7625unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7626{
82b32774
NA		 7627 if (is_64_bit_mode(vcpu))
7628 return kvm_rip_read(vcpu);
7629 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7630 kvm_rip_read(vcpu));
7631}
7632EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7633
82b32774
NA		 7634bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7635{
7636 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7637}
7638EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7639
94fe45da
JK		 7640unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7641{
7642 unsigned long rflags;
7643
7644 rflags = kvm_x86_ops->get_rflags(vcpu);
7645 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7646 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7647 return rflags;
7648}
7649EXPORT_SYMBOL_GPL(kvm_get_rflags);
7650
6addfc42 7651static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7652{
7653 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7654 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7655 rflags |= X86_EFLAGS_TF;
94fe45da 7656 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7657}
7658
7659void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7660{
7661 __kvm_set_rflags(vcpu, rflags);
3842d135 7662 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7663}
7664EXPORT_SYMBOL_GPL(kvm_set_rflags);
7665
56028d08
GN		 7666void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7667{
7668 int r;
7669
fb67e14f 7670 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7671 work->wakeup_all)
56028d08
GN		 7672 return;
7673
7674 r = kvm_mmu_reload(vcpu);
7675 if (unlikely(r))
7676 return;
7677
fb67e14f
XG		 7678 if (!vcpu->arch.mmu.direct_map &&
7679 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7680 return;
7681
56028d08
GN		 7682 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7683}
7684
af585b92
GN		 7685static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7686{
7687 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7688}
7689
7690static inline u32 kvm_async_pf_next_probe(u32 key)
7691{
7692 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7693}
7694
7695static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7696{
7697 u32 key = kvm_async_pf_hash_fn(gfn);
7698
7699 while (vcpu->arch.apf.gfns[key] != ~0)
7700 key = kvm_async_pf_next_probe(key);
7701
7702 vcpu->arch.apf.gfns[key] = gfn;
7703}
7704
7705static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7706{
7707 int i;
7708 u32 key = kvm_async_pf_hash_fn(gfn);
7709
7710 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7711 (vcpu->arch.apf.gfns[key] != gfn &&
7712 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7713 key = kvm_async_pf_next_probe(key);
7714
7715 return key;
7716}
7717
7718bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7719{
7720 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7721}
7722
7723static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7724{
7725 u32 i, j, k;
7726
7727 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7728 while (true) {
7729 vcpu->arch.apf.gfns[i] = ~0;
7730 do {
7731 j = kvm_async_pf_next_probe(j);
7732 if (vcpu->arch.apf.gfns[j] == ~0)
7733 return;
7734 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7735 /*
7736 * k lies cyclically in ]i,j]
7737 * | i.k.j |
7738 * |....j i.k.| or |.k..j i...|
7739 */
7740 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7741 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7742 i = j;
7743 }
7744}
7745
7c90705b
GN		 7746static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7747{
7748
7749 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7750 sizeof(val));
7751}
7752
af585b92
GN		 7753void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7754 struct kvm_async_pf *work)
7755{
6389ee94
AK		 7756 struct x86_exception fault;
7757
7c90705b 7758 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7759 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7760
7761 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7762 (vcpu->arch.apf.send_user_only &&
7763 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7764 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7765 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7766 fault.vector = PF_VECTOR;
7767 fault.error_code_valid = true;
7768 fault.error_code = 0;
7769 fault.nested_page_fault = false;
7770 fault.address = work->arch.token;
7771 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7772 }
af585b92
GN		 7773}
7774
7775void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7776 struct kvm_async_pf *work)
7777{
6389ee94
AK		 7778 struct x86_exception fault;
7779
7c90705b 7780 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7781 if (work->wakeup_all)
7c90705b
GN		 7782 work->arch.token = ~0; /* broadcast wakeup */
7783 else
7784 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7785
7786 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7787 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7788 fault.vector = PF_VECTOR;
7789 fault.error_code_valid = true;
7790 fault.error_code = 0;
7791 fault.nested_page_fault = false;
7792 fault.address = work->arch.token;
7793 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7794 }
e6d53e3b 7795 vcpu->arch.apf.halted = false;
a4fa1635 7796 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7797}
7798
7799bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7800{
7801 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7802 return true;
7803 else
7804 return !kvm_event_needs_reinjection(vcpu) &&
7805 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7806}
7807
e0f0bbc5
AW		 7808void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7809{
7810 atomic_inc(&kvm->arch.noncoherent_dma_count);
7811}
7812EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7813
7814void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7815{
7816 atomic_dec(&kvm->arch.noncoherent_dma_count);
7817}
7818EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7819
7820bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7821{
7822 return atomic_read(&kvm->arch.noncoherent_dma_count);
7823}
7824EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7825
229456fc
MT		 7826EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7827EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7828EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7829EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7830EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7831EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7832EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7833EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7834EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7835EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7836EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7837EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7838EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7839EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux kernel - Deliverables
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