projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: SVM: Report emulated SVM features to userspace
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
268 unsigned nr, bool has_error, u32 error_code)
269{
270 u32 prev_nr;
271 int class1, class2;
272
273 if (!vcpu->arch.exception.pending) {
274 queue:
275 vcpu->arch.exception.pending = true;
276 vcpu->arch.exception.has_error_code = has_error;
277 vcpu->arch.exception.nr = nr;
278 vcpu->arch.exception.error_code = error_code;
279 return;
280 }
281
282 /* to check exception */
283 prev_nr = vcpu->arch.exception.nr;
284 if (prev_nr == DF_VECTOR) {
285 /* triple fault -> shutdown */
286 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
287 return;
288 }
289 class1 = exception_class(prev_nr);
290 class2 = exception_class(nr);
291 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
292 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
293 /* generate double fault per SDM Table 5-5 */
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = true;
296 vcpu->arch.exception.nr = DF_VECTOR;
297 vcpu->arch.exception.error_code = 0;
298 } else
299 /* replace previous exception with a new one in a hope
300 that instruction re-execution will regenerate lost
301 exception */
302 goto queue;
303}
304
298101da
AK		 305void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
306{
3fd28fce 307 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 308}
309EXPORT_SYMBOL_GPL(kvm_queue_exception);
310
c3c91fee
AK		 311void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
312 u32 error_code)
313{
314 ++vcpu->stat.pf_guest;
ad312c7c 315 vcpu->arch.cr2 = addr;
c3c91fee
AK		 316 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
317}
318
3419ffc8
SY		 319void kvm_inject_nmi(struct kvm_vcpu *vcpu)
320{
321 vcpu->arch.nmi_pending = 1;
322}
323EXPORT_SYMBOL_GPL(kvm_inject_nmi);
324
298101da
AK		 325void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
326{
3fd28fce 327 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
330
0a79b009
AK		 331/*
332 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
333 * a #GP and return false.
334 */
335bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 336{
0a79b009
AK		 337 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
338 return true;
339 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
340 return false;
298101da 341}
0a79b009 342EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 343
a03490ed
CO		 344/*
345 * Load the pae pdptrs. Return true is they are all valid.
346 */
347int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
348{
349 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
350 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
351 int i;
352 int ret;
ad312c7c 353 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 354
a03490ed
CO		 355 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
356 offset * sizeof(u64), sizeof(pdpte));
357 if (ret < 0) {
358 ret = 0;
359 goto out;
360 }
361 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 362 if (is_present_gpte(pdpte[i]) &&
20c466b5 363 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 364 ret = 0;
365 goto out;
366 }
367 }
368 ret = 1;
369
ad312c7c 370 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 371 __set_bit(VCPU_EXREG_PDPTR,
372 (unsigned long *)&vcpu->arch.regs_avail);
373 __set_bit(VCPU_EXREG_PDPTR,
374 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 375out:
a03490ed
CO		 376
377 return ret;
378}
cc4b6871 379EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 380
d835dfec
AK		 381static bool pdptrs_changed(struct kvm_vcpu *vcpu)
382{
ad312c7c 383 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 384 bool changed = true;
385 int r;
386
387 if (is_long_mode(vcpu) || !is_pae(vcpu))
388 return false;
389
6de4f3ad
AK		 390 if (!test_bit(VCPU_EXREG_PDPTR,
391 (unsigned long *)&vcpu->arch.regs_avail))
392 return true;
393
ad312c7c 394 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 395 if (r < 0)
396 goto out;
ad312c7c 397 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 398out:
d835dfec
AK		 399
400 return changed;
401}
402
2d3ad1f4 403void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 404{
f9a48e6a
AK		 405 cr0 |= X86_CR0_ET;
406
ab344828
GN		 407#ifdef CONFIG_X86_64
408 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 409 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 410 return;
411 }
ab344828
GN		 412#endif
413
414 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 415
416 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 417 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 418 return;
419 }
420
421 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 422 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 423 return;
424 }
425
426 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
427#ifdef CONFIG_X86_64
f6801dff 428 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 429 int cs_db, cs_l;
430
431 if (!is_pae(vcpu)) {
c1a5d4f9 432 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 433 return;
434 }
435 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
436 if (cs_l) {
c1a5d4f9 437 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 438 return;
439
440 }
441 } else
442#endif
ad312c7c 443 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447
448 }
449
450 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 451
a03490ed 452 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 453 return;
454}
2d3ad1f4 455EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 456
2d3ad1f4 457void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 458{
4d4ec087 459 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 462
2d3ad1f4 463void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 464{
fc78f519 465 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 466 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
467
a03490ed 468 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 469 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 470 return;
471 }
472
473 if (is_long_mode(vcpu)) {
474 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 475 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 476 return;
477 }
a2edf57f
AK		 478 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
479 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 480 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 481 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 482 return;
483 }
484
485 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 486 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 487 return;
488 }
489 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 490 vcpu->arch.cr4 = cr4;
a03490ed 491 kvm_mmu_reset_context(vcpu);
a03490ed 492}
2d3ad1f4 493EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 494
2d3ad1f4 495void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 496{
ad312c7c 497 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 498 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 499 kvm_mmu_flush_tlb(vcpu);
500 return;
501 }
502
a03490ed
CO		 503 if (is_long_mode(vcpu)) {
504 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 505 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 506 return;
507 }
508 } else {
509 if (is_pae(vcpu)) {
510 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 511 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 512 return;
513 }
514 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 515 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 516 return;
517 }
518 }
519 /*
520 * We don't check reserved bits in nonpae mode, because
521 * this isn't enforced, and VMware depends on this.
522 */
523 }
524
a03490ed
CO		 525 /*
526 * Does the new cr3 value map to physical memory? (Note, we
527 * catch an invalid cr3 even in real-mode, because it would
528 * cause trouble later on when we turn on paging anyway.)
529 *
530 * A real CPU would silently accept an invalid cr3 and would
531 * attempt to use it - with largely undefined (and often hard
532 * to debug) behavior on the guest side.
533 */
534 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 535 kvm_inject_gp(vcpu, 0);
a03490ed 536 else {
ad312c7c
ZX		 537 vcpu->arch.cr3 = cr3;
538 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 539 }
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 542
2d3ad1f4 543void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 544{
545 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 546 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 547 return;
548 }
549 if (irqchip_in_kernel(vcpu->kvm))
550 kvm_lapic_set_tpr(vcpu, cr8);
551 else
ad312c7c 552 vcpu->arch.cr8 = cr8;
a03490ed 553}
2d3ad1f4 554EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 555
2d3ad1f4 556unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 557{
558 if (irqchip_in_kernel(vcpu->kvm))
559 return kvm_lapic_get_cr8(vcpu);
560 else
ad312c7c 561 return vcpu->arch.cr8;
a03490ed 562}
2d3ad1f4 563EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 564
020df079
GN		 565int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
566{
567 switch (dr) {
568 case 0 ... 3:
569 vcpu->arch.db[dr] = val;
570 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
571 vcpu->arch.eff_db[dr] = val;
572 break;
573 case 4:
574 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
575 kvm_queue_exception(vcpu, UD_VECTOR);
576 return 1;
577 }
578 /* fall through */
579 case 6:
580 if (val & 0xffffffff00000000ULL) {
581 kvm_inject_gp(vcpu, 0);
582 return 1;
583 }
584 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
585 break;
586 case 5:
587 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
588 kvm_queue_exception(vcpu, UD_VECTOR);
589 return 1;
590 }
591 /* fall through */
592 default: /* 7 */
593 if (val & 0xffffffff00000000ULL) {
594 kvm_inject_gp(vcpu, 0);
595 return 1;
596 }
597 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
598 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
599 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
600 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
601 }
602 break;
603 }
604
605 return 0;
606}
607EXPORT_SYMBOL_GPL(kvm_set_dr);
608
609int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
610{
611 switch (dr) {
612 case 0 ... 3:
613 *val = vcpu->arch.db[dr];
614 break;
615 case 4:
616 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
617 kvm_queue_exception(vcpu, UD_VECTOR);
618 return 1;
619 }
620 /* fall through */
621 case 6:
622 *val = vcpu->arch.dr6;
623 break;
624 case 5:
625 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
626 kvm_queue_exception(vcpu, UD_VECTOR);
627 return 1;
628 }
629 /* fall through */
630 default: /* 7 */
631 *val = vcpu->arch.dr7;
632 break;
633 }
634
635 return 0;
636}
637EXPORT_SYMBOL_GPL(kvm_get_dr);
638
d8017474
AG		 639static inline u32 bit(int bitno)
640{
641 return 1 << (bitno & 31);
642}
643
043405e1
CO		 644/*
645 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
646 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
647 *
648 * This list is modified at module load time to reflect the
e3267cbb
GC		 649 * capabilities of the host cpu. This capabilities test skips MSRs that are
650 * kvm-specific. Those are put in the beginning of the list.
043405e1 651 */
e3267cbb 652
10388a07 653#define KVM_SAVE_MSRS_BEGIN 5
043405e1 654static u32 msrs_to_save[] = {
e3267cbb 655 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 656 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 657 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 658 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
659 MSR_K6_STAR,
660#ifdef CONFIG_X86_64
661 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
662#endif
e3267cbb 663 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 664};
665
666static unsigned num_msrs_to_save;
667
668static u32 emulated_msrs[] = {
669 MSR_IA32_MISC_ENABLE,
670};
671
15c4a640
CO		 672static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
673{
f2b4b7dd 674 if (efer & efer_reserved_bits) {
c1a5d4f9 675 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 676 return;
677 }
678
679 if (is_paging(vcpu)
f6801dff 680 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 681 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 682 return;
683 }
684
1b2fd70c
AG		 685 if (efer & EFER_FFXSR) {
686 struct kvm_cpuid_entry2 *feat;
687
688 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
689 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 690 kvm_inject_gp(vcpu, 0);
691 return;
692 }
693 }
694
d8017474
AG		 695 if (efer & EFER_SVME) {
696 struct kvm_cpuid_entry2 *feat;
697
698 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
699 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 700 kvm_inject_gp(vcpu, 0);
701 return;
702 }
703 }
704
15c4a640
CO		 705 kvm_x86_ops->set_efer(vcpu, efer);
706
707 efer &= ~EFER_LMA;
f6801dff 708 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 709
f6801dff 710 vcpu->arch.efer = efer;
9645bb56
AK		 711
712 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
713 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 714}
715
f2b4b7dd
JR		 716void kvm_enable_efer_bits(u64 mask)
717{
718 efer_reserved_bits &= ~mask;
719}
720EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
721
722
15c4a640
CO		 723/*
724 * Writes msr value into into the appropriate "register".
725 * Returns 0 on success, non-0 otherwise.
726 * Assumes vcpu_load() was already called.
727 */
728int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
729{
730 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
731}
732
313a3dc7
CO		 733/*
734 * Adapt set_msr() to msr_io()'s calling convention
735 */
736static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
737{
738 return kvm_set_msr(vcpu, index, *data);
739}
740
18068523
GOC		 741static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
742{
743 static int version;
50d0a0f9 744 struct pvclock_wall_clock wc;
923de3cf 745 struct timespec boot;
18068523
GOC		 746
747 if (!wall_clock)
748 return;
749
750 version++;
751
18068523
GOC		 752 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
753
50d0a0f9
GH		 754 /*
755 * The guest calculates current wall clock time by adding
756 * system time (updated by kvm_write_guest_time below) to the
757 * wall clock specified here. guest system time equals host
758 * system time for us, thus we must fill in host boot time here.
759 */
923de3cf 760 getboottime(&boot);
50d0a0f9
GH		 761
762 wc.sec = boot.tv_sec;
763 wc.nsec = boot.tv_nsec;
764 wc.version = version;
18068523
GOC		 765
766 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
767
768 version++;
769 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 770}
771
50d0a0f9
GH		 772static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
773{
774 uint32_t quotient, remainder;
775
776 /* Don't try to replace with do_div(), this one calculates
777 * "(dividend << 32) / divisor" */
778 __asm__ ( "divl %4"
779 : "=a" (quotient), "=d" (remainder)
780 : "0" (0), "1" (dividend), "r" (divisor) );
781 return quotient;
782}
783
784static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
785{
786 uint64_t nsecs = 1000000000LL;
787 int32_t shift = 0;
788 uint64_t tps64;
789 uint32_t tps32;
790
791 tps64 = tsc_khz * 1000LL;
792 while (tps64 > nsecs*2) {
793 tps64 >>= 1;
794 shift--;
795 }
796
797 tps32 = (uint32_t)tps64;
798 while (tps32 <= (uint32_t)nsecs) {
799 tps32 <<= 1;
800 shift++;
801 }
802
803 hv_clock->tsc_shift = shift;
804 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
805
806 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 807 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 808 hv_clock->tsc_to_system_mul);
809}
810
c8076604
GH		 811static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
812
18068523
GOC		 813static void kvm_write_guest_time(struct kvm_vcpu *v)
814{
815 struct timespec ts;
816 unsigned long flags;
817 struct kvm_vcpu_arch *vcpu = &v->arch;
818 void *shared_kaddr;
463656c0 819 unsigned long this_tsc_khz;
18068523
GOC		 820
821 if ((!vcpu->time_page))
822 return;
823
463656c0
AK		 824 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
825 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
826 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
827 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 828 }
463656c0 829 put_cpu_var(cpu_tsc_khz);
50d0a0f9 830
18068523
GOC		 831 /* Keep irq disabled to prevent changes to the clock */
832 local_irq_save(flags);
af24a4e4 833 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 834 ktime_get_ts(&ts);
923de3cf 835 monotonic_to_bootbased(&ts);
18068523
GOC		 836 local_irq_restore(flags);
837
838 /* With all the info we got, fill in the values */
839
840 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 841 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
842
18068523
GOC		 843 /*
844 * The interface expects us to write an even number signaling that the
845 * update is finished. Since the guest won't see the intermediate
50d0a0f9 846 * state, we just increase by 2 at the end.
18068523 847 */
50d0a0f9 848 vcpu->hv_clock.version += 2;
18068523
GOC		 849
850 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
851
852 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 853 sizeof(vcpu->hv_clock));
18068523
GOC		 854
855 kunmap_atomic(shared_kaddr, KM_USER0);
856
857 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
858}
859
c8076604
GH		 860static int kvm_request_guest_time_update(struct kvm_vcpu *v)
861{
862 struct kvm_vcpu_arch *vcpu = &v->arch;
863
864 if (!vcpu->time_page)
865 return 0;
866 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
867 return 1;
868}
869
9ba075a6
AK		 870static bool msr_mtrr_valid(unsigned msr)
871{
872 switch (msr) {
873 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
874 case MSR_MTRRfix64K_00000:
875 case MSR_MTRRfix16K_80000:
876 case MSR_MTRRfix16K_A0000:
877 case MSR_MTRRfix4K_C0000:
878 case MSR_MTRRfix4K_C8000:
879 case MSR_MTRRfix4K_D0000:
880 case MSR_MTRRfix4K_D8000:
881 case MSR_MTRRfix4K_E0000:
882 case MSR_MTRRfix4K_E8000:
883 case MSR_MTRRfix4K_F0000:
884 case MSR_MTRRfix4K_F8000:
885 case MSR_MTRRdefType:
886 case MSR_IA32_CR_PAT:
887 return true;
888 case 0x2f8:
889 return true;
890 }
891 return false;
892}
893
d6289b93
MT		 894static bool valid_pat_type(unsigned t)
895{
896 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
897}
898
899static bool valid_mtrr_type(unsigned t)
900{
901 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
902}
903
904static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
905{
906 int i;
907
908 if (!msr_mtrr_valid(msr))
909 return false;
910
911 if (msr == MSR_IA32_CR_PAT) {
912 for (i = 0; i < 8; i++)
913 if (!valid_pat_type((data >> (i * 8)) & 0xff))
914 return false;
915 return true;
916 } else if (msr == MSR_MTRRdefType) {
917 if (data & ~0xcff)
918 return false;
919 return valid_mtrr_type(data & 0xff);
920 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
921 for (i = 0; i < 8 ; i++)
922 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
923 return false;
924 return true;
925 }
926
927 /* variable MTRRs */
928 return valid_mtrr_type(data & 0xff);
929}
930
9ba075a6
AK		 931static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
932{
0bed3b56
SY		 933 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
934
d6289b93 935 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 936 return 1;
937
0bed3b56
SY		 938 if (msr == MSR_MTRRdefType) {
939 vcpu->arch.mtrr_state.def_type = data;
940 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
941 } else if (msr == MSR_MTRRfix64K_00000)
942 p[0] = data;
943 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
944 p[1 + msr - MSR_MTRRfix16K_80000] = data;
945 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
946 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
947 else if (msr == MSR_IA32_CR_PAT)
948 vcpu->arch.pat = data;
949 else { /* Variable MTRRs */
950 int idx, is_mtrr_mask;
951 u64 *pt;
952
953 idx = (msr - 0x200) / 2;
954 is_mtrr_mask = msr - 0x200 - 2 * idx;
955 if (!is_mtrr_mask)
956 pt =
957 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
958 else
959 pt =
960 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
961 *pt = data;
962 }
963
964 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 965 return 0;
966}
15c4a640 967
890ca9ae 968static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 969{
890ca9ae
HY		 970 u64 mcg_cap = vcpu->arch.mcg_cap;
971 unsigned bank_num = mcg_cap & 0xff;
972
15c4a640 973 switch (msr) {
15c4a640 974 case MSR_IA32_MCG_STATUS:
890ca9ae 975 vcpu->arch.mcg_status = data;
15c4a640 976 break;
c7ac679c 977 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 978 if (!(mcg_cap & MCG_CTL_P))
979 return 1;
980 if (data != 0 && data != ~(u64)0)
981 return -1;
982 vcpu->arch.mcg_ctl = data;
983 break;
984 default:
985 if (msr >= MSR_IA32_MC0_CTL &&
986 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
987 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 988 /* only 0 or all 1s can be written to IA32_MCi_CTL
989 * some Linux kernels though clear bit 10 in bank 4 to
990 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
991 * this to avoid an uncatched #GP in the guest
992 */
890ca9ae 993 if ((offset & 0x3) == 0 &&
114be429 994 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 995 return -1;
996 vcpu->arch.mce_banks[offset] = data;
997 break;
998 }
999 return 1;
1000 }
1001 return 0;
1002}
1003
ffde22ac
ES		 1004static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1005{
1006 struct kvm *kvm = vcpu->kvm;
1007 int lm = is_long_mode(vcpu);
1008 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1009 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1010 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1011 : kvm->arch.xen_hvm_config.blob_size_32;
1012 u32 page_num = data & ~PAGE_MASK;
1013 u64 page_addr = data & PAGE_MASK;
1014 u8 *page;
1015 int r;
1016
1017 r = -E2BIG;
1018 if (page_num >= blob_size)
1019 goto out;
1020 r = -ENOMEM;
1021 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1022 if (!page)
1023 goto out;
1024 r = -EFAULT;
1025 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1026 goto out_free;
1027 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1028 goto out_free;
1029 r = 0;
1030out_free:
1031 kfree(page);
1032out:
1033 return r;
1034}
1035
55cd8e5a
GN		 1036static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1037{
1038 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1039}
1040
1041static bool kvm_hv_msr_partition_wide(u32 msr)
1042{
1043 bool r = false;
1044 switch (msr) {
1045 case HV_X64_MSR_GUEST_OS_ID:
1046 case HV_X64_MSR_HYPERCALL:
1047 r = true;
1048 break;
1049 }
1050
1051 return r;
1052}
1053
1054static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1055{
1056 struct kvm *kvm = vcpu->kvm;
1057
1058 switch (msr) {
1059 case HV_X64_MSR_GUEST_OS_ID:
1060 kvm->arch.hv_guest_os_id = data;
1061 /* setting guest os id to zero disables hypercall page */
1062 if (!kvm->arch.hv_guest_os_id)
1063 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1064 break;
1065 case HV_X64_MSR_HYPERCALL: {
1066 u64 gfn;
1067 unsigned long addr;
1068 u8 instructions[4];
1069
1070 /* if guest os id is not set hypercall should remain disabled */
1071 if (!kvm->arch.hv_guest_os_id)
1072 break;
1073 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1074 kvm->arch.hv_hypercall = data;
1075 break;
1076 }
1077 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1078 addr = gfn_to_hva(kvm, gfn);
1079 if (kvm_is_error_hva(addr))
1080 return 1;
1081 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1082 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1083 if (copy_to_user((void __user *)addr, instructions, 4))
1084 return 1;
1085 kvm->arch.hv_hypercall = data;
1086 break;
1087 }
1088 default:
1089 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1090 "data 0x%llx\n", msr, data);
1091 return 1;
1092 }
1093 return 0;
1094}
1095
1096static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1097{
10388a07
GN		 1098 switch (msr) {
1099 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1100 unsigned long addr;
55cd8e5a 1101
10388a07
GN		 1102 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1103 vcpu->arch.hv_vapic = data;
1104 break;
1105 }
1106 addr = gfn_to_hva(vcpu->kvm, data >>
1107 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1108 if (kvm_is_error_hva(addr))
1109 return 1;
1110 if (clear_user((void __user *)addr, PAGE_SIZE))
1111 return 1;
1112 vcpu->arch.hv_vapic = data;
1113 break;
1114 }
1115 case HV_X64_MSR_EOI:
1116 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1117 case HV_X64_MSR_ICR:
1118 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1119 case HV_X64_MSR_TPR:
1120 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1121 default:
1122 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1123 "data 0x%llx\n", msr, data);
1124 return 1;
1125 }
1126
1127 return 0;
55cd8e5a
GN		 1128}
1129
15c4a640
CO		 1130int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1131{
1132 switch (msr) {
15c4a640
CO		 1133 case MSR_EFER:
1134 set_efer(vcpu, data);
1135 break;
8f1589d9
AP		 1136 case MSR_K7_HWCR:
1137 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1138 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1139 if (data != 0) {
1140 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1141 data);
1142 return 1;
1143 }
15c4a640 1144 break;
f7c6d140
AP		 1145 case MSR_FAM10H_MMIO_CONF_BASE:
1146 if (data != 0) {
1147 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1148 "0x%llx\n", data);
1149 return 1;
1150 }
15c4a640 1151 break;
c323c0e5 1152 case MSR_AMD64_NB_CFG:
c7ac679c 1153 break;
b5e2fec0
AG		 1154 case MSR_IA32_DEBUGCTLMSR:
1155 if (!data) {
1156 /* We support the non-activated case already */
1157 break;
1158 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1159 /* Values other than LBR and BTF are vendor-specific,
1160 thus reserved and should throw a #GP */
1161 return 1;
1162 }
1163 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1164 __func__, data);
1165 break;
15c4a640
CO		 1166 case MSR_IA32_UCODE_REV:
1167 case MSR_IA32_UCODE_WRITE:
61a6bd67 1168 case MSR_VM_HSAVE_PA:
6098ca93 1169 case MSR_AMD64_PATCH_LOADER:
15c4a640 1170 break;
9ba075a6
AK		 1171 case 0x200 ... 0x2ff:
1172 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1173 case MSR_IA32_APICBASE:
1174 kvm_set_apic_base(vcpu, data);
1175 break;
0105d1a5
GN		 1176 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1177 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1178 case MSR_IA32_MISC_ENABLE:
ad312c7c 1179 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1180 break;
18068523
GOC		 1181 case MSR_KVM_WALL_CLOCK:
1182 vcpu->kvm->arch.wall_clock = data;
1183 kvm_write_wall_clock(vcpu->kvm, data);
1184 break;
1185 case MSR_KVM_SYSTEM_TIME: {
1186 if (vcpu->arch.time_page) {
1187 kvm_release_page_dirty(vcpu->arch.time_page);
1188 vcpu->arch.time_page = NULL;
1189 }
1190
1191 vcpu->arch.time = data;
1192
1193 /* we verify if the enable bit is set... */
1194 if (!(data & 1))
1195 break;
1196
1197 /* ...but clean it before doing the actual write */
1198 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1199
18068523
GOC		 1200 vcpu->arch.time_page =
1201 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1202
1203 if (is_error_page(vcpu->arch.time_page)) {
1204 kvm_release_page_clean(vcpu->arch.time_page);
1205 vcpu->arch.time_page = NULL;
1206 }
1207
c8076604 1208 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1209 break;
1210 }
890ca9ae
HY		 1211 case MSR_IA32_MCG_CTL:
1212 case MSR_IA32_MCG_STATUS:
1213 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1214 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1215
1216 /* Performance counters are not protected by a CPUID bit,
1217 * so we should check all of them in the generic path for the sake of
1218 * cross vendor migration.
1219 * Writing a zero into the event select MSRs disables them,
1220 * which we perfectly emulate ;-). Any other value should be at least
1221 * reported, some guests depend on them.
1222 */
1223 case MSR_P6_EVNTSEL0:
1224 case MSR_P6_EVNTSEL1:
1225 case MSR_K7_EVNTSEL0:
1226 case MSR_K7_EVNTSEL1:
1227 case MSR_K7_EVNTSEL2:
1228 case MSR_K7_EVNTSEL3:
1229 if (data != 0)
1230 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1231 "0x%x data 0x%llx\n", msr, data);
1232 break;
1233 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1234 * so we ignore writes to make it happy.
1235 */
1236 case MSR_P6_PERFCTR0:
1237 case MSR_P6_PERFCTR1:
1238 case MSR_K7_PERFCTR0:
1239 case MSR_K7_PERFCTR1:
1240 case MSR_K7_PERFCTR2:
1241 case MSR_K7_PERFCTR3:
1242 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1243 "0x%x data 0x%llx\n", msr, data);
1244 break;
55cd8e5a
GN		 1245 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1246 if (kvm_hv_msr_partition_wide(msr)) {
1247 int r;
1248 mutex_lock(&vcpu->kvm->lock);
1249 r = set_msr_hyperv_pw(vcpu, msr, data);
1250 mutex_unlock(&vcpu->kvm->lock);
1251 return r;
1252 } else
1253 return set_msr_hyperv(vcpu, msr, data);
1254 break;
15c4a640 1255 default:
ffde22ac
ES		 1256 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1257 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1258 if (!ignore_msrs) {
1259 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1260 msr, data);
1261 return 1;
1262 } else {
1263 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1264 msr, data);
1265 break;
1266 }
15c4a640
CO		 1267 }
1268 return 0;
1269}
1270EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1271
1272
1273/*
1274 * Reads an msr value (of 'msr_index') into 'pdata'.
1275 * Returns 0 on success, non-0 otherwise.
1276 * Assumes vcpu_load() was already called.
1277 */
1278int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1279{
1280 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1281}
1282
9ba075a6
AK		 1283static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1284{
0bed3b56
SY		 1285 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1286
9ba075a6
AK		 1287 if (!msr_mtrr_valid(msr))
1288 return 1;
1289
0bed3b56
SY		 1290 if (msr == MSR_MTRRdefType)
1291 *pdata = vcpu->arch.mtrr_state.def_type +
1292 (vcpu->arch.mtrr_state.enabled << 10);
1293 else if (msr == MSR_MTRRfix64K_00000)
1294 *pdata = p[0];
1295 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1296 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1297 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1298 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1299 else if (msr == MSR_IA32_CR_PAT)
1300 *pdata = vcpu->arch.pat;
1301 else { /* Variable MTRRs */
1302 int idx, is_mtrr_mask;
1303 u64 *pt;
1304
1305 idx = (msr - 0x200) / 2;
1306 is_mtrr_mask = msr - 0x200 - 2 * idx;
1307 if (!is_mtrr_mask)
1308 pt =
1309 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1310 else
1311 pt =
1312 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1313 *pdata = *pt;
1314 }
1315
9ba075a6
AK		 1316 return 0;
1317}
1318
890ca9ae 1319static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1320{
1321 u64 data;
890ca9ae
HY		 1322 u64 mcg_cap = vcpu->arch.mcg_cap;
1323 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1324
1325 switch (msr) {
15c4a640
CO		 1326 case MSR_IA32_P5_MC_ADDR:
1327 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1328 data = 0;
1329 break;
15c4a640 1330 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1331 data = vcpu->arch.mcg_cap;
1332 break;
c7ac679c 1333 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1334 if (!(mcg_cap & MCG_CTL_P))
1335 return 1;
1336 data = vcpu->arch.mcg_ctl;
1337 break;
1338 case MSR_IA32_MCG_STATUS:
1339 data = vcpu->arch.mcg_status;
1340 break;
1341 default:
1342 if (msr >= MSR_IA32_MC0_CTL &&
1343 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1344 u32 offset = msr - MSR_IA32_MC0_CTL;
1345 data = vcpu->arch.mce_banks[offset];
1346 break;
1347 }
1348 return 1;
1349 }
1350 *pdata = data;
1351 return 0;
1352}
1353
55cd8e5a
GN		 1354static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1355{
1356 u64 data = 0;
1357 struct kvm *kvm = vcpu->kvm;
1358
1359 switch (msr) {
1360 case HV_X64_MSR_GUEST_OS_ID:
1361 data = kvm->arch.hv_guest_os_id;
1362 break;
1363 case HV_X64_MSR_HYPERCALL:
1364 data = kvm->arch.hv_hypercall;
1365 break;
1366 default:
1367 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1368 return 1;
1369 }
1370
1371 *pdata = data;
1372 return 0;
1373}
1374
1375static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1376{
1377 u64 data = 0;
1378
1379 switch (msr) {
1380 case HV_X64_MSR_VP_INDEX: {
1381 int r;
1382 struct kvm_vcpu *v;
1383 kvm_for_each_vcpu(r, v, vcpu->kvm)
1384 if (v == vcpu)
1385 data = r;
1386 break;
1387 }
10388a07
GN		 1388 case HV_X64_MSR_EOI:
1389 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1390 case HV_X64_MSR_ICR:
1391 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1392 case HV_X64_MSR_TPR:
1393 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1394 default:
1395 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1396 return 1;
1397 }
1398 *pdata = data;
1399 return 0;
1400}
1401
890ca9ae
HY		 1402int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1403{
1404 u64 data;
1405
1406 switch (msr) {
890ca9ae 1407 case MSR_IA32_PLATFORM_ID:
15c4a640 1408 case MSR_IA32_UCODE_REV:
15c4a640 1409 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1410 case MSR_IA32_DEBUGCTLMSR:
1411 case MSR_IA32_LASTBRANCHFROMIP:
1412 case MSR_IA32_LASTBRANCHTOIP:
1413 case MSR_IA32_LASTINTFROMIP:
1414 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1415 case MSR_K8_SYSCFG:
1416 case MSR_K7_HWCR:
61a6bd67 1417 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1418 case MSR_P6_PERFCTR0:
1419 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1420 case MSR_P6_EVNTSEL0:
1421 case MSR_P6_EVNTSEL1:
9e699624 1422 case MSR_K7_EVNTSEL0:
1f3ee616 1423 case MSR_K7_PERFCTR0:
1fdbd48c 1424 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1425 case MSR_AMD64_NB_CFG:
f7c6d140 1426 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1427 data = 0;
1428 break;
9ba075a6
AK		 1429 case MSR_MTRRcap:
1430 data = 0x500 | KVM_NR_VAR_MTRR;
1431 break;
1432 case 0x200 ... 0x2ff:
1433 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1434 case 0xcd: /* fsb frequency */
1435 data = 3;
1436 break;
1437 case MSR_IA32_APICBASE:
1438 data = kvm_get_apic_base(vcpu);
1439 break;
0105d1a5
GN		 1440 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1441 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1442 break;
15c4a640 1443 case MSR_IA32_MISC_ENABLE:
ad312c7c 1444 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1445 break;
847f0ad8
AG		 1446 case MSR_IA32_PERF_STATUS:
1447 /* TSC increment by tick */
1448 data = 1000ULL;
1449 /* CPU multiplier */
1450 data |= (((uint64_t)4ULL) << 40);
1451 break;
15c4a640 1452 case MSR_EFER:
f6801dff 1453 data = vcpu->arch.efer;
15c4a640 1454 break;
18068523
GOC		 1455 case MSR_KVM_WALL_CLOCK:
1456 data = vcpu->kvm->arch.wall_clock;
1457 break;
1458 case MSR_KVM_SYSTEM_TIME:
1459 data = vcpu->arch.time;
1460 break;
890ca9ae
HY		 1461 case MSR_IA32_P5_MC_ADDR:
1462 case MSR_IA32_P5_MC_TYPE:
1463 case MSR_IA32_MCG_CAP:
1464 case MSR_IA32_MCG_CTL:
1465 case MSR_IA32_MCG_STATUS:
1466 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1467 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1468 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1469 if (kvm_hv_msr_partition_wide(msr)) {
1470 int r;
1471 mutex_lock(&vcpu->kvm->lock);
1472 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1473 mutex_unlock(&vcpu->kvm->lock);
1474 return r;
1475 } else
1476 return get_msr_hyperv(vcpu, msr, pdata);
1477 break;
15c4a640 1478 default:
ed85c068
AP		 1479 if (!ignore_msrs) {
1480 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1481 return 1;
1482 } else {
1483 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1484 data = 0;
1485 }
1486 break;
15c4a640
CO		 1487 }
1488 *pdata = data;
1489 return 0;
1490}
1491EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1492
313a3dc7
CO		 1493/*
1494 * Read or write a bunch of msrs. All parameters are kernel addresses.
1495 *
1496 * @return number of msrs set successfully.
1497 */
1498static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1499 struct kvm_msr_entry *entries,
1500 int (*do_msr)(struct kvm_vcpu *vcpu,
1501 unsigned index, u64 *data))
1502{
f656ce01 1503 int i, idx;
313a3dc7
CO		 1504
1505 vcpu_load(vcpu);
1506
f656ce01 1507 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1508 for (i = 0; i < msrs->nmsrs; ++i)
1509 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1510 break;
f656ce01 1511 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1512
1513 vcpu_put(vcpu);
1514
1515 return i;
1516}
1517
1518/*
1519 * Read or write a bunch of msrs. Parameters are user addresses.
1520 *
1521 * @return number of msrs set successfully.
1522 */
1523static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1524 int (*do_msr)(struct kvm_vcpu *vcpu,
1525 unsigned index, u64 *data),
1526 int writeback)
1527{
1528 struct kvm_msrs msrs;
1529 struct kvm_msr_entry *entries;
1530 int r, n;
1531 unsigned size;
1532
1533 r = -EFAULT;
1534 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1535 goto out;
1536
1537 r = -E2BIG;
1538 if (msrs.nmsrs >= MAX_IO_MSRS)
1539 goto out;
1540
1541 r = -ENOMEM;
1542 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1543 entries = vmalloc(size);
1544 if (!entries)
1545 goto out;
1546
1547 r = -EFAULT;
1548 if (copy_from_user(entries, user_msrs->entries, size))
1549 goto out_free;
1550
1551 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1552 if (r < 0)
1553 goto out_free;
1554
1555 r = -EFAULT;
1556 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1557 goto out_free;
1558
1559 r = n;
1560
1561out_free:
1562 vfree(entries);
1563out:
1564 return r;
1565}
1566
018d00d2
ZX		 1567int kvm_dev_ioctl_check_extension(long ext)
1568{
1569 int r;
1570
1571 switch (ext) {
1572 case KVM_CAP_IRQCHIP:
1573 case KVM_CAP_HLT:
1574 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1575 case KVM_CAP_SET_TSS_ADDR:
07716717 1576 case KVM_CAP_EXT_CPUID:
c8076604 1577 case KVM_CAP_CLOCKSOURCE:
7837699f 1578 case KVM_CAP_PIT:
a28e4f5a 1579 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1580 case KVM_CAP_MP_STATE:
ed848624 1581 case KVM_CAP_SYNC_MMU:
52d939a0 1582 case KVM_CAP_REINJECT_CONTROL:
4925663a 1583 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1584 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1585 case KVM_CAP_IRQFD:
d34e6b17 1586 case KVM_CAP_IOEVENTFD:
c5ff41ce 1587 case KVM_CAP_PIT2:
e9f42757 1588 case KVM_CAP_PIT_STATE2:
b927a3ce 1589 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1590 case KVM_CAP_XEN_HVM:
afbcf7ab 1591 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1592 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1593 case KVM_CAP_HYPERV:
10388a07 1594 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1595 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1596 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1597 case KVM_CAP_DEBUGREGS:
d2be1651 1598 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1599 r = 1;
1600 break;
542472b5
LV		 1601 case KVM_CAP_COALESCED_MMIO:
1602 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1603 break;
774ead3a
AK		 1604 case KVM_CAP_VAPIC:
1605 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1606 break;
f725230a
AK		 1607 case KVM_CAP_NR_VCPUS:
1608 r = KVM_MAX_VCPUS;
1609 break;
a988b910
AK		 1610 case KVM_CAP_NR_MEMSLOTS:
1611 r = KVM_MEMORY_SLOTS;
1612 break;
a68a6a72
MT		 1613 case KVM_CAP_PV_MMU: /* obsolete */
1614 r = 0;
2f333bcb 1615 break;
62c476c7 1616 case KVM_CAP_IOMMU:
19de40a8 1617 r = iommu_found();
62c476c7 1618 break;
890ca9ae
HY		 1619 case KVM_CAP_MCE:
1620 r = KVM_MAX_MCE_BANKS;
1621 break;
018d00d2
ZX		 1622 default:
1623 r = 0;
1624 break;
1625 }
1626 return r;
1627
1628}
1629
043405e1
CO		 1630long kvm_arch_dev_ioctl(struct file *filp,
1631 unsigned int ioctl, unsigned long arg)
1632{
1633 void __user *argp = (void __user *)arg;
1634 long r;
1635
1636 switch (ioctl) {
1637 case KVM_GET_MSR_INDEX_LIST: {
1638 struct kvm_msr_list __user *user_msr_list = argp;
1639 struct kvm_msr_list msr_list;
1640 unsigned n;
1641
1642 r = -EFAULT;
1643 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1644 goto out;
1645 n = msr_list.nmsrs;
1646 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1647 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1648 goto out;
1649 r = -E2BIG;
e125e7b6 1650 if (n < msr_list.nmsrs)
043405e1
CO		 1651 goto out;
1652 r = -EFAULT;
1653 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1654 num_msrs_to_save * sizeof(u32)))
1655 goto out;
e125e7b6 1656 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1657 &emulated_msrs,
1658 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1659 goto out;
1660 r = 0;
1661 break;
1662 }
674eea0f
AK		 1663 case KVM_GET_SUPPORTED_CPUID: {
1664 struct kvm_cpuid2 __user *cpuid_arg = argp;
1665 struct kvm_cpuid2 cpuid;
1666
1667 r = -EFAULT;
1668 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1669 goto out;
1670 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1671 cpuid_arg->entries);
674eea0f
AK		 1672 if (r)
1673 goto out;
1674
1675 r = -EFAULT;
1676 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1677 goto out;
1678 r = 0;
1679 break;
1680 }
890ca9ae
HY		 1681 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1682 u64 mce_cap;
1683
1684 mce_cap = KVM_MCE_CAP_SUPPORTED;
1685 r = -EFAULT;
1686 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1687 goto out;
1688 r = 0;
1689 break;
1690 }
043405e1
CO		 1691 default:
1692 r = -EINVAL;
1693 }
1694out:
1695 return r;
1696}
1697
313a3dc7
CO		 1698void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1699{
1700 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1701 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1702 unsigned long khz = cpufreq_quick_get(cpu);
1703 if (!khz)
1704 khz = tsc_khz;
1705 per_cpu(cpu_tsc_khz, cpu) = khz;
1706 }
c8076604 1707 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1708}
1709
1710void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1711{
9327fd11 1712 kvm_put_guest_fpu(vcpu);
02daab21 1713 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1714}
1715
07716717 1716static int is_efer_nx(void)
313a3dc7 1717{
e286e86e 1718 unsigned long long efer = 0;
313a3dc7 1719
e286e86e 1720 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1721 return efer & EFER_NX;
1722}
1723
1724static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1725{
1726 int i;
1727 struct kvm_cpuid_entry2 *e, *entry;
1728
313a3dc7 1729 entry = NULL;
ad312c7c
ZX		 1730 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1731 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1732 if (e->function == 0x80000001) {
1733 entry = e;
1734 break;
1735 }
1736 }
07716717 1737 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1738 entry->edx &= ~(1 << 20);
1739 printk(KERN_INFO "kvm: guest NX capability removed\n");
1740 }
1741}
1742
07716717 1743/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1744static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1745 struct kvm_cpuid *cpuid,
1746 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1747{
1748 int r, i;
1749 struct kvm_cpuid_entry *cpuid_entries;
1750
1751 r = -E2BIG;
1752 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1753 goto out;
1754 r = -ENOMEM;
1755 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1756 if (!cpuid_entries)
1757 goto out;
1758 r = -EFAULT;
1759 if (copy_from_user(cpuid_entries, entries,
1760 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1761 goto out_free;
1762 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1763 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1764 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1765 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1766 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1767 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1768 vcpu->arch.cpuid_entries[i].index = 0;
1769 vcpu->arch.cpuid_entries[i].flags = 0;
1770 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1771 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1772 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1773 }
1774 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1775 cpuid_fix_nx_cap(vcpu);
1776 r = 0;
fc61b800 1777 kvm_apic_set_version(vcpu);
0e851880 1778 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1779
1780out_free:
1781 vfree(cpuid_entries);
1782out:
1783 return r;
1784}
1785
1786static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1787 struct kvm_cpuid2 *cpuid,
1788 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1789{
1790 int r;
1791
1792 r = -E2BIG;
1793 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1794 goto out;
1795 r = -EFAULT;
ad312c7c 1796 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1797 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1798 goto out;
ad312c7c 1799 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1800 kvm_apic_set_version(vcpu);
0e851880 1801 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1802 return 0;
1803
1804out:
1805 return r;
1806}
1807
07716717 1808static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1809 struct kvm_cpuid2 *cpuid,
1810 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1811{
1812 int r;
1813
1814 r = -E2BIG;
ad312c7c 1815 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1816 goto out;
1817 r = -EFAULT;
ad312c7c 1818 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1819 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1820 goto out;
1821 return 0;
1822
1823out:
ad312c7c 1824 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1825 return r;
1826}
1827
07716717 1828static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1829 u32 index)
07716717
DK		 1830{
1831 entry->function = function;
1832 entry->index = index;
1833 cpuid_count(entry->function, entry->index,
19355475 1834 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1835 entry->flags = 0;
1836}
1837
7faa4ee1
AK		 1838#define F(x) bit(X86_FEATURE_##x)
1839
07716717
DK		 1840static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1841 u32 index, int *nent, int maxnent)
1842{
7faa4ee1 1843 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1844#ifdef CONFIG_X86_64
17cc3935
SY		 1845 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1846 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1847 unsigned f_lm = F(LM);
1848#else
17cc3935 1849 unsigned f_gbpages = 0;
7faa4ee1 1850 unsigned f_lm = 0;
07716717 1851#endif
4e47c7a6 1852 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1853
1854 /* cpuid 1.edx */
1855 const u32 kvm_supported_word0_x86_features =
1856 F(FPU) | F(VME) | F(DE) | F(PSE) |
1857 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1858 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1859 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1860 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1861 0 /* Reserved, DS, ACPI */ | F(MMX) |
1862 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1863 0 /* HTT, TM, Reserved, PBE */;
1864 /* cpuid 0x80000001.edx */
1865 const u32 kvm_supported_word1_x86_features =
1866 F(FPU) | F(VME) | F(DE) | F(PSE) |
1867 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1868 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1869 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1870 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1871 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1872 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1873 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1874 /* cpuid 1.ecx */
1875 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1876 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1877 0 /* DS-CPL, VMX, SMX, EST */ |
1878 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1879 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1880 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1881 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1882 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1883 /* cpuid 0x80000001.ecx */
07716717 1884 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1885 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1886 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1887 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1888 0 /* SKINIT */ | 0 /* WDT */;
07716717 1889
19355475 1890 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1891 get_cpu();
1892 do_cpuid_1_ent(entry, function, index);
1893 ++*nent;
1894
1895 switch (function) {
1896 case 0:
1897 entry->eax = min(entry->eax, (u32)0xb);
1898 break;
1899 case 1:
1900 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1901 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1902 /* we support x2apic emulation even if host does not support
1903 * it since we emulate x2apic in software */
1904 entry->ecx |= F(X2APIC);
07716717
DK		 1905 break;
1906 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1907 * may return different values. This forces us to get_cpu() before
1908 * issuing the first command, and also to emulate this annoying behavior
1909 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1910 case 2: {
1911 int t, times = entry->eax & 0xff;
1912
1913 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1914 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1915 for (t = 1; t < times && *nent < maxnent; ++t) {
1916 do_cpuid_1_ent(&entry[t], function, 0);
1917 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1918 ++*nent;
1919 }
1920 break;
1921 }
1922 /* function 4 and 0xb have additional index. */
1923 case 4: {
14af3f3c 1924 int i, cache_type;
07716717
DK		 1925
1926 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1927 /* read more entries until cache_type is zero */
14af3f3c
HH		 1928 for (i = 1; *nent < maxnent; ++i) {
1929 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1930 if (!cache_type)
1931 break;
14af3f3c
HH		 1932 do_cpuid_1_ent(&entry[i], function, i);
1933 entry[i].flags |=
07716717
DK		 1934 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1935 ++*nent;
1936 }
1937 break;
1938 }
1939 case 0xb: {
14af3f3c 1940 int i, level_type;
07716717
DK		 1941
1942 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1943 /* read more entries until level_type is zero */
14af3f3c 1944 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1945 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1946 if (!level_type)
1947 break;
14af3f3c
HH		 1948 do_cpuid_1_ent(&entry[i], function, i);
1949 entry[i].flags |=
07716717
DK		 1950 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1951 ++*nent;
1952 }
1953 break;
1954 }
1955 case 0x80000000:
1956 entry->eax = min(entry->eax, 0x8000001a);
1957 break;
1958 case 0x80000001:
1959 entry->edx &= kvm_supported_word1_x86_features;
1960 entry->ecx &= kvm_supported_word6_x86_features;
1961 break;
1962 }
d4330ef2
JR		 1963
1964 kvm_x86_ops->set_supported_cpuid(function, entry);
1965
07716717
DK		 1966 put_cpu();
1967}
1968
7faa4ee1
AK		 1969#undef F
1970
674eea0f 1971static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1972 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1973{
1974 struct kvm_cpuid_entry2 *cpuid_entries;
1975 int limit, nent = 0, r = -E2BIG;
1976 u32 func;
1977
1978 if (cpuid->nent < 1)
1979 goto out;
6a544355
AK		 1980 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1981 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1982 r = -ENOMEM;
1983 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1984 if (!cpuid_entries)
1985 goto out;
1986
1987 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1988 limit = cpuid_entries[0].eax;
1989 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1990 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1991 &nent, cpuid->nent);
07716717
DK		 1992 r = -E2BIG;
1993 if (nent >= cpuid->nent)
1994 goto out_free;
1995
1996 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1997 limit = cpuid_entries[nent - 1].eax;
1998 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1999 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2000 &nent, cpuid->nent);
cb007648
MM		 2001 r = -E2BIG;
2002 if (nent >= cpuid->nent)
2003 goto out_free;
2004
07716717
DK		 2005 r = -EFAULT;
2006 if (copy_to_user(entries, cpuid_entries,
19355475 2007 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2008 goto out_free;
2009 cpuid->nent = nent;
2010 r = 0;
2011
2012out_free:
2013 vfree(cpuid_entries);
2014out:
2015 return r;
2016}
2017
313a3dc7
CO		 2018static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2019 struct kvm_lapic_state *s)
2020{
2021 vcpu_load(vcpu);
ad312c7c 2022 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2023 vcpu_put(vcpu);
2024
2025 return 0;
2026}
2027
2028static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2029 struct kvm_lapic_state *s)
2030{
2031 vcpu_load(vcpu);
ad312c7c 2032 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2033 kvm_apic_post_state_restore(vcpu);
cb142eb7 2034 update_cr8_intercept(vcpu);
313a3dc7
CO		 2035 vcpu_put(vcpu);
2036
2037 return 0;
2038}
2039
f77bc6a4
ZX		 2040static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2041 struct kvm_interrupt *irq)
2042{
2043 if (irq->irq < 0 || irq->irq >= 256)
2044 return -EINVAL;
2045 if (irqchip_in_kernel(vcpu->kvm))
2046 return -ENXIO;
2047 vcpu_load(vcpu);
2048
66fd3f7f 2049 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2050
2051 vcpu_put(vcpu);
2052
2053 return 0;
2054}
2055
c4abb7c9
JK		 2056static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2057{
2058 vcpu_load(vcpu);
2059 kvm_inject_nmi(vcpu);
2060 vcpu_put(vcpu);
2061
2062 return 0;
2063}
2064
b209749f
AK		 2065static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2066 struct kvm_tpr_access_ctl *tac)
2067{
2068 if (tac->flags)
2069 return -EINVAL;
2070 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2071 return 0;
2072}
2073
890ca9ae
HY		 2074static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2075 u64 mcg_cap)
2076{
2077 int r;
2078 unsigned bank_num = mcg_cap & 0xff, bank;
2079
2080 r = -EINVAL;
a9e38c3e 2081 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2082 goto out;
2083 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2084 goto out;
2085 r = 0;
2086 vcpu->arch.mcg_cap = mcg_cap;
2087 /* Init IA32_MCG_CTL to all 1s */
2088 if (mcg_cap & MCG_CTL_P)
2089 vcpu->arch.mcg_ctl = ~(u64)0;
2090 /* Init IA32_MCi_CTL to all 1s */
2091 for (bank = 0; bank < bank_num; bank++)
2092 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2093out:
2094 return r;
2095}
2096
2097static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2098 struct kvm_x86_mce *mce)
2099{
2100 u64 mcg_cap = vcpu->arch.mcg_cap;
2101 unsigned bank_num = mcg_cap & 0xff;
2102 u64 *banks = vcpu->arch.mce_banks;
2103
2104 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2105 return -EINVAL;
2106 /*
2107 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2108 * reporting is disabled
2109 */
2110 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2111 vcpu->arch.mcg_ctl != ~(u64)0)
2112 return 0;
2113 banks += 4 * mce->bank;
2114 /*
2115 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2116 * reporting is disabled for the bank
2117 */
2118 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2119 return 0;
2120 if (mce->status & MCI_STATUS_UC) {
2121 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2122 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2123 printk(KERN_DEBUG "kvm: set_mce: "
2124 "injects mce exception while "
2125 "previous one is in progress!\n");
2126 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2127 return 0;
2128 }
2129 if (banks[1] & MCI_STATUS_VAL)
2130 mce->status |= MCI_STATUS_OVER;
2131 banks[2] = mce->addr;
2132 banks[3] = mce->misc;
2133 vcpu->arch.mcg_status = mce->mcg_status;
2134 banks[1] = mce->status;
2135 kvm_queue_exception(vcpu, MC_VECTOR);
2136 } else if (!(banks[1] & MCI_STATUS_VAL)
2137 || !(banks[1] & MCI_STATUS_UC)) {
2138 if (banks[1] & MCI_STATUS_VAL)
2139 mce->status |= MCI_STATUS_OVER;
2140 banks[2] = mce->addr;
2141 banks[3] = mce->misc;
2142 banks[1] = mce->status;
2143 } else
2144 banks[1] |= MCI_STATUS_OVER;
2145 return 0;
2146}
2147
3cfc3092
JK		 2148static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2149 struct kvm_vcpu_events *events)
2150{
2151 vcpu_load(vcpu);
2152
03b82a30
JK		 2153 events->exception.injected =
2154 vcpu->arch.exception.pending &&
2155 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2156 events->exception.nr = vcpu->arch.exception.nr;
2157 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2158 events->exception.error_code = vcpu->arch.exception.error_code;
2159
03b82a30
JK		 2160 events->interrupt.injected =
2161 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2162 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2163 events->interrupt.soft = 0;
48005f64
JK		 2164 events->interrupt.shadow =
2165 kvm_x86_ops->get_interrupt_shadow(vcpu,
2166 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2167
2168 events->nmi.injected = vcpu->arch.nmi_injected;
2169 events->nmi.pending = vcpu->arch.nmi_pending;
2170 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2171
2172 events->sipi_vector = vcpu->arch.sipi_vector;
2173
dab4b911 2174 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2175 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2176 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2177
2178 vcpu_put(vcpu);
2179}
2180
2181static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2182 struct kvm_vcpu_events *events)
2183{
dab4b911 2184 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2185 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2186 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2187 return -EINVAL;
2188
2189 vcpu_load(vcpu);
2190
2191 vcpu->arch.exception.pending = events->exception.injected;
2192 vcpu->arch.exception.nr = events->exception.nr;
2193 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2194 vcpu->arch.exception.error_code = events->exception.error_code;
2195
2196 vcpu->arch.interrupt.pending = events->interrupt.injected;
2197 vcpu->arch.interrupt.nr = events->interrupt.nr;
2198 vcpu->arch.interrupt.soft = events->interrupt.soft;
2199 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2200 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2201 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2202 kvm_x86_ops->set_interrupt_shadow(vcpu,
2203 events->interrupt.shadow);
3cfc3092
JK		 2204
2205 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2206 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2207 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2208 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2209
dab4b911
JK		 2210 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2211 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2212
2213 vcpu_put(vcpu);
2214
2215 return 0;
2216}
2217
a1efbe77
JK		 2218static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2219 struct kvm_debugregs *dbgregs)
2220{
2221 vcpu_load(vcpu);
2222
2223 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2224 dbgregs->dr6 = vcpu->arch.dr6;
2225 dbgregs->dr7 = vcpu->arch.dr7;
2226 dbgregs->flags = 0;
2227
2228 vcpu_put(vcpu);
2229}
2230
2231static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2232 struct kvm_debugregs *dbgregs)
2233{
2234 if (dbgregs->flags)
2235 return -EINVAL;
2236
2237 vcpu_load(vcpu);
2238
2239 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2240 vcpu->arch.dr6 = dbgregs->dr6;
2241 vcpu->arch.dr7 = dbgregs->dr7;
2242
2243 vcpu_put(vcpu);
2244
2245 return 0;
2246}
2247
313a3dc7
CO		 2248long kvm_arch_vcpu_ioctl(struct file *filp,
2249 unsigned int ioctl, unsigned long arg)
2250{
2251 struct kvm_vcpu *vcpu = filp->private_data;
2252 void __user *argp = (void __user *)arg;
2253 int r;
b772ff36 2254 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2255
2256 switch (ioctl) {
2257 case KVM_GET_LAPIC: {
2204ae3c
MT		 2258 r = -EINVAL;
2259 if (!vcpu->arch.apic)
2260 goto out;
b772ff36 2261 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2262
b772ff36
DH		 2263 r = -ENOMEM;
2264 if (!lapic)
2265 goto out;
2266 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2267 if (r)
2268 goto out;
2269 r = -EFAULT;
b772ff36 2270 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2271 goto out;
2272 r = 0;
2273 break;
2274 }
2275 case KVM_SET_LAPIC: {
2204ae3c
MT		 2276 r = -EINVAL;
2277 if (!vcpu->arch.apic)
2278 goto out;
b772ff36
DH		 2279 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2280 r = -ENOMEM;
2281 if (!lapic)
2282 goto out;
313a3dc7 2283 r = -EFAULT;
b772ff36 2284 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2285 goto out;
b772ff36 2286 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2287 if (r)
2288 goto out;
2289 r = 0;
2290 break;
2291 }
f77bc6a4
ZX		 2292 case KVM_INTERRUPT: {
2293 struct kvm_interrupt irq;
2294
2295 r = -EFAULT;
2296 if (copy_from_user(&irq, argp, sizeof irq))
2297 goto out;
2298 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2299 if (r)
2300 goto out;
2301 r = 0;
2302 break;
2303 }
c4abb7c9
JK		 2304 case KVM_NMI: {
2305 r = kvm_vcpu_ioctl_nmi(vcpu);
2306 if (r)
2307 goto out;
2308 r = 0;
2309 break;
2310 }
313a3dc7
CO		 2311 case KVM_SET_CPUID: {
2312 struct kvm_cpuid __user *cpuid_arg = argp;
2313 struct kvm_cpuid cpuid;
2314
2315 r = -EFAULT;
2316 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2317 goto out;
2318 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2319 if (r)
2320 goto out;
2321 break;
2322 }
07716717
DK		 2323 case KVM_SET_CPUID2: {
2324 struct kvm_cpuid2 __user *cpuid_arg = argp;
2325 struct kvm_cpuid2 cpuid;
2326
2327 r = -EFAULT;
2328 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2329 goto out;
2330 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2331 cpuid_arg->entries);
07716717
DK		 2332 if (r)
2333 goto out;
2334 break;
2335 }
2336 case KVM_GET_CPUID2: {
2337 struct kvm_cpuid2 __user *cpuid_arg = argp;
2338 struct kvm_cpuid2 cpuid;
2339
2340 r = -EFAULT;
2341 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2342 goto out;
2343 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2344 cpuid_arg->entries);
07716717
DK		 2345 if (r)
2346 goto out;
2347 r = -EFAULT;
2348 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2349 goto out;
2350 r = 0;
2351 break;
2352 }
313a3dc7
CO		 2353 case KVM_GET_MSRS:
2354 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2355 break;
2356 case KVM_SET_MSRS:
2357 r = msr_io(vcpu, argp, do_set_msr, 0);
2358 break;
b209749f
AK		 2359 case KVM_TPR_ACCESS_REPORTING: {
2360 struct kvm_tpr_access_ctl tac;
2361
2362 r = -EFAULT;
2363 if (copy_from_user(&tac, argp, sizeof tac))
2364 goto out;
2365 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2366 if (r)
2367 goto out;
2368 r = -EFAULT;
2369 if (copy_to_user(argp, &tac, sizeof tac))
2370 goto out;
2371 r = 0;
2372 break;
2373 };
b93463aa
AK		 2374 case KVM_SET_VAPIC_ADDR: {
2375 struct kvm_vapic_addr va;
2376
2377 r = -EINVAL;
2378 if (!irqchip_in_kernel(vcpu->kvm))
2379 goto out;
2380 r = -EFAULT;
2381 if (copy_from_user(&va, argp, sizeof va))
2382 goto out;
2383 r = 0;
2384 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2385 break;
2386 }
890ca9ae
HY		 2387 case KVM_X86_SETUP_MCE: {
2388 u64 mcg_cap;
2389
2390 r = -EFAULT;
2391 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2392 goto out;
2393 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2394 break;
2395 }
2396 case KVM_X86_SET_MCE: {
2397 struct kvm_x86_mce mce;
2398
2399 r = -EFAULT;
2400 if (copy_from_user(&mce, argp, sizeof mce))
2401 goto out;
2402 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2403 break;
2404 }
3cfc3092
JK		 2405 case KVM_GET_VCPU_EVENTS: {
2406 struct kvm_vcpu_events events;
2407
2408 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2409
2410 r = -EFAULT;
2411 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2412 break;
2413 r = 0;
2414 break;
2415 }
2416 case KVM_SET_VCPU_EVENTS: {
2417 struct kvm_vcpu_events events;
2418
2419 r = -EFAULT;
2420 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2421 break;
2422
2423 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2424 break;
2425 }
a1efbe77
JK		 2426 case KVM_GET_DEBUGREGS: {
2427 struct kvm_debugregs dbgregs;
2428
2429 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2430
2431 r = -EFAULT;
2432 if (copy_to_user(argp, &dbgregs,
2433 sizeof(struct kvm_debugregs)))
2434 break;
2435 r = 0;
2436 break;
2437 }
2438 case KVM_SET_DEBUGREGS: {
2439 struct kvm_debugregs dbgregs;
2440
2441 r = -EFAULT;
2442 if (copy_from_user(&dbgregs, argp,
2443 sizeof(struct kvm_debugregs)))
2444 break;
2445
2446 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2447 break;
2448 }
313a3dc7
CO		 2449 default:
2450 r = -EINVAL;
2451 }
2452out:
7a6ce84c 2453 kfree(lapic);
313a3dc7
CO		 2454 return r;
2455}
2456
1fe779f8
CO		 2457static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2458{
2459 int ret;
2460
2461 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2462 return -1;
2463 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2464 return ret;
2465}
2466
b927a3ce
SY		 2467static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2468 u64 ident_addr)
2469{
2470 kvm->arch.ept_identity_map_addr = ident_addr;
2471 return 0;
2472}
2473
1fe779f8
CO		 2474static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2475 u32 kvm_nr_mmu_pages)
2476{
2477 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2478 return -EINVAL;
2479
79fac95e 2480 mutex_lock(&kvm->slots_lock);
7c8a83b7 2481 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2482
2483 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2484 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2485
7c8a83b7 2486 spin_unlock(&kvm->mmu_lock);
79fac95e 2487 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2488 return 0;
2489}
2490
2491static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2492{
f05e70ac 2493 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2494}
2495
a983fb23
MT		 2496gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2497{
2498 int i;
2499 struct kvm_mem_alias *alias;
2500 struct kvm_mem_aliases *aliases;
2501
90d83dc3 2502 aliases = kvm_aliases(kvm);
a983fb23
MT		 2503
2504 for (i = 0; i < aliases->naliases; ++i) {
2505 alias = &aliases->aliases[i];
2506 if (alias->flags & KVM_ALIAS_INVALID)
2507 continue;
2508 if (gfn >= alias->base_gfn
2509 && gfn < alias->base_gfn + alias->npages)
2510 return alias->target_gfn + gfn - alias->base_gfn;
2511 }
2512 return gfn;
2513}
2514
e9f85cde
ZX		 2515gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2516{
2517 int i;
2518 struct kvm_mem_alias *alias;
a983fb23
MT		 2519 struct kvm_mem_aliases *aliases;
2520
90d83dc3 2521 aliases = kvm_aliases(kvm);
e9f85cde 2522
fef9cce0
MT		 2523 for (i = 0; i < aliases->naliases; ++i) {
2524 alias = &aliases->aliases[i];
e9f85cde
ZX		 2525 if (gfn >= alias->base_gfn
2526 && gfn < alias->base_gfn + alias->npages)
2527 return alias->target_gfn + gfn - alias->base_gfn;
2528 }
2529 return gfn;
2530}
2531
1fe779f8
CO		 2532/*
2533 * Set a new alias region. Aliases map a portion of physical memory into
2534 * another portion. This is useful for memory windows, for example the PC
2535 * VGA region.
2536 */
2537static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2538 struct kvm_memory_alias *alias)
2539{
2540 int r, n;
2541 struct kvm_mem_alias *p;
a983fb23 2542 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2543
2544 r = -EINVAL;
2545 /* General sanity checks */
2546 if (alias->memory_size & (PAGE_SIZE - 1))
2547 goto out;
2548 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2549 goto out;
2550 if (alias->slot >= KVM_ALIAS_SLOTS)
2551 goto out;
2552 if (alias->guest_phys_addr + alias->memory_size
2553 < alias->guest_phys_addr)
2554 goto out;
2555 if (alias->target_phys_addr + alias->memory_size
2556 < alias->target_phys_addr)
2557 goto out;
2558
a983fb23
MT		 2559 r = -ENOMEM;
2560 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2561 if (!aliases)
2562 goto out;
2563
79fac95e 2564 mutex_lock(&kvm->slots_lock);
1fe779f8 2565
a983fb23
MT		 2566 /* invalidate any gfn reference in case of deletion/shrinking */
2567 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2568 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2569 old_aliases = kvm->arch.aliases;
2570 rcu_assign_pointer(kvm->arch.aliases, aliases);
2571 synchronize_srcu_expedited(&kvm->srcu);
2572 kvm_mmu_zap_all(kvm);
2573 kfree(old_aliases);
2574
2575 r = -ENOMEM;
2576 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2577 if (!aliases)
2578 goto out_unlock;
2579
2580 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2581
2582 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2583 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2584 p->npages = alias->memory_size >> PAGE_SHIFT;
2585 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2586 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2587
2588 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2589 if (aliases->aliases[n - 1].npages)
1fe779f8 2590 break;
fef9cce0 2591 aliases->naliases = n;
1fe779f8 2592
a983fb23
MT		 2593 old_aliases = kvm->arch.aliases;
2594 rcu_assign_pointer(kvm->arch.aliases, aliases);
2595 synchronize_srcu_expedited(&kvm->srcu);
2596 kfree(old_aliases);
2597 r = 0;
1fe779f8 2598
a983fb23 2599out_unlock:
79fac95e 2600 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2601out:
2602 return r;
2603}
2604
2605static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2606{
2607 int r;
2608
2609 r = 0;
2610 switch (chip->chip_id) {
2611 case KVM_IRQCHIP_PIC_MASTER:
2612 memcpy(&chip->chip.pic,
2613 &pic_irqchip(kvm)->pics[0],
2614 sizeof(struct kvm_pic_state));
2615 break;
2616 case KVM_IRQCHIP_PIC_SLAVE:
2617 memcpy(&chip->chip.pic,
2618 &pic_irqchip(kvm)->pics[1],
2619 sizeof(struct kvm_pic_state));
2620 break;
2621 case KVM_IRQCHIP_IOAPIC:
eba0226b 2622 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2623 break;
2624 default:
2625 r = -EINVAL;
2626 break;
2627 }
2628 return r;
2629}
2630
2631static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2632{
2633 int r;
2634
2635 r = 0;
2636 switch (chip->chip_id) {
2637 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2638 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2639 memcpy(&pic_irqchip(kvm)->pics[0],
2640 &chip->chip.pic,
2641 sizeof(struct kvm_pic_state));
fa8273e9 2642 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2643 break;
2644 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2645 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2646 memcpy(&pic_irqchip(kvm)->pics[1],
2647 &chip->chip.pic,
2648 sizeof(struct kvm_pic_state));
fa8273e9 2649 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2650 break;
2651 case KVM_IRQCHIP_IOAPIC:
eba0226b 2652 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2653 break;
2654 default:
2655 r = -EINVAL;
2656 break;
2657 }
2658 kvm_pic_update_irq(pic_irqchip(kvm));
2659 return r;
2660}
2661
e0f63cb9
SY		 2662static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2663{
2664 int r = 0;
2665
894a9c55 2666 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2667 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2668 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2669 return r;
2670}
2671
2672static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2673{
2674 int r = 0;
2675
894a9c55 2676 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2677 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2678 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2679 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2680 return r;
2681}
2682
2683static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2684{
2685 int r = 0;
2686
2687 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2688 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2689 sizeof(ps->channels));
2690 ps->flags = kvm->arch.vpit->pit_state.flags;
2691 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2692 return r;
2693}
2694
2695static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2696{
2697 int r = 0, start = 0;
2698 u32 prev_legacy, cur_legacy;
2699 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2700 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2701 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2702 if (!prev_legacy && cur_legacy)
2703 start = 1;
2704 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2705 sizeof(kvm->arch.vpit->pit_state.channels));
2706 kvm->arch.vpit->pit_state.flags = ps->flags;
2707 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2708 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2709 return r;
2710}
2711
52d939a0
MT		 2712static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2713 struct kvm_reinject_control *control)
2714{
2715 if (!kvm->arch.vpit)
2716 return -ENXIO;
894a9c55 2717 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2718 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2719 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2720 return 0;
2721}
2722
5bb064dc
ZX		 2723/*
2724 * Get (and clear) the dirty memory log for a memory slot.
2725 */
2726int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2727 struct kvm_dirty_log *log)
2728{
87bf6e7d 2729 int r, i;
5bb064dc 2730 struct kvm_memory_slot *memslot;
87bf6e7d 2731 unsigned long n;
b050b015
MT		 2732 unsigned long is_dirty = 0;
2733 unsigned long *dirty_bitmap = NULL;
5bb064dc 2734
79fac95e 2735 mutex_lock(&kvm->slots_lock);
5bb064dc 2736
b050b015
MT		 2737 r = -EINVAL;
2738 if (log->slot >= KVM_MEMORY_SLOTS)
2739 goto out;
2740
2741 memslot = &kvm->memslots->memslots[log->slot];
2742 r = -ENOENT;
2743 if (!memslot->dirty_bitmap)
2744 goto out;
2745
87bf6e7d 2746 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2747
2748 r = -ENOMEM;
2749 dirty_bitmap = vmalloc(n);
2750 if (!dirty_bitmap)
5bb064dc 2751 goto out;
b050b015
MT		 2752 memset(dirty_bitmap, 0, n);
2753
2754 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2755 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2756
2757 /* If nothing is dirty, don't bother messing with page tables. */
2758 if (is_dirty) {
b050b015
MT		 2759 struct kvm_memslots *slots, *old_slots;
2760
7c8a83b7 2761 spin_lock(&kvm->mmu_lock);
5bb064dc 2762 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2763 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2764
2765 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2766 if (!slots)
2767 goto out_free;
2768
2769 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2770 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2771
2772 old_slots = kvm->memslots;
2773 rcu_assign_pointer(kvm->memslots, slots);
2774 synchronize_srcu_expedited(&kvm->srcu);
2775 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2776 kfree(old_slots);
5bb064dc 2777 }
b050b015 2778
5bb064dc 2779 r = 0;
b050b015
MT		 2780 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2781 r = -EFAULT;
2782out_free:
2783 vfree(dirty_bitmap);
5bb064dc 2784out:
79fac95e 2785 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2786 return r;
2787}
2788
1fe779f8
CO		 2789long kvm_arch_vm_ioctl(struct file *filp,
2790 unsigned int ioctl, unsigned long arg)
2791{
2792 struct kvm *kvm = filp->private_data;
2793 void __user *argp = (void __user *)arg;
367e1319 2794 int r = -ENOTTY;
f0d66275
DH		 2795 /*
2796 * This union makes it completely explicit to gcc-3.x
2797 * that these two variables' stack usage should be
2798 * combined, not added together.
2799 */
2800 union {
2801 struct kvm_pit_state ps;
e9f42757 2802 struct kvm_pit_state2 ps2;
f0d66275 2803 struct kvm_memory_alias alias;
c5ff41ce 2804 struct kvm_pit_config pit_config;
f0d66275 2805 } u;
1fe779f8
CO		 2806
2807 switch (ioctl) {
2808 case KVM_SET_TSS_ADDR:
2809 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2810 if (r < 0)
2811 goto out;
2812 break;
b927a3ce
SY		 2813 case KVM_SET_IDENTITY_MAP_ADDR: {
2814 u64 ident_addr;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2818 goto out;
2819 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2820 if (r < 0)
2821 goto out;
2822 break;
2823 }
1fe779f8
CO		 2824 case KVM_SET_MEMORY_REGION: {
2825 struct kvm_memory_region kvm_mem;
2826 struct kvm_userspace_memory_region kvm_userspace_mem;
2827
2828 r = -EFAULT;
2829 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2830 goto out;
2831 kvm_userspace_mem.slot = kvm_mem.slot;
2832 kvm_userspace_mem.flags = kvm_mem.flags;
2833 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2834 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2835 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2836 if (r)
2837 goto out;
2838 break;
2839 }
2840 case KVM_SET_NR_MMU_PAGES:
2841 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2842 if (r)
2843 goto out;
2844 break;
2845 case KVM_GET_NR_MMU_PAGES:
2846 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2847 break;
f0d66275 2848 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2849 r = -EFAULT;
f0d66275 2850 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2851 goto out;
f0d66275 2852 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2853 if (r)
2854 goto out;
2855 break;
3ddea128
MT		 2856 case KVM_CREATE_IRQCHIP: {
2857 struct kvm_pic *vpic;
2858
2859 mutex_lock(&kvm->lock);
2860 r = -EEXIST;
2861 if (kvm->arch.vpic)
2862 goto create_irqchip_unlock;
1fe779f8 2863 r = -ENOMEM;
3ddea128
MT		 2864 vpic = kvm_create_pic(kvm);
2865 if (vpic) {
1fe779f8
CO		 2866 r = kvm_ioapic_init(kvm);
2867 if (r) {
72bb2fcd
WY		 2868 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2869 &vpic->dev);
3ddea128
MT		 2870 kfree(vpic);
2871 goto create_irqchip_unlock;
1fe779f8
CO		 2872 }
2873 } else
3ddea128
MT		 2874 goto create_irqchip_unlock;
2875 smp_wmb();
2876 kvm->arch.vpic = vpic;
2877 smp_wmb();
399ec807
AK		 2878 r = kvm_setup_default_irq_routing(kvm);
2879 if (r) {
3ddea128 2880 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2881 kvm_ioapic_destroy(kvm);
2882 kvm_destroy_pic(kvm);
3ddea128 2883 mutex_unlock(&kvm->irq_lock);
399ec807 2884 }
3ddea128
MT		 2885 create_irqchip_unlock:
2886 mutex_unlock(&kvm->lock);
1fe779f8 2887 break;
3ddea128 2888 }
7837699f 2889 case KVM_CREATE_PIT:
c5ff41ce
JK		 2890 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2891 goto create_pit;
2892 case KVM_CREATE_PIT2:
2893 r = -EFAULT;
2894 if (copy_from_user(&u.pit_config, argp,
2895 sizeof(struct kvm_pit_config)))
2896 goto out;
2897 create_pit:
79fac95e 2898 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2899 r = -EEXIST;
2900 if (kvm->arch.vpit)
2901 goto create_pit_unlock;
7837699f 2902 r = -ENOMEM;
c5ff41ce 2903 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2904 if (kvm->arch.vpit)
2905 r = 0;
269e05e4 2906 create_pit_unlock:
79fac95e 2907 mutex_unlock(&kvm->slots_lock);
7837699f 2908 break;
4925663a 2909 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2910 case KVM_IRQ_LINE: {
2911 struct kvm_irq_level irq_event;
2912
2913 r = -EFAULT;
2914 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2915 goto out;
160d2f6c 2916 r = -ENXIO;
1fe779f8 2917 if (irqchip_in_kernel(kvm)) {
4925663a 2918 __s32 status;
4925663a
GN		 2919 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2920 irq_event.irq, irq_event.level);
4925663a 2921 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2922 r = -EFAULT;
4925663a
GN		 2923 irq_event.status = status;
2924 if (copy_to_user(argp, &irq_event,
2925 sizeof irq_event))
2926 goto out;
2927 }
1fe779f8
CO		 2928 r = 0;
2929 }
2930 break;
2931 }
2932 case KVM_GET_IRQCHIP: {
2933 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2934 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2935
f0d66275
DH		 2936 r = -ENOMEM;
2937 if (!chip)
1fe779f8 2938 goto out;
f0d66275
DH		 2939 r = -EFAULT;
2940 if (copy_from_user(chip, argp, sizeof *chip))
2941 goto get_irqchip_out;
1fe779f8
CO		 2942 r = -ENXIO;
2943 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2944 goto get_irqchip_out;
2945 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2946 if (r)
f0d66275 2947 goto get_irqchip_out;
1fe779f8 2948 r = -EFAULT;
f0d66275
DH		 2949 if (copy_to_user(argp, chip, sizeof *chip))
2950 goto get_irqchip_out;
1fe779f8 2951 r = 0;
f0d66275
DH		 2952 get_irqchip_out:
2953 kfree(chip);
2954 if (r)
2955 goto out;
1fe779f8
CO		 2956 break;
2957 }
2958 case KVM_SET_IRQCHIP: {
2959 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2960 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2961
f0d66275
DH		 2962 r = -ENOMEM;
2963 if (!chip)
1fe779f8 2964 goto out;
f0d66275
DH		 2965 r = -EFAULT;
2966 if (copy_from_user(chip, argp, sizeof *chip))
2967 goto set_irqchip_out;
1fe779f8
CO		 2968 r = -ENXIO;
2969 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2970 goto set_irqchip_out;
2971 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2972 if (r)
f0d66275 2973 goto set_irqchip_out;
1fe779f8 2974 r = 0;
f0d66275
DH		 2975 set_irqchip_out:
2976 kfree(chip);
2977 if (r)
2978 goto out;
1fe779f8
CO		 2979 break;
2980 }
e0f63cb9 2981 case KVM_GET_PIT: {
e0f63cb9 2982 r = -EFAULT;
f0d66275 2983 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2984 goto out;
2985 r = -ENXIO;
2986 if (!kvm->arch.vpit)
2987 goto out;
f0d66275 2988 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2989 if (r)
2990 goto out;
2991 r = -EFAULT;
f0d66275 2992 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2993 goto out;
2994 r = 0;
2995 break;
2996 }
2997 case KVM_SET_PIT: {
e0f63cb9 2998 r = -EFAULT;
f0d66275 2999 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3000 goto out;
3001 r = -ENXIO;
3002 if (!kvm->arch.vpit)
3003 goto out;
f0d66275 3004 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3005 if (r)
3006 goto out;
3007 r = 0;
3008 break;
3009 }
e9f42757
BK		 3010 case KVM_GET_PIT2: {
3011 r = -ENXIO;
3012 if (!kvm->arch.vpit)
3013 goto out;
3014 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3015 if (r)
3016 goto out;
3017 r = -EFAULT;
3018 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3019 goto out;
3020 r = 0;
3021 break;
3022 }
3023 case KVM_SET_PIT2: {
3024 r = -EFAULT;
3025 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3026 goto out;
3027 r = -ENXIO;
3028 if (!kvm->arch.vpit)
3029 goto out;
3030 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3031 if (r)
3032 goto out;
3033 r = 0;
3034 break;
3035 }
52d939a0
MT		 3036 case KVM_REINJECT_CONTROL: {
3037 struct kvm_reinject_control control;
3038 r = -EFAULT;
3039 if (copy_from_user(&control, argp, sizeof(control)))
3040 goto out;
3041 r = kvm_vm_ioctl_reinject(kvm, &control);
3042 if (r)
3043 goto out;
3044 r = 0;
3045 break;
3046 }
ffde22ac
ES		 3047 case KVM_XEN_HVM_CONFIG: {
3048 r = -EFAULT;
3049 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3050 sizeof(struct kvm_xen_hvm_config)))
3051 goto out;
3052 r = -EINVAL;
3053 if (kvm->arch.xen_hvm_config.flags)
3054 goto out;
3055 r = 0;
3056 break;
3057 }
afbcf7ab
GC		 3058 case KVM_SET_CLOCK: {
3059 struct timespec now;
3060 struct kvm_clock_data user_ns;
3061 u64 now_ns;
3062 s64 delta;
3063
3064 r = -EFAULT;
3065 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3066 goto out;
3067
3068 r = -EINVAL;
3069 if (user_ns.flags)
3070 goto out;
3071
3072 r = 0;
3073 ktime_get_ts(&now);
3074 now_ns = timespec_to_ns(&now);
3075 delta = user_ns.clock - now_ns;
3076 kvm->arch.kvmclock_offset = delta;
3077 break;
3078 }
3079 case KVM_GET_CLOCK: {
3080 struct timespec now;
3081 struct kvm_clock_data user_ns;
3082 u64 now_ns;
3083
3084 ktime_get_ts(&now);
3085 now_ns = timespec_to_ns(&now);
3086 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3087 user_ns.flags = 0;
3088
3089 r = -EFAULT;
3090 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3091 goto out;
3092 r = 0;
3093 break;
3094 }
3095
1fe779f8
CO		 3096 default:
3097 ;
3098 }
3099out:
3100 return r;
3101}
3102
a16b043c 3103static void kvm_init_msr_list(void)
043405e1
CO		 3104{
3105 u32 dummy[2];
3106 unsigned i, j;
3107
e3267cbb
GC		 3108 /* skip the first msrs in the list. KVM-specific */
3109 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3110 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3111 continue;
3112 if (j < i)
3113 msrs_to_save[j] = msrs_to_save[i];
3114 j++;
3115 }
3116 num_msrs_to_save = j;
3117}
3118
bda9020e
MT		 3119static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3120 const void *v)
bbd9b64e 3121{
bda9020e
MT		 3122 if (vcpu->arch.apic &&
3123 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3124 return 0;
bbd9b64e 3125
e93f8a0f 3126 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3127}
3128
bda9020e 3129static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3130{
bda9020e
MT		 3131 if (vcpu->arch.apic &&
3132 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3133 return 0;
bbd9b64e 3134
e93f8a0f 3135 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3136}
3137
2dafc6c2
GN		 3138static void kvm_set_segment(struct kvm_vcpu *vcpu,
3139 struct kvm_segment *var, int seg)
3140{
3141 kvm_x86_ops->set_segment(vcpu, var, seg);
3142}
3143
3144void kvm_get_segment(struct kvm_vcpu *vcpu,
3145 struct kvm_segment *var, int seg)
3146{
3147 kvm_x86_ops->get_segment(vcpu, var, seg);
3148}
3149
1871c602
GN		 3150gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3151{
3152 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3153 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3154}
3155
3156 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3157{
3158 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3159 access |= PFERR_FETCH_MASK;
3160 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3161}
3162
3163gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3164{
3165 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3166 access |= PFERR_WRITE_MASK;
3167 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3168}
3169
3170/* uses this to access any guest's mapped memory without checking CPL */
3171gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3172{
3173 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3174}
3175
3176static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3177 struct kvm_vcpu *vcpu, u32 access,
3178 u32 *error)
bbd9b64e
CO		 3179{
3180 void *data = val;
10589a46 3181 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3182
3183 while (bytes) {
1871c602 3184 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3185 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3186 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3187 int ret;
3188
10589a46
MT		 3189 if (gpa == UNMAPPED_GVA) {
3190 r = X86EMUL_PROPAGATE_FAULT;
3191 goto out;
3192 }
77c2002e 3193 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3194 if (ret < 0) {
3195 r = X86EMUL_UNHANDLEABLE;
3196 goto out;
3197 }
bbd9b64e 3198
77c2002e
IE		 3199 bytes -= toread;
3200 data += toread;
3201 addr += toread;
bbd9b64e 3202 }
10589a46 3203out:
10589a46 3204 return r;
bbd9b64e 3205}
77c2002e 3206
1871c602
GN		 3207/* used for instruction fetching */
3208static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3209 struct kvm_vcpu *vcpu, u32 *error)
3210{
3211 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3212 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3213 access | PFERR_FETCH_MASK, error);
3214}
3215
3216static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3217 struct kvm_vcpu *vcpu, u32 *error)
3218{
3219 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3220 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3221 error);
3222}
3223
3224static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3225 struct kvm_vcpu *vcpu, u32 *error)
3226{
3227 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3228}
3229
7972995b 3230static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3231 unsigned int bytes,
7972995b 3232 struct kvm_vcpu *vcpu,
2dafc6c2 3233 u32 *error)
77c2002e
IE		 3234{
3235 void *data = val;
3236 int r = X86EMUL_CONTINUE;
3237
3238 while (bytes) {
7972995b
GN		 3239 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3240 PFERR_WRITE_MASK, error);
77c2002e
IE		 3241 unsigned offset = addr & (PAGE_SIZE-1);
3242 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3243 int ret;
3244
3245 if (gpa == UNMAPPED_GVA) {
3246 r = X86EMUL_PROPAGATE_FAULT;
3247 goto out;
3248 }
3249 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3250 if (ret < 0) {
3251 r = X86EMUL_UNHANDLEABLE;
3252 goto out;
3253 }
3254
3255 bytes -= towrite;
3256 data += towrite;
3257 addr += towrite;
3258 }
3259out:
3260 return r;
3261}
3262
bbd9b64e
CO		 3263static int emulator_read_emulated(unsigned long addr,
3264 void *val,
3265 unsigned int bytes,
3266 struct kvm_vcpu *vcpu)
3267{
bbd9b64e 3268 gpa_t gpa;
1871c602 3269 u32 error_code;
bbd9b64e
CO		 3270
3271 if (vcpu->mmio_read_completed) {
3272 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3273 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3274 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3275 vcpu->mmio_read_completed = 0;
3276 return X86EMUL_CONTINUE;
3277 }
3278
1871c602
GN		 3279 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3280
3281 if (gpa == UNMAPPED_GVA) {
3282 kvm_inject_page_fault(vcpu, addr, error_code);
3283 return X86EMUL_PROPAGATE_FAULT;
3284 }
bbd9b64e
CO		 3285
3286 /* For APIC access vmexit */
3287 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3288 goto mmio;
3289
1871c602 3290 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3291 == X86EMUL_CONTINUE)
bbd9b64e 3292 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3293
3294mmio:
3295 /*
3296 * Is this MMIO handled locally?
3297 */
aec51dc4
AK		 3298 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3299 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3300 return X86EMUL_CONTINUE;
3301 }
aec51dc4
AK		 3302
3303 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3304
3305 vcpu->mmio_needed = 1;
3306 vcpu->mmio_phys_addr = gpa;
3307 vcpu->mmio_size = bytes;
3308 vcpu->mmio_is_write = 0;
3309
3310 return X86EMUL_UNHANDLEABLE;
3311}
3312
3200f405 3313int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3314 const void *val, int bytes)
bbd9b64e
CO		 3315{
3316 int ret;
3317
3318 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3319 if (ret < 0)
bbd9b64e 3320 return 0;
ad218f85 3321 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3322 return 1;
3323}
3324
3325static int emulator_write_emulated_onepage(unsigned long addr,
3326 const void *val,
3327 unsigned int bytes,
8f6abd06 3328 struct kvm_vcpu *vcpu)
bbd9b64e 3329{
10589a46 3330 gpa_t gpa;
1871c602 3331 u32 error_code;
10589a46 3332
1871c602 3333 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3334
3335 if (gpa == UNMAPPED_GVA) {
1871c602 3336 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3337 return X86EMUL_PROPAGATE_FAULT;
3338 }
3339
3340 /* For APIC access vmexit */
3341 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3342 goto mmio;
3343
3344 if (emulator_write_phys(vcpu, gpa, val, bytes))
3345 return X86EMUL_CONTINUE;
3346
3347mmio:
aec51dc4 3348 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3349 /*
3350 * Is this MMIO handled locally?
3351 */
bda9020e 3352 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3353 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3354
3355 vcpu->mmio_needed = 1;
3356 vcpu->mmio_phys_addr = gpa;
3357 vcpu->mmio_size = bytes;
3358 vcpu->mmio_is_write = 1;
3359 memcpy(vcpu->mmio_data, val, bytes);
3360
3361 return X86EMUL_CONTINUE;
3362}
3363
8f6abd06
GN		 3364int emulator_write_emulated(unsigned long addr,
3365 const void *val,
3366 unsigned int bytes,
3367 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3368{
3369 /* Crossing a page boundary? */
3370 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3371 int rc, now;
3372
3373 now = -addr & ~PAGE_MASK;
8f6abd06 3374 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
bbd9b64e
CO		 3375 if (rc != X86EMUL_CONTINUE)
3376 return rc;
3377 addr += now;
3378 val += now;
3379 bytes -= now;
3380 }
8f6abd06 3381 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
bbd9b64e
CO		 3382}
3383EXPORT_SYMBOL_GPL(emulator_write_emulated);
3384
daea3e73
AK		 3385#define CMPXCHG_TYPE(t, ptr, old, new) \
3386 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3387
3388#ifdef CONFIG_X86_64
3389# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3390#else
3391# define CMPXCHG64(ptr, old, new) \
9749a6c0 3392 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3393#endif
3394
bbd9b64e
CO		 3395static int emulator_cmpxchg_emulated(unsigned long addr,
3396 const void *old,
3397 const void *new,
3398 unsigned int bytes,
3399 struct kvm_vcpu *vcpu)
3400{
daea3e73
AK		 3401 gpa_t gpa;
3402 struct page *page;
3403 char *kaddr;
3404 bool exchanged;
2bacc55c 3405
daea3e73
AK		 3406 /* guests cmpxchg8b have to be emulated atomically */
3407 if (bytes > 8 || (bytes & (bytes - 1)))
3408 goto emul_write;
10589a46 3409
daea3e73 3410 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3411
daea3e73
AK		 3412 if (gpa == UNMAPPED_GVA ||
3413 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3414 goto emul_write;
2bacc55c 3415
daea3e73
AK		 3416 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3417 goto emul_write;
72dc67a6 3418
daea3e73 3419 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3420
daea3e73
AK		 3421 kaddr = kmap_atomic(page, KM_USER0);
3422 kaddr += offset_in_page(gpa);
3423 switch (bytes) {
3424 case 1:
3425 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3426 break;
3427 case 2:
3428 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3429 break;
3430 case 4:
3431 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3432 break;
3433 case 8:
3434 exchanged = CMPXCHG64(kaddr, old, new);
3435 break;
3436 default:
3437 BUG();
2bacc55c 3438 }
daea3e73
AK		 3439 kunmap_atomic(kaddr, KM_USER0);
3440 kvm_release_page_dirty(page);
3441
3442 if (!exchanged)
3443 return X86EMUL_CMPXCHG_FAILED;
3444
8f6abd06
GN		 3445 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3446
3447 return X86EMUL_CONTINUE;
4a5f48f6 3448
3200f405 3449emul_write:
daea3e73 3450 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3451
bbd9b64e
CO		 3452 return emulator_write_emulated(addr, new, bytes, vcpu);
3453}
3454
cf8f70bf
GN		 3455static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3456{
3457 /* TODO: String I/O for in kernel device */
3458 int r;
3459
3460 if (vcpu->arch.pio.in)
3461 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3462 vcpu->arch.pio.size, pd);
3463 else
3464 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3465 vcpu->arch.pio.port, vcpu->arch.pio.size,
3466 pd);
3467 return r;
3468}
3469
3470
3471static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3472 unsigned int count, struct kvm_vcpu *vcpu)
3473{
7972995b 3474 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3475 goto data_avail;
3476
3477 trace_kvm_pio(1, port, size, 1);
3478
3479 vcpu->arch.pio.port = port;
3480 vcpu->arch.pio.in = 1;
7972995b 3481 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3482 vcpu->arch.pio.size = size;
3483
3484 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3485 data_avail:
3486 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3487 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3488 return 1;
3489 }
3490
3491 vcpu->run->exit_reason = KVM_EXIT_IO;
3492 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3493 vcpu->run->io.size = size;
3494 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3495 vcpu->run->io.count = count;
3496 vcpu->run->io.port = port;
3497
3498 return 0;
3499}
3500
3501static int emulator_pio_out_emulated(int size, unsigned short port,
3502 const void *val, unsigned int count,
3503 struct kvm_vcpu *vcpu)
3504{
3505 trace_kvm_pio(0, port, size, 1);
3506
3507 vcpu->arch.pio.port = port;
3508 vcpu->arch.pio.in = 0;
7972995b 3509 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3510 vcpu->arch.pio.size = size;
3511
3512 memcpy(vcpu->arch.pio_data, val, size * count);
3513
3514 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3515 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3516 return 1;
3517 }
3518
3519 vcpu->run->exit_reason = KVM_EXIT_IO;
3520 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3521 vcpu->run->io.size = size;
3522 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3523 vcpu->run->io.count = count;
3524 vcpu->run->io.port = port;
3525
3526 return 0;
3527}
3528
bbd9b64e
CO		 3529static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3530{
3531 return kvm_x86_ops->get_segment_base(vcpu, seg);
3532}
3533
3534int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3535{
a7052897 3536 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3537 return X86EMUL_CONTINUE;
3538}
3539
3540int emulate_clts(struct kvm_vcpu *vcpu)
3541{
4d4ec087 3542 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3543 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3544 return X86EMUL_CONTINUE;
3545}
3546
3547int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3548{
020df079 3549 return kvm_get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3550}
3551
3552int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3553{
3554 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3555
020df079 3556 return kvm_set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3557}
3558
3559void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3560{
bbd9b64e 3561 u8 opcodes[4];
5fdbf976 3562 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3563 unsigned long rip_linear;
3564
f76c710d 3565 if (!printk_ratelimit())
bbd9b64e
CO		 3566 return;
3567
25be4608
GC		 3568 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3569
1871c602 3570 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3571
3572 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3573 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3574}
3575EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3576
52a46617
GN		 3577static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3578{
3579 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3580}
3581
3582static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3583{
3584 unsigned long value;
3585
3586 switch (cr) {
3587 case 0:
3588 value = kvm_read_cr0(vcpu);
3589 break;
3590 case 2:
3591 value = vcpu->arch.cr2;
3592 break;
3593 case 3:
3594 value = vcpu->arch.cr3;
3595 break;
3596 case 4:
3597 value = kvm_read_cr4(vcpu);
3598 break;
3599 case 8:
3600 value = kvm_get_cr8(vcpu);
3601 break;
3602 default:
3603 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3604 return 0;
3605 }
3606
3607 return value;
3608}
3609
3610static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3611{
3612 switch (cr) {
3613 case 0:
3614 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3615 break;
3616 case 2:
3617 vcpu->arch.cr2 = val;
3618 break;
3619 case 3:
3620 kvm_set_cr3(vcpu, val);
3621 break;
3622 case 4:
3623 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3624 break;
3625 case 8:
3626 kvm_set_cr8(vcpu, val & 0xfUL);
3627 break;
3628 default:
3629 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3630 }
3631}
3632
9c537244
GN		 3633static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3634{
3635 return kvm_x86_ops->get_cpl(vcpu);
3636}
3637
2dafc6c2
GN		 3638static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3639{
3640 kvm_x86_ops->get_gdt(vcpu, dt);
3641}
3642
3643static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3644 struct kvm_vcpu *vcpu)
3645{
3646 struct kvm_segment var;
3647
3648 kvm_get_segment(vcpu, &var, seg);
3649
3650 if (var.unusable)
3651 return false;
3652
3653 if (var.g)
3654 var.limit >>= 12;
3655 set_desc_limit(desc, var.limit);
3656 set_desc_base(desc, (unsigned long)var.base);
3657 desc->type = var.type;
3658 desc->s = var.s;
3659 desc->dpl = var.dpl;
3660 desc->p = var.present;
3661 desc->avl = var.avl;
3662 desc->l = var.l;
3663 desc->d = var.db;
3664 desc->g = var.g;
3665
3666 return true;
3667}
3668
3669static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3670 struct kvm_vcpu *vcpu)
3671{
3672 struct kvm_segment var;
3673
3674 /* needed to preserve selector */
3675 kvm_get_segment(vcpu, &var, seg);
3676
3677 var.base = get_desc_base(desc);
3678 var.limit = get_desc_limit(desc);
3679 if (desc->g)
3680 var.limit = (var.limit << 12) | 0xfff;
3681 var.type = desc->type;
3682 var.present = desc->p;
3683 var.dpl = desc->dpl;
3684 var.db = desc->d;
3685 var.s = desc->s;
3686 var.l = desc->l;
3687 var.g = desc->g;
3688 var.avl = desc->avl;
3689 var.present = desc->p;
3690 var.unusable = !var.present;
3691 var.padding = 0;
3692
3693 kvm_set_segment(vcpu, &var, seg);
3694 return;
3695}
3696
3697static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3698{
3699 struct kvm_segment kvm_seg;
3700
3701 kvm_get_segment(vcpu, &kvm_seg, seg);
3702 return kvm_seg.selector;
3703}
3704
3705static void emulator_set_segment_selector(u16 sel, int seg,
3706 struct kvm_vcpu *vcpu)
3707{
3708 struct kvm_segment kvm_seg;
3709
3710 kvm_get_segment(vcpu, &kvm_seg, seg);
3711 kvm_seg.selector = sel;
3712 kvm_set_segment(vcpu, &kvm_seg, seg);
3713}
3714
482ac18a
GN		 3715static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3716{
3717 kvm_x86_ops->set_rflags(vcpu, rflags);
3718}
3719
14af3f3c 3720static struct x86_emulate_ops emulate_ops = {
1871c602 3721 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3722 .write_std = kvm_write_guest_virt_system,
1871c602 3723 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3724 .read_emulated = emulator_read_emulated,
3725 .write_emulated = emulator_write_emulated,
3726 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3727 .pio_in_emulated = emulator_pio_in_emulated,
3728 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3729 .get_cached_descriptor = emulator_get_cached_descriptor,
3730 .set_cached_descriptor = emulator_set_cached_descriptor,
3731 .get_segment_selector = emulator_get_segment_selector,
3732 .set_segment_selector = emulator_set_segment_selector,
3733 .get_gdt = emulator_get_gdt,
52a46617
GN		 3734 .get_cr = emulator_get_cr,
3735 .set_cr = emulator_set_cr,
9c537244 3736 .cpl = emulator_get_cpl,
482ac18a 3737 .set_rflags = emulator_set_rflags,
bbd9b64e
CO		 3738};
3739
5fdbf976
MT		 3740static void cache_all_regs(struct kvm_vcpu *vcpu)
3741{
3742 kvm_register_read(vcpu, VCPU_REGS_RAX);
3743 kvm_register_read(vcpu, VCPU_REGS_RSP);
3744 kvm_register_read(vcpu, VCPU_REGS_RIP);
3745 vcpu->arch.regs_dirty = ~0;
3746}
3747
bbd9b64e 3748int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3749 unsigned long cr2,
3750 u16 error_code,
571008da 3751 int emulation_type)
bbd9b64e 3752{
310b5d30 3753 int r, shadow_mask;
571008da 3754 struct decode_cache *c;
851ba692 3755 struct kvm_run *run = vcpu->run;
bbd9b64e 3756
26eef70c 3757 kvm_clear_exception_queue(vcpu);
ad312c7c 3758 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3759 /*
56e82318 3760 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3761 * instead of direct ->regs accesses, can save hundred cycles
3762 * on Intel for instructions that don't read/change RSP, for
3763 * for example.
3764 */
3765 cache_all_regs(vcpu);
bbd9b64e
CO		 3766
3767 vcpu->mmio_is_write = 0;
bbd9b64e 3768
571008da 3769 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3770 int cs_db, cs_l;
3771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3772
ad312c7c 3773 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3774 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3775 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3776 vcpu->arch.emulate_ctxt.mode =
a0044755 3777 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3778 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3779 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3780 ? X86EMUL_MODE_PROT64 : cs_db
3781 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3782
ad312c7c 3783 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3784 trace_kvm_emulate_insn_start(vcpu);
571008da 3785
0cb5762e
AP		 3786 /* Only allow emulation of specific instructions on #UD
3787 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3788 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3789 if (emulation_type & EMULTYPE_TRAP_UD) {
3790 if (!c->twobyte)
3791 return EMULATE_FAIL;
3792 switch (c->b) {
3793 case 0x01: /* VMMCALL */
3794 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3795 return EMULATE_FAIL;
3796 break;
3797 case 0x34: /* sysenter */
3798 case 0x35: /* sysexit */
3799 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3800 return EMULATE_FAIL;
3801 break;
3802 case 0x05: /* syscall */
3803 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3804 return EMULATE_FAIL;
3805 break;
3806 default:
3807 return EMULATE_FAIL;
3808 }
3809
3810 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3811 return EMULATE_FAIL;
3812 }
571008da 3813
f2b5756b 3814 ++vcpu->stat.insn_emulation;
bbd9b64e 3815 if (r) {
f2b5756b 3816 ++vcpu->stat.insn_emulation_fail;
e46479f8 3817 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3818 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3819 return EMULATE_DONE;
3820 return EMULATE_FAIL;
3821 }
3822 }
3823
ba8afb6b
GN		 3824 if (emulation_type & EMULTYPE_SKIP) {
3825 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3826 return EMULATE_DONE;
3827 }
3828
5cd21917 3829restart:
ad312c7c 3830 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3831 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3832
3833 if (r == 0)
3834 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3835
7972995b 3836 if (vcpu->arch.pio.count) {
cf8f70bf 3837 if (!vcpu->arch.pio.in)
7972995b 3838 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3839 return EMULATE_DO_MMIO;
3840 }
3841
112592da 3842 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3843 run->exit_reason = KVM_EXIT_MMIO;
3844 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3845 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3846 run->mmio.len = vcpu->mmio_size;
3847 run->mmio.is_write = vcpu->mmio_is_write;
3848 }
3849
3850 if (r) {
3851 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
5cd21917 3852 goto done;
bbd9b64e 3853 if (!vcpu->mmio_needed) {
e46479f8
AK		 3854 ++vcpu->stat.insn_emulation_fail;
3855 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3856 kvm_report_emulation_failure(vcpu, "mmio");
3857 return EMULATE_FAIL;
3858 }
3859 return EMULATE_DO_MMIO;
3860 }
3861
bbd9b64e
CO		 3862 if (vcpu->mmio_is_write) {
3863 vcpu->mmio_needed = 0;
3864 return EMULATE_DO_MMIO;
3865 }
3866
5cd21917
GN		 3867done:
3868 if (vcpu->arch.exception.pending)
3869 vcpu->arch.emulate_ctxt.restart = false;
3870
3871 if (vcpu->arch.emulate_ctxt.restart)
3872 goto restart;
3873
bbd9b64e
CO		 3874 return EMULATE_DONE;
3875}
3876EXPORT_SYMBOL_GPL(emulate_instruction);
3877
cf8f70bf
GN		 3878int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
3879{
3880 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3881 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3882 /* do not return to emulator after return from userspace */
7972995b 3883 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3884 return ret;
3885}
3886EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
3887
c8076604
GH		 3888static void bounce_off(void *info)
3889{
3890 /* nothing */
3891}
3892
c8076604
GH		 3893static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3894 void *data)
3895{
3896 struct cpufreq_freqs *freq = data;
3897 struct kvm *kvm;
3898 struct kvm_vcpu *vcpu;
3899 int i, send_ipi = 0;
3900
c8076604
GH		 3901 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3902 return 0;
3903 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3904 return 0;
0cca7907 3905 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3906
3907 spin_lock(&kvm_lock);
3908 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3909 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3910 if (vcpu->cpu != freq->cpu)
3911 continue;
3912 if (!kvm_request_guest_time_update(vcpu))
3913 continue;
3914 if (vcpu->cpu != smp_processor_id())
3915 send_ipi++;
3916 }
3917 }
3918 spin_unlock(&kvm_lock);
3919
3920 if (freq->old < freq->new && send_ipi) {
3921 /*
3922 * We upscale the frequency. Must make the guest
3923 * doesn't see old kvmclock values while running with
3924 * the new frequency, otherwise we risk the guest sees
3925 * time go backwards.
3926 *
3927 * In case we update the frequency for another cpu
3928 * (which might be in guest context) send an interrupt
3929 * to kick the cpu out of guest context. Next time
3930 * guest context is entered kvmclock will be updated,
3931 * so the guest will not see stale values.
3932 */
3933 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3934 }
3935 return 0;
3936}
3937
3938static struct notifier_block kvmclock_cpufreq_notifier_block = {
3939 .notifier_call = kvmclock_cpufreq_notifier
3940};
3941
b820cc0c
ZA		 3942static void kvm_timer_init(void)
3943{
3944 int cpu;
3945
b820cc0c 3946 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3947 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3948 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3949 for_each_online_cpu(cpu) {
3950 unsigned long khz = cpufreq_get(cpu);
3951 if (!khz)
3952 khz = tsc_khz;
3953 per_cpu(cpu_tsc_khz, cpu) = khz;
3954 }
0cca7907
ZA		 3955 } else {
3956 for_each_possible_cpu(cpu)
3957 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3958 }
3959}
3960
ff9d07a0
ZY		 3961static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
3962
3963static int kvm_is_in_guest(void)
3964{
3965 return percpu_read(current_vcpu) != NULL;
3966}
3967
3968static int kvm_is_user_mode(void)
3969{
3970 int user_mode = 3;
dcf46b94 3971
ff9d07a0
ZY		 3972 if (percpu_read(current_vcpu))
3973 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 3974
ff9d07a0
ZY		 3975 return user_mode != 0;
3976}
3977
3978static unsigned long kvm_get_guest_ip(void)
3979{
3980 unsigned long ip = 0;
dcf46b94 3981
ff9d07a0
ZY		 3982 if (percpu_read(current_vcpu))
3983 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 3984
ff9d07a0
ZY		 3985 return ip;
3986}
3987
3988static struct perf_guest_info_callbacks kvm_guest_cbs = {
3989 .is_in_guest = kvm_is_in_guest,
3990 .is_user_mode = kvm_is_user_mode,
3991 .get_guest_ip = kvm_get_guest_ip,
3992};
3993
3994void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
3995{
3996 percpu_write(current_vcpu, vcpu);
3997}
3998EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
3999
4000void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4001{
4002 percpu_write(current_vcpu, NULL);
4003}
4004EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4005
f8c16bba 4006int kvm_arch_init(void *opaque)
043405e1 4007{
b820cc0c 4008 int r;
f8c16bba
ZX		 4009 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4010
f8c16bba
ZX		 4011 if (kvm_x86_ops) {
4012 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4013 r = -EEXIST;
4014 goto out;
f8c16bba
ZX		 4015 }
4016
4017 if (!ops->cpu_has_kvm_support()) {
4018 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4019 r = -EOPNOTSUPP;
4020 goto out;
f8c16bba
ZX		 4021 }
4022 if (ops->disabled_by_bios()) {
4023 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4024 r = -EOPNOTSUPP;
4025 goto out;
f8c16bba
ZX		 4026 }
4027
97db56ce
AK		 4028 r = kvm_mmu_module_init();
4029 if (r)
4030 goto out;
4031
4032 kvm_init_msr_list();
4033
f8c16bba 4034 kvm_x86_ops = ops;
56c6d28a 4035 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4036 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4037 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4038 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4039
b820cc0c 4040 kvm_timer_init();
c8076604 4041
ff9d07a0
ZY		 4042 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4043
f8c16bba 4044 return 0;
56c6d28a
ZX		 4045
4046out:
56c6d28a 4047 return r;
043405e1 4048}
8776e519 4049
f8c16bba
ZX		 4050void kvm_arch_exit(void)
4051{
ff9d07a0
ZY		 4052 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4053
888d256e
JK		 4054 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4055 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4056 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4057 kvm_x86_ops = NULL;
56c6d28a
ZX		 4058 kvm_mmu_module_exit();
4059}
f8c16bba 4060
8776e519
HB		 4061int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4062{
4063 ++vcpu->stat.halt_exits;
4064 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4065 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4066 return 1;
4067 } else {
4068 vcpu->run->exit_reason = KVM_EXIT_HLT;
4069 return 0;
4070 }
4071}
4072EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4073
2f333bcb
MT		 4074static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4075 unsigned long a1)
4076{
4077 if (is_long_mode(vcpu))
4078 return a0;
4079 else
4080 return a0 | ((gpa_t)a1 << 32);
4081}
4082
55cd8e5a
GN		 4083int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4084{
4085 u64 param, ingpa, outgpa, ret;
4086 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4087 bool fast, longmode;
4088 int cs_db, cs_l;
4089
4090 /*
4091 * hypercall generates UD from non zero cpl and real mode
4092 * per HYPER-V spec
4093 */
3eeb3288 4094 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4095 kvm_queue_exception(vcpu, UD_VECTOR);
4096 return 0;
4097 }
4098
4099 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4100 longmode = is_long_mode(vcpu) && cs_l == 1;
4101
4102 if (!longmode) {
ccd46936
GN		 4103 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4104 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4105 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4106 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4107 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4108 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4109 }
4110#ifdef CONFIG_X86_64
4111 else {
4112 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4113 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4114 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4115 }
4116#endif
4117
4118 code = param & 0xffff;
4119 fast = (param >> 16) & 0x1;
4120 rep_cnt = (param >> 32) & 0xfff;
4121 rep_idx = (param >> 48) & 0xfff;
4122
4123 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4124
c25bc163
GN		 4125 switch (code) {
4126 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4127 kvm_vcpu_on_spin(vcpu);
4128 break;
4129 default:
4130 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4131 break;
4132 }
55cd8e5a
GN		 4133
4134 ret = res | (((u64)rep_done & 0xfff) << 32);
4135 if (longmode) {
4136 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4137 } else {
4138 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4139 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4140 }
4141
4142 return 1;
4143}
4144
8776e519
HB		 4145int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4146{
4147 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4148 int r = 1;
8776e519 4149
55cd8e5a
GN		 4150 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4151 return kvm_hv_hypercall(vcpu);
4152
5fdbf976
MT		 4153 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4154 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4155 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4156 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4157 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4158
229456fc 4159 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4160
8776e519
HB		 4161 if (!is_long_mode(vcpu)) {
4162 nr &= 0xFFFFFFFF;
4163 a0 &= 0xFFFFFFFF;
4164 a1 &= 0xFFFFFFFF;
4165 a2 &= 0xFFFFFFFF;
4166 a3 &= 0xFFFFFFFF;
4167 }
4168
07708c4a
JK		 4169 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4170 ret = -KVM_EPERM;
4171 goto out;
4172 }
4173
8776e519 4174 switch (nr) {
b93463aa
AK		 4175 case KVM_HC_VAPIC_POLL_IRQ:
4176 ret = 0;
4177 break;
2f333bcb
MT		 4178 case KVM_HC_MMU_OP:
4179 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4180 break;
8776e519
HB		 4181 default:
4182 ret = -KVM_ENOSYS;
4183 break;
4184 }
07708c4a 4185out:
5fdbf976 4186 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4187 ++vcpu->stat.hypercalls;
2f333bcb 4188 return r;
8776e519
HB		 4189}
4190EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4191
4192int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4193{
4194 char instruction[3];
5fdbf976 4195 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4196
8776e519
HB		 4197 /*
4198 * Blow out the MMU to ensure that no other VCPU has an active mapping
4199 * to ensure that the updated hypercall appears atomically across all
4200 * VCPUs.
4201 */
4202 kvm_mmu_zap_all(vcpu->kvm);
4203
8776e519 4204 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4205
8f6abd06 4206 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4207}
4208
8776e519
HB		 4209void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4210{
89a27f4d 4211 struct desc_ptr dt = { limit, base };
8776e519
HB		 4212
4213 kvm_x86_ops->set_gdt(vcpu, &dt);
4214}
4215
4216void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4217{
89a27f4d 4218 struct desc_ptr dt = { limit, base };
8776e519
HB		 4219
4220 kvm_x86_ops->set_idt(vcpu, &dt);
4221}
4222
07716717
DK		 4223static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4224{
ad312c7c
ZX		 4225 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4226 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4227
4228 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4229 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4230 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4231 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4232 if (ej->function == e->function) {
4233 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4234 return j;
4235 }
4236 }
4237 return 0; /* silence gcc, even though control never reaches here */
4238}
4239
4240/* find an entry with matching function, matching index (if needed), and that
4241 * should be read next (if it's stateful) */
4242static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4243 u32 function, u32 index)
4244{
4245 if (e->function != function)
4246 return 0;
4247 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4248 return 0;
4249 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4250 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4251 return 0;
4252 return 1;
4253}
4254
d8017474
AG		 4255struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4256 u32 function, u32 index)
8776e519
HB		 4257{
4258 int i;
d8017474 4259 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4260
ad312c7c 4261 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4262 struct kvm_cpuid_entry2 *e;
4263
ad312c7c 4264 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4265 if (is_matching_cpuid_entry(e, function, index)) {
4266 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4267 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4268 best = e;
4269 break;
4270 }
4271 /*
4272 * Both basic or both extended?
4273 */
4274 if (((e->function ^ function) & 0x80000000) == 0)
4275 if (!best || e->function > best->function)
4276 best = e;
4277 }
d8017474
AG		 4278 return best;
4279}
0e851880 4280EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4281
82725b20
DE		 4282int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4283{
4284 struct kvm_cpuid_entry2 *best;
4285
f7a71197
AK		 4286 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4287 if (!best || best->eax < 0x80000008)
4288 goto not_found;
82725b20
DE		 4289 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4290 if (best)
4291 return best->eax & 0xff;
f7a71197 4292not_found:
82725b20
DE		 4293 return 36;
4294}
4295
d8017474
AG		 4296void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4297{
4298 u32 function, index;
4299 struct kvm_cpuid_entry2 *best;
4300
4301 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4302 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4303 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4304 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4305 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4306 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4307 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4308 if (best) {
5fdbf976
MT		 4309 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4310 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4311 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4312 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4313 }
8776e519 4314 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4315 trace_kvm_cpuid(function,
4316 kvm_register_read(vcpu, VCPU_REGS_RAX),
4317 kvm_register_read(vcpu, VCPU_REGS_RBX),
4318 kvm_register_read(vcpu, VCPU_REGS_RCX),
4319 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4320}
4321EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4322
b6c7a5dc
HB		 4323/*
4324 * Check if userspace requested an interrupt window, and that the
4325 * interrupt window is open.
4326 *
4327 * No need to exit to userspace if we already have an interrupt queued.
4328 */
851ba692 4329static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4330{
8061823a 4331 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4332 vcpu->run->request_interrupt_window &&
5df56646 4333 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4334}
4335
851ba692 4336static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4337{
851ba692
AK		 4338 struct kvm_run *kvm_run = vcpu->run;
4339
91586a3b 4340 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4341 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4342 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4343 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4344 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4345 else
b6c7a5dc 4346 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4347 kvm_arch_interrupt_allowed(vcpu) &&
4348 !kvm_cpu_has_interrupt(vcpu) &&
4349 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4350}
4351
b93463aa
AK		 4352static void vapic_enter(struct kvm_vcpu *vcpu)
4353{
4354 struct kvm_lapic *apic = vcpu->arch.apic;
4355 struct page *page;
4356
4357 if (!apic || !apic->vapic_addr)
4358 return;
4359
4360 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4361
4362 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4363}
4364
4365static void vapic_exit(struct kvm_vcpu *vcpu)
4366{
4367 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4368 int idx;
b93463aa
AK		 4369
4370 if (!apic || !apic->vapic_addr)
4371 return;
4372
f656ce01 4373 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4374 kvm_release_page_dirty(apic->vapic_page);
4375 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4376 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4377}
4378
95ba8273
GN		 4379static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4380{
4381 int max_irr, tpr;
4382
4383 if (!kvm_x86_ops->update_cr8_intercept)
4384 return;
4385
88c808fd
AK		 4386 if (!vcpu->arch.apic)
4387 return;
4388
8db3baa2
GN		 4389 if (!vcpu->arch.apic->vapic_addr)
4390 max_irr = kvm_lapic_find_highest_irr(vcpu);
4391 else
4392 max_irr = -1;
95ba8273
GN		 4393
4394 if (max_irr != -1)
4395 max_irr >>= 4;
4396
4397 tpr = kvm_lapic_get_cr8(vcpu);
4398
4399 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4400}
4401
851ba692 4402static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4403{
4404 /* try to reinject previous events if any */
b59bb7bd 4405 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4406 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4407 vcpu->arch.exception.has_error_code,
4408 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4409 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4410 vcpu->arch.exception.has_error_code,
4411 vcpu->arch.exception.error_code);
4412 return;
4413 }
4414
95ba8273
GN		 4415 if (vcpu->arch.nmi_injected) {
4416 kvm_x86_ops->set_nmi(vcpu);
4417 return;
4418 }
4419
4420 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4421 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4422 return;
4423 }
4424
4425 /* try to inject new event if pending */
4426 if (vcpu->arch.nmi_pending) {
4427 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4428 vcpu->arch.nmi_pending = false;
4429 vcpu->arch.nmi_injected = true;
4430 kvm_x86_ops->set_nmi(vcpu);
4431 }
4432 } else if (kvm_cpu_has_interrupt(vcpu)) {
4433 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4434 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4435 false);
4436 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4437 }
4438 }
4439}
4440
851ba692 4441static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4442{
4443 int r;
6a8b1d13 4444 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4445 vcpu->run->request_interrupt_window;
b6c7a5dc 4446
2e53d63a
MT		 4447 if (vcpu->requests)
4448 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4449 kvm_mmu_unload(vcpu);
4450
b6c7a5dc
HB		 4451 r = kvm_mmu_reload(vcpu);
4452 if (unlikely(r))
4453 goto out;
4454
2f52d58c
AK		 4455 if (vcpu->requests) {
4456 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4457 __kvm_migrate_timers(vcpu);
c8076604
GH		 4458 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4459 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4460 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4461 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4462 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4463 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4464 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4465 &vcpu->requests)) {
851ba692 4466 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4467 r = 0;
4468 goto out;
4469 }
71c4dfaf 4470 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4471 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4472 r = 0;
4473 goto out;
4474 }
02daab21
AK		 4475 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4476 vcpu->fpu_active = 0;
4477 kvm_x86_ops->fpu_deactivate(vcpu);
4478 }
2f52d58c 4479 }
b93463aa 4480
b6c7a5dc
HB		 4481 preempt_disable();
4482
4483 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4484 if (vcpu->fpu_active)
4485 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4486
4487 local_irq_disable();
4488
32f88400
MT		 4489 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4490 smp_mb__after_clear_bit();
4491
d7690175 4492 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4493 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4494 local_irq_enable();
4495 preempt_enable();
4496 r = 1;
4497 goto out;
4498 }
4499
851ba692 4500 inject_pending_event(vcpu);
b6c7a5dc 4501
6a8b1d13
GN		 4502 /* enable NMI/IRQ window open exits if needed */
4503 if (vcpu->arch.nmi_pending)
4504 kvm_x86_ops->enable_nmi_window(vcpu);
4505 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4506 kvm_x86_ops->enable_irq_window(vcpu);
4507
95ba8273 4508 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4509 update_cr8_intercept(vcpu);
4510 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4511 }
b93463aa 4512
f656ce01 4513 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4514
b6c7a5dc
HB		 4515 kvm_guest_enter();
4516
42dbaa5a 4517 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4518 set_debugreg(0, 7);
4519 set_debugreg(vcpu->arch.eff_db[0], 0);
4520 set_debugreg(vcpu->arch.eff_db[1], 1);
4521 set_debugreg(vcpu->arch.eff_db[2], 2);
4522 set_debugreg(vcpu->arch.eff_db[3], 3);
4523 }
b6c7a5dc 4524
229456fc 4525 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4526 kvm_x86_ops->run(vcpu);
b6c7a5dc 4527
24f1e32c
FW		 4528 /*
4529 * If the guest has used debug registers, at least dr7
4530 * will be disabled while returning to the host.
4531 * If we don't have active breakpoints in the host, we don't
4532 * care about the messed up debug address registers. But if
4533 * we have some of them active, restore the old state.
4534 */
59d8eb53 4535 if (hw_breakpoint_active())
24f1e32c 4536 hw_breakpoint_restore();
42dbaa5a 4537
32f88400 4538 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4539 local_irq_enable();
4540
4541 ++vcpu->stat.exits;
4542
4543 /*
4544 * We must have an instruction between local_irq_enable() and
4545 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4546 * the interrupt shadow. The stat.exits increment will do nicely.
4547 * But we need to prevent reordering, hence this barrier():
4548 */
4549 barrier();
4550
4551 kvm_guest_exit();
4552
4553 preempt_enable();
4554
f656ce01 4555 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4556
b6c7a5dc
HB		 4557 /*
4558 * Profile KVM exit RIPs:
4559 */
4560 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4561 unsigned long rip = kvm_rip_read(vcpu);
4562 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4563 }
4564
298101da 4565
b93463aa
AK		 4566 kvm_lapic_sync_from_vapic(vcpu);
4567
851ba692 4568 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4569out:
4570 return r;
4571}
b6c7a5dc 4572
09cec754 4573
851ba692 4574static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4575{
4576 int r;
f656ce01 4577 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4578
4579 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4580 pr_debug("vcpu %d received sipi with vector # %x\n",
4581 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4582 kvm_lapic_reset(vcpu);
5f179287 4583 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4584 if (r)
4585 return r;
4586 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4587 }
4588
f656ce01 4589 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4590 vapic_enter(vcpu);
4591
4592 r = 1;
4593 while (r > 0) {
af2152f5 4594 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4595 r = vcpu_enter_guest(vcpu);
d7690175 4596 else {
f656ce01 4597 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4598 kvm_vcpu_block(vcpu);
f656ce01 4599 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4600 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4601 {
4602 switch(vcpu->arch.mp_state) {
4603 case KVM_MP_STATE_HALTED:
d7690175 4604 vcpu->arch.mp_state =
09cec754
GN		 4605 KVM_MP_STATE_RUNNABLE;
4606 case KVM_MP_STATE_RUNNABLE:
4607 break;
4608 case KVM_MP_STATE_SIPI_RECEIVED:
4609 default:
4610 r = -EINTR;
4611 break;
4612 }
4613 }
d7690175
MT		 4614 }
4615
09cec754
GN		 4616 if (r <= 0)
4617 break;
4618
4619 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4620 if (kvm_cpu_has_pending_timer(vcpu))
4621 kvm_inject_pending_timer_irqs(vcpu);
4622
851ba692 4623 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4624 r = -EINTR;
851ba692 4625 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4626 ++vcpu->stat.request_irq_exits;
4627 }
4628 if (signal_pending(current)) {
4629 r = -EINTR;
851ba692 4630 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4631 ++vcpu->stat.signal_exits;
4632 }
4633 if (need_resched()) {
f656ce01 4634 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4635 kvm_resched(vcpu);
f656ce01 4636 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4637 }
b6c7a5dc
HB		 4638 }
4639
f656ce01 4640 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4641 post_kvm_run_save(vcpu);
b6c7a5dc 4642
b93463aa
AK		 4643 vapic_exit(vcpu);
4644
b6c7a5dc
HB		 4645 return r;
4646}
4647
4648int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4649{
4650 int r;
4651 sigset_t sigsaved;
4652
4653 vcpu_load(vcpu);
4654
ac9f6dc0
AK		 4655 if (vcpu->sigset_active)
4656 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4657
a4535290 4658 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4659 kvm_vcpu_block(vcpu);
d7690175 4660 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4661 r = -EAGAIN;
4662 goto out;
b6c7a5dc
HB		 4663 }
4664
b6c7a5dc
HB		 4665 /* re-sync apic's tpr */
4666 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4667 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4668
92bf9748
GN		 4669 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4670 vcpu->arch.emulate_ctxt.restart) {
4671 if (vcpu->mmio_needed) {
4672 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4673 vcpu->mmio_read_completed = 1;
4674 vcpu->mmio_needed = 0;
b6c7a5dc 4675 }
5cd21917
GN		 4676 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4677 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
4678 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4679 if (r == EMULATE_DO_MMIO) {
4680 r = 0;
4681 goto out;
4682 }
4683 }
5fdbf976
MT		 4684 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4685 kvm_register_write(vcpu, VCPU_REGS_RAX,
4686 kvm_run->hypercall.ret);
b6c7a5dc 4687
851ba692 4688 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4689
4690out:
4691 if (vcpu->sigset_active)
4692 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4693
4694 vcpu_put(vcpu);
4695 return r;
4696}
4697
4698int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4699{
4700 vcpu_load(vcpu);
4701
5fdbf976
MT		 4702 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4703 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4704 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4705 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4706 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4707 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4708 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4709 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4710#ifdef CONFIG_X86_64
5fdbf976
MT		 4711 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4712 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4713 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4714 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4715 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4716 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4717 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4718 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4719#endif
4720
5fdbf976 4721 regs->rip = kvm_rip_read(vcpu);
91586a3b 4722 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4723
4724 vcpu_put(vcpu);
4725
4726 return 0;
4727}
4728
4729int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4730{
4731 vcpu_load(vcpu);
4732
5fdbf976
MT		 4733 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4734 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4735 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4736 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4737 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4738 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4739 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4740 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4741#ifdef CONFIG_X86_64
5fdbf976
MT		 4742 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4743 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4744 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4745 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4746 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4747 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4748 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4749 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4750#endif
4751
5fdbf976 4752 kvm_rip_write(vcpu, regs->rip);
91586a3b 4753 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4754
b4f14abd
JK		 4755 vcpu->arch.exception.pending = false;
4756
b6c7a5dc
HB		 4757 vcpu_put(vcpu);
4758
4759 return 0;
4760}
4761
b6c7a5dc
HB		 4762void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4763{
4764 struct kvm_segment cs;
4765
3e6e0aab 4766 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4767 *db = cs.db;
4768 *l = cs.l;
4769}
4770EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4771
4772int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4773 struct kvm_sregs *sregs)
4774{
89a27f4d 4775 struct desc_ptr dt;
b6c7a5dc
HB		 4776
4777 vcpu_load(vcpu);
4778
3e6e0aab
GT		 4779 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4780 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4781 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4782 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4783 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4784 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4785
3e6e0aab
GT		 4786 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4787 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4788
4789 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4790 sregs->idt.limit = dt.size;
4791 sregs->idt.base = dt.address;
b6c7a5dc 4792 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4793 sregs->gdt.limit = dt.size;
4794 sregs->gdt.base = dt.address;
b6c7a5dc 4795
4d4ec087 4796 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4797 sregs->cr2 = vcpu->arch.cr2;
4798 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4799 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4800 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4801 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4802 sregs->apic_base = kvm_get_apic_base(vcpu);
4803
923c61bb 4804 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4805
36752c9b 4806 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4807 set_bit(vcpu->arch.interrupt.nr,
4808 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4809
b6c7a5dc
HB		 4810 vcpu_put(vcpu);
4811
4812 return 0;
4813}
4814
62d9f0db
MT		 4815int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4816 struct kvm_mp_state *mp_state)
4817{
4818 vcpu_load(vcpu);
4819 mp_state->mp_state = vcpu->arch.mp_state;
4820 vcpu_put(vcpu);
4821 return 0;
4822}
4823
4824int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4825 struct kvm_mp_state *mp_state)
4826{
4827 vcpu_load(vcpu);
4828 vcpu->arch.mp_state = mp_state->mp_state;
4829 vcpu_put(vcpu);
4830 return 0;
4831}
4832
e269fb21
JK		 4833int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4834 bool has_error_code, u32 error_code)
37817f29 4835{
ceffb459
GN		 4836 int cs_db, cs_l, ret;
4837 cache_all_regs(vcpu);
37817f29 4838
ceffb459 4839 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
b237ac37 4840
ceffb459
GN		 4841 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4842 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4843 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4844 vcpu->arch.emulate_ctxt.mode =
4845 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4846 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4847 ? X86EMUL_MODE_VM86 : cs_l
4848 ? X86EMUL_MODE_PROT64 : cs_db
4849 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
37817f29 4850
ceffb459 4851 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4852 tss_selector, reason, has_error_code,
4853 error_code);
37817f29 4854
19d04437
GN		 4855 if (ret)
4856 return EMULATE_FAIL;
37817f29 4857
19d04437
GN		 4858 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4859 return EMULATE_DONE;
37817f29
IE		 4860}
4861EXPORT_SYMBOL_GPL(kvm_task_switch);
4862
b6c7a5dc
HB		 4863int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4864 struct kvm_sregs *sregs)
4865{
4866 int mmu_reset_needed = 0;
923c61bb 4867 int pending_vec, max_bits;
89a27f4d 4868 struct desc_ptr dt;
b6c7a5dc
HB		 4869
4870 vcpu_load(vcpu);
4871
89a27f4d
GN		 4872 dt.size = sregs->idt.limit;
4873 dt.address = sregs->idt.base;
b6c7a5dc 4874 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4875 dt.size = sregs->gdt.limit;
4876 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4877 kvm_x86_ops->set_gdt(vcpu, &dt);
4878
ad312c7c
ZX		 4879 vcpu->arch.cr2 = sregs->cr2;
4880 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4881 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4882
2d3ad1f4 4883 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4884
f6801dff 4885 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4886 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4887 kvm_set_apic_base(vcpu, sregs->apic_base);
4888
4d4ec087 4889 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4890 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4891 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4892
fc78f519 4893 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4894 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4895 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4896 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4897 mmu_reset_needed = 1;
4898 }
b6c7a5dc
HB		 4899
4900 if (mmu_reset_needed)
4901 kvm_mmu_reset_context(vcpu);
4902
923c61bb
GN		 4903 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4904 pending_vec = find_first_bit(
4905 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4906 if (pending_vec < max_bits) {
66fd3f7f 4907 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4908 pr_debug("Set back pending irq %d\n", pending_vec);
4909 if (irqchip_in_kernel(vcpu->kvm))
4910 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4911 }
4912
3e6e0aab
GT		 4913 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4914 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4915 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4916 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4917 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4918 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4919
3e6e0aab
GT		 4920 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4921 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4922
5f0269f5
ME		 4923 update_cr8_intercept(vcpu);
4924
9c3e4aab 4925 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4926 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4927 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4928 !is_protmode(vcpu))
9c3e4aab
MT		 4929 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4930
b6c7a5dc
HB		 4931 vcpu_put(vcpu);
4932
4933 return 0;
4934}
4935
d0bfb940
JK		 4936int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4937 struct kvm_guest_debug *dbg)
b6c7a5dc 4938{
355be0b9 4939 unsigned long rflags;
ae675ef0 4940 int i, r;
b6c7a5dc
HB		 4941
4942 vcpu_load(vcpu);
4943
4f926bf2
JK		 4944 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4945 r = -EBUSY;
4946 if (vcpu->arch.exception.pending)
4947 goto unlock_out;
4948 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4949 kvm_queue_exception(vcpu, DB_VECTOR);
4950 else
4951 kvm_queue_exception(vcpu, BP_VECTOR);
4952 }
4953
91586a3b
JK		 4954 /*
4955 * Read rflags as long as potentially injected trace flags are still
4956 * filtered out.
4957 */
4958 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4959
4960 vcpu->guest_debug = dbg->control;
4961 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4962 vcpu->guest_debug = 0;
4963
4964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4965 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4966 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4967 vcpu->arch.switch_db_regs =
4968 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4969 } else {
4970 for (i = 0; i < KVM_NR_DB_REGS; i++)
4971 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4972 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4973 }
4974
f92653ee
JK		 4975 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4976 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
4977 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 4978
91586a3b
JK		 4979 /*
4980 * Trigger an rflags update that will inject or remove the trace
4981 * flags.
4982 */
4983 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4984
355be0b9 4985 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 4986
4f926bf2 4987 r = 0;
d0bfb940 4988
4f926bf2 4989unlock_out:
b6c7a5dc
HB		 4990 vcpu_put(vcpu);
4991
4992 return r;
4993}
4994
d0752060
HB		 4995/*
4996 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4997 * we have asm/x86/processor.h
4998 */
4999struct fxsave {
5000 u16 cwd;
5001 u16 swd;
5002 u16 twd;
5003 u16 fop;
5004 u64 rip;
5005 u64 rdp;
5006 u32 mxcsr;
5007 u32 mxcsr_mask;
5008 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5009#ifdef CONFIG_X86_64
5010 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5011#else
5012 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5013#endif
5014};
5015
8b006791
ZX		 5016/*
5017 * Translate a guest virtual address to a guest physical address.
5018 */
5019int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5020 struct kvm_translation *tr)
5021{
5022 unsigned long vaddr = tr->linear_address;
5023 gpa_t gpa;
f656ce01 5024 int idx;
8b006791
ZX		 5025
5026 vcpu_load(vcpu);
f656ce01 5027 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5028 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5029 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5030 tr->physical_address = gpa;
5031 tr->valid = gpa != UNMAPPED_GVA;
5032 tr->writeable = 1;
5033 tr->usermode = 0;
8b006791
ZX		 5034 vcpu_put(vcpu);
5035
5036 return 0;
5037}
5038
d0752060
HB		 5039int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5040{
ad312c7c 5041 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5042
5043 vcpu_load(vcpu);
5044
5045 memcpy(fpu->fpr, fxsave->st_space, 128);
5046 fpu->fcw = fxsave->cwd;
5047 fpu->fsw = fxsave->swd;
5048 fpu->ftwx = fxsave->twd;
5049 fpu->last_opcode = fxsave->fop;
5050 fpu->last_ip = fxsave->rip;
5051 fpu->last_dp = fxsave->rdp;
5052 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5053
5054 vcpu_put(vcpu);
5055
5056 return 0;
5057}
5058
5059int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5060{
ad312c7c 5061 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5062
5063 vcpu_load(vcpu);
5064
5065 memcpy(fxsave->st_space, fpu->fpr, 128);
5066 fxsave->cwd = fpu->fcw;
5067 fxsave->swd = fpu->fsw;
5068 fxsave->twd = fpu->ftwx;
5069 fxsave->fop = fpu->last_opcode;
5070 fxsave->rip = fpu->last_ip;
5071 fxsave->rdp = fpu->last_dp;
5072 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5073
5074 vcpu_put(vcpu);
5075
5076 return 0;
5077}
5078
5079void fx_init(struct kvm_vcpu *vcpu)
5080{
5081 unsigned after_mxcsr_mask;
5082
bc1a34f1
AA		 5083 /*
5084 * Touch the fpu the first time in non atomic context as if
5085 * this is the first fpu instruction the exception handler
5086 * will fire before the instruction returns and it'll have to
5087 * allocate ram with GFP_KERNEL.
5088 */
5089 if (!used_math())
d6e88aec 5090 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5091
d0752060
HB		 5092 /* Initialize guest FPU by resetting ours and saving into guest's */
5093 preempt_disable();
d6e88aec
AK		 5094 kvm_fx_save(&vcpu->arch.host_fx_image);
5095 kvm_fx_finit();
5096 kvm_fx_save(&vcpu->arch.guest_fx_image);
5097 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5098 preempt_enable();
5099
ad312c7c 5100 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5101 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5102 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5103 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5104 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5105}
5106EXPORT_SYMBOL_GPL(fx_init);
5107
5108void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5109{
2608d7a1 5110 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5111 return;
5112
5113 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5114 kvm_fx_save(&vcpu->arch.host_fx_image);
5115 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5116 trace_kvm_fpu(1);
d0752060 5117}
d0752060
HB		 5118
5119void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5120{
5121 if (!vcpu->guest_fpu_loaded)
5122 return;
5123
5124 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5125 kvm_fx_save(&vcpu->arch.guest_fx_image);
5126 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5127 ++vcpu->stat.fpu_reload;
02daab21 5128 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5129 trace_kvm_fpu(0);
d0752060 5130}
e9b11c17
ZX		 5131
5132void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5133{
7f1ea208
JR		 5134 if (vcpu->arch.time_page) {
5135 kvm_release_page_dirty(vcpu->arch.time_page);
5136 vcpu->arch.time_page = NULL;
5137 }
5138
e9b11c17
ZX		 5139 kvm_x86_ops->vcpu_free(vcpu);
5140}
5141
5142struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5143 unsigned int id)
5144{
26e5215f
AK		 5145 return kvm_x86_ops->vcpu_create(kvm, id);
5146}
e9b11c17 5147
26e5215f
AK		 5148int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5149{
5150 int r;
e9b11c17
ZX		 5151
5152 /* We do fxsave: this must be aligned. */
ad312c7c 5153 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5154
0bed3b56 5155 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5156 vcpu_load(vcpu);
5157 r = kvm_arch_vcpu_reset(vcpu);
5158 if (r == 0)
5159 r = kvm_mmu_setup(vcpu);
5160 vcpu_put(vcpu);
5161 if (r < 0)
5162 goto free_vcpu;
5163
26e5215f 5164 return 0;
e9b11c17
ZX		 5165free_vcpu:
5166 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5167 return r;
e9b11c17
ZX		 5168}
5169
d40ccc62 5170void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5171{
5172 vcpu_load(vcpu);
5173 kvm_mmu_unload(vcpu);
5174 vcpu_put(vcpu);
5175
5176 kvm_x86_ops->vcpu_free(vcpu);
5177}
5178
5179int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5180{
448fa4a9
JK		 5181 vcpu->arch.nmi_pending = false;
5182 vcpu->arch.nmi_injected = false;
5183
42dbaa5a
JK		 5184 vcpu->arch.switch_db_regs = 0;
5185 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5186 vcpu->arch.dr6 = DR6_FIXED_1;
5187 vcpu->arch.dr7 = DR7_FIXED_1;
5188
e9b11c17
ZX		 5189 return kvm_x86_ops->vcpu_reset(vcpu);
5190}
5191
10474ae8 5192int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5193{
0cca7907
ZA		 5194 /*
5195 * Since this may be called from a hotplug notifcation,
5196 * we can't get the CPU frequency directly.
5197 */
5198 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5199 int cpu = raw_smp_processor_id();
5200 per_cpu(cpu_tsc_khz, cpu) = 0;
5201 }
18863bdd
AK		 5202
5203 kvm_shared_msr_cpu_online();
5204
10474ae8 5205 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5206}
5207
5208void kvm_arch_hardware_disable(void *garbage)
5209{
5210 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5211 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5212}
5213
5214int kvm_arch_hardware_setup(void)
5215{
5216 return kvm_x86_ops->hardware_setup();
5217}
5218
5219void kvm_arch_hardware_unsetup(void)
5220{
5221 kvm_x86_ops->hardware_unsetup();
5222}
5223
5224void kvm_arch_check_processor_compat(void *rtn)
5225{
5226 kvm_x86_ops->check_processor_compatibility(rtn);
5227}
5228
5229int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5230{
5231 struct page *page;
5232 struct kvm *kvm;
5233 int r;
5234
5235 BUG_ON(vcpu->kvm == NULL);
5236 kvm = vcpu->kvm;
5237
ad312c7c 5238 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5239 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5240 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5241 else
a4535290 5242 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5243
5244 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5245 if (!page) {
5246 r = -ENOMEM;
5247 goto fail;
5248 }
ad312c7c 5249 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5250
5251 r = kvm_mmu_create(vcpu);
5252 if (r < 0)
5253 goto fail_free_pio_data;
5254
5255 if (irqchip_in_kernel(kvm)) {
5256 r = kvm_create_lapic(vcpu);
5257 if (r < 0)
5258 goto fail_mmu_destroy;
5259 }
5260
890ca9ae
HY		 5261 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5262 GFP_KERNEL);
5263 if (!vcpu->arch.mce_banks) {
5264 r = -ENOMEM;
443c39bc 5265 goto fail_free_lapic;
890ca9ae
HY		 5266 }
5267 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5268
e9b11c17 5269 return 0;
443c39bc
WY		 5270fail_free_lapic:
5271 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5272fail_mmu_destroy:
5273 kvm_mmu_destroy(vcpu);
5274fail_free_pio_data:
ad312c7c 5275 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5276fail:
5277 return r;
5278}
5279
5280void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5281{
f656ce01
MT		 5282 int idx;
5283
36cb93fd 5284 kfree(vcpu->arch.mce_banks);
e9b11c17 5285 kvm_free_lapic(vcpu);
f656ce01 5286 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5287 kvm_mmu_destroy(vcpu);
f656ce01 5288 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5289 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5290}
d19a9cd2
ZX		 5291
5292struct kvm *kvm_arch_create_vm(void)
5293{
5294 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5295
5296 if (!kvm)
5297 return ERR_PTR(-ENOMEM);
5298
fef9cce0
MT		 5299 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5300 if (!kvm->arch.aliases) {
5301 kfree(kvm);
5302 return ERR_PTR(-ENOMEM);
5303 }
5304
f05e70ac 5305 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5306 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5307
5550af4d
SY		 5308 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5309 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5310
53f658b3
MT		 5311 rdtscll(kvm->arch.vm_init_tsc);
5312
d19a9cd2
ZX		 5313 return kvm;
5314}
5315
5316static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5317{
5318 vcpu_load(vcpu);
5319 kvm_mmu_unload(vcpu);
5320 vcpu_put(vcpu);
5321}
5322
5323static void kvm_free_vcpus(struct kvm *kvm)
5324{
5325 unsigned int i;
988a2cae 5326 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5327
5328 /*
5329 * Unpin any mmu pages first.
5330 */
988a2cae
GN		 5331 kvm_for_each_vcpu(i, vcpu, kvm)
5332 kvm_unload_vcpu_mmu(vcpu);
5333 kvm_for_each_vcpu(i, vcpu, kvm)
5334 kvm_arch_vcpu_free(vcpu);
5335
5336 mutex_lock(&kvm->lock);
5337 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5338 kvm->vcpus[i] = NULL;
d19a9cd2 5339
988a2cae
GN		 5340 atomic_set(&kvm->online_vcpus, 0);
5341 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5342}
5343
ad8ba2cd
SY		 5344void kvm_arch_sync_events(struct kvm *kvm)
5345{
ba4cef31 5346 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5347}
5348
d19a9cd2
ZX		 5349void kvm_arch_destroy_vm(struct kvm *kvm)
5350{
6eb55818 5351 kvm_iommu_unmap_guest(kvm);
7837699f 5352 kvm_free_pit(kvm);
d7deeeb0
ZX		 5353 kfree(kvm->arch.vpic);
5354 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5355 kvm_free_vcpus(kvm);
5356 kvm_free_physmem(kvm);
3d45830c
AK		 5357 if (kvm->arch.apic_access_page)
5358 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5359 if (kvm->arch.ept_identity_pagetable)
5360 put_page(kvm->arch.ept_identity_pagetable);
64749204 5361 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5362 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5363 kfree(kvm);
5364}
0de10343 5365
f7784b8e
MT		 5366int kvm_arch_prepare_memory_region(struct kvm *kvm,
5367 struct kvm_memory_slot *memslot,
0de10343 5368 struct kvm_memory_slot old,
f7784b8e 5369 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5370 int user_alloc)
5371{
f7784b8e 5372 int npages = memslot->npages;
0de10343
ZX		 5373
5374 /*To keep backward compatibility with older userspace,
5375 *x86 needs to hanlde !user_alloc case.
5376 */
5377 if (!user_alloc) {
5378 if (npages && !old.rmap) {
604b38ac
AA		 5379 unsigned long userspace_addr;
5380
72dc67a6 5381 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5382 userspace_addr = do_mmap(NULL, 0,
5383 npages * PAGE_SIZE,
5384 PROT_READ | PROT_WRITE,
acee3c04 5385 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5386 0);
72dc67a6 5387 up_write(&current->mm->mmap_sem);
0de10343 5388
604b38ac
AA		 5389 if (IS_ERR((void *)userspace_addr))
5390 return PTR_ERR((void *)userspace_addr);
5391
604b38ac 5392 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5393 }
5394 }
5395
f7784b8e
MT		 5396
5397 return 0;
5398}
5399
5400void kvm_arch_commit_memory_region(struct kvm *kvm,
5401 struct kvm_userspace_memory_region *mem,
5402 struct kvm_memory_slot old,
5403 int user_alloc)
5404{
5405
5406 int npages = mem->memory_size >> PAGE_SHIFT;
5407
5408 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5409 int ret;
5410
5411 down_write(&current->mm->mmap_sem);
5412 ret = do_munmap(current->mm, old.userspace_addr,
5413 old.npages * PAGE_SIZE);
5414 up_write(&current->mm->mmap_sem);
5415 if (ret < 0)
5416 printk(KERN_WARNING
5417 "kvm_vm_ioctl_set_memory_region: "
5418 "failed to munmap memory\n");
5419 }
5420
7c8a83b7 5421 spin_lock(&kvm->mmu_lock);
f05e70ac 5422 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5423 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5424 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5425 }
5426
5427 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5428 spin_unlock(&kvm->mmu_lock);
0de10343 5429}
1d737c8a 5430
34d4cb8f
MT		 5431void kvm_arch_flush_shadow(struct kvm *kvm)
5432{
5433 kvm_mmu_zap_all(kvm);
8986ecc0 5434 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5435}
5436
1d737c8a
ZX		 5437int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5438{
a4535290 5439 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5440 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5441 || vcpu->arch.nmi_pending ||
5442 (kvm_arch_interrupt_allowed(vcpu) &&
5443 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5444}
5736199a 5445
5736199a
ZX		 5446void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5447{
32f88400
MT		 5448 int me;
5449 int cpu = vcpu->cpu;
5736199a
ZX		 5450
5451 if (waitqueue_active(&vcpu->wq)) {
5452 wake_up_interruptible(&vcpu->wq);
5453 ++vcpu->stat.halt_wakeup;
5454 }
32f88400
MT		 5455
5456 me = get_cpu();
5457 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5458 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5459 smp_send_reschedule(cpu);
e9571ed5 5460 put_cpu();
5736199a 5461}
78646121
GN		 5462
5463int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5464{
5465 return kvm_x86_ops->interrupt_allowed(vcpu);
5466}
229456fc 5467
f92653ee
JK		 5468bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5469{
5470 unsigned long current_rip = kvm_rip_read(vcpu) +
5471 get_segment_base(vcpu, VCPU_SREG_CS);
5472
5473 return current_rip == linear_rip;
5474}
5475EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5476
94fe45da
JK		 5477unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5478{
5479 unsigned long rflags;
5480
5481 rflags = kvm_x86_ops->get_rflags(vcpu);
5482 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5483 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5484 return rflags;
5485}
5486EXPORT_SYMBOL_GPL(kvm_get_rflags);
5487
5488void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5489{
5490 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5491 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5492 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5493 kvm_x86_ops->set_rflags(vcpu, rflags);
5494}
5495EXPORT_SYMBOL_GPL(kvm_set_rflags);
5496
229456fc
MT		 5497EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5498EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5499EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5500EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5501EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5502EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5503EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5504EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5505EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5506EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5507EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5508EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
This page took 0.700968 seconds and 5 git commands to generate.