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KVM: x86: fix for buffer overflow in handling of MSR_KVM_SYSTEM_TIME (CVE-2013-1796)
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
8b6e4547 165static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
d6aa1000 166
af585b92
GN		 167static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168{
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172}
173
18863bdd
AK		 174static void kvm_on_user_return(struct user_return_notifier *urn)
175{
176 unsigned slot;
18863bdd
AK		 177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 179 struct kvm_shared_msr_values *values;
18863bdd
AK		 180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
18863bdd
AK		 186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190}
191
2bf78fa7 192static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 193{
18863bdd 194 u64 value;
013f6a5d
MT		 195 unsigned int cpu = smp_processor_id();
196 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 197
2bf78fa7
SY		 198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207}
208
209void kvm_define_shared_msr(unsigned slot, u32 msr)
210{
18863bdd
AK		 211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
18863bdd
AK		 216}
217EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219static void kvm_shared_msr_cpu_online(void)
220{
221 unsigned i;
18863bdd
AK		 222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 224 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 225}
226
d5696725 227void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 228{
013f6a5d
MT		 229 unsigned int cpu = smp_processor_id();
230 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 231
2bf78fa7 232 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 233 return;
2bf78fa7
SY		 234 smsr->values[slot].curr = value;
235 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 236 if (!smsr->registered) {
237 smsr->urn.on_user_return = kvm_on_user_return;
238 user_return_notifier_register(&smsr->urn);
239 smsr->registered = true;
240 }
241}
242EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
243
3548bab5
AK		 244static void drop_user_return_notifiers(void *ignore)
245{
013f6a5d
MT		 246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 248
249 if (smsr->registered)
250 kvm_on_user_return(&smsr->urn);
251}
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
8a5a87d9 255 return vcpu->arch.apic_base;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_get_apic_base);
258
259void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
260{
261 /* TODO: reserve bits check */
8a5a87d9 262 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 263}
264EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
3fd28fce
ED		 266#define EXCPT_BENIGN 0
267#define EXCPT_CONTRIBUTORY 1
268#define EXCPT_PF 2
269
270static int exception_class(int vector)
271{
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285}
286
287static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
3fd28fce
ED		 290{
291 u32 prev_nr;
292 int class1, class2;
293
3842d135
AK		 294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
3fd28fce
ED		 296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
3f0fd292 302 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
a8eeb04a 310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327}
328
298101da
AK		 329void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
ce7ddec4 331 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 332}
333EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
ce7ddec4
JR		 335void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336{
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338}
339EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
db8fcefa 341void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 342{
db8fcefa
AP		 343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347}
348EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 349
6389ee94 350void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 351{
352 ++vcpu->stat.pf_guest;
6389ee94
AK		 353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 355}
27d6c865 356EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 357
6389ee94 358void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 359{
6389ee94
AK		 360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 362 else
6389ee94 363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 364}
365
3419ffc8
SY		 366void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367{
7460fb4a
AK		 368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 370}
371EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
298101da
AK		 373void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
ce7ddec4 375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 376}
377EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
ce7ddec4
JR		 379void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380{
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382}
383EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
0a79b009
AK		 385/*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 390{
0a79b009
AK		 391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
298101da 395}
0a79b009 396EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 397
ec92fe44
JR		 398/*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406{
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418}
419EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
3d06b8bf
JR		 421int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423{
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426}
427
a03490ed
CO		 428/*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
ff03a073 431int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 432{
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
ff03a073 437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 438
ff03a073
JR		 439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 447 if (is_present_gpte(pdpte[i]) &&
20c466b5 448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
ff03a073 455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 460out:
a03490ed
CO		 461
462 return ret;
463}
cc4b6871 464EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 465
d835dfec
AK		 466static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467{
ff03a073 468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 469 bool changed = true;
3d06b8bf
JR		 470 int offset;
471 gfn_t gfn;
d835dfec
AK		 472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
6de4f3ad
AK		 477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
9f8fe504
AK		 481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 485 if (r < 0)
486 goto out;
ff03a073 487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 488out:
d835dfec
AK		 489
490 return changed;
491}
492
49a9b07e 493int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 494{
aad82703
SY		 495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
f9a48e6a
AK		 499 cr0 |= X86_CR0_ET;
500
ab344828 501#ifdef CONFIG_X86_64
0f12244f
GN		 502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
ab344828
GN		 504#endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 507
0f12244f
GN		 508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
a03490ed 510
0f12244f
GN		 511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
a03490ed
CO		 513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515#ifdef CONFIG_X86_64
f6801dff 516 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 517 int cs_db, cs_l;
518
0f12244f
GN		 519 if (!is_pae(vcpu))
520 return 1;
a03490ed 521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 522 if (cs_l)
523 return 1;
a03490ed
CO		 524 } else
525#endif
ff03a073 526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 527 kvm_read_cr3(vcpu)))
0f12244f 528 return 1;
a03490ed
CO		 529 }
530
ad756a16
MJ		 531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532 return 1;
533
a03490ed 534 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 535
d170c419 536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 537 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 538 kvm_async_pf_hash_reset(vcpu);
539 }
e5f3f027 540
aad82703
SY		 541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 543 return 0;
544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 546
2d3ad1f4 547void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 548{
49a9b07e 549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 550}
2d3ad1f4 551EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 552
2acf923e
DC		 553int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 u64 xcr0;
556
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
559 return 1;
560 xcr0 = xcr;
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
562 return 1;
563 if (!(xcr0 & XSTATE_FP))
564 return 1;
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566 return 1;
567 if (xcr0 & ~host_xcr0)
568 return 1;
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
571 return 0;
572}
573
574int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575{
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
578 return 1;
579 }
580 return 0;
581}
582EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
a83b29c6 584int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 585{
fc78f519 586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 589 if (cr4 & CR4_RESERVED_BITS)
590 return 1;
a03490ed 591
2acf923e
DC		 592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593 return 1;
594
c68b734f
YW		 595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596 return 1;
597
74dc2b4f
YW		 598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
0f12244f
GN		 608 return 1;
609
ad756a16
MJ		 610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
612 return 1;
613
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616 return 1;
617 }
618
5e1746d6 619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 620 return 1;
a03490ed 621
ad756a16
MJ		 622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 627 kvm_update_cpuid(vcpu);
2acf923e 628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
471842ec 642 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644 return 1;
645 } else
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
647 return 1;
a03490ed
CO		 648 } else {
649 if (is_pae(vcpu)) {
0f12244f
GN		 650 if (cr3 & CR3_PAE_RESERVED_BITS)
651 return 1;
ff03a073
JR		 652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 654 return 1;
a03490ed
CO		 655 }
656 /*
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
659 */
660 }
661
a03490ed
CO		 662 /*
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
666 *
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
670 */
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 672 return 1;
673 vcpu->arch.cr3 = cr3;
aff48baa 674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 675 vcpu->arch.mmu.new_cr3(vcpu);
676 return 0;
677}
2d3ad1f4 678EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 679
eea1cff9 680int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 681{
0f12244f
GN		 682 if (cr8 & CR8_RESERVED_BITS)
683 return 1;
a03490ed
CO		 684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
686 else
ad312c7c 687 vcpu->arch.cr8 = cr8;
0f12244f
GN		 688 return 0;
689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 691
2d3ad1f4 692unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 693{
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
696 else
ad312c7c 697 return vcpu->arch.cr8;
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 700
c8639010
JK		 701static void kvm_update_dr7(struct kvm_vcpu *vcpu)
702{
703 unsigned long dr7;
704
705 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
706 dr7 = vcpu->arch.guest_debug_dr7;
707 else
708 dr7 = vcpu->arch.dr7;
709 kvm_x86_ops->set_dr7(vcpu, dr7);
710 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
711}
712
338dbc97 713static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 714{
715 switch (dr) {
716 case 0 ... 3:
717 vcpu->arch.db[dr] = val;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
719 vcpu->arch.eff_db[dr] = val;
720 break;
721 case 4:
338dbc97
GN		 722 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
723 return 1; /* #UD */
020df079
GN		 724 /* fall through */
725 case 6:
338dbc97
GN		 726 if (val & 0xffffffff00000000ULL)
727 return -1; /* #GP */
020df079
GN		 728 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
729 break;
730 case 5:
338dbc97
GN		 731 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
732 return 1; /* #UD */
020df079
GN		 733 /* fall through */
734 default: /* 7 */
338dbc97
GN		 735 if (val & 0xffffffff00000000ULL)
736 return -1; /* #GP */
020df079 737 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 738 kvm_update_dr7(vcpu);
020df079
GN		 739 break;
740 }
741
742 return 0;
743}
338dbc97
GN		 744
745int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
746{
747 int res;
748
749 res = __kvm_set_dr(vcpu, dr, val);
750 if (res > 0)
751 kvm_queue_exception(vcpu, UD_VECTOR);
752 else if (res < 0)
753 kvm_inject_gp(vcpu, 0);
754
755 return res;
756}
020df079
GN		 757EXPORT_SYMBOL_GPL(kvm_set_dr);
758
338dbc97 759static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 760{
761 switch (dr) {
762 case 0 ... 3:
763 *val = vcpu->arch.db[dr];
764 break;
765 case 4:
338dbc97 766 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 767 return 1;
020df079
GN		 768 /* fall through */
769 case 6:
770 *val = vcpu->arch.dr6;
771 break;
772 case 5:
338dbc97 773 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 774 return 1;
020df079
GN		 775 /* fall through */
776 default: /* 7 */
777 *val = vcpu->arch.dr7;
778 break;
779 }
780
781 return 0;
782}
338dbc97
GN		 783
784int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
785{
786 if (_kvm_get_dr(vcpu, dr, val)) {
787 kvm_queue_exception(vcpu, UD_VECTOR);
788 return 1;
789 }
790 return 0;
791}
020df079
GN		 792EXPORT_SYMBOL_GPL(kvm_get_dr);
793
022cd0e8
AK		 794bool kvm_rdpmc(struct kvm_vcpu *vcpu)
795{
796 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
797 u64 data;
798 int err;
799
800 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
801 if (err)
802 return err;
803 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
804 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
805 return err;
806}
807EXPORT_SYMBOL_GPL(kvm_rdpmc);
808
043405e1
CO		 809/*
810 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
811 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
812 *
813 * This list is modified at module load time to reflect the
e3267cbb
GC		 814 * capabilities of the host cpu. This capabilities test skips MSRs that are
815 * kvm-specific. Those are put in the beginning of the list.
043405e1 816 */
e3267cbb 817
439793d4 818#define KVM_SAVE_MSRS_BEGIN 10
043405e1 819static u32 msrs_to_save[] = {
e3267cbb 820 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 821 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 822 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 823 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 824 MSR_KVM_PV_EOI_EN,
043405e1 825 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 826 MSR_STAR,
043405e1
CO		 827#ifdef CONFIG_X86_64
828 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
829#endif
e90aa41e 830 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 831};
832
833static unsigned num_msrs_to_save;
834
f1d24831 835static const u32 emulated_msrs[] = {
ba904635 836 MSR_IA32_TSC_ADJUST,
a3e06bbe 837 MSR_IA32_TSCDEADLINE,
043405e1 838 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 839 MSR_IA32_MCG_STATUS,
840 MSR_IA32_MCG_CTL,
043405e1
CO		 841};
842
b69e8cae 843static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 844{
aad82703
SY		 845 u64 old_efer = vcpu->arch.efer;
846
b69e8cae
RJ		 847 if (efer & efer_reserved_bits)
848 return 1;
15c4a640
CO		 849
850 if (is_paging(vcpu)
b69e8cae
RJ		 851 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
852 return 1;
15c4a640 853
1b2fd70c
AG		 854 if (efer & EFER_FFXSR) {
855 struct kvm_cpuid_entry2 *feat;
856
857 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 858 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
859 return 1;
1b2fd70c
AG		 860 }
861
d8017474
AG		 862 if (efer & EFER_SVME) {
863 struct kvm_cpuid_entry2 *feat;
864
865 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 866 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
867 return 1;
d8017474
AG		 868 }
869
15c4a640 870 efer &= ~EFER_LMA;
f6801dff 871 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 872
a3d204e2
SY		 873 kvm_x86_ops->set_efer(vcpu, efer);
874
aad82703
SY		 875 /* Update reserved bits */
876 if ((efer ^ old_efer) & EFER_NX)
877 kvm_mmu_reset_context(vcpu);
878
b69e8cae 879 return 0;
15c4a640
CO		 880}
881
f2b4b7dd
JR		 882void kvm_enable_efer_bits(u64 mask)
883{
884 efer_reserved_bits &= ~mask;
885}
886EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
887
888
15c4a640
CO		 889/*
890 * Writes msr value into into the appropriate "register".
891 * Returns 0 on success, non-0 otherwise.
892 * Assumes vcpu_load() was already called.
893 */
8fe8ab46 894int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 895{
8fe8ab46 896 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 897}
898
313a3dc7
CO		 899/*
900 * Adapt set_msr() to msr_io()'s calling convention
901 */
902static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
903{
8fe8ab46
WA		 904 struct msr_data msr;
905
906 msr.data = *data;
907 msr.index = index;
908 msr.host_initiated = true;
909 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 910}
911
16e8d74d
MT		 912#ifdef CONFIG_X86_64
913struct pvclock_gtod_data {
914 seqcount_t seq;
915
916 struct { /* extract of a clocksource struct */
917 int vclock_mode;
918 cycle_t cycle_last;
919 cycle_t mask;
920 u32 mult;
921 u32 shift;
922 } clock;
923
924 /* open coded 'struct timespec' */
925 u64 monotonic_time_snsec;
926 time_t monotonic_time_sec;
927};
928
929static struct pvclock_gtod_data pvclock_gtod_data;
930
931static void update_pvclock_gtod(struct timekeeper *tk)
932{
933 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
934
935 write_seqcount_begin(&vdata->seq);
936
937 /* copy pvclock gtod data */
938 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
939 vdata->clock.cycle_last = tk->clock->cycle_last;
940 vdata->clock.mask = tk->clock->mask;
941 vdata->clock.mult = tk->mult;
942 vdata->clock.shift = tk->shift;
943
944 vdata->monotonic_time_sec = tk->xtime_sec
945 + tk->wall_to_monotonic.tv_sec;
946 vdata->monotonic_time_snsec = tk->xtime_nsec
947 + (tk->wall_to_monotonic.tv_nsec
948 << tk->shift);
949 while (vdata->monotonic_time_snsec >=
950 (((u64)NSEC_PER_SEC) << tk->shift)) {
951 vdata->monotonic_time_snsec -=
952 ((u64)NSEC_PER_SEC) << tk->shift;
953 vdata->monotonic_time_sec++;
954 }
955
956 write_seqcount_end(&vdata->seq);
957}
958#endif
959
960
18068523
GOC		 961static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
962{
9ed3c444
AK		 963 int version;
964 int r;
50d0a0f9 965 struct pvclock_wall_clock wc;
923de3cf 966 struct timespec boot;
18068523
GOC		 967
968 if (!wall_clock)
969 return;
970
9ed3c444
AK		 971 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
972 if (r)
973 return;
974
975 if (version & 1)
976 ++version; /* first time write, random junk */
977
978 ++version;
18068523 979
18068523
GOC		 980 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
981
50d0a0f9
GH		 982 /*
983 * The guest calculates current wall clock time by adding
34c238a1 984 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 985 * wall clock specified here. guest system time equals host
986 * system time for us, thus we must fill in host boot time here.
987 */
923de3cf 988 getboottime(&boot);
50d0a0f9 989
4b648665
BR		 990 if (kvm->arch.kvmclock_offset) {
991 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
992 boot = timespec_sub(boot, ts);
993 }
50d0a0f9
GH		 994 wc.sec = boot.tv_sec;
995 wc.nsec = boot.tv_nsec;
996 wc.version = version;
18068523
GOC		 997
998 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
999
1000 version++;
1001 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1002}
1003
50d0a0f9
GH		 1004static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1005{
1006 uint32_t quotient, remainder;
1007
1008 /* Don't try to replace with do_div(), this one calculates
1009 * "(dividend << 32) / divisor" */
1010 __asm__ ( "divl %4"
1011 : "=a" (quotient), "=d" (remainder)
1012 : "0" (0), "1" (dividend), "r" (divisor) );
1013 return quotient;
1014}
1015
5f4e3f88
ZA		 1016static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1017 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1018{
5f4e3f88 1019 uint64_t scaled64;
50d0a0f9
GH		 1020 int32_t shift = 0;
1021 uint64_t tps64;
1022 uint32_t tps32;
1023
5f4e3f88
ZA		 1024 tps64 = base_khz * 1000LL;
1025 scaled64 = scaled_khz * 1000LL;
50933623 1026 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1027 tps64 >>= 1;
1028 shift--;
1029 }
1030
1031 tps32 = (uint32_t)tps64;
50933623
JK		 1032 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1033 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1034 scaled64 >>= 1;
1035 else
1036 tps32 <<= 1;
50d0a0f9
GH		 1037 shift++;
1038 }
1039
5f4e3f88
ZA		 1040 *pshift = shift;
1041 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1042
5f4e3f88
ZA		 1043 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1044 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1045}
1046
759379dd
ZA		 1047static inline u64 get_kernel_ns(void)
1048{
1049 struct timespec ts;
1050
1051 WARN_ON(preemptible());
1052 ktime_get_ts(&ts);
1053 monotonic_to_bootbased(&ts);
1054 return timespec_to_ns(&ts);
50d0a0f9
GH		 1055}
1056
d828199e 1057#ifdef CONFIG_X86_64
16e8d74d 1058static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1059#endif
16e8d74d 1060
c8076604 1061static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1062unsigned long max_tsc_khz;
c8076604 1063
cc578287 1064static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1065{
cc578287
ZA		 1066 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1067 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1068}
1069
cc578287 1070static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1071{
cc578287
ZA		 1072 u64 v = (u64)khz * (1000000 + ppm);
1073 do_div(v, 1000000);
1074 return v;
1e993611
JR		 1075}
1076
cc578287 1077static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1078{
cc578287
ZA		 1079 u32 thresh_lo, thresh_hi;
1080 int use_scaling = 0;
217fc9cf 1081
c285545f
ZA		 1082 /* Compute a scale to convert nanoseconds in TSC cycles */
1083 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1084 &vcpu->arch.virtual_tsc_shift,
1085 &vcpu->arch.virtual_tsc_mult);
1086 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1087
1088 /*
1089 * Compute the variation in TSC rate which is acceptable
1090 * within the range of tolerance and decide if the
1091 * rate being applied is within that bounds of the hardware
1092 * rate. If so, no scaling or compensation need be done.
1093 */
1094 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1095 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1096 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1097 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1098 use_scaling = 1;
1099 }
1100 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1101}
1102
1103static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1104{
e26101b1 1105 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1106 vcpu->arch.virtual_tsc_mult,
1107 vcpu->arch.virtual_tsc_shift);
e26101b1 1108 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1109 return tsc;
1110}
1111
b48aa97e
MT		 1112void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1113{
1114#ifdef CONFIG_X86_64
1115 bool vcpus_matched;
1116 bool do_request = false;
1117 struct kvm_arch *ka = &vcpu->kvm->arch;
1118 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1119
1120 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1121 atomic_read(&vcpu->kvm->online_vcpus));
1122
1123 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1124 if (!ka->use_master_clock)
1125 do_request = 1;
1126
1127 if (!vcpus_matched && ka->use_master_clock)
1128 do_request = 1;
1129
1130 if (do_request)
1131 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1132
1133 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1134 atomic_read(&vcpu->kvm->online_vcpus),
1135 ka->use_master_clock, gtod->clock.vclock_mode);
1136#endif
1137}
1138
ba904635
WA		 1139static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1140{
1141 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1142 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1143}
1144
8fe8ab46 1145void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1146{
1147 struct kvm *kvm = vcpu->kvm;
f38e098f 1148 u64 offset, ns, elapsed;
99e3e30a 1149 unsigned long flags;
02626b6a 1150 s64 usdiff;
b48aa97e 1151 bool matched;
8fe8ab46 1152 u64 data = msr->data;
99e3e30a 1153
038f8c11 1154 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1155 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1156 ns = get_kernel_ns();
f38e098f 1157 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1158
1159 /* n.b - signed multiplication and division required */
02626b6a 1160 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1161#ifdef CONFIG_X86_64
02626b6a 1162 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1163#else
1164 /* do_div() only does unsigned */
1165 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1166 : "=A"(usdiff)
1167 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1168#endif
02626b6a
MT		 1169 do_div(elapsed, 1000);
1170 usdiff -= elapsed;
1171 if (usdiff < 0)
1172 usdiff = -usdiff;
f38e098f
ZA		 1173
1174 /*
5d3cb0f6
ZA		 1175 * Special case: TSC write with a small delta (1 second) of virtual
1176 * cycle time against real time is interpreted as an attempt to
1177 * synchronize the CPU.
1178 *
1179 * For a reliable TSC, we can match TSC offsets, and for an unstable
1180 * TSC, we add elapsed time in this computation. We could let the
1181 * compensation code attempt to catch up if we fall behind, but
1182 * it's better to try to match offsets from the beginning.
1183 */
02626b6a 1184 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1185 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1186 if (!check_tsc_unstable()) {
e26101b1 1187 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1188 pr_debug("kvm: matched tsc offset for %llu\n", data);
1189 } else {
857e4099 1190 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1191 data += delta;
1192 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1193 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1194 }
b48aa97e 1195 matched = true;
e26101b1
ZA		 1196 } else {
1197 /*
1198 * We split periods of matched TSC writes into generations.
1199 * For each generation, we track the original measured
1200 * nanosecond time, offset, and write, so if TSCs are in
1201 * sync, we can match exact offset, and if not, we can match
4a969980 1202 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1203 *
1204 * These values are tracked in kvm->arch.cur_xxx variables.
1205 */
1206 kvm->arch.cur_tsc_generation++;
1207 kvm->arch.cur_tsc_nsec = ns;
1208 kvm->arch.cur_tsc_write = data;
1209 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1210 matched = false;
e26101b1
ZA		 1211 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1212 kvm->arch.cur_tsc_generation, data);
f38e098f 1213 }
e26101b1
ZA		 1214
1215 /*
1216 * We also track th most recent recorded KHZ, write and time to
1217 * allow the matching interval to be extended at each write.
1218 */
f38e098f
ZA		 1219 kvm->arch.last_tsc_nsec = ns;
1220 kvm->arch.last_tsc_write = data;
5d3cb0f6 1221 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1222
1223 /* Reset of TSC must disable overshoot protection below */
1224 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1225 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1226
1227 /* Keep track of which generation this VCPU has synchronized to */
1228 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1229 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1230 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1231
ba904635
WA		 1232 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1233 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1234 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1235 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1236
1237 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1238 if (matched)
1239 kvm->arch.nr_vcpus_matched_tsc++;
1240 else
1241 kvm->arch.nr_vcpus_matched_tsc = 0;
1242
1243 kvm_track_tsc_matching(vcpu);
1244 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1245}
e26101b1 1246
99e3e30a
ZA		 1247EXPORT_SYMBOL_GPL(kvm_write_tsc);
1248
d828199e
MT		 1249#ifdef CONFIG_X86_64
1250
1251static cycle_t read_tsc(void)
1252{
1253 cycle_t ret;
1254 u64 last;
1255
1256 /*
1257 * Empirically, a fence (of type that depends on the CPU)
1258 * before rdtsc is enough to ensure that rdtsc is ordered
1259 * with respect to loads. The various CPU manuals are unclear
1260 * as to whether rdtsc can be reordered with later loads,
1261 * but no one has ever seen it happen.
1262 */
1263 rdtsc_barrier();
1264 ret = (cycle_t)vget_cycles();
1265
1266 last = pvclock_gtod_data.clock.cycle_last;
1267
1268 if (likely(ret >= last))
1269 return ret;
1270
1271 /*
1272 * GCC likes to generate cmov here, but this branch is extremely
1273 * predictable (it's just a funciton of time and the likely is
1274 * very likely) and there's a data dependence, so force GCC
1275 * to generate a branch instead. I don't barrier() because
1276 * we don't actually need a barrier, and if this function
1277 * ever gets inlined it will generate worse code.
1278 */
1279 asm volatile ("");
1280 return last;
1281}
1282
1283static inline u64 vgettsc(cycle_t *cycle_now)
1284{
1285 long v;
1286 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1287
1288 *cycle_now = read_tsc();
1289
1290 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1291 return v * gtod->clock.mult;
1292}
1293
1294static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1295{
1296 unsigned long seq;
1297 u64 ns;
1298 int mode;
1299 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1300
1301 ts->tv_nsec = 0;
1302 do {
1303 seq = read_seqcount_begin(&gtod->seq);
1304 mode = gtod->clock.vclock_mode;
1305 ts->tv_sec = gtod->monotonic_time_sec;
1306 ns = gtod->monotonic_time_snsec;
1307 ns += vgettsc(cycle_now);
1308 ns >>= gtod->clock.shift;
1309 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1310 timespec_add_ns(ts, ns);
1311
1312 return mode;
1313}
1314
1315/* returns true if host is using tsc clocksource */
1316static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1317{
1318 struct timespec ts;
1319
1320 /* checked again under seqlock below */
1321 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1322 return false;
1323
1324 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1325 return false;
1326
1327 monotonic_to_bootbased(&ts);
1328 *kernel_ns = timespec_to_ns(&ts);
1329
1330 return true;
1331}
1332#endif
1333
1334/*
1335 *
b48aa97e
MT		 1336 * Assuming a stable TSC across physical CPUS, and a stable TSC
1337 * across virtual CPUs, the following condition is possible.
1338 * Each numbered line represents an event visible to both
d828199e
MT		 1339 * CPUs at the next numbered event.
1340 *
1341 * "timespecX" represents host monotonic time. "tscX" represents
1342 * RDTSC value.
1343 *
1344 * VCPU0 on CPU0 | VCPU1 on CPU1
1345 *
1346 * 1. read timespec0,tsc0
1347 * 2. | timespec1 = timespec0 + N
1348 * | tsc1 = tsc0 + M
1349 * 3. transition to guest | transition to guest
1350 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1351 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1352 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1353 *
1354 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1355 *
1356 * - ret0 < ret1
1357 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1358 * ...
1359 * - 0 < N - M => M < N
1360 *
1361 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1362 * always the case (the difference between two distinct xtime instances
1363 * might be smaller then the difference between corresponding TSC reads,
1364 * when updating guest vcpus pvclock areas).
1365 *
1366 * To avoid that problem, do not allow visibility of distinct
1367 * system_timestamp/tsc_timestamp values simultaneously: use a master
1368 * copy of host monotonic time values. Update that master copy
1369 * in lockstep.
1370 *
b48aa97e 1371 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1372 *
1373 */
1374
1375static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1376{
1377#ifdef CONFIG_X86_64
1378 struct kvm_arch *ka = &kvm->arch;
1379 int vclock_mode;
b48aa97e
MT		 1380 bool host_tsc_clocksource, vcpus_matched;
1381
1382 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1383 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1384
1385 /*
1386 * If the host uses TSC clock, then passthrough TSC as stable
1387 * to the guest.
1388 */
b48aa97e 1389 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1390 &ka->master_kernel_ns,
1391 &ka->master_cycle_now);
1392
b48aa97e
MT		 1393 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1394
d828199e
MT		 1395 if (ka->use_master_clock)
1396 atomic_set(&kvm_guest_has_master_clock, 1);
1397
1398 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1399 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1400 vcpus_matched);
d828199e
MT		 1401#endif
1402}
1403
34c238a1 1404static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1405{
d828199e 1406 unsigned long flags, this_tsc_khz;
18068523 1407 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1408 struct kvm_arch *ka = &v->kvm->arch;
18068523 1409 void *shared_kaddr;
1d5f066e 1410 s64 kernel_ns, max_kernel_ns;
d828199e 1411 u64 tsc_timestamp, host_tsc;
78c0337a 1412 struct pvclock_vcpu_time_info *guest_hv_clock;
51d59c6b 1413 u8 pvclock_flags;
d828199e
MT		 1414 bool use_master_clock;
1415
1416 kernel_ns = 0;
1417 host_tsc = 0;
18068523 1418
d828199e
MT		 1419 /*
1420 * If the host uses TSC clock, then passthrough TSC as stable
1421 * to the guest.
1422 */
1423 spin_lock(&ka->pvclock_gtod_sync_lock);
1424 use_master_clock = ka->use_master_clock;
1425 if (use_master_clock) {
1426 host_tsc = ka->master_cycle_now;
1427 kernel_ns = ka->master_kernel_ns;
1428 }
1429 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1430
1431 /* Keep irq disabled to prevent changes to the clock */
1432 local_irq_save(flags);
1433 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1434 if (unlikely(this_tsc_khz == 0)) {
1435 local_irq_restore(flags);
1436 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1437 return 1;
1438 }
d828199e
MT		 1439 if (!use_master_clock) {
1440 host_tsc = native_read_tsc();
1441 kernel_ns = get_kernel_ns();
1442 }
1443
1444 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1445
c285545f
ZA		 1446 /*
1447 * We may have to catch up the TSC to match elapsed wall clock
1448 * time for two reasons, even if kvmclock is used.
1449 * 1) CPU could have been running below the maximum TSC rate
1450 * 2) Broken TSC compensation resets the base at each VCPU
1451 * entry to avoid unknown leaps of TSC even when running
1452 * again on the same CPU. This may cause apparent elapsed
1453 * time to disappear, and the guest to stand still or run
1454 * very slowly.
1455 */
1456 if (vcpu->tsc_catchup) {
1457 u64 tsc = compute_guest_tsc(v, kernel_ns);
1458 if (tsc > tsc_timestamp) {
f1e2b260 1459 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1460 tsc_timestamp = tsc;
1461 }
50d0a0f9
GH		 1462 }
1463
18068523
GOC		 1464 local_irq_restore(flags);
1465
c285545f
ZA		 1466 if (!vcpu->time_page)
1467 return 0;
18068523 1468
1d5f066e
ZA		 1469 /*
1470 * Time as measured by the TSC may go backwards when resetting the base
1471 * tsc_timestamp. The reason for this is that the TSC resolution is
1472 * higher than the resolution of the other clock scales. Thus, many
1473 * possible measurments of the TSC correspond to one measurement of any
1474 * other clock, and so a spread of values is possible. This is not a
1475 * problem for the computation of the nanosecond clock; with TSC rates
1476 * around 1GHZ, there can only be a few cycles which correspond to one
1477 * nanosecond value, and any path through this code will inevitably
1478 * take longer than that. However, with the kernel_ns value itself,
1479 * the precision may be much lower, down to HZ granularity. If the
1480 * first sampling of TSC against kernel_ns ends in the low part of the
1481 * range, and the second in the high end of the range, we can get:
1482 *
1483 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1484 *
1485 * As the sampling errors potentially range in the thousands of cycles,
1486 * it is possible such a time value has already been observed by the
1487 * guest. To protect against this, we must compute the system time as
1488 * observed by the guest and ensure the new system time is greater.
1489 */
1490 max_kernel_ns = 0;
b183aa58 1491 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1492 max_kernel_ns = vcpu->last_guest_tsc -
1493 vcpu->hv_clock.tsc_timestamp;
1494 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1495 vcpu->hv_clock.tsc_to_system_mul,
1496 vcpu->hv_clock.tsc_shift);
1497 max_kernel_ns += vcpu->last_kernel_ns;
1498 }
afbcf7ab 1499
e48672fa 1500 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1501 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1502 &vcpu->hv_clock.tsc_shift,
1503 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1504 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1505 }
1506
d828199e
MT		 1507 /* with a master <monotonic time, tsc value> tuple,
1508 * pvclock clock reads always increase at the (scaled) rate
1509 * of guest TSC - no need to deal with sampling errors.
1510 */
1511 if (!use_master_clock) {
1512 if (max_kernel_ns > kernel_ns)
1513 kernel_ns = max_kernel_ns;
1514 }
8cfdc000 1515 /* With all the info we got, fill in the values */
1d5f066e 1516 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1517 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1518 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1519 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1520
18068523
GOC		 1521 /*
1522 * The interface expects us to write an even number signaling that the
1523 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1524 * state, we just increase by 2 at the end.
18068523 1525 */
50d0a0f9 1526 vcpu->hv_clock.version += 2;
18068523 1527
8fd75e12 1528 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523 1529
78c0337a
MT		 1530 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1531
1532 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1533 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1534
1535 if (vcpu->pvclock_set_guest_stopped_request) {
1536 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1537 vcpu->pvclock_set_guest_stopped_request = false;
1538 }
1539
d828199e
MT		 1540 /* If the host uses TSC clocksource, then it is stable */
1541 if (use_master_clock)
1542 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1543
78c0337a
MT		 1544 vcpu->hv_clock.flags = pvclock_flags;
1545
18068523 1546 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1547 sizeof(vcpu->hv_clock));
18068523 1548
8fd75e12 1549 kunmap_atomic(shared_kaddr);
18068523
GOC		 1550
1551 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1552 return 0;
c8076604
GH		 1553}
1554
9ba075a6
AK		 1555static bool msr_mtrr_valid(unsigned msr)
1556{
1557 switch (msr) {
1558 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1559 case MSR_MTRRfix64K_00000:
1560 case MSR_MTRRfix16K_80000:
1561 case MSR_MTRRfix16K_A0000:
1562 case MSR_MTRRfix4K_C0000:
1563 case MSR_MTRRfix4K_C8000:
1564 case MSR_MTRRfix4K_D0000:
1565 case MSR_MTRRfix4K_D8000:
1566 case MSR_MTRRfix4K_E0000:
1567 case MSR_MTRRfix4K_E8000:
1568 case MSR_MTRRfix4K_F0000:
1569 case MSR_MTRRfix4K_F8000:
1570 case MSR_MTRRdefType:
1571 case MSR_IA32_CR_PAT:
1572 return true;
1573 case 0x2f8:
1574 return true;
1575 }
1576 return false;
1577}
1578
d6289b93
MT		 1579static bool valid_pat_type(unsigned t)
1580{
1581 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1582}
1583
1584static bool valid_mtrr_type(unsigned t)
1585{
1586 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1587}
1588
1589static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1590{
1591 int i;
1592
1593 if (!msr_mtrr_valid(msr))
1594 return false;
1595
1596 if (msr == MSR_IA32_CR_PAT) {
1597 for (i = 0; i < 8; i++)
1598 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1599 return false;
1600 return true;
1601 } else if (msr == MSR_MTRRdefType) {
1602 if (data & ~0xcff)
1603 return false;
1604 return valid_mtrr_type(data & 0xff);
1605 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1606 for (i = 0; i < 8 ; i++)
1607 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1608 return false;
1609 return true;
1610 }
1611
1612 /* variable MTRRs */
1613 return valid_mtrr_type(data & 0xff);
1614}
1615
9ba075a6
AK		 1616static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1617{
0bed3b56
SY		 1618 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1619
d6289b93 1620 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1621 return 1;
1622
0bed3b56
SY		 1623 if (msr == MSR_MTRRdefType) {
1624 vcpu->arch.mtrr_state.def_type = data;
1625 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1626 } else if (msr == MSR_MTRRfix64K_00000)
1627 p[0] = data;
1628 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1629 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1630 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1631 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1632 else if (msr == MSR_IA32_CR_PAT)
1633 vcpu->arch.pat = data;
1634 else { /* Variable MTRRs */
1635 int idx, is_mtrr_mask;
1636 u64 *pt;
1637
1638 idx = (msr - 0x200) / 2;
1639 is_mtrr_mask = msr - 0x200 - 2 * idx;
1640 if (!is_mtrr_mask)
1641 pt =
1642 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1643 else
1644 pt =
1645 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1646 *pt = data;
1647 }
1648
1649 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1650 return 0;
1651}
15c4a640 1652
890ca9ae 1653static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1654{
890ca9ae
HY		 1655 u64 mcg_cap = vcpu->arch.mcg_cap;
1656 unsigned bank_num = mcg_cap & 0xff;
1657
15c4a640 1658 switch (msr) {
15c4a640 1659 case MSR_IA32_MCG_STATUS:
890ca9ae 1660 vcpu->arch.mcg_status = data;
15c4a640 1661 break;
c7ac679c 1662 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1663 if (!(mcg_cap & MCG_CTL_P))
1664 return 1;
1665 if (data != 0 && data != ~(u64)0)
1666 return -1;
1667 vcpu->arch.mcg_ctl = data;
1668 break;
1669 default:
1670 if (msr >= MSR_IA32_MC0_CTL &&
1671 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1672 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1673 /* only 0 or all 1s can be written to IA32_MCi_CTL
1674 * some Linux kernels though clear bit 10 in bank 4 to
1675 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1676 * this to avoid an uncatched #GP in the guest
1677 */
890ca9ae 1678 if ((offset & 0x3) == 0 &&
114be429 1679 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1680 return -1;
1681 vcpu->arch.mce_banks[offset] = data;
1682 break;
1683 }
1684 return 1;
1685 }
1686 return 0;
1687}
1688
ffde22ac
ES		 1689static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1690{
1691 struct kvm *kvm = vcpu->kvm;
1692 int lm = is_long_mode(vcpu);
1693 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1694 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1695 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1696 : kvm->arch.xen_hvm_config.blob_size_32;
1697 u32 page_num = data & ~PAGE_MASK;
1698 u64 page_addr = data & PAGE_MASK;
1699 u8 *page;
1700 int r;
1701
1702 r = -E2BIG;
1703 if (page_num >= blob_size)
1704 goto out;
1705 r = -ENOMEM;
ff5c2c03
SL		 1706 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1707 if (IS_ERR(page)) {
1708 r = PTR_ERR(page);
ffde22ac 1709 goto out;
ff5c2c03 1710 }
ffde22ac
ES		 1711 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1712 goto out_free;
1713 r = 0;
1714out_free:
1715 kfree(page);
1716out:
1717 return r;
1718}
1719
55cd8e5a
GN		 1720static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1721{
1722 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1723}
1724
1725static bool kvm_hv_msr_partition_wide(u32 msr)
1726{
1727 bool r = false;
1728 switch (msr) {
1729 case HV_X64_MSR_GUEST_OS_ID:
1730 case HV_X64_MSR_HYPERCALL:
1731 r = true;
1732 break;
1733 }
1734
1735 return r;
1736}
1737
1738static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1739{
1740 struct kvm *kvm = vcpu->kvm;
1741
1742 switch (msr) {
1743 case HV_X64_MSR_GUEST_OS_ID:
1744 kvm->arch.hv_guest_os_id = data;
1745 /* setting guest os id to zero disables hypercall page */
1746 if (!kvm->arch.hv_guest_os_id)
1747 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1748 break;
1749 case HV_X64_MSR_HYPERCALL: {
1750 u64 gfn;
1751 unsigned long addr;
1752 u8 instructions[4];
1753
1754 /* if guest os id is not set hypercall should remain disabled */
1755 if (!kvm->arch.hv_guest_os_id)
1756 break;
1757 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1758 kvm->arch.hv_hypercall = data;
1759 break;
1760 }
1761 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1762 addr = gfn_to_hva(kvm, gfn);
1763 if (kvm_is_error_hva(addr))
1764 return 1;
1765 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1766 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1767 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1768 return 1;
1769 kvm->arch.hv_hypercall = data;
1770 break;
1771 }
1772 default:
a737f256
CD		 1773 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1774 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1775 return 1;
1776 }
1777 return 0;
1778}
1779
1780static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1781{
10388a07
GN		 1782 switch (msr) {
1783 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1784 unsigned long addr;
55cd8e5a 1785
10388a07
GN		 1786 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1787 vcpu->arch.hv_vapic = data;
1788 break;
1789 }
1790 addr = gfn_to_hva(vcpu->kvm, data >>
1791 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1792 if (kvm_is_error_hva(addr))
1793 return 1;
8b0cedff 1794 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1795 return 1;
1796 vcpu->arch.hv_vapic = data;
1797 break;
1798 }
1799 case HV_X64_MSR_EOI:
1800 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1801 case HV_X64_MSR_ICR:
1802 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1803 case HV_X64_MSR_TPR:
1804 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1805 default:
a737f256
CD		 1806 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1807 "data 0x%llx\n", msr, data);
10388a07
GN		 1808 return 1;
1809 }
1810
1811 return 0;
55cd8e5a
GN		 1812}
1813
344d9588
GN		 1814static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1815{
1816 gpa_t gpa = data & ~0x3f;
1817
4a969980 1818 /* Bits 2:5 are reserved, Should be zero */
6adba527 1819 if (data & 0x3c)
344d9588
GN		 1820 return 1;
1821
1822 vcpu->arch.apf.msr_val = data;
1823
1824 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1825 kvm_clear_async_pf_completion_queue(vcpu);
1826 kvm_async_pf_hash_reset(vcpu);
1827 return 0;
1828 }
1829
1830 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1831 return 1;
1832
6adba527 1833 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1834 kvm_async_pf_wakeup_all(vcpu);
1835 return 0;
1836}
1837
12f9a48f
GC		 1838static void kvmclock_reset(struct kvm_vcpu *vcpu)
1839{
1840 if (vcpu->arch.time_page) {
1841 kvm_release_page_dirty(vcpu->arch.time_page);
1842 vcpu->arch.time_page = NULL;
1843 }
1844}
1845
c9aaa895
GC		 1846static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1847{
1848 u64 delta;
1849
1850 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1851 return;
1852
1853 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1854 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1855 vcpu->arch.st.accum_steal = delta;
1856}
1857
1858static void record_steal_time(struct kvm_vcpu *vcpu)
1859{
1860 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1861 return;
1862
1863 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1864 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1865 return;
1866
1867 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1868 vcpu->arch.st.steal.version += 2;
1869 vcpu->arch.st.accum_steal = 0;
1870
1871 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1872 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1873}
1874
8fe8ab46 1875int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1876{
5753785f 1877 bool pr = false;
8fe8ab46
WA		 1878 u32 msr = msr_info->index;
1879 u64 data = msr_info->data;
5753785f 1880
15c4a640 1881 switch (msr) {
2e32b719
BP		 1882 case MSR_AMD64_NB_CFG:
1883 case MSR_IA32_UCODE_REV:
1884 case MSR_IA32_UCODE_WRITE:
1885 case MSR_VM_HSAVE_PA:
1886 case MSR_AMD64_PATCH_LOADER:
1887 case MSR_AMD64_BU_CFG2:
1888 break;
1889
15c4a640 1890 case MSR_EFER:
b69e8cae 1891 return set_efer(vcpu, data);
8f1589d9
AP		 1892 case MSR_K7_HWCR:
1893 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1894 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1895 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1896 if (data != 0) {
a737f256
CD		 1897 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1898 data);
8f1589d9
AP		 1899 return 1;
1900 }
15c4a640 1901 break;
f7c6d140
AP		 1902 case MSR_FAM10H_MMIO_CONF_BASE:
1903 if (data != 0) {
a737f256
CD		 1904 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1905 "0x%llx\n", data);
f7c6d140
AP		 1906 return 1;
1907 }
15c4a640 1908 break;
b5e2fec0
AG		 1909 case MSR_IA32_DEBUGCTLMSR:
1910 if (!data) {
1911 /* We support the non-activated case already */
1912 break;
1913 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1914 /* Values other than LBR and BTF are vendor-specific,
1915 thus reserved and should throw a #GP */
1916 return 1;
1917 }
a737f256
CD		 1918 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1919 __func__, data);
b5e2fec0 1920 break;
9ba075a6
AK		 1921 case 0x200 ... 0x2ff:
1922 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1923 case MSR_IA32_APICBASE:
1924 kvm_set_apic_base(vcpu, data);
1925 break;
0105d1a5
GN		 1926 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1927 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1928 case MSR_IA32_TSCDEADLINE:
1929 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1930 break;
ba904635
WA		 1931 case MSR_IA32_TSC_ADJUST:
1932 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1933 if (!msr_info->host_initiated) {
1934 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1935 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1936 }
1937 vcpu->arch.ia32_tsc_adjust_msr = data;
1938 }
1939 break;
15c4a640 1940 case MSR_IA32_MISC_ENABLE:
ad312c7c 1941 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1942 break;
11c6bffa 1943 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1944 case MSR_KVM_WALL_CLOCK:
1945 vcpu->kvm->arch.wall_clock = data;
1946 kvm_write_wall_clock(vcpu->kvm, data);
1947 break;
11c6bffa 1948 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1949 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1950 kvmclock_reset(vcpu);
18068523
GOC		 1951
1952 vcpu->arch.time = data;
c285545f 1953 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1954
1955 /* we verify if the enable bit is set... */
1956 if (!(data & 1))
1957 break;
1958
1959 /* ...but clean it before doing the actual write */
1960 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1961
c300aa64
AH		 1962 /* Check that the address is 32-byte aligned. */
1963 if (vcpu->arch.time_offset &
1964 (sizeof(struct pvclock_vcpu_time_info) - 1))
1965 break;
1966
18068523
GOC		 1967 vcpu->arch.time_page =
1968 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1969
32cad84f 1970 if (is_error_page(vcpu->arch.time_page))
18068523 1971 vcpu->arch.time_page = NULL;
32cad84f 1972
18068523
GOC		 1973 break;
1974 }
344d9588
GN		 1975 case MSR_KVM_ASYNC_PF_EN:
1976 if (kvm_pv_enable_async_pf(vcpu, data))
1977 return 1;
1978 break;
c9aaa895
GC		 1979 case MSR_KVM_STEAL_TIME:
1980
1981 if (unlikely(!sched_info_on()))
1982 return 1;
1983
1984 if (data & KVM_STEAL_RESERVED_MASK)
1985 return 1;
1986
1987 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1988 data & KVM_STEAL_VALID_BITS))
1989 return 1;
1990
1991 vcpu->arch.st.msr_val = data;
1992
1993 if (!(data & KVM_MSR_ENABLED))
1994 break;
1995
1996 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1997
1998 preempt_disable();
1999 accumulate_steal_time(vcpu);
2000 preempt_enable();
2001
2002 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2003
2004 break;
ae7a2a3f
MT		 2005 case MSR_KVM_PV_EOI_EN:
2006 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2007 return 1;
2008 break;
c9aaa895 2009
890ca9ae
HY		 2010 case MSR_IA32_MCG_CTL:
2011 case MSR_IA32_MCG_STATUS:
2012 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2013 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2014
2015 /* Performance counters are not protected by a CPUID bit,
2016 * so we should check all of them in the generic path for the sake of
2017 * cross vendor migration.
2018 * Writing a zero into the event select MSRs disables them,
2019 * which we perfectly emulate ;-). Any other value should be at least
2020 * reported, some guests depend on them.
2021 */
71db6023
AP		 2022 case MSR_K7_EVNTSEL0:
2023 case MSR_K7_EVNTSEL1:
2024 case MSR_K7_EVNTSEL2:
2025 case MSR_K7_EVNTSEL3:
2026 if (data != 0)
a737f256
CD		 2027 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2028 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2029 break;
2030 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2031 * so we ignore writes to make it happy.
2032 */
71db6023
AP		 2033 case MSR_K7_PERFCTR0:
2034 case MSR_K7_PERFCTR1:
2035 case MSR_K7_PERFCTR2:
2036 case MSR_K7_PERFCTR3:
a737f256
CD		 2037 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2038 "0x%x data 0x%llx\n", msr, data);
71db6023 2039 break;
5753785f
GN		 2040 case MSR_P6_PERFCTR0:
2041 case MSR_P6_PERFCTR1:
2042 pr = true;
2043 case MSR_P6_EVNTSEL0:
2044 case MSR_P6_EVNTSEL1:
2045 if (kvm_pmu_msr(vcpu, msr))
2046 return kvm_pmu_set_msr(vcpu, msr, data);
2047
2048 if (pr || data != 0)
a737f256
CD		 2049 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2050 "0x%x data 0x%llx\n", msr, data);
5753785f 2051 break;
84e0cefa
JS		 2052 case MSR_K7_CLK_CTL:
2053 /*
2054 * Ignore all writes to this no longer documented MSR.
2055 * Writes are only relevant for old K7 processors,
2056 * all pre-dating SVM, but a recommended workaround from
4a969980 2057 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2058 * affected processor models on the command line, hence
2059 * the need to ignore the workaround.
2060 */
2061 break;
55cd8e5a
GN		 2062 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2063 if (kvm_hv_msr_partition_wide(msr)) {
2064 int r;
2065 mutex_lock(&vcpu->kvm->lock);
2066 r = set_msr_hyperv_pw(vcpu, msr, data);
2067 mutex_unlock(&vcpu->kvm->lock);
2068 return r;
2069 } else
2070 return set_msr_hyperv(vcpu, msr, data);
2071 break;
91c9c3ed 2072 case MSR_IA32_BBL_CR_CTL3:
2073 /* Drop writes to this legacy MSR -- see rdmsr
2074 * counterpart for further detail.
2075 */
a737f256 2076 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2077 break;
2b036c6b
BO		 2078 case MSR_AMD64_OSVW_ID_LENGTH:
2079 if (!guest_cpuid_has_osvw(vcpu))
2080 return 1;
2081 vcpu->arch.osvw.length = data;
2082 break;
2083 case MSR_AMD64_OSVW_STATUS:
2084 if (!guest_cpuid_has_osvw(vcpu))
2085 return 1;
2086 vcpu->arch.osvw.status = data;
2087 break;
15c4a640 2088 default:
ffde22ac
ES		 2089 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2090 return xen_hvm_config(vcpu, data);
f5132b01
GN		 2091 if (kvm_pmu_msr(vcpu, msr))
2092 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 2093 if (!ignore_msrs) {
a737f256
CD		 2094 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2095 msr, data);
ed85c068
AP		 2096 return 1;
2097 } else {
a737f256
CD		 2098 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2099 msr, data);
ed85c068
AP		 2100 break;
2101 }
15c4a640
CO		 2102 }
2103 return 0;
2104}
2105EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2106
2107
2108/*
2109 * Reads an msr value (of 'msr_index') into 'pdata'.
2110 * Returns 0 on success, non-0 otherwise.
2111 * Assumes vcpu_load() was already called.
2112 */
2113int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2114{
2115 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2116}
2117
9ba075a6
AK		 2118static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2119{
0bed3b56
SY		 2120 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2121
9ba075a6
AK		 2122 if (!msr_mtrr_valid(msr))
2123 return 1;
2124
0bed3b56
SY		 2125 if (msr == MSR_MTRRdefType)
2126 *pdata = vcpu->arch.mtrr_state.def_type +
2127 (vcpu->arch.mtrr_state.enabled << 10);
2128 else if (msr == MSR_MTRRfix64K_00000)
2129 *pdata = p[0];
2130 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2131 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2132 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2133 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2134 else if (msr == MSR_IA32_CR_PAT)
2135 *pdata = vcpu->arch.pat;
2136 else { /* Variable MTRRs */
2137 int idx, is_mtrr_mask;
2138 u64 *pt;
2139
2140 idx = (msr - 0x200) / 2;
2141 is_mtrr_mask = msr - 0x200 - 2 * idx;
2142 if (!is_mtrr_mask)
2143 pt =
2144 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2145 else
2146 pt =
2147 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2148 *pdata = *pt;
2149 }
2150
9ba075a6
AK		 2151 return 0;
2152}
2153
890ca9ae 2154static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2155{
2156 u64 data;
890ca9ae
HY		 2157 u64 mcg_cap = vcpu->arch.mcg_cap;
2158 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2159
2160 switch (msr) {
15c4a640
CO		 2161 case MSR_IA32_P5_MC_ADDR:
2162 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2163 data = 0;
2164 break;
15c4a640 2165 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2166 data = vcpu->arch.mcg_cap;
2167 break;
c7ac679c 2168 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2169 if (!(mcg_cap & MCG_CTL_P))
2170 return 1;
2171 data = vcpu->arch.mcg_ctl;
2172 break;
2173 case MSR_IA32_MCG_STATUS:
2174 data = vcpu->arch.mcg_status;
2175 break;
2176 default:
2177 if (msr >= MSR_IA32_MC0_CTL &&
2178 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2179 u32 offset = msr - MSR_IA32_MC0_CTL;
2180 data = vcpu->arch.mce_banks[offset];
2181 break;
2182 }
2183 return 1;
2184 }
2185 *pdata = data;
2186 return 0;
2187}
2188
55cd8e5a
GN		 2189static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2190{
2191 u64 data = 0;
2192 struct kvm *kvm = vcpu->kvm;
2193
2194 switch (msr) {
2195 case HV_X64_MSR_GUEST_OS_ID:
2196 data = kvm->arch.hv_guest_os_id;
2197 break;
2198 case HV_X64_MSR_HYPERCALL:
2199 data = kvm->arch.hv_hypercall;
2200 break;
2201 default:
a737f256 2202 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2203 return 1;
2204 }
2205
2206 *pdata = data;
2207 return 0;
2208}
2209
2210static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2211{
2212 u64 data = 0;
2213
2214 switch (msr) {
2215 case HV_X64_MSR_VP_INDEX: {
2216 int r;
2217 struct kvm_vcpu *v;
2218 kvm_for_each_vcpu(r, v, vcpu->kvm)
2219 if (v == vcpu)
2220 data = r;
2221 break;
2222 }
10388a07
GN		 2223 case HV_X64_MSR_EOI:
2224 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2225 case HV_X64_MSR_ICR:
2226 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2227 case HV_X64_MSR_TPR:
2228 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2229 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2230 data = vcpu->arch.hv_vapic;
2231 break;
55cd8e5a 2232 default:
a737f256 2233 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2234 return 1;
2235 }
2236 *pdata = data;
2237 return 0;
2238}
2239
890ca9ae
HY		 2240int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2241{
2242 u64 data;
2243
2244 switch (msr) {
890ca9ae 2245 case MSR_IA32_PLATFORM_ID:
15c4a640 2246 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2247 case MSR_IA32_DEBUGCTLMSR:
2248 case MSR_IA32_LASTBRANCHFROMIP:
2249 case MSR_IA32_LASTBRANCHTOIP:
2250 case MSR_IA32_LASTINTFROMIP:
2251 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2252 case MSR_K8_SYSCFG:
2253 case MSR_K7_HWCR:
61a6bd67 2254 case MSR_VM_HSAVE_PA:
9e699624 2255 case MSR_K7_EVNTSEL0:
1f3ee616 2256 case MSR_K7_PERFCTR0:
1fdbd48c 2257 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2258 case MSR_AMD64_NB_CFG:
f7c6d140 2259 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2260 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2261 data = 0;
2262 break;
5753785f
GN		 2263 case MSR_P6_PERFCTR0:
2264 case MSR_P6_PERFCTR1:
2265 case MSR_P6_EVNTSEL0:
2266 case MSR_P6_EVNTSEL1:
2267 if (kvm_pmu_msr(vcpu, msr))
2268 return kvm_pmu_get_msr(vcpu, msr, pdata);
2269 data = 0;
2270 break;
742bc670
MT		 2271 case MSR_IA32_UCODE_REV:
2272 data = 0x100000000ULL;
2273 break;
9ba075a6
AK		 2274 case MSR_MTRRcap:
2275 data = 0x500 | KVM_NR_VAR_MTRR;
2276 break;
2277 case 0x200 ... 0x2ff:
2278 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2279 case 0xcd: /* fsb frequency */
2280 data = 3;
2281 break;
7b914098
JS		 2282 /*
2283 * MSR_EBC_FREQUENCY_ID
2284 * Conservative value valid for even the basic CPU models.
2285 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2286 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2287 * and 266MHz for model 3, or 4. Set Core Clock
2288 * Frequency to System Bus Frequency Ratio to 1 (bits
2289 * 31:24) even though these are only valid for CPU
2290 * models > 2, however guests may end up dividing or
2291 * multiplying by zero otherwise.
2292 */
2293 case MSR_EBC_FREQUENCY_ID:
2294 data = 1 << 24;
2295 break;
15c4a640
CO		 2296 case MSR_IA32_APICBASE:
2297 data = kvm_get_apic_base(vcpu);
2298 break;
0105d1a5
GN		 2299 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2300 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2301 break;
a3e06bbe
LJ		 2302 case MSR_IA32_TSCDEADLINE:
2303 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2304 break;
ba904635
WA		 2305 case MSR_IA32_TSC_ADJUST:
2306 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2307 break;
15c4a640 2308 case MSR_IA32_MISC_ENABLE:
ad312c7c 2309 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2310 break;
847f0ad8
AG		 2311 case MSR_IA32_PERF_STATUS:
2312 /* TSC increment by tick */
2313 data = 1000ULL;
2314 /* CPU multiplier */
2315 data |= (((uint64_t)4ULL) << 40);
2316 break;
15c4a640 2317 case MSR_EFER:
f6801dff 2318 data = vcpu->arch.efer;
15c4a640 2319 break;
18068523 2320 case MSR_KVM_WALL_CLOCK:
11c6bffa 2321 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2322 data = vcpu->kvm->arch.wall_clock;
2323 break;
2324 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2325 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2326 data = vcpu->arch.time;
2327 break;
344d9588
GN		 2328 case MSR_KVM_ASYNC_PF_EN:
2329 data = vcpu->arch.apf.msr_val;
2330 break;
c9aaa895
GC		 2331 case MSR_KVM_STEAL_TIME:
2332 data = vcpu->arch.st.msr_val;
2333 break;
1d92128f
MT		 2334 case MSR_KVM_PV_EOI_EN:
2335 data = vcpu->arch.pv_eoi.msr_val;
2336 break;
890ca9ae
HY		 2337 case MSR_IA32_P5_MC_ADDR:
2338 case MSR_IA32_P5_MC_TYPE:
2339 case MSR_IA32_MCG_CAP:
2340 case MSR_IA32_MCG_CTL:
2341 case MSR_IA32_MCG_STATUS:
2342 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2343 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2344 case MSR_K7_CLK_CTL:
2345 /*
2346 * Provide expected ramp-up count for K7. All other
2347 * are set to zero, indicating minimum divisors for
2348 * every field.
2349 *
2350 * This prevents guest kernels on AMD host with CPU
2351 * type 6, model 8 and higher from exploding due to
2352 * the rdmsr failing.
2353 */
2354 data = 0x20000000;
2355 break;
55cd8e5a
GN		 2356 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2357 if (kvm_hv_msr_partition_wide(msr)) {
2358 int r;
2359 mutex_lock(&vcpu->kvm->lock);
2360 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2361 mutex_unlock(&vcpu->kvm->lock);
2362 return r;
2363 } else
2364 return get_msr_hyperv(vcpu, msr, pdata);
2365 break;
91c9c3ed 2366 case MSR_IA32_BBL_CR_CTL3:
2367 /* This legacy MSR exists but isn't fully documented in current
2368 * silicon. It is however accessed by winxp in very narrow
2369 * scenarios where it sets bit #19, itself documented as
2370 * a "reserved" bit. Best effort attempt to source coherent
2371 * read data here should the balance of the register be
2372 * interpreted by the guest:
2373 *
2374 * L2 cache control register 3: 64GB range, 256KB size,
2375 * enabled, latency 0x1, configured
2376 */
2377 data = 0xbe702111;
2378 break;
2b036c6b
BO		 2379 case MSR_AMD64_OSVW_ID_LENGTH:
2380 if (!guest_cpuid_has_osvw(vcpu))
2381 return 1;
2382 data = vcpu->arch.osvw.length;
2383 break;
2384 case MSR_AMD64_OSVW_STATUS:
2385 if (!guest_cpuid_has_osvw(vcpu))
2386 return 1;
2387 data = vcpu->arch.osvw.status;
2388 break;
15c4a640 2389 default:
f5132b01
GN		 2390 if (kvm_pmu_msr(vcpu, msr))
2391 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2392 if (!ignore_msrs) {
a737f256 2393 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2394 return 1;
2395 } else {
a737f256 2396 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2397 data = 0;
2398 }
2399 break;
15c4a640
CO		 2400 }
2401 *pdata = data;
2402 return 0;
2403}
2404EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2405
313a3dc7
CO		 2406/*
2407 * Read or write a bunch of msrs. All parameters are kernel addresses.
2408 *
2409 * @return number of msrs set successfully.
2410 */
2411static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2412 struct kvm_msr_entry *entries,
2413 int (*do_msr)(struct kvm_vcpu *vcpu,
2414 unsigned index, u64 *data))
2415{
f656ce01 2416 int i, idx;
313a3dc7 2417
f656ce01 2418 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2419 for (i = 0; i < msrs->nmsrs; ++i)
2420 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2421 break;
f656ce01 2422 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2423
313a3dc7
CO		 2424 return i;
2425}
2426
2427/*
2428 * Read or write a bunch of msrs. Parameters are user addresses.
2429 *
2430 * @return number of msrs set successfully.
2431 */
2432static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2433 int (*do_msr)(struct kvm_vcpu *vcpu,
2434 unsigned index, u64 *data),
2435 int writeback)
2436{
2437 struct kvm_msrs msrs;
2438 struct kvm_msr_entry *entries;
2439 int r, n;
2440 unsigned size;
2441
2442 r = -EFAULT;
2443 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2444 goto out;
2445
2446 r = -E2BIG;
2447 if (msrs.nmsrs >= MAX_IO_MSRS)
2448 goto out;
2449
313a3dc7 2450 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2451 entries = memdup_user(user_msrs->entries, size);
2452 if (IS_ERR(entries)) {
2453 r = PTR_ERR(entries);
313a3dc7 2454 goto out;
ff5c2c03 2455 }
313a3dc7
CO		 2456
2457 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2458 if (r < 0)
2459 goto out_free;
2460
2461 r = -EFAULT;
2462 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2463 goto out_free;
2464
2465 r = n;
2466
2467out_free:
7a73c028 2468 kfree(entries);
313a3dc7
CO		 2469out:
2470 return r;
2471}
2472
018d00d2
ZX		 2473int kvm_dev_ioctl_check_extension(long ext)
2474{
2475 int r;
2476
2477 switch (ext) {
2478 case KVM_CAP_IRQCHIP:
2479 case KVM_CAP_HLT:
2480 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2481 case KVM_CAP_SET_TSS_ADDR:
07716717 2482 case KVM_CAP_EXT_CPUID:
c8076604 2483 case KVM_CAP_CLOCKSOURCE:
7837699f 2484 case KVM_CAP_PIT:
a28e4f5a 2485 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2486 case KVM_CAP_MP_STATE:
ed848624 2487 case KVM_CAP_SYNC_MMU:
a355c85c 2488 case KVM_CAP_USER_NMI:
52d939a0 2489 case KVM_CAP_REINJECT_CONTROL:
4925663a 2490 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2491 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2492 case KVM_CAP_IRQFD:
d34e6b17 2493 case KVM_CAP_IOEVENTFD:
c5ff41ce 2494 case KVM_CAP_PIT2:
e9f42757 2495 case KVM_CAP_PIT_STATE2:
b927a3ce 2496 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2497 case KVM_CAP_XEN_HVM:
afbcf7ab 2498 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2499 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2500 case KVM_CAP_HYPERV:
10388a07 2501 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2502 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2503 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2504 case KVM_CAP_DEBUGREGS:
d2be1651 2505 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2506 case KVM_CAP_XSAVE:
344d9588 2507 case KVM_CAP_ASYNC_PF:
92a1f12d 2508 case KVM_CAP_GET_TSC_KHZ:
07700a94 2509 case KVM_CAP_PCI_2_3:
1c0b28c2 2510 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2511 case KVM_CAP_READONLY_MEM:
7a84428a 2512 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2513 r = 1;
2514 break;
542472b5
LV		 2515 case KVM_CAP_COALESCED_MMIO:
2516 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2517 break;
774ead3a
AK		 2518 case KVM_CAP_VAPIC:
2519 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2520 break;
f725230a 2521 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2522 r = KVM_SOFT_MAX_VCPUS;
2523 break;
2524 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2525 r = KVM_MAX_VCPUS;
2526 break;
a988b910 2527 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2528 r = KVM_USER_MEM_SLOTS;
a988b910 2529 break;
a68a6a72
MT		 2530 case KVM_CAP_PV_MMU: /* obsolete */
2531 r = 0;
2f333bcb 2532 break;
62c476c7 2533 case KVM_CAP_IOMMU:
a1b60c1c 2534 r = iommu_present(&pci_bus_type);
62c476c7 2535 break;
890ca9ae
HY		 2536 case KVM_CAP_MCE:
2537 r = KVM_MAX_MCE_BANKS;
2538 break;
2d5b5a66
SY		 2539 case KVM_CAP_XCRS:
2540 r = cpu_has_xsave;
2541 break;
92a1f12d
JR		 2542 case KVM_CAP_TSC_CONTROL:
2543 r = kvm_has_tsc_control;
2544 break;
4d25a066
JK		 2545 case KVM_CAP_TSC_DEADLINE_TIMER:
2546 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2547 break;
018d00d2
ZX		 2548 default:
2549 r = 0;
2550 break;
2551 }
2552 return r;
2553
2554}
2555
043405e1
CO		 2556long kvm_arch_dev_ioctl(struct file *filp,
2557 unsigned int ioctl, unsigned long arg)
2558{
2559 void __user *argp = (void __user *)arg;
2560 long r;
2561
2562 switch (ioctl) {
2563 case KVM_GET_MSR_INDEX_LIST: {
2564 struct kvm_msr_list __user *user_msr_list = argp;
2565 struct kvm_msr_list msr_list;
2566 unsigned n;
2567
2568 r = -EFAULT;
2569 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2570 goto out;
2571 n = msr_list.nmsrs;
2572 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2573 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2574 goto out;
2575 r = -E2BIG;
e125e7b6 2576 if (n < msr_list.nmsrs)
043405e1
CO		 2577 goto out;
2578 r = -EFAULT;
2579 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2580 num_msrs_to_save * sizeof(u32)))
2581 goto out;
e125e7b6 2582 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2583 &emulated_msrs,
2584 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2585 goto out;
2586 r = 0;
2587 break;
2588 }
674eea0f
AK		 2589 case KVM_GET_SUPPORTED_CPUID: {
2590 struct kvm_cpuid2 __user *cpuid_arg = argp;
2591 struct kvm_cpuid2 cpuid;
2592
2593 r = -EFAULT;
2594 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2595 goto out;
2596 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2597 cpuid_arg->entries);
674eea0f
AK		 2598 if (r)
2599 goto out;
2600
2601 r = -EFAULT;
2602 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2603 goto out;
2604 r = 0;
2605 break;
2606 }
890ca9ae
HY		 2607 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2608 u64 mce_cap;
2609
2610 mce_cap = KVM_MCE_CAP_SUPPORTED;
2611 r = -EFAULT;
2612 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2613 goto out;
2614 r = 0;
2615 break;
2616 }
043405e1
CO		 2617 default:
2618 r = -EINVAL;
2619 }
2620out:
2621 return r;
2622}
2623
f5f48ee1
SY		 2624static void wbinvd_ipi(void *garbage)
2625{
2626 wbinvd();
2627}
2628
2629static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2630{
2631 return vcpu->kvm->arch.iommu_domain &&
2632 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2633}
2634
313a3dc7
CO		 2635void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2636{
f5f48ee1
SY		 2637 /* Address WBINVD may be executed by guest */
2638 if (need_emulate_wbinvd(vcpu)) {
2639 if (kvm_x86_ops->has_wbinvd_exit())
2640 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2641 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2642 smp_call_function_single(vcpu->cpu,
2643 wbinvd_ipi, NULL, 1);
2644 }
2645
313a3dc7 2646 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2647
0dd6a6ed
ZA		 2648 /* Apply any externally detected TSC adjustments (due to suspend) */
2649 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2650 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2651 vcpu->arch.tsc_offset_adjustment = 0;
2652 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2653 }
8f6055cb 2654
48434c20 2655 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2656 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2657 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2658 if (tsc_delta < 0)
2659 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2660 if (check_tsc_unstable()) {
b183aa58
ZA		 2661 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2662 vcpu->arch.last_guest_tsc);
2663 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2664 vcpu->arch.tsc_catchup = 1;
c285545f 2665 }
d98d07ca
MT		 2666 /*
2667 * On a host with synchronized TSC, there is no need to update
2668 * kvmclock on vcpu->cpu migration
2669 */
2670 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2671 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2672 if (vcpu->cpu != cpu)
2673 kvm_migrate_timers(vcpu);
e48672fa 2674 vcpu->cpu = cpu;
6b7d7e76 2675 }
c9aaa895
GC		 2676
2677 accumulate_steal_time(vcpu);
2678 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2679}
2680
2681void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2682{
02daab21 2683 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2684 kvm_put_guest_fpu(vcpu);
6f526ec5 2685 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2686}
2687
313a3dc7
CO		 2688static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2689 struct kvm_lapic_state *s)
2690{
ad312c7c 2691 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2692
2693 return 0;
2694}
2695
2696static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2697 struct kvm_lapic_state *s)
2698{
64eb0620 2699 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2700 update_cr8_intercept(vcpu);
313a3dc7
CO		 2701
2702 return 0;
2703}
2704
f77bc6a4
ZX		 2705static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2706 struct kvm_interrupt *irq)
2707{
a50abc3b 2708 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2709 return -EINVAL;
2710 if (irqchip_in_kernel(vcpu->kvm))
2711 return -ENXIO;
f77bc6a4 2712
66fd3f7f 2713 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2714 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2715
f77bc6a4
ZX		 2716 return 0;
2717}
2718
c4abb7c9
JK		 2719static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2720{
c4abb7c9 2721 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2722
2723 return 0;
2724}
2725
b209749f
AK		 2726static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2727 struct kvm_tpr_access_ctl *tac)
2728{
2729 if (tac->flags)
2730 return -EINVAL;
2731 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2732 return 0;
2733}
2734
890ca9ae
HY		 2735static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2736 u64 mcg_cap)
2737{
2738 int r;
2739 unsigned bank_num = mcg_cap & 0xff, bank;
2740
2741 r = -EINVAL;
a9e38c3e 2742 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2743 goto out;
2744 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2745 goto out;
2746 r = 0;
2747 vcpu->arch.mcg_cap = mcg_cap;
2748 /* Init IA32_MCG_CTL to all 1s */
2749 if (mcg_cap & MCG_CTL_P)
2750 vcpu->arch.mcg_ctl = ~(u64)0;
2751 /* Init IA32_MCi_CTL to all 1s */
2752 for (bank = 0; bank < bank_num; bank++)
2753 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2754out:
2755 return r;
2756}
2757
2758static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2759 struct kvm_x86_mce *mce)
2760{
2761 u64 mcg_cap = vcpu->arch.mcg_cap;
2762 unsigned bank_num = mcg_cap & 0xff;
2763 u64 *banks = vcpu->arch.mce_banks;
2764
2765 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2766 return -EINVAL;
2767 /*
2768 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2769 * reporting is disabled
2770 */
2771 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2772 vcpu->arch.mcg_ctl != ~(u64)0)
2773 return 0;
2774 banks += 4 * mce->bank;
2775 /*
2776 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2777 * reporting is disabled for the bank
2778 */
2779 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2780 return 0;
2781 if (mce->status & MCI_STATUS_UC) {
2782 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2783 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2784 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2785 return 0;
2786 }
2787 if (banks[1] & MCI_STATUS_VAL)
2788 mce->status |= MCI_STATUS_OVER;
2789 banks[2] = mce->addr;
2790 banks[3] = mce->misc;
2791 vcpu->arch.mcg_status = mce->mcg_status;
2792 banks[1] = mce->status;
2793 kvm_queue_exception(vcpu, MC_VECTOR);
2794 } else if (!(banks[1] & MCI_STATUS_VAL)
2795 || !(banks[1] & MCI_STATUS_UC)) {
2796 if (banks[1] & MCI_STATUS_VAL)
2797 mce->status |= MCI_STATUS_OVER;
2798 banks[2] = mce->addr;
2799 banks[3] = mce->misc;
2800 banks[1] = mce->status;
2801 } else
2802 banks[1] |= MCI_STATUS_OVER;
2803 return 0;
2804}
2805
3cfc3092
JK		 2806static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2807 struct kvm_vcpu_events *events)
2808{
7460fb4a 2809 process_nmi(vcpu);
03b82a30
JK		 2810 events->exception.injected =
2811 vcpu->arch.exception.pending &&
2812 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2813 events->exception.nr = vcpu->arch.exception.nr;
2814 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2815 events->exception.pad = 0;
3cfc3092
JK		 2816 events->exception.error_code = vcpu->arch.exception.error_code;
2817
03b82a30
JK		 2818 events->interrupt.injected =
2819 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2820 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2821 events->interrupt.soft = 0;
48005f64
JK		 2822 events->interrupt.shadow =
2823 kvm_x86_ops->get_interrupt_shadow(vcpu,
2824 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2825
2826 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2827 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2828 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2829 events->nmi.pad = 0;
3cfc3092
JK		 2830
2831 events->sipi_vector = vcpu->arch.sipi_vector;
2832
dab4b911 2833 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2834 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2835 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2836 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2837}
2838
2839static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2840 struct kvm_vcpu_events *events)
2841{
dab4b911 2842 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2843 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2844 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2845 return -EINVAL;
2846
7460fb4a 2847 process_nmi(vcpu);
3cfc3092
JK		 2848 vcpu->arch.exception.pending = events->exception.injected;
2849 vcpu->arch.exception.nr = events->exception.nr;
2850 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2851 vcpu->arch.exception.error_code = events->exception.error_code;
2852
2853 vcpu->arch.interrupt.pending = events->interrupt.injected;
2854 vcpu->arch.interrupt.nr = events->interrupt.nr;
2855 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2856 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2857 kvm_x86_ops->set_interrupt_shadow(vcpu,
2858 events->interrupt.shadow);
3cfc3092
JK		 2859
2860 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2861 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2862 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2863 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2864
dab4b911
JK		 2865 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2866 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2867
3842d135
AK		 2868 kvm_make_request(KVM_REQ_EVENT, vcpu);
2869
3cfc3092
JK		 2870 return 0;
2871}
2872
a1efbe77
JK		 2873static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2874 struct kvm_debugregs *dbgregs)
2875{
a1efbe77
JK		 2876 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2877 dbgregs->dr6 = vcpu->arch.dr6;
2878 dbgregs->dr7 = vcpu->arch.dr7;
2879 dbgregs->flags = 0;
97e69aa6 2880 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2881}
2882
2883static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2884 struct kvm_debugregs *dbgregs)
2885{
2886 if (dbgregs->flags)
2887 return -EINVAL;
2888
a1efbe77
JK		 2889 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2890 vcpu->arch.dr6 = dbgregs->dr6;
2891 vcpu->arch.dr7 = dbgregs->dr7;
2892
a1efbe77
JK		 2893 return 0;
2894}
2895
2d5b5a66
SY		 2896static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2897 struct kvm_xsave *guest_xsave)
2898{
2899 if (cpu_has_xsave)
2900 memcpy(guest_xsave->region,
2901 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2902 xstate_size);
2d5b5a66
SY		 2903 else {
2904 memcpy(guest_xsave->region,
2905 &vcpu->arch.guest_fpu.state->fxsave,
2906 sizeof(struct i387_fxsave_struct));
2907 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2908 XSTATE_FPSSE;
2909 }
2910}
2911
2912static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2913 struct kvm_xsave *guest_xsave)
2914{
2915 u64 xstate_bv =
2916 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2917
2918 if (cpu_has_xsave)
2919 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2920 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2921 else {
2922 if (xstate_bv & ~XSTATE_FPSSE)
2923 return -EINVAL;
2924 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2925 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2926 }
2927 return 0;
2928}
2929
2930static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2931 struct kvm_xcrs *guest_xcrs)
2932{
2933 if (!cpu_has_xsave) {
2934 guest_xcrs->nr_xcrs = 0;
2935 return;
2936 }
2937
2938 guest_xcrs->nr_xcrs = 1;
2939 guest_xcrs->flags = 0;
2940 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2941 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2942}
2943
2944static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2945 struct kvm_xcrs *guest_xcrs)
2946{
2947 int i, r = 0;
2948
2949 if (!cpu_has_xsave)
2950 return -EINVAL;
2951
2952 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2953 return -EINVAL;
2954
2955 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2956 /* Only support XCR0 currently */
2957 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2958 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2959 guest_xcrs->xcrs[0].value);
2960 break;
2961 }
2962 if (r)
2963 r = -EINVAL;
2964 return r;
2965}
2966
1c0b28c2
EM		 2967/*
2968 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2969 * stopped by the hypervisor. This function will be called from the host only.
2970 * EINVAL is returned when the host attempts to set the flag for a guest that
2971 * does not support pv clocks.
2972 */
2973static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2974{
1c0b28c2
EM		 2975 if (!vcpu->arch.time_page)
2976 return -EINVAL;
51d59c6b 2977 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2978 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2979 return 0;
2980}
2981
313a3dc7
CO		 2982long kvm_arch_vcpu_ioctl(struct file *filp,
2983 unsigned int ioctl, unsigned long arg)
2984{
2985 struct kvm_vcpu *vcpu = filp->private_data;
2986 void __user *argp = (void __user *)arg;
2987 int r;
d1ac91d8
AK		 2988 union {
2989 struct kvm_lapic_state *lapic;
2990 struct kvm_xsave *xsave;
2991 struct kvm_xcrs *xcrs;
2992 void *buffer;
2993 } u;
2994
2995 u.buffer = NULL;
313a3dc7
CO		 2996 switch (ioctl) {
2997 case KVM_GET_LAPIC: {
2204ae3c
MT		 2998 r = -EINVAL;
2999 if (!vcpu->arch.apic)
3000 goto out;
d1ac91d8 3001 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3002
b772ff36 3003 r = -ENOMEM;
d1ac91d8 3004 if (!u.lapic)
b772ff36 3005 goto out;
d1ac91d8 3006 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3007 if (r)
3008 goto out;
3009 r = -EFAULT;
d1ac91d8 3010 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3011 goto out;
3012 r = 0;
3013 break;
3014 }
3015 case KVM_SET_LAPIC: {
2204ae3c
MT		 3016 r = -EINVAL;
3017 if (!vcpu->arch.apic)
3018 goto out;
ff5c2c03 3019 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3020 if (IS_ERR(u.lapic))
3021 return PTR_ERR(u.lapic);
ff5c2c03 3022
d1ac91d8 3023 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3024 break;
3025 }
f77bc6a4
ZX		 3026 case KVM_INTERRUPT: {
3027 struct kvm_interrupt irq;
3028
3029 r = -EFAULT;
3030 if (copy_from_user(&irq, argp, sizeof irq))
3031 goto out;
3032 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3033 break;
3034 }
c4abb7c9
JK		 3035 case KVM_NMI: {
3036 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3037 break;
3038 }
313a3dc7
CO		 3039 case KVM_SET_CPUID: {
3040 struct kvm_cpuid __user *cpuid_arg = argp;
3041 struct kvm_cpuid cpuid;
3042
3043 r = -EFAULT;
3044 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3045 goto out;
3046 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3047 break;
3048 }
07716717
DK		 3049 case KVM_SET_CPUID2: {
3050 struct kvm_cpuid2 __user *cpuid_arg = argp;
3051 struct kvm_cpuid2 cpuid;
3052
3053 r = -EFAULT;
3054 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3055 goto out;
3056 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3057 cpuid_arg->entries);
07716717
DK		 3058 break;
3059 }
3060 case KVM_GET_CPUID2: {
3061 struct kvm_cpuid2 __user *cpuid_arg = argp;
3062 struct kvm_cpuid2 cpuid;
3063
3064 r = -EFAULT;
3065 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3066 goto out;
3067 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3068 cpuid_arg->entries);
07716717
DK		 3069 if (r)
3070 goto out;
3071 r = -EFAULT;
3072 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3073 goto out;
3074 r = 0;
3075 break;
3076 }
313a3dc7
CO		 3077 case KVM_GET_MSRS:
3078 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3079 break;
3080 case KVM_SET_MSRS:
3081 r = msr_io(vcpu, argp, do_set_msr, 0);
3082 break;
b209749f
AK		 3083 case KVM_TPR_ACCESS_REPORTING: {
3084 struct kvm_tpr_access_ctl tac;
3085
3086 r = -EFAULT;
3087 if (copy_from_user(&tac, argp, sizeof tac))
3088 goto out;
3089 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3090 if (r)
3091 goto out;
3092 r = -EFAULT;
3093 if (copy_to_user(argp, &tac, sizeof tac))
3094 goto out;
3095 r = 0;
3096 break;
3097 };
b93463aa
AK		 3098 case KVM_SET_VAPIC_ADDR: {
3099 struct kvm_vapic_addr va;
3100
3101 r = -EINVAL;
3102 if (!irqchip_in_kernel(vcpu->kvm))
3103 goto out;
3104 r = -EFAULT;
3105 if (copy_from_user(&va, argp, sizeof va))
3106 goto out;
3107 r = 0;
3108 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3109 break;
3110 }
890ca9ae
HY		 3111 case KVM_X86_SETUP_MCE: {
3112 u64 mcg_cap;
3113
3114 r = -EFAULT;
3115 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3116 goto out;
3117 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3118 break;
3119 }
3120 case KVM_X86_SET_MCE: {
3121 struct kvm_x86_mce mce;
3122
3123 r = -EFAULT;
3124 if (copy_from_user(&mce, argp, sizeof mce))
3125 goto out;
3126 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3127 break;
3128 }
3cfc3092
JK		 3129 case KVM_GET_VCPU_EVENTS: {
3130 struct kvm_vcpu_events events;
3131
3132 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3133
3134 r = -EFAULT;
3135 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3136 break;
3137 r = 0;
3138 break;
3139 }
3140 case KVM_SET_VCPU_EVENTS: {
3141 struct kvm_vcpu_events events;
3142
3143 r = -EFAULT;
3144 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3145 break;
3146
3147 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3148 break;
3149 }
a1efbe77
JK		 3150 case KVM_GET_DEBUGREGS: {
3151 struct kvm_debugregs dbgregs;
3152
3153 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3154
3155 r = -EFAULT;
3156 if (copy_to_user(argp, &dbgregs,
3157 sizeof(struct kvm_debugregs)))
3158 break;
3159 r = 0;
3160 break;
3161 }
3162 case KVM_SET_DEBUGREGS: {
3163 struct kvm_debugregs dbgregs;
3164
3165 r = -EFAULT;
3166 if (copy_from_user(&dbgregs, argp,
3167 sizeof(struct kvm_debugregs)))
3168 break;
3169
3170 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3171 break;
3172 }
2d5b5a66 3173 case KVM_GET_XSAVE: {
d1ac91d8 3174 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3175 r = -ENOMEM;
d1ac91d8 3176 if (!u.xsave)
2d5b5a66
SY		 3177 break;
3178
d1ac91d8 3179 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3180
3181 r = -EFAULT;
d1ac91d8 3182 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3183 break;
3184 r = 0;
3185 break;
3186 }
3187 case KVM_SET_XSAVE: {
ff5c2c03 3188 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3189 if (IS_ERR(u.xsave))
3190 return PTR_ERR(u.xsave);
2d5b5a66 3191
d1ac91d8 3192 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3193 break;
3194 }
3195 case KVM_GET_XCRS: {
d1ac91d8 3196 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3197 r = -ENOMEM;
d1ac91d8 3198 if (!u.xcrs)
2d5b5a66
SY		 3199 break;
3200
d1ac91d8 3201 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3202
3203 r = -EFAULT;
d1ac91d8 3204 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3205 sizeof(struct kvm_xcrs)))
3206 break;
3207 r = 0;
3208 break;
3209 }
3210 case KVM_SET_XCRS: {
ff5c2c03 3211 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3212 if (IS_ERR(u.xcrs))
3213 return PTR_ERR(u.xcrs);
2d5b5a66 3214
d1ac91d8 3215 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3216 break;
3217 }
92a1f12d
JR		 3218 case KVM_SET_TSC_KHZ: {
3219 u32 user_tsc_khz;
3220
3221 r = -EINVAL;
92a1f12d
JR		 3222 user_tsc_khz = (u32)arg;
3223
3224 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3225 goto out;
3226
cc578287
ZA		 3227 if (user_tsc_khz == 0)
3228 user_tsc_khz = tsc_khz;
3229
3230 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3231
3232 r = 0;
3233 goto out;
3234 }
3235 case KVM_GET_TSC_KHZ: {
cc578287 3236 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3237 goto out;
3238 }
1c0b28c2
EM		 3239 case KVM_KVMCLOCK_CTRL: {
3240 r = kvm_set_guest_paused(vcpu);
3241 goto out;
3242 }
313a3dc7
CO		 3243 default:
3244 r = -EINVAL;
3245 }
3246out:
d1ac91d8 3247 kfree(u.buffer);
313a3dc7
CO		 3248 return r;
3249}
3250
5b1c1493
CO		 3251int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3252{
3253 return VM_FAULT_SIGBUS;
3254}
3255
1fe779f8
CO		 3256static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3257{
3258 int ret;
3259
3260 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3261 return -EINVAL;
1fe779f8
CO		 3262 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3263 return ret;
3264}
3265
b927a3ce
SY		 3266static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3267 u64 ident_addr)
3268{
3269 kvm->arch.ept_identity_map_addr = ident_addr;
3270 return 0;
3271}
3272
1fe779f8
CO		 3273static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3274 u32 kvm_nr_mmu_pages)
3275{
3276 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3277 return -EINVAL;
3278
79fac95e 3279 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3280
3281 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3282 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3283
79fac95e 3284 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3285 return 0;
3286}
3287
3288static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3289{
39de71ec 3290 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3291}
3292
1fe779f8
CO		 3293static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3294{
3295 int r;
3296
3297 r = 0;
3298 switch (chip->chip_id) {
3299 case KVM_IRQCHIP_PIC_MASTER:
3300 memcpy(&chip->chip.pic,
3301 &pic_irqchip(kvm)->pics[0],
3302 sizeof(struct kvm_pic_state));
3303 break;
3304 case KVM_IRQCHIP_PIC_SLAVE:
3305 memcpy(&chip->chip.pic,
3306 &pic_irqchip(kvm)->pics[1],
3307 sizeof(struct kvm_pic_state));
3308 break;
3309 case KVM_IRQCHIP_IOAPIC:
eba0226b 3310 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3311 break;
3312 default:
3313 r = -EINVAL;
3314 break;
3315 }
3316 return r;
3317}
3318
3319static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3320{
3321 int r;
3322
3323 r = 0;
3324 switch (chip->chip_id) {
3325 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3326 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3327 memcpy(&pic_irqchip(kvm)->pics[0],
3328 &chip->chip.pic,
3329 sizeof(struct kvm_pic_state));
f4f51050 3330 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3331 break;
3332 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3333 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3334 memcpy(&pic_irqchip(kvm)->pics[1],
3335 &chip->chip.pic,
3336 sizeof(struct kvm_pic_state));
f4f51050 3337 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3338 break;
3339 case KVM_IRQCHIP_IOAPIC:
eba0226b 3340 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3341 break;
3342 default:
3343 r = -EINVAL;
3344 break;
3345 }
3346 kvm_pic_update_irq(pic_irqchip(kvm));
3347 return r;
3348}
3349
e0f63cb9
SY		 3350static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3351{
3352 int r = 0;
3353
894a9c55 3354 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3355 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3356 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3357 return r;
3358}
3359
3360static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3361{
3362 int r = 0;
3363
894a9c55 3364 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3365 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3366 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3367 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3368 return r;
3369}
3370
3371static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3372{
3373 int r = 0;
3374
3375 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3376 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3377 sizeof(ps->channels));
3378 ps->flags = kvm->arch.vpit->pit_state.flags;
3379 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3380 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3381 return r;
3382}
3383
3384static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3385{
3386 int r = 0, start = 0;
3387 u32 prev_legacy, cur_legacy;
3388 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3389 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3390 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3391 if (!prev_legacy && cur_legacy)
3392 start = 1;
3393 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3394 sizeof(kvm->arch.vpit->pit_state.channels));
3395 kvm->arch.vpit->pit_state.flags = ps->flags;
3396 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3397 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3398 return r;
3399}
3400
52d939a0
MT		 3401static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3402 struct kvm_reinject_control *control)
3403{
3404 if (!kvm->arch.vpit)
3405 return -ENXIO;
894a9c55 3406 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3407 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3408 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3409 return 0;
3410}
3411
95d4c16c 3412/**
60c34612
TY		 3413 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3414 * @kvm: kvm instance
3415 * @log: slot id and address to which we copy the log
95d4c16c 3416 *
60c34612
TY		 3417 * We need to keep it in mind that VCPU threads can write to the bitmap
3418 * concurrently. So, to avoid losing data, we keep the following order for
3419 * each bit:
95d4c16c 3420 *
60c34612
TY		 3421 * 1. Take a snapshot of the bit and clear it if needed.
3422 * 2. Write protect the corresponding page.
3423 * 3. Flush TLB's if needed.
3424 * 4. Copy the snapshot to the userspace.
95d4c16c 3425 *
60c34612
TY		 3426 * Between 2 and 3, the guest may write to the page using the remaining TLB
3427 * entry. This is not a problem because the page will be reported dirty at
3428 * step 4 using the snapshot taken before and step 3 ensures that successive
3429 * writes will be logged for the next call.
5bb064dc 3430 */
60c34612 3431int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3432{
7850ac54 3433 int r;
5bb064dc 3434 struct kvm_memory_slot *memslot;
60c34612
TY		 3435 unsigned long n, i;
3436 unsigned long *dirty_bitmap;
3437 unsigned long *dirty_bitmap_buffer;
3438 bool is_dirty = false;
5bb064dc 3439
79fac95e 3440 mutex_lock(&kvm->slots_lock);
5bb064dc 3441
b050b015 3442 r = -EINVAL;
bbacc0c1 3443 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3444 goto out;
3445
28a37544 3446 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3447
3448 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3449 r = -ENOENT;
60c34612 3450 if (!dirty_bitmap)
b050b015
MT		 3451 goto out;
3452
87bf6e7d 3453 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3454
60c34612
TY		 3455 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3456 memset(dirty_bitmap_buffer, 0, n);
b050b015 3457
60c34612 3458 spin_lock(&kvm->mmu_lock);
b050b015 3459
60c34612
TY		 3460 for (i = 0; i < n / sizeof(long); i++) {
3461 unsigned long mask;
3462 gfn_t offset;
cdfca7b3 3463
60c34612
TY		 3464 if (!dirty_bitmap[i])
3465 continue;
b050b015 3466
60c34612 3467 is_dirty = true;
914ebccd 3468
60c34612
TY		 3469 mask = xchg(&dirty_bitmap[i], 0);
3470 dirty_bitmap_buffer[i] = mask;
edde99ce 3471
60c34612
TY		 3472 offset = i * BITS_PER_LONG;
3473 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3474 }
60c34612
TY		 3475 if (is_dirty)
3476 kvm_flush_remote_tlbs(kvm);
3477
3478 spin_unlock(&kvm->mmu_lock);
3479
3480 r = -EFAULT;
3481 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3482 goto out;
b050b015 3483
5bb064dc
ZX		 3484 r = 0;
3485out:
79fac95e 3486 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3487 return r;
3488}
3489
23d43cf9
CD		 3490int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3491{
3492 if (!irqchip_in_kernel(kvm))
3493 return -ENXIO;
3494
3495 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3496 irq_event->irq, irq_event->level);
3497 return 0;
3498}
3499
1fe779f8
CO		 3500long kvm_arch_vm_ioctl(struct file *filp,
3501 unsigned int ioctl, unsigned long arg)
3502{
3503 struct kvm *kvm = filp->private_data;
3504 void __user *argp = (void __user *)arg;
367e1319 3505 int r = -ENOTTY;
f0d66275
DH		 3506 /*
3507 * This union makes it completely explicit to gcc-3.x
3508 * that these two variables' stack usage should be
3509 * combined, not added together.
3510 */
3511 union {
3512 struct kvm_pit_state ps;
e9f42757 3513 struct kvm_pit_state2 ps2;
c5ff41ce 3514 struct kvm_pit_config pit_config;
f0d66275 3515 } u;
1fe779f8
CO		 3516
3517 switch (ioctl) {
3518 case KVM_SET_TSS_ADDR:
3519 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3520 break;
b927a3ce
SY		 3521 case KVM_SET_IDENTITY_MAP_ADDR: {
3522 u64 ident_addr;
3523
3524 r = -EFAULT;
3525 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3526 goto out;
3527 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3528 break;
3529 }
1fe779f8
CO		 3530 case KVM_SET_NR_MMU_PAGES:
3531 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3532 break;
3533 case KVM_GET_NR_MMU_PAGES:
3534 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3535 break;
3ddea128
MT		 3536 case KVM_CREATE_IRQCHIP: {
3537 struct kvm_pic *vpic;
3538
3539 mutex_lock(&kvm->lock);
3540 r = -EEXIST;
3541 if (kvm->arch.vpic)
3542 goto create_irqchip_unlock;
3e515705
AK		 3543 r = -EINVAL;
3544 if (atomic_read(&kvm->online_vcpus))
3545 goto create_irqchip_unlock;
1fe779f8 3546 r = -ENOMEM;
3ddea128
MT		 3547 vpic = kvm_create_pic(kvm);
3548 if (vpic) {
1fe779f8
CO		 3549 r = kvm_ioapic_init(kvm);
3550 if (r) {
175504cd 3551 mutex_lock(&kvm->slots_lock);
72bb2fcd 3552 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3553 &vpic->dev_master);
3554 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3555 &vpic->dev_slave);
3556 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3557 &vpic->dev_eclr);
175504cd 3558 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3559 kfree(vpic);
3560 goto create_irqchip_unlock;
1fe779f8
CO		 3561 }
3562 } else
3ddea128
MT		 3563 goto create_irqchip_unlock;
3564 smp_wmb();
3565 kvm->arch.vpic = vpic;
3566 smp_wmb();
399ec807
AK		 3567 r = kvm_setup_default_irq_routing(kvm);
3568 if (r) {
175504cd 3569 mutex_lock(&kvm->slots_lock);
3ddea128 3570 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3571 kvm_ioapic_destroy(kvm);
3572 kvm_destroy_pic(kvm);
3ddea128 3573 mutex_unlock(&kvm->irq_lock);
175504cd 3574 mutex_unlock(&kvm->slots_lock);
399ec807 3575 }
3ddea128
MT		 3576 create_irqchip_unlock:
3577 mutex_unlock(&kvm->lock);
1fe779f8 3578 break;
3ddea128 3579 }
7837699f 3580 case KVM_CREATE_PIT:
c5ff41ce
JK		 3581 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3582 goto create_pit;
3583 case KVM_CREATE_PIT2:
3584 r = -EFAULT;
3585 if (copy_from_user(&u.pit_config, argp,
3586 sizeof(struct kvm_pit_config)))
3587 goto out;
3588 create_pit:
79fac95e 3589 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3590 r = -EEXIST;
3591 if (kvm->arch.vpit)
3592 goto create_pit_unlock;
7837699f 3593 r = -ENOMEM;
c5ff41ce 3594 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3595 if (kvm->arch.vpit)
3596 r = 0;
269e05e4 3597 create_pit_unlock:
79fac95e 3598 mutex_unlock(&kvm->slots_lock);
7837699f 3599 break;
1fe779f8
CO		 3600 case KVM_GET_IRQCHIP: {
3601 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3602 struct kvm_irqchip *chip;
1fe779f8 3603
ff5c2c03
SL		 3604 chip = memdup_user(argp, sizeof(*chip));
3605 if (IS_ERR(chip)) {
3606 r = PTR_ERR(chip);
1fe779f8 3607 goto out;
ff5c2c03
SL		 3608 }
3609
1fe779f8
CO		 3610 r = -ENXIO;
3611 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3612 goto get_irqchip_out;
3613 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3614 if (r)
f0d66275 3615 goto get_irqchip_out;
1fe779f8 3616 r = -EFAULT;
f0d66275
DH		 3617 if (copy_to_user(argp, chip, sizeof *chip))
3618 goto get_irqchip_out;
1fe779f8 3619 r = 0;
f0d66275
DH		 3620 get_irqchip_out:
3621 kfree(chip);
1fe779f8
CO		 3622 break;
3623 }
3624 case KVM_SET_IRQCHIP: {
3625 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3626 struct kvm_irqchip *chip;
1fe779f8 3627
ff5c2c03
SL		 3628 chip = memdup_user(argp, sizeof(*chip));
3629 if (IS_ERR(chip)) {
3630 r = PTR_ERR(chip);
1fe779f8 3631 goto out;
ff5c2c03
SL		 3632 }
3633
1fe779f8
CO		 3634 r = -ENXIO;
3635 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3636 goto set_irqchip_out;
3637 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3638 if (r)
f0d66275 3639 goto set_irqchip_out;
1fe779f8 3640 r = 0;
f0d66275
DH		 3641 set_irqchip_out:
3642 kfree(chip);
1fe779f8
CO		 3643 break;
3644 }
e0f63cb9 3645 case KVM_GET_PIT: {
e0f63cb9 3646 r = -EFAULT;
f0d66275 3647 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3648 goto out;
3649 r = -ENXIO;
3650 if (!kvm->arch.vpit)
3651 goto out;
f0d66275 3652 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3653 if (r)
3654 goto out;
3655 r = -EFAULT;
f0d66275 3656 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3657 goto out;
3658 r = 0;
3659 break;
3660 }
3661 case KVM_SET_PIT: {
e0f63cb9 3662 r = -EFAULT;
f0d66275 3663 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3664 goto out;
3665 r = -ENXIO;
3666 if (!kvm->arch.vpit)
3667 goto out;
f0d66275 3668 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3669 break;
3670 }
e9f42757
BK		 3671 case KVM_GET_PIT2: {
3672 r = -ENXIO;
3673 if (!kvm->arch.vpit)
3674 goto out;
3675 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3676 if (r)
3677 goto out;
3678 r = -EFAULT;
3679 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3680 goto out;
3681 r = 0;
3682 break;
3683 }
3684 case KVM_SET_PIT2: {
3685 r = -EFAULT;
3686 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3687 goto out;
3688 r = -ENXIO;
3689 if (!kvm->arch.vpit)
3690 goto out;
3691 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3692 break;
3693 }
52d939a0
MT		 3694 case KVM_REINJECT_CONTROL: {
3695 struct kvm_reinject_control control;
3696 r = -EFAULT;
3697 if (copy_from_user(&control, argp, sizeof(control)))
3698 goto out;
3699 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3700 break;
3701 }
ffde22ac
ES		 3702 case KVM_XEN_HVM_CONFIG: {
3703 r = -EFAULT;
3704 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3705 sizeof(struct kvm_xen_hvm_config)))
3706 goto out;
3707 r = -EINVAL;
3708 if (kvm->arch.xen_hvm_config.flags)
3709 goto out;
3710 r = 0;
3711 break;
3712 }
afbcf7ab 3713 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3714 struct kvm_clock_data user_ns;
3715 u64 now_ns;
3716 s64 delta;
3717
3718 r = -EFAULT;
3719 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3720 goto out;
3721
3722 r = -EINVAL;
3723 if (user_ns.flags)
3724 goto out;
3725
3726 r = 0;
395c6b0a 3727 local_irq_disable();
759379dd 3728 now_ns = get_kernel_ns();
afbcf7ab 3729 delta = user_ns.clock - now_ns;
395c6b0a 3730 local_irq_enable();
afbcf7ab
GC		 3731 kvm->arch.kvmclock_offset = delta;
3732 break;
3733 }
3734 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3735 struct kvm_clock_data user_ns;
3736 u64 now_ns;
3737
395c6b0a 3738 local_irq_disable();
759379dd 3739 now_ns = get_kernel_ns();
afbcf7ab 3740 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3741 local_irq_enable();
afbcf7ab 3742 user_ns.flags = 0;
97e69aa6 3743 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3744
3745 r = -EFAULT;
3746 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3747 goto out;
3748 r = 0;
3749 break;
3750 }
3751
1fe779f8
CO		 3752 default:
3753 ;
3754 }
3755out:
3756 return r;
3757}
3758
a16b043c 3759static void kvm_init_msr_list(void)
043405e1
CO		 3760{
3761 u32 dummy[2];
3762 unsigned i, j;
3763
e3267cbb
GC		 3764 /* skip the first msrs in the list. KVM-specific */
3765 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3766 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3767 continue;
3768 if (j < i)
3769 msrs_to_save[j] = msrs_to_save[i];
3770 j++;
3771 }
3772 num_msrs_to_save = j;
3773}
3774
bda9020e
MT		 3775static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3776 const void *v)
bbd9b64e 3777{
70252a10
AK		 3778 int handled = 0;
3779 int n;
3780
3781 do {
3782 n = min(len, 8);
3783 if (!(vcpu->arch.apic &&
3784 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3785 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3786 break;
3787 handled += n;
3788 addr += n;
3789 len -= n;
3790 v += n;
3791 } while (len);
bbd9b64e 3792
70252a10 3793 return handled;
bbd9b64e
CO		 3794}
3795
bda9020e 3796static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3797{
70252a10
AK		 3798 int handled = 0;
3799 int n;
3800
3801 do {
3802 n = min(len, 8);
3803 if (!(vcpu->arch.apic &&
3804 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3805 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3806 break;
3807 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3808 handled += n;
3809 addr += n;
3810 len -= n;
3811 v += n;
3812 } while (len);
bbd9b64e 3813
70252a10 3814 return handled;
bbd9b64e
CO		 3815}
3816
2dafc6c2
GN		 3817static void kvm_set_segment(struct kvm_vcpu *vcpu,
3818 struct kvm_segment *var, int seg)
3819{
3820 kvm_x86_ops->set_segment(vcpu, var, seg);
3821}
3822
3823void kvm_get_segment(struct kvm_vcpu *vcpu,
3824 struct kvm_segment *var, int seg)
3825{
3826 kvm_x86_ops->get_segment(vcpu, var, seg);
3827}
3828
e459e322 3829gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3830{
3831 gpa_t t_gpa;
ab9ae313 3832 struct x86_exception exception;
02f59dc9
JR		 3833
3834 BUG_ON(!mmu_is_nested(vcpu));
3835
3836 /* NPT walks are always user-walks */
3837 access |= PFERR_USER_MASK;
ab9ae313 3838 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3839
3840 return t_gpa;
3841}
3842
ab9ae313
AK		 3843gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3844 struct x86_exception *exception)
1871c602
GN		 3845{
3846 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3847 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3848}
3849
ab9ae313
AK		 3850 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3851 struct x86_exception *exception)
1871c602
GN		 3852{
3853 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3854 access |= PFERR_FETCH_MASK;
ab9ae313 3855 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3856}
3857
ab9ae313
AK		 3858gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3859 struct x86_exception *exception)
1871c602
GN		 3860{
3861 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3862 access |= PFERR_WRITE_MASK;
ab9ae313 3863 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3864}
3865
3866/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3867gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3868 struct x86_exception *exception)
1871c602 3869{
ab9ae313 3870 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3871}
3872
3873static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3874 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3875 struct x86_exception *exception)
bbd9b64e
CO		 3876{
3877 void *data = val;
10589a46 3878 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3879
3880 while (bytes) {
14dfe855 3881 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3882 exception);
bbd9b64e 3883 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3884 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3885 int ret;
3886
bcc55cba 3887 if (gpa == UNMAPPED_GVA)
ab9ae313 3888 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3889 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3890 if (ret < 0) {
c3cd7ffa 3891 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3892 goto out;
3893 }
bbd9b64e 3894
77c2002e
IE		 3895 bytes -= toread;
3896 data += toread;
3897 addr += toread;
bbd9b64e 3898 }
10589a46 3899out:
10589a46 3900 return r;
bbd9b64e 3901}
77c2002e 3902
1871c602 3903/* used for instruction fetching */
0f65dd70
AK		 3904static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3905 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3906 struct x86_exception *exception)
1871c602 3907{
0f65dd70 3908 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3909 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3910
1871c602 3911 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3912 access | PFERR_FETCH_MASK,
3913 exception);
1871c602
GN		 3914}
3915
064aea77 3916int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3917 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3918 struct x86_exception *exception)
1871c602 3919{
0f65dd70 3920 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3921 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3922
1871c602 3923 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3924 exception);
1871c602 3925}
064aea77 3926EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3927
0f65dd70
AK		 3928static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3929 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3930 struct x86_exception *exception)
1871c602 3931{
0f65dd70 3932 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3933 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3934}
3935
6a4d7550 3936int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3937 gva_t addr, void *val,
2dafc6c2 3938 unsigned int bytes,
bcc55cba 3939 struct x86_exception *exception)
77c2002e 3940{
0f65dd70 3941 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3942 void *data = val;
3943 int r = X86EMUL_CONTINUE;
3944
3945 while (bytes) {
14dfe855
JR		 3946 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3947 PFERR_WRITE_MASK,
ab9ae313 3948 exception);
77c2002e
IE		 3949 unsigned offset = addr & (PAGE_SIZE-1);
3950 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3951 int ret;
3952
bcc55cba 3953 if (gpa == UNMAPPED_GVA)
ab9ae313 3954 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3955 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3956 if (ret < 0) {
c3cd7ffa 3957 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3958 goto out;
3959 }
3960
3961 bytes -= towrite;
3962 data += towrite;
3963 addr += towrite;
3964 }
3965out:
3966 return r;
3967}
6a4d7550 3968EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3969
af7cc7d1
XG		 3970static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3971 gpa_t *gpa, struct x86_exception *exception,
3972 bool write)
3973{
97d64b78
AK		 3974 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3975 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3976
97d64b78
AK		 3977 if (vcpu_match_mmio_gva(vcpu, gva)
3978 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3979 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3980 (gva & (PAGE_SIZE - 1));
4f022648 3981 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3982 return 1;
3983 }
3984
af7cc7d1
XG		 3985 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3986
3987 if (*gpa == UNMAPPED_GVA)
3988 return -1;
3989
3990 /* For APIC access vmexit */
3991 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3992 return 1;
3993
4f022648
XG		 3994 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3995 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3996 return 1;
4f022648 3997 }
bebb106a 3998
af7cc7d1
XG		 3999 return 0;
4000}
4001
3200f405 4002int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4003 const void *val, int bytes)
bbd9b64e
CO		 4004{
4005 int ret;
4006
4007 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4008 if (ret < 0)
bbd9b64e 4009 return 0;
f57f2ef5 4010 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4011 return 1;
4012}
4013
77d197b2
XG		 4014struct read_write_emulator_ops {
4015 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4016 int bytes);
4017 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4018 void *val, int bytes);
4019 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4020 int bytes, void *val);
4021 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4022 void *val, int bytes);
4023 bool write;
4024};
4025
4026static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4027{
4028 if (vcpu->mmio_read_completed) {
77d197b2 4029 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4030 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4031 vcpu->mmio_read_completed = 0;
4032 return 1;
4033 }
4034
4035 return 0;
4036}
4037
4038static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4039 void *val, int bytes)
4040{
4041 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4042}
4043
4044static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4045 void *val, int bytes)
4046{
4047 return emulator_write_phys(vcpu, gpa, val, bytes);
4048}
4049
4050static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4051{
4052 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4053 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4054}
4055
4056static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4057 void *val, int bytes)
4058{
4059 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4060 return X86EMUL_IO_NEEDED;
4061}
4062
4063static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4064 void *val, int bytes)
4065{
f78146b0
AK		 4066 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4067
87da7e66 4068 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4069 return X86EMUL_CONTINUE;
4070}
4071
0fbe9b0b 4072static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4073 .read_write_prepare = read_prepare,
4074 .read_write_emulate = read_emulate,
4075 .read_write_mmio = vcpu_mmio_read,
4076 .read_write_exit_mmio = read_exit_mmio,
4077};
4078
0fbe9b0b 4079static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4080 .read_write_emulate = write_emulate,
4081 .read_write_mmio = write_mmio,
4082 .read_write_exit_mmio = write_exit_mmio,
4083 .write = true,
4084};
4085
22388a3c
XG		 4086static int emulator_read_write_onepage(unsigned long addr, void *val,
4087 unsigned int bytes,
4088 struct x86_exception *exception,
4089 struct kvm_vcpu *vcpu,
0fbe9b0b 4090 const struct read_write_emulator_ops *ops)
bbd9b64e 4091{
af7cc7d1
XG		 4092 gpa_t gpa;
4093 int handled, ret;
22388a3c 4094 bool write = ops->write;
f78146b0 4095 struct kvm_mmio_fragment *frag;
10589a46 4096
22388a3c 4097 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4098
af7cc7d1 4099 if (ret < 0)
bbd9b64e 4100 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4101
4102 /* For APIC access vmexit */
af7cc7d1 4103 if (ret)
bbd9b64e
CO		 4104 goto mmio;
4105
22388a3c 4106 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4107 return X86EMUL_CONTINUE;
4108
4109mmio:
4110 /*
4111 * Is this MMIO handled locally?
4112 */
22388a3c 4113 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4114 if (handled == bytes)
bbd9b64e 4115 return X86EMUL_CONTINUE;
bbd9b64e 4116
70252a10
AK		 4117 gpa += handled;
4118 bytes -= handled;
4119 val += handled;
4120
87da7e66
XG		 4121 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4122 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4123 frag->gpa = gpa;
4124 frag->data = val;
4125 frag->len = bytes;
f78146b0 4126 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4127}
4128
22388a3c
XG		 4129int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4130 void *val, unsigned int bytes,
4131 struct x86_exception *exception,
0fbe9b0b 4132 const struct read_write_emulator_ops *ops)
bbd9b64e 4133{
0f65dd70 4134 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4135 gpa_t gpa;
4136 int rc;
4137
4138 if (ops->read_write_prepare &&
4139 ops->read_write_prepare(vcpu, val, bytes))
4140 return X86EMUL_CONTINUE;
4141
4142 vcpu->mmio_nr_fragments = 0;
0f65dd70 4143
bbd9b64e
CO		 4144 /* Crossing a page boundary? */
4145 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4146 int now;
bbd9b64e
CO		 4147
4148 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4149 rc = emulator_read_write_onepage(addr, val, now, exception,
4150 vcpu, ops);
4151
bbd9b64e
CO		 4152 if (rc != X86EMUL_CONTINUE)
4153 return rc;
4154 addr += now;
4155 val += now;
4156 bytes -= now;
4157 }
22388a3c 4158
f78146b0
AK		 4159 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4160 vcpu, ops);
4161 if (rc != X86EMUL_CONTINUE)
4162 return rc;
4163
4164 if (!vcpu->mmio_nr_fragments)
4165 return rc;
4166
4167 gpa = vcpu->mmio_fragments[0].gpa;
4168
4169 vcpu->mmio_needed = 1;
4170 vcpu->mmio_cur_fragment = 0;
4171
87da7e66 4172 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4173 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4174 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4175 vcpu->run->mmio.phys_addr = gpa;
4176
4177 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4178}
4179
4180static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4181 unsigned long addr,
4182 void *val,
4183 unsigned int bytes,
4184 struct x86_exception *exception)
4185{
4186 return emulator_read_write(ctxt, addr, val, bytes,
4187 exception, &read_emultor);
4188}
4189
4190int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4191 unsigned long addr,
4192 const void *val,
4193 unsigned int bytes,
4194 struct x86_exception *exception)
4195{
4196 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4197 exception, &write_emultor);
bbd9b64e 4198}
bbd9b64e 4199
daea3e73
AK		 4200#define CMPXCHG_TYPE(t, ptr, old, new) \
4201 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4202
4203#ifdef CONFIG_X86_64
4204# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4205#else
4206# define CMPXCHG64(ptr, old, new) \
9749a6c0 4207 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4208#endif
4209
0f65dd70
AK		 4210static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4211 unsigned long addr,
bbd9b64e
CO		 4212 const void *old,
4213 const void *new,
4214 unsigned int bytes,
0f65dd70 4215 struct x86_exception *exception)
bbd9b64e 4216{
0f65dd70 4217 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4218 gpa_t gpa;
4219 struct page *page;
4220 char *kaddr;
4221 bool exchanged;
2bacc55c 4222
daea3e73
AK		 4223 /* guests cmpxchg8b have to be emulated atomically */
4224 if (bytes > 8 || (bytes & (bytes - 1)))
4225 goto emul_write;
10589a46 4226
daea3e73 4227 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4228
daea3e73
AK		 4229 if (gpa == UNMAPPED_GVA ||
4230 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4231 goto emul_write;
2bacc55c 4232
daea3e73
AK		 4233 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4234 goto emul_write;
72dc67a6 4235
daea3e73 4236 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4237 if (is_error_page(page))
c19b8bd6 4238 goto emul_write;
72dc67a6 4239
8fd75e12 4240 kaddr = kmap_atomic(page);
daea3e73
AK		 4241 kaddr += offset_in_page(gpa);
4242 switch (bytes) {
4243 case 1:
4244 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4245 break;
4246 case 2:
4247 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4248 break;
4249 case 4:
4250 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4251 break;
4252 case 8:
4253 exchanged = CMPXCHG64(kaddr, old, new);
4254 break;
4255 default:
4256 BUG();
2bacc55c 4257 }
8fd75e12 4258 kunmap_atomic(kaddr);
daea3e73
AK		 4259 kvm_release_page_dirty(page);
4260
4261 if (!exchanged)
4262 return X86EMUL_CMPXCHG_FAILED;
4263
f57f2ef5 4264 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4265
4266 return X86EMUL_CONTINUE;
4a5f48f6 4267
3200f405 4268emul_write:
daea3e73 4269 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4270
0f65dd70 4271 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4272}
4273
cf8f70bf
GN		 4274static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4275{
4276 /* TODO: String I/O for in kernel device */
4277 int r;
4278
4279 if (vcpu->arch.pio.in)
4280 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4281 vcpu->arch.pio.size, pd);
4282 else
4283 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4284 vcpu->arch.pio.port, vcpu->arch.pio.size,
4285 pd);
4286 return r;
4287}
4288
6f6fbe98
XG		 4289static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4290 unsigned short port, void *val,
4291 unsigned int count, bool in)
cf8f70bf 4292{
6f6fbe98 4293 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4294
4295 vcpu->arch.pio.port = port;
6f6fbe98 4296 vcpu->arch.pio.in = in;
7972995b 4297 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4298 vcpu->arch.pio.size = size;
4299
4300 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4301 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4302 return 1;
4303 }
4304
4305 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4306 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4307 vcpu->run->io.size = size;
4308 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4309 vcpu->run->io.count = count;
4310 vcpu->run->io.port = port;
4311
4312 return 0;
4313}
4314
6f6fbe98
XG		 4315static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4316 int size, unsigned short port, void *val,
4317 unsigned int count)
cf8f70bf 4318{
ca1d4a9e 4319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4320 int ret;
ca1d4a9e 4321
6f6fbe98
XG		 4322 if (vcpu->arch.pio.count)
4323 goto data_avail;
cf8f70bf 4324
6f6fbe98
XG		 4325 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4326 if (ret) {
4327data_avail:
4328 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4329 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4330 return 1;
4331 }
4332
cf8f70bf
GN		 4333 return 0;
4334}
4335
6f6fbe98
XG		 4336static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4337 int size, unsigned short port,
4338 const void *val, unsigned int count)
4339{
4340 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4341
4342 memcpy(vcpu->arch.pio_data, val, size * count);
4343 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4344}
4345
bbd9b64e
CO		 4346static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4347{
4348 return kvm_x86_ops->get_segment_base(vcpu, seg);
4349}
4350
3cb16fe7 4351static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4352{
3cb16fe7 4353 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4354}
4355
f5f48ee1
SY		 4356int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4357{
4358 if (!need_emulate_wbinvd(vcpu))
4359 return X86EMUL_CONTINUE;
4360
4361 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4362 int cpu = get_cpu();
4363
4364 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4365 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4366 wbinvd_ipi, NULL, 1);
2eec7343 4367 put_cpu();
f5f48ee1 4368 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4369 } else
4370 wbinvd();
f5f48ee1
SY		 4371 return X86EMUL_CONTINUE;
4372}
4373EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4374
bcaf5cc5
AK		 4375static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4376{
4377 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4378}
4379
717746e3 4380int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4381{
717746e3 4382 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4383}
4384
717746e3 4385int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4386{
338dbc97 4387
717746e3 4388 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4389}
4390
52a46617 4391static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4392{
52a46617 4393 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4394}
4395
717746e3 4396static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4397{
717746e3 4398 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4399 unsigned long value;
4400
4401 switch (cr) {
4402 case 0:
4403 value = kvm_read_cr0(vcpu);
4404 break;
4405 case 2:
4406 value = vcpu->arch.cr2;
4407 break;
4408 case 3:
9f8fe504 4409 value = kvm_read_cr3(vcpu);
52a46617
GN		 4410 break;
4411 case 4:
4412 value = kvm_read_cr4(vcpu);
4413 break;
4414 case 8:
4415 value = kvm_get_cr8(vcpu);
4416 break;
4417 default:
a737f256 4418 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4419 return 0;
4420 }
4421
4422 return value;
4423}
4424
717746e3 4425static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4426{
717746e3 4427 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4428 int res = 0;
4429
52a46617
GN		 4430 switch (cr) {
4431 case 0:
49a9b07e 4432 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4433 break;
4434 case 2:
4435 vcpu->arch.cr2 = val;
4436 break;
4437 case 3:
2390218b 4438 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4439 break;
4440 case 4:
a83b29c6 4441 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4442 break;
4443 case 8:
eea1cff9 4444 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4445 break;
4446 default:
a737f256 4447 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4448 res = -1;
52a46617 4449 }
0f12244f
GN		 4450
4451 return res;
52a46617
GN		 4452}
4453
4cee4798
KW		 4454static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4455{
4456 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4457}
4458
717746e3 4459static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4460{
717746e3 4461 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4462}
4463
4bff1e86 4464static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4465{
4bff1e86 4466 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4467}
4468
4bff1e86 4469static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4470{
4bff1e86 4471 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4472}
4473
1ac9d0cf
AK		 4474static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4475{
4476 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4477}
4478
4479static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4480{
4481 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4482}
4483
4bff1e86
AK		 4484static unsigned long emulator_get_cached_segment_base(
4485 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4486{
4bff1e86 4487 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4488}
4489
1aa36616
AK		 4490static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4491 struct desc_struct *desc, u32 *base3,
4492 int seg)
2dafc6c2
GN		 4493{
4494 struct kvm_segment var;
4495
4bff1e86 4496 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4497 *selector = var.selector;
2dafc6c2 4498
378a8b09
GN		 4499 if (var.unusable) {
4500 memset(desc, 0, sizeof(*desc));
2dafc6c2 4501 return false;
378a8b09 4502 }
2dafc6c2
GN		 4503
4504 if (var.g)
4505 var.limit >>= 12;
4506 set_desc_limit(desc, var.limit);
4507 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4508#ifdef CONFIG_X86_64
4509 if (base3)
4510 *base3 = var.base >> 32;
4511#endif
2dafc6c2
GN		 4512 desc->type = var.type;
4513 desc->s = var.s;
4514 desc->dpl = var.dpl;
4515 desc->p = var.present;
4516 desc->avl = var.avl;
4517 desc->l = var.l;
4518 desc->d = var.db;
4519 desc->g = var.g;
4520
4521 return true;
4522}
4523
1aa36616
AK		 4524static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4525 struct desc_struct *desc, u32 base3,
4526 int seg)
2dafc6c2 4527{
4bff1e86 4528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4529 struct kvm_segment var;
4530
1aa36616 4531 var.selector = selector;
2dafc6c2 4532 var.base = get_desc_base(desc);
5601d05b
GN		 4533#ifdef CONFIG_X86_64
4534 var.base |= ((u64)base3) << 32;
4535#endif
2dafc6c2
GN		 4536 var.limit = get_desc_limit(desc);
4537 if (desc->g)
4538 var.limit = (var.limit << 12) | 0xfff;
4539 var.type = desc->type;
4540 var.present = desc->p;
4541 var.dpl = desc->dpl;
4542 var.db = desc->d;
4543 var.s = desc->s;
4544 var.l = desc->l;
4545 var.g = desc->g;
4546 var.avl = desc->avl;
4547 var.present = desc->p;
4548 var.unusable = !var.present;
4549 var.padding = 0;
4550
4551 kvm_set_segment(vcpu, &var, seg);
4552 return;
4553}
4554
717746e3
AK		 4555static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4556 u32 msr_index, u64 *pdata)
4557{
4558 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4559}
4560
4561static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4562 u32 msr_index, u64 data)
4563{
8fe8ab46
WA		 4564 struct msr_data msr;
4565
4566 msr.data = data;
4567 msr.index = msr_index;
4568 msr.host_initiated = false;
4569 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4570}
4571
222d21aa
AK		 4572static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4573 u32 pmc, u64 *pdata)
4574{
4575 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4576}
4577
6c3287f7
AK		 4578static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4579{
4580 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4581}
4582
5037f6f3
AK		 4583static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4584{
4585 preempt_disable();
5197b808 4586 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4587 /*
4588 * CR0.TS may reference the host fpu state, not the guest fpu state,
4589 * so it may be clear at this point.
4590 */
4591 clts();
4592}
4593
4594static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4595{
4596 preempt_enable();
4597}
4598
2953538e 4599static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4600 struct x86_instruction_info *info,
c4f035c6
AK		 4601 enum x86_intercept_stage stage)
4602{
2953538e 4603 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4604}
4605
0017f93a 4606static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4607 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4608{
0017f93a 4609 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4610}
4611
dd856efa
AK		 4612static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4613{
4614 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4615}
4616
4617static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4618{
4619 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4620}
4621
0225fb50 4622static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4623 .read_gpr = emulator_read_gpr,
4624 .write_gpr = emulator_write_gpr,
1871c602 4625 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4626 .write_std = kvm_write_guest_virt_system,
1871c602 4627 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4628 .read_emulated = emulator_read_emulated,
4629 .write_emulated = emulator_write_emulated,
4630 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4631 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4632 .pio_in_emulated = emulator_pio_in_emulated,
4633 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4634 .get_segment = emulator_get_segment,
4635 .set_segment = emulator_set_segment,
5951c442 4636 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4637 .get_gdt = emulator_get_gdt,
160ce1f1 4638 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4639 .set_gdt = emulator_set_gdt,
4640 .set_idt = emulator_set_idt,
52a46617
GN		 4641 .get_cr = emulator_get_cr,
4642 .set_cr = emulator_set_cr,
4cee4798 4643 .set_rflags = emulator_set_rflags,
9c537244 4644 .cpl = emulator_get_cpl,
35aa5375
GN		 4645 .get_dr = emulator_get_dr,
4646 .set_dr = emulator_set_dr,
717746e3
AK		 4647 .set_msr = emulator_set_msr,
4648 .get_msr = emulator_get_msr,
222d21aa 4649 .read_pmc = emulator_read_pmc,
6c3287f7 4650 .halt = emulator_halt,
bcaf5cc5 4651 .wbinvd = emulator_wbinvd,
d6aa1000 4652 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4653 .get_fpu = emulator_get_fpu,
4654 .put_fpu = emulator_put_fpu,
c4f035c6 4655 .intercept = emulator_intercept,
bdb42f5a 4656 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4657};
4658
95cb2295
GN		 4659static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4660{
4661 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4662 /*
4663 * an sti; sti; sequence only disable interrupts for the first
4664 * instruction. So, if the last instruction, be it emulated or
4665 * not, left the system with the INT_STI flag enabled, it
4666 * means that the last instruction is an sti. We should not
4667 * leave the flag on in this case. The same goes for mov ss
4668 */
4669 if (!(int_shadow & mask))
4670 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4671}
4672
54b8486f
GN		 4673static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4674{
4675 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4676 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4677 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4678 else if (ctxt->exception.error_code_valid)
4679 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4680 ctxt->exception.error_code);
54b8486f 4681 else
da9cb575 4682 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4683}
4684
dd856efa 4685static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4686{
9dac77fa 4687 memset(&ctxt->twobyte, 0,
dd856efa 4688 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4689
9dac77fa
AK		 4690 ctxt->fetch.start = 0;
4691 ctxt->fetch.end = 0;
4692 ctxt->io_read.pos = 0;
4693 ctxt->io_read.end = 0;
4694 ctxt->mem_read.pos = 0;
4695 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4696}
4697
8ec4722d
MG		 4698static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4699{
adf52235 4700 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4701 int cs_db, cs_l;
4702
8ec4722d
MG		 4703 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4704
adf52235
TY		 4705 ctxt->eflags = kvm_get_rflags(vcpu);
4706 ctxt->eip = kvm_rip_read(vcpu);
4707 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4708 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4709 cs_l ? X86EMUL_MODE_PROT64 :
4710 cs_db ? X86EMUL_MODE_PROT32 :
4711 X86EMUL_MODE_PROT16;
4712 ctxt->guest_mode = is_guest_mode(vcpu);
4713
dd856efa 4714 init_decode_cache(ctxt);
7ae441ea 4715 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4716}
4717
71f9833b 4718int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4719{
9d74191a 4720 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4721 int ret;
4722
4723 init_emulate_ctxt(vcpu);
4724
9dac77fa
AK		 4725 ctxt->op_bytes = 2;
4726 ctxt->ad_bytes = 2;
4727 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4728 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4729
4730 if (ret != X86EMUL_CONTINUE)
4731 return EMULATE_FAIL;
4732
9dac77fa 4733 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4734 kvm_rip_write(vcpu, ctxt->eip);
4735 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4736
4737 if (irq == NMI_VECTOR)
7460fb4a 4738 vcpu->arch.nmi_pending = 0;
63995653
MG		 4739 else
4740 vcpu->arch.interrupt.pending = false;
4741
4742 return EMULATE_DONE;
4743}
4744EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4745
6d77dbfc
GN		 4746static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4747{
fc3a9157
JR		 4748 int r = EMULATE_DONE;
4749
6d77dbfc
GN		 4750 ++vcpu->stat.insn_emulation_fail;
4751 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4752 if (!is_guest_mode(vcpu)) {
4753 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4754 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4755 vcpu->run->internal.ndata = 0;
4756 r = EMULATE_FAIL;
4757 }
6d77dbfc 4758 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4759
4760 return r;
6d77dbfc
GN		 4761}
4762
93c05d3e
XG		 4763static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4764 bool write_fault_to_shadow_pgtable)
a6f177ef 4765{
95b3cf69 4766 gpa_t gpa = cr2;
8e3d9d06 4767 pfn_t pfn;
a6f177ef 4768
95b3cf69
XG		 4769 if (!vcpu->arch.mmu.direct_map) {
4770 /*
4771 * Write permission should be allowed since only
4772 * write access need to be emulated.
4773 */
4774 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4775
95b3cf69
XG		 4776 /*
4777 * If the mapping is invalid in guest, let cpu retry
4778 * it to generate fault.
4779 */
4780 if (gpa == UNMAPPED_GVA)
4781 return true;
4782 }
a6f177ef 4783
8e3d9d06
XG		 4784 /*
4785 * Do not retry the unhandleable instruction if it faults on the
4786 * readonly host memory, otherwise it will goto a infinite loop:
4787 * retry instruction -> write #PF -> emulation fail -> retry
4788 * instruction -> ...
4789 */
4790 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4791
4792 /*
4793 * If the instruction failed on the error pfn, it can not be fixed,
4794 * report the error to userspace.
4795 */
4796 if (is_error_noslot_pfn(pfn))
4797 return false;
4798
4799 kvm_release_pfn_clean(pfn);
4800
4801 /* The instructions are well-emulated on direct mmu. */
4802 if (vcpu->arch.mmu.direct_map) {
4803 unsigned int indirect_shadow_pages;
4804
4805 spin_lock(&vcpu->kvm->mmu_lock);
4806 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4807 spin_unlock(&vcpu->kvm->mmu_lock);
4808
4809 if (indirect_shadow_pages)
4810 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4811
a6f177ef 4812 return true;
8e3d9d06 4813 }
a6f177ef 4814
95b3cf69
XG		 4815 /*
4816 * if emulation was due to access to shadowed page table
4817 * and it failed try to unshadow page and re-enter the
4818 * guest to let CPU execute the instruction.
4819 */
4820 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4821
4822 /*
4823 * If the access faults on its page table, it can not
4824 * be fixed by unprotecting shadow page and it should
4825 * be reported to userspace.
4826 */
4827 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4828}
4829
1cb3f3ae
XG		 4830static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4831 unsigned long cr2, int emulation_type)
4832{
4833 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4834 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4835
4836 last_retry_eip = vcpu->arch.last_retry_eip;
4837 last_retry_addr = vcpu->arch.last_retry_addr;
4838
4839 /*
4840 * If the emulation is caused by #PF and it is non-page_table
4841 * writing instruction, it means the VM-EXIT is caused by shadow
4842 * page protected, we can zap the shadow page and retry this
4843 * instruction directly.
4844 *
4845 * Note: if the guest uses a non-page-table modifying instruction
4846 * on the PDE that points to the instruction, then we will unmap
4847 * the instruction and go to an infinite loop. So, we cache the
4848 * last retried eip and the last fault address, if we meet the eip
4849 * and the address again, we can break out of the potential infinite
4850 * loop.
4851 */
4852 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4853
4854 if (!(emulation_type & EMULTYPE_RETRY))
4855 return false;
4856
4857 if (x86_page_table_writing_insn(ctxt))
4858 return false;
4859
4860 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4861 return false;
4862
4863 vcpu->arch.last_retry_eip = ctxt->eip;
4864 vcpu->arch.last_retry_addr = cr2;
4865
4866 if (!vcpu->arch.mmu.direct_map)
4867 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4868
22368028 4869 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4870
4871 return true;
4872}
4873
716d51ab
GN		 4874static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4875static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4876
51d8b661
AP		 4877int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4878 unsigned long cr2,
dc25e89e
AP		 4879 int emulation_type,
4880 void *insn,
4881 int insn_len)
bbd9b64e 4882{
95cb2295 4883 int r;
9d74191a 4884 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4885 bool writeback = true;
93c05d3e 4886 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4887
93c05d3e
XG		 4888 /*
4889 * Clear write_fault_to_shadow_pgtable here to ensure it is
4890 * never reused.
4891 */
4892 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4893 kvm_clear_exception_queue(vcpu);
8d7d8102 4894
571008da 4895 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4896 init_emulate_ctxt(vcpu);
9d74191a
TY		 4897 ctxt->interruptibility = 0;
4898 ctxt->have_exception = false;
4899 ctxt->perm_ok = false;
bbd9b64e 4900
9d74191a 4901 ctxt->only_vendor_specific_insn
4005996e
AK		 4902 = emulation_type & EMULTYPE_TRAP_UD;
4903
9d74191a 4904 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4905
e46479f8 4906 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4907 ++vcpu->stat.insn_emulation;
1d2887e2 4908 if (r != EMULATION_OK) {
4005996e
AK		 4909 if (emulation_type & EMULTYPE_TRAP_UD)
4910 return EMULATE_FAIL;
93c05d3e
XG		 4911 if (reexecute_instruction(vcpu, cr2,
4912 write_fault_to_spt))
bbd9b64e 4913 return EMULATE_DONE;
6d77dbfc
GN		 4914 if (emulation_type & EMULTYPE_SKIP)
4915 return EMULATE_FAIL;
4916 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4917 }
4918 }
4919
ba8afb6b 4920 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4921 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4922 return EMULATE_DONE;
4923 }
4924
1cb3f3ae
XG		 4925 if (retry_instruction(ctxt, cr2, emulation_type))
4926 return EMULATE_DONE;
4927
7ae441ea 4928 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4929 changes registers values during IO operation */
7ae441ea
GN		 4930 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4931 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4932 emulator_invalidate_register_cache(ctxt);
7ae441ea 4933 }
4d2179e1 4934
5cd21917 4935restart:
9d74191a 4936 r = x86_emulate_insn(ctxt);
bbd9b64e 4937
775fde86
JR		 4938 if (r == EMULATION_INTERCEPTED)
4939 return EMULATE_DONE;
4940
d2ddd1c4 4941 if (r == EMULATION_FAILED) {
93c05d3e 4942 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt))
c3cd7ffa
GN		 4943 return EMULATE_DONE;
4944
6d77dbfc 4945 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4946 }
4947
9d74191a 4948 if (ctxt->have_exception) {
54b8486f 4949 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4950 r = EMULATE_DONE;
4951 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4952 if (!vcpu->arch.pio.in)
4953 vcpu->arch.pio.count = 0;
716d51ab 4954 else {
7ae441ea 4955 writeback = false;
716d51ab
GN		 4956 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4957 }
e85d28f8 4958 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4959 } else if (vcpu->mmio_needed) {
4960 if (!vcpu->mmio_is_write)
4961 writeback = false;
e85d28f8 4962 r = EMULATE_DO_MMIO;
716d51ab 4963 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4964 } else if (r == EMULATION_RESTART)
5cd21917 4965 goto restart;
d2ddd1c4
GN		 4966 else
4967 r = EMULATE_DONE;
f850e2e6 4968
7ae441ea 4969 if (writeback) {
9d74191a
TY		 4970 toggle_interruptibility(vcpu, ctxt->interruptibility);
4971 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4972 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4973 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4974 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4975 } else
4976 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4977
4978 return r;
de7d789a 4979}
51d8b661 4980EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4981
cf8f70bf 4982int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4983{
cf8f70bf 4984 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4985 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4986 size, port, &val, 1);
cf8f70bf 4987 /* do not return to emulator after return from userspace */
7972995b 4988 vcpu->arch.pio.count = 0;
de7d789a
CO		 4989 return ret;
4990}
cf8f70bf 4991EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4992
8cfdc000
ZA		 4993static void tsc_bad(void *info)
4994{
0a3aee0d 4995 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4996}
4997
4998static void tsc_khz_changed(void *data)
c8076604 4999{
8cfdc000
ZA		 5000 struct cpufreq_freqs *freq = data;
5001 unsigned long khz = 0;
5002
5003 if (data)
5004 khz = freq->new;
5005 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5006 khz = cpufreq_quick_get(raw_smp_processor_id());
5007 if (!khz)
5008 khz = tsc_khz;
0a3aee0d 5009 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5010}
5011
c8076604
GH		 5012static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5013 void *data)
5014{
5015 struct cpufreq_freqs *freq = data;
5016 struct kvm *kvm;
5017 struct kvm_vcpu *vcpu;
5018 int i, send_ipi = 0;
5019
8cfdc000
ZA		 5020 /*
5021 * We allow guests to temporarily run on slowing clocks,
5022 * provided we notify them after, or to run on accelerating
5023 * clocks, provided we notify them before. Thus time never
5024 * goes backwards.
5025 *
5026 * However, we have a problem. We can't atomically update
5027 * the frequency of a given CPU from this function; it is
5028 * merely a notifier, which can be called from any CPU.
5029 * Changing the TSC frequency at arbitrary points in time
5030 * requires a recomputation of local variables related to
5031 * the TSC for each VCPU. We must flag these local variables
5032 * to be updated and be sure the update takes place with the
5033 * new frequency before any guests proceed.
5034 *
5035 * Unfortunately, the combination of hotplug CPU and frequency
5036 * change creates an intractable locking scenario; the order
5037 * of when these callouts happen is undefined with respect to
5038 * CPU hotplug, and they can race with each other. As such,
5039 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5040 * undefined; you can actually have a CPU frequency change take
5041 * place in between the computation of X and the setting of the
5042 * variable. To protect against this problem, all updates of
5043 * the per_cpu tsc_khz variable are done in an interrupt
5044 * protected IPI, and all callers wishing to update the value
5045 * must wait for a synchronous IPI to complete (which is trivial
5046 * if the caller is on the CPU already). This establishes the
5047 * necessary total order on variable updates.
5048 *
5049 * Note that because a guest time update may take place
5050 * anytime after the setting of the VCPU's request bit, the
5051 * correct TSC value must be set before the request. However,
5052 * to ensure the update actually makes it to any guest which
5053 * starts running in hardware virtualization between the set
5054 * and the acquisition of the spinlock, we must also ping the
5055 * CPU after setting the request bit.
5056 *
5057 */
5058
c8076604
GH		 5059 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5060 return 0;
5061 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5062 return 0;
8cfdc000
ZA		 5063
5064 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5065
e935b837 5066 raw_spin_lock(&kvm_lock);
c8076604 5067 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5068 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5069 if (vcpu->cpu != freq->cpu)
5070 continue;
c285545f 5071 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5072 if (vcpu->cpu != smp_processor_id())
8cfdc000 5073 send_ipi = 1;
c8076604
GH		 5074 }
5075 }
e935b837 5076 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5077
5078 if (freq->old < freq->new && send_ipi) {
5079 /*
5080 * We upscale the frequency. Must make the guest
5081 * doesn't see old kvmclock values while running with
5082 * the new frequency, otherwise we risk the guest sees
5083 * time go backwards.
5084 *
5085 * In case we update the frequency for another cpu
5086 * (which might be in guest context) send an interrupt
5087 * to kick the cpu out of guest context. Next time
5088 * guest context is entered kvmclock will be updated,
5089 * so the guest will not see stale values.
5090 */
8cfdc000 5091 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5092 }
5093 return 0;
5094}
5095
5096static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5097 .notifier_call = kvmclock_cpufreq_notifier
5098};
5099
5100static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5101 unsigned long action, void *hcpu)
5102{
5103 unsigned int cpu = (unsigned long)hcpu;
5104
5105 switch (action) {
5106 case CPU_ONLINE:
5107 case CPU_DOWN_FAILED:
5108 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5109 break;
5110 case CPU_DOWN_PREPARE:
5111 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5112 break;
5113 }
5114 return NOTIFY_OK;
5115}
5116
5117static struct notifier_block kvmclock_cpu_notifier_block = {
5118 .notifier_call = kvmclock_cpu_notifier,
5119 .priority = -INT_MAX
c8076604
GH		 5120};
5121
b820cc0c
ZA		 5122static void kvm_timer_init(void)
5123{
5124 int cpu;
5125
c285545f 5126 max_tsc_khz = tsc_khz;
8cfdc000 5127 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5128 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5129#ifdef CONFIG_CPU_FREQ
5130 struct cpufreq_policy policy;
5131 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5132 cpu = get_cpu();
5133 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5134 if (policy.cpuinfo.max_freq)
5135 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5136 put_cpu();
c285545f 5137#endif
b820cc0c
ZA		 5138 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5139 CPUFREQ_TRANSITION_NOTIFIER);
5140 }
c285545f 5141 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5142 for_each_online_cpu(cpu)
5143 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5144}
5145
ff9d07a0
ZY		 5146static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5147
f5132b01 5148int kvm_is_in_guest(void)
ff9d07a0 5149{
086c9855 5150 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5151}
5152
5153static int kvm_is_user_mode(void)
5154{
5155 int user_mode = 3;
dcf46b94 5156
086c9855
AS		 5157 if (__this_cpu_read(current_vcpu))
5158 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5159
ff9d07a0
ZY		 5160 return user_mode != 0;
5161}
5162
5163static unsigned long kvm_get_guest_ip(void)
5164{
5165 unsigned long ip = 0;
dcf46b94 5166
086c9855
AS		 5167 if (__this_cpu_read(current_vcpu))
5168 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5169
ff9d07a0
ZY		 5170 return ip;
5171}
5172
5173static struct perf_guest_info_callbacks kvm_guest_cbs = {
5174 .is_in_guest = kvm_is_in_guest,
5175 .is_user_mode = kvm_is_user_mode,
5176 .get_guest_ip = kvm_get_guest_ip,
5177};
5178
5179void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5180{
086c9855 5181 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5182}
5183EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5184
5185void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5186{
086c9855 5187 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5188}
5189EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5190
ce88decf
XG		 5191static void kvm_set_mmio_spte_mask(void)
5192{
5193 u64 mask;
5194 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5195
5196 /*
5197 * Set the reserved bits and the present bit of an paging-structure
5198 * entry to generate page fault with PFER.RSV = 1.
5199 */
5200 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5201 mask |= 1ull;
5202
5203#ifdef CONFIG_X86_64
5204 /*
5205 * If reserved bit is not supported, clear the present bit to disable
5206 * mmio page fault.
5207 */
5208 if (maxphyaddr == 52)
5209 mask &= ~1ull;
5210#endif
5211
5212 kvm_mmu_set_mmio_spte_mask(mask);
5213}
5214
16e8d74d
MT		 5215#ifdef CONFIG_X86_64
5216static void pvclock_gtod_update_fn(struct work_struct *work)
5217{
d828199e
MT		 5218 struct kvm *kvm;
5219
5220 struct kvm_vcpu *vcpu;
5221 int i;
5222
5223 raw_spin_lock(&kvm_lock);
5224 list_for_each_entry(kvm, &vm_list, vm_list)
5225 kvm_for_each_vcpu(i, vcpu, kvm)
5226 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5227 atomic_set(&kvm_guest_has_master_clock, 0);
5228 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5229}
5230
5231static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5232
5233/*
5234 * Notification about pvclock gtod data update.
5235 */
5236static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5237 void *priv)
5238{
5239 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5240 struct timekeeper *tk = priv;
5241
5242 update_pvclock_gtod(tk);
5243
5244 /* disable master clock if host does not trust, or does not
5245 * use, TSC clocksource
5246 */
5247 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5248 atomic_read(&kvm_guest_has_master_clock) != 0)
5249 queue_work(system_long_wq, &pvclock_gtod_work);
5250
5251 return 0;
5252}
5253
5254static struct notifier_block pvclock_gtod_notifier = {
5255 .notifier_call = pvclock_gtod_notify,
5256};
5257#endif
5258
f8c16bba 5259int kvm_arch_init(void *opaque)
043405e1 5260{
b820cc0c 5261 int r;
f8c16bba
ZX		 5262 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5263
f8c16bba
ZX		 5264 if (kvm_x86_ops) {
5265 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5266 r = -EEXIST;
5267 goto out;
f8c16bba
ZX		 5268 }
5269
5270 if (!ops->cpu_has_kvm_support()) {
5271 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5272 r = -EOPNOTSUPP;
5273 goto out;
f8c16bba
ZX		 5274 }
5275 if (ops->disabled_by_bios()) {
5276 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5277 r = -EOPNOTSUPP;
5278 goto out;
f8c16bba
ZX		 5279 }
5280
013f6a5d
MT		 5281 r = -ENOMEM;
5282 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5283 if (!shared_msrs) {
5284 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5285 goto out;
5286 }
5287
97db56ce
AK		 5288 r = kvm_mmu_module_init();
5289 if (r)
013f6a5d 5290 goto out_free_percpu;
97db56ce 5291
ce88decf 5292 kvm_set_mmio_spte_mask();
97db56ce
AK		 5293 kvm_init_msr_list();
5294
f8c16bba 5295 kvm_x86_ops = ops;
7b52345e 5296 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5297 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5298
b820cc0c 5299 kvm_timer_init();
c8076604 5300
ff9d07a0
ZY		 5301 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5302
2acf923e
DC		 5303 if (cpu_has_xsave)
5304 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5305
c5cc421b 5306 kvm_lapic_init();
16e8d74d
MT		 5307#ifdef CONFIG_X86_64
5308 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5309#endif
5310
f8c16bba 5311 return 0;
56c6d28a 5312
013f6a5d
MT		 5313out_free_percpu:
5314 free_percpu(shared_msrs);
56c6d28a 5315out:
56c6d28a 5316 return r;
043405e1 5317}
8776e519 5318
f8c16bba
ZX		 5319void kvm_arch_exit(void)
5320{
ff9d07a0
ZY		 5321 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5322
888d256e
JK		 5323 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5324 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5325 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5326 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5327#ifdef CONFIG_X86_64
5328 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5329#endif
f8c16bba 5330 kvm_x86_ops = NULL;
56c6d28a 5331 kvm_mmu_module_exit();
013f6a5d 5332 free_percpu(shared_msrs);
56c6d28a 5333}
f8c16bba 5334
8776e519
HB		 5335int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5336{
5337 ++vcpu->stat.halt_exits;
5338 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5339 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5340 return 1;
5341 } else {
5342 vcpu->run->exit_reason = KVM_EXIT_HLT;
5343 return 0;
5344 }
5345}
5346EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5347
55cd8e5a
GN		 5348int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5349{
5350 u64 param, ingpa, outgpa, ret;
5351 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5352 bool fast, longmode;
5353 int cs_db, cs_l;
5354
5355 /*
5356 * hypercall generates UD from non zero cpl and real mode
5357 * per HYPER-V spec
5358 */
3eeb3288 5359 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5360 kvm_queue_exception(vcpu, UD_VECTOR);
5361 return 0;
5362 }
5363
5364 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5365 longmode = is_long_mode(vcpu) && cs_l == 1;
5366
5367 if (!longmode) {
ccd46936
GN		 5368 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5369 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5370 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5371 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5372 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5373 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5374 }
5375#ifdef CONFIG_X86_64
5376 else {
5377 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5378 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5379 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5380 }
5381#endif
5382
5383 code = param & 0xffff;
5384 fast = (param >> 16) & 0x1;
5385 rep_cnt = (param >> 32) & 0xfff;
5386 rep_idx = (param >> 48) & 0xfff;
5387
5388 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5389
c25bc163
GN		 5390 switch (code) {
5391 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5392 kvm_vcpu_on_spin(vcpu);
5393 break;
5394 default:
5395 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5396 break;
5397 }
55cd8e5a
GN		 5398
5399 ret = res | (((u64)rep_done & 0xfff) << 32);
5400 if (longmode) {
5401 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5402 } else {
5403 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5404 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5405 }
5406
5407 return 1;
5408}
5409
8776e519
HB		 5410int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5411{
5412 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5413 int r = 1;
8776e519 5414
55cd8e5a
GN		 5415 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5416 return kvm_hv_hypercall(vcpu);
5417
5fdbf976
MT		 5418 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5419 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5420 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5421 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5422 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5423
229456fc 5424 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5425
8776e519
HB		 5426 if (!is_long_mode(vcpu)) {
5427 nr &= 0xFFFFFFFF;
5428 a0 &= 0xFFFFFFFF;
5429 a1 &= 0xFFFFFFFF;
5430 a2 &= 0xFFFFFFFF;
5431 a3 &= 0xFFFFFFFF;
5432 }
5433
07708c4a
JK		 5434 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5435 ret = -KVM_EPERM;
5436 goto out;
5437 }
5438
8776e519 5439 switch (nr) {
b93463aa
AK		 5440 case KVM_HC_VAPIC_POLL_IRQ:
5441 ret = 0;
5442 break;
8776e519
HB		 5443 default:
5444 ret = -KVM_ENOSYS;
5445 break;
5446 }
07708c4a 5447out:
5fdbf976 5448 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5449 ++vcpu->stat.hypercalls;
2f333bcb 5450 return r;
8776e519
HB		 5451}
5452EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5453
b6785def 5454static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5455{
d6aa1000 5456 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5457 char instruction[3];
5fdbf976 5458 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5459
8776e519
HB		 5460 /*
5461 * Blow out the MMU to ensure that no other VCPU has an active mapping
5462 * to ensure that the updated hypercall appears atomically across all
5463 * VCPUs.
5464 */
5465 kvm_mmu_zap_all(vcpu->kvm);
5466
8776e519 5467 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5468
9d74191a 5469 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5470}
5471
b6c7a5dc
HB		 5472/*
5473 * Check if userspace requested an interrupt window, and that the
5474 * interrupt window is open.
5475 *
5476 * No need to exit to userspace if we already have an interrupt queued.
5477 */
851ba692 5478static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5479{
8061823a 5480 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5481 vcpu->run->request_interrupt_window &&
5df56646 5482 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5483}
5484
851ba692 5485static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5486{
851ba692
AK		 5487 struct kvm_run *kvm_run = vcpu->run;
5488
91586a3b 5489 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5490 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5491 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5492 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5493 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5494 else
b6c7a5dc 5495 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5496 kvm_arch_interrupt_allowed(vcpu) &&
5497 !kvm_cpu_has_interrupt(vcpu) &&
5498 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5499}
5500
4484141a 5501static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5502{
5503 struct kvm_lapic *apic = vcpu->arch.apic;
5504 struct page *page;
5505
5506 if (!apic || !apic->vapic_addr)
4484141a 5507 return 0;
b93463aa
AK		 5508
5509 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5510 if (is_error_page(page))
5511 return -EFAULT;
72dc67a6
IE		 5512
5513 vcpu->arch.apic->vapic_page = page;
4484141a 5514 return 0;
b93463aa
AK		 5515}
5516
5517static void vapic_exit(struct kvm_vcpu *vcpu)
5518{
5519 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5520 int idx;
b93463aa
AK		 5521
5522 if (!apic || !apic->vapic_addr)
5523 return;
5524
f656ce01 5525 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5526 kvm_release_page_dirty(apic->vapic_page);
5527 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5528 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5529}
5530
95ba8273
GN		 5531static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5532{
5533 int max_irr, tpr;
5534
5535 if (!kvm_x86_ops->update_cr8_intercept)
5536 return;
5537
88c808fd
AK		 5538 if (!vcpu->arch.apic)
5539 return;
5540
8db3baa2
GN		 5541 if (!vcpu->arch.apic->vapic_addr)
5542 max_irr = kvm_lapic_find_highest_irr(vcpu);
5543 else
5544 max_irr = -1;
95ba8273
GN		 5545
5546 if (max_irr != -1)
5547 max_irr >>= 4;
5548
5549 tpr = kvm_lapic_get_cr8(vcpu);
5550
5551 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5552}
5553
851ba692 5554static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5555{
5556 /* try to reinject previous events if any */
b59bb7bd 5557 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5558 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5559 vcpu->arch.exception.has_error_code,
5560 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5561 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5562 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5563 vcpu->arch.exception.error_code,
5564 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5565 return;
5566 }
5567
95ba8273
GN		 5568 if (vcpu->arch.nmi_injected) {
5569 kvm_x86_ops->set_nmi(vcpu);
5570 return;
5571 }
5572
5573 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5574 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5575 return;
5576 }
5577
5578 /* try to inject new event if pending */
5579 if (vcpu->arch.nmi_pending) {
5580 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5581 --vcpu->arch.nmi_pending;
95ba8273
GN		 5582 vcpu->arch.nmi_injected = true;
5583 kvm_x86_ops->set_nmi(vcpu);
5584 }
c7c9c56c 5585 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5586 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5587 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5588 false);
5589 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5590 }
5591 }
5592}
5593
2acf923e
DC		 5594static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5595{
5596 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5597 !vcpu->guest_xcr0_loaded) {
5598 /* kvm_set_xcr() also depends on this */
5599 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5600 vcpu->guest_xcr0_loaded = 1;
5601 }
5602}
5603
5604static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5605{
5606 if (vcpu->guest_xcr0_loaded) {
5607 if (vcpu->arch.xcr0 != host_xcr0)
5608 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5609 vcpu->guest_xcr0_loaded = 0;
5610 }
5611}
5612
7460fb4a
AK		 5613static void process_nmi(struct kvm_vcpu *vcpu)
5614{
5615 unsigned limit = 2;
5616
5617 /*
5618 * x86 is limited to one NMI running, and one NMI pending after it.
5619 * If an NMI is already in progress, limit further NMIs to just one.
5620 * Otherwise, allow two (and we'll inject the first one immediately).
5621 */
5622 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5623 limit = 1;
5624
5625 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5626 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5627 kvm_make_request(KVM_REQ_EVENT, vcpu);
5628}
5629
d828199e
MT		 5630static void kvm_gen_update_masterclock(struct kvm *kvm)
5631{
5632#ifdef CONFIG_X86_64
5633 int i;
5634 struct kvm_vcpu *vcpu;
5635 struct kvm_arch *ka = &kvm->arch;
5636
5637 spin_lock(&ka->pvclock_gtod_sync_lock);
5638 kvm_make_mclock_inprogress_request(kvm);
5639 /* no guest entries from this point */
5640 pvclock_update_vm_gtod_copy(kvm);
5641
5642 kvm_for_each_vcpu(i, vcpu, kvm)
5643 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5644
5645 /* guest entries allowed */
5646 kvm_for_each_vcpu(i, vcpu, kvm)
5647 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5648
5649 spin_unlock(&ka->pvclock_gtod_sync_lock);
5650#endif
5651}
5652
c7c9c56c
YZ		 5653static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
5654{
5655 u64 eoi_exit_bitmap[4];
5656
5657 memset(eoi_exit_bitmap, 0, 32);
5658
5659 kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
5660 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5661}
5662
851ba692 5663static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5664{
5665 int r;
6a8b1d13 5666 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5667 vcpu->run->request_interrupt_window;
d6185f20 5668 bool req_immediate_exit = 0;
b6c7a5dc 5669
3e007509 5670 if (vcpu->requests) {
a8eeb04a 5671 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5672 kvm_mmu_unload(vcpu);
a8eeb04a 5673 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5674 __kvm_migrate_timers(vcpu);
d828199e
MT		 5675 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5676 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5677 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5678 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5679 if (unlikely(r))
5680 goto out;
5681 }
a8eeb04a 5682 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5683 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5684 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5685 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5686 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5687 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5688 r = 0;
5689 goto out;
5690 }
a8eeb04a 5691 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5692 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5693 r = 0;
5694 goto out;
5695 }
a8eeb04a 5696 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5697 vcpu->fpu_active = 0;
5698 kvm_x86_ops->fpu_deactivate(vcpu);
5699 }
af585b92
GN		 5700 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5701 /* Page is swapped out. Do synthetic halt */
5702 vcpu->arch.apf.halted = true;
5703 r = 1;
5704 goto out;
5705 }
c9aaa895
GC		 5706 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5707 record_steal_time(vcpu);
7460fb4a
AK		 5708 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5709 process_nmi(vcpu);
d6185f20
NHE		 5710 req_immediate_exit =
5711 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5712 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5713 kvm_handle_pmu_event(vcpu);
5714 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5715 kvm_deliver_pmi(vcpu);
c7c9c56c
YZ		 5716 if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
5717 update_eoi_exitmap(vcpu);
2f52d58c 5718 }
b93463aa 5719
b463a6f7
AK		 5720 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5721 inject_pending_event(vcpu);
5722
5723 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5724 if (vcpu->arch.nmi_pending)
b463a6f7 5725 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5726 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
b463a6f7
AK		 5727 kvm_x86_ops->enable_irq_window(vcpu);
5728
5729 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5730 /*
5731 * Update architecture specific hints for APIC
5732 * virtual interrupt delivery.
5733 */
5734 if (kvm_x86_ops->hwapic_irr_update)
5735 kvm_x86_ops->hwapic_irr_update(vcpu,
5736 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5737 update_cr8_intercept(vcpu);
5738 kvm_lapic_sync_to_vapic(vcpu);
5739 }
5740 }
5741
d8368af8
AK		 5742 r = kvm_mmu_reload(vcpu);
5743 if (unlikely(r)) {
d905c069 5744 goto cancel_injection;
d8368af8
AK		 5745 }
5746
b6c7a5dc
HB		 5747 preempt_disable();
5748
5749 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5750 if (vcpu->fpu_active)
5751 kvm_load_guest_fpu(vcpu);
2acf923e 5752 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5753
6b7e2d09
XG		 5754 vcpu->mode = IN_GUEST_MODE;
5755
5756 /* We should set ->mode before check ->requests,
5757 * see the comment in make_all_cpus_request.
5758 */
5759 smp_mb();
b6c7a5dc 5760
d94e1dc9 5761 local_irq_disable();
32f88400 5762
6b7e2d09 5763 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5764 || need_resched() || signal_pending(current)) {
6b7e2d09 5765 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5766 smp_wmb();
6c142801
AK		 5767 local_irq_enable();
5768 preempt_enable();
5769 r = 1;
d905c069 5770 goto cancel_injection;
6c142801
AK		 5771 }
5772
f656ce01 5773 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5774
d6185f20
NHE		 5775 if (req_immediate_exit)
5776 smp_send_reschedule(vcpu->cpu);
5777
b6c7a5dc
HB		 5778 kvm_guest_enter();
5779
42dbaa5a 5780 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5781 set_debugreg(0, 7);
5782 set_debugreg(vcpu->arch.eff_db[0], 0);
5783 set_debugreg(vcpu->arch.eff_db[1], 1);
5784 set_debugreg(vcpu->arch.eff_db[2], 2);
5785 set_debugreg(vcpu->arch.eff_db[3], 3);
5786 }
b6c7a5dc 5787
229456fc 5788 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5789 kvm_x86_ops->run(vcpu);
b6c7a5dc 5790
24f1e32c
FW		 5791 /*
5792 * If the guest has used debug registers, at least dr7
5793 * will be disabled while returning to the host.
5794 * If we don't have active breakpoints in the host, we don't
5795 * care about the messed up debug address registers. But if
5796 * we have some of them active, restore the old state.
5797 */
59d8eb53 5798 if (hw_breakpoint_active())
24f1e32c 5799 hw_breakpoint_restore();
42dbaa5a 5800
886b470c
MT		 5801 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5802 native_read_tsc());
1d5f066e 5803
6b7e2d09 5804 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5805 smp_wmb();
b6c7a5dc
HB		 5806 local_irq_enable();
5807
5808 ++vcpu->stat.exits;
5809
5810 /*
5811 * We must have an instruction between local_irq_enable() and
5812 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5813 * the interrupt shadow. The stat.exits increment will do nicely.
5814 * But we need to prevent reordering, hence this barrier():
5815 */
5816 barrier();
5817
5818 kvm_guest_exit();
5819
5820 preempt_enable();
5821
f656ce01 5822 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5823
b6c7a5dc
HB		 5824 /*
5825 * Profile KVM exit RIPs:
5826 */
5827 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5828 unsigned long rip = kvm_rip_read(vcpu);
5829 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5830 }
5831
cc578287
ZA		 5832 if (unlikely(vcpu->arch.tsc_always_catchup))
5833 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5834
5cfb1d5a
MT		 5835 if (vcpu->arch.apic_attention)
5836 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5837
851ba692 5838 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5839 return r;
5840
5841cancel_injection:
5842 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5843 if (unlikely(vcpu->arch.apic_attention))
5844 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5845out:
5846 return r;
5847}
b6c7a5dc 5848
09cec754 5849
851ba692 5850static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5851{
5852 int r;
f656ce01 5853 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5854
5855 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5856 pr_debug("vcpu %d received sipi with vector # %x\n",
5857 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5858 kvm_lapic_reset(vcpu);
8b6e4547 5859 r = kvm_vcpu_reset(vcpu);
d7690175
MT		 5860 if (r)
5861 return r;
5862 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5863 }
5864
f656ce01 5865 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5866 r = vapic_enter(vcpu);
5867 if (r) {
5868 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5869 return r;
5870 }
d7690175
MT		 5871
5872 r = 1;
5873 while (r > 0) {
af585b92
GN		 5874 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5875 !vcpu->arch.apf.halted)
851ba692 5876 r = vcpu_enter_guest(vcpu);
d7690175 5877 else {
f656ce01 5878 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5879 kvm_vcpu_block(vcpu);
f656ce01 5880 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5881 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5882 {
5883 switch(vcpu->arch.mp_state) {
5884 case KVM_MP_STATE_HALTED:
d7690175 5885 vcpu->arch.mp_state =
09cec754
GN		 5886 KVM_MP_STATE_RUNNABLE;
5887 case KVM_MP_STATE_RUNNABLE:
af585b92 5888 vcpu->arch.apf.halted = false;
09cec754
GN		 5889 break;
5890 case KVM_MP_STATE_SIPI_RECEIVED:
5891 default:
5892 r = -EINTR;
5893 break;
5894 }
5895 }
d7690175
MT		 5896 }
5897
09cec754
GN		 5898 if (r <= 0)
5899 break;
5900
5901 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5902 if (kvm_cpu_has_pending_timer(vcpu))
5903 kvm_inject_pending_timer_irqs(vcpu);
5904
851ba692 5905 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5906 r = -EINTR;
851ba692 5907 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5908 ++vcpu->stat.request_irq_exits;
5909 }
af585b92
GN		 5910
5911 kvm_check_async_pf_completion(vcpu);
5912
09cec754
GN		 5913 if (signal_pending(current)) {
5914 r = -EINTR;
851ba692 5915 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5916 ++vcpu->stat.signal_exits;
5917 }
5918 if (need_resched()) {
f656ce01 5919 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5920 kvm_resched(vcpu);
f656ce01 5921 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5922 }
b6c7a5dc
HB		 5923 }
5924
f656ce01 5925 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5926
b93463aa
AK		 5927 vapic_exit(vcpu);
5928
b6c7a5dc
HB		 5929 return r;
5930}
5931
716d51ab
GN		 5932static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5933{
5934 int r;
5935 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5936 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5937 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5938 if (r != EMULATE_DONE)
5939 return 0;
5940 return 1;
5941}
5942
5943static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5944{
5945 BUG_ON(!vcpu->arch.pio.count);
5946
5947 return complete_emulated_io(vcpu);
5948}
5949
f78146b0
AK		 5950/*
5951 * Implements the following, as a state machine:
5952 *
5953 * read:
5954 * for each fragment
87da7e66
XG		 5955 * for each mmio piece in the fragment
5956 * write gpa, len
5957 * exit
5958 * copy data
f78146b0
AK		 5959 * execute insn
5960 *
5961 * write:
5962 * for each fragment
87da7e66
XG		 5963 * for each mmio piece in the fragment
5964 * write gpa, len
5965 * copy data
5966 * exit
f78146b0 5967 */
716d51ab 5968static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5969{
5970 struct kvm_run *run = vcpu->run;
f78146b0 5971 struct kvm_mmio_fragment *frag;
87da7e66 5972 unsigned len;
5287f194 5973
716d51ab 5974 BUG_ON(!vcpu->mmio_needed);
5287f194 5975
716d51ab 5976 /* Complete previous fragment */
87da7e66
XG		 5977 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5978 len = min(8u, frag->len);
716d51ab 5979 if (!vcpu->mmio_is_write)
87da7e66
XG		 5980 memcpy(frag->data, run->mmio.data, len);
5981
5982 if (frag->len <= 8) {
5983 /* Switch to the next fragment. */
5984 frag++;
5985 vcpu->mmio_cur_fragment++;
5986 } else {
5987 /* Go forward to the next mmio piece. */
5988 frag->data += len;
5989 frag->gpa += len;
5990 frag->len -= len;
5991 }
5992
716d51ab
GN		 5993 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5994 vcpu->mmio_needed = 0;
cef4dea0 5995 if (vcpu->mmio_is_write)
716d51ab
GN		 5996 return 1;
5997 vcpu->mmio_read_completed = 1;
5998 return complete_emulated_io(vcpu);
5999 }
87da7e66 6000
716d51ab
GN		 6001 run->exit_reason = KVM_EXIT_MMIO;
6002 run->mmio.phys_addr = frag->gpa;
6003 if (vcpu->mmio_is_write)
87da7e66
XG		 6004 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6005 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6006 run->mmio.is_write = vcpu->mmio_is_write;
6007 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6008 return 0;
5287f194
AK		 6009}
6010
716d51ab 6011
b6c7a5dc
HB		 6012int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6013{
6014 int r;
6015 sigset_t sigsaved;
6016
e5c30142
AK		 6017 if (!tsk_used_math(current) && init_fpu(current))
6018 return -ENOMEM;
6019
ac9f6dc0
AK		 6020 if (vcpu->sigset_active)
6021 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6022
a4535290 6023 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6024 kvm_vcpu_block(vcpu);
d7690175 6025 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6026 r = -EAGAIN;
6027 goto out;
b6c7a5dc
HB		 6028 }
6029
b6c7a5dc 6030 /* re-sync apic's tpr */
eea1cff9
AP		 6031 if (!irqchip_in_kernel(vcpu->kvm)) {
6032 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6033 r = -EINVAL;
6034 goto out;
6035 }
6036 }
b6c7a5dc 6037
716d51ab
GN		 6038 if (unlikely(vcpu->arch.complete_userspace_io)) {
6039 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6040 vcpu->arch.complete_userspace_io = NULL;
6041 r = cui(vcpu);
6042 if (r <= 0)
6043 goto out;
6044 } else
6045 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6046
851ba692 6047 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6048
6049out:
f1d86e46 6050 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6051 if (vcpu->sigset_active)
6052 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6053
b6c7a5dc
HB		 6054 return r;
6055}
6056
6057int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6058{
7ae441ea
GN		 6059 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6060 /*
6061 * We are here if userspace calls get_regs() in the middle of
6062 * instruction emulation. Registers state needs to be copied
4a969980 6063 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6064 * that usually, but some bad designed PV devices (vmware
6065 * backdoor interface) need this to work
6066 */
dd856efa 6067 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6068 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6069 }
5fdbf976
MT		 6070 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6071 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6072 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6073 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6074 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6075 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6076 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6077 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6078#ifdef CONFIG_X86_64
5fdbf976
MT		 6079 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6080 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6081 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6082 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6083 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6084 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6085 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6086 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6087#endif
6088
5fdbf976 6089 regs->rip = kvm_rip_read(vcpu);
91586a3b 6090 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6091
b6c7a5dc
HB		 6092 return 0;
6093}
6094
6095int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6096{
7ae441ea
GN		 6097 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6098 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6099
5fdbf976
MT		 6100 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6101 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6102 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6103 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6104 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6105 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6106 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6107 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6108#ifdef CONFIG_X86_64
5fdbf976
MT		 6109 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6110 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6111 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6112 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6113 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6114 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6115 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6116 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6117#endif
6118
5fdbf976 6119 kvm_rip_write(vcpu, regs->rip);
91586a3b 6120 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6121
b4f14abd
JK		 6122 vcpu->arch.exception.pending = false;
6123
3842d135
AK		 6124 kvm_make_request(KVM_REQ_EVENT, vcpu);
6125
b6c7a5dc
HB		 6126 return 0;
6127}
6128
b6c7a5dc
HB		 6129void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6130{
6131 struct kvm_segment cs;
6132
3e6e0aab 6133 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6134 *db = cs.db;
6135 *l = cs.l;
6136}
6137EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6138
6139int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6140 struct kvm_sregs *sregs)
6141{
89a27f4d 6142 struct desc_ptr dt;
b6c7a5dc 6143
3e6e0aab
GT		 6144 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6145 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6146 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6147 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6148 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6149 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6150
3e6e0aab
GT		 6151 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6152 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6153
6154 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6155 sregs->idt.limit = dt.size;
6156 sregs->idt.base = dt.address;
b6c7a5dc 6157 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6158 sregs->gdt.limit = dt.size;
6159 sregs->gdt.base = dt.address;
b6c7a5dc 6160
4d4ec087 6161 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6162 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6163 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6164 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6165 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6166 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6167 sregs->apic_base = kvm_get_apic_base(vcpu);
6168
923c61bb 6169 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6170
36752c9b 6171 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6172 set_bit(vcpu->arch.interrupt.nr,
6173 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6174
b6c7a5dc
HB		 6175 return 0;
6176}
6177
62d9f0db
MT		 6178int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6179 struct kvm_mp_state *mp_state)
6180{
62d9f0db 6181 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6182 return 0;
6183}
6184
6185int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6186 struct kvm_mp_state *mp_state)
6187{
62d9f0db 6188 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6189 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6190 return 0;
6191}
6192
7f3d35fd
KW		 6193int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6194 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6195{
9d74191a 6196 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6197 int ret;
e01c2426 6198
8ec4722d 6199 init_emulate_ctxt(vcpu);
c697518a 6200
7f3d35fd 6201 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6202 has_error_code, error_code);
c697518a 6203
c697518a 6204 if (ret)
19d04437 6205 return EMULATE_FAIL;
37817f29 6206
9d74191a
TY		 6207 kvm_rip_write(vcpu, ctxt->eip);
6208 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6209 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6210 return EMULATE_DONE;
37817f29
IE		 6211}
6212EXPORT_SYMBOL_GPL(kvm_task_switch);
6213
b6c7a5dc
HB		 6214int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6215 struct kvm_sregs *sregs)
6216{
6217 int mmu_reset_needed = 0;
63f42e02 6218 int pending_vec, max_bits, idx;
89a27f4d 6219 struct desc_ptr dt;
b6c7a5dc 6220
6d1068b3
PM		 6221 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6222 return -EINVAL;
6223
89a27f4d
GN		 6224 dt.size = sregs->idt.limit;
6225 dt.address = sregs->idt.base;
b6c7a5dc 6226 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6227 dt.size = sregs->gdt.limit;
6228 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6229 kvm_x86_ops->set_gdt(vcpu, &dt);
6230
ad312c7c 6231 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6232 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6233 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6234 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6235
2d3ad1f4 6236 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6237
f6801dff 6238 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6239 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6240 kvm_set_apic_base(vcpu, sregs->apic_base);
6241
4d4ec087 6242 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6243 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6244 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6245
fc78f519 6246 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6247 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6248 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6249 kvm_update_cpuid(vcpu);
63f42e02
XG		 6250
6251 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6252 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6253 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6254 mmu_reset_needed = 1;
6255 }
63f42e02 6256 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6257
6258 if (mmu_reset_needed)
6259 kvm_mmu_reset_context(vcpu);
6260
a50abc3b 6261 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6262 pending_vec = find_first_bit(
6263 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6264 if (pending_vec < max_bits) {
66fd3f7f 6265 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6266 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6267 }
6268
3e6e0aab
GT		 6269 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6270 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6271 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6272 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6273 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6274 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6275
3e6e0aab
GT		 6276 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6277 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6278
5f0269f5
ME		 6279 update_cr8_intercept(vcpu);
6280
9c3e4aab 6281 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6282 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6283 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6284 !is_protmode(vcpu))
9c3e4aab
MT		 6285 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6286
3842d135
AK		 6287 kvm_make_request(KVM_REQ_EVENT, vcpu);
6288
b6c7a5dc
HB		 6289 return 0;
6290}
6291
d0bfb940
JK		 6292int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6293 struct kvm_guest_debug *dbg)
b6c7a5dc 6294{
355be0b9 6295 unsigned long rflags;
ae675ef0 6296 int i, r;
b6c7a5dc 6297
4f926bf2
JK		 6298 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6299 r = -EBUSY;
6300 if (vcpu->arch.exception.pending)
2122ff5e 6301 goto out;
4f926bf2
JK		 6302 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6303 kvm_queue_exception(vcpu, DB_VECTOR);
6304 else
6305 kvm_queue_exception(vcpu, BP_VECTOR);
6306 }
6307
91586a3b
JK		 6308 /*
6309 * Read rflags as long as potentially injected trace flags are still
6310 * filtered out.
6311 */
6312 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6313
6314 vcpu->guest_debug = dbg->control;
6315 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6316 vcpu->guest_debug = 0;
6317
6318 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6319 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6320 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6321 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6322 } else {
6323 for (i = 0; i < KVM_NR_DB_REGS; i++)
6324 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6325 }
c8639010 6326 kvm_update_dr7(vcpu);
ae675ef0 6327
f92653ee
JK		 6328 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6329 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6330 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6331
91586a3b
JK		 6332 /*
6333 * Trigger an rflags update that will inject or remove the trace
6334 * flags.
6335 */
6336 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6337
c8639010 6338 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6339
4f926bf2 6340 r = 0;
d0bfb940 6341
2122ff5e 6342out:
b6c7a5dc
HB		 6343
6344 return r;
6345}
6346
8b006791
ZX		 6347/*
6348 * Translate a guest virtual address to a guest physical address.
6349 */
6350int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6351 struct kvm_translation *tr)
6352{
6353 unsigned long vaddr = tr->linear_address;
6354 gpa_t gpa;
f656ce01 6355 int idx;
8b006791 6356
f656ce01 6357 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6358 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6359 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6360 tr->physical_address = gpa;
6361 tr->valid = gpa != UNMAPPED_GVA;
6362 tr->writeable = 1;
6363 tr->usermode = 0;
8b006791
ZX		 6364
6365 return 0;
6366}
6367
d0752060
HB		 6368int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6369{
98918833
SY		 6370 struct i387_fxsave_struct *fxsave =
6371 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6372
d0752060
HB		 6373 memcpy(fpu->fpr, fxsave->st_space, 128);
6374 fpu->fcw = fxsave->cwd;
6375 fpu->fsw = fxsave->swd;
6376 fpu->ftwx = fxsave->twd;
6377 fpu->last_opcode = fxsave->fop;
6378 fpu->last_ip = fxsave->rip;
6379 fpu->last_dp = fxsave->rdp;
6380 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6381
d0752060
HB		 6382 return 0;
6383}
6384
6385int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6386{
98918833
SY		 6387 struct i387_fxsave_struct *fxsave =
6388 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6389
d0752060
HB		 6390 memcpy(fxsave->st_space, fpu->fpr, 128);
6391 fxsave->cwd = fpu->fcw;
6392 fxsave->swd = fpu->fsw;
6393 fxsave->twd = fpu->ftwx;
6394 fxsave->fop = fpu->last_opcode;
6395 fxsave->rip = fpu->last_ip;
6396 fxsave->rdp = fpu->last_dp;
6397 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6398
d0752060
HB		 6399 return 0;
6400}
6401
10ab25cd 6402int fx_init(struct kvm_vcpu *vcpu)
d0752060 6403{
10ab25cd
JK		 6404 int err;
6405
6406 err = fpu_alloc(&vcpu->arch.guest_fpu);
6407 if (err)
6408 return err;
6409
98918833 6410 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6411
2acf923e
DC		 6412 /*
6413 * Ensure guest xcr0 is valid for loading
6414 */
6415 vcpu->arch.xcr0 = XSTATE_FP;
6416
ad312c7c 6417 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6418
6419 return 0;
d0752060
HB		 6420}
6421EXPORT_SYMBOL_GPL(fx_init);
6422
98918833
SY		 6423static void fx_free(struct kvm_vcpu *vcpu)
6424{
6425 fpu_free(&vcpu->arch.guest_fpu);
6426}
6427
d0752060
HB		 6428void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6429{
2608d7a1 6430 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6431 return;
6432
2acf923e
DC		 6433 /*
6434 * Restore all possible states in the guest,
6435 * and assume host would use all available bits.
6436 * Guest xcr0 would be loaded later.
6437 */
6438 kvm_put_guest_xcr0(vcpu);
d0752060 6439 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6440 __kernel_fpu_begin();
98918833 6441 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6442 trace_kvm_fpu(1);
d0752060 6443}
d0752060
HB		 6444
6445void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6446{
2acf923e
DC		 6447 kvm_put_guest_xcr0(vcpu);
6448
d0752060
HB		 6449 if (!vcpu->guest_fpu_loaded)
6450 return;
6451
6452 vcpu->guest_fpu_loaded = 0;
98918833 6453 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6454 __kernel_fpu_end();
f096ed85 6455 ++vcpu->stat.fpu_reload;
a8eeb04a 6456 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6457 trace_kvm_fpu(0);
d0752060 6458}
e9b11c17
ZX		 6459
6460void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6461{
12f9a48f 6462 kvmclock_reset(vcpu);
7f1ea208 6463
f5f48ee1 6464 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6465 fx_free(vcpu);
e9b11c17
ZX		 6466 kvm_x86_ops->vcpu_free(vcpu);
6467}
6468
6469struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6470 unsigned int id)
6471{
6755bae8
ZA		 6472 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6473 printk_once(KERN_WARNING
6474 "kvm: SMP vm created on host with unstable TSC; "
6475 "guest TSC will not be reliable\n");
26e5215f
AK		 6476 return kvm_x86_ops->vcpu_create(kvm, id);
6477}
e9b11c17 6478
26e5215f
AK		 6479int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6480{
6481 int r;
e9b11c17 6482
0bed3b56 6483 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6484 r = vcpu_load(vcpu);
6485 if (r)
6486 return r;
8b6e4547 6487 r = kvm_vcpu_reset(vcpu);
e9b11c17
ZX		 6488 if (r == 0)
6489 r = kvm_mmu_setup(vcpu);
6490 vcpu_put(vcpu);
e9b11c17 6491
26e5215f 6492 return r;
e9b11c17
ZX		 6493}
6494
42897d86
MT		 6495int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6496{
6497 int r;
8fe8ab46 6498 struct msr_data msr;
42897d86
MT		 6499
6500 r = vcpu_load(vcpu);
6501 if (r)
6502 return r;
8fe8ab46
WA		 6503 msr.data = 0x0;
6504 msr.index = MSR_IA32_TSC;
6505 msr.host_initiated = true;
6506 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6507 vcpu_put(vcpu);
6508
6509 return r;
6510}
6511
d40ccc62 6512void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6513{
9fc77441 6514 int r;
344d9588
GN		 6515 vcpu->arch.apf.msr_val = 0;
6516
9fc77441
MT		 6517 r = vcpu_load(vcpu);
6518 BUG_ON(r);
e9b11c17
ZX		 6519 kvm_mmu_unload(vcpu);
6520 vcpu_put(vcpu);
6521
98918833 6522 fx_free(vcpu);
e9b11c17
ZX		 6523 kvm_x86_ops->vcpu_free(vcpu);
6524}
6525
8b6e4547 6526static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6527{
7460fb4a
AK		 6528 atomic_set(&vcpu->arch.nmi_queued, 0);
6529 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6530 vcpu->arch.nmi_injected = false;
6531
42dbaa5a
JK		 6532 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6533 vcpu->arch.dr6 = DR6_FIXED_1;
6534 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6535 kvm_update_dr7(vcpu);
42dbaa5a 6536
3842d135 6537 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6538 vcpu->arch.apf.msr_val = 0;
c9aaa895 6539 vcpu->arch.st.msr_val = 0;
3842d135 6540
12f9a48f
GC		 6541 kvmclock_reset(vcpu);
6542
af585b92
GN		 6543 kvm_clear_async_pf_completion_queue(vcpu);
6544 kvm_async_pf_hash_reset(vcpu);
6545 vcpu->arch.apf.halted = false;
3842d135 6546
f5132b01
GN		 6547 kvm_pmu_reset(vcpu);
6548
66f7b72e
JS		 6549 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6550 vcpu->arch.regs_avail = ~0;
6551 vcpu->arch.regs_dirty = ~0;
6552
e9b11c17
ZX		 6553 return kvm_x86_ops->vcpu_reset(vcpu);
6554}
6555
10474ae8 6556int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6557{
ca84d1a2
ZA		 6558 struct kvm *kvm;
6559 struct kvm_vcpu *vcpu;
6560 int i;
0dd6a6ed
ZA		 6561 int ret;
6562 u64 local_tsc;
6563 u64 max_tsc = 0;
6564 bool stable, backwards_tsc = false;
18863bdd
AK		 6565
6566 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6567 ret = kvm_x86_ops->hardware_enable(garbage);
6568 if (ret != 0)
6569 return ret;
6570
6571 local_tsc = native_read_tsc();
6572 stable = !check_tsc_unstable();
6573 list_for_each_entry(kvm, &vm_list, vm_list) {
6574 kvm_for_each_vcpu(i, vcpu, kvm) {
6575 if (!stable && vcpu->cpu == smp_processor_id())
6576 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6577 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6578 backwards_tsc = true;
6579 if (vcpu->arch.last_host_tsc > max_tsc)
6580 max_tsc = vcpu->arch.last_host_tsc;
6581 }
6582 }
6583 }
6584
6585 /*
6586 * Sometimes, even reliable TSCs go backwards. This happens on
6587 * platforms that reset TSC during suspend or hibernate actions, but
6588 * maintain synchronization. We must compensate. Fortunately, we can
6589 * detect that condition here, which happens early in CPU bringup,
6590 * before any KVM threads can be running. Unfortunately, we can't
6591 * bring the TSCs fully up to date with real time, as we aren't yet far
6592 * enough into CPU bringup that we know how much real time has actually
6593 * elapsed; our helper function, get_kernel_ns() will be using boot
6594 * variables that haven't been updated yet.
6595 *
6596 * So we simply find the maximum observed TSC above, then record the
6597 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6598 * the adjustment will be applied. Note that we accumulate
6599 * adjustments, in case multiple suspend cycles happen before some VCPU
6600 * gets a chance to run again. In the event that no KVM threads get a
6601 * chance to run, we will miss the entire elapsed period, as we'll have
6602 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6603 * loose cycle time. This isn't too big a deal, since the loss will be
6604 * uniform across all VCPUs (not to mention the scenario is extremely
6605 * unlikely). It is possible that a second hibernate recovery happens
6606 * much faster than a first, causing the observed TSC here to be
6607 * smaller; this would require additional padding adjustment, which is
6608 * why we set last_host_tsc to the local tsc observed here.
6609 *
6610 * N.B. - this code below runs only on platforms with reliable TSC,
6611 * as that is the only way backwards_tsc is set above. Also note
6612 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6613 * have the same delta_cyc adjustment applied if backwards_tsc
6614 * is detected. Note further, this adjustment is only done once,
6615 * as we reset last_host_tsc on all VCPUs to stop this from being
6616 * called multiple times (one for each physical CPU bringup).
6617 *
4a969980 6618 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6619 * will be compensated by the logic in vcpu_load, which sets the TSC to
6620 * catchup mode. This will catchup all VCPUs to real time, but cannot
6621 * guarantee that they stay in perfect synchronization.
6622 */
6623 if (backwards_tsc) {
6624 u64 delta_cyc = max_tsc - local_tsc;
6625 list_for_each_entry(kvm, &vm_list, vm_list) {
6626 kvm_for_each_vcpu(i, vcpu, kvm) {
6627 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6628 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6629 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6630 &vcpu->requests);
0dd6a6ed
ZA		 6631 }
6632
6633 /*
6634 * We have to disable TSC offset matching.. if you were
6635 * booting a VM while issuing an S4 host suspend....
6636 * you may have some problem. Solving this issue is
6637 * left as an exercise to the reader.
6638 */
6639 kvm->arch.last_tsc_nsec = 0;
6640 kvm->arch.last_tsc_write = 0;
6641 }
6642
6643 }
6644 return 0;
e9b11c17
ZX		 6645}
6646
6647void kvm_arch_hardware_disable(void *garbage)
6648{
6649 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6650 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6651}
6652
6653int kvm_arch_hardware_setup(void)
6654{
6655 return kvm_x86_ops->hardware_setup();
6656}
6657
6658void kvm_arch_hardware_unsetup(void)
6659{
6660 kvm_x86_ops->hardware_unsetup();
6661}
6662
6663void kvm_arch_check_processor_compat(void *rtn)
6664{
6665 kvm_x86_ops->check_processor_compatibility(rtn);
6666}
6667
3e515705
AK		 6668bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6669{
6670 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6671}
6672
54e9818f
GN		 6673struct static_key kvm_no_apic_vcpu __read_mostly;
6674
e9b11c17
ZX		 6675int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6676{
6677 struct page *page;
6678 struct kvm *kvm;
6679 int r;
6680
6681 BUG_ON(vcpu->kvm == NULL);
6682 kvm = vcpu->kvm;
6683
9aabc88f 6684 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6685 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6686 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6687 else
a4535290 6688 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6689
6690 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6691 if (!page) {
6692 r = -ENOMEM;
6693 goto fail;
6694 }
ad312c7c 6695 vcpu->arch.pio_data = page_address(page);
e9b11c17 6696
cc578287 6697 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6698
e9b11c17
ZX		 6699 r = kvm_mmu_create(vcpu);
6700 if (r < 0)
6701 goto fail_free_pio_data;
6702
6703 if (irqchip_in_kernel(kvm)) {
6704 r = kvm_create_lapic(vcpu);
6705 if (r < 0)
6706 goto fail_mmu_destroy;
54e9818f
GN		 6707 } else
6708 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6709
890ca9ae
HY		 6710 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6711 GFP_KERNEL);
6712 if (!vcpu->arch.mce_banks) {
6713 r = -ENOMEM;
443c39bc 6714 goto fail_free_lapic;
890ca9ae
HY		 6715 }
6716 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6717
f5f48ee1
SY		 6718 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6719 goto fail_free_mce_banks;
6720
66f7b72e
JS		 6721 r = fx_init(vcpu);
6722 if (r)
6723 goto fail_free_wbinvd_dirty_mask;
6724
ba904635 6725 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
af585b92 6726 kvm_async_pf_hash_reset(vcpu);
f5132b01 6727 kvm_pmu_init(vcpu);
af585b92 6728
e9b11c17 6729 return 0;
66f7b72e
JS		 6730fail_free_wbinvd_dirty_mask:
6731 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6732fail_free_mce_banks:
6733 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6734fail_free_lapic:
6735 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6736fail_mmu_destroy:
6737 kvm_mmu_destroy(vcpu);
6738fail_free_pio_data:
ad312c7c 6739 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6740fail:
6741 return r;
6742}
6743
6744void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6745{
f656ce01
MT		 6746 int idx;
6747
f5132b01 6748 kvm_pmu_destroy(vcpu);
36cb93fd 6749 kfree(vcpu->arch.mce_banks);
e9b11c17 6750 kvm_free_lapic(vcpu);
f656ce01 6751 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6752 kvm_mmu_destroy(vcpu);
f656ce01 6753 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6754 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6755 if (!irqchip_in_kernel(vcpu->kvm))
6756 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6757}
d19a9cd2 6758
e08b9637 6759int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6760{
e08b9637
CO		 6761 if (type)
6762 return -EINVAL;
6763
f05e70ac 6764 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6765 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6766
5550af4d
SY		 6767 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6768 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6769 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6770 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6771 &kvm->arch.irq_sources_bitmap);
5550af4d 6772
038f8c11 6773 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6774 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6775 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6776
6777 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6778
d89f5eff 6779 return 0;
d19a9cd2
ZX		 6780}
6781
6782static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6783{
9fc77441
MT		 6784 int r;
6785 r = vcpu_load(vcpu);
6786 BUG_ON(r);
d19a9cd2
ZX		 6787 kvm_mmu_unload(vcpu);
6788 vcpu_put(vcpu);
6789}
6790
6791static void kvm_free_vcpus(struct kvm *kvm)
6792{
6793 unsigned int i;
988a2cae 6794 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6795
6796 /*
6797 * Unpin any mmu pages first.
6798 */
af585b92
GN		 6799 kvm_for_each_vcpu(i, vcpu, kvm) {
6800 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6801 kvm_unload_vcpu_mmu(vcpu);
af585b92 6802 }
988a2cae
GN		 6803 kvm_for_each_vcpu(i, vcpu, kvm)
6804 kvm_arch_vcpu_free(vcpu);
6805
6806 mutex_lock(&kvm->lock);
6807 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6808 kvm->vcpus[i] = NULL;
d19a9cd2 6809
988a2cae
GN		 6810 atomic_set(&kvm->online_vcpus, 0);
6811 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6812}
6813
ad8ba2cd
SY		 6814void kvm_arch_sync_events(struct kvm *kvm)
6815{
ba4cef31 6816 kvm_free_all_assigned_devices(kvm);
aea924f6 6817 kvm_free_pit(kvm);
ad8ba2cd
SY		 6818}
6819
d19a9cd2
ZX		 6820void kvm_arch_destroy_vm(struct kvm *kvm)
6821{
6eb55818 6822 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6823 kfree(kvm->arch.vpic);
6824 kfree(kvm->arch.vioapic);
d19a9cd2 6825 kvm_free_vcpus(kvm);
3d45830c
AK		 6826 if (kvm->arch.apic_access_page)
6827 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6828 if (kvm->arch.ept_identity_pagetable)
6829 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6830 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6831}
0de10343 6832
db3fe4eb
TY		 6833void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6834 struct kvm_memory_slot *dont)
6835{
6836 int i;
6837
d89cc617
TY		 6838 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6839 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6840 kvm_kvfree(free->arch.rmap[i]);
6841 free->arch.rmap[i] = NULL;
77d11309 6842 }
d89cc617
TY		 6843 if (i == 0)
6844 continue;
6845
6846 if (!dont || free->arch.lpage_info[i - 1] !=
6847 dont->arch.lpage_info[i - 1]) {
6848 kvm_kvfree(free->arch.lpage_info[i - 1]);
6849 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6850 }
6851 }
6852}
6853
6854int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6855{
6856 int i;
6857
d89cc617 6858 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6859 unsigned long ugfn;
6860 int lpages;
d89cc617 6861 int level = i + 1;
db3fe4eb
TY		 6862
6863 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6864 slot->base_gfn, level) + 1;
6865
d89cc617
TY		 6866 slot->arch.rmap[i] =
6867 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6868 if (!slot->arch.rmap[i])
77d11309 6869 goto out_free;
d89cc617
TY		 6870 if (i == 0)
6871 continue;
77d11309 6872
d89cc617
TY		 6873 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6874 sizeof(*slot->arch.lpage_info[i - 1]));
6875 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6876 goto out_free;
6877
6878 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6879 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6880 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6881 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6882 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6883 /*
6884 * If the gfn and userspace address are not aligned wrt each
6885 * other, or if explicitly asked to, disable large page
6886 * support for this slot
6887 */
6888 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6889 !kvm_largepages_enabled()) {
6890 unsigned long j;
6891
6892 for (j = 0; j < lpages; ++j)
d89cc617 6893 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6894 }
6895 }
6896
6897 return 0;
6898
6899out_free:
d89cc617
TY		 6900 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6901 kvm_kvfree(slot->arch.rmap[i]);
6902 slot->arch.rmap[i] = NULL;
6903 if (i == 0)
6904 continue;
6905
6906 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6907 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6908 }
6909 return -ENOMEM;
6910}
6911
f7784b8e
MT		 6912int kvm_arch_prepare_memory_region(struct kvm *kvm,
6913 struct kvm_memory_slot *memslot,
0de10343 6914 struct kvm_memory_slot old,
f7784b8e 6915 struct kvm_userspace_memory_region *mem,
f82a8cfe 6916 bool user_alloc)
0de10343 6917{
f7784b8e 6918 int npages = memslot->npages;
7ac77099 6919
7a905b14
TY		 6920 /*
6921 * Only private memory slots need to be mapped here since
6922 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 6923 */
7a905b14
TY		 6924 if ((memslot->id >= KVM_USER_MEM_SLOTS) && npages && !old.npages) {
6925 unsigned long userspace_addr;
604b38ac 6926
7a905b14
TY		 6927 /*
6928 * MAP_SHARED to prevent internal slot pages from being moved
6929 * by fork()/COW.
6930 */
6931 userspace_addr = vm_mmap(NULL, 0, npages * PAGE_SIZE,
6932 PROT_READ | PROT_WRITE,
6933 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 6934
7a905b14
TY		 6935 if (IS_ERR((void *)userspace_addr))
6936 return PTR_ERR((void *)userspace_addr);
604b38ac 6937
7a905b14 6938 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6939 }
6940
f7784b8e
MT		 6941 return 0;
6942}
6943
6944void kvm_arch_commit_memory_region(struct kvm *kvm,
6945 struct kvm_userspace_memory_region *mem,
6946 struct kvm_memory_slot old,
f82a8cfe 6947 bool user_alloc)
f7784b8e
MT		 6948{
6949
48c0e4e9 6950 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6951
7a905b14 6952 if ((mem->slot >= KVM_USER_MEM_SLOTS) && old.npages && !npages) {
f7784b8e
MT		 6953 int ret;
6954
bfce281c 6955 ret = vm_munmap(old.userspace_addr,
f7784b8e 6956 old.npages * PAGE_SIZE);
f7784b8e
MT		 6957 if (ret < 0)
6958 printk(KERN_WARNING
6959 "kvm_vm_ioctl_set_memory_region: "
6960 "failed to munmap memory\n");
6961 }
6962
48c0e4e9
XG		 6963 if (!kvm->arch.n_requested_mmu_pages)
6964 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6965
48c0e4e9 6966 if (nr_mmu_pages)
0de10343 6967 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 6968 /*
6969 * Write protect all pages for dirty logging.
6970 * Existing largepage mappings are destroyed here and new ones will
6971 * not be created until the end of the logging.
6972 */
9d1beefb 6973 if (npages && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 6974 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 6975 /*
6976 * If memory slot is created, or moved, we need to clear all
6977 * mmio sptes.
6978 */
6979 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6980 kvm_mmu_zap_all(kvm);
6981 kvm_reload_remote_mmus(kvm);
6982 }
0de10343 6983}
1d737c8a 6984
2df72e9b 6985void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6986{
6987 kvm_mmu_zap_all(kvm);
8986ecc0 6988 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6989}
6990
2df72e9b
MT		 6991void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6992 struct kvm_memory_slot *slot)
6993{
6994 kvm_arch_flush_shadow_all(kvm);
6995}
6996
1d737c8a
ZX		 6997int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6998{
af585b92
GN		 6999 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7000 !vcpu->arch.apf.halted)
7001 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 7002 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 7003 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7004 (kvm_arch_interrupt_allowed(vcpu) &&
7005 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7006}
5736199a 7007
b6d33834 7008int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7009{
b6d33834 7010 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7011}
78646121
GN		 7012
7013int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7014{
7015 return kvm_x86_ops->interrupt_allowed(vcpu);
7016}
229456fc 7017
f92653ee
JK		 7018bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7019{
7020 unsigned long current_rip = kvm_rip_read(vcpu) +
7021 get_segment_base(vcpu, VCPU_SREG_CS);
7022
7023 return current_rip == linear_rip;
7024}
7025EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7026
94fe45da
JK		 7027unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7028{
7029 unsigned long rflags;
7030
7031 rflags = kvm_x86_ops->get_rflags(vcpu);
7032 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7033 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7034 return rflags;
7035}
7036EXPORT_SYMBOL_GPL(kvm_get_rflags);
7037
7038void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7039{
7040 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7041 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7042 rflags |= X86_EFLAGS_TF;
94fe45da 7043 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7044 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7045}
7046EXPORT_SYMBOL_GPL(kvm_set_rflags);
7047
56028d08
GN		 7048void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7049{
7050 int r;
7051
fb67e14f 7052 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7053 is_error_page(work->page))
56028d08
GN		 7054 return;
7055
7056 r = kvm_mmu_reload(vcpu);
7057 if (unlikely(r))
7058 return;
7059
fb67e14f
XG		 7060 if (!vcpu->arch.mmu.direct_map &&
7061 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7062 return;
7063
56028d08
GN		 7064 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7065}
7066
af585b92
GN		 7067static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7068{
7069 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7070}
7071
7072static inline u32 kvm_async_pf_next_probe(u32 key)
7073{
7074 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7075}
7076
7077static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7078{
7079 u32 key = kvm_async_pf_hash_fn(gfn);
7080
7081 while (vcpu->arch.apf.gfns[key] != ~0)
7082 key = kvm_async_pf_next_probe(key);
7083
7084 vcpu->arch.apf.gfns[key] = gfn;
7085}
7086
7087static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7088{
7089 int i;
7090 u32 key = kvm_async_pf_hash_fn(gfn);
7091
7092 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7093 (vcpu->arch.apf.gfns[key] != gfn &&
7094 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7095 key = kvm_async_pf_next_probe(key);
7096
7097 return key;
7098}
7099
7100bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7101{
7102 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7103}
7104
7105static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7106{
7107 u32 i, j, k;
7108
7109 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7110 while (true) {
7111 vcpu->arch.apf.gfns[i] = ~0;
7112 do {
7113 j = kvm_async_pf_next_probe(j);
7114 if (vcpu->arch.apf.gfns[j] == ~0)
7115 return;
7116 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7117 /*
7118 * k lies cyclically in ]i,j]
7119 * | i.k.j |
7120 * |....j i.k.| or |.k..j i...|
7121 */
7122 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7123 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7124 i = j;
7125 }
7126}
7127
7c90705b
GN		 7128static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7129{
7130
7131 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7132 sizeof(val));
7133}
7134
af585b92
GN		 7135void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7136 struct kvm_async_pf *work)
7137{
6389ee94
AK		 7138 struct x86_exception fault;
7139
7c90705b 7140 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7141 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7142
7143 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7144 (vcpu->arch.apf.send_user_only &&
7145 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7146 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7147 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7148 fault.vector = PF_VECTOR;
7149 fault.error_code_valid = true;
7150 fault.error_code = 0;
7151 fault.nested_page_fault = false;
7152 fault.address = work->arch.token;
7153 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7154 }
af585b92
GN		 7155}
7156
7157void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7158 struct kvm_async_pf *work)
7159{
6389ee94
AK		 7160 struct x86_exception fault;
7161
7c90705b
GN		 7162 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7163 if (is_error_page(work->page))
7164 work->arch.token = ~0; /* broadcast wakeup */
7165 else
7166 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7167
7168 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7169 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7170 fault.vector = PF_VECTOR;
7171 fault.error_code_valid = true;
7172 fault.error_code = 0;
7173 fault.nested_page_fault = false;
7174 fault.address = work->arch.token;
7175 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7176 }
e6d53e3b 7177 vcpu->arch.apf.halted = false;
a4fa1635 7178 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7179}
7180
7181bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7182{
7183 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7184 return true;
7185 else
7186 return !kvm_event_needs_reinjection(vcpu) &&
7187 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7188}
7189
229456fc
MT		 7190EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7191EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7192EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7193EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7194EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7195EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7196EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7197EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7198EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7199EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7200EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7201EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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