projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: svm: unconditionally intercept #DB
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
2acf923e
DC		 676 if (!(xcr0 & XSTATE_FP))
677 return 1;
678 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
686 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
390bd528
LJ		 690 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
691 return 1;
692
612263b3
CP		 693 if (xcr0 & XSTATE_AVX512) {
694 if (!(xcr0 & XSTATE_YMM))
695 return 1;
696 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
697 return 1;
698 }
42bdf991 699 kvm_put_guest_xcr0(vcpu);
2acf923e 700 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 701
702 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
703 kvm_update_cpuid(vcpu);
2acf923e
DC		 704 return 0;
705}
706
707int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
708{
764bcbc5
Z		 709 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
710 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 711 kvm_inject_gp(vcpu, 0);
712 return 1;
713 }
714 return 0;
715}
716EXPORT_SYMBOL_GPL(kvm_set_xcr);
717
a83b29c6 718int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 719{
fc78f519 720 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 721 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
722 X86_CR4_SMEP | X86_CR4_SMAP;
723
0f12244f
GN		 724 if (cr4 & CR4_RESERVED_BITS)
725 return 1;
a03490ed 726
2acf923e
DC		 727 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
728 return 1;
729
c68b734f
YW		 730 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
731 return 1;
732
97ec8c06
FW		 733 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
734 return 1;
735
afcbf13f 736 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 737 return 1;
738
a03490ed 739 if (is_long_mode(vcpu)) {
0f12244f
GN		 740 if (!(cr4 & X86_CR4_PAE))
741 return 1;
a2edf57f
AK		 742 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
743 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 744 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
745 kvm_read_cr3(vcpu)))
0f12244f
GN		 746 return 1;
747
ad756a16
MJ		 748 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
749 if (!guest_cpuid_has_pcid(vcpu))
750 return 1;
751
752 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
753 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
754 return 1;
755 }
756
5e1746d6 757 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 758 return 1;
a03490ed 759
ad756a16
MJ		 760 if (((cr4 ^ old_cr4) & pdptr_bits) ||
761 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 762 kvm_mmu_reset_context(vcpu);
0f12244f 763
2acf923e 764 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 765 kvm_update_cpuid(vcpu);
2acf923e 766
0f12244f
GN		 767 return 0;
768}
2d3ad1f4 769EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 770
2390218b 771int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 772{
ac146235 773#ifdef CONFIG_X86_64
9d88fca7 774 cr3 &= ~CR3_PCID_INVD;
ac146235 775#endif
9d88fca7 776
9f8fe504 777 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 778 kvm_mmu_sync_roots(vcpu);
77c3913b 779 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 780 return 0;
d835dfec
AK		 781 }
782
a03490ed 783 if (is_long_mode(vcpu)) {
d9f89b88
JK		 784 if (cr3 & CR3_L_MODE_RESERVED_BITS)
785 return 1;
786 } else if (is_pae(vcpu) && is_paging(vcpu) &&
787 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 788 return 1;
a03490ed 789
0f12244f 790 vcpu->arch.cr3 = cr3;
aff48baa 791 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 792 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 796
eea1cff9 797int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 798{
0f12244f
GN		 799 if (cr8 & CR8_RESERVED_BITS)
800 return 1;
35754c98 801 if (lapic_in_kernel(vcpu))
a03490ed
CO		 802 kvm_lapic_set_tpr(vcpu, cr8);
803 else
ad312c7c 804 vcpu->arch.cr8 = cr8;
0f12244f
GN		 805 return 0;
806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 808
2d3ad1f4 809unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 810{
35754c98 811 if (lapic_in_kernel(vcpu))
a03490ed
CO		 812 return kvm_lapic_get_cr8(vcpu);
813 else
ad312c7c 814 return vcpu->arch.cr8;
a03490ed 815}
2d3ad1f4 816EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 817
ae561ede
NA		 818static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
819{
820 int i;
821
822 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
823 for (i = 0; i < KVM_NR_DB_REGS; i++)
824 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
825 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
826 }
827}
828
73aaf249
JK		 829static void kvm_update_dr6(struct kvm_vcpu *vcpu)
830{
831 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
832 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
833}
834
c8639010
JK		 835static void kvm_update_dr7(struct kvm_vcpu *vcpu)
836{
837 unsigned long dr7;
838
839 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
840 dr7 = vcpu->arch.guest_debug_dr7;
841 else
842 dr7 = vcpu->arch.dr7;
843 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 844 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
845 if (dr7 & DR7_BP_EN_MASK)
846 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 847}
848
6f43ed01
NA		 849static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
850{
851 u64 fixed = DR6_FIXED_1;
852
853 if (!guest_cpuid_has_rtm(vcpu))
854 fixed |= DR6_RTM;
855 return fixed;
856}
857
338dbc97 858static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 859{
860 switch (dr) {
861 case 0 ... 3:
862 vcpu->arch.db[dr] = val;
863 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
864 vcpu->arch.eff_db[dr] = val;
865 break;
866 case 4:
020df079
GN		 867 /* fall through */
868 case 6:
338dbc97
GN		 869 if (val & 0xffffffff00000000ULL)
870 return -1; /* #GP */
6f43ed01 871 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 872 kvm_update_dr6(vcpu);
020df079
GN		 873 break;
874 case 5:
020df079
GN		 875 /* fall through */
876 default: /* 7 */
338dbc97
GN		 877 if (val & 0xffffffff00000000ULL)
878 return -1; /* #GP */
020df079 879 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 880 kvm_update_dr7(vcpu);
020df079
GN		 881 break;
882 }
883
884 return 0;
885}
338dbc97
GN		 886
887int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
888{
16f8a6f9 889 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 890 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 891 return 1;
892 }
893 return 0;
338dbc97 894}
020df079
GN		 895EXPORT_SYMBOL_GPL(kvm_set_dr);
896
16f8a6f9 897int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 898{
899 switch (dr) {
900 case 0 ... 3:
901 *val = vcpu->arch.db[dr];
902 break;
903 case 4:
020df079
GN		 904 /* fall through */
905 case 6:
73aaf249
JK		 906 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
907 *val = vcpu->arch.dr6;
908 else
909 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 910 break;
911 case 5:
020df079
GN		 912 /* fall through */
913 default: /* 7 */
914 *val = vcpu->arch.dr7;
915 break;
916 }
338dbc97
GN		 917 return 0;
918}
020df079
GN		 919EXPORT_SYMBOL_GPL(kvm_get_dr);
920
022cd0e8
AK		 921bool kvm_rdpmc(struct kvm_vcpu *vcpu)
922{
923 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
924 u64 data;
925 int err;
926
c6702c9d 927 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 928 if (err)
929 return err;
930 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
931 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
932 return err;
933}
934EXPORT_SYMBOL_GPL(kvm_rdpmc);
935
043405e1
CO		 936/*
937 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
938 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
939 *
940 * This list is modified at module load time to reflect the
e3267cbb 941 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 942 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
943 * may depend on host virtualization features rather than host cpu features.
043405e1 944 */
e3267cbb 945
043405e1
CO		 946static u32 msrs_to_save[] = {
947 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 948 MSR_STAR,
043405e1
CO		 949#ifdef CONFIG_X86_64
950 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
951#endif
b3897a49 952 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 953 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 954};
955
956static unsigned num_msrs_to_save;
957
62ef68bb
PB		 958static u32 emulated_msrs[] = {
959 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
960 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
961 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
962 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 963 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
964 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 965 HV_X64_MSR_RESET,
11c4b1ca 966 HV_X64_MSR_VP_INDEX,
9eec50b8 967 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 968 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
969 MSR_KVM_PV_EOI_EN,
970
ba904635 971 MSR_IA32_TSC_ADJUST,
a3e06bbe 972 MSR_IA32_TSCDEADLINE,
043405e1 973 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 974 MSR_IA32_MCG_STATUS,
975 MSR_IA32_MCG_CTL,
64d60670 976 MSR_IA32_SMBASE,
043405e1
CO		 977};
978
62ef68bb
PB		 979static unsigned num_emulated_msrs;
980
384bb783 981bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 982{
b69e8cae 983 if (efer & efer_reserved_bits)
384bb783 984 return false;
15c4a640 985
1b2fd70c
AG		 986 if (efer & EFER_FFXSR) {
987 struct kvm_cpuid_entry2 *feat;
988
989 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 990 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 991 return false;
1b2fd70c
AG		 992 }
993
d8017474
AG		 994 if (efer & EFER_SVME) {
995 struct kvm_cpuid_entry2 *feat;
996
997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 998 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 999 return false;
d8017474
AG		 1000 }
1001
384bb783
JK		 1002 return true;
1003}
1004EXPORT_SYMBOL_GPL(kvm_valid_efer);
1005
1006static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1007{
1008 u64 old_efer = vcpu->arch.efer;
1009
1010 if (!kvm_valid_efer(vcpu, efer))
1011 return 1;
1012
1013 if (is_paging(vcpu)
1014 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1015 return 1;
1016
15c4a640 1017 efer &= ~EFER_LMA;
f6801dff 1018 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1019
a3d204e2
SY		 1020 kvm_x86_ops->set_efer(vcpu, efer);
1021
aad82703
SY		 1022 /* Update reserved bits */
1023 if ((efer ^ old_efer) & EFER_NX)
1024 kvm_mmu_reset_context(vcpu);
1025
b69e8cae 1026 return 0;
15c4a640
CO		 1027}
1028
f2b4b7dd
JR		 1029void kvm_enable_efer_bits(u64 mask)
1030{
1031 efer_reserved_bits &= ~mask;
1032}
1033EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1034
15c4a640
CO		 1035/*
1036 * Writes msr value into into the appropriate "register".
1037 * Returns 0 on success, non-0 otherwise.
1038 * Assumes vcpu_load() was already called.
1039 */
8fe8ab46 1040int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1041{
854e8bb1
NA		 1042 switch (msr->index) {
1043 case MSR_FS_BASE:
1044 case MSR_GS_BASE:
1045 case MSR_KERNEL_GS_BASE:
1046 case MSR_CSTAR:
1047 case MSR_LSTAR:
1048 if (is_noncanonical_address(msr->data))
1049 return 1;
1050 break;
1051 case MSR_IA32_SYSENTER_EIP:
1052 case MSR_IA32_SYSENTER_ESP:
1053 /*
1054 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1055 * non-canonical address is written on Intel but not on
1056 * AMD (which ignores the top 32-bits, because it does
1057 * not implement 64-bit SYSENTER).
1058 *
1059 * 64-bit code should hence be able to write a non-canonical
1060 * value on AMD. Making the address canonical ensures that
1061 * vmentry does not fail on Intel after writing a non-canonical
1062 * value, and that something deterministic happens if the guest
1063 * invokes 64-bit SYSENTER.
1064 */
1065 msr->data = get_canonical(msr->data);
1066 }
8fe8ab46 1067 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1068}
854e8bb1 1069EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1070
313a3dc7
CO		 1071/*
1072 * Adapt set_msr() to msr_io()'s calling convention
1073 */
609e36d3
PB		 1074static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1075{
1076 struct msr_data msr;
1077 int r;
1078
1079 msr.index = index;
1080 msr.host_initiated = true;
1081 r = kvm_get_msr(vcpu, &msr);
1082 if (r)
1083 return r;
1084
1085 *data = msr.data;
1086 return 0;
1087}
1088
313a3dc7
CO		 1089static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1090{
8fe8ab46
WA		 1091 struct msr_data msr;
1092
1093 msr.data = *data;
1094 msr.index = index;
1095 msr.host_initiated = true;
1096 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1097}
1098
16e8d74d
MT		 1099#ifdef CONFIG_X86_64
1100struct pvclock_gtod_data {
1101 seqcount_t seq;
1102
1103 struct { /* extract of a clocksource struct */
1104 int vclock_mode;
1105 cycle_t cycle_last;
1106 cycle_t mask;
1107 u32 mult;
1108 u32 shift;
1109 } clock;
1110
cbcf2dd3
TG		 1111 u64 boot_ns;
1112 u64 nsec_base;
16e8d74d
MT		 1113};
1114
1115static struct pvclock_gtod_data pvclock_gtod_data;
1116
1117static void update_pvclock_gtod(struct timekeeper *tk)
1118{
1119 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1120 u64 boot_ns;
1121
876e7881 1122 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1123
1124 write_seqcount_begin(&vdata->seq);
1125
1126 /* copy pvclock gtod data */
876e7881
PZ		 1127 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1128 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1129 vdata->clock.mask = tk->tkr_mono.mask;
1130 vdata->clock.mult = tk->tkr_mono.mult;
1131 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1132
cbcf2dd3 1133 vdata->boot_ns = boot_ns;
876e7881 1134 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1135
1136 write_seqcount_end(&vdata->seq);
1137}
1138#endif
1139
bab5bb39
NK		 1140void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1141{
1142 /*
1143 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1144 * vcpu_enter_guest. This function is only called from
1145 * the physical CPU that is running vcpu.
1146 */
1147 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1148}
16e8d74d 1149
18068523
GOC		 1150static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1151{
9ed3c444
AK		 1152 int version;
1153 int r;
50d0a0f9 1154 struct pvclock_wall_clock wc;
923de3cf 1155 struct timespec boot;
18068523
GOC		 1156
1157 if (!wall_clock)
1158 return;
1159
9ed3c444
AK		 1160 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1161 if (r)
1162 return;
1163
1164 if (version & 1)
1165 ++version; /* first time write, random junk */
1166
1167 ++version;
18068523 1168
18068523
GOC		 1169 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1170
50d0a0f9
GH		 1171 /*
1172 * The guest calculates current wall clock time by adding
34c238a1 1173 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1174 * wall clock specified here. guest system time equals host
1175 * system time for us, thus we must fill in host boot time here.
1176 */
923de3cf 1177 getboottime(&boot);
50d0a0f9 1178
4b648665
BR		 1179 if (kvm->arch.kvmclock_offset) {
1180 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1181 boot = timespec_sub(boot, ts);
1182 }
50d0a0f9
GH		 1183 wc.sec = boot.tv_sec;
1184 wc.nsec = boot.tv_nsec;
1185 wc.version = version;
18068523
GOC		 1186
1187 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1188
1189 version++;
1190 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1191}
1192
50d0a0f9
GH		 1193static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1194{
1195 uint32_t quotient, remainder;
1196
1197 /* Don't try to replace with do_div(), this one calculates
1198 * "(dividend << 32) / divisor" */
1199 __asm__ ( "divl %4"
1200 : "=a" (quotient), "=d" (remainder)
1201 : "0" (0), "1" (dividend), "r" (divisor) );
1202 return quotient;
1203}
1204
5f4e3f88
ZA		 1205static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1206 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1207{
5f4e3f88 1208 uint64_t scaled64;
50d0a0f9
GH		 1209 int32_t shift = 0;
1210 uint64_t tps64;
1211 uint32_t tps32;
1212
5f4e3f88
ZA		 1213 tps64 = base_khz * 1000LL;
1214 scaled64 = scaled_khz * 1000LL;
50933623 1215 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1216 tps64 >>= 1;
1217 shift--;
1218 }
1219
1220 tps32 = (uint32_t)tps64;
50933623
JK		 1221 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1222 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1223 scaled64 >>= 1;
1224 else
1225 tps32 <<= 1;
50d0a0f9
GH		 1226 shift++;
1227 }
1228
5f4e3f88
ZA		 1229 *pshift = shift;
1230 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1231
5f4e3f88
ZA		 1232 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1233 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1234}
1235
d828199e 1236#ifdef CONFIG_X86_64
16e8d74d 1237static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1238#endif
16e8d74d 1239
c8076604 1240static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1241static unsigned long max_tsc_khz;
c8076604 1242
cc578287 1243static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1244{
cc578287
ZA		 1245 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1246 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1247}
1248
cc578287 1249static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1250{
cc578287
ZA		 1251 u64 v = (u64)khz * (1000000 + ppm);
1252 do_div(v, 1000000);
1253 return v;
1e993611
JR		 1254}
1255
381d585c
HZ		 1256static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1257{
1258 u64 ratio;
1259
1260 /* Guest TSC same frequency as host TSC? */
1261 if (!scale) {
1262 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1263 return 0;
1264 }
1265
1266 /* TSC scaling supported? */
1267 if (!kvm_has_tsc_control) {
1268 if (user_tsc_khz > tsc_khz) {
1269 vcpu->arch.tsc_catchup = 1;
1270 vcpu->arch.tsc_always_catchup = 1;
1271 return 0;
1272 } else {
1273 WARN(1, "user requested TSC rate below hardware speed\n");
1274 return -1;
1275 }
1276 }
1277
1278 /* TSC scaling required - calculate ratio */
1279 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1280 user_tsc_khz, tsc_khz);
1281
1282 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1283 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1284 user_tsc_khz);
1285 return -1;
1286 }
1287
1288 vcpu->arch.tsc_scaling_ratio = ratio;
1289 return 0;
1290}
1291
1292static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1293{
cc578287
ZA		 1294 u32 thresh_lo, thresh_hi;
1295 int use_scaling = 0;
217fc9cf 1296
03ba32ca 1297 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1298 if (this_tsc_khz == 0) {
1299 /* set tsc_scaling_ratio to a safe value */
1300 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1301 return -1;
ad721883 1302 }
03ba32ca 1303
c285545f
ZA		 1304 /* Compute a scale to convert nanoseconds in TSC cycles */
1305 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1306 &vcpu->arch.virtual_tsc_shift,
1307 &vcpu->arch.virtual_tsc_mult);
1308 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1309
1310 /*
1311 * Compute the variation in TSC rate which is acceptable
1312 * within the range of tolerance and decide if the
1313 * rate being applied is within that bounds of the hardware
1314 * rate. If so, no scaling or compensation need be done.
1315 */
1316 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1317 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1318 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1319 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1320 use_scaling = 1;
1321 }
381d585c 1322 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1323}
1324
1325static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1326{
e26101b1 1327 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1328 vcpu->arch.virtual_tsc_mult,
1329 vcpu->arch.virtual_tsc_shift);
e26101b1 1330 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1331 return tsc;
1332}
1333
69b0049a 1334static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1335{
1336#ifdef CONFIG_X86_64
1337 bool vcpus_matched;
b48aa97e
MT		 1338 struct kvm_arch *ka = &vcpu->kvm->arch;
1339 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1340
1341 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1342 atomic_read(&vcpu->kvm->online_vcpus));
1343
7f187922
MT		 1344 /*
1345 * Once the masterclock is enabled, always perform request in
1346 * order to update it.
1347 *
1348 * In order to enable masterclock, the host clocksource must be TSC
1349 * and the vcpus need to have matched TSCs. When that happens,
1350 * perform request to enable masterclock.
1351 */
1352 if (ka->use_master_clock ||
1353 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1354 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1355
1356 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1357 atomic_read(&vcpu->kvm->online_vcpus),
1358 ka->use_master_clock, gtod->clock.vclock_mode);
1359#endif
1360}
1361
ba904635
WA		 1362static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1363{
1364 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1365 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1366}
1367
35181e86
HZ		 1368/*
1369 * Multiply tsc by a fixed point number represented by ratio.
1370 *
1371 * The most significant 64-N bits (mult) of ratio represent the
1372 * integral part of the fixed point number; the remaining N bits
1373 * (frac) represent the fractional part, ie. ratio represents a fixed
1374 * point number (mult + frac * 2^(-N)).
1375 *
1376 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1377 */
1378static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1379{
1380 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1381}
1382
1383u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1384{
1385 u64 _tsc = tsc;
1386 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1387
1388 if (ratio != kvm_default_tsc_scaling_ratio)
1389 _tsc = __scale_tsc(ratio, tsc);
1390
1391 return _tsc;
1392}
1393EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1394
07c1419a
HZ		 1395static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1396{
1397 u64 tsc;
1398
1399 tsc = kvm_scale_tsc(vcpu, rdtsc());
1400
1401 return target_tsc - tsc;
1402}
1403
4ba76538
HZ		 1404u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1405{
1406 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1407}
1408EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1409
8fe8ab46 1410void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1411{
1412 struct kvm *kvm = vcpu->kvm;
f38e098f 1413 u64 offset, ns, elapsed;
99e3e30a 1414 unsigned long flags;
02626b6a 1415 s64 usdiff;
b48aa97e 1416 bool matched;
0d3da0d2 1417 bool already_matched;
8fe8ab46 1418 u64 data = msr->data;
99e3e30a 1419
038f8c11 1420 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1421 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1422 ns = get_kernel_ns();
f38e098f 1423 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1424
03ba32ca 1425 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1426 int faulted = 0;
1427
03ba32ca
MT		 1428 /* n.b - signed multiplication and division required */
1429 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1430#ifdef CONFIG_X86_64
03ba32ca 1431 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1432#else
03ba32ca 1433 /* do_div() only does unsigned */
8915aa27
MT		 1434 asm("1: idivl %[divisor]\n"
1435 "2: xor %%edx, %%edx\n"
1436 " movl $0, %[faulted]\n"
1437 "3:\n"
1438 ".section .fixup,\"ax\"\n"
1439 "4: movl $1, %[faulted]\n"
1440 " jmp 3b\n"
1441 ".previous\n"
1442
1443 _ASM_EXTABLE(1b, 4b)
1444
1445 : "=A"(usdiff), [faulted] "=r" (faulted)
1446 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1447
5d3cb0f6 1448#endif
03ba32ca
MT		 1449 do_div(elapsed, 1000);
1450 usdiff -= elapsed;
1451 if (usdiff < 0)
1452 usdiff = -usdiff;
8915aa27
MT		 1453
1454 /* idivl overflow => difference is larger than USEC_PER_SEC */
1455 if (faulted)
1456 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1457 } else
1458 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1459
1460 /*
5d3cb0f6
ZA		 1461 * Special case: TSC write with a small delta (1 second) of virtual
1462 * cycle time against real time is interpreted as an attempt to
1463 * synchronize the CPU.
1464 *
1465 * For a reliable TSC, we can match TSC offsets, and for an unstable
1466 * TSC, we add elapsed time in this computation. We could let the
1467 * compensation code attempt to catch up if we fall behind, but
1468 * it's better to try to match offsets from the beginning.
1469 */
02626b6a 1470 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1471 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1472 if (!check_tsc_unstable()) {
e26101b1 1473 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1474 pr_debug("kvm: matched tsc offset for %llu\n", data);
1475 } else {
857e4099 1476 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1477 data += delta;
07c1419a 1478 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1479 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1480 }
b48aa97e 1481 matched = true;
0d3da0d2 1482 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1483 } else {
1484 /*
1485 * We split periods of matched TSC writes into generations.
1486 * For each generation, we track the original measured
1487 * nanosecond time, offset, and write, so if TSCs are in
1488 * sync, we can match exact offset, and if not, we can match
4a969980 1489 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1490 *
1491 * These values are tracked in kvm->arch.cur_xxx variables.
1492 */
1493 kvm->arch.cur_tsc_generation++;
1494 kvm->arch.cur_tsc_nsec = ns;
1495 kvm->arch.cur_tsc_write = data;
1496 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1497 matched = false;
0d3da0d2 1498 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1499 kvm->arch.cur_tsc_generation, data);
f38e098f 1500 }
e26101b1
ZA		 1501
1502 /*
1503 * We also track th most recent recorded KHZ, write and time to
1504 * allow the matching interval to be extended at each write.
1505 */
f38e098f
ZA		 1506 kvm->arch.last_tsc_nsec = ns;
1507 kvm->arch.last_tsc_write = data;
5d3cb0f6 1508 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1509
b183aa58 1510 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1511
1512 /* Keep track of which generation this VCPU has synchronized to */
1513 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1514 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1515 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1516
ba904635
WA		 1517 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1518 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1519 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1520 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1521
1522 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1523 if (!matched) {
b48aa97e 1524 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1525 } else if (!already_matched) {
1526 kvm->arch.nr_vcpus_matched_tsc++;
1527 }
b48aa97e
MT		 1528
1529 kvm_track_tsc_matching(vcpu);
1530 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1531}
e26101b1 1532
99e3e30a
ZA		 1533EXPORT_SYMBOL_GPL(kvm_write_tsc);
1534
58ea6767
HZ		 1535static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1536 s64 adjustment)
1537{
1538 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1539}
1540
1541static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1542{
1543 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1544 WARN_ON(adjustment < 0);
1545 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1546 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1547}
1548
d828199e
MT		 1549#ifdef CONFIG_X86_64
1550
1551static cycle_t read_tsc(void)
1552{
03b9730b
AL		 1553 cycle_t ret = (cycle_t)rdtsc_ordered();
1554 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1555
1556 if (likely(ret >= last))
1557 return ret;
1558
1559 /*
1560 * GCC likes to generate cmov here, but this branch is extremely
1561 * predictable (it's just a funciton of time and the likely is
1562 * very likely) and there's a data dependence, so force GCC
1563 * to generate a branch instead. I don't barrier() because
1564 * we don't actually need a barrier, and if this function
1565 * ever gets inlined it will generate worse code.
1566 */
1567 asm volatile ("");
1568 return last;
1569}
1570
1571static inline u64 vgettsc(cycle_t *cycle_now)
1572{
1573 long v;
1574 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1575
1576 *cycle_now = read_tsc();
1577
1578 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1579 return v * gtod->clock.mult;
1580}
1581
cbcf2dd3 1582static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1583{
cbcf2dd3 1584 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1585 unsigned long seq;
d828199e 1586 int mode;
cbcf2dd3 1587 u64 ns;
d828199e 1588
d828199e
MT		 1589 do {
1590 seq = read_seqcount_begin(&gtod->seq);
1591 mode = gtod->clock.vclock_mode;
cbcf2dd3 1592 ns = gtod->nsec_base;
d828199e
MT		 1593 ns += vgettsc(cycle_now);
1594 ns >>= gtod->clock.shift;
cbcf2dd3 1595 ns += gtod->boot_ns;
d828199e 1596 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1597 *t = ns;
d828199e
MT		 1598
1599 return mode;
1600}
1601
1602/* returns true if host is using tsc clocksource */
1603static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1604{
d828199e
MT		 1605 /* checked again under seqlock below */
1606 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1607 return false;
1608
cbcf2dd3 1609 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1610}
1611#endif
1612
1613/*
1614 *
b48aa97e
MT		 1615 * Assuming a stable TSC across physical CPUS, and a stable TSC
1616 * across virtual CPUs, the following condition is possible.
1617 * Each numbered line represents an event visible to both
d828199e
MT		 1618 * CPUs at the next numbered event.
1619 *
1620 * "timespecX" represents host monotonic time. "tscX" represents
1621 * RDTSC value.
1622 *
1623 * VCPU0 on CPU0 | VCPU1 on CPU1
1624 *
1625 * 1. read timespec0,tsc0
1626 * 2. | timespec1 = timespec0 + N
1627 * | tsc1 = tsc0 + M
1628 * 3. transition to guest | transition to guest
1629 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1630 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1631 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1632 *
1633 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1634 *
1635 * - ret0 < ret1
1636 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1637 * ...
1638 * - 0 < N - M => M < N
1639 *
1640 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1641 * always the case (the difference between two distinct xtime instances
1642 * might be smaller then the difference between corresponding TSC reads,
1643 * when updating guest vcpus pvclock areas).
1644 *
1645 * To avoid that problem, do not allow visibility of distinct
1646 * system_timestamp/tsc_timestamp values simultaneously: use a master
1647 * copy of host monotonic time values. Update that master copy
1648 * in lockstep.
1649 *
b48aa97e 1650 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1651 *
1652 */
1653
1654static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1655{
1656#ifdef CONFIG_X86_64
1657 struct kvm_arch *ka = &kvm->arch;
1658 int vclock_mode;
b48aa97e
MT		 1659 bool host_tsc_clocksource, vcpus_matched;
1660
1661 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1662 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1663
1664 /*
1665 * If the host uses TSC clock, then passthrough TSC as stable
1666 * to the guest.
1667 */
b48aa97e 1668 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1669 &ka->master_kernel_ns,
1670 &ka->master_cycle_now);
1671
16a96021 1672 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1673 && !backwards_tsc_observed
1674 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1675
d828199e
MT		 1676 if (ka->use_master_clock)
1677 atomic_set(&kvm_guest_has_master_clock, 1);
1678
1679 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1680 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1681 vcpus_matched);
d828199e
MT		 1682#endif
1683}
1684
2e762ff7
MT		 1685static void kvm_gen_update_masterclock(struct kvm *kvm)
1686{
1687#ifdef CONFIG_X86_64
1688 int i;
1689 struct kvm_vcpu *vcpu;
1690 struct kvm_arch *ka = &kvm->arch;
1691
1692 spin_lock(&ka->pvclock_gtod_sync_lock);
1693 kvm_make_mclock_inprogress_request(kvm);
1694 /* no guest entries from this point */
1695 pvclock_update_vm_gtod_copy(kvm);
1696
1697 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1698 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1699
1700 /* guest entries allowed */
1701 kvm_for_each_vcpu(i, vcpu, kvm)
1702 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1703
1704 spin_unlock(&ka->pvclock_gtod_sync_lock);
1705#endif
1706}
1707
34c238a1 1708static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1709{
27cca94e 1710 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1711 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1712 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1713 s64 kernel_ns;
d828199e 1714 u64 tsc_timestamp, host_tsc;
0b79459b 1715 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1716 u8 pvclock_flags;
d828199e
MT		 1717 bool use_master_clock;
1718
1719 kernel_ns = 0;
1720 host_tsc = 0;
18068523 1721
d828199e
MT		 1722 /*
1723 * If the host uses TSC clock, then passthrough TSC as stable
1724 * to the guest.
1725 */
1726 spin_lock(&ka->pvclock_gtod_sync_lock);
1727 use_master_clock = ka->use_master_clock;
1728 if (use_master_clock) {
1729 host_tsc = ka->master_cycle_now;
1730 kernel_ns = ka->master_kernel_ns;
1731 }
1732 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1733
1734 /* Keep irq disabled to prevent changes to the clock */
1735 local_irq_save(flags);
89cbc767 1736 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1737 if (unlikely(this_tsc_khz == 0)) {
1738 local_irq_restore(flags);
1739 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1740 return 1;
1741 }
d828199e 1742 if (!use_master_clock) {
4ea1636b 1743 host_tsc = rdtsc();
d828199e
MT		 1744 kernel_ns = get_kernel_ns();
1745 }
1746
4ba76538 1747 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1748
c285545f
ZA		 1749 /*
1750 * We may have to catch up the TSC to match elapsed wall clock
1751 * time for two reasons, even if kvmclock is used.
1752 * 1) CPU could have been running below the maximum TSC rate
1753 * 2) Broken TSC compensation resets the base at each VCPU
1754 * entry to avoid unknown leaps of TSC even when running
1755 * again on the same CPU. This may cause apparent elapsed
1756 * time to disappear, and the guest to stand still or run
1757 * very slowly.
1758 */
1759 if (vcpu->tsc_catchup) {
1760 u64 tsc = compute_guest_tsc(v, kernel_ns);
1761 if (tsc > tsc_timestamp) {
f1e2b260 1762 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1763 tsc_timestamp = tsc;
1764 }
50d0a0f9
GH		 1765 }
1766
18068523
GOC		 1767 local_irq_restore(flags);
1768
0b79459b 1769 if (!vcpu->pv_time_enabled)
c285545f 1770 return 0;
18068523 1771
e48672fa 1772 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1773 tgt_tsc_khz = kvm_has_tsc_control ?
1774 vcpu->virtual_tsc_khz : this_tsc_khz;
1775 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1776 &vcpu->hv_clock.tsc_shift,
1777 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1778 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1779 }
1780
1781 /* With all the info we got, fill in the values */
1d5f066e 1782 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1783 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1784 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1785
09a0c3f1
OH		 1786 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1787 &guest_hv_clock, sizeof(guest_hv_clock))))
1788 return 0;
1789
5dca0d91
RK		 1790 /* This VCPU is paused, but it's legal for a guest to read another
1791 * VCPU's kvmclock, so we really have to follow the specification where
1792 * it says that version is odd if data is being modified, and even after
1793 * it is consistent.
1794 *
1795 * Version field updates must be kept separate. This is because
1796 * kvm_write_guest_cached might use a "rep movs" instruction, and
1797 * writes within a string instruction are weakly ordered. So there
1798 * are three writes overall.
1799 *
1800 * As a small optimization, only write the version field in the first
1801 * and third write. The vcpu->pv_time cache is still valid, because the
1802 * version field is the first in the struct.
18068523 1803 */
5dca0d91
RK		 1804 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1805
1806 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1807 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1808 &vcpu->hv_clock,
1809 sizeof(vcpu->hv_clock.version));
1810
1811 smp_wmb();
78c0337a
MT		 1812
1813 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1814 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1815
1816 if (vcpu->pvclock_set_guest_stopped_request) {
1817 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1818 vcpu->pvclock_set_guest_stopped_request = false;
1819 }
1820
d828199e
MT		 1821 /* If the host uses TSC clocksource, then it is stable */
1822 if (use_master_clock)
1823 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1824
78c0337a
MT		 1825 vcpu->hv_clock.flags = pvclock_flags;
1826
ce1a5e60
DM		 1827 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1828
0b79459b
AH		 1829 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1830 &vcpu->hv_clock,
1831 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1832
1833 smp_wmb();
1834
1835 vcpu->hv_clock.version++;
1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock.version));
8cfdc000 1839 return 0;
c8076604
GH		 1840}
1841
0061d53d
MT		 1842/*
1843 * kvmclock updates which are isolated to a given vcpu, such as
1844 * vcpu->cpu migration, should not allow system_timestamp from
1845 * the rest of the vcpus to remain static. Otherwise ntp frequency
1846 * correction applies to one vcpu's system_timestamp but not
1847 * the others.
1848 *
1849 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1850 * We need to rate-limit these requests though, as they can
1851 * considerably slow guests that have a large number of vcpus.
1852 * The time for a remote vcpu to update its kvmclock is bound
1853 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1854 */
1855
7e44e449
AJ		 1856#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1857
1858static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1859{
1860 int i;
7e44e449
AJ		 1861 struct delayed_work *dwork = to_delayed_work(work);
1862 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1863 kvmclock_update_work);
1864 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1865 struct kvm_vcpu *vcpu;
1866
1867 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1868 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1869 kvm_vcpu_kick(vcpu);
1870 }
1871}
1872
7e44e449
AJ		 1873static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1874{
1875 struct kvm *kvm = v->kvm;
1876
105b21bb 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1878 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1879 KVMCLOCK_UPDATE_DELAY);
1880}
1881
332967a3
AJ		 1882#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1883
1884static void kvmclock_sync_fn(struct work_struct *work)
1885{
1886 struct delayed_work *dwork = to_delayed_work(work);
1887 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1888 kvmclock_sync_work);
1889 struct kvm *kvm = container_of(ka, struct kvm, arch);
1890
630994b3
MT		 1891 if (!kvmclock_periodic_sync)
1892 return;
1893
332967a3
AJ		 1894 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1895 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1896 KVMCLOCK_SYNC_PERIOD);
1897}
1898
890ca9ae 1899static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1900{
890ca9ae
HY		 1901 u64 mcg_cap = vcpu->arch.mcg_cap;
1902 unsigned bank_num = mcg_cap & 0xff;
1903
15c4a640 1904 switch (msr) {
15c4a640 1905 case MSR_IA32_MCG_STATUS:
890ca9ae 1906 vcpu->arch.mcg_status = data;
15c4a640 1907 break;
c7ac679c 1908 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1909 if (!(mcg_cap & MCG_CTL_P))
1910 return 1;
1911 if (data != 0 && data != ~(u64)0)
1912 return -1;
1913 vcpu->arch.mcg_ctl = data;
1914 break;
1915 default:
1916 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1917 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1918 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1919 /* only 0 or all 1s can be written to IA32_MCi_CTL
1920 * some Linux kernels though clear bit 10 in bank 4 to
1921 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1922 * this to avoid an uncatched #GP in the guest
1923 */
890ca9ae 1924 if ((offset & 0x3) == 0 &&
114be429 1925 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1926 return -1;
1927 vcpu->arch.mce_banks[offset] = data;
1928 break;
1929 }
1930 return 1;
1931 }
1932 return 0;
1933}
1934
ffde22ac
ES		 1935static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1936{
1937 struct kvm *kvm = vcpu->kvm;
1938 int lm = is_long_mode(vcpu);
1939 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1940 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1941 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1942 : kvm->arch.xen_hvm_config.blob_size_32;
1943 u32 page_num = data & ~PAGE_MASK;
1944 u64 page_addr = data & PAGE_MASK;
1945 u8 *page;
1946 int r;
1947
1948 r = -E2BIG;
1949 if (page_num >= blob_size)
1950 goto out;
1951 r = -ENOMEM;
ff5c2c03
SL		 1952 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1953 if (IS_ERR(page)) {
1954 r = PTR_ERR(page);
ffde22ac 1955 goto out;
ff5c2c03 1956 }
54bf36aa 1957 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1958 goto out_free;
1959 r = 0;
1960out_free:
1961 kfree(page);
1962out:
1963 return r;
1964}
1965
344d9588
GN		 1966static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1967{
1968 gpa_t gpa = data & ~0x3f;
1969
4a969980 1970 /* Bits 2:5 are reserved, Should be zero */
6adba527 1971 if (data & 0x3c)
344d9588
GN		 1972 return 1;
1973
1974 vcpu->arch.apf.msr_val = data;
1975
1976 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1977 kvm_clear_async_pf_completion_queue(vcpu);
1978 kvm_async_pf_hash_reset(vcpu);
1979 return 0;
1980 }
1981
8f964525
AH		 1982 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1983 sizeof(u32)))
344d9588
GN		 1984 return 1;
1985
6adba527 1986 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1987 kvm_async_pf_wakeup_all(vcpu);
1988 return 0;
1989}
1990
12f9a48f
GC		 1991static void kvmclock_reset(struct kvm_vcpu *vcpu)
1992{
0b79459b 1993 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1994}
1995
c9aaa895
GC		 1996static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1997{
1998 u64 delta;
1999
2000 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2001 return;
2002
2003 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2004 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2005 vcpu->arch.st.accum_steal = delta;
2006}
2007
2008static void record_steal_time(struct kvm_vcpu *vcpu)
2009{
7cae2bed
MT		 2010 accumulate_steal_time(vcpu);
2011
c9aaa895
GC		 2012 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2013 return;
2014
2015 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2016 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2017 return;
2018
2019 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2020 vcpu->arch.st.steal.version += 2;
2021 vcpu->arch.st.accum_steal = 0;
2022
2023 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2024 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2025}
2026
8fe8ab46 2027int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2028{
5753785f 2029 bool pr = false;
8fe8ab46
WA		 2030 u32 msr = msr_info->index;
2031 u64 data = msr_info->data;
5753785f 2032
15c4a640 2033 switch (msr) {
2e32b719
BP		 2034 case MSR_AMD64_NB_CFG:
2035 case MSR_IA32_UCODE_REV:
2036 case MSR_IA32_UCODE_WRITE:
2037 case MSR_VM_HSAVE_PA:
2038 case MSR_AMD64_PATCH_LOADER:
2039 case MSR_AMD64_BU_CFG2:
2040 break;
2041
15c4a640 2042 case MSR_EFER:
b69e8cae 2043 return set_efer(vcpu, data);
8f1589d9
AP		 2044 case MSR_K7_HWCR:
2045 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2046 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2047 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2048 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2049 if (data != 0) {
a737f256
CD		 2050 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2051 data);
8f1589d9
AP		 2052 return 1;
2053 }
15c4a640 2054 break;
f7c6d140
AP		 2055 case MSR_FAM10H_MMIO_CONF_BASE:
2056 if (data != 0) {
a737f256
CD		 2057 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2058 "0x%llx\n", data);
f7c6d140
AP		 2059 return 1;
2060 }
15c4a640 2061 break;
b5e2fec0
AG		 2062 case MSR_IA32_DEBUGCTLMSR:
2063 if (!data) {
2064 /* We support the non-activated case already */
2065 break;
2066 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2067 /* Values other than LBR and BTF are vendor-specific,
2068 thus reserved and should throw a #GP */
2069 return 1;
2070 }
a737f256
CD		 2071 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2072 __func__, data);
b5e2fec0 2073 break;
9ba075a6 2074 case 0x200 ... 0x2ff:
ff53604b 2075 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2076 case MSR_IA32_APICBASE:
58cb628d 2077 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2078 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2079 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2080 case MSR_IA32_TSCDEADLINE:
2081 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2082 break;
ba904635
WA		 2083 case MSR_IA32_TSC_ADJUST:
2084 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2085 if (!msr_info->host_initiated) {
d913b904 2086 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2087 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2088 }
2089 vcpu->arch.ia32_tsc_adjust_msr = data;
2090 }
2091 break;
15c4a640 2092 case MSR_IA32_MISC_ENABLE:
ad312c7c 2093 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2094 break;
64d60670
PB		 2095 case MSR_IA32_SMBASE:
2096 if (!msr_info->host_initiated)
2097 return 1;
2098 vcpu->arch.smbase = data;
2099 break;
11c6bffa 2100 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2101 case MSR_KVM_WALL_CLOCK:
2102 vcpu->kvm->arch.wall_clock = data;
2103 kvm_write_wall_clock(vcpu->kvm, data);
2104 break;
11c6bffa 2105 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2106 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2107 u64 gpa_offset;
54750f2c
MT		 2108 struct kvm_arch *ka = &vcpu->kvm->arch;
2109
12f9a48f 2110 kvmclock_reset(vcpu);
18068523 2111
54750f2c
MT		 2112 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2113 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2114
2115 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2116 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2117 &vcpu->requests);
2118
2119 ka->boot_vcpu_runs_old_kvmclock = tmp;
2120 }
2121
18068523 2122 vcpu->arch.time = data;
0061d53d 2123 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2124
2125 /* we verify if the enable bit is set... */
2126 if (!(data & 1))
2127 break;
2128
0b79459b 2129 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2130
0b79459b 2131 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2132 &vcpu->arch.pv_time, data & ~1ULL,
2133 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2134 vcpu->arch.pv_time_enabled = false;
2135 else
2136 vcpu->arch.pv_time_enabled = true;
32cad84f 2137
18068523
GOC		 2138 break;
2139 }
344d9588
GN		 2140 case MSR_KVM_ASYNC_PF_EN:
2141 if (kvm_pv_enable_async_pf(vcpu, data))
2142 return 1;
2143 break;
c9aaa895
GC		 2144 case MSR_KVM_STEAL_TIME:
2145
2146 if (unlikely(!sched_info_on()))
2147 return 1;
2148
2149 if (data & KVM_STEAL_RESERVED_MASK)
2150 return 1;
2151
2152 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2153 data & KVM_STEAL_VALID_BITS,
2154 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2155 return 1;
2156
2157 vcpu->arch.st.msr_val = data;
2158
2159 if (!(data & KVM_MSR_ENABLED))
2160 break;
2161
c9aaa895
GC		 2162 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2163
2164 break;
ae7a2a3f
MT		 2165 case MSR_KVM_PV_EOI_EN:
2166 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2167 return 1;
2168 break;
c9aaa895 2169
890ca9ae
HY		 2170 case MSR_IA32_MCG_CTL:
2171 case MSR_IA32_MCG_STATUS:
81760dcc 2172 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2173 return set_msr_mce(vcpu, msr, data);
71db6023 2174
6912ac32
WH		 2175 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2176 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2177 pr = true; /* fall through */
2178 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2179 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2180 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2181 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2182
2183 if (pr || data != 0)
a737f256
CD		 2184 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2185 "0x%x data 0x%llx\n", msr, data);
5753785f 2186 break;
84e0cefa
JS		 2187 case MSR_K7_CLK_CTL:
2188 /*
2189 * Ignore all writes to this no longer documented MSR.
2190 * Writes are only relevant for old K7 processors,
2191 * all pre-dating SVM, but a recommended workaround from
4a969980 2192 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2193 * affected processor models on the command line, hence
2194 * the need to ignore the workaround.
2195 */
2196 break;
55cd8e5a 2197 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2198 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2199 case HV_X64_MSR_CRASH_CTL:
2200 return kvm_hv_set_msr_common(vcpu, msr, data,
2201 msr_info->host_initiated);
91c9c3ed 2202 case MSR_IA32_BBL_CR_CTL3:
2203 /* Drop writes to this legacy MSR -- see rdmsr
2204 * counterpart for further detail.
2205 */
a737f256 2206 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2207 break;
2b036c6b
BO		 2208 case MSR_AMD64_OSVW_ID_LENGTH:
2209 if (!guest_cpuid_has_osvw(vcpu))
2210 return 1;
2211 vcpu->arch.osvw.length = data;
2212 break;
2213 case MSR_AMD64_OSVW_STATUS:
2214 if (!guest_cpuid_has_osvw(vcpu))
2215 return 1;
2216 vcpu->arch.osvw.status = data;
2217 break;
15c4a640 2218 default:
ffde22ac
ES		 2219 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2220 return xen_hvm_config(vcpu, data);
c6702c9d 2221 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2222 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2223 if (!ignore_msrs) {
a737f256
CD		 2224 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2225 msr, data);
ed85c068
AP		 2226 return 1;
2227 } else {
a737f256
CD		 2228 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2229 msr, data);
ed85c068
AP		 2230 break;
2231 }
15c4a640
CO		 2232 }
2233 return 0;
2234}
2235EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2236
2237
2238/*
2239 * Reads an msr value (of 'msr_index') into 'pdata'.
2240 * Returns 0 on success, non-0 otherwise.
2241 * Assumes vcpu_load() was already called.
2242 */
609e36d3 2243int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2244{
609e36d3 2245 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2246}
ff651cb6 2247EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2248
890ca9ae 2249static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2250{
2251 u64 data;
890ca9ae
HY		 2252 u64 mcg_cap = vcpu->arch.mcg_cap;
2253 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2254
2255 switch (msr) {
15c4a640
CO		 2256 case MSR_IA32_P5_MC_ADDR:
2257 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2258 data = 0;
2259 break;
15c4a640 2260 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2261 data = vcpu->arch.mcg_cap;
2262 break;
c7ac679c 2263 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2264 if (!(mcg_cap & MCG_CTL_P))
2265 return 1;
2266 data = vcpu->arch.mcg_ctl;
2267 break;
2268 case MSR_IA32_MCG_STATUS:
2269 data = vcpu->arch.mcg_status;
2270 break;
2271 default:
2272 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2273 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2274 u32 offset = msr - MSR_IA32_MC0_CTL;
2275 data = vcpu->arch.mce_banks[offset];
2276 break;
2277 }
2278 return 1;
2279 }
2280 *pdata = data;
2281 return 0;
2282}
2283
609e36d3 2284int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2285{
609e36d3 2286 switch (msr_info->index) {
890ca9ae 2287 case MSR_IA32_PLATFORM_ID:
15c4a640 2288 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2289 case MSR_IA32_DEBUGCTLMSR:
2290 case MSR_IA32_LASTBRANCHFROMIP:
2291 case MSR_IA32_LASTBRANCHTOIP:
2292 case MSR_IA32_LASTINTFROMIP:
2293 case MSR_IA32_LASTINTTOIP:
60af2ecd 2294 case MSR_K8_SYSCFG:
3afb1121
PB		 2295 case MSR_K8_TSEG_ADDR:
2296 case MSR_K8_TSEG_MASK:
60af2ecd 2297 case MSR_K7_HWCR:
61a6bd67 2298 case MSR_VM_HSAVE_PA:
1fdbd48c 2299 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2300 case MSR_AMD64_NB_CFG:
f7c6d140 2301 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2302 case MSR_AMD64_BU_CFG2:
609e36d3 2303 msr_info->data = 0;
15c4a640 2304 break;
6912ac32
WH		 2305 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2306 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2307 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2308 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2309 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2310 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2311 msr_info->data = 0;
5753785f 2312 break;
742bc670 2313 case MSR_IA32_UCODE_REV:
609e36d3 2314 msr_info->data = 0x100000000ULL;
742bc670 2315 break;
9ba075a6 2316 case MSR_MTRRcap:
9ba075a6 2317 case 0x200 ... 0x2ff:
ff53604b 2318 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2319 case 0xcd: /* fsb frequency */
609e36d3 2320 msr_info->data = 3;
15c4a640 2321 break;
7b914098
JS		 2322 /*
2323 * MSR_EBC_FREQUENCY_ID
2324 * Conservative value valid for even the basic CPU models.
2325 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2326 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2327 * and 266MHz for model 3, or 4. Set Core Clock
2328 * Frequency to System Bus Frequency Ratio to 1 (bits
2329 * 31:24) even though these are only valid for CPU
2330 * models > 2, however guests may end up dividing or
2331 * multiplying by zero otherwise.
2332 */
2333 case MSR_EBC_FREQUENCY_ID:
609e36d3 2334 msr_info->data = 1 << 24;
7b914098 2335 break;
15c4a640 2336 case MSR_IA32_APICBASE:
609e36d3 2337 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2338 break;
0105d1a5 2339 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2340 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2341 break;
a3e06bbe 2342 case MSR_IA32_TSCDEADLINE:
609e36d3 2343 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2344 break;
ba904635 2345 case MSR_IA32_TSC_ADJUST:
609e36d3 2346 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2347 break;
15c4a640 2348 case MSR_IA32_MISC_ENABLE:
609e36d3 2349 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2350 break;
64d60670
PB		 2351 case MSR_IA32_SMBASE:
2352 if (!msr_info->host_initiated)
2353 return 1;
2354 msr_info->data = vcpu->arch.smbase;
15c4a640 2355 break;
847f0ad8
AG		 2356 case MSR_IA32_PERF_STATUS:
2357 /* TSC increment by tick */
609e36d3 2358 msr_info->data = 1000ULL;
847f0ad8 2359 /* CPU multiplier */
b0996ae4 2360 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2361 break;
15c4a640 2362 case MSR_EFER:
609e36d3 2363 msr_info->data = vcpu->arch.efer;
15c4a640 2364 break;
18068523 2365 case MSR_KVM_WALL_CLOCK:
11c6bffa 2366 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2367 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2368 break;
2369 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2370 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2371 msr_info->data = vcpu->arch.time;
18068523 2372 break;
344d9588 2373 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2374 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2375 break;
c9aaa895 2376 case MSR_KVM_STEAL_TIME:
609e36d3 2377 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2378 break;
1d92128f 2379 case MSR_KVM_PV_EOI_EN:
609e36d3 2380 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2381 break;
890ca9ae
HY		 2382 case MSR_IA32_P5_MC_ADDR:
2383 case MSR_IA32_P5_MC_TYPE:
2384 case MSR_IA32_MCG_CAP:
2385 case MSR_IA32_MCG_CTL:
2386 case MSR_IA32_MCG_STATUS:
81760dcc 2387 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2388 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2389 case MSR_K7_CLK_CTL:
2390 /*
2391 * Provide expected ramp-up count for K7. All other
2392 * are set to zero, indicating minimum divisors for
2393 * every field.
2394 *
2395 * This prevents guest kernels on AMD host with CPU
2396 * type 6, model 8 and higher from exploding due to
2397 * the rdmsr failing.
2398 */
609e36d3 2399 msr_info->data = 0x20000000;
84e0cefa 2400 break;
55cd8e5a 2401 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2402 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2403 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2404 return kvm_hv_get_msr_common(vcpu,
2405 msr_info->index, &msr_info->data);
55cd8e5a 2406 break;
91c9c3ed 2407 case MSR_IA32_BBL_CR_CTL3:
2408 /* This legacy MSR exists but isn't fully documented in current
2409 * silicon. It is however accessed by winxp in very narrow
2410 * scenarios where it sets bit #19, itself documented as
2411 * a "reserved" bit. Best effort attempt to source coherent
2412 * read data here should the balance of the register be
2413 * interpreted by the guest:
2414 *
2415 * L2 cache control register 3: 64GB range, 256KB size,
2416 * enabled, latency 0x1, configured
2417 */
609e36d3 2418 msr_info->data = 0xbe702111;
91c9c3ed 2419 break;
2b036c6b
BO		 2420 case MSR_AMD64_OSVW_ID_LENGTH:
2421 if (!guest_cpuid_has_osvw(vcpu))
2422 return 1;
609e36d3 2423 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2424 break;
2425 case MSR_AMD64_OSVW_STATUS:
2426 if (!guest_cpuid_has_osvw(vcpu))
2427 return 1;
609e36d3 2428 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2429 break;
15c4a640 2430 default:
c6702c9d 2431 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2432 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2433 if (!ignore_msrs) {
609e36d3 2434 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2435 return 1;
2436 } else {
609e36d3
PB		 2437 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2438 msr_info->data = 0;
ed85c068
AP		 2439 }
2440 break;
15c4a640 2441 }
15c4a640
CO		 2442 return 0;
2443}
2444EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2445
313a3dc7
CO		 2446/*
2447 * Read or write a bunch of msrs. All parameters are kernel addresses.
2448 *
2449 * @return number of msrs set successfully.
2450 */
2451static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2452 struct kvm_msr_entry *entries,
2453 int (*do_msr)(struct kvm_vcpu *vcpu,
2454 unsigned index, u64 *data))
2455{
f656ce01 2456 int i, idx;
313a3dc7 2457
f656ce01 2458 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2459 for (i = 0; i < msrs->nmsrs; ++i)
2460 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2461 break;
f656ce01 2462 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2463
313a3dc7
CO		 2464 return i;
2465}
2466
2467/*
2468 * Read or write a bunch of msrs. Parameters are user addresses.
2469 *
2470 * @return number of msrs set successfully.
2471 */
2472static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2473 int (*do_msr)(struct kvm_vcpu *vcpu,
2474 unsigned index, u64 *data),
2475 int writeback)
2476{
2477 struct kvm_msrs msrs;
2478 struct kvm_msr_entry *entries;
2479 int r, n;
2480 unsigned size;
2481
2482 r = -EFAULT;
2483 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2484 goto out;
2485
2486 r = -E2BIG;
2487 if (msrs.nmsrs >= MAX_IO_MSRS)
2488 goto out;
2489
313a3dc7 2490 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2491 entries = memdup_user(user_msrs->entries, size);
2492 if (IS_ERR(entries)) {
2493 r = PTR_ERR(entries);
313a3dc7 2494 goto out;
ff5c2c03 2495 }
313a3dc7
CO		 2496
2497 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2498 if (r < 0)
2499 goto out_free;
2500
2501 r = -EFAULT;
2502 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2503 goto out_free;
2504
2505 r = n;
2506
2507out_free:
7a73c028 2508 kfree(entries);
313a3dc7
CO		 2509out:
2510 return r;
2511}
2512
784aa3d7 2513int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2514{
2515 int r;
2516
2517 switch (ext) {
2518 case KVM_CAP_IRQCHIP:
2519 case KVM_CAP_HLT:
2520 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2521 case KVM_CAP_SET_TSS_ADDR:
07716717 2522 case KVM_CAP_EXT_CPUID:
9c15bb1d 2523 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2524 case KVM_CAP_CLOCKSOURCE:
7837699f 2525 case KVM_CAP_PIT:
a28e4f5a 2526 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2527 case KVM_CAP_MP_STATE:
ed848624 2528 case KVM_CAP_SYNC_MMU:
a355c85c 2529 case KVM_CAP_USER_NMI:
52d939a0 2530 case KVM_CAP_REINJECT_CONTROL:
4925663a 2531 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2532 case KVM_CAP_IOEVENTFD:
f848a5a8 2533 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2534 case KVM_CAP_PIT2:
e9f42757 2535 case KVM_CAP_PIT_STATE2:
b927a3ce 2536 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2537 case KVM_CAP_XEN_HVM:
afbcf7ab 2538 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2539 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2540 case KVM_CAP_HYPERV:
10388a07 2541 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2542 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2543 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2544 case KVM_CAP_DEBUGREGS:
d2be1651 2545 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2546 case KVM_CAP_XSAVE:
344d9588 2547 case KVM_CAP_ASYNC_PF:
92a1f12d 2548 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2549 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2550 case KVM_CAP_READONLY_MEM:
5f66b620 2551 case KVM_CAP_HYPERV_TIME:
100943c5 2552 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2553 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2554 case KVM_CAP_ENABLE_CAP_VM:
2555 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2556 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2557 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2558#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2559 case KVM_CAP_ASSIGN_DEV_IRQ:
2560 case KVM_CAP_PCI_2_3:
2561#endif
018d00d2
ZX		 2562 r = 1;
2563 break;
6d396b55
PB		 2564 case KVM_CAP_X86_SMM:
2565 /* SMBASE is usually relocated above 1M on modern chipsets,
2566 * and SMM handlers might indeed rely on 4G segment limits,
2567 * so do not report SMM to be available if real mode is
2568 * emulated via vm86 mode. Still, do not go to great lengths
2569 * to avoid userspace's usage of the feature, because it is a
2570 * fringe case that is not enabled except via specific settings
2571 * of the module parameters.
2572 */
2573 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2574 break;
542472b5
LV		 2575 case KVM_CAP_COALESCED_MMIO:
2576 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2577 break;
774ead3a
AK		 2578 case KVM_CAP_VAPIC:
2579 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2580 break;
f725230a 2581 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2582 r = KVM_SOFT_MAX_VCPUS;
2583 break;
2584 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2585 r = KVM_MAX_VCPUS;
2586 break;
a988b910 2587 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2588 r = KVM_USER_MEM_SLOTS;
a988b910 2589 break;
a68a6a72
MT		 2590 case KVM_CAP_PV_MMU: /* obsolete */
2591 r = 0;
2f333bcb 2592 break;
4cee4b72 2593#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2594 case KVM_CAP_IOMMU:
a1b60c1c 2595 r = iommu_present(&pci_bus_type);
62c476c7 2596 break;
4cee4b72 2597#endif
890ca9ae
HY		 2598 case KVM_CAP_MCE:
2599 r = KVM_MAX_MCE_BANKS;
2600 break;
2d5b5a66
SY		 2601 case KVM_CAP_XCRS:
2602 r = cpu_has_xsave;
2603 break;
92a1f12d
JR		 2604 case KVM_CAP_TSC_CONTROL:
2605 r = kvm_has_tsc_control;
2606 break;
018d00d2
ZX		 2607 default:
2608 r = 0;
2609 break;
2610 }
2611 return r;
2612
2613}
2614
043405e1
CO		 2615long kvm_arch_dev_ioctl(struct file *filp,
2616 unsigned int ioctl, unsigned long arg)
2617{
2618 void __user *argp = (void __user *)arg;
2619 long r;
2620
2621 switch (ioctl) {
2622 case KVM_GET_MSR_INDEX_LIST: {
2623 struct kvm_msr_list __user *user_msr_list = argp;
2624 struct kvm_msr_list msr_list;
2625 unsigned n;
2626
2627 r = -EFAULT;
2628 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2629 goto out;
2630 n = msr_list.nmsrs;
62ef68bb 2631 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2632 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2633 goto out;
2634 r = -E2BIG;
e125e7b6 2635 if (n < msr_list.nmsrs)
043405e1
CO		 2636 goto out;
2637 r = -EFAULT;
2638 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2639 num_msrs_to_save * sizeof(u32)))
2640 goto out;
e125e7b6 2641 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2642 &emulated_msrs,
62ef68bb 2643 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2644 goto out;
2645 r = 0;
2646 break;
2647 }
9c15bb1d
BP		 2648 case KVM_GET_SUPPORTED_CPUID:
2649 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2650 struct kvm_cpuid2 __user *cpuid_arg = argp;
2651 struct kvm_cpuid2 cpuid;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2655 goto out;
9c15bb1d
BP		 2656
2657 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2658 ioctl);
674eea0f
AK		 2659 if (r)
2660 goto out;
2661
2662 r = -EFAULT;
2663 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2664 goto out;
2665 r = 0;
2666 break;
2667 }
890ca9ae
HY		 2668 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2669 u64 mce_cap;
2670
2671 mce_cap = KVM_MCE_CAP_SUPPORTED;
2672 r = -EFAULT;
2673 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2674 goto out;
2675 r = 0;
2676 break;
2677 }
043405e1
CO		 2678 default:
2679 r = -EINVAL;
2680 }
2681out:
2682 return r;
2683}
2684
f5f48ee1
SY		 2685static void wbinvd_ipi(void *garbage)
2686{
2687 wbinvd();
2688}
2689
2690static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2691{
e0f0bbc5 2692 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2693}
2694
313a3dc7
CO		 2695void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2696{
f5f48ee1
SY		 2697 /* Address WBINVD may be executed by guest */
2698 if (need_emulate_wbinvd(vcpu)) {
2699 if (kvm_x86_ops->has_wbinvd_exit())
2700 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2701 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2702 smp_call_function_single(vcpu->cpu,
2703 wbinvd_ipi, NULL, 1);
2704 }
2705
313a3dc7 2706 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2707
0dd6a6ed
ZA		 2708 /* Apply any externally detected TSC adjustments (due to suspend) */
2709 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2710 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2711 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2712 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2713 }
8f6055cb 2714
48434c20 2715 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2716 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2717 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2718 if (tsc_delta < 0)
2719 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2720 if (check_tsc_unstable()) {
07c1419a 2721 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2722 vcpu->arch.last_guest_tsc);
2723 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2724 vcpu->arch.tsc_catchup = 1;
c285545f 2725 }
d98d07ca
MT		 2726 /*
2727 * On a host with synchronized TSC, there is no need to update
2728 * kvmclock on vcpu->cpu migration
2729 */
2730 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2731 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2732 if (vcpu->cpu != cpu)
2733 kvm_migrate_timers(vcpu);
e48672fa 2734 vcpu->cpu = cpu;
6b7d7e76 2735 }
c9aaa895 2736
c9aaa895 2737 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2738}
2739
2740void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2741{
02daab21 2742 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2743 kvm_put_guest_fpu(vcpu);
4ea1636b 2744 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2745}
2746
313a3dc7
CO		 2747static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2748 struct kvm_lapic_state *s)
2749{
5a71785d 2750 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2751 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2752
2753 return 0;
2754}
2755
2756static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2757 struct kvm_lapic_state *s)
2758{
64eb0620 2759 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2760 update_cr8_intercept(vcpu);
313a3dc7
CO		 2761
2762 return 0;
2763}
2764
f77bc6a4
ZX		 2765static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2766 struct kvm_interrupt *irq)
2767{
02cdb50f 2768 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2769 return -EINVAL;
1c1a9ce9
SR		 2770
2771 if (!irqchip_in_kernel(vcpu->kvm)) {
2772 kvm_queue_interrupt(vcpu, irq->irq, false);
2773 kvm_make_request(KVM_REQ_EVENT, vcpu);
2774 return 0;
2775 }
2776
2777 /*
2778 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2779 * fail for in-kernel 8259.
2780 */
2781 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2782 return -ENXIO;
f77bc6a4 2783
1c1a9ce9
SR		 2784 if (vcpu->arch.pending_external_vector != -1)
2785 return -EEXIST;
f77bc6a4 2786
1c1a9ce9 2787 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2788 return 0;
2789}
2790
c4abb7c9
JK		 2791static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2792{
c4abb7c9 2793 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2794
2795 return 0;
2796}
2797
f077825a
PB		 2798static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2799{
64d60670
PB		 2800 kvm_make_request(KVM_REQ_SMI, vcpu);
2801
f077825a
PB		 2802 return 0;
2803}
2804
b209749f
AK		 2805static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2806 struct kvm_tpr_access_ctl *tac)
2807{
2808 if (tac->flags)
2809 return -EINVAL;
2810 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2811 return 0;
2812}
2813
890ca9ae
HY		 2814static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2815 u64 mcg_cap)
2816{
2817 int r;
2818 unsigned bank_num = mcg_cap & 0xff, bank;
2819
2820 r = -EINVAL;
a9e38c3e 2821 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2822 goto out;
2823 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2824 goto out;
2825 r = 0;
2826 vcpu->arch.mcg_cap = mcg_cap;
2827 /* Init IA32_MCG_CTL to all 1s */
2828 if (mcg_cap & MCG_CTL_P)
2829 vcpu->arch.mcg_ctl = ~(u64)0;
2830 /* Init IA32_MCi_CTL to all 1s */
2831 for (bank = 0; bank < bank_num; bank++)
2832 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2833out:
2834 return r;
2835}
2836
2837static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2838 struct kvm_x86_mce *mce)
2839{
2840 u64 mcg_cap = vcpu->arch.mcg_cap;
2841 unsigned bank_num = mcg_cap & 0xff;
2842 u64 *banks = vcpu->arch.mce_banks;
2843
2844 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2845 return -EINVAL;
2846 /*
2847 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2848 * reporting is disabled
2849 */
2850 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2851 vcpu->arch.mcg_ctl != ~(u64)0)
2852 return 0;
2853 banks += 4 * mce->bank;
2854 /*
2855 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2856 * reporting is disabled for the bank
2857 */
2858 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2859 return 0;
2860 if (mce->status & MCI_STATUS_UC) {
2861 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2862 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2863 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2864 return 0;
2865 }
2866 if (banks[1] & MCI_STATUS_VAL)
2867 mce->status |= MCI_STATUS_OVER;
2868 banks[2] = mce->addr;
2869 banks[3] = mce->misc;
2870 vcpu->arch.mcg_status = mce->mcg_status;
2871 banks[1] = mce->status;
2872 kvm_queue_exception(vcpu, MC_VECTOR);
2873 } else if (!(banks[1] & MCI_STATUS_VAL)
2874 || !(banks[1] & MCI_STATUS_UC)) {
2875 if (banks[1] & MCI_STATUS_VAL)
2876 mce->status |= MCI_STATUS_OVER;
2877 banks[2] = mce->addr;
2878 banks[3] = mce->misc;
2879 banks[1] = mce->status;
2880 } else
2881 banks[1] |= MCI_STATUS_OVER;
2882 return 0;
2883}
2884
3cfc3092
JK		 2885static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2886 struct kvm_vcpu_events *events)
2887{
7460fb4a 2888 process_nmi(vcpu);
03b82a30
JK		 2889 events->exception.injected =
2890 vcpu->arch.exception.pending &&
2891 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2892 events->exception.nr = vcpu->arch.exception.nr;
2893 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2894 events->exception.pad = 0;
3cfc3092
JK		 2895 events->exception.error_code = vcpu->arch.exception.error_code;
2896
03b82a30
JK		 2897 events->interrupt.injected =
2898 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2899 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2900 events->interrupt.soft = 0;
37ccdcbe 2901 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2902
2903 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2904 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2905 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2906 events->nmi.pad = 0;
3cfc3092 2907
66450a21 2908 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2909
f077825a
PB		 2910 events->smi.smm = is_smm(vcpu);
2911 events->smi.pending = vcpu->arch.smi_pending;
2912 events->smi.smm_inside_nmi =
2913 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2914 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2915
dab4b911 2916 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2917 | KVM_VCPUEVENT_VALID_SHADOW
2918 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2919 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2920}
2921
2922static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2923 struct kvm_vcpu_events *events)
2924{
dab4b911 2925 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2926 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2927 | KVM_VCPUEVENT_VALID_SHADOW
2928 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2929 return -EINVAL;
2930
7460fb4a 2931 process_nmi(vcpu);
3cfc3092
JK		 2932 vcpu->arch.exception.pending = events->exception.injected;
2933 vcpu->arch.exception.nr = events->exception.nr;
2934 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2935 vcpu->arch.exception.error_code = events->exception.error_code;
2936
2937 vcpu->arch.interrupt.pending = events->interrupt.injected;
2938 vcpu->arch.interrupt.nr = events->interrupt.nr;
2939 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2940 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2941 kvm_x86_ops->set_interrupt_shadow(vcpu,
2942 events->interrupt.shadow);
3cfc3092
JK		 2943
2944 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2945 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2946 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2947 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2948
66450a21
JK		 2949 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2950 kvm_vcpu_has_lapic(vcpu))
2951 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2952
f077825a
PB		 2953 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2954 if (events->smi.smm)
2955 vcpu->arch.hflags |= HF_SMM_MASK;
2956 else
2957 vcpu->arch.hflags &= ~HF_SMM_MASK;
2958 vcpu->arch.smi_pending = events->smi.pending;
2959 if (events->smi.smm_inside_nmi)
2960 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2961 else
2962 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2963 if (kvm_vcpu_has_lapic(vcpu)) {
2964 if (events->smi.latched_init)
2965 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2966 else
2967 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2968 }
2969 }
2970
3842d135
AK		 2971 kvm_make_request(KVM_REQ_EVENT, vcpu);
2972
3cfc3092
JK		 2973 return 0;
2974}
2975
a1efbe77
JK		 2976static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2977 struct kvm_debugregs *dbgregs)
2978{
73aaf249
JK		 2979 unsigned long val;
2980
a1efbe77 2981 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2982 kvm_get_dr(vcpu, 6, &val);
73aaf249 2983 dbgregs->dr6 = val;
a1efbe77
JK		 2984 dbgregs->dr7 = vcpu->arch.dr7;
2985 dbgregs->flags = 0;
97e69aa6 2986 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2987}
2988
2989static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2990 struct kvm_debugregs *dbgregs)
2991{
2992 if (dbgregs->flags)
2993 return -EINVAL;
2994
a1efbe77 2995 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2996 kvm_update_dr0123(vcpu);
a1efbe77 2997 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2998 kvm_update_dr6(vcpu);
a1efbe77 2999 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3000 kvm_update_dr7(vcpu);
a1efbe77 3001
a1efbe77
JK		 3002 return 0;
3003}
3004
df1daba7
PB		 3005#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3006
3007static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3008{
c47ada30 3009 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3010 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3011 u64 valid;
3012
3013 /*
3014 * Copy legacy XSAVE area, to avoid complications with CPUID
3015 * leaves 0 and 1 in the loop below.
3016 */
3017 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3018
3019 /* Set XSTATE_BV */
3020 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3021
3022 /*
3023 * Copy each region from the possibly compacted offset to the
3024 * non-compacted offset.
3025 */
3026 valid = xstate_bv & ~XSTATE_FPSSE;
3027 while (valid) {
3028 u64 feature = valid & -valid;
3029 int index = fls64(feature) - 1;
3030 void *src = get_xsave_addr(xsave, feature);
3031
3032 if (src) {
3033 u32 size, offset, ecx, edx;
3034 cpuid_count(XSTATE_CPUID, index,
3035 &size, &offset, &ecx, &edx);
3036 memcpy(dest + offset, src, size);
3037 }
3038
3039 valid -= feature;
3040 }
3041}
3042
3043static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3044{
c47ada30 3045 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3046 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3047 u64 valid;
3048
3049 /*
3050 * Copy legacy XSAVE area, to avoid complications with CPUID
3051 * leaves 0 and 1 in the loop below.
3052 */
3053 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3054
3055 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3056 xsave->header.xfeatures = xstate_bv;
df1daba7 3057 if (cpu_has_xsaves)
3a54450b 3058 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3059
3060 /*
3061 * Copy each region from the non-compacted offset to the
3062 * possibly compacted offset.
3063 */
3064 valid = xstate_bv & ~XSTATE_FPSSE;
3065 while (valid) {
3066 u64 feature = valid & -valid;
3067 int index = fls64(feature) - 1;
3068 void *dest = get_xsave_addr(xsave, feature);
3069
3070 if (dest) {
3071 u32 size, offset, ecx, edx;
3072 cpuid_count(XSTATE_CPUID, index,
3073 &size, &offset, &ecx, &edx);
3074 memcpy(dest, src + offset, size);
ee4100da 3075 }
df1daba7
PB		 3076
3077 valid -= feature;
3078 }
3079}
3080
2d5b5a66
SY		 3081static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3082 struct kvm_xsave *guest_xsave)
3083{
4344ee98 3084 if (cpu_has_xsave) {
df1daba7
PB		 3085 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3086 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3087 } else {
2d5b5a66 3088 memcpy(guest_xsave->region,
7366ed77 3089 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3090 sizeof(struct fxregs_state));
2d5b5a66
SY		 3091 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3092 XSTATE_FPSSE;
3093 }
3094}
3095
3096static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3097 struct kvm_xsave *guest_xsave)
3098{
3099 u64 xstate_bv =
3100 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3101
d7876f1b
PB		 3102 if (cpu_has_xsave) {
3103 /*
3104 * Here we allow setting states that are not present in
3105 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3106 * with old userspace.
3107 */
4ff41732 3108 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3109 return -EINVAL;
df1daba7 3110 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3111 } else {
2d5b5a66
SY		 3112 if (xstate_bv & ~XSTATE_FPSSE)
3113 return -EINVAL;
7366ed77 3114 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3115 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3116 }
3117 return 0;
3118}
3119
3120static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3121 struct kvm_xcrs *guest_xcrs)
3122{
3123 if (!cpu_has_xsave) {
3124 guest_xcrs->nr_xcrs = 0;
3125 return;
3126 }
3127
3128 guest_xcrs->nr_xcrs = 1;
3129 guest_xcrs->flags = 0;
3130 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3131 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3132}
3133
3134static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3135 struct kvm_xcrs *guest_xcrs)
3136{
3137 int i, r = 0;
3138
3139 if (!cpu_has_xsave)
3140 return -EINVAL;
3141
3142 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3143 return -EINVAL;
3144
3145 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3146 /* Only support XCR0 currently */
c67a04cb 3147 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3148 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3149 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3150 break;
3151 }
3152 if (r)
3153 r = -EINVAL;
3154 return r;
3155}
3156
1c0b28c2
EM		 3157/*
3158 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3159 * stopped by the hypervisor. This function will be called from the host only.
3160 * EINVAL is returned when the host attempts to set the flag for a guest that
3161 * does not support pv clocks.
3162 */
3163static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3164{
0b79459b 3165 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3166 return -EINVAL;
51d59c6b 3167 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3168 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3169 return 0;
3170}
3171
313a3dc7
CO		 3172long kvm_arch_vcpu_ioctl(struct file *filp,
3173 unsigned int ioctl, unsigned long arg)
3174{
3175 struct kvm_vcpu *vcpu = filp->private_data;
3176 void __user *argp = (void __user *)arg;
3177 int r;
d1ac91d8
AK		 3178 union {
3179 struct kvm_lapic_state *lapic;
3180 struct kvm_xsave *xsave;
3181 struct kvm_xcrs *xcrs;
3182 void *buffer;
3183 } u;
3184
3185 u.buffer = NULL;
313a3dc7
CO		 3186 switch (ioctl) {
3187 case KVM_GET_LAPIC: {
2204ae3c
MT		 3188 r = -EINVAL;
3189 if (!vcpu->arch.apic)
3190 goto out;
d1ac91d8 3191 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3192
b772ff36 3193 r = -ENOMEM;
d1ac91d8 3194 if (!u.lapic)
b772ff36 3195 goto out;
d1ac91d8 3196 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3197 if (r)
3198 goto out;
3199 r = -EFAULT;
d1ac91d8 3200 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3201 goto out;
3202 r = 0;
3203 break;
3204 }
3205 case KVM_SET_LAPIC: {
2204ae3c
MT		 3206 r = -EINVAL;
3207 if (!vcpu->arch.apic)
3208 goto out;
ff5c2c03 3209 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3210 if (IS_ERR(u.lapic))
3211 return PTR_ERR(u.lapic);
ff5c2c03 3212
d1ac91d8 3213 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3214 break;
3215 }
f77bc6a4
ZX		 3216 case KVM_INTERRUPT: {
3217 struct kvm_interrupt irq;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&irq, argp, sizeof irq))
3221 goto out;
3222 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3223 break;
3224 }
c4abb7c9
JK		 3225 case KVM_NMI: {
3226 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3227 break;
3228 }
f077825a
PB		 3229 case KVM_SMI: {
3230 r = kvm_vcpu_ioctl_smi(vcpu);
3231 break;
3232 }
313a3dc7
CO		 3233 case KVM_SET_CPUID: {
3234 struct kvm_cpuid __user *cpuid_arg = argp;
3235 struct kvm_cpuid cpuid;
3236
3237 r = -EFAULT;
3238 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3239 goto out;
3240 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3241 break;
3242 }
07716717
DK		 3243 case KVM_SET_CPUID2: {
3244 struct kvm_cpuid2 __user *cpuid_arg = argp;
3245 struct kvm_cpuid2 cpuid;
3246
3247 r = -EFAULT;
3248 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3249 goto out;
3250 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3251 cpuid_arg->entries);
07716717
DK		 3252 break;
3253 }
3254 case KVM_GET_CPUID2: {
3255 struct kvm_cpuid2 __user *cpuid_arg = argp;
3256 struct kvm_cpuid2 cpuid;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3260 goto out;
3261 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3262 cpuid_arg->entries);
07716717
DK		 3263 if (r)
3264 goto out;
3265 r = -EFAULT;
3266 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3267 goto out;
3268 r = 0;
3269 break;
3270 }
313a3dc7 3271 case KVM_GET_MSRS:
609e36d3 3272 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3273 break;
3274 case KVM_SET_MSRS:
3275 r = msr_io(vcpu, argp, do_set_msr, 0);
3276 break;
b209749f
AK		 3277 case KVM_TPR_ACCESS_REPORTING: {
3278 struct kvm_tpr_access_ctl tac;
3279
3280 r = -EFAULT;
3281 if (copy_from_user(&tac, argp, sizeof tac))
3282 goto out;
3283 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3284 if (r)
3285 goto out;
3286 r = -EFAULT;
3287 if (copy_to_user(argp, &tac, sizeof tac))
3288 goto out;
3289 r = 0;
3290 break;
3291 };
b93463aa
AK		 3292 case KVM_SET_VAPIC_ADDR: {
3293 struct kvm_vapic_addr va;
3294
3295 r = -EINVAL;
35754c98 3296 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3297 goto out;
3298 r = -EFAULT;
3299 if (copy_from_user(&va, argp, sizeof va))
3300 goto out;
fda4e2e8 3301 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3302 break;
3303 }
890ca9ae
HY		 3304 case KVM_X86_SETUP_MCE: {
3305 u64 mcg_cap;
3306
3307 r = -EFAULT;
3308 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3309 goto out;
3310 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3311 break;
3312 }
3313 case KVM_X86_SET_MCE: {
3314 struct kvm_x86_mce mce;
3315
3316 r = -EFAULT;
3317 if (copy_from_user(&mce, argp, sizeof mce))
3318 goto out;
3319 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3320 break;
3321 }
3cfc3092
JK		 3322 case KVM_GET_VCPU_EVENTS: {
3323 struct kvm_vcpu_events events;
3324
3325 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3326
3327 r = -EFAULT;
3328 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3329 break;
3330 r = 0;
3331 break;
3332 }
3333 case KVM_SET_VCPU_EVENTS: {
3334 struct kvm_vcpu_events events;
3335
3336 r = -EFAULT;
3337 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3338 break;
3339
3340 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3341 break;
3342 }
a1efbe77
JK		 3343 case KVM_GET_DEBUGREGS: {
3344 struct kvm_debugregs dbgregs;
3345
3346 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3347
3348 r = -EFAULT;
3349 if (copy_to_user(argp, &dbgregs,
3350 sizeof(struct kvm_debugregs)))
3351 break;
3352 r = 0;
3353 break;
3354 }
3355 case KVM_SET_DEBUGREGS: {
3356 struct kvm_debugregs dbgregs;
3357
3358 r = -EFAULT;
3359 if (copy_from_user(&dbgregs, argp,
3360 sizeof(struct kvm_debugregs)))
3361 break;
3362
3363 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3364 break;
3365 }
2d5b5a66 3366 case KVM_GET_XSAVE: {
d1ac91d8 3367 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3368 r = -ENOMEM;
d1ac91d8 3369 if (!u.xsave)
2d5b5a66
SY		 3370 break;
3371
d1ac91d8 3372 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3373
3374 r = -EFAULT;
d1ac91d8 3375 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3376 break;
3377 r = 0;
3378 break;
3379 }
3380 case KVM_SET_XSAVE: {
ff5c2c03 3381 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3382 if (IS_ERR(u.xsave))
3383 return PTR_ERR(u.xsave);
2d5b5a66 3384
d1ac91d8 3385 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3386 break;
3387 }
3388 case KVM_GET_XCRS: {
d1ac91d8 3389 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3390 r = -ENOMEM;
d1ac91d8 3391 if (!u.xcrs)
2d5b5a66
SY		 3392 break;
3393
d1ac91d8 3394 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3395
3396 r = -EFAULT;
d1ac91d8 3397 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3398 sizeof(struct kvm_xcrs)))
3399 break;
3400 r = 0;
3401 break;
3402 }
3403 case KVM_SET_XCRS: {
ff5c2c03 3404 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3405 if (IS_ERR(u.xcrs))
3406 return PTR_ERR(u.xcrs);
2d5b5a66 3407
d1ac91d8 3408 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3409 break;
3410 }
92a1f12d
JR		 3411 case KVM_SET_TSC_KHZ: {
3412 u32 user_tsc_khz;
3413
3414 r = -EINVAL;
92a1f12d
JR		 3415 user_tsc_khz = (u32)arg;
3416
3417 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3418 goto out;
3419
cc578287
ZA		 3420 if (user_tsc_khz == 0)
3421 user_tsc_khz = tsc_khz;
3422
381d585c
HZ		 3423 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3424 r = 0;
92a1f12d 3425
92a1f12d
JR		 3426 goto out;
3427 }
3428 case KVM_GET_TSC_KHZ: {
cc578287 3429 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3430 goto out;
3431 }
1c0b28c2
EM		 3432 case KVM_KVMCLOCK_CTRL: {
3433 r = kvm_set_guest_paused(vcpu);
3434 goto out;
3435 }
313a3dc7
CO		 3436 default:
3437 r = -EINVAL;
3438 }
3439out:
d1ac91d8 3440 kfree(u.buffer);
313a3dc7
CO		 3441 return r;
3442}
3443
5b1c1493
CO		 3444int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3445{
3446 return VM_FAULT_SIGBUS;
3447}
3448
1fe779f8
CO		 3449static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3450{
3451 int ret;
3452
3453 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3454 return -EINVAL;
1fe779f8
CO		 3455 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3456 return ret;
3457}
3458
b927a3ce
SY		 3459static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3460 u64 ident_addr)
3461{
3462 kvm->arch.ept_identity_map_addr = ident_addr;
3463 return 0;
3464}
3465
1fe779f8
CO		 3466static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3467 u32 kvm_nr_mmu_pages)
3468{
3469 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3470 return -EINVAL;
3471
79fac95e 3472 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3473
3474 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3475 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3476
79fac95e 3477 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3478 return 0;
3479}
3480
3481static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3482{
39de71ec 3483 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3484}
3485
1fe779f8
CO		 3486static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3487{
3488 int r;
3489
3490 r = 0;
3491 switch (chip->chip_id) {
3492 case KVM_IRQCHIP_PIC_MASTER:
3493 memcpy(&chip->chip.pic,
3494 &pic_irqchip(kvm)->pics[0],
3495 sizeof(struct kvm_pic_state));
3496 break;
3497 case KVM_IRQCHIP_PIC_SLAVE:
3498 memcpy(&chip->chip.pic,
3499 &pic_irqchip(kvm)->pics[1],
3500 sizeof(struct kvm_pic_state));
3501 break;
3502 case KVM_IRQCHIP_IOAPIC:
eba0226b 3503 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3504 break;
3505 default:
3506 r = -EINVAL;
3507 break;
3508 }
3509 return r;
3510}
3511
3512static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3513{
3514 int r;
3515
3516 r = 0;
3517 switch (chip->chip_id) {
3518 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3519 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3520 memcpy(&pic_irqchip(kvm)->pics[0],
3521 &chip->chip.pic,
3522 sizeof(struct kvm_pic_state));
f4f51050 3523 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3524 break;
3525 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3526 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3527 memcpy(&pic_irqchip(kvm)->pics[1],
3528 &chip->chip.pic,
3529 sizeof(struct kvm_pic_state));
f4f51050 3530 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3531 break;
3532 case KVM_IRQCHIP_IOAPIC:
eba0226b 3533 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3534 break;
3535 default:
3536 r = -EINVAL;
3537 break;
3538 }
3539 kvm_pic_update_irq(pic_irqchip(kvm));
3540 return r;
3541}
3542
e0f63cb9
SY		 3543static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3544{
894a9c55 3545 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3546 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3547 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3548 return 0;
e0f63cb9
SY		 3549}
3550
3551static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3552{
894a9c55 3553 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3554 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3555 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3556 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3557 return 0;
e9f42757
BK		 3558}
3559
3560static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3561{
e9f42757
BK		 3562 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3563 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3564 sizeof(ps->channels));
3565 ps->flags = kvm->arch.vpit->pit_state.flags;
3566 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3567 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3568 return 0;
e9f42757
BK		 3569}
3570
3571static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3572{
2da29bcc 3573 int start = 0;
e9f42757
BK		 3574 u32 prev_legacy, cur_legacy;
3575 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3576 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3577 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3578 if (!prev_legacy && cur_legacy)
3579 start = 1;
3580 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3581 sizeof(kvm->arch.vpit->pit_state.channels));
3582 kvm->arch.vpit->pit_state.flags = ps->flags;
3583 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3584 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3585 return 0;
e0f63cb9
SY		 3586}
3587
52d939a0
MT		 3588static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3589 struct kvm_reinject_control *control)
3590{
3591 if (!kvm->arch.vpit)
3592 return -ENXIO;
894a9c55 3593 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3594 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3595 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3596 return 0;
3597}
3598
95d4c16c 3599/**
60c34612
TY		 3600 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3601 * @kvm: kvm instance
3602 * @log: slot id and address to which we copy the log
95d4c16c 3603 *
e108ff2f
PB		 3604 * Steps 1-4 below provide general overview of dirty page logging. See
3605 * kvm_get_dirty_log_protect() function description for additional details.
3606 *
3607 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3608 * always flush the TLB (step 4) even if previous step failed and the dirty
3609 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3610 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3611 * writes will be marked dirty for next log read.
95d4c16c 3612 *
60c34612
TY		 3613 * 1. Take a snapshot of the bit and clear it if needed.
3614 * 2. Write protect the corresponding page.
e108ff2f
PB		 3615 * 3. Copy the snapshot to the userspace.
3616 * 4. Flush TLB's if needed.
5bb064dc 3617 */
60c34612 3618int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3619{
60c34612 3620 bool is_dirty = false;
e108ff2f 3621 int r;
5bb064dc 3622
79fac95e 3623 mutex_lock(&kvm->slots_lock);
5bb064dc 3624
88178fd4
KH		 3625 /*
3626 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3627 */
3628 if (kvm_x86_ops->flush_log_dirty)
3629 kvm_x86_ops->flush_log_dirty(kvm);
3630
e108ff2f 3631 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3632
3633 /*
3634 * All the TLBs can be flushed out of mmu lock, see the comments in
3635 * kvm_mmu_slot_remove_write_access().
3636 */
e108ff2f 3637 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3638 if (is_dirty)
3639 kvm_flush_remote_tlbs(kvm);
3640
79fac95e 3641 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3642 return r;
3643}
3644
aa2fbe6d
YZ		 3645int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3646 bool line_status)
23d43cf9
CD		 3647{
3648 if (!irqchip_in_kernel(kvm))
3649 return -ENXIO;
3650
3651 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3652 irq_event->irq, irq_event->level,
3653 line_status);
23d43cf9
CD		 3654 return 0;
3655}
3656
90de4a18
NA		 3657static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3658 struct kvm_enable_cap *cap)
3659{
3660 int r;
3661
3662 if (cap->flags)
3663 return -EINVAL;
3664
3665 switch (cap->cap) {
3666 case KVM_CAP_DISABLE_QUIRKS:
3667 kvm->arch.disabled_quirks = cap->args[0];
3668 r = 0;
3669 break;
49df6397
SR		 3670 case KVM_CAP_SPLIT_IRQCHIP: {
3671 mutex_lock(&kvm->lock);
b053b2ae
SR		 3672 r = -EINVAL;
3673 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3674 goto split_irqchip_unlock;
49df6397
SR		 3675 r = -EEXIST;
3676 if (irqchip_in_kernel(kvm))
3677 goto split_irqchip_unlock;
3678 if (atomic_read(&kvm->online_vcpus))
3679 goto split_irqchip_unlock;
3680 r = kvm_setup_empty_irq_routing(kvm);
3681 if (r)
3682 goto split_irqchip_unlock;
3683 /* Pairs with irqchip_in_kernel. */
3684 smp_wmb();
3685 kvm->arch.irqchip_split = true;
b053b2ae 3686 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3687 r = 0;
3688split_irqchip_unlock:
3689 mutex_unlock(&kvm->lock);
3690 break;
3691 }
90de4a18
NA		 3692 default:
3693 r = -EINVAL;
3694 break;
3695 }
3696 return r;
3697}
3698
1fe779f8
CO		 3699long kvm_arch_vm_ioctl(struct file *filp,
3700 unsigned int ioctl, unsigned long arg)
3701{
3702 struct kvm *kvm = filp->private_data;
3703 void __user *argp = (void __user *)arg;
367e1319 3704 int r = -ENOTTY;
f0d66275
DH		 3705 /*
3706 * This union makes it completely explicit to gcc-3.x
3707 * that these two variables' stack usage should be
3708 * combined, not added together.
3709 */
3710 union {
3711 struct kvm_pit_state ps;
e9f42757 3712 struct kvm_pit_state2 ps2;
c5ff41ce 3713 struct kvm_pit_config pit_config;
f0d66275 3714 } u;
1fe779f8
CO		 3715
3716 switch (ioctl) {
3717 case KVM_SET_TSS_ADDR:
3718 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3719 break;
b927a3ce
SY		 3720 case KVM_SET_IDENTITY_MAP_ADDR: {
3721 u64 ident_addr;
3722
3723 r = -EFAULT;
3724 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3725 goto out;
3726 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3727 break;
3728 }
1fe779f8
CO		 3729 case KVM_SET_NR_MMU_PAGES:
3730 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3731 break;
3732 case KVM_GET_NR_MMU_PAGES:
3733 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3734 break;
3ddea128
MT		 3735 case KVM_CREATE_IRQCHIP: {
3736 struct kvm_pic *vpic;
3737
3738 mutex_lock(&kvm->lock);
3739 r = -EEXIST;
3740 if (kvm->arch.vpic)
3741 goto create_irqchip_unlock;
3e515705
AK		 3742 r = -EINVAL;
3743 if (atomic_read(&kvm->online_vcpus))
3744 goto create_irqchip_unlock;
1fe779f8 3745 r = -ENOMEM;
3ddea128
MT		 3746 vpic = kvm_create_pic(kvm);
3747 if (vpic) {
1fe779f8
CO		 3748 r = kvm_ioapic_init(kvm);
3749 if (r) {
175504cd 3750 mutex_lock(&kvm->slots_lock);
71ba994c 3751 kvm_destroy_pic(vpic);
175504cd 3752 mutex_unlock(&kvm->slots_lock);
3ddea128 3753 goto create_irqchip_unlock;
1fe779f8
CO		 3754 }
3755 } else
3ddea128 3756 goto create_irqchip_unlock;
399ec807
AK		 3757 r = kvm_setup_default_irq_routing(kvm);
3758 if (r) {
175504cd 3759 mutex_lock(&kvm->slots_lock);
3ddea128 3760 mutex_lock(&kvm->irq_lock);
72bb2fcd 3761 kvm_ioapic_destroy(kvm);
71ba994c 3762 kvm_destroy_pic(vpic);
3ddea128 3763 mutex_unlock(&kvm->irq_lock);
175504cd 3764 mutex_unlock(&kvm->slots_lock);
71ba994c 3765 goto create_irqchip_unlock;
399ec807 3766 }
71ba994c
PB		 3767 /* Write kvm->irq_routing before kvm->arch.vpic. */
3768 smp_wmb();
3769 kvm->arch.vpic = vpic;
3ddea128
MT		 3770 create_irqchip_unlock:
3771 mutex_unlock(&kvm->lock);
1fe779f8 3772 break;
3ddea128 3773 }
7837699f 3774 case KVM_CREATE_PIT:
c5ff41ce
JK		 3775 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3776 goto create_pit;
3777 case KVM_CREATE_PIT2:
3778 r = -EFAULT;
3779 if (copy_from_user(&u.pit_config, argp,
3780 sizeof(struct kvm_pit_config)))
3781 goto out;
3782 create_pit:
79fac95e 3783 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3784 r = -EEXIST;
3785 if (kvm->arch.vpit)
3786 goto create_pit_unlock;
7837699f 3787 r = -ENOMEM;
c5ff41ce 3788 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3789 if (kvm->arch.vpit)
3790 r = 0;
269e05e4 3791 create_pit_unlock:
79fac95e 3792 mutex_unlock(&kvm->slots_lock);
7837699f 3793 break;
1fe779f8
CO		 3794 case KVM_GET_IRQCHIP: {
3795 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3796 struct kvm_irqchip *chip;
1fe779f8 3797
ff5c2c03
SL		 3798 chip = memdup_user(argp, sizeof(*chip));
3799 if (IS_ERR(chip)) {
3800 r = PTR_ERR(chip);
1fe779f8 3801 goto out;
ff5c2c03
SL		 3802 }
3803
1fe779f8 3804 r = -ENXIO;
49df6397 3805 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3806 goto get_irqchip_out;
3807 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3808 if (r)
f0d66275 3809 goto get_irqchip_out;
1fe779f8 3810 r = -EFAULT;
f0d66275
DH		 3811 if (copy_to_user(argp, chip, sizeof *chip))
3812 goto get_irqchip_out;
1fe779f8 3813 r = 0;
f0d66275
DH		 3814 get_irqchip_out:
3815 kfree(chip);
1fe779f8
CO		 3816 break;
3817 }
3818 case KVM_SET_IRQCHIP: {
3819 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3820 struct kvm_irqchip *chip;
1fe779f8 3821
ff5c2c03
SL		 3822 chip = memdup_user(argp, sizeof(*chip));
3823 if (IS_ERR(chip)) {
3824 r = PTR_ERR(chip);
1fe779f8 3825 goto out;
ff5c2c03
SL		 3826 }
3827
1fe779f8 3828 r = -ENXIO;
49df6397 3829 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3830 goto set_irqchip_out;
3831 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3832 if (r)
f0d66275 3833 goto set_irqchip_out;
1fe779f8 3834 r = 0;
f0d66275
DH		 3835 set_irqchip_out:
3836 kfree(chip);
1fe779f8
CO		 3837 break;
3838 }
e0f63cb9 3839 case KVM_GET_PIT: {
e0f63cb9 3840 r = -EFAULT;
f0d66275 3841 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3842 goto out;
3843 r = -ENXIO;
3844 if (!kvm->arch.vpit)
3845 goto out;
f0d66275 3846 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3847 if (r)
3848 goto out;
3849 r = -EFAULT;
f0d66275 3850 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3851 goto out;
3852 r = 0;
3853 break;
3854 }
3855 case KVM_SET_PIT: {
e0f63cb9 3856 r = -EFAULT;
f0d66275 3857 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3858 goto out;
3859 r = -ENXIO;
3860 if (!kvm->arch.vpit)
3861 goto out;
f0d66275 3862 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3863 break;
3864 }
e9f42757
BK		 3865 case KVM_GET_PIT2: {
3866 r = -ENXIO;
3867 if (!kvm->arch.vpit)
3868 goto out;
3869 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3870 if (r)
3871 goto out;
3872 r = -EFAULT;
3873 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3874 goto out;
3875 r = 0;
3876 break;
3877 }
3878 case KVM_SET_PIT2: {
3879 r = -EFAULT;
3880 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3881 goto out;
3882 r = -ENXIO;
3883 if (!kvm->arch.vpit)
3884 goto out;
3885 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3886 break;
3887 }
52d939a0
MT		 3888 case KVM_REINJECT_CONTROL: {
3889 struct kvm_reinject_control control;
3890 r = -EFAULT;
3891 if (copy_from_user(&control, argp, sizeof(control)))
3892 goto out;
3893 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3894 break;
3895 }
d71ba788
PB		 3896 case KVM_SET_BOOT_CPU_ID:
3897 r = 0;
3898 mutex_lock(&kvm->lock);
3899 if (atomic_read(&kvm->online_vcpus) != 0)
3900 r = -EBUSY;
3901 else
3902 kvm->arch.bsp_vcpu_id = arg;
3903 mutex_unlock(&kvm->lock);
3904 break;
ffde22ac
ES		 3905 case KVM_XEN_HVM_CONFIG: {
3906 r = -EFAULT;
3907 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3908 sizeof(struct kvm_xen_hvm_config)))
3909 goto out;
3910 r = -EINVAL;
3911 if (kvm->arch.xen_hvm_config.flags)
3912 goto out;
3913 r = 0;
3914 break;
3915 }
afbcf7ab 3916 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3917 struct kvm_clock_data user_ns;
3918 u64 now_ns;
3919 s64 delta;
3920
3921 r = -EFAULT;
3922 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3923 goto out;
3924
3925 r = -EINVAL;
3926 if (user_ns.flags)
3927 goto out;
3928
3929 r = 0;
395c6b0a 3930 local_irq_disable();
759379dd 3931 now_ns = get_kernel_ns();
afbcf7ab 3932 delta = user_ns.clock - now_ns;
395c6b0a 3933 local_irq_enable();
afbcf7ab 3934 kvm->arch.kvmclock_offset = delta;
2e762ff7 3935 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3936 break;
3937 }
3938 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3939 struct kvm_clock_data user_ns;
3940 u64 now_ns;
3941
395c6b0a 3942 local_irq_disable();
759379dd 3943 now_ns = get_kernel_ns();
afbcf7ab 3944 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3945 local_irq_enable();
afbcf7ab 3946 user_ns.flags = 0;
97e69aa6 3947 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3948
3949 r = -EFAULT;
3950 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3951 goto out;
3952 r = 0;
3953 break;
3954 }
90de4a18
NA		 3955 case KVM_ENABLE_CAP: {
3956 struct kvm_enable_cap cap;
afbcf7ab 3957
90de4a18
NA		 3958 r = -EFAULT;
3959 if (copy_from_user(&cap, argp, sizeof(cap)))
3960 goto out;
3961 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3962 break;
3963 }
1fe779f8 3964 default:
c274e03a 3965 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3966 }
3967out:
3968 return r;
3969}
3970
a16b043c 3971static void kvm_init_msr_list(void)
043405e1
CO		 3972{
3973 u32 dummy[2];
3974 unsigned i, j;
3975
62ef68bb 3976 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3977 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3978 continue;
93c4adc7
PB		 3979
3980 /*
3981 * Even MSRs that are valid in the host may not be exposed
3982 * to the guests in some cases. We could work around this
3983 * in VMX with the generic MSR save/load machinery, but it
3984 * is not really worthwhile since it will really only
3985 * happen with nested virtualization.
3986 */
3987 switch (msrs_to_save[i]) {
3988 case MSR_IA32_BNDCFGS:
3989 if (!kvm_x86_ops->mpx_supported())
3990 continue;
3991 break;
3992 default:
3993 break;
3994 }
3995
043405e1
CO		 3996 if (j < i)
3997 msrs_to_save[j] = msrs_to_save[i];
3998 j++;
3999 }
4000 num_msrs_to_save = j;
62ef68bb
PB		 4001
4002 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4003 switch (emulated_msrs[i]) {
6d396b55
PB		 4004 case MSR_IA32_SMBASE:
4005 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4006 continue;
4007 break;
62ef68bb
PB		 4008 default:
4009 break;
4010 }
4011
4012 if (j < i)
4013 emulated_msrs[j] = emulated_msrs[i];
4014 j++;
4015 }
4016 num_emulated_msrs = j;
043405e1
CO		 4017}
4018
bda9020e
MT		 4019static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4020 const void *v)
bbd9b64e 4021{
70252a10
AK		 4022 int handled = 0;
4023 int n;
4024
4025 do {
4026 n = min(len, 8);
4027 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4028 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4029 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4030 break;
4031 handled += n;
4032 addr += n;
4033 len -= n;
4034 v += n;
4035 } while (len);
bbd9b64e 4036
70252a10 4037 return handled;
bbd9b64e
CO		 4038}
4039
bda9020e 4040static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4041{
70252a10
AK		 4042 int handled = 0;
4043 int n;
4044
4045 do {
4046 n = min(len, 8);
4047 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4048 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4049 addr, n, v))
4050 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4051 break;
4052 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4053 handled += n;
4054 addr += n;
4055 len -= n;
4056 v += n;
4057 } while (len);
bbd9b64e 4058
70252a10 4059 return handled;
bbd9b64e
CO		 4060}
4061
2dafc6c2
GN		 4062static void kvm_set_segment(struct kvm_vcpu *vcpu,
4063 struct kvm_segment *var, int seg)
4064{
4065 kvm_x86_ops->set_segment(vcpu, var, seg);
4066}
4067
4068void kvm_get_segment(struct kvm_vcpu *vcpu,
4069 struct kvm_segment *var, int seg)
4070{
4071 kvm_x86_ops->get_segment(vcpu, var, seg);
4072}
4073
54987b7a
PB		 4074gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4075 struct x86_exception *exception)
02f59dc9
JR		 4076{
4077 gpa_t t_gpa;
02f59dc9
JR		 4078
4079 BUG_ON(!mmu_is_nested(vcpu));
4080
4081 /* NPT walks are always user-walks */
4082 access |= PFERR_USER_MASK;
54987b7a 4083 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4084
4085 return t_gpa;
4086}
4087
ab9ae313
AK		 4088gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4089 struct x86_exception *exception)
1871c602
GN		 4090{
4091 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4092 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4093}
4094
ab9ae313
AK		 4095 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4096 struct x86_exception *exception)
1871c602
GN		 4097{
4098 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4099 access |= PFERR_FETCH_MASK;
ab9ae313 4100 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4101}
4102
ab9ae313
AK		 4103gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4104 struct x86_exception *exception)
1871c602
GN		 4105{
4106 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4107 access |= PFERR_WRITE_MASK;
ab9ae313 4108 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4109}
4110
4111/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4112gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4113 struct x86_exception *exception)
1871c602 4114{
ab9ae313 4115 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4116}
4117
4118static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4119 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4120 struct x86_exception *exception)
bbd9b64e
CO		 4121{
4122 void *data = val;
10589a46 4123 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4124
4125 while (bytes) {
14dfe855 4126 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4127 exception);
bbd9b64e 4128 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4129 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4130 int ret;
4131
bcc55cba 4132 if (gpa == UNMAPPED_GVA)
ab9ae313 4133 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4134 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4135 offset, toread);
10589a46 4136 if (ret < 0) {
c3cd7ffa 4137 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4138 goto out;
4139 }
bbd9b64e 4140
77c2002e
IE		 4141 bytes -= toread;
4142 data += toread;
4143 addr += toread;
bbd9b64e 4144 }
10589a46 4145out:
10589a46 4146 return r;
bbd9b64e 4147}
77c2002e 4148
1871c602 4149/* used for instruction fetching */
0f65dd70
AK		 4150static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4151 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4152 struct x86_exception *exception)
1871c602 4153{
0f65dd70 4154 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4155 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4156 unsigned offset;
4157 int ret;
0f65dd70 4158
44583cba
PB		 4159 /* Inline kvm_read_guest_virt_helper for speed. */
4160 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4161 exception);
4162 if (unlikely(gpa == UNMAPPED_GVA))
4163 return X86EMUL_PROPAGATE_FAULT;
4164
4165 offset = addr & (PAGE_SIZE-1);
4166 if (WARN_ON(offset + bytes > PAGE_SIZE))
4167 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4168 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4169 offset, bytes);
44583cba
PB		 4170 if (unlikely(ret < 0))
4171 return X86EMUL_IO_NEEDED;
4172
4173 return X86EMUL_CONTINUE;
1871c602
GN		 4174}
4175
064aea77 4176int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4177 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4178 struct x86_exception *exception)
1871c602 4179{
0f65dd70 4180 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4181 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4182
1871c602 4183 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4184 exception);
1871c602 4185}
064aea77 4186EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4187
0f65dd70
AK		 4188static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4189 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4190 struct x86_exception *exception)
1871c602 4191{
0f65dd70 4192 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4193 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4194}
4195
7a036a6f
RK		 4196static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4197 unsigned long addr, void *val, unsigned int bytes)
4198{
4199 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4200 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4201
4202 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4203}
4204
6a4d7550 4205int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4206 gva_t addr, void *val,
2dafc6c2 4207 unsigned int bytes,
bcc55cba 4208 struct x86_exception *exception)
77c2002e 4209{
0f65dd70 4210 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4211 void *data = val;
4212 int r = X86EMUL_CONTINUE;
4213
4214 while (bytes) {
14dfe855
JR		 4215 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4216 PFERR_WRITE_MASK,
ab9ae313 4217 exception);
77c2002e
IE		 4218 unsigned offset = addr & (PAGE_SIZE-1);
4219 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4220 int ret;
4221
bcc55cba 4222 if (gpa == UNMAPPED_GVA)
ab9ae313 4223 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4224 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4225 if (ret < 0) {
c3cd7ffa 4226 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4227 goto out;
4228 }
4229
4230 bytes -= towrite;
4231 data += towrite;
4232 addr += towrite;
4233 }
4234out:
4235 return r;
4236}
6a4d7550 4237EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4238
af7cc7d1
XG		 4239static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4240 gpa_t *gpa, struct x86_exception *exception,
4241 bool write)
4242{
97d64b78
AK		 4243 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4244 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4245
97d64b78 4246 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4247 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4248 vcpu->arch.access, access)) {
bebb106a
XG		 4249 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4250 (gva & (PAGE_SIZE - 1));
4f022648 4251 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4252 return 1;
4253 }
4254
af7cc7d1
XG		 4255 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4256
4257 if (*gpa == UNMAPPED_GVA)
4258 return -1;
4259
4260 /* For APIC access vmexit */
4261 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4262 return 1;
4263
4f022648
XG		 4264 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4265 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4266 return 1;
4f022648 4267 }
bebb106a 4268
af7cc7d1
XG		 4269 return 0;
4270}
4271
3200f405 4272int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4273 const void *val, int bytes)
bbd9b64e
CO		 4274{
4275 int ret;
4276
54bf36aa 4277 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4278 if (ret < 0)
bbd9b64e 4279 return 0;
f57f2ef5 4280 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4281 return 1;
4282}
4283
77d197b2
XG		 4284struct read_write_emulator_ops {
4285 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4286 int bytes);
4287 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4288 void *val, int bytes);
4289 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4290 int bytes, void *val);
4291 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4292 void *val, int bytes);
4293 bool write;
4294};
4295
4296static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4297{
4298 if (vcpu->mmio_read_completed) {
77d197b2 4299 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4300 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4301 vcpu->mmio_read_completed = 0;
4302 return 1;
4303 }
4304
4305 return 0;
4306}
4307
4308static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4309 void *val, int bytes)
4310{
54bf36aa 4311 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4312}
4313
4314static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4315 void *val, int bytes)
4316{
4317 return emulator_write_phys(vcpu, gpa, val, bytes);
4318}
4319
4320static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4321{
4322 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4323 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4324}
4325
4326static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4327 void *val, int bytes)
4328{
4329 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4330 return X86EMUL_IO_NEEDED;
4331}
4332
4333static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4334 void *val, int bytes)
4335{
f78146b0
AK		 4336 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4337
87da7e66 4338 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4339 return X86EMUL_CONTINUE;
4340}
4341
0fbe9b0b 4342static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4343 .read_write_prepare = read_prepare,
4344 .read_write_emulate = read_emulate,
4345 .read_write_mmio = vcpu_mmio_read,
4346 .read_write_exit_mmio = read_exit_mmio,
4347};
4348
0fbe9b0b 4349static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4350 .read_write_emulate = write_emulate,
4351 .read_write_mmio = write_mmio,
4352 .read_write_exit_mmio = write_exit_mmio,
4353 .write = true,
4354};
4355
22388a3c
XG		 4356static int emulator_read_write_onepage(unsigned long addr, void *val,
4357 unsigned int bytes,
4358 struct x86_exception *exception,
4359 struct kvm_vcpu *vcpu,
0fbe9b0b 4360 const struct read_write_emulator_ops *ops)
bbd9b64e 4361{
af7cc7d1
XG		 4362 gpa_t gpa;
4363 int handled, ret;
22388a3c 4364 bool write = ops->write;
f78146b0 4365 struct kvm_mmio_fragment *frag;
10589a46 4366
22388a3c 4367 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4368
af7cc7d1 4369 if (ret < 0)
bbd9b64e 4370 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4371
4372 /* For APIC access vmexit */
af7cc7d1 4373 if (ret)
bbd9b64e
CO		 4374 goto mmio;
4375
22388a3c 4376 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4377 return X86EMUL_CONTINUE;
4378
4379mmio:
4380 /*
4381 * Is this MMIO handled locally?
4382 */
22388a3c 4383 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4384 if (handled == bytes)
bbd9b64e 4385 return X86EMUL_CONTINUE;
bbd9b64e 4386
70252a10
AK		 4387 gpa += handled;
4388 bytes -= handled;
4389 val += handled;
4390
87da7e66
XG		 4391 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4392 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4393 frag->gpa = gpa;
4394 frag->data = val;
4395 frag->len = bytes;
f78146b0 4396 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4397}
4398
52eb5a6d
XL		 4399static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4400 unsigned long addr,
22388a3c
XG		 4401 void *val, unsigned int bytes,
4402 struct x86_exception *exception,
0fbe9b0b 4403 const struct read_write_emulator_ops *ops)
bbd9b64e 4404{
0f65dd70 4405 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4406 gpa_t gpa;
4407 int rc;
4408
4409 if (ops->read_write_prepare &&
4410 ops->read_write_prepare(vcpu, val, bytes))
4411 return X86EMUL_CONTINUE;
4412
4413 vcpu->mmio_nr_fragments = 0;
0f65dd70 4414
bbd9b64e
CO		 4415 /* Crossing a page boundary? */
4416 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4417 int now;
bbd9b64e
CO		 4418
4419 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4420 rc = emulator_read_write_onepage(addr, val, now, exception,
4421 vcpu, ops);
4422
bbd9b64e
CO		 4423 if (rc != X86EMUL_CONTINUE)
4424 return rc;
4425 addr += now;
bac15531
NA		 4426 if (ctxt->mode != X86EMUL_MODE_PROT64)
4427 addr = (u32)addr;
bbd9b64e
CO		 4428 val += now;
4429 bytes -= now;
4430 }
22388a3c 4431
f78146b0
AK		 4432 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4433 vcpu, ops);
4434 if (rc != X86EMUL_CONTINUE)
4435 return rc;
4436
4437 if (!vcpu->mmio_nr_fragments)
4438 return rc;
4439
4440 gpa = vcpu->mmio_fragments[0].gpa;
4441
4442 vcpu->mmio_needed = 1;
4443 vcpu->mmio_cur_fragment = 0;
4444
87da7e66 4445 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4446 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4447 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4448 vcpu->run->mmio.phys_addr = gpa;
4449
4450 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4451}
4452
4453static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4454 unsigned long addr,
4455 void *val,
4456 unsigned int bytes,
4457 struct x86_exception *exception)
4458{
4459 return emulator_read_write(ctxt, addr, val, bytes,
4460 exception, &read_emultor);
4461}
4462
52eb5a6d 4463static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4464 unsigned long addr,
4465 const void *val,
4466 unsigned int bytes,
4467 struct x86_exception *exception)
4468{
4469 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4470 exception, &write_emultor);
bbd9b64e 4471}
bbd9b64e 4472
daea3e73
AK		 4473#define CMPXCHG_TYPE(t, ptr, old, new) \
4474 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4475
4476#ifdef CONFIG_X86_64
4477# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4478#else
4479# define CMPXCHG64(ptr, old, new) \
9749a6c0 4480 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4481#endif
4482
0f65dd70
AK		 4483static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4484 unsigned long addr,
bbd9b64e
CO		 4485 const void *old,
4486 const void *new,
4487 unsigned int bytes,
0f65dd70 4488 struct x86_exception *exception)
bbd9b64e 4489{
0f65dd70 4490 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4491 gpa_t gpa;
4492 struct page *page;
4493 char *kaddr;
4494 bool exchanged;
2bacc55c 4495
daea3e73
AK		 4496 /* guests cmpxchg8b have to be emulated atomically */
4497 if (bytes > 8 || (bytes & (bytes - 1)))
4498 goto emul_write;
10589a46 4499
daea3e73 4500 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4501
daea3e73
AK		 4502 if (gpa == UNMAPPED_GVA ||
4503 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4504 goto emul_write;
2bacc55c 4505
daea3e73
AK		 4506 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4507 goto emul_write;
72dc67a6 4508
54bf36aa 4509 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4510 if (is_error_page(page))
c19b8bd6 4511 goto emul_write;
72dc67a6 4512
8fd75e12 4513 kaddr = kmap_atomic(page);
daea3e73
AK		 4514 kaddr += offset_in_page(gpa);
4515 switch (bytes) {
4516 case 1:
4517 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4518 break;
4519 case 2:
4520 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4521 break;
4522 case 4:
4523 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4524 break;
4525 case 8:
4526 exchanged = CMPXCHG64(kaddr, old, new);
4527 break;
4528 default:
4529 BUG();
2bacc55c 4530 }
8fd75e12 4531 kunmap_atomic(kaddr);
daea3e73
AK		 4532 kvm_release_page_dirty(page);
4533
4534 if (!exchanged)
4535 return X86EMUL_CMPXCHG_FAILED;
4536
54bf36aa 4537 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4538 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4539
4540 return X86EMUL_CONTINUE;
4a5f48f6 4541
3200f405 4542emul_write:
daea3e73 4543 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4544
0f65dd70 4545 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4546}
4547
cf8f70bf
GN		 4548static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4549{
4550 /* TODO: String I/O for in kernel device */
4551 int r;
4552
4553 if (vcpu->arch.pio.in)
e32edf4f 4554 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4555 vcpu->arch.pio.size, pd);
4556 else
e32edf4f 4557 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4558 vcpu->arch.pio.port, vcpu->arch.pio.size,
4559 pd);
4560 return r;
4561}
4562
6f6fbe98
XG		 4563static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4564 unsigned short port, void *val,
4565 unsigned int count, bool in)
cf8f70bf 4566{
cf8f70bf 4567 vcpu->arch.pio.port = port;
6f6fbe98 4568 vcpu->arch.pio.in = in;
7972995b 4569 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4570 vcpu->arch.pio.size = size;
4571
4572 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4573 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4574 return 1;
4575 }
4576
4577 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4578 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4579 vcpu->run->io.size = size;
4580 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4581 vcpu->run->io.count = count;
4582 vcpu->run->io.port = port;
4583
4584 return 0;
4585}
4586
6f6fbe98
XG		 4587static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4588 int size, unsigned short port, void *val,
4589 unsigned int count)
cf8f70bf 4590{
ca1d4a9e 4591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4592 int ret;
ca1d4a9e 4593
6f6fbe98
XG		 4594 if (vcpu->arch.pio.count)
4595 goto data_avail;
cf8f70bf 4596
6f6fbe98
XG		 4597 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4598 if (ret) {
4599data_avail:
4600 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4601 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4602 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4603 return 1;
4604 }
4605
cf8f70bf
GN		 4606 return 0;
4607}
4608
6f6fbe98
XG		 4609static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4610 int size, unsigned short port,
4611 const void *val, unsigned int count)
4612{
4613 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4614
4615 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4616 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4617 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4618}
4619
bbd9b64e
CO		 4620static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4621{
4622 return kvm_x86_ops->get_segment_base(vcpu, seg);
4623}
4624
3cb16fe7 4625static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4626{
3cb16fe7 4627 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4628}
4629
5cb56059 4630int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4631{
4632 if (!need_emulate_wbinvd(vcpu))
4633 return X86EMUL_CONTINUE;
4634
4635 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4636 int cpu = get_cpu();
4637
4638 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4639 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4640 wbinvd_ipi, NULL, 1);
2eec7343 4641 put_cpu();
f5f48ee1 4642 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4643 } else
4644 wbinvd();
f5f48ee1
SY		 4645 return X86EMUL_CONTINUE;
4646}
5cb56059
JS		 4647
4648int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4649{
4650 kvm_x86_ops->skip_emulated_instruction(vcpu);
4651 return kvm_emulate_wbinvd_noskip(vcpu);
4652}
f5f48ee1
SY		 4653EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4654
5cb56059
JS		 4655
4656
bcaf5cc5
AK		 4657static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4658{
5cb56059 4659 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4660}
4661
52eb5a6d
XL		 4662static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4663 unsigned long *dest)
bbd9b64e 4664{
16f8a6f9 4665 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4666}
4667
52eb5a6d
XL		 4668static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4669 unsigned long value)
bbd9b64e 4670{
338dbc97 4671
717746e3 4672 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4673}
4674
52a46617 4675static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4676{
52a46617 4677 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4678}
4679
717746e3 4680static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4681{
717746e3 4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4683 unsigned long value;
4684
4685 switch (cr) {
4686 case 0:
4687 value = kvm_read_cr0(vcpu);
4688 break;
4689 case 2:
4690 value = vcpu->arch.cr2;
4691 break;
4692 case 3:
9f8fe504 4693 value = kvm_read_cr3(vcpu);
52a46617
GN		 4694 break;
4695 case 4:
4696 value = kvm_read_cr4(vcpu);
4697 break;
4698 case 8:
4699 value = kvm_get_cr8(vcpu);
4700 break;
4701 default:
a737f256 4702 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4703 return 0;
4704 }
4705
4706 return value;
4707}
4708
717746e3 4709static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4710{
717746e3 4711 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4712 int res = 0;
4713
52a46617
GN		 4714 switch (cr) {
4715 case 0:
49a9b07e 4716 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4717 break;
4718 case 2:
4719 vcpu->arch.cr2 = val;
4720 break;
4721 case 3:
2390218b 4722 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4723 break;
4724 case 4:
a83b29c6 4725 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4726 break;
4727 case 8:
eea1cff9 4728 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4729 break;
4730 default:
a737f256 4731 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4732 res = -1;
52a46617 4733 }
0f12244f
GN		 4734
4735 return res;
52a46617
GN		 4736}
4737
717746e3 4738static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4739{
717746e3 4740 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4741}
4742
4bff1e86 4743static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4744{
4bff1e86 4745 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4746}
4747
4bff1e86 4748static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4749{
4bff1e86 4750 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4751}
4752
1ac9d0cf
AK		 4753static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4754{
4755 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4756}
4757
4758static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4759{
4760 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4761}
4762
4bff1e86
AK		 4763static unsigned long emulator_get_cached_segment_base(
4764 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4765{
4bff1e86 4766 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4767}
4768
1aa36616
AK		 4769static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4770 struct desc_struct *desc, u32 *base3,
4771 int seg)
2dafc6c2
GN		 4772{
4773 struct kvm_segment var;
4774
4bff1e86 4775 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4776 *selector = var.selector;
2dafc6c2 4777
378a8b09
GN		 4778 if (var.unusable) {
4779 memset(desc, 0, sizeof(*desc));
2dafc6c2 4780 return false;
378a8b09 4781 }
2dafc6c2
GN		 4782
4783 if (var.g)
4784 var.limit >>= 12;
4785 set_desc_limit(desc, var.limit);
4786 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4787#ifdef CONFIG_X86_64
4788 if (base3)
4789 *base3 = var.base >> 32;
4790#endif
2dafc6c2
GN		 4791 desc->type = var.type;
4792 desc->s = var.s;
4793 desc->dpl = var.dpl;
4794 desc->p = var.present;
4795 desc->avl = var.avl;
4796 desc->l = var.l;
4797 desc->d = var.db;
4798 desc->g = var.g;
4799
4800 return true;
4801}
4802
1aa36616
AK		 4803static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4804 struct desc_struct *desc, u32 base3,
4805 int seg)
2dafc6c2 4806{
4bff1e86 4807 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4808 struct kvm_segment var;
4809
1aa36616 4810 var.selector = selector;
2dafc6c2 4811 var.base = get_desc_base(desc);
5601d05b
GN		 4812#ifdef CONFIG_X86_64
4813 var.base |= ((u64)base3) << 32;
4814#endif
2dafc6c2
GN		 4815 var.limit = get_desc_limit(desc);
4816 if (desc->g)
4817 var.limit = (var.limit << 12) | 0xfff;
4818 var.type = desc->type;
2dafc6c2
GN		 4819 var.dpl = desc->dpl;
4820 var.db = desc->d;
4821 var.s = desc->s;
4822 var.l = desc->l;
4823 var.g = desc->g;
4824 var.avl = desc->avl;
4825 var.present = desc->p;
4826 var.unusable = !var.present;
4827 var.padding = 0;
4828
4829 kvm_set_segment(vcpu, &var, seg);
4830 return;
4831}
4832
717746e3
AK		 4833static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4834 u32 msr_index, u64 *pdata)
4835{
609e36d3
PB		 4836 struct msr_data msr;
4837 int r;
4838
4839 msr.index = msr_index;
4840 msr.host_initiated = false;
4841 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4842 if (r)
4843 return r;
4844
4845 *pdata = msr.data;
4846 return 0;
717746e3
AK		 4847}
4848
4849static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4850 u32 msr_index, u64 data)
4851{
8fe8ab46
WA		 4852 struct msr_data msr;
4853
4854 msr.data = data;
4855 msr.index = msr_index;
4856 msr.host_initiated = false;
4857 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4858}
4859
64d60670
PB		 4860static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4861{
4862 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4863
4864 return vcpu->arch.smbase;
4865}
4866
4867static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4868{
4869 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4870
4871 vcpu->arch.smbase = smbase;
4872}
4873
67f4d428
NA		 4874static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4875 u32 pmc)
4876{
c6702c9d 4877 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4878}
4879
222d21aa
AK		 4880static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4881 u32 pmc, u64 *pdata)
4882{
c6702c9d 4883 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4884}
4885
6c3287f7
AK		 4886static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4887{
4888 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4889}
4890
5037f6f3
AK		 4891static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4892{
4893 preempt_disable();
5197b808 4894 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4895 /*
4896 * CR0.TS may reference the host fpu state, not the guest fpu state,
4897 * so it may be clear at this point.
4898 */
4899 clts();
4900}
4901
4902static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4903{
4904 preempt_enable();
4905}
4906
2953538e 4907static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4908 struct x86_instruction_info *info,
c4f035c6
AK		 4909 enum x86_intercept_stage stage)
4910{
2953538e 4911 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4912}
4913
0017f93a 4914static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4915 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4916{
0017f93a 4917 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4918}
4919
dd856efa
AK		 4920static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4921{
4922 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4923}
4924
4925static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4926{
4927 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4928}
4929
801806d9
NA		 4930static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4931{
4932 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4933}
4934
0225fb50 4935static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4936 .read_gpr = emulator_read_gpr,
4937 .write_gpr = emulator_write_gpr,
1871c602 4938 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4939 .write_std = kvm_write_guest_virt_system,
7a036a6f 4940 .read_phys = kvm_read_guest_phys_system,
1871c602 4941 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4942 .read_emulated = emulator_read_emulated,
4943 .write_emulated = emulator_write_emulated,
4944 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4945 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4946 .pio_in_emulated = emulator_pio_in_emulated,
4947 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4948 .get_segment = emulator_get_segment,
4949 .set_segment = emulator_set_segment,
5951c442 4950 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4951 .get_gdt = emulator_get_gdt,
160ce1f1 4952 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4953 .set_gdt = emulator_set_gdt,
4954 .set_idt = emulator_set_idt,
52a46617
GN		 4955 .get_cr = emulator_get_cr,
4956 .set_cr = emulator_set_cr,
9c537244 4957 .cpl = emulator_get_cpl,
35aa5375
GN		 4958 .get_dr = emulator_get_dr,
4959 .set_dr = emulator_set_dr,
64d60670
PB		 4960 .get_smbase = emulator_get_smbase,
4961 .set_smbase = emulator_set_smbase,
717746e3
AK		 4962 .set_msr = emulator_set_msr,
4963 .get_msr = emulator_get_msr,
67f4d428 4964 .check_pmc = emulator_check_pmc,
222d21aa 4965 .read_pmc = emulator_read_pmc,
6c3287f7 4966 .halt = emulator_halt,
bcaf5cc5 4967 .wbinvd = emulator_wbinvd,
d6aa1000 4968 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4969 .get_fpu = emulator_get_fpu,
4970 .put_fpu = emulator_put_fpu,
c4f035c6 4971 .intercept = emulator_intercept,
bdb42f5a 4972 .get_cpuid = emulator_get_cpuid,
801806d9 4973 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4974};
4975
95cb2295
GN		 4976static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4977{
37ccdcbe 4978 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4979 /*
4980 * an sti; sti; sequence only disable interrupts for the first
4981 * instruction. So, if the last instruction, be it emulated or
4982 * not, left the system with the INT_STI flag enabled, it
4983 * means that the last instruction is an sti. We should not
4984 * leave the flag on in this case. The same goes for mov ss
4985 */
37ccdcbe
PB		 4986 if (int_shadow & mask)
4987 mask = 0;
6addfc42 4988 if (unlikely(int_shadow || mask)) {
95cb2295 4989 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4990 if (!mask)
4991 kvm_make_request(KVM_REQ_EVENT, vcpu);
4992 }
95cb2295
GN		 4993}
4994
ef54bcfe 4995static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4996{
4997 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4998 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4999 return kvm_propagate_fault(vcpu, &ctxt->exception);
5000
5001 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5002 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5003 ctxt->exception.error_code);
54b8486f 5004 else
da9cb575 5005 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5006 return false;
54b8486f
GN		 5007}
5008
8ec4722d
MG		 5009static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5010{
adf52235 5011 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5012 int cs_db, cs_l;
5013
8ec4722d
MG		 5014 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5015
adf52235
TY		 5016 ctxt->eflags = kvm_get_rflags(vcpu);
5017 ctxt->eip = kvm_rip_read(vcpu);
5018 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5019 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5020 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5021 cs_db ? X86EMUL_MODE_PROT32 :
5022 X86EMUL_MODE_PROT16;
a584539b 5023 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5024 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5025 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5026 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5027
dd856efa 5028 init_decode_cache(ctxt);
7ae441ea 5029 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5030}
5031
71f9833b 5032int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5033{
9d74191a 5034 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5035 int ret;
5036
5037 init_emulate_ctxt(vcpu);
5038
9dac77fa
AK		 5039 ctxt->op_bytes = 2;
5040 ctxt->ad_bytes = 2;
5041 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5042 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5043
5044 if (ret != X86EMUL_CONTINUE)
5045 return EMULATE_FAIL;
5046
9dac77fa 5047 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5048 kvm_rip_write(vcpu, ctxt->eip);
5049 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5050
5051 if (irq == NMI_VECTOR)
7460fb4a 5052 vcpu->arch.nmi_pending = 0;
63995653
MG		 5053 else
5054 vcpu->arch.interrupt.pending = false;
5055
5056 return EMULATE_DONE;
5057}
5058EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5059
6d77dbfc
GN		 5060static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5061{
fc3a9157
JR		 5062 int r = EMULATE_DONE;
5063
6d77dbfc
GN		 5064 ++vcpu->stat.insn_emulation_fail;
5065 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5066 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5067 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5068 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5069 vcpu->run->internal.ndata = 0;
5070 r = EMULATE_FAIL;
5071 }
6d77dbfc 5072 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5073
5074 return r;
6d77dbfc
GN		 5075}
5076
93c05d3e 5077static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5078 bool write_fault_to_shadow_pgtable,
5079 int emulation_type)
a6f177ef 5080{
95b3cf69 5081 gpa_t gpa = cr2;
8e3d9d06 5082 pfn_t pfn;
a6f177ef 5083
991eebf9
GN		 5084 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5085 return false;
5086
95b3cf69
XG		 5087 if (!vcpu->arch.mmu.direct_map) {
5088 /*
5089 * Write permission should be allowed since only
5090 * write access need to be emulated.
5091 */
5092 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5093
95b3cf69
XG		 5094 /*
5095 * If the mapping is invalid in guest, let cpu retry
5096 * it to generate fault.
5097 */
5098 if (gpa == UNMAPPED_GVA)
5099 return true;
5100 }
a6f177ef 5101
8e3d9d06
XG		 5102 /*
5103 * Do not retry the unhandleable instruction if it faults on the
5104 * readonly host memory, otherwise it will goto a infinite loop:
5105 * retry instruction -> write #PF -> emulation fail -> retry
5106 * instruction -> ...
5107 */
5108 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5109
5110 /*
5111 * If the instruction failed on the error pfn, it can not be fixed,
5112 * report the error to userspace.
5113 */
5114 if (is_error_noslot_pfn(pfn))
5115 return false;
5116
5117 kvm_release_pfn_clean(pfn);
5118
5119 /* The instructions are well-emulated on direct mmu. */
5120 if (vcpu->arch.mmu.direct_map) {
5121 unsigned int indirect_shadow_pages;
5122
5123 spin_lock(&vcpu->kvm->mmu_lock);
5124 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5125 spin_unlock(&vcpu->kvm->mmu_lock);
5126
5127 if (indirect_shadow_pages)
5128 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5129
a6f177ef 5130 return true;
8e3d9d06 5131 }
a6f177ef 5132
95b3cf69
XG		 5133 /*
5134 * if emulation was due to access to shadowed page table
5135 * and it failed try to unshadow page and re-enter the
5136 * guest to let CPU execute the instruction.
5137 */
5138 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5139
5140 /*
5141 * If the access faults on its page table, it can not
5142 * be fixed by unprotecting shadow page and it should
5143 * be reported to userspace.
5144 */
5145 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5146}
5147
1cb3f3ae
XG		 5148static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5149 unsigned long cr2, int emulation_type)
5150{
5151 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5152 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5153
5154 last_retry_eip = vcpu->arch.last_retry_eip;
5155 last_retry_addr = vcpu->arch.last_retry_addr;
5156
5157 /*
5158 * If the emulation is caused by #PF and it is non-page_table
5159 * writing instruction, it means the VM-EXIT is caused by shadow
5160 * page protected, we can zap the shadow page and retry this
5161 * instruction directly.
5162 *
5163 * Note: if the guest uses a non-page-table modifying instruction
5164 * on the PDE that points to the instruction, then we will unmap
5165 * the instruction and go to an infinite loop. So, we cache the
5166 * last retried eip and the last fault address, if we meet the eip
5167 * and the address again, we can break out of the potential infinite
5168 * loop.
5169 */
5170 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5171
5172 if (!(emulation_type & EMULTYPE_RETRY))
5173 return false;
5174
5175 if (x86_page_table_writing_insn(ctxt))
5176 return false;
5177
5178 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5179 return false;
5180
5181 vcpu->arch.last_retry_eip = ctxt->eip;
5182 vcpu->arch.last_retry_addr = cr2;
5183
5184 if (!vcpu->arch.mmu.direct_map)
5185 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5186
22368028 5187 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5188
5189 return true;
5190}
5191
716d51ab
GN		 5192static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5193static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5194
64d60670 5195static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5196{
64d60670 5197 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5198 /* This is a good place to trace that we are exiting SMM. */
5199 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5200
64d60670
PB		 5201 if (unlikely(vcpu->arch.smi_pending)) {
5202 kvm_make_request(KVM_REQ_SMI, vcpu);
5203 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5204 } else {
5205 /* Process a latched INIT, if any. */
5206 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5207 }
5208 }
699023e2
PB		 5209
5210 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5211}
5212
5213static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5214{
5215 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5216
a584539b 5217 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5218
5219 if (changed & HF_SMM_MASK)
5220 kvm_smm_changed(vcpu);
a584539b
PB		 5221}
5222
4a1e10d5
PB		 5223static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5224 unsigned long *db)
5225{
5226 u32 dr6 = 0;
5227 int i;
5228 u32 enable, rwlen;
5229
5230 enable = dr7;
5231 rwlen = dr7 >> 16;
5232 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5233 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5234 dr6 |= (1 << i);
5235 return dr6;
5236}
5237
6addfc42 5238static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5239{
5240 struct kvm_run *kvm_run = vcpu->run;
5241
5242 /*
6addfc42
PB		 5243 * rflags is the old, "raw" value of the flags. The new value has
5244 * not been saved yet.
663f4c61
PB		 5245 *
5246 * This is correct even for TF set by the guest, because "the
5247 * processor will not generate this exception after the instruction
5248 * that sets the TF flag".
5249 */
663f4c61
PB		 5250 if (unlikely(rflags & X86_EFLAGS_TF)) {
5251 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5252 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5253 DR6_RTM;
663f4c61
PB		 5254 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5255 kvm_run->debug.arch.exception = DB_VECTOR;
5256 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5257 *r = EMULATE_USER_EXIT;
5258 } else {
5259 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5260 /*
5261 * "Certain debug exceptions may clear bit 0-3. The
5262 * remaining contents of the DR6 register are never
5263 * cleared by the processor".
5264 */
5265 vcpu->arch.dr6 &= ~15;
6f43ed01 5266 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5267 kvm_queue_exception(vcpu, DB_VECTOR);
5268 }
5269 }
5270}
5271
4a1e10d5
PB		 5272static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5273{
4a1e10d5
PB		 5274 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5275 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5276 struct kvm_run *kvm_run = vcpu->run;
5277 unsigned long eip = kvm_get_linear_rip(vcpu);
5278 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5279 vcpu->arch.guest_debug_dr7,
5280 vcpu->arch.eff_db);
5281
5282 if (dr6 != 0) {
6f43ed01 5283 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5284 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5285 kvm_run->debug.arch.exception = DB_VECTOR;
5286 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5287 *r = EMULATE_USER_EXIT;
5288 return true;
5289 }
5290 }
5291
4161a569
NA		 5292 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5293 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5294 unsigned long eip = kvm_get_linear_rip(vcpu);
5295 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5296 vcpu->arch.dr7,
5297 vcpu->arch.db);
5298
5299 if (dr6 != 0) {
5300 vcpu->arch.dr6 &= ~15;
6f43ed01 5301 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5302 kvm_queue_exception(vcpu, DB_VECTOR);
5303 *r = EMULATE_DONE;
5304 return true;
5305 }
5306 }
5307
5308 return false;
5309}
5310
51d8b661
AP		 5311int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5312 unsigned long cr2,
dc25e89e
AP		 5313 int emulation_type,
5314 void *insn,
5315 int insn_len)
bbd9b64e 5316{
95cb2295 5317 int r;
9d74191a 5318 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5319 bool writeback = true;
93c05d3e 5320 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5321
93c05d3e
XG		 5322 /*
5323 * Clear write_fault_to_shadow_pgtable here to ensure it is
5324 * never reused.
5325 */
5326 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5327 kvm_clear_exception_queue(vcpu);
8d7d8102 5328
571008da 5329 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5330 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5331
5332 /*
5333 * We will reenter on the same instruction since
5334 * we do not set complete_userspace_io. This does not
5335 * handle watchpoints yet, those would be handled in
5336 * the emulate_ops.
5337 */
5338 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5339 return r;
5340
9d74191a
TY		 5341 ctxt->interruptibility = 0;
5342 ctxt->have_exception = false;
e0ad0b47 5343 ctxt->exception.vector = -1;
9d74191a 5344 ctxt->perm_ok = false;
bbd9b64e 5345
b51e974f 5346 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5347
9d74191a 5348 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5349
e46479f8 5350 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5351 ++vcpu->stat.insn_emulation;
1d2887e2 5352 if (r != EMULATION_OK) {
4005996e
AK		 5353 if (emulation_type & EMULTYPE_TRAP_UD)
5354 return EMULATE_FAIL;
991eebf9
GN		 5355 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5356 emulation_type))
bbd9b64e 5357 return EMULATE_DONE;
6d77dbfc
GN		 5358 if (emulation_type & EMULTYPE_SKIP)
5359 return EMULATE_FAIL;
5360 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5361 }
5362 }
5363
ba8afb6b 5364 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5365 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5366 if (ctxt->eflags & X86_EFLAGS_RF)
5367 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5368 return EMULATE_DONE;
5369 }
5370
1cb3f3ae
XG		 5371 if (retry_instruction(ctxt, cr2, emulation_type))
5372 return EMULATE_DONE;
5373
7ae441ea 5374 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5375 changes registers values during IO operation */
7ae441ea
GN		 5376 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5377 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5378 emulator_invalidate_register_cache(ctxt);
7ae441ea 5379 }
4d2179e1 5380
5cd21917 5381restart:
9d74191a 5382 r = x86_emulate_insn(ctxt);
bbd9b64e 5383
775fde86
JR		 5384 if (r == EMULATION_INTERCEPTED)
5385 return EMULATE_DONE;
5386
d2ddd1c4 5387 if (r == EMULATION_FAILED) {
991eebf9
GN		 5388 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5389 emulation_type))
c3cd7ffa
GN		 5390 return EMULATE_DONE;
5391
6d77dbfc 5392 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5393 }
5394
9d74191a 5395 if (ctxt->have_exception) {
d2ddd1c4 5396 r = EMULATE_DONE;
ef54bcfe
PB		 5397 if (inject_emulated_exception(vcpu))
5398 return r;
d2ddd1c4 5399 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5400 if (!vcpu->arch.pio.in) {
5401 /* FIXME: return into emulator if single-stepping. */
3457e419 5402 vcpu->arch.pio.count = 0;
0912c977 5403 } else {
7ae441ea 5404 writeback = false;
716d51ab
GN		 5405 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5406 }
ac0a48c3 5407 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5408 } else if (vcpu->mmio_needed) {
5409 if (!vcpu->mmio_is_write)
5410 writeback = false;
ac0a48c3 5411 r = EMULATE_USER_EXIT;
716d51ab 5412 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5413 } else if (r == EMULATION_RESTART)
5cd21917 5414 goto restart;
d2ddd1c4
GN		 5415 else
5416 r = EMULATE_DONE;
f850e2e6 5417
7ae441ea 5418 if (writeback) {
6addfc42 5419 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5420 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5421 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5422 if (vcpu->arch.hflags != ctxt->emul_flags)
5423 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5424 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5425 if (r == EMULATE_DONE)
6addfc42 5426 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5427 if (!ctxt->have_exception ||
5428 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5429 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5430
5431 /*
5432 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5433 * do nothing, and it will be requested again as soon as
5434 * the shadow expires. But we still need to check here,
5435 * because POPF has no interrupt shadow.
5436 */
5437 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5438 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5439 } else
5440 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5441
5442 return r;
de7d789a 5443}
51d8b661 5444EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5445
cf8f70bf 5446int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5447{
cf8f70bf 5448 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5449 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5450 size, port, &val, 1);
cf8f70bf 5451 /* do not return to emulator after return from userspace */
7972995b 5452 vcpu->arch.pio.count = 0;
de7d789a
CO		 5453 return ret;
5454}
cf8f70bf 5455EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5456
8cfdc000
ZA		 5457static void tsc_bad(void *info)
5458{
0a3aee0d 5459 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5460}
5461
5462static void tsc_khz_changed(void *data)
c8076604 5463{
8cfdc000
ZA		 5464 struct cpufreq_freqs *freq = data;
5465 unsigned long khz = 0;
5466
5467 if (data)
5468 khz = freq->new;
5469 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5470 khz = cpufreq_quick_get(raw_smp_processor_id());
5471 if (!khz)
5472 khz = tsc_khz;
0a3aee0d 5473 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5474}
5475
c8076604
GH		 5476static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5477 void *data)
5478{
5479 struct cpufreq_freqs *freq = data;
5480 struct kvm *kvm;
5481 struct kvm_vcpu *vcpu;
5482 int i, send_ipi = 0;
5483
8cfdc000
ZA		 5484 /*
5485 * We allow guests to temporarily run on slowing clocks,
5486 * provided we notify them after, or to run on accelerating
5487 * clocks, provided we notify them before. Thus time never
5488 * goes backwards.
5489 *
5490 * However, we have a problem. We can't atomically update
5491 * the frequency of a given CPU from this function; it is
5492 * merely a notifier, which can be called from any CPU.
5493 * Changing the TSC frequency at arbitrary points in time
5494 * requires a recomputation of local variables related to
5495 * the TSC for each VCPU. We must flag these local variables
5496 * to be updated and be sure the update takes place with the
5497 * new frequency before any guests proceed.
5498 *
5499 * Unfortunately, the combination of hotplug CPU and frequency
5500 * change creates an intractable locking scenario; the order
5501 * of when these callouts happen is undefined with respect to
5502 * CPU hotplug, and they can race with each other. As such,
5503 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5504 * undefined; you can actually have a CPU frequency change take
5505 * place in between the computation of X and the setting of the
5506 * variable. To protect against this problem, all updates of
5507 * the per_cpu tsc_khz variable are done in an interrupt
5508 * protected IPI, and all callers wishing to update the value
5509 * must wait for a synchronous IPI to complete (which is trivial
5510 * if the caller is on the CPU already). This establishes the
5511 * necessary total order on variable updates.
5512 *
5513 * Note that because a guest time update may take place
5514 * anytime after the setting of the VCPU's request bit, the
5515 * correct TSC value must be set before the request. However,
5516 * to ensure the update actually makes it to any guest which
5517 * starts running in hardware virtualization between the set
5518 * and the acquisition of the spinlock, we must also ping the
5519 * CPU after setting the request bit.
5520 *
5521 */
5522
c8076604
GH		 5523 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5524 return 0;
5525 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5526 return 0;
8cfdc000
ZA		 5527
5528 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5529
2f303b74 5530 spin_lock(&kvm_lock);
c8076604 5531 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5532 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5533 if (vcpu->cpu != freq->cpu)
5534 continue;
c285545f 5535 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5536 if (vcpu->cpu != smp_processor_id())
8cfdc000 5537 send_ipi = 1;
c8076604
GH		 5538 }
5539 }
2f303b74 5540 spin_unlock(&kvm_lock);
c8076604
GH		 5541
5542 if (freq->old < freq->new && send_ipi) {
5543 /*
5544 * We upscale the frequency. Must make the guest
5545 * doesn't see old kvmclock values while running with
5546 * the new frequency, otherwise we risk the guest sees
5547 * time go backwards.
5548 *
5549 * In case we update the frequency for another cpu
5550 * (which might be in guest context) send an interrupt
5551 * to kick the cpu out of guest context. Next time
5552 * guest context is entered kvmclock will be updated,
5553 * so the guest will not see stale values.
5554 */
8cfdc000 5555 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5556 }
5557 return 0;
5558}
5559
5560static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5561 .notifier_call = kvmclock_cpufreq_notifier
5562};
5563
5564static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5565 unsigned long action, void *hcpu)
5566{
5567 unsigned int cpu = (unsigned long)hcpu;
5568
5569 switch (action) {
5570 case CPU_ONLINE:
5571 case CPU_DOWN_FAILED:
5572 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5573 break;
5574 case CPU_DOWN_PREPARE:
5575 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5576 break;
5577 }
5578 return NOTIFY_OK;
5579}
5580
5581static struct notifier_block kvmclock_cpu_notifier_block = {
5582 .notifier_call = kvmclock_cpu_notifier,
5583 .priority = -INT_MAX
c8076604
GH		 5584};
5585
b820cc0c
ZA		 5586static void kvm_timer_init(void)
5587{
5588 int cpu;
5589
c285545f 5590 max_tsc_khz = tsc_khz;
460dd42e
SB		 5591
5592 cpu_notifier_register_begin();
b820cc0c 5593 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5594#ifdef CONFIG_CPU_FREQ
5595 struct cpufreq_policy policy;
5596 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5597 cpu = get_cpu();
5598 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5599 if (policy.cpuinfo.max_freq)
5600 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5601 put_cpu();
c285545f 5602#endif
b820cc0c
ZA		 5603 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5604 CPUFREQ_TRANSITION_NOTIFIER);
5605 }
c285545f 5606 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5607 for_each_online_cpu(cpu)
5608 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5609
5610 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5611 cpu_notifier_register_done();
5612
b820cc0c
ZA		 5613}
5614
ff9d07a0
ZY		 5615static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5616
f5132b01 5617int kvm_is_in_guest(void)
ff9d07a0 5618{
086c9855 5619 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5620}
5621
5622static int kvm_is_user_mode(void)
5623{
5624 int user_mode = 3;
dcf46b94 5625
086c9855
AS		 5626 if (__this_cpu_read(current_vcpu))
5627 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5628
ff9d07a0
ZY		 5629 return user_mode != 0;
5630}
5631
5632static unsigned long kvm_get_guest_ip(void)
5633{
5634 unsigned long ip = 0;
dcf46b94 5635
086c9855
AS		 5636 if (__this_cpu_read(current_vcpu))
5637 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5638
ff9d07a0
ZY		 5639 return ip;
5640}
5641
5642static struct perf_guest_info_callbacks kvm_guest_cbs = {
5643 .is_in_guest = kvm_is_in_guest,
5644 .is_user_mode = kvm_is_user_mode,
5645 .get_guest_ip = kvm_get_guest_ip,
5646};
5647
5648void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5649{
086c9855 5650 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5651}
5652EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5653
5654void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5655{
086c9855 5656 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5657}
5658EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5659
ce88decf
XG		 5660static void kvm_set_mmio_spte_mask(void)
5661{
5662 u64 mask;
5663 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5664
5665 /*
5666 * Set the reserved bits and the present bit of an paging-structure
5667 * entry to generate page fault with PFER.RSV = 1.
5668 */
885032b9 5669 /* Mask the reserved physical address bits. */
d1431483 5670 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5671
5672 /* Bit 62 is always reserved for 32bit host. */
5673 mask |= 0x3ull << 62;
5674
5675 /* Set the present bit. */
ce88decf
XG		 5676 mask |= 1ull;
5677
5678#ifdef CONFIG_X86_64
5679 /*
5680 * If reserved bit is not supported, clear the present bit to disable
5681 * mmio page fault.
5682 */
5683 if (maxphyaddr == 52)
5684 mask &= ~1ull;
5685#endif
5686
5687 kvm_mmu_set_mmio_spte_mask(mask);
5688}
5689
16e8d74d
MT		 5690#ifdef CONFIG_X86_64
5691static void pvclock_gtod_update_fn(struct work_struct *work)
5692{
d828199e
MT		 5693 struct kvm *kvm;
5694
5695 struct kvm_vcpu *vcpu;
5696 int i;
5697
2f303b74 5698 spin_lock(&kvm_lock);
d828199e
MT		 5699 list_for_each_entry(kvm, &vm_list, vm_list)
5700 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5701 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5702 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5703 spin_unlock(&kvm_lock);
16e8d74d
MT		 5704}
5705
5706static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5707
5708/*
5709 * Notification about pvclock gtod data update.
5710 */
5711static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5712 void *priv)
5713{
5714 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5715 struct timekeeper *tk = priv;
5716
5717 update_pvclock_gtod(tk);
5718
5719 /* disable master clock if host does not trust, or does not
5720 * use, TSC clocksource
5721 */
5722 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5723 atomic_read(&kvm_guest_has_master_clock) != 0)
5724 queue_work(system_long_wq, &pvclock_gtod_work);
5725
5726 return 0;
5727}
5728
5729static struct notifier_block pvclock_gtod_notifier = {
5730 .notifier_call = pvclock_gtod_notify,
5731};
5732#endif
5733
f8c16bba 5734int kvm_arch_init(void *opaque)
043405e1 5735{
b820cc0c 5736 int r;
6b61edf7 5737 struct kvm_x86_ops *ops = opaque;
f8c16bba 5738
f8c16bba
ZX		 5739 if (kvm_x86_ops) {
5740 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5741 r = -EEXIST;
5742 goto out;
f8c16bba
ZX		 5743 }
5744
5745 if (!ops->cpu_has_kvm_support()) {
5746 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5747 r = -EOPNOTSUPP;
5748 goto out;
f8c16bba
ZX		 5749 }
5750 if (ops->disabled_by_bios()) {
5751 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5752 r = -EOPNOTSUPP;
5753 goto out;
f8c16bba
ZX		 5754 }
5755
013f6a5d
MT		 5756 r = -ENOMEM;
5757 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5758 if (!shared_msrs) {
5759 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5760 goto out;
5761 }
5762
97db56ce
AK		 5763 r = kvm_mmu_module_init();
5764 if (r)
013f6a5d 5765 goto out_free_percpu;
97db56ce 5766
ce88decf 5767 kvm_set_mmio_spte_mask();
97db56ce 5768
f8c16bba 5769 kvm_x86_ops = ops;
920c8377 5770
7b52345e 5771 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5772 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5773
b820cc0c 5774 kvm_timer_init();
c8076604 5775
ff9d07a0
ZY		 5776 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5777
2acf923e
DC		 5778 if (cpu_has_xsave)
5779 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5780
c5cc421b 5781 kvm_lapic_init();
16e8d74d
MT		 5782#ifdef CONFIG_X86_64
5783 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5784#endif
5785
f8c16bba 5786 return 0;
56c6d28a 5787
013f6a5d
MT		 5788out_free_percpu:
5789 free_percpu(shared_msrs);
56c6d28a 5790out:
56c6d28a 5791 return r;
043405e1 5792}
8776e519 5793
f8c16bba
ZX		 5794void kvm_arch_exit(void)
5795{
ff9d07a0
ZY		 5796 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5797
888d256e
JK		 5798 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5799 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5800 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5801 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5802#ifdef CONFIG_X86_64
5803 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5804#endif
f8c16bba 5805 kvm_x86_ops = NULL;
56c6d28a 5806 kvm_mmu_module_exit();
013f6a5d 5807 free_percpu(shared_msrs);
56c6d28a 5808}
f8c16bba 5809
5cb56059 5810int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5811{
5812 ++vcpu->stat.halt_exits;
35754c98 5813 if (lapic_in_kernel(vcpu)) {
a4535290 5814 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5815 return 1;
5816 } else {
5817 vcpu->run->exit_reason = KVM_EXIT_HLT;
5818 return 0;
5819 }
5820}
5cb56059
JS		 5821EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5822
5823int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5824{
5825 kvm_x86_ops->skip_emulated_instruction(vcpu);
5826 return kvm_vcpu_halt(vcpu);
5827}
8776e519
HB		 5828EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5829
6aef266c
SV		 5830/*
5831 * kvm_pv_kick_cpu_op: Kick a vcpu.
5832 *
5833 * @apicid - apicid of vcpu to be kicked.
5834 */
5835static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5836{
24d2166b 5837 struct kvm_lapic_irq lapic_irq;
6aef266c 5838
24d2166b
R		 5839 lapic_irq.shorthand = 0;
5840 lapic_irq.dest_mode = 0;
5841 lapic_irq.dest_id = apicid;
93bbf0b8 5842 lapic_irq.msi_redir_hint = false;
6aef266c 5843
24d2166b 5844 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5845 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5846}
5847
8776e519
HB		 5848int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5849{
5850 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5851 int op_64_bit, r = 1;
8776e519 5852
5cb56059
JS		 5853 kvm_x86_ops->skip_emulated_instruction(vcpu);
5854
55cd8e5a
GN		 5855 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5856 return kvm_hv_hypercall(vcpu);
5857
5fdbf976
MT		 5858 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5859 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5860 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5861 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5862 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5863
229456fc 5864 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5865
a449c7aa
NA		 5866 op_64_bit = is_64_bit_mode(vcpu);
5867 if (!op_64_bit) {
8776e519
HB		 5868 nr &= 0xFFFFFFFF;
5869 a0 &= 0xFFFFFFFF;
5870 a1 &= 0xFFFFFFFF;
5871 a2 &= 0xFFFFFFFF;
5872 a3 &= 0xFFFFFFFF;
5873 }
5874
07708c4a
JK		 5875 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5876 ret = -KVM_EPERM;
5877 goto out;
5878 }
5879
8776e519 5880 switch (nr) {
b93463aa
AK		 5881 case KVM_HC_VAPIC_POLL_IRQ:
5882 ret = 0;
5883 break;
6aef266c
SV		 5884 case KVM_HC_KICK_CPU:
5885 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5886 ret = 0;
5887 break;
8776e519
HB		 5888 default:
5889 ret = -KVM_ENOSYS;
5890 break;
5891 }
07708c4a 5892out:
a449c7aa
NA		 5893 if (!op_64_bit)
5894 ret = (u32)ret;
5fdbf976 5895 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5896 ++vcpu->stat.hypercalls;
2f333bcb 5897 return r;
8776e519
HB		 5898}
5899EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5900
b6785def 5901static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5902{
d6aa1000 5903 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5904 char instruction[3];
5fdbf976 5905 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5906
8776e519 5907 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5908
9d74191a 5909 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5910}
5911
b6c7a5dc
HB		 5912/*
5913 * Check if userspace requested an interrupt window, and that the
5914 * interrupt window is open.
5915 *
5916 * No need to exit to userspace if we already have an interrupt queued.
5917 */
851ba692 5918static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5919{
1c1a9ce9
SR		 5920 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5921 return false;
5922
5923 if (kvm_cpu_has_interrupt(vcpu))
5924 return false;
5925
5926 return (irqchip_split(vcpu->kvm)
5927 ? kvm_apic_accept_pic_intr(vcpu)
5928 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5929}
5930
851ba692 5931static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5932{
851ba692
AK		 5933 struct kvm_run *kvm_run = vcpu->run;
5934
91586a3b 5935 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5936 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5937 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5938 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5939 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5940 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5941 kvm_arch_interrupt_allowed(vcpu) &&
5942 !kvm_cpu_has_interrupt(vcpu) &&
5943 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5944 else if (!pic_in_kernel(vcpu->kvm))
5945 kvm_run->ready_for_interrupt_injection =
5946 kvm_apic_accept_pic_intr(vcpu) &&
5947 !kvm_cpu_has_interrupt(vcpu);
5948 else
5949 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5950}
5951
95ba8273
GN		 5952static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5953{
5954 int max_irr, tpr;
5955
5956 if (!kvm_x86_ops->update_cr8_intercept)
5957 return;
5958
88c808fd
AK		 5959 if (!vcpu->arch.apic)
5960 return;
5961
8db3baa2
GN		 5962 if (!vcpu->arch.apic->vapic_addr)
5963 max_irr = kvm_lapic_find_highest_irr(vcpu);
5964 else
5965 max_irr = -1;
95ba8273
GN		 5966
5967 if (max_irr != -1)
5968 max_irr >>= 4;
5969
5970 tpr = kvm_lapic_get_cr8(vcpu);
5971
5972 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5973}
5974
b6b8a145 5975static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5976{
b6b8a145
JK		 5977 int r;
5978
95ba8273 5979 /* try to reinject previous events if any */
b59bb7bd 5980 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5981 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5982 vcpu->arch.exception.has_error_code,
5983 vcpu->arch.exception.error_code);
d6e8c854
NA		 5984
5985 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5986 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5987 X86_EFLAGS_RF);
5988
6bdf0662
NA		 5989 if (vcpu->arch.exception.nr == DB_VECTOR &&
5990 (vcpu->arch.dr7 & DR7_GD)) {
5991 vcpu->arch.dr7 &= ~DR7_GD;
5992 kvm_update_dr7(vcpu);
5993 }
5994
b59bb7bd
GN		 5995 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5996 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5997 vcpu->arch.exception.error_code,
5998 vcpu->arch.exception.reinject);
b6b8a145 5999 return 0;
b59bb7bd
GN		 6000 }
6001
95ba8273
GN		 6002 if (vcpu->arch.nmi_injected) {
6003 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6004 return 0;
95ba8273
GN		 6005 }
6006
6007 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6008 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6009 return 0;
6010 }
6011
6012 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6013 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6014 if (r != 0)
6015 return r;
95ba8273
GN		 6016 }
6017
6018 /* try to inject new event if pending */
6019 if (vcpu->arch.nmi_pending) {
6020 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6021 --vcpu->arch.nmi_pending;
95ba8273
GN		 6022 vcpu->arch.nmi_injected = true;
6023 kvm_x86_ops->set_nmi(vcpu);
6024 }
c7c9c56c 6025 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6026 /*
6027 * Because interrupts can be injected asynchronously, we are
6028 * calling check_nested_events again here to avoid a race condition.
6029 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6030 * proposal and current concerns. Perhaps we should be setting
6031 * KVM_REQ_EVENT only on certain events and not unconditionally?
6032 */
6033 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6034 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6035 if (r != 0)
6036 return r;
6037 }
95ba8273 6038 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6039 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6040 false);
6041 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6042 }
6043 }
b6b8a145 6044 return 0;
95ba8273
GN		 6045}
6046
7460fb4a
AK		 6047static void process_nmi(struct kvm_vcpu *vcpu)
6048{
6049 unsigned limit = 2;
6050
6051 /*
6052 * x86 is limited to one NMI running, and one NMI pending after it.
6053 * If an NMI is already in progress, limit further NMIs to just one.
6054 * Otherwise, allow two (and we'll inject the first one immediately).
6055 */
6056 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6057 limit = 1;
6058
6059 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6060 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6061 kvm_make_request(KVM_REQ_EVENT, vcpu);
6062}
6063
660a5d51
PB		 6064#define put_smstate(type, buf, offset, val) \
6065 *(type *)((buf) + (offset) - 0x7e00) = val
6066
6067static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6068{
6069 u32 flags = 0;
6070 flags |= seg->g << 23;
6071 flags |= seg->db << 22;
6072 flags |= seg->l << 21;
6073 flags |= seg->avl << 20;
6074 flags |= seg->present << 15;
6075 flags |= seg->dpl << 13;
6076 flags |= seg->s << 12;
6077 flags |= seg->type << 8;
6078 return flags;
6079}
6080
6081static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6082{
6083 struct kvm_segment seg;
6084 int offset;
6085
6086 kvm_get_segment(vcpu, &seg, n);
6087 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6088
6089 if (n < 3)
6090 offset = 0x7f84 + n * 12;
6091 else
6092 offset = 0x7f2c + (n - 3) * 12;
6093
6094 put_smstate(u32, buf, offset + 8, seg.base);
6095 put_smstate(u32, buf, offset + 4, seg.limit);
6096 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6097}
6098
efbb288a 6099#ifdef CONFIG_X86_64
660a5d51
PB		 6100static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6101{
6102 struct kvm_segment seg;
6103 int offset;
6104 u16 flags;
6105
6106 kvm_get_segment(vcpu, &seg, n);
6107 offset = 0x7e00 + n * 16;
6108
6109 flags = process_smi_get_segment_flags(&seg) >> 8;
6110 put_smstate(u16, buf, offset, seg.selector);
6111 put_smstate(u16, buf, offset + 2, flags);
6112 put_smstate(u32, buf, offset + 4, seg.limit);
6113 put_smstate(u64, buf, offset + 8, seg.base);
6114}
efbb288a 6115#endif
660a5d51
PB		 6116
6117static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6118{
6119 struct desc_ptr dt;
6120 struct kvm_segment seg;
6121 unsigned long val;
6122 int i;
6123
6124 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6125 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6126 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6127 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6128
6129 for (i = 0; i < 8; i++)
6130 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6131
6132 kvm_get_dr(vcpu, 6, &val);
6133 put_smstate(u32, buf, 0x7fcc, (u32)val);
6134 kvm_get_dr(vcpu, 7, &val);
6135 put_smstate(u32, buf, 0x7fc8, (u32)val);
6136
6137 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6138 put_smstate(u32, buf, 0x7fc4, seg.selector);
6139 put_smstate(u32, buf, 0x7f64, seg.base);
6140 put_smstate(u32, buf, 0x7f60, seg.limit);
6141 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6142
6143 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6144 put_smstate(u32, buf, 0x7fc0, seg.selector);
6145 put_smstate(u32, buf, 0x7f80, seg.base);
6146 put_smstate(u32, buf, 0x7f7c, seg.limit);
6147 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6148
6149 kvm_x86_ops->get_gdt(vcpu, &dt);
6150 put_smstate(u32, buf, 0x7f74, dt.address);
6151 put_smstate(u32, buf, 0x7f70, dt.size);
6152
6153 kvm_x86_ops->get_idt(vcpu, &dt);
6154 put_smstate(u32, buf, 0x7f58, dt.address);
6155 put_smstate(u32, buf, 0x7f54, dt.size);
6156
6157 for (i = 0; i < 6; i++)
6158 process_smi_save_seg_32(vcpu, buf, i);
6159
6160 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6161
6162 /* revision id */
6163 put_smstate(u32, buf, 0x7efc, 0x00020000);
6164 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6165}
6166
6167static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6168{
6169#ifdef CONFIG_X86_64
6170 struct desc_ptr dt;
6171 struct kvm_segment seg;
6172 unsigned long val;
6173 int i;
6174
6175 for (i = 0; i < 16; i++)
6176 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6177
6178 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6179 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6180
6181 kvm_get_dr(vcpu, 6, &val);
6182 put_smstate(u64, buf, 0x7f68, val);
6183 kvm_get_dr(vcpu, 7, &val);
6184 put_smstate(u64, buf, 0x7f60, val);
6185
6186 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6187 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6188 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6189
6190 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6191
6192 /* revision id */
6193 put_smstate(u32, buf, 0x7efc, 0x00020064);
6194
6195 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6196
6197 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6198 put_smstate(u16, buf, 0x7e90, seg.selector);
6199 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6200 put_smstate(u32, buf, 0x7e94, seg.limit);
6201 put_smstate(u64, buf, 0x7e98, seg.base);
6202
6203 kvm_x86_ops->get_idt(vcpu, &dt);
6204 put_smstate(u32, buf, 0x7e84, dt.size);
6205 put_smstate(u64, buf, 0x7e88, dt.address);
6206
6207 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6208 put_smstate(u16, buf, 0x7e70, seg.selector);
6209 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6210 put_smstate(u32, buf, 0x7e74, seg.limit);
6211 put_smstate(u64, buf, 0x7e78, seg.base);
6212
6213 kvm_x86_ops->get_gdt(vcpu, &dt);
6214 put_smstate(u32, buf, 0x7e64, dt.size);
6215 put_smstate(u64, buf, 0x7e68, dt.address);
6216
6217 for (i = 0; i < 6; i++)
6218 process_smi_save_seg_64(vcpu, buf, i);
6219#else
6220 WARN_ON_ONCE(1);
6221#endif
6222}
6223
64d60670
PB		 6224static void process_smi(struct kvm_vcpu *vcpu)
6225{
660a5d51 6226 struct kvm_segment cs, ds;
18c3626e 6227 struct desc_ptr dt;
660a5d51
PB		 6228 char buf[512];
6229 u32 cr0;
6230
64d60670
PB		 6231 if (is_smm(vcpu)) {
6232 vcpu->arch.smi_pending = true;
6233 return;
6234 }
6235
660a5d51
PB		 6236 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6237 vcpu->arch.hflags |= HF_SMM_MASK;
6238 memset(buf, 0, 512);
6239 if (guest_cpuid_has_longmode(vcpu))
6240 process_smi_save_state_64(vcpu, buf);
6241 else
6242 process_smi_save_state_32(vcpu, buf);
6243
54bf36aa 6244 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6245
6246 if (kvm_x86_ops->get_nmi_mask(vcpu))
6247 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6248 else
6249 kvm_x86_ops->set_nmi_mask(vcpu, true);
6250
6251 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6252 kvm_rip_write(vcpu, 0x8000);
6253
6254 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6255 kvm_x86_ops->set_cr0(vcpu, cr0);
6256 vcpu->arch.cr0 = cr0;
6257
6258 kvm_x86_ops->set_cr4(vcpu, 0);
6259
18c3626e
PB		 6260 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6261 dt.address = dt.size = 0;
6262 kvm_x86_ops->set_idt(vcpu, &dt);
6263
660a5d51
PB		 6264 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6265
6266 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6267 cs.base = vcpu->arch.smbase;
6268
6269 ds.selector = 0;
6270 ds.base = 0;
6271
6272 cs.limit = ds.limit = 0xffffffff;
6273 cs.type = ds.type = 0x3;
6274 cs.dpl = ds.dpl = 0;
6275 cs.db = ds.db = 0;
6276 cs.s = ds.s = 1;
6277 cs.l = ds.l = 0;
6278 cs.g = ds.g = 1;
6279 cs.avl = ds.avl = 0;
6280 cs.present = ds.present = 1;
6281 cs.unusable = ds.unusable = 0;
6282 cs.padding = ds.padding = 0;
6283
6284 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6285 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6286 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6287 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6288 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6289 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6290
6291 if (guest_cpuid_has_longmode(vcpu))
6292 kvm_x86_ops->set_efer(vcpu, 0);
6293
6294 kvm_update_cpuid(vcpu);
6295 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6296}
6297
3d81bc7e 6298static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6299{
3d81bc7e
YZ		 6300 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6301 return;
c7c9c56c 6302
3bb345f3 6303 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6304
b053b2ae
SR		 6305 if (irqchip_split(vcpu->kvm))
6306 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb
RK		 6307 else {
6308 kvm_x86_ops->sync_pir_to_irr(vcpu);
b053b2ae 6309 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb 6310 }
3bb345f3 6311 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6312}
6313
a70656b6
RK		 6314static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6315{
6316 ++vcpu->stat.tlb_flush;
6317 kvm_x86_ops->tlb_flush(vcpu);
6318}
6319
4256f43f
TC		 6320void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6321{
c24ae0dc
TC		 6322 struct page *page = NULL;
6323
35754c98 6324 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6325 return;
6326
4256f43f
TC		 6327 if (!kvm_x86_ops->set_apic_access_page_addr)
6328 return;
6329
c24ae0dc 6330 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6331 if (is_error_page(page))
6332 return;
c24ae0dc
TC		 6333 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6334
6335 /*
6336 * Do not pin apic access page in memory, the MMU notifier
6337 * will call us again if it is migrated or swapped out.
6338 */
6339 put_page(page);
4256f43f
TC		 6340}
6341EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6342
fe71557a
TC		 6343void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6344 unsigned long address)
6345{
c24ae0dc
TC		 6346 /*
6347 * The physical address of apic access page is stored in the VMCS.
6348 * Update it when it becomes invalid.
6349 */
6350 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6351 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6352}
6353
9357d939 6354/*
362c698f 6355 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6356 * exiting to the userspace. Otherwise, the value will be returned to the
6357 * userspace.
6358 */
851ba692 6359static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6360{
6361 int r;
35754c98 6362 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6363 vcpu->run->request_interrupt_window;
730dca42 6364 bool req_immediate_exit = false;
b6c7a5dc 6365
3e007509 6366 if (vcpu->requests) {
a8eeb04a 6367 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6368 kvm_mmu_unload(vcpu);
a8eeb04a 6369 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6370 __kvm_migrate_timers(vcpu);
d828199e
MT		 6371 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6372 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6373 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6374 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6375 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6376 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6377 if (unlikely(r))
6378 goto out;
6379 }
a8eeb04a 6380 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6381 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6382 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6383 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6384 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6385 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6386 r = 0;
6387 goto out;
6388 }
a8eeb04a 6389 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6390 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6391 r = 0;
6392 goto out;
6393 }
a8eeb04a 6394 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6395 vcpu->fpu_active = 0;
6396 kvm_x86_ops->fpu_deactivate(vcpu);
6397 }
af585b92
GN		 6398 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6399 /* Page is swapped out. Do synthetic halt */
6400 vcpu->arch.apf.halted = true;
6401 r = 1;
6402 goto out;
6403 }
c9aaa895
GC		 6404 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6405 record_steal_time(vcpu);
64d60670
PB		 6406 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6407 process_smi(vcpu);
7460fb4a
AK		 6408 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6409 process_nmi(vcpu);
f5132b01 6410 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6411 kvm_pmu_handle_event(vcpu);
f5132b01 6412 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6413 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6414 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6415 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6416 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6417 (void *) vcpu->arch.eoi_exit_bitmap)) {
6418 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6419 vcpu->run->eoi.vector =
6420 vcpu->arch.pending_ioapic_eoi;
6421 r = 0;
6422 goto out;
6423 }
6424 }
3d81bc7e
YZ		 6425 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6426 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6427 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6428 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6429 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6430 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6431 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6432 r = 0;
6433 goto out;
6434 }
e516cebb
AS		 6435 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6436 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6437 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6438 r = 0;
6439 goto out;
6440 }
2f52d58c 6441 }
b93463aa 6442
bf9f6ac8
FW		 6443 /*
6444 * KVM_REQ_EVENT is not set when posted interrupts are set by
6445 * VT-d hardware, so we have to update RVI unconditionally.
6446 */
6447 if (kvm_lapic_enabled(vcpu)) {
6448 /*
6449 * Update architecture specific hints for APIC
6450 * virtual interrupt delivery.
6451 */
6452 if (kvm_x86_ops->hwapic_irr_update)
6453 kvm_x86_ops->hwapic_irr_update(vcpu,
6454 kvm_lapic_find_highest_irr(vcpu));
6455 }
6456
b463a6f7 6457 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6458 kvm_apic_accept_events(vcpu);
6459 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6460 r = 1;
6461 goto out;
6462 }
6463
b6b8a145
JK		 6464 if (inject_pending_event(vcpu, req_int_win) != 0)
6465 req_immediate_exit = true;
b463a6f7 6466 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6467 else if (vcpu->arch.nmi_pending)
c9a7953f 6468 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6469 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6470 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6471
6472 if (kvm_lapic_enabled(vcpu)) {
6473 update_cr8_intercept(vcpu);
6474 kvm_lapic_sync_to_vapic(vcpu);
6475 }
6476 }
6477
d8368af8
AK		 6478 r = kvm_mmu_reload(vcpu);
6479 if (unlikely(r)) {
d905c069 6480 goto cancel_injection;
d8368af8
AK		 6481 }
6482
b6c7a5dc
HB		 6483 preempt_disable();
6484
6485 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6486 if (vcpu->fpu_active)
6487 kvm_load_guest_fpu(vcpu);
2acf923e 6488 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6489
6b7e2d09
XG		 6490 vcpu->mode = IN_GUEST_MODE;
6491
01b71917
MT		 6492 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6493
6b7e2d09
XG		 6494 /* We should set ->mode before check ->requests,
6495 * see the comment in make_all_cpus_request.
6496 */
01b71917 6497 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6498
d94e1dc9 6499 local_irq_disable();
32f88400 6500
6b7e2d09 6501 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6502 || need_resched() || signal_pending(current)) {
6b7e2d09 6503 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6504 smp_wmb();
6c142801
AK		 6505 local_irq_enable();
6506 preempt_enable();
01b71917 6507 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6508 r = 1;
d905c069 6509 goto cancel_injection;
6c142801
AK		 6510 }
6511
d6185f20
NHE		 6512 if (req_immediate_exit)
6513 smp_send_reschedule(vcpu->cpu);
6514
ccf73aaf 6515 __kvm_guest_enter();
b6c7a5dc 6516
42dbaa5a 6517 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6518 set_debugreg(0, 7);
6519 set_debugreg(vcpu->arch.eff_db[0], 0);
6520 set_debugreg(vcpu->arch.eff_db[1], 1);
6521 set_debugreg(vcpu->arch.eff_db[2], 2);
6522 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6523 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6524 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6525 }
b6c7a5dc 6526
229456fc 6527 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6528 wait_lapic_expire(vcpu);
851ba692 6529 kvm_x86_ops->run(vcpu);
b6c7a5dc 6530
c77fb5fe
PB		 6531 /*
6532 * Do this here before restoring debug registers on the host. And
6533 * since we do this before handling the vmexit, a DR access vmexit
6534 * can (a) read the correct value of the debug registers, (b) set
6535 * KVM_DEBUGREG_WONT_EXIT again.
6536 */
6537 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6538 int i;
6539
6540 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6541 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6542 for (i = 0; i < KVM_NR_DB_REGS; i++)
6543 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6544 }
6545
24f1e32c
FW		 6546 /*
6547 * If the guest has used debug registers, at least dr7
6548 * will be disabled while returning to the host.
6549 * If we don't have active breakpoints in the host, we don't
6550 * care about the messed up debug address registers. But if
6551 * we have some of them active, restore the old state.
6552 */
59d8eb53 6553 if (hw_breakpoint_active())
24f1e32c 6554 hw_breakpoint_restore();
42dbaa5a 6555
4ba76538 6556 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6557
6b7e2d09 6558 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6559 smp_wmb();
a547c6db
YZ		 6560
6561 /* Interrupt is enabled by handle_external_intr() */
6562 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6563
6564 ++vcpu->stat.exits;
6565
6566 /*
6567 * We must have an instruction between local_irq_enable() and
6568 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6569 * the interrupt shadow. The stat.exits increment will do nicely.
6570 * But we need to prevent reordering, hence this barrier():
6571 */
6572 barrier();
6573
6574 kvm_guest_exit();
6575
6576 preempt_enable();
6577
f656ce01 6578 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6579
b6c7a5dc
HB		 6580 /*
6581 * Profile KVM exit RIPs:
6582 */
6583 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6584 unsigned long rip = kvm_rip_read(vcpu);
6585 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6586 }
6587
cc578287
ZA		 6588 if (unlikely(vcpu->arch.tsc_always_catchup))
6589 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6590
5cfb1d5a
MT		 6591 if (vcpu->arch.apic_attention)
6592 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6593
851ba692 6594 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6595 return r;
6596
6597cancel_injection:
6598 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6599 if (unlikely(vcpu->arch.apic_attention))
6600 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6601out:
6602 return r;
6603}
b6c7a5dc 6604
362c698f
PB		 6605static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6606{
bf9f6ac8
FW		 6607 if (!kvm_arch_vcpu_runnable(vcpu) &&
6608 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6609 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6610 kvm_vcpu_block(vcpu);
6611 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6612
6613 if (kvm_x86_ops->post_block)
6614 kvm_x86_ops->post_block(vcpu);
6615
9c8fd1ba
PB		 6616 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6617 return 1;
6618 }
362c698f
PB		 6619
6620 kvm_apic_accept_events(vcpu);
6621 switch(vcpu->arch.mp_state) {
6622 case KVM_MP_STATE_HALTED:
6623 vcpu->arch.pv.pv_unhalted = false;
6624 vcpu->arch.mp_state =
6625 KVM_MP_STATE_RUNNABLE;
6626 case KVM_MP_STATE_RUNNABLE:
6627 vcpu->arch.apf.halted = false;
6628 break;
6629 case KVM_MP_STATE_INIT_RECEIVED:
6630 break;
6631 default:
6632 return -EINTR;
6633 break;
6634 }
6635 return 1;
6636}
09cec754 6637
5d9bc648
PB		 6638static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6639{
6640 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6641 !vcpu->arch.apf.halted);
6642}
6643
362c698f 6644static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6645{
6646 int r;
f656ce01 6647 struct kvm *kvm = vcpu->kvm;
d7690175 6648
f656ce01 6649 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6650
362c698f 6651 for (;;) {
58f800d5 6652 if (kvm_vcpu_running(vcpu)) {
851ba692 6653 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6654 } else {
362c698f 6655 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6656 }
6657
09cec754
GN		 6658 if (r <= 0)
6659 break;
6660
6661 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6662 if (kvm_cpu_has_pending_timer(vcpu))
6663 kvm_inject_pending_timer_irqs(vcpu);
6664
851ba692 6665 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6666 r = 0;
6667 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6668 ++vcpu->stat.request_irq_exits;
362c698f 6669 break;
09cec754 6670 }
af585b92
GN		 6671
6672 kvm_check_async_pf_completion(vcpu);
6673
09cec754
GN		 6674 if (signal_pending(current)) {
6675 r = -EINTR;
851ba692 6676 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6677 ++vcpu->stat.signal_exits;
362c698f 6678 break;
09cec754
GN		 6679 }
6680 if (need_resched()) {
f656ce01 6681 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6682 cond_resched();
f656ce01 6683 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6684 }
b6c7a5dc
HB		 6685 }
6686
f656ce01 6687 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6688
6689 return r;
6690}
6691
716d51ab
GN		 6692static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6693{
6694 int r;
6695 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6696 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6697 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6698 if (r != EMULATE_DONE)
6699 return 0;
6700 return 1;
6701}
6702
6703static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6704{
6705 BUG_ON(!vcpu->arch.pio.count);
6706
6707 return complete_emulated_io(vcpu);
6708}
6709
f78146b0
AK		 6710/*
6711 * Implements the following, as a state machine:
6712 *
6713 * read:
6714 * for each fragment
87da7e66
XG		 6715 * for each mmio piece in the fragment
6716 * write gpa, len
6717 * exit
6718 * copy data
f78146b0
AK		 6719 * execute insn
6720 *
6721 * write:
6722 * for each fragment
87da7e66
XG		 6723 * for each mmio piece in the fragment
6724 * write gpa, len
6725 * copy data
6726 * exit
f78146b0 6727 */
716d51ab 6728static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6729{
6730 struct kvm_run *run = vcpu->run;
f78146b0 6731 struct kvm_mmio_fragment *frag;
87da7e66 6732 unsigned len;
5287f194 6733
716d51ab 6734 BUG_ON(!vcpu->mmio_needed);
5287f194 6735
716d51ab 6736 /* Complete previous fragment */
87da7e66
XG		 6737 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6738 len = min(8u, frag->len);
716d51ab 6739 if (!vcpu->mmio_is_write)
87da7e66
XG		 6740 memcpy(frag->data, run->mmio.data, len);
6741
6742 if (frag->len <= 8) {
6743 /* Switch to the next fragment. */
6744 frag++;
6745 vcpu->mmio_cur_fragment++;
6746 } else {
6747 /* Go forward to the next mmio piece. */
6748 frag->data += len;
6749 frag->gpa += len;
6750 frag->len -= len;
6751 }
6752
a08d3b3b 6753 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6754 vcpu->mmio_needed = 0;
0912c977
PB		 6755
6756 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6757 if (vcpu->mmio_is_write)
716d51ab
GN		 6758 return 1;
6759 vcpu->mmio_read_completed = 1;
6760 return complete_emulated_io(vcpu);
6761 }
87da7e66 6762
716d51ab
GN		 6763 run->exit_reason = KVM_EXIT_MMIO;
6764 run->mmio.phys_addr = frag->gpa;
6765 if (vcpu->mmio_is_write)
87da7e66
XG		 6766 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6767 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6768 run->mmio.is_write = vcpu->mmio_is_write;
6769 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6770 return 0;
5287f194
AK		 6771}
6772
716d51ab 6773
b6c7a5dc
HB		 6774int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6775{
c5bedc68 6776 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6777 int r;
6778 sigset_t sigsaved;
6779
c4d72e2d 6780 fpu__activate_curr(fpu);
e5c30142 6781
ac9f6dc0
AK		 6782 if (vcpu->sigset_active)
6783 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6784
a4535290 6785 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6786 kvm_vcpu_block(vcpu);
66450a21 6787 kvm_apic_accept_events(vcpu);
d7690175 6788 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6789 r = -EAGAIN;
6790 goto out;
b6c7a5dc
HB		 6791 }
6792
b6c7a5dc 6793 /* re-sync apic's tpr */
35754c98 6794 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6795 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6796 r = -EINVAL;
6797 goto out;
6798 }
6799 }
b6c7a5dc 6800
716d51ab
GN		 6801 if (unlikely(vcpu->arch.complete_userspace_io)) {
6802 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6803 vcpu->arch.complete_userspace_io = NULL;
6804 r = cui(vcpu);
6805 if (r <= 0)
6806 goto out;
6807 } else
6808 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6809
362c698f 6810 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6811
6812out:
f1d86e46 6813 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6814 if (vcpu->sigset_active)
6815 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6816
b6c7a5dc
HB		 6817 return r;
6818}
6819
6820int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6821{
7ae441ea
GN		 6822 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6823 /*
6824 * We are here if userspace calls get_regs() in the middle of
6825 * instruction emulation. Registers state needs to be copied
4a969980 6826 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6827 * that usually, but some bad designed PV devices (vmware
6828 * backdoor interface) need this to work
6829 */
dd856efa 6830 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6831 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6832 }
5fdbf976
MT		 6833 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6834 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6835 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6836 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6837 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6838 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6839 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6840 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6841#ifdef CONFIG_X86_64
5fdbf976
MT		 6842 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6843 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6844 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6845 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6846 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6847 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6848 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6849 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6850#endif
6851
5fdbf976 6852 regs->rip = kvm_rip_read(vcpu);
91586a3b 6853 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6854
b6c7a5dc
HB		 6855 return 0;
6856}
6857
6858int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6859{
7ae441ea
GN		 6860 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6861 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6862
5fdbf976
MT		 6863 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6864 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6865 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6866 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6867 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6868 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6869 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6870 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6871#ifdef CONFIG_X86_64
5fdbf976
MT		 6872 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6873 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6874 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6875 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6876 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6877 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6878 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6879 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6880#endif
6881
5fdbf976 6882 kvm_rip_write(vcpu, regs->rip);
91586a3b 6883 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6884
b4f14abd
JK		 6885 vcpu->arch.exception.pending = false;
6886
3842d135
AK		 6887 kvm_make_request(KVM_REQ_EVENT, vcpu);
6888
b6c7a5dc
HB		 6889 return 0;
6890}
6891
b6c7a5dc
HB		 6892void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6893{
6894 struct kvm_segment cs;
6895
3e6e0aab 6896 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6897 *db = cs.db;
6898 *l = cs.l;
6899}
6900EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6901
6902int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6903 struct kvm_sregs *sregs)
6904{
89a27f4d 6905 struct desc_ptr dt;
b6c7a5dc 6906
3e6e0aab
GT		 6907 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6908 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6909 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6910 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6911 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6912 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6913
3e6e0aab
GT		 6914 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6915 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6916
6917 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6918 sregs->idt.limit = dt.size;
6919 sregs->idt.base = dt.address;
b6c7a5dc 6920 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6921 sregs->gdt.limit = dt.size;
6922 sregs->gdt.base = dt.address;
b6c7a5dc 6923
4d4ec087 6924 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6925 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6926 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6927 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6928 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6929 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6930 sregs->apic_base = kvm_get_apic_base(vcpu);
6931
923c61bb 6932 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6933
36752c9b 6934 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6935 set_bit(vcpu->arch.interrupt.nr,
6936 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6937
b6c7a5dc
HB		 6938 return 0;
6939}
6940
62d9f0db
MT		 6941int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6942 struct kvm_mp_state *mp_state)
6943{
66450a21 6944 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6945 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6946 vcpu->arch.pv.pv_unhalted)
6947 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6948 else
6949 mp_state->mp_state = vcpu->arch.mp_state;
6950
62d9f0db
MT		 6951 return 0;
6952}
6953
6954int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6955 struct kvm_mp_state *mp_state)
6956{
66450a21
JK		 6957 if (!kvm_vcpu_has_lapic(vcpu) &&
6958 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6959 return -EINVAL;
6960
6961 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6962 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6963 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6964 } else
6965 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6966 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6967 return 0;
6968}
6969
7f3d35fd
KW		 6970int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6971 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6972{
9d74191a 6973 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6974 int ret;
e01c2426 6975
8ec4722d 6976 init_emulate_ctxt(vcpu);
c697518a 6977
7f3d35fd 6978 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6979 has_error_code, error_code);
c697518a 6980
c697518a 6981 if (ret)
19d04437 6982 return EMULATE_FAIL;
37817f29 6983
9d74191a
TY		 6984 kvm_rip_write(vcpu, ctxt->eip);
6985 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6986 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6987 return EMULATE_DONE;
37817f29
IE		 6988}
6989EXPORT_SYMBOL_GPL(kvm_task_switch);
6990
b6c7a5dc
HB		 6991int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6992 struct kvm_sregs *sregs)
6993{
58cb628d 6994 struct msr_data apic_base_msr;
b6c7a5dc 6995 int mmu_reset_needed = 0;
63f42e02 6996 int pending_vec, max_bits, idx;
89a27f4d 6997 struct desc_ptr dt;
b6c7a5dc 6998
6d1068b3
PM		 6999 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7000 return -EINVAL;
7001
89a27f4d
GN		 7002 dt.size = sregs->idt.limit;
7003 dt.address = sregs->idt.base;
b6c7a5dc 7004 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7005 dt.size = sregs->gdt.limit;
7006 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7007 kvm_x86_ops->set_gdt(vcpu, &dt);
7008
ad312c7c 7009 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7010 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7011 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7012 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7013
2d3ad1f4 7014 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7015
f6801dff 7016 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7017 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7018 apic_base_msr.data = sregs->apic_base;
7019 apic_base_msr.host_initiated = true;
7020 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7021
4d4ec087 7022 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7023 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7024 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7025
fc78f519 7026 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7027 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7028 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7029 kvm_update_cpuid(vcpu);
63f42e02
XG		 7030
7031 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7032 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7033 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7034 mmu_reset_needed = 1;
7035 }
63f42e02 7036 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7037
7038 if (mmu_reset_needed)
7039 kvm_mmu_reset_context(vcpu);
7040
a50abc3b 7041 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7042 pending_vec = find_first_bit(
7043 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7044 if (pending_vec < max_bits) {
66fd3f7f 7045 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7046 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7047 }
7048
3e6e0aab
GT		 7049 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7050 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7051 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7052 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7053 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7054 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7055
3e6e0aab
GT		 7056 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7057 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7058
5f0269f5
ME		 7059 update_cr8_intercept(vcpu);
7060
9c3e4aab 7061 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7062 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7063 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7064 !is_protmode(vcpu))
9c3e4aab
MT		 7065 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7066
3842d135
AK		 7067 kvm_make_request(KVM_REQ_EVENT, vcpu);
7068
b6c7a5dc
HB		 7069 return 0;
7070}
7071
d0bfb940
JK		 7072int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7073 struct kvm_guest_debug *dbg)
b6c7a5dc 7074{
355be0b9 7075 unsigned long rflags;
ae675ef0 7076 int i, r;
b6c7a5dc 7077
4f926bf2
JK		 7078 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7079 r = -EBUSY;
7080 if (vcpu->arch.exception.pending)
2122ff5e 7081 goto out;
4f926bf2
JK		 7082 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7083 kvm_queue_exception(vcpu, DB_VECTOR);
7084 else
7085 kvm_queue_exception(vcpu, BP_VECTOR);
7086 }
7087
91586a3b
JK		 7088 /*
7089 * Read rflags as long as potentially injected trace flags are still
7090 * filtered out.
7091 */
7092 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7093
7094 vcpu->guest_debug = dbg->control;
7095 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7096 vcpu->guest_debug = 0;
7097
7098 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7099 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7100 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7101 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7102 } else {
7103 for (i = 0; i < KVM_NR_DB_REGS; i++)
7104 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7105 }
c8639010 7106 kvm_update_dr7(vcpu);
ae675ef0 7107
f92653ee
JK		 7108 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7109 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7110 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7111
91586a3b
JK		 7112 /*
7113 * Trigger an rflags update that will inject or remove the trace
7114 * flags.
7115 */
7116 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7117
c8639010 7118 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7119
4f926bf2 7120 r = 0;
d0bfb940 7121
2122ff5e 7122out:
b6c7a5dc
HB		 7123
7124 return r;
7125}
7126
8b006791
ZX		 7127/*
7128 * Translate a guest virtual address to a guest physical address.
7129 */
7130int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7131 struct kvm_translation *tr)
7132{
7133 unsigned long vaddr = tr->linear_address;
7134 gpa_t gpa;
f656ce01 7135 int idx;
8b006791 7136
f656ce01 7137 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7138 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7139 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7140 tr->physical_address = gpa;
7141 tr->valid = gpa != UNMAPPED_GVA;
7142 tr->writeable = 1;
7143 tr->usermode = 0;
8b006791
ZX		 7144
7145 return 0;
7146}
7147
d0752060
HB		 7148int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7149{
c47ada30 7150 struct fxregs_state *fxsave =
7366ed77 7151 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7152
d0752060
HB		 7153 memcpy(fpu->fpr, fxsave->st_space, 128);
7154 fpu->fcw = fxsave->cwd;
7155 fpu->fsw = fxsave->swd;
7156 fpu->ftwx = fxsave->twd;
7157 fpu->last_opcode = fxsave->fop;
7158 fpu->last_ip = fxsave->rip;
7159 fpu->last_dp = fxsave->rdp;
7160 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7161
d0752060
HB		 7162 return 0;
7163}
7164
7165int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7166{
c47ada30 7167 struct fxregs_state *fxsave =
7366ed77 7168 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7169
d0752060
HB		 7170 memcpy(fxsave->st_space, fpu->fpr, 128);
7171 fxsave->cwd = fpu->fcw;
7172 fxsave->swd = fpu->fsw;
7173 fxsave->twd = fpu->ftwx;
7174 fxsave->fop = fpu->last_opcode;
7175 fxsave->rip = fpu->last_ip;
7176 fxsave->rdp = fpu->last_dp;
7177 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7178
d0752060
HB		 7179 return 0;
7180}
7181
0ee6a517 7182static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7183{
bf935b0b 7184 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7185 if (cpu_has_xsaves)
7366ed77 7186 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7187 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7188
2acf923e
DC		 7189 /*
7190 * Ensure guest xcr0 is valid for loading
7191 */
7192 vcpu->arch.xcr0 = XSTATE_FP;
7193
ad312c7c 7194 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7195}
d0752060
HB		 7196
7197void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7198{
2608d7a1 7199 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7200 return;
7201
2acf923e
DC		 7202 /*
7203 * Restore all possible states in the guest,
7204 * and assume host would use all available bits.
7205 * Guest xcr0 would be loaded later.
7206 */
7207 kvm_put_guest_xcr0(vcpu);
d0752060 7208 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7209 __kernel_fpu_begin();
003e2e8b 7210 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7211 trace_kvm_fpu(1);
d0752060 7212}
d0752060
HB		 7213
7214void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7215{
2acf923e
DC		 7216 kvm_put_guest_xcr0(vcpu);
7217
653f52c3
RR		 7218 if (!vcpu->guest_fpu_loaded) {
7219 vcpu->fpu_counter = 0;
d0752060 7220 return;
653f52c3 7221 }
d0752060
HB		 7222
7223 vcpu->guest_fpu_loaded = 0;
4f836347 7224 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7225 __kernel_fpu_end();
f096ed85 7226 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7227 /*
7228 * If using eager FPU mode, or if the guest is a frequent user
7229 * of the FPU, just leave the FPU active for next time.
7230 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7231 * the FPU in bursts will revert to loading it on demand.
7232 */
a9b4fb7e 7233 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7234 if (++vcpu->fpu_counter < 5)
7235 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7236 }
0c04851c 7237 trace_kvm_fpu(0);
d0752060 7238}
e9b11c17
ZX		 7239
7240void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7241{
12f9a48f 7242 kvmclock_reset(vcpu);
7f1ea208 7243
f5f48ee1 7244 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7245 kvm_x86_ops->vcpu_free(vcpu);
7246}
7247
7248struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7249 unsigned int id)
7250{
c447e76b
LL		 7251 struct kvm_vcpu *vcpu;
7252
6755bae8
ZA		 7253 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7254 printk_once(KERN_WARNING
7255 "kvm: SMP vm created on host with unstable TSC; "
7256 "guest TSC will not be reliable\n");
c447e76b
LL		 7257
7258 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7259
c447e76b 7260 return vcpu;
26e5215f 7261}
e9b11c17 7262
26e5215f
AK		 7263int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7264{
7265 int r;
e9b11c17 7266
19efffa2 7267 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7268 r = vcpu_load(vcpu);
7269 if (r)
7270 return r;
d28bc9dd 7271 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7272 kvm_mmu_setup(vcpu);
e9b11c17 7273 vcpu_put(vcpu);
26e5215f 7274 return r;
e9b11c17
ZX		 7275}
7276
31928aa5 7277void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7278{
8fe8ab46 7279 struct msr_data msr;
332967a3 7280 struct kvm *kvm = vcpu->kvm;
42897d86 7281
31928aa5
DD		 7282 if (vcpu_load(vcpu))
7283 return;
8fe8ab46
WA		 7284 msr.data = 0x0;
7285 msr.index = MSR_IA32_TSC;
7286 msr.host_initiated = true;
7287 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7288 vcpu_put(vcpu);
7289
630994b3
MT		 7290 if (!kvmclock_periodic_sync)
7291 return;
7292
332967a3
AJ		 7293 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7294 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7295}
7296
d40ccc62 7297void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7298{
9fc77441 7299 int r;
344d9588
GN		 7300 vcpu->arch.apf.msr_val = 0;
7301
9fc77441
MT		 7302 r = vcpu_load(vcpu);
7303 BUG_ON(r);
e9b11c17
ZX		 7304 kvm_mmu_unload(vcpu);
7305 vcpu_put(vcpu);
7306
7307 kvm_x86_ops->vcpu_free(vcpu);
7308}
7309
d28bc9dd 7310void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7311{
e69fab5d
PB		 7312 vcpu->arch.hflags = 0;
7313
7460fb4a
AK		 7314 atomic_set(&vcpu->arch.nmi_queued, 0);
7315 vcpu->arch.nmi_pending = 0;
448fa4a9 7316 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7317 kvm_clear_interrupt_queue(vcpu);
7318 kvm_clear_exception_queue(vcpu);
448fa4a9 7319
42dbaa5a 7320 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7321 kvm_update_dr0123(vcpu);
6f43ed01 7322 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7323 kvm_update_dr6(vcpu);
42dbaa5a 7324 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7325 kvm_update_dr7(vcpu);
42dbaa5a 7326
1119022c
NA		 7327 vcpu->arch.cr2 = 0;
7328
3842d135 7329 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7330 vcpu->arch.apf.msr_val = 0;
c9aaa895 7331 vcpu->arch.st.msr_val = 0;
3842d135 7332
12f9a48f
GC		 7333 kvmclock_reset(vcpu);
7334
af585b92
GN		 7335 kvm_clear_async_pf_completion_queue(vcpu);
7336 kvm_async_pf_hash_reset(vcpu);
7337 vcpu->arch.apf.halted = false;
3842d135 7338
64d60670 7339 if (!init_event) {
d28bc9dd 7340 kvm_pmu_reset(vcpu);
64d60670
PB		 7341 vcpu->arch.smbase = 0x30000;
7342 }
f5132b01 7343
66f7b72e
JS		 7344 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7345 vcpu->arch.regs_avail = ~0;
7346 vcpu->arch.regs_dirty = ~0;
7347
d28bc9dd 7348 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7349}
7350
2b4a273b 7351void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7352{
7353 struct kvm_segment cs;
7354
7355 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7356 cs.selector = vector << 8;
7357 cs.base = vector << 12;
7358 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7359 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7360}
7361
13a34e06 7362int kvm_arch_hardware_enable(void)
e9b11c17 7363{
ca84d1a2
ZA		 7364 struct kvm *kvm;
7365 struct kvm_vcpu *vcpu;
7366 int i;
0dd6a6ed
ZA		 7367 int ret;
7368 u64 local_tsc;
7369 u64 max_tsc = 0;
7370 bool stable, backwards_tsc = false;
18863bdd
AK		 7371
7372 kvm_shared_msr_cpu_online();
13a34e06 7373 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7374 if (ret != 0)
7375 return ret;
7376
4ea1636b 7377 local_tsc = rdtsc();
0dd6a6ed
ZA		 7378 stable = !check_tsc_unstable();
7379 list_for_each_entry(kvm, &vm_list, vm_list) {
7380 kvm_for_each_vcpu(i, vcpu, kvm) {
7381 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7382 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7383 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7384 backwards_tsc = true;
7385 if (vcpu->arch.last_host_tsc > max_tsc)
7386 max_tsc = vcpu->arch.last_host_tsc;
7387 }
7388 }
7389 }
7390
7391 /*
7392 * Sometimes, even reliable TSCs go backwards. This happens on
7393 * platforms that reset TSC during suspend or hibernate actions, but
7394 * maintain synchronization. We must compensate. Fortunately, we can
7395 * detect that condition here, which happens early in CPU bringup,
7396 * before any KVM threads can be running. Unfortunately, we can't
7397 * bring the TSCs fully up to date with real time, as we aren't yet far
7398 * enough into CPU bringup that we know how much real time has actually
7399 * elapsed; our helper function, get_kernel_ns() will be using boot
7400 * variables that haven't been updated yet.
7401 *
7402 * So we simply find the maximum observed TSC above, then record the
7403 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7404 * the adjustment will be applied. Note that we accumulate
7405 * adjustments, in case multiple suspend cycles happen before some VCPU
7406 * gets a chance to run again. In the event that no KVM threads get a
7407 * chance to run, we will miss the entire elapsed period, as we'll have
7408 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7409 * loose cycle time. This isn't too big a deal, since the loss will be
7410 * uniform across all VCPUs (not to mention the scenario is extremely
7411 * unlikely). It is possible that a second hibernate recovery happens
7412 * much faster than a first, causing the observed TSC here to be
7413 * smaller; this would require additional padding adjustment, which is
7414 * why we set last_host_tsc to the local tsc observed here.
7415 *
7416 * N.B. - this code below runs only on platforms with reliable TSC,
7417 * as that is the only way backwards_tsc is set above. Also note
7418 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7419 * have the same delta_cyc adjustment applied if backwards_tsc
7420 * is detected. Note further, this adjustment is only done once,
7421 * as we reset last_host_tsc on all VCPUs to stop this from being
7422 * called multiple times (one for each physical CPU bringup).
7423 *
4a969980 7424 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7425 * will be compensated by the logic in vcpu_load, which sets the TSC to
7426 * catchup mode. This will catchup all VCPUs to real time, but cannot
7427 * guarantee that they stay in perfect synchronization.
7428 */
7429 if (backwards_tsc) {
7430 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7431 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7432 list_for_each_entry(kvm, &vm_list, vm_list) {
7433 kvm_for_each_vcpu(i, vcpu, kvm) {
7434 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7435 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7436 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7437 }
7438
7439 /*
7440 * We have to disable TSC offset matching.. if you were
7441 * booting a VM while issuing an S4 host suspend....
7442 * you may have some problem. Solving this issue is
7443 * left as an exercise to the reader.
7444 */
7445 kvm->arch.last_tsc_nsec = 0;
7446 kvm->arch.last_tsc_write = 0;
7447 }
7448
7449 }
7450 return 0;
e9b11c17
ZX		 7451}
7452
13a34e06 7453void kvm_arch_hardware_disable(void)
e9b11c17 7454{
13a34e06
RK		 7455 kvm_x86_ops->hardware_disable();
7456 drop_user_return_notifiers();
e9b11c17
ZX		 7457}
7458
7459int kvm_arch_hardware_setup(void)
7460{
9e9c3fe4
NA		 7461 int r;
7462
7463 r = kvm_x86_ops->hardware_setup();
7464 if (r != 0)
7465 return r;
7466
35181e86
HZ		 7467 if (kvm_has_tsc_control) {
7468 /*
7469 * Make sure the user can only configure tsc_khz values that
7470 * fit into a signed integer.
7471 * A min value is not calculated needed because it will always
7472 * be 1 on all machines.
7473 */
7474 u64 max = min(0x7fffffffULL,
7475 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7476 kvm_max_guest_tsc_khz = max;
7477
ad721883 7478 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7479 }
ad721883 7480
9e9c3fe4
NA		 7481 kvm_init_msr_list();
7482 return 0;
e9b11c17
ZX		 7483}
7484
7485void kvm_arch_hardware_unsetup(void)
7486{
7487 kvm_x86_ops->hardware_unsetup();
7488}
7489
7490void kvm_arch_check_processor_compat(void *rtn)
7491{
7492 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7493}
7494
7495bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7496{
7497 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7498}
7499EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7500
7501bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7502{
7503 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7504}
7505
3e515705
AK		 7506bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7507{
35754c98 7508 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7509}
7510
54e9818f
GN		 7511struct static_key kvm_no_apic_vcpu __read_mostly;
7512
e9b11c17
ZX		 7513int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7514{
7515 struct page *page;
7516 struct kvm *kvm;
7517 int r;
7518
7519 BUG_ON(vcpu->kvm == NULL);
7520 kvm = vcpu->kvm;
7521
6aef266c 7522 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7523 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7524 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7525 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7526 else
a4535290 7527 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7528
7529 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7530 if (!page) {
7531 r = -ENOMEM;
7532 goto fail;
7533 }
ad312c7c 7534 vcpu->arch.pio_data = page_address(page);
e9b11c17 7535
cc578287 7536 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7537
e9b11c17
ZX		 7538 r = kvm_mmu_create(vcpu);
7539 if (r < 0)
7540 goto fail_free_pio_data;
7541
7542 if (irqchip_in_kernel(kvm)) {
7543 r = kvm_create_lapic(vcpu);
7544 if (r < 0)
7545 goto fail_mmu_destroy;
54e9818f
GN		 7546 } else
7547 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7548
890ca9ae
HY		 7549 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7550 GFP_KERNEL);
7551 if (!vcpu->arch.mce_banks) {
7552 r = -ENOMEM;
443c39bc 7553 goto fail_free_lapic;
890ca9ae
HY		 7554 }
7555 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7556
f1797359
WY		 7557 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7558 r = -ENOMEM;
f5f48ee1 7559 goto fail_free_mce_banks;
f1797359 7560 }
f5f48ee1 7561
0ee6a517 7562 fx_init(vcpu);
66f7b72e 7563
ba904635 7564 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7565 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7566
7567 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7568 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7569
5a4f55cd
EK		 7570 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7571
74545705
RK		 7572 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7573
af585b92 7574 kvm_async_pf_hash_reset(vcpu);
f5132b01 7575 kvm_pmu_init(vcpu);
af585b92 7576
1c1a9ce9
SR		 7577 vcpu->arch.pending_external_vector = -1;
7578
e9b11c17 7579 return 0;
0ee6a517 7580
f5f48ee1
SY		 7581fail_free_mce_banks:
7582 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7583fail_free_lapic:
7584 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7585fail_mmu_destroy:
7586 kvm_mmu_destroy(vcpu);
7587fail_free_pio_data:
ad312c7c 7588 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7589fail:
7590 return r;
7591}
7592
7593void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7594{
f656ce01
MT		 7595 int idx;
7596
f5132b01 7597 kvm_pmu_destroy(vcpu);
36cb93fd 7598 kfree(vcpu->arch.mce_banks);
e9b11c17 7599 kvm_free_lapic(vcpu);
f656ce01 7600 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7601 kvm_mmu_destroy(vcpu);
f656ce01 7602 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7603 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7604 if (!lapic_in_kernel(vcpu))
54e9818f 7605 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7606}
d19a9cd2 7607
e790d9ef
RK		 7608void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7609{
ae97a3b8 7610 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7611}
7612
e08b9637 7613int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7614{
e08b9637
CO		 7615 if (type)
7616 return -EINVAL;
7617
6ef768fa 7618 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7619 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7620 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7621 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7622 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7623
5550af4d
SY		 7624 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7625 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7626 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7627 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7628 &kvm->arch.irq_sources_bitmap);
5550af4d 7629
038f8c11 7630 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7631 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7632 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7633
7634 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7635
7e44e449 7636 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7637 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7638
d89f5eff 7639 return 0;
d19a9cd2
ZX		 7640}
7641
7642static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7643{
9fc77441
MT		 7644 int r;
7645 r = vcpu_load(vcpu);
7646 BUG_ON(r);
d19a9cd2
ZX		 7647 kvm_mmu_unload(vcpu);
7648 vcpu_put(vcpu);
7649}
7650
7651static void kvm_free_vcpus(struct kvm *kvm)
7652{
7653 unsigned int i;
988a2cae 7654 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7655
7656 /*
7657 * Unpin any mmu pages first.
7658 */
af585b92
GN		 7659 kvm_for_each_vcpu(i, vcpu, kvm) {
7660 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7661 kvm_unload_vcpu_mmu(vcpu);
af585b92 7662 }
988a2cae
GN		 7663 kvm_for_each_vcpu(i, vcpu, kvm)
7664 kvm_arch_vcpu_free(vcpu);
7665
7666 mutex_lock(&kvm->lock);
7667 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7668 kvm->vcpus[i] = NULL;
d19a9cd2 7669
988a2cae
GN		 7670 atomic_set(&kvm->online_vcpus, 0);
7671 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7672}
7673
ad8ba2cd
SY		 7674void kvm_arch_sync_events(struct kvm *kvm)
7675{
332967a3 7676 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7677 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7678 kvm_free_all_assigned_devices(kvm);
aea924f6 7679 kvm_free_pit(kvm);
ad8ba2cd
SY		 7680}
7681
1d8007bd 7682int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7683{
7684 int i, r;
25188b99 7685 unsigned long hva;
f0d648bd
PB		 7686 struct kvm_memslots *slots = kvm_memslots(kvm);
7687 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7688
7689 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7690 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7691 return -EINVAL;
9da0e4d5 7692
f0d648bd
PB		 7693 slot = id_to_memslot(slots, id);
7694 if (size) {
7695 if (WARN_ON(slot->npages))
7696 return -EEXIST;
7697
7698 /*
7699 * MAP_SHARED to prevent internal slot pages from being moved
7700 * by fork()/COW.
7701 */
7702 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7703 MAP_SHARED | MAP_ANONYMOUS, 0);
7704 if (IS_ERR((void *)hva))
7705 return PTR_ERR((void *)hva);
7706 } else {
7707 if (!slot->npages)
7708 return 0;
9da0e4d5 7709
f0d648bd
PB		 7710 hva = 0;
7711 }
7712
7713 old = *slot;
9da0e4d5 7714 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7715 struct kvm_userspace_memory_region m;
9da0e4d5 7716
1d8007bd
PB		 7717 m.slot = id | (i << 16);
7718 m.flags = 0;
7719 m.guest_phys_addr = gpa;
f0d648bd 7720 m.userspace_addr = hva;
1d8007bd 7721 m.memory_size = size;
9da0e4d5
PB		 7722 r = __kvm_set_memory_region(kvm, &m);
7723 if (r < 0)
7724 return r;
7725 }
7726
f0d648bd
PB		 7727 if (!size) {
7728 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7729 WARN_ON(r < 0);
7730 }
7731
9da0e4d5
PB		 7732 return 0;
7733}
7734EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7735
1d8007bd 7736int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7737{
7738 int r;
7739
7740 mutex_lock(&kvm->slots_lock);
1d8007bd 7741 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7742 mutex_unlock(&kvm->slots_lock);
7743
7744 return r;
7745}
7746EXPORT_SYMBOL_GPL(x86_set_memory_region);
7747
d19a9cd2
ZX		 7748void kvm_arch_destroy_vm(struct kvm *kvm)
7749{
27469d29
AH		 7750 if (current->mm == kvm->mm) {
7751 /*
7752 * Free memory regions allocated on behalf of userspace,
7753 * unless the the memory map has changed due to process exit
7754 * or fd copying.
7755 */
1d8007bd
PB		 7756 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7757 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7758 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7759 }
6eb55818 7760 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7761 kfree(kvm->arch.vpic);
7762 kfree(kvm->arch.vioapic);
d19a9cd2 7763 kvm_free_vcpus(kvm);
1e08ec4a 7764 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7765}
0de10343 7766
5587027c 7767void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7768 struct kvm_memory_slot *dont)
7769{
7770 int i;
7771
d89cc617
TY		 7772 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7773 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7774 kvfree(free->arch.rmap[i]);
d89cc617 7775 free->arch.rmap[i] = NULL;
77d11309 7776 }
d89cc617
TY		 7777 if (i == 0)
7778 continue;
7779
7780 if (!dont || free->arch.lpage_info[i - 1] !=
7781 dont->arch.lpage_info[i - 1]) {
548ef284 7782 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7783 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7784 }
7785 }
7786}
7787
5587027c
AK		 7788int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7789 unsigned long npages)
db3fe4eb
TY		 7790{
7791 int i;
7792
d89cc617 7793 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7794 unsigned long ugfn;
7795 int lpages;
d89cc617 7796 int level = i + 1;
db3fe4eb
TY		 7797
7798 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7799 slot->base_gfn, level) + 1;
7800
d89cc617
TY		 7801 slot->arch.rmap[i] =
7802 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7803 if (!slot->arch.rmap[i])
77d11309 7804 goto out_free;
d89cc617
TY		 7805 if (i == 0)
7806 continue;
77d11309 7807
d89cc617
TY		 7808 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7809 sizeof(*slot->arch.lpage_info[i - 1]));
7810 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7811 goto out_free;
7812
7813 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7814 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7815 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7816 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7817 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7818 /*
7819 * If the gfn and userspace address are not aligned wrt each
7820 * other, or if explicitly asked to, disable large page
7821 * support for this slot
7822 */
7823 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7824 !kvm_largepages_enabled()) {
7825 unsigned long j;
7826
7827 for (j = 0; j < lpages; ++j)
d89cc617 7828 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7829 }
7830 }
7831
7832 return 0;
7833
7834out_free:
d89cc617 7835 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7836 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7837 slot->arch.rmap[i] = NULL;
7838 if (i == 0)
7839 continue;
7840
548ef284 7841 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7842 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7843 }
7844 return -ENOMEM;
7845}
7846
15f46015 7847void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7848{
e6dff7d1
TY		 7849 /*
7850 * memslots->generation has been incremented.
7851 * mmio generation may have reached its maximum value.
7852 */
54bf36aa 7853 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7854}
7855
f7784b8e
MT		 7856int kvm_arch_prepare_memory_region(struct kvm *kvm,
7857 struct kvm_memory_slot *memslot,
09170a49 7858 const struct kvm_userspace_memory_region *mem,
7b6195a9 7859 enum kvm_mr_change change)
0de10343 7860{
f7784b8e
MT		 7861 return 0;
7862}
7863
88178fd4
KH		 7864static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7865 struct kvm_memory_slot *new)
7866{
7867 /* Still write protect RO slot */
7868 if (new->flags & KVM_MEM_READONLY) {
7869 kvm_mmu_slot_remove_write_access(kvm, new);
7870 return;
7871 }
7872
7873 /*
7874 * Call kvm_x86_ops dirty logging hooks when they are valid.
7875 *
7876 * kvm_x86_ops->slot_disable_log_dirty is called when:
7877 *
7878 * - KVM_MR_CREATE with dirty logging is disabled
7879 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7880 *
7881 * The reason is, in case of PML, we need to set D-bit for any slots
7882 * with dirty logging disabled in order to eliminate unnecessary GPA
7883 * logging in PML buffer (and potential PML buffer full VMEXT). This
7884 * guarantees leaving PML enabled during guest's lifetime won't have
7885 * any additonal overhead from PML when guest is running with dirty
7886 * logging disabled for memory slots.
7887 *
7888 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7889 * to dirty logging mode.
7890 *
7891 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7892 *
7893 * In case of write protect:
7894 *
7895 * Write protect all pages for dirty logging.
7896 *
7897 * All the sptes including the large sptes which point to this
7898 * slot are set to readonly. We can not create any new large
7899 * spte on this slot until the end of the logging.
7900 *
7901 * See the comments in fast_page_fault().
7902 */
7903 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7904 if (kvm_x86_ops->slot_enable_log_dirty)
7905 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7906 else
7907 kvm_mmu_slot_remove_write_access(kvm, new);
7908 } else {
7909 if (kvm_x86_ops->slot_disable_log_dirty)
7910 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7911 }
7912}
7913
f7784b8e 7914void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7915 const struct kvm_userspace_memory_region *mem,
8482644a 7916 const struct kvm_memory_slot *old,
f36f3f28 7917 const struct kvm_memory_slot *new,
8482644a 7918 enum kvm_mr_change change)
f7784b8e 7919{
8482644a 7920 int nr_mmu_pages = 0;
f7784b8e 7921
48c0e4e9
XG		 7922 if (!kvm->arch.n_requested_mmu_pages)
7923 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7924
48c0e4e9 7925 if (nr_mmu_pages)
0de10343 7926 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7927
3ea3b7fa
WL		 7928 /*
7929 * Dirty logging tracks sptes in 4k granularity, meaning that large
7930 * sptes have to be split. If live migration is successful, the guest
7931 * in the source machine will be destroyed and large sptes will be
7932 * created in the destination. However, if the guest continues to run
7933 * in the source machine (for example if live migration fails), small
7934 * sptes will remain around and cause bad performance.
7935 *
7936 * Scan sptes if dirty logging has been stopped, dropping those
7937 * which can be collapsed into a single large-page spte. Later
7938 * page faults will create the large-page sptes.
7939 */
7940 if ((change != KVM_MR_DELETE) &&
7941 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7942 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7943 kvm_mmu_zap_collapsible_sptes(kvm, new);
7944
c972f3b1 7945 /*
88178fd4 7946 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7947 *
88178fd4
KH		 7948 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7949 * been zapped so no dirty logging staff is needed for old slot. For
7950 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7951 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7952 *
7953 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7954 */
88178fd4 7955 if (change != KVM_MR_DELETE)
f36f3f28 7956 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7957}
1d737c8a 7958
2df72e9b 7959void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7960{
6ca18b69 7961 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7962}
7963
2df72e9b
MT		 7964void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7965 struct kvm_memory_slot *slot)
7966{
6ca18b69 7967 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7968}
7969
5d9bc648
PB		 7970static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7971{
7972 if (!list_empty_careful(&vcpu->async_pf.done))
7973 return true;
7974
7975 if (kvm_apic_has_events(vcpu))
7976 return true;
7977
7978 if (vcpu->arch.pv.pv_unhalted)
7979 return true;
7980
7981 if (atomic_read(&vcpu->arch.nmi_queued))
7982 return true;
7983
73917739
PB		 7984 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7985 return true;
7986
5d9bc648
PB		 7987 if (kvm_arch_interrupt_allowed(vcpu) &&
7988 kvm_cpu_has_interrupt(vcpu))
7989 return true;
7990
7991 return false;
7992}
7993
1d737c8a
ZX		 7994int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7995{
b6b8a145
JK		 7996 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7997 kvm_x86_ops->check_nested_events(vcpu, false);
7998
5d9bc648 7999 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8000}
5736199a 8001
b6d33834 8002int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8003{
b6d33834 8004 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8005}
78646121
GN		 8006
8007int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8008{
8009 return kvm_x86_ops->interrupt_allowed(vcpu);
8010}
229456fc 8011
82b32774 8012unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8013{
82b32774
NA		 8014 if (is_64_bit_mode(vcpu))
8015 return kvm_rip_read(vcpu);
8016 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8017 kvm_rip_read(vcpu));
8018}
8019EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8020
82b32774
NA		 8021bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8022{
8023 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8024}
8025EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8026
94fe45da
JK		 8027unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8028{
8029 unsigned long rflags;
8030
8031 rflags = kvm_x86_ops->get_rflags(vcpu);
8032 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8033 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8034 return rflags;
8035}
8036EXPORT_SYMBOL_GPL(kvm_get_rflags);
8037
6addfc42 8038static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8039{
8040 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8041 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8042 rflags |= X86_EFLAGS_TF;
94fe45da 8043 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8044}
8045
8046void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8047{
8048 __kvm_set_rflags(vcpu, rflags);
3842d135 8049 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8050}
8051EXPORT_SYMBOL_GPL(kvm_set_rflags);
8052
56028d08
GN		 8053void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8054{
8055 int r;
8056
fb67e14f 8057 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8058 work->wakeup_all)
56028d08
GN		 8059 return;
8060
8061 r = kvm_mmu_reload(vcpu);
8062 if (unlikely(r))
8063 return;
8064
fb67e14f
XG		 8065 if (!vcpu->arch.mmu.direct_map &&
8066 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8067 return;
8068
56028d08
GN		 8069 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8070}
8071
af585b92
GN		 8072static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8073{
8074 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8075}
8076
8077static inline u32 kvm_async_pf_next_probe(u32 key)
8078{
8079 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8080}
8081
8082static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8083{
8084 u32 key = kvm_async_pf_hash_fn(gfn);
8085
8086 while (vcpu->arch.apf.gfns[key] != ~0)
8087 key = kvm_async_pf_next_probe(key);
8088
8089 vcpu->arch.apf.gfns[key] = gfn;
8090}
8091
8092static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8093{
8094 int i;
8095 u32 key = kvm_async_pf_hash_fn(gfn);
8096
8097 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8098 (vcpu->arch.apf.gfns[key] != gfn &&
8099 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8100 key = kvm_async_pf_next_probe(key);
8101
8102 return key;
8103}
8104
8105bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8106{
8107 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8108}
8109
8110static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8111{
8112 u32 i, j, k;
8113
8114 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8115 while (true) {
8116 vcpu->arch.apf.gfns[i] = ~0;
8117 do {
8118 j = kvm_async_pf_next_probe(j);
8119 if (vcpu->arch.apf.gfns[j] == ~0)
8120 return;
8121 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8122 /*
8123 * k lies cyclically in ]i,j]
8124 * | i.k.j |
8125 * |....j i.k.| or |.k..j i...|
8126 */
8127 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8128 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8129 i = j;
8130 }
8131}
8132
7c90705b
GN		 8133static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8134{
8135
8136 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8137 sizeof(val));
8138}
8139
af585b92
GN		 8140void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8141 struct kvm_async_pf *work)
8142{
6389ee94
AK		 8143 struct x86_exception fault;
8144
7c90705b 8145 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8146 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8147
8148 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8149 (vcpu->arch.apf.send_user_only &&
8150 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8151 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8152 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8153 fault.vector = PF_VECTOR;
8154 fault.error_code_valid = true;
8155 fault.error_code = 0;
8156 fault.nested_page_fault = false;
8157 fault.address = work->arch.token;
8158 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8159 }
af585b92
GN		 8160}
8161
8162void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8163 struct kvm_async_pf *work)
8164{
6389ee94
AK		 8165 struct x86_exception fault;
8166
7c90705b 8167 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8168 if (work->wakeup_all)
7c90705b
GN		 8169 work->arch.token = ~0; /* broadcast wakeup */
8170 else
8171 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8172
8173 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8174 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8175 fault.vector = PF_VECTOR;
8176 fault.error_code_valid = true;
8177 fault.error_code = 0;
8178 fault.nested_page_fault = false;
8179 fault.address = work->arch.token;
8180 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8181 }
e6d53e3b 8182 vcpu->arch.apf.halted = false;
a4fa1635 8183 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8184}
8185
8186bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8187{
8188 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8189 return true;
8190 else
8191 return !kvm_event_needs_reinjection(vcpu) &&
8192 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8193}
8194
5544eb9b
PB		 8195void kvm_arch_start_assignment(struct kvm *kvm)
8196{
8197 atomic_inc(&kvm->arch.assigned_device_count);
8198}
8199EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8200
8201void kvm_arch_end_assignment(struct kvm *kvm)
8202{
8203 atomic_dec(&kvm->arch.assigned_device_count);
8204}
8205EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8206
8207bool kvm_arch_has_assigned_device(struct kvm *kvm)
8208{
8209 return atomic_read(&kvm->arch.assigned_device_count);
8210}
8211EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8212
e0f0bbc5
AW		 8213void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8214{
8215 atomic_inc(&kvm->arch.noncoherent_dma_count);
8216}
8217EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8218
8219void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8220{
8221 atomic_dec(&kvm->arch.noncoherent_dma_count);
8222}
8223EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8224
8225bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8226{
8227 return atomic_read(&kvm->arch.noncoherent_dma_count);
8228}
8229EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8230
87276880
FW		 8231int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8232 struct irq_bypass_producer *prod)
8233{
8234 struct kvm_kernel_irqfd *irqfd =
8235 container_of(cons, struct kvm_kernel_irqfd, consumer);
8236
8237 if (kvm_x86_ops->update_pi_irte) {
8238 irqfd->producer = prod;
8239 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8240 prod->irq, irqfd->gsi, 1);
8241 }
8242
8243 return -EINVAL;
8244}
8245
8246void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8247 struct irq_bypass_producer *prod)
8248{
8249 int ret;
8250 struct kvm_kernel_irqfd *irqfd =
8251 container_of(cons, struct kvm_kernel_irqfd, consumer);
8252
8253 if (!kvm_x86_ops->update_pi_irte) {
8254 WARN_ON(irqfd->producer != NULL);
8255 return;
8256 }
8257
8258 WARN_ON(irqfd->producer != prod);
8259 irqfd->producer = NULL;
8260
8261 /*
8262 * When producer of consumer is unregistered, we change back to
8263 * remapped mode, so we can re-use the current implementation
8264 * when the irq is masked/disabed or the consumer side (KVM
8265 * int this case doesn't want to receive the interrupts.
8266 */
8267 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8268 if (ret)
8269 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8270 " fails: %d\n", irqfd->consumer.token, ret);
8271}
8272
8273int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8274 uint32_t guest_irq, bool set)
8275{
8276 if (!kvm_x86_ops->update_pi_irte)
8277 return -EINVAL;
8278
8279 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8280}
8281
229456fc 8282EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8283EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8284EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8285EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8286EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8287EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8288EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8289EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8290EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8291EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8292EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8293EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8294EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8295EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8296EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8297EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8298EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux kernel - Deliverables
This page took 2.562908 seconds and 5 git commands to generate.