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kvm, vmx: Really fix lazy FPU on nested guest
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
afcbf13f 655 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 656 return 1;
657
a03490ed 658 if (is_long_mode(vcpu)) {
0f12244f
GN		 659 if (!(cr4 & X86_CR4_PAE))
660 return 1;
a2edf57f
AK		 661 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
662 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 663 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
664 kvm_read_cr3(vcpu)))
0f12244f
GN		 665 return 1;
666
ad756a16
MJ		 667 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
668 if (!guest_cpuid_has_pcid(vcpu))
669 return 1;
670
671 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
672 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
673 return 1;
674 }
675
5e1746d6 676 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 677 return 1;
a03490ed 678
ad756a16
MJ		 679 if (((cr4 ^ old_cr4) & pdptr_bits) ||
680 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 681 kvm_mmu_reset_context(vcpu);
0f12244f 682
2acf923e 683 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 684 kvm_update_cpuid(vcpu);
2acf923e 685
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 689
2390218b 690int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 691{
9f8fe504 692 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 693 kvm_mmu_sync_roots(vcpu);
d835dfec 694 kvm_mmu_flush_tlb(vcpu);
0f12244f 695 return 0;
d835dfec
AK		 696 }
697
a03490ed 698 if (is_long_mode(vcpu)) {
471842ec 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 700 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
701 return 1;
702 } else
703 if (cr3 & CR3_L_MODE_RESERVED_BITS)
704 return 1;
a03490ed
CO		 705 } else {
706 if (is_pae(vcpu)) {
0f12244f
GN		 707 if (cr3 & CR3_PAE_RESERVED_BITS)
708 return 1;
ff03a073
JR		 709 if (is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 711 return 1;
a03490ed
CO		 712 }
713 /*
714 * We don't check reserved bits in nonpae mode, because
715 * this isn't enforced, and VMware depends on this.
716 */
717 }
718
0f12244f 719 vcpu->arch.cr3 = cr3;
aff48baa 720 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 721 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 722 return 0;
723}
2d3ad1f4 724EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 725
eea1cff9 726int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 727{
0f12244f
GN		 728 if (cr8 & CR8_RESERVED_BITS)
729 return 1;
a03490ed
CO		 730 if (irqchip_in_kernel(vcpu->kvm))
731 kvm_lapic_set_tpr(vcpu, cr8);
732 else
ad312c7c 733 vcpu->arch.cr8 = cr8;
0f12244f
GN		 734 return 0;
735}
2d3ad1f4 736EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 737
2d3ad1f4 738unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 739{
740 if (irqchip_in_kernel(vcpu->kvm))
741 return kvm_lapic_get_cr8(vcpu);
742 else
ad312c7c 743 return vcpu->arch.cr8;
a03490ed 744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 746
73aaf249
JK		 747static void kvm_update_dr6(struct kvm_vcpu *vcpu)
748{
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
751}
752
c8639010
JK		 753static void kvm_update_dr7(struct kvm_vcpu *vcpu)
754{
755 unsigned long dr7;
756
757 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
758 dr7 = vcpu->arch.guest_debug_dr7;
759 else
760 dr7 = vcpu->arch.dr7;
761 kvm_x86_ops->set_dr7(vcpu, dr7);
762 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
763}
764
338dbc97 765static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 766{
767 switch (dr) {
768 case 0 ... 3:
769 vcpu->arch.db[dr] = val;
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 vcpu->arch.eff_db[dr] = val;
772 break;
773 case 4:
338dbc97
GN		 774 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
775 return 1; /* #UD */
020df079
GN		 776 /* fall through */
777 case 6:
338dbc97
GN		 778 if (val & 0xffffffff00000000ULL)
779 return -1; /* #GP */
020df079 780 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 781 kvm_update_dr6(vcpu);
020df079
GN		 782 break;
783 case 5:
338dbc97
GN		 784 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
785 return 1; /* #UD */
020df079
GN		 786 /* fall through */
787 default: /* 7 */
338dbc97
GN		 788 if (val & 0xffffffff00000000ULL)
789 return -1; /* #GP */
020df079 790 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 791 kvm_update_dr7(vcpu);
020df079
GN		 792 break;
793 }
794
795 return 0;
796}
338dbc97
GN		 797
798int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
799{
800 int res;
801
802 res = __kvm_set_dr(vcpu, dr, val);
803 if (res > 0)
804 kvm_queue_exception(vcpu, UD_VECTOR);
805 else if (res < 0)
806 kvm_inject_gp(vcpu, 0);
807
808 return res;
809}
020df079
GN		 810EXPORT_SYMBOL_GPL(kvm_set_dr);
811
338dbc97 812static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 813{
814 switch (dr) {
815 case 0 ... 3:
816 *val = vcpu->arch.db[dr];
817 break;
818 case 4:
338dbc97 819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 820 return 1;
020df079
GN		 821 /* fall through */
822 case 6:
73aaf249
JK		 823 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
824 *val = vcpu->arch.dr6;
825 else
826 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 827 break;
828 case 5:
338dbc97 829 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 830 return 1;
020df079
GN		 831 /* fall through */
832 default: /* 7 */
833 *val = vcpu->arch.dr7;
834 break;
835 }
836
837 return 0;
838}
338dbc97
GN		 839
840int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
841{
842 if (_kvm_get_dr(vcpu, dr, val)) {
843 kvm_queue_exception(vcpu, UD_VECTOR);
844 return 1;
845 }
846 return 0;
847}
020df079
GN		 848EXPORT_SYMBOL_GPL(kvm_get_dr);
849
022cd0e8
AK		 850bool kvm_rdpmc(struct kvm_vcpu *vcpu)
851{
852 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
853 u64 data;
854 int err;
855
856 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
857 if (err)
858 return err;
859 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
860 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
861 return err;
862}
863EXPORT_SYMBOL_GPL(kvm_rdpmc);
864
043405e1
CO		 865/*
866 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
867 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
868 *
869 * This list is modified at module load time to reflect the
e3267cbb
GC		 870 * capabilities of the host cpu. This capabilities test skips MSRs that are
871 * kvm-specific. Those are put in the beginning of the list.
043405e1 872 */
e3267cbb 873
e984097b 874#define KVM_SAVE_MSRS_BEGIN 12
043405e1 875static u32 msrs_to_save[] = {
e3267cbb 876 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 877 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 878 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 879 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 880 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 881 MSR_KVM_PV_EOI_EN,
043405e1 882 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 883 MSR_STAR,
043405e1
CO		 884#ifdef CONFIG_X86_64
885 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
886#endif
b3897a49 887 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 888 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 889};
890
891static unsigned num_msrs_to_save;
892
f1d24831 893static const u32 emulated_msrs[] = {
ba904635 894 MSR_IA32_TSC_ADJUST,
a3e06bbe 895 MSR_IA32_TSCDEADLINE,
043405e1 896 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 897 MSR_IA32_MCG_STATUS,
898 MSR_IA32_MCG_CTL,
043405e1
CO		 899};
900
384bb783 901bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 902{
b69e8cae 903 if (efer & efer_reserved_bits)
384bb783 904 return false;
15c4a640 905
1b2fd70c
AG		 906 if (efer & EFER_FFXSR) {
907 struct kvm_cpuid_entry2 *feat;
908
909 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 910 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 911 return false;
1b2fd70c
AG		 912 }
913
d8017474
AG		 914 if (efer & EFER_SVME) {
915 struct kvm_cpuid_entry2 *feat;
916
917 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 918 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 919 return false;
d8017474
AG		 920 }
921
384bb783
JK		 922 return true;
923}
924EXPORT_SYMBOL_GPL(kvm_valid_efer);
925
926static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
927{
928 u64 old_efer = vcpu->arch.efer;
929
930 if (!kvm_valid_efer(vcpu, efer))
931 return 1;
932
933 if (is_paging(vcpu)
934 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
935 return 1;
936
15c4a640 937 efer &= ~EFER_LMA;
f6801dff 938 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 939
a3d204e2
SY		 940 kvm_x86_ops->set_efer(vcpu, efer);
941
aad82703
SY		 942 /* Update reserved bits */
943 if ((efer ^ old_efer) & EFER_NX)
944 kvm_mmu_reset_context(vcpu);
945
b69e8cae 946 return 0;
15c4a640
CO		 947}
948
f2b4b7dd
JR		 949void kvm_enable_efer_bits(u64 mask)
950{
951 efer_reserved_bits &= ~mask;
952}
953EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
954
955
15c4a640
CO		 956/*
957 * Writes msr value into into the appropriate "register".
958 * Returns 0 on success, non-0 otherwise.
959 * Assumes vcpu_load() was already called.
960 */
8fe8ab46 961int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 962{
8fe8ab46 963 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 964}
965
313a3dc7
CO		 966/*
967 * Adapt set_msr() to msr_io()'s calling convention
968 */
969static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
970{
8fe8ab46
WA		 971 struct msr_data msr;
972
973 msr.data = *data;
974 msr.index = index;
975 msr.host_initiated = true;
976 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 977}
978
16e8d74d
MT		 979#ifdef CONFIG_X86_64
980struct pvclock_gtod_data {
981 seqcount_t seq;
982
983 struct { /* extract of a clocksource struct */
984 int vclock_mode;
985 cycle_t cycle_last;
986 cycle_t mask;
987 u32 mult;
988 u32 shift;
989 } clock;
990
991 /* open coded 'struct timespec' */
992 u64 monotonic_time_snsec;
993 time_t monotonic_time_sec;
994};
995
996static struct pvclock_gtod_data pvclock_gtod_data;
997
998static void update_pvclock_gtod(struct timekeeper *tk)
999{
1000 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1001
1002 write_seqcount_begin(&vdata->seq);
1003
1004 /* copy pvclock gtod data */
1005 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1006 vdata->clock.cycle_last = tk->clock->cycle_last;
1007 vdata->clock.mask = tk->clock->mask;
1008 vdata->clock.mult = tk->mult;
1009 vdata->clock.shift = tk->shift;
1010
1011 vdata->monotonic_time_sec = tk->xtime_sec
1012 + tk->wall_to_monotonic.tv_sec;
1013 vdata->monotonic_time_snsec = tk->xtime_nsec
1014 + (tk->wall_to_monotonic.tv_nsec
1015 << tk->shift);
1016 while (vdata->monotonic_time_snsec >=
1017 (((u64)NSEC_PER_SEC) << tk->shift)) {
1018 vdata->monotonic_time_snsec -=
1019 ((u64)NSEC_PER_SEC) << tk->shift;
1020 vdata->monotonic_time_sec++;
1021 }
1022
1023 write_seqcount_end(&vdata->seq);
1024}
1025#endif
1026
1027
18068523
GOC		 1028static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1029{
9ed3c444
AK		 1030 int version;
1031 int r;
50d0a0f9 1032 struct pvclock_wall_clock wc;
923de3cf 1033 struct timespec boot;
18068523
GOC		 1034
1035 if (!wall_clock)
1036 return;
1037
9ed3c444
AK		 1038 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1039 if (r)
1040 return;
1041
1042 if (version & 1)
1043 ++version; /* first time write, random junk */
1044
1045 ++version;
18068523 1046
18068523
GOC		 1047 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1048
50d0a0f9
GH		 1049 /*
1050 * The guest calculates current wall clock time by adding
34c238a1 1051 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1052 * wall clock specified here. guest system time equals host
1053 * system time for us, thus we must fill in host boot time here.
1054 */
923de3cf 1055 getboottime(&boot);
50d0a0f9 1056
4b648665
BR		 1057 if (kvm->arch.kvmclock_offset) {
1058 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1059 boot = timespec_sub(boot, ts);
1060 }
50d0a0f9
GH		 1061 wc.sec = boot.tv_sec;
1062 wc.nsec = boot.tv_nsec;
1063 wc.version = version;
18068523
GOC		 1064
1065 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1066
1067 version++;
1068 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1069}
1070
50d0a0f9
GH		 1071static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1072{
1073 uint32_t quotient, remainder;
1074
1075 /* Don't try to replace with do_div(), this one calculates
1076 * "(dividend << 32) / divisor" */
1077 __asm__ ( "divl %4"
1078 : "=a" (quotient), "=d" (remainder)
1079 : "0" (0), "1" (dividend), "r" (divisor) );
1080 return quotient;
1081}
1082
5f4e3f88
ZA		 1083static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1084 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1085{
5f4e3f88 1086 uint64_t scaled64;
50d0a0f9
GH		 1087 int32_t shift = 0;
1088 uint64_t tps64;
1089 uint32_t tps32;
1090
5f4e3f88
ZA		 1091 tps64 = base_khz * 1000LL;
1092 scaled64 = scaled_khz * 1000LL;
50933623 1093 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1094 tps64 >>= 1;
1095 shift--;
1096 }
1097
1098 tps32 = (uint32_t)tps64;
50933623
JK		 1099 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1100 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1101 scaled64 >>= 1;
1102 else
1103 tps32 <<= 1;
50d0a0f9
GH		 1104 shift++;
1105 }
1106
5f4e3f88
ZA		 1107 *pshift = shift;
1108 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1109
5f4e3f88
ZA		 1110 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1111 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1112}
1113
759379dd
ZA		 1114static inline u64 get_kernel_ns(void)
1115{
1116 struct timespec ts;
1117
1118 WARN_ON(preemptible());
1119 ktime_get_ts(&ts);
1120 monotonic_to_bootbased(&ts);
1121 return timespec_to_ns(&ts);
50d0a0f9
GH		 1122}
1123
d828199e 1124#ifdef CONFIG_X86_64
16e8d74d 1125static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1126#endif
16e8d74d 1127
c8076604 1128static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1129unsigned long max_tsc_khz;
c8076604 1130
cc578287 1131static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1132{
cc578287
ZA		 1133 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1134 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1135}
1136
cc578287 1137static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1138{
cc578287
ZA		 1139 u64 v = (u64)khz * (1000000 + ppm);
1140 do_div(v, 1000000);
1141 return v;
1e993611
JR		 1142}
1143
cc578287 1144static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1145{
cc578287
ZA		 1146 u32 thresh_lo, thresh_hi;
1147 int use_scaling = 0;
217fc9cf 1148
03ba32ca
MT		 1149 /* tsc_khz can be zero if TSC calibration fails */
1150 if (this_tsc_khz == 0)
1151 return;
1152
c285545f
ZA		 1153 /* Compute a scale to convert nanoseconds in TSC cycles */
1154 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1155 &vcpu->arch.virtual_tsc_shift,
1156 &vcpu->arch.virtual_tsc_mult);
1157 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1158
1159 /*
1160 * Compute the variation in TSC rate which is acceptable
1161 * within the range of tolerance and decide if the
1162 * rate being applied is within that bounds of the hardware
1163 * rate. If so, no scaling or compensation need be done.
1164 */
1165 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1166 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1167 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1168 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1169 use_scaling = 1;
1170 }
1171 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1172}
1173
1174static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1175{
e26101b1 1176 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1177 vcpu->arch.virtual_tsc_mult,
1178 vcpu->arch.virtual_tsc_shift);
e26101b1 1179 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1180 return tsc;
1181}
1182
b48aa97e
MT		 1183void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1184{
1185#ifdef CONFIG_X86_64
1186 bool vcpus_matched;
1187 bool do_request = false;
1188 struct kvm_arch *ka = &vcpu->kvm->arch;
1189 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1190
1191 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1192 atomic_read(&vcpu->kvm->online_vcpus));
1193
1194 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1195 if (!ka->use_master_clock)
1196 do_request = 1;
1197
1198 if (!vcpus_matched && ka->use_master_clock)
1199 do_request = 1;
1200
1201 if (do_request)
1202 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1203
1204 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1205 atomic_read(&vcpu->kvm->online_vcpus),
1206 ka->use_master_clock, gtod->clock.vclock_mode);
1207#endif
1208}
1209
ba904635
WA		 1210static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1211{
1212 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1213 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1214}
1215
8fe8ab46 1216void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1217{
1218 struct kvm *kvm = vcpu->kvm;
f38e098f 1219 u64 offset, ns, elapsed;
99e3e30a 1220 unsigned long flags;
02626b6a 1221 s64 usdiff;
b48aa97e 1222 bool matched;
8fe8ab46 1223 u64 data = msr->data;
99e3e30a 1224
038f8c11 1225 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1226 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1227 ns = get_kernel_ns();
f38e098f 1228 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1229
03ba32ca 1230 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1231 int faulted = 0;
1232
03ba32ca
MT		 1233 /* n.b - signed multiplication and division required */
1234 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1235#ifdef CONFIG_X86_64
03ba32ca 1236 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1237#else
03ba32ca 1238 /* do_div() only does unsigned */
8915aa27
MT		 1239 asm("1: idivl %[divisor]\n"
1240 "2: xor %%edx, %%edx\n"
1241 " movl $0, %[faulted]\n"
1242 "3:\n"
1243 ".section .fixup,\"ax\"\n"
1244 "4: movl $1, %[faulted]\n"
1245 " jmp 3b\n"
1246 ".previous\n"
1247
1248 _ASM_EXTABLE(1b, 4b)
1249
1250 : "=A"(usdiff), [faulted] "=r" (faulted)
1251 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1252
5d3cb0f6 1253#endif
03ba32ca
MT		 1254 do_div(elapsed, 1000);
1255 usdiff -= elapsed;
1256 if (usdiff < 0)
1257 usdiff = -usdiff;
8915aa27
MT		 1258
1259 /* idivl overflow => difference is larger than USEC_PER_SEC */
1260 if (faulted)
1261 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1262 } else
1263 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1264
1265 /*
5d3cb0f6
ZA		 1266 * Special case: TSC write with a small delta (1 second) of virtual
1267 * cycle time against real time is interpreted as an attempt to
1268 * synchronize the CPU.
1269 *
1270 * For a reliable TSC, we can match TSC offsets, and for an unstable
1271 * TSC, we add elapsed time in this computation. We could let the
1272 * compensation code attempt to catch up if we fall behind, but
1273 * it's better to try to match offsets from the beginning.
1274 */
02626b6a 1275 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1276 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1277 if (!check_tsc_unstable()) {
e26101b1 1278 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1279 pr_debug("kvm: matched tsc offset for %llu\n", data);
1280 } else {
857e4099 1281 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1282 data += delta;
1283 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1284 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1285 }
b48aa97e 1286 matched = true;
e26101b1
ZA		 1287 } else {
1288 /*
1289 * We split periods of matched TSC writes into generations.
1290 * For each generation, we track the original measured
1291 * nanosecond time, offset, and write, so if TSCs are in
1292 * sync, we can match exact offset, and if not, we can match
4a969980 1293 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1294 *
1295 * These values are tracked in kvm->arch.cur_xxx variables.
1296 */
1297 kvm->arch.cur_tsc_generation++;
1298 kvm->arch.cur_tsc_nsec = ns;
1299 kvm->arch.cur_tsc_write = data;
1300 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1301 matched = false;
e26101b1
ZA		 1302 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1303 kvm->arch.cur_tsc_generation, data);
f38e098f 1304 }
e26101b1
ZA		 1305
1306 /*
1307 * We also track th most recent recorded KHZ, write and time to
1308 * allow the matching interval to be extended at each write.
1309 */
f38e098f
ZA		 1310 kvm->arch.last_tsc_nsec = ns;
1311 kvm->arch.last_tsc_write = data;
5d3cb0f6 1312 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1313
b183aa58 1314 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1315
1316 /* Keep track of which generation this VCPU has synchronized to */
1317 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1318 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1319 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1320
ba904635
WA		 1321 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1322 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1323 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1324 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1325
1326 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1327 if (matched)
1328 kvm->arch.nr_vcpus_matched_tsc++;
1329 else
1330 kvm->arch.nr_vcpus_matched_tsc = 0;
1331
1332 kvm_track_tsc_matching(vcpu);
1333 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1334}
e26101b1 1335
99e3e30a
ZA		 1336EXPORT_SYMBOL_GPL(kvm_write_tsc);
1337
d828199e
MT		 1338#ifdef CONFIG_X86_64
1339
1340static cycle_t read_tsc(void)
1341{
1342 cycle_t ret;
1343 u64 last;
1344
1345 /*
1346 * Empirically, a fence (of type that depends on the CPU)
1347 * before rdtsc is enough to ensure that rdtsc is ordered
1348 * with respect to loads. The various CPU manuals are unclear
1349 * as to whether rdtsc can be reordered with later loads,
1350 * but no one has ever seen it happen.
1351 */
1352 rdtsc_barrier();
1353 ret = (cycle_t)vget_cycles();
1354
1355 last = pvclock_gtod_data.clock.cycle_last;
1356
1357 if (likely(ret >= last))
1358 return ret;
1359
1360 /*
1361 * GCC likes to generate cmov here, but this branch is extremely
1362 * predictable (it's just a funciton of time and the likely is
1363 * very likely) and there's a data dependence, so force GCC
1364 * to generate a branch instead. I don't barrier() because
1365 * we don't actually need a barrier, and if this function
1366 * ever gets inlined it will generate worse code.
1367 */
1368 asm volatile ("");
1369 return last;
1370}
1371
1372static inline u64 vgettsc(cycle_t *cycle_now)
1373{
1374 long v;
1375 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1376
1377 *cycle_now = read_tsc();
1378
1379 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1380 return v * gtod->clock.mult;
1381}
1382
1383static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1384{
1385 unsigned long seq;
1386 u64 ns;
1387 int mode;
1388 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1389
1390 ts->tv_nsec = 0;
1391 do {
1392 seq = read_seqcount_begin(&gtod->seq);
1393 mode = gtod->clock.vclock_mode;
1394 ts->tv_sec = gtod->monotonic_time_sec;
1395 ns = gtod->monotonic_time_snsec;
1396 ns += vgettsc(cycle_now);
1397 ns >>= gtod->clock.shift;
1398 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1399 timespec_add_ns(ts, ns);
1400
1401 return mode;
1402}
1403
1404/* returns true if host is using tsc clocksource */
1405static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1406{
1407 struct timespec ts;
1408
1409 /* checked again under seqlock below */
1410 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1411 return false;
1412
1413 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1414 return false;
1415
1416 monotonic_to_bootbased(&ts);
1417 *kernel_ns = timespec_to_ns(&ts);
1418
1419 return true;
1420}
1421#endif
1422
1423/*
1424 *
b48aa97e
MT		 1425 * Assuming a stable TSC across physical CPUS, and a stable TSC
1426 * across virtual CPUs, the following condition is possible.
1427 * Each numbered line represents an event visible to both
d828199e
MT		 1428 * CPUs at the next numbered event.
1429 *
1430 * "timespecX" represents host monotonic time. "tscX" represents
1431 * RDTSC value.
1432 *
1433 * VCPU0 on CPU0 | VCPU1 on CPU1
1434 *
1435 * 1. read timespec0,tsc0
1436 * 2. | timespec1 = timespec0 + N
1437 * | tsc1 = tsc0 + M
1438 * 3. transition to guest | transition to guest
1439 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1440 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1441 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1442 *
1443 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1444 *
1445 * - ret0 < ret1
1446 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1447 * ...
1448 * - 0 < N - M => M < N
1449 *
1450 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1451 * always the case (the difference between two distinct xtime instances
1452 * might be smaller then the difference between corresponding TSC reads,
1453 * when updating guest vcpus pvclock areas).
1454 *
1455 * To avoid that problem, do not allow visibility of distinct
1456 * system_timestamp/tsc_timestamp values simultaneously: use a master
1457 * copy of host monotonic time values. Update that master copy
1458 * in lockstep.
1459 *
b48aa97e 1460 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1461 *
1462 */
1463
1464static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1465{
1466#ifdef CONFIG_X86_64
1467 struct kvm_arch *ka = &kvm->arch;
1468 int vclock_mode;
b48aa97e
MT		 1469 bool host_tsc_clocksource, vcpus_matched;
1470
1471 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1472 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1473
1474 /*
1475 * If the host uses TSC clock, then passthrough TSC as stable
1476 * to the guest.
1477 */
b48aa97e 1478 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1479 &ka->master_kernel_ns,
1480 &ka->master_cycle_now);
1481
b48aa97e
MT		 1482 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1483
d828199e
MT		 1484 if (ka->use_master_clock)
1485 atomic_set(&kvm_guest_has_master_clock, 1);
1486
1487 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1488 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1489 vcpus_matched);
d828199e
MT		 1490#endif
1491}
1492
2e762ff7
MT		 1493static void kvm_gen_update_masterclock(struct kvm *kvm)
1494{
1495#ifdef CONFIG_X86_64
1496 int i;
1497 struct kvm_vcpu *vcpu;
1498 struct kvm_arch *ka = &kvm->arch;
1499
1500 spin_lock(&ka->pvclock_gtod_sync_lock);
1501 kvm_make_mclock_inprogress_request(kvm);
1502 /* no guest entries from this point */
1503 pvclock_update_vm_gtod_copy(kvm);
1504
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1507
1508 /* guest entries allowed */
1509 kvm_for_each_vcpu(i, vcpu, kvm)
1510 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1511
1512 spin_unlock(&ka->pvclock_gtod_sync_lock);
1513#endif
1514}
1515
34c238a1 1516static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1517{
d828199e 1518 unsigned long flags, this_tsc_khz;
18068523 1519 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1520 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1521 s64 kernel_ns;
d828199e 1522 u64 tsc_timestamp, host_tsc;
0b79459b 1523 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1524 u8 pvclock_flags;
d828199e
MT		 1525 bool use_master_clock;
1526
1527 kernel_ns = 0;
1528 host_tsc = 0;
18068523 1529
d828199e
MT		 1530 /*
1531 * If the host uses TSC clock, then passthrough TSC as stable
1532 * to the guest.
1533 */
1534 spin_lock(&ka->pvclock_gtod_sync_lock);
1535 use_master_clock = ka->use_master_clock;
1536 if (use_master_clock) {
1537 host_tsc = ka->master_cycle_now;
1538 kernel_ns = ka->master_kernel_ns;
1539 }
1540 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1541
1542 /* Keep irq disabled to prevent changes to the clock */
1543 local_irq_save(flags);
1544 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1545 if (unlikely(this_tsc_khz == 0)) {
1546 local_irq_restore(flags);
1547 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1548 return 1;
1549 }
d828199e
MT		 1550 if (!use_master_clock) {
1551 host_tsc = native_read_tsc();
1552 kernel_ns = get_kernel_ns();
1553 }
1554
1555 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1556
c285545f
ZA		 1557 /*
1558 * We may have to catch up the TSC to match elapsed wall clock
1559 * time for two reasons, even if kvmclock is used.
1560 * 1) CPU could have been running below the maximum TSC rate
1561 * 2) Broken TSC compensation resets the base at each VCPU
1562 * entry to avoid unknown leaps of TSC even when running
1563 * again on the same CPU. This may cause apparent elapsed
1564 * time to disappear, and the guest to stand still or run
1565 * very slowly.
1566 */
1567 if (vcpu->tsc_catchup) {
1568 u64 tsc = compute_guest_tsc(v, kernel_ns);
1569 if (tsc > tsc_timestamp) {
f1e2b260 1570 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1571 tsc_timestamp = tsc;
1572 }
50d0a0f9
GH		 1573 }
1574
18068523
GOC		 1575 local_irq_restore(flags);
1576
0b79459b 1577 if (!vcpu->pv_time_enabled)
c285545f 1578 return 0;
18068523 1579
e48672fa 1580 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1581 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1582 &vcpu->hv_clock.tsc_shift,
1583 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1584 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1585 }
1586
1587 /* With all the info we got, fill in the values */
1d5f066e 1588 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1589 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1590 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1591
18068523
GOC		 1592 /*
1593 * The interface expects us to write an even number signaling that the
1594 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1595 * state, we just increase by 2 at the end.
18068523 1596 */
50d0a0f9 1597 vcpu->hv_clock.version += 2;
18068523 1598
0b79459b
AH		 1599 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1600 &guest_hv_clock, sizeof(guest_hv_clock))))
1601 return 0;
78c0337a
MT		 1602
1603 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1604 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1605
1606 if (vcpu->pvclock_set_guest_stopped_request) {
1607 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1608 vcpu->pvclock_set_guest_stopped_request = false;
1609 }
1610
d828199e
MT		 1611 /* If the host uses TSC clocksource, then it is stable */
1612 if (use_master_clock)
1613 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1614
78c0337a
MT		 1615 vcpu->hv_clock.flags = pvclock_flags;
1616
0b79459b
AH		 1617 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1618 &vcpu->hv_clock,
1619 sizeof(vcpu->hv_clock));
8cfdc000 1620 return 0;
c8076604
GH		 1621}
1622
0061d53d
MT		 1623/*
1624 * kvmclock updates which are isolated to a given vcpu, such as
1625 * vcpu->cpu migration, should not allow system_timestamp from
1626 * the rest of the vcpus to remain static. Otherwise ntp frequency
1627 * correction applies to one vcpu's system_timestamp but not
1628 * the others.
1629 *
1630 * So in those cases, request a kvmclock update for all vcpus.
1631 * The worst case for a remote vcpu to update its kvmclock
1632 * is then bounded by maximum nohz sleep latency.
1633 */
1634
1635static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1636{
1637 int i;
1638 struct kvm *kvm = v->kvm;
1639 struct kvm_vcpu *vcpu;
1640
1641 kvm_for_each_vcpu(i, vcpu, kvm) {
1642 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1643 kvm_vcpu_kick(vcpu);
1644 }
1645}
1646
9ba075a6
AK		 1647static bool msr_mtrr_valid(unsigned msr)
1648{
1649 switch (msr) {
1650 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1651 case MSR_MTRRfix64K_00000:
1652 case MSR_MTRRfix16K_80000:
1653 case MSR_MTRRfix16K_A0000:
1654 case MSR_MTRRfix4K_C0000:
1655 case MSR_MTRRfix4K_C8000:
1656 case MSR_MTRRfix4K_D0000:
1657 case MSR_MTRRfix4K_D8000:
1658 case MSR_MTRRfix4K_E0000:
1659 case MSR_MTRRfix4K_E8000:
1660 case MSR_MTRRfix4K_F0000:
1661 case MSR_MTRRfix4K_F8000:
1662 case MSR_MTRRdefType:
1663 case MSR_IA32_CR_PAT:
1664 return true;
1665 case 0x2f8:
1666 return true;
1667 }
1668 return false;
1669}
1670
d6289b93
MT		 1671static bool valid_pat_type(unsigned t)
1672{
1673 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1674}
1675
1676static bool valid_mtrr_type(unsigned t)
1677{
1678 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1679}
1680
1681static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1682{
1683 int i;
1684
1685 if (!msr_mtrr_valid(msr))
1686 return false;
1687
1688 if (msr == MSR_IA32_CR_PAT) {
1689 for (i = 0; i < 8; i++)
1690 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1691 return false;
1692 return true;
1693 } else if (msr == MSR_MTRRdefType) {
1694 if (data & ~0xcff)
1695 return false;
1696 return valid_mtrr_type(data & 0xff);
1697 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1698 for (i = 0; i < 8 ; i++)
1699 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1700 return false;
1701 return true;
1702 }
1703
1704 /* variable MTRRs */
1705 return valid_mtrr_type(data & 0xff);
1706}
1707
9ba075a6
AK		 1708static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1709{
0bed3b56
SY		 1710 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1711
d6289b93 1712 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1713 return 1;
1714
0bed3b56
SY		 1715 if (msr == MSR_MTRRdefType) {
1716 vcpu->arch.mtrr_state.def_type = data;
1717 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1718 } else if (msr == MSR_MTRRfix64K_00000)
1719 p[0] = data;
1720 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1721 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1722 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1723 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1724 else if (msr == MSR_IA32_CR_PAT)
1725 vcpu->arch.pat = data;
1726 else { /* Variable MTRRs */
1727 int idx, is_mtrr_mask;
1728 u64 *pt;
1729
1730 idx = (msr - 0x200) / 2;
1731 is_mtrr_mask = msr - 0x200 - 2 * idx;
1732 if (!is_mtrr_mask)
1733 pt =
1734 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1735 else
1736 pt =
1737 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1738 *pt = data;
1739 }
1740
1741 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1742 return 0;
1743}
15c4a640 1744
890ca9ae 1745static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1746{
890ca9ae
HY		 1747 u64 mcg_cap = vcpu->arch.mcg_cap;
1748 unsigned bank_num = mcg_cap & 0xff;
1749
15c4a640 1750 switch (msr) {
15c4a640 1751 case MSR_IA32_MCG_STATUS:
890ca9ae 1752 vcpu->arch.mcg_status = data;
15c4a640 1753 break;
c7ac679c 1754 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1755 if (!(mcg_cap & MCG_CTL_P))
1756 return 1;
1757 if (data != 0 && data != ~(u64)0)
1758 return -1;
1759 vcpu->arch.mcg_ctl = data;
1760 break;
1761 default:
1762 if (msr >= MSR_IA32_MC0_CTL &&
1763 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1764 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1765 /* only 0 or all 1s can be written to IA32_MCi_CTL
1766 * some Linux kernels though clear bit 10 in bank 4 to
1767 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1768 * this to avoid an uncatched #GP in the guest
1769 */
890ca9ae 1770 if ((offset & 0x3) == 0 &&
114be429 1771 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1772 return -1;
1773 vcpu->arch.mce_banks[offset] = data;
1774 break;
1775 }
1776 return 1;
1777 }
1778 return 0;
1779}
1780
ffde22ac
ES		 1781static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1782{
1783 struct kvm *kvm = vcpu->kvm;
1784 int lm = is_long_mode(vcpu);
1785 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1786 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1787 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1788 : kvm->arch.xen_hvm_config.blob_size_32;
1789 u32 page_num = data & ~PAGE_MASK;
1790 u64 page_addr = data & PAGE_MASK;
1791 u8 *page;
1792 int r;
1793
1794 r = -E2BIG;
1795 if (page_num >= blob_size)
1796 goto out;
1797 r = -ENOMEM;
ff5c2c03
SL		 1798 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1799 if (IS_ERR(page)) {
1800 r = PTR_ERR(page);
ffde22ac 1801 goto out;
ff5c2c03 1802 }
ffde22ac
ES		 1803 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1804 goto out_free;
1805 r = 0;
1806out_free:
1807 kfree(page);
1808out:
1809 return r;
1810}
1811
55cd8e5a
GN		 1812static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1813{
1814 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1815}
1816
1817static bool kvm_hv_msr_partition_wide(u32 msr)
1818{
1819 bool r = false;
1820 switch (msr) {
1821 case HV_X64_MSR_GUEST_OS_ID:
1822 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1823 case HV_X64_MSR_REFERENCE_TSC:
1824 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1825 r = true;
1826 break;
1827 }
1828
1829 return r;
1830}
1831
1832static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1833{
1834 struct kvm *kvm = vcpu->kvm;
1835
1836 switch (msr) {
1837 case HV_X64_MSR_GUEST_OS_ID:
1838 kvm->arch.hv_guest_os_id = data;
1839 /* setting guest os id to zero disables hypercall page */
1840 if (!kvm->arch.hv_guest_os_id)
1841 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1842 break;
1843 case HV_X64_MSR_HYPERCALL: {
1844 u64 gfn;
1845 unsigned long addr;
1846 u8 instructions[4];
1847
1848 /* if guest os id is not set hypercall should remain disabled */
1849 if (!kvm->arch.hv_guest_os_id)
1850 break;
1851 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1852 kvm->arch.hv_hypercall = data;
1853 break;
1854 }
1855 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1856 addr = gfn_to_hva(kvm, gfn);
1857 if (kvm_is_error_hva(addr))
1858 return 1;
1859 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1860 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1861 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1862 return 1;
1863 kvm->arch.hv_hypercall = data;
b94b64c9 1864 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1865 break;
1866 }
e984097b
VR		 1867 case HV_X64_MSR_REFERENCE_TSC: {
1868 u64 gfn;
1869 HV_REFERENCE_TSC_PAGE tsc_ref;
1870 memset(&tsc_ref, 0, sizeof(tsc_ref));
1871 kvm->arch.hv_tsc_page = data;
1872 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1873 break;
1874 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1875 if (kvm_write_guest(kvm, data,
1876 &tsc_ref, sizeof(tsc_ref)))
1877 return 1;
1878 mark_page_dirty(kvm, gfn);
1879 break;
1880 }
55cd8e5a 1881 default:
a737f256
CD		 1882 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1883 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1884 return 1;
1885 }
1886 return 0;
1887}
1888
1889static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1890{
10388a07
GN		 1891 switch (msr) {
1892 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1893 u64 gfn;
10388a07 1894 unsigned long addr;
55cd8e5a 1895
10388a07
GN		 1896 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1897 vcpu->arch.hv_vapic = data;
1898 break;
1899 }
b3af1e88
VR		 1900 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1901 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1902 if (kvm_is_error_hva(addr))
1903 return 1;
8b0cedff 1904 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1905 return 1;
1906 vcpu->arch.hv_vapic = data;
b3af1e88 1907 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1908 break;
1909 }
1910 case HV_X64_MSR_EOI:
1911 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1912 case HV_X64_MSR_ICR:
1913 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1914 case HV_X64_MSR_TPR:
1915 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1916 default:
a737f256
CD		 1917 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1918 "data 0x%llx\n", msr, data);
10388a07
GN		 1919 return 1;
1920 }
1921
1922 return 0;
55cd8e5a
GN		 1923}
1924
344d9588
GN		 1925static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1926{
1927 gpa_t gpa = data & ~0x3f;
1928
4a969980 1929 /* Bits 2:5 are reserved, Should be zero */
6adba527 1930 if (data & 0x3c)
344d9588
GN		 1931 return 1;
1932
1933 vcpu->arch.apf.msr_val = data;
1934
1935 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1936 kvm_clear_async_pf_completion_queue(vcpu);
1937 kvm_async_pf_hash_reset(vcpu);
1938 return 0;
1939 }
1940
8f964525
AH		 1941 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1942 sizeof(u32)))
344d9588
GN		 1943 return 1;
1944
6adba527 1945 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1946 kvm_async_pf_wakeup_all(vcpu);
1947 return 0;
1948}
1949
12f9a48f
GC		 1950static void kvmclock_reset(struct kvm_vcpu *vcpu)
1951{
0b79459b 1952 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1953}
1954
c9aaa895
GC		 1955static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1956{
1957 u64 delta;
1958
1959 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1960 return;
1961
1962 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1963 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1964 vcpu->arch.st.accum_steal = delta;
1965}
1966
1967static void record_steal_time(struct kvm_vcpu *vcpu)
1968{
1969 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1970 return;
1971
1972 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1973 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1974 return;
1975
1976 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1977 vcpu->arch.st.steal.version += 2;
1978 vcpu->arch.st.accum_steal = 0;
1979
1980 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1981 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1982}
1983
8fe8ab46 1984int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1985{
5753785f 1986 bool pr = false;
8fe8ab46
WA		 1987 u32 msr = msr_info->index;
1988 u64 data = msr_info->data;
5753785f 1989
15c4a640 1990 switch (msr) {
2e32b719
BP		 1991 case MSR_AMD64_NB_CFG:
1992 case MSR_IA32_UCODE_REV:
1993 case MSR_IA32_UCODE_WRITE:
1994 case MSR_VM_HSAVE_PA:
1995 case MSR_AMD64_PATCH_LOADER:
1996 case MSR_AMD64_BU_CFG2:
1997 break;
1998
15c4a640 1999 case MSR_EFER:
b69e8cae 2000 return set_efer(vcpu, data);
8f1589d9
AP		 2001 case MSR_K7_HWCR:
2002 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2003 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2004 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2005 if (data != 0) {
a737f256
CD		 2006 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2007 data);
8f1589d9
AP		 2008 return 1;
2009 }
15c4a640 2010 break;
f7c6d140
AP		 2011 case MSR_FAM10H_MMIO_CONF_BASE:
2012 if (data != 0) {
a737f256
CD		 2013 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2014 "0x%llx\n", data);
f7c6d140
AP		 2015 return 1;
2016 }
15c4a640 2017 break;
b5e2fec0
AG		 2018 case MSR_IA32_DEBUGCTLMSR:
2019 if (!data) {
2020 /* We support the non-activated case already */
2021 break;
2022 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2023 /* Values other than LBR and BTF are vendor-specific,
2024 thus reserved and should throw a #GP */
2025 return 1;
2026 }
a737f256
CD		 2027 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2028 __func__, data);
b5e2fec0 2029 break;
9ba075a6
AK		 2030 case 0x200 ... 0x2ff:
2031 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2032 case MSR_IA32_APICBASE:
58cb628d 2033 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2034 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2035 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2036 case MSR_IA32_TSCDEADLINE:
2037 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2038 break;
ba904635
WA		 2039 case MSR_IA32_TSC_ADJUST:
2040 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2041 if (!msr_info->host_initiated) {
2042 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2043 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2044 }
2045 vcpu->arch.ia32_tsc_adjust_msr = data;
2046 }
2047 break;
15c4a640 2048 case MSR_IA32_MISC_ENABLE:
ad312c7c 2049 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2050 break;
11c6bffa 2051 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2052 case MSR_KVM_WALL_CLOCK:
2053 vcpu->kvm->arch.wall_clock = data;
2054 kvm_write_wall_clock(vcpu->kvm, data);
2055 break;
11c6bffa 2056 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2057 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2058 u64 gpa_offset;
12f9a48f 2059 kvmclock_reset(vcpu);
18068523
GOC		 2060
2061 vcpu->arch.time = data;
0061d53d 2062 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2063
2064 /* we verify if the enable bit is set... */
2065 if (!(data & 1))
2066 break;
2067
0b79459b 2068 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2069
0b79459b 2070 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2071 &vcpu->arch.pv_time, data & ~1ULL,
2072 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2073 vcpu->arch.pv_time_enabled = false;
2074 else
2075 vcpu->arch.pv_time_enabled = true;
32cad84f 2076
18068523
GOC		 2077 break;
2078 }
344d9588
GN		 2079 case MSR_KVM_ASYNC_PF_EN:
2080 if (kvm_pv_enable_async_pf(vcpu, data))
2081 return 1;
2082 break;
c9aaa895
GC		 2083 case MSR_KVM_STEAL_TIME:
2084
2085 if (unlikely(!sched_info_on()))
2086 return 1;
2087
2088 if (data & KVM_STEAL_RESERVED_MASK)
2089 return 1;
2090
2091 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2092 data & KVM_STEAL_VALID_BITS,
2093 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2094 return 1;
2095
2096 vcpu->arch.st.msr_val = data;
2097
2098 if (!(data & KVM_MSR_ENABLED))
2099 break;
2100
2101 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2102
2103 preempt_disable();
2104 accumulate_steal_time(vcpu);
2105 preempt_enable();
2106
2107 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2108
2109 break;
ae7a2a3f
MT		 2110 case MSR_KVM_PV_EOI_EN:
2111 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2112 return 1;
2113 break;
c9aaa895 2114
890ca9ae
HY		 2115 case MSR_IA32_MCG_CTL:
2116 case MSR_IA32_MCG_STATUS:
2117 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2118 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2119
2120 /* Performance counters are not protected by a CPUID bit,
2121 * so we should check all of them in the generic path for the sake of
2122 * cross vendor migration.
2123 * Writing a zero into the event select MSRs disables them,
2124 * which we perfectly emulate ;-). Any other value should be at least
2125 * reported, some guests depend on them.
2126 */
71db6023
AP		 2127 case MSR_K7_EVNTSEL0:
2128 case MSR_K7_EVNTSEL1:
2129 case MSR_K7_EVNTSEL2:
2130 case MSR_K7_EVNTSEL3:
2131 if (data != 0)
a737f256
CD		 2132 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2133 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2134 break;
2135 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2136 * so we ignore writes to make it happy.
2137 */
71db6023
AP		 2138 case MSR_K7_PERFCTR0:
2139 case MSR_K7_PERFCTR1:
2140 case MSR_K7_PERFCTR2:
2141 case MSR_K7_PERFCTR3:
a737f256
CD		 2142 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2143 "0x%x data 0x%llx\n", msr, data);
71db6023 2144 break;
5753785f
GN		 2145 case MSR_P6_PERFCTR0:
2146 case MSR_P6_PERFCTR1:
2147 pr = true;
2148 case MSR_P6_EVNTSEL0:
2149 case MSR_P6_EVNTSEL1:
2150 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2151 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2152
2153 if (pr || data != 0)
a737f256
CD		 2154 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2155 "0x%x data 0x%llx\n", msr, data);
5753785f 2156 break;
84e0cefa
JS		 2157 case MSR_K7_CLK_CTL:
2158 /*
2159 * Ignore all writes to this no longer documented MSR.
2160 * Writes are only relevant for old K7 processors,
2161 * all pre-dating SVM, but a recommended workaround from
4a969980 2162 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2163 * affected processor models on the command line, hence
2164 * the need to ignore the workaround.
2165 */
2166 break;
55cd8e5a
GN		 2167 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2168 if (kvm_hv_msr_partition_wide(msr)) {
2169 int r;
2170 mutex_lock(&vcpu->kvm->lock);
2171 r = set_msr_hyperv_pw(vcpu, msr, data);
2172 mutex_unlock(&vcpu->kvm->lock);
2173 return r;
2174 } else
2175 return set_msr_hyperv(vcpu, msr, data);
2176 break;
91c9c3ed 2177 case MSR_IA32_BBL_CR_CTL3:
2178 /* Drop writes to this legacy MSR -- see rdmsr
2179 * counterpart for further detail.
2180 */
a737f256 2181 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2182 break;
2b036c6b
BO		 2183 case MSR_AMD64_OSVW_ID_LENGTH:
2184 if (!guest_cpuid_has_osvw(vcpu))
2185 return 1;
2186 vcpu->arch.osvw.length = data;
2187 break;
2188 case MSR_AMD64_OSVW_STATUS:
2189 if (!guest_cpuid_has_osvw(vcpu))
2190 return 1;
2191 vcpu->arch.osvw.status = data;
2192 break;
15c4a640 2193 default:
ffde22ac
ES		 2194 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2195 return xen_hvm_config(vcpu, data);
f5132b01 2196 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2197 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2198 if (!ignore_msrs) {
a737f256
CD		 2199 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2200 msr, data);
ed85c068
AP		 2201 return 1;
2202 } else {
a737f256
CD		 2203 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2204 msr, data);
ed85c068
AP		 2205 break;
2206 }
15c4a640
CO		 2207 }
2208 return 0;
2209}
2210EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2211
2212
2213/*
2214 * Reads an msr value (of 'msr_index') into 'pdata'.
2215 * Returns 0 on success, non-0 otherwise.
2216 * Assumes vcpu_load() was already called.
2217 */
2218int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2219{
2220 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2221}
2222
9ba075a6
AK		 2223static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2224{
0bed3b56
SY		 2225 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2226
9ba075a6
AK		 2227 if (!msr_mtrr_valid(msr))
2228 return 1;
2229
0bed3b56
SY		 2230 if (msr == MSR_MTRRdefType)
2231 *pdata = vcpu->arch.mtrr_state.def_type +
2232 (vcpu->arch.mtrr_state.enabled << 10);
2233 else if (msr == MSR_MTRRfix64K_00000)
2234 *pdata = p[0];
2235 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2236 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2237 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2238 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2239 else if (msr == MSR_IA32_CR_PAT)
2240 *pdata = vcpu->arch.pat;
2241 else { /* Variable MTRRs */
2242 int idx, is_mtrr_mask;
2243 u64 *pt;
2244
2245 idx = (msr - 0x200) / 2;
2246 is_mtrr_mask = msr - 0x200 - 2 * idx;
2247 if (!is_mtrr_mask)
2248 pt =
2249 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2250 else
2251 pt =
2252 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2253 *pdata = *pt;
2254 }
2255
9ba075a6
AK		 2256 return 0;
2257}
2258
890ca9ae 2259static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2260{
2261 u64 data;
890ca9ae
HY		 2262 u64 mcg_cap = vcpu->arch.mcg_cap;
2263 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2264
2265 switch (msr) {
15c4a640
CO		 2266 case MSR_IA32_P5_MC_ADDR:
2267 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2268 data = 0;
2269 break;
15c4a640 2270 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2271 data = vcpu->arch.mcg_cap;
2272 break;
c7ac679c 2273 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2274 if (!(mcg_cap & MCG_CTL_P))
2275 return 1;
2276 data = vcpu->arch.mcg_ctl;
2277 break;
2278 case MSR_IA32_MCG_STATUS:
2279 data = vcpu->arch.mcg_status;
2280 break;
2281 default:
2282 if (msr >= MSR_IA32_MC0_CTL &&
2283 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2284 u32 offset = msr - MSR_IA32_MC0_CTL;
2285 data = vcpu->arch.mce_banks[offset];
2286 break;
2287 }
2288 return 1;
2289 }
2290 *pdata = data;
2291 return 0;
2292}
2293
55cd8e5a
GN		 2294static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2295{
2296 u64 data = 0;
2297 struct kvm *kvm = vcpu->kvm;
2298
2299 switch (msr) {
2300 case HV_X64_MSR_GUEST_OS_ID:
2301 data = kvm->arch.hv_guest_os_id;
2302 break;
2303 case HV_X64_MSR_HYPERCALL:
2304 data = kvm->arch.hv_hypercall;
2305 break;
e984097b
VR		 2306 case HV_X64_MSR_TIME_REF_COUNT: {
2307 data =
2308 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2309 break;
2310 }
2311 case HV_X64_MSR_REFERENCE_TSC:
2312 data = kvm->arch.hv_tsc_page;
2313 break;
55cd8e5a 2314 default:
a737f256 2315 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2316 return 1;
2317 }
2318
2319 *pdata = data;
2320 return 0;
2321}
2322
2323static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2324{
2325 u64 data = 0;
2326
2327 switch (msr) {
2328 case HV_X64_MSR_VP_INDEX: {
2329 int r;
2330 struct kvm_vcpu *v;
684851a1
TY		 2331 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2332 if (v == vcpu) {
55cd8e5a 2333 data = r;
684851a1
TY		 2334 break;
2335 }
2336 }
55cd8e5a
GN		 2337 break;
2338 }
10388a07
GN		 2339 case HV_X64_MSR_EOI:
2340 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2341 case HV_X64_MSR_ICR:
2342 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2343 case HV_X64_MSR_TPR:
2344 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2345 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2346 data = vcpu->arch.hv_vapic;
2347 break;
55cd8e5a 2348 default:
a737f256 2349 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2350 return 1;
2351 }
2352 *pdata = data;
2353 return 0;
2354}
2355
890ca9ae
HY		 2356int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2357{
2358 u64 data;
2359
2360 switch (msr) {
890ca9ae 2361 case MSR_IA32_PLATFORM_ID:
15c4a640 2362 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2363 case MSR_IA32_DEBUGCTLMSR:
2364 case MSR_IA32_LASTBRANCHFROMIP:
2365 case MSR_IA32_LASTBRANCHTOIP:
2366 case MSR_IA32_LASTINTFROMIP:
2367 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2368 case MSR_K8_SYSCFG:
2369 case MSR_K7_HWCR:
61a6bd67 2370 case MSR_VM_HSAVE_PA:
9e699624 2371 case MSR_K7_EVNTSEL0:
1f3ee616 2372 case MSR_K7_PERFCTR0:
1fdbd48c 2373 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2374 case MSR_AMD64_NB_CFG:
f7c6d140 2375 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2376 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2377 data = 0;
2378 break;
5753785f
GN		 2379 case MSR_P6_PERFCTR0:
2380 case MSR_P6_PERFCTR1:
2381 case MSR_P6_EVNTSEL0:
2382 case MSR_P6_EVNTSEL1:
2383 if (kvm_pmu_msr(vcpu, msr))
2384 return kvm_pmu_get_msr(vcpu, msr, pdata);
2385 data = 0;
2386 break;
742bc670
MT		 2387 case MSR_IA32_UCODE_REV:
2388 data = 0x100000000ULL;
2389 break;
9ba075a6
AK		 2390 case MSR_MTRRcap:
2391 data = 0x500 | KVM_NR_VAR_MTRR;
2392 break;
2393 case 0x200 ... 0x2ff:
2394 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2395 case 0xcd: /* fsb frequency */
2396 data = 3;
2397 break;
7b914098
JS		 2398 /*
2399 * MSR_EBC_FREQUENCY_ID
2400 * Conservative value valid for even the basic CPU models.
2401 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2402 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2403 * and 266MHz for model 3, or 4. Set Core Clock
2404 * Frequency to System Bus Frequency Ratio to 1 (bits
2405 * 31:24) even though these are only valid for CPU
2406 * models > 2, however guests may end up dividing or
2407 * multiplying by zero otherwise.
2408 */
2409 case MSR_EBC_FREQUENCY_ID:
2410 data = 1 << 24;
2411 break;
15c4a640
CO		 2412 case MSR_IA32_APICBASE:
2413 data = kvm_get_apic_base(vcpu);
2414 break;
0105d1a5
GN		 2415 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2416 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2417 break;
a3e06bbe
LJ		 2418 case MSR_IA32_TSCDEADLINE:
2419 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2420 break;
ba904635
WA		 2421 case MSR_IA32_TSC_ADJUST:
2422 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2423 break;
15c4a640 2424 case MSR_IA32_MISC_ENABLE:
ad312c7c 2425 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2426 break;
847f0ad8
AG		 2427 case MSR_IA32_PERF_STATUS:
2428 /* TSC increment by tick */
2429 data = 1000ULL;
2430 /* CPU multiplier */
2431 data |= (((uint64_t)4ULL) << 40);
2432 break;
15c4a640 2433 case MSR_EFER:
f6801dff 2434 data = vcpu->arch.efer;
15c4a640 2435 break;
18068523 2436 case MSR_KVM_WALL_CLOCK:
11c6bffa 2437 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2438 data = vcpu->kvm->arch.wall_clock;
2439 break;
2440 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2441 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2442 data = vcpu->arch.time;
2443 break;
344d9588
GN		 2444 case MSR_KVM_ASYNC_PF_EN:
2445 data = vcpu->arch.apf.msr_val;
2446 break;
c9aaa895
GC		 2447 case MSR_KVM_STEAL_TIME:
2448 data = vcpu->arch.st.msr_val;
2449 break;
1d92128f
MT		 2450 case MSR_KVM_PV_EOI_EN:
2451 data = vcpu->arch.pv_eoi.msr_val;
2452 break;
890ca9ae
HY		 2453 case MSR_IA32_P5_MC_ADDR:
2454 case MSR_IA32_P5_MC_TYPE:
2455 case MSR_IA32_MCG_CAP:
2456 case MSR_IA32_MCG_CTL:
2457 case MSR_IA32_MCG_STATUS:
2458 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2459 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2460 case MSR_K7_CLK_CTL:
2461 /*
2462 * Provide expected ramp-up count for K7. All other
2463 * are set to zero, indicating minimum divisors for
2464 * every field.
2465 *
2466 * This prevents guest kernels on AMD host with CPU
2467 * type 6, model 8 and higher from exploding due to
2468 * the rdmsr failing.
2469 */
2470 data = 0x20000000;
2471 break;
55cd8e5a
GN		 2472 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2473 if (kvm_hv_msr_partition_wide(msr)) {
2474 int r;
2475 mutex_lock(&vcpu->kvm->lock);
2476 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2477 mutex_unlock(&vcpu->kvm->lock);
2478 return r;
2479 } else
2480 return get_msr_hyperv(vcpu, msr, pdata);
2481 break;
91c9c3ed 2482 case MSR_IA32_BBL_CR_CTL3:
2483 /* This legacy MSR exists but isn't fully documented in current
2484 * silicon. It is however accessed by winxp in very narrow
2485 * scenarios where it sets bit #19, itself documented as
2486 * a "reserved" bit. Best effort attempt to source coherent
2487 * read data here should the balance of the register be
2488 * interpreted by the guest:
2489 *
2490 * L2 cache control register 3: 64GB range, 256KB size,
2491 * enabled, latency 0x1, configured
2492 */
2493 data = 0xbe702111;
2494 break;
2b036c6b
BO		 2495 case MSR_AMD64_OSVW_ID_LENGTH:
2496 if (!guest_cpuid_has_osvw(vcpu))
2497 return 1;
2498 data = vcpu->arch.osvw.length;
2499 break;
2500 case MSR_AMD64_OSVW_STATUS:
2501 if (!guest_cpuid_has_osvw(vcpu))
2502 return 1;
2503 data = vcpu->arch.osvw.status;
2504 break;
15c4a640 2505 default:
f5132b01
GN		 2506 if (kvm_pmu_msr(vcpu, msr))
2507 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2508 if (!ignore_msrs) {
a737f256 2509 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2510 return 1;
2511 } else {
a737f256 2512 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2513 data = 0;
2514 }
2515 break;
15c4a640
CO		 2516 }
2517 *pdata = data;
2518 return 0;
2519}
2520EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2521
313a3dc7
CO		 2522/*
2523 * Read or write a bunch of msrs. All parameters are kernel addresses.
2524 *
2525 * @return number of msrs set successfully.
2526 */
2527static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2528 struct kvm_msr_entry *entries,
2529 int (*do_msr)(struct kvm_vcpu *vcpu,
2530 unsigned index, u64 *data))
2531{
f656ce01 2532 int i, idx;
313a3dc7 2533
f656ce01 2534 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2535 for (i = 0; i < msrs->nmsrs; ++i)
2536 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2537 break;
f656ce01 2538 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2539
313a3dc7
CO		 2540 return i;
2541}
2542
2543/*
2544 * Read or write a bunch of msrs. Parameters are user addresses.
2545 *
2546 * @return number of msrs set successfully.
2547 */
2548static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2549 int (*do_msr)(struct kvm_vcpu *vcpu,
2550 unsigned index, u64 *data),
2551 int writeback)
2552{
2553 struct kvm_msrs msrs;
2554 struct kvm_msr_entry *entries;
2555 int r, n;
2556 unsigned size;
2557
2558 r = -EFAULT;
2559 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2560 goto out;
2561
2562 r = -E2BIG;
2563 if (msrs.nmsrs >= MAX_IO_MSRS)
2564 goto out;
2565
313a3dc7 2566 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2567 entries = memdup_user(user_msrs->entries, size);
2568 if (IS_ERR(entries)) {
2569 r = PTR_ERR(entries);
313a3dc7 2570 goto out;
ff5c2c03 2571 }
313a3dc7
CO		 2572
2573 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2574 if (r < 0)
2575 goto out_free;
2576
2577 r = -EFAULT;
2578 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2579 goto out_free;
2580
2581 r = n;
2582
2583out_free:
7a73c028 2584 kfree(entries);
313a3dc7
CO		 2585out:
2586 return r;
2587}
2588
018d00d2
ZX		 2589int kvm_dev_ioctl_check_extension(long ext)
2590{
2591 int r;
2592
2593 switch (ext) {
2594 case KVM_CAP_IRQCHIP:
2595 case KVM_CAP_HLT:
2596 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2597 case KVM_CAP_SET_TSS_ADDR:
07716717 2598 case KVM_CAP_EXT_CPUID:
9c15bb1d 2599 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2600 case KVM_CAP_CLOCKSOURCE:
7837699f 2601 case KVM_CAP_PIT:
a28e4f5a 2602 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2603 case KVM_CAP_MP_STATE:
ed848624 2604 case KVM_CAP_SYNC_MMU:
a355c85c 2605 case KVM_CAP_USER_NMI:
52d939a0 2606 case KVM_CAP_REINJECT_CONTROL:
4925663a 2607 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2608 case KVM_CAP_IRQFD:
d34e6b17 2609 case KVM_CAP_IOEVENTFD:
c5ff41ce 2610 case KVM_CAP_PIT2:
e9f42757 2611 case KVM_CAP_PIT_STATE2:
b927a3ce 2612 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2613 case KVM_CAP_XEN_HVM:
afbcf7ab 2614 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2615 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2616 case KVM_CAP_HYPERV:
10388a07 2617 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2618 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2619 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2620 case KVM_CAP_DEBUGREGS:
d2be1651 2621 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2622 case KVM_CAP_XSAVE:
344d9588 2623 case KVM_CAP_ASYNC_PF:
92a1f12d 2624 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2625 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2626 case KVM_CAP_READONLY_MEM:
5f66b620 2627 case KVM_CAP_HYPERV_TIME:
2a5bab10
AW		 2628#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2629 case KVM_CAP_ASSIGN_DEV_IRQ:
2630 case KVM_CAP_PCI_2_3:
2631#endif
018d00d2
ZX		 2632 r = 1;
2633 break;
542472b5
LV		 2634 case KVM_CAP_COALESCED_MMIO:
2635 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2636 break;
774ead3a
AK		 2637 case KVM_CAP_VAPIC:
2638 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2639 break;
f725230a 2640 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2641 r = KVM_SOFT_MAX_VCPUS;
2642 break;
2643 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2644 r = KVM_MAX_VCPUS;
2645 break;
a988b910 2646 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2647 r = KVM_USER_MEM_SLOTS;
a988b910 2648 break;
a68a6a72
MT		 2649 case KVM_CAP_PV_MMU: /* obsolete */
2650 r = 0;
2f333bcb 2651 break;
4cee4b72 2652#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2653 case KVM_CAP_IOMMU:
a1b60c1c 2654 r = iommu_present(&pci_bus_type);
62c476c7 2655 break;
4cee4b72 2656#endif
890ca9ae
HY		 2657 case KVM_CAP_MCE:
2658 r = KVM_MAX_MCE_BANKS;
2659 break;
2d5b5a66
SY		 2660 case KVM_CAP_XCRS:
2661 r = cpu_has_xsave;
2662 break;
92a1f12d
JR		 2663 case KVM_CAP_TSC_CONTROL:
2664 r = kvm_has_tsc_control;
2665 break;
4d25a066
JK		 2666 case KVM_CAP_TSC_DEADLINE_TIMER:
2667 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2668 break;
018d00d2
ZX		 2669 default:
2670 r = 0;
2671 break;
2672 }
2673 return r;
2674
2675}
2676
043405e1
CO		 2677long kvm_arch_dev_ioctl(struct file *filp,
2678 unsigned int ioctl, unsigned long arg)
2679{
2680 void __user *argp = (void __user *)arg;
2681 long r;
2682
2683 switch (ioctl) {
2684 case KVM_GET_MSR_INDEX_LIST: {
2685 struct kvm_msr_list __user *user_msr_list = argp;
2686 struct kvm_msr_list msr_list;
2687 unsigned n;
2688
2689 r = -EFAULT;
2690 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2691 goto out;
2692 n = msr_list.nmsrs;
2693 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2694 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2695 goto out;
2696 r = -E2BIG;
e125e7b6 2697 if (n < msr_list.nmsrs)
043405e1
CO		 2698 goto out;
2699 r = -EFAULT;
2700 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2701 num_msrs_to_save * sizeof(u32)))
2702 goto out;
e125e7b6 2703 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2704 &emulated_msrs,
2705 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2706 goto out;
2707 r = 0;
2708 break;
2709 }
9c15bb1d
BP		 2710 case KVM_GET_SUPPORTED_CPUID:
2711 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2712 struct kvm_cpuid2 __user *cpuid_arg = argp;
2713 struct kvm_cpuid2 cpuid;
2714
2715 r = -EFAULT;
2716 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2717 goto out;
9c15bb1d
BP		 2718
2719 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2720 ioctl);
674eea0f
AK		 2721 if (r)
2722 goto out;
2723
2724 r = -EFAULT;
2725 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2726 goto out;
2727 r = 0;
2728 break;
2729 }
890ca9ae
HY		 2730 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2731 u64 mce_cap;
2732
2733 mce_cap = KVM_MCE_CAP_SUPPORTED;
2734 r = -EFAULT;
2735 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2736 goto out;
2737 r = 0;
2738 break;
2739 }
043405e1
CO		 2740 default:
2741 r = -EINVAL;
2742 }
2743out:
2744 return r;
2745}
2746
f5f48ee1
SY		 2747static void wbinvd_ipi(void *garbage)
2748{
2749 wbinvd();
2750}
2751
2752static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2753{
e0f0bbc5 2754 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2755}
2756
313a3dc7
CO		 2757void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2758{
f5f48ee1
SY		 2759 /* Address WBINVD may be executed by guest */
2760 if (need_emulate_wbinvd(vcpu)) {
2761 if (kvm_x86_ops->has_wbinvd_exit())
2762 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2763 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2764 smp_call_function_single(vcpu->cpu,
2765 wbinvd_ipi, NULL, 1);
2766 }
2767
313a3dc7 2768 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2769
0dd6a6ed
ZA		 2770 /* Apply any externally detected TSC adjustments (due to suspend) */
2771 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2772 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2773 vcpu->arch.tsc_offset_adjustment = 0;
2774 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2775 }
8f6055cb 2776
48434c20 2777 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2778 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2779 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2780 if (tsc_delta < 0)
2781 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2782 if (check_tsc_unstable()) {
b183aa58
ZA		 2783 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2784 vcpu->arch.last_guest_tsc);
2785 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2786 vcpu->arch.tsc_catchup = 1;
c285545f 2787 }
d98d07ca
MT		 2788 /*
2789 * On a host with synchronized TSC, there is no need to update
2790 * kvmclock on vcpu->cpu migration
2791 */
2792 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2793 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2794 if (vcpu->cpu != cpu)
2795 kvm_migrate_timers(vcpu);
e48672fa 2796 vcpu->cpu = cpu;
6b7d7e76 2797 }
c9aaa895
GC		 2798
2799 accumulate_steal_time(vcpu);
2800 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2801}
2802
2803void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2804{
02daab21 2805 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2806 kvm_put_guest_fpu(vcpu);
6f526ec5 2807 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2808}
2809
313a3dc7
CO		 2810static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2811 struct kvm_lapic_state *s)
2812{
5a71785d 2813 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2814 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2815
2816 return 0;
2817}
2818
2819static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2820 struct kvm_lapic_state *s)
2821{
64eb0620 2822 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2823 update_cr8_intercept(vcpu);
313a3dc7
CO		 2824
2825 return 0;
2826}
2827
f77bc6a4
ZX		 2828static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2829 struct kvm_interrupt *irq)
2830{
02cdb50f 2831 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2832 return -EINVAL;
2833 if (irqchip_in_kernel(vcpu->kvm))
2834 return -ENXIO;
f77bc6a4 2835
66fd3f7f 2836 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2837 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2838
f77bc6a4
ZX		 2839 return 0;
2840}
2841
c4abb7c9
JK		 2842static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2843{
c4abb7c9 2844 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2845
2846 return 0;
2847}
2848
b209749f
AK		 2849static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2850 struct kvm_tpr_access_ctl *tac)
2851{
2852 if (tac->flags)
2853 return -EINVAL;
2854 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2855 return 0;
2856}
2857
890ca9ae
HY		 2858static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2859 u64 mcg_cap)
2860{
2861 int r;
2862 unsigned bank_num = mcg_cap & 0xff, bank;
2863
2864 r = -EINVAL;
a9e38c3e 2865 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2866 goto out;
2867 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2868 goto out;
2869 r = 0;
2870 vcpu->arch.mcg_cap = mcg_cap;
2871 /* Init IA32_MCG_CTL to all 1s */
2872 if (mcg_cap & MCG_CTL_P)
2873 vcpu->arch.mcg_ctl = ~(u64)0;
2874 /* Init IA32_MCi_CTL to all 1s */
2875 for (bank = 0; bank < bank_num; bank++)
2876 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2877out:
2878 return r;
2879}
2880
2881static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2882 struct kvm_x86_mce *mce)
2883{
2884 u64 mcg_cap = vcpu->arch.mcg_cap;
2885 unsigned bank_num = mcg_cap & 0xff;
2886 u64 *banks = vcpu->arch.mce_banks;
2887
2888 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2889 return -EINVAL;
2890 /*
2891 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2892 * reporting is disabled
2893 */
2894 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2895 vcpu->arch.mcg_ctl != ~(u64)0)
2896 return 0;
2897 banks += 4 * mce->bank;
2898 /*
2899 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2900 * reporting is disabled for the bank
2901 */
2902 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2903 return 0;
2904 if (mce->status & MCI_STATUS_UC) {
2905 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2906 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2907 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2908 return 0;
2909 }
2910 if (banks[1] & MCI_STATUS_VAL)
2911 mce->status |= MCI_STATUS_OVER;
2912 banks[2] = mce->addr;
2913 banks[3] = mce->misc;
2914 vcpu->arch.mcg_status = mce->mcg_status;
2915 banks[1] = mce->status;
2916 kvm_queue_exception(vcpu, MC_VECTOR);
2917 } else if (!(banks[1] & MCI_STATUS_VAL)
2918 || !(banks[1] & MCI_STATUS_UC)) {
2919 if (banks[1] & MCI_STATUS_VAL)
2920 mce->status |= MCI_STATUS_OVER;
2921 banks[2] = mce->addr;
2922 banks[3] = mce->misc;
2923 banks[1] = mce->status;
2924 } else
2925 banks[1] |= MCI_STATUS_OVER;
2926 return 0;
2927}
2928
3cfc3092
JK		 2929static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2930 struct kvm_vcpu_events *events)
2931{
7460fb4a 2932 process_nmi(vcpu);
03b82a30
JK		 2933 events->exception.injected =
2934 vcpu->arch.exception.pending &&
2935 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2936 events->exception.nr = vcpu->arch.exception.nr;
2937 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2938 events->exception.pad = 0;
3cfc3092
JK		 2939 events->exception.error_code = vcpu->arch.exception.error_code;
2940
03b82a30
JK		 2941 events->interrupt.injected =
2942 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2943 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2944 events->interrupt.soft = 0;
48005f64
JK		 2945 events->interrupt.shadow =
2946 kvm_x86_ops->get_interrupt_shadow(vcpu,
2947 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2948
2949 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2950 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2951 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2952 events->nmi.pad = 0;
3cfc3092 2953
66450a21 2954 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2955
dab4b911 2956 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2957 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2958 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2959}
2960
2961static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2962 struct kvm_vcpu_events *events)
2963{
dab4b911 2964 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2965 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2966 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2967 return -EINVAL;
2968
7460fb4a 2969 process_nmi(vcpu);
3cfc3092
JK		 2970 vcpu->arch.exception.pending = events->exception.injected;
2971 vcpu->arch.exception.nr = events->exception.nr;
2972 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2973 vcpu->arch.exception.error_code = events->exception.error_code;
2974
2975 vcpu->arch.interrupt.pending = events->interrupt.injected;
2976 vcpu->arch.interrupt.nr = events->interrupt.nr;
2977 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2978 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2979 kvm_x86_ops->set_interrupt_shadow(vcpu,
2980 events->interrupt.shadow);
3cfc3092
JK		 2981
2982 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2983 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2984 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2985 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2986
66450a21
JK		 2987 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2988 kvm_vcpu_has_lapic(vcpu))
2989 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2990
3842d135
AK		 2991 kvm_make_request(KVM_REQ_EVENT, vcpu);
2992
3cfc3092
JK		 2993 return 0;
2994}
2995
a1efbe77
JK		 2996static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2997 struct kvm_debugregs *dbgregs)
2998{
73aaf249
JK		 2999 unsigned long val;
3000
a1efbe77 3001 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3002 _kvm_get_dr(vcpu, 6, &val);
3003 dbgregs->dr6 = val;
a1efbe77
JK		 3004 dbgregs->dr7 = vcpu->arch.dr7;
3005 dbgregs->flags = 0;
97e69aa6 3006 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3007}
3008
3009static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3010 struct kvm_debugregs *dbgregs)
3011{
3012 if (dbgregs->flags)
3013 return -EINVAL;
3014
a1efbe77
JK		 3015 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3016 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3017 kvm_update_dr6(vcpu);
a1efbe77 3018 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3019 kvm_update_dr7(vcpu);
a1efbe77 3020
a1efbe77
JK		 3021 return 0;
3022}
3023
2d5b5a66
SY		 3024static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3025 struct kvm_xsave *guest_xsave)
3026{
4344ee98 3027 if (cpu_has_xsave) {
2d5b5a66
SY		 3028 memcpy(guest_xsave->region,
3029 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3030 vcpu->arch.guest_xstate_size);
3031 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3032 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3033 } else {
2d5b5a66
SY		 3034 memcpy(guest_xsave->region,
3035 &vcpu->arch.guest_fpu.state->fxsave,
3036 sizeof(struct i387_fxsave_struct));
3037 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3038 XSTATE_FPSSE;
3039 }
3040}
3041
3042static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3043 struct kvm_xsave *guest_xsave)
3044{
3045 u64 xstate_bv =
3046 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3047
d7876f1b
PB		 3048 if (cpu_has_xsave) {
3049 /*
3050 * Here we allow setting states that are not present in
3051 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3052 * with old userspace.
3053 */
3054 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3055 return -EINVAL;
3056 if (xstate_bv & ~host_xcr0)
3057 return -EINVAL;
2d5b5a66 3058 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3059 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3060 } else {
2d5b5a66
SY		 3061 if (xstate_bv & ~XSTATE_FPSSE)
3062 return -EINVAL;
3063 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3064 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3065 }
3066 return 0;
3067}
3068
3069static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3070 struct kvm_xcrs *guest_xcrs)
3071{
3072 if (!cpu_has_xsave) {
3073 guest_xcrs->nr_xcrs = 0;
3074 return;
3075 }
3076
3077 guest_xcrs->nr_xcrs = 1;
3078 guest_xcrs->flags = 0;
3079 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3080 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3081}
3082
3083static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3084 struct kvm_xcrs *guest_xcrs)
3085{
3086 int i, r = 0;
3087
3088 if (!cpu_has_xsave)
3089 return -EINVAL;
3090
3091 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3092 return -EINVAL;
3093
3094 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3095 /* Only support XCR0 currently */
c67a04cb 3096 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3097 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3098 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3099 break;
3100 }
3101 if (r)
3102 r = -EINVAL;
3103 return r;
3104}
3105
1c0b28c2
EM		 3106/*
3107 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3108 * stopped by the hypervisor. This function will be called from the host only.
3109 * EINVAL is returned when the host attempts to set the flag for a guest that
3110 * does not support pv clocks.
3111 */
3112static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3113{
0b79459b 3114 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3115 return -EINVAL;
51d59c6b 3116 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3117 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3118 return 0;
3119}
3120
313a3dc7
CO		 3121long kvm_arch_vcpu_ioctl(struct file *filp,
3122 unsigned int ioctl, unsigned long arg)
3123{
3124 struct kvm_vcpu *vcpu = filp->private_data;
3125 void __user *argp = (void __user *)arg;
3126 int r;
d1ac91d8
AK		 3127 union {
3128 struct kvm_lapic_state *lapic;
3129 struct kvm_xsave *xsave;
3130 struct kvm_xcrs *xcrs;
3131 void *buffer;
3132 } u;
3133
3134 u.buffer = NULL;
313a3dc7
CO		 3135 switch (ioctl) {
3136 case KVM_GET_LAPIC: {
2204ae3c
MT		 3137 r = -EINVAL;
3138 if (!vcpu->arch.apic)
3139 goto out;
d1ac91d8 3140 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3141
b772ff36 3142 r = -ENOMEM;
d1ac91d8 3143 if (!u.lapic)
b772ff36 3144 goto out;
d1ac91d8 3145 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3146 if (r)
3147 goto out;
3148 r = -EFAULT;
d1ac91d8 3149 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3150 goto out;
3151 r = 0;
3152 break;
3153 }
3154 case KVM_SET_LAPIC: {
2204ae3c
MT		 3155 r = -EINVAL;
3156 if (!vcpu->arch.apic)
3157 goto out;
ff5c2c03 3158 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3159 if (IS_ERR(u.lapic))
3160 return PTR_ERR(u.lapic);
ff5c2c03 3161
d1ac91d8 3162 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3163 break;
3164 }
f77bc6a4
ZX		 3165 case KVM_INTERRUPT: {
3166 struct kvm_interrupt irq;
3167
3168 r = -EFAULT;
3169 if (copy_from_user(&irq, argp, sizeof irq))
3170 goto out;
3171 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3172 break;
3173 }
c4abb7c9
JK		 3174 case KVM_NMI: {
3175 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3176 break;
3177 }
313a3dc7
CO		 3178 case KVM_SET_CPUID: {
3179 struct kvm_cpuid __user *cpuid_arg = argp;
3180 struct kvm_cpuid cpuid;
3181
3182 r = -EFAULT;
3183 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3184 goto out;
3185 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3186 break;
3187 }
07716717
DK		 3188 case KVM_SET_CPUID2: {
3189 struct kvm_cpuid2 __user *cpuid_arg = argp;
3190 struct kvm_cpuid2 cpuid;
3191
3192 r = -EFAULT;
3193 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3194 goto out;
3195 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3196 cpuid_arg->entries);
07716717
DK		 3197 break;
3198 }
3199 case KVM_GET_CPUID2: {
3200 struct kvm_cpuid2 __user *cpuid_arg = argp;
3201 struct kvm_cpuid2 cpuid;
3202
3203 r = -EFAULT;
3204 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3205 goto out;
3206 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3207 cpuid_arg->entries);
07716717
DK		 3208 if (r)
3209 goto out;
3210 r = -EFAULT;
3211 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3212 goto out;
3213 r = 0;
3214 break;
3215 }
313a3dc7
CO		 3216 case KVM_GET_MSRS:
3217 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3218 break;
3219 case KVM_SET_MSRS:
3220 r = msr_io(vcpu, argp, do_set_msr, 0);
3221 break;
b209749f
AK		 3222 case KVM_TPR_ACCESS_REPORTING: {
3223 struct kvm_tpr_access_ctl tac;
3224
3225 r = -EFAULT;
3226 if (copy_from_user(&tac, argp, sizeof tac))
3227 goto out;
3228 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3229 if (r)
3230 goto out;
3231 r = -EFAULT;
3232 if (copy_to_user(argp, &tac, sizeof tac))
3233 goto out;
3234 r = 0;
3235 break;
3236 };
b93463aa
AK		 3237 case KVM_SET_VAPIC_ADDR: {
3238 struct kvm_vapic_addr va;
3239
3240 r = -EINVAL;
3241 if (!irqchip_in_kernel(vcpu->kvm))
3242 goto out;
3243 r = -EFAULT;
3244 if (copy_from_user(&va, argp, sizeof va))
3245 goto out;
fda4e2e8 3246 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3247 break;
3248 }
890ca9ae
HY		 3249 case KVM_X86_SETUP_MCE: {
3250 u64 mcg_cap;
3251
3252 r = -EFAULT;
3253 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3254 goto out;
3255 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3256 break;
3257 }
3258 case KVM_X86_SET_MCE: {
3259 struct kvm_x86_mce mce;
3260
3261 r = -EFAULT;
3262 if (copy_from_user(&mce, argp, sizeof mce))
3263 goto out;
3264 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3265 break;
3266 }
3cfc3092
JK		 3267 case KVM_GET_VCPU_EVENTS: {
3268 struct kvm_vcpu_events events;
3269
3270 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3271
3272 r = -EFAULT;
3273 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3274 break;
3275 r = 0;
3276 break;
3277 }
3278 case KVM_SET_VCPU_EVENTS: {
3279 struct kvm_vcpu_events events;
3280
3281 r = -EFAULT;
3282 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3283 break;
3284
3285 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3286 break;
3287 }
a1efbe77
JK		 3288 case KVM_GET_DEBUGREGS: {
3289 struct kvm_debugregs dbgregs;
3290
3291 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3292
3293 r = -EFAULT;
3294 if (copy_to_user(argp, &dbgregs,
3295 sizeof(struct kvm_debugregs)))
3296 break;
3297 r = 0;
3298 break;
3299 }
3300 case KVM_SET_DEBUGREGS: {
3301 struct kvm_debugregs dbgregs;
3302
3303 r = -EFAULT;
3304 if (copy_from_user(&dbgregs, argp,
3305 sizeof(struct kvm_debugregs)))
3306 break;
3307
3308 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3309 break;
3310 }
2d5b5a66 3311 case KVM_GET_XSAVE: {
d1ac91d8 3312 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3313 r = -ENOMEM;
d1ac91d8 3314 if (!u.xsave)
2d5b5a66
SY		 3315 break;
3316
d1ac91d8 3317 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3318
3319 r = -EFAULT;
d1ac91d8 3320 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3321 break;
3322 r = 0;
3323 break;
3324 }
3325 case KVM_SET_XSAVE: {
ff5c2c03 3326 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3327 if (IS_ERR(u.xsave))
3328 return PTR_ERR(u.xsave);
2d5b5a66 3329
d1ac91d8 3330 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3331 break;
3332 }
3333 case KVM_GET_XCRS: {
d1ac91d8 3334 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3335 r = -ENOMEM;
d1ac91d8 3336 if (!u.xcrs)
2d5b5a66
SY		 3337 break;
3338
d1ac91d8 3339 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3340
3341 r = -EFAULT;
d1ac91d8 3342 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3343 sizeof(struct kvm_xcrs)))
3344 break;
3345 r = 0;
3346 break;
3347 }
3348 case KVM_SET_XCRS: {
ff5c2c03 3349 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3350 if (IS_ERR(u.xcrs))
3351 return PTR_ERR(u.xcrs);
2d5b5a66 3352
d1ac91d8 3353 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3354 break;
3355 }
92a1f12d
JR		 3356 case KVM_SET_TSC_KHZ: {
3357 u32 user_tsc_khz;
3358
3359 r = -EINVAL;
92a1f12d
JR		 3360 user_tsc_khz = (u32)arg;
3361
3362 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3363 goto out;
3364
cc578287
ZA		 3365 if (user_tsc_khz == 0)
3366 user_tsc_khz = tsc_khz;
3367
3368 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3369
3370 r = 0;
3371 goto out;
3372 }
3373 case KVM_GET_TSC_KHZ: {
cc578287 3374 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3375 goto out;
3376 }
1c0b28c2
EM		 3377 case KVM_KVMCLOCK_CTRL: {
3378 r = kvm_set_guest_paused(vcpu);
3379 goto out;
3380 }
313a3dc7
CO		 3381 default:
3382 r = -EINVAL;
3383 }
3384out:
d1ac91d8 3385 kfree(u.buffer);
313a3dc7
CO		 3386 return r;
3387}
3388
5b1c1493
CO		 3389int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3390{
3391 return VM_FAULT_SIGBUS;
3392}
3393
1fe779f8
CO		 3394static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3395{
3396 int ret;
3397
3398 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3399 return -EINVAL;
1fe779f8
CO		 3400 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3401 return ret;
3402}
3403
b927a3ce
SY		 3404static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3405 u64 ident_addr)
3406{
3407 kvm->arch.ept_identity_map_addr = ident_addr;
3408 return 0;
3409}
3410
1fe779f8
CO		 3411static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3412 u32 kvm_nr_mmu_pages)
3413{
3414 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3415 return -EINVAL;
3416
79fac95e 3417 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3418
3419 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3420 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3421
79fac95e 3422 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3423 return 0;
3424}
3425
3426static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3427{
39de71ec 3428 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3429}
3430
1fe779f8
CO		 3431static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3432{
3433 int r;
3434
3435 r = 0;
3436 switch (chip->chip_id) {
3437 case KVM_IRQCHIP_PIC_MASTER:
3438 memcpy(&chip->chip.pic,
3439 &pic_irqchip(kvm)->pics[0],
3440 sizeof(struct kvm_pic_state));
3441 break;
3442 case KVM_IRQCHIP_PIC_SLAVE:
3443 memcpy(&chip->chip.pic,
3444 &pic_irqchip(kvm)->pics[1],
3445 sizeof(struct kvm_pic_state));
3446 break;
3447 case KVM_IRQCHIP_IOAPIC:
eba0226b 3448 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3449 break;
3450 default:
3451 r = -EINVAL;
3452 break;
3453 }
3454 return r;
3455}
3456
3457static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3458{
3459 int r;
3460
3461 r = 0;
3462 switch (chip->chip_id) {
3463 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3464 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3465 memcpy(&pic_irqchip(kvm)->pics[0],
3466 &chip->chip.pic,
3467 sizeof(struct kvm_pic_state));
f4f51050 3468 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3469 break;
3470 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3471 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3472 memcpy(&pic_irqchip(kvm)->pics[1],
3473 &chip->chip.pic,
3474 sizeof(struct kvm_pic_state));
f4f51050 3475 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3476 break;
3477 case KVM_IRQCHIP_IOAPIC:
eba0226b 3478 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3479 break;
3480 default:
3481 r = -EINVAL;
3482 break;
3483 }
3484 kvm_pic_update_irq(pic_irqchip(kvm));
3485 return r;
3486}
3487
e0f63cb9
SY		 3488static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3489{
3490 int r = 0;
3491
894a9c55 3492 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3493 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3494 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3495 return r;
3496}
3497
3498static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3499{
3500 int r = 0;
3501
894a9c55 3502 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3503 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3504 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3505 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3506 return r;
3507}
3508
3509static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3510{
3511 int r = 0;
3512
3513 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3514 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3515 sizeof(ps->channels));
3516 ps->flags = kvm->arch.vpit->pit_state.flags;
3517 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3518 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3519 return r;
3520}
3521
3522static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3523{
3524 int r = 0, start = 0;
3525 u32 prev_legacy, cur_legacy;
3526 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3527 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3528 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3529 if (!prev_legacy && cur_legacy)
3530 start = 1;
3531 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3532 sizeof(kvm->arch.vpit->pit_state.channels));
3533 kvm->arch.vpit->pit_state.flags = ps->flags;
3534 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3535 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3536 return r;
3537}
3538
52d939a0
MT		 3539static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3540 struct kvm_reinject_control *control)
3541{
3542 if (!kvm->arch.vpit)
3543 return -ENXIO;
894a9c55 3544 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3545 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3546 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3547 return 0;
3548}
3549
95d4c16c 3550/**
60c34612
TY		 3551 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3552 * @kvm: kvm instance
3553 * @log: slot id and address to which we copy the log
95d4c16c 3554 *
60c34612
TY		 3555 * We need to keep it in mind that VCPU threads can write to the bitmap
3556 * concurrently. So, to avoid losing data, we keep the following order for
3557 * each bit:
95d4c16c 3558 *
60c34612
TY		 3559 * 1. Take a snapshot of the bit and clear it if needed.
3560 * 2. Write protect the corresponding page.
3561 * 3. Flush TLB's if needed.
3562 * 4. Copy the snapshot to the userspace.
95d4c16c 3563 *
60c34612
TY		 3564 * Between 2 and 3, the guest may write to the page using the remaining TLB
3565 * entry. This is not a problem because the page will be reported dirty at
3566 * step 4 using the snapshot taken before and step 3 ensures that successive
3567 * writes will be logged for the next call.
5bb064dc 3568 */
60c34612 3569int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3570{
7850ac54 3571 int r;
5bb064dc 3572 struct kvm_memory_slot *memslot;
60c34612
TY		 3573 unsigned long n, i;
3574 unsigned long *dirty_bitmap;
3575 unsigned long *dirty_bitmap_buffer;
3576 bool is_dirty = false;
5bb064dc 3577
79fac95e 3578 mutex_lock(&kvm->slots_lock);
5bb064dc 3579
b050b015 3580 r = -EINVAL;
bbacc0c1 3581 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3582 goto out;
3583
28a37544 3584 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3585
3586 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3587 r = -ENOENT;
60c34612 3588 if (!dirty_bitmap)
b050b015
MT		 3589 goto out;
3590
87bf6e7d 3591 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3592
60c34612
TY		 3593 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3594 memset(dirty_bitmap_buffer, 0, n);
b050b015 3595
60c34612 3596 spin_lock(&kvm->mmu_lock);
b050b015 3597
60c34612
TY		 3598 for (i = 0; i < n / sizeof(long); i++) {
3599 unsigned long mask;
3600 gfn_t offset;
cdfca7b3 3601
60c34612
TY		 3602 if (!dirty_bitmap[i])
3603 continue;
b050b015 3604
60c34612 3605 is_dirty = true;
914ebccd 3606
60c34612
TY		 3607 mask = xchg(&dirty_bitmap[i], 0);
3608 dirty_bitmap_buffer[i] = mask;
edde99ce 3609
60c34612
TY		 3610 offset = i * BITS_PER_LONG;
3611 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3612 }
60c34612
TY		 3613 if (is_dirty)
3614 kvm_flush_remote_tlbs(kvm);
3615
3616 spin_unlock(&kvm->mmu_lock);
3617
3618 r = -EFAULT;
3619 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3620 goto out;
b050b015 3621
5bb064dc
ZX		 3622 r = 0;
3623out:
79fac95e 3624 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3625 return r;
3626}
3627
aa2fbe6d
YZ		 3628int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3629 bool line_status)
23d43cf9
CD		 3630{
3631 if (!irqchip_in_kernel(kvm))
3632 return -ENXIO;
3633
3634 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3635 irq_event->irq, irq_event->level,
3636 line_status);
23d43cf9
CD		 3637 return 0;
3638}
3639
1fe779f8
CO		 3640long kvm_arch_vm_ioctl(struct file *filp,
3641 unsigned int ioctl, unsigned long arg)
3642{
3643 struct kvm *kvm = filp->private_data;
3644 void __user *argp = (void __user *)arg;
367e1319 3645 int r = -ENOTTY;
f0d66275
DH		 3646 /*
3647 * This union makes it completely explicit to gcc-3.x
3648 * that these two variables' stack usage should be
3649 * combined, not added together.
3650 */
3651 union {
3652 struct kvm_pit_state ps;
e9f42757 3653 struct kvm_pit_state2 ps2;
c5ff41ce 3654 struct kvm_pit_config pit_config;
f0d66275 3655 } u;
1fe779f8
CO		 3656
3657 switch (ioctl) {
3658 case KVM_SET_TSS_ADDR:
3659 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3660 break;
b927a3ce
SY		 3661 case KVM_SET_IDENTITY_MAP_ADDR: {
3662 u64 ident_addr;
3663
3664 r = -EFAULT;
3665 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3666 goto out;
3667 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3668 break;
3669 }
1fe779f8
CO		 3670 case KVM_SET_NR_MMU_PAGES:
3671 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3672 break;
3673 case KVM_GET_NR_MMU_PAGES:
3674 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3675 break;
3ddea128
MT		 3676 case KVM_CREATE_IRQCHIP: {
3677 struct kvm_pic *vpic;
3678
3679 mutex_lock(&kvm->lock);
3680 r = -EEXIST;
3681 if (kvm->arch.vpic)
3682 goto create_irqchip_unlock;
3e515705
AK		 3683 r = -EINVAL;
3684 if (atomic_read(&kvm->online_vcpus))
3685 goto create_irqchip_unlock;
1fe779f8 3686 r = -ENOMEM;
3ddea128
MT		 3687 vpic = kvm_create_pic(kvm);
3688 if (vpic) {
1fe779f8
CO		 3689 r = kvm_ioapic_init(kvm);
3690 if (r) {
175504cd 3691 mutex_lock(&kvm->slots_lock);
72bb2fcd 3692 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3693 &vpic->dev_master);
3694 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3695 &vpic->dev_slave);
3696 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3697 &vpic->dev_eclr);
175504cd 3698 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3699 kfree(vpic);
3700 goto create_irqchip_unlock;
1fe779f8
CO		 3701 }
3702 } else
3ddea128
MT		 3703 goto create_irqchip_unlock;
3704 smp_wmb();
3705 kvm->arch.vpic = vpic;
3706 smp_wmb();
399ec807
AK		 3707 r = kvm_setup_default_irq_routing(kvm);
3708 if (r) {
175504cd 3709 mutex_lock(&kvm->slots_lock);
3ddea128 3710 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3711 kvm_ioapic_destroy(kvm);
3712 kvm_destroy_pic(kvm);
3ddea128 3713 mutex_unlock(&kvm->irq_lock);
175504cd 3714 mutex_unlock(&kvm->slots_lock);
399ec807 3715 }
3ddea128
MT		 3716 create_irqchip_unlock:
3717 mutex_unlock(&kvm->lock);
1fe779f8 3718 break;
3ddea128 3719 }
7837699f 3720 case KVM_CREATE_PIT:
c5ff41ce
JK		 3721 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3722 goto create_pit;
3723 case KVM_CREATE_PIT2:
3724 r = -EFAULT;
3725 if (copy_from_user(&u.pit_config, argp,
3726 sizeof(struct kvm_pit_config)))
3727 goto out;
3728 create_pit:
79fac95e 3729 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3730 r = -EEXIST;
3731 if (kvm->arch.vpit)
3732 goto create_pit_unlock;
7837699f 3733 r = -ENOMEM;
c5ff41ce 3734 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3735 if (kvm->arch.vpit)
3736 r = 0;
269e05e4 3737 create_pit_unlock:
79fac95e 3738 mutex_unlock(&kvm->slots_lock);
7837699f 3739 break;
1fe779f8
CO		 3740 case KVM_GET_IRQCHIP: {
3741 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3742 struct kvm_irqchip *chip;
1fe779f8 3743
ff5c2c03
SL		 3744 chip = memdup_user(argp, sizeof(*chip));
3745 if (IS_ERR(chip)) {
3746 r = PTR_ERR(chip);
1fe779f8 3747 goto out;
ff5c2c03
SL		 3748 }
3749
1fe779f8
CO		 3750 r = -ENXIO;
3751 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3752 goto get_irqchip_out;
3753 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3754 if (r)
f0d66275 3755 goto get_irqchip_out;
1fe779f8 3756 r = -EFAULT;
f0d66275
DH		 3757 if (copy_to_user(argp, chip, sizeof *chip))
3758 goto get_irqchip_out;
1fe779f8 3759 r = 0;
f0d66275
DH		 3760 get_irqchip_out:
3761 kfree(chip);
1fe779f8
CO		 3762 break;
3763 }
3764 case KVM_SET_IRQCHIP: {
3765 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3766 struct kvm_irqchip *chip;
1fe779f8 3767
ff5c2c03
SL		 3768 chip = memdup_user(argp, sizeof(*chip));
3769 if (IS_ERR(chip)) {
3770 r = PTR_ERR(chip);
1fe779f8 3771 goto out;
ff5c2c03
SL		 3772 }
3773
1fe779f8
CO		 3774 r = -ENXIO;
3775 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3776 goto set_irqchip_out;
3777 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3778 if (r)
f0d66275 3779 goto set_irqchip_out;
1fe779f8 3780 r = 0;
f0d66275
DH		 3781 set_irqchip_out:
3782 kfree(chip);
1fe779f8
CO		 3783 break;
3784 }
e0f63cb9 3785 case KVM_GET_PIT: {
e0f63cb9 3786 r = -EFAULT;
f0d66275 3787 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3788 goto out;
3789 r = -ENXIO;
3790 if (!kvm->arch.vpit)
3791 goto out;
f0d66275 3792 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3793 if (r)
3794 goto out;
3795 r = -EFAULT;
f0d66275 3796 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3797 goto out;
3798 r = 0;
3799 break;
3800 }
3801 case KVM_SET_PIT: {
e0f63cb9 3802 r = -EFAULT;
f0d66275 3803 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3804 goto out;
3805 r = -ENXIO;
3806 if (!kvm->arch.vpit)
3807 goto out;
f0d66275 3808 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3809 break;
3810 }
e9f42757
BK		 3811 case KVM_GET_PIT2: {
3812 r = -ENXIO;
3813 if (!kvm->arch.vpit)
3814 goto out;
3815 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3816 if (r)
3817 goto out;
3818 r = -EFAULT;
3819 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3820 goto out;
3821 r = 0;
3822 break;
3823 }
3824 case KVM_SET_PIT2: {
3825 r = -EFAULT;
3826 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3827 goto out;
3828 r = -ENXIO;
3829 if (!kvm->arch.vpit)
3830 goto out;
3831 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3832 break;
3833 }
52d939a0
MT		 3834 case KVM_REINJECT_CONTROL: {
3835 struct kvm_reinject_control control;
3836 r = -EFAULT;
3837 if (copy_from_user(&control, argp, sizeof(control)))
3838 goto out;
3839 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3840 break;
3841 }
ffde22ac
ES		 3842 case KVM_XEN_HVM_CONFIG: {
3843 r = -EFAULT;
3844 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3845 sizeof(struct kvm_xen_hvm_config)))
3846 goto out;
3847 r = -EINVAL;
3848 if (kvm->arch.xen_hvm_config.flags)
3849 goto out;
3850 r = 0;
3851 break;
3852 }
afbcf7ab 3853 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3854 struct kvm_clock_data user_ns;
3855 u64 now_ns;
3856 s64 delta;
3857
3858 r = -EFAULT;
3859 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3860 goto out;
3861
3862 r = -EINVAL;
3863 if (user_ns.flags)
3864 goto out;
3865
3866 r = 0;
395c6b0a 3867 local_irq_disable();
759379dd 3868 now_ns = get_kernel_ns();
afbcf7ab 3869 delta = user_ns.clock - now_ns;
395c6b0a 3870 local_irq_enable();
afbcf7ab 3871 kvm->arch.kvmclock_offset = delta;
2e762ff7 3872 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3873 break;
3874 }
3875 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3876 struct kvm_clock_data user_ns;
3877 u64 now_ns;
3878
395c6b0a 3879 local_irq_disable();
759379dd 3880 now_ns = get_kernel_ns();
afbcf7ab 3881 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3882 local_irq_enable();
afbcf7ab 3883 user_ns.flags = 0;
97e69aa6 3884 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3885
3886 r = -EFAULT;
3887 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3888 goto out;
3889 r = 0;
3890 break;
3891 }
3892
1fe779f8
CO		 3893 default:
3894 ;
3895 }
3896out:
3897 return r;
3898}
3899
a16b043c 3900static void kvm_init_msr_list(void)
043405e1
CO		 3901{
3902 u32 dummy[2];
3903 unsigned i, j;
3904
e3267cbb
GC		 3905 /* skip the first msrs in the list. KVM-specific */
3906 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3907 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3908 continue;
3909 if (j < i)
3910 msrs_to_save[j] = msrs_to_save[i];
3911 j++;
3912 }
3913 num_msrs_to_save = j;
3914}
3915
bda9020e
MT		 3916static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3917 const void *v)
bbd9b64e 3918{
70252a10
AK		 3919 int handled = 0;
3920 int n;
3921
3922 do {
3923 n = min(len, 8);
3924 if (!(vcpu->arch.apic &&
3925 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3926 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3927 break;
3928 handled += n;
3929 addr += n;
3930 len -= n;
3931 v += n;
3932 } while (len);
bbd9b64e 3933
70252a10 3934 return handled;
bbd9b64e
CO		 3935}
3936
bda9020e 3937static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3938{
70252a10
AK		 3939 int handled = 0;
3940 int n;
3941
3942 do {
3943 n = min(len, 8);
3944 if (!(vcpu->arch.apic &&
3945 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3946 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3947 break;
3948 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3949 handled += n;
3950 addr += n;
3951 len -= n;
3952 v += n;
3953 } while (len);
bbd9b64e 3954
70252a10 3955 return handled;
bbd9b64e
CO		 3956}
3957
2dafc6c2
GN		 3958static void kvm_set_segment(struct kvm_vcpu *vcpu,
3959 struct kvm_segment *var, int seg)
3960{
3961 kvm_x86_ops->set_segment(vcpu, var, seg);
3962}
3963
3964void kvm_get_segment(struct kvm_vcpu *vcpu,
3965 struct kvm_segment *var, int seg)
3966{
3967 kvm_x86_ops->get_segment(vcpu, var, seg);
3968}
3969
e459e322 3970gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3971{
3972 gpa_t t_gpa;
ab9ae313 3973 struct x86_exception exception;
02f59dc9
JR		 3974
3975 BUG_ON(!mmu_is_nested(vcpu));
3976
3977 /* NPT walks are always user-walks */
3978 access |= PFERR_USER_MASK;
ab9ae313 3979 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3980
3981 return t_gpa;
3982}
3983
ab9ae313
AK		 3984gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3985 struct x86_exception *exception)
1871c602
GN		 3986{
3987 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3988 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3989}
3990
ab9ae313
AK		 3991 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3992 struct x86_exception *exception)
1871c602
GN		 3993{
3994 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3995 access |= PFERR_FETCH_MASK;
ab9ae313 3996 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3997}
3998
ab9ae313
AK		 3999gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4000 struct x86_exception *exception)
1871c602
GN		 4001{
4002 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4003 access |= PFERR_WRITE_MASK;
ab9ae313 4004 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4005}
4006
4007/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4008gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4009 struct x86_exception *exception)
1871c602 4010{
ab9ae313 4011 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4012}
4013
4014static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4015 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4016 struct x86_exception *exception)
bbd9b64e
CO		 4017{
4018 void *data = val;
10589a46 4019 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4020
4021 while (bytes) {
14dfe855 4022 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4023 exception);
bbd9b64e 4024 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4025 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4026 int ret;
4027
bcc55cba 4028 if (gpa == UNMAPPED_GVA)
ab9ae313 4029 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4030 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4031 if (ret < 0) {
c3cd7ffa 4032 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4033 goto out;
4034 }
bbd9b64e 4035
77c2002e
IE		 4036 bytes -= toread;
4037 data += toread;
4038 addr += toread;
bbd9b64e 4039 }
10589a46 4040out:
10589a46 4041 return r;
bbd9b64e 4042}
77c2002e 4043
1871c602 4044/* used for instruction fetching */
0f65dd70
AK		 4045static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4046 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4047 struct x86_exception *exception)
1871c602 4048{
0f65dd70 4049 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4050 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4051
1871c602 4052 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4053 access | PFERR_FETCH_MASK,
4054 exception);
1871c602
GN		 4055}
4056
064aea77 4057int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4058 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4059 struct x86_exception *exception)
1871c602 4060{
0f65dd70 4061 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4062 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4063
1871c602 4064 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4065 exception);
1871c602 4066}
064aea77 4067EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4068
0f65dd70
AK		 4069static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4070 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4071 struct x86_exception *exception)
1871c602 4072{
0f65dd70 4073 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4074 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4075}
4076
6a4d7550 4077int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4078 gva_t addr, void *val,
2dafc6c2 4079 unsigned int bytes,
bcc55cba 4080 struct x86_exception *exception)
77c2002e 4081{
0f65dd70 4082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4083 void *data = val;
4084 int r = X86EMUL_CONTINUE;
4085
4086 while (bytes) {
14dfe855
JR		 4087 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4088 PFERR_WRITE_MASK,
ab9ae313 4089 exception);
77c2002e
IE		 4090 unsigned offset = addr & (PAGE_SIZE-1);
4091 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4092 int ret;
4093
bcc55cba 4094 if (gpa == UNMAPPED_GVA)
ab9ae313 4095 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4096 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4097 if (ret < 0) {
c3cd7ffa 4098 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4099 goto out;
4100 }
4101
4102 bytes -= towrite;
4103 data += towrite;
4104 addr += towrite;
4105 }
4106out:
4107 return r;
4108}
6a4d7550 4109EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4110
af7cc7d1
XG		 4111static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4112 gpa_t *gpa, struct x86_exception *exception,
4113 bool write)
4114{
97d64b78
AK		 4115 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4116 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4117
97d64b78
AK		 4118 if (vcpu_match_mmio_gva(vcpu, gva)
4119 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4120 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4121 (gva & (PAGE_SIZE - 1));
4f022648 4122 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4123 return 1;
4124 }
4125
af7cc7d1
XG		 4126 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4127
4128 if (*gpa == UNMAPPED_GVA)
4129 return -1;
4130
4131 /* For APIC access vmexit */
4132 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4133 return 1;
4134
4f022648
XG		 4135 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4136 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4137 return 1;
4f022648 4138 }
bebb106a 4139
af7cc7d1
XG		 4140 return 0;
4141}
4142
3200f405 4143int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4144 const void *val, int bytes)
bbd9b64e
CO		 4145{
4146 int ret;
4147
4148 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4149 if (ret < 0)
bbd9b64e 4150 return 0;
f57f2ef5 4151 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4152 return 1;
4153}
4154
77d197b2
XG		 4155struct read_write_emulator_ops {
4156 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4157 int bytes);
4158 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4159 void *val, int bytes);
4160 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4161 int bytes, void *val);
4162 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4163 void *val, int bytes);
4164 bool write;
4165};
4166
4167static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4168{
4169 if (vcpu->mmio_read_completed) {
77d197b2 4170 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4171 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4172 vcpu->mmio_read_completed = 0;
4173 return 1;
4174 }
4175
4176 return 0;
4177}
4178
4179static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4180 void *val, int bytes)
4181{
4182 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4183}
4184
4185static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4186 void *val, int bytes)
4187{
4188 return emulator_write_phys(vcpu, gpa, val, bytes);
4189}
4190
4191static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4192{
4193 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4194 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4195}
4196
4197static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4198 void *val, int bytes)
4199{
4200 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4201 return X86EMUL_IO_NEEDED;
4202}
4203
4204static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4205 void *val, int bytes)
4206{
f78146b0
AK		 4207 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4208
87da7e66 4209 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4210 return X86EMUL_CONTINUE;
4211}
4212
0fbe9b0b 4213static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4214 .read_write_prepare = read_prepare,
4215 .read_write_emulate = read_emulate,
4216 .read_write_mmio = vcpu_mmio_read,
4217 .read_write_exit_mmio = read_exit_mmio,
4218};
4219
0fbe9b0b 4220static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4221 .read_write_emulate = write_emulate,
4222 .read_write_mmio = write_mmio,
4223 .read_write_exit_mmio = write_exit_mmio,
4224 .write = true,
4225};
4226
22388a3c
XG		 4227static int emulator_read_write_onepage(unsigned long addr, void *val,
4228 unsigned int bytes,
4229 struct x86_exception *exception,
4230 struct kvm_vcpu *vcpu,
0fbe9b0b 4231 const struct read_write_emulator_ops *ops)
bbd9b64e 4232{
af7cc7d1
XG		 4233 gpa_t gpa;
4234 int handled, ret;
22388a3c 4235 bool write = ops->write;
f78146b0 4236 struct kvm_mmio_fragment *frag;
10589a46 4237
22388a3c 4238 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4239
af7cc7d1 4240 if (ret < 0)
bbd9b64e 4241 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4242
4243 /* For APIC access vmexit */
af7cc7d1 4244 if (ret)
bbd9b64e
CO		 4245 goto mmio;
4246
22388a3c 4247 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4248 return X86EMUL_CONTINUE;
4249
4250mmio:
4251 /*
4252 * Is this MMIO handled locally?
4253 */
22388a3c 4254 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4255 if (handled == bytes)
bbd9b64e 4256 return X86EMUL_CONTINUE;
bbd9b64e 4257
70252a10
AK		 4258 gpa += handled;
4259 bytes -= handled;
4260 val += handled;
4261
87da7e66
XG		 4262 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4263 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4264 frag->gpa = gpa;
4265 frag->data = val;
4266 frag->len = bytes;
f78146b0 4267 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4268}
4269
22388a3c
XG		 4270int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4271 void *val, unsigned int bytes,
4272 struct x86_exception *exception,
0fbe9b0b 4273 const struct read_write_emulator_ops *ops)
bbd9b64e 4274{
0f65dd70 4275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4276 gpa_t gpa;
4277 int rc;
4278
4279 if (ops->read_write_prepare &&
4280 ops->read_write_prepare(vcpu, val, bytes))
4281 return X86EMUL_CONTINUE;
4282
4283 vcpu->mmio_nr_fragments = 0;
0f65dd70 4284
bbd9b64e
CO		 4285 /* Crossing a page boundary? */
4286 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4287 int now;
bbd9b64e
CO		 4288
4289 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4290 rc = emulator_read_write_onepage(addr, val, now, exception,
4291 vcpu, ops);
4292
bbd9b64e
CO		 4293 if (rc != X86EMUL_CONTINUE)
4294 return rc;
4295 addr += now;
4296 val += now;
4297 bytes -= now;
4298 }
22388a3c 4299
f78146b0
AK		 4300 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4301 vcpu, ops);
4302 if (rc != X86EMUL_CONTINUE)
4303 return rc;
4304
4305 if (!vcpu->mmio_nr_fragments)
4306 return rc;
4307
4308 gpa = vcpu->mmio_fragments[0].gpa;
4309
4310 vcpu->mmio_needed = 1;
4311 vcpu->mmio_cur_fragment = 0;
4312
87da7e66 4313 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4314 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4315 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4316 vcpu->run->mmio.phys_addr = gpa;
4317
4318 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4319}
4320
4321static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4322 unsigned long addr,
4323 void *val,
4324 unsigned int bytes,
4325 struct x86_exception *exception)
4326{
4327 return emulator_read_write(ctxt, addr, val, bytes,
4328 exception, &read_emultor);
4329}
4330
4331int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4332 unsigned long addr,
4333 const void *val,
4334 unsigned int bytes,
4335 struct x86_exception *exception)
4336{
4337 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4338 exception, &write_emultor);
bbd9b64e 4339}
bbd9b64e 4340
daea3e73
AK		 4341#define CMPXCHG_TYPE(t, ptr, old, new) \
4342 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4343
4344#ifdef CONFIG_X86_64
4345# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4346#else
4347# define CMPXCHG64(ptr, old, new) \
9749a6c0 4348 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4349#endif
4350
0f65dd70
AK		 4351static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4352 unsigned long addr,
bbd9b64e
CO		 4353 const void *old,
4354 const void *new,
4355 unsigned int bytes,
0f65dd70 4356 struct x86_exception *exception)
bbd9b64e 4357{
0f65dd70 4358 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4359 gpa_t gpa;
4360 struct page *page;
4361 char *kaddr;
4362 bool exchanged;
2bacc55c 4363
daea3e73
AK		 4364 /* guests cmpxchg8b have to be emulated atomically */
4365 if (bytes > 8 || (bytes & (bytes - 1)))
4366 goto emul_write;
10589a46 4367
daea3e73 4368 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4369
daea3e73
AK		 4370 if (gpa == UNMAPPED_GVA ||
4371 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4372 goto emul_write;
2bacc55c 4373
daea3e73
AK		 4374 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4375 goto emul_write;
72dc67a6 4376
daea3e73 4377 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4378 if (is_error_page(page))
c19b8bd6 4379 goto emul_write;
72dc67a6 4380
8fd75e12 4381 kaddr = kmap_atomic(page);
daea3e73
AK		 4382 kaddr += offset_in_page(gpa);
4383 switch (bytes) {
4384 case 1:
4385 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4386 break;
4387 case 2:
4388 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4389 break;
4390 case 4:
4391 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4392 break;
4393 case 8:
4394 exchanged = CMPXCHG64(kaddr, old, new);
4395 break;
4396 default:
4397 BUG();
2bacc55c 4398 }
8fd75e12 4399 kunmap_atomic(kaddr);
daea3e73
AK		 4400 kvm_release_page_dirty(page);
4401
4402 if (!exchanged)
4403 return X86EMUL_CMPXCHG_FAILED;
4404
d3714010 4405 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4406 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4407
4408 return X86EMUL_CONTINUE;
4a5f48f6 4409
3200f405 4410emul_write:
daea3e73 4411 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4412
0f65dd70 4413 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4414}
4415
cf8f70bf
GN		 4416static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4417{
4418 /* TODO: String I/O for in kernel device */
4419 int r;
4420
4421 if (vcpu->arch.pio.in)
4422 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4423 vcpu->arch.pio.size, pd);
4424 else
4425 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4426 vcpu->arch.pio.port, vcpu->arch.pio.size,
4427 pd);
4428 return r;
4429}
4430
6f6fbe98
XG		 4431static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4432 unsigned short port, void *val,
4433 unsigned int count, bool in)
cf8f70bf 4434{
6f6fbe98 4435 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4436
4437 vcpu->arch.pio.port = port;
6f6fbe98 4438 vcpu->arch.pio.in = in;
7972995b 4439 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4440 vcpu->arch.pio.size = size;
4441
4442 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4443 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4444 return 1;
4445 }
4446
4447 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4448 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4449 vcpu->run->io.size = size;
4450 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4451 vcpu->run->io.count = count;
4452 vcpu->run->io.port = port;
4453
4454 return 0;
4455}
4456
6f6fbe98
XG		 4457static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4458 int size, unsigned short port, void *val,
4459 unsigned int count)
cf8f70bf 4460{
ca1d4a9e 4461 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4462 int ret;
ca1d4a9e 4463
6f6fbe98
XG		 4464 if (vcpu->arch.pio.count)
4465 goto data_avail;
cf8f70bf 4466
6f6fbe98
XG		 4467 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4468 if (ret) {
4469data_avail:
4470 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4471 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4472 return 1;
4473 }
4474
cf8f70bf
GN		 4475 return 0;
4476}
4477
6f6fbe98
XG		 4478static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4479 int size, unsigned short port,
4480 const void *val, unsigned int count)
4481{
4482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4483
4484 memcpy(vcpu->arch.pio_data, val, size * count);
4485 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4486}
4487
bbd9b64e
CO		 4488static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4489{
4490 return kvm_x86_ops->get_segment_base(vcpu, seg);
4491}
4492
3cb16fe7 4493static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4494{
3cb16fe7 4495 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4496}
4497
f5f48ee1
SY		 4498int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4499{
4500 if (!need_emulate_wbinvd(vcpu))
4501 return X86EMUL_CONTINUE;
4502
4503 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4504 int cpu = get_cpu();
4505
4506 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4507 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4508 wbinvd_ipi, NULL, 1);
2eec7343 4509 put_cpu();
f5f48ee1 4510 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4511 } else
4512 wbinvd();
f5f48ee1
SY		 4513 return X86EMUL_CONTINUE;
4514}
4515EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4516
bcaf5cc5
AK		 4517static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4518{
4519 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4520}
4521
717746e3 4522int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4523{
717746e3 4524 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4525}
4526
717746e3 4527int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4528{
338dbc97 4529
717746e3 4530 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4531}
4532
52a46617 4533static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4534{
52a46617 4535 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4536}
4537
717746e3 4538static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4539{
717746e3 4540 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4541 unsigned long value;
4542
4543 switch (cr) {
4544 case 0:
4545 value = kvm_read_cr0(vcpu);
4546 break;
4547 case 2:
4548 value = vcpu->arch.cr2;
4549 break;
4550 case 3:
9f8fe504 4551 value = kvm_read_cr3(vcpu);
52a46617
GN		 4552 break;
4553 case 4:
4554 value = kvm_read_cr4(vcpu);
4555 break;
4556 case 8:
4557 value = kvm_get_cr8(vcpu);
4558 break;
4559 default:
a737f256 4560 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4561 return 0;
4562 }
4563
4564 return value;
4565}
4566
717746e3 4567static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4568{
717746e3 4569 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4570 int res = 0;
4571
52a46617
GN		 4572 switch (cr) {
4573 case 0:
49a9b07e 4574 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4575 break;
4576 case 2:
4577 vcpu->arch.cr2 = val;
4578 break;
4579 case 3:
2390218b 4580 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4581 break;
4582 case 4:
a83b29c6 4583 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4584 break;
4585 case 8:
eea1cff9 4586 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4587 break;
4588 default:
a737f256 4589 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4590 res = -1;
52a46617 4591 }
0f12244f
GN		 4592
4593 return res;
52a46617
GN		 4594}
4595
4cee4798
KW		 4596static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4597{
4598 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4599}
4600
717746e3 4601static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4602{
717746e3 4603 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4604}
4605
4bff1e86 4606static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4607{
4bff1e86 4608 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4609}
4610
4bff1e86 4611static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4612{
4bff1e86 4613 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4614}
4615
1ac9d0cf
AK		 4616static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4617{
4618 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4619}
4620
4621static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4622{
4623 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4624}
4625
4bff1e86
AK		 4626static unsigned long emulator_get_cached_segment_base(
4627 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4628{
4bff1e86 4629 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4630}
4631
1aa36616
AK		 4632static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4633 struct desc_struct *desc, u32 *base3,
4634 int seg)
2dafc6c2
GN		 4635{
4636 struct kvm_segment var;
4637
4bff1e86 4638 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4639 *selector = var.selector;
2dafc6c2 4640
378a8b09
GN		 4641 if (var.unusable) {
4642 memset(desc, 0, sizeof(*desc));
2dafc6c2 4643 return false;
378a8b09 4644 }
2dafc6c2
GN		 4645
4646 if (var.g)
4647 var.limit >>= 12;
4648 set_desc_limit(desc, var.limit);
4649 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4650#ifdef CONFIG_X86_64
4651 if (base3)
4652 *base3 = var.base >> 32;
4653#endif
2dafc6c2
GN		 4654 desc->type = var.type;
4655 desc->s = var.s;
4656 desc->dpl = var.dpl;
4657 desc->p = var.present;
4658 desc->avl = var.avl;
4659 desc->l = var.l;
4660 desc->d = var.db;
4661 desc->g = var.g;
4662
4663 return true;
4664}
4665
1aa36616
AK		 4666static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4667 struct desc_struct *desc, u32 base3,
4668 int seg)
2dafc6c2 4669{
4bff1e86 4670 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4671 struct kvm_segment var;
4672
1aa36616 4673 var.selector = selector;
2dafc6c2 4674 var.base = get_desc_base(desc);
5601d05b
GN		 4675#ifdef CONFIG_X86_64
4676 var.base |= ((u64)base3) << 32;
4677#endif
2dafc6c2
GN		 4678 var.limit = get_desc_limit(desc);
4679 if (desc->g)
4680 var.limit = (var.limit << 12) | 0xfff;
4681 var.type = desc->type;
4682 var.present = desc->p;
4683 var.dpl = desc->dpl;
4684 var.db = desc->d;
4685 var.s = desc->s;
4686 var.l = desc->l;
4687 var.g = desc->g;
4688 var.avl = desc->avl;
4689 var.present = desc->p;
4690 var.unusable = !var.present;
4691 var.padding = 0;
4692
4693 kvm_set_segment(vcpu, &var, seg);
4694 return;
4695}
4696
717746e3
AK		 4697static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4698 u32 msr_index, u64 *pdata)
4699{
4700 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4701}
4702
4703static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4704 u32 msr_index, u64 data)
4705{
8fe8ab46
WA		 4706 struct msr_data msr;
4707
4708 msr.data = data;
4709 msr.index = msr_index;
4710 msr.host_initiated = false;
4711 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4712}
4713
222d21aa
AK		 4714static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4715 u32 pmc, u64 *pdata)
4716{
4717 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4718}
4719
6c3287f7
AK		 4720static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4721{
4722 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4723}
4724
5037f6f3
AK		 4725static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4726{
4727 preempt_disable();
5197b808 4728 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4729 /*
4730 * CR0.TS may reference the host fpu state, not the guest fpu state,
4731 * so it may be clear at this point.
4732 */
4733 clts();
4734}
4735
4736static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4737{
4738 preempt_enable();
4739}
4740
2953538e 4741static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4742 struct x86_instruction_info *info,
c4f035c6
AK		 4743 enum x86_intercept_stage stage)
4744{
2953538e 4745 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4746}
4747
0017f93a 4748static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4749 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4750{
0017f93a 4751 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4752}
4753
dd856efa
AK		 4754static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4755{
4756 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4757}
4758
4759static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4760{
4761 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4762}
4763
0225fb50 4764static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4765 .read_gpr = emulator_read_gpr,
4766 .write_gpr = emulator_write_gpr,
1871c602 4767 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4768 .write_std = kvm_write_guest_virt_system,
1871c602 4769 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4770 .read_emulated = emulator_read_emulated,
4771 .write_emulated = emulator_write_emulated,
4772 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4773 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4774 .pio_in_emulated = emulator_pio_in_emulated,
4775 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4776 .get_segment = emulator_get_segment,
4777 .set_segment = emulator_set_segment,
5951c442 4778 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4779 .get_gdt = emulator_get_gdt,
160ce1f1 4780 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4781 .set_gdt = emulator_set_gdt,
4782 .set_idt = emulator_set_idt,
52a46617
GN		 4783 .get_cr = emulator_get_cr,
4784 .set_cr = emulator_set_cr,
4cee4798 4785 .set_rflags = emulator_set_rflags,
9c537244 4786 .cpl = emulator_get_cpl,
35aa5375
GN		 4787 .get_dr = emulator_get_dr,
4788 .set_dr = emulator_set_dr,
717746e3
AK		 4789 .set_msr = emulator_set_msr,
4790 .get_msr = emulator_get_msr,
222d21aa 4791 .read_pmc = emulator_read_pmc,
6c3287f7 4792 .halt = emulator_halt,
bcaf5cc5 4793 .wbinvd = emulator_wbinvd,
d6aa1000 4794 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4795 .get_fpu = emulator_get_fpu,
4796 .put_fpu = emulator_put_fpu,
c4f035c6 4797 .intercept = emulator_intercept,
bdb42f5a 4798 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4799};
4800
95cb2295
GN		 4801static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4802{
4803 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4804 /*
4805 * an sti; sti; sequence only disable interrupts for the first
4806 * instruction. So, if the last instruction, be it emulated or
4807 * not, left the system with the INT_STI flag enabled, it
4808 * means that the last instruction is an sti. We should not
4809 * leave the flag on in this case. The same goes for mov ss
4810 */
4811 if (!(int_shadow & mask))
4812 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4813}
4814
54b8486f
GN		 4815static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4816{
4817 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4818 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4819 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4820 else if (ctxt->exception.error_code_valid)
4821 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4822 ctxt->exception.error_code);
54b8486f 4823 else
da9cb575 4824 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4825}
4826
dd856efa 4827static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4828{
1ce19dc1
BP		 4829 memset(&ctxt->opcode_len, 0,
4830 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4831
9dac77fa
AK		 4832 ctxt->fetch.start = 0;
4833 ctxt->fetch.end = 0;
4834 ctxt->io_read.pos = 0;
4835 ctxt->io_read.end = 0;
4836 ctxt->mem_read.pos = 0;
4837 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4838}
4839
8ec4722d
MG		 4840static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4841{
adf52235 4842 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4843 int cs_db, cs_l;
4844
8ec4722d
MG		 4845 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4846
adf52235
TY		 4847 ctxt->eflags = kvm_get_rflags(vcpu);
4848 ctxt->eip = kvm_rip_read(vcpu);
4849 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4850 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4851 cs_l ? X86EMUL_MODE_PROT64 :
4852 cs_db ? X86EMUL_MODE_PROT32 :
4853 X86EMUL_MODE_PROT16;
4854 ctxt->guest_mode = is_guest_mode(vcpu);
4855
dd856efa 4856 init_decode_cache(ctxt);
7ae441ea 4857 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4858}
4859
71f9833b 4860int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4861{
9d74191a 4862 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4863 int ret;
4864
4865 init_emulate_ctxt(vcpu);
4866
9dac77fa
AK		 4867 ctxt->op_bytes = 2;
4868 ctxt->ad_bytes = 2;
4869 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4870 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4871
4872 if (ret != X86EMUL_CONTINUE)
4873 return EMULATE_FAIL;
4874
9dac77fa 4875 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4876 kvm_rip_write(vcpu, ctxt->eip);
4877 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4878
4879 if (irq == NMI_VECTOR)
7460fb4a 4880 vcpu->arch.nmi_pending = 0;
63995653
MG		 4881 else
4882 vcpu->arch.interrupt.pending = false;
4883
4884 return EMULATE_DONE;
4885}
4886EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4887
6d77dbfc
GN		 4888static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4889{
fc3a9157
JR		 4890 int r = EMULATE_DONE;
4891
6d77dbfc
GN		 4892 ++vcpu->stat.insn_emulation_fail;
4893 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4894 if (!is_guest_mode(vcpu)) {
4895 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4896 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4897 vcpu->run->internal.ndata = 0;
4898 r = EMULATE_FAIL;
4899 }
6d77dbfc 4900 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4901
4902 return r;
6d77dbfc
GN		 4903}
4904
93c05d3e 4905static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4906 bool write_fault_to_shadow_pgtable,
4907 int emulation_type)
a6f177ef 4908{
95b3cf69 4909 gpa_t gpa = cr2;
8e3d9d06 4910 pfn_t pfn;
a6f177ef 4911
991eebf9
GN		 4912 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4913 return false;
4914
95b3cf69
XG		 4915 if (!vcpu->arch.mmu.direct_map) {
4916 /*
4917 * Write permission should be allowed since only
4918 * write access need to be emulated.
4919 */
4920 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4921
95b3cf69
XG		 4922 /*
4923 * If the mapping is invalid in guest, let cpu retry
4924 * it to generate fault.
4925 */
4926 if (gpa == UNMAPPED_GVA)
4927 return true;
4928 }
a6f177ef 4929
8e3d9d06
XG		 4930 /*
4931 * Do not retry the unhandleable instruction if it faults on the
4932 * readonly host memory, otherwise it will goto a infinite loop:
4933 * retry instruction -> write #PF -> emulation fail -> retry
4934 * instruction -> ...
4935 */
4936 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4937
4938 /*
4939 * If the instruction failed on the error pfn, it can not be fixed,
4940 * report the error to userspace.
4941 */
4942 if (is_error_noslot_pfn(pfn))
4943 return false;
4944
4945 kvm_release_pfn_clean(pfn);
4946
4947 /* The instructions are well-emulated on direct mmu. */
4948 if (vcpu->arch.mmu.direct_map) {
4949 unsigned int indirect_shadow_pages;
4950
4951 spin_lock(&vcpu->kvm->mmu_lock);
4952 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4953 spin_unlock(&vcpu->kvm->mmu_lock);
4954
4955 if (indirect_shadow_pages)
4956 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4957
a6f177ef 4958 return true;
8e3d9d06 4959 }
a6f177ef 4960
95b3cf69
XG		 4961 /*
4962 * if emulation was due to access to shadowed page table
4963 * and it failed try to unshadow page and re-enter the
4964 * guest to let CPU execute the instruction.
4965 */
4966 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4967
4968 /*
4969 * If the access faults on its page table, it can not
4970 * be fixed by unprotecting shadow page and it should
4971 * be reported to userspace.
4972 */
4973 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4974}
4975
1cb3f3ae
XG		 4976static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4977 unsigned long cr2, int emulation_type)
4978{
4979 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4980 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4981
4982 last_retry_eip = vcpu->arch.last_retry_eip;
4983 last_retry_addr = vcpu->arch.last_retry_addr;
4984
4985 /*
4986 * If the emulation is caused by #PF and it is non-page_table
4987 * writing instruction, it means the VM-EXIT is caused by shadow
4988 * page protected, we can zap the shadow page and retry this
4989 * instruction directly.
4990 *
4991 * Note: if the guest uses a non-page-table modifying instruction
4992 * on the PDE that points to the instruction, then we will unmap
4993 * the instruction and go to an infinite loop. So, we cache the
4994 * last retried eip and the last fault address, if we meet the eip
4995 * and the address again, we can break out of the potential infinite
4996 * loop.
4997 */
4998 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4999
5000 if (!(emulation_type & EMULTYPE_RETRY))
5001 return false;
5002
5003 if (x86_page_table_writing_insn(ctxt))
5004 return false;
5005
5006 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5007 return false;
5008
5009 vcpu->arch.last_retry_eip = ctxt->eip;
5010 vcpu->arch.last_retry_addr = cr2;
5011
5012 if (!vcpu->arch.mmu.direct_map)
5013 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5014
22368028 5015 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5016
5017 return true;
5018}
5019
716d51ab
GN		 5020static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5021static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5022
4a1e10d5
PB		 5023static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5024 unsigned long *db)
5025{
5026 u32 dr6 = 0;
5027 int i;
5028 u32 enable, rwlen;
5029
5030 enable = dr7;
5031 rwlen = dr7 >> 16;
5032 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5033 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5034 dr6 |= (1 << i);
5035 return dr6;
5036}
5037
663f4c61
PB		 5038static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5039{
5040 struct kvm_run *kvm_run = vcpu->run;
5041
5042 /*
5043 * Use the "raw" value to see if TF was passed to the processor.
5044 * Note that the new value of the flags has not been saved yet.
5045 *
5046 * This is correct even for TF set by the guest, because "the
5047 * processor will not generate this exception after the instruction
5048 * that sets the TF flag".
5049 */
5050 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5051
5052 if (unlikely(rflags & X86_EFLAGS_TF)) {
5053 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5054 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5055 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5056 kvm_run->debug.arch.exception = DB_VECTOR;
5057 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5058 *r = EMULATE_USER_EXIT;
5059 } else {
5060 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5061 /*
5062 * "Certain debug exceptions may clear bit 0-3. The
5063 * remaining contents of the DR6 register are never
5064 * cleared by the processor".
5065 */
5066 vcpu->arch.dr6 &= ~15;
5067 vcpu->arch.dr6 |= DR6_BS;
5068 kvm_queue_exception(vcpu, DB_VECTOR);
5069 }
5070 }
5071}
5072
4a1e10d5
PB		 5073static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5074{
5075 struct kvm_run *kvm_run = vcpu->run;
5076 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5077 u32 dr6 = 0;
5078
5079 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5080 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5081 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5082 vcpu->arch.guest_debug_dr7,
5083 vcpu->arch.eff_db);
5084
5085 if (dr6 != 0) {
5086 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5087 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5088 get_segment_base(vcpu, VCPU_SREG_CS);
5089
5090 kvm_run->debug.arch.exception = DB_VECTOR;
5091 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5092 *r = EMULATE_USER_EXIT;
5093 return true;
5094 }
5095 }
5096
5097 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5098 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5099 vcpu->arch.dr7,
5100 vcpu->arch.db);
5101
5102 if (dr6 != 0) {
5103 vcpu->arch.dr6 &= ~15;
5104 vcpu->arch.dr6 |= dr6;
5105 kvm_queue_exception(vcpu, DB_VECTOR);
5106 *r = EMULATE_DONE;
5107 return true;
5108 }
5109 }
5110
5111 return false;
5112}
5113
51d8b661
AP		 5114int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5115 unsigned long cr2,
dc25e89e
AP		 5116 int emulation_type,
5117 void *insn,
5118 int insn_len)
bbd9b64e 5119{
95cb2295 5120 int r;
9d74191a 5121 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5122 bool writeback = true;
93c05d3e 5123 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5124
93c05d3e
XG		 5125 /*
5126 * Clear write_fault_to_shadow_pgtable here to ensure it is
5127 * never reused.
5128 */
5129 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5130 kvm_clear_exception_queue(vcpu);
8d7d8102 5131
571008da 5132 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5133 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5134
5135 /*
5136 * We will reenter on the same instruction since
5137 * we do not set complete_userspace_io. This does not
5138 * handle watchpoints yet, those would be handled in
5139 * the emulate_ops.
5140 */
5141 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5142 return r;
5143
9d74191a
TY		 5144 ctxt->interruptibility = 0;
5145 ctxt->have_exception = false;
5146 ctxt->perm_ok = false;
bbd9b64e 5147
b51e974f 5148 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5149
9d74191a 5150 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5151
e46479f8 5152 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5153 ++vcpu->stat.insn_emulation;
1d2887e2 5154 if (r != EMULATION_OK) {
4005996e
AK		 5155 if (emulation_type & EMULTYPE_TRAP_UD)
5156 return EMULATE_FAIL;
991eebf9
GN		 5157 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5158 emulation_type))
bbd9b64e 5159 return EMULATE_DONE;
6d77dbfc
GN		 5160 if (emulation_type & EMULTYPE_SKIP)
5161 return EMULATE_FAIL;
5162 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5163 }
5164 }
5165
ba8afb6b 5166 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5167 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5168 return EMULATE_DONE;
5169 }
5170
1cb3f3ae
XG		 5171 if (retry_instruction(ctxt, cr2, emulation_type))
5172 return EMULATE_DONE;
5173
7ae441ea 5174 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5175 changes registers values during IO operation */
7ae441ea
GN		 5176 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5177 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5178 emulator_invalidate_register_cache(ctxt);
7ae441ea 5179 }
4d2179e1 5180
5cd21917 5181restart:
9d74191a 5182 r = x86_emulate_insn(ctxt);
bbd9b64e 5183
775fde86
JR		 5184 if (r == EMULATION_INTERCEPTED)
5185 return EMULATE_DONE;
5186
d2ddd1c4 5187 if (r == EMULATION_FAILED) {
991eebf9
GN		 5188 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5189 emulation_type))
c3cd7ffa
GN		 5190 return EMULATE_DONE;
5191
6d77dbfc 5192 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5193 }
5194
9d74191a 5195 if (ctxt->have_exception) {
54b8486f 5196 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5197 r = EMULATE_DONE;
5198 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5199 if (!vcpu->arch.pio.in) {
5200 /* FIXME: return into emulator if single-stepping. */
3457e419 5201 vcpu->arch.pio.count = 0;
0912c977 5202 } else {
7ae441ea 5203 writeback = false;
716d51ab
GN		 5204 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5205 }
ac0a48c3 5206 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5207 } else if (vcpu->mmio_needed) {
5208 if (!vcpu->mmio_is_write)
5209 writeback = false;
ac0a48c3 5210 r = EMULATE_USER_EXIT;
716d51ab 5211 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5212 } else if (r == EMULATION_RESTART)
5cd21917 5213 goto restart;
d2ddd1c4
GN		 5214 else
5215 r = EMULATE_DONE;
f850e2e6 5216
7ae441ea 5217 if (writeback) {
9d74191a 5218 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5219 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5220 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5221 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5222 if (r == EMULATE_DONE)
5223 kvm_vcpu_check_singlestep(vcpu, &r);
5224 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5225 } else
5226 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5227
5228 return r;
de7d789a 5229}
51d8b661 5230EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5231
cf8f70bf 5232int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5233{
cf8f70bf 5234 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5235 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5236 size, port, &val, 1);
cf8f70bf 5237 /* do not return to emulator after return from userspace */
7972995b 5238 vcpu->arch.pio.count = 0;
de7d789a
CO		 5239 return ret;
5240}
cf8f70bf 5241EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5242
8cfdc000
ZA		 5243static void tsc_bad(void *info)
5244{
0a3aee0d 5245 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5246}
5247
5248static void tsc_khz_changed(void *data)
c8076604 5249{
8cfdc000
ZA		 5250 struct cpufreq_freqs *freq = data;
5251 unsigned long khz = 0;
5252
5253 if (data)
5254 khz = freq->new;
5255 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5256 khz = cpufreq_quick_get(raw_smp_processor_id());
5257 if (!khz)
5258 khz = tsc_khz;
0a3aee0d 5259 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5260}
5261
c8076604
GH		 5262static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5263 void *data)
5264{
5265 struct cpufreq_freqs *freq = data;
5266 struct kvm *kvm;
5267 struct kvm_vcpu *vcpu;
5268 int i, send_ipi = 0;
5269
8cfdc000
ZA		 5270 /*
5271 * We allow guests to temporarily run on slowing clocks,
5272 * provided we notify them after, or to run on accelerating
5273 * clocks, provided we notify them before. Thus time never
5274 * goes backwards.
5275 *
5276 * However, we have a problem. We can't atomically update
5277 * the frequency of a given CPU from this function; it is
5278 * merely a notifier, which can be called from any CPU.
5279 * Changing the TSC frequency at arbitrary points in time
5280 * requires a recomputation of local variables related to
5281 * the TSC for each VCPU. We must flag these local variables
5282 * to be updated and be sure the update takes place with the
5283 * new frequency before any guests proceed.
5284 *
5285 * Unfortunately, the combination of hotplug CPU and frequency
5286 * change creates an intractable locking scenario; the order
5287 * of when these callouts happen is undefined with respect to
5288 * CPU hotplug, and they can race with each other. As such,
5289 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5290 * undefined; you can actually have a CPU frequency change take
5291 * place in between the computation of X and the setting of the
5292 * variable. To protect against this problem, all updates of
5293 * the per_cpu tsc_khz variable are done in an interrupt
5294 * protected IPI, and all callers wishing to update the value
5295 * must wait for a synchronous IPI to complete (which is trivial
5296 * if the caller is on the CPU already). This establishes the
5297 * necessary total order on variable updates.
5298 *
5299 * Note that because a guest time update may take place
5300 * anytime after the setting of the VCPU's request bit, the
5301 * correct TSC value must be set before the request. However,
5302 * to ensure the update actually makes it to any guest which
5303 * starts running in hardware virtualization between the set
5304 * and the acquisition of the spinlock, we must also ping the
5305 * CPU after setting the request bit.
5306 *
5307 */
5308
c8076604
GH		 5309 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5310 return 0;
5311 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5312 return 0;
8cfdc000
ZA		 5313
5314 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5315
2f303b74 5316 spin_lock(&kvm_lock);
c8076604 5317 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5318 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5319 if (vcpu->cpu != freq->cpu)
5320 continue;
c285545f 5321 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5322 if (vcpu->cpu != smp_processor_id())
8cfdc000 5323 send_ipi = 1;
c8076604
GH		 5324 }
5325 }
2f303b74 5326 spin_unlock(&kvm_lock);
c8076604
GH		 5327
5328 if (freq->old < freq->new && send_ipi) {
5329 /*
5330 * We upscale the frequency. Must make the guest
5331 * doesn't see old kvmclock values while running with
5332 * the new frequency, otherwise we risk the guest sees
5333 * time go backwards.
5334 *
5335 * In case we update the frequency for another cpu
5336 * (which might be in guest context) send an interrupt
5337 * to kick the cpu out of guest context. Next time
5338 * guest context is entered kvmclock will be updated,
5339 * so the guest will not see stale values.
5340 */
8cfdc000 5341 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5342 }
5343 return 0;
5344}
5345
5346static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5347 .notifier_call = kvmclock_cpufreq_notifier
5348};
5349
5350static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5351 unsigned long action, void *hcpu)
5352{
5353 unsigned int cpu = (unsigned long)hcpu;
5354
5355 switch (action) {
5356 case CPU_ONLINE:
5357 case CPU_DOWN_FAILED:
5358 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5359 break;
5360 case CPU_DOWN_PREPARE:
5361 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5362 break;
5363 }
5364 return NOTIFY_OK;
5365}
5366
5367static struct notifier_block kvmclock_cpu_notifier_block = {
5368 .notifier_call = kvmclock_cpu_notifier,
5369 .priority = -INT_MAX
c8076604
GH		 5370};
5371
b820cc0c
ZA		 5372static void kvm_timer_init(void)
5373{
5374 int cpu;
5375
c285545f 5376 max_tsc_khz = tsc_khz;
8cfdc000 5377 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5378 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5379#ifdef CONFIG_CPU_FREQ
5380 struct cpufreq_policy policy;
5381 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5382 cpu = get_cpu();
5383 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5384 if (policy.cpuinfo.max_freq)
5385 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5386 put_cpu();
c285545f 5387#endif
b820cc0c
ZA		 5388 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5389 CPUFREQ_TRANSITION_NOTIFIER);
5390 }
c285545f 5391 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5392 for_each_online_cpu(cpu)
5393 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5394}
5395
ff9d07a0
ZY		 5396static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5397
f5132b01 5398int kvm_is_in_guest(void)
ff9d07a0 5399{
086c9855 5400 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5401}
5402
5403static int kvm_is_user_mode(void)
5404{
5405 int user_mode = 3;
dcf46b94 5406
086c9855
AS		 5407 if (__this_cpu_read(current_vcpu))
5408 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5409
ff9d07a0
ZY		 5410 return user_mode != 0;
5411}
5412
5413static unsigned long kvm_get_guest_ip(void)
5414{
5415 unsigned long ip = 0;
dcf46b94 5416
086c9855
AS		 5417 if (__this_cpu_read(current_vcpu))
5418 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5419
ff9d07a0
ZY		 5420 return ip;
5421}
5422
5423static struct perf_guest_info_callbacks kvm_guest_cbs = {
5424 .is_in_guest = kvm_is_in_guest,
5425 .is_user_mode = kvm_is_user_mode,
5426 .get_guest_ip = kvm_get_guest_ip,
5427};
5428
5429void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5430{
086c9855 5431 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5432}
5433EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5434
5435void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5436{
086c9855 5437 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5438}
5439EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5440
ce88decf
XG		 5441static void kvm_set_mmio_spte_mask(void)
5442{
5443 u64 mask;
5444 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5445
5446 /*
5447 * Set the reserved bits and the present bit of an paging-structure
5448 * entry to generate page fault with PFER.RSV = 1.
5449 */
885032b9
XG		 5450 /* Mask the reserved physical address bits. */
5451 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5452
5453 /* Bit 62 is always reserved for 32bit host. */
5454 mask |= 0x3ull << 62;
5455
5456 /* Set the present bit. */
ce88decf
XG		 5457 mask |= 1ull;
5458
5459#ifdef CONFIG_X86_64
5460 /*
5461 * If reserved bit is not supported, clear the present bit to disable
5462 * mmio page fault.
5463 */
5464 if (maxphyaddr == 52)
5465 mask &= ~1ull;
5466#endif
5467
5468 kvm_mmu_set_mmio_spte_mask(mask);
5469}
5470
16e8d74d
MT		 5471#ifdef CONFIG_X86_64
5472static void pvclock_gtod_update_fn(struct work_struct *work)
5473{
d828199e
MT		 5474 struct kvm *kvm;
5475
5476 struct kvm_vcpu *vcpu;
5477 int i;
5478
2f303b74 5479 spin_lock(&kvm_lock);
d828199e
MT		 5480 list_for_each_entry(kvm, &vm_list, vm_list)
5481 kvm_for_each_vcpu(i, vcpu, kvm)
5482 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5483 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5484 spin_unlock(&kvm_lock);
16e8d74d
MT		 5485}
5486
5487static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5488
5489/*
5490 * Notification about pvclock gtod data update.
5491 */
5492static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5493 void *priv)
5494{
5495 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5496 struct timekeeper *tk = priv;
5497
5498 update_pvclock_gtod(tk);
5499
5500 /* disable master clock if host does not trust, or does not
5501 * use, TSC clocksource
5502 */
5503 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5504 atomic_read(&kvm_guest_has_master_clock) != 0)
5505 queue_work(system_long_wq, &pvclock_gtod_work);
5506
5507 return 0;
5508}
5509
5510static struct notifier_block pvclock_gtod_notifier = {
5511 .notifier_call = pvclock_gtod_notify,
5512};
5513#endif
5514
f8c16bba 5515int kvm_arch_init(void *opaque)
043405e1 5516{
b820cc0c 5517 int r;
6b61edf7 5518 struct kvm_x86_ops *ops = opaque;
f8c16bba 5519
f8c16bba
ZX		 5520 if (kvm_x86_ops) {
5521 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5522 r = -EEXIST;
5523 goto out;
f8c16bba
ZX		 5524 }
5525
5526 if (!ops->cpu_has_kvm_support()) {
5527 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5528 r = -EOPNOTSUPP;
5529 goto out;
f8c16bba
ZX		 5530 }
5531 if (ops->disabled_by_bios()) {
5532 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5533 r = -EOPNOTSUPP;
5534 goto out;
f8c16bba
ZX		 5535 }
5536
013f6a5d
MT		 5537 r = -ENOMEM;
5538 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5539 if (!shared_msrs) {
5540 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5541 goto out;
5542 }
5543
97db56ce
AK		 5544 r = kvm_mmu_module_init();
5545 if (r)
013f6a5d 5546 goto out_free_percpu;
97db56ce 5547
ce88decf 5548 kvm_set_mmio_spte_mask();
97db56ce
AK		 5549 kvm_init_msr_list();
5550
f8c16bba 5551 kvm_x86_ops = ops;
7b52345e 5552 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5553 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5554
b820cc0c 5555 kvm_timer_init();
c8076604 5556
ff9d07a0
ZY		 5557 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5558
2acf923e
DC		 5559 if (cpu_has_xsave)
5560 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5561
c5cc421b 5562 kvm_lapic_init();
16e8d74d
MT		 5563#ifdef CONFIG_X86_64
5564 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5565#endif
5566
f8c16bba 5567 return 0;
56c6d28a 5568
013f6a5d
MT		 5569out_free_percpu:
5570 free_percpu(shared_msrs);
56c6d28a 5571out:
56c6d28a 5572 return r;
043405e1 5573}
8776e519 5574
f8c16bba
ZX		 5575void kvm_arch_exit(void)
5576{
ff9d07a0
ZY		 5577 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5578
888d256e
JK		 5579 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5580 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5581 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5582 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5583#ifdef CONFIG_X86_64
5584 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5585#endif
f8c16bba 5586 kvm_x86_ops = NULL;
56c6d28a 5587 kvm_mmu_module_exit();
013f6a5d 5588 free_percpu(shared_msrs);
56c6d28a 5589}
f8c16bba 5590
8776e519
HB		 5591int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5592{
5593 ++vcpu->stat.halt_exits;
5594 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5595 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5596 return 1;
5597 } else {
5598 vcpu->run->exit_reason = KVM_EXIT_HLT;
5599 return 0;
5600 }
5601}
5602EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5603
55cd8e5a
GN		 5604int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5605{
5606 u64 param, ingpa, outgpa, ret;
5607 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5608 bool fast, longmode;
5609 int cs_db, cs_l;
5610
5611 /*
5612 * hypercall generates UD from non zero cpl and real mode
5613 * per HYPER-V spec
5614 */
3eeb3288 5615 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5616 kvm_queue_exception(vcpu, UD_VECTOR);
5617 return 0;
5618 }
5619
5620 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5621 longmode = is_long_mode(vcpu) && cs_l == 1;
5622
5623 if (!longmode) {
ccd46936
GN		 5624 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5625 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5626 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5627 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5628 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5629 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5630 }
5631#ifdef CONFIG_X86_64
5632 else {
5633 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5634 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5635 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5636 }
5637#endif
5638
5639 code = param & 0xffff;
5640 fast = (param >> 16) & 0x1;
5641 rep_cnt = (param >> 32) & 0xfff;
5642 rep_idx = (param >> 48) & 0xfff;
5643
5644 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5645
c25bc163
GN		 5646 switch (code) {
5647 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5648 kvm_vcpu_on_spin(vcpu);
5649 break;
5650 default:
5651 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5652 break;
5653 }
55cd8e5a
GN		 5654
5655 ret = res | (((u64)rep_done & 0xfff) << 32);
5656 if (longmode) {
5657 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5658 } else {
5659 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5660 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5661 }
5662
5663 return 1;
5664}
5665
6aef266c
SV		 5666/*
5667 * kvm_pv_kick_cpu_op: Kick a vcpu.
5668 *
5669 * @apicid - apicid of vcpu to be kicked.
5670 */
5671static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5672{
24d2166b 5673 struct kvm_lapic_irq lapic_irq;
6aef266c 5674
24d2166b
R		 5675 lapic_irq.shorthand = 0;
5676 lapic_irq.dest_mode = 0;
5677 lapic_irq.dest_id = apicid;
6aef266c 5678
24d2166b
R		 5679 lapic_irq.delivery_mode = APIC_DM_REMRD;
5680 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5681}
5682
8776e519
HB		 5683int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5684{
5685 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5686 int r = 1;
8776e519 5687
55cd8e5a
GN		 5688 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5689 return kvm_hv_hypercall(vcpu);
5690
5fdbf976
MT		 5691 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5692 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5693 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5694 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5695 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5696
229456fc 5697 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5698
8776e519
HB		 5699 if (!is_long_mode(vcpu)) {
5700 nr &= 0xFFFFFFFF;
5701 a0 &= 0xFFFFFFFF;
5702 a1 &= 0xFFFFFFFF;
5703 a2 &= 0xFFFFFFFF;
5704 a3 &= 0xFFFFFFFF;
5705 }
5706
07708c4a
JK		 5707 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5708 ret = -KVM_EPERM;
5709 goto out;
5710 }
5711
8776e519 5712 switch (nr) {
b93463aa
AK		 5713 case KVM_HC_VAPIC_POLL_IRQ:
5714 ret = 0;
5715 break;
6aef266c
SV		 5716 case KVM_HC_KICK_CPU:
5717 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5718 ret = 0;
5719 break;
8776e519
HB		 5720 default:
5721 ret = -KVM_ENOSYS;
5722 break;
5723 }
07708c4a 5724out:
5fdbf976 5725 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5726 ++vcpu->stat.hypercalls;
2f333bcb 5727 return r;
8776e519
HB		 5728}
5729EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5730
b6785def 5731static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5732{
d6aa1000 5733 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5734 char instruction[3];
5fdbf976 5735 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5736
8776e519 5737 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5738
9d74191a 5739 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5740}
5741
b6c7a5dc
HB		 5742/*
5743 * Check if userspace requested an interrupt window, and that the
5744 * interrupt window is open.
5745 *
5746 * No need to exit to userspace if we already have an interrupt queued.
5747 */
851ba692 5748static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5749{
8061823a 5750 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5751 vcpu->run->request_interrupt_window &&
5df56646 5752 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5753}
5754
851ba692 5755static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5756{
851ba692
AK		 5757 struct kvm_run *kvm_run = vcpu->run;
5758
91586a3b 5759 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5760 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5761 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5762 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5763 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5764 else
b6c7a5dc 5765 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5766 kvm_arch_interrupt_allowed(vcpu) &&
5767 !kvm_cpu_has_interrupt(vcpu) &&
5768 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5769}
5770
95ba8273
GN		 5771static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5772{
5773 int max_irr, tpr;
5774
5775 if (!kvm_x86_ops->update_cr8_intercept)
5776 return;
5777
88c808fd
AK		 5778 if (!vcpu->arch.apic)
5779 return;
5780
8db3baa2
GN		 5781 if (!vcpu->arch.apic->vapic_addr)
5782 max_irr = kvm_lapic_find_highest_irr(vcpu);
5783 else
5784 max_irr = -1;
95ba8273
GN		 5785
5786 if (max_irr != -1)
5787 max_irr >>= 4;
5788
5789 tpr = kvm_lapic_get_cr8(vcpu);
5790
5791 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5792}
5793
851ba692 5794static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5795{
5796 /* try to reinject previous events if any */
b59bb7bd 5797 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5798 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5799 vcpu->arch.exception.has_error_code,
5800 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5801 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5802 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5803 vcpu->arch.exception.error_code,
5804 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5805 return;
5806 }
5807
95ba8273
GN		 5808 if (vcpu->arch.nmi_injected) {
5809 kvm_x86_ops->set_nmi(vcpu);
5810 return;
5811 }
5812
5813 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5814 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5815 return;
5816 }
5817
5818 /* try to inject new event if pending */
5819 if (vcpu->arch.nmi_pending) {
5820 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5821 --vcpu->arch.nmi_pending;
95ba8273
GN		 5822 vcpu->arch.nmi_injected = true;
5823 kvm_x86_ops->set_nmi(vcpu);
5824 }
c7c9c56c 5825 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5826 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5827 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5828 false);
5829 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5830 }
5831 }
5832}
5833
7460fb4a
AK		 5834static void process_nmi(struct kvm_vcpu *vcpu)
5835{
5836 unsigned limit = 2;
5837
5838 /*
5839 * x86 is limited to one NMI running, and one NMI pending after it.
5840 * If an NMI is already in progress, limit further NMIs to just one.
5841 * Otherwise, allow two (and we'll inject the first one immediately).
5842 */
5843 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5844 limit = 1;
5845
5846 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5847 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5848 kvm_make_request(KVM_REQ_EVENT, vcpu);
5849}
5850
3d81bc7e 5851static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5852{
5853 u64 eoi_exit_bitmap[4];
cf9e65b7 5854 u32 tmr[8];
c7c9c56c 5855
3d81bc7e
YZ		 5856 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5857 return;
c7c9c56c
YZ		 5858
5859 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5860 memset(tmr, 0, 32);
c7c9c56c 5861
cf9e65b7 5862 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5863 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5864 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5865}
5866
9357d939
TY		 5867/*
5868 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5869 * exiting to the userspace. Otherwise, the value will be returned to the
5870 * userspace.
5871 */
851ba692 5872static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5873{
5874 int r;
6a8b1d13 5875 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5876 vcpu->run->request_interrupt_window;
730dca42 5877 bool req_immediate_exit = false;
b6c7a5dc 5878
3e007509 5879 if (vcpu->requests) {
a8eeb04a 5880 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5881 kvm_mmu_unload(vcpu);
a8eeb04a 5882 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5883 __kvm_migrate_timers(vcpu);
d828199e
MT		 5884 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5885 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5886 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5887 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5888 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5889 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5890 if (unlikely(r))
5891 goto out;
5892 }
a8eeb04a 5893 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5894 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5895 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5896 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5897 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5898 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5899 r = 0;
5900 goto out;
5901 }
a8eeb04a 5902 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5903 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5904 r = 0;
5905 goto out;
5906 }
a8eeb04a 5907 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5908 vcpu->fpu_active = 0;
5909 kvm_x86_ops->fpu_deactivate(vcpu);
5910 }
af585b92
GN		 5911 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5912 /* Page is swapped out. Do synthetic halt */
5913 vcpu->arch.apf.halted = true;
5914 r = 1;
5915 goto out;
5916 }
c9aaa895
GC		 5917 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5918 record_steal_time(vcpu);
7460fb4a
AK		 5919 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5920 process_nmi(vcpu);
f5132b01
GN		 5921 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5922 kvm_handle_pmu_event(vcpu);
5923 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5924 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5925 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5926 vcpu_scan_ioapic(vcpu);
2f52d58c 5927 }
b93463aa 5928
b463a6f7 5929 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5930 kvm_apic_accept_events(vcpu);
5931 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5932 r = 1;
5933 goto out;
5934 }
5935
b463a6f7
AK		 5936 inject_pending_event(vcpu);
5937
5938 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5939 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5940 req_immediate_exit =
5941 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5942 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5943 req_immediate_exit =
5944 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5945
5946 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5947 /*
5948 * Update architecture specific hints for APIC
5949 * virtual interrupt delivery.
5950 */
5951 if (kvm_x86_ops->hwapic_irr_update)
5952 kvm_x86_ops->hwapic_irr_update(vcpu,
5953 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5954 update_cr8_intercept(vcpu);
5955 kvm_lapic_sync_to_vapic(vcpu);
5956 }
5957 }
5958
d8368af8
AK		 5959 r = kvm_mmu_reload(vcpu);
5960 if (unlikely(r)) {
d905c069 5961 goto cancel_injection;
d8368af8
AK		 5962 }
5963
b6c7a5dc
HB		 5964 preempt_disable();
5965
5966 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5967 if (vcpu->fpu_active)
5968 kvm_load_guest_fpu(vcpu);
2acf923e 5969 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5970
6b7e2d09
XG		 5971 vcpu->mode = IN_GUEST_MODE;
5972
01b71917
MT		 5973 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5974
6b7e2d09
XG		 5975 /* We should set ->mode before check ->requests,
5976 * see the comment in make_all_cpus_request.
5977 */
01b71917 5978 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5979
d94e1dc9 5980 local_irq_disable();
32f88400 5981
6b7e2d09 5982 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5983 || need_resched() || signal_pending(current)) {
6b7e2d09 5984 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5985 smp_wmb();
6c142801
AK		 5986 local_irq_enable();
5987 preempt_enable();
01b71917 5988 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5989 r = 1;
d905c069 5990 goto cancel_injection;
6c142801
AK		 5991 }
5992
d6185f20
NHE		 5993 if (req_immediate_exit)
5994 smp_send_reschedule(vcpu->cpu);
5995
b6c7a5dc
HB		 5996 kvm_guest_enter();
5997
42dbaa5a 5998 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5999 set_debugreg(0, 7);
6000 set_debugreg(vcpu->arch.eff_db[0], 0);
6001 set_debugreg(vcpu->arch.eff_db[1], 1);
6002 set_debugreg(vcpu->arch.eff_db[2], 2);
6003 set_debugreg(vcpu->arch.eff_db[3], 3);
6004 }
b6c7a5dc 6005
229456fc 6006 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6007 kvm_x86_ops->run(vcpu);
b6c7a5dc 6008
24f1e32c
FW		 6009 /*
6010 * If the guest has used debug registers, at least dr7
6011 * will be disabled while returning to the host.
6012 * If we don't have active breakpoints in the host, we don't
6013 * care about the messed up debug address registers. But if
6014 * we have some of them active, restore the old state.
6015 */
59d8eb53 6016 if (hw_breakpoint_active())
24f1e32c 6017 hw_breakpoint_restore();
42dbaa5a 6018
886b470c
MT		 6019 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6020 native_read_tsc());
1d5f066e 6021
6b7e2d09 6022 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6023 smp_wmb();
a547c6db
YZ		 6024
6025 /* Interrupt is enabled by handle_external_intr() */
6026 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6027
6028 ++vcpu->stat.exits;
6029
6030 /*
6031 * We must have an instruction between local_irq_enable() and
6032 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6033 * the interrupt shadow. The stat.exits increment will do nicely.
6034 * But we need to prevent reordering, hence this barrier():
6035 */
6036 barrier();
6037
6038 kvm_guest_exit();
6039
6040 preempt_enable();
6041
f656ce01 6042 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6043
b6c7a5dc
HB		 6044 /*
6045 * Profile KVM exit RIPs:
6046 */
6047 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6048 unsigned long rip = kvm_rip_read(vcpu);
6049 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6050 }
6051
cc578287
ZA		 6052 if (unlikely(vcpu->arch.tsc_always_catchup))
6053 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6054
5cfb1d5a
MT		 6055 if (vcpu->arch.apic_attention)
6056 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6057
851ba692 6058 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6059 return r;
6060
6061cancel_injection:
6062 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6063 if (unlikely(vcpu->arch.apic_attention))
6064 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6065out:
6066 return r;
6067}
b6c7a5dc 6068
09cec754 6069
851ba692 6070static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6071{
6072 int r;
f656ce01 6073 struct kvm *kvm = vcpu->kvm;
d7690175 6074
f656ce01 6075 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6076
6077 r = 1;
6078 while (r > 0) {
af585b92
GN		 6079 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6080 !vcpu->arch.apf.halted)
851ba692 6081 r = vcpu_enter_guest(vcpu);
d7690175 6082 else {
f656ce01 6083 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6084 kvm_vcpu_block(vcpu);
f656ce01 6085 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6086 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6087 kvm_apic_accept_events(vcpu);
09cec754
GN		 6088 switch(vcpu->arch.mp_state) {
6089 case KVM_MP_STATE_HALTED:
6aef266c 6090 vcpu->arch.pv.pv_unhalted = false;
d7690175 6091 vcpu->arch.mp_state =
09cec754
GN		 6092 KVM_MP_STATE_RUNNABLE;
6093 case KVM_MP_STATE_RUNNABLE:
af585b92 6094 vcpu->arch.apf.halted = false;
09cec754 6095 break;
66450a21
JK		 6096 case KVM_MP_STATE_INIT_RECEIVED:
6097 break;
09cec754
GN		 6098 default:
6099 r = -EINTR;
6100 break;
6101 }
6102 }
d7690175
MT		 6103 }
6104
09cec754
GN		 6105 if (r <= 0)
6106 break;
6107
6108 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6109 if (kvm_cpu_has_pending_timer(vcpu))
6110 kvm_inject_pending_timer_irqs(vcpu);
6111
851ba692 6112 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6113 r = -EINTR;
851ba692 6114 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6115 ++vcpu->stat.request_irq_exits;
6116 }
af585b92
GN		 6117
6118 kvm_check_async_pf_completion(vcpu);
6119
09cec754
GN		 6120 if (signal_pending(current)) {
6121 r = -EINTR;
851ba692 6122 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6123 ++vcpu->stat.signal_exits;
6124 }
6125 if (need_resched()) {
f656ce01 6126 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6127 cond_resched();
f656ce01 6128 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6129 }
b6c7a5dc
HB		 6130 }
6131
f656ce01 6132 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6133
6134 return r;
6135}
6136
716d51ab
GN		 6137static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6138{
6139 int r;
6140 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6141 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6142 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6143 if (r != EMULATE_DONE)
6144 return 0;
6145 return 1;
6146}
6147
6148static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6149{
6150 BUG_ON(!vcpu->arch.pio.count);
6151
6152 return complete_emulated_io(vcpu);
6153}
6154
f78146b0
AK		 6155/*
6156 * Implements the following, as a state machine:
6157 *
6158 * read:
6159 * for each fragment
87da7e66
XG		 6160 * for each mmio piece in the fragment
6161 * write gpa, len
6162 * exit
6163 * copy data
f78146b0
AK		 6164 * execute insn
6165 *
6166 * write:
6167 * for each fragment
87da7e66
XG		 6168 * for each mmio piece in the fragment
6169 * write gpa, len
6170 * copy data
6171 * exit
f78146b0 6172 */
716d51ab 6173static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6174{
6175 struct kvm_run *run = vcpu->run;
f78146b0 6176 struct kvm_mmio_fragment *frag;
87da7e66 6177 unsigned len;
5287f194 6178
716d51ab 6179 BUG_ON(!vcpu->mmio_needed);
5287f194 6180
716d51ab 6181 /* Complete previous fragment */
87da7e66
XG		 6182 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6183 len = min(8u, frag->len);
716d51ab 6184 if (!vcpu->mmio_is_write)
87da7e66
XG		 6185 memcpy(frag->data, run->mmio.data, len);
6186
6187 if (frag->len <= 8) {
6188 /* Switch to the next fragment. */
6189 frag++;
6190 vcpu->mmio_cur_fragment++;
6191 } else {
6192 /* Go forward to the next mmio piece. */
6193 frag->data += len;
6194 frag->gpa += len;
6195 frag->len -= len;
6196 }
6197
716d51ab
GN		 6198 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6199 vcpu->mmio_needed = 0;
0912c977
PB		 6200
6201 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6202 if (vcpu->mmio_is_write)
716d51ab
GN		 6203 return 1;
6204 vcpu->mmio_read_completed = 1;
6205 return complete_emulated_io(vcpu);
6206 }
87da7e66 6207
716d51ab
GN		 6208 run->exit_reason = KVM_EXIT_MMIO;
6209 run->mmio.phys_addr = frag->gpa;
6210 if (vcpu->mmio_is_write)
87da7e66
XG		 6211 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6212 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6213 run->mmio.is_write = vcpu->mmio_is_write;
6214 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6215 return 0;
5287f194
AK		 6216}
6217
716d51ab 6218
b6c7a5dc
HB		 6219int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6220{
6221 int r;
6222 sigset_t sigsaved;
6223
e5c30142
AK		 6224 if (!tsk_used_math(current) && init_fpu(current))
6225 return -ENOMEM;
6226
ac9f6dc0
AK		 6227 if (vcpu->sigset_active)
6228 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6229
a4535290 6230 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6231 kvm_vcpu_block(vcpu);
66450a21 6232 kvm_apic_accept_events(vcpu);
d7690175 6233 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6234 r = -EAGAIN;
6235 goto out;
b6c7a5dc
HB		 6236 }
6237
b6c7a5dc 6238 /* re-sync apic's tpr */
eea1cff9
AP		 6239 if (!irqchip_in_kernel(vcpu->kvm)) {
6240 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6241 r = -EINVAL;
6242 goto out;
6243 }
6244 }
b6c7a5dc 6245
716d51ab
GN		 6246 if (unlikely(vcpu->arch.complete_userspace_io)) {
6247 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6248 vcpu->arch.complete_userspace_io = NULL;
6249 r = cui(vcpu);
6250 if (r <= 0)
6251 goto out;
6252 } else
6253 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6254
851ba692 6255 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6256
6257out:
f1d86e46 6258 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6259 if (vcpu->sigset_active)
6260 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6261
b6c7a5dc
HB		 6262 return r;
6263}
6264
6265int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6266{
7ae441ea
GN		 6267 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6268 /*
6269 * We are here if userspace calls get_regs() in the middle of
6270 * instruction emulation. Registers state needs to be copied
4a969980 6271 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6272 * that usually, but some bad designed PV devices (vmware
6273 * backdoor interface) need this to work
6274 */
dd856efa 6275 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6276 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6277 }
5fdbf976
MT		 6278 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6279 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6280 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6281 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6282 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6283 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6284 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6285 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6286#ifdef CONFIG_X86_64
5fdbf976
MT		 6287 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6288 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6289 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6290 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6291 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6292 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6293 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6294 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6295#endif
6296
5fdbf976 6297 regs->rip = kvm_rip_read(vcpu);
91586a3b 6298 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6299
b6c7a5dc
HB		 6300 return 0;
6301}
6302
6303int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6304{
7ae441ea
GN		 6305 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6306 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6307
5fdbf976
MT		 6308 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6309 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6310 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6311 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6312 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6313 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6314 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6315 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6316#ifdef CONFIG_X86_64
5fdbf976
MT		 6317 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6318 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6319 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6320 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6321 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6322 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6323 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6324 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6325#endif
6326
5fdbf976 6327 kvm_rip_write(vcpu, regs->rip);
91586a3b 6328 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6329
b4f14abd
JK		 6330 vcpu->arch.exception.pending = false;
6331
3842d135
AK		 6332 kvm_make_request(KVM_REQ_EVENT, vcpu);
6333
b6c7a5dc
HB		 6334 return 0;
6335}
6336
b6c7a5dc
HB		 6337void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6338{
6339 struct kvm_segment cs;
6340
3e6e0aab 6341 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6342 *db = cs.db;
6343 *l = cs.l;
6344}
6345EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6346
6347int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6348 struct kvm_sregs *sregs)
6349{
89a27f4d 6350 struct desc_ptr dt;
b6c7a5dc 6351
3e6e0aab
GT		 6352 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6353 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6354 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6355 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6356 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6357 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6358
3e6e0aab
GT		 6359 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6360 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6361
6362 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6363 sregs->idt.limit = dt.size;
6364 sregs->idt.base = dt.address;
b6c7a5dc 6365 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6366 sregs->gdt.limit = dt.size;
6367 sregs->gdt.base = dt.address;
b6c7a5dc 6368
4d4ec087 6369 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6370 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6371 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6372 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6373 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6374 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6375 sregs->apic_base = kvm_get_apic_base(vcpu);
6376
923c61bb 6377 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6378
36752c9b 6379 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6380 set_bit(vcpu->arch.interrupt.nr,
6381 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6382
b6c7a5dc
HB		 6383 return 0;
6384}
6385
62d9f0db
MT		 6386int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6387 struct kvm_mp_state *mp_state)
6388{
66450a21 6389 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6390 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6391 vcpu->arch.pv.pv_unhalted)
6392 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6393 else
6394 mp_state->mp_state = vcpu->arch.mp_state;
6395
62d9f0db
MT		 6396 return 0;
6397}
6398
6399int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6400 struct kvm_mp_state *mp_state)
6401{
66450a21
JK		 6402 if (!kvm_vcpu_has_lapic(vcpu) &&
6403 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6404 return -EINVAL;
6405
6406 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6407 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6408 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6409 } else
6410 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6411 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6412 return 0;
6413}
6414
7f3d35fd
KW		 6415int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6416 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6417{
9d74191a 6418 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6419 int ret;
e01c2426 6420
8ec4722d 6421 init_emulate_ctxt(vcpu);
c697518a 6422
7f3d35fd 6423 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6424 has_error_code, error_code);
c697518a 6425
c697518a 6426 if (ret)
19d04437 6427 return EMULATE_FAIL;
37817f29 6428
9d74191a
TY		 6429 kvm_rip_write(vcpu, ctxt->eip);
6430 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6431 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6432 return EMULATE_DONE;
37817f29
IE		 6433}
6434EXPORT_SYMBOL_GPL(kvm_task_switch);
6435
b6c7a5dc
HB		 6436int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6437 struct kvm_sregs *sregs)
6438{
58cb628d 6439 struct msr_data apic_base_msr;
b6c7a5dc 6440 int mmu_reset_needed = 0;
63f42e02 6441 int pending_vec, max_bits, idx;
89a27f4d 6442 struct desc_ptr dt;
b6c7a5dc 6443
6d1068b3
PM		 6444 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6445 return -EINVAL;
6446
89a27f4d
GN		 6447 dt.size = sregs->idt.limit;
6448 dt.address = sregs->idt.base;
b6c7a5dc 6449 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6450 dt.size = sregs->gdt.limit;
6451 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6452 kvm_x86_ops->set_gdt(vcpu, &dt);
6453
ad312c7c 6454 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6455 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6456 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6457 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6458
2d3ad1f4 6459 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6460
f6801dff 6461 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6462 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6463 apic_base_msr.data = sregs->apic_base;
6464 apic_base_msr.host_initiated = true;
6465 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6466
4d4ec087 6467 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6468 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6469 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6470
fc78f519 6471 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6472 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6473 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6474 kvm_update_cpuid(vcpu);
63f42e02
XG		 6475
6476 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6477 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6478 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6479 mmu_reset_needed = 1;
6480 }
63f42e02 6481 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6482
6483 if (mmu_reset_needed)
6484 kvm_mmu_reset_context(vcpu);
6485
a50abc3b 6486 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6487 pending_vec = find_first_bit(
6488 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6489 if (pending_vec < max_bits) {
66fd3f7f 6490 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6491 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6492 }
6493
3e6e0aab
GT		 6494 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6495 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6496 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6497 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6498 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6499 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6500
3e6e0aab
GT		 6501 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6502 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6503
5f0269f5
ME		 6504 update_cr8_intercept(vcpu);
6505
9c3e4aab 6506 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6507 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6508 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6509 !is_protmode(vcpu))
9c3e4aab
MT		 6510 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6511
3842d135
AK		 6512 kvm_make_request(KVM_REQ_EVENT, vcpu);
6513
b6c7a5dc
HB		 6514 return 0;
6515}
6516
d0bfb940
JK		 6517int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6518 struct kvm_guest_debug *dbg)
b6c7a5dc 6519{
355be0b9 6520 unsigned long rflags;
ae675ef0 6521 int i, r;
b6c7a5dc 6522
4f926bf2
JK		 6523 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6524 r = -EBUSY;
6525 if (vcpu->arch.exception.pending)
2122ff5e 6526 goto out;
4f926bf2
JK		 6527 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6528 kvm_queue_exception(vcpu, DB_VECTOR);
6529 else
6530 kvm_queue_exception(vcpu, BP_VECTOR);
6531 }
6532
91586a3b
JK		 6533 /*
6534 * Read rflags as long as potentially injected trace flags are still
6535 * filtered out.
6536 */
6537 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6538
6539 vcpu->guest_debug = dbg->control;
6540 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6541 vcpu->guest_debug = 0;
6542
6543 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6544 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6545 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6546 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6547 } else {
6548 for (i = 0; i < KVM_NR_DB_REGS; i++)
6549 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6550 }
c8639010 6551 kvm_update_dr7(vcpu);
ae675ef0 6552
f92653ee
JK		 6553 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6554 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6555 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6556
91586a3b
JK		 6557 /*
6558 * Trigger an rflags update that will inject or remove the trace
6559 * flags.
6560 */
6561 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6562
c8639010 6563 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6564
4f926bf2 6565 r = 0;
d0bfb940 6566
2122ff5e 6567out:
b6c7a5dc
HB		 6568
6569 return r;
6570}
6571
8b006791
ZX		 6572/*
6573 * Translate a guest virtual address to a guest physical address.
6574 */
6575int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6576 struct kvm_translation *tr)
6577{
6578 unsigned long vaddr = tr->linear_address;
6579 gpa_t gpa;
f656ce01 6580 int idx;
8b006791 6581
f656ce01 6582 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6583 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6584 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6585 tr->physical_address = gpa;
6586 tr->valid = gpa != UNMAPPED_GVA;
6587 tr->writeable = 1;
6588 tr->usermode = 0;
8b006791
ZX		 6589
6590 return 0;
6591}
6592
d0752060
HB		 6593int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6594{
98918833
SY		 6595 struct i387_fxsave_struct *fxsave =
6596 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6597
d0752060
HB		 6598 memcpy(fpu->fpr, fxsave->st_space, 128);
6599 fpu->fcw = fxsave->cwd;
6600 fpu->fsw = fxsave->swd;
6601 fpu->ftwx = fxsave->twd;
6602 fpu->last_opcode = fxsave->fop;
6603 fpu->last_ip = fxsave->rip;
6604 fpu->last_dp = fxsave->rdp;
6605 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6606
d0752060
HB		 6607 return 0;
6608}
6609
6610int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6611{
98918833
SY		 6612 struct i387_fxsave_struct *fxsave =
6613 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6614
d0752060
HB		 6615 memcpy(fxsave->st_space, fpu->fpr, 128);
6616 fxsave->cwd = fpu->fcw;
6617 fxsave->swd = fpu->fsw;
6618 fxsave->twd = fpu->ftwx;
6619 fxsave->fop = fpu->last_opcode;
6620 fxsave->rip = fpu->last_ip;
6621 fxsave->rdp = fpu->last_dp;
6622 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6623
d0752060
HB		 6624 return 0;
6625}
6626
10ab25cd 6627int fx_init(struct kvm_vcpu *vcpu)
d0752060 6628{
10ab25cd
JK		 6629 int err;
6630
6631 err = fpu_alloc(&vcpu->arch.guest_fpu);
6632 if (err)
6633 return err;
6634
98918833 6635 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6636
2acf923e
DC		 6637 /*
6638 * Ensure guest xcr0 is valid for loading
6639 */
6640 vcpu->arch.xcr0 = XSTATE_FP;
6641
ad312c7c 6642 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6643
6644 return 0;
d0752060
HB		 6645}
6646EXPORT_SYMBOL_GPL(fx_init);
6647
98918833
SY		 6648static void fx_free(struct kvm_vcpu *vcpu)
6649{
6650 fpu_free(&vcpu->arch.guest_fpu);
6651}
6652
d0752060
HB		 6653void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6654{
2608d7a1 6655 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6656 return;
6657
2acf923e
DC		 6658 /*
6659 * Restore all possible states in the guest,
6660 * and assume host would use all available bits.
6661 * Guest xcr0 would be loaded later.
6662 */
6663 kvm_put_guest_xcr0(vcpu);
d0752060 6664 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6665 __kernel_fpu_begin();
98918833 6666 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6667 trace_kvm_fpu(1);
d0752060 6668}
d0752060
HB		 6669
6670void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6671{
2acf923e
DC		 6672 kvm_put_guest_xcr0(vcpu);
6673
d0752060
HB		 6674 if (!vcpu->guest_fpu_loaded)
6675 return;
6676
6677 vcpu->guest_fpu_loaded = 0;
98918833 6678 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6679 __kernel_fpu_end();
f096ed85 6680 ++vcpu->stat.fpu_reload;
a8eeb04a 6681 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6682 trace_kvm_fpu(0);
d0752060 6683}
e9b11c17
ZX		 6684
6685void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6686{
12f9a48f 6687 kvmclock_reset(vcpu);
7f1ea208 6688
f5f48ee1 6689 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6690 fx_free(vcpu);
e9b11c17
ZX		 6691 kvm_x86_ops->vcpu_free(vcpu);
6692}
6693
6694struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6695 unsigned int id)
6696{
6755bae8
ZA		 6697 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6698 printk_once(KERN_WARNING
6699 "kvm: SMP vm created on host with unstable TSC; "
6700 "guest TSC will not be reliable\n");
26e5215f
AK		 6701 return kvm_x86_ops->vcpu_create(kvm, id);
6702}
e9b11c17 6703
26e5215f
AK		 6704int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6705{
6706 int r;
e9b11c17 6707
0bed3b56 6708 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6709 r = vcpu_load(vcpu);
6710 if (r)
6711 return r;
57f252f2 6712 kvm_vcpu_reset(vcpu);
8a3c1a33 6713 kvm_mmu_setup(vcpu);
e9b11c17 6714 vcpu_put(vcpu);
e9b11c17 6715
26e5215f 6716 return r;
e9b11c17
ZX		 6717}
6718
42897d86
MT		 6719int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6720{
6721 int r;
8fe8ab46 6722 struct msr_data msr;
42897d86
MT		 6723
6724 r = vcpu_load(vcpu);
6725 if (r)
6726 return r;
8fe8ab46
WA		 6727 msr.data = 0x0;
6728 msr.index = MSR_IA32_TSC;
6729 msr.host_initiated = true;
6730 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6731 vcpu_put(vcpu);
6732
6733 return r;
6734}
6735
d40ccc62 6736void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6737{
9fc77441 6738 int r;
344d9588
GN		 6739 vcpu->arch.apf.msr_val = 0;
6740
9fc77441
MT		 6741 r = vcpu_load(vcpu);
6742 BUG_ON(r);
e9b11c17
ZX		 6743 kvm_mmu_unload(vcpu);
6744 vcpu_put(vcpu);
6745
98918833 6746 fx_free(vcpu);
e9b11c17
ZX		 6747 kvm_x86_ops->vcpu_free(vcpu);
6748}
6749
66450a21 6750void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6751{
7460fb4a
AK		 6752 atomic_set(&vcpu->arch.nmi_queued, 0);
6753 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6754 vcpu->arch.nmi_injected = false;
6755
42dbaa5a
JK		 6756 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6757 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6758 kvm_update_dr6(vcpu);
42dbaa5a 6759 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6760 kvm_update_dr7(vcpu);
42dbaa5a 6761
3842d135 6762 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6763 vcpu->arch.apf.msr_val = 0;
c9aaa895 6764 vcpu->arch.st.msr_val = 0;
3842d135 6765
12f9a48f
GC		 6766 kvmclock_reset(vcpu);
6767
af585b92
GN		 6768 kvm_clear_async_pf_completion_queue(vcpu);
6769 kvm_async_pf_hash_reset(vcpu);
6770 vcpu->arch.apf.halted = false;
3842d135 6771
f5132b01
GN		 6772 kvm_pmu_reset(vcpu);
6773
66f7b72e
JS		 6774 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6775 vcpu->arch.regs_avail = ~0;
6776 vcpu->arch.regs_dirty = ~0;
6777
57f252f2 6778 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6779}
6780
66450a21
JK		 6781void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6782{
6783 struct kvm_segment cs;
6784
6785 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6786 cs.selector = vector << 8;
6787 cs.base = vector << 12;
6788 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6789 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6790}
6791
10474ae8 6792int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6793{
ca84d1a2
ZA		 6794 struct kvm *kvm;
6795 struct kvm_vcpu *vcpu;
6796 int i;
0dd6a6ed
ZA		 6797 int ret;
6798 u64 local_tsc;
6799 u64 max_tsc = 0;
6800 bool stable, backwards_tsc = false;
18863bdd
AK		 6801
6802 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6803 ret = kvm_x86_ops->hardware_enable(garbage);
6804 if (ret != 0)
6805 return ret;
6806
6807 local_tsc = native_read_tsc();
6808 stable = !check_tsc_unstable();
6809 list_for_each_entry(kvm, &vm_list, vm_list) {
6810 kvm_for_each_vcpu(i, vcpu, kvm) {
6811 if (!stable && vcpu->cpu == smp_processor_id())
6812 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6813 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6814 backwards_tsc = true;
6815 if (vcpu->arch.last_host_tsc > max_tsc)
6816 max_tsc = vcpu->arch.last_host_tsc;
6817 }
6818 }
6819 }
6820
6821 /*
6822 * Sometimes, even reliable TSCs go backwards. This happens on
6823 * platforms that reset TSC during suspend or hibernate actions, but
6824 * maintain synchronization. We must compensate. Fortunately, we can
6825 * detect that condition here, which happens early in CPU bringup,
6826 * before any KVM threads can be running. Unfortunately, we can't
6827 * bring the TSCs fully up to date with real time, as we aren't yet far
6828 * enough into CPU bringup that we know how much real time has actually
6829 * elapsed; our helper function, get_kernel_ns() will be using boot
6830 * variables that haven't been updated yet.
6831 *
6832 * So we simply find the maximum observed TSC above, then record the
6833 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6834 * the adjustment will be applied. Note that we accumulate
6835 * adjustments, in case multiple suspend cycles happen before some VCPU
6836 * gets a chance to run again. In the event that no KVM threads get a
6837 * chance to run, we will miss the entire elapsed period, as we'll have
6838 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6839 * loose cycle time. This isn't too big a deal, since the loss will be
6840 * uniform across all VCPUs (not to mention the scenario is extremely
6841 * unlikely). It is possible that a second hibernate recovery happens
6842 * much faster than a first, causing the observed TSC here to be
6843 * smaller; this would require additional padding adjustment, which is
6844 * why we set last_host_tsc to the local tsc observed here.
6845 *
6846 * N.B. - this code below runs only on platforms with reliable TSC,
6847 * as that is the only way backwards_tsc is set above. Also note
6848 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6849 * have the same delta_cyc adjustment applied if backwards_tsc
6850 * is detected. Note further, this adjustment is only done once,
6851 * as we reset last_host_tsc on all VCPUs to stop this from being
6852 * called multiple times (one for each physical CPU bringup).
6853 *
4a969980 6854 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6855 * will be compensated by the logic in vcpu_load, which sets the TSC to
6856 * catchup mode. This will catchup all VCPUs to real time, but cannot
6857 * guarantee that they stay in perfect synchronization.
6858 */
6859 if (backwards_tsc) {
6860 u64 delta_cyc = max_tsc - local_tsc;
6861 list_for_each_entry(kvm, &vm_list, vm_list) {
6862 kvm_for_each_vcpu(i, vcpu, kvm) {
6863 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6864 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6865 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6866 &vcpu->requests);
0dd6a6ed
ZA		 6867 }
6868
6869 /*
6870 * We have to disable TSC offset matching.. if you were
6871 * booting a VM while issuing an S4 host suspend....
6872 * you may have some problem. Solving this issue is
6873 * left as an exercise to the reader.
6874 */
6875 kvm->arch.last_tsc_nsec = 0;
6876 kvm->arch.last_tsc_write = 0;
6877 }
6878
6879 }
6880 return 0;
e9b11c17
ZX		 6881}
6882
6883void kvm_arch_hardware_disable(void *garbage)
6884{
6885 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6886 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6887}
6888
6889int kvm_arch_hardware_setup(void)
6890{
6891 return kvm_x86_ops->hardware_setup();
6892}
6893
6894void kvm_arch_hardware_unsetup(void)
6895{
6896 kvm_x86_ops->hardware_unsetup();
6897}
6898
6899void kvm_arch_check_processor_compat(void *rtn)
6900{
6901 kvm_x86_ops->check_processor_compatibility(rtn);
6902}
6903
3e515705
AK		 6904bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6905{
6906 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6907}
6908
54e9818f
GN		 6909struct static_key kvm_no_apic_vcpu __read_mostly;
6910
e9b11c17
ZX		 6911int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6912{
6913 struct page *page;
6914 struct kvm *kvm;
6915 int r;
6916
6917 BUG_ON(vcpu->kvm == NULL);
6918 kvm = vcpu->kvm;
6919
6aef266c 6920 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6921 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6922 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6923 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6924 else
a4535290 6925 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6926
6927 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6928 if (!page) {
6929 r = -ENOMEM;
6930 goto fail;
6931 }
ad312c7c 6932 vcpu->arch.pio_data = page_address(page);
e9b11c17 6933
cc578287 6934 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6935
e9b11c17
ZX		 6936 r = kvm_mmu_create(vcpu);
6937 if (r < 0)
6938 goto fail_free_pio_data;
6939
6940 if (irqchip_in_kernel(kvm)) {
6941 r = kvm_create_lapic(vcpu);
6942 if (r < 0)
6943 goto fail_mmu_destroy;
54e9818f
GN		 6944 } else
6945 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6946
890ca9ae
HY		 6947 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6948 GFP_KERNEL);
6949 if (!vcpu->arch.mce_banks) {
6950 r = -ENOMEM;
443c39bc 6951 goto fail_free_lapic;
890ca9ae
HY		 6952 }
6953 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6954
f1797359
WY		 6955 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6956 r = -ENOMEM;
f5f48ee1 6957 goto fail_free_mce_banks;
f1797359 6958 }
f5f48ee1 6959
66f7b72e
JS		 6960 r = fx_init(vcpu);
6961 if (r)
6962 goto fail_free_wbinvd_dirty_mask;
6963
ba904635 6964 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6965 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6966
6967 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6968 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6969
af585b92 6970 kvm_async_pf_hash_reset(vcpu);
f5132b01 6971 kvm_pmu_init(vcpu);
af585b92 6972
e9b11c17 6973 return 0;
66f7b72e
JS		 6974fail_free_wbinvd_dirty_mask:
6975 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6976fail_free_mce_banks:
6977 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6978fail_free_lapic:
6979 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6980fail_mmu_destroy:
6981 kvm_mmu_destroy(vcpu);
6982fail_free_pio_data:
ad312c7c 6983 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6984fail:
6985 return r;
6986}
6987
6988void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6989{
f656ce01
MT		 6990 int idx;
6991
f5132b01 6992 kvm_pmu_destroy(vcpu);
36cb93fd 6993 kfree(vcpu->arch.mce_banks);
e9b11c17 6994 kvm_free_lapic(vcpu);
f656ce01 6995 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6996 kvm_mmu_destroy(vcpu);
f656ce01 6997 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6998 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6999 if (!irqchip_in_kernel(vcpu->kvm))
7000 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7001}
d19a9cd2 7002
e08b9637 7003int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7004{
e08b9637
CO		 7005 if (type)
7006 return -EINVAL;
7007
f05e70ac 7008 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7009 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7010 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7011 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7012
5550af4d
SY		 7013 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7014 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7015 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7016 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7017 &kvm->arch.irq_sources_bitmap);
5550af4d 7018
038f8c11 7019 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7020 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7021 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7022
7023 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7024
d89f5eff 7025 return 0;
d19a9cd2
ZX		 7026}
7027
7028static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7029{
9fc77441
MT		 7030 int r;
7031 r = vcpu_load(vcpu);
7032 BUG_ON(r);
d19a9cd2
ZX		 7033 kvm_mmu_unload(vcpu);
7034 vcpu_put(vcpu);
7035}
7036
7037static void kvm_free_vcpus(struct kvm *kvm)
7038{
7039 unsigned int i;
988a2cae 7040 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7041
7042 /*
7043 * Unpin any mmu pages first.
7044 */
af585b92
GN		 7045 kvm_for_each_vcpu(i, vcpu, kvm) {
7046 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7047 kvm_unload_vcpu_mmu(vcpu);
af585b92 7048 }
988a2cae
GN		 7049 kvm_for_each_vcpu(i, vcpu, kvm)
7050 kvm_arch_vcpu_free(vcpu);
7051
7052 mutex_lock(&kvm->lock);
7053 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7054 kvm->vcpus[i] = NULL;
d19a9cd2 7055
988a2cae
GN		 7056 atomic_set(&kvm->online_vcpus, 0);
7057 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7058}
7059
ad8ba2cd
SY		 7060void kvm_arch_sync_events(struct kvm *kvm)
7061{
ba4cef31 7062 kvm_free_all_assigned_devices(kvm);
aea924f6 7063 kvm_free_pit(kvm);
ad8ba2cd
SY		 7064}
7065
d19a9cd2
ZX		 7066void kvm_arch_destroy_vm(struct kvm *kvm)
7067{
27469d29
AH		 7068 if (current->mm == kvm->mm) {
7069 /*
7070 * Free memory regions allocated on behalf of userspace,
7071 * unless the the memory map has changed due to process exit
7072 * or fd copying.
7073 */
7074 struct kvm_userspace_memory_region mem;
7075 memset(&mem, 0, sizeof(mem));
7076 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7077 kvm_set_memory_region(kvm, &mem);
7078
7079 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7080 kvm_set_memory_region(kvm, &mem);
7081
7082 mem.slot = TSS_PRIVATE_MEMSLOT;
7083 kvm_set_memory_region(kvm, &mem);
7084 }
6eb55818 7085 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7086 kfree(kvm->arch.vpic);
7087 kfree(kvm->arch.vioapic);
d19a9cd2 7088 kvm_free_vcpus(kvm);
3d45830c
AK		 7089 if (kvm->arch.apic_access_page)
7090 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7091 if (kvm->arch.ept_identity_pagetable)
7092 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7093 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7094}
0de10343 7095
5587027c 7096void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7097 struct kvm_memory_slot *dont)
7098{
7099 int i;
7100
d89cc617
TY		 7101 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7102 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7103 kvm_kvfree(free->arch.rmap[i]);
7104 free->arch.rmap[i] = NULL;
77d11309 7105 }
d89cc617
TY		 7106 if (i == 0)
7107 continue;
7108
7109 if (!dont || free->arch.lpage_info[i - 1] !=
7110 dont->arch.lpage_info[i - 1]) {
7111 kvm_kvfree(free->arch.lpage_info[i - 1]);
7112 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7113 }
7114 }
7115}
7116
5587027c
AK		 7117int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7118 unsigned long npages)
db3fe4eb
TY		 7119{
7120 int i;
7121
d89cc617 7122 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7123 unsigned long ugfn;
7124 int lpages;
d89cc617 7125 int level = i + 1;
db3fe4eb
TY		 7126
7127 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7128 slot->base_gfn, level) + 1;
7129
d89cc617
TY		 7130 slot->arch.rmap[i] =
7131 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7132 if (!slot->arch.rmap[i])
77d11309 7133 goto out_free;
d89cc617
TY		 7134 if (i == 0)
7135 continue;
77d11309 7136
d89cc617
TY		 7137 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7138 sizeof(*slot->arch.lpage_info[i - 1]));
7139 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7140 goto out_free;
7141
7142 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7143 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7144 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7145 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7146 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7147 /*
7148 * If the gfn and userspace address are not aligned wrt each
7149 * other, or if explicitly asked to, disable large page
7150 * support for this slot
7151 */
7152 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7153 !kvm_largepages_enabled()) {
7154 unsigned long j;
7155
7156 for (j = 0; j < lpages; ++j)
d89cc617 7157 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7158 }
7159 }
7160
7161 return 0;
7162
7163out_free:
d89cc617
TY		 7164 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7165 kvm_kvfree(slot->arch.rmap[i]);
7166 slot->arch.rmap[i] = NULL;
7167 if (i == 0)
7168 continue;
7169
7170 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7171 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7172 }
7173 return -ENOMEM;
7174}
7175
e59dbe09
TY		 7176void kvm_arch_memslots_updated(struct kvm *kvm)
7177{
e6dff7d1
TY		 7178 /*
7179 * memslots->generation has been incremented.
7180 * mmio generation may have reached its maximum value.
7181 */
7182 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7183}
7184
f7784b8e
MT		 7185int kvm_arch_prepare_memory_region(struct kvm *kvm,
7186 struct kvm_memory_slot *memslot,
f7784b8e 7187 struct kvm_userspace_memory_region *mem,
7b6195a9 7188 enum kvm_mr_change change)
0de10343 7189{
7a905b14
TY		 7190 /*
7191 * Only private memory slots need to be mapped here since
7192 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7193 */
7b6195a9 7194 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7195 unsigned long userspace_addr;
604b38ac 7196
7a905b14
TY		 7197 /*
7198 * MAP_SHARED to prevent internal slot pages from being moved
7199 * by fork()/COW.
7200 */
7b6195a9 7201 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7202 PROT_READ | PROT_WRITE,
7203 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7204
7a905b14
TY		 7205 if (IS_ERR((void *)userspace_addr))
7206 return PTR_ERR((void *)userspace_addr);
604b38ac 7207
7a905b14 7208 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7209 }
7210
f7784b8e
MT		 7211 return 0;
7212}
7213
7214void kvm_arch_commit_memory_region(struct kvm *kvm,
7215 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7216 const struct kvm_memory_slot *old,
7217 enum kvm_mr_change change)
f7784b8e
MT		 7218{
7219
8482644a 7220 int nr_mmu_pages = 0;
f7784b8e 7221
8482644a 7222 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7223 int ret;
7224
8482644a
TY		 7225 ret = vm_munmap(old->userspace_addr,
7226 old->npages * PAGE_SIZE);
f7784b8e
MT		 7227 if (ret < 0)
7228 printk(KERN_WARNING
7229 "kvm_vm_ioctl_set_memory_region: "
7230 "failed to munmap memory\n");
7231 }
7232
48c0e4e9
XG		 7233 if (!kvm->arch.n_requested_mmu_pages)
7234 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7235
48c0e4e9 7236 if (nr_mmu_pages)
0de10343 7237 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7238 /*
7239 * Write protect all pages for dirty logging.
7240 * Existing largepage mappings are destroyed here and new ones will
7241 * not be created until the end of the logging.
7242 */
8482644a 7243 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7244 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7245}
1d737c8a 7246
2df72e9b 7247void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7248{
6ca18b69 7249 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7250}
7251
2df72e9b
MT		 7252void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7253 struct kvm_memory_slot *slot)
7254{
6ca18b69 7255 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7256}
7257
1d737c8a
ZX		 7258int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7259{
af585b92
GN		 7260 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7261 !vcpu->arch.apf.halted)
7262 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7263 || kvm_apic_has_events(vcpu)
6aef266c 7264 || vcpu->arch.pv.pv_unhalted
7460fb4a 7265 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7266 (kvm_arch_interrupt_allowed(vcpu) &&
7267 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7268}
5736199a 7269
b6d33834 7270int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7271{
b6d33834 7272 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7273}
78646121
GN		 7274
7275int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7276{
7277 return kvm_x86_ops->interrupt_allowed(vcpu);
7278}
229456fc 7279
f92653ee
JK		 7280bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7281{
7282 unsigned long current_rip = kvm_rip_read(vcpu) +
7283 get_segment_base(vcpu, VCPU_SREG_CS);
7284
7285 return current_rip == linear_rip;
7286}
7287EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7288
94fe45da
JK		 7289unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7290{
7291 unsigned long rflags;
7292
7293 rflags = kvm_x86_ops->get_rflags(vcpu);
7294 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7295 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7296 return rflags;
7297}
7298EXPORT_SYMBOL_GPL(kvm_get_rflags);
7299
7300void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7301{
7302 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7303 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7304 rflags |= X86_EFLAGS_TF;
94fe45da 7305 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7306 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7307}
7308EXPORT_SYMBOL_GPL(kvm_set_rflags);
7309
56028d08
GN		 7310void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7311{
7312 int r;
7313
fb67e14f 7314 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7315 work->wakeup_all)
56028d08
GN		 7316 return;
7317
7318 r = kvm_mmu_reload(vcpu);
7319 if (unlikely(r))
7320 return;
7321
fb67e14f
XG		 7322 if (!vcpu->arch.mmu.direct_map &&
7323 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7324 return;
7325
56028d08
GN		 7326 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7327}
7328
af585b92
GN		 7329static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7330{
7331 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7332}
7333
7334static inline u32 kvm_async_pf_next_probe(u32 key)
7335{
7336 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7337}
7338
7339static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7340{
7341 u32 key = kvm_async_pf_hash_fn(gfn);
7342
7343 while (vcpu->arch.apf.gfns[key] != ~0)
7344 key = kvm_async_pf_next_probe(key);
7345
7346 vcpu->arch.apf.gfns[key] = gfn;
7347}
7348
7349static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7350{
7351 int i;
7352 u32 key = kvm_async_pf_hash_fn(gfn);
7353
7354 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7355 (vcpu->arch.apf.gfns[key] != gfn &&
7356 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7357 key = kvm_async_pf_next_probe(key);
7358
7359 return key;
7360}
7361
7362bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7363{
7364 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7365}
7366
7367static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7368{
7369 u32 i, j, k;
7370
7371 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7372 while (true) {
7373 vcpu->arch.apf.gfns[i] = ~0;
7374 do {
7375 j = kvm_async_pf_next_probe(j);
7376 if (vcpu->arch.apf.gfns[j] == ~0)
7377 return;
7378 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7379 /*
7380 * k lies cyclically in ]i,j]
7381 * | i.k.j |
7382 * |....j i.k.| or |.k..j i...|
7383 */
7384 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7385 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7386 i = j;
7387 }
7388}
7389
7c90705b
GN		 7390static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7391{
7392
7393 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7394 sizeof(val));
7395}
7396
af585b92
GN		 7397void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7398 struct kvm_async_pf *work)
7399{
6389ee94
AK		 7400 struct x86_exception fault;
7401
7c90705b 7402 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7403 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7404
7405 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7406 (vcpu->arch.apf.send_user_only &&
7407 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7408 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7409 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7410 fault.vector = PF_VECTOR;
7411 fault.error_code_valid = true;
7412 fault.error_code = 0;
7413 fault.nested_page_fault = false;
7414 fault.address = work->arch.token;
7415 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7416 }
af585b92
GN		 7417}
7418
7419void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7420 struct kvm_async_pf *work)
7421{
6389ee94
AK		 7422 struct x86_exception fault;
7423
7c90705b 7424 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7425 if (work->wakeup_all)
7c90705b
GN		 7426 work->arch.token = ~0; /* broadcast wakeup */
7427 else
7428 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7429
7430 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7431 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7432 fault.vector = PF_VECTOR;
7433 fault.error_code_valid = true;
7434 fault.error_code = 0;
7435 fault.nested_page_fault = false;
7436 fault.address = work->arch.token;
7437 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7438 }
e6d53e3b 7439 vcpu->arch.apf.halted = false;
a4fa1635 7440 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7441}
7442
7443bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7444{
7445 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7446 return true;
7447 else
7448 return !kvm_event_needs_reinjection(vcpu) &&
7449 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7450}
7451
e0f0bbc5
AW		 7452void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7453{
7454 atomic_inc(&kvm->arch.noncoherent_dma_count);
7455}
7456EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7457
7458void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7459{
7460 atomic_dec(&kvm->arch.noncoherent_dma_count);
7461}
7462EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7463
7464bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7465{
7466 return atomic_read(&kvm->arch.noncoherent_dma_count);
7467}
7468EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7469
229456fc
MT		 7470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7472EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7473EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7474EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7475EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7476EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7477EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7478EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7479EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7480EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7481EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7482EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux kernel - Deliverables
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