Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
9611c187 | 9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
10 | * |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
14 | * Amit Shah <amit.shah@qumranet.com> |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
16 | * |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
edf88417 | 22 | #include <linux/kvm_host.h> |
313a3dc7 | 23 | #include "irq.h" |
1d737c8a | 24 | #include "mmu.h" |
7837699f | 25 | #include "i8254.h" |
37817f29 | 26 | #include "tss.h" |
5fdbf976 | 27 | #include "kvm_cache_regs.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
c9eab58f | 30 | #include "assigned-dev.h" |
313a3dc7 | 31 | |
18068523 | 32 | #include <linux/clocksource.h> |
4d5c5d0f | 33 | #include <linux/interrupt.h> |
313a3dc7 CO |
34 | #include <linux/kvm.h> |
35 | #include <linux/fs.h> | |
36 | #include <linux/vmalloc.h> | |
5fb76f9b | 37 | #include <linux/module.h> |
0de10343 | 38 | #include <linux/mman.h> |
2bacc55c | 39 | #include <linux/highmem.h> |
19de40a8 | 40 | #include <linux/iommu.h> |
62c476c7 | 41 | #include <linux/intel-iommu.h> |
c8076604 | 42 | #include <linux/cpufreq.h> |
18863bdd | 43 | #include <linux/user-return-notifier.h> |
a983fb23 | 44 | #include <linux/srcu.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
ff9d07a0 | 46 | #include <linux/perf_event.h> |
7bee342a | 47 | #include <linux/uaccess.h> |
af585b92 | 48 | #include <linux/hash.h> |
a1b60c1c | 49 | #include <linux/pci.h> |
16e8d74d MT |
50 | #include <linux/timekeeper_internal.h> |
51 | #include <linux/pvclock_gtod.h> | |
aec51dc4 | 52 | #include <trace/events/kvm.h> |
2ed152af | 53 | |
229456fc MT |
54 | #define CREATE_TRACE_POINTS |
55 | #include "trace.h" | |
043405e1 | 56 | |
24f1e32c | 57 | #include <asm/debugreg.h> |
d825ed0a | 58 | #include <asm/msr.h> |
a5f61300 | 59 | #include <asm/desc.h> |
0bed3b56 | 60 | #include <asm/mtrr.h> |
890ca9ae | 61 | #include <asm/mce.h> |
7cf30855 | 62 | #include <asm/i387.h> |
1361b83a | 63 | #include <asm/fpu-internal.h> /* Ugh! */ |
98918833 | 64 | #include <asm/xcr.h> |
1d5f066e | 65 | #include <asm/pvclock.h> |
217fc9cf | 66 | #include <asm/div64.h> |
043405e1 | 67 | |
313a3dc7 | 68 | #define MAX_IO_MSRS 256 |
890ca9ae | 69 | #define KVM_MAX_MCE_BANKS 32 |
5854dbca | 70 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) |
890ca9ae | 71 | |
0f65dd70 AK |
72 | #define emul_to_vcpu(ctxt) \ |
73 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
74 | ||
50a37eb4 JR |
75 | /* EFER defaults: |
76 | * - enable syscall per default because its emulated by KVM | |
77 | * - enable LME and LMA per default on 64 bit KVM | |
78 | */ | |
79 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
80 | static |
81 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 82 | #else |
1260edbe | 83 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 84 | #endif |
313a3dc7 | 85 | |
ba1389b7 AK |
86 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
87 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 88 | |
cb142eb7 | 89 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 90 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 91 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
674eea0f | 92 | |
97896d04 | 93 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 94 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 95 | |
476bc001 RR |
96 | static bool ignore_msrs = 0; |
97 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
ed85c068 | 98 | |
9ed96e87 MT |
99 | unsigned int min_timer_period_us = 500; |
100 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
101 | ||
630994b3 MT |
102 | static bool __read_mostly kvmclock_periodic_sync = true; |
103 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
104 | ||
92a1f12d JR |
105 | bool kvm_has_tsc_control; |
106 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
107 | u32 kvm_max_guest_tsc_khz; | |
108 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
109 | ||
cc578287 ZA |
110 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
111 | static u32 tsc_tolerance_ppm = 250; | |
112 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
113 | ||
d0659d94 MT |
114 | /* lapic timer advance (tscdeadline mode only) in nanoseconds */ |
115 | unsigned int lapic_timer_advance_ns = 0; | |
116 | module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); | |
117 | ||
16a96021 MT |
118 | static bool backwards_tsc_observed = false; |
119 | ||
18863bdd AK |
120 | #define KVM_NR_SHARED_MSRS 16 |
121 | ||
122 | struct kvm_shared_msrs_global { | |
123 | int nr; | |
2bf78fa7 | 124 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
125 | }; |
126 | ||
127 | struct kvm_shared_msrs { | |
128 | struct user_return_notifier urn; | |
129 | bool registered; | |
2bf78fa7 SY |
130 | struct kvm_shared_msr_values { |
131 | u64 host; | |
132 | u64 curr; | |
133 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
134 | }; |
135 | ||
136 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 137 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 138 | |
417bc304 | 139 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
140 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
141 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
142 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
143 | { "invlpg", VCPU_STAT(invlpg) }, | |
144 | { "exits", VCPU_STAT(exits) }, | |
145 | { "io_exits", VCPU_STAT(io_exits) }, | |
146 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
147 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
148 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 149 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 150 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 151 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
ba1389b7 | 152 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 153 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
154 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
155 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
156 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
157 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
158 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
159 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
160 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 161 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 162 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
163 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
164 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
165 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
166 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
167 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
168 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 169 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 170 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 171 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 172 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
173 | { NULL } |
174 | }; | |
175 | ||
2acf923e DC |
176 | u64 __read_mostly host_xcr0; |
177 | ||
b6785def | 178 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 179 | |
af585b92 GN |
180 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
181 | { | |
182 | int i; | |
183 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
184 | vcpu->arch.apf.gfns[i] = ~0; | |
185 | } | |
186 | ||
18863bdd AK |
187 | static void kvm_on_user_return(struct user_return_notifier *urn) |
188 | { | |
189 | unsigned slot; | |
18863bdd AK |
190 | struct kvm_shared_msrs *locals |
191 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 192 | struct kvm_shared_msr_values *values; |
18863bdd AK |
193 | |
194 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
195 | values = &locals->values[slot]; |
196 | if (values->host != values->curr) { | |
197 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
198 | values->curr = values->host; | |
18863bdd AK |
199 | } |
200 | } | |
201 | locals->registered = false; | |
202 | user_return_notifier_unregister(urn); | |
203 | } | |
204 | ||
2bf78fa7 | 205 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 206 | { |
18863bdd | 207 | u64 value; |
013f6a5d MT |
208 | unsigned int cpu = smp_processor_id(); |
209 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 210 | |
2bf78fa7 SY |
211 | /* only read, and nobody should modify it at this time, |
212 | * so don't need lock */ | |
213 | if (slot >= shared_msrs_global.nr) { | |
214 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
215 | return; | |
216 | } | |
217 | rdmsrl_safe(msr, &value); | |
218 | smsr->values[slot].host = value; | |
219 | smsr->values[slot].curr = value; | |
220 | } | |
221 | ||
222 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
223 | { | |
0123be42 | 224 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
18863bdd AK |
225 | if (slot >= shared_msrs_global.nr) |
226 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
227 | shared_msrs_global.msrs[slot] = msr; |
228 | /* we need ensured the shared_msr_global have been updated */ | |
229 | smp_wmb(); | |
18863bdd AK |
230 | } |
231 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
232 | ||
233 | static void kvm_shared_msr_cpu_online(void) | |
234 | { | |
235 | unsigned i; | |
18863bdd AK |
236 | |
237 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 238 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
239 | } |
240 | ||
8b3c3104 | 241 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 242 | { |
013f6a5d MT |
243 | unsigned int cpu = smp_processor_id(); |
244 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 245 | int err; |
18863bdd | 246 | |
2bf78fa7 | 247 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 248 | return 0; |
2bf78fa7 | 249 | smsr->values[slot].curr = value; |
8b3c3104 AH |
250 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
251 | if (err) | |
252 | return 1; | |
253 | ||
18863bdd AK |
254 | if (!smsr->registered) { |
255 | smsr->urn.on_user_return = kvm_on_user_return; | |
256 | user_return_notifier_register(&smsr->urn); | |
257 | smsr->registered = true; | |
258 | } | |
8b3c3104 | 259 | return 0; |
18863bdd AK |
260 | } |
261 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
262 | ||
13a34e06 | 263 | static void drop_user_return_notifiers(void) |
3548bab5 | 264 | { |
013f6a5d MT |
265 | unsigned int cpu = smp_processor_id(); |
266 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
267 | |
268 | if (smsr->registered) | |
269 | kvm_on_user_return(&smsr->urn); | |
270 | } | |
271 | ||
6866b83e CO |
272 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
273 | { | |
8a5a87d9 | 274 | return vcpu->arch.apic_base; |
6866b83e CO |
275 | } |
276 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
277 | ||
58cb628d JK |
278 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
279 | { | |
280 | u64 old_state = vcpu->arch.apic_base & | |
281 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
282 | u64 new_state = msr_info->data & | |
283 | (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); | |
284 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | | |
285 | 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); | |
286 | ||
287 | if (!msr_info->host_initiated && | |
288 | ((msr_info->data & reserved_bits) != 0 || | |
289 | new_state == X2APIC_ENABLE || | |
290 | (new_state == MSR_IA32_APICBASE_ENABLE && | |
291 | old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || | |
292 | (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && | |
293 | old_state == 0))) | |
294 | return 1; | |
295 | ||
296 | kvm_lapic_set_base(vcpu, msr_info->data); | |
297 | return 0; | |
6866b83e CO |
298 | } |
299 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
300 | ||
2605fc21 | 301 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
302 | { |
303 | /* Fault while not rebooting. We want the trace. */ | |
304 | BUG(); | |
305 | } | |
306 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
307 | ||
3fd28fce ED |
308 | #define EXCPT_BENIGN 0 |
309 | #define EXCPT_CONTRIBUTORY 1 | |
310 | #define EXCPT_PF 2 | |
311 | ||
312 | static int exception_class(int vector) | |
313 | { | |
314 | switch (vector) { | |
315 | case PF_VECTOR: | |
316 | return EXCPT_PF; | |
317 | case DE_VECTOR: | |
318 | case TS_VECTOR: | |
319 | case NP_VECTOR: | |
320 | case SS_VECTOR: | |
321 | case GP_VECTOR: | |
322 | return EXCPT_CONTRIBUTORY; | |
323 | default: | |
324 | break; | |
325 | } | |
326 | return EXCPT_BENIGN; | |
327 | } | |
328 | ||
d6e8c854 NA |
329 | #define EXCPT_FAULT 0 |
330 | #define EXCPT_TRAP 1 | |
331 | #define EXCPT_ABORT 2 | |
332 | #define EXCPT_INTERRUPT 3 | |
333 | ||
334 | static int exception_type(int vector) | |
335 | { | |
336 | unsigned int mask; | |
337 | ||
338 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
339 | return EXCPT_INTERRUPT; | |
340 | ||
341 | mask = 1 << vector; | |
342 | ||
343 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
344 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
345 | return EXCPT_TRAP; | |
346 | ||
347 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
348 | return EXCPT_ABORT; | |
349 | ||
350 | /* Reserved exceptions will result in fault */ | |
351 | return EXCPT_FAULT; | |
352 | } | |
353 | ||
3fd28fce | 354 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 JR |
355 | unsigned nr, bool has_error, u32 error_code, |
356 | bool reinject) | |
3fd28fce ED |
357 | { |
358 | u32 prev_nr; | |
359 | int class1, class2; | |
360 | ||
3842d135 AK |
361 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
362 | ||
3fd28fce ED |
363 | if (!vcpu->arch.exception.pending) { |
364 | queue: | |
3ffb2468 NA |
365 | if (has_error && !is_protmode(vcpu)) |
366 | has_error = false; | |
3fd28fce ED |
367 | vcpu->arch.exception.pending = true; |
368 | vcpu->arch.exception.has_error_code = has_error; | |
369 | vcpu->arch.exception.nr = nr; | |
370 | vcpu->arch.exception.error_code = error_code; | |
3f0fd292 | 371 | vcpu->arch.exception.reinject = reinject; |
3fd28fce ED |
372 | return; |
373 | } | |
374 | ||
375 | /* to check exception */ | |
376 | prev_nr = vcpu->arch.exception.nr; | |
377 | if (prev_nr == DF_VECTOR) { | |
378 | /* triple fault -> shutdown */ | |
a8eeb04a | 379 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
380 | return; |
381 | } | |
382 | class1 = exception_class(prev_nr); | |
383 | class2 = exception_class(nr); | |
384 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
385 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
386 | /* generate double fault per SDM Table 5-5 */ | |
387 | vcpu->arch.exception.pending = true; | |
388 | vcpu->arch.exception.has_error_code = true; | |
389 | vcpu->arch.exception.nr = DF_VECTOR; | |
390 | vcpu->arch.exception.error_code = 0; | |
391 | } else | |
392 | /* replace previous exception with a new one in a hope | |
393 | that instruction re-execution will regenerate lost | |
394 | exception */ | |
395 | goto queue; | |
396 | } | |
397 | ||
298101da AK |
398 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
399 | { | |
ce7ddec4 | 400 | kvm_multiple_exception(vcpu, nr, false, 0, false); |
298101da AK |
401 | } |
402 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
403 | ||
ce7ddec4 JR |
404 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
405 | { | |
406 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
407 | } | |
408 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
409 | ||
db8fcefa | 410 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 411 | { |
db8fcefa AP |
412 | if (err) |
413 | kvm_inject_gp(vcpu, 0); | |
414 | else | |
415 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
416 | } | |
417 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 418 | |
6389ee94 | 419 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
420 | { |
421 | ++vcpu->stat.pf_guest; | |
6389ee94 AK |
422 | vcpu->arch.cr2 = fault->address; |
423 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
c3c91fee | 424 | } |
27d6c865 | 425 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 426 | |
ef54bcfe | 427 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 428 | { |
6389ee94 AK |
429 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
430 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 431 | else |
6389ee94 | 432 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
ef54bcfe PB |
433 | |
434 | return fault->nested_page_fault; | |
d4f8cf66 JR |
435 | } |
436 | ||
3419ffc8 SY |
437 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
438 | { | |
7460fb4a AK |
439 | atomic_inc(&vcpu->arch.nmi_queued); |
440 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
441 | } |
442 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
443 | ||
298101da AK |
444 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
445 | { | |
ce7ddec4 | 446 | kvm_multiple_exception(vcpu, nr, true, error_code, false); |
298101da AK |
447 | } |
448 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
449 | ||
ce7ddec4 JR |
450 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
451 | { | |
452 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
453 | } | |
454 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
455 | ||
0a79b009 AK |
456 | /* |
457 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
458 | * a #GP and return false. | |
459 | */ | |
460 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 461 | { |
0a79b009 AK |
462 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
463 | return true; | |
464 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
465 | return false; | |
298101da | 466 | } |
0a79b009 | 467 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 468 | |
16f8a6f9 NA |
469 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
470 | { | |
471 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
472 | return true; | |
473 | ||
474 | kvm_queue_exception(vcpu, UD_VECTOR); | |
475 | return false; | |
476 | } | |
477 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
478 | ||
ec92fe44 JR |
479 | /* |
480 | * This function will be used to read from the physical memory of the currently | |
481 | * running guest. The difference to kvm_read_guest_page is that this function | |
482 | * can read from guest physical or from the guest's guest physical memory. | |
483 | */ | |
484 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
485 | gfn_t ngfn, void *data, int offset, int len, | |
486 | u32 access) | |
487 | { | |
54987b7a | 488 | struct x86_exception exception; |
ec92fe44 JR |
489 | gfn_t real_gfn; |
490 | gpa_t ngpa; | |
491 | ||
492 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 493 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
494 | if (real_gfn == UNMAPPED_GVA) |
495 | return -EFAULT; | |
496 | ||
497 | real_gfn = gpa_to_gfn(real_gfn); | |
498 | ||
499 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
500 | } | |
501 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
502 | ||
69b0049a | 503 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
504 | void *data, int offset, int len, u32 access) |
505 | { | |
506 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
507 | data, offset, len, access); | |
508 | } | |
509 | ||
a03490ed CO |
510 | /* |
511 | * Load the pae pdptrs. Return true is they are all valid. | |
512 | */ | |
ff03a073 | 513 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
514 | { |
515 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
516 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
517 | int i; | |
518 | int ret; | |
ff03a073 | 519 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 520 | |
ff03a073 JR |
521 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
522 | offset * sizeof(u64), sizeof(pdpte), | |
523 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
524 | if (ret < 0) { |
525 | ret = 0; | |
526 | goto out; | |
527 | } | |
528 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 529 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 530 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
531 | ret = 0; |
532 | goto out; | |
533 | } | |
534 | } | |
535 | ret = 1; | |
536 | ||
ff03a073 | 537 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
538 | __set_bit(VCPU_EXREG_PDPTR, |
539 | (unsigned long *)&vcpu->arch.regs_avail); | |
540 | __set_bit(VCPU_EXREG_PDPTR, | |
541 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 542 | out: |
a03490ed CO |
543 | |
544 | return ret; | |
545 | } | |
cc4b6871 | 546 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 547 | |
d835dfec AK |
548 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
549 | { | |
ff03a073 | 550 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 551 | bool changed = true; |
3d06b8bf JR |
552 | int offset; |
553 | gfn_t gfn; | |
d835dfec AK |
554 | int r; |
555 | ||
556 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
557 | return false; | |
558 | ||
6de4f3ad AK |
559 | if (!test_bit(VCPU_EXREG_PDPTR, |
560 | (unsigned long *)&vcpu->arch.regs_avail)) | |
561 | return true; | |
562 | ||
9f8fe504 AK |
563 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; |
564 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
565 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
566 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
567 | if (r < 0) |
568 | goto out; | |
ff03a073 | 569 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 570 | out: |
d835dfec AK |
571 | |
572 | return changed; | |
573 | } | |
574 | ||
49a9b07e | 575 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 576 | { |
aad82703 | 577 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 578 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 579 | |
f9a48e6a AK |
580 | cr0 |= X86_CR0_ET; |
581 | ||
ab344828 | 582 | #ifdef CONFIG_X86_64 |
0f12244f GN |
583 | if (cr0 & 0xffffffff00000000UL) |
584 | return 1; | |
ab344828 GN |
585 | #endif |
586 | ||
587 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 588 | |
0f12244f GN |
589 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
590 | return 1; | |
a03490ed | 591 | |
0f12244f GN |
592 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
593 | return 1; | |
a03490ed CO |
594 | |
595 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
596 | #ifdef CONFIG_X86_64 | |
f6801dff | 597 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
598 | int cs_db, cs_l; |
599 | ||
0f12244f GN |
600 | if (!is_pae(vcpu)) |
601 | return 1; | |
a03490ed | 602 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
603 | if (cs_l) |
604 | return 1; | |
a03490ed CO |
605 | } else |
606 | #endif | |
ff03a073 | 607 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 608 | kvm_read_cr3(vcpu))) |
0f12244f | 609 | return 1; |
a03490ed CO |
610 | } |
611 | ||
ad756a16 MJ |
612 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
613 | return 1; | |
614 | ||
a03490ed | 615 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 616 | |
d170c419 | 617 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 618 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
619 | kvm_async_pf_hash_reset(vcpu); |
620 | } | |
e5f3f027 | 621 | |
aad82703 SY |
622 | if ((cr0 ^ old_cr0) & update_bits) |
623 | kvm_mmu_reset_context(vcpu); | |
0f12244f GN |
624 | return 0; |
625 | } | |
2d3ad1f4 | 626 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 627 | |
2d3ad1f4 | 628 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 629 | { |
49a9b07e | 630 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 631 | } |
2d3ad1f4 | 632 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 633 | |
42bdf991 MT |
634 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
635 | { | |
636 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
637 | !vcpu->guest_xcr0_loaded) { | |
638 | /* kvm_set_xcr() also depends on this */ | |
639 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
640 | vcpu->guest_xcr0_loaded = 1; | |
641 | } | |
642 | } | |
643 | ||
644 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
645 | { | |
646 | if (vcpu->guest_xcr0_loaded) { | |
647 | if (vcpu->arch.xcr0 != host_xcr0) | |
648 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
649 | vcpu->guest_xcr0_loaded = 0; | |
650 | } | |
651 | } | |
652 | ||
69b0049a | 653 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 654 | { |
56c103ec LJ |
655 | u64 xcr0 = xcr; |
656 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 657 | u64 valid_bits; |
2acf923e DC |
658 | |
659 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
660 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
661 | return 1; | |
2acf923e DC |
662 | if (!(xcr0 & XSTATE_FP)) |
663 | return 1; | |
664 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
665 | return 1; | |
46c34cb0 PB |
666 | |
667 | /* | |
668 | * Do not allow the guest to set bits that we do not support | |
669 | * saving. However, xcr0 bit 0 is always set, even if the | |
670 | * emulated CPU does not support XSAVE (see fx_init). | |
671 | */ | |
672 | valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; | |
673 | if (xcr0 & ~valid_bits) | |
2acf923e | 674 | return 1; |
46c34cb0 | 675 | |
390bd528 LJ |
676 | if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) |
677 | return 1; | |
678 | ||
612263b3 CP |
679 | if (xcr0 & XSTATE_AVX512) { |
680 | if (!(xcr0 & XSTATE_YMM)) | |
681 | return 1; | |
682 | if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) | |
683 | return 1; | |
684 | } | |
42bdf991 | 685 | kvm_put_guest_xcr0(vcpu); |
2acf923e | 686 | vcpu->arch.xcr0 = xcr0; |
56c103ec LJ |
687 | |
688 | if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) | |
689 | kvm_update_cpuid(vcpu); | |
2acf923e DC |
690 | return 0; |
691 | } | |
692 | ||
693 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
694 | { | |
764bcbc5 Z |
695 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
696 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
697 | kvm_inject_gp(vcpu, 0); |
698 | return 1; | |
699 | } | |
700 | return 0; | |
701 | } | |
702 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
703 | ||
a83b29c6 | 704 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 705 | { |
fc78f519 | 706 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
edc90b7d XG |
707 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | |
708 | X86_CR4_SMEP | X86_CR4_SMAP; | |
709 | ||
0f12244f GN |
710 | if (cr4 & CR4_RESERVED_BITS) |
711 | return 1; | |
a03490ed | 712 | |
2acf923e DC |
713 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) |
714 | return 1; | |
715 | ||
c68b734f YW |
716 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) |
717 | return 1; | |
718 | ||
97ec8c06 FW |
719 | if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) |
720 | return 1; | |
721 | ||
afcbf13f | 722 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) |
74dc2b4f YW |
723 | return 1; |
724 | ||
a03490ed | 725 | if (is_long_mode(vcpu)) { |
0f12244f GN |
726 | if (!(cr4 & X86_CR4_PAE)) |
727 | return 1; | |
a2edf57f AK |
728 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
729 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
730 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
731 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
732 | return 1; |
733 | ||
ad756a16 MJ |
734 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
735 | if (!guest_cpuid_has_pcid(vcpu)) | |
736 | return 1; | |
737 | ||
738 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
739 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
740 | return 1; | |
741 | } | |
742 | ||
5e1746d6 | 743 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 744 | return 1; |
a03490ed | 745 | |
ad756a16 MJ |
746 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
747 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 748 | kvm_mmu_reset_context(vcpu); |
0f12244f | 749 | |
2acf923e | 750 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) |
00b27a3e | 751 | kvm_update_cpuid(vcpu); |
2acf923e | 752 | |
0f12244f GN |
753 | return 0; |
754 | } | |
2d3ad1f4 | 755 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 756 | |
2390218b | 757 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 758 | { |
ac146235 | 759 | #ifdef CONFIG_X86_64 |
9d88fca7 | 760 | cr3 &= ~CR3_PCID_INVD; |
ac146235 | 761 | #endif |
9d88fca7 | 762 | |
9f8fe504 | 763 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
0ba73cda | 764 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 765 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
0f12244f | 766 | return 0; |
d835dfec AK |
767 | } |
768 | ||
a03490ed | 769 | if (is_long_mode(vcpu)) { |
d9f89b88 JK |
770 | if (cr3 & CR3_L_MODE_RESERVED_BITS) |
771 | return 1; | |
772 | } else if (is_pae(vcpu) && is_paging(vcpu) && | |
773 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 774 | return 1; |
a03490ed | 775 | |
0f12244f | 776 | vcpu->arch.cr3 = cr3; |
aff48baa | 777 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
d8d173da | 778 | kvm_mmu_new_cr3(vcpu); |
0f12244f GN |
779 | return 0; |
780 | } | |
2d3ad1f4 | 781 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 782 | |
eea1cff9 | 783 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 784 | { |
0f12244f GN |
785 | if (cr8 & CR8_RESERVED_BITS) |
786 | return 1; | |
a03490ed CO |
787 | if (irqchip_in_kernel(vcpu->kvm)) |
788 | kvm_lapic_set_tpr(vcpu, cr8); | |
789 | else | |
ad312c7c | 790 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
791 | return 0; |
792 | } | |
2d3ad1f4 | 793 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 794 | |
2d3ad1f4 | 795 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
796 | { |
797 | if (irqchip_in_kernel(vcpu->kvm)) | |
798 | return kvm_lapic_get_cr8(vcpu); | |
799 | else | |
ad312c7c | 800 | return vcpu->arch.cr8; |
a03490ed | 801 | } |
2d3ad1f4 | 802 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 803 | |
ae561ede NA |
804 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
805 | { | |
806 | int i; | |
807 | ||
808 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
809 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
810 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
811 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
812 | } | |
813 | } | |
814 | ||
73aaf249 JK |
815 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
816 | { | |
817 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
818 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
819 | } | |
820 | ||
c8639010 JK |
821 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
822 | { | |
823 | unsigned long dr7; | |
824 | ||
825 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
826 | dr7 = vcpu->arch.guest_debug_dr7; | |
827 | else | |
828 | dr7 = vcpu->arch.dr7; | |
829 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
830 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
831 | if (dr7 & DR7_BP_EN_MASK) | |
832 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
833 | } |
834 | ||
6f43ed01 NA |
835 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
836 | { | |
837 | u64 fixed = DR6_FIXED_1; | |
838 | ||
839 | if (!guest_cpuid_has_rtm(vcpu)) | |
840 | fixed |= DR6_RTM; | |
841 | return fixed; | |
842 | } | |
843 | ||
338dbc97 | 844 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
845 | { |
846 | switch (dr) { | |
847 | case 0 ... 3: | |
848 | vcpu->arch.db[dr] = val; | |
849 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
850 | vcpu->arch.eff_db[dr] = val; | |
851 | break; | |
852 | case 4: | |
020df079 GN |
853 | /* fall through */ |
854 | case 6: | |
338dbc97 GN |
855 | if (val & 0xffffffff00000000ULL) |
856 | return -1; /* #GP */ | |
6f43ed01 | 857 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 858 | kvm_update_dr6(vcpu); |
020df079 GN |
859 | break; |
860 | case 5: | |
020df079 GN |
861 | /* fall through */ |
862 | default: /* 7 */ | |
338dbc97 GN |
863 | if (val & 0xffffffff00000000ULL) |
864 | return -1; /* #GP */ | |
020df079 | 865 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 866 | kvm_update_dr7(vcpu); |
020df079 GN |
867 | break; |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
338dbc97 GN |
872 | |
873 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
874 | { | |
16f8a6f9 | 875 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 876 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
877 | return 1; |
878 | } | |
879 | return 0; | |
338dbc97 | 880 | } |
020df079 GN |
881 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
882 | ||
16f8a6f9 | 883 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
884 | { |
885 | switch (dr) { | |
886 | case 0 ... 3: | |
887 | *val = vcpu->arch.db[dr]; | |
888 | break; | |
889 | case 4: | |
020df079 GN |
890 | /* fall through */ |
891 | case 6: | |
73aaf249 JK |
892 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
893 | *val = vcpu->arch.dr6; | |
894 | else | |
895 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
896 | break; |
897 | case 5: | |
020df079 GN |
898 | /* fall through */ |
899 | default: /* 7 */ | |
900 | *val = vcpu->arch.dr7; | |
901 | break; | |
902 | } | |
338dbc97 GN |
903 | return 0; |
904 | } | |
020df079 GN |
905 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
906 | ||
022cd0e8 AK |
907 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
908 | { | |
909 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
910 | u64 data; | |
911 | int err; | |
912 | ||
913 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
914 | if (err) | |
915 | return err; | |
916 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
917 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
918 | return err; | |
919 | } | |
920 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
921 | ||
043405e1 CO |
922 | /* |
923 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
924 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
925 | * | |
926 | * This list is modified at module load time to reflect the | |
e3267cbb | 927 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
62ef68bb PB |
928 | * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs |
929 | * may depend on host virtualization features rather than host cpu features. | |
043405e1 | 930 | */ |
e3267cbb | 931 | |
043405e1 CO |
932 | static u32 msrs_to_save[] = { |
933 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
8c06585d | 934 | MSR_STAR, |
043405e1 CO |
935 | #ifdef CONFIG_X86_64 |
936 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
937 | #endif | |
b3897a49 | 938 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
0dd376e7 | 939 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS |
043405e1 CO |
940 | }; |
941 | ||
942 | static unsigned num_msrs_to_save; | |
943 | ||
62ef68bb PB |
944 | static u32 emulated_msrs[] = { |
945 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
946 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
947 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
948 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
949 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
950 | MSR_KVM_PV_EOI_EN, | |
951 | ||
ba904635 | 952 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 953 | MSR_IA32_TSCDEADLINE, |
043405e1 | 954 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
955 | MSR_IA32_MCG_STATUS, |
956 | MSR_IA32_MCG_CTL, | |
64d60670 | 957 | MSR_IA32_SMBASE, |
043405e1 CO |
958 | }; |
959 | ||
62ef68bb PB |
960 | static unsigned num_emulated_msrs; |
961 | ||
384bb783 | 962 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 963 | { |
b69e8cae | 964 | if (efer & efer_reserved_bits) |
384bb783 | 965 | return false; |
15c4a640 | 966 | |
1b2fd70c AG |
967 | if (efer & EFER_FFXSR) { |
968 | struct kvm_cpuid_entry2 *feat; | |
969 | ||
970 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 971 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) |
384bb783 | 972 | return false; |
1b2fd70c AG |
973 | } |
974 | ||
d8017474 AG |
975 | if (efer & EFER_SVME) { |
976 | struct kvm_cpuid_entry2 *feat; | |
977 | ||
978 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
b69e8cae | 979 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) |
384bb783 | 980 | return false; |
d8017474 AG |
981 | } |
982 | ||
384bb783 JK |
983 | return true; |
984 | } | |
985 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
986 | ||
987 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
988 | { | |
989 | u64 old_efer = vcpu->arch.efer; | |
990 | ||
991 | if (!kvm_valid_efer(vcpu, efer)) | |
992 | return 1; | |
993 | ||
994 | if (is_paging(vcpu) | |
995 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
996 | return 1; | |
997 | ||
15c4a640 | 998 | efer &= ~EFER_LMA; |
f6801dff | 999 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1000 | |
a3d204e2 SY |
1001 | kvm_x86_ops->set_efer(vcpu, efer); |
1002 | ||
aad82703 SY |
1003 | /* Update reserved bits */ |
1004 | if ((efer ^ old_efer) & EFER_NX) | |
1005 | kvm_mmu_reset_context(vcpu); | |
1006 | ||
b69e8cae | 1007 | return 0; |
15c4a640 CO |
1008 | } |
1009 | ||
f2b4b7dd JR |
1010 | void kvm_enable_efer_bits(u64 mask) |
1011 | { | |
1012 | efer_reserved_bits &= ~mask; | |
1013 | } | |
1014 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1015 | ||
15c4a640 CO |
1016 | /* |
1017 | * Writes msr value into into the appropriate "register". | |
1018 | * Returns 0 on success, non-0 otherwise. | |
1019 | * Assumes vcpu_load() was already called. | |
1020 | */ | |
8fe8ab46 | 1021 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1022 | { |
854e8bb1 NA |
1023 | switch (msr->index) { |
1024 | case MSR_FS_BASE: | |
1025 | case MSR_GS_BASE: | |
1026 | case MSR_KERNEL_GS_BASE: | |
1027 | case MSR_CSTAR: | |
1028 | case MSR_LSTAR: | |
1029 | if (is_noncanonical_address(msr->data)) | |
1030 | return 1; | |
1031 | break; | |
1032 | case MSR_IA32_SYSENTER_EIP: | |
1033 | case MSR_IA32_SYSENTER_ESP: | |
1034 | /* | |
1035 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1036 | * non-canonical address is written on Intel but not on | |
1037 | * AMD (which ignores the top 32-bits, because it does | |
1038 | * not implement 64-bit SYSENTER). | |
1039 | * | |
1040 | * 64-bit code should hence be able to write a non-canonical | |
1041 | * value on AMD. Making the address canonical ensures that | |
1042 | * vmentry does not fail on Intel after writing a non-canonical | |
1043 | * value, and that something deterministic happens if the guest | |
1044 | * invokes 64-bit SYSENTER. | |
1045 | */ | |
1046 | msr->data = get_canonical(msr->data); | |
1047 | } | |
8fe8ab46 | 1048 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1049 | } |
854e8bb1 | 1050 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1051 | |
313a3dc7 CO |
1052 | /* |
1053 | * Adapt set_msr() to msr_io()'s calling convention | |
1054 | */ | |
609e36d3 PB |
1055 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1056 | { | |
1057 | struct msr_data msr; | |
1058 | int r; | |
1059 | ||
1060 | msr.index = index; | |
1061 | msr.host_initiated = true; | |
1062 | r = kvm_get_msr(vcpu, &msr); | |
1063 | if (r) | |
1064 | return r; | |
1065 | ||
1066 | *data = msr.data; | |
1067 | return 0; | |
1068 | } | |
1069 | ||
313a3dc7 CO |
1070 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1071 | { | |
8fe8ab46 WA |
1072 | struct msr_data msr; |
1073 | ||
1074 | msr.data = *data; | |
1075 | msr.index = index; | |
1076 | msr.host_initiated = true; | |
1077 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1078 | } |
1079 | ||
16e8d74d MT |
1080 | #ifdef CONFIG_X86_64 |
1081 | struct pvclock_gtod_data { | |
1082 | seqcount_t seq; | |
1083 | ||
1084 | struct { /* extract of a clocksource struct */ | |
1085 | int vclock_mode; | |
1086 | cycle_t cycle_last; | |
1087 | cycle_t mask; | |
1088 | u32 mult; | |
1089 | u32 shift; | |
1090 | } clock; | |
1091 | ||
cbcf2dd3 TG |
1092 | u64 boot_ns; |
1093 | u64 nsec_base; | |
16e8d74d MT |
1094 | }; |
1095 | ||
1096 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1097 | ||
1098 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1099 | { | |
1100 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1101 | u64 boot_ns; |
1102 | ||
876e7881 | 1103 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1104 | |
1105 | write_seqcount_begin(&vdata->seq); | |
1106 | ||
1107 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1108 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1109 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1110 | vdata->clock.mask = tk->tkr_mono.mask; | |
1111 | vdata->clock.mult = tk->tkr_mono.mult; | |
1112 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1113 | |
cbcf2dd3 | 1114 | vdata->boot_ns = boot_ns; |
876e7881 | 1115 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d MT |
1116 | |
1117 | write_seqcount_end(&vdata->seq); | |
1118 | } | |
1119 | #endif | |
1120 | ||
bab5bb39 NK |
1121 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1122 | { | |
1123 | /* | |
1124 | * Note: KVM_REQ_PENDING_TIMER is implicitly checked in | |
1125 | * vcpu_enter_guest. This function is only called from | |
1126 | * the physical CPU that is running vcpu. | |
1127 | */ | |
1128 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1129 | } | |
16e8d74d | 1130 | |
18068523 GOC |
1131 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1132 | { | |
9ed3c444 AK |
1133 | int version; |
1134 | int r; | |
50d0a0f9 | 1135 | struct pvclock_wall_clock wc; |
923de3cf | 1136 | struct timespec boot; |
18068523 GOC |
1137 | |
1138 | if (!wall_clock) | |
1139 | return; | |
1140 | ||
9ed3c444 AK |
1141 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1142 | if (r) | |
1143 | return; | |
1144 | ||
1145 | if (version & 1) | |
1146 | ++version; /* first time write, random junk */ | |
1147 | ||
1148 | ++version; | |
18068523 | 1149 | |
18068523 GOC |
1150 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
1151 | ||
50d0a0f9 GH |
1152 | /* |
1153 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1154 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1155 | * wall clock specified here. guest system time equals host |
1156 | * system time for us, thus we must fill in host boot time here. | |
1157 | */ | |
923de3cf | 1158 | getboottime(&boot); |
50d0a0f9 | 1159 | |
4b648665 BR |
1160 | if (kvm->arch.kvmclock_offset) { |
1161 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1162 | boot = timespec_sub(boot, ts); | |
1163 | } | |
50d0a0f9 GH |
1164 | wc.sec = boot.tv_sec; |
1165 | wc.nsec = boot.tv_nsec; | |
1166 | wc.version = version; | |
18068523 GOC |
1167 | |
1168 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1169 | ||
1170 | version++; | |
1171 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1172 | } |
1173 | ||
50d0a0f9 GH |
1174 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1175 | { | |
1176 | uint32_t quotient, remainder; | |
1177 | ||
1178 | /* Don't try to replace with do_div(), this one calculates | |
1179 | * "(dividend << 32) / divisor" */ | |
1180 | __asm__ ( "divl %4" | |
1181 | : "=a" (quotient), "=d" (remainder) | |
1182 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1183 | return quotient; | |
1184 | } | |
1185 | ||
5f4e3f88 ZA |
1186 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, |
1187 | s8 *pshift, u32 *pmultiplier) | |
50d0a0f9 | 1188 | { |
5f4e3f88 | 1189 | uint64_t scaled64; |
50d0a0f9 GH |
1190 | int32_t shift = 0; |
1191 | uint64_t tps64; | |
1192 | uint32_t tps32; | |
1193 | ||
5f4e3f88 ZA |
1194 | tps64 = base_khz * 1000LL; |
1195 | scaled64 = scaled_khz * 1000LL; | |
50933623 | 1196 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1197 | tps64 >>= 1; |
1198 | shift--; | |
1199 | } | |
1200 | ||
1201 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1202 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1203 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1204 | scaled64 >>= 1; |
1205 | else | |
1206 | tps32 <<= 1; | |
50d0a0f9 GH |
1207 | shift++; |
1208 | } | |
1209 | ||
5f4e3f88 ZA |
1210 | *pshift = shift; |
1211 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 | 1212 | |
5f4e3f88 ZA |
1213 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", |
1214 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
50d0a0f9 GH |
1215 | } |
1216 | ||
759379dd ZA |
1217 | static inline u64 get_kernel_ns(void) |
1218 | { | |
bb0b5812 | 1219 | return ktime_get_boot_ns(); |
50d0a0f9 GH |
1220 | } |
1221 | ||
d828199e | 1222 | #ifdef CONFIG_X86_64 |
16e8d74d | 1223 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1224 | #endif |
16e8d74d | 1225 | |
c8076604 | 1226 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1227 | static unsigned long max_tsc_khz; |
c8076604 | 1228 | |
cc578287 | 1229 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) |
8cfdc000 | 1230 | { |
cc578287 ZA |
1231 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, |
1232 | vcpu->arch.virtual_tsc_shift); | |
8cfdc000 ZA |
1233 | } |
1234 | ||
cc578287 | 1235 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1236 | { |
cc578287 ZA |
1237 | u64 v = (u64)khz * (1000000 + ppm); |
1238 | do_div(v, 1000000); | |
1239 | return v; | |
1e993611 JR |
1240 | } |
1241 | ||
cc578287 | 1242 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) |
759379dd | 1243 | { |
cc578287 ZA |
1244 | u32 thresh_lo, thresh_hi; |
1245 | int use_scaling = 0; | |
217fc9cf | 1246 | |
03ba32ca MT |
1247 | /* tsc_khz can be zero if TSC calibration fails */ |
1248 | if (this_tsc_khz == 0) | |
1249 | return; | |
1250 | ||
c285545f ZA |
1251 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
1252 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
cc578287 ZA |
1253 | &vcpu->arch.virtual_tsc_shift, |
1254 | &vcpu->arch.virtual_tsc_mult); | |
1255 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1256 | ||
1257 | /* | |
1258 | * Compute the variation in TSC rate which is acceptable | |
1259 | * within the range of tolerance and decide if the | |
1260 | * rate being applied is within that bounds of the hardware | |
1261 | * rate. If so, no scaling or compensation need be done. | |
1262 | */ | |
1263 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1264 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1265 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1266 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1267 | use_scaling = 1; | |
1268 | } | |
1269 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
c285545f ZA |
1270 | } |
1271 | ||
1272 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1273 | { | |
e26101b1 | 1274 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1275 | vcpu->arch.virtual_tsc_mult, |
1276 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1277 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1278 | return tsc; |
1279 | } | |
1280 | ||
69b0049a | 1281 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1282 | { |
1283 | #ifdef CONFIG_X86_64 | |
1284 | bool vcpus_matched; | |
b48aa97e MT |
1285 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1286 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1287 | ||
1288 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1289 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1290 | ||
7f187922 MT |
1291 | /* |
1292 | * Once the masterclock is enabled, always perform request in | |
1293 | * order to update it. | |
1294 | * | |
1295 | * In order to enable masterclock, the host clocksource must be TSC | |
1296 | * and the vcpus need to have matched TSCs. When that happens, | |
1297 | * perform request to enable masterclock. | |
1298 | */ | |
1299 | if (ka->use_master_clock || | |
1300 | (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) | |
b48aa97e MT |
1301 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1302 | ||
1303 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1304 | atomic_read(&vcpu->kvm->online_vcpus), | |
1305 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1306 | #endif | |
1307 | } | |
1308 | ||
ba904635 WA |
1309 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1310 | { | |
1311 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1312 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1313 | } | |
1314 | ||
8fe8ab46 | 1315 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1316 | { |
1317 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1318 | u64 offset, ns, elapsed; |
99e3e30a | 1319 | unsigned long flags; |
02626b6a | 1320 | s64 usdiff; |
b48aa97e | 1321 | bool matched; |
0d3da0d2 | 1322 | bool already_matched; |
8fe8ab46 | 1323 | u64 data = msr->data; |
99e3e30a | 1324 | |
038f8c11 | 1325 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
857e4099 | 1326 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); |
759379dd | 1327 | ns = get_kernel_ns(); |
f38e098f | 1328 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1329 | |
03ba32ca | 1330 | if (vcpu->arch.virtual_tsc_khz) { |
8915aa27 MT |
1331 | int faulted = 0; |
1332 | ||
03ba32ca MT |
1333 | /* n.b - signed multiplication and division required */ |
1334 | usdiff = data - kvm->arch.last_tsc_write; | |
5d3cb0f6 | 1335 | #ifdef CONFIG_X86_64 |
03ba32ca | 1336 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; |
5d3cb0f6 | 1337 | #else |
03ba32ca | 1338 | /* do_div() only does unsigned */ |
8915aa27 MT |
1339 | asm("1: idivl %[divisor]\n" |
1340 | "2: xor %%edx, %%edx\n" | |
1341 | " movl $0, %[faulted]\n" | |
1342 | "3:\n" | |
1343 | ".section .fixup,\"ax\"\n" | |
1344 | "4: movl $1, %[faulted]\n" | |
1345 | " jmp 3b\n" | |
1346 | ".previous\n" | |
1347 | ||
1348 | _ASM_EXTABLE(1b, 4b) | |
1349 | ||
1350 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1351 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1352 | ||
5d3cb0f6 | 1353 | #endif |
03ba32ca MT |
1354 | do_div(elapsed, 1000); |
1355 | usdiff -= elapsed; | |
1356 | if (usdiff < 0) | |
1357 | usdiff = -usdiff; | |
8915aa27 MT |
1358 | |
1359 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1360 | if (faulted) | |
1361 | usdiff = USEC_PER_SEC; | |
03ba32ca MT |
1362 | } else |
1363 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
f38e098f ZA |
1364 | |
1365 | /* | |
5d3cb0f6 ZA |
1366 | * Special case: TSC write with a small delta (1 second) of virtual |
1367 | * cycle time against real time is interpreted as an attempt to | |
1368 | * synchronize the CPU. | |
1369 | * | |
1370 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1371 | * TSC, we add elapsed time in this computation. We could let the | |
1372 | * compensation code attempt to catch up if we fall behind, but | |
1373 | * it's better to try to match offsets from the beginning. | |
1374 | */ | |
02626b6a | 1375 | if (usdiff < USEC_PER_SEC && |
5d3cb0f6 | 1376 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
f38e098f | 1377 | if (!check_tsc_unstable()) { |
e26101b1 | 1378 | offset = kvm->arch.cur_tsc_offset; |
f38e098f ZA |
1379 | pr_debug("kvm: matched tsc offset for %llu\n", data); |
1380 | } else { | |
857e4099 | 1381 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 ZA |
1382 | data += delta; |
1383 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
759379dd | 1384 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); |
f38e098f | 1385 | } |
b48aa97e | 1386 | matched = true; |
0d3da0d2 | 1387 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1388 | } else { |
1389 | /* | |
1390 | * We split periods of matched TSC writes into generations. | |
1391 | * For each generation, we track the original measured | |
1392 | * nanosecond time, offset, and write, so if TSCs are in | |
1393 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1394 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1395 | * |
1396 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1397 | */ | |
1398 | kvm->arch.cur_tsc_generation++; | |
1399 | kvm->arch.cur_tsc_nsec = ns; | |
1400 | kvm->arch.cur_tsc_write = data; | |
1401 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1402 | matched = false; |
0d3da0d2 | 1403 | pr_debug("kvm: new tsc generation %llu, clock %llu\n", |
e26101b1 | 1404 | kvm->arch.cur_tsc_generation, data); |
f38e098f | 1405 | } |
e26101b1 ZA |
1406 | |
1407 | /* | |
1408 | * We also track th most recent recorded KHZ, write and time to | |
1409 | * allow the matching interval to be extended at each write. | |
1410 | */ | |
f38e098f ZA |
1411 | kvm->arch.last_tsc_nsec = ns; |
1412 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1413 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1414 | |
b183aa58 | 1415 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1416 | |
1417 | /* Keep track of which generation this VCPU has synchronized to */ | |
1418 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1419 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1420 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1421 | ||
ba904635 WA |
1422 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) |
1423 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
e26101b1 ZA |
1424 | kvm_x86_ops->write_tsc_offset(vcpu, offset); |
1425 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
b48aa97e MT |
1426 | |
1427 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1428 | if (!matched) { |
b48aa97e | 1429 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1430 | } else if (!already_matched) { |
1431 | kvm->arch.nr_vcpus_matched_tsc++; | |
1432 | } | |
b48aa97e MT |
1433 | |
1434 | kvm_track_tsc_matching(vcpu); | |
1435 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1436 | } |
e26101b1 | 1437 | |
99e3e30a ZA |
1438 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1439 | ||
d828199e MT |
1440 | #ifdef CONFIG_X86_64 |
1441 | ||
1442 | static cycle_t read_tsc(void) | |
1443 | { | |
1444 | cycle_t ret; | |
1445 | u64 last; | |
1446 | ||
1447 | /* | |
1448 | * Empirically, a fence (of type that depends on the CPU) | |
1449 | * before rdtsc is enough to ensure that rdtsc is ordered | |
1450 | * with respect to loads. The various CPU manuals are unclear | |
1451 | * as to whether rdtsc can be reordered with later loads, | |
1452 | * but no one has ever seen it happen. | |
1453 | */ | |
1454 | rdtsc_barrier(); | |
1455 | ret = (cycle_t)vget_cycles(); | |
1456 | ||
1457 | last = pvclock_gtod_data.clock.cycle_last; | |
1458 | ||
1459 | if (likely(ret >= last)) | |
1460 | return ret; | |
1461 | ||
1462 | /* | |
1463 | * GCC likes to generate cmov here, but this branch is extremely | |
1464 | * predictable (it's just a funciton of time and the likely is | |
1465 | * very likely) and there's a data dependence, so force GCC | |
1466 | * to generate a branch instead. I don't barrier() because | |
1467 | * we don't actually need a barrier, and if this function | |
1468 | * ever gets inlined it will generate worse code. | |
1469 | */ | |
1470 | asm volatile (""); | |
1471 | return last; | |
1472 | } | |
1473 | ||
1474 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1475 | { | |
1476 | long v; | |
1477 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1478 | ||
1479 | *cycle_now = read_tsc(); | |
1480 | ||
1481 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1482 | return v * gtod->clock.mult; | |
1483 | } | |
1484 | ||
cbcf2dd3 | 1485 | static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) |
d828199e | 1486 | { |
cbcf2dd3 | 1487 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1488 | unsigned long seq; |
d828199e | 1489 | int mode; |
cbcf2dd3 | 1490 | u64 ns; |
d828199e | 1491 | |
d828199e MT |
1492 | do { |
1493 | seq = read_seqcount_begin(>od->seq); | |
1494 | mode = gtod->clock.vclock_mode; | |
cbcf2dd3 | 1495 | ns = gtod->nsec_base; |
d828199e MT |
1496 | ns += vgettsc(cycle_now); |
1497 | ns >>= gtod->clock.shift; | |
cbcf2dd3 | 1498 | ns += gtod->boot_ns; |
d828199e | 1499 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1500 | *t = ns; |
d828199e MT |
1501 | |
1502 | return mode; | |
1503 | } | |
1504 | ||
1505 | /* returns true if host is using tsc clocksource */ | |
1506 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1507 | { | |
d828199e MT |
1508 | /* checked again under seqlock below */ |
1509 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1510 | return false; | |
1511 | ||
cbcf2dd3 | 1512 | return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; |
d828199e MT |
1513 | } |
1514 | #endif | |
1515 | ||
1516 | /* | |
1517 | * | |
b48aa97e MT |
1518 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1519 | * across virtual CPUs, the following condition is possible. | |
1520 | * Each numbered line represents an event visible to both | |
d828199e MT |
1521 | * CPUs at the next numbered event. |
1522 | * | |
1523 | * "timespecX" represents host monotonic time. "tscX" represents | |
1524 | * RDTSC value. | |
1525 | * | |
1526 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1527 | * | |
1528 | * 1. read timespec0,tsc0 | |
1529 | * 2. | timespec1 = timespec0 + N | |
1530 | * | tsc1 = tsc0 + M | |
1531 | * 3. transition to guest | transition to guest | |
1532 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1533 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1534 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1535 | * | |
1536 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1537 | * | |
1538 | * - ret0 < ret1 | |
1539 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1540 | * ... | |
1541 | * - 0 < N - M => M < N | |
1542 | * | |
1543 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1544 | * always the case (the difference between two distinct xtime instances | |
1545 | * might be smaller then the difference between corresponding TSC reads, | |
1546 | * when updating guest vcpus pvclock areas). | |
1547 | * | |
1548 | * To avoid that problem, do not allow visibility of distinct | |
1549 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1550 | * copy of host monotonic time values. Update that master copy | |
1551 | * in lockstep. | |
1552 | * | |
b48aa97e | 1553 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
1554 | * |
1555 | */ | |
1556 | ||
1557 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1558 | { | |
1559 | #ifdef CONFIG_X86_64 | |
1560 | struct kvm_arch *ka = &kvm->arch; | |
1561 | int vclock_mode; | |
b48aa97e MT |
1562 | bool host_tsc_clocksource, vcpus_matched; |
1563 | ||
1564 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1565 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
1566 | |
1567 | /* | |
1568 | * If the host uses TSC clock, then passthrough TSC as stable | |
1569 | * to the guest. | |
1570 | */ | |
b48aa97e | 1571 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
1572 | &ka->master_kernel_ns, |
1573 | &ka->master_cycle_now); | |
1574 | ||
16a96021 | 1575 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
54750f2c MT |
1576 | && !backwards_tsc_observed |
1577 | && !ka->boot_vcpu_runs_old_kvmclock; | |
b48aa97e | 1578 | |
d828199e MT |
1579 | if (ka->use_master_clock) |
1580 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1581 | ||
1582 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
1583 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
1584 | vcpus_matched); | |
d828199e MT |
1585 | #endif |
1586 | } | |
1587 | ||
2e762ff7 MT |
1588 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
1589 | { | |
1590 | #ifdef CONFIG_X86_64 | |
1591 | int i; | |
1592 | struct kvm_vcpu *vcpu; | |
1593 | struct kvm_arch *ka = &kvm->arch; | |
1594 | ||
1595 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1596 | kvm_make_mclock_inprogress_request(kvm); | |
1597 | /* no guest entries from this point */ | |
1598 | pvclock_update_vm_gtod_copy(kvm); | |
1599 | ||
1600 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 1601 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
1602 | |
1603 | /* guest entries allowed */ | |
1604 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1605 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1606 | ||
1607 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1608 | #endif | |
1609 | } | |
1610 | ||
34c238a1 | 1611 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 1612 | { |
d828199e | 1613 | unsigned long flags, this_tsc_khz; |
18068523 | 1614 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 1615 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 1616 | s64 kernel_ns; |
d828199e | 1617 | u64 tsc_timestamp, host_tsc; |
0b79459b | 1618 | struct pvclock_vcpu_time_info guest_hv_clock; |
51d59c6b | 1619 | u8 pvclock_flags; |
d828199e MT |
1620 | bool use_master_clock; |
1621 | ||
1622 | kernel_ns = 0; | |
1623 | host_tsc = 0; | |
18068523 | 1624 | |
d828199e MT |
1625 | /* |
1626 | * If the host uses TSC clock, then passthrough TSC as stable | |
1627 | * to the guest. | |
1628 | */ | |
1629 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1630 | use_master_clock = ka->use_master_clock; | |
1631 | if (use_master_clock) { | |
1632 | host_tsc = ka->master_cycle_now; | |
1633 | kernel_ns = ka->master_kernel_ns; | |
1634 | } | |
1635 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
1636 | |
1637 | /* Keep irq disabled to prevent changes to the clock */ | |
1638 | local_irq_save(flags); | |
89cbc767 | 1639 | this_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
c09664bb MT |
1640 | if (unlikely(this_tsc_khz == 0)) { |
1641 | local_irq_restore(flags); | |
1642 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1643 | return 1; | |
1644 | } | |
d828199e MT |
1645 | if (!use_master_clock) { |
1646 | host_tsc = native_read_tsc(); | |
1647 | kernel_ns = get_kernel_ns(); | |
1648 | } | |
1649 | ||
1650 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); | |
1651 | ||
c285545f ZA |
1652 | /* |
1653 | * We may have to catch up the TSC to match elapsed wall clock | |
1654 | * time for two reasons, even if kvmclock is used. | |
1655 | * 1) CPU could have been running below the maximum TSC rate | |
1656 | * 2) Broken TSC compensation resets the base at each VCPU | |
1657 | * entry to avoid unknown leaps of TSC even when running | |
1658 | * again on the same CPU. This may cause apparent elapsed | |
1659 | * time to disappear, and the guest to stand still or run | |
1660 | * very slowly. | |
1661 | */ | |
1662 | if (vcpu->tsc_catchup) { | |
1663 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1664 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 1665 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
1666 | tsc_timestamp = tsc; |
1667 | } | |
50d0a0f9 GH |
1668 | } |
1669 | ||
18068523 GOC |
1670 | local_irq_restore(flags); |
1671 | ||
0b79459b | 1672 | if (!vcpu->pv_time_enabled) |
c285545f | 1673 | return 0; |
18068523 | 1674 | |
e48672fa | 1675 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { |
5f4e3f88 ZA |
1676 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, |
1677 | &vcpu->hv_clock.tsc_shift, | |
1678 | &vcpu->hv_clock.tsc_to_system_mul); | |
e48672fa | 1679 | vcpu->hw_tsc_khz = this_tsc_khz; |
8cfdc000 ZA |
1680 | } |
1681 | ||
1682 | /* With all the info we got, fill in the values */ | |
1d5f066e | 1683 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 1684 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 1685 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 1686 | |
09a0c3f1 OH |
1687 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
1688 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1689 | return 0; | |
1690 | ||
5dca0d91 RK |
1691 | /* This VCPU is paused, but it's legal for a guest to read another |
1692 | * VCPU's kvmclock, so we really have to follow the specification where | |
1693 | * it says that version is odd if data is being modified, and even after | |
1694 | * it is consistent. | |
1695 | * | |
1696 | * Version field updates must be kept separate. This is because | |
1697 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
1698 | * writes within a string instruction are weakly ordered. So there | |
1699 | * are three writes overall. | |
1700 | * | |
1701 | * As a small optimization, only write the version field in the first | |
1702 | * and third write. The vcpu->pv_time cache is still valid, because the | |
1703 | * version field is the first in the struct. | |
18068523 | 1704 | */ |
5dca0d91 RK |
1705 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); |
1706 | ||
1707 | vcpu->hv_clock.version = guest_hv_clock.version + 1; | |
1708 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1709 | &vcpu->hv_clock, | |
1710 | sizeof(vcpu->hv_clock.version)); | |
1711 | ||
1712 | smp_wmb(); | |
78c0337a MT |
1713 | |
1714 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
0b79459b | 1715 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); |
78c0337a MT |
1716 | |
1717 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1718 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1719 | vcpu->pvclock_set_guest_stopped_request = false; | |
1720 | } | |
1721 | ||
b7e60c5a MT |
1722 | pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO; |
1723 | ||
d828199e MT |
1724 | /* If the host uses TSC clocksource, then it is stable */ |
1725 | if (use_master_clock) | |
1726 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1727 | ||
78c0337a MT |
1728 | vcpu->hv_clock.flags = pvclock_flags; |
1729 | ||
ce1a5e60 DM |
1730 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
1731 | ||
0b79459b AH |
1732 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
1733 | &vcpu->hv_clock, | |
1734 | sizeof(vcpu->hv_clock)); | |
5dca0d91 RK |
1735 | |
1736 | smp_wmb(); | |
1737 | ||
1738 | vcpu->hv_clock.version++; | |
1739 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1740 | &vcpu->hv_clock, | |
1741 | sizeof(vcpu->hv_clock.version)); | |
8cfdc000 | 1742 | return 0; |
c8076604 GH |
1743 | } |
1744 | ||
0061d53d MT |
1745 | /* |
1746 | * kvmclock updates which are isolated to a given vcpu, such as | |
1747 | * vcpu->cpu migration, should not allow system_timestamp from | |
1748 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1749 | * correction applies to one vcpu's system_timestamp but not | |
1750 | * the others. | |
1751 | * | |
1752 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
1753 | * We need to rate-limit these requests though, as they can |
1754 | * considerably slow guests that have a large number of vcpus. | |
1755 | * The time for a remote vcpu to update its kvmclock is bound | |
1756 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
1757 | */ |
1758 | ||
7e44e449 AJ |
1759 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
1760 | ||
1761 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
1762 | { |
1763 | int i; | |
7e44e449 AJ |
1764 | struct delayed_work *dwork = to_delayed_work(work); |
1765 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1766 | kvmclock_update_work); | |
1767 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
1768 | struct kvm_vcpu *vcpu; |
1769 | ||
1770 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 1771 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
1772 | kvm_vcpu_kick(vcpu); |
1773 | } | |
1774 | } | |
1775 | ||
7e44e449 AJ |
1776 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
1777 | { | |
1778 | struct kvm *kvm = v->kvm; | |
1779 | ||
105b21bb | 1780 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
1781 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
1782 | KVMCLOCK_UPDATE_DELAY); | |
1783 | } | |
1784 | ||
332967a3 AJ |
1785 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
1786 | ||
1787 | static void kvmclock_sync_fn(struct work_struct *work) | |
1788 | { | |
1789 | struct delayed_work *dwork = to_delayed_work(work); | |
1790 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
1791 | kvmclock_sync_work); | |
1792 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
1793 | ||
630994b3 MT |
1794 | if (!kvmclock_periodic_sync) |
1795 | return; | |
1796 | ||
332967a3 AJ |
1797 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
1798 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
1799 | KVMCLOCK_SYNC_PERIOD); | |
1800 | } | |
1801 | ||
9ba075a6 AK |
1802 | static bool msr_mtrr_valid(unsigned msr) |
1803 | { | |
1804 | switch (msr) { | |
1805 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1806 | case MSR_MTRRfix64K_00000: | |
1807 | case MSR_MTRRfix16K_80000: | |
1808 | case MSR_MTRRfix16K_A0000: | |
1809 | case MSR_MTRRfix4K_C0000: | |
1810 | case MSR_MTRRfix4K_C8000: | |
1811 | case MSR_MTRRfix4K_D0000: | |
1812 | case MSR_MTRRfix4K_D8000: | |
1813 | case MSR_MTRRfix4K_E0000: | |
1814 | case MSR_MTRRfix4K_E8000: | |
1815 | case MSR_MTRRfix4K_F0000: | |
1816 | case MSR_MTRRfix4K_F8000: | |
1817 | case MSR_MTRRdefType: | |
1818 | case MSR_IA32_CR_PAT: | |
1819 | return true; | |
1820 | case 0x2f8: | |
1821 | return true; | |
1822 | } | |
1823 | return false; | |
1824 | } | |
1825 | ||
d6289b93 MT |
1826 | static bool valid_pat_type(unsigned t) |
1827 | { | |
1828 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1829 | } | |
1830 | ||
1831 | static bool valid_mtrr_type(unsigned t) | |
1832 | { | |
1833 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1834 | } | |
1835 | ||
4566654b | 1836 | bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
d6289b93 MT |
1837 | { |
1838 | int i; | |
fd275235 | 1839 | u64 mask; |
d6289b93 MT |
1840 | |
1841 | if (!msr_mtrr_valid(msr)) | |
1842 | return false; | |
1843 | ||
1844 | if (msr == MSR_IA32_CR_PAT) { | |
1845 | for (i = 0; i < 8; i++) | |
1846 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1847 | return false; | |
1848 | return true; | |
1849 | } else if (msr == MSR_MTRRdefType) { | |
1850 | if (data & ~0xcff) | |
1851 | return false; | |
1852 | return valid_mtrr_type(data & 0xff); | |
1853 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1854 | for (i = 0; i < 8 ; i++) | |
1855 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1856 | return false; | |
1857 | return true; | |
1858 | } | |
1859 | ||
1860 | /* variable MTRRs */ | |
adfb5d27 WL |
1861 | WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); |
1862 | ||
fd275235 | 1863 | mask = (~0ULL) << cpuid_maxphyaddr(vcpu); |
d7a2a246 | 1864 | if ((msr & 1) == 0) { |
adfb5d27 | 1865 | /* MTRR base */ |
d7a2a246 WL |
1866 | if (!valid_mtrr_type(data & 0xff)) |
1867 | return false; | |
1868 | mask |= 0xf00; | |
1869 | } else | |
1870 | /* MTRR mask */ | |
1871 | mask |= 0x7ff; | |
1872 | if (data & mask) { | |
1873 | kvm_inject_gp(vcpu, 0); | |
1874 | return false; | |
1875 | } | |
1876 | ||
adfb5d27 | 1877 | return true; |
d6289b93 | 1878 | } |
4566654b | 1879 | EXPORT_SYMBOL_GPL(kvm_mtrr_valid); |
d6289b93 | 1880 | |
efdfe536 XG |
1881 | static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr) |
1882 | { | |
1883 | struct mtrr_state_type *mtrr_state = &vcpu->arch.mtrr_state; | |
1884 | unsigned char mtrr_enabled = mtrr_state->enabled; | |
1885 | gfn_t start, end, mask; | |
1886 | int index; | |
1887 | bool is_fixed = true; | |
1888 | ||
1889 | if (msr == MSR_IA32_CR_PAT || !tdp_enabled || | |
1890 | !kvm_arch_has_noncoherent_dma(vcpu->kvm)) | |
1891 | return; | |
1892 | ||
1893 | if (!(mtrr_enabled & 0x2) && msr != MSR_MTRRdefType) | |
1894 | return; | |
1895 | ||
1896 | switch (msr) { | |
1897 | case MSR_MTRRfix64K_00000: | |
1898 | start = 0x0; | |
1899 | end = 0x80000; | |
1900 | break; | |
1901 | case MSR_MTRRfix16K_80000: | |
1902 | start = 0x80000; | |
1903 | end = 0xa0000; | |
1904 | break; | |
1905 | case MSR_MTRRfix16K_A0000: | |
1906 | start = 0xa0000; | |
1907 | end = 0xc0000; | |
1908 | break; | |
1909 | case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000: | |
1910 | index = msr - MSR_MTRRfix4K_C0000; | |
1911 | start = 0xc0000 + index * (32 << 10); | |
1912 | end = start + (32 << 10); | |
1913 | break; | |
1914 | case MSR_MTRRdefType: | |
1915 | is_fixed = false; | |
1916 | start = 0x0; | |
1917 | end = ~0ULL; | |
1918 | break; | |
1919 | default: | |
1920 | /* variable range MTRRs. */ | |
1921 | is_fixed = false; | |
1922 | index = (msr - 0x200) / 2; | |
1923 | start = (((u64)mtrr_state->var_ranges[index].base_hi) << 32) + | |
1924 | (mtrr_state->var_ranges[index].base_lo & PAGE_MASK); | |
1925 | mask = (((u64)mtrr_state->var_ranges[index].mask_hi) << 32) + | |
1926 | (mtrr_state->var_ranges[index].mask_lo & PAGE_MASK); | |
1927 | mask |= ~0ULL << cpuid_maxphyaddr(vcpu); | |
1928 | ||
1929 | end = ((start & mask) | ~mask) + 1; | |
1930 | } | |
1931 | ||
1932 | if (is_fixed && !(mtrr_enabled & 0x1)) | |
1933 | return; | |
1934 | ||
1935 | kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end)); | |
1936 | } | |
1937 | ||
9ba075a6 AK |
1938 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1939 | { | |
0bed3b56 SY |
1940 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1941 | ||
4566654b | 1942 | if (!kvm_mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
1943 | return 1; |
1944 | ||
0bed3b56 SY |
1945 | if (msr == MSR_MTRRdefType) { |
1946 | vcpu->arch.mtrr_state.def_type = data; | |
1947 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1948 | } else if (msr == MSR_MTRRfix64K_00000) | |
1949 | p[0] = data; | |
1950 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1951 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1952 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1953 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1954 | else if (msr == MSR_IA32_CR_PAT) | |
1955 | vcpu->arch.pat = data; | |
1956 | else { /* Variable MTRRs */ | |
1957 | int idx, is_mtrr_mask; | |
1958 | u64 *pt; | |
1959 | ||
1960 | idx = (msr - 0x200) / 2; | |
1961 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1962 | if (!is_mtrr_mask) | |
1963 | pt = | |
1964 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1965 | else | |
1966 | pt = | |
1967 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1968 | *pt = data; | |
1969 | } | |
1970 | ||
efdfe536 | 1971 | update_mtrr(vcpu, msr); |
9ba075a6 AK |
1972 | return 0; |
1973 | } | |
15c4a640 | 1974 | |
890ca9ae | 1975 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 1976 | { |
890ca9ae HY |
1977 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1978 | unsigned bank_num = mcg_cap & 0xff; | |
1979 | ||
15c4a640 | 1980 | switch (msr) { |
15c4a640 | 1981 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 1982 | vcpu->arch.mcg_status = data; |
15c4a640 | 1983 | break; |
c7ac679c | 1984 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1985 | if (!(mcg_cap & MCG_CTL_P)) |
1986 | return 1; | |
1987 | if (data != 0 && data != ~(u64)0) | |
1988 | return -1; | |
1989 | vcpu->arch.mcg_ctl = data; | |
1990 | break; | |
1991 | default: | |
1992 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 1993 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 1994 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
1995 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
1996 | * some Linux kernels though clear bit 10 in bank 4 to | |
1997 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1998 | * this to avoid an uncatched #GP in the guest | |
1999 | */ | |
890ca9ae | 2000 | if ((offset & 0x3) == 0 && |
114be429 | 2001 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
2002 | return -1; |
2003 | vcpu->arch.mce_banks[offset] = data; | |
2004 | break; | |
2005 | } | |
2006 | return 1; | |
2007 | } | |
2008 | return 0; | |
2009 | } | |
2010 | ||
ffde22ac ES |
2011 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2012 | { | |
2013 | struct kvm *kvm = vcpu->kvm; | |
2014 | int lm = is_long_mode(vcpu); | |
2015 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2016 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2017 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2018 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2019 | u32 page_num = data & ~PAGE_MASK; | |
2020 | u64 page_addr = data & PAGE_MASK; | |
2021 | u8 *page; | |
2022 | int r; | |
2023 | ||
2024 | r = -E2BIG; | |
2025 | if (page_num >= blob_size) | |
2026 | goto out; | |
2027 | r = -ENOMEM; | |
ff5c2c03 SL |
2028 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
2029 | if (IS_ERR(page)) { | |
2030 | r = PTR_ERR(page); | |
ffde22ac | 2031 | goto out; |
ff5c2c03 | 2032 | } |
ffde22ac ES |
2033 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) |
2034 | goto out_free; | |
2035 | r = 0; | |
2036 | out_free: | |
2037 | kfree(page); | |
2038 | out: | |
2039 | return r; | |
2040 | } | |
2041 | ||
55cd8e5a GN |
2042 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
2043 | { | |
2044 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
2045 | } | |
2046 | ||
2047 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
2048 | { | |
2049 | bool r = false; | |
2050 | switch (msr) { | |
2051 | case HV_X64_MSR_GUEST_OS_ID: | |
2052 | case HV_X64_MSR_HYPERCALL: | |
e984097b VR |
2053 | case HV_X64_MSR_REFERENCE_TSC: |
2054 | case HV_X64_MSR_TIME_REF_COUNT: | |
55cd8e5a GN |
2055 | r = true; |
2056 | break; | |
2057 | } | |
2058 | ||
2059 | return r; | |
2060 | } | |
2061 | ||
2062 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2063 | { | |
2064 | struct kvm *kvm = vcpu->kvm; | |
2065 | ||
2066 | switch (msr) { | |
2067 | case HV_X64_MSR_GUEST_OS_ID: | |
2068 | kvm->arch.hv_guest_os_id = data; | |
2069 | /* setting guest os id to zero disables hypercall page */ | |
2070 | if (!kvm->arch.hv_guest_os_id) | |
2071 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
2072 | break; | |
2073 | case HV_X64_MSR_HYPERCALL: { | |
2074 | u64 gfn; | |
2075 | unsigned long addr; | |
2076 | u8 instructions[4]; | |
2077 | ||
2078 | /* if guest os id is not set hypercall should remain disabled */ | |
2079 | if (!kvm->arch.hv_guest_os_id) | |
2080 | break; | |
2081 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
2082 | kvm->arch.hv_hypercall = data; | |
2083 | break; | |
2084 | } | |
2085 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
2086 | addr = gfn_to_hva(kvm, gfn); | |
2087 | if (kvm_is_error_hva(addr)) | |
2088 | return 1; | |
2089 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
2090 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
8b0cedff | 2091 | if (__copy_to_user((void __user *)addr, instructions, 4)) |
55cd8e5a GN |
2092 | return 1; |
2093 | kvm->arch.hv_hypercall = data; | |
b94b64c9 | 2094 | mark_page_dirty(kvm, gfn); |
55cd8e5a GN |
2095 | break; |
2096 | } | |
e984097b VR |
2097 | case HV_X64_MSR_REFERENCE_TSC: { |
2098 | u64 gfn; | |
2099 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
2100 | memset(&tsc_ref, 0, sizeof(tsc_ref)); | |
2101 | kvm->arch.hv_tsc_page = data; | |
2102 | if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) | |
2103 | break; | |
2104 | gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; | |
e1fa108d | 2105 | if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, |
e984097b VR |
2106 | &tsc_ref, sizeof(tsc_ref))) |
2107 | return 1; | |
2108 | mark_page_dirty(kvm, gfn); | |
2109 | break; | |
2110 | } | |
55cd8e5a | 2111 | default: |
a737f256 CD |
2112 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
2113 | "data 0x%llx\n", msr, data); | |
55cd8e5a GN |
2114 | return 1; |
2115 | } | |
2116 | return 0; | |
2117 | } | |
2118 | ||
2119 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2120 | { | |
10388a07 GN |
2121 | switch (msr) { |
2122 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
b3af1e88 | 2123 | u64 gfn; |
10388a07 | 2124 | unsigned long addr; |
55cd8e5a | 2125 | |
10388a07 GN |
2126 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
2127 | vcpu->arch.hv_vapic = data; | |
b63cf42f MT |
2128 | if (kvm_lapic_enable_pv_eoi(vcpu, 0)) |
2129 | return 1; | |
10388a07 GN |
2130 | break; |
2131 | } | |
b3af1e88 VR |
2132 | gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; |
2133 | addr = gfn_to_hva(vcpu->kvm, gfn); | |
10388a07 GN |
2134 | if (kvm_is_error_hva(addr)) |
2135 | return 1; | |
8b0cedff | 2136 | if (__clear_user((void __user *)addr, PAGE_SIZE)) |
10388a07 GN |
2137 | return 1; |
2138 | vcpu->arch.hv_vapic = data; | |
b3af1e88 | 2139 | mark_page_dirty(vcpu->kvm, gfn); |
b63cf42f MT |
2140 | if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) |
2141 | return 1; | |
10388a07 GN |
2142 | break; |
2143 | } | |
2144 | case HV_X64_MSR_EOI: | |
2145 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
2146 | case HV_X64_MSR_ICR: | |
2147 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
2148 | case HV_X64_MSR_TPR: | |
2149 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
2150 | default: | |
a737f256 CD |
2151 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " |
2152 | "data 0x%llx\n", msr, data); | |
10388a07 GN |
2153 | return 1; |
2154 | } | |
2155 | ||
2156 | return 0; | |
55cd8e5a GN |
2157 | } |
2158 | ||
344d9588 GN |
2159 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2160 | { | |
2161 | gpa_t gpa = data & ~0x3f; | |
2162 | ||
4a969980 | 2163 | /* Bits 2:5 are reserved, Should be zero */ |
6adba527 | 2164 | if (data & 0x3c) |
344d9588 GN |
2165 | return 1; |
2166 | ||
2167 | vcpu->arch.apf.msr_val = data; | |
2168 | ||
2169 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2170 | kvm_clear_async_pf_completion_queue(vcpu); | |
2171 | kvm_async_pf_hash_reset(vcpu); | |
2172 | return 0; | |
2173 | } | |
2174 | ||
8f964525 AH |
2175 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
2176 | sizeof(u32))) | |
344d9588 GN |
2177 | return 1; |
2178 | ||
6adba527 | 2179 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
344d9588 GN |
2180 | kvm_async_pf_wakeup_all(vcpu); |
2181 | return 0; | |
2182 | } | |
2183 | ||
12f9a48f GC |
2184 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2185 | { | |
0b79459b | 2186 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2187 | } |
2188 | ||
c9aaa895 GC |
2189 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) |
2190 | { | |
2191 | u64 delta; | |
2192 | ||
2193 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2194 | return; | |
2195 | ||
2196 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
2197 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2198 | vcpu->arch.st.accum_steal = delta; | |
2199 | } | |
2200 | ||
2201 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
2202 | { | |
2203 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2204 | return; | |
2205 | ||
2206 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2207 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
2208 | return; | |
2209 | ||
2210 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
2211 | vcpu->arch.st.steal.version += 2; | |
2212 | vcpu->arch.st.accum_steal = 0; | |
2213 | ||
2214 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
2215 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
2216 | } | |
2217 | ||
8fe8ab46 | 2218 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2219 | { |
5753785f | 2220 | bool pr = false; |
8fe8ab46 WA |
2221 | u32 msr = msr_info->index; |
2222 | u64 data = msr_info->data; | |
5753785f | 2223 | |
15c4a640 | 2224 | switch (msr) { |
2e32b719 BP |
2225 | case MSR_AMD64_NB_CFG: |
2226 | case MSR_IA32_UCODE_REV: | |
2227 | case MSR_IA32_UCODE_WRITE: | |
2228 | case MSR_VM_HSAVE_PA: | |
2229 | case MSR_AMD64_PATCH_LOADER: | |
2230 | case MSR_AMD64_BU_CFG2: | |
2231 | break; | |
2232 | ||
15c4a640 | 2233 | case MSR_EFER: |
b69e8cae | 2234 | return set_efer(vcpu, data); |
8f1589d9 AP |
2235 | case MSR_K7_HWCR: |
2236 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2237 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2238 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
22d48b2d | 2239 | data &= ~(u64)0x40000; /* ignore Mc status write enable */ |
8f1589d9 | 2240 | if (data != 0) { |
a737f256 CD |
2241 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2242 | data); | |
8f1589d9 AP |
2243 | return 1; |
2244 | } | |
15c4a640 | 2245 | break; |
f7c6d140 AP |
2246 | case MSR_FAM10H_MMIO_CONF_BASE: |
2247 | if (data != 0) { | |
a737f256 CD |
2248 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2249 | "0x%llx\n", data); | |
f7c6d140 AP |
2250 | return 1; |
2251 | } | |
15c4a640 | 2252 | break; |
b5e2fec0 AG |
2253 | case MSR_IA32_DEBUGCTLMSR: |
2254 | if (!data) { | |
2255 | /* We support the non-activated case already */ | |
2256 | break; | |
2257 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2258 | /* Values other than LBR and BTF are vendor-specific, | |
2259 | thus reserved and should throw a #GP */ | |
2260 | return 1; | |
2261 | } | |
a737f256 CD |
2262 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2263 | __func__, data); | |
b5e2fec0 | 2264 | break; |
9ba075a6 AK |
2265 | case 0x200 ... 0x2ff: |
2266 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 | 2267 | case MSR_IA32_APICBASE: |
58cb628d | 2268 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2269 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2270 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2271 | case MSR_IA32_TSCDEADLINE: |
2272 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2273 | break; | |
ba904635 WA |
2274 | case MSR_IA32_TSC_ADJUST: |
2275 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2276 | if (!msr_info->host_initiated) { | |
d913b904 | 2277 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 WA |
2278 | kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); |
2279 | } | |
2280 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2281 | } | |
2282 | break; | |
15c4a640 | 2283 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 2284 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 2285 | break; |
64d60670 PB |
2286 | case MSR_IA32_SMBASE: |
2287 | if (!msr_info->host_initiated) | |
2288 | return 1; | |
2289 | vcpu->arch.smbase = data; | |
2290 | break; | |
11c6bffa | 2291 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2292 | case MSR_KVM_WALL_CLOCK: |
2293 | vcpu->kvm->arch.wall_clock = data; | |
2294 | kvm_write_wall_clock(vcpu->kvm, data); | |
2295 | break; | |
11c6bffa | 2296 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2297 | case MSR_KVM_SYSTEM_TIME: { |
0b79459b | 2298 | u64 gpa_offset; |
54750f2c MT |
2299 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2300 | ||
12f9a48f | 2301 | kvmclock_reset(vcpu); |
18068523 | 2302 | |
54750f2c MT |
2303 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2304 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2305 | ||
2306 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
2307 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, | |
2308 | &vcpu->requests); | |
2309 | ||
2310 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
b7e60c5a MT |
2311 | |
2312 | ka->kvmclock_offset = -get_kernel_ns(); | |
54750f2c MT |
2313 | } |
2314 | ||
18068523 | 2315 | vcpu->arch.time = data; |
0061d53d | 2316 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2317 | |
2318 | /* we verify if the enable bit is set... */ | |
2319 | if (!(data & 1)) | |
2320 | break; | |
2321 | ||
0b79459b | 2322 | gpa_offset = data & ~(PAGE_MASK | 1); |
18068523 | 2323 | |
0b79459b | 2324 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2325 | &vcpu->arch.pv_time, data & ~1ULL, |
2326 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2327 | vcpu->arch.pv_time_enabled = false; |
2328 | else | |
2329 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2330 | |
18068523 GOC |
2331 | break; |
2332 | } | |
344d9588 GN |
2333 | case MSR_KVM_ASYNC_PF_EN: |
2334 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2335 | return 1; | |
2336 | break; | |
c9aaa895 GC |
2337 | case MSR_KVM_STEAL_TIME: |
2338 | ||
2339 | if (unlikely(!sched_info_on())) | |
2340 | return 1; | |
2341 | ||
2342 | if (data & KVM_STEAL_RESERVED_MASK) | |
2343 | return 1; | |
2344 | ||
2345 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
8f964525 AH |
2346 | data & KVM_STEAL_VALID_BITS, |
2347 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2348 | return 1; |
2349 | ||
2350 | vcpu->arch.st.msr_val = data; | |
2351 | ||
2352 | if (!(data & KVM_MSR_ENABLED)) | |
2353 | break; | |
2354 | ||
2355 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2356 | ||
2357 | preempt_disable(); | |
2358 | accumulate_steal_time(vcpu); | |
2359 | preempt_enable(); | |
2360 | ||
2361 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2362 | ||
2363 | break; | |
ae7a2a3f MT |
2364 | case MSR_KVM_PV_EOI_EN: |
2365 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2366 | return 1; | |
2367 | break; | |
c9aaa895 | 2368 | |
890ca9ae HY |
2369 | case MSR_IA32_MCG_CTL: |
2370 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2371 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
890ca9ae | 2372 | return set_msr_mce(vcpu, msr, data); |
71db6023 AP |
2373 | |
2374 | /* Performance counters are not protected by a CPUID bit, | |
2375 | * so we should check all of them in the generic path for the sake of | |
2376 | * cross vendor migration. | |
2377 | * Writing a zero into the event select MSRs disables them, | |
2378 | * which we perfectly emulate ;-). Any other value should be at least | |
2379 | * reported, some guests depend on them. | |
2380 | */ | |
71db6023 AP |
2381 | case MSR_K7_EVNTSEL0: |
2382 | case MSR_K7_EVNTSEL1: | |
2383 | case MSR_K7_EVNTSEL2: | |
2384 | case MSR_K7_EVNTSEL3: | |
2385 | if (data != 0) | |
a737f256 CD |
2386 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2387 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 AP |
2388 | break; |
2389 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
2390 | * so we ignore writes to make it happy. | |
2391 | */ | |
71db6023 AP |
2392 | case MSR_K7_PERFCTR0: |
2393 | case MSR_K7_PERFCTR1: | |
2394 | case MSR_K7_PERFCTR2: | |
2395 | case MSR_K7_PERFCTR3: | |
a737f256 CD |
2396 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " |
2397 | "0x%x data 0x%llx\n", msr, data); | |
71db6023 | 2398 | break; |
5753785f GN |
2399 | case MSR_P6_PERFCTR0: |
2400 | case MSR_P6_PERFCTR1: | |
2401 | pr = true; | |
2402 | case MSR_P6_EVNTSEL0: | |
2403 | case MSR_P6_EVNTSEL1: | |
2404 | if (kvm_pmu_msr(vcpu, msr)) | |
afd80d85 | 2405 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2406 | |
2407 | if (pr || data != 0) | |
a737f256 CD |
2408 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2409 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2410 | break; |
84e0cefa JS |
2411 | case MSR_K7_CLK_CTL: |
2412 | /* | |
2413 | * Ignore all writes to this no longer documented MSR. | |
2414 | * Writes are only relevant for old K7 processors, | |
2415 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2416 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2417 | * affected processor models on the command line, hence |
2418 | * the need to ignore the workaround. | |
2419 | */ | |
2420 | break; | |
55cd8e5a GN |
2421 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
2422 | if (kvm_hv_msr_partition_wide(msr)) { | |
2423 | int r; | |
2424 | mutex_lock(&vcpu->kvm->lock); | |
2425 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
2426 | mutex_unlock(&vcpu->kvm->lock); | |
2427 | return r; | |
2428 | } else | |
2429 | return set_msr_hyperv(vcpu, msr, data); | |
2430 | break; | |
91c9c3ed | 2431 | case MSR_IA32_BBL_CR_CTL3: |
2432 | /* Drop writes to this legacy MSR -- see rdmsr | |
2433 | * counterpart for further detail. | |
2434 | */ | |
a737f256 | 2435 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); |
91c9c3ed | 2436 | break; |
2b036c6b BO |
2437 | case MSR_AMD64_OSVW_ID_LENGTH: |
2438 | if (!guest_cpuid_has_osvw(vcpu)) | |
2439 | return 1; | |
2440 | vcpu->arch.osvw.length = data; | |
2441 | break; | |
2442 | case MSR_AMD64_OSVW_STATUS: | |
2443 | if (!guest_cpuid_has_osvw(vcpu)) | |
2444 | return 1; | |
2445 | vcpu->arch.osvw.status = data; | |
2446 | break; | |
15c4a640 | 2447 | default: |
ffde22ac ES |
2448 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2449 | return xen_hvm_config(vcpu, data); | |
f5132b01 | 2450 | if (kvm_pmu_msr(vcpu, msr)) |
afd80d85 | 2451 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2452 | if (!ignore_msrs) { |
a737f256 CD |
2453 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", |
2454 | msr, data); | |
ed85c068 AP |
2455 | return 1; |
2456 | } else { | |
a737f256 CD |
2457 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", |
2458 | msr, data); | |
ed85c068 AP |
2459 | break; |
2460 | } | |
15c4a640 CO |
2461 | } |
2462 | return 0; | |
2463 | } | |
2464 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2465 | ||
2466 | ||
2467 | /* | |
2468 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2469 | * Returns 0 on success, non-0 otherwise. | |
2470 | * Assumes vcpu_load() was already called. | |
2471 | */ | |
609e36d3 | 2472 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 2473 | { |
609e36d3 | 2474 | return kvm_x86_ops->get_msr(vcpu, msr); |
15c4a640 | 2475 | } |
ff651cb6 | 2476 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2477 | |
9ba075a6 AK |
2478 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2479 | { | |
0bed3b56 SY |
2480 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
2481 | ||
9ba075a6 AK |
2482 | if (!msr_mtrr_valid(msr)) |
2483 | return 1; | |
2484 | ||
0bed3b56 SY |
2485 | if (msr == MSR_MTRRdefType) |
2486 | *pdata = vcpu->arch.mtrr_state.def_type + | |
2487 | (vcpu->arch.mtrr_state.enabled << 10); | |
2488 | else if (msr == MSR_MTRRfix64K_00000) | |
2489 | *pdata = p[0]; | |
2490 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
2491 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
2492 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
2493 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
2494 | else if (msr == MSR_IA32_CR_PAT) | |
2495 | *pdata = vcpu->arch.pat; | |
2496 | else { /* Variable MTRRs */ | |
2497 | int idx, is_mtrr_mask; | |
2498 | u64 *pt; | |
2499 | ||
2500 | idx = (msr - 0x200) / 2; | |
2501 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
2502 | if (!is_mtrr_mask) | |
2503 | pt = | |
2504 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
2505 | else | |
2506 | pt = | |
2507 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
2508 | *pdata = *pt; | |
2509 | } | |
2510 | ||
9ba075a6 AK |
2511 | return 0; |
2512 | } | |
2513 | ||
890ca9ae | 2514 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
2515 | { |
2516 | u64 data; | |
890ca9ae HY |
2517 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2518 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2519 | |
2520 | switch (msr) { | |
15c4a640 CO |
2521 | case MSR_IA32_P5_MC_ADDR: |
2522 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2523 | data = 0; |
2524 | break; | |
15c4a640 | 2525 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2526 | data = vcpu->arch.mcg_cap; |
2527 | break; | |
c7ac679c | 2528 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
2529 | if (!(mcg_cap & MCG_CTL_P)) |
2530 | return 1; | |
2531 | data = vcpu->arch.mcg_ctl; | |
2532 | break; | |
2533 | case MSR_IA32_MCG_STATUS: | |
2534 | data = vcpu->arch.mcg_status; | |
2535 | break; | |
2536 | default: | |
2537 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2538 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2539 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2540 | data = vcpu->arch.mce_banks[offset]; | |
2541 | break; | |
2542 | } | |
2543 | return 1; | |
2544 | } | |
2545 | *pdata = data; | |
2546 | return 0; | |
2547 | } | |
2548 | ||
55cd8e5a GN |
2549 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
2550 | { | |
2551 | u64 data = 0; | |
2552 | struct kvm *kvm = vcpu->kvm; | |
2553 | ||
2554 | switch (msr) { | |
2555 | case HV_X64_MSR_GUEST_OS_ID: | |
2556 | data = kvm->arch.hv_guest_os_id; | |
2557 | break; | |
2558 | case HV_X64_MSR_HYPERCALL: | |
2559 | data = kvm->arch.hv_hypercall; | |
2560 | break; | |
e984097b VR |
2561 | case HV_X64_MSR_TIME_REF_COUNT: { |
2562 | data = | |
2563 | div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); | |
2564 | break; | |
2565 | } | |
2566 | case HV_X64_MSR_REFERENCE_TSC: | |
2567 | data = kvm->arch.hv_tsc_page; | |
2568 | break; | |
55cd8e5a | 2569 | default: |
a737f256 | 2570 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2571 | return 1; |
2572 | } | |
2573 | ||
2574 | *pdata = data; | |
2575 | return 0; | |
2576 | } | |
2577 | ||
2578 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2579 | { | |
2580 | u64 data = 0; | |
2581 | ||
2582 | switch (msr) { | |
2583 | case HV_X64_MSR_VP_INDEX: { | |
2584 | int r; | |
2585 | struct kvm_vcpu *v; | |
684851a1 TY |
2586 | kvm_for_each_vcpu(r, v, vcpu->kvm) { |
2587 | if (v == vcpu) { | |
55cd8e5a | 2588 | data = r; |
684851a1 TY |
2589 | break; |
2590 | } | |
2591 | } | |
55cd8e5a GN |
2592 | break; |
2593 | } | |
10388a07 GN |
2594 | case HV_X64_MSR_EOI: |
2595 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
2596 | case HV_X64_MSR_ICR: | |
2597 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
2598 | case HV_X64_MSR_TPR: | |
2599 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
14fa67ee | 2600 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
d1613ad5 MW |
2601 | data = vcpu->arch.hv_vapic; |
2602 | break; | |
55cd8e5a | 2603 | default: |
a737f256 | 2604 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); |
55cd8e5a GN |
2605 | return 1; |
2606 | } | |
2607 | *pdata = data; | |
2608 | return 0; | |
2609 | } | |
2610 | ||
609e36d3 | 2611 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae HY |
2612 | { |
2613 | u64 data; | |
2614 | ||
609e36d3 | 2615 | switch (msr_info->index) { |
890ca9ae | 2616 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2617 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2618 | case MSR_IA32_DEBUGCTLMSR: |
2619 | case MSR_IA32_LASTBRANCHFROMIP: | |
2620 | case MSR_IA32_LASTBRANCHTOIP: | |
2621 | case MSR_IA32_LASTINTFROMIP: | |
2622 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
2623 | case MSR_K8_SYSCFG: |
2624 | case MSR_K7_HWCR: | |
61a6bd67 | 2625 | case MSR_VM_HSAVE_PA: |
9e699624 | 2626 | case MSR_K7_EVNTSEL0: |
dc9b2d93 WH |
2627 | case MSR_K7_EVNTSEL1: |
2628 | case MSR_K7_EVNTSEL2: | |
2629 | case MSR_K7_EVNTSEL3: | |
1f3ee616 | 2630 | case MSR_K7_PERFCTR0: |
dc9b2d93 WH |
2631 | case MSR_K7_PERFCTR1: |
2632 | case MSR_K7_PERFCTR2: | |
2633 | case MSR_K7_PERFCTR3: | |
1fdbd48c | 2634 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2635 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2636 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2637 | case MSR_AMD64_BU_CFG2: |
609e36d3 | 2638 | msr_info->data = 0; |
15c4a640 | 2639 | break; |
5753785f GN |
2640 | case MSR_P6_PERFCTR0: |
2641 | case MSR_P6_PERFCTR1: | |
2642 | case MSR_P6_EVNTSEL0: | |
2643 | case MSR_P6_EVNTSEL1: | |
609e36d3 PB |
2644 | if (kvm_pmu_msr(vcpu, msr_info->index)) |
2645 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); | |
2646 | msr_info->data = 0; | |
5753785f | 2647 | break; |
742bc670 | 2648 | case MSR_IA32_UCODE_REV: |
609e36d3 | 2649 | msr_info->data = 0x100000000ULL; |
742bc670 | 2650 | break; |
9ba075a6 | 2651 | case MSR_MTRRcap: |
609e36d3 | 2652 | msr_info->data = 0x500 | KVM_NR_VAR_MTRR; |
9ba075a6 AK |
2653 | break; |
2654 | case 0x200 ... 0x2ff: | |
609e36d3 | 2655 | return get_msr_mtrr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 2656 | case 0xcd: /* fsb frequency */ |
609e36d3 | 2657 | msr_info->data = 3; |
15c4a640 | 2658 | break; |
7b914098 JS |
2659 | /* |
2660 | * MSR_EBC_FREQUENCY_ID | |
2661 | * Conservative value valid for even the basic CPU models. | |
2662 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2663 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2664 | * and 266MHz for model 3, or 4. Set Core Clock | |
2665 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2666 | * 31:24) even though these are only valid for CPU | |
2667 | * models > 2, however guests may end up dividing or | |
2668 | * multiplying by zero otherwise. | |
2669 | */ | |
2670 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 2671 | msr_info->data = 1 << 24; |
7b914098 | 2672 | break; |
15c4a640 | 2673 | case MSR_IA32_APICBASE: |
609e36d3 | 2674 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 2675 | break; |
0105d1a5 | 2676 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 2677 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 2678 | break; |
a3e06bbe | 2679 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 2680 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 2681 | break; |
ba904635 | 2682 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 2683 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 2684 | break; |
15c4a640 | 2685 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 2686 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2687 | break; |
64d60670 PB |
2688 | case MSR_IA32_SMBASE: |
2689 | if (!msr_info->host_initiated) | |
2690 | return 1; | |
2691 | msr_info->data = vcpu->arch.smbase; | |
2692 | break; | |
847f0ad8 AG |
2693 | case MSR_IA32_PERF_STATUS: |
2694 | /* TSC increment by tick */ | |
609e36d3 | 2695 | msr_info->data = 1000ULL; |
847f0ad8 AG |
2696 | /* CPU multiplier */ |
2697 | data |= (((uint64_t)4ULL) << 40); | |
2698 | break; | |
15c4a640 | 2699 | case MSR_EFER: |
609e36d3 | 2700 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 2701 | break; |
18068523 | 2702 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2703 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 2704 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
2705 | break; |
2706 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2707 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 2708 | msr_info->data = vcpu->arch.time; |
18068523 | 2709 | break; |
344d9588 | 2710 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 2711 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 2712 | break; |
c9aaa895 | 2713 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 2714 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 2715 | break; |
1d92128f | 2716 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 2717 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 2718 | break; |
890ca9ae HY |
2719 | case MSR_IA32_P5_MC_ADDR: |
2720 | case MSR_IA32_P5_MC_TYPE: | |
2721 | case MSR_IA32_MCG_CAP: | |
2722 | case MSR_IA32_MCG_CTL: | |
2723 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2724 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
609e36d3 | 2725 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data); |
84e0cefa JS |
2726 | case MSR_K7_CLK_CTL: |
2727 | /* | |
2728 | * Provide expected ramp-up count for K7. All other | |
2729 | * are set to zero, indicating minimum divisors for | |
2730 | * every field. | |
2731 | * | |
2732 | * This prevents guest kernels on AMD host with CPU | |
2733 | * type 6, model 8 and higher from exploding due to | |
2734 | * the rdmsr failing. | |
2735 | */ | |
609e36d3 | 2736 | msr_info->data = 0x20000000; |
84e0cefa | 2737 | break; |
55cd8e5a | 2738 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
609e36d3 | 2739 | if (kvm_hv_msr_partition_wide(msr_info->index)) { |
55cd8e5a GN |
2740 | int r; |
2741 | mutex_lock(&vcpu->kvm->lock); | |
609e36d3 | 2742 | r = get_msr_hyperv_pw(vcpu, msr_info->index, &msr_info->data); |
55cd8e5a GN |
2743 | mutex_unlock(&vcpu->kvm->lock); |
2744 | return r; | |
2745 | } else | |
609e36d3 | 2746 | return get_msr_hyperv(vcpu, msr_info->index, &msr_info->data); |
55cd8e5a | 2747 | break; |
91c9c3ed | 2748 | case MSR_IA32_BBL_CR_CTL3: |
2749 | /* This legacy MSR exists but isn't fully documented in current | |
2750 | * silicon. It is however accessed by winxp in very narrow | |
2751 | * scenarios where it sets bit #19, itself documented as | |
2752 | * a "reserved" bit. Best effort attempt to source coherent | |
2753 | * read data here should the balance of the register be | |
2754 | * interpreted by the guest: | |
2755 | * | |
2756 | * L2 cache control register 3: 64GB range, 256KB size, | |
2757 | * enabled, latency 0x1, configured | |
2758 | */ | |
609e36d3 | 2759 | msr_info->data = 0xbe702111; |
91c9c3ed | 2760 | break; |
2b036c6b BO |
2761 | case MSR_AMD64_OSVW_ID_LENGTH: |
2762 | if (!guest_cpuid_has_osvw(vcpu)) | |
2763 | return 1; | |
609e36d3 | 2764 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
2765 | break; |
2766 | case MSR_AMD64_OSVW_STATUS: | |
2767 | if (!guest_cpuid_has_osvw(vcpu)) | |
2768 | return 1; | |
609e36d3 | 2769 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 2770 | break; |
15c4a640 | 2771 | default: |
609e36d3 PB |
2772 | if (kvm_pmu_msr(vcpu, msr_info->index)) |
2773 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); | |
ed85c068 | 2774 | if (!ignore_msrs) { |
609e36d3 | 2775 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); |
ed85c068 AP |
2776 | return 1; |
2777 | } else { | |
609e36d3 PB |
2778 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); |
2779 | msr_info->data = 0; | |
ed85c068 AP |
2780 | } |
2781 | break; | |
15c4a640 | 2782 | } |
15c4a640 CO |
2783 | return 0; |
2784 | } | |
2785 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2786 | ||
313a3dc7 CO |
2787 | /* |
2788 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2789 | * | |
2790 | * @return number of msrs set successfully. | |
2791 | */ | |
2792 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2793 | struct kvm_msr_entry *entries, | |
2794 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2795 | unsigned index, u64 *data)) | |
2796 | { | |
f656ce01 | 2797 | int i, idx; |
313a3dc7 | 2798 | |
f656ce01 | 2799 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
2800 | for (i = 0; i < msrs->nmsrs; ++i) |
2801 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2802 | break; | |
f656ce01 | 2803 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 2804 | |
313a3dc7 CO |
2805 | return i; |
2806 | } | |
2807 | ||
2808 | /* | |
2809 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2810 | * | |
2811 | * @return number of msrs set successfully. | |
2812 | */ | |
2813 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2814 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2815 | unsigned index, u64 *data), | |
2816 | int writeback) | |
2817 | { | |
2818 | struct kvm_msrs msrs; | |
2819 | struct kvm_msr_entry *entries; | |
2820 | int r, n; | |
2821 | unsigned size; | |
2822 | ||
2823 | r = -EFAULT; | |
2824 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2825 | goto out; | |
2826 | ||
2827 | r = -E2BIG; | |
2828 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2829 | goto out; | |
2830 | ||
313a3dc7 | 2831 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
2832 | entries = memdup_user(user_msrs->entries, size); |
2833 | if (IS_ERR(entries)) { | |
2834 | r = PTR_ERR(entries); | |
313a3dc7 | 2835 | goto out; |
ff5c2c03 | 2836 | } |
313a3dc7 CO |
2837 | |
2838 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2839 | if (r < 0) | |
2840 | goto out_free; | |
2841 | ||
2842 | r = -EFAULT; | |
2843 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2844 | goto out_free; | |
2845 | ||
2846 | r = n; | |
2847 | ||
2848 | out_free: | |
7a73c028 | 2849 | kfree(entries); |
313a3dc7 CO |
2850 | out: |
2851 | return r; | |
2852 | } | |
2853 | ||
784aa3d7 | 2854 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 ZX |
2855 | { |
2856 | int r; | |
2857 | ||
2858 | switch (ext) { | |
2859 | case KVM_CAP_IRQCHIP: | |
2860 | case KVM_CAP_HLT: | |
2861 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 2862 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 2863 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 2864 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 2865 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 2866 | case KVM_CAP_PIT: |
a28e4f5a | 2867 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 2868 | case KVM_CAP_MP_STATE: |
ed848624 | 2869 | case KVM_CAP_SYNC_MMU: |
a355c85c | 2870 | case KVM_CAP_USER_NMI: |
52d939a0 | 2871 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 2872 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 2873 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 2874 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 2875 | case KVM_CAP_PIT2: |
e9f42757 | 2876 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 2877 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 2878 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 2879 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 2880 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 2881 | case KVM_CAP_HYPERV: |
10388a07 | 2882 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 2883 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 2884 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 2885 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 2886 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 2887 | case KVM_CAP_XSAVE: |
344d9588 | 2888 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 2889 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 2890 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 2891 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 2892 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 2893 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 2894 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 NA |
2895 | case KVM_CAP_ENABLE_CAP_VM: |
2896 | case KVM_CAP_DISABLE_QUIRKS: | |
2a5bab10 AW |
2897 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
2898 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2899 | case KVM_CAP_PCI_2_3: | |
2900 | #endif | |
018d00d2 ZX |
2901 | r = 1; |
2902 | break; | |
542472b5 LV |
2903 | case KVM_CAP_COALESCED_MMIO: |
2904 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2905 | break; | |
774ead3a AK |
2906 | case KVM_CAP_VAPIC: |
2907 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2908 | break; | |
f725230a | 2909 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
2910 | r = KVM_SOFT_MAX_VCPUS; |
2911 | break; | |
2912 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
2913 | r = KVM_MAX_VCPUS; |
2914 | break; | |
a988b910 | 2915 | case KVM_CAP_NR_MEMSLOTS: |
bbacc0c1 | 2916 | r = KVM_USER_MEM_SLOTS; |
a988b910 | 2917 | break; |
a68a6a72 MT |
2918 | case KVM_CAP_PV_MMU: /* obsolete */ |
2919 | r = 0; | |
2f333bcb | 2920 | break; |
4cee4b72 | 2921 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT |
62c476c7 | 2922 | case KVM_CAP_IOMMU: |
a1b60c1c | 2923 | r = iommu_present(&pci_bus_type); |
62c476c7 | 2924 | break; |
4cee4b72 | 2925 | #endif |
890ca9ae HY |
2926 | case KVM_CAP_MCE: |
2927 | r = KVM_MAX_MCE_BANKS; | |
2928 | break; | |
2d5b5a66 SY |
2929 | case KVM_CAP_XCRS: |
2930 | r = cpu_has_xsave; | |
2931 | break; | |
92a1f12d JR |
2932 | case KVM_CAP_TSC_CONTROL: |
2933 | r = kvm_has_tsc_control; | |
2934 | break; | |
018d00d2 ZX |
2935 | default: |
2936 | r = 0; | |
2937 | break; | |
2938 | } | |
2939 | return r; | |
2940 | ||
2941 | } | |
2942 | ||
043405e1 CO |
2943 | long kvm_arch_dev_ioctl(struct file *filp, |
2944 | unsigned int ioctl, unsigned long arg) | |
2945 | { | |
2946 | void __user *argp = (void __user *)arg; | |
2947 | long r; | |
2948 | ||
2949 | switch (ioctl) { | |
2950 | case KVM_GET_MSR_INDEX_LIST: { | |
2951 | struct kvm_msr_list __user *user_msr_list = argp; | |
2952 | struct kvm_msr_list msr_list; | |
2953 | unsigned n; | |
2954 | ||
2955 | r = -EFAULT; | |
2956 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2957 | goto out; | |
2958 | n = msr_list.nmsrs; | |
62ef68bb | 2959 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
043405e1 CO |
2960 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) |
2961 | goto out; | |
2962 | r = -E2BIG; | |
e125e7b6 | 2963 | if (n < msr_list.nmsrs) |
043405e1 CO |
2964 | goto out; |
2965 | r = -EFAULT; | |
2966 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2967 | num_msrs_to_save * sizeof(u32))) | |
2968 | goto out; | |
e125e7b6 | 2969 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 2970 | &emulated_msrs, |
62ef68bb | 2971 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
2972 | goto out; |
2973 | r = 0; | |
2974 | break; | |
2975 | } | |
9c15bb1d BP |
2976 | case KVM_GET_SUPPORTED_CPUID: |
2977 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
2978 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
2979 | struct kvm_cpuid2 cpuid; | |
2980 | ||
2981 | r = -EFAULT; | |
2982 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2983 | goto out; | |
9c15bb1d BP |
2984 | |
2985 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2986 | ioctl); | |
674eea0f AK |
2987 | if (r) |
2988 | goto out; | |
2989 | ||
2990 | r = -EFAULT; | |
2991 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2992 | goto out; | |
2993 | r = 0; | |
2994 | break; | |
2995 | } | |
890ca9ae HY |
2996 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
2997 | u64 mce_cap; | |
2998 | ||
2999 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
3000 | r = -EFAULT; | |
3001 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
3002 | goto out; | |
3003 | r = 0; | |
3004 | break; | |
3005 | } | |
043405e1 CO |
3006 | default: |
3007 | r = -EINVAL; | |
3008 | } | |
3009 | out: | |
3010 | return r; | |
3011 | } | |
3012 | ||
f5f48ee1 SY |
3013 | static void wbinvd_ipi(void *garbage) |
3014 | { | |
3015 | wbinvd(); | |
3016 | } | |
3017 | ||
3018 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3019 | { | |
e0f0bbc5 | 3020 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3021 | } |
3022 | ||
313a3dc7 CO |
3023 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3024 | { | |
f5f48ee1 SY |
3025 | /* Address WBINVD may be executed by guest */ |
3026 | if (need_emulate_wbinvd(vcpu)) { | |
3027 | if (kvm_x86_ops->has_wbinvd_exit()) | |
3028 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
3029 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3030 | smp_call_function_single(vcpu->cpu, | |
3031 | wbinvd_ipi, NULL, 1); | |
3032 | } | |
3033 | ||
313a3dc7 | 3034 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 3035 | |
0dd6a6ed ZA |
3036 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3037 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3038 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3039 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3040 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3041 | } |
8f6055cb | 3042 | |
48434c20 | 3043 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { |
6f526ec5 ZA |
3044 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
3045 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
e48672fa ZA |
3046 | if (tsc_delta < 0) |
3047 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
c285545f | 3048 | if (check_tsc_unstable()) { |
b183aa58 ZA |
3049 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, |
3050 | vcpu->arch.last_guest_tsc); | |
3051 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
c285545f | 3052 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3053 | } |
d98d07ca MT |
3054 | /* |
3055 | * On a host with synchronized TSC, there is no need to update | |
3056 | * kvmclock on vcpu->cpu migration | |
3057 | */ | |
3058 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3059 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f ZA |
3060 | if (vcpu->cpu != cpu) |
3061 | kvm_migrate_timers(vcpu); | |
e48672fa | 3062 | vcpu->cpu = cpu; |
6b7d7e76 | 3063 | } |
c9aaa895 GC |
3064 | |
3065 | accumulate_steal_time(vcpu); | |
3066 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
313a3dc7 CO |
3067 | } |
3068 | ||
3069 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
3070 | { | |
02daab21 | 3071 | kvm_x86_ops->vcpu_put(vcpu); |
1c11e713 | 3072 | kvm_put_guest_fpu(vcpu); |
6f526ec5 | 3073 | vcpu->arch.last_host_tsc = native_read_tsc(); |
313a3dc7 CO |
3074 | } |
3075 | ||
313a3dc7 CO |
3076 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
3077 | struct kvm_lapic_state *s) | |
3078 | { | |
5a71785d | 3079 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
ad312c7c | 3080 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
3081 | |
3082 | return 0; | |
3083 | } | |
3084 | ||
3085 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
3086 | struct kvm_lapic_state *s) | |
3087 | { | |
64eb0620 | 3088 | kvm_apic_post_state_restore(vcpu, s); |
cb142eb7 | 3089 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
3090 | |
3091 | return 0; | |
3092 | } | |
3093 | ||
f77bc6a4 ZX |
3094 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
3095 | struct kvm_interrupt *irq) | |
3096 | { | |
02cdb50f | 3097 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 ZX |
3098 | return -EINVAL; |
3099 | if (irqchip_in_kernel(vcpu->kvm)) | |
3100 | return -ENXIO; | |
f77bc6a4 | 3101 | |
66fd3f7f | 3102 | kvm_queue_interrupt(vcpu, irq->irq, false); |
3842d135 | 3103 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 | 3104 | |
f77bc6a4 ZX |
3105 | return 0; |
3106 | } | |
3107 | ||
c4abb7c9 JK |
3108 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
3109 | { | |
c4abb7c9 | 3110 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
3111 | |
3112 | return 0; | |
3113 | } | |
3114 | ||
f077825a PB |
3115 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
3116 | { | |
64d60670 PB |
3117 | kvm_make_request(KVM_REQ_SMI, vcpu); |
3118 | ||
f077825a PB |
3119 | return 0; |
3120 | } | |
3121 | ||
b209749f AK |
3122 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
3123 | struct kvm_tpr_access_ctl *tac) | |
3124 | { | |
3125 | if (tac->flags) | |
3126 | return -EINVAL; | |
3127 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
3128 | return 0; | |
3129 | } | |
3130 | ||
890ca9ae HY |
3131 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
3132 | u64 mcg_cap) | |
3133 | { | |
3134 | int r; | |
3135 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3136 | ||
3137 | r = -EINVAL; | |
a9e38c3e | 3138 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
3139 | goto out; |
3140 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
3141 | goto out; | |
3142 | r = 0; | |
3143 | vcpu->arch.mcg_cap = mcg_cap; | |
3144 | /* Init IA32_MCG_CTL to all 1s */ | |
3145 | if (mcg_cap & MCG_CTL_P) | |
3146 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3147 | /* Init IA32_MCi_CTL to all 1s */ | |
3148 | for (bank = 0; bank < bank_num; bank++) | |
3149 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
3150 | out: | |
3151 | return r; | |
3152 | } | |
3153 | ||
3154 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3155 | struct kvm_x86_mce *mce) | |
3156 | { | |
3157 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3158 | unsigned bank_num = mcg_cap & 0xff; | |
3159 | u64 *banks = vcpu->arch.mce_banks; | |
3160 | ||
3161 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3162 | return -EINVAL; | |
3163 | /* | |
3164 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3165 | * reporting is disabled | |
3166 | */ | |
3167 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3168 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3169 | return 0; | |
3170 | banks += 4 * mce->bank; | |
3171 | /* | |
3172 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3173 | * reporting is disabled for the bank | |
3174 | */ | |
3175 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3176 | return 0; | |
3177 | if (mce->status & MCI_STATUS_UC) { | |
3178 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3179 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3180 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3181 | return 0; |
3182 | } | |
3183 | if (banks[1] & MCI_STATUS_VAL) | |
3184 | mce->status |= MCI_STATUS_OVER; | |
3185 | banks[2] = mce->addr; | |
3186 | banks[3] = mce->misc; | |
3187 | vcpu->arch.mcg_status = mce->mcg_status; | |
3188 | banks[1] = mce->status; | |
3189 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3190 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3191 | || !(banks[1] & MCI_STATUS_UC)) { | |
3192 | if (banks[1] & MCI_STATUS_VAL) | |
3193 | mce->status |= MCI_STATUS_OVER; | |
3194 | banks[2] = mce->addr; | |
3195 | banks[3] = mce->misc; | |
3196 | banks[1] = mce->status; | |
3197 | } else | |
3198 | banks[1] |= MCI_STATUS_OVER; | |
3199 | return 0; | |
3200 | } | |
3201 | ||
3cfc3092 JK |
3202 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3203 | struct kvm_vcpu_events *events) | |
3204 | { | |
7460fb4a | 3205 | process_nmi(vcpu); |
03b82a30 JK |
3206 | events->exception.injected = |
3207 | vcpu->arch.exception.pending && | |
3208 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
3209 | events->exception.nr = vcpu->arch.exception.nr; |
3210 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
97e69aa6 | 3211 | events->exception.pad = 0; |
3cfc3092 JK |
3212 | events->exception.error_code = vcpu->arch.exception.error_code; |
3213 | ||
03b82a30 JK |
3214 | events->interrupt.injected = |
3215 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 3216 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3217 | events->interrupt.soft = 0; |
37ccdcbe | 3218 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3219 | |
3220 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3221 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3222 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3223 | events->nmi.pad = 0; |
3cfc3092 | 3224 | |
66450a21 | 3225 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3226 | |
f077825a PB |
3227 | events->smi.smm = is_smm(vcpu); |
3228 | events->smi.pending = vcpu->arch.smi_pending; | |
3229 | events->smi.smm_inside_nmi = | |
3230 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
3231 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
3232 | ||
dab4b911 | 3233 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
3234 | | KVM_VCPUEVENT_VALID_SHADOW |
3235 | | KVM_VCPUEVENT_VALID_SMM); | |
97e69aa6 | 3236 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3237 | } |
3238 | ||
3239 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
3240 | struct kvm_vcpu_events *events) | |
3241 | { | |
dab4b911 | 3242 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3243 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a PB |
3244 | | KVM_VCPUEVENT_VALID_SHADOW |
3245 | | KVM_VCPUEVENT_VALID_SMM)) | |
3cfc3092 JK |
3246 | return -EINVAL; |
3247 | ||
7460fb4a | 3248 | process_nmi(vcpu); |
3cfc3092 JK |
3249 | vcpu->arch.exception.pending = events->exception.injected; |
3250 | vcpu->arch.exception.nr = events->exception.nr; | |
3251 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3252 | vcpu->arch.exception.error_code = events->exception.error_code; | |
3253 | ||
3254 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
3255 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
3256 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3257 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3258 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3259 | events->interrupt.shadow); | |
3cfc3092 JK |
3260 | |
3261 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3262 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3263 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3264 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3265 | ||
66450a21 JK |
3266 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
3267 | kvm_vcpu_has_lapic(vcpu)) | |
3268 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
3cfc3092 | 3269 | |
f077825a PB |
3270 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
3271 | if (events->smi.smm) | |
3272 | vcpu->arch.hflags |= HF_SMM_MASK; | |
3273 | else | |
3274 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
3275 | vcpu->arch.smi_pending = events->smi.pending; | |
3276 | if (events->smi.smm_inside_nmi) | |
3277 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
3278 | else | |
3279 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; | |
3280 | if (kvm_vcpu_has_lapic(vcpu)) { | |
3281 | if (events->smi.latched_init) | |
3282 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3283 | else | |
3284 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3285 | } | |
3286 | } | |
3287 | ||
3842d135 AK |
3288 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3289 | ||
3cfc3092 JK |
3290 | return 0; |
3291 | } | |
3292 | ||
a1efbe77 JK |
3293 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3294 | struct kvm_debugregs *dbgregs) | |
3295 | { | |
73aaf249 JK |
3296 | unsigned long val; |
3297 | ||
a1efbe77 | 3298 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3299 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3300 | dbgregs->dr6 = val; |
a1efbe77 JK |
3301 | dbgregs->dr7 = vcpu->arch.dr7; |
3302 | dbgregs->flags = 0; | |
97e69aa6 | 3303 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3304 | } |
3305 | ||
3306 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3307 | struct kvm_debugregs *dbgregs) | |
3308 | { | |
3309 | if (dbgregs->flags) | |
3310 | return -EINVAL; | |
3311 | ||
a1efbe77 | 3312 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3313 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3314 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3315 | kvm_update_dr6(vcpu); |
a1efbe77 | 3316 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3317 | kvm_update_dr7(vcpu); |
a1efbe77 | 3318 | |
a1efbe77 JK |
3319 | return 0; |
3320 | } | |
3321 | ||
df1daba7 PB |
3322 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3323 | ||
3324 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3325 | { | |
3326 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3327 | u64 xstate_bv = xsave->xsave_hdr.xstate_bv; | |
3328 | u64 valid; | |
3329 | ||
3330 | /* | |
3331 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3332 | * leaves 0 and 1 in the loop below. | |
3333 | */ | |
3334 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3335 | ||
3336 | /* Set XSTATE_BV */ | |
3337 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; | |
3338 | ||
3339 | /* | |
3340 | * Copy each region from the possibly compacted offset to the | |
3341 | * non-compacted offset. | |
3342 | */ | |
3343 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3344 | while (valid) { | |
3345 | u64 feature = valid & -valid; | |
3346 | int index = fls64(feature) - 1; | |
3347 | void *src = get_xsave_addr(xsave, feature); | |
3348 | ||
3349 | if (src) { | |
3350 | u32 size, offset, ecx, edx; | |
3351 | cpuid_count(XSTATE_CPUID, index, | |
3352 | &size, &offset, &ecx, &edx); | |
3353 | memcpy(dest + offset, src, size); | |
3354 | } | |
3355 | ||
3356 | valid -= feature; | |
3357 | } | |
3358 | } | |
3359 | ||
3360 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3361 | { | |
3362 | struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; | |
3363 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); | |
3364 | u64 valid; | |
3365 | ||
3366 | /* | |
3367 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3368 | * leaves 0 and 1 in the loop below. | |
3369 | */ | |
3370 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3371 | ||
3372 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
3373 | xsave->xsave_hdr.xstate_bv = xstate_bv; | |
3374 | if (cpu_has_xsaves) | |
3375 | xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
3376 | ||
3377 | /* | |
3378 | * Copy each region from the non-compacted offset to the | |
3379 | * possibly compacted offset. | |
3380 | */ | |
3381 | valid = xstate_bv & ~XSTATE_FPSSE; | |
3382 | while (valid) { | |
3383 | u64 feature = valid & -valid; | |
3384 | int index = fls64(feature) - 1; | |
3385 | void *dest = get_xsave_addr(xsave, feature); | |
3386 | ||
3387 | if (dest) { | |
3388 | u32 size, offset, ecx, edx; | |
3389 | cpuid_count(XSTATE_CPUID, index, | |
3390 | &size, &offset, &ecx, &edx); | |
3391 | memcpy(dest, src + offset, size); | |
3392 | } else | |
3393 | WARN_ON_ONCE(1); | |
3394 | ||
3395 | valid -= feature; | |
3396 | } | |
3397 | } | |
3398 | ||
2d5b5a66 SY |
3399 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3400 | struct kvm_xsave *guest_xsave) | |
3401 | { | |
4344ee98 | 3402 | if (cpu_has_xsave) { |
df1daba7 PB |
3403 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3404 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3405 | } else { |
2d5b5a66 SY |
3406 | memcpy(guest_xsave->region, |
3407 | &vcpu->arch.guest_fpu.state->fxsave, | |
3408 | sizeof(struct i387_fxsave_struct)); | |
3409 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
3410 | XSTATE_FPSSE; | |
3411 | } | |
3412 | } | |
3413 | ||
3414 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3415 | struct kvm_xsave *guest_xsave) | |
3416 | { | |
3417 | u64 xstate_bv = | |
3418 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3419 | ||
d7876f1b PB |
3420 | if (cpu_has_xsave) { |
3421 | /* | |
3422 | * Here we allow setting states that are not present in | |
3423 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3424 | * with old userspace. | |
3425 | */ | |
4ff41732 | 3426 | if (xstate_bv & ~kvm_supported_xcr0()) |
d7876f1b | 3427 | return -EINVAL; |
df1daba7 | 3428 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3429 | } else { |
2d5b5a66 SY |
3430 | if (xstate_bv & ~XSTATE_FPSSE) |
3431 | return -EINVAL; | |
3432 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
3433 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
3434 | } | |
3435 | return 0; | |
3436 | } | |
3437 | ||
3438 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3439 | struct kvm_xcrs *guest_xcrs) | |
3440 | { | |
3441 | if (!cpu_has_xsave) { | |
3442 | guest_xcrs->nr_xcrs = 0; | |
3443 | return; | |
3444 | } | |
3445 | ||
3446 | guest_xcrs->nr_xcrs = 1; | |
3447 | guest_xcrs->flags = 0; | |
3448 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3449 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3450 | } | |
3451 | ||
3452 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3453 | struct kvm_xcrs *guest_xcrs) | |
3454 | { | |
3455 | int i, r = 0; | |
3456 | ||
3457 | if (!cpu_has_xsave) | |
3458 | return -EINVAL; | |
3459 | ||
3460 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3461 | return -EINVAL; | |
3462 | ||
3463 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3464 | /* Only support XCR0 currently */ | |
c67a04cb | 3465 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3466 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3467 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3468 | break; |
3469 | } | |
3470 | if (r) | |
3471 | r = -EINVAL; | |
3472 | return r; | |
3473 | } | |
3474 | ||
1c0b28c2 EM |
3475 | /* |
3476 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3477 | * stopped by the hypervisor. This function will be called from the host only. | |
3478 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3479 | * does not support pv clocks. | |
3480 | */ | |
3481 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3482 | { | |
0b79459b | 3483 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3484 | return -EINVAL; |
51d59c6b | 3485 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3486 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3487 | return 0; | |
3488 | } | |
3489 | ||
313a3dc7 CO |
3490 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3491 | unsigned int ioctl, unsigned long arg) | |
3492 | { | |
3493 | struct kvm_vcpu *vcpu = filp->private_data; | |
3494 | void __user *argp = (void __user *)arg; | |
3495 | int r; | |
d1ac91d8 AK |
3496 | union { |
3497 | struct kvm_lapic_state *lapic; | |
3498 | struct kvm_xsave *xsave; | |
3499 | struct kvm_xcrs *xcrs; | |
3500 | void *buffer; | |
3501 | } u; | |
3502 | ||
3503 | u.buffer = NULL; | |
313a3dc7 CO |
3504 | switch (ioctl) { |
3505 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
3506 | r = -EINVAL; |
3507 | if (!vcpu->arch.apic) | |
3508 | goto out; | |
d1ac91d8 | 3509 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 3510 | |
b772ff36 | 3511 | r = -ENOMEM; |
d1ac91d8 | 3512 | if (!u.lapic) |
b772ff36 | 3513 | goto out; |
d1ac91d8 | 3514 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3515 | if (r) |
3516 | goto out; | |
3517 | r = -EFAULT; | |
d1ac91d8 | 3518 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3519 | goto out; |
3520 | r = 0; | |
3521 | break; | |
3522 | } | |
3523 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
3524 | r = -EINVAL; |
3525 | if (!vcpu->arch.apic) | |
3526 | goto out; | |
ff5c2c03 | 3527 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
18595411 GC |
3528 | if (IS_ERR(u.lapic)) |
3529 | return PTR_ERR(u.lapic); | |
ff5c2c03 | 3530 | |
d1ac91d8 | 3531 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3532 | break; |
3533 | } | |
f77bc6a4 ZX |
3534 | case KVM_INTERRUPT: { |
3535 | struct kvm_interrupt irq; | |
3536 | ||
3537 | r = -EFAULT; | |
3538 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3539 | goto out; | |
3540 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
3541 | break; |
3542 | } | |
c4abb7c9 JK |
3543 | case KVM_NMI: { |
3544 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
3545 | break; |
3546 | } | |
f077825a PB |
3547 | case KVM_SMI: { |
3548 | r = kvm_vcpu_ioctl_smi(vcpu); | |
3549 | break; | |
3550 | } | |
313a3dc7 CO |
3551 | case KVM_SET_CPUID: { |
3552 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3553 | struct kvm_cpuid cpuid; | |
3554 | ||
3555 | r = -EFAULT; | |
3556 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3557 | goto out; | |
3558 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
3559 | break; |
3560 | } | |
07716717 DK |
3561 | case KVM_SET_CPUID2: { |
3562 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3563 | struct kvm_cpuid2 cpuid; | |
3564 | ||
3565 | r = -EFAULT; | |
3566 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3567 | goto out; | |
3568 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 3569 | cpuid_arg->entries); |
07716717 DK |
3570 | break; |
3571 | } | |
3572 | case KVM_GET_CPUID2: { | |
3573 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3574 | struct kvm_cpuid2 cpuid; | |
3575 | ||
3576 | r = -EFAULT; | |
3577 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3578 | goto out; | |
3579 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 3580 | cpuid_arg->entries); |
07716717 DK |
3581 | if (r) |
3582 | goto out; | |
3583 | r = -EFAULT; | |
3584 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3585 | goto out; | |
3586 | r = 0; | |
3587 | break; | |
3588 | } | |
313a3dc7 | 3589 | case KVM_GET_MSRS: |
609e36d3 | 3590 | r = msr_io(vcpu, argp, do_get_msr, 1); |
313a3dc7 CO |
3591 | break; |
3592 | case KVM_SET_MSRS: | |
3593 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3594 | break; | |
b209749f AK |
3595 | case KVM_TPR_ACCESS_REPORTING: { |
3596 | struct kvm_tpr_access_ctl tac; | |
3597 | ||
3598 | r = -EFAULT; | |
3599 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3600 | goto out; | |
3601 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3602 | if (r) | |
3603 | goto out; | |
3604 | r = -EFAULT; | |
3605 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3606 | goto out; | |
3607 | r = 0; | |
3608 | break; | |
3609 | }; | |
b93463aa AK |
3610 | case KVM_SET_VAPIC_ADDR: { |
3611 | struct kvm_vapic_addr va; | |
3612 | ||
3613 | r = -EINVAL; | |
3614 | if (!irqchip_in_kernel(vcpu->kvm)) | |
3615 | goto out; | |
3616 | r = -EFAULT; | |
3617 | if (copy_from_user(&va, argp, sizeof va)) | |
3618 | goto out; | |
fda4e2e8 | 3619 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
b93463aa AK |
3620 | break; |
3621 | } | |
890ca9ae HY |
3622 | case KVM_X86_SETUP_MCE: { |
3623 | u64 mcg_cap; | |
3624 | ||
3625 | r = -EFAULT; | |
3626 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3627 | goto out; | |
3628 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3629 | break; | |
3630 | } | |
3631 | case KVM_X86_SET_MCE: { | |
3632 | struct kvm_x86_mce mce; | |
3633 | ||
3634 | r = -EFAULT; | |
3635 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3636 | goto out; | |
3637 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3638 | break; | |
3639 | } | |
3cfc3092 JK |
3640 | case KVM_GET_VCPU_EVENTS: { |
3641 | struct kvm_vcpu_events events; | |
3642 | ||
3643 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3644 | ||
3645 | r = -EFAULT; | |
3646 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3647 | break; | |
3648 | r = 0; | |
3649 | break; | |
3650 | } | |
3651 | case KVM_SET_VCPU_EVENTS: { | |
3652 | struct kvm_vcpu_events events; | |
3653 | ||
3654 | r = -EFAULT; | |
3655 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3656 | break; | |
3657 | ||
3658 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3659 | break; | |
3660 | } | |
a1efbe77 JK |
3661 | case KVM_GET_DEBUGREGS: { |
3662 | struct kvm_debugregs dbgregs; | |
3663 | ||
3664 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3665 | ||
3666 | r = -EFAULT; | |
3667 | if (copy_to_user(argp, &dbgregs, | |
3668 | sizeof(struct kvm_debugregs))) | |
3669 | break; | |
3670 | r = 0; | |
3671 | break; | |
3672 | } | |
3673 | case KVM_SET_DEBUGREGS: { | |
3674 | struct kvm_debugregs dbgregs; | |
3675 | ||
3676 | r = -EFAULT; | |
3677 | if (copy_from_user(&dbgregs, argp, | |
3678 | sizeof(struct kvm_debugregs))) | |
3679 | break; | |
3680 | ||
3681 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3682 | break; | |
3683 | } | |
2d5b5a66 | 3684 | case KVM_GET_XSAVE: { |
d1ac91d8 | 3685 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); |
2d5b5a66 | 3686 | r = -ENOMEM; |
d1ac91d8 | 3687 | if (!u.xsave) |
2d5b5a66 SY |
3688 | break; |
3689 | ||
d1ac91d8 | 3690 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3691 | |
3692 | r = -EFAULT; | |
d1ac91d8 | 3693 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
3694 | break; |
3695 | r = 0; | |
3696 | break; | |
3697 | } | |
3698 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 3699 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
18595411 GC |
3700 | if (IS_ERR(u.xsave)) |
3701 | return PTR_ERR(u.xsave); | |
2d5b5a66 | 3702 | |
d1ac91d8 | 3703 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
3704 | break; |
3705 | } | |
3706 | case KVM_GET_XCRS: { | |
d1ac91d8 | 3707 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); |
2d5b5a66 | 3708 | r = -ENOMEM; |
d1ac91d8 | 3709 | if (!u.xcrs) |
2d5b5a66 SY |
3710 | break; |
3711 | ||
d1ac91d8 | 3712 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3713 | |
3714 | r = -EFAULT; | |
d1ac91d8 | 3715 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
3716 | sizeof(struct kvm_xcrs))) |
3717 | break; | |
3718 | r = 0; | |
3719 | break; | |
3720 | } | |
3721 | case KVM_SET_XCRS: { | |
ff5c2c03 | 3722 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
18595411 GC |
3723 | if (IS_ERR(u.xcrs)) |
3724 | return PTR_ERR(u.xcrs); | |
2d5b5a66 | 3725 | |
d1ac91d8 | 3726 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
3727 | break; |
3728 | } | |
92a1f12d JR |
3729 | case KVM_SET_TSC_KHZ: { |
3730 | u32 user_tsc_khz; | |
3731 | ||
3732 | r = -EINVAL; | |
92a1f12d JR |
3733 | user_tsc_khz = (u32)arg; |
3734 | ||
3735 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3736 | goto out; | |
3737 | ||
cc578287 ZA |
3738 | if (user_tsc_khz == 0) |
3739 | user_tsc_khz = tsc_khz; | |
3740 | ||
3741 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
92a1f12d JR |
3742 | |
3743 | r = 0; | |
3744 | goto out; | |
3745 | } | |
3746 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 3747 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
3748 | goto out; |
3749 | } | |
1c0b28c2 EM |
3750 | case KVM_KVMCLOCK_CTRL: { |
3751 | r = kvm_set_guest_paused(vcpu); | |
3752 | goto out; | |
3753 | } | |
313a3dc7 CO |
3754 | default: |
3755 | r = -EINVAL; | |
3756 | } | |
3757 | out: | |
d1ac91d8 | 3758 | kfree(u.buffer); |
313a3dc7 CO |
3759 | return r; |
3760 | } | |
3761 | ||
5b1c1493 CO |
3762 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
3763 | { | |
3764 | return VM_FAULT_SIGBUS; | |
3765 | } | |
3766 | ||
1fe779f8 CO |
3767 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
3768 | { | |
3769 | int ret; | |
3770 | ||
3771 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 3772 | return -EINVAL; |
1fe779f8 CO |
3773 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
3774 | return ret; | |
3775 | } | |
3776 | ||
b927a3ce SY |
3777 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
3778 | u64 ident_addr) | |
3779 | { | |
3780 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3781 | return 0; | |
3782 | } | |
3783 | ||
1fe779f8 CO |
3784 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
3785 | u32 kvm_nr_mmu_pages) | |
3786 | { | |
3787 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3788 | return -EINVAL; | |
3789 | ||
79fac95e | 3790 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
3791 | |
3792 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 3793 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 3794 | |
79fac95e | 3795 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
3796 | return 0; |
3797 | } | |
3798 | ||
3799 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3800 | { | |
39de71ec | 3801 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
3802 | } |
3803 | ||
1fe779f8 CO |
3804 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
3805 | { | |
3806 | int r; | |
3807 | ||
3808 | r = 0; | |
3809 | switch (chip->chip_id) { | |
3810 | case KVM_IRQCHIP_PIC_MASTER: | |
3811 | memcpy(&chip->chip.pic, | |
3812 | &pic_irqchip(kvm)->pics[0], | |
3813 | sizeof(struct kvm_pic_state)); | |
3814 | break; | |
3815 | case KVM_IRQCHIP_PIC_SLAVE: | |
3816 | memcpy(&chip->chip.pic, | |
3817 | &pic_irqchip(kvm)->pics[1], | |
3818 | sizeof(struct kvm_pic_state)); | |
3819 | break; | |
3820 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3821 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3822 | break; |
3823 | default: | |
3824 | r = -EINVAL; | |
3825 | break; | |
3826 | } | |
3827 | return r; | |
3828 | } | |
3829 | ||
3830 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3831 | { | |
3832 | int r; | |
3833 | ||
3834 | r = 0; | |
3835 | switch (chip->chip_id) { | |
3836 | case KVM_IRQCHIP_PIC_MASTER: | |
f4f51050 | 3837 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3838 | memcpy(&pic_irqchip(kvm)->pics[0], |
3839 | &chip->chip.pic, | |
3840 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3841 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3842 | break; |
3843 | case KVM_IRQCHIP_PIC_SLAVE: | |
f4f51050 | 3844 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3845 | memcpy(&pic_irqchip(kvm)->pics[1], |
3846 | &chip->chip.pic, | |
3847 | sizeof(struct kvm_pic_state)); | |
f4f51050 | 3848 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
3849 | break; |
3850 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 3851 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
3852 | break; |
3853 | default: | |
3854 | r = -EINVAL; | |
3855 | break; | |
3856 | } | |
3857 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3858 | return r; | |
3859 | } | |
3860 | ||
e0f63cb9 SY |
3861 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
3862 | { | |
3863 | int r = 0; | |
3864 | ||
894a9c55 | 3865 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3866 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 3867 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3868 | return r; |
3869 | } | |
3870 | ||
3871 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3872 | { | |
3873 | int r = 0; | |
3874 | ||
894a9c55 | 3875 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 3876 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
3877 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
3878 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3879 | return r; | |
3880 | } | |
3881 | ||
3882 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3883 | { | |
3884 | int r = 0; | |
3885 | ||
3886 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3887 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3888 | sizeof(ps->channels)); | |
3889 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3890 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 3891 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
e9f42757 BK |
3892 | return r; |
3893 | } | |
3894 | ||
3895 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3896 | { | |
3897 | int r = 0, start = 0; | |
3898 | u32 prev_legacy, cur_legacy; | |
3899 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3900 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3901 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3902 | if (!prev_legacy && cur_legacy) | |
3903 | start = 1; | |
3904 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3905 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3906 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3907 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 3908 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
3909 | return r; |
3910 | } | |
3911 | ||
52d939a0 MT |
3912 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
3913 | struct kvm_reinject_control *control) | |
3914 | { | |
3915 | if (!kvm->arch.vpit) | |
3916 | return -ENXIO; | |
894a9c55 | 3917 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 3918 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; |
894a9c55 | 3919 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
3920 | return 0; |
3921 | } | |
3922 | ||
95d4c16c | 3923 | /** |
60c34612 TY |
3924 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
3925 | * @kvm: kvm instance | |
3926 | * @log: slot id and address to which we copy the log | |
95d4c16c | 3927 | * |
e108ff2f PB |
3928 | * Steps 1-4 below provide general overview of dirty page logging. See |
3929 | * kvm_get_dirty_log_protect() function description for additional details. | |
3930 | * | |
3931 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
3932 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
3933 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
3934 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
3935 | * writes will be marked dirty for next log read. | |
95d4c16c | 3936 | * |
60c34612 TY |
3937 | * 1. Take a snapshot of the bit and clear it if needed. |
3938 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
3939 | * 3. Copy the snapshot to the userspace. |
3940 | * 4. Flush TLB's if needed. | |
5bb064dc | 3941 | */ |
60c34612 | 3942 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 3943 | { |
60c34612 | 3944 | bool is_dirty = false; |
e108ff2f | 3945 | int r; |
5bb064dc | 3946 | |
79fac95e | 3947 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 3948 | |
88178fd4 KH |
3949 | /* |
3950 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
3951 | */ | |
3952 | if (kvm_x86_ops->flush_log_dirty) | |
3953 | kvm_x86_ops->flush_log_dirty(kvm); | |
3954 | ||
e108ff2f | 3955 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
198c74f4 XG |
3956 | |
3957 | /* | |
3958 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
3959 | * kvm_mmu_slot_remove_write_access(). | |
3960 | */ | |
e108ff2f | 3961 | lockdep_assert_held(&kvm->slots_lock); |
198c74f4 XG |
3962 | if (is_dirty) |
3963 | kvm_flush_remote_tlbs(kvm); | |
3964 | ||
79fac95e | 3965 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
3966 | return r; |
3967 | } | |
3968 | ||
aa2fbe6d YZ |
3969 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
3970 | bool line_status) | |
23d43cf9 CD |
3971 | { |
3972 | if (!irqchip_in_kernel(kvm)) | |
3973 | return -ENXIO; | |
3974 | ||
3975 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
3976 | irq_event->irq, irq_event->level, |
3977 | line_status); | |
23d43cf9 CD |
3978 | return 0; |
3979 | } | |
3980 | ||
90de4a18 NA |
3981 | static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
3982 | struct kvm_enable_cap *cap) | |
3983 | { | |
3984 | int r; | |
3985 | ||
3986 | if (cap->flags) | |
3987 | return -EINVAL; | |
3988 | ||
3989 | switch (cap->cap) { | |
3990 | case KVM_CAP_DISABLE_QUIRKS: | |
3991 | kvm->arch.disabled_quirks = cap->args[0]; | |
3992 | r = 0; | |
3993 | break; | |
3994 | default: | |
3995 | r = -EINVAL; | |
3996 | break; | |
3997 | } | |
3998 | return r; | |
3999 | } | |
4000 | ||
1fe779f8 CO |
4001 | long kvm_arch_vm_ioctl(struct file *filp, |
4002 | unsigned int ioctl, unsigned long arg) | |
4003 | { | |
4004 | struct kvm *kvm = filp->private_data; | |
4005 | void __user *argp = (void __user *)arg; | |
367e1319 | 4006 | int r = -ENOTTY; |
f0d66275 DH |
4007 | /* |
4008 | * This union makes it completely explicit to gcc-3.x | |
4009 | * that these two variables' stack usage should be | |
4010 | * combined, not added together. | |
4011 | */ | |
4012 | union { | |
4013 | struct kvm_pit_state ps; | |
e9f42757 | 4014 | struct kvm_pit_state2 ps2; |
c5ff41ce | 4015 | struct kvm_pit_config pit_config; |
f0d66275 | 4016 | } u; |
1fe779f8 CO |
4017 | |
4018 | switch (ioctl) { | |
4019 | case KVM_SET_TSS_ADDR: | |
4020 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 4021 | break; |
b927a3ce SY |
4022 | case KVM_SET_IDENTITY_MAP_ADDR: { |
4023 | u64 ident_addr; | |
4024 | ||
4025 | r = -EFAULT; | |
4026 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
4027 | goto out; | |
4028 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
b927a3ce SY |
4029 | break; |
4030 | } | |
1fe779f8 CO |
4031 | case KVM_SET_NR_MMU_PAGES: |
4032 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
4033 | break; |
4034 | case KVM_GET_NR_MMU_PAGES: | |
4035 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
4036 | break; | |
3ddea128 MT |
4037 | case KVM_CREATE_IRQCHIP: { |
4038 | struct kvm_pic *vpic; | |
4039 | ||
4040 | mutex_lock(&kvm->lock); | |
4041 | r = -EEXIST; | |
4042 | if (kvm->arch.vpic) | |
4043 | goto create_irqchip_unlock; | |
3e515705 AK |
4044 | r = -EINVAL; |
4045 | if (atomic_read(&kvm->online_vcpus)) | |
4046 | goto create_irqchip_unlock; | |
1fe779f8 | 4047 | r = -ENOMEM; |
3ddea128 MT |
4048 | vpic = kvm_create_pic(kvm); |
4049 | if (vpic) { | |
1fe779f8 CO |
4050 | r = kvm_ioapic_init(kvm); |
4051 | if (r) { | |
175504cd | 4052 | mutex_lock(&kvm->slots_lock); |
72bb2fcd | 4053 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
4054 | &vpic->dev_master); |
4055 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
4056 | &vpic->dev_slave); | |
4057 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
4058 | &vpic->dev_eclr); | |
175504cd | 4059 | mutex_unlock(&kvm->slots_lock); |
3ddea128 MT |
4060 | kfree(vpic); |
4061 | goto create_irqchip_unlock; | |
1fe779f8 CO |
4062 | } |
4063 | } else | |
3ddea128 MT |
4064 | goto create_irqchip_unlock; |
4065 | smp_wmb(); | |
4066 | kvm->arch.vpic = vpic; | |
4067 | smp_wmb(); | |
399ec807 AK |
4068 | r = kvm_setup_default_irq_routing(kvm); |
4069 | if (r) { | |
175504cd | 4070 | mutex_lock(&kvm->slots_lock); |
3ddea128 | 4071 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
4072 | kvm_ioapic_destroy(kvm); |
4073 | kvm_destroy_pic(kvm); | |
3ddea128 | 4074 | mutex_unlock(&kvm->irq_lock); |
175504cd | 4075 | mutex_unlock(&kvm->slots_lock); |
399ec807 | 4076 | } |
3ddea128 MT |
4077 | create_irqchip_unlock: |
4078 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 4079 | break; |
3ddea128 | 4080 | } |
7837699f | 4081 | case KVM_CREATE_PIT: |
c5ff41ce JK |
4082 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
4083 | goto create_pit; | |
4084 | case KVM_CREATE_PIT2: | |
4085 | r = -EFAULT; | |
4086 | if (copy_from_user(&u.pit_config, argp, | |
4087 | sizeof(struct kvm_pit_config))) | |
4088 | goto out; | |
4089 | create_pit: | |
79fac95e | 4090 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
4091 | r = -EEXIST; |
4092 | if (kvm->arch.vpit) | |
4093 | goto create_pit_unlock; | |
7837699f | 4094 | r = -ENOMEM; |
c5ff41ce | 4095 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
4096 | if (kvm->arch.vpit) |
4097 | r = 0; | |
269e05e4 | 4098 | create_pit_unlock: |
79fac95e | 4099 | mutex_unlock(&kvm->slots_lock); |
7837699f | 4100 | break; |
1fe779f8 CO |
4101 | case KVM_GET_IRQCHIP: { |
4102 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4103 | struct kvm_irqchip *chip; |
1fe779f8 | 4104 | |
ff5c2c03 SL |
4105 | chip = memdup_user(argp, sizeof(*chip)); |
4106 | if (IS_ERR(chip)) { | |
4107 | r = PTR_ERR(chip); | |
1fe779f8 | 4108 | goto out; |
ff5c2c03 SL |
4109 | } |
4110 | ||
1fe779f8 CO |
4111 | r = -ENXIO; |
4112 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
4113 | goto get_irqchip_out; |
4114 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 4115 | if (r) |
f0d66275 | 4116 | goto get_irqchip_out; |
1fe779f8 | 4117 | r = -EFAULT; |
f0d66275 DH |
4118 | if (copy_to_user(argp, chip, sizeof *chip)) |
4119 | goto get_irqchip_out; | |
1fe779f8 | 4120 | r = 0; |
f0d66275 DH |
4121 | get_irqchip_out: |
4122 | kfree(chip); | |
1fe779f8 CO |
4123 | break; |
4124 | } | |
4125 | case KVM_SET_IRQCHIP: { | |
4126 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4127 | struct kvm_irqchip *chip; |
1fe779f8 | 4128 | |
ff5c2c03 SL |
4129 | chip = memdup_user(argp, sizeof(*chip)); |
4130 | if (IS_ERR(chip)) { | |
4131 | r = PTR_ERR(chip); | |
1fe779f8 | 4132 | goto out; |
ff5c2c03 SL |
4133 | } |
4134 | ||
1fe779f8 CO |
4135 | r = -ENXIO; |
4136 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
4137 | goto set_irqchip_out; |
4138 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 4139 | if (r) |
f0d66275 | 4140 | goto set_irqchip_out; |
1fe779f8 | 4141 | r = 0; |
f0d66275 DH |
4142 | set_irqchip_out: |
4143 | kfree(chip); | |
1fe779f8 CO |
4144 | break; |
4145 | } | |
e0f63cb9 | 4146 | case KVM_GET_PIT: { |
e0f63cb9 | 4147 | r = -EFAULT; |
f0d66275 | 4148 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4149 | goto out; |
4150 | r = -ENXIO; | |
4151 | if (!kvm->arch.vpit) | |
4152 | goto out; | |
f0d66275 | 4153 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
4154 | if (r) |
4155 | goto out; | |
4156 | r = -EFAULT; | |
f0d66275 | 4157 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4158 | goto out; |
4159 | r = 0; | |
4160 | break; | |
4161 | } | |
4162 | case KVM_SET_PIT: { | |
e0f63cb9 | 4163 | r = -EFAULT; |
f0d66275 | 4164 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
4165 | goto out; |
4166 | r = -ENXIO; | |
4167 | if (!kvm->arch.vpit) | |
4168 | goto out; | |
f0d66275 | 4169 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
4170 | break; |
4171 | } | |
e9f42757 BK |
4172 | case KVM_GET_PIT2: { |
4173 | r = -ENXIO; | |
4174 | if (!kvm->arch.vpit) | |
4175 | goto out; | |
4176 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
4177 | if (r) | |
4178 | goto out; | |
4179 | r = -EFAULT; | |
4180 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
4181 | goto out; | |
4182 | r = 0; | |
4183 | break; | |
4184 | } | |
4185 | case KVM_SET_PIT2: { | |
4186 | r = -EFAULT; | |
4187 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
4188 | goto out; | |
4189 | r = -ENXIO; | |
4190 | if (!kvm->arch.vpit) | |
4191 | goto out; | |
4192 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
4193 | break; |
4194 | } | |
52d939a0 MT |
4195 | case KVM_REINJECT_CONTROL: { |
4196 | struct kvm_reinject_control control; | |
4197 | r = -EFAULT; | |
4198 | if (copy_from_user(&control, argp, sizeof(control))) | |
4199 | goto out; | |
4200 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
4201 | break; |
4202 | } | |
ffde22ac ES |
4203 | case KVM_XEN_HVM_CONFIG: { |
4204 | r = -EFAULT; | |
4205 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
4206 | sizeof(struct kvm_xen_hvm_config))) | |
4207 | goto out; | |
4208 | r = -EINVAL; | |
4209 | if (kvm->arch.xen_hvm_config.flags) | |
4210 | goto out; | |
4211 | r = 0; | |
4212 | break; | |
4213 | } | |
afbcf7ab | 4214 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4215 | struct kvm_clock_data user_ns; |
4216 | u64 now_ns; | |
4217 | s64 delta; | |
4218 | ||
4219 | r = -EFAULT; | |
4220 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
4221 | goto out; | |
4222 | ||
4223 | r = -EINVAL; | |
4224 | if (user_ns.flags) | |
4225 | goto out; | |
4226 | ||
4227 | r = 0; | |
395c6b0a | 4228 | local_irq_disable(); |
759379dd | 4229 | now_ns = get_kernel_ns(); |
afbcf7ab | 4230 | delta = user_ns.clock - now_ns; |
395c6b0a | 4231 | local_irq_enable(); |
afbcf7ab | 4232 | kvm->arch.kvmclock_offset = delta; |
2e762ff7 | 4233 | kvm_gen_update_masterclock(kvm); |
afbcf7ab GC |
4234 | break; |
4235 | } | |
4236 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
4237 | struct kvm_clock_data user_ns; |
4238 | u64 now_ns; | |
4239 | ||
395c6b0a | 4240 | local_irq_disable(); |
759379dd | 4241 | now_ns = get_kernel_ns(); |
afbcf7ab | 4242 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; |
395c6b0a | 4243 | local_irq_enable(); |
afbcf7ab | 4244 | user_ns.flags = 0; |
97e69aa6 | 4245 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4246 | |
4247 | r = -EFAULT; | |
4248 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4249 | goto out; | |
4250 | r = 0; | |
4251 | break; | |
4252 | } | |
90de4a18 NA |
4253 | case KVM_ENABLE_CAP: { |
4254 | struct kvm_enable_cap cap; | |
afbcf7ab | 4255 | |
90de4a18 NA |
4256 | r = -EFAULT; |
4257 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4258 | goto out; | |
4259 | r = kvm_vm_ioctl_enable_cap(kvm, &cap); | |
4260 | break; | |
4261 | } | |
1fe779f8 | 4262 | default: |
c274e03a | 4263 | r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); |
1fe779f8 CO |
4264 | } |
4265 | out: | |
4266 | return r; | |
4267 | } | |
4268 | ||
a16b043c | 4269 | static void kvm_init_msr_list(void) |
043405e1 CO |
4270 | { |
4271 | u32 dummy[2]; | |
4272 | unsigned i, j; | |
4273 | ||
62ef68bb | 4274 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { |
043405e1 CO |
4275 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4276 | continue; | |
93c4adc7 PB |
4277 | |
4278 | /* | |
4279 | * Even MSRs that are valid in the host may not be exposed | |
4280 | * to the guests in some cases. We could work around this | |
4281 | * in VMX with the generic MSR save/load machinery, but it | |
4282 | * is not really worthwhile since it will really only | |
4283 | * happen with nested virtualization. | |
4284 | */ | |
4285 | switch (msrs_to_save[i]) { | |
4286 | case MSR_IA32_BNDCFGS: | |
4287 | if (!kvm_x86_ops->mpx_supported()) | |
4288 | continue; | |
4289 | break; | |
4290 | default: | |
4291 | break; | |
4292 | } | |
4293 | ||
043405e1 CO |
4294 | if (j < i) |
4295 | msrs_to_save[j] = msrs_to_save[i]; | |
4296 | j++; | |
4297 | } | |
4298 | num_msrs_to_save = j; | |
62ef68bb PB |
4299 | |
4300 | for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { | |
4301 | switch (emulated_msrs[i]) { | |
4302 | default: | |
4303 | break; | |
4304 | } | |
4305 | ||
4306 | if (j < i) | |
4307 | emulated_msrs[j] = emulated_msrs[i]; | |
4308 | j++; | |
4309 | } | |
4310 | num_emulated_msrs = j; | |
043405e1 CO |
4311 | } |
4312 | ||
bda9020e MT |
4313 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
4314 | const void *v) | |
bbd9b64e | 4315 | { |
70252a10 AK |
4316 | int handled = 0; |
4317 | int n; | |
4318 | ||
4319 | do { | |
4320 | n = min(len, 8); | |
4321 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4322 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
4323 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4324 | break; |
4325 | handled += n; | |
4326 | addr += n; | |
4327 | len -= n; | |
4328 | v += n; | |
4329 | } while (len); | |
bbd9b64e | 4330 | |
70252a10 | 4331 | return handled; |
bbd9b64e CO |
4332 | } |
4333 | ||
bda9020e | 4334 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 4335 | { |
70252a10 AK |
4336 | int handled = 0; |
4337 | int n; | |
4338 | ||
4339 | do { | |
4340 | n = min(len, 8); | |
4341 | if (!(vcpu->arch.apic && | |
e32edf4f NN |
4342 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
4343 | addr, n, v)) | |
4344 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
4345 | break; |
4346 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
4347 | handled += n; | |
4348 | addr += n; | |
4349 | len -= n; | |
4350 | v += n; | |
4351 | } while (len); | |
bbd9b64e | 4352 | |
70252a10 | 4353 | return handled; |
bbd9b64e CO |
4354 | } |
4355 | ||
2dafc6c2 GN |
4356 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
4357 | struct kvm_segment *var, int seg) | |
4358 | { | |
4359 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
4360 | } | |
4361 | ||
4362 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
4363 | struct kvm_segment *var, int seg) | |
4364 | { | |
4365 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
4366 | } | |
4367 | ||
54987b7a PB |
4368 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
4369 | struct x86_exception *exception) | |
02f59dc9 JR |
4370 | { |
4371 | gpa_t t_gpa; | |
02f59dc9 JR |
4372 | |
4373 | BUG_ON(!mmu_is_nested(vcpu)); | |
4374 | ||
4375 | /* NPT walks are always user-walks */ | |
4376 | access |= PFERR_USER_MASK; | |
54987b7a | 4377 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
4378 | |
4379 | return t_gpa; | |
4380 | } | |
4381 | ||
ab9ae313 AK |
4382 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
4383 | struct x86_exception *exception) | |
1871c602 GN |
4384 | { |
4385 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 4386 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4387 | } |
4388 | ||
ab9ae313 AK |
4389 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
4390 | struct x86_exception *exception) | |
1871c602 GN |
4391 | { |
4392 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4393 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 4394 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4395 | } |
4396 | ||
ab9ae313 AK |
4397 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
4398 | struct x86_exception *exception) | |
1871c602 GN |
4399 | { |
4400 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4401 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 4402 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
4403 | } |
4404 | ||
4405 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
4406 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
4407 | struct x86_exception *exception) | |
1871c602 | 4408 | { |
ab9ae313 | 4409 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
4410 | } |
4411 | ||
4412 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
4413 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 4414 | struct x86_exception *exception) |
bbd9b64e CO |
4415 | { |
4416 | void *data = val; | |
10589a46 | 4417 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
4418 | |
4419 | while (bytes) { | |
14dfe855 | 4420 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 4421 | exception); |
bbd9b64e | 4422 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 4423 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
4424 | int ret; |
4425 | ||
bcc55cba | 4426 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4427 | return X86EMUL_PROPAGATE_FAULT; |
44583cba PB |
4428 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, |
4429 | offset, toread); | |
10589a46 | 4430 | if (ret < 0) { |
c3cd7ffa | 4431 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
4432 | goto out; |
4433 | } | |
bbd9b64e | 4434 | |
77c2002e IE |
4435 | bytes -= toread; |
4436 | data += toread; | |
4437 | addr += toread; | |
bbd9b64e | 4438 | } |
10589a46 | 4439 | out: |
10589a46 | 4440 | return r; |
bbd9b64e | 4441 | } |
77c2002e | 4442 | |
1871c602 | 4443 | /* used for instruction fetching */ |
0f65dd70 AK |
4444 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
4445 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4446 | struct x86_exception *exception) |
1871c602 | 4447 | { |
0f65dd70 | 4448 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4449 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
4450 | unsigned offset; |
4451 | int ret; | |
0f65dd70 | 4452 | |
44583cba PB |
4453 | /* Inline kvm_read_guest_virt_helper for speed. */ |
4454 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
4455 | exception); | |
4456 | if (unlikely(gpa == UNMAPPED_GVA)) | |
4457 | return X86EMUL_PROPAGATE_FAULT; | |
4458 | ||
4459 | offset = addr & (PAGE_SIZE-1); | |
4460 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
4461 | bytes = (unsigned)PAGE_SIZE - offset; | |
4462 | ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, | |
4463 | offset, bytes); | |
4464 | if (unlikely(ret < 0)) | |
4465 | return X86EMUL_IO_NEEDED; | |
4466 | ||
4467 | return X86EMUL_CONTINUE; | |
1871c602 GN |
4468 | } |
4469 | ||
064aea77 | 4470 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4471 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 4472 | struct x86_exception *exception) |
1871c602 | 4473 | { |
0f65dd70 | 4474 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 4475 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 4476 | |
1871c602 | 4477 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 4478 | exception); |
1871c602 | 4479 | } |
064aea77 | 4480 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 4481 | |
0f65dd70 AK |
4482 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
4483 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 4484 | struct x86_exception *exception) |
1871c602 | 4485 | { |
0f65dd70 | 4486 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
bcc55cba | 4487 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); |
1871c602 GN |
4488 | } |
4489 | ||
6a4d7550 | 4490 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, |
0f65dd70 | 4491 | gva_t addr, void *val, |
2dafc6c2 | 4492 | unsigned int bytes, |
bcc55cba | 4493 | struct x86_exception *exception) |
77c2002e | 4494 | { |
0f65dd70 | 4495 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
77c2002e IE |
4496 | void *data = val; |
4497 | int r = X86EMUL_CONTINUE; | |
4498 | ||
4499 | while (bytes) { | |
14dfe855 JR |
4500 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
4501 | PFERR_WRITE_MASK, | |
ab9ae313 | 4502 | exception); |
77c2002e IE |
4503 | unsigned offset = addr & (PAGE_SIZE-1); |
4504 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4505 | int ret; | |
4506 | ||
bcc55cba | 4507 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 4508 | return X86EMUL_PROPAGATE_FAULT; |
77c2002e IE |
4509 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); |
4510 | if (ret < 0) { | |
c3cd7ffa | 4511 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
4512 | goto out; |
4513 | } | |
4514 | ||
4515 | bytes -= towrite; | |
4516 | data += towrite; | |
4517 | addr += towrite; | |
4518 | } | |
4519 | out: | |
4520 | return r; | |
4521 | } | |
6a4d7550 | 4522 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 4523 | |
af7cc7d1 XG |
4524 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
4525 | gpa_t *gpa, struct x86_exception *exception, | |
4526 | bool write) | |
4527 | { | |
97d64b78 AK |
4528 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
4529 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 4530 | |
97d64b78 | 4531 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 FW |
4532 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
4533 | vcpu->arch.access, access)) { | |
bebb106a XG |
4534 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
4535 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 4536 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
4537 | return 1; |
4538 | } | |
4539 | ||
af7cc7d1 XG |
4540 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
4541 | ||
4542 | if (*gpa == UNMAPPED_GVA) | |
4543 | return -1; | |
4544 | ||
4545 | /* For APIC access vmexit */ | |
4546 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4547 | return 1; | |
4548 | ||
4f022648 XG |
4549 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { |
4550 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
bebb106a | 4551 | return 1; |
4f022648 | 4552 | } |
bebb106a | 4553 | |
af7cc7d1 XG |
4554 | return 0; |
4555 | } | |
4556 | ||
3200f405 | 4557 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 4558 | const void *val, int bytes) |
bbd9b64e CO |
4559 | { |
4560 | int ret; | |
4561 | ||
4562 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 4563 | if (ret < 0) |
bbd9b64e | 4564 | return 0; |
f57f2ef5 | 4565 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
4566 | return 1; |
4567 | } | |
4568 | ||
77d197b2 XG |
4569 | struct read_write_emulator_ops { |
4570 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4571 | int bytes); | |
4572 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4573 | void *val, int bytes); | |
4574 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4575 | int bytes, void *val); | |
4576 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4577 | void *val, int bytes); | |
4578 | bool write; | |
4579 | }; | |
4580 | ||
4581 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4582 | { | |
4583 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 4584 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
f78146b0 | 4585 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); |
77d197b2 XG |
4586 | vcpu->mmio_read_completed = 0; |
4587 | return 1; | |
4588 | } | |
4589 | ||
4590 | return 0; | |
4591 | } | |
4592 | ||
4593 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4594 | void *val, int bytes) | |
4595 | { | |
4596 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
4597 | } | |
4598 | ||
4599 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4600 | void *val, int bytes) | |
4601 | { | |
4602 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4603 | } | |
4604 | ||
4605 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4606 | { | |
4607 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4608 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4609 | } | |
4610 | ||
4611 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4612 | void *val, int bytes) | |
4613 | { | |
4614 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4615 | return X86EMUL_IO_NEEDED; | |
4616 | } | |
4617 | ||
4618 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4619 | void *val, int bytes) | |
4620 | { | |
f78146b0 AK |
4621 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
4622 | ||
87da7e66 | 4623 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
4624 | return X86EMUL_CONTINUE; |
4625 | } | |
4626 | ||
0fbe9b0b | 4627 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
4628 | .read_write_prepare = read_prepare, |
4629 | .read_write_emulate = read_emulate, | |
4630 | .read_write_mmio = vcpu_mmio_read, | |
4631 | .read_write_exit_mmio = read_exit_mmio, | |
4632 | }; | |
4633 | ||
0fbe9b0b | 4634 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
4635 | .read_write_emulate = write_emulate, |
4636 | .read_write_mmio = write_mmio, | |
4637 | .read_write_exit_mmio = write_exit_mmio, | |
4638 | .write = true, | |
4639 | }; | |
4640 | ||
22388a3c XG |
4641 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
4642 | unsigned int bytes, | |
4643 | struct x86_exception *exception, | |
4644 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 4645 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4646 | { |
af7cc7d1 XG |
4647 | gpa_t gpa; |
4648 | int handled, ret; | |
22388a3c | 4649 | bool write = ops->write; |
f78146b0 | 4650 | struct kvm_mmio_fragment *frag; |
10589a46 | 4651 | |
22388a3c | 4652 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); |
bbd9b64e | 4653 | |
af7cc7d1 | 4654 | if (ret < 0) |
bbd9b64e | 4655 | return X86EMUL_PROPAGATE_FAULT; |
bbd9b64e CO |
4656 | |
4657 | /* For APIC access vmexit */ | |
af7cc7d1 | 4658 | if (ret) |
bbd9b64e CO |
4659 | goto mmio; |
4660 | ||
22388a3c | 4661 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
4662 | return X86EMUL_CONTINUE; |
4663 | ||
4664 | mmio: | |
4665 | /* | |
4666 | * Is this MMIO handled locally? | |
4667 | */ | |
22388a3c | 4668 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 4669 | if (handled == bytes) |
bbd9b64e | 4670 | return X86EMUL_CONTINUE; |
bbd9b64e | 4671 | |
70252a10 AK |
4672 | gpa += handled; |
4673 | bytes -= handled; | |
4674 | val += handled; | |
4675 | ||
87da7e66 XG |
4676 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
4677 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4678 | frag->gpa = gpa; | |
4679 | frag->data = val; | |
4680 | frag->len = bytes; | |
f78146b0 | 4681 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
4682 | } |
4683 | ||
52eb5a6d XL |
4684 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
4685 | unsigned long addr, | |
22388a3c XG |
4686 | void *val, unsigned int bytes, |
4687 | struct x86_exception *exception, | |
0fbe9b0b | 4688 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 4689 | { |
0f65dd70 | 4690 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
4691 | gpa_t gpa; |
4692 | int rc; | |
4693 | ||
4694 | if (ops->read_write_prepare && | |
4695 | ops->read_write_prepare(vcpu, val, bytes)) | |
4696 | return X86EMUL_CONTINUE; | |
4697 | ||
4698 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 4699 | |
bbd9b64e CO |
4700 | /* Crossing a page boundary? */ |
4701 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 4702 | int now; |
bbd9b64e CO |
4703 | |
4704 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
4705 | rc = emulator_read_write_onepage(addr, val, now, exception, |
4706 | vcpu, ops); | |
4707 | ||
bbd9b64e CO |
4708 | if (rc != X86EMUL_CONTINUE) |
4709 | return rc; | |
4710 | addr += now; | |
bac15531 NA |
4711 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
4712 | addr = (u32)addr; | |
bbd9b64e CO |
4713 | val += now; |
4714 | bytes -= now; | |
4715 | } | |
22388a3c | 4716 | |
f78146b0 AK |
4717 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
4718 | vcpu, ops); | |
4719 | if (rc != X86EMUL_CONTINUE) | |
4720 | return rc; | |
4721 | ||
4722 | if (!vcpu->mmio_nr_fragments) | |
4723 | return rc; | |
4724 | ||
4725 | gpa = vcpu->mmio_fragments[0].gpa; | |
4726 | ||
4727 | vcpu->mmio_needed = 1; | |
4728 | vcpu->mmio_cur_fragment = 0; | |
4729 | ||
87da7e66 | 4730 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
4731 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
4732 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4733 | vcpu->run->mmio.phys_addr = gpa; | |
4734 | ||
4735 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
4736 | } |
4737 | ||
4738 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4739 | unsigned long addr, | |
4740 | void *val, | |
4741 | unsigned int bytes, | |
4742 | struct x86_exception *exception) | |
4743 | { | |
4744 | return emulator_read_write(ctxt, addr, val, bytes, | |
4745 | exception, &read_emultor); | |
4746 | } | |
4747 | ||
52eb5a6d | 4748 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
4749 | unsigned long addr, |
4750 | const void *val, | |
4751 | unsigned int bytes, | |
4752 | struct x86_exception *exception) | |
4753 | { | |
4754 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4755 | exception, &write_emultor); | |
bbd9b64e | 4756 | } |
bbd9b64e | 4757 | |
daea3e73 AK |
4758 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
4759 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4760 | ||
4761 | #ifdef CONFIG_X86_64 | |
4762 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4763 | #else | |
4764 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 4765 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
4766 | #endif |
4767 | ||
0f65dd70 AK |
4768 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
4769 | unsigned long addr, | |
bbd9b64e CO |
4770 | const void *old, |
4771 | const void *new, | |
4772 | unsigned int bytes, | |
0f65dd70 | 4773 | struct x86_exception *exception) |
bbd9b64e | 4774 | { |
0f65dd70 | 4775 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 AK |
4776 | gpa_t gpa; |
4777 | struct page *page; | |
4778 | char *kaddr; | |
4779 | bool exchanged; | |
2bacc55c | 4780 | |
daea3e73 AK |
4781 | /* guests cmpxchg8b have to be emulated atomically */ |
4782 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4783 | goto emul_write; | |
10589a46 | 4784 | |
daea3e73 | 4785 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 4786 | |
daea3e73 AK |
4787 | if (gpa == UNMAPPED_GVA || |
4788 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4789 | goto emul_write; | |
2bacc55c | 4790 | |
daea3e73 AK |
4791 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
4792 | goto emul_write; | |
72dc67a6 | 4793 | |
daea3e73 | 4794 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
32cad84f | 4795 | if (is_error_page(page)) |
c19b8bd6 | 4796 | goto emul_write; |
72dc67a6 | 4797 | |
8fd75e12 | 4798 | kaddr = kmap_atomic(page); |
daea3e73 AK |
4799 | kaddr += offset_in_page(gpa); |
4800 | switch (bytes) { | |
4801 | case 1: | |
4802 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4803 | break; | |
4804 | case 2: | |
4805 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4806 | break; | |
4807 | case 4: | |
4808 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4809 | break; | |
4810 | case 8: | |
4811 | exchanged = CMPXCHG64(kaddr, old, new); | |
4812 | break; | |
4813 | default: | |
4814 | BUG(); | |
2bacc55c | 4815 | } |
8fd75e12 | 4816 | kunmap_atomic(kaddr); |
daea3e73 AK |
4817 | kvm_release_page_dirty(page); |
4818 | ||
4819 | if (!exchanged) | |
4820 | return X86EMUL_CMPXCHG_FAILED; | |
4821 | ||
d3714010 | 4822 | mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); |
f57f2ef5 | 4823 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
4824 | |
4825 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 4826 | |
3200f405 | 4827 | emul_write: |
daea3e73 | 4828 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 4829 | |
0f65dd70 | 4830 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
4831 | } |
4832 | ||
cf8f70bf GN |
4833 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
4834 | { | |
4835 | /* TODO: String I/O for in kernel device */ | |
4836 | int r; | |
4837 | ||
4838 | if (vcpu->arch.pio.in) | |
e32edf4f | 4839 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, |
cf8f70bf GN |
4840 | vcpu->arch.pio.size, pd); |
4841 | else | |
e32edf4f | 4842 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, |
cf8f70bf GN |
4843 | vcpu->arch.pio.port, vcpu->arch.pio.size, |
4844 | pd); | |
4845 | return r; | |
4846 | } | |
4847 | ||
6f6fbe98 XG |
4848 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
4849 | unsigned short port, void *val, | |
4850 | unsigned int count, bool in) | |
cf8f70bf | 4851 | { |
cf8f70bf | 4852 | vcpu->arch.pio.port = port; |
6f6fbe98 | 4853 | vcpu->arch.pio.in = in; |
7972995b | 4854 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
4855 | vcpu->arch.pio.size = size; |
4856 | ||
4857 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 4858 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4859 | return 1; |
4860 | } | |
4861 | ||
4862 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 4863 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
4864 | vcpu->run->io.size = size; |
4865 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4866 | vcpu->run->io.count = count; | |
4867 | vcpu->run->io.port = port; | |
4868 | ||
4869 | return 0; | |
4870 | } | |
4871 | ||
6f6fbe98 XG |
4872 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
4873 | int size, unsigned short port, void *val, | |
4874 | unsigned int count) | |
cf8f70bf | 4875 | { |
ca1d4a9e | 4876 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 4877 | int ret; |
ca1d4a9e | 4878 | |
6f6fbe98 XG |
4879 | if (vcpu->arch.pio.count) |
4880 | goto data_avail; | |
cf8f70bf | 4881 | |
6f6fbe98 XG |
4882 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
4883 | if (ret) { | |
4884 | data_avail: | |
4885 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 4886 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 4887 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
4888 | return 1; |
4889 | } | |
4890 | ||
cf8f70bf GN |
4891 | return 0; |
4892 | } | |
4893 | ||
6f6fbe98 XG |
4894 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
4895 | int size, unsigned short port, | |
4896 | const void *val, unsigned int count) | |
4897 | { | |
4898 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4899 | ||
4900 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 4901 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
4902 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
4903 | } | |
4904 | ||
bbd9b64e CO |
4905 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4906 | { | |
4907 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4908 | } | |
4909 | ||
3cb16fe7 | 4910 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 4911 | { |
3cb16fe7 | 4912 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
4913 | } |
4914 | ||
5cb56059 | 4915 | int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
4916 | { |
4917 | if (!need_emulate_wbinvd(vcpu)) | |
4918 | return X86EMUL_CONTINUE; | |
4919 | ||
4920 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
4921 | int cpu = get_cpu(); |
4922 | ||
4923 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
4924 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
4925 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 4926 | put_cpu(); |
f5f48ee1 | 4927 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
4928 | } else |
4929 | wbinvd(); | |
f5f48ee1 SY |
4930 | return X86EMUL_CONTINUE; |
4931 | } | |
5cb56059 JS |
4932 | |
4933 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4934 | { | |
4935 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
4936 | return kvm_emulate_wbinvd_noskip(vcpu); | |
4937 | } | |
f5f48ee1 SY |
4938 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
4939 | ||
5cb56059 JS |
4940 | |
4941 | ||
bcaf5cc5 AK |
4942 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
4943 | { | |
5cb56059 | 4944 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
4945 | } |
4946 | ||
52eb5a6d XL |
4947 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4948 | unsigned long *dest) | |
bbd9b64e | 4949 | { |
16f8a6f9 | 4950 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
4951 | } |
4952 | ||
52eb5a6d XL |
4953 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
4954 | unsigned long value) | |
bbd9b64e | 4955 | { |
338dbc97 | 4956 | |
717746e3 | 4957 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
4958 | } |
4959 | ||
52a46617 | 4960 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 4961 | { |
52a46617 | 4962 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
4963 | } |
4964 | ||
717746e3 | 4965 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 4966 | { |
717746e3 | 4967 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
4968 | unsigned long value; |
4969 | ||
4970 | switch (cr) { | |
4971 | case 0: | |
4972 | value = kvm_read_cr0(vcpu); | |
4973 | break; | |
4974 | case 2: | |
4975 | value = vcpu->arch.cr2; | |
4976 | break; | |
4977 | case 3: | |
9f8fe504 | 4978 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
4979 | break; |
4980 | case 4: | |
4981 | value = kvm_read_cr4(vcpu); | |
4982 | break; | |
4983 | case 8: | |
4984 | value = kvm_get_cr8(vcpu); | |
4985 | break; | |
4986 | default: | |
a737f256 | 4987 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
4988 | return 0; |
4989 | } | |
4990 | ||
4991 | return value; | |
4992 | } | |
4993 | ||
717746e3 | 4994 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 4995 | { |
717746e3 | 4996 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
4997 | int res = 0; |
4998 | ||
52a46617 GN |
4999 | switch (cr) { |
5000 | case 0: | |
49a9b07e | 5001 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
5002 | break; |
5003 | case 2: | |
5004 | vcpu->arch.cr2 = val; | |
5005 | break; | |
5006 | case 3: | |
2390218b | 5007 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
5008 | break; |
5009 | case 4: | |
a83b29c6 | 5010 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
5011 | break; |
5012 | case 8: | |
eea1cff9 | 5013 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
5014 | break; |
5015 | default: | |
a737f256 | 5016 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 5017 | res = -1; |
52a46617 | 5018 | } |
0f12244f GN |
5019 | |
5020 | return res; | |
52a46617 GN |
5021 | } |
5022 | ||
717746e3 | 5023 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 5024 | { |
717746e3 | 5025 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
5026 | } |
5027 | ||
4bff1e86 | 5028 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 5029 | { |
4bff1e86 | 5030 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
5031 | } |
5032 | ||
4bff1e86 | 5033 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 5034 | { |
4bff1e86 | 5035 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
5036 | } |
5037 | ||
1ac9d0cf AK |
5038 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
5039 | { | |
5040 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
5041 | } | |
5042 | ||
5043 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
5044 | { | |
5045 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
5046 | } | |
5047 | ||
4bff1e86 AK |
5048 | static unsigned long emulator_get_cached_segment_base( |
5049 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 5050 | { |
4bff1e86 | 5051 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
5052 | } |
5053 | ||
1aa36616 AK |
5054 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
5055 | struct desc_struct *desc, u32 *base3, | |
5056 | int seg) | |
2dafc6c2 GN |
5057 | { |
5058 | struct kvm_segment var; | |
5059 | ||
4bff1e86 | 5060 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 5061 | *selector = var.selector; |
2dafc6c2 | 5062 | |
378a8b09 GN |
5063 | if (var.unusable) { |
5064 | memset(desc, 0, sizeof(*desc)); | |
2dafc6c2 | 5065 | return false; |
378a8b09 | 5066 | } |
2dafc6c2 GN |
5067 | |
5068 | if (var.g) | |
5069 | var.limit >>= 12; | |
5070 | set_desc_limit(desc, var.limit); | |
5071 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
5072 | #ifdef CONFIG_X86_64 |
5073 | if (base3) | |
5074 | *base3 = var.base >> 32; | |
5075 | #endif | |
2dafc6c2 GN |
5076 | desc->type = var.type; |
5077 | desc->s = var.s; | |
5078 | desc->dpl = var.dpl; | |
5079 | desc->p = var.present; | |
5080 | desc->avl = var.avl; | |
5081 | desc->l = var.l; | |
5082 | desc->d = var.db; | |
5083 | desc->g = var.g; | |
5084 | ||
5085 | return true; | |
5086 | } | |
5087 | ||
1aa36616 AK |
5088 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
5089 | struct desc_struct *desc, u32 base3, | |
5090 | int seg) | |
2dafc6c2 | 5091 | { |
4bff1e86 | 5092 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
5093 | struct kvm_segment var; |
5094 | ||
1aa36616 | 5095 | var.selector = selector; |
2dafc6c2 | 5096 | var.base = get_desc_base(desc); |
5601d05b GN |
5097 | #ifdef CONFIG_X86_64 |
5098 | var.base |= ((u64)base3) << 32; | |
5099 | #endif | |
2dafc6c2 GN |
5100 | var.limit = get_desc_limit(desc); |
5101 | if (desc->g) | |
5102 | var.limit = (var.limit << 12) | 0xfff; | |
5103 | var.type = desc->type; | |
2dafc6c2 GN |
5104 | var.dpl = desc->dpl; |
5105 | var.db = desc->d; | |
5106 | var.s = desc->s; | |
5107 | var.l = desc->l; | |
5108 | var.g = desc->g; | |
5109 | var.avl = desc->avl; | |
5110 | var.present = desc->p; | |
5111 | var.unusable = !var.present; | |
5112 | var.padding = 0; | |
5113 | ||
5114 | kvm_set_segment(vcpu, &var, seg); | |
5115 | return; | |
5116 | } | |
5117 | ||
717746e3 AK |
5118 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
5119 | u32 msr_index, u64 *pdata) | |
5120 | { | |
609e36d3 PB |
5121 | struct msr_data msr; |
5122 | int r; | |
5123 | ||
5124 | msr.index = msr_index; | |
5125 | msr.host_initiated = false; | |
5126 | r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); | |
5127 | if (r) | |
5128 | return r; | |
5129 | ||
5130 | *pdata = msr.data; | |
5131 | return 0; | |
717746e3 AK |
5132 | } |
5133 | ||
5134 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
5135 | u32 msr_index, u64 data) | |
5136 | { | |
8fe8ab46 WA |
5137 | struct msr_data msr; |
5138 | ||
5139 | msr.data = data; | |
5140 | msr.index = msr_index; | |
5141 | msr.host_initiated = false; | |
5142 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
5143 | } |
5144 | ||
64d60670 PB |
5145 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
5146 | { | |
5147 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5148 | ||
5149 | return vcpu->arch.smbase; | |
5150 | } | |
5151 | ||
5152 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
5153 | { | |
5154 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5155 | ||
5156 | vcpu->arch.smbase = smbase; | |
5157 | } | |
5158 | ||
67f4d428 NA |
5159 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
5160 | u32 pmc) | |
5161 | { | |
5162 | return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); | |
5163 | } | |
5164 | ||
222d21aa AK |
5165 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
5166 | u32 pmc, u64 *pdata) | |
5167 | { | |
5168 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
5169 | } | |
5170 | ||
6c3287f7 AK |
5171 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
5172 | { | |
5173 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
5174 | } | |
5175 | ||
5037f6f3 AK |
5176 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) |
5177 | { | |
5178 | preempt_disable(); | |
5197b808 | 5179 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); |
5037f6f3 AK |
5180 | /* |
5181 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
5182 | * so it may be clear at this point. | |
5183 | */ | |
5184 | clts(); | |
5185 | } | |
5186 | ||
5187 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
5188 | { | |
5189 | preempt_enable(); | |
5190 | } | |
5191 | ||
2953538e | 5192 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 5193 | struct x86_instruction_info *info, |
c4f035c6 AK |
5194 | enum x86_intercept_stage stage) |
5195 | { | |
2953538e | 5196 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
5197 | } |
5198 | ||
0017f93a | 5199 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
bdb42f5a SB |
5200 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) |
5201 | { | |
0017f93a | 5202 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); |
bdb42f5a SB |
5203 | } |
5204 | ||
dd856efa AK |
5205 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
5206 | { | |
5207 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
5208 | } | |
5209 | ||
5210 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
5211 | { | |
5212 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
5213 | } | |
5214 | ||
801806d9 NA |
5215 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
5216 | { | |
5217 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
5218 | } | |
5219 | ||
0225fb50 | 5220 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
5221 | .read_gpr = emulator_read_gpr, |
5222 | .write_gpr = emulator_write_gpr, | |
1871c602 | 5223 | .read_std = kvm_read_guest_virt_system, |
2dafc6c2 | 5224 | .write_std = kvm_write_guest_virt_system, |
1871c602 | 5225 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
5226 | .read_emulated = emulator_read_emulated, |
5227 | .write_emulated = emulator_write_emulated, | |
5228 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 5229 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
5230 | .pio_in_emulated = emulator_pio_in_emulated, |
5231 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
5232 | .get_segment = emulator_get_segment, |
5233 | .set_segment = emulator_set_segment, | |
5951c442 | 5234 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 5235 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 5236 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
5237 | .set_gdt = emulator_set_gdt, |
5238 | .set_idt = emulator_set_idt, | |
52a46617 GN |
5239 | .get_cr = emulator_get_cr, |
5240 | .set_cr = emulator_set_cr, | |
9c537244 | 5241 | .cpl = emulator_get_cpl, |
35aa5375 GN |
5242 | .get_dr = emulator_get_dr, |
5243 | .set_dr = emulator_set_dr, | |
64d60670 PB |
5244 | .get_smbase = emulator_get_smbase, |
5245 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
5246 | .set_msr = emulator_set_msr, |
5247 | .get_msr = emulator_get_msr, | |
67f4d428 | 5248 | .check_pmc = emulator_check_pmc, |
222d21aa | 5249 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 5250 | .halt = emulator_halt, |
bcaf5cc5 | 5251 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 5252 | .fix_hypercall = emulator_fix_hypercall, |
5037f6f3 AK |
5253 | .get_fpu = emulator_get_fpu, |
5254 | .put_fpu = emulator_put_fpu, | |
c4f035c6 | 5255 | .intercept = emulator_intercept, |
bdb42f5a | 5256 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 5257 | .set_nmi_mask = emulator_set_nmi_mask, |
bbd9b64e CO |
5258 | }; |
5259 | ||
95cb2295 GN |
5260 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
5261 | { | |
37ccdcbe | 5262 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
5263 | /* |
5264 | * an sti; sti; sequence only disable interrupts for the first | |
5265 | * instruction. So, if the last instruction, be it emulated or | |
5266 | * not, left the system with the INT_STI flag enabled, it | |
5267 | * means that the last instruction is an sti. We should not | |
5268 | * leave the flag on in this case. The same goes for mov ss | |
5269 | */ | |
37ccdcbe PB |
5270 | if (int_shadow & mask) |
5271 | mask = 0; | |
6addfc42 | 5272 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 5273 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
5274 | if (!mask) |
5275 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5276 | } | |
95cb2295 GN |
5277 | } |
5278 | ||
ef54bcfe | 5279 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
5280 | { |
5281 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 5282 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
5283 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
5284 | ||
5285 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
5286 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
5287 | ctxt->exception.error_code); | |
54b8486f | 5288 | else |
da9cb575 | 5289 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 5290 | return false; |
54b8486f GN |
5291 | } |
5292 | ||
8ec4722d MG |
5293 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
5294 | { | |
adf52235 | 5295 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
5296 | int cs_db, cs_l; |
5297 | ||
8ec4722d MG |
5298 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
5299 | ||
adf52235 TY |
5300 | ctxt->eflags = kvm_get_rflags(vcpu); |
5301 | ctxt->eip = kvm_rip_read(vcpu); | |
5302 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
5303 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 5304 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
5305 | cs_db ? X86EMUL_MODE_PROT32 : |
5306 | X86EMUL_MODE_PROT16; | |
a584539b | 5307 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
5308 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
5309 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
a584539b | 5310 | ctxt->emul_flags = vcpu->arch.hflags; |
adf52235 | 5311 | |
dd856efa | 5312 | init_decode_cache(ctxt); |
7ae441ea | 5313 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
5314 | } |
5315 | ||
71f9833b | 5316 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 5317 | { |
9d74191a | 5318 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
5319 | int ret; |
5320 | ||
5321 | init_emulate_ctxt(vcpu); | |
5322 | ||
9dac77fa AK |
5323 | ctxt->op_bytes = 2; |
5324 | ctxt->ad_bytes = 2; | |
5325 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 5326 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
5327 | |
5328 | if (ret != X86EMUL_CONTINUE) | |
5329 | return EMULATE_FAIL; | |
5330 | ||
9dac77fa | 5331 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
5332 | kvm_rip_write(vcpu, ctxt->eip); |
5333 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 MG |
5334 | |
5335 | if (irq == NMI_VECTOR) | |
7460fb4a | 5336 | vcpu->arch.nmi_pending = 0; |
63995653 MG |
5337 | else |
5338 | vcpu->arch.interrupt.pending = false; | |
5339 | ||
5340 | return EMULATE_DONE; | |
5341 | } | |
5342 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
5343 | ||
6d77dbfc GN |
5344 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) |
5345 | { | |
fc3a9157 JR |
5346 | int r = EMULATE_DONE; |
5347 | ||
6d77dbfc GN |
5348 | ++vcpu->stat.insn_emulation_fail; |
5349 | trace_kvm_emulate_insn_failed(vcpu); | |
a2b9e6c1 | 5350 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
5351 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5352 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5353 | vcpu->run->internal.ndata = 0; | |
5354 | r = EMULATE_FAIL; | |
5355 | } | |
6d77dbfc | 5356 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
5357 | |
5358 | return r; | |
6d77dbfc GN |
5359 | } |
5360 | ||
93c05d3e | 5361 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
5362 | bool write_fault_to_shadow_pgtable, |
5363 | int emulation_type) | |
a6f177ef | 5364 | { |
95b3cf69 | 5365 | gpa_t gpa = cr2; |
8e3d9d06 | 5366 | pfn_t pfn; |
a6f177ef | 5367 | |
991eebf9 GN |
5368 | if (emulation_type & EMULTYPE_NO_REEXECUTE) |
5369 | return false; | |
5370 | ||
95b3cf69 XG |
5371 | if (!vcpu->arch.mmu.direct_map) { |
5372 | /* | |
5373 | * Write permission should be allowed since only | |
5374 | * write access need to be emulated. | |
5375 | */ | |
5376 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 5377 | |
95b3cf69 XG |
5378 | /* |
5379 | * If the mapping is invalid in guest, let cpu retry | |
5380 | * it to generate fault. | |
5381 | */ | |
5382 | if (gpa == UNMAPPED_GVA) | |
5383 | return true; | |
5384 | } | |
a6f177ef | 5385 | |
8e3d9d06 XG |
5386 | /* |
5387 | * Do not retry the unhandleable instruction if it faults on the | |
5388 | * readonly host memory, otherwise it will goto a infinite loop: | |
5389 | * retry instruction -> write #PF -> emulation fail -> retry | |
5390 | * instruction -> ... | |
5391 | */ | |
5392 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
5393 | |
5394 | /* | |
5395 | * If the instruction failed on the error pfn, it can not be fixed, | |
5396 | * report the error to userspace. | |
5397 | */ | |
5398 | if (is_error_noslot_pfn(pfn)) | |
5399 | return false; | |
5400 | ||
5401 | kvm_release_pfn_clean(pfn); | |
5402 | ||
5403 | /* The instructions are well-emulated on direct mmu. */ | |
5404 | if (vcpu->arch.mmu.direct_map) { | |
5405 | unsigned int indirect_shadow_pages; | |
5406 | ||
5407 | spin_lock(&vcpu->kvm->mmu_lock); | |
5408 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
5409 | spin_unlock(&vcpu->kvm->mmu_lock); | |
5410 | ||
5411 | if (indirect_shadow_pages) | |
5412 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
5413 | ||
a6f177ef | 5414 | return true; |
8e3d9d06 | 5415 | } |
a6f177ef | 5416 | |
95b3cf69 XG |
5417 | /* |
5418 | * if emulation was due to access to shadowed page table | |
5419 | * and it failed try to unshadow page and re-enter the | |
5420 | * guest to let CPU execute the instruction. | |
5421 | */ | |
5422 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
5423 | |
5424 | /* | |
5425 | * If the access faults on its page table, it can not | |
5426 | * be fixed by unprotecting shadow page and it should | |
5427 | * be reported to userspace. | |
5428 | */ | |
5429 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
5430 | } |
5431 | ||
1cb3f3ae XG |
5432 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
5433 | unsigned long cr2, int emulation_type) | |
5434 | { | |
5435 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5436 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
5437 | ||
5438 | last_retry_eip = vcpu->arch.last_retry_eip; | |
5439 | last_retry_addr = vcpu->arch.last_retry_addr; | |
5440 | ||
5441 | /* | |
5442 | * If the emulation is caused by #PF and it is non-page_table | |
5443 | * writing instruction, it means the VM-EXIT is caused by shadow | |
5444 | * page protected, we can zap the shadow page and retry this | |
5445 | * instruction directly. | |
5446 | * | |
5447 | * Note: if the guest uses a non-page-table modifying instruction | |
5448 | * on the PDE that points to the instruction, then we will unmap | |
5449 | * the instruction and go to an infinite loop. So, we cache the | |
5450 | * last retried eip and the last fault address, if we meet the eip | |
5451 | * and the address again, we can break out of the potential infinite | |
5452 | * loop. | |
5453 | */ | |
5454 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
5455 | ||
5456 | if (!(emulation_type & EMULTYPE_RETRY)) | |
5457 | return false; | |
5458 | ||
5459 | if (x86_page_table_writing_insn(ctxt)) | |
5460 | return false; | |
5461 | ||
5462 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
5463 | return false; | |
5464 | ||
5465 | vcpu->arch.last_retry_eip = ctxt->eip; | |
5466 | vcpu->arch.last_retry_addr = cr2; | |
5467 | ||
5468 | if (!vcpu->arch.mmu.direct_map) | |
5469 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
5470 | ||
22368028 | 5471 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
5472 | |
5473 | return true; | |
5474 | } | |
5475 | ||
716d51ab GN |
5476 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
5477 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
5478 | ||
64d60670 | 5479 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 5480 | { |
64d60670 PB |
5481 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
5482 | if (unlikely(vcpu->arch.smi_pending)) { | |
5483 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
5484 | vcpu->arch.smi_pending = 0; | |
cd7764fe PB |
5485 | } else { |
5486 | /* Process a latched INIT, if any. */ | |
5487 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 PB |
5488 | } |
5489 | } | |
5490 | } | |
5491 | ||
5492 | static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) | |
5493 | { | |
5494 | unsigned changed = vcpu->arch.hflags ^ emul_flags; | |
5495 | ||
a584539b | 5496 | vcpu->arch.hflags = emul_flags; |
64d60670 PB |
5497 | |
5498 | if (changed & HF_SMM_MASK) | |
5499 | kvm_smm_changed(vcpu); | |
a584539b PB |
5500 | } |
5501 | ||
4a1e10d5 PB |
5502 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
5503 | unsigned long *db) | |
5504 | { | |
5505 | u32 dr6 = 0; | |
5506 | int i; | |
5507 | u32 enable, rwlen; | |
5508 | ||
5509 | enable = dr7; | |
5510 | rwlen = dr7 >> 16; | |
5511 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5512 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5513 | dr6 |= (1 << i); | |
5514 | return dr6; | |
5515 | } | |
5516 | ||
6addfc42 | 5517 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) |
663f4c61 PB |
5518 | { |
5519 | struct kvm_run *kvm_run = vcpu->run; | |
5520 | ||
5521 | /* | |
6addfc42 PB |
5522 | * rflags is the old, "raw" value of the flags. The new value has |
5523 | * not been saved yet. | |
663f4c61 PB |
5524 | * |
5525 | * This is correct even for TF set by the guest, because "the | |
5526 | * processor will not generate this exception after the instruction | |
5527 | * that sets the TF flag". | |
5528 | */ | |
663f4c61 PB |
5529 | if (unlikely(rflags & X86_EFLAGS_TF)) { |
5530 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
6f43ed01 NA |
5531 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | |
5532 | DR6_RTM; | |
663f4c61 PB |
5533 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; |
5534 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5535 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5536 | *r = EMULATE_USER_EXIT; | |
5537 | } else { | |
5538 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5539 | /* | |
5540 | * "Certain debug exceptions may clear bit 0-3. The | |
5541 | * remaining contents of the DR6 register are never | |
5542 | * cleared by the processor". | |
5543 | */ | |
5544 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5545 | vcpu->arch.dr6 |= DR6_BS | DR6_RTM; |
663f4c61 PB |
5546 | kvm_queue_exception(vcpu, DB_VECTOR); |
5547 | } | |
5548 | } | |
5549 | } | |
5550 | ||
4a1e10d5 PB |
5551 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
5552 | { | |
4a1e10d5 PB |
5553 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
5554 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
5555 | struct kvm_run *kvm_run = vcpu->run; |
5556 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
5557 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5558 | vcpu->arch.guest_debug_dr7, |
5559 | vcpu->arch.eff_db); | |
5560 | ||
5561 | if (dr6 != 0) { | |
6f43ed01 | 5562 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 5563 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
5564 | kvm_run->debug.arch.exception = DB_VECTOR; |
5565 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5566 | *r = EMULATE_USER_EXIT; | |
5567 | return true; | |
5568 | } | |
5569 | } | |
5570 | ||
4161a569 NA |
5571 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
5572 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
5573 | unsigned long eip = kvm_get_linear_rip(vcpu); |
5574 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
5575 | vcpu->arch.dr7, |
5576 | vcpu->arch.db); | |
5577 | ||
5578 | if (dr6 != 0) { | |
5579 | vcpu->arch.dr6 &= ~15; | |
6f43ed01 | 5580 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
5581 | kvm_queue_exception(vcpu, DB_VECTOR); |
5582 | *r = EMULATE_DONE; | |
5583 | return true; | |
5584 | } | |
5585 | } | |
5586 | ||
5587 | return false; | |
5588 | } | |
5589 | ||
51d8b661 AP |
5590 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
5591 | unsigned long cr2, | |
dc25e89e AP |
5592 | int emulation_type, |
5593 | void *insn, | |
5594 | int insn_len) | |
bbd9b64e | 5595 | { |
95cb2295 | 5596 | int r; |
9d74191a | 5597 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 5598 | bool writeback = true; |
93c05d3e | 5599 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 5600 | |
93c05d3e XG |
5601 | /* |
5602 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5603 | * never reused. | |
5604 | */ | |
5605 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 5606 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 5607 | |
571008da | 5608 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 5609 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
5610 | |
5611 | /* | |
5612 | * We will reenter on the same instruction since | |
5613 | * we do not set complete_userspace_io. This does not | |
5614 | * handle watchpoints yet, those would be handled in | |
5615 | * the emulate_ops. | |
5616 | */ | |
5617 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5618 | return r; | |
5619 | ||
9d74191a TY |
5620 | ctxt->interruptibility = 0; |
5621 | ctxt->have_exception = false; | |
e0ad0b47 | 5622 | ctxt->exception.vector = -1; |
9d74191a | 5623 | ctxt->perm_ok = false; |
bbd9b64e | 5624 | |
b51e974f | 5625 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 5626 | |
9d74191a | 5627 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 5628 | |
e46479f8 | 5629 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 5630 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 5631 | if (r != EMULATION_OK) { |
4005996e AK |
5632 | if (emulation_type & EMULTYPE_TRAP_UD) |
5633 | return EMULATE_FAIL; | |
991eebf9 GN |
5634 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5635 | emulation_type)) | |
bbd9b64e | 5636 | return EMULATE_DONE; |
6d77dbfc GN |
5637 | if (emulation_type & EMULTYPE_SKIP) |
5638 | return EMULATE_FAIL; | |
5639 | return handle_emulation_failure(vcpu); | |
bbd9b64e CO |
5640 | } |
5641 | } | |
5642 | ||
ba8afb6b | 5643 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 5644 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
5645 | if (ctxt->eflags & X86_EFLAGS_RF) |
5646 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
5647 | return EMULATE_DONE; |
5648 | } | |
5649 | ||
1cb3f3ae XG |
5650 | if (retry_instruction(ctxt, cr2, emulation_type)) |
5651 | return EMULATE_DONE; | |
5652 | ||
7ae441ea | 5653 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 5654 | changes registers values during IO operation */ |
7ae441ea GN |
5655 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
5656 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 5657 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 5658 | } |
4d2179e1 | 5659 | |
5cd21917 | 5660 | restart: |
9d74191a | 5661 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 5662 | |
775fde86 JR |
5663 | if (r == EMULATION_INTERCEPTED) |
5664 | return EMULATE_DONE; | |
5665 | ||
d2ddd1c4 | 5666 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
5667 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
5668 | emulation_type)) | |
c3cd7ffa GN |
5669 | return EMULATE_DONE; |
5670 | ||
6d77dbfc | 5671 | return handle_emulation_failure(vcpu); |
bbd9b64e CO |
5672 | } |
5673 | ||
9d74191a | 5674 | if (ctxt->have_exception) { |
d2ddd1c4 | 5675 | r = EMULATE_DONE; |
ef54bcfe PB |
5676 | if (inject_emulated_exception(vcpu)) |
5677 | return r; | |
d2ddd1c4 | 5678 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
5679 | if (!vcpu->arch.pio.in) { |
5680 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 5681 | vcpu->arch.pio.count = 0; |
0912c977 | 5682 | } else { |
7ae441ea | 5683 | writeback = false; |
716d51ab GN |
5684 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
5685 | } | |
ac0a48c3 | 5686 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
5687 | } else if (vcpu->mmio_needed) { |
5688 | if (!vcpu->mmio_is_write) | |
5689 | writeback = false; | |
ac0a48c3 | 5690 | r = EMULATE_USER_EXIT; |
716d51ab | 5691 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 5692 | } else if (r == EMULATION_RESTART) |
5cd21917 | 5693 | goto restart; |
d2ddd1c4 GN |
5694 | else |
5695 | r = EMULATE_DONE; | |
f850e2e6 | 5696 | |
7ae441ea | 5697 | if (writeback) { |
6addfc42 | 5698 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 5699 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 5700 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
a584539b PB |
5701 | if (vcpu->arch.hflags != ctxt->emul_flags) |
5702 | kvm_set_hflags(vcpu, ctxt->emul_flags); | |
9d74191a | 5703 | kvm_rip_write(vcpu, ctxt->eip); |
663f4c61 | 5704 | if (r == EMULATE_DONE) |
6addfc42 | 5705 | kvm_vcpu_check_singlestep(vcpu, rflags, &r); |
38827dbd NA |
5706 | if (!ctxt->have_exception || |
5707 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) | |
5708 | __kvm_set_rflags(vcpu, ctxt->eflags); | |
6addfc42 PB |
5709 | |
5710 | /* | |
5711 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
5712 | * do nothing, and it will be requested again as soon as | |
5713 | * the shadow expires. But we still need to check here, | |
5714 | * because POPF has no interrupt shadow. | |
5715 | */ | |
5716 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
5717 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
5718 | } else |
5719 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
5720 | |
5721 | return r; | |
de7d789a | 5722 | } |
51d8b661 | 5723 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); |
de7d789a | 5724 | |
cf8f70bf | 5725 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) |
de7d789a | 5726 | { |
cf8f70bf | 5727 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
ca1d4a9e AK |
5728 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
5729 | size, port, &val, 1); | |
cf8f70bf | 5730 | /* do not return to emulator after return from userspace */ |
7972995b | 5731 | vcpu->arch.pio.count = 0; |
de7d789a CO |
5732 | return ret; |
5733 | } | |
cf8f70bf | 5734 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); |
de7d789a | 5735 | |
8cfdc000 ZA |
5736 | static void tsc_bad(void *info) |
5737 | { | |
0a3aee0d | 5738 | __this_cpu_write(cpu_tsc_khz, 0); |
8cfdc000 ZA |
5739 | } |
5740 | ||
5741 | static void tsc_khz_changed(void *data) | |
c8076604 | 5742 | { |
8cfdc000 ZA |
5743 | struct cpufreq_freqs *freq = data; |
5744 | unsigned long khz = 0; | |
5745 | ||
5746 | if (data) | |
5747 | khz = freq->new; | |
5748 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5749 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5750 | if (!khz) | |
5751 | khz = tsc_khz; | |
0a3aee0d | 5752 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
5753 | } |
5754 | ||
c8076604 GH |
5755 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
5756 | void *data) | |
5757 | { | |
5758 | struct cpufreq_freqs *freq = data; | |
5759 | struct kvm *kvm; | |
5760 | struct kvm_vcpu *vcpu; | |
5761 | int i, send_ipi = 0; | |
5762 | ||
8cfdc000 ZA |
5763 | /* |
5764 | * We allow guests to temporarily run on slowing clocks, | |
5765 | * provided we notify them after, or to run on accelerating | |
5766 | * clocks, provided we notify them before. Thus time never | |
5767 | * goes backwards. | |
5768 | * | |
5769 | * However, we have a problem. We can't atomically update | |
5770 | * the frequency of a given CPU from this function; it is | |
5771 | * merely a notifier, which can be called from any CPU. | |
5772 | * Changing the TSC frequency at arbitrary points in time | |
5773 | * requires a recomputation of local variables related to | |
5774 | * the TSC for each VCPU. We must flag these local variables | |
5775 | * to be updated and be sure the update takes place with the | |
5776 | * new frequency before any guests proceed. | |
5777 | * | |
5778 | * Unfortunately, the combination of hotplug CPU and frequency | |
5779 | * change creates an intractable locking scenario; the order | |
5780 | * of when these callouts happen is undefined with respect to | |
5781 | * CPU hotplug, and they can race with each other. As such, | |
5782 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5783 | * undefined; you can actually have a CPU frequency change take | |
5784 | * place in between the computation of X and the setting of the | |
5785 | * variable. To protect against this problem, all updates of | |
5786 | * the per_cpu tsc_khz variable are done in an interrupt | |
5787 | * protected IPI, and all callers wishing to update the value | |
5788 | * must wait for a synchronous IPI to complete (which is trivial | |
5789 | * if the caller is on the CPU already). This establishes the | |
5790 | * necessary total order on variable updates. | |
5791 | * | |
5792 | * Note that because a guest time update may take place | |
5793 | * anytime after the setting of the VCPU's request bit, the | |
5794 | * correct TSC value must be set before the request. However, | |
5795 | * to ensure the update actually makes it to any guest which | |
5796 | * starts running in hardware virtualization between the set | |
5797 | * and the acquisition of the spinlock, we must also ping the | |
5798 | * CPU after setting the request bit. | |
5799 | * | |
5800 | */ | |
5801 | ||
c8076604 GH |
5802 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
5803 | return 0; | |
5804 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5805 | return 0; | |
8cfdc000 ZA |
5806 | |
5807 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
c8076604 | 5808 | |
2f303b74 | 5809 | spin_lock(&kvm_lock); |
c8076604 | 5810 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 5811 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
5812 | if (vcpu->cpu != freq->cpu) |
5813 | continue; | |
c285545f | 5814 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
c8076604 | 5815 | if (vcpu->cpu != smp_processor_id()) |
8cfdc000 | 5816 | send_ipi = 1; |
c8076604 GH |
5817 | } |
5818 | } | |
2f303b74 | 5819 | spin_unlock(&kvm_lock); |
c8076604 GH |
5820 | |
5821 | if (freq->old < freq->new && send_ipi) { | |
5822 | /* | |
5823 | * We upscale the frequency. Must make the guest | |
5824 | * doesn't see old kvmclock values while running with | |
5825 | * the new frequency, otherwise we risk the guest sees | |
5826 | * time go backwards. | |
5827 | * | |
5828 | * In case we update the frequency for another cpu | |
5829 | * (which might be in guest context) send an interrupt | |
5830 | * to kick the cpu out of guest context. Next time | |
5831 | * guest context is entered kvmclock will be updated, | |
5832 | * so the guest will not see stale values. | |
5833 | */ | |
8cfdc000 | 5834 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); |
c8076604 GH |
5835 | } |
5836 | return 0; | |
5837 | } | |
5838 | ||
5839 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
5840 | .notifier_call = kvmclock_cpufreq_notifier |
5841 | }; | |
5842 | ||
5843 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5844 | unsigned long action, void *hcpu) | |
5845 | { | |
5846 | unsigned int cpu = (unsigned long)hcpu; | |
5847 | ||
5848 | switch (action) { | |
5849 | case CPU_ONLINE: | |
5850 | case CPU_DOWN_FAILED: | |
5851 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5852 | break; | |
5853 | case CPU_DOWN_PREPARE: | |
5854 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5855 | break; | |
5856 | } | |
5857 | return NOTIFY_OK; | |
5858 | } | |
5859 | ||
5860 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5861 | .notifier_call = kvmclock_cpu_notifier, | |
5862 | .priority = -INT_MAX | |
c8076604 GH |
5863 | }; |
5864 | ||
b820cc0c ZA |
5865 | static void kvm_timer_init(void) |
5866 | { | |
5867 | int cpu; | |
5868 | ||
c285545f | 5869 | max_tsc_khz = tsc_khz; |
460dd42e SB |
5870 | |
5871 | cpu_notifier_register_begin(); | |
b820cc0c | 5872 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
5873 | #ifdef CONFIG_CPU_FREQ |
5874 | struct cpufreq_policy policy; | |
5875 | memset(&policy, 0, sizeof(policy)); | |
3e26f230 AK |
5876 | cpu = get_cpu(); |
5877 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
5878 | if (policy.cpuinfo.max_freq) |
5879 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 5880 | put_cpu(); |
c285545f | 5881 | #endif |
b820cc0c ZA |
5882 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
5883 | CPUFREQ_TRANSITION_NOTIFIER); | |
5884 | } | |
c285545f | 5885 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); |
8cfdc000 ZA |
5886 | for_each_online_cpu(cpu) |
5887 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
460dd42e SB |
5888 | |
5889 | __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5890 | cpu_notifier_register_done(); | |
5891 | ||
b820cc0c ZA |
5892 | } |
5893 | ||
ff9d07a0 ZY |
5894 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
5895 | ||
f5132b01 | 5896 | int kvm_is_in_guest(void) |
ff9d07a0 | 5897 | { |
086c9855 | 5898 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
5899 | } |
5900 | ||
5901 | static int kvm_is_user_mode(void) | |
5902 | { | |
5903 | int user_mode = 3; | |
dcf46b94 | 5904 | |
086c9855 AS |
5905 | if (__this_cpu_read(current_vcpu)) |
5906 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5907 | |
ff9d07a0 ZY |
5908 | return user_mode != 0; |
5909 | } | |
5910 | ||
5911 | static unsigned long kvm_get_guest_ip(void) | |
5912 | { | |
5913 | unsigned long ip = 0; | |
dcf46b94 | 5914 | |
086c9855 AS |
5915 | if (__this_cpu_read(current_vcpu)) |
5916 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 5917 | |
ff9d07a0 ZY |
5918 | return ip; |
5919 | } | |
5920 | ||
5921 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5922 | .is_in_guest = kvm_is_in_guest, | |
5923 | .is_user_mode = kvm_is_user_mode, | |
5924 | .get_guest_ip = kvm_get_guest_ip, | |
5925 | }; | |
5926 | ||
5927 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5928 | { | |
086c9855 | 5929 | __this_cpu_write(current_vcpu, vcpu); |
ff9d07a0 ZY |
5930 | } |
5931 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5932 | ||
5933 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5934 | { | |
086c9855 | 5935 | __this_cpu_write(current_vcpu, NULL); |
ff9d07a0 ZY |
5936 | } |
5937 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5938 | ||
ce88decf XG |
5939 | static void kvm_set_mmio_spte_mask(void) |
5940 | { | |
5941 | u64 mask; | |
5942 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5943 | ||
5944 | /* | |
5945 | * Set the reserved bits and the present bit of an paging-structure | |
5946 | * entry to generate page fault with PFER.RSV = 1. | |
5947 | */ | |
885032b9 | 5948 | /* Mask the reserved physical address bits. */ |
d1431483 | 5949 | mask = rsvd_bits(maxphyaddr, 51); |
885032b9 XG |
5950 | |
5951 | /* Bit 62 is always reserved for 32bit host. */ | |
5952 | mask |= 0x3ull << 62; | |
5953 | ||
5954 | /* Set the present bit. */ | |
ce88decf XG |
5955 | mask |= 1ull; |
5956 | ||
5957 | #ifdef CONFIG_X86_64 | |
5958 | /* | |
5959 | * If reserved bit is not supported, clear the present bit to disable | |
5960 | * mmio page fault. | |
5961 | */ | |
5962 | if (maxphyaddr == 52) | |
5963 | mask &= ~1ull; | |
5964 | #endif | |
5965 | ||
5966 | kvm_mmu_set_mmio_spte_mask(mask); | |
5967 | } | |
5968 | ||
16e8d74d MT |
5969 | #ifdef CONFIG_X86_64 |
5970 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5971 | { | |
d828199e MT |
5972 | struct kvm *kvm; |
5973 | ||
5974 | struct kvm_vcpu *vcpu; | |
5975 | int i; | |
5976 | ||
2f303b74 | 5977 | spin_lock(&kvm_lock); |
d828199e MT |
5978 | list_for_each_entry(kvm, &vm_list, vm_list) |
5979 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 5980 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 5981 | atomic_set(&kvm_guest_has_master_clock, 0); |
2f303b74 | 5982 | spin_unlock(&kvm_lock); |
16e8d74d MT |
5983 | } |
5984 | ||
5985 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5986 | ||
5987 | /* | |
5988 | * Notification about pvclock gtod data update. | |
5989 | */ | |
5990 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5991 | void *priv) | |
5992 | { | |
5993 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5994 | struct timekeeper *tk = priv; | |
5995 | ||
5996 | update_pvclock_gtod(tk); | |
5997 | ||
5998 | /* disable master clock if host does not trust, or does not | |
5999 | * use, TSC clocksource | |
6000 | */ | |
6001 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
6002 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
6003 | queue_work(system_long_wq, &pvclock_gtod_work); | |
6004 | ||
6005 | return 0; | |
6006 | } | |
6007 | ||
6008 | static struct notifier_block pvclock_gtod_notifier = { | |
6009 | .notifier_call = pvclock_gtod_notify, | |
6010 | }; | |
6011 | #endif | |
6012 | ||
f8c16bba | 6013 | int kvm_arch_init(void *opaque) |
043405e1 | 6014 | { |
b820cc0c | 6015 | int r; |
6b61edf7 | 6016 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 6017 | |
f8c16bba ZX |
6018 | if (kvm_x86_ops) { |
6019 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
6020 | r = -EEXIST; |
6021 | goto out; | |
f8c16bba ZX |
6022 | } |
6023 | ||
6024 | if (!ops->cpu_has_kvm_support()) { | |
6025 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
6026 | r = -EOPNOTSUPP; |
6027 | goto out; | |
f8c16bba ZX |
6028 | } |
6029 | if (ops->disabled_by_bios()) { | |
6030 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
6031 | r = -EOPNOTSUPP; |
6032 | goto out; | |
f8c16bba ZX |
6033 | } |
6034 | ||
013f6a5d MT |
6035 | r = -ENOMEM; |
6036 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
6037 | if (!shared_msrs) { | |
6038 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
6039 | goto out; | |
6040 | } | |
6041 | ||
97db56ce AK |
6042 | r = kvm_mmu_module_init(); |
6043 | if (r) | |
013f6a5d | 6044 | goto out_free_percpu; |
97db56ce | 6045 | |
ce88decf | 6046 | kvm_set_mmio_spte_mask(); |
97db56ce | 6047 | |
f8c16bba | 6048 | kvm_x86_ops = ops; |
920c8377 | 6049 | |
7b52345e | 6050 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
4b12f0de | 6051 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 6052 | |
b820cc0c | 6053 | kvm_timer_init(); |
c8076604 | 6054 | |
ff9d07a0 ZY |
6055 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
6056 | ||
2acf923e DC |
6057 | if (cpu_has_xsave) |
6058 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
6059 | ||
c5cc421b | 6060 | kvm_lapic_init(); |
16e8d74d MT |
6061 | #ifdef CONFIG_X86_64 |
6062 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
6063 | #endif | |
6064 | ||
f8c16bba | 6065 | return 0; |
56c6d28a | 6066 | |
013f6a5d MT |
6067 | out_free_percpu: |
6068 | free_percpu(shared_msrs); | |
56c6d28a | 6069 | out: |
56c6d28a | 6070 | return r; |
043405e1 | 6071 | } |
8776e519 | 6072 | |
f8c16bba ZX |
6073 | void kvm_arch_exit(void) |
6074 | { | |
ff9d07a0 ZY |
6075 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
6076 | ||
888d256e JK |
6077 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
6078 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
6079 | CPUFREQ_TRANSITION_NOTIFIER); | |
8cfdc000 | 6080 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); |
16e8d74d MT |
6081 | #ifdef CONFIG_X86_64 |
6082 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
6083 | #endif | |
f8c16bba | 6084 | kvm_x86_ops = NULL; |
56c6d28a | 6085 | kvm_mmu_module_exit(); |
013f6a5d | 6086 | free_percpu(shared_msrs); |
56c6d28a | 6087 | } |
f8c16bba | 6088 | |
5cb56059 | 6089 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
6090 | { |
6091 | ++vcpu->stat.halt_exits; | |
6092 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 6093 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
6094 | return 1; |
6095 | } else { | |
6096 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
6097 | return 0; | |
6098 | } | |
6099 | } | |
5cb56059 JS |
6100 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
6101 | ||
6102 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
6103 | { | |
6104 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
6105 | return kvm_vcpu_halt(vcpu); | |
6106 | } | |
8776e519 HB |
6107 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
6108 | ||
55cd8e5a GN |
6109 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
6110 | { | |
6111 | u64 param, ingpa, outgpa, ret; | |
6112 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
6113 | bool fast, longmode; | |
55cd8e5a GN |
6114 | |
6115 | /* | |
6116 | * hypercall generates UD from non zero cpl and real mode | |
6117 | * per HYPER-V spec | |
6118 | */ | |
3eeb3288 | 6119 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
6120 | kvm_queue_exception(vcpu, UD_VECTOR); |
6121 | return 0; | |
6122 | } | |
6123 | ||
a449c7aa | 6124 | longmode = is_64_bit_mode(vcpu); |
55cd8e5a GN |
6125 | |
6126 | if (!longmode) { | |
ccd46936 GN |
6127 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
6128 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
6129 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
6130 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
6131 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
6132 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
6133 | } |
6134 | #ifdef CONFIG_X86_64 | |
6135 | else { | |
6136 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6137 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6138 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
6139 | } | |
6140 | #endif | |
6141 | ||
6142 | code = param & 0xffff; | |
6143 | fast = (param >> 16) & 0x1; | |
6144 | rep_cnt = (param >> 32) & 0xfff; | |
6145 | rep_idx = (param >> 48) & 0xfff; | |
6146 | ||
6147 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
6148 | ||
c25bc163 GN |
6149 | switch (code) { |
6150 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
6151 | kvm_vcpu_on_spin(vcpu); | |
6152 | break; | |
6153 | default: | |
6154 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
6155 | break; | |
6156 | } | |
55cd8e5a GN |
6157 | |
6158 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
6159 | if (longmode) { | |
6160 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
6161 | } else { | |
6162 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
6163 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
6164 | } | |
6165 | ||
6166 | return 1; | |
6167 | } | |
6168 | ||
6aef266c SV |
6169 | /* |
6170 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
6171 | * | |
6172 | * @apicid - apicid of vcpu to be kicked. | |
6173 | */ | |
6174 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
6175 | { | |
24d2166b | 6176 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 6177 | |
24d2166b R |
6178 | lapic_irq.shorthand = 0; |
6179 | lapic_irq.dest_mode = 0; | |
6180 | lapic_irq.dest_id = apicid; | |
93bbf0b8 | 6181 | lapic_irq.msi_redir_hint = false; |
6aef266c | 6182 | |
24d2166b | 6183 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 6184 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
6185 | } |
6186 | ||
8776e519 HB |
6187 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
6188 | { | |
6189 | unsigned long nr, a0, a1, a2, a3, ret; | |
a449c7aa | 6190 | int op_64_bit, r = 1; |
8776e519 | 6191 | |
5cb56059 JS |
6192 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
6193 | ||
55cd8e5a GN |
6194 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
6195 | return kvm_hv_hypercall(vcpu); | |
6196 | ||
5fdbf976 MT |
6197 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6198 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6199 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6200 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6201 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 6202 | |
229456fc | 6203 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 6204 | |
a449c7aa NA |
6205 | op_64_bit = is_64_bit_mode(vcpu); |
6206 | if (!op_64_bit) { | |
8776e519 HB |
6207 | nr &= 0xFFFFFFFF; |
6208 | a0 &= 0xFFFFFFFF; | |
6209 | a1 &= 0xFFFFFFFF; | |
6210 | a2 &= 0xFFFFFFFF; | |
6211 | a3 &= 0xFFFFFFFF; | |
6212 | } | |
6213 | ||
07708c4a JK |
6214 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
6215 | ret = -KVM_EPERM; | |
6216 | goto out; | |
6217 | } | |
6218 | ||
8776e519 | 6219 | switch (nr) { |
b93463aa AK |
6220 | case KVM_HC_VAPIC_POLL_IRQ: |
6221 | ret = 0; | |
6222 | break; | |
6aef266c SV |
6223 | case KVM_HC_KICK_CPU: |
6224 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
6225 | ret = 0; | |
6226 | break; | |
8776e519 HB |
6227 | default: |
6228 | ret = -KVM_ENOSYS; | |
6229 | break; | |
6230 | } | |
07708c4a | 6231 | out: |
a449c7aa NA |
6232 | if (!op_64_bit) |
6233 | ret = (u32)ret; | |
5fdbf976 | 6234 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 6235 | ++vcpu->stat.hypercalls; |
2f333bcb | 6236 | return r; |
8776e519 HB |
6237 | } |
6238 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
6239 | ||
b6785def | 6240 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 6241 | { |
d6aa1000 | 6242 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 6243 | char instruction[3]; |
5fdbf976 | 6244 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 6245 | |
8776e519 | 6246 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 6247 | |
9d74191a | 6248 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); |
8776e519 HB |
6249 | } |
6250 | ||
b6c7a5dc HB |
6251 | /* |
6252 | * Check if userspace requested an interrupt window, and that the | |
6253 | * interrupt window is open. | |
6254 | * | |
6255 | * No need to exit to userspace if we already have an interrupt queued. | |
6256 | */ | |
851ba692 | 6257 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6258 | { |
8061823a | 6259 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 6260 | vcpu->run->request_interrupt_window && |
5df56646 | 6261 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
6262 | } |
6263 | ||
851ba692 | 6264 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 6265 | { |
851ba692 AK |
6266 | struct kvm_run *kvm_run = vcpu->run; |
6267 | ||
91586a3b | 6268 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 6269 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 6270 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 6271 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 6272 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 6273 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 6274 | else |
b6c7a5dc | 6275 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
6276 | kvm_arch_interrupt_allowed(vcpu) && |
6277 | !kvm_cpu_has_interrupt(vcpu) && | |
6278 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
6279 | } |
6280 | ||
95ba8273 GN |
6281 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
6282 | { | |
6283 | int max_irr, tpr; | |
6284 | ||
6285 | if (!kvm_x86_ops->update_cr8_intercept) | |
6286 | return; | |
6287 | ||
88c808fd AK |
6288 | if (!vcpu->arch.apic) |
6289 | return; | |
6290 | ||
8db3baa2 GN |
6291 | if (!vcpu->arch.apic->vapic_addr) |
6292 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
6293 | else | |
6294 | max_irr = -1; | |
95ba8273 GN |
6295 | |
6296 | if (max_irr != -1) | |
6297 | max_irr >>= 4; | |
6298 | ||
6299 | tpr = kvm_lapic_get_cr8(vcpu); | |
6300 | ||
6301 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
6302 | } | |
6303 | ||
b6b8a145 | 6304 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 6305 | { |
b6b8a145 JK |
6306 | int r; |
6307 | ||
95ba8273 | 6308 | /* try to reinject previous events if any */ |
b59bb7bd | 6309 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
6310 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
6311 | vcpu->arch.exception.has_error_code, | |
6312 | vcpu->arch.exception.error_code); | |
d6e8c854 NA |
6313 | |
6314 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) | |
6315 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
6316 | X86_EFLAGS_RF); | |
6317 | ||
6bdf0662 NA |
6318 | if (vcpu->arch.exception.nr == DB_VECTOR && |
6319 | (vcpu->arch.dr7 & DR7_GD)) { | |
6320 | vcpu->arch.dr7 &= ~DR7_GD; | |
6321 | kvm_update_dr7(vcpu); | |
6322 | } | |
6323 | ||
b59bb7bd GN |
6324 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
6325 | vcpu->arch.exception.has_error_code, | |
ce7ddec4 JR |
6326 | vcpu->arch.exception.error_code, |
6327 | vcpu->arch.exception.reinject); | |
b6b8a145 | 6328 | return 0; |
b59bb7bd GN |
6329 | } |
6330 | ||
95ba8273 GN |
6331 | if (vcpu->arch.nmi_injected) { |
6332 | kvm_x86_ops->set_nmi(vcpu); | |
b6b8a145 | 6333 | return 0; |
95ba8273 GN |
6334 | } |
6335 | ||
6336 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 6337 | kvm_x86_ops->set_irq(vcpu); |
b6b8a145 JK |
6338 | return 0; |
6339 | } | |
6340 | ||
6341 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6342 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6343 | if (r != 0) | |
6344 | return r; | |
95ba8273 GN |
6345 | } |
6346 | ||
6347 | /* try to inject new event if pending */ | |
6348 | if (vcpu->arch.nmi_pending) { | |
6349 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
7460fb4a | 6350 | --vcpu->arch.nmi_pending; |
95ba8273 GN |
6351 | vcpu->arch.nmi_injected = true; |
6352 | kvm_x86_ops->set_nmi(vcpu); | |
6353 | } | |
c7c9c56c | 6354 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
6355 | /* |
6356 | * Because interrupts can be injected asynchronously, we are | |
6357 | * calling check_nested_events again here to avoid a race condition. | |
6358 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
6359 | * proposal and current concerns. Perhaps we should be setting | |
6360 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
6361 | */ | |
6362 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
6363 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
6364 | if (r != 0) | |
6365 | return r; | |
6366 | } | |
95ba8273 | 6367 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
6368 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
6369 | false); | |
6370 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
6371 | } |
6372 | } | |
b6b8a145 | 6373 | return 0; |
95ba8273 GN |
6374 | } |
6375 | ||
7460fb4a AK |
6376 | static void process_nmi(struct kvm_vcpu *vcpu) |
6377 | { | |
6378 | unsigned limit = 2; | |
6379 | ||
6380 | /* | |
6381 | * x86 is limited to one NMI running, and one NMI pending after it. | |
6382 | * If an NMI is already in progress, limit further NMIs to just one. | |
6383 | * Otherwise, allow two (and we'll inject the first one immediately). | |
6384 | */ | |
6385 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
6386 | limit = 1; | |
6387 | ||
6388 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
6389 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
6390 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6391 | } | |
6392 | ||
64d60670 PB |
6393 | static void process_smi(struct kvm_vcpu *vcpu) |
6394 | { | |
6395 | if (is_smm(vcpu)) { | |
6396 | vcpu->arch.smi_pending = true; | |
6397 | return; | |
6398 | } | |
6399 | ||
6400 | printk_once(KERN_DEBUG "Ignoring guest SMI\n"); | |
6401 | } | |
6402 | ||
3d81bc7e | 6403 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c YZ |
6404 | { |
6405 | u64 eoi_exit_bitmap[4]; | |
cf9e65b7 | 6406 | u32 tmr[8]; |
c7c9c56c | 6407 | |
3d81bc7e YZ |
6408 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
6409 | return; | |
c7c9c56c YZ |
6410 | |
6411 | memset(eoi_exit_bitmap, 0, 32); | |
cf9e65b7 | 6412 | memset(tmr, 0, 32); |
c7c9c56c | 6413 | |
cf9e65b7 | 6414 | kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); |
c7c9c56c | 6415 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
cf9e65b7 | 6416 | kvm_apic_update_tmr(vcpu, tmr); |
c7c9c56c YZ |
6417 | } |
6418 | ||
a70656b6 RK |
6419 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) |
6420 | { | |
6421 | ++vcpu->stat.tlb_flush; | |
6422 | kvm_x86_ops->tlb_flush(vcpu); | |
6423 | } | |
6424 | ||
4256f43f TC |
6425 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
6426 | { | |
c24ae0dc TC |
6427 | struct page *page = NULL; |
6428 | ||
f439ed27 PB |
6429 | if (!irqchip_in_kernel(vcpu->kvm)) |
6430 | return; | |
6431 | ||
4256f43f TC |
6432 | if (!kvm_x86_ops->set_apic_access_page_addr) |
6433 | return; | |
6434 | ||
c24ae0dc | 6435 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
6436 | if (is_error_page(page)) |
6437 | return; | |
c24ae0dc TC |
6438 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
6439 | ||
6440 | /* | |
6441 | * Do not pin apic access page in memory, the MMU notifier | |
6442 | * will call us again if it is migrated or swapped out. | |
6443 | */ | |
6444 | put_page(page); | |
4256f43f TC |
6445 | } |
6446 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
6447 | ||
fe71557a TC |
6448 | void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, |
6449 | unsigned long address) | |
6450 | { | |
c24ae0dc TC |
6451 | /* |
6452 | * The physical address of apic access page is stored in the VMCS. | |
6453 | * Update it when it becomes invalid. | |
6454 | */ | |
6455 | if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) | |
6456 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
fe71557a TC |
6457 | } |
6458 | ||
9357d939 | 6459 | /* |
362c698f | 6460 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
6461 | * exiting to the userspace. Otherwise, the value will be returned to the |
6462 | * userspace. | |
6463 | */ | |
851ba692 | 6464 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
6465 | { |
6466 | int r; | |
6a8b1d13 | 6467 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 6468 | vcpu->run->request_interrupt_window; |
730dca42 | 6469 | bool req_immediate_exit = false; |
b6c7a5dc | 6470 | |
3e007509 | 6471 | if (vcpu->requests) { |
a8eeb04a | 6472 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 6473 | kvm_mmu_unload(vcpu); |
a8eeb04a | 6474 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 6475 | __kvm_migrate_timers(vcpu); |
d828199e MT |
6476 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6477 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
6478 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
6479 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
6480 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
6481 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
6482 | if (unlikely(r)) |
6483 | goto out; | |
6484 | } | |
a8eeb04a | 6485 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 6486 | kvm_mmu_sync_roots(vcpu); |
a8eeb04a | 6487 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
a70656b6 | 6488 | kvm_vcpu_flush_tlb(vcpu); |
a8eeb04a | 6489 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 6490 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
6491 | r = 0; |
6492 | goto out; | |
6493 | } | |
a8eeb04a | 6494 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 6495 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
6496 | r = 0; |
6497 | goto out; | |
6498 | } | |
a8eeb04a | 6499 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { |
02daab21 AK |
6500 | vcpu->fpu_active = 0; |
6501 | kvm_x86_ops->fpu_deactivate(vcpu); | |
6502 | } | |
af585b92 GN |
6503 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
6504 | /* Page is swapped out. Do synthetic halt */ | |
6505 | vcpu->arch.apf.halted = true; | |
6506 | r = 1; | |
6507 | goto out; | |
6508 | } | |
c9aaa895 GC |
6509 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
6510 | record_steal_time(vcpu); | |
64d60670 PB |
6511 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
6512 | process_smi(vcpu); | |
7460fb4a AK |
6513 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
6514 | process_nmi(vcpu); | |
f5132b01 GN |
6515 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
6516 | kvm_handle_pmu_event(vcpu); | |
6517 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
6518 | kvm_deliver_pmi(vcpu); | |
3d81bc7e YZ |
6519 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
6520 | vcpu_scan_ioapic(vcpu); | |
4256f43f TC |
6521 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
6522 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2f52d58c | 6523 | } |
b93463aa | 6524 | |
b463a6f7 | 6525 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
66450a21 JK |
6526 | kvm_apic_accept_events(vcpu); |
6527 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
6528 | r = 1; | |
6529 | goto out; | |
6530 | } | |
6531 | ||
b6b8a145 JK |
6532 | if (inject_pending_event(vcpu, req_int_win) != 0) |
6533 | req_immediate_exit = true; | |
b463a6f7 | 6534 | /* enable NMI/IRQ window open exits if needed */ |
b6b8a145 | 6535 | else if (vcpu->arch.nmi_pending) |
c9a7953f | 6536 | kvm_x86_ops->enable_nmi_window(vcpu); |
c7c9c56c | 6537 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) |
c9a7953f | 6538 | kvm_x86_ops->enable_irq_window(vcpu); |
b463a6f7 AK |
6539 | |
6540 | if (kvm_lapic_enabled(vcpu)) { | |
c7c9c56c YZ |
6541 | /* |
6542 | * Update architecture specific hints for APIC | |
6543 | * virtual interrupt delivery. | |
6544 | */ | |
6545 | if (kvm_x86_ops->hwapic_irr_update) | |
6546 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
6547 | kvm_lapic_find_highest_irr(vcpu)); | |
b463a6f7 AK |
6548 | update_cr8_intercept(vcpu); |
6549 | kvm_lapic_sync_to_vapic(vcpu); | |
6550 | } | |
6551 | } | |
6552 | ||
d8368af8 AK |
6553 | r = kvm_mmu_reload(vcpu); |
6554 | if (unlikely(r)) { | |
d905c069 | 6555 | goto cancel_injection; |
d8368af8 AK |
6556 | } |
6557 | ||
b6c7a5dc HB |
6558 | preempt_disable(); |
6559 | ||
6560 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
6561 | if (vcpu->fpu_active) |
6562 | kvm_load_guest_fpu(vcpu); | |
2acf923e | 6563 | kvm_load_guest_xcr0(vcpu); |
b6c7a5dc | 6564 | |
6b7e2d09 XG |
6565 | vcpu->mode = IN_GUEST_MODE; |
6566 | ||
01b71917 MT |
6567 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
6568 | ||
6b7e2d09 XG |
6569 | /* We should set ->mode before check ->requests, |
6570 | * see the comment in make_all_cpus_request. | |
6571 | */ | |
01b71917 | 6572 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 6573 | |
d94e1dc9 | 6574 | local_irq_disable(); |
32f88400 | 6575 | |
6b7e2d09 | 6576 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests |
d94e1dc9 | 6577 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 6578 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6579 | smp_wmb(); |
6c142801 AK |
6580 | local_irq_enable(); |
6581 | preempt_enable(); | |
01b71917 | 6582 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 6583 | r = 1; |
d905c069 | 6584 | goto cancel_injection; |
6c142801 AK |
6585 | } |
6586 | ||
d6185f20 NHE |
6587 | if (req_immediate_exit) |
6588 | smp_send_reschedule(vcpu->cpu); | |
6589 | ||
ccf73aaf | 6590 | __kvm_guest_enter(); |
b6c7a5dc | 6591 | |
42dbaa5a | 6592 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
6593 | set_debugreg(0, 7); |
6594 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
6595 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
6596 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
6597 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 6598 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 6599 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 6600 | } |
b6c7a5dc | 6601 | |
229456fc | 6602 | trace_kvm_entry(vcpu->vcpu_id); |
d0659d94 | 6603 | wait_lapic_expire(vcpu); |
851ba692 | 6604 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 6605 | |
c77fb5fe PB |
6606 | /* |
6607 | * Do this here before restoring debug registers on the host. And | |
6608 | * since we do this before handling the vmexit, a DR access vmexit | |
6609 | * can (a) read the correct value of the debug registers, (b) set | |
6610 | * KVM_DEBUGREG_WONT_EXIT again. | |
6611 | */ | |
6612 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
6613 | int i; | |
6614 | ||
6615 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); | |
6616 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
6617 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6618 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
6619 | } | |
6620 | ||
24f1e32c FW |
6621 | /* |
6622 | * If the guest has used debug registers, at least dr7 | |
6623 | * will be disabled while returning to the host. | |
6624 | * If we don't have active breakpoints in the host, we don't | |
6625 | * care about the messed up debug address registers. But if | |
6626 | * we have some of them active, restore the old state. | |
6627 | */ | |
59d8eb53 | 6628 | if (hw_breakpoint_active()) |
24f1e32c | 6629 | hw_breakpoint_restore(); |
42dbaa5a | 6630 | |
886b470c MT |
6631 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, |
6632 | native_read_tsc()); | |
1d5f066e | 6633 | |
6b7e2d09 | 6634 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 6635 | smp_wmb(); |
a547c6db YZ |
6636 | |
6637 | /* Interrupt is enabled by handle_external_intr() */ | |
6638 | kvm_x86_ops->handle_external_intr(vcpu); | |
b6c7a5dc HB |
6639 | |
6640 | ++vcpu->stat.exits; | |
6641 | ||
6642 | /* | |
6643 | * We must have an instruction between local_irq_enable() and | |
6644 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6645 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6646 | * But we need to prevent reordering, hence this barrier(): | |
6647 | */ | |
6648 | barrier(); | |
6649 | ||
6650 | kvm_guest_exit(); | |
6651 | ||
6652 | preempt_enable(); | |
6653 | ||
f656ce01 | 6654 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 6655 | |
b6c7a5dc HB |
6656 | /* |
6657 | * Profile KVM exit RIPs: | |
6658 | */ | |
6659 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
6660 | unsigned long rip = kvm_rip_read(vcpu); |
6661 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
6662 | } |
6663 | ||
cc578287 ZA |
6664 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
6665 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 6666 | |
5cfb1d5a MT |
6667 | if (vcpu->arch.apic_attention) |
6668 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 6669 | |
851ba692 | 6670 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
6671 | return r; |
6672 | ||
6673 | cancel_injection: | |
6674 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
6675 | if (unlikely(vcpu->arch.apic_attention)) |
6676 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
6677 | out: |
6678 | return r; | |
6679 | } | |
b6c7a5dc | 6680 | |
362c698f PB |
6681 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
6682 | { | |
9c8fd1ba PB |
6683 | if (!kvm_arch_vcpu_runnable(vcpu)) { |
6684 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
6685 | kvm_vcpu_block(vcpu); | |
6686 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
6687 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) | |
6688 | return 1; | |
6689 | } | |
362c698f PB |
6690 | |
6691 | kvm_apic_accept_events(vcpu); | |
6692 | switch(vcpu->arch.mp_state) { | |
6693 | case KVM_MP_STATE_HALTED: | |
6694 | vcpu->arch.pv.pv_unhalted = false; | |
6695 | vcpu->arch.mp_state = | |
6696 | KVM_MP_STATE_RUNNABLE; | |
6697 | case KVM_MP_STATE_RUNNABLE: | |
6698 | vcpu->arch.apf.halted = false; | |
6699 | break; | |
6700 | case KVM_MP_STATE_INIT_RECEIVED: | |
6701 | break; | |
6702 | default: | |
6703 | return -EINTR; | |
6704 | break; | |
6705 | } | |
6706 | return 1; | |
6707 | } | |
09cec754 | 6708 | |
362c698f | 6709 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
6710 | { |
6711 | int r; | |
f656ce01 | 6712 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 6713 | |
f656ce01 | 6714 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6715 | |
362c698f | 6716 | for (;;) { |
af585b92 GN |
6717 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
6718 | !vcpu->arch.apf.halted) | |
851ba692 | 6719 | r = vcpu_enter_guest(vcpu); |
362c698f PB |
6720 | else |
6721 | r = vcpu_block(kvm, vcpu); | |
09cec754 GN |
6722 | if (r <= 0) |
6723 | break; | |
6724 | ||
6725 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6726 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6727 | kvm_inject_pending_timer_irqs(vcpu); | |
6728 | ||
851ba692 | 6729 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 6730 | r = -EINTR; |
851ba692 | 6731 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6732 | ++vcpu->stat.request_irq_exits; |
362c698f | 6733 | break; |
09cec754 | 6734 | } |
af585b92 GN |
6735 | |
6736 | kvm_check_async_pf_completion(vcpu); | |
6737 | ||
09cec754 GN |
6738 | if (signal_pending(current)) { |
6739 | r = -EINTR; | |
851ba692 | 6740 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 6741 | ++vcpu->stat.signal_exits; |
362c698f | 6742 | break; |
09cec754 GN |
6743 | } |
6744 | if (need_resched()) { | |
f656ce01 | 6745 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 6746 | cond_resched(); |
f656ce01 | 6747 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 6748 | } |
b6c7a5dc HB |
6749 | } |
6750 | ||
f656ce01 | 6751 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
6752 | |
6753 | return r; | |
6754 | } | |
6755 | ||
716d51ab GN |
6756 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
6757 | { | |
6758 | int r; | |
6759 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6760 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6761 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6762 | if (r != EMULATE_DONE) | |
6763 | return 0; | |
6764 | return 1; | |
6765 | } | |
6766 | ||
6767 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6768 | { | |
6769 | BUG_ON(!vcpu->arch.pio.count); | |
6770 | ||
6771 | return complete_emulated_io(vcpu); | |
6772 | } | |
6773 | ||
f78146b0 AK |
6774 | /* |
6775 | * Implements the following, as a state machine: | |
6776 | * | |
6777 | * read: | |
6778 | * for each fragment | |
87da7e66 XG |
6779 | * for each mmio piece in the fragment |
6780 | * write gpa, len | |
6781 | * exit | |
6782 | * copy data | |
f78146b0 AK |
6783 | * execute insn |
6784 | * | |
6785 | * write: | |
6786 | * for each fragment | |
87da7e66 XG |
6787 | * for each mmio piece in the fragment |
6788 | * write gpa, len | |
6789 | * copy data | |
6790 | * exit | |
f78146b0 | 6791 | */ |
716d51ab | 6792 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
6793 | { |
6794 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 6795 | struct kvm_mmio_fragment *frag; |
87da7e66 | 6796 | unsigned len; |
5287f194 | 6797 | |
716d51ab | 6798 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 6799 | |
716d51ab | 6800 | /* Complete previous fragment */ |
87da7e66 XG |
6801 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
6802 | len = min(8u, frag->len); | |
716d51ab | 6803 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
6804 | memcpy(frag->data, run->mmio.data, len); |
6805 | ||
6806 | if (frag->len <= 8) { | |
6807 | /* Switch to the next fragment. */ | |
6808 | frag++; | |
6809 | vcpu->mmio_cur_fragment++; | |
6810 | } else { | |
6811 | /* Go forward to the next mmio piece. */ | |
6812 | frag->data += len; | |
6813 | frag->gpa += len; | |
6814 | frag->len -= len; | |
6815 | } | |
6816 | ||
a08d3b3b | 6817 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 6818 | vcpu->mmio_needed = 0; |
0912c977 PB |
6819 | |
6820 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 6821 | if (vcpu->mmio_is_write) |
716d51ab GN |
6822 | return 1; |
6823 | vcpu->mmio_read_completed = 1; | |
6824 | return complete_emulated_io(vcpu); | |
6825 | } | |
87da7e66 | 6826 | |
716d51ab GN |
6827 | run->exit_reason = KVM_EXIT_MMIO; |
6828 | run->mmio.phys_addr = frag->gpa; | |
6829 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
6830 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
6831 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
6832 | run->mmio.is_write = vcpu->mmio_is_write; |
6833 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6834 | return 0; | |
5287f194 AK |
6835 | } |
6836 | ||
716d51ab | 6837 | |
b6c7a5dc HB |
6838 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6839 | { | |
6840 | int r; | |
6841 | sigset_t sigsaved; | |
6842 | ||
e5c30142 AK |
6843 | if (!tsk_used_math(current) && init_fpu(current)) |
6844 | return -ENOMEM; | |
6845 | ||
ac9f6dc0 AK |
6846 | if (vcpu->sigset_active) |
6847 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6848 | ||
a4535290 | 6849 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 6850 | kvm_vcpu_block(vcpu); |
66450a21 | 6851 | kvm_apic_accept_events(vcpu); |
d7690175 | 6852 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
6853 | r = -EAGAIN; |
6854 | goto out; | |
b6c7a5dc HB |
6855 | } |
6856 | ||
b6c7a5dc | 6857 | /* re-sync apic's tpr */ |
eea1cff9 AP |
6858 | if (!irqchip_in_kernel(vcpu->kvm)) { |
6859 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
6860 | r = -EINVAL; | |
6861 | goto out; | |
6862 | } | |
6863 | } | |
b6c7a5dc | 6864 | |
716d51ab GN |
6865 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
6866 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6867 | vcpu->arch.complete_userspace_io = NULL; | |
6868 | r = cui(vcpu); | |
6869 | if (r <= 0) | |
6870 | goto out; | |
6871 | } else | |
6872 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 6873 | |
362c698f | 6874 | r = vcpu_run(vcpu); |
b6c7a5dc HB |
6875 | |
6876 | out: | |
f1d86e46 | 6877 | post_kvm_run_save(vcpu); |
b6c7a5dc HB |
6878 | if (vcpu->sigset_active) |
6879 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6880 | ||
b6c7a5dc HB |
6881 | return r; |
6882 | } | |
6883 | ||
6884 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6885 | { | |
7ae441ea GN |
6886 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
6887 | /* | |
6888 | * We are here if userspace calls get_regs() in the middle of | |
6889 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 6890 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
6891 | * that usually, but some bad designed PV devices (vmware |
6892 | * backdoor interface) need this to work | |
6893 | */ | |
dd856efa | 6894 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
6895 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
6896 | } | |
5fdbf976 MT |
6897 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
6898 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6899 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6900 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6901 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6902 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6903 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6904 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 6905 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6906 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
6907 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6908 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6909 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6910 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6911 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6912 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6913 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
6914 | #endif |
6915 | ||
5fdbf976 | 6916 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 6917 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc | 6918 | |
b6c7a5dc HB |
6919 | return 0; |
6920 | } | |
6921 | ||
6922 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6923 | { | |
7ae441ea GN |
6924 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
6925 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6926 | ||
5fdbf976 MT |
6927 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
6928 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6929 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6930 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6931 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6932 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6933 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6934 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 6935 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
6936 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
6937 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6938 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6939 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6940 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6941 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6942 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6943 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
6944 | #endif |
6945 | ||
5fdbf976 | 6946 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 6947 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 6948 | |
b4f14abd JK |
6949 | vcpu->arch.exception.pending = false; |
6950 | ||
3842d135 AK |
6951 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6952 | ||
b6c7a5dc HB |
6953 | return 0; |
6954 | } | |
6955 | ||
b6c7a5dc HB |
6956 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
6957 | { | |
6958 | struct kvm_segment cs; | |
6959 | ||
3e6e0aab | 6960 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
6961 | *db = cs.db; |
6962 | *l = cs.l; | |
6963 | } | |
6964 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6965 | ||
6966 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6967 | struct kvm_sregs *sregs) | |
6968 | { | |
89a27f4d | 6969 | struct desc_ptr dt; |
b6c7a5dc | 6970 | |
3e6e0aab GT |
6971 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
6972 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6973 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6974 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6975 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6976 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 6977 | |
3e6e0aab GT |
6978 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
6979 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
6980 | |
6981 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
6982 | sregs->idt.limit = dt.size; |
6983 | sregs->idt.base = dt.address; | |
b6c7a5dc | 6984 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
6985 | sregs->gdt.limit = dt.size; |
6986 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 6987 | |
4d4ec087 | 6988 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 6989 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 6990 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 6991 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 6992 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 6993 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
6994 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6995 | ||
923c61bb | 6996 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 6997 | |
36752c9b | 6998 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
6999 | set_bit(vcpu->arch.interrupt.nr, |
7000 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 7001 | |
b6c7a5dc HB |
7002 | return 0; |
7003 | } | |
7004 | ||
62d9f0db MT |
7005 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
7006 | struct kvm_mp_state *mp_state) | |
7007 | { | |
66450a21 | 7008 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
7009 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
7010 | vcpu->arch.pv.pv_unhalted) | |
7011 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
7012 | else | |
7013 | mp_state->mp_state = vcpu->arch.mp_state; | |
7014 | ||
62d9f0db MT |
7015 | return 0; |
7016 | } | |
7017 | ||
7018 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
7019 | struct kvm_mp_state *mp_state) | |
7020 | { | |
66450a21 JK |
7021 | if (!kvm_vcpu_has_lapic(vcpu) && |
7022 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
7023 | return -EINVAL; | |
7024 | ||
7025 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
7026 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
7027 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
7028 | } else | |
7029 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 7030 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
62d9f0db MT |
7031 | return 0; |
7032 | } | |
7033 | ||
7f3d35fd KW |
7034 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
7035 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 7036 | { |
9d74191a | 7037 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 7038 | int ret; |
e01c2426 | 7039 | |
8ec4722d | 7040 | init_emulate_ctxt(vcpu); |
c697518a | 7041 | |
7f3d35fd | 7042 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 7043 | has_error_code, error_code); |
c697518a | 7044 | |
c697518a | 7045 | if (ret) |
19d04437 | 7046 | return EMULATE_FAIL; |
37817f29 | 7047 | |
9d74191a TY |
7048 | kvm_rip_write(vcpu, ctxt->eip); |
7049 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 7050 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 7051 | return EMULATE_DONE; |
37817f29 IE |
7052 | } |
7053 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
7054 | ||
b6c7a5dc HB |
7055 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
7056 | struct kvm_sregs *sregs) | |
7057 | { | |
58cb628d | 7058 | struct msr_data apic_base_msr; |
b6c7a5dc | 7059 | int mmu_reset_needed = 0; |
63f42e02 | 7060 | int pending_vec, max_bits, idx; |
89a27f4d | 7061 | struct desc_ptr dt; |
b6c7a5dc | 7062 | |
6d1068b3 PM |
7063 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) |
7064 | return -EINVAL; | |
7065 | ||
89a27f4d GN |
7066 | dt.size = sregs->idt.limit; |
7067 | dt.address = sregs->idt.base; | |
b6c7a5dc | 7068 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
7069 | dt.size = sregs->gdt.limit; |
7070 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
7071 | kvm_x86_ops->set_gdt(vcpu, &dt); |
7072 | ||
ad312c7c | 7073 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 7074 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 7075 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 7076 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 7077 | |
2d3ad1f4 | 7078 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 7079 | |
f6801dff | 7080 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 7081 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
58cb628d JK |
7082 | apic_base_msr.data = sregs->apic_base; |
7083 | apic_base_msr.host_initiated = true; | |
7084 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
b6c7a5dc | 7085 | |
4d4ec087 | 7086 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 7087 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 7088 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 7089 | |
fc78f519 | 7090 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 7091 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
3ea3aa8c | 7092 | if (sregs->cr4 & X86_CR4_OSXSAVE) |
00b27a3e | 7093 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
7094 | |
7095 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
7c93be44 | 7096 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
9f8fe504 | 7097 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
7098 | mmu_reset_needed = 1; |
7099 | } | |
63f42e02 | 7100 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
7101 | |
7102 | if (mmu_reset_needed) | |
7103 | kvm_mmu_reset_context(vcpu); | |
7104 | ||
a50abc3b | 7105 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
7106 | pending_vec = find_first_bit( |
7107 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
7108 | if (pending_vec < max_bits) { | |
66fd3f7f | 7109 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 7110 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
7111 | } |
7112 | ||
3e6e0aab GT |
7113 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
7114 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
7115 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
7116 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
7117 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
7118 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 7119 | |
3e6e0aab GT |
7120 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
7121 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 7122 | |
5f0269f5 ME |
7123 | update_cr8_intercept(vcpu); |
7124 | ||
9c3e4aab | 7125 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 7126 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 7127 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 7128 | !is_protmode(vcpu)) |
9c3e4aab MT |
7129 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7130 | ||
3842d135 AK |
7131 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
7132 | ||
b6c7a5dc HB |
7133 | return 0; |
7134 | } | |
7135 | ||
d0bfb940 JK |
7136 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
7137 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 7138 | { |
355be0b9 | 7139 | unsigned long rflags; |
ae675ef0 | 7140 | int i, r; |
b6c7a5dc | 7141 | |
4f926bf2 JK |
7142 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
7143 | r = -EBUSY; | |
7144 | if (vcpu->arch.exception.pending) | |
2122ff5e | 7145 | goto out; |
4f926bf2 JK |
7146 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
7147 | kvm_queue_exception(vcpu, DB_VECTOR); | |
7148 | else | |
7149 | kvm_queue_exception(vcpu, BP_VECTOR); | |
7150 | } | |
7151 | ||
91586a3b JK |
7152 | /* |
7153 | * Read rflags as long as potentially injected trace flags are still | |
7154 | * filtered out. | |
7155 | */ | |
7156 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
7157 | |
7158 | vcpu->guest_debug = dbg->control; | |
7159 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
7160 | vcpu->guest_debug = 0; | |
7161 | ||
7162 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
7163 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
7164 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 7165 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
7166 | } else { |
7167 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
7168 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 7169 | } |
c8639010 | 7170 | kvm_update_dr7(vcpu); |
ae675ef0 | 7171 | |
f92653ee JK |
7172 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
7173 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
7174 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 7175 | |
91586a3b JK |
7176 | /* |
7177 | * Trigger an rflags update that will inject or remove the trace | |
7178 | * flags. | |
7179 | */ | |
7180 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 7181 | |
c8639010 | 7182 | kvm_x86_ops->update_db_bp_intercept(vcpu); |
b6c7a5dc | 7183 | |
4f926bf2 | 7184 | r = 0; |
d0bfb940 | 7185 | |
2122ff5e | 7186 | out: |
b6c7a5dc HB |
7187 | |
7188 | return r; | |
7189 | } | |
7190 | ||
8b006791 ZX |
7191 | /* |
7192 | * Translate a guest virtual address to a guest physical address. | |
7193 | */ | |
7194 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
7195 | struct kvm_translation *tr) | |
7196 | { | |
7197 | unsigned long vaddr = tr->linear_address; | |
7198 | gpa_t gpa; | |
f656ce01 | 7199 | int idx; |
8b006791 | 7200 | |
f656ce01 | 7201 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 7202 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 7203 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
7204 | tr->physical_address = gpa; |
7205 | tr->valid = gpa != UNMAPPED_GVA; | |
7206 | tr->writeable = 1; | |
7207 | tr->usermode = 0; | |
8b006791 ZX |
7208 | |
7209 | return 0; | |
7210 | } | |
7211 | ||
d0752060 HB |
7212 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
7213 | { | |
98918833 SY |
7214 | struct i387_fxsave_struct *fxsave = |
7215 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 7216 | |
d0752060 HB |
7217 | memcpy(fpu->fpr, fxsave->st_space, 128); |
7218 | fpu->fcw = fxsave->cwd; | |
7219 | fpu->fsw = fxsave->swd; | |
7220 | fpu->ftwx = fxsave->twd; | |
7221 | fpu->last_opcode = fxsave->fop; | |
7222 | fpu->last_ip = fxsave->rip; | |
7223 | fpu->last_dp = fxsave->rdp; | |
7224 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
7225 | ||
d0752060 HB |
7226 | return 0; |
7227 | } | |
7228 | ||
7229 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
7230 | { | |
98918833 SY |
7231 | struct i387_fxsave_struct *fxsave = |
7232 | &vcpu->arch.guest_fpu.state->fxsave; | |
d0752060 | 7233 | |
d0752060 HB |
7234 | memcpy(fxsave->st_space, fpu->fpr, 128); |
7235 | fxsave->cwd = fpu->fcw; | |
7236 | fxsave->swd = fpu->fsw; | |
7237 | fxsave->twd = fpu->ftwx; | |
7238 | fxsave->fop = fpu->last_opcode; | |
7239 | fxsave->rip = fpu->last_ip; | |
7240 | fxsave->rdp = fpu->last_dp; | |
7241 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
7242 | ||
d0752060 HB |
7243 | return 0; |
7244 | } | |
7245 | ||
d28bc9dd | 7246 | int fx_init(struct kvm_vcpu *vcpu, bool init_event) |
d0752060 | 7247 | { |
10ab25cd JK |
7248 | int err; |
7249 | ||
7250 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
7251 | if (err) | |
7252 | return err; | |
7253 | ||
d28bc9dd NA |
7254 | if (!init_event) |
7255 | fpu_finit(&vcpu->arch.guest_fpu); | |
7256 | ||
df1daba7 PB |
7257 | if (cpu_has_xsaves) |
7258 | vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = | |
7259 | host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
d0752060 | 7260 | |
2acf923e DC |
7261 | /* |
7262 | * Ensure guest xcr0 is valid for loading | |
7263 | */ | |
7264 | vcpu->arch.xcr0 = XSTATE_FP; | |
7265 | ||
ad312c7c | 7266 | vcpu->arch.cr0 |= X86_CR0_ET; |
10ab25cd JK |
7267 | |
7268 | return 0; | |
d0752060 HB |
7269 | } |
7270 | EXPORT_SYMBOL_GPL(fx_init); | |
7271 | ||
98918833 SY |
7272 | static void fx_free(struct kvm_vcpu *vcpu) |
7273 | { | |
7274 | fpu_free(&vcpu->arch.guest_fpu); | |
7275 | } | |
7276 | ||
d0752060 HB |
7277 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) |
7278 | { | |
2608d7a1 | 7279 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
7280 | return; |
7281 | ||
2acf923e DC |
7282 | /* |
7283 | * Restore all possible states in the guest, | |
7284 | * and assume host would use all available bits. | |
7285 | * Guest xcr0 would be loaded later. | |
7286 | */ | |
7287 | kvm_put_guest_xcr0(vcpu); | |
d0752060 | 7288 | vcpu->guest_fpu_loaded = 1; |
b1a74bf8 | 7289 | __kernel_fpu_begin(); |
98918833 | 7290 | fpu_restore_checking(&vcpu->arch.guest_fpu); |
0c04851c | 7291 | trace_kvm_fpu(1); |
d0752060 | 7292 | } |
d0752060 HB |
7293 | |
7294 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
7295 | { | |
2acf923e DC |
7296 | kvm_put_guest_xcr0(vcpu); |
7297 | ||
653f52c3 RR |
7298 | if (!vcpu->guest_fpu_loaded) { |
7299 | vcpu->fpu_counter = 0; | |
d0752060 | 7300 | return; |
653f52c3 | 7301 | } |
d0752060 HB |
7302 | |
7303 | vcpu->guest_fpu_loaded = 0; | |
98918833 | 7304 | fpu_save_init(&vcpu->arch.guest_fpu); |
b1a74bf8 | 7305 | __kernel_fpu_end(); |
f096ed85 | 7306 | ++vcpu->stat.fpu_reload; |
653f52c3 RR |
7307 | /* |
7308 | * If using eager FPU mode, or if the guest is a frequent user | |
7309 | * of the FPU, just leave the FPU active for next time. | |
7310 | * Every 255 times fpu_counter rolls over to 0; a guest that uses | |
7311 | * the FPU in bursts will revert to loading it on demand. | |
7312 | */ | |
a9b4fb7e | 7313 | if (!vcpu->arch.eager_fpu) { |
653f52c3 RR |
7314 | if (++vcpu->fpu_counter < 5) |
7315 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); | |
7316 | } | |
0c04851c | 7317 | trace_kvm_fpu(0); |
d0752060 | 7318 | } |
e9b11c17 ZX |
7319 | |
7320 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
7321 | { | |
12f9a48f | 7322 | kvmclock_reset(vcpu); |
7f1ea208 | 7323 | |
f5f48ee1 | 7324 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
98918833 | 7325 | fx_free(vcpu); |
e9b11c17 ZX |
7326 | kvm_x86_ops->vcpu_free(vcpu); |
7327 | } | |
7328 | ||
7329 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
7330 | unsigned int id) | |
7331 | { | |
c447e76b LL |
7332 | struct kvm_vcpu *vcpu; |
7333 | ||
6755bae8 ZA |
7334 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
7335 | printk_once(KERN_WARNING | |
7336 | "kvm: SMP vm created on host with unstable TSC; " | |
7337 | "guest TSC will not be reliable\n"); | |
c447e76b LL |
7338 | |
7339 | vcpu = kvm_x86_ops->vcpu_create(kvm, id); | |
7340 | ||
7341 | /* | |
7342 | * Activate fpu unconditionally in case the guest needs eager FPU. It will be | |
7343 | * deactivated soon if it doesn't. | |
7344 | */ | |
7345 | kvm_x86_ops->fpu_activate(vcpu); | |
7346 | return vcpu; | |
26e5215f | 7347 | } |
e9b11c17 | 7348 | |
26e5215f AK |
7349 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
7350 | { | |
7351 | int r; | |
e9b11c17 | 7352 | |
0bed3b56 | 7353 | vcpu->arch.mtrr_state.have_fixed = 1; |
9fc77441 MT |
7354 | r = vcpu_load(vcpu); |
7355 | if (r) | |
7356 | return r; | |
d28bc9dd | 7357 | kvm_vcpu_reset(vcpu, false); |
8a3c1a33 | 7358 | kvm_mmu_setup(vcpu); |
e9b11c17 | 7359 | vcpu_put(vcpu); |
e9b11c17 | 7360 | |
26e5215f | 7361 | return r; |
e9b11c17 ZX |
7362 | } |
7363 | ||
31928aa5 | 7364 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 7365 | { |
8fe8ab46 | 7366 | struct msr_data msr; |
332967a3 | 7367 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 7368 | |
31928aa5 DD |
7369 | if (vcpu_load(vcpu)) |
7370 | return; | |
8fe8ab46 WA |
7371 | msr.data = 0x0; |
7372 | msr.index = MSR_IA32_TSC; | |
7373 | msr.host_initiated = true; | |
7374 | kvm_write_tsc(vcpu, &msr); | |
42897d86 MT |
7375 | vcpu_put(vcpu); |
7376 | ||
630994b3 MT |
7377 | if (!kvmclock_periodic_sync) |
7378 | return; | |
7379 | ||
332967a3 AJ |
7380 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
7381 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
7382 | } |
7383 | ||
d40ccc62 | 7384 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 7385 | { |
9fc77441 | 7386 | int r; |
344d9588 GN |
7387 | vcpu->arch.apf.msr_val = 0; |
7388 | ||
9fc77441 MT |
7389 | r = vcpu_load(vcpu); |
7390 | BUG_ON(r); | |
e9b11c17 ZX |
7391 | kvm_mmu_unload(vcpu); |
7392 | vcpu_put(vcpu); | |
7393 | ||
98918833 | 7394 | fx_free(vcpu); |
e9b11c17 ZX |
7395 | kvm_x86_ops->vcpu_free(vcpu); |
7396 | } | |
7397 | ||
d28bc9dd | 7398 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 7399 | { |
e69fab5d PB |
7400 | vcpu->arch.hflags = 0; |
7401 | ||
7460fb4a AK |
7402 | atomic_set(&vcpu->arch.nmi_queued, 0); |
7403 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 7404 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
7405 | kvm_clear_interrupt_queue(vcpu); |
7406 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 7407 | |
42dbaa5a | 7408 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 7409 | kvm_update_dr0123(vcpu); |
6f43ed01 | 7410 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 7411 | kvm_update_dr6(vcpu); |
42dbaa5a | 7412 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 7413 | kvm_update_dr7(vcpu); |
42dbaa5a | 7414 | |
1119022c NA |
7415 | vcpu->arch.cr2 = 0; |
7416 | ||
3842d135 | 7417 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 7418 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 7419 | vcpu->arch.st.msr_val = 0; |
3842d135 | 7420 | |
12f9a48f GC |
7421 | kvmclock_reset(vcpu); |
7422 | ||
af585b92 GN |
7423 | kvm_clear_async_pf_completion_queue(vcpu); |
7424 | kvm_async_pf_hash_reset(vcpu); | |
7425 | vcpu->arch.apf.halted = false; | |
3842d135 | 7426 | |
64d60670 | 7427 | if (!init_event) { |
d28bc9dd | 7428 | kvm_pmu_reset(vcpu); |
64d60670 PB |
7429 | vcpu->arch.smbase = 0x30000; |
7430 | } | |
f5132b01 | 7431 | |
66f7b72e JS |
7432 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
7433 | vcpu->arch.regs_avail = ~0; | |
7434 | vcpu->arch.regs_dirty = ~0; | |
7435 | ||
d28bc9dd | 7436 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
7437 | } |
7438 | ||
2b4a273b | 7439 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
7440 | { |
7441 | struct kvm_segment cs; | |
7442 | ||
7443 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
7444 | cs.selector = vector << 8; | |
7445 | cs.base = vector << 12; | |
7446 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7447 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
7448 | } |
7449 | ||
13a34e06 | 7450 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 7451 | { |
ca84d1a2 ZA |
7452 | struct kvm *kvm; |
7453 | struct kvm_vcpu *vcpu; | |
7454 | int i; | |
0dd6a6ed ZA |
7455 | int ret; |
7456 | u64 local_tsc; | |
7457 | u64 max_tsc = 0; | |
7458 | bool stable, backwards_tsc = false; | |
18863bdd AK |
7459 | |
7460 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 7461 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
7462 | if (ret != 0) |
7463 | return ret; | |
7464 | ||
7465 | local_tsc = native_read_tsc(); | |
7466 | stable = !check_tsc_unstable(); | |
7467 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7468 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7469 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 7470 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7471 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
7472 | backwards_tsc = true; | |
7473 | if (vcpu->arch.last_host_tsc > max_tsc) | |
7474 | max_tsc = vcpu->arch.last_host_tsc; | |
7475 | } | |
7476 | } | |
7477 | } | |
7478 | ||
7479 | /* | |
7480 | * Sometimes, even reliable TSCs go backwards. This happens on | |
7481 | * platforms that reset TSC during suspend or hibernate actions, but | |
7482 | * maintain synchronization. We must compensate. Fortunately, we can | |
7483 | * detect that condition here, which happens early in CPU bringup, | |
7484 | * before any KVM threads can be running. Unfortunately, we can't | |
7485 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
7486 | * enough into CPU bringup that we know how much real time has actually | |
7487 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
7488 | * variables that haven't been updated yet. | |
7489 | * | |
7490 | * So we simply find the maximum observed TSC above, then record the | |
7491 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
7492 | * the adjustment will be applied. Note that we accumulate | |
7493 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
7494 | * gets a chance to run again. In the event that no KVM threads get a | |
7495 | * chance to run, we will miss the entire elapsed period, as we'll have | |
7496 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
7497 | * loose cycle time. This isn't too big a deal, since the loss will be | |
7498 | * uniform across all VCPUs (not to mention the scenario is extremely | |
7499 | * unlikely). It is possible that a second hibernate recovery happens | |
7500 | * much faster than a first, causing the observed TSC here to be | |
7501 | * smaller; this would require additional padding adjustment, which is | |
7502 | * why we set last_host_tsc to the local tsc observed here. | |
7503 | * | |
7504 | * N.B. - this code below runs only on platforms with reliable TSC, | |
7505 | * as that is the only way backwards_tsc is set above. Also note | |
7506 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
7507 | * have the same delta_cyc adjustment applied if backwards_tsc | |
7508 | * is detected. Note further, this adjustment is only done once, | |
7509 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
7510 | * called multiple times (one for each physical CPU bringup). | |
7511 | * | |
4a969980 | 7512 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
7513 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
7514 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
7515 | * guarantee that they stay in perfect synchronization. | |
7516 | */ | |
7517 | if (backwards_tsc) { | |
7518 | u64 delta_cyc = max_tsc - local_tsc; | |
16a96021 | 7519 | backwards_tsc_observed = true; |
0dd6a6ed ZA |
7520 | list_for_each_entry(kvm, &vm_list, vm_list) { |
7521 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7522 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
7523 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 7524 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
7525 | } |
7526 | ||
7527 | /* | |
7528 | * We have to disable TSC offset matching.. if you were | |
7529 | * booting a VM while issuing an S4 host suspend.... | |
7530 | * you may have some problem. Solving this issue is | |
7531 | * left as an exercise to the reader. | |
7532 | */ | |
7533 | kvm->arch.last_tsc_nsec = 0; | |
7534 | kvm->arch.last_tsc_write = 0; | |
7535 | } | |
7536 | ||
7537 | } | |
7538 | return 0; | |
e9b11c17 ZX |
7539 | } |
7540 | ||
13a34e06 | 7541 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 7542 | { |
13a34e06 RK |
7543 | kvm_x86_ops->hardware_disable(); |
7544 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
7545 | } |
7546 | ||
7547 | int kvm_arch_hardware_setup(void) | |
7548 | { | |
9e9c3fe4 NA |
7549 | int r; |
7550 | ||
7551 | r = kvm_x86_ops->hardware_setup(); | |
7552 | if (r != 0) | |
7553 | return r; | |
7554 | ||
7555 | kvm_init_msr_list(); | |
7556 | return 0; | |
e9b11c17 ZX |
7557 | } |
7558 | ||
7559 | void kvm_arch_hardware_unsetup(void) | |
7560 | { | |
7561 | kvm_x86_ops->hardware_unsetup(); | |
7562 | } | |
7563 | ||
7564 | void kvm_arch_check_processor_compat(void *rtn) | |
7565 | { | |
7566 | kvm_x86_ops->check_processor_compatibility(rtn); | |
7567 | } | |
7568 | ||
3e515705 AK |
7569 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) |
7570 | { | |
7571 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
7572 | } | |
7573 | ||
54e9818f GN |
7574 | struct static_key kvm_no_apic_vcpu __read_mostly; |
7575 | ||
e9b11c17 ZX |
7576 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
7577 | { | |
7578 | struct page *page; | |
7579 | struct kvm *kvm; | |
7580 | int r; | |
7581 | ||
7582 | BUG_ON(vcpu->kvm == NULL); | |
7583 | kvm = vcpu->kvm; | |
7584 | ||
6aef266c | 7585 | vcpu->arch.pv.pv_unhalted = false; |
9aabc88f | 7586 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
58d269d8 | 7587 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 7588 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 7589 | else |
a4535290 | 7590 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
7591 | |
7592 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
7593 | if (!page) { | |
7594 | r = -ENOMEM; | |
7595 | goto fail; | |
7596 | } | |
ad312c7c | 7597 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 7598 | |
cc578287 | 7599 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 7600 | |
e9b11c17 ZX |
7601 | r = kvm_mmu_create(vcpu); |
7602 | if (r < 0) | |
7603 | goto fail_free_pio_data; | |
7604 | ||
7605 | if (irqchip_in_kernel(kvm)) { | |
7606 | r = kvm_create_lapic(vcpu); | |
7607 | if (r < 0) | |
7608 | goto fail_mmu_destroy; | |
54e9818f GN |
7609 | } else |
7610 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 7611 | |
890ca9ae HY |
7612 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
7613 | GFP_KERNEL); | |
7614 | if (!vcpu->arch.mce_banks) { | |
7615 | r = -ENOMEM; | |
443c39bc | 7616 | goto fail_free_lapic; |
890ca9ae HY |
7617 | } |
7618 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
7619 | ||
f1797359 WY |
7620 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { |
7621 | r = -ENOMEM; | |
f5f48ee1 | 7622 | goto fail_free_mce_banks; |
f1797359 | 7623 | } |
f5f48ee1 | 7624 | |
d28bc9dd | 7625 | r = fx_init(vcpu, false); |
66f7b72e JS |
7626 | if (r) |
7627 | goto fail_free_wbinvd_dirty_mask; | |
7628 | ||
ba904635 | 7629 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; |
0b79459b | 7630 | vcpu->arch.pv_time_enabled = false; |
d7876f1b PB |
7631 | |
7632 | vcpu->arch.guest_supported_xcr0 = 0; | |
4344ee98 | 7633 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 7634 | |
5a4f55cd EK |
7635 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
7636 | ||
74545705 RK |
7637 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; |
7638 | ||
af585b92 | 7639 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 7640 | kvm_pmu_init(vcpu); |
af585b92 | 7641 | |
e9b11c17 | 7642 | return 0; |
66f7b72e JS |
7643 | fail_free_wbinvd_dirty_mask: |
7644 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
7645 | fail_free_mce_banks: |
7646 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
7647 | fail_free_lapic: |
7648 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
7649 | fail_mmu_destroy: |
7650 | kvm_mmu_destroy(vcpu); | |
7651 | fail_free_pio_data: | |
ad312c7c | 7652 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
7653 | fail: |
7654 | return r; | |
7655 | } | |
7656 | ||
7657 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
7658 | { | |
f656ce01 MT |
7659 | int idx; |
7660 | ||
f5132b01 | 7661 | kvm_pmu_destroy(vcpu); |
36cb93fd | 7662 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 7663 | kvm_free_lapic(vcpu); |
f656ce01 | 7664 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 7665 | kvm_mmu_destroy(vcpu); |
f656ce01 | 7666 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 7667 | free_page((unsigned long)vcpu->arch.pio_data); |
54e9818f GN |
7668 | if (!irqchip_in_kernel(vcpu->kvm)) |
7669 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 | 7670 | } |
d19a9cd2 | 7671 | |
e790d9ef RK |
7672 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
7673 | { | |
ae97a3b8 | 7674 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
7675 | } |
7676 | ||
e08b9637 | 7677 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 7678 | { |
e08b9637 CO |
7679 | if (type) |
7680 | return -EINVAL; | |
7681 | ||
6ef768fa | 7682 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 7683 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
365c8868 | 7684 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
4d5c5d0f | 7685 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 7686 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 7687 | |
5550af4d SY |
7688 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
7689 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
7690 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
7691 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7692 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 7693 | |
038f8c11 | 7694 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 7695 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
7696 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
7697 | ||
7698 | pvclock_update_vm_gtod_copy(kvm); | |
53f658b3 | 7699 | |
7e44e449 | 7700 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 7701 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 7702 | |
d89f5eff | 7703 | return 0; |
d19a9cd2 ZX |
7704 | } |
7705 | ||
7706 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7707 | { | |
9fc77441 MT |
7708 | int r; |
7709 | r = vcpu_load(vcpu); | |
7710 | BUG_ON(r); | |
d19a9cd2 ZX |
7711 | kvm_mmu_unload(vcpu); |
7712 | vcpu_put(vcpu); | |
7713 | } | |
7714 | ||
7715 | static void kvm_free_vcpus(struct kvm *kvm) | |
7716 | { | |
7717 | unsigned int i; | |
988a2cae | 7718 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
7719 | |
7720 | /* | |
7721 | * Unpin any mmu pages first. | |
7722 | */ | |
af585b92 GN |
7723 | kvm_for_each_vcpu(i, vcpu, kvm) { |
7724 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 7725 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 7726 | } |
988a2cae GN |
7727 | kvm_for_each_vcpu(i, vcpu, kvm) |
7728 | kvm_arch_vcpu_free(vcpu); | |
7729 | ||
7730 | mutex_lock(&kvm->lock); | |
7731 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7732 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 7733 | |
988a2cae GN |
7734 | atomic_set(&kvm->online_vcpus, 0); |
7735 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
7736 | } |
7737 | ||
ad8ba2cd SY |
7738 | void kvm_arch_sync_events(struct kvm *kvm) |
7739 | { | |
332967a3 | 7740 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 7741 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
ba4cef31 | 7742 | kvm_free_all_assigned_devices(kvm); |
aea924f6 | 7743 | kvm_free_pit(kvm); |
ad8ba2cd SY |
7744 | } |
7745 | ||
d19a9cd2 ZX |
7746 | void kvm_arch_destroy_vm(struct kvm *kvm) |
7747 | { | |
27469d29 AH |
7748 | if (current->mm == kvm->mm) { |
7749 | /* | |
7750 | * Free memory regions allocated on behalf of userspace, | |
7751 | * unless the the memory map has changed due to process exit | |
7752 | * or fd copying. | |
7753 | */ | |
7754 | struct kvm_userspace_memory_region mem; | |
7755 | memset(&mem, 0, sizeof(mem)); | |
7756 | mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
7757 | kvm_set_memory_region(kvm, &mem); | |
7758 | ||
7759 | mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
7760 | kvm_set_memory_region(kvm, &mem); | |
7761 | ||
7762 | mem.slot = TSS_PRIVATE_MEMSLOT; | |
7763 | kvm_set_memory_region(kvm, &mem); | |
7764 | } | |
6eb55818 | 7765 | kvm_iommu_unmap_guest(kvm); |
d7deeeb0 ZX |
7766 | kfree(kvm->arch.vpic); |
7767 | kfree(kvm->arch.vioapic); | |
d19a9cd2 | 7768 | kvm_free_vcpus(kvm); |
1e08ec4a | 7769 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
d19a9cd2 | 7770 | } |
0de10343 | 7771 | |
5587027c | 7772 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
7773 | struct kvm_memory_slot *dont) |
7774 | { | |
7775 | int i; | |
7776 | ||
d89cc617 TY |
7777 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
7778 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 7779 | kvfree(free->arch.rmap[i]); |
d89cc617 | 7780 | free->arch.rmap[i] = NULL; |
77d11309 | 7781 | } |
d89cc617 TY |
7782 | if (i == 0) |
7783 | continue; | |
7784 | ||
7785 | if (!dont || free->arch.lpage_info[i - 1] != | |
7786 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 7787 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 7788 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7789 | } |
7790 | } | |
7791 | } | |
7792 | ||
5587027c AK |
7793 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
7794 | unsigned long npages) | |
db3fe4eb TY |
7795 | { |
7796 | int i; | |
7797 | ||
d89cc617 | 7798 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
db3fe4eb TY |
7799 | unsigned long ugfn; |
7800 | int lpages; | |
d89cc617 | 7801 | int level = i + 1; |
db3fe4eb TY |
7802 | |
7803 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7804 | slot->base_gfn, level) + 1; | |
7805 | ||
d89cc617 TY |
7806 | slot->arch.rmap[i] = |
7807 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7808 | if (!slot->arch.rmap[i]) | |
77d11309 | 7809 | goto out_free; |
d89cc617 TY |
7810 | if (i == 0) |
7811 | continue; | |
77d11309 | 7812 | |
d89cc617 TY |
7813 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * |
7814 | sizeof(*slot->arch.lpage_info[i - 1])); | |
7815 | if (!slot->arch.lpage_info[i - 1]) | |
db3fe4eb TY |
7816 | goto out_free; |
7817 | ||
7818 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
d89cc617 | 7819 | slot->arch.lpage_info[i - 1][0].write_count = 1; |
db3fe4eb | 7820 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
d89cc617 | 7821 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; |
db3fe4eb TY |
7822 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
7823 | /* | |
7824 | * If the gfn and userspace address are not aligned wrt each | |
7825 | * other, or if explicitly asked to, disable large page | |
7826 | * support for this slot | |
7827 | */ | |
7828 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7829 | !kvm_largepages_enabled()) { | |
7830 | unsigned long j; | |
7831 | ||
7832 | for (j = 0; j < lpages; ++j) | |
d89cc617 | 7833 | slot->arch.lpage_info[i - 1][j].write_count = 1; |
db3fe4eb TY |
7834 | } |
7835 | } | |
7836 | ||
7837 | return 0; | |
7838 | ||
7839 | out_free: | |
d89cc617 | 7840 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 7841 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
7842 | slot->arch.rmap[i] = NULL; |
7843 | if (i == 0) | |
7844 | continue; | |
7845 | ||
548ef284 | 7846 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 7847 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
7848 | } |
7849 | return -ENOMEM; | |
7850 | } | |
7851 | ||
15f46015 | 7852 | void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) |
e59dbe09 | 7853 | { |
e6dff7d1 TY |
7854 | /* |
7855 | * memslots->generation has been incremented. | |
7856 | * mmio generation may have reached its maximum value. | |
7857 | */ | |
7858 | kvm_mmu_invalidate_mmio_sptes(kvm); | |
e59dbe09 TY |
7859 | } |
7860 | ||
f7784b8e MT |
7861 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
7862 | struct kvm_memory_slot *memslot, | |
09170a49 | 7863 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 7864 | enum kvm_mr_change change) |
0de10343 | 7865 | { |
7a905b14 TY |
7866 | /* |
7867 | * Only private memory slots need to be mapped here since | |
7868 | * KVM_SET_MEMORY_REGION ioctl is no longer supported. | |
0de10343 | 7869 | */ |
7b6195a9 | 7870 | if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { |
7a905b14 | 7871 | unsigned long userspace_addr; |
604b38ac | 7872 | |
7a905b14 TY |
7873 | /* |
7874 | * MAP_SHARED to prevent internal slot pages from being moved | |
7875 | * by fork()/COW. | |
7876 | */ | |
7b6195a9 | 7877 | userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, |
7a905b14 TY |
7878 | PROT_READ | PROT_WRITE, |
7879 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
0de10343 | 7880 | |
7a905b14 TY |
7881 | if (IS_ERR((void *)userspace_addr)) |
7882 | return PTR_ERR((void *)userspace_addr); | |
604b38ac | 7883 | |
7a905b14 | 7884 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
7885 | } |
7886 | ||
f7784b8e MT |
7887 | return 0; |
7888 | } | |
7889 | ||
88178fd4 KH |
7890 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
7891 | struct kvm_memory_slot *new) | |
7892 | { | |
7893 | /* Still write protect RO slot */ | |
7894 | if (new->flags & KVM_MEM_READONLY) { | |
7895 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7896 | return; | |
7897 | } | |
7898 | ||
7899 | /* | |
7900 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
7901 | * | |
7902 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
7903 | * | |
7904 | * - KVM_MR_CREATE with dirty logging is disabled | |
7905 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
7906 | * | |
7907 | * The reason is, in case of PML, we need to set D-bit for any slots | |
7908 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
7909 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
7910 | * guarantees leaving PML enabled during guest's lifetime won't have | |
7911 | * any additonal overhead from PML when guest is running with dirty | |
7912 | * logging disabled for memory slots. | |
7913 | * | |
7914 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
7915 | * to dirty logging mode. | |
7916 | * | |
7917 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
7918 | * | |
7919 | * In case of write protect: | |
7920 | * | |
7921 | * Write protect all pages for dirty logging. | |
7922 | * | |
7923 | * All the sptes including the large sptes which point to this | |
7924 | * slot are set to readonly. We can not create any new large | |
7925 | * spte on this slot until the end of the logging. | |
7926 | * | |
7927 | * See the comments in fast_page_fault(). | |
7928 | */ | |
7929 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
7930 | if (kvm_x86_ops->slot_enable_log_dirty) | |
7931 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
7932 | else | |
7933 | kvm_mmu_slot_remove_write_access(kvm, new); | |
7934 | } else { | |
7935 | if (kvm_x86_ops->slot_disable_log_dirty) | |
7936 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
7937 | } | |
7938 | } | |
7939 | ||
f7784b8e | 7940 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 7941 | const struct kvm_userspace_memory_region *mem, |
8482644a | 7942 | const struct kvm_memory_slot *old, |
f36f3f28 | 7943 | const struct kvm_memory_slot *new, |
8482644a | 7944 | enum kvm_mr_change change) |
f7784b8e | 7945 | { |
8482644a | 7946 | int nr_mmu_pages = 0; |
f7784b8e | 7947 | |
f36f3f28 | 7948 | if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) { |
f7784b8e MT |
7949 | int ret; |
7950 | ||
8482644a TY |
7951 | ret = vm_munmap(old->userspace_addr, |
7952 | old->npages * PAGE_SIZE); | |
f7784b8e MT |
7953 | if (ret < 0) |
7954 | printk(KERN_WARNING | |
7955 | "kvm_vm_ioctl_set_memory_region: " | |
7956 | "failed to munmap memory\n"); | |
7957 | } | |
7958 | ||
48c0e4e9 XG |
7959 | if (!kvm->arch.n_requested_mmu_pages) |
7960 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
7961 | ||
48c0e4e9 | 7962 | if (nr_mmu_pages) |
0de10343 | 7963 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); |
1c91cad4 | 7964 | |
3ea3b7fa WL |
7965 | /* |
7966 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
7967 | * sptes have to be split. If live migration is successful, the guest | |
7968 | * in the source machine will be destroyed and large sptes will be | |
7969 | * created in the destination. However, if the guest continues to run | |
7970 | * in the source machine (for example if live migration fails), small | |
7971 | * sptes will remain around and cause bad performance. | |
7972 | * | |
7973 | * Scan sptes if dirty logging has been stopped, dropping those | |
7974 | * which can be collapsed into a single large-page spte. Later | |
7975 | * page faults will create the large-page sptes. | |
7976 | */ | |
7977 | if ((change != KVM_MR_DELETE) && | |
7978 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
7979 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
7980 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
7981 | ||
c972f3b1 | 7982 | /* |
88178fd4 | 7983 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 7984 | * |
88178fd4 KH |
7985 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
7986 | * been zapped so no dirty logging staff is needed for old slot. For | |
7987 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
7988 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
7989 | * |
7990 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 7991 | */ |
88178fd4 | 7992 | if (change != KVM_MR_DELETE) |
f36f3f28 | 7993 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 7994 | } |
1d737c8a | 7995 | |
2df72e9b | 7996 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 7997 | { |
6ca18b69 | 7998 | kvm_mmu_invalidate_zap_all_pages(kvm); |
34d4cb8f MT |
7999 | } |
8000 | ||
2df72e9b MT |
8001 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
8002 | struct kvm_memory_slot *slot) | |
8003 | { | |
6ca18b69 | 8004 | kvm_mmu_invalidate_zap_all_pages(kvm); |
2df72e9b MT |
8005 | } |
8006 | ||
1d737c8a ZX |
8007 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
8008 | { | |
b6b8a145 JK |
8009 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
8010 | kvm_x86_ops->check_nested_events(vcpu, false); | |
8011 | ||
af585b92 GN |
8012 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
8013 | !vcpu->arch.apf.halted) | |
8014 | || !list_empty_careful(&vcpu->async_pf.done) | |
66450a21 | 8015 | || kvm_apic_has_events(vcpu) |
6aef266c | 8016 | || vcpu->arch.pv.pv_unhalted |
7460fb4a | 8017 | || atomic_read(&vcpu->arch.nmi_queued) || |
a1b37100 GN |
8018 | (kvm_arch_interrupt_allowed(vcpu) && |
8019 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 8020 | } |
5736199a | 8021 | |
b6d33834 | 8022 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 8023 | { |
b6d33834 | 8024 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 8025 | } |
78646121 GN |
8026 | |
8027 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
8028 | { | |
8029 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
8030 | } | |
229456fc | 8031 | |
82b32774 | 8032 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 8033 | { |
82b32774 NA |
8034 | if (is_64_bit_mode(vcpu)) |
8035 | return kvm_rip_read(vcpu); | |
8036 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
8037 | kvm_rip_read(vcpu)); | |
8038 | } | |
8039 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 8040 | |
82b32774 NA |
8041 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
8042 | { | |
8043 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
8044 | } |
8045 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
8046 | ||
94fe45da JK |
8047 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
8048 | { | |
8049 | unsigned long rflags; | |
8050 | ||
8051 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
8052 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 8053 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
8054 | return rflags; |
8055 | } | |
8056 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
8057 | ||
6addfc42 | 8058 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
8059 | { |
8060 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 8061 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 8062 | rflags |= X86_EFLAGS_TF; |
94fe45da | 8063 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
8064 | } |
8065 | ||
8066 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
8067 | { | |
8068 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 8069 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
8070 | } |
8071 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
8072 | ||
56028d08 GN |
8073 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
8074 | { | |
8075 | int r; | |
8076 | ||
fb67e14f | 8077 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || |
f2e10669 | 8078 | work->wakeup_all) |
56028d08 GN |
8079 | return; |
8080 | ||
8081 | r = kvm_mmu_reload(vcpu); | |
8082 | if (unlikely(r)) | |
8083 | return; | |
8084 | ||
fb67e14f XG |
8085 | if (!vcpu->arch.mmu.direct_map && |
8086 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
8087 | return; | |
8088 | ||
56028d08 GN |
8089 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); |
8090 | } | |
8091 | ||
af585b92 GN |
8092 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
8093 | { | |
8094 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
8095 | } | |
8096 | ||
8097 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
8098 | { | |
8099 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
8100 | } | |
8101 | ||
8102 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8103 | { | |
8104 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8105 | ||
8106 | while (vcpu->arch.apf.gfns[key] != ~0) | |
8107 | key = kvm_async_pf_next_probe(key); | |
8108 | ||
8109 | vcpu->arch.apf.gfns[key] = gfn; | |
8110 | } | |
8111 | ||
8112 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8113 | { | |
8114 | int i; | |
8115 | u32 key = kvm_async_pf_hash_fn(gfn); | |
8116 | ||
8117 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
8118 | (vcpu->arch.apf.gfns[key] != gfn && |
8119 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
8120 | key = kvm_async_pf_next_probe(key); |
8121 | ||
8122 | return key; | |
8123 | } | |
8124 | ||
8125 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8126 | { | |
8127 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
8128 | } | |
8129 | ||
8130 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
8131 | { | |
8132 | u32 i, j, k; | |
8133 | ||
8134 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
8135 | while (true) { | |
8136 | vcpu->arch.apf.gfns[i] = ~0; | |
8137 | do { | |
8138 | j = kvm_async_pf_next_probe(j); | |
8139 | if (vcpu->arch.apf.gfns[j] == ~0) | |
8140 | return; | |
8141 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
8142 | /* | |
8143 | * k lies cyclically in ]i,j] | |
8144 | * | i.k.j | | |
8145 | * |....j i.k.| or |.k..j i...| | |
8146 | */ | |
8147 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
8148 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
8149 | i = j; | |
8150 | } | |
8151 | } | |
8152 | ||
7c90705b GN |
8153 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
8154 | { | |
8155 | ||
8156 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
8157 | sizeof(val)); | |
8158 | } | |
8159 | ||
af585b92 GN |
8160 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
8161 | struct kvm_async_pf *work) | |
8162 | { | |
6389ee94 AK |
8163 | struct x86_exception fault; |
8164 | ||
7c90705b | 8165 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 8166 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b GN |
8167 | |
8168 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
fc5f06fa GN |
8169 | (vcpu->arch.apf.send_user_only && |
8170 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7c90705b GN |
8171 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
8172 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
8173 | fault.vector = PF_VECTOR; |
8174 | fault.error_code_valid = true; | |
8175 | fault.error_code = 0; | |
8176 | fault.nested_page_fault = false; | |
8177 | fault.address = work->arch.token; | |
8178 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8179 | } |
af585b92 GN |
8180 | } |
8181 | ||
8182 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
8183 | struct kvm_async_pf *work) | |
8184 | { | |
6389ee94 AK |
8185 | struct x86_exception fault; |
8186 | ||
7c90705b | 8187 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
f2e10669 | 8188 | if (work->wakeup_all) |
7c90705b GN |
8189 | work->arch.token = ~0; /* broadcast wakeup */ |
8190 | else | |
8191 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
8192 | ||
8193 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
8194 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
6389ee94 AK |
8195 | fault.vector = PF_VECTOR; |
8196 | fault.error_code_valid = true; | |
8197 | fault.error_code = 0; | |
8198 | fault.nested_page_fault = false; | |
8199 | fault.address = work->arch.token; | |
8200 | kvm_inject_page_fault(vcpu, &fault); | |
7c90705b | 8201 | } |
e6d53e3b | 8202 | vcpu->arch.apf.halted = false; |
a4fa1635 | 8203 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
8204 | } |
8205 | ||
8206 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
8207 | { | |
8208 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
8209 | return true; | |
8210 | else | |
8211 | return !kvm_event_needs_reinjection(vcpu) && | |
8212 | kvm_x86_ops->interrupt_allowed(vcpu); | |
af585b92 GN |
8213 | } |
8214 | ||
e0f0bbc5 AW |
8215 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
8216 | { | |
8217 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
8218 | } | |
8219 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
8220 | ||
8221 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
8222 | { | |
8223 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
8224 | } | |
8225 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
8226 | ||
8227 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
8228 | { | |
8229 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
8230 | } | |
8231 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
8232 | ||
229456fc MT |
8233 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
8234 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
8235 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
8236 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
8237 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 8238 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 8239 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 8240 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 8241 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 8242 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 8243 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 8244 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 8245 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 8246 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 8247 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |