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KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
aec51dc4 54#include <trace/events/kvm.h>
2ed152af 55
229456fc
MT		 56#define CREATE_TRACE_POINTS
57#include "trace.h"
043405e1 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 225 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 226 if (slot >= shared_msrs_global.nr)
227 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 228}
229EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
230
231static void kvm_shared_msr_cpu_online(void)
232{
233 unsigned i;
18863bdd
AK		 234
235 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 236 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 237}
238
8b3c3104 239int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 240{
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 243 int err;
18863bdd 244
2bf78fa7 245 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 246 return 0;
2bf78fa7 247 smsr->values[slot].curr = value;
8b3c3104
AH		 248 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
249 if (err)
250 return 1;
251
18863bdd
AK		 252 if (!smsr->registered) {
253 smsr->urn.on_user_return = kvm_on_user_return;
254 user_return_notifier_register(&smsr->urn);
255 smsr->registered = true;
256 }
8b3c3104 257 return 0;
18863bdd
AK		 258}
259EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
260
13a34e06 261static void drop_user_return_notifiers(void)
3548bab5 262{
013f6a5d
MT		 263 unsigned int cpu = smp_processor_id();
264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 265
266 if (smsr->registered)
267 kvm_on_user_return(&smsr->urn);
268}
269
6866b83e
CO		 270u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
271{
8a5a87d9 272 return vcpu->arch.apic_base;
6866b83e
CO		 273}
274EXPORT_SYMBOL_GPL(kvm_get_apic_base);
275
58cb628d
JK		 276int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
277{
278 u64 old_state = vcpu->arch.apic_base &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 new_state = msr_info->data &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
283 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
284
285 if (!msr_info->host_initiated &&
286 ((msr_info->data & reserved_bits) != 0 ||
287 new_state == X2APIC_ENABLE ||
288 (new_state == MSR_IA32_APICBASE_ENABLE &&
289 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
290 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
291 old_state == 0)))
292 return 1;
293
294 kvm_lapic_set_base(vcpu, msr_info->data);
295 return 0;
6866b83e
CO		 296}
297EXPORT_SYMBOL_GPL(kvm_set_apic_base);
298
2605fc21 299asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 300{
301 /* Fault while not rebooting. We want the trace. */
302 BUG();
303}
304EXPORT_SYMBOL_GPL(kvm_spurious_fault);
305
3fd28fce
ED		 306#define EXCPT_BENIGN 0
307#define EXCPT_CONTRIBUTORY 1
308#define EXCPT_PF 2
309
310static int exception_class(int vector)
311{
312 switch (vector) {
313 case PF_VECTOR:
314 return EXCPT_PF;
315 case DE_VECTOR:
316 case TS_VECTOR:
317 case NP_VECTOR:
318 case SS_VECTOR:
319 case GP_VECTOR:
320 return EXCPT_CONTRIBUTORY;
321 default:
322 break;
323 }
324 return EXCPT_BENIGN;
325}
326
d6e8c854
NA		 327#define EXCPT_FAULT 0
328#define EXCPT_TRAP 1
329#define EXCPT_ABORT 2
330#define EXCPT_INTERRUPT 3
331
332static int exception_type(int vector)
333{
334 unsigned int mask;
335
336 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
337 return EXCPT_INTERRUPT;
338
339 mask = 1 << vector;
340
341 /* #DB is trap, as instruction watchpoints are handled elsewhere */
342 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
343 return EXCPT_TRAP;
344
345 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
346 return EXCPT_ABORT;
347
348 /* Reserved exceptions will result in fault */
349 return EXCPT_FAULT;
350}
351
3fd28fce 352static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 353 unsigned nr, bool has_error, u32 error_code,
354 bool reinject)
3fd28fce
ED		 355{
356 u32 prev_nr;
357 int class1, class2;
358
3842d135
AK		 359 kvm_make_request(KVM_REQ_EVENT, vcpu);
360
3fd28fce
ED		 361 if (!vcpu->arch.exception.pending) {
362 queue:
3ffb2468
NA		 363 if (has_error && !is_protmode(vcpu))
364 has_error = false;
3fd28fce
ED		 365 vcpu->arch.exception.pending = true;
366 vcpu->arch.exception.has_error_code = has_error;
367 vcpu->arch.exception.nr = nr;
368 vcpu->arch.exception.error_code = error_code;
3f0fd292 369 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 370 return;
371 }
372
373 /* to check exception */
374 prev_nr = vcpu->arch.exception.nr;
375 if (prev_nr == DF_VECTOR) {
376 /* triple fault -> shutdown */
a8eeb04a 377 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 378 return;
379 }
380 class1 = exception_class(prev_nr);
381 class2 = exception_class(nr);
382 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
383 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
384 /* generate double fault per SDM Table 5-5 */
385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = true;
387 vcpu->arch.exception.nr = DF_VECTOR;
388 vcpu->arch.exception.error_code = 0;
389 } else
390 /* replace previous exception with a new one in a hope
391 that instruction re-execution will regenerate lost
392 exception */
393 goto queue;
394}
395
298101da
AK		 396void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
397{
ce7ddec4 398 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 399}
400EXPORT_SYMBOL_GPL(kvm_queue_exception);
401
ce7ddec4
JR		 402void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
403{
404 kvm_multiple_exception(vcpu, nr, false, 0, true);
405}
406EXPORT_SYMBOL_GPL(kvm_requeue_exception);
407
db8fcefa 408void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 409{
db8fcefa
AP		 410 if (err)
411 kvm_inject_gp(vcpu, 0);
412 else
413 kvm_x86_ops->skip_emulated_instruction(vcpu);
414}
415EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 416
6389ee94 417void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 418{
419 ++vcpu->stat.pf_guest;
6389ee94
AK		 420 vcpu->arch.cr2 = fault->address;
421 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 422}
27d6c865 423EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 424
ef54bcfe 425static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 426{
6389ee94
AK		 427 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
428 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 429 else
6389ee94 430 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 431
432 return fault->nested_page_fault;
d4f8cf66
JR		 433}
434
3419ffc8
SY		 435void kvm_inject_nmi(struct kvm_vcpu *vcpu)
436{
7460fb4a
AK		 437 atomic_inc(&vcpu->arch.nmi_queued);
438 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 439}
440EXPORT_SYMBOL_GPL(kvm_inject_nmi);
441
298101da
AK		 442void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
443{
ce7ddec4 444 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 445}
446EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
447
ce7ddec4
JR		 448void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
449{
450 kvm_multiple_exception(vcpu, nr, true, error_code, true);
451}
452EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
453
0a79b009
AK		 454/*
455 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
456 * a #GP and return false.
457 */
458bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 459{
0a79b009
AK		 460 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
461 return true;
462 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
463 return false;
298101da 464}
0a79b009 465EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 466
16f8a6f9
NA		 467bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
468{
469 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
470 return true;
471
472 kvm_queue_exception(vcpu, UD_VECTOR);
473 return false;
474}
475EXPORT_SYMBOL_GPL(kvm_require_dr);
476
ec92fe44
JR		 477/*
478 * This function will be used to read from the physical memory of the currently
54bf36aa 479 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 480 * can read from guest physical or from the guest's guest physical memory.
481 */
482int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
483 gfn_t ngfn, void *data, int offset, int len,
484 u32 access)
485{
54987b7a 486 struct x86_exception exception;
ec92fe44
JR		 487 gfn_t real_gfn;
488 gpa_t ngpa;
489
490 ngpa = gfn_to_gpa(ngfn);
54987b7a 491 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 492 if (real_gfn == UNMAPPED_GVA)
493 return -EFAULT;
494
495 real_gfn = gpa_to_gfn(real_gfn);
496
54bf36aa 497 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 498}
499EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
500
69b0049a 501static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 502 void *data, int offset, int len, u32 access)
503{
504 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
505 data, offset, len, access);
506}
507
a03490ed
CO		 508/*
509 * Load the pae pdptrs. Return true is they are all valid.
510 */
ff03a073 511int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 512{
513 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
514 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
515 int i;
516 int ret;
ff03a073 517 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 518
ff03a073
JR		 519 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
520 offset * sizeof(u64), sizeof(pdpte),
521 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 522 if (ret < 0) {
523 ret = 0;
524 goto out;
525 }
526 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 527 if (is_present_gpte(pdpte[i]) &&
20c466b5 528 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 529 ret = 0;
530 goto out;
531 }
532 }
533 ret = 1;
534
ff03a073 535 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_avail);
538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 540out:
a03490ed
CO		 541
542 return ret;
543}
cc4b6871 544EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 545
d835dfec
AK		 546static bool pdptrs_changed(struct kvm_vcpu *vcpu)
547{
ff03a073 548 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 549 bool changed = true;
3d06b8bf
JR		 550 int offset;
551 gfn_t gfn;
d835dfec
AK		 552 int r;
553
554 if (is_long_mode(vcpu) || !is_pae(vcpu))
555 return false;
556
6de4f3ad
AK		 557 if (!test_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail))
559 return true;
560
9f8fe504
AK		 561 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
562 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 563 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
564 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 565 if (r < 0)
566 goto out;
ff03a073 567 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 568out:
d835dfec
AK		 569
570 return changed;
571}
572
49a9b07e 573int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 574{
aad82703 575 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 576 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 577
f9a48e6a
AK		 578 cr0 |= X86_CR0_ET;
579
ab344828 580#ifdef CONFIG_X86_64
0f12244f
GN		 581 if (cr0 & 0xffffffff00000000UL)
582 return 1;
ab344828
GN		 583#endif
584
585 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 586
0f12244f
GN		 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588 return 1;
a03490ed 589
0f12244f
GN		 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591 return 1;
a03490ed
CO		 592
593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594#ifdef CONFIG_X86_64
f6801dff 595 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 596 int cs_db, cs_l;
597
0f12244f
GN		 598 if (!is_pae(vcpu))
599 return 1;
a03490ed 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 601 if (cs_l)
602 return 1;
a03490ed
CO		 603 } else
604#endif
ff03a073 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 606 kvm_read_cr3(vcpu)))
0f12244f 607 return 1;
a03490ed
CO		 608 }
609
ad756a16
MJ		 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611 return 1;
612
a03490ed 613 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 614
d170c419 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 616 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 617 kvm_async_pf_hash_reset(vcpu);
618 }
e5f3f027 619
aad82703
SY		 620 if ((cr0 ^ old_cr0) & update_bits)
621 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 622
623 if ((cr0 ^ old_cr0) & X86_CR0_CD)
624 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
625
0f12244f
GN		 626 return 0;
627}
2d3ad1f4 628EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 629
2d3ad1f4 630void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 631{
49a9b07e 632 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 633}
2d3ad1f4 634EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 635
42bdf991
MT		 636static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
637{
638 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
639 !vcpu->guest_xcr0_loaded) {
640 /* kvm_set_xcr() also depends on this */
641 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
642 vcpu->guest_xcr0_loaded = 1;
643 }
644}
645
646static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
647{
648 if (vcpu->guest_xcr0_loaded) {
649 if (vcpu->arch.xcr0 != host_xcr0)
650 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
651 vcpu->guest_xcr0_loaded = 0;
652 }
653}
654
69b0049a 655static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 656{
56c103ec
LJ		 657 u64 xcr0 = xcr;
658 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 659 u64 valid_bits;
2acf923e
DC		 660
661 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
662 if (index != XCR_XFEATURE_ENABLED_MASK)
663 return 1;
2acf923e
DC		 664 if (!(xcr0 & XSTATE_FP))
665 return 1;
666 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
667 return 1;
46c34cb0
PB		 668
669 /*
670 * Do not allow the guest to set bits that we do not support
671 * saving. However, xcr0 bit 0 is always set, even if the
672 * emulated CPU does not support XSAVE (see fx_init).
673 */
674 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
675 if (xcr0 & ~valid_bits)
2acf923e 676 return 1;
46c34cb0 677
390bd528
LJ		 678 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
679 return 1;
680
612263b3
CP		 681 if (xcr0 & XSTATE_AVX512) {
682 if (!(xcr0 & XSTATE_YMM))
683 return 1;
684 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
685 return 1;
686 }
42bdf991 687 kvm_put_guest_xcr0(vcpu);
2acf923e 688 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 689
690 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
691 kvm_update_cpuid(vcpu);
2acf923e
DC		 692 return 0;
693}
694
695int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
696{
764bcbc5
Z		 697 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
698 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 699 kvm_inject_gp(vcpu, 0);
700 return 1;
701 }
702 return 0;
703}
704EXPORT_SYMBOL_GPL(kvm_set_xcr);
705
a83b29c6 706int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 707{
fc78f519 708 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 709 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
710 X86_CR4_SMEP | X86_CR4_SMAP;
711
0f12244f
GN		 712 if (cr4 & CR4_RESERVED_BITS)
713 return 1;
a03490ed 714
2acf923e
DC		 715 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
716 return 1;
717
c68b734f
YW		 718 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
719 return 1;
720
97ec8c06
FW		 721 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
722 return 1;
723
afcbf13f 724 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 725 return 1;
726
a03490ed 727 if (is_long_mode(vcpu)) {
0f12244f
GN		 728 if (!(cr4 & X86_CR4_PAE))
729 return 1;
a2edf57f
AK		 730 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
731 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 732 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
733 kvm_read_cr3(vcpu)))
0f12244f
GN		 734 return 1;
735
ad756a16
MJ		 736 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
737 if (!guest_cpuid_has_pcid(vcpu))
738 return 1;
739
740 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
741 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
742 return 1;
743 }
744
5e1746d6 745 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 746 return 1;
a03490ed 747
ad756a16
MJ		 748 if (((cr4 ^ old_cr4) & pdptr_bits) ||
749 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 750 kvm_mmu_reset_context(vcpu);
0f12244f 751
2acf923e 752 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 753 kvm_update_cpuid(vcpu);
2acf923e 754
0f12244f
GN		 755 return 0;
756}
2d3ad1f4 757EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 758
2390218b 759int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 760{
ac146235 761#ifdef CONFIG_X86_64
9d88fca7 762 cr3 &= ~CR3_PCID_INVD;
ac146235 763#endif
9d88fca7 764
9f8fe504 765 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 766 kvm_mmu_sync_roots(vcpu);
77c3913b 767 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 768 return 0;
d835dfec
AK		 769 }
770
a03490ed 771 if (is_long_mode(vcpu)) {
d9f89b88
JK		 772 if (cr3 & CR3_L_MODE_RESERVED_BITS)
773 return 1;
774 } else if (is_pae(vcpu) && is_paging(vcpu) &&
775 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 776 return 1;
a03490ed 777
0f12244f 778 vcpu->arch.cr3 = cr3;
aff48baa 779 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 780 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 784
eea1cff9 785int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 786{
0f12244f
GN		 787 if (cr8 & CR8_RESERVED_BITS)
788 return 1;
a03490ed
CO		 789 if (irqchip_in_kernel(vcpu->kvm))
790 kvm_lapic_set_tpr(vcpu, cr8);
791 else
ad312c7c 792 vcpu->arch.cr8 = cr8;
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 796
2d3ad1f4 797unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 798{
799 if (irqchip_in_kernel(vcpu->kvm))
800 return kvm_lapic_get_cr8(vcpu);
801 else
ad312c7c 802 return vcpu->arch.cr8;
a03490ed 803}
2d3ad1f4 804EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 805
ae561ede
NA		 806static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
807{
808 int i;
809
810 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
811 for (i = 0; i < KVM_NR_DB_REGS; i++)
812 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
813 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
814 }
815}
816
73aaf249
JK		 817static void kvm_update_dr6(struct kvm_vcpu *vcpu)
818{
819 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
820 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
821}
822
c8639010
JK		 823static void kvm_update_dr7(struct kvm_vcpu *vcpu)
824{
825 unsigned long dr7;
826
827 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
828 dr7 = vcpu->arch.guest_debug_dr7;
829 else
830 dr7 = vcpu->arch.dr7;
831 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 832 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
833 if (dr7 & DR7_BP_EN_MASK)
834 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 835}
836
6f43ed01
NA		 837static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
838{
839 u64 fixed = DR6_FIXED_1;
840
841 if (!guest_cpuid_has_rtm(vcpu))
842 fixed |= DR6_RTM;
843 return fixed;
844}
845
338dbc97 846static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 847{
848 switch (dr) {
849 case 0 ... 3:
850 vcpu->arch.db[dr] = val;
851 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
852 vcpu->arch.eff_db[dr] = val;
853 break;
854 case 4:
020df079
GN		 855 /* fall through */
856 case 6:
338dbc97
GN		 857 if (val & 0xffffffff00000000ULL)
858 return -1; /* #GP */
6f43ed01 859 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 860 kvm_update_dr6(vcpu);
020df079
GN		 861 break;
862 case 5:
020df079
GN		 863 /* fall through */
864 default: /* 7 */
338dbc97
GN		 865 if (val & 0xffffffff00000000ULL)
866 return -1; /* #GP */
020df079 867 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 868 kvm_update_dr7(vcpu);
020df079
GN		 869 break;
870 }
871
872 return 0;
873}
338dbc97
GN		 874
875int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
876{
16f8a6f9 877 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 878 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 879 return 1;
880 }
881 return 0;
338dbc97 882}
020df079
GN		 883EXPORT_SYMBOL_GPL(kvm_set_dr);
884
16f8a6f9 885int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 886{
887 switch (dr) {
888 case 0 ... 3:
889 *val = vcpu->arch.db[dr];
890 break;
891 case 4:
020df079
GN		 892 /* fall through */
893 case 6:
73aaf249
JK		 894 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
895 *val = vcpu->arch.dr6;
896 else
897 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 898 break;
899 case 5:
020df079
GN		 900 /* fall through */
901 default: /* 7 */
902 *val = vcpu->arch.dr7;
903 break;
904 }
338dbc97
GN		 905 return 0;
906}
020df079
GN		 907EXPORT_SYMBOL_GPL(kvm_get_dr);
908
022cd0e8
AK		 909bool kvm_rdpmc(struct kvm_vcpu *vcpu)
910{
911 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
912 u64 data;
913 int err;
914
c6702c9d 915 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 916 if (err)
917 return err;
918 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
919 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
920 return err;
921}
922EXPORT_SYMBOL_GPL(kvm_rdpmc);
923
043405e1
CO		 924/*
925 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
926 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
927 *
928 * This list is modified at module load time to reflect the
e3267cbb 929 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 930 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
931 * may depend on host virtualization features rather than host cpu features.
043405e1 932 */
e3267cbb 933
043405e1
CO		 934static u32 msrs_to_save[] = {
935 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 936 MSR_STAR,
043405e1
CO		 937#ifdef CONFIG_X86_64
938 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
939#endif
b3897a49 940 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 941 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 942};
943
944static unsigned num_msrs_to_save;
945
62ef68bb
PB		 946static u32 emulated_msrs[] = {
947 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
948 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
949 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
950 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 951 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
952 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
62ef68bb
PB		 953 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
954 MSR_KVM_PV_EOI_EN,
955
ba904635 956 MSR_IA32_TSC_ADJUST,
a3e06bbe 957 MSR_IA32_TSCDEADLINE,
043405e1 958 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 959 MSR_IA32_MCG_STATUS,
960 MSR_IA32_MCG_CTL,
64d60670 961 MSR_IA32_SMBASE,
043405e1
CO		 962};
963
62ef68bb
PB		 964static unsigned num_emulated_msrs;
965
384bb783 966bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 967{
b69e8cae 968 if (efer & efer_reserved_bits)
384bb783 969 return false;
15c4a640 970
1b2fd70c
AG		 971 if (efer & EFER_FFXSR) {
972 struct kvm_cpuid_entry2 *feat;
973
974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 975 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 976 return false;
1b2fd70c
AG		 977 }
978
d8017474
AG		 979 if (efer & EFER_SVME) {
980 struct kvm_cpuid_entry2 *feat;
981
982 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 983 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 984 return false;
d8017474
AG		 985 }
986
384bb783
JK		 987 return true;
988}
989EXPORT_SYMBOL_GPL(kvm_valid_efer);
990
991static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
992{
993 u64 old_efer = vcpu->arch.efer;
994
995 if (!kvm_valid_efer(vcpu, efer))
996 return 1;
997
998 if (is_paging(vcpu)
999 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1000 return 1;
1001
15c4a640 1002 efer &= ~EFER_LMA;
f6801dff 1003 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1004
a3d204e2
SY		 1005 kvm_x86_ops->set_efer(vcpu, efer);
1006
aad82703
SY		 1007 /* Update reserved bits */
1008 if ((efer ^ old_efer) & EFER_NX)
1009 kvm_mmu_reset_context(vcpu);
1010
b69e8cae 1011 return 0;
15c4a640
CO		 1012}
1013
f2b4b7dd
JR		 1014void kvm_enable_efer_bits(u64 mask)
1015{
1016 efer_reserved_bits &= ~mask;
1017}
1018EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1019
15c4a640
CO		 1020/*
1021 * Writes msr value into into the appropriate "register".
1022 * Returns 0 on success, non-0 otherwise.
1023 * Assumes vcpu_load() was already called.
1024 */
8fe8ab46 1025int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1026{
854e8bb1
NA		 1027 switch (msr->index) {
1028 case MSR_FS_BASE:
1029 case MSR_GS_BASE:
1030 case MSR_KERNEL_GS_BASE:
1031 case MSR_CSTAR:
1032 case MSR_LSTAR:
1033 if (is_noncanonical_address(msr->data))
1034 return 1;
1035 break;
1036 case MSR_IA32_SYSENTER_EIP:
1037 case MSR_IA32_SYSENTER_ESP:
1038 /*
1039 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1040 * non-canonical address is written on Intel but not on
1041 * AMD (which ignores the top 32-bits, because it does
1042 * not implement 64-bit SYSENTER).
1043 *
1044 * 64-bit code should hence be able to write a non-canonical
1045 * value on AMD. Making the address canonical ensures that
1046 * vmentry does not fail on Intel after writing a non-canonical
1047 * value, and that something deterministic happens if the guest
1048 * invokes 64-bit SYSENTER.
1049 */
1050 msr->data = get_canonical(msr->data);
1051 }
8fe8ab46 1052 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1053}
854e8bb1 1054EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1055
313a3dc7
CO		 1056/*
1057 * Adapt set_msr() to msr_io()'s calling convention
1058 */
609e36d3
PB		 1059static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1060{
1061 struct msr_data msr;
1062 int r;
1063
1064 msr.index = index;
1065 msr.host_initiated = true;
1066 r = kvm_get_msr(vcpu, &msr);
1067 if (r)
1068 return r;
1069
1070 *data = msr.data;
1071 return 0;
1072}
1073
313a3dc7
CO		 1074static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1075{
8fe8ab46
WA		 1076 struct msr_data msr;
1077
1078 msr.data = *data;
1079 msr.index = index;
1080 msr.host_initiated = true;
1081 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1082}
1083
16e8d74d
MT		 1084#ifdef CONFIG_X86_64
1085struct pvclock_gtod_data {
1086 seqcount_t seq;
1087
1088 struct { /* extract of a clocksource struct */
1089 int vclock_mode;
1090 cycle_t cycle_last;
1091 cycle_t mask;
1092 u32 mult;
1093 u32 shift;
1094 } clock;
1095
cbcf2dd3
TG		 1096 u64 boot_ns;
1097 u64 nsec_base;
16e8d74d
MT		 1098};
1099
1100static struct pvclock_gtod_data pvclock_gtod_data;
1101
1102static void update_pvclock_gtod(struct timekeeper *tk)
1103{
1104 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1105 u64 boot_ns;
1106
876e7881 1107 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1108
1109 write_seqcount_begin(&vdata->seq);
1110
1111 /* copy pvclock gtod data */
876e7881
PZ		 1112 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1113 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1114 vdata->clock.mask = tk->tkr_mono.mask;
1115 vdata->clock.mult = tk->tkr_mono.mult;
1116 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1117
cbcf2dd3 1118 vdata->boot_ns = boot_ns;
876e7881 1119 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1120
1121 write_seqcount_end(&vdata->seq);
1122}
1123#endif
1124
bab5bb39
NK		 1125void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1126{
1127 /*
1128 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1129 * vcpu_enter_guest. This function is only called from
1130 * the physical CPU that is running vcpu.
1131 */
1132 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1133}
16e8d74d 1134
18068523
GOC		 1135static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1136{
9ed3c444
AK		 1137 int version;
1138 int r;
50d0a0f9 1139 struct pvclock_wall_clock wc;
923de3cf 1140 struct timespec boot;
18068523
GOC		 1141
1142 if (!wall_clock)
1143 return;
1144
9ed3c444
AK		 1145 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1146 if (r)
1147 return;
1148
1149 if (version & 1)
1150 ++version; /* first time write, random junk */
1151
1152 ++version;
18068523 1153
18068523
GOC		 1154 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1155
50d0a0f9
GH		 1156 /*
1157 * The guest calculates current wall clock time by adding
34c238a1 1158 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1159 * wall clock specified here. guest system time equals host
1160 * system time for us, thus we must fill in host boot time here.
1161 */
923de3cf 1162 getboottime(&boot);
50d0a0f9 1163
4b648665
BR		 1164 if (kvm->arch.kvmclock_offset) {
1165 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1166 boot = timespec_sub(boot, ts);
1167 }
50d0a0f9
GH		 1168 wc.sec = boot.tv_sec;
1169 wc.nsec = boot.tv_nsec;
1170 wc.version = version;
18068523
GOC		 1171
1172 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1173
1174 version++;
1175 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1176}
1177
50d0a0f9
GH		 1178static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1179{
1180 uint32_t quotient, remainder;
1181
1182 /* Don't try to replace with do_div(), this one calculates
1183 * "(dividend << 32) / divisor" */
1184 __asm__ ( "divl %4"
1185 : "=a" (quotient), "=d" (remainder)
1186 : "0" (0), "1" (dividend), "r" (divisor) );
1187 return quotient;
1188}
1189
5f4e3f88
ZA		 1190static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1191 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1192{
5f4e3f88 1193 uint64_t scaled64;
50d0a0f9
GH		 1194 int32_t shift = 0;
1195 uint64_t tps64;
1196 uint32_t tps32;
1197
5f4e3f88
ZA		 1198 tps64 = base_khz * 1000LL;
1199 scaled64 = scaled_khz * 1000LL;
50933623 1200 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1201 tps64 >>= 1;
1202 shift--;
1203 }
1204
1205 tps32 = (uint32_t)tps64;
50933623
JK		 1206 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1207 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1208 scaled64 >>= 1;
1209 else
1210 tps32 <<= 1;
50d0a0f9
GH		 1211 shift++;
1212 }
1213
5f4e3f88
ZA		 1214 *pshift = shift;
1215 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1216
5f4e3f88
ZA		 1217 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1218 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1219}
1220
d828199e 1221#ifdef CONFIG_X86_64
16e8d74d 1222static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1223#endif
16e8d74d 1224
c8076604 1225static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1226static unsigned long max_tsc_khz;
c8076604 1227
cc578287 1228static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1229{
cc578287
ZA		 1230 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1231 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1232}
1233
cc578287 1234static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1235{
cc578287
ZA		 1236 u64 v = (u64)khz * (1000000 + ppm);
1237 do_div(v, 1000000);
1238 return v;
1e993611
JR		 1239}
1240
cc578287 1241static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1242{
cc578287
ZA		 1243 u32 thresh_lo, thresh_hi;
1244 int use_scaling = 0;
217fc9cf 1245
03ba32ca
MT		 1246 /* tsc_khz can be zero if TSC calibration fails */
1247 if (this_tsc_khz == 0)
1248 return;
1249
c285545f
ZA		 1250 /* Compute a scale to convert nanoseconds in TSC cycles */
1251 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1252 &vcpu->arch.virtual_tsc_shift,
1253 &vcpu->arch.virtual_tsc_mult);
1254 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1255
1256 /*
1257 * Compute the variation in TSC rate which is acceptable
1258 * within the range of tolerance and decide if the
1259 * rate being applied is within that bounds of the hardware
1260 * rate. If so, no scaling or compensation need be done.
1261 */
1262 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1263 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1264 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1265 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1266 use_scaling = 1;
1267 }
1268 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1269}
1270
1271static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1272{
e26101b1 1273 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1274 vcpu->arch.virtual_tsc_mult,
1275 vcpu->arch.virtual_tsc_shift);
e26101b1 1276 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1277 return tsc;
1278}
1279
69b0049a 1280static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1281{
1282#ifdef CONFIG_X86_64
1283 bool vcpus_matched;
b48aa97e
MT		 1284 struct kvm_arch *ka = &vcpu->kvm->arch;
1285 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1286
1287 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1288 atomic_read(&vcpu->kvm->online_vcpus));
1289
7f187922
MT		 1290 /*
1291 * Once the masterclock is enabled, always perform request in
1292 * order to update it.
1293 *
1294 * In order to enable masterclock, the host clocksource must be TSC
1295 * and the vcpus need to have matched TSCs. When that happens,
1296 * perform request to enable masterclock.
1297 */
1298 if (ka->use_master_clock ||
1299 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1300 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1301
1302 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1303 atomic_read(&vcpu->kvm->online_vcpus),
1304 ka->use_master_clock, gtod->clock.vclock_mode);
1305#endif
1306}
1307
ba904635
WA		 1308static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1309{
1310 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1311 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1312}
1313
8fe8ab46 1314void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1315{
1316 struct kvm *kvm = vcpu->kvm;
f38e098f 1317 u64 offset, ns, elapsed;
99e3e30a 1318 unsigned long flags;
02626b6a 1319 s64 usdiff;
b48aa97e 1320 bool matched;
0d3da0d2 1321 bool already_matched;
8fe8ab46 1322 u64 data = msr->data;
99e3e30a 1323
038f8c11 1324 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1325 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1326 ns = get_kernel_ns();
f38e098f 1327 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1328
03ba32ca 1329 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1330 int faulted = 0;
1331
03ba32ca
MT		 1332 /* n.b - signed multiplication and division required */
1333 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1334#ifdef CONFIG_X86_64
03ba32ca 1335 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1336#else
03ba32ca 1337 /* do_div() only does unsigned */
8915aa27
MT		 1338 asm("1: idivl %[divisor]\n"
1339 "2: xor %%edx, %%edx\n"
1340 " movl $0, %[faulted]\n"
1341 "3:\n"
1342 ".section .fixup,\"ax\"\n"
1343 "4: movl $1, %[faulted]\n"
1344 " jmp 3b\n"
1345 ".previous\n"
1346
1347 _ASM_EXTABLE(1b, 4b)
1348
1349 : "=A"(usdiff), [faulted] "=r" (faulted)
1350 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1351
5d3cb0f6 1352#endif
03ba32ca
MT		 1353 do_div(elapsed, 1000);
1354 usdiff -= elapsed;
1355 if (usdiff < 0)
1356 usdiff = -usdiff;
8915aa27
MT		 1357
1358 /* idivl overflow => difference is larger than USEC_PER_SEC */
1359 if (faulted)
1360 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1361 } else
1362 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1363
1364 /*
5d3cb0f6
ZA		 1365 * Special case: TSC write with a small delta (1 second) of virtual
1366 * cycle time against real time is interpreted as an attempt to
1367 * synchronize the CPU.
1368 *
1369 * For a reliable TSC, we can match TSC offsets, and for an unstable
1370 * TSC, we add elapsed time in this computation. We could let the
1371 * compensation code attempt to catch up if we fall behind, but
1372 * it's better to try to match offsets from the beginning.
1373 */
02626b6a 1374 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1375 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1376 if (!check_tsc_unstable()) {
e26101b1 1377 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1378 pr_debug("kvm: matched tsc offset for %llu\n", data);
1379 } else {
857e4099 1380 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1381 data += delta;
1382 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1383 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1384 }
b48aa97e 1385 matched = true;
0d3da0d2 1386 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1387 } else {
1388 /*
1389 * We split periods of matched TSC writes into generations.
1390 * For each generation, we track the original measured
1391 * nanosecond time, offset, and write, so if TSCs are in
1392 * sync, we can match exact offset, and if not, we can match
4a969980 1393 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1394 *
1395 * These values are tracked in kvm->arch.cur_xxx variables.
1396 */
1397 kvm->arch.cur_tsc_generation++;
1398 kvm->arch.cur_tsc_nsec = ns;
1399 kvm->arch.cur_tsc_write = data;
1400 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1401 matched = false;
0d3da0d2 1402 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1403 kvm->arch.cur_tsc_generation, data);
f38e098f 1404 }
e26101b1
ZA		 1405
1406 /*
1407 * We also track th most recent recorded KHZ, write and time to
1408 * allow the matching interval to be extended at each write.
1409 */
f38e098f
ZA		 1410 kvm->arch.last_tsc_nsec = ns;
1411 kvm->arch.last_tsc_write = data;
5d3cb0f6 1412 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1413
b183aa58 1414 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1415
1416 /* Keep track of which generation this VCPU has synchronized to */
1417 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1418 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1419 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1420
ba904635
WA		 1421 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1422 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1423 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1424 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1425
1426 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1427 if (!matched) {
b48aa97e 1428 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1429 } else if (!already_matched) {
1430 kvm->arch.nr_vcpus_matched_tsc++;
1431 }
b48aa97e
MT		 1432
1433 kvm_track_tsc_matching(vcpu);
1434 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1435}
e26101b1 1436
99e3e30a
ZA		 1437EXPORT_SYMBOL_GPL(kvm_write_tsc);
1438
d828199e
MT		 1439#ifdef CONFIG_X86_64
1440
1441static cycle_t read_tsc(void)
1442{
1443 cycle_t ret;
1444 u64 last;
1445
1446 /*
1447 * Empirically, a fence (of type that depends on the CPU)
1448 * before rdtsc is enough to ensure that rdtsc is ordered
1449 * with respect to loads. The various CPU manuals are unclear
1450 * as to whether rdtsc can be reordered with later loads,
1451 * but no one has ever seen it happen.
1452 */
1453 rdtsc_barrier();
1454 ret = (cycle_t)vget_cycles();
1455
1456 last = pvclock_gtod_data.clock.cycle_last;
1457
1458 if (likely(ret >= last))
1459 return ret;
1460
1461 /*
1462 * GCC likes to generate cmov here, but this branch is extremely
1463 * predictable (it's just a funciton of time and the likely is
1464 * very likely) and there's a data dependence, so force GCC
1465 * to generate a branch instead. I don't barrier() because
1466 * we don't actually need a barrier, and if this function
1467 * ever gets inlined it will generate worse code.
1468 */
1469 asm volatile ("");
1470 return last;
1471}
1472
1473static inline u64 vgettsc(cycle_t *cycle_now)
1474{
1475 long v;
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477
1478 *cycle_now = read_tsc();
1479
1480 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1481 return v * gtod->clock.mult;
1482}
1483
cbcf2dd3 1484static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1485{
cbcf2dd3 1486 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1487 unsigned long seq;
d828199e 1488 int mode;
cbcf2dd3 1489 u64 ns;
d828199e 1490
d828199e
MT		 1491 do {
1492 seq = read_seqcount_begin(&gtod->seq);
1493 mode = gtod->clock.vclock_mode;
cbcf2dd3 1494 ns = gtod->nsec_base;
d828199e
MT		 1495 ns += vgettsc(cycle_now);
1496 ns >>= gtod->clock.shift;
cbcf2dd3 1497 ns += gtod->boot_ns;
d828199e 1498 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1499 *t = ns;
d828199e
MT		 1500
1501 return mode;
1502}
1503
1504/* returns true if host is using tsc clocksource */
1505static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1506{
d828199e
MT		 1507 /* checked again under seqlock below */
1508 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1509 return false;
1510
cbcf2dd3 1511 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1512}
1513#endif
1514
1515/*
1516 *
b48aa97e
MT		 1517 * Assuming a stable TSC across physical CPUS, and a stable TSC
1518 * across virtual CPUs, the following condition is possible.
1519 * Each numbered line represents an event visible to both
d828199e
MT		 1520 * CPUs at the next numbered event.
1521 *
1522 * "timespecX" represents host monotonic time. "tscX" represents
1523 * RDTSC value.
1524 *
1525 * VCPU0 on CPU0 | VCPU1 on CPU1
1526 *
1527 * 1. read timespec0,tsc0
1528 * 2. | timespec1 = timespec0 + N
1529 * | tsc1 = tsc0 + M
1530 * 3. transition to guest | transition to guest
1531 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1532 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1533 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1534 *
1535 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1536 *
1537 * - ret0 < ret1
1538 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1539 * ...
1540 * - 0 < N - M => M < N
1541 *
1542 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1543 * always the case (the difference between two distinct xtime instances
1544 * might be smaller then the difference between corresponding TSC reads,
1545 * when updating guest vcpus pvclock areas).
1546 *
1547 * To avoid that problem, do not allow visibility of distinct
1548 * system_timestamp/tsc_timestamp values simultaneously: use a master
1549 * copy of host monotonic time values. Update that master copy
1550 * in lockstep.
1551 *
b48aa97e 1552 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1553 *
1554 */
1555
1556static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1557{
1558#ifdef CONFIG_X86_64
1559 struct kvm_arch *ka = &kvm->arch;
1560 int vclock_mode;
b48aa97e
MT		 1561 bool host_tsc_clocksource, vcpus_matched;
1562
1563 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1564 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1565
1566 /*
1567 * If the host uses TSC clock, then passthrough TSC as stable
1568 * to the guest.
1569 */
b48aa97e 1570 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1571 &ka->master_kernel_ns,
1572 &ka->master_cycle_now);
1573
16a96021 1574 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1575 && !backwards_tsc_observed
1576 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1577
d828199e
MT		 1578 if (ka->use_master_clock)
1579 atomic_set(&kvm_guest_has_master_clock, 1);
1580
1581 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1582 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1583 vcpus_matched);
d828199e
MT		 1584#endif
1585}
1586
2e762ff7
MT		 1587static void kvm_gen_update_masterclock(struct kvm *kvm)
1588{
1589#ifdef CONFIG_X86_64
1590 int i;
1591 struct kvm_vcpu *vcpu;
1592 struct kvm_arch *ka = &kvm->arch;
1593
1594 spin_lock(&ka->pvclock_gtod_sync_lock);
1595 kvm_make_mclock_inprogress_request(kvm);
1596 /* no guest entries from this point */
1597 pvclock_update_vm_gtod_copy(kvm);
1598
1599 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1600 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1601
1602 /* guest entries allowed */
1603 kvm_for_each_vcpu(i, vcpu, kvm)
1604 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1605
1606 spin_unlock(&ka->pvclock_gtod_sync_lock);
1607#endif
1608}
1609
34c238a1 1610static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1611{
d828199e 1612 unsigned long flags, this_tsc_khz;
18068523 1613 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1614 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1615 s64 kernel_ns;
d828199e 1616 u64 tsc_timestamp, host_tsc;
0b79459b 1617 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1618 u8 pvclock_flags;
d828199e
MT		 1619 bool use_master_clock;
1620
1621 kernel_ns = 0;
1622 host_tsc = 0;
18068523 1623
d828199e
MT		 1624 /*
1625 * If the host uses TSC clock, then passthrough TSC as stable
1626 * to the guest.
1627 */
1628 spin_lock(&ka->pvclock_gtod_sync_lock);
1629 use_master_clock = ka->use_master_clock;
1630 if (use_master_clock) {
1631 host_tsc = ka->master_cycle_now;
1632 kernel_ns = ka->master_kernel_ns;
1633 }
1634 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1635
1636 /* Keep irq disabled to prevent changes to the clock */
1637 local_irq_save(flags);
89cbc767 1638 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1639 if (unlikely(this_tsc_khz == 0)) {
1640 local_irq_restore(flags);
1641 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1642 return 1;
1643 }
d828199e
MT		 1644 if (!use_master_clock) {
1645 host_tsc = native_read_tsc();
1646 kernel_ns = get_kernel_ns();
1647 }
1648
1649 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1650
c285545f
ZA		 1651 /*
1652 * We may have to catch up the TSC to match elapsed wall clock
1653 * time for two reasons, even if kvmclock is used.
1654 * 1) CPU could have been running below the maximum TSC rate
1655 * 2) Broken TSC compensation resets the base at each VCPU
1656 * entry to avoid unknown leaps of TSC even when running
1657 * again on the same CPU. This may cause apparent elapsed
1658 * time to disappear, and the guest to stand still or run
1659 * very slowly.
1660 */
1661 if (vcpu->tsc_catchup) {
1662 u64 tsc = compute_guest_tsc(v, kernel_ns);
1663 if (tsc > tsc_timestamp) {
f1e2b260 1664 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1665 tsc_timestamp = tsc;
1666 }
50d0a0f9
GH		 1667 }
1668
18068523
GOC		 1669 local_irq_restore(flags);
1670
0b79459b 1671 if (!vcpu->pv_time_enabled)
c285545f 1672 return 0;
18068523 1673
e48672fa 1674 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1675 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1676 &vcpu->hv_clock.tsc_shift,
1677 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1678 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1679 }
1680
1681 /* With all the info we got, fill in the values */
1d5f066e 1682 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1683 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1684 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1685
09a0c3f1
OH		 1686 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1687 &guest_hv_clock, sizeof(guest_hv_clock))))
1688 return 0;
1689
5dca0d91
RK		 1690 /* This VCPU is paused, but it's legal for a guest to read another
1691 * VCPU's kvmclock, so we really have to follow the specification where
1692 * it says that version is odd if data is being modified, and even after
1693 * it is consistent.
1694 *
1695 * Version field updates must be kept separate. This is because
1696 * kvm_write_guest_cached might use a "rep movs" instruction, and
1697 * writes within a string instruction are weakly ordered. So there
1698 * are three writes overall.
1699 *
1700 * As a small optimization, only write the version field in the first
1701 * and third write. The vcpu->pv_time cache is still valid, because the
1702 * version field is the first in the struct.
18068523 1703 */
5dca0d91
RK		 1704 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1705
1706 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1707 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1708 &vcpu->hv_clock,
1709 sizeof(vcpu->hv_clock.version));
1710
1711 smp_wmb();
78c0337a
MT		 1712
1713 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1714 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1715
1716 if (vcpu->pvclock_set_guest_stopped_request) {
1717 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1718 vcpu->pvclock_set_guest_stopped_request = false;
1719 }
1720
b7e60c5a
MT		 1721 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1722
d828199e
MT		 1723 /* If the host uses TSC clocksource, then it is stable */
1724 if (use_master_clock)
1725 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1726
78c0337a
MT		 1727 vcpu->hv_clock.flags = pvclock_flags;
1728
ce1a5e60
DM		 1729 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1730
0b79459b
AH		 1731 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1732 &vcpu->hv_clock,
1733 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1734
1735 smp_wmb();
1736
1737 vcpu->hv_clock.version++;
1738 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1739 &vcpu->hv_clock,
1740 sizeof(vcpu->hv_clock.version));
8cfdc000 1741 return 0;
c8076604
GH		 1742}
1743
0061d53d
MT		 1744/*
1745 * kvmclock updates which are isolated to a given vcpu, such as
1746 * vcpu->cpu migration, should not allow system_timestamp from
1747 * the rest of the vcpus to remain static. Otherwise ntp frequency
1748 * correction applies to one vcpu's system_timestamp but not
1749 * the others.
1750 *
1751 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1752 * We need to rate-limit these requests though, as they can
1753 * considerably slow guests that have a large number of vcpus.
1754 * The time for a remote vcpu to update its kvmclock is bound
1755 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1756 */
1757
7e44e449
AJ		 1758#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1759
1760static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1761{
1762 int i;
7e44e449
AJ		 1763 struct delayed_work *dwork = to_delayed_work(work);
1764 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1765 kvmclock_update_work);
1766 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1767 struct kvm_vcpu *vcpu;
1768
1769 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1771 kvm_vcpu_kick(vcpu);
1772 }
1773}
1774
7e44e449
AJ		 1775static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1776{
1777 struct kvm *kvm = v->kvm;
1778
105b21bb 1779 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1780 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1781 KVMCLOCK_UPDATE_DELAY);
1782}
1783
332967a3
AJ		 1784#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1785
1786static void kvmclock_sync_fn(struct work_struct *work)
1787{
1788 struct delayed_work *dwork = to_delayed_work(work);
1789 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1790 kvmclock_sync_work);
1791 struct kvm *kvm = container_of(ka, struct kvm, arch);
1792
630994b3
MT		 1793 if (!kvmclock_periodic_sync)
1794 return;
1795
332967a3
AJ		 1796 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1797 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1798 KVMCLOCK_SYNC_PERIOD);
1799}
1800
890ca9ae 1801static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1802{
890ca9ae
HY		 1803 u64 mcg_cap = vcpu->arch.mcg_cap;
1804 unsigned bank_num = mcg_cap & 0xff;
1805
15c4a640 1806 switch (msr) {
15c4a640 1807 case MSR_IA32_MCG_STATUS:
890ca9ae 1808 vcpu->arch.mcg_status = data;
15c4a640 1809 break;
c7ac679c 1810 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1811 if (!(mcg_cap & MCG_CTL_P))
1812 return 1;
1813 if (data != 0 && data != ~(u64)0)
1814 return -1;
1815 vcpu->arch.mcg_ctl = data;
1816 break;
1817 default:
1818 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1819 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1820 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1821 /* only 0 or all 1s can be written to IA32_MCi_CTL
1822 * some Linux kernels though clear bit 10 in bank 4 to
1823 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1824 * this to avoid an uncatched #GP in the guest
1825 */
890ca9ae 1826 if ((offset & 0x3) == 0 &&
114be429 1827 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1828 return -1;
1829 vcpu->arch.mce_banks[offset] = data;
1830 break;
1831 }
1832 return 1;
1833 }
1834 return 0;
1835}
1836
ffde22ac
ES		 1837static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1838{
1839 struct kvm *kvm = vcpu->kvm;
1840 int lm = is_long_mode(vcpu);
1841 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1842 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1843 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1844 : kvm->arch.xen_hvm_config.blob_size_32;
1845 u32 page_num = data & ~PAGE_MASK;
1846 u64 page_addr = data & PAGE_MASK;
1847 u8 *page;
1848 int r;
1849
1850 r = -E2BIG;
1851 if (page_num >= blob_size)
1852 goto out;
1853 r = -ENOMEM;
ff5c2c03
SL		 1854 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1855 if (IS_ERR(page)) {
1856 r = PTR_ERR(page);
ffde22ac 1857 goto out;
ff5c2c03 1858 }
54bf36aa 1859 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1860 goto out_free;
1861 r = 0;
1862out_free:
1863 kfree(page);
1864out:
1865 return r;
1866}
1867
344d9588
GN		 1868static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1869{
1870 gpa_t gpa = data & ~0x3f;
1871
4a969980 1872 /* Bits 2:5 are reserved, Should be zero */
6adba527 1873 if (data & 0x3c)
344d9588
GN		 1874 return 1;
1875
1876 vcpu->arch.apf.msr_val = data;
1877
1878 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1879 kvm_clear_async_pf_completion_queue(vcpu);
1880 kvm_async_pf_hash_reset(vcpu);
1881 return 0;
1882 }
1883
8f964525
AH		 1884 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1885 sizeof(u32)))
344d9588
GN		 1886 return 1;
1887
6adba527 1888 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1889 kvm_async_pf_wakeup_all(vcpu);
1890 return 0;
1891}
1892
12f9a48f
GC		 1893static void kvmclock_reset(struct kvm_vcpu *vcpu)
1894{
0b79459b 1895 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1896}
1897
c9aaa895
GC		 1898static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1899{
1900 u64 delta;
1901
1902 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1903 return;
1904
1905 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1906 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1907 vcpu->arch.st.accum_steal = delta;
1908}
1909
1910static void record_steal_time(struct kvm_vcpu *vcpu)
1911{
1912 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1913 return;
1914
1915 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1916 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1917 return;
1918
1919 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1920 vcpu->arch.st.steal.version += 2;
1921 vcpu->arch.st.accum_steal = 0;
1922
1923 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1924 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1925}
1926
8fe8ab46 1927int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1928{
5753785f 1929 bool pr = false;
8fe8ab46
WA		 1930 u32 msr = msr_info->index;
1931 u64 data = msr_info->data;
5753785f 1932
15c4a640 1933 switch (msr) {
2e32b719
BP		 1934 case MSR_AMD64_NB_CFG:
1935 case MSR_IA32_UCODE_REV:
1936 case MSR_IA32_UCODE_WRITE:
1937 case MSR_VM_HSAVE_PA:
1938 case MSR_AMD64_PATCH_LOADER:
1939 case MSR_AMD64_BU_CFG2:
1940 break;
1941
15c4a640 1942 case MSR_EFER:
b69e8cae 1943 return set_efer(vcpu, data);
8f1589d9
AP		 1944 case MSR_K7_HWCR:
1945 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1946 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1947 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1948 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1949 if (data != 0) {
a737f256
CD		 1950 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1951 data);
8f1589d9
AP		 1952 return 1;
1953 }
15c4a640 1954 break;
f7c6d140
AP		 1955 case MSR_FAM10H_MMIO_CONF_BASE:
1956 if (data != 0) {
a737f256
CD		 1957 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1958 "0x%llx\n", data);
f7c6d140
AP		 1959 return 1;
1960 }
15c4a640 1961 break;
b5e2fec0
AG		 1962 case MSR_IA32_DEBUGCTLMSR:
1963 if (!data) {
1964 /* We support the non-activated case already */
1965 break;
1966 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1967 /* Values other than LBR and BTF are vendor-specific,
1968 thus reserved and should throw a #GP */
1969 return 1;
1970 }
a737f256
CD		 1971 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1972 __func__, data);
b5e2fec0 1973 break;
9ba075a6 1974 case 0x200 ... 0x2ff:
ff53604b 1975 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1976 case MSR_IA32_APICBASE:
58cb628d 1977 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1978 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1979 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1980 case MSR_IA32_TSCDEADLINE:
1981 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1982 break;
ba904635
WA		 1983 case MSR_IA32_TSC_ADJUST:
1984 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1985 if (!msr_info->host_initiated) {
d913b904 1986 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 1987 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1988 }
1989 vcpu->arch.ia32_tsc_adjust_msr = data;
1990 }
1991 break;
15c4a640 1992 case MSR_IA32_MISC_ENABLE:
ad312c7c 1993 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1994 break;
64d60670
PB		 1995 case MSR_IA32_SMBASE:
1996 if (!msr_info->host_initiated)
1997 return 1;
1998 vcpu->arch.smbase = data;
1999 break;
11c6bffa 2000 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2001 case MSR_KVM_WALL_CLOCK:
2002 vcpu->kvm->arch.wall_clock = data;
2003 kvm_write_wall_clock(vcpu->kvm, data);
2004 break;
11c6bffa 2005 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2006 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2007 u64 gpa_offset;
54750f2c
MT		 2008 struct kvm_arch *ka = &vcpu->kvm->arch;
2009
12f9a48f 2010 kvmclock_reset(vcpu);
18068523 2011
54750f2c
MT		 2012 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2013 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2014
2015 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2016 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2017 &vcpu->requests);
2018
2019 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2020
2021 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2022 }
2023
18068523 2024 vcpu->arch.time = data;
0061d53d 2025 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2026
2027 /* we verify if the enable bit is set... */
2028 if (!(data & 1))
2029 break;
2030
0b79459b 2031 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2032
0b79459b 2033 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2034 &vcpu->arch.pv_time, data & ~1ULL,
2035 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2036 vcpu->arch.pv_time_enabled = false;
2037 else
2038 vcpu->arch.pv_time_enabled = true;
32cad84f 2039
18068523
GOC		 2040 break;
2041 }
344d9588
GN		 2042 case MSR_KVM_ASYNC_PF_EN:
2043 if (kvm_pv_enable_async_pf(vcpu, data))
2044 return 1;
2045 break;
c9aaa895
GC		 2046 case MSR_KVM_STEAL_TIME:
2047
2048 if (unlikely(!sched_info_on()))
2049 return 1;
2050
2051 if (data & KVM_STEAL_RESERVED_MASK)
2052 return 1;
2053
2054 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2055 data & KVM_STEAL_VALID_BITS,
2056 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2057 return 1;
2058
2059 vcpu->arch.st.msr_val = data;
2060
2061 if (!(data & KVM_MSR_ENABLED))
2062 break;
2063
2064 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2065
2066 preempt_disable();
2067 accumulate_steal_time(vcpu);
2068 preempt_enable();
2069
2070 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2071
2072 break;
ae7a2a3f
MT		 2073 case MSR_KVM_PV_EOI_EN:
2074 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2075 return 1;
2076 break;
c9aaa895 2077
890ca9ae
HY		 2078 case MSR_IA32_MCG_CTL:
2079 case MSR_IA32_MCG_STATUS:
81760dcc 2080 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2081 return set_msr_mce(vcpu, msr, data);
71db6023 2082
6912ac32
WH		 2083 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2084 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2085 pr = true; /* fall through */
2086 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2087 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2088 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2089 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2090
2091 if (pr || data != 0)
a737f256
CD		 2092 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2093 "0x%x data 0x%llx\n", msr, data);
5753785f 2094 break;
84e0cefa
JS		 2095 case MSR_K7_CLK_CTL:
2096 /*
2097 * Ignore all writes to this no longer documented MSR.
2098 * Writes are only relevant for old K7 processors,
2099 * all pre-dating SVM, but a recommended workaround from
4a969980 2100 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2101 * affected processor models on the command line, hence
2102 * the need to ignore the workaround.
2103 */
2104 break;
55cd8e5a 2105 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2106 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2107 case HV_X64_MSR_CRASH_CTL:
2108 return kvm_hv_set_msr_common(vcpu, msr, data,
2109 msr_info->host_initiated);
91c9c3ed 2110 case MSR_IA32_BBL_CR_CTL3:
2111 /* Drop writes to this legacy MSR -- see rdmsr
2112 * counterpart for further detail.
2113 */
a737f256 2114 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2115 break;
2b036c6b
BO		 2116 case MSR_AMD64_OSVW_ID_LENGTH:
2117 if (!guest_cpuid_has_osvw(vcpu))
2118 return 1;
2119 vcpu->arch.osvw.length = data;
2120 break;
2121 case MSR_AMD64_OSVW_STATUS:
2122 if (!guest_cpuid_has_osvw(vcpu))
2123 return 1;
2124 vcpu->arch.osvw.status = data;
2125 break;
15c4a640 2126 default:
ffde22ac
ES		 2127 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2128 return xen_hvm_config(vcpu, data);
c6702c9d 2129 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2130 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2131 if (!ignore_msrs) {
a737f256
CD		 2132 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2133 msr, data);
ed85c068
AP		 2134 return 1;
2135 } else {
a737f256
CD		 2136 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2137 msr, data);
ed85c068
AP		 2138 break;
2139 }
15c4a640
CO		 2140 }
2141 return 0;
2142}
2143EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2144
2145
2146/*
2147 * Reads an msr value (of 'msr_index') into 'pdata'.
2148 * Returns 0 on success, non-0 otherwise.
2149 * Assumes vcpu_load() was already called.
2150 */
609e36d3 2151int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2152{
609e36d3 2153 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2154}
ff651cb6 2155EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2156
890ca9ae 2157static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2158{
2159 u64 data;
890ca9ae
HY		 2160 u64 mcg_cap = vcpu->arch.mcg_cap;
2161 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2162
2163 switch (msr) {
15c4a640
CO		 2164 case MSR_IA32_P5_MC_ADDR:
2165 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2166 data = 0;
2167 break;
15c4a640 2168 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2169 data = vcpu->arch.mcg_cap;
2170 break;
c7ac679c 2171 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2172 if (!(mcg_cap & MCG_CTL_P))
2173 return 1;
2174 data = vcpu->arch.mcg_ctl;
2175 break;
2176 case MSR_IA32_MCG_STATUS:
2177 data = vcpu->arch.mcg_status;
2178 break;
2179 default:
2180 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2181 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2182 u32 offset = msr - MSR_IA32_MC0_CTL;
2183 data = vcpu->arch.mce_banks[offset];
2184 break;
2185 }
2186 return 1;
2187 }
2188 *pdata = data;
2189 return 0;
2190}
2191
609e36d3 2192int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2193{
609e36d3 2194 switch (msr_info->index) {
890ca9ae 2195 case MSR_IA32_PLATFORM_ID:
15c4a640 2196 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2197 case MSR_IA32_DEBUGCTLMSR:
2198 case MSR_IA32_LASTBRANCHFROMIP:
2199 case MSR_IA32_LASTBRANCHTOIP:
2200 case MSR_IA32_LASTINTFROMIP:
2201 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2202 case MSR_K8_SYSCFG:
2203 case MSR_K7_HWCR:
61a6bd67 2204 case MSR_VM_HSAVE_PA:
1fdbd48c 2205 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2206 case MSR_AMD64_NB_CFG:
f7c6d140 2207 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2208 case MSR_AMD64_BU_CFG2:
609e36d3 2209 msr_info->data = 0;
15c4a640 2210 break;
6912ac32
WH		 2211 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2212 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2213 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2214 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2215 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2216 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2217 msr_info->data = 0;
5753785f 2218 break;
742bc670 2219 case MSR_IA32_UCODE_REV:
609e36d3 2220 msr_info->data = 0x100000000ULL;
742bc670 2221 break;
9ba075a6 2222 case MSR_MTRRcap:
9ba075a6 2223 case 0x200 ... 0x2ff:
ff53604b 2224 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2225 case 0xcd: /* fsb frequency */
609e36d3 2226 msr_info->data = 3;
15c4a640 2227 break;
7b914098
JS		 2228 /*
2229 * MSR_EBC_FREQUENCY_ID
2230 * Conservative value valid for even the basic CPU models.
2231 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2232 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2233 * and 266MHz for model 3, or 4. Set Core Clock
2234 * Frequency to System Bus Frequency Ratio to 1 (bits
2235 * 31:24) even though these are only valid for CPU
2236 * models > 2, however guests may end up dividing or
2237 * multiplying by zero otherwise.
2238 */
2239 case MSR_EBC_FREQUENCY_ID:
609e36d3 2240 msr_info->data = 1 << 24;
7b914098 2241 break;
15c4a640 2242 case MSR_IA32_APICBASE:
609e36d3 2243 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2244 break;
0105d1a5 2245 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2246 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2247 break;
a3e06bbe 2248 case MSR_IA32_TSCDEADLINE:
609e36d3 2249 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2250 break;
ba904635 2251 case MSR_IA32_TSC_ADJUST:
609e36d3 2252 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2253 break;
15c4a640 2254 case MSR_IA32_MISC_ENABLE:
609e36d3 2255 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2256 break;
64d60670
PB		 2257 case MSR_IA32_SMBASE:
2258 if (!msr_info->host_initiated)
2259 return 1;
2260 msr_info->data = vcpu->arch.smbase;
15c4a640 2261 break;
847f0ad8
AG		 2262 case MSR_IA32_PERF_STATUS:
2263 /* TSC increment by tick */
609e36d3 2264 msr_info->data = 1000ULL;
847f0ad8 2265 /* CPU multiplier */
b0996ae4 2266 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2267 break;
15c4a640 2268 case MSR_EFER:
609e36d3 2269 msr_info->data = vcpu->arch.efer;
15c4a640 2270 break;
18068523 2271 case MSR_KVM_WALL_CLOCK:
11c6bffa 2272 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2273 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2274 break;
2275 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2276 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2277 msr_info->data = vcpu->arch.time;
18068523 2278 break;
344d9588 2279 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2280 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2281 break;
c9aaa895 2282 case MSR_KVM_STEAL_TIME:
609e36d3 2283 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2284 break;
1d92128f 2285 case MSR_KVM_PV_EOI_EN:
609e36d3 2286 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2287 break;
890ca9ae
HY		 2288 case MSR_IA32_P5_MC_ADDR:
2289 case MSR_IA32_P5_MC_TYPE:
2290 case MSR_IA32_MCG_CAP:
2291 case MSR_IA32_MCG_CTL:
2292 case MSR_IA32_MCG_STATUS:
81760dcc 2293 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2294 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2295 case MSR_K7_CLK_CTL:
2296 /*
2297 * Provide expected ramp-up count for K7. All other
2298 * are set to zero, indicating minimum divisors for
2299 * every field.
2300 *
2301 * This prevents guest kernels on AMD host with CPU
2302 * type 6, model 8 and higher from exploding due to
2303 * the rdmsr failing.
2304 */
609e36d3 2305 msr_info->data = 0x20000000;
84e0cefa 2306 break;
55cd8e5a 2307 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2308 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2309 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2310 return kvm_hv_get_msr_common(vcpu,
2311 msr_info->index, &msr_info->data);
55cd8e5a 2312 break;
91c9c3ed 2313 case MSR_IA32_BBL_CR_CTL3:
2314 /* This legacy MSR exists but isn't fully documented in current
2315 * silicon. It is however accessed by winxp in very narrow
2316 * scenarios where it sets bit #19, itself documented as
2317 * a "reserved" bit. Best effort attempt to source coherent
2318 * read data here should the balance of the register be
2319 * interpreted by the guest:
2320 *
2321 * L2 cache control register 3: 64GB range, 256KB size,
2322 * enabled, latency 0x1, configured
2323 */
609e36d3 2324 msr_info->data = 0xbe702111;
91c9c3ed 2325 break;
2b036c6b
BO		 2326 case MSR_AMD64_OSVW_ID_LENGTH:
2327 if (!guest_cpuid_has_osvw(vcpu))
2328 return 1;
609e36d3 2329 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2330 break;
2331 case MSR_AMD64_OSVW_STATUS:
2332 if (!guest_cpuid_has_osvw(vcpu))
2333 return 1;
609e36d3 2334 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2335 break;
15c4a640 2336 default:
c6702c9d 2337 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2338 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2339 if (!ignore_msrs) {
609e36d3 2340 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2341 return 1;
2342 } else {
609e36d3
PB		 2343 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2344 msr_info->data = 0;
ed85c068
AP		 2345 }
2346 break;
15c4a640 2347 }
15c4a640
CO		 2348 return 0;
2349}
2350EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2351
313a3dc7
CO		 2352/*
2353 * Read or write a bunch of msrs. All parameters are kernel addresses.
2354 *
2355 * @return number of msrs set successfully.
2356 */
2357static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2358 struct kvm_msr_entry *entries,
2359 int (*do_msr)(struct kvm_vcpu *vcpu,
2360 unsigned index, u64 *data))
2361{
f656ce01 2362 int i, idx;
313a3dc7 2363
f656ce01 2364 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2365 for (i = 0; i < msrs->nmsrs; ++i)
2366 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2367 break;
f656ce01 2368 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2369
313a3dc7
CO		 2370 return i;
2371}
2372
2373/*
2374 * Read or write a bunch of msrs. Parameters are user addresses.
2375 *
2376 * @return number of msrs set successfully.
2377 */
2378static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2379 int (*do_msr)(struct kvm_vcpu *vcpu,
2380 unsigned index, u64 *data),
2381 int writeback)
2382{
2383 struct kvm_msrs msrs;
2384 struct kvm_msr_entry *entries;
2385 int r, n;
2386 unsigned size;
2387
2388 r = -EFAULT;
2389 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2390 goto out;
2391
2392 r = -E2BIG;
2393 if (msrs.nmsrs >= MAX_IO_MSRS)
2394 goto out;
2395
313a3dc7 2396 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2397 entries = memdup_user(user_msrs->entries, size);
2398 if (IS_ERR(entries)) {
2399 r = PTR_ERR(entries);
313a3dc7 2400 goto out;
ff5c2c03 2401 }
313a3dc7
CO		 2402
2403 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2404 if (r < 0)
2405 goto out_free;
2406
2407 r = -EFAULT;
2408 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2409 goto out_free;
2410
2411 r = n;
2412
2413out_free:
7a73c028 2414 kfree(entries);
313a3dc7
CO		 2415out:
2416 return r;
2417}
2418
784aa3d7 2419int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2420{
2421 int r;
2422
2423 switch (ext) {
2424 case KVM_CAP_IRQCHIP:
2425 case KVM_CAP_HLT:
2426 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2427 case KVM_CAP_SET_TSS_ADDR:
07716717 2428 case KVM_CAP_EXT_CPUID:
9c15bb1d 2429 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2430 case KVM_CAP_CLOCKSOURCE:
7837699f 2431 case KVM_CAP_PIT:
a28e4f5a 2432 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2433 case KVM_CAP_MP_STATE:
ed848624 2434 case KVM_CAP_SYNC_MMU:
a355c85c 2435 case KVM_CAP_USER_NMI:
52d939a0 2436 case KVM_CAP_REINJECT_CONTROL:
4925663a 2437 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2438 case KVM_CAP_IOEVENTFD:
f848a5a8 2439 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2440 case KVM_CAP_PIT2:
e9f42757 2441 case KVM_CAP_PIT_STATE2:
b927a3ce 2442 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2443 case KVM_CAP_XEN_HVM:
afbcf7ab 2444 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2445 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2446 case KVM_CAP_HYPERV:
10388a07 2447 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2448 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2449 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2450 case KVM_CAP_DEBUGREGS:
d2be1651 2451 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2452 case KVM_CAP_XSAVE:
344d9588 2453 case KVM_CAP_ASYNC_PF:
92a1f12d 2454 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2455 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2456 case KVM_CAP_READONLY_MEM:
5f66b620 2457 case KVM_CAP_HYPERV_TIME:
100943c5 2458 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2459 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2460 case KVM_CAP_ENABLE_CAP_VM:
2461 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2462 case KVM_CAP_SET_BOOT_CPU_ID:
2a5bab10
AW		 2463#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2464 case KVM_CAP_ASSIGN_DEV_IRQ:
2465 case KVM_CAP_PCI_2_3:
2466#endif
018d00d2
ZX		 2467 r = 1;
2468 break;
6d396b55
PB		 2469 case KVM_CAP_X86_SMM:
2470 /* SMBASE is usually relocated above 1M on modern chipsets,
2471 * and SMM handlers might indeed rely on 4G segment limits,
2472 * so do not report SMM to be available if real mode is
2473 * emulated via vm86 mode. Still, do not go to great lengths
2474 * to avoid userspace's usage of the feature, because it is a
2475 * fringe case that is not enabled except via specific settings
2476 * of the module parameters.
2477 */
2478 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2479 break;
542472b5
LV		 2480 case KVM_CAP_COALESCED_MMIO:
2481 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2482 break;
774ead3a
AK		 2483 case KVM_CAP_VAPIC:
2484 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2485 break;
f725230a 2486 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2487 r = KVM_SOFT_MAX_VCPUS;
2488 break;
2489 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2490 r = KVM_MAX_VCPUS;
2491 break;
a988b910 2492 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2493 r = KVM_USER_MEM_SLOTS;
a988b910 2494 break;
a68a6a72
MT		 2495 case KVM_CAP_PV_MMU: /* obsolete */
2496 r = 0;
2f333bcb 2497 break;
4cee4b72 2498#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2499 case KVM_CAP_IOMMU:
a1b60c1c 2500 r = iommu_present(&pci_bus_type);
62c476c7 2501 break;
4cee4b72 2502#endif
890ca9ae
HY		 2503 case KVM_CAP_MCE:
2504 r = KVM_MAX_MCE_BANKS;
2505 break;
2d5b5a66
SY		 2506 case KVM_CAP_XCRS:
2507 r = cpu_has_xsave;
2508 break;
92a1f12d
JR		 2509 case KVM_CAP_TSC_CONTROL:
2510 r = kvm_has_tsc_control;
2511 break;
018d00d2
ZX		 2512 default:
2513 r = 0;
2514 break;
2515 }
2516 return r;
2517
2518}
2519
043405e1
CO		 2520long kvm_arch_dev_ioctl(struct file *filp,
2521 unsigned int ioctl, unsigned long arg)
2522{
2523 void __user *argp = (void __user *)arg;
2524 long r;
2525
2526 switch (ioctl) {
2527 case KVM_GET_MSR_INDEX_LIST: {
2528 struct kvm_msr_list __user *user_msr_list = argp;
2529 struct kvm_msr_list msr_list;
2530 unsigned n;
2531
2532 r = -EFAULT;
2533 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2534 goto out;
2535 n = msr_list.nmsrs;
62ef68bb 2536 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2537 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2538 goto out;
2539 r = -E2BIG;
e125e7b6 2540 if (n < msr_list.nmsrs)
043405e1
CO		 2541 goto out;
2542 r = -EFAULT;
2543 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2544 num_msrs_to_save * sizeof(u32)))
2545 goto out;
e125e7b6 2546 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2547 &emulated_msrs,
62ef68bb 2548 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2549 goto out;
2550 r = 0;
2551 break;
2552 }
9c15bb1d
BP		 2553 case KVM_GET_SUPPORTED_CPUID:
2554 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2555 struct kvm_cpuid2 __user *cpuid_arg = argp;
2556 struct kvm_cpuid2 cpuid;
2557
2558 r = -EFAULT;
2559 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2560 goto out;
9c15bb1d
BP		 2561
2562 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2563 ioctl);
674eea0f
AK		 2564 if (r)
2565 goto out;
2566
2567 r = -EFAULT;
2568 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2569 goto out;
2570 r = 0;
2571 break;
2572 }
890ca9ae
HY		 2573 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2574 u64 mce_cap;
2575
2576 mce_cap = KVM_MCE_CAP_SUPPORTED;
2577 r = -EFAULT;
2578 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2579 goto out;
2580 r = 0;
2581 break;
2582 }
043405e1
CO		 2583 default:
2584 r = -EINVAL;
2585 }
2586out:
2587 return r;
2588}
2589
f5f48ee1
SY		 2590static void wbinvd_ipi(void *garbage)
2591{
2592 wbinvd();
2593}
2594
2595static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2596{
e0f0bbc5 2597 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2598}
2599
313a3dc7
CO		 2600void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2601{
f5f48ee1
SY		 2602 /* Address WBINVD may be executed by guest */
2603 if (need_emulate_wbinvd(vcpu)) {
2604 if (kvm_x86_ops->has_wbinvd_exit())
2605 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2606 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2607 smp_call_function_single(vcpu->cpu,
2608 wbinvd_ipi, NULL, 1);
2609 }
2610
313a3dc7 2611 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2612
0dd6a6ed
ZA		 2613 /* Apply any externally detected TSC adjustments (due to suspend) */
2614 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2615 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2616 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2617 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2618 }
8f6055cb 2619
48434c20 2620 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2621 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2622 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2623 if (tsc_delta < 0)
2624 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2625 if (check_tsc_unstable()) {
b183aa58
ZA		 2626 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2627 vcpu->arch.last_guest_tsc);
2628 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2629 vcpu->arch.tsc_catchup = 1;
c285545f 2630 }
d98d07ca
MT		 2631 /*
2632 * On a host with synchronized TSC, there is no need to update
2633 * kvmclock on vcpu->cpu migration
2634 */
2635 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2636 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2637 if (vcpu->cpu != cpu)
2638 kvm_migrate_timers(vcpu);
e48672fa 2639 vcpu->cpu = cpu;
6b7d7e76 2640 }
c9aaa895
GC		 2641
2642 accumulate_steal_time(vcpu);
2643 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2644}
2645
2646void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2647{
02daab21 2648 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2649 kvm_put_guest_fpu(vcpu);
6f526ec5 2650 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2651}
2652
313a3dc7
CO		 2653static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2654 struct kvm_lapic_state *s)
2655{
5a71785d 2656 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2657 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2658
2659 return 0;
2660}
2661
2662static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2663 struct kvm_lapic_state *s)
2664{
64eb0620 2665 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2666 update_cr8_intercept(vcpu);
313a3dc7
CO		 2667
2668 return 0;
2669}
2670
f77bc6a4
ZX		 2671static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2672 struct kvm_interrupt *irq)
2673{
02cdb50f 2674 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2675 return -EINVAL;
2676 if (irqchip_in_kernel(vcpu->kvm))
2677 return -ENXIO;
f77bc6a4 2678
66fd3f7f 2679 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2680 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2681
f77bc6a4
ZX		 2682 return 0;
2683}
2684
c4abb7c9
JK		 2685static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2686{
c4abb7c9 2687 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2688
2689 return 0;
2690}
2691
f077825a
PB		 2692static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2693{
64d60670
PB		 2694 kvm_make_request(KVM_REQ_SMI, vcpu);
2695
f077825a
PB		 2696 return 0;
2697}
2698
b209749f
AK		 2699static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2700 struct kvm_tpr_access_ctl *tac)
2701{
2702 if (tac->flags)
2703 return -EINVAL;
2704 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2705 return 0;
2706}
2707
890ca9ae
HY		 2708static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2709 u64 mcg_cap)
2710{
2711 int r;
2712 unsigned bank_num = mcg_cap & 0xff, bank;
2713
2714 r = -EINVAL;
a9e38c3e 2715 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2716 goto out;
2717 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2718 goto out;
2719 r = 0;
2720 vcpu->arch.mcg_cap = mcg_cap;
2721 /* Init IA32_MCG_CTL to all 1s */
2722 if (mcg_cap & MCG_CTL_P)
2723 vcpu->arch.mcg_ctl = ~(u64)0;
2724 /* Init IA32_MCi_CTL to all 1s */
2725 for (bank = 0; bank < bank_num; bank++)
2726 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2727out:
2728 return r;
2729}
2730
2731static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2732 struct kvm_x86_mce *mce)
2733{
2734 u64 mcg_cap = vcpu->arch.mcg_cap;
2735 unsigned bank_num = mcg_cap & 0xff;
2736 u64 *banks = vcpu->arch.mce_banks;
2737
2738 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2739 return -EINVAL;
2740 /*
2741 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2742 * reporting is disabled
2743 */
2744 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2745 vcpu->arch.mcg_ctl != ~(u64)0)
2746 return 0;
2747 banks += 4 * mce->bank;
2748 /*
2749 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2750 * reporting is disabled for the bank
2751 */
2752 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2753 return 0;
2754 if (mce->status & MCI_STATUS_UC) {
2755 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2756 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2757 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2758 return 0;
2759 }
2760 if (banks[1] & MCI_STATUS_VAL)
2761 mce->status |= MCI_STATUS_OVER;
2762 banks[2] = mce->addr;
2763 banks[3] = mce->misc;
2764 vcpu->arch.mcg_status = mce->mcg_status;
2765 banks[1] = mce->status;
2766 kvm_queue_exception(vcpu, MC_VECTOR);
2767 } else if (!(banks[1] & MCI_STATUS_VAL)
2768 || !(banks[1] & MCI_STATUS_UC)) {
2769 if (banks[1] & MCI_STATUS_VAL)
2770 mce->status |= MCI_STATUS_OVER;
2771 banks[2] = mce->addr;
2772 banks[3] = mce->misc;
2773 banks[1] = mce->status;
2774 } else
2775 banks[1] |= MCI_STATUS_OVER;
2776 return 0;
2777}
2778
3cfc3092
JK		 2779static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2780 struct kvm_vcpu_events *events)
2781{
7460fb4a 2782 process_nmi(vcpu);
03b82a30
JK		 2783 events->exception.injected =
2784 vcpu->arch.exception.pending &&
2785 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2786 events->exception.nr = vcpu->arch.exception.nr;
2787 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2788 events->exception.pad = 0;
3cfc3092
JK		 2789 events->exception.error_code = vcpu->arch.exception.error_code;
2790
03b82a30
JK		 2791 events->interrupt.injected =
2792 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2793 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2794 events->interrupt.soft = 0;
37ccdcbe 2795 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2796
2797 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2798 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2799 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2800 events->nmi.pad = 0;
3cfc3092 2801
66450a21 2802 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2803
f077825a
PB		 2804 events->smi.smm = is_smm(vcpu);
2805 events->smi.pending = vcpu->arch.smi_pending;
2806 events->smi.smm_inside_nmi =
2807 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2808 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2809
dab4b911 2810 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2811 | KVM_VCPUEVENT_VALID_SHADOW
2812 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2813 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2814}
2815
2816static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2817 struct kvm_vcpu_events *events)
2818{
dab4b911 2819 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2820 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2821 | KVM_VCPUEVENT_VALID_SHADOW
2822 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2823 return -EINVAL;
2824
7460fb4a 2825 process_nmi(vcpu);
3cfc3092
JK		 2826 vcpu->arch.exception.pending = events->exception.injected;
2827 vcpu->arch.exception.nr = events->exception.nr;
2828 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2829 vcpu->arch.exception.error_code = events->exception.error_code;
2830
2831 vcpu->arch.interrupt.pending = events->interrupt.injected;
2832 vcpu->arch.interrupt.nr = events->interrupt.nr;
2833 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2834 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2835 kvm_x86_ops->set_interrupt_shadow(vcpu,
2836 events->interrupt.shadow);
3cfc3092
JK		 2837
2838 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2839 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2840 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2841 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2842
66450a21
JK		 2843 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2844 kvm_vcpu_has_lapic(vcpu))
2845 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2846
f077825a
PB		 2847 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2848 if (events->smi.smm)
2849 vcpu->arch.hflags |= HF_SMM_MASK;
2850 else
2851 vcpu->arch.hflags &= ~HF_SMM_MASK;
2852 vcpu->arch.smi_pending = events->smi.pending;
2853 if (events->smi.smm_inside_nmi)
2854 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2855 else
2856 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2857 if (kvm_vcpu_has_lapic(vcpu)) {
2858 if (events->smi.latched_init)
2859 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2860 else
2861 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2862 }
2863 }
2864
3842d135
AK		 2865 kvm_make_request(KVM_REQ_EVENT, vcpu);
2866
3cfc3092
JK		 2867 return 0;
2868}
2869
a1efbe77
JK		 2870static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2871 struct kvm_debugregs *dbgregs)
2872{
73aaf249
JK		 2873 unsigned long val;
2874
a1efbe77 2875 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2876 kvm_get_dr(vcpu, 6, &val);
73aaf249 2877 dbgregs->dr6 = val;
a1efbe77
JK		 2878 dbgregs->dr7 = vcpu->arch.dr7;
2879 dbgregs->flags = 0;
97e69aa6 2880 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2881}
2882
2883static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2884 struct kvm_debugregs *dbgregs)
2885{
2886 if (dbgregs->flags)
2887 return -EINVAL;
2888
a1efbe77 2889 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2890 kvm_update_dr0123(vcpu);
a1efbe77 2891 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2892 kvm_update_dr6(vcpu);
a1efbe77 2893 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2894 kvm_update_dr7(vcpu);
a1efbe77 2895
a1efbe77
JK		 2896 return 0;
2897}
2898
df1daba7
PB		 2899#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2900
2901static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2902{
c47ada30 2903 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2904 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2905 u64 valid;
2906
2907 /*
2908 * Copy legacy XSAVE area, to avoid complications with CPUID
2909 * leaves 0 and 1 in the loop below.
2910 */
2911 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2912
2913 /* Set XSTATE_BV */
2914 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2915
2916 /*
2917 * Copy each region from the possibly compacted offset to the
2918 * non-compacted offset.
2919 */
2920 valid = xstate_bv & ~XSTATE_FPSSE;
2921 while (valid) {
2922 u64 feature = valid & -valid;
2923 int index = fls64(feature) - 1;
2924 void *src = get_xsave_addr(xsave, feature);
2925
2926 if (src) {
2927 u32 size, offset, ecx, edx;
2928 cpuid_count(XSTATE_CPUID, index,
2929 &size, &offset, &ecx, &edx);
2930 memcpy(dest + offset, src, size);
2931 }
2932
2933 valid -= feature;
2934 }
2935}
2936
2937static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2938{
c47ada30 2939 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2940 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2941 u64 valid;
2942
2943 /*
2944 * Copy legacy XSAVE area, to avoid complications with CPUID
2945 * leaves 0 and 1 in the loop below.
2946 */
2947 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2948
2949 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2950 xsave->header.xfeatures = xstate_bv;
df1daba7 2951 if (cpu_has_xsaves)
3a54450b 2952 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2953
2954 /*
2955 * Copy each region from the non-compacted offset to the
2956 * possibly compacted offset.
2957 */
2958 valid = xstate_bv & ~XSTATE_FPSSE;
2959 while (valid) {
2960 u64 feature = valid & -valid;
2961 int index = fls64(feature) - 1;
2962 void *dest = get_xsave_addr(xsave, feature);
2963
2964 if (dest) {
2965 u32 size, offset, ecx, edx;
2966 cpuid_count(XSTATE_CPUID, index,
2967 &size, &offset, &ecx, &edx);
2968 memcpy(dest, src + offset, size);
ee4100da 2969 }
df1daba7
PB		 2970
2971 valid -= feature;
2972 }
2973}
2974
2d5b5a66
SY		 2975static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2976 struct kvm_xsave *guest_xsave)
2977{
4344ee98 2978 if (cpu_has_xsave) {
df1daba7
PB		 2979 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2980 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2981 } else {
2d5b5a66 2982 memcpy(guest_xsave->region,
7366ed77 2983 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2984 sizeof(struct fxregs_state));
2d5b5a66
SY		 2985 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2986 XSTATE_FPSSE;
2987 }
2988}
2989
2990static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2991 struct kvm_xsave *guest_xsave)
2992{
2993 u64 xstate_bv =
2994 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2995
d7876f1b
PB		 2996 if (cpu_has_xsave) {
2997 /*
2998 * Here we allow setting states that are not present in
2999 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3000 * with old userspace.
3001 */
4ff41732 3002 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3003 return -EINVAL;
df1daba7 3004 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3005 } else {
2d5b5a66
SY		 3006 if (xstate_bv & ~XSTATE_FPSSE)
3007 return -EINVAL;
7366ed77 3008 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3009 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3010 }
3011 return 0;
3012}
3013
3014static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3015 struct kvm_xcrs *guest_xcrs)
3016{
3017 if (!cpu_has_xsave) {
3018 guest_xcrs->nr_xcrs = 0;
3019 return;
3020 }
3021
3022 guest_xcrs->nr_xcrs = 1;
3023 guest_xcrs->flags = 0;
3024 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3025 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3026}
3027
3028static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3029 struct kvm_xcrs *guest_xcrs)
3030{
3031 int i, r = 0;
3032
3033 if (!cpu_has_xsave)
3034 return -EINVAL;
3035
3036 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3037 return -EINVAL;
3038
3039 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3040 /* Only support XCR0 currently */
c67a04cb 3041 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3042 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3043 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3044 break;
3045 }
3046 if (r)
3047 r = -EINVAL;
3048 return r;
3049}
3050
1c0b28c2
EM		 3051/*
3052 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3053 * stopped by the hypervisor. This function will be called from the host only.
3054 * EINVAL is returned when the host attempts to set the flag for a guest that
3055 * does not support pv clocks.
3056 */
3057static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3058{
0b79459b 3059 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3060 return -EINVAL;
51d59c6b 3061 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3063 return 0;
3064}
3065
313a3dc7
CO		 3066long kvm_arch_vcpu_ioctl(struct file *filp,
3067 unsigned int ioctl, unsigned long arg)
3068{
3069 struct kvm_vcpu *vcpu = filp->private_data;
3070 void __user *argp = (void __user *)arg;
3071 int r;
d1ac91d8
AK		 3072 union {
3073 struct kvm_lapic_state *lapic;
3074 struct kvm_xsave *xsave;
3075 struct kvm_xcrs *xcrs;
3076 void *buffer;
3077 } u;
3078
3079 u.buffer = NULL;
313a3dc7
CO		 3080 switch (ioctl) {
3081 case KVM_GET_LAPIC: {
2204ae3c
MT		 3082 r = -EINVAL;
3083 if (!vcpu->arch.apic)
3084 goto out;
d1ac91d8 3085 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3086
b772ff36 3087 r = -ENOMEM;
d1ac91d8 3088 if (!u.lapic)
b772ff36 3089 goto out;
d1ac91d8 3090 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3091 if (r)
3092 goto out;
3093 r = -EFAULT;
d1ac91d8 3094 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3095 goto out;
3096 r = 0;
3097 break;
3098 }
3099 case KVM_SET_LAPIC: {
2204ae3c
MT		 3100 r = -EINVAL;
3101 if (!vcpu->arch.apic)
3102 goto out;
ff5c2c03 3103 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3104 if (IS_ERR(u.lapic))
3105 return PTR_ERR(u.lapic);
ff5c2c03 3106
d1ac91d8 3107 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3108 break;
3109 }
f77bc6a4
ZX		 3110 case KVM_INTERRUPT: {
3111 struct kvm_interrupt irq;
3112
3113 r = -EFAULT;
3114 if (copy_from_user(&irq, argp, sizeof irq))
3115 goto out;
3116 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3117 break;
3118 }
c4abb7c9
JK		 3119 case KVM_NMI: {
3120 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3121 break;
3122 }
f077825a
PB		 3123 case KVM_SMI: {
3124 r = kvm_vcpu_ioctl_smi(vcpu);
3125 break;
3126 }
313a3dc7
CO		 3127 case KVM_SET_CPUID: {
3128 struct kvm_cpuid __user *cpuid_arg = argp;
3129 struct kvm_cpuid cpuid;
3130
3131 r = -EFAULT;
3132 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3133 goto out;
3134 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3135 break;
3136 }
07716717
DK		 3137 case KVM_SET_CPUID2: {
3138 struct kvm_cpuid2 __user *cpuid_arg = argp;
3139 struct kvm_cpuid2 cpuid;
3140
3141 r = -EFAULT;
3142 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3143 goto out;
3144 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3145 cpuid_arg->entries);
07716717
DK		 3146 break;
3147 }
3148 case KVM_GET_CPUID2: {
3149 struct kvm_cpuid2 __user *cpuid_arg = argp;
3150 struct kvm_cpuid2 cpuid;
3151
3152 r = -EFAULT;
3153 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3154 goto out;
3155 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3156 cpuid_arg->entries);
07716717
DK		 3157 if (r)
3158 goto out;
3159 r = -EFAULT;
3160 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3161 goto out;
3162 r = 0;
3163 break;
3164 }
313a3dc7 3165 case KVM_GET_MSRS:
609e36d3 3166 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3167 break;
3168 case KVM_SET_MSRS:
3169 r = msr_io(vcpu, argp, do_set_msr, 0);
3170 break;
b209749f
AK		 3171 case KVM_TPR_ACCESS_REPORTING: {
3172 struct kvm_tpr_access_ctl tac;
3173
3174 r = -EFAULT;
3175 if (copy_from_user(&tac, argp, sizeof tac))
3176 goto out;
3177 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3178 if (r)
3179 goto out;
3180 r = -EFAULT;
3181 if (copy_to_user(argp, &tac, sizeof tac))
3182 goto out;
3183 r = 0;
3184 break;
3185 };
b93463aa
AK		 3186 case KVM_SET_VAPIC_ADDR: {
3187 struct kvm_vapic_addr va;
3188
3189 r = -EINVAL;
3190 if (!irqchip_in_kernel(vcpu->kvm))
3191 goto out;
3192 r = -EFAULT;
3193 if (copy_from_user(&va, argp, sizeof va))
3194 goto out;
fda4e2e8 3195 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3196 break;
3197 }
890ca9ae
HY		 3198 case KVM_X86_SETUP_MCE: {
3199 u64 mcg_cap;
3200
3201 r = -EFAULT;
3202 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3203 goto out;
3204 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3205 break;
3206 }
3207 case KVM_X86_SET_MCE: {
3208 struct kvm_x86_mce mce;
3209
3210 r = -EFAULT;
3211 if (copy_from_user(&mce, argp, sizeof mce))
3212 goto out;
3213 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3214 break;
3215 }
3cfc3092
JK		 3216 case KVM_GET_VCPU_EVENTS: {
3217 struct kvm_vcpu_events events;
3218
3219 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3220
3221 r = -EFAULT;
3222 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3223 break;
3224 r = 0;
3225 break;
3226 }
3227 case KVM_SET_VCPU_EVENTS: {
3228 struct kvm_vcpu_events events;
3229
3230 r = -EFAULT;
3231 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3232 break;
3233
3234 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3235 break;
3236 }
a1efbe77
JK		 3237 case KVM_GET_DEBUGREGS: {
3238 struct kvm_debugregs dbgregs;
3239
3240 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3241
3242 r = -EFAULT;
3243 if (copy_to_user(argp, &dbgregs,
3244 sizeof(struct kvm_debugregs)))
3245 break;
3246 r = 0;
3247 break;
3248 }
3249 case KVM_SET_DEBUGREGS: {
3250 struct kvm_debugregs dbgregs;
3251
3252 r = -EFAULT;
3253 if (copy_from_user(&dbgregs, argp,
3254 sizeof(struct kvm_debugregs)))
3255 break;
3256
3257 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3258 break;
3259 }
2d5b5a66 3260 case KVM_GET_XSAVE: {
d1ac91d8 3261 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3262 r = -ENOMEM;
d1ac91d8 3263 if (!u.xsave)
2d5b5a66
SY		 3264 break;
3265
d1ac91d8 3266 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3267
3268 r = -EFAULT;
d1ac91d8 3269 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3270 break;
3271 r = 0;
3272 break;
3273 }
3274 case KVM_SET_XSAVE: {
ff5c2c03 3275 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3276 if (IS_ERR(u.xsave))
3277 return PTR_ERR(u.xsave);
2d5b5a66 3278
d1ac91d8 3279 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3280 break;
3281 }
3282 case KVM_GET_XCRS: {
d1ac91d8 3283 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3284 r = -ENOMEM;
d1ac91d8 3285 if (!u.xcrs)
2d5b5a66
SY		 3286 break;
3287
d1ac91d8 3288 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3289
3290 r = -EFAULT;
d1ac91d8 3291 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3292 sizeof(struct kvm_xcrs)))
3293 break;
3294 r = 0;
3295 break;
3296 }
3297 case KVM_SET_XCRS: {
ff5c2c03 3298 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3299 if (IS_ERR(u.xcrs))
3300 return PTR_ERR(u.xcrs);
2d5b5a66 3301
d1ac91d8 3302 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3303 break;
3304 }
92a1f12d
JR		 3305 case KVM_SET_TSC_KHZ: {
3306 u32 user_tsc_khz;
3307
3308 r = -EINVAL;
92a1f12d
JR		 3309 user_tsc_khz = (u32)arg;
3310
3311 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3312 goto out;
3313
cc578287
ZA		 3314 if (user_tsc_khz == 0)
3315 user_tsc_khz = tsc_khz;
3316
3317 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3318
3319 r = 0;
3320 goto out;
3321 }
3322 case KVM_GET_TSC_KHZ: {
cc578287 3323 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3324 goto out;
3325 }
1c0b28c2
EM		 3326 case KVM_KVMCLOCK_CTRL: {
3327 r = kvm_set_guest_paused(vcpu);
3328 goto out;
3329 }
313a3dc7
CO		 3330 default:
3331 r = -EINVAL;
3332 }
3333out:
d1ac91d8 3334 kfree(u.buffer);
313a3dc7
CO		 3335 return r;
3336}
3337
5b1c1493
CO		 3338int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3339{
3340 return VM_FAULT_SIGBUS;
3341}
3342
1fe779f8
CO		 3343static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3344{
3345 int ret;
3346
3347 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3348 return -EINVAL;
1fe779f8
CO		 3349 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3350 return ret;
3351}
3352
b927a3ce
SY		 3353static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3354 u64 ident_addr)
3355{
3356 kvm->arch.ept_identity_map_addr = ident_addr;
3357 return 0;
3358}
3359
1fe779f8
CO		 3360static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3361 u32 kvm_nr_mmu_pages)
3362{
3363 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3364 return -EINVAL;
3365
79fac95e 3366 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3367
3368 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3369 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3370
79fac95e 3371 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3372 return 0;
3373}
3374
3375static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3376{
39de71ec 3377 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3378}
3379
1fe779f8
CO		 3380static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3381{
3382 int r;
3383
3384 r = 0;
3385 switch (chip->chip_id) {
3386 case KVM_IRQCHIP_PIC_MASTER:
3387 memcpy(&chip->chip.pic,
3388 &pic_irqchip(kvm)->pics[0],
3389 sizeof(struct kvm_pic_state));
3390 break;
3391 case KVM_IRQCHIP_PIC_SLAVE:
3392 memcpy(&chip->chip.pic,
3393 &pic_irqchip(kvm)->pics[1],
3394 sizeof(struct kvm_pic_state));
3395 break;
3396 case KVM_IRQCHIP_IOAPIC:
eba0226b 3397 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3398 break;
3399 default:
3400 r = -EINVAL;
3401 break;
3402 }
3403 return r;
3404}
3405
3406static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3407{
3408 int r;
3409
3410 r = 0;
3411 switch (chip->chip_id) {
3412 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3413 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3414 memcpy(&pic_irqchip(kvm)->pics[0],
3415 &chip->chip.pic,
3416 sizeof(struct kvm_pic_state));
f4f51050 3417 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3418 break;
3419 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3420 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3421 memcpy(&pic_irqchip(kvm)->pics[1],
3422 &chip->chip.pic,
3423 sizeof(struct kvm_pic_state));
f4f51050 3424 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3425 break;
3426 case KVM_IRQCHIP_IOAPIC:
eba0226b 3427 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3428 break;
3429 default:
3430 r = -EINVAL;
3431 break;
3432 }
3433 kvm_pic_update_irq(pic_irqchip(kvm));
3434 return r;
3435}
3436
e0f63cb9
SY		 3437static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3438{
3439 int r = 0;
3440
894a9c55 3441 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3442 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3443 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3444 return r;
3445}
3446
3447static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3448{
3449 int r = 0;
3450
894a9c55 3451 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3452 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3453 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3454 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3455 return r;
3456}
3457
3458static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3459{
3460 int r = 0;
3461
3462 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3463 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3464 sizeof(ps->channels));
3465 ps->flags = kvm->arch.vpit->pit_state.flags;
3466 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3467 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3468 return r;
3469}
3470
3471static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3472{
3473 int r = 0, start = 0;
3474 u32 prev_legacy, cur_legacy;
3475 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3476 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3477 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3478 if (!prev_legacy && cur_legacy)
3479 start = 1;
3480 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3481 sizeof(kvm->arch.vpit->pit_state.channels));
3482 kvm->arch.vpit->pit_state.flags = ps->flags;
3483 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3484 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3485 return r;
3486}
3487
52d939a0
MT		 3488static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3489 struct kvm_reinject_control *control)
3490{
3491 if (!kvm->arch.vpit)
3492 return -ENXIO;
894a9c55 3493 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3494 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3495 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3496 return 0;
3497}
3498
95d4c16c 3499/**
60c34612
TY		 3500 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3501 * @kvm: kvm instance
3502 * @log: slot id and address to which we copy the log
95d4c16c 3503 *
e108ff2f
PB		 3504 * Steps 1-4 below provide general overview of dirty page logging. See
3505 * kvm_get_dirty_log_protect() function description for additional details.
3506 *
3507 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3508 * always flush the TLB (step 4) even if previous step failed and the dirty
3509 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3510 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3511 * writes will be marked dirty for next log read.
95d4c16c 3512 *
60c34612
TY		 3513 * 1. Take a snapshot of the bit and clear it if needed.
3514 * 2. Write protect the corresponding page.
e108ff2f
PB		 3515 * 3. Copy the snapshot to the userspace.
3516 * 4. Flush TLB's if needed.
5bb064dc 3517 */
60c34612 3518int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3519{
60c34612 3520 bool is_dirty = false;
e108ff2f 3521 int r;
5bb064dc 3522
79fac95e 3523 mutex_lock(&kvm->slots_lock);
5bb064dc 3524
88178fd4
KH		 3525 /*
3526 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3527 */
3528 if (kvm_x86_ops->flush_log_dirty)
3529 kvm_x86_ops->flush_log_dirty(kvm);
3530
e108ff2f 3531 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3532
3533 /*
3534 * All the TLBs can be flushed out of mmu lock, see the comments in
3535 * kvm_mmu_slot_remove_write_access().
3536 */
e108ff2f 3537 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3538 if (is_dirty)
3539 kvm_flush_remote_tlbs(kvm);
3540
79fac95e 3541 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3542 return r;
3543}
3544
aa2fbe6d
YZ		 3545int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3546 bool line_status)
23d43cf9
CD		 3547{
3548 if (!irqchip_in_kernel(kvm))
3549 return -ENXIO;
3550
3551 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3552 irq_event->irq, irq_event->level,
3553 line_status);
23d43cf9
CD		 3554 return 0;
3555}
3556
90de4a18
NA		 3557static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3558 struct kvm_enable_cap *cap)
3559{
3560 int r;
3561
3562 if (cap->flags)
3563 return -EINVAL;
3564
3565 switch (cap->cap) {
3566 case KVM_CAP_DISABLE_QUIRKS:
3567 kvm->arch.disabled_quirks = cap->args[0];
3568 r = 0;
3569 break;
3570 default:
3571 r = -EINVAL;
3572 break;
3573 }
3574 return r;
3575}
3576
1fe779f8
CO		 3577long kvm_arch_vm_ioctl(struct file *filp,
3578 unsigned int ioctl, unsigned long arg)
3579{
3580 struct kvm *kvm = filp->private_data;
3581 void __user *argp = (void __user *)arg;
367e1319 3582 int r = -ENOTTY;
f0d66275
DH		 3583 /*
3584 * This union makes it completely explicit to gcc-3.x
3585 * that these two variables' stack usage should be
3586 * combined, not added together.
3587 */
3588 union {
3589 struct kvm_pit_state ps;
e9f42757 3590 struct kvm_pit_state2 ps2;
c5ff41ce 3591 struct kvm_pit_config pit_config;
f0d66275 3592 } u;
1fe779f8
CO		 3593
3594 switch (ioctl) {
3595 case KVM_SET_TSS_ADDR:
3596 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3597 break;
b927a3ce
SY		 3598 case KVM_SET_IDENTITY_MAP_ADDR: {
3599 u64 ident_addr;
3600
3601 r = -EFAULT;
3602 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3603 goto out;
3604 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3605 break;
3606 }
1fe779f8
CO		 3607 case KVM_SET_NR_MMU_PAGES:
3608 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3609 break;
3610 case KVM_GET_NR_MMU_PAGES:
3611 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3612 break;
3ddea128
MT		 3613 case KVM_CREATE_IRQCHIP: {
3614 struct kvm_pic *vpic;
3615
3616 mutex_lock(&kvm->lock);
3617 r = -EEXIST;
3618 if (kvm->arch.vpic)
3619 goto create_irqchip_unlock;
3e515705
AK		 3620 r = -EINVAL;
3621 if (atomic_read(&kvm->online_vcpus))
3622 goto create_irqchip_unlock;
1fe779f8 3623 r = -ENOMEM;
3ddea128
MT		 3624 vpic = kvm_create_pic(kvm);
3625 if (vpic) {
1fe779f8
CO		 3626 r = kvm_ioapic_init(kvm);
3627 if (r) {
175504cd 3628 mutex_lock(&kvm->slots_lock);
71ba994c 3629 kvm_destroy_pic(vpic);
175504cd 3630 mutex_unlock(&kvm->slots_lock);
3ddea128 3631 goto create_irqchip_unlock;
1fe779f8
CO		 3632 }
3633 } else
3ddea128 3634 goto create_irqchip_unlock;
399ec807
AK		 3635 r = kvm_setup_default_irq_routing(kvm);
3636 if (r) {
175504cd 3637 mutex_lock(&kvm->slots_lock);
3ddea128 3638 mutex_lock(&kvm->irq_lock);
72bb2fcd 3639 kvm_ioapic_destroy(kvm);
71ba994c 3640 kvm_destroy_pic(vpic);
3ddea128 3641 mutex_unlock(&kvm->irq_lock);
175504cd 3642 mutex_unlock(&kvm->slots_lock);
71ba994c 3643 goto create_irqchip_unlock;
399ec807 3644 }
71ba994c
PB		 3645 /* Write kvm->irq_routing before kvm->arch.vpic. */
3646 smp_wmb();
3647 kvm->arch.vpic = vpic;
3ddea128
MT		 3648 create_irqchip_unlock:
3649 mutex_unlock(&kvm->lock);
1fe779f8 3650 break;
3ddea128 3651 }
7837699f 3652 case KVM_CREATE_PIT:
c5ff41ce
JK		 3653 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3654 goto create_pit;
3655 case KVM_CREATE_PIT2:
3656 r = -EFAULT;
3657 if (copy_from_user(&u.pit_config, argp,
3658 sizeof(struct kvm_pit_config)))
3659 goto out;
3660 create_pit:
79fac95e 3661 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3662 r = -EEXIST;
3663 if (kvm->arch.vpit)
3664 goto create_pit_unlock;
7837699f 3665 r = -ENOMEM;
c5ff41ce 3666 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3667 if (kvm->arch.vpit)
3668 r = 0;
269e05e4 3669 create_pit_unlock:
79fac95e 3670 mutex_unlock(&kvm->slots_lock);
7837699f 3671 break;
1fe779f8
CO		 3672 case KVM_GET_IRQCHIP: {
3673 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3674 struct kvm_irqchip *chip;
1fe779f8 3675
ff5c2c03
SL		 3676 chip = memdup_user(argp, sizeof(*chip));
3677 if (IS_ERR(chip)) {
3678 r = PTR_ERR(chip);
1fe779f8 3679 goto out;
ff5c2c03
SL		 3680 }
3681
1fe779f8
CO		 3682 r = -ENXIO;
3683 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3684 goto get_irqchip_out;
3685 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3686 if (r)
f0d66275 3687 goto get_irqchip_out;
1fe779f8 3688 r = -EFAULT;
f0d66275
DH		 3689 if (copy_to_user(argp, chip, sizeof *chip))
3690 goto get_irqchip_out;
1fe779f8 3691 r = 0;
f0d66275
DH		 3692 get_irqchip_out:
3693 kfree(chip);
1fe779f8
CO		 3694 break;
3695 }
3696 case KVM_SET_IRQCHIP: {
3697 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3698 struct kvm_irqchip *chip;
1fe779f8 3699
ff5c2c03
SL		 3700 chip = memdup_user(argp, sizeof(*chip));
3701 if (IS_ERR(chip)) {
3702 r = PTR_ERR(chip);
1fe779f8 3703 goto out;
ff5c2c03
SL		 3704 }
3705
1fe779f8
CO		 3706 r = -ENXIO;
3707 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3708 goto set_irqchip_out;
3709 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3710 if (r)
f0d66275 3711 goto set_irqchip_out;
1fe779f8 3712 r = 0;
f0d66275
DH		 3713 set_irqchip_out:
3714 kfree(chip);
1fe779f8
CO		 3715 break;
3716 }
e0f63cb9 3717 case KVM_GET_PIT: {
e0f63cb9 3718 r = -EFAULT;
f0d66275 3719 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3720 goto out;
3721 r = -ENXIO;
3722 if (!kvm->arch.vpit)
3723 goto out;
f0d66275 3724 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3725 if (r)
3726 goto out;
3727 r = -EFAULT;
f0d66275 3728 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3729 goto out;
3730 r = 0;
3731 break;
3732 }
3733 case KVM_SET_PIT: {
e0f63cb9 3734 r = -EFAULT;
f0d66275 3735 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3736 goto out;
3737 r = -ENXIO;
3738 if (!kvm->arch.vpit)
3739 goto out;
f0d66275 3740 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3741 break;
3742 }
e9f42757
BK		 3743 case KVM_GET_PIT2: {
3744 r = -ENXIO;
3745 if (!kvm->arch.vpit)
3746 goto out;
3747 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3748 if (r)
3749 goto out;
3750 r = -EFAULT;
3751 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3752 goto out;
3753 r = 0;
3754 break;
3755 }
3756 case KVM_SET_PIT2: {
3757 r = -EFAULT;
3758 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3759 goto out;
3760 r = -ENXIO;
3761 if (!kvm->arch.vpit)
3762 goto out;
3763 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3764 break;
3765 }
52d939a0
MT		 3766 case KVM_REINJECT_CONTROL: {
3767 struct kvm_reinject_control control;
3768 r = -EFAULT;
3769 if (copy_from_user(&control, argp, sizeof(control)))
3770 goto out;
3771 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3772 break;
3773 }
d71ba788
PB		 3774 case KVM_SET_BOOT_CPU_ID:
3775 r = 0;
3776 mutex_lock(&kvm->lock);
3777 if (atomic_read(&kvm->online_vcpus) != 0)
3778 r = -EBUSY;
3779 else
3780 kvm->arch.bsp_vcpu_id = arg;
3781 mutex_unlock(&kvm->lock);
3782 break;
ffde22ac
ES		 3783 case KVM_XEN_HVM_CONFIG: {
3784 r = -EFAULT;
3785 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3786 sizeof(struct kvm_xen_hvm_config)))
3787 goto out;
3788 r = -EINVAL;
3789 if (kvm->arch.xen_hvm_config.flags)
3790 goto out;
3791 r = 0;
3792 break;
3793 }
afbcf7ab 3794 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3795 struct kvm_clock_data user_ns;
3796 u64 now_ns;
3797 s64 delta;
3798
3799 r = -EFAULT;
3800 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3801 goto out;
3802
3803 r = -EINVAL;
3804 if (user_ns.flags)
3805 goto out;
3806
3807 r = 0;
395c6b0a 3808 local_irq_disable();
759379dd 3809 now_ns = get_kernel_ns();
afbcf7ab 3810 delta = user_ns.clock - now_ns;
395c6b0a 3811 local_irq_enable();
afbcf7ab 3812 kvm->arch.kvmclock_offset = delta;
2e762ff7 3813 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3814 break;
3815 }
3816 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3817 struct kvm_clock_data user_ns;
3818 u64 now_ns;
3819
395c6b0a 3820 local_irq_disable();
759379dd 3821 now_ns = get_kernel_ns();
afbcf7ab 3822 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3823 local_irq_enable();
afbcf7ab 3824 user_ns.flags = 0;
97e69aa6 3825 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3826
3827 r = -EFAULT;
3828 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3829 goto out;
3830 r = 0;
3831 break;
3832 }
90de4a18
NA		 3833 case KVM_ENABLE_CAP: {
3834 struct kvm_enable_cap cap;
afbcf7ab 3835
90de4a18
NA		 3836 r = -EFAULT;
3837 if (copy_from_user(&cap, argp, sizeof(cap)))
3838 goto out;
3839 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3840 break;
3841 }
1fe779f8 3842 default:
c274e03a 3843 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3844 }
3845out:
3846 return r;
3847}
3848
a16b043c 3849static void kvm_init_msr_list(void)
043405e1
CO		 3850{
3851 u32 dummy[2];
3852 unsigned i, j;
3853
62ef68bb 3854 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3855 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3856 continue;
93c4adc7
PB		 3857
3858 /*
3859 * Even MSRs that are valid in the host may not be exposed
3860 * to the guests in some cases. We could work around this
3861 * in VMX with the generic MSR save/load machinery, but it
3862 * is not really worthwhile since it will really only
3863 * happen with nested virtualization.
3864 */
3865 switch (msrs_to_save[i]) {
3866 case MSR_IA32_BNDCFGS:
3867 if (!kvm_x86_ops->mpx_supported())
3868 continue;
3869 break;
3870 default:
3871 break;
3872 }
3873
043405e1
CO		 3874 if (j < i)
3875 msrs_to_save[j] = msrs_to_save[i];
3876 j++;
3877 }
3878 num_msrs_to_save = j;
62ef68bb
PB		 3879
3880 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3881 switch (emulated_msrs[i]) {
6d396b55
PB		 3882 case MSR_IA32_SMBASE:
3883 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3884 continue;
3885 break;
62ef68bb
PB		 3886 default:
3887 break;
3888 }
3889
3890 if (j < i)
3891 emulated_msrs[j] = emulated_msrs[i];
3892 j++;
3893 }
3894 num_emulated_msrs = j;
043405e1
CO		 3895}
3896
bda9020e
MT		 3897static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3898 const void *v)
bbd9b64e 3899{
70252a10
AK		 3900 int handled = 0;
3901 int n;
3902
3903 do {
3904 n = min(len, 8);
3905 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3906 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3907 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3908 break;
3909 handled += n;
3910 addr += n;
3911 len -= n;
3912 v += n;
3913 } while (len);
bbd9b64e 3914
70252a10 3915 return handled;
bbd9b64e
CO		 3916}
3917
bda9020e 3918static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3919{
70252a10
AK		 3920 int handled = 0;
3921 int n;
3922
3923 do {
3924 n = min(len, 8);
3925 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3926 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3927 addr, n, v))
3928 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3929 break;
3930 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3931 handled += n;
3932 addr += n;
3933 len -= n;
3934 v += n;
3935 } while (len);
bbd9b64e 3936
70252a10 3937 return handled;
bbd9b64e
CO		 3938}
3939
2dafc6c2
GN		 3940static void kvm_set_segment(struct kvm_vcpu *vcpu,
3941 struct kvm_segment *var, int seg)
3942{
3943 kvm_x86_ops->set_segment(vcpu, var, seg);
3944}
3945
3946void kvm_get_segment(struct kvm_vcpu *vcpu,
3947 struct kvm_segment *var, int seg)
3948{
3949 kvm_x86_ops->get_segment(vcpu, var, seg);
3950}
3951
54987b7a
PB		 3952gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3953 struct x86_exception *exception)
02f59dc9
JR		 3954{
3955 gpa_t t_gpa;
02f59dc9
JR		 3956
3957 BUG_ON(!mmu_is_nested(vcpu));
3958
3959 /* NPT walks are always user-walks */
3960 access |= PFERR_USER_MASK;
54987b7a 3961 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3962
3963 return t_gpa;
3964}
3965
ab9ae313
AK		 3966gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3967 struct x86_exception *exception)
1871c602
GN		 3968{
3969 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3970 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3971}
3972
ab9ae313
AK		 3973 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3974 struct x86_exception *exception)
1871c602
GN		 3975{
3976 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3977 access |= PFERR_FETCH_MASK;
ab9ae313 3978 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3979}
3980
ab9ae313
AK		 3981gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3982 struct x86_exception *exception)
1871c602
GN		 3983{
3984 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3985 access |= PFERR_WRITE_MASK;
ab9ae313 3986 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3987}
3988
3989/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3990gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3991 struct x86_exception *exception)
1871c602 3992{
ab9ae313 3993 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3994}
3995
3996static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3997 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3998 struct x86_exception *exception)
bbd9b64e
CO		 3999{
4000 void *data = val;
10589a46 4001 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4002
4003 while (bytes) {
14dfe855 4004 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4005 exception);
bbd9b64e 4006 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4007 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4008 int ret;
4009
bcc55cba 4010 if (gpa == UNMAPPED_GVA)
ab9ae313 4011 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4012 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4013 offset, toread);
10589a46 4014 if (ret < 0) {
c3cd7ffa 4015 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4016 goto out;
4017 }
bbd9b64e 4018
77c2002e
IE		 4019 bytes -= toread;
4020 data += toread;
4021 addr += toread;
bbd9b64e 4022 }
10589a46 4023out:
10589a46 4024 return r;
bbd9b64e 4025}
77c2002e 4026
1871c602 4027/* used for instruction fetching */
0f65dd70
AK		 4028static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4029 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4030 struct x86_exception *exception)
1871c602 4031{
0f65dd70 4032 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4033 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4034 unsigned offset;
4035 int ret;
0f65dd70 4036
44583cba
PB		 4037 /* Inline kvm_read_guest_virt_helper for speed. */
4038 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4039 exception);
4040 if (unlikely(gpa == UNMAPPED_GVA))
4041 return X86EMUL_PROPAGATE_FAULT;
4042
4043 offset = addr & (PAGE_SIZE-1);
4044 if (WARN_ON(offset + bytes > PAGE_SIZE))
4045 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4046 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4047 offset, bytes);
44583cba
PB		 4048 if (unlikely(ret < 0))
4049 return X86EMUL_IO_NEEDED;
4050
4051 return X86EMUL_CONTINUE;
1871c602
GN		 4052}
4053
064aea77 4054int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4055 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4056 struct x86_exception *exception)
1871c602 4057{
0f65dd70 4058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4059 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4060
1871c602 4061 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4062 exception);
1871c602 4063}
064aea77 4064EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4065
0f65dd70
AK		 4066static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4067 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4068 struct x86_exception *exception)
1871c602 4069{
0f65dd70 4070 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4071 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4072}
4073
6a4d7550 4074int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4075 gva_t addr, void *val,
2dafc6c2 4076 unsigned int bytes,
bcc55cba 4077 struct x86_exception *exception)
77c2002e 4078{
0f65dd70 4079 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4080 void *data = val;
4081 int r = X86EMUL_CONTINUE;
4082
4083 while (bytes) {
14dfe855
JR		 4084 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4085 PFERR_WRITE_MASK,
ab9ae313 4086 exception);
77c2002e
IE		 4087 unsigned offset = addr & (PAGE_SIZE-1);
4088 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4089 int ret;
4090
bcc55cba 4091 if (gpa == UNMAPPED_GVA)
ab9ae313 4092 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4093 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4094 if (ret < 0) {
c3cd7ffa 4095 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4096 goto out;
4097 }
4098
4099 bytes -= towrite;
4100 data += towrite;
4101 addr += towrite;
4102 }
4103out:
4104 return r;
4105}
6a4d7550 4106EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4107
af7cc7d1
XG		 4108static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4109 gpa_t *gpa, struct x86_exception *exception,
4110 bool write)
4111{
97d64b78
AK		 4112 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4113 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4114
97d64b78 4115 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4116 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4117 vcpu->arch.access, access)) {
bebb106a
XG		 4118 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4119 (gva & (PAGE_SIZE - 1));
4f022648 4120 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4121 return 1;
4122 }
4123
af7cc7d1
XG		 4124 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4125
4126 if (*gpa == UNMAPPED_GVA)
4127 return -1;
4128
4129 /* For APIC access vmexit */
4130 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4131 return 1;
4132
4f022648
XG		 4133 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4134 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4135 return 1;
4f022648 4136 }
bebb106a 4137
af7cc7d1
XG		 4138 return 0;
4139}
4140
3200f405 4141int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4142 const void *val, int bytes)
bbd9b64e
CO		 4143{
4144 int ret;
4145
54bf36aa 4146 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4147 if (ret < 0)
bbd9b64e 4148 return 0;
f57f2ef5 4149 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4150 return 1;
4151}
4152
77d197b2
XG		 4153struct read_write_emulator_ops {
4154 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4155 int bytes);
4156 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4157 void *val, int bytes);
4158 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4159 int bytes, void *val);
4160 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4161 void *val, int bytes);
4162 bool write;
4163};
4164
4165static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4166{
4167 if (vcpu->mmio_read_completed) {
77d197b2 4168 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4169 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4170 vcpu->mmio_read_completed = 0;
4171 return 1;
4172 }
4173
4174 return 0;
4175}
4176
4177static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4178 void *val, int bytes)
4179{
54bf36aa 4180 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4181}
4182
4183static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4184 void *val, int bytes)
4185{
4186 return emulator_write_phys(vcpu, gpa, val, bytes);
4187}
4188
4189static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4190{
4191 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4192 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4193}
4194
4195static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4196 void *val, int bytes)
4197{
4198 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4199 return X86EMUL_IO_NEEDED;
4200}
4201
4202static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4203 void *val, int bytes)
4204{
f78146b0
AK		 4205 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4206
87da7e66 4207 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4208 return X86EMUL_CONTINUE;
4209}
4210
0fbe9b0b 4211static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4212 .read_write_prepare = read_prepare,
4213 .read_write_emulate = read_emulate,
4214 .read_write_mmio = vcpu_mmio_read,
4215 .read_write_exit_mmio = read_exit_mmio,
4216};
4217
0fbe9b0b 4218static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4219 .read_write_emulate = write_emulate,
4220 .read_write_mmio = write_mmio,
4221 .read_write_exit_mmio = write_exit_mmio,
4222 .write = true,
4223};
4224
22388a3c
XG		 4225static int emulator_read_write_onepage(unsigned long addr, void *val,
4226 unsigned int bytes,
4227 struct x86_exception *exception,
4228 struct kvm_vcpu *vcpu,
0fbe9b0b 4229 const struct read_write_emulator_ops *ops)
bbd9b64e 4230{
af7cc7d1
XG		 4231 gpa_t gpa;
4232 int handled, ret;
22388a3c 4233 bool write = ops->write;
f78146b0 4234 struct kvm_mmio_fragment *frag;
10589a46 4235
22388a3c 4236 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4237
af7cc7d1 4238 if (ret < 0)
bbd9b64e 4239 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4240
4241 /* For APIC access vmexit */
af7cc7d1 4242 if (ret)
bbd9b64e
CO		 4243 goto mmio;
4244
22388a3c 4245 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4246 return X86EMUL_CONTINUE;
4247
4248mmio:
4249 /*
4250 * Is this MMIO handled locally?
4251 */
22388a3c 4252 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4253 if (handled == bytes)
bbd9b64e 4254 return X86EMUL_CONTINUE;
bbd9b64e 4255
70252a10
AK		 4256 gpa += handled;
4257 bytes -= handled;
4258 val += handled;
4259
87da7e66
XG		 4260 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4261 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4262 frag->gpa = gpa;
4263 frag->data = val;
4264 frag->len = bytes;
f78146b0 4265 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4266}
4267
52eb5a6d
XL		 4268static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4269 unsigned long addr,
22388a3c
XG		 4270 void *val, unsigned int bytes,
4271 struct x86_exception *exception,
0fbe9b0b 4272 const struct read_write_emulator_ops *ops)
bbd9b64e 4273{
0f65dd70 4274 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4275 gpa_t gpa;
4276 int rc;
4277
4278 if (ops->read_write_prepare &&
4279 ops->read_write_prepare(vcpu, val, bytes))
4280 return X86EMUL_CONTINUE;
4281
4282 vcpu->mmio_nr_fragments = 0;
0f65dd70 4283
bbd9b64e
CO		 4284 /* Crossing a page boundary? */
4285 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4286 int now;
bbd9b64e
CO		 4287
4288 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4289 rc = emulator_read_write_onepage(addr, val, now, exception,
4290 vcpu, ops);
4291
bbd9b64e
CO		 4292 if (rc != X86EMUL_CONTINUE)
4293 return rc;
4294 addr += now;
bac15531
NA		 4295 if (ctxt->mode != X86EMUL_MODE_PROT64)
4296 addr = (u32)addr;
bbd9b64e
CO		 4297 val += now;
4298 bytes -= now;
4299 }
22388a3c 4300
f78146b0
AK		 4301 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4302 vcpu, ops);
4303 if (rc != X86EMUL_CONTINUE)
4304 return rc;
4305
4306 if (!vcpu->mmio_nr_fragments)
4307 return rc;
4308
4309 gpa = vcpu->mmio_fragments[0].gpa;
4310
4311 vcpu->mmio_needed = 1;
4312 vcpu->mmio_cur_fragment = 0;
4313
87da7e66 4314 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4315 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4316 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4317 vcpu->run->mmio.phys_addr = gpa;
4318
4319 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4320}
4321
4322static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4323 unsigned long addr,
4324 void *val,
4325 unsigned int bytes,
4326 struct x86_exception *exception)
4327{
4328 return emulator_read_write(ctxt, addr, val, bytes,
4329 exception, &read_emultor);
4330}
4331
52eb5a6d 4332static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4333 unsigned long addr,
4334 const void *val,
4335 unsigned int bytes,
4336 struct x86_exception *exception)
4337{
4338 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4339 exception, &write_emultor);
bbd9b64e 4340}
bbd9b64e 4341
daea3e73
AK		 4342#define CMPXCHG_TYPE(t, ptr, old, new) \
4343 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4344
4345#ifdef CONFIG_X86_64
4346# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4347#else
4348# define CMPXCHG64(ptr, old, new) \
9749a6c0 4349 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4350#endif
4351
0f65dd70
AK		 4352static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4353 unsigned long addr,
bbd9b64e
CO		 4354 const void *old,
4355 const void *new,
4356 unsigned int bytes,
0f65dd70 4357 struct x86_exception *exception)
bbd9b64e 4358{
0f65dd70 4359 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4360 gpa_t gpa;
4361 struct page *page;
4362 char *kaddr;
4363 bool exchanged;
2bacc55c 4364
daea3e73
AK		 4365 /* guests cmpxchg8b have to be emulated atomically */
4366 if (bytes > 8 || (bytes & (bytes - 1)))
4367 goto emul_write;
10589a46 4368
daea3e73 4369 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4370
daea3e73
AK		 4371 if (gpa == UNMAPPED_GVA ||
4372 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4373 goto emul_write;
2bacc55c 4374
daea3e73
AK		 4375 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4376 goto emul_write;
72dc67a6 4377
54bf36aa 4378 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4379 if (is_error_page(page))
c19b8bd6 4380 goto emul_write;
72dc67a6 4381
8fd75e12 4382 kaddr = kmap_atomic(page);
daea3e73
AK		 4383 kaddr += offset_in_page(gpa);
4384 switch (bytes) {
4385 case 1:
4386 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4387 break;
4388 case 2:
4389 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4390 break;
4391 case 4:
4392 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4393 break;
4394 case 8:
4395 exchanged = CMPXCHG64(kaddr, old, new);
4396 break;
4397 default:
4398 BUG();
2bacc55c 4399 }
8fd75e12 4400 kunmap_atomic(kaddr);
daea3e73
AK		 4401 kvm_release_page_dirty(page);
4402
4403 if (!exchanged)
4404 return X86EMUL_CMPXCHG_FAILED;
4405
54bf36aa 4406 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4407 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4408
4409 return X86EMUL_CONTINUE;
4a5f48f6 4410
3200f405 4411emul_write:
daea3e73 4412 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4413
0f65dd70 4414 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4415}
4416
cf8f70bf
GN		 4417static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4418{
4419 /* TODO: String I/O for in kernel device */
4420 int r;
4421
4422 if (vcpu->arch.pio.in)
e32edf4f 4423 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4424 vcpu->arch.pio.size, pd);
4425 else
e32edf4f 4426 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4427 vcpu->arch.pio.port, vcpu->arch.pio.size,
4428 pd);
4429 return r;
4430}
4431
6f6fbe98
XG		 4432static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4433 unsigned short port, void *val,
4434 unsigned int count, bool in)
cf8f70bf 4435{
cf8f70bf 4436 vcpu->arch.pio.port = port;
6f6fbe98 4437 vcpu->arch.pio.in = in;
7972995b 4438 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4439 vcpu->arch.pio.size = size;
4440
4441 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4442 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4443 return 1;
4444 }
4445
4446 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4447 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4448 vcpu->run->io.size = size;
4449 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4450 vcpu->run->io.count = count;
4451 vcpu->run->io.port = port;
4452
4453 return 0;
4454}
4455
6f6fbe98
XG		 4456static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4457 int size, unsigned short port, void *val,
4458 unsigned int count)
cf8f70bf 4459{
ca1d4a9e 4460 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4461 int ret;
ca1d4a9e 4462
6f6fbe98
XG		 4463 if (vcpu->arch.pio.count)
4464 goto data_avail;
cf8f70bf 4465
6f6fbe98
XG		 4466 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4467 if (ret) {
4468data_avail:
4469 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4470 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4471 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4472 return 1;
4473 }
4474
cf8f70bf
GN		 4475 return 0;
4476}
4477
6f6fbe98
XG		 4478static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4479 int size, unsigned short port,
4480 const void *val, unsigned int count)
4481{
4482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4483
4484 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4485 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4486 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4487}
4488
bbd9b64e
CO		 4489static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4490{
4491 return kvm_x86_ops->get_segment_base(vcpu, seg);
4492}
4493
3cb16fe7 4494static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4495{
3cb16fe7 4496 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4497}
4498
5cb56059 4499int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4500{
4501 if (!need_emulate_wbinvd(vcpu))
4502 return X86EMUL_CONTINUE;
4503
4504 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4505 int cpu = get_cpu();
4506
4507 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4508 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4509 wbinvd_ipi, NULL, 1);
2eec7343 4510 put_cpu();
f5f48ee1 4511 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4512 } else
4513 wbinvd();
f5f48ee1
SY		 4514 return X86EMUL_CONTINUE;
4515}
5cb56059
JS		 4516
4517int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4518{
4519 kvm_x86_ops->skip_emulated_instruction(vcpu);
4520 return kvm_emulate_wbinvd_noskip(vcpu);
4521}
f5f48ee1
SY		 4522EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4523
5cb56059
JS		 4524
4525
bcaf5cc5
AK		 4526static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4527{
5cb56059 4528 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4529}
4530
52eb5a6d
XL		 4531static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4532 unsigned long *dest)
bbd9b64e 4533{
16f8a6f9 4534 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4535}
4536
52eb5a6d
XL		 4537static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4538 unsigned long value)
bbd9b64e 4539{
338dbc97 4540
717746e3 4541 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4542}
4543
52a46617 4544static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4545{
52a46617 4546 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4547}
4548
717746e3 4549static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4550{
717746e3 4551 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4552 unsigned long value;
4553
4554 switch (cr) {
4555 case 0:
4556 value = kvm_read_cr0(vcpu);
4557 break;
4558 case 2:
4559 value = vcpu->arch.cr2;
4560 break;
4561 case 3:
9f8fe504 4562 value = kvm_read_cr3(vcpu);
52a46617
GN		 4563 break;
4564 case 4:
4565 value = kvm_read_cr4(vcpu);
4566 break;
4567 case 8:
4568 value = kvm_get_cr8(vcpu);
4569 break;
4570 default:
a737f256 4571 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4572 return 0;
4573 }
4574
4575 return value;
4576}
4577
717746e3 4578static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4579{
717746e3 4580 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4581 int res = 0;
4582
52a46617
GN		 4583 switch (cr) {
4584 case 0:
49a9b07e 4585 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4586 break;
4587 case 2:
4588 vcpu->arch.cr2 = val;
4589 break;
4590 case 3:
2390218b 4591 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4592 break;
4593 case 4:
a83b29c6 4594 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4595 break;
4596 case 8:
eea1cff9 4597 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4598 break;
4599 default:
a737f256 4600 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4601 res = -1;
52a46617 4602 }
0f12244f
GN		 4603
4604 return res;
52a46617
GN		 4605}
4606
717746e3 4607static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4608{
717746e3 4609 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4610}
4611
4bff1e86 4612static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4613{
4bff1e86 4614 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4615}
4616
4bff1e86 4617static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4618{
4bff1e86 4619 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4620}
4621
1ac9d0cf
AK		 4622static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4623{
4624 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4625}
4626
4627static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4628{
4629 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4630}
4631
4bff1e86
AK		 4632static unsigned long emulator_get_cached_segment_base(
4633 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4634{
4bff1e86 4635 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4636}
4637
1aa36616
AK		 4638static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4639 struct desc_struct *desc, u32 *base3,
4640 int seg)
2dafc6c2
GN		 4641{
4642 struct kvm_segment var;
4643
4bff1e86 4644 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4645 *selector = var.selector;
2dafc6c2 4646
378a8b09
GN		 4647 if (var.unusable) {
4648 memset(desc, 0, sizeof(*desc));
2dafc6c2 4649 return false;
378a8b09 4650 }
2dafc6c2
GN		 4651
4652 if (var.g)
4653 var.limit >>= 12;
4654 set_desc_limit(desc, var.limit);
4655 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4656#ifdef CONFIG_X86_64
4657 if (base3)
4658 *base3 = var.base >> 32;
4659#endif
2dafc6c2
GN		 4660 desc->type = var.type;
4661 desc->s = var.s;
4662 desc->dpl = var.dpl;
4663 desc->p = var.present;
4664 desc->avl = var.avl;
4665 desc->l = var.l;
4666 desc->d = var.db;
4667 desc->g = var.g;
4668
4669 return true;
4670}
4671
1aa36616
AK		 4672static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4673 struct desc_struct *desc, u32 base3,
4674 int seg)
2dafc6c2 4675{
4bff1e86 4676 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4677 struct kvm_segment var;
4678
1aa36616 4679 var.selector = selector;
2dafc6c2 4680 var.base = get_desc_base(desc);
5601d05b
GN		 4681#ifdef CONFIG_X86_64
4682 var.base |= ((u64)base3) << 32;
4683#endif
2dafc6c2
GN		 4684 var.limit = get_desc_limit(desc);
4685 if (desc->g)
4686 var.limit = (var.limit << 12) | 0xfff;
4687 var.type = desc->type;
2dafc6c2
GN		 4688 var.dpl = desc->dpl;
4689 var.db = desc->d;
4690 var.s = desc->s;
4691 var.l = desc->l;
4692 var.g = desc->g;
4693 var.avl = desc->avl;
4694 var.present = desc->p;
4695 var.unusable = !var.present;
4696 var.padding = 0;
4697
4698 kvm_set_segment(vcpu, &var, seg);
4699 return;
4700}
4701
717746e3
AK		 4702static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4703 u32 msr_index, u64 *pdata)
4704{
609e36d3
PB		 4705 struct msr_data msr;
4706 int r;
4707
4708 msr.index = msr_index;
4709 msr.host_initiated = false;
4710 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4711 if (r)
4712 return r;
4713
4714 *pdata = msr.data;
4715 return 0;
717746e3
AK		 4716}
4717
4718static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4719 u32 msr_index, u64 data)
4720{
8fe8ab46
WA		 4721 struct msr_data msr;
4722
4723 msr.data = data;
4724 msr.index = msr_index;
4725 msr.host_initiated = false;
4726 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4727}
4728
64d60670
PB		 4729static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4730{
4731 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4732
4733 return vcpu->arch.smbase;
4734}
4735
4736static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4737{
4738 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4739
4740 vcpu->arch.smbase = smbase;
4741}
4742
67f4d428
NA		 4743static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4744 u32 pmc)
4745{
c6702c9d 4746 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4747}
4748
222d21aa
AK		 4749static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4750 u32 pmc, u64 *pdata)
4751{
c6702c9d 4752 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4753}
4754
6c3287f7
AK		 4755static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4756{
4757 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4758}
4759
5037f6f3
AK		 4760static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4761{
4762 preempt_disable();
5197b808 4763 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4764 /*
4765 * CR0.TS may reference the host fpu state, not the guest fpu state,
4766 * so it may be clear at this point.
4767 */
4768 clts();
4769}
4770
4771static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4772{
4773 preempt_enable();
4774}
4775
2953538e 4776static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4777 struct x86_instruction_info *info,
c4f035c6
AK		 4778 enum x86_intercept_stage stage)
4779{
2953538e 4780 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4781}
4782
0017f93a 4783static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4784 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4785{
0017f93a 4786 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4787}
4788
dd856efa
AK		 4789static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4790{
4791 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4792}
4793
4794static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4795{
4796 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4797}
4798
801806d9
NA		 4799static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4800{
4801 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4802}
4803
0225fb50 4804static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4805 .read_gpr = emulator_read_gpr,
4806 .write_gpr = emulator_write_gpr,
1871c602 4807 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4808 .write_std = kvm_write_guest_virt_system,
1871c602 4809 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4810 .read_emulated = emulator_read_emulated,
4811 .write_emulated = emulator_write_emulated,
4812 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4813 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4814 .pio_in_emulated = emulator_pio_in_emulated,
4815 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4816 .get_segment = emulator_get_segment,
4817 .set_segment = emulator_set_segment,
5951c442 4818 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4819 .get_gdt = emulator_get_gdt,
160ce1f1 4820 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4821 .set_gdt = emulator_set_gdt,
4822 .set_idt = emulator_set_idt,
52a46617
GN		 4823 .get_cr = emulator_get_cr,
4824 .set_cr = emulator_set_cr,
9c537244 4825 .cpl = emulator_get_cpl,
35aa5375
GN		 4826 .get_dr = emulator_get_dr,
4827 .set_dr = emulator_set_dr,
64d60670
PB		 4828 .get_smbase = emulator_get_smbase,
4829 .set_smbase = emulator_set_smbase,
717746e3
AK		 4830 .set_msr = emulator_set_msr,
4831 .get_msr = emulator_get_msr,
67f4d428 4832 .check_pmc = emulator_check_pmc,
222d21aa 4833 .read_pmc = emulator_read_pmc,
6c3287f7 4834 .halt = emulator_halt,
bcaf5cc5 4835 .wbinvd = emulator_wbinvd,
d6aa1000 4836 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4837 .get_fpu = emulator_get_fpu,
4838 .put_fpu = emulator_put_fpu,
c4f035c6 4839 .intercept = emulator_intercept,
bdb42f5a 4840 .get_cpuid = emulator_get_cpuid,
801806d9 4841 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4842};
4843
95cb2295
GN		 4844static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4845{
37ccdcbe 4846 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4847 /*
4848 * an sti; sti; sequence only disable interrupts for the first
4849 * instruction. So, if the last instruction, be it emulated or
4850 * not, left the system with the INT_STI flag enabled, it
4851 * means that the last instruction is an sti. We should not
4852 * leave the flag on in this case. The same goes for mov ss
4853 */
37ccdcbe
PB		 4854 if (int_shadow & mask)
4855 mask = 0;
6addfc42 4856 if (unlikely(int_shadow || mask)) {
95cb2295 4857 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4858 if (!mask)
4859 kvm_make_request(KVM_REQ_EVENT, vcpu);
4860 }
95cb2295
GN		 4861}
4862
ef54bcfe 4863static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4864{
4865 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4866 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4867 return kvm_propagate_fault(vcpu, &ctxt->exception);
4868
4869 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4870 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4871 ctxt->exception.error_code);
54b8486f 4872 else
da9cb575 4873 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4874 return false;
54b8486f
GN		 4875}
4876
8ec4722d
MG		 4877static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4878{
adf52235 4879 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4880 int cs_db, cs_l;
4881
8ec4722d
MG		 4882 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4883
adf52235
TY		 4884 ctxt->eflags = kvm_get_rflags(vcpu);
4885 ctxt->eip = kvm_rip_read(vcpu);
4886 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4887 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4888 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4889 cs_db ? X86EMUL_MODE_PROT32 :
4890 X86EMUL_MODE_PROT16;
a584539b 4891 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4892 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4893 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4894 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4895
dd856efa 4896 init_decode_cache(ctxt);
7ae441ea 4897 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4898}
4899
71f9833b 4900int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4901{
9d74191a 4902 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4903 int ret;
4904
4905 init_emulate_ctxt(vcpu);
4906
9dac77fa
AK		 4907 ctxt->op_bytes = 2;
4908 ctxt->ad_bytes = 2;
4909 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4910 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4911
4912 if (ret != X86EMUL_CONTINUE)
4913 return EMULATE_FAIL;
4914
9dac77fa 4915 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4916 kvm_rip_write(vcpu, ctxt->eip);
4917 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4918
4919 if (irq == NMI_VECTOR)
7460fb4a 4920 vcpu->arch.nmi_pending = 0;
63995653
MG		 4921 else
4922 vcpu->arch.interrupt.pending = false;
4923
4924 return EMULATE_DONE;
4925}
4926EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4927
6d77dbfc
GN		 4928static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4929{
fc3a9157
JR		 4930 int r = EMULATE_DONE;
4931
6d77dbfc
GN		 4932 ++vcpu->stat.insn_emulation_fail;
4933 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4934 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4935 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4936 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4937 vcpu->run->internal.ndata = 0;
4938 r = EMULATE_FAIL;
4939 }
6d77dbfc 4940 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4941
4942 return r;
6d77dbfc
GN		 4943}
4944
93c05d3e 4945static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4946 bool write_fault_to_shadow_pgtable,
4947 int emulation_type)
a6f177ef 4948{
95b3cf69 4949 gpa_t gpa = cr2;
8e3d9d06 4950 pfn_t pfn;
a6f177ef 4951
991eebf9
GN		 4952 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4953 return false;
4954
95b3cf69
XG		 4955 if (!vcpu->arch.mmu.direct_map) {
4956 /*
4957 * Write permission should be allowed since only
4958 * write access need to be emulated.
4959 */
4960 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4961
95b3cf69
XG		 4962 /*
4963 * If the mapping is invalid in guest, let cpu retry
4964 * it to generate fault.
4965 */
4966 if (gpa == UNMAPPED_GVA)
4967 return true;
4968 }
a6f177ef 4969
8e3d9d06
XG		 4970 /*
4971 * Do not retry the unhandleable instruction if it faults on the
4972 * readonly host memory, otherwise it will goto a infinite loop:
4973 * retry instruction -> write #PF -> emulation fail -> retry
4974 * instruction -> ...
4975 */
4976 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4977
4978 /*
4979 * If the instruction failed on the error pfn, it can not be fixed,
4980 * report the error to userspace.
4981 */
4982 if (is_error_noslot_pfn(pfn))
4983 return false;
4984
4985 kvm_release_pfn_clean(pfn);
4986
4987 /* The instructions are well-emulated on direct mmu. */
4988 if (vcpu->arch.mmu.direct_map) {
4989 unsigned int indirect_shadow_pages;
4990
4991 spin_lock(&vcpu->kvm->mmu_lock);
4992 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4993 spin_unlock(&vcpu->kvm->mmu_lock);
4994
4995 if (indirect_shadow_pages)
4996 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4997
a6f177ef 4998 return true;
8e3d9d06 4999 }
a6f177ef 5000
95b3cf69
XG		 5001 /*
5002 * if emulation was due to access to shadowed page table
5003 * and it failed try to unshadow page and re-enter the
5004 * guest to let CPU execute the instruction.
5005 */
5006 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5007
5008 /*
5009 * If the access faults on its page table, it can not
5010 * be fixed by unprotecting shadow page and it should
5011 * be reported to userspace.
5012 */
5013 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5014}
5015
1cb3f3ae
XG		 5016static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5017 unsigned long cr2, int emulation_type)
5018{
5019 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5020 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5021
5022 last_retry_eip = vcpu->arch.last_retry_eip;
5023 last_retry_addr = vcpu->arch.last_retry_addr;
5024
5025 /*
5026 * If the emulation is caused by #PF and it is non-page_table
5027 * writing instruction, it means the VM-EXIT is caused by shadow
5028 * page protected, we can zap the shadow page and retry this
5029 * instruction directly.
5030 *
5031 * Note: if the guest uses a non-page-table modifying instruction
5032 * on the PDE that points to the instruction, then we will unmap
5033 * the instruction and go to an infinite loop. So, we cache the
5034 * last retried eip and the last fault address, if we meet the eip
5035 * and the address again, we can break out of the potential infinite
5036 * loop.
5037 */
5038 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5039
5040 if (!(emulation_type & EMULTYPE_RETRY))
5041 return false;
5042
5043 if (x86_page_table_writing_insn(ctxt))
5044 return false;
5045
5046 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5047 return false;
5048
5049 vcpu->arch.last_retry_eip = ctxt->eip;
5050 vcpu->arch.last_retry_addr = cr2;
5051
5052 if (!vcpu->arch.mmu.direct_map)
5053 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5054
22368028 5055 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5056
5057 return true;
5058}
5059
716d51ab
GN		 5060static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5061static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5062
64d60670 5063static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5064{
64d60670 5065 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5066 /* This is a good place to trace that we are exiting SMM. */
5067 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5068
64d60670
PB		 5069 if (unlikely(vcpu->arch.smi_pending)) {
5070 kvm_make_request(KVM_REQ_SMI, vcpu);
5071 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5072 } else {
5073 /* Process a latched INIT, if any. */
5074 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5075 }
5076 }
699023e2
PB		 5077
5078 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5079}
5080
5081static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5082{
5083 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5084
a584539b 5085 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5086
5087 if (changed & HF_SMM_MASK)
5088 kvm_smm_changed(vcpu);
a584539b
PB		 5089}
5090
4a1e10d5
PB		 5091static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5092 unsigned long *db)
5093{
5094 u32 dr6 = 0;
5095 int i;
5096 u32 enable, rwlen;
5097
5098 enable = dr7;
5099 rwlen = dr7 >> 16;
5100 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5101 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5102 dr6 |= (1 << i);
5103 return dr6;
5104}
5105
6addfc42 5106static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5107{
5108 struct kvm_run *kvm_run = vcpu->run;
5109
5110 /*
6addfc42
PB		 5111 * rflags is the old, "raw" value of the flags. The new value has
5112 * not been saved yet.
663f4c61
PB		 5113 *
5114 * This is correct even for TF set by the guest, because "the
5115 * processor will not generate this exception after the instruction
5116 * that sets the TF flag".
5117 */
663f4c61
PB		 5118 if (unlikely(rflags & X86_EFLAGS_TF)) {
5119 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5120 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5121 DR6_RTM;
663f4c61
PB		 5122 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5123 kvm_run->debug.arch.exception = DB_VECTOR;
5124 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5125 *r = EMULATE_USER_EXIT;
5126 } else {
5127 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5128 /*
5129 * "Certain debug exceptions may clear bit 0-3. The
5130 * remaining contents of the DR6 register are never
5131 * cleared by the processor".
5132 */
5133 vcpu->arch.dr6 &= ~15;
6f43ed01 5134 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5135 kvm_queue_exception(vcpu, DB_VECTOR);
5136 }
5137 }
5138}
5139
4a1e10d5
PB		 5140static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5141{
4a1e10d5
PB		 5142 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5143 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5144 struct kvm_run *kvm_run = vcpu->run;
5145 unsigned long eip = kvm_get_linear_rip(vcpu);
5146 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5147 vcpu->arch.guest_debug_dr7,
5148 vcpu->arch.eff_db);
5149
5150 if (dr6 != 0) {
6f43ed01 5151 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5152 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5153 kvm_run->debug.arch.exception = DB_VECTOR;
5154 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5155 *r = EMULATE_USER_EXIT;
5156 return true;
5157 }
5158 }
5159
4161a569
NA		 5160 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5161 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5162 unsigned long eip = kvm_get_linear_rip(vcpu);
5163 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5164 vcpu->arch.dr7,
5165 vcpu->arch.db);
5166
5167 if (dr6 != 0) {
5168 vcpu->arch.dr6 &= ~15;
6f43ed01 5169 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5170 kvm_queue_exception(vcpu, DB_VECTOR);
5171 *r = EMULATE_DONE;
5172 return true;
5173 }
5174 }
5175
5176 return false;
5177}
5178
51d8b661
AP		 5179int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5180 unsigned long cr2,
dc25e89e
AP		 5181 int emulation_type,
5182 void *insn,
5183 int insn_len)
bbd9b64e 5184{
95cb2295 5185 int r;
9d74191a 5186 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5187 bool writeback = true;
93c05d3e 5188 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5189
93c05d3e
XG		 5190 /*
5191 * Clear write_fault_to_shadow_pgtable here to ensure it is
5192 * never reused.
5193 */
5194 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5195 kvm_clear_exception_queue(vcpu);
8d7d8102 5196
571008da 5197 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5198 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5199
5200 /*
5201 * We will reenter on the same instruction since
5202 * we do not set complete_userspace_io. This does not
5203 * handle watchpoints yet, those would be handled in
5204 * the emulate_ops.
5205 */
5206 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5207 return r;
5208
9d74191a
TY		 5209 ctxt->interruptibility = 0;
5210 ctxt->have_exception = false;
e0ad0b47 5211 ctxt->exception.vector = -1;
9d74191a 5212 ctxt->perm_ok = false;
bbd9b64e 5213
b51e974f 5214 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5215
9d74191a 5216 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5217
e46479f8 5218 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5219 ++vcpu->stat.insn_emulation;
1d2887e2 5220 if (r != EMULATION_OK) {
4005996e
AK		 5221 if (emulation_type & EMULTYPE_TRAP_UD)
5222 return EMULATE_FAIL;
991eebf9
GN		 5223 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5224 emulation_type))
bbd9b64e 5225 return EMULATE_DONE;
6d77dbfc
GN		 5226 if (emulation_type & EMULTYPE_SKIP)
5227 return EMULATE_FAIL;
5228 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5229 }
5230 }
5231
ba8afb6b 5232 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5233 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5234 if (ctxt->eflags & X86_EFLAGS_RF)
5235 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5236 return EMULATE_DONE;
5237 }
5238
1cb3f3ae
XG		 5239 if (retry_instruction(ctxt, cr2, emulation_type))
5240 return EMULATE_DONE;
5241
7ae441ea 5242 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5243 changes registers values during IO operation */
7ae441ea
GN		 5244 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5245 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5246 emulator_invalidate_register_cache(ctxt);
7ae441ea 5247 }
4d2179e1 5248
5cd21917 5249restart:
9d74191a 5250 r = x86_emulate_insn(ctxt);
bbd9b64e 5251
775fde86
JR		 5252 if (r == EMULATION_INTERCEPTED)
5253 return EMULATE_DONE;
5254
d2ddd1c4 5255 if (r == EMULATION_FAILED) {
991eebf9
GN		 5256 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5257 emulation_type))
c3cd7ffa
GN		 5258 return EMULATE_DONE;
5259
6d77dbfc 5260 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5261 }
5262
9d74191a 5263 if (ctxt->have_exception) {
d2ddd1c4 5264 r = EMULATE_DONE;
ef54bcfe
PB		 5265 if (inject_emulated_exception(vcpu))
5266 return r;
d2ddd1c4 5267 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5268 if (!vcpu->arch.pio.in) {
5269 /* FIXME: return into emulator if single-stepping. */
3457e419 5270 vcpu->arch.pio.count = 0;
0912c977 5271 } else {
7ae441ea 5272 writeback = false;
716d51ab
GN		 5273 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5274 }
ac0a48c3 5275 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5276 } else if (vcpu->mmio_needed) {
5277 if (!vcpu->mmio_is_write)
5278 writeback = false;
ac0a48c3 5279 r = EMULATE_USER_EXIT;
716d51ab 5280 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5281 } else if (r == EMULATION_RESTART)
5cd21917 5282 goto restart;
d2ddd1c4
GN		 5283 else
5284 r = EMULATE_DONE;
f850e2e6 5285
7ae441ea 5286 if (writeback) {
6addfc42 5287 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5288 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5289 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5290 if (vcpu->arch.hflags != ctxt->emul_flags)
5291 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5292 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5293 if (r == EMULATE_DONE)
6addfc42 5294 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5295 if (!ctxt->have_exception ||
5296 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5297 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5298
5299 /*
5300 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5301 * do nothing, and it will be requested again as soon as
5302 * the shadow expires. But we still need to check here,
5303 * because POPF has no interrupt shadow.
5304 */
5305 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5306 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5307 } else
5308 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5309
5310 return r;
de7d789a 5311}
51d8b661 5312EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5313
cf8f70bf 5314int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5315{
cf8f70bf 5316 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5317 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5318 size, port, &val, 1);
cf8f70bf 5319 /* do not return to emulator after return from userspace */
7972995b 5320 vcpu->arch.pio.count = 0;
de7d789a
CO		 5321 return ret;
5322}
cf8f70bf 5323EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5324
8cfdc000
ZA		 5325static void tsc_bad(void *info)
5326{
0a3aee0d 5327 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5328}
5329
5330static void tsc_khz_changed(void *data)
c8076604 5331{
8cfdc000
ZA		 5332 struct cpufreq_freqs *freq = data;
5333 unsigned long khz = 0;
5334
5335 if (data)
5336 khz = freq->new;
5337 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5338 khz = cpufreq_quick_get(raw_smp_processor_id());
5339 if (!khz)
5340 khz = tsc_khz;
0a3aee0d 5341 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5342}
5343
c8076604
GH		 5344static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5345 void *data)
5346{
5347 struct cpufreq_freqs *freq = data;
5348 struct kvm *kvm;
5349 struct kvm_vcpu *vcpu;
5350 int i, send_ipi = 0;
5351
8cfdc000
ZA		 5352 /*
5353 * We allow guests to temporarily run on slowing clocks,
5354 * provided we notify them after, or to run on accelerating
5355 * clocks, provided we notify them before. Thus time never
5356 * goes backwards.
5357 *
5358 * However, we have a problem. We can't atomically update
5359 * the frequency of a given CPU from this function; it is
5360 * merely a notifier, which can be called from any CPU.
5361 * Changing the TSC frequency at arbitrary points in time
5362 * requires a recomputation of local variables related to
5363 * the TSC for each VCPU. We must flag these local variables
5364 * to be updated and be sure the update takes place with the
5365 * new frequency before any guests proceed.
5366 *
5367 * Unfortunately, the combination of hotplug CPU and frequency
5368 * change creates an intractable locking scenario; the order
5369 * of when these callouts happen is undefined with respect to
5370 * CPU hotplug, and they can race with each other. As such,
5371 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5372 * undefined; you can actually have a CPU frequency change take
5373 * place in between the computation of X and the setting of the
5374 * variable. To protect against this problem, all updates of
5375 * the per_cpu tsc_khz variable are done in an interrupt
5376 * protected IPI, and all callers wishing to update the value
5377 * must wait for a synchronous IPI to complete (which is trivial
5378 * if the caller is on the CPU already). This establishes the
5379 * necessary total order on variable updates.
5380 *
5381 * Note that because a guest time update may take place
5382 * anytime after the setting of the VCPU's request bit, the
5383 * correct TSC value must be set before the request. However,
5384 * to ensure the update actually makes it to any guest which
5385 * starts running in hardware virtualization between the set
5386 * and the acquisition of the spinlock, we must also ping the
5387 * CPU after setting the request bit.
5388 *
5389 */
5390
c8076604
GH		 5391 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5392 return 0;
5393 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5394 return 0;
8cfdc000
ZA		 5395
5396 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5397
2f303b74 5398 spin_lock(&kvm_lock);
c8076604 5399 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5400 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5401 if (vcpu->cpu != freq->cpu)
5402 continue;
c285545f 5403 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5404 if (vcpu->cpu != smp_processor_id())
8cfdc000 5405 send_ipi = 1;
c8076604
GH		 5406 }
5407 }
2f303b74 5408 spin_unlock(&kvm_lock);
c8076604
GH		 5409
5410 if (freq->old < freq->new && send_ipi) {
5411 /*
5412 * We upscale the frequency. Must make the guest
5413 * doesn't see old kvmclock values while running with
5414 * the new frequency, otherwise we risk the guest sees
5415 * time go backwards.
5416 *
5417 * In case we update the frequency for another cpu
5418 * (which might be in guest context) send an interrupt
5419 * to kick the cpu out of guest context. Next time
5420 * guest context is entered kvmclock will be updated,
5421 * so the guest will not see stale values.
5422 */
8cfdc000 5423 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5424 }
5425 return 0;
5426}
5427
5428static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5429 .notifier_call = kvmclock_cpufreq_notifier
5430};
5431
5432static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5433 unsigned long action, void *hcpu)
5434{
5435 unsigned int cpu = (unsigned long)hcpu;
5436
5437 switch (action) {
5438 case CPU_ONLINE:
5439 case CPU_DOWN_FAILED:
5440 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5441 break;
5442 case CPU_DOWN_PREPARE:
5443 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5444 break;
5445 }
5446 return NOTIFY_OK;
5447}
5448
5449static struct notifier_block kvmclock_cpu_notifier_block = {
5450 .notifier_call = kvmclock_cpu_notifier,
5451 .priority = -INT_MAX
c8076604
GH		 5452};
5453
b820cc0c
ZA		 5454static void kvm_timer_init(void)
5455{
5456 int cpu;
5457
c285545f 5458 max_tsc_khz = tsc_khz;
460dd42e
SB		 5459
5460 cpu_notifier_register_begin();
b820cc0c 5461 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5462#ifdef CONFIG_CPU_FREQ
5463 struct cpufreq_policy policy;
5464 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5465 cpu = get_cpu();
5466 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5467 if (policy.cpuinfo.max_freq)
5468 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5469 put_cpu();
c285545f 5470#endif
b820cc0c
ZA		 5471 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5472 CPUFREQ_TRANSITION_NOTIFIER);
5473 }
c285545f 5474 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5475 for_each_online_cpu(cpu)
5476 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5477
5478 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5479 cpu_notifier_register_done();
5480
b820cc0c
ZA		 5481}
5482
ff9d07a0
ZY		 5483static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5484
f5132b01 5485int kvm_is_in_guest(void)
ff9d07a0 5486{
086c9855 5487 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5488}
5489
5490static int kvm_is_user_mode(void)
5491{
5492 int user_mode = 3;
dcf46b94 5493
086c9855
AS		 5494 if (__this_cpu_read(current_vcpu))
5495 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5496
ff9d07a0
ZY		 5497 return user_mode != 0;
5498}
5499
5500static unsigned long kvm_get_guest_ip(void)
5501{
5502 unsigned long ip = 0;
dcf46b94 5503
086c9855
AS		 5504 if (__this_cpu_read(current_vcpu))
5505 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5506
ff9d07a0
ZY		 5507 return ip;
5508}
5509
5510static struct perf_guest_info_callbacks kvm_guest_cbs = {
5511 .is_in_guest = kvm_is_in_guest,
5512 .is_user_mode = kvm_is_user_mode,
5513 .get_guest_ip = kvm_get_guest_ip,
5514};
5515
5516void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5517{
086c9855 5518 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5519}
5520EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5521
5522void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5523{
086c9855 5524 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5525}
5526EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5527
ce88decf
XG		 5528static void kvm_set_mmio_spte_mask(void)
5529{
5530 u64 mask;
5531 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5532
5533 /*
5534 * Set the reserved bits and the present bit of an paging-structure
5535 * entry to generate page fault with PFER.RSV = 1.
5536 */
885032b9 5537 /* Mask the reserved physical address bits. */
d1431483 5538 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5539
5540 /* Bit 62 is always reserved for 32bit host. */
5541 mask |= 0x3ull << 62;
5542
5543 /* Set the present bit. */
ce88decf
XG		 5544 mask |= 1ull;
5545
5546#ifdef CONFIG_X86_64
5547 /*
5548 * If reserved bit is not supported, clear the present bit to disable
5549 * mmio page fault.
5550 */
5551 if (maxphyaddr == 52)
5552 mask &= ~1ull;
5553#endif
5554
5555 kvm_mmu_set_mmio_spte_mask(mask);
5556}
5557
16e8d74d
MT		 5558#ifdef CONFIG_X86_64
5559static void pvclock_gtod_update_fn(struct work_struct *work)
5560{
d828199e
MT		 5561 struct kvm *kvm;
5562
5563 struct kvm_vcpu *vcpu;
5564 int i;
5565
2f303b74 5566 spin_lock(&kvm_lock);
d828199e
MT		 5567 list_for_each_entry(kvm, &vm_list, vm_list)
5568 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5569 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5570 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5571 spin_unlock(&kvm_lock);
16e8d74d
MT		 5572}
5573
5574static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5575
5576/*
5577 * Notification about pvclock gtod data update.
5578 */
5579static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5580 void *priv)
5581{
5582 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5583 struct timekeeper *tk = priv;
5584
5585 update_pvclock_gtod(tk);
5586
5587 /* disable master clock if host does not trust, or does not
5588 * use, TSC clocksource
5589 */
5590 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5591 atomic_read(&kvm_guest_has_master_clock) != 0)
5592 queue_work(system_long_wq, &pvclock_gtod_work);
5593
5594 return 0;
5595}
5596
5597static struct notifier_block pvclock_gtod_notifier = {
5598 .notifier_call = pvclock_gtod_notify,
5599};
5600#endif
5601
f8c16bba 5602int kvm_arch_init(void *opaque)
043405e1 5603{
b820cc0c 5604 int r;
6b61edf7 5605 struct kvm_x86_ops *ops = opaque;
f8c16bba 5606
f8c16bba
ZX		 5607 if (kvm_x86_ops) {
5608 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5609 r = -EEXIST;
5610 goto out;
f8c16bba
ZX		 5611 }
5612
5613 if (!ops->cpu_has_kvm_support()) {
5614 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5615 r = -EOPNOTSUPP;
5616 goto out;
f8c16bba
ZX		 5617 }
5618 if (ops->disabled_by_bios()) {
5619 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5620 r = -EOPNOTSUPP;
5621 goto out;
f8c16bba
ZX		 5622 }
5623
013f6a5d
MT		 5624 r = -ENOMEM;
5625 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5626 if (!shared_msrs) {
5627 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5628 goto out;
5629 }
5630
97db56ce
AK		 5631 r = kvm_mmu_module_init();
5632 if (r)
013f6a5d 5633 goto out_free_percpu;
97db56ce 5634
ce88decf 5635 kvm_set_mmio_spte_mask();
97db56ce 5636
f8c16bba 5637 kvm_x86_ops = ops;
920c8377 5638
7b52345e 5639 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5640 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5641
b820cc0c 5642 kvm_timer_init();
c8076604 5643
ff9d07a0
ZY		 5644 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5645
2acf923e
DC		 5646 if (cpu_has_xsave)
5647 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5648
c5cc421b 5649 kvm_lapic_init();
16e8d74d
MT		 5650#ifdef CONFIG_X86_64
5651 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5652#endif
5653
f8c16bba 5654 return 0;
56c6d28a 5655
013f6a5d
MT		 5656out_free_percpu:
5657 free_percpu(shared_msrs);
56c6d28a 5658out:
56c6d28a 5659 return r;
043405e1 5660}
8776e519 5661
f8c16bba
ZX		 5662void kvm_arch_exit(void)
5663{
ff9d07a0
ZY		 5664 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5665
888d256e
JK		 5666 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5667 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5668 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5669 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5670#ifdef CONFIG_X86_64
5671 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5672#endif
f8c16bba 5673 kvm_x86_ops = NULL;
56c6d28a 5674 kvm_mmu_module_exit();
013f6a5d 5675 free_percpu(shared_msrs);
56c6d28a 5676}
f8c16bba 5677
5cb56059 5678int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5679{
5680 ++vcpu->stat.halt_exits;
5681 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5682 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5683 return 1;
5684 } else {
5685 vcpu->run->exit_reason = KVM_EXIT_HLT;
5686 return 0;
5687 }
5688}
5cb56059
JS		 5689EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5690
5691int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5692{
5693 kvm_x86_ops->skip_emulated_instruction(vcpu);
5694 return kvm_vcpu_halt(vcpu);
5695}
8776e519
HB		 5696EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5697
6aef266c
SV		 5698/*
5699 * kvm_pv_kick_cpu_op: Kick a vcpu.
5700 *
5701 * @apicid - apicid of vcpu to be kicked.
5702 */
5703static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5704{
24d2166b 5705 struct kvm_lapic_irq lapic_irq;
6aef266c 5706
24d2166b
R		 5707 lapic_irq.shorthand = 0;
5708 lapic_irq.dest_mode = 0;
5709 lapic_irq.dest_id = apicid;
93bbf0b8 5710 lapic_irq.msi_redir_hint = false;
6aef266c 5711
24d2166b 5712 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5713 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5714}
5715
8776e519
HB		 5716int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5717{
5718 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5719 int op_64_bit, r = 1;
8776e519 5720
5cb56059
JS		 5721 kvm_x86_ops->skip_emulated_instruction(vcpu);
5722
55cd8e5a
GN		 5723 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5724 return kvm_hv_hypercall(vcpu);
5725
5fdbf976
MT		 5726 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5727 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5728 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5729 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5730 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5731
229456fc 5732 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5733
a449c7aa
NA		 5734 op_64_bit = is_64_bit_mode(vcpu);
5735 if (!op_64_bit) {
8776e519
HB		 5736 nr &= 0xFFFFFFFF;
5737 a0 &= 0xFFFFFFFF;
5738 a1 &= 0xFFFFFFFF;
5739 a2 &= 0xFFFFFFFF;
5740 a3 &= 0xFFFFFFFF;
5741 }
5742
07708c4a
JK		 5743 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5744 ret = -KVM_EPERM;
5745 goto out;
5746 }
5747
8776e519 5748 switch (nr) {
b93463aa
AK		 5749 case KVM_HC_VAPIC_POLL_IRQ:
5750 ret = 0;
5751 break;
6aef266c
SV		 5752 case KVM_HC_KICK_CPU:
5753 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5754 ret = 0;
5755 break;
8776e519
HB		 5756 default:
5757 ret = -KVM_ENOSYS;
5758 break;
5759 }
07708c4a 5760out:
a449c7aa
NA		 5761 if (!op_64_bit)
5762 ret = (u32)ret;
5fdbf976 5763 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5764 ++vcpu->stat.hypercalls;
2f333bcb 5765 return r;
8776e519
HB		 5766}
5767EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5768
b6785def 5769static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5770{
d6aa1000 5771 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5772 char instruction[3];
5fdbf976 5773 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5774
8776e519 5775 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5776
9d74191a 5777 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5778}
5779
b6c7a5dc
HB		 5780/*
5781 * Check if userspace requested an interrupt window, and that the
5782 * interrupt window is open.
5783 *
5784 * No need to exit to userspace if we already have an interrupt queued.
5785 */
851ba692 5786static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5787{
8061823a 5788 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5789 vcpu->run->request_interrupt_window &&
5df56646 5790 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5791}
5792
851ba692 5793static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5794{
851ba692
AK		 5795 struct kvm_run *kvm_run = vcpu->run;
5796
91586a3b 5797 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5798 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5799 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5800 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5801 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5802 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5803 else
b6c7a5dc 5804 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5805 kvm_arch_interrupt_allowed(vcpu) &&
5806 !kvm_cpu_has_interrupt(vcpu) &&
5807 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5808}
5809
95ba8273
GN		 5810static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5811{
5812 int max_irr, tpr;
5813
5814 if (!kvm_x86_ops->update_cr8_intercept)
5815 return;
5816
88c808fd
AK		 5817 if (!vcpu->arch.apic)
5818 return;
5819
8db3baa2
GN		 5820 if (!vcpu->arch.apic->vapic_addr)
5821 max_irr = kvm_lapic_find_highest_irr(vcpu);
5822 else
5823 max_irr = -1;
95ba8273
GN		 5824
5825 if (max_irr != -1)
5826 max_irr >>= 4;
5827
5828 tpr = kvm_lapic_get_cr8(vcpu);
5829
5830 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5831}
5832
b6b8a145 5833static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5834{
b6b8a145
JK		 5835 int r;
5836
95ba8273 5837 /* try to reinject previous events if any */
b59bb7bd 5838 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5839 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5840 vcpu->arch.exception.has_error_code,
5841 vcpu->arch.exception.error_code);
d6e8c854
NA		 5842
5843 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5844 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5845 X86_EFLAGS_RF);
5846
6bdf0662
NA		 5847 if (vcpu->arch.exception.nr == DB_VECTOR &&
5848 (vcpu->arch.dr7 & DR7_GD)) {
5849 vcpu->arch.dr7 &= ~DR7_GD;
5850 kvm_update_dr7(vcpu);
5851 }
5852
b59bb7bd
GN		 5853 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5854 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5855 vcpu->arch.exception.error_code,
5856 vcpu->arch.exception.reinject);
b6b8a145 5857 return 0;
b59bb7bd
GN		 5858 }
5859
95ba8273
GN		 5860 if (vcpu->arch.nmi_injected) {
5861 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5862 return 0;
95ba8273
GN		 5863 }
5864
5865 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5866 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5867 return 0;
5868 }
5869
5870 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5871 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5872 if (r != 0)
5873 return r;
95ba8273
GN		 5874 }
5875
5876 /* try to inject new event if pending */
5877 if (vcpu->arch.nmi_pending) {
5878 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5879 --vcpu->arch.nmi_pending;
95ba8273
GN		 5880 vcpu->arch.nmi_injected = true;
5881 kvm_x86_ops->set_nmi(vcpu);
5882 }
c7c9c56c 5883 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5884 /*
5885 * Because interrupts can be injected asynchronously, we are
5886 * calling check_nested_events again here to avoid a race condition.
5887 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5888 * proposal and current concerns. Perhaps we should be setting
5889 * KVM_REQ_EVENT only on certain events and not unconditionally?
5890 */
5891 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5892 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5893 if (r != 0)
5894 return r;
5895 }
95ba8273 5896 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5897 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5898 false);
5899 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5900 }
5901 }
b6b8a145 5902 return 0;
95ba8273
GN		 5903}
5904
7460fb4a
AK		 5905static void process_nmi(struct kvm_vcpu *vcpu)
5906{
5907 unsigned limit = 2;
5908
5909 /*
5910 * x86 is limited to one NMI running, and one NMI pending after it.
5911 * If an NMI is already in progress, limit further NMIs to just one.
5912 * Otherwise, allow two (and we'll inject the first one immediately).
5913 */
5914 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5915 limit = 1;
5916
5917 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5918 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5919 kvm_make_request(KVM_REQ_EVENT, vcpu);
5920}
5921
660a5d51
PB		 5922#define put_smstate(type, buf, offset, val) \
5923 *(type *)((buf) + (offset) - 0x7e00) = val
5924
5925static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5926{
5927 u32 flags = 0;
5928 flags |= seg->g << 23;
5929 flags |= seg->db << 22;
5930 flags |= seg->l << 21;
5931 flags |= seg->avl << 20;
5932 flags |= seg->present << 15;
5933 flags |= seg->dpl << 13;
5934 flags |= seg->s << 12;
5935 flags |= seg->type << 8;
5936 return flags;
5937}
5938
5939static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5940{
5941 struct kvm_segment seg;
5942 int offset;
5943
5944 kvm_get_segment(vcpu, &seg, n);
5945 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5946
5947 if (n < 3)
5948 offset = 0x7f84 + n * 12;
5949 else
5950 offset = 0x7f2c + (n - 3) * 12;
5951
5952 put_smstate(u32, buf, offset + 8, seg.base);
5953 put_smstate(u32, buf, offset + 4, seg.limit);
5954 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5955}
5956
5957static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5958{
5959 struct kvm_segment seg;
5960 int offset;
5961 u16 flags;
5962
5963 kvm_get_segment(vcpu, &seg, n);
5964 offset = 0x7e00 + n * 16;
5965
5966 flags = process_smi_get_segment_flags(&seg) >> 8;
5967 put_smstate(u16, buf, offset, seg.selector);
5968 put_smstate(u16, buf, offset + 2, flags);
5969 put_smstate(u32, buf, offset + 4, seg.limit);
5970 put_smstate(u64, buf, offset + 8, seg.base);
5971}
5972
5973static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
5974{
5975 struct desc_ptr dt;
5976 struct kvm_segment seg;
5977 unsigned long val;
5978 int i;
5979
5980 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
5981 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
5982 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
5983 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
5984
5985 for (i = 0; i < 8; i++)
5986 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
5987
5988 kvm_get_dr(vcpu, 6, &val);
5989 put_smstate(u32, buf, 0x7fcc, (u32)val);
5990 kvm_get_dr(vcpu, 7, &val);
5991 put_smstate(u32, buf, 0x7fc8, (u32)val);
5992
5993 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
5994 put_smstate(u32, buf, 0x7fc4, seg.selector);
5995 put_smstate(u32, buf, 0x7f64, seg.base);
5996 put_smstate(u32, buf, 0x7f60, seg.limit);
5997 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
5998
5999 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6000 put_smstate(u32, buf, 0x7fc0, seg.selector);
6001 put_smstate(u32, buf, 0x7f80, seg.base);
6002 put_smstate(u32, buf, 0x7f7c, seg.limit);
6003 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6004
6005 kvm_x86_ops->get_gdt(vcpu, &dt);
6006 put_smstate(u32, buf, 0x7f74, dt.address);
6007 put_smstate(u32, buf, 0x7f70, dt.size);
6008
6009 kvm_x86_ops->get_idt(vcpu, &dt);
6010 put_smstate(u32, buf, 0x7f58, dt.address);
6011 put_smstate(u32, buf, 0x7f54, dt.size);
6012
6013 for (i = 0; i < 6; i++)
6014 process_smi_save_seg_32(vcpu, buf, i);
6015
6016 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6017
6018 /* revision id */
6019 put_smstate(u32, buf, 0x7efc, 0x00020000);
6020 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6021}
6022
6023static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6024{
6025#ifdef CONFIG_X86_64
6026 struct desc_ptr dt;
6027 struct kvm_segment seg;
6028 unsigned long val;
6029 int i;
6030
6031 for (i = 0; i < 16; i++)
6032 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6033
6034 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6035 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6036
6037 kvm_get_dr(vcpu, 6, &val);
6038 put_smstate(u64, buf, 0x7f68, val);
6039 kvm_get_dr(vcpu, 7, &val);
6040 put_smstate(u64, buf, 0x7f60, val);
6041
6042 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6043 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6044 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6045
6046 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6047
6048 /* revision id */
6049 put_smstate(u32, buf, 0x7efc, 0x00020064);
6050
6051 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6052
6053 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6054 put_smstate(u16, buf, 0x7e90, seg.selector);
6055 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6056 put_smstate(u32, buf, 0x7e94, seg.limit);
6057 put_smstate(u64, buf, 0x7e98, seg.base);
6058
6059 kvm_x86_ops->get_idt(vcpu, &dt);
6060 put_smstate(u32, buf, 0x7e84, dt.size);
6061 put_smstate(u64, buf, 0x7e88, dt.address);
6062
6063 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6064 put_smstate(u16, buf, 0x7e70, seg.selector);
6065 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6066 put_smstate(u32, buf, 0x7e74, seg.limit);
6067 put_smstate(u64, buf, 0x7e78, seg.base);
6068
6069 kvm_x86_ops->get_gdt(vcpu, &dt);
6070 put_smstate(u32, buf, 0x7e64, dt.size);
6071 put_smstate(u64, buf, 0x7e68, dt.address);
6072
6073 for (i = 0; i < 6; i++)
6074 process_smi_save_seg_64(vcpu, buf, i);
6075#else
6076 WARN_ON_ONCE(1);
6077#endif
6078}
6079
64d60670
PB		 6080static void process_smi(struct kvm_vcpu *vcpu)
6081{
660a5d51
PB		 6082 struct kvm_segment cs, ds;
6083 char buf[512];
6084 u32 cr0;
6085
64d60670
PB		 6086 if (is_smm(vcpu)) {
6087 vcpu->arch.smi_pending = true;
6088 return;
6089 }
6090
660a5d51
PB		 6091 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6092 vcpu->arch.hflags |= HF_SMM_MASK;
6093 memset(buf, 0, 512);
6094 if (guest_cpuid_has_longmode(vcpu))
6095 process_smi_save_state_64(vcpu, buf);
6096 else
6097 process_smi_save_state_32(vcpu, buf);
6098
54bf36aa 6099 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6100
6101 if (kvm_x86_ops->get_nmi_mask(vcpu))
6102 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6103 else
6104 kvm_x86_ops->set_nmi_mask(vcpu, true);
6105
6106 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6107 kvm_rip_write(vcpu, 0x8000);
6108
6109 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6110 kvm_x86_ops->set_cr0(vcpu, cr0);
6111 vcpu->arch.cr0 = cr0;
6112
6113 kvm_x86_ops->set_cr4(vcpu, 0);
6114
6115 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6116
6117 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6118 cs.base = vcpu->arch.smbase;
6119
6120 ds.selector = 0;
6121 ds.base = 0;
6122
6123 cs.limit = ds.limit = 0xffffffff;
6124 cs.type = ds.type = 0x3;
6125 cs.dpl = ds.dpl = 0;
6126 cs.db = ds.db = 0;
6127 cs.s = ds.s = 1;
6128 cs.l = ds.l = 0;
6129 cs.g = ds.g = 1;
6130 cs.avl = ds.avl = 0;
6131 cs.present = ds.present = 1;
6132 cs.unusable = ds.unusable = 0;
6133 cs.padding = ds.padding = 0;
6134
6135 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6136 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6137 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6138 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6139 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6140 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6141
6142 if (guest_cpuid_has_longmode(vcpu))
6143 kvm_x86_ops->set_efer(vcpu, 0);
6144
6145 kvm_update_cpuid(vcpu);
6146 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6147}
6148
3d81bc7e 6149static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6150{
6151 u64 eoi_exit_bitmap[4];
cf9e65b7 6152 u32 tmr[8];
c7c9c56c 6153
3d81bc7e
YZ		 6154 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6155 return;
c7c9c56c
YZ		 6156
6157 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6158 memset(tmr, 0, 32);
c7c9c56c 6159
cf9e65b7 6160 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6161 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6162 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6163}
6164
a70656b6
RK		 6165static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6166{
6167 ++vcpu->stat.tlb_flush;
6168 kvm_x86_ops->tlb_flush(vcpu);
6169}
6170
4256f43f
TC		 6171void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6172{
c24ae0dc
TC		 6173 struct page *page = NULL;
6174
f439ed27
PB		 6175 if (!irqchip_in_kernel(vcpu->kvm))
6176 return;
6177
4256f43f
TC		 6178 if (!kvm_x86_ops->set_apic_access_page_addr)
6179 return;
6180
c24ae0dc 6181 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6182 if (is_error_page(page))
6183 return;
c24ae0dc
TC		 6184 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6185
6186 /*
6187 * Do not pin apic access page in memory, the MMU notifier
6188 * will call us again if it is migrated or swapped out.
6189 */
6190 put_page(page);
4256f43f
TC		 6191}
6192EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6193
fe71557a
TC		 6194void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6195 unsigned long address)
6196{
c24ae0dc
TC		 6197 /*
6198 * The physical address of apic access page is stored in the VMCS.
6199 * Update it when it becomes invalid.
6200 */
6201 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6202 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6203}
6204
9357d939 6205/*
362c698f 6206 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6207 * exiting to the userspace. Otherwise, the value will be returned to the
6208 * userspace.
6209 */
851ba692 6210static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6211{
6212 int r;
6a8b1d13 6213 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6214 vcpu->run->request_interrupt_window;
730dca42 6215 bool req_immediate_exit = false;
b6c7a5dc 6216
3e007509 6217 if (vcpu->requests) {
a8eeb04a 6218 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6219 kvm_mmu_unload(vcpu);
a8eeb04a 6220 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6221 __kvm_migrate_timers(vcpu);
d828199e
MT		 6222 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6223 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6224 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6225 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6226 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6227 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6228 if (unlikely(r))
6229 goto out;
6230 }
a8eeb04a 6231 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6232 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6233 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6234 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6235 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6236 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6237 r = 0;
6238 goto out;
6239 }
a8eeb04a 6240 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6241 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6242 r = 0;
6243 goto out;
6244 }
a8eeb04a 6245 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6246 vcpu->fpu_active = 0;
6247 kvm_x86_ops->fpu_deactivate(vcpu);
6248 }
af585b92
GN		 6249 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6250 /* Page is swapped out. Do synthetic halt */
6251 vcpu->arch.apf.halted = true;
6252 r = 1;
6253 goto out;
6254 }
c9aaa895
GC		 6255 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6256 record_steal_time(vcpu);
64d60670
PB		 6257 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6258 process_smi(vcpu);
7460fb4a
AK		 6259 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6260 process_nmi(vcpu);
f5132b01 6261 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6262 kvm_pmu_handle_event(vcpu);
f5132b01 6263 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6264 kvm_pmu_deliver_pmi(vcpu);
3d81bc7e
YZ		 6265 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6266 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6267 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6268 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6269 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6270 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6271 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6272 r = 0;
6273 goto out;
6274 }
2f52d58c 6275 }
b93463aa 6276
b463a6f7 6277 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6278 kvm_apic_accept_events(vcpu);
6279 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6280 r = 1;
6281 goto out;
6282 }
6283
b6b8a145
JK		 6284 if (inject_pending_event(vcpu, req_int_win) != 0)
6285 req_immediate_exit = true;
b463a6f7 6286 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6287 else if (vcpu->arch.nmi_pending)
c9a7953f 6288 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6289 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6290 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6291
6292 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6293 /*
6294 * Update architecture specific hints for APIC
6295 * virtual interrupt delivery.
6296 */
6297 if (kvm_x86_ops->hwapic_irr_update)
6298 kvm_x86_ops->hwapic_irr_update(vcpu,
6299 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6300 update_cr8_intercept(vcpu);
6301 kvm_lapic_sync_to_vapic(vcpu);
6302 }
6303 }
6304
d8368af8
AK		 6305 r = kvm_mmu_reload(vcpu);
6306 if (unlikely(r)) {
d905c069 6307 goto cancel_injection;
d8368af8
AK		 6308 }
6309
b6c7a5dc
HB		 6310 preempt_disable();
6311
6312 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6313 if (vcpu->fpu_active)
6314 kvm_load_guest_fpu(vcpu);
2acf923e 6315 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6316
6b7e2d09
XG		 6317 vcpu->mode = IN_GUEST_MODE;
6318
01b71917
MT		 6319 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6320
6b7e2d09
XG		 6321 /* We should set ->mode before check ->requests,
6322 * see the comment in make_all_cpus_request.
6323 */
01b71917 6324 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6325
d94e1dc9 6326 local_irq_disable();
32f88400 6327
6b7e2d09 6328 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6329 || need_resched() || signal_pending(current)) {
6b7e2d09 6330 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6331 smp_wmb();
6c142801
AK		 6332 local_irq_enable();
6333 preempt_enable();
01b71917 6334 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6335 r = 1;
d905c069 6336 goto cancel_injection;
6c142801
AK		 6337 }
6338
d6185f20
NHE		 6339 if (req_immediate_exit)
6340 smp_send_reschedule(vcpu->cpu);
6341
ccf73aaf 6342 __kvm_guest_enter();
b6c7a5dc 6343
42dbaa5a 6344 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6345 set_debugreg(0, 7);
6346 set_debugreg(vcpu->arch.eff_db[0], 0);
6347 set_debugreg(vcpu->arch.eff_db[1], 1);
6348 set_debugreg(vcpu->arch.eff_db[2], 2);
6349 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6350 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6351 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6352 }
b6c7a5dc 6353
229456fc 6354 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6355 wait_lapic_expire(vcpu);
851ba692 6356 kvm_x86_ops->run(vcpu);
b6c7a5dc 6357
c77fb5fe
PB		 6358 /*
6359 * Do this here before restoring debug registers on the host. And
6360 * since we do this before handling the vmexit, a DR access vmexit
6361 * can (a) read the correct value of the debug registers, (b) set
6362 * KVM_DEBUGREG_WONT_EXIT again.
6363 */
6364 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6365 int i;
6366
6367 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6368 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6369 for (i = 0; i < KVM_NR_DB_REGS; i++)
6370 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6371 }
6372
24f1e32c
FW		 6373 /*
6374 * If the guest has used debug registers, at least dr7
6375 * will be disabled while returning to the host.
6376 * If we don't have active breakpoints in the host, we don't
6377 * care about the messed up debug address registers. But if
6378 * we have some of them active, restore the old state.
6379 */
59d8eb53 6380 if (hw_breakpoint_active())
24f1e32c 6381 hw_breakpoint_restore();
42dbaa5a 6382
886b470c
MT		 6383 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6384 native_read_tsc());
1d5f066e 6385
6b7e2d09 6386 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6387 smp_wmb();
a547c6db
YZ		 6388
6389 /* Interrupt is enabled by handle_external_intr() */
6390 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6391
6392 ++vcpu->stat.exits;
6393
6394 /*
6395 * We must have an instruction between local_irq_enable() and
6396 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6397 * the interrupt shadow. The stat.exits increment will do nicely.
6398 * But we need to prevent reordering, hence this barrier():
6399 */
6400 barrier();
6401
6402 kvm_guest_exit();
6403
6404 preempt_enable();
6405
f656ce01 6406 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6407
b6c7a5dc
HB		 6408 /*
6409 * Profile KVM exit RIPs:
6410 */
6411 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6412 unsigned long rip = kvm_rip_read(vcpu);
6413 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6414 }
6415
cc578287
ZA		 6416 if (unlikely(vcpu->arch.tsc_always_catchup))
6417 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6418
5cfb1d5a
MT		 6419 if (vcpu->arch.apic_attention)
6420 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6421
851ba692 6422 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6423 return r;
6424
6425cancel_injection:
6426 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6427 if (unlikely(vcpu->arch.apic_attention))
6428 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6429out:
6430 return r;
6431}
b6c7a5dc 6432
362c698f
PB		 6433static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6434{
9c8fd1ba
PB		 6435 if (!kvm_arch_vcpu_runnable(vcpu)) {
6436 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6437 kvm_vcpu_block(vcpu);
6438 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6439 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6440 return 1;
6441 }
362c698f
PB		 6442
6443 kvm_apic_accept_events(vcpu);
6444 switch(vcpu->arch.mp_state) {
6445 case KVM_MP_STATE_HALTED:
6446 vcpu->arch.pv.pv_unhalted = false;
6447 vcpu->arch.mp_state =
6448 KVM_MP_STATE_RUNNABLE;
6449 case KVM_MP_STATE_RUNNABLE:
6450 vcpu->arch.apf.halted = false;
6451 break;
6452 case KVM_MP_STATE_INIT_RECEIVED:
6453 break;
6454 default:
6455 return -EINTR;
6456 break;
6457 }
6458 return 1;
6459}
09cec754 6460
362c698f 6461static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6462{
6463 int r;
f656ce01 6464 struct kvm *kvm = vcpu->kvm;
d7690175 6465
f656ce01 6466 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6467
362c698f 6468 for (;;) {
af585b92
GN		 6469 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6470 !vcpu->arch.apf.halted)
851ba692 6471 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6472 else
6473 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6474 if (r <= 0)
6475 break;
6476
6477 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6478 if (kvm_cpu_has_pending_timer(vcpu))
6479 kvm_inject_pending_timer_irqs(vcpu);
6480
851ba692 6481 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6482 r = -EINTR;
851ba692 6483 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6484 ++vcpu->stat.request_irq_exits;
362c698f 6485 break;
09cec754 6486 }
af585b92
GN		 6487
6488 kvm_check_async_pf_completion(vcpu);
6489
09cec754
GN		 6490 if (signal_pending(current)) {
6491 r = -EINTR;
851ba692 6492 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6493 ++vcpu->stat.signal_exits;
362c698f 6494 break;
09cec754
GN		 6495 }
6496 if (need_resched()) {
f656ce01 6497 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6498 cond_resched();
f656ce01 6499 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6500 }
b6c7a5dc
HB		 6501 }
6502
f656ce01 6503 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6504
6505 return r;
6506}
6507
716d51ab
GN		 6508static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6509{
6510 int r;
6511 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6512 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6513 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6514 if (r != EMULATE_DONE)
6515 return 0;
6516 return 1;
6517}
6518
6519static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6520{
6521 BUG_ON(!vcpu->arch.pio.count);
6522
6523 return complete_emulated_io(vcpu);
6524}
6525
f78146b0
AK		 6526/*
6527 * Implements the following, as a state machine:
6528 *
6529 * read:
6530 * for each fragment
87da7e66
XG		 6531 * for each mmio piece in the fragment
6532 * write gpa, len
6533 * exit
6534 * copy data
f78146b0
AK		 6535 * execute insn
6536 *
6537 * write:
6538 * for each fragment
87da7e66
XG		 6539 * for each mmio piece in the fragment
6540 * write gpa, len
6541 * copy data
6542 * exit
f78146b0 6543 */
716d51ab 6544static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6545{
6546 struct kvm_run *run = vcpu->run;
f78146b0 6547 struct kvm_mmio_fragment *frag;
87da7e66 6548 unsigned len;
5287f194 6549
716d51ab 6550 BUG_ON(!vcpu->mmio_needed);
5287f194 6551
716d51ab 6552 /* Complete previous fragment */
87da7e66
XG		 6553 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6554 len = min(8u, frag->len);
716d51ab 6555 if (!vcpu->mmio_is_write)
87da7e66
XG		 6556 memcpy(frag->data, run->mmio.data, len);
6557
6558 if (frag->len <= 8) {
6559 /* Switch to the next fragment. */
6560 frag++;
6561 vcpu->mmio_cur_fragment++;
6562 } else {
6563 /* Go forward to the next mmio piece. */
6564 frag->data += len;
6565 frag->gpa += len;
6566 frag->len -= len;
6567 }
6568
a08d3b3b 6569 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6570 vcpu->mmio_needed = 0;
0912c977
PB		 6571
6572 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6573 if (vcpu->mmio_is_write)
716d51ab
GN		 6574 return 1;
6575 vcpu->mmio_read_completed = 1;
6576 return complete_emulated_io(vcpu);
6577 }
87da7e66 6578
716d51ab
GN		 6579 run->exit_reason = KVM_EXIT_MMIO;
6580 run->mmio.phys_addr = frag->gpa;
6581 if (vcpu->mmio_is_write)
87da7e66
XG		 6582 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6583 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6584 run->mmio.is_write = vcpu->mmio_is_write;
6585 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6586 return 0;
5287f194
AK		 6587}
6588
716d51ab 6589
b6c7a5dc
HB		 6590int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6591{
c5bedc68 6592 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6593 int r;
6594 sigset_t sigsaved;
6595
c4d72e2d 6596 fpu__activate_curr(fpu);
e5c30142 6597
ac9f6dc0
AK		 6598 if (vcpu->sigset_active)
6599 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6600
a4535290 6601 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6602 kvm_vcpu_block(vcpu);
66450a21 6603 kvm_apic_accept_events(vcpu);
d7690175 6604 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6605 r = -EAGAIN;
6606 goto out;
b6c7a5dc
HB		 6607 }
6608
b6c7a5dc 6609 /* re-sync apic's tpr */
eea1cff9
AP		 6610 if (!irqchip_in_kernel(vcpu->kvm)) {
6611 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6612 r = -EINVAL;
6613 goto out;
6614 }
6615 }
b6c7a5dc 6616
716d51ab
GN		 6617 if (unlikely(vcpu->arch.complete_userspace_io)) {
6618 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6619 vcpu->arch.complete_userspace_io = NULL;
6620 r = cui(vcpu);
6621 if (r <= 0)
6622 goto out;
6623 } else
6624 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6625
362c698f 6626 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6627
6628out:
f1d86e46 6629 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6630 if (vcpu->sigset_active)
6631 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6632
b6c7a5dc
HB		 6633 return r;
6634}
6635
6636int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6637{
7ae441ea
GN		 6638 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6639 /*
6640 * We are here if userspace calls get_regs() in the middle of
6641 * instruction emulation. Registers state needs to be copied
4a969980 6642 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6643 * that usually, but some bad designed PV devices (vmware
6644 * backdoor interface) need this to work
6645 */
dd856efa 6646 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6647 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6648 }
5fdbf976
MT		 6649 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6650 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6651 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6652 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6653 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6654 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6655 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6656 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6657#ifdef CONFIG_X86_64
5fdbf976
MT		 6658 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6659 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6660 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6661 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6662 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6663 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6664 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6665 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6666#endif
6667
5fdbf976 6668 regs->rip = kvm_rip_read(vcpu);
91586a3b 6669 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6670
b6c7a5dc
HB		 6671 return 0;
6672}
6673
6674int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6675{
7ae441ea
GN		 6676 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6677 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6678
5fdbf976
MT		 6679 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6680 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6681 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6682 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6683 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6684 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6685 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6686 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6687#ifdef CONFIG_X86_64
5fdbf976
MT		 6688 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6689 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6690 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6691 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6692 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6693 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6694 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6695 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6696#endif
6697
5fdbf976 6698 kvm_rip_write(vcpu, regs->rip);
91586a3b 6699 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6700
b4f14abd
JK		 6701 vcpu->arch.exception.pending = false;
6702
3842d135
AK		 6703 kvm_make_request(KVM_REQ_EVENT, vcpu);
6704
b6c7a5dc
HB		 6705 return 0;
6706}
6707
b6c7a5dc
HB		 6708void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6709{
6710 struct kvm_segment cs;
6711
3e6e0aab 6712 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6713 *db = cs.db;
6714 *l = cs.l;
6715}
6716EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6717
6718int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6719 struct kvm_sregs *sregs)
6720{
89a27f4d 6721 struct desc_ptr dt;
b6c7a5dc 6722
3e6e0aab
GT		 6723 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6724 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6725 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6726 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6727 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6728 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6729
3e6e0aab
GT		 6730 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6731 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6732
6733 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6734 sregs->idt.limit = dt.size;
6735 sregs->idt.base = dt.address;
b6c7a5dc 6736 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6737 sregs->gdt.limit = dt.size;
6738 sregs->gdt.base = dt.address;
b6c7a5dc 6739
4d4ec087 6740 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6741 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6742 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6743 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6744 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6745 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6746 sregs->apic_base = kvm_get_apic_base(vcpu);
6747
923c61bb 6748 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6749
36752c9b 6750 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6751 set_bit(vcpu->arch.interrupt.nr,
6752 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6753
b6c7a5dc
HB		 6754 return 0;
6755}
6756
62d9f0db
MT		 6757int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6758 struct kvm_mp_state *mp_state)
6759{
66450a21 6760 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6761 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6762 vcpu->arch.pv.pv_unhalted)
6763 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6764 else
6765 mp_state->mp_state = vcpu->arch.mp_state;
6766
62d9f0db
MT		 6767 return 0;
6768}
6769
6770int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6771 struct kvm_mp_state *mp_state)
6772{
66450a21
JK		 6773 if (!kvm_vcpu_has_lapic(vcpu) &&
6774 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6775 return -EINVAL;
6776
6777 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6778 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6779 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6780 } else
6781 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6782 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6783 return 0;
6784}
6785
7f3d35fd
KW		 6786int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6787 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6788{
9d74191a 6789 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6790 int ret;
e01c2426 6791
8ec4722d 6792 init_emulate_ctxt(vcpu);
c697518a 6793
7f3d35fd 6794 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6795 has_error_code, error_code);
c697518a 6796
c697518a 6797 if (ret)
19d04437 6798 return EMULATE_FAIL;
37817f29 6799
9d74191a
TY		 6800 kvm_rip_write(vcpu, ctxt->eip);
6801 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6802 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6803 return EMULATE_DONE;
37817f29
IE		 6804}
6805EXPORT_SYMBOL_GPL(kvm_task_switch);
6806
b6c7a5dc
HB		 6807int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6808 struct kvm_sregs *sregs)
6809{
58cb628d 6810 struct msr_data apic_base_msr;
b6c7a5dc 6811 int mmu_reset_needed = 0;
63f42e02 6812 int pending_vec, max_bits, idx;
89a27f4d 6813 struct desc_ptr dt;
b6c7a5dc 6814
6d1068b3
PM		 6815 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6816 return -EINVAL;
6817
89a27f4d
GN		 6818 dt.size = sregs->idt.limit;
6819 dt.address = sregs->idt.base;
b6c7a5dc 6820 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6821 dt.size = sregs->gdt.limit;
6822 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6823 kvm_x86_ops->set_gdt(vcpu, &dt);
6824
ad312c7c 6825 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6826 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6827 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6828 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6829
2d3ad1f4 6830 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6831
f6801dff 6832 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6833 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6834 apic_base_msr.data = sregs->apic_base;
6835 apic_base_msr.host_initiated = true;
6836 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6837
4d4ec087 6838 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6839 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6840 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6841
fc78f519 6842 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6843 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6844 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6845 kvm_update_cpuid(vcpu);
63f42e02
XG		 6846
6847 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6848 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6849 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6850 mmu_reset_needed = 1;
6851 }
63f42e02 6852 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6853
6854 if (mmu_reset_needed)
6855 kvm_mmu_reset_context(vcpu);
6856
a50abc3b 6857 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6858 pending_vec = find_first_bit(
6859 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6860 if (pending_vec < max_bits) {
66fd3f7f 6861 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6862 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6863 }
6864
3e6e0aab
GT		 6865 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6866 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6867 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6868 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6869 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6870 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6871
3e6e0aab
GT		 6872 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6873 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6874
5f0269f5
ME		 6875 update_cr8_intercept(vcpu);
6876
9c3e4aab 6877 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6878 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6879 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6880 !is_protmode(vcpu))
9c3e4aab
MT		 6881 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6882
3842d135
AK		 6883 kvm_make_request(KVM_REQ_EVENT, vcpu);
6884
b6c7a5dc
HB		 6885 return 0;
6886}
6887
d0bfb940
JK		 6888int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6889 struct kvm_guest_debug *dbg)
b6c7a5dc 6890{
355be0b9 6891 unsigned long rflags;
ae675ef0 6892 int i, r;
b6c7a5dc 6893
4f926bf2
JK		 6894 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6895 r = -EBUSY;
6896 if (vcpu->arch.exception.pending)
2122ff5e 6897 goto out;
4f926bf2
JK		 6898 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6899 kvm_queue_exception(vcpu, DB_VECTOR);
6900 else
6901 kvm_queue_exception(vcpu, BP_VECTOR);
6902 }
6903
91586a3b
JK		 6904 /*
6905 * Read rflags as long as potentially injected trace flags are still
6906 * filtered out.
6907 */
6908 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6909
6910 vcpu->guest_debug = dbg->control;
6911 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6912 vcpu->guest_debug = 0;
6913
6914 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6915 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6916 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6917 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6918 } else {
6919 for (i = 0; i < KVM_NR_DB_REGS; i++)
6920 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6921 }
c8639010 6922 kvm_update_dr7(vcpu);
ae675ef0 6923
f92653ee
JK		 6924 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6925 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6926 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6927
91586a3b
JK		 6928 /*
6929 * Trigger an rflags update that will inject or remove the trace
6930 * flags.
6931 */
6932 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6933
c8639010 6934 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6935
4f926bf2 6936 r = 0;
d0bfb940 6937
2122ff5e 6938out:
b6c7a5dc
HB		 6939
6940 return r;
6941}
6942
8b006791
ZX		 6943/*
6944 * Translate a guest virtual address to a guest physical address.
6945 */
6946int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6947 struct kvm_translation *tr)
6948{
6949 unsigned long vaddr = tr->linear_address;
6950 gpa_t gpa;
f656ce01 6951 int idx;
8b006791 6952
f656ce01 6953 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6954 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6955 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6956 tr->physical_address = gpa;
6957 tr->valid = gpa != UNMAPPED_GVA;
6958 tr->writeable = 1;
6959 tr->usermode = 0;
8b006791
ZX		 6960
6961 return 0;
6962}
6963
d0752060
HB		 6964int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6965{
c47ada30 6966 struct fxregs_state *fxsave =
7366ed77 6967 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6968
d0752060
HB		 6969 memcpy(fpu->fpr, fxsave->st_space, 128);
6970 fpu->fcw = fxsave->cwd;
6971 fpu->fsw = fxsave->swd;
6972 fpu->ftwx = fxsave->twd;
6973 fpu->last_opcode = fxsave->fop;
6974 fpu->last_ip = fxsave->rip;
6975 fpu->last_dp = fxsave->rdp;
6976 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6977
d0752060
HB		 6978 return 0;
6979}
6980
6981int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6982{
c47ada30 6983 struct fxregs_state *fxsave =
7366ed77 6984 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6985
d0752060
HB		 6986 memcpy(fxsave->st_space, fpu->fpr, 128);
6987 fxsave->cwd = fpu->fcw;
6988 fxsave->swd = fpu->fsw;
6989 fxsave->twd = fpu->ftwx;
6990 fxsave->fop = fpu->last_opcode;
6991 fxsave->rip = fpu->last_ip;
6992 fxsave->rdp = fpu->last_dp;
6993 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6994
d0752060
HB		 6995 return 0;
6996}
6997
0ee6a517 6998static void fx_init(struct kvm_vcpu *vcpu)
d0752060 6999{
bf935b0b 7000 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7001 if (cpu_has_xsaves)
7366ed77 7002 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7003 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7004
2acf923e
DC		 7005 /*
7006 * Ensure guest xcr0 is valid for loading
7007 */
7008 vcpu->arch.xcr0 = XSTATE_FP;
7009
ad312c7c 7010 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7011}
d0752060
HB		 7012
7013void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7014{
2608d7a1 7015 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7016 return;
7017
2acf923e
DC		 7018 /*
7019 * Restore all possible states in the guest,
7020 * and assume host would use all available bits.
7021 * Guest xcr0 would be loaded later.
7022 */
7023 kvm_put_guest_xcr0(vcpu);
d0752060 7024 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7025 __kernel_fpu_begin();
003e2e8b 7026 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7027 trace_kvm_fpu(1);
d0752060 7028}
d0752060
HB		 7029
7030void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7031{
2acf923e
DC		 7032 kvm_put_guest_xcr0(vcpu);
7033
653f52c3
RR		 7034 if (!vcpu->guest_fpu_loaded) {
7035 vcpu->fpu_counter = 0;
d0752060 7036 return;
653f52c3 7037 }
d0752060
HB		 7038
7039 vcpu->guest_fpu_loaded = 0;
4f836347 7040 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7041 __kernel_fpu_end();
f096ed85 7042 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7043 /*
7044 * If using eager FPU mode, or if the guest is a frequent user
7045 * of the FPU, just leave the FPU active for next time.
7046 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7047 * the FPU in bursts will revert to loading it on demand.
7048 */
a9b4fb7e 7049 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7050 if (++vcpu->fpu_counter < 5)
7051 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7052 }
0c04851c 7053 trace_kvm_fpu(0);
d0752060 7054}
e9b11c17
ZX		 7055
7056void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7057{
12f9a48f 7058 kvmclock_reset(vcpu);
7f1ea208 7059
f5f48ee1 7060 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7061 kvm_x86_ops->vcpu_free(vcpu);
7062}
7063
7064struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7065 unsigned int id)
7066{
c447e76b
LL		 7067 struct kvm_vcpu *vcpu;
7068
6755bae8
ZA		 7069 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7070 printk_once(KERN_WARNING
7071 "kvm: SMP vm created on host with unstable TSC; "
7072 "guest TSC will not be reliable\n");
c447e76b
LL		 7073
7074 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7075
c447e76b 7076 return vcpu;
26e5215f 7077}
e9b11c17 7078
26e5215f
AK		 7079int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7080{
7081 int r;
e9b11c17 7082
19efffa2 7083 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7084 r = vcpu_load(vcpu);
7085 if (r)
7086 return r;
d28bc9dd 7087 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7088 kvm_mmu_setup(vcpu);
e9b11c17 7089 vcpu_put(vcpu);
26e5215f 7090 return r;
e9b11c17
ZX		 7091}
7092
31928aa5 7093void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7094{
8fe8ab46 7095 struct msr_data msr;
332967a3 7096 struct kvm *kvm = vcpu->kvm;
42897d86 7097
31928aa5
DD		 7098 if (vcpu_load(vcpu))
7099 return;
8fe8ab46
WA		 7100 msr.data = 0x0;
7101 msr.index = MSR_IA32_TSC;
7102 msr.host_initiated = true;
7103 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7104 vcpu_put(vcpu);
7105
630994b3
MT		 7106 if (!kvmclock_periodic_sync)
7107 return;
7108
332967a3
AJ		 7109 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7110 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7111}
7112
d40ccc62 7113void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7114{
9fc77441 7115 int r;
344d9588
GN		 7116 vcpu->arch.apf.msr_val = 0;
7117
9fc77441
MT		 7118 r = vcpu_load(vcpu);
7119 BUG_ON(r);
e9b11c17
ZX		 7120 kvm_mmu_unload(vcpu);
7121 vcpu_put(vcpu);
7122
7123 kvm_x86_ops->vcpu_free(vcpu);
7124}
7125
d28bc9dd 7126void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7127{
e69fab5d
PB		 7128 vcpu->arch.hflags = 0;
7129
7460fb4a
AK		 7130 atomic_set(&vcpu->arch.nmi_queued, 0);
7131 vcpu->arch.nmi_pending = 0;
448fa4a9 7132 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7133 kvm_clear_interrupt_queue(vcpu);
7134 kvm_clear_exception_queue(vcpu);
448fa4a9 7135
42dbaa5a 7136 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7137 kvm_update_dr0123(vcpu);
6f43ed01 7138 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7139 kvm_update_dr6(vcpu);
42dbaa5a 7140 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7141 kvm_update_dr7(vcpu);
42dbaa5a 7142
1119022c
NA		 7143 vcpu->arch.cr2 = 0;
7144
3842d135 7145 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7146 vcpu->arch.apf.msr_val = 0;
c9aaa895 7147 vcpu->arch.st.msr_val = 0;
3842d135 7148
12f9a48f
GC		 7149 kvmclock_reset(vcpu);
7150
af585b92
GN		 7151 kvm_clear_async_pf_completion_queue(vcpu);
7152 kvm_async_pf_hash_reset(vcpu);
7153 vcpu->arch.apf.halted = false;
3842d135 7154
64d60670 7155 if (!init_event) {
d28bc9dd 7156 kvm_pmu_reset(vcpu);
64d60670
PB		 7157 vcpu->arch.smbase = 0x30000;
7158 }
f5132b01 7159
66f7b72e
JS		 7160 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7161 vcpu->arch.regs_avail = ~0;
7162 vcpu->arch.regs_dirty = ~0;
7163
d28bc9dd 7164 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7165}
7166
2b4a273b 7167void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7168{
7169 struct kvm_segment cs;
7170
7171 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7172 cs.selector = vector << 8;
7173 cs.base = vector << 12;
7174 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7175 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7176}
7177
13a34e06 7178int kvm_arch_hardware_enable(void)
e9b11c17 7179{
ca84d1a2
ZA		 7180 struct kvm *kvm;
7181 struct kvm_vcpu *vcpu;
7182 int i;
0dd6a6ed
ZA		 7183 int ret;
7184 u64 local_tsc;
7185 u64 max_tsc = 0;
7186 bool stable, backwards_tsc = false;
18863bdd
AK		 7187
7188 kvm_shared_msr_cpu_online();
13a34e06 7189 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7190 if (ret != 0)
7191 return ret;
7192
7193 local_tsc = native_read_tsc();
7194 stable = !check_tsc_unstable();
7195 list_for_each_entry(kvm, &vm_list, vm_list) {
7196 kvm_for_each_vcpu(i, vcpu, kvm) {
7197 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7199 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7200 backwards_tsc = true;
7201 if (vcpu->arch.last_host_tsc > max_tsc)
7202 max_tsc = vcpu->arch.last_host_tsc;
7203 }
7204 }
7205 }
7206
7207 /*
7208 * Sometimes, even reliable TSCs go backwards. This happens on
7209 * platforms that reset TSC during suspend or hibernate actions, but
7210 * maintain synchronization. We must compensate. Fortunately, we can
7211 * detect that condition here, which happens early in CPU bringup,
7212 * before any KVM threads can be running. Unfortunately, we can't
7213 * bring the TSCs fully up to date with real time, as we aren't yet far
7214 * enough into CPU bringup that we know how much real time has actually
7215 * elapsed; our helper function, get_kernel_ns() will be using boot
7216 * variables that haven't been updated yet.
7217 *
7218 * So we simply find the maximum observed TSC above, then record the
7219 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7220 * the adjustment will be applied. Note that we accumulate
7221 * adjustments, in case multiple suspend cycles happen before some VCPU
7222 * gets a chance to run again. In the event that no KVM threads get a
7223 * chance to run, we will miss the entire elapsed period, as we'll have
7224 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7225 * loose cycle time. This isn't too big a deal, since the loss will be
7226 * uniform across all VCPUs (not to mention the scenario is extremely
7227 * unlikely). It is possible that a second hibernate recovery happens
7228 * much faster than a first, causing the observed TSC here to be
7229 * smaller; this would require additional padding adjustment, which is
7230 * why we set last_host_tsc to the local tsc observed here.
7231 *
7232 * N.B. - this code below runs only on platforms with reliable TSC,
7233 * as that is the only way backwards_tsc is set above. Also note
7234 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7235 * have the same delta_cyc adjustment applied if backwards_tsc
7236 * is detected. Note further, this adjustment is only done once,
7237 * as we reset last_host_tsc on all VCPUs to stop this from being
7238 * called multiple times (one for each physical CPU bringup).
7239 *
4a969980 7240 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7241 * will be compensated by the logic in vcpu_load, which sets the TSC to
7242 * catchup mode. This will catchup all VCPUs to real time, but cannot
7243 * guarantee that they stay in perfect synchronization.
7244 */
7245 if (backwards_tsc) {
7246 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7247 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7248 list_for_each_entry(kvm, &vm_list, vm_list) {
7249 kvm_for_each_vcpu(i, vcpu, kvm) {
7250 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7251 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7252 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7253 }
7254
7255 /*
7256 * We have to disable TSC offset matching.. if you were
7257 * booting a VM while issuing an S4 host suspend....
7258 * you may have some problem. Solving this issue is
7259 * left as an exercise to the reader.
7260 */
7261 kvm->arch.last_tsc_nsec = 0;
7262 kvm->arch.last_tsc_write = 0;
7263 }
7264
7265 }
7266 return 0;
e9b11c17
ZX		 7267}
7268
13a34e06 7269void kvm_arch_hardware_disable(void)
e9b11c17 7270{
13a34e06
RK		 7271 kvm_x86_ops->hardware_disable();
7272 drop_user_return_notifiers();
e9b11c17
ZX		 7273}
7274
7275int kvm_arch_hardware_setup(void)
7276{
9e9c3fe4
NA		 7277 int r;
7278
7279 r = kvm_x86_ops->hardware_setup();
7280 if (r != 0)
7281 return r;
7282
7283 kvm_init_msr_list();
7284 return 0;
e9b11c17
ZX		 7285}
7286
7287void kvm_arch_hardware_unsetup(void)
7288{
7289 kvm_x86_ops->hardware_unsetup();
7290}
7291
7292void kvm_arch_check_processor_compat(void *rtn)
7293{
7294 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7295}
7296
7297bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7298{
7299 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7300}
7301EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7302
7303bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7304{
7305 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7306}
7307
3e515705
AK		 7308bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7309{
7310 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7311}
7312
54e9818f
GN		 7313struct static_key kvm_no_apic_vcpu __read_mostly;
7314
e9b11c17
ZX		 7315int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7316{
7317 struct page *page;
7318 struct kvm *kvm;
7319 int r;
7320
7321 BUG_ON(vcpu->kvm == NULL);
7322 kvm = vcpu->kvm;
7323
6aef266c 7324 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7325 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7326 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7327 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7328 else
a4535290 7329 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7330
7331 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7332 if (!page) {
7333 r = -ENOMEM;
7334 goto fail;
7335 }
ad312c7c 7336 vcpu->arch.pio_data = page_address(page);
e9b11c17 7337
cc578287 7338 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7339
e9b11c17
ZX		 7340 r = kvm_mmu_create(vcpu);
7341 if (r < 0)
7342 goto fail_free_pio_data;
7343
7344 if (irqchip_in_kernel(kvm)) {
7345 r = kvm_create_lapic(vcpu);
7346 if (r < 0)
7347 goto fail_mmu_destroy;
54e9818f
GN		 7348 } else
7349 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7350
890ca9ae
HY		 7351 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7352 GFP_KERNEL);
7353 if (!vcpu->arch.mce_banks) {
7354 r = -ENOMEM;
443c39bc 7355 goto fail_free_lapic;
890ca9ae
HY		 7356 }
7357 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7358
f1797359
WY		 7359 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7360 r = -ENOMEM;
f5f48ee1 7361 goto fail_free_mce_banks;
f1797359 7362 }
f5f48ee1 7363
0ee6a517 7364 fx_init(vcpu);
66f7b72e 7365
ba904635 7366 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7367 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7368
7369 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7370 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7371
5a4f55cd
EK		 7372 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7373
74545705
RK		 7374 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7375
af585b92 7376 kvm_async_pf_hash_reset(vcpu);
f5132b01 7377 kvm_pmu_init(vcpu);
af585b92 7378
e9b11c17 7379 return 0;
0ee6a517 7380
f5f48ee1
SY		 7381fail_free_mce_banks:
7382 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7383fail_free_lapic:
7384 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7385fail_mmu_destroy:
7386 kvm_mmu_destroy(vcpu);
7387fail_free_pio_data:
ad312c7c 7388 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7389fail:
7390 return r;
7391}
7392
7393void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7394{
f656ce01
MT		 7395 int idx;
7396
f5132b01 7397 kvm_pmu_destroy(vcpu);
36cb93fd 7398 kfree(vcpu->arch.mce_banks);
e9b11c17 7399 kvm_free_lapic(vcpu);
f656ce01 7400 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7401 kvm_mmu_destroy(vcpu);
f656ce01 7402 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7403 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7404 if (!irqchip_in_kernel(vcpu->kvm))
7405 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7406}
d19a9cd2 7407
e790d9ef
RK		 7408void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7409{
ae97a3b8 7410 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7411}
7412
e08b9637 7413int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7414{
e08b9637
CO		 7415 if (type)
7416 return -EINVAL;
7417
6ef768fa 7418 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7419 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7420 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7421 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7422 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7423
5550af4d
SY		 7424 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7425 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7426 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7427 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7428 &kvm->arch.irq_sources_bitmap);
5550af4d 7429
038f8c11 7430 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7431 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7432 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7433
7434 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7435
7e44e449 7436 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7437 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7438
d89f5eff 7439 return 0;
d19a9cd2
ZX		 7440}
7441
7442static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7443{
9fc77441
MT		 7444 int r;
7445 r = vcpu_load(vcpu);
7446 BUG_ON(r);
d19a9cd2
ZX		 7447 kvm_mmu_unload(vcpu);
7448 vcpu_put(vcpu);
7449}
7450
7451static void kvm_free_vcpus(struct kvm *kvm)
7452{
7453 unsigned int i;
988a2cae 7454 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7455
7456 /*
7457 * Unpin any mmu pages first.
7458 */
af585b92
GN		 7459 kvm_for_each_vcpu(i, vcpu, kvm) {
7460 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7461 kvm_unload_vcpu_mmu(vcpu);
af585b92 7462 }
988a2cae
GN		 7463 kvm_for_each_vcpu(i, vcpu, kvm)
7464 kvm_arch_vcpu_free(vcpu);
7465
7466 mutex_lock(&kvm->lock);
7467 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7468 kvm->vcpus[i] = NULL;
d19a9cd2 7469
988a2cae
GN		 7470 atomic_set(&kvm->online_vcpus, 0);
7471 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7472}
7473
ad8ba2cd
SY		 7474void kvm_arch_sync_events(struct kvm *kvm)
7475{
332967a3 7476 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7477 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7478 kvm_free_all_assigned_devices(kvm);
aea924f6 7479 kvm_free_pit(kvm);
ad8ba2cd
SY		 7480}
7481
9da0e4d5
PB		 7482int __x86_set_memory_region(struct kvm *kvm,
7483 const struct kvm_userspace_memory_region *mem)
7484{
7485 int i, r;
7486
7487 /* Called with kvm->slots_lock held. */
7488 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7489
7490 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7491 struct kvm_userspace_memory_region m = *mem;
7492
7493 m.slot |= i << 16;
7494 r = __kvm_set_memory_region(kvm, &m);
7495 if (r < 0)
7496 return r;
7497 }
7498
7499 return 0;
7500}
7501EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7502
7503int x86_set_memory_region(struct kvm *kvm,
7504 const struct kvm_userspace_memory_region *mem)
7505{
7506 int r;
7507
7508 mutex_lock(&kvm->slots_lock);
7509 r = __x86_set_memory_region(kvm, mem);
7510 mutex_unlock(&kvm->slots_lock);
7511
7512 return r;
7513}
7514EXPORT_SYMBOL_GPL(x86_set_memory_region);
7515
d19a9cd2
ZX		 7516void kvm_arch_destroy_vm(struct kvm *kvm)
7517{
27469d29
AH		 7518 if (current->mm == kvm->mm) {
7519 /*
7520 * Free memory regions allocated on behalf of userspace,
7521 * unless the the memory map has changed due to process exit
7522 * or fd copying.
7523 */
7524 struct kvm_userspace_memory_region mem;
7525 memset(&mem, 0, sizeof(mem));
7526 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7527 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7528
7529 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7530 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7531
7532 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7533 x86_set_memory_region(kvm, &mem);
27469d29 7534 }
6eb55818 7535 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7536 kfree(kvm->arch.vpic);
7537 kfree(kvm->arch.vioapic);
d19a9cd2 7538 kvm_free_vcpus(kvm);
1e08ec4a 7539 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7540}
0de10343 7541
5587027c 7542void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7543 struct kvm_memory_slot *dont)
7544{
7545 int i;
7546
d89cc617
TY		 7547 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7548 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7549 kvfree(free->arch.rmap[i]);
d89cc617 7550 free->arch.rmap[i] = NULL;
77d11309 7551 }
d89cc617
TY		 7552 if (i == 0)
7553 continue;
7554
7555 if (!dont || free->arch.lpage_info[i - 1] !=
7556 dont->arch.lpage_info[i - 1]) {
548ef284 7557 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7558 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7559 }
7560 }
7561}
7562
5587027c
AK		 7563int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7564 unsigned long npages)
db3fe4eb
TY		 7565{
7566 int i;
7567
d89cc617 7568 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7569 unsigned long ugfn;
7570 int lpages;
d89cc617 7571 int level = i + 1;
db3fe4eb
TY		 7572
7573 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7574 slot->base_gfn, level) + 1;
7575
d89cc617
TY		 7576 slot->arch.rmap[i] =
7577 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7578 if (!slot->arch.rmap[i])
77d11309 7579 goto out_free;
d89cc617
TY		 7580 if (i == 0)
7581 continue;
77d11309 7582
d89cc617
TY		 7583 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7584 sizeof(*slot->arch.lpage_info[i - 1]));
7585 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7586 goto out_free;
7587
7588 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7589 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7590 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7591 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7592 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7593 /*
7594 * If the gfn and userspace address are not aligned wrt each
7595 * other, or if explicitly asked to, disable large page
7596 * support for this slot
7597 */
7598 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7599 !kvm_largepages_enabled()) {
7600 unsigned long j;
7601
7602 for (j = 0; j < lpages; ++j)
d89cc617 7603 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7604 }
7605 }
7606
7607 return 0;
7608
7609out_free:
d89cc617 7610 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7611 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7612 slot->arch.rmap[i] = NULL;
7613 if (i == 0)
7614 continue;
7615
548ef284 7616 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7617 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7618 }
7619 return -ENOMEM;
7620}
7621
15f46015 7622void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7623{
e6dff7d1
TY		 7624 /*
7625 * memslots->generation has been incremented.
7626 * mmio generation may have reached its maximum value.
7627 */
54bf36aa 7628 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7629}
7630
f7784b8e
MT		 7631int kvm_arch_prepare_memory_region(struct kvm *kvm,
7632 struct kvm_memory_slot *memslot,
09170a49 7633 const struct kvm_userspace_memory_region *mem,
7b6195a9 7634 enum kvm_mr_change change)
0de10343 7635{
7a905b14
TY		 7636 /*
7637 * Only private memory slots need to be mapped here since
7638 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7639 */
7b6195a9 7640 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7641 unsigned long userspace_addr;
604b38ac 7642
7a905b14
TY		 7643 /*
7644 * MAP_SHARED to prevent internal slot pages from being moved
7645 * by fork()/COW.
7646 */
7b6195a9 7647 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7648 PROT_READ | PROT_WRITE,
7649 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7650
7a905b14
TY		 7651 if (IS_ERR((void *)userspace_addr))
7652 return PTR_ERR((void *)userspace_addr);
604b38ac 7653
7a905b14 7654 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7655 }
7656
f7784b8e
MT		 7657 return 0;
7658}
7659
88178fd4
KH		 7660static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7661 struct kvm_memory_slot *new)
7662{
7663 /* Still write protect RO slot */
7664 if (new->flags & KVM_MEM_READONLY) {
7665 kvm_mmu_slot_remove_write_access(kvm, new);
7666 return;
7667 }
7668
7669 /*
7670 * Call kvm_x86_ops dirty logging hooks when they are valid.
7671 *
7672 * kvm_x86_ops->slot_disable_log_dirty is called when:
7673 *
7674 * - KVM_MR_CREATE with dirty logging is disabled
7675 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7676 *
7677 * The reason is, in case of PML, we need to set D-bit for any slots
7678 * with dirty logging disabled in order to eliminate unnecessary GPA
7679 * logging in PML buffer (and potential PML buffer full VMEXT). This
7680 * guarantees leaving PML enabled during guest's lifetime won't have
7681 * any additonal overhead from PML when guest is running with dirty
7682 * logging disabled for memory slots.
7683 *
7684 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7685 * to dirty logging mode.
7686 *
7687 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7688 *
7689 * In case of write protect:
7690 *
7691 * Write protect all pages for dirty logging.
7692 *
7693 * All the sptes including the large sptes which point to this
7694 * slot are set to readonly. We can not create any new large
7695 * spte on this slot until the end of the logging.
7696 *
7697 * See the comments in fast_page_fault().
7698 */
7699 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7700 if (kvm_x86_ops->slot_enable_log_dirty)
7701 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7702 else
7703 kvm_mmu_slot_remove_write_access(kvm, new);
7704 } else {
7705 if (kvm_x86_ops->slot_disable_log_dirty)
7706 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7707 }
7708}
7709
f7784b8e 7710void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7711 const struct kvm_userspace_memory_region *mem,
8482644a 7712 const struct kvm_memory_slot *old,
f36f3f28 7713 const struct kvm_memory_slot *new,
8482644a 7714 enum kvm_mr_change change)
f7784b8e 7715{
8482644a 7716 int nr_mmu_pages = 0;
f7784b8e 7717
f36f3f28 7718 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7719 int ret;
7720
8482644a
TY		 7721 ret = vm_munmap(old->userspace_addr,
7722 old->npages * PAGE_SIZE);
f7784b8e
MT		 7723 if (ret < 0)
7724 printk(KERN_WARNING
7725 "kvm_vm_ioctl_set_memory_region: "
7726 "failed to munmap memory\n");
7727 }
7728
48c0e4e9
XG		 7729 if (!kvm->arch.n_requested_mmu_pages)
7730 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7731
48c0e4e9 7732 if (nr_mmu_pages)
0de10343 7733 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7734
3ea3b7fa
WL		 7735 /*
7736 * Dirty logging tracks sptes in 4k granularity, meaning that large
7737 * sptes have to be split. If live migration is successful, the guest
7738 * in the source machine will be destroyed and large sptes will be
7739 * created in the destination. However, if the guest continues to run
7740 * in the source machine (for example if live migration fails), small
7741 * sptes will remain around and cause bad performance.
7742 *
7743 * Scan sptes if dirty logging has been stopped, dropping those
7744 * which can be collapsed into a single large-page spte. Later
7745 * page faults will create the large-page sptes.
7746 */
7747 if ((change != KVM_MR_DELETE) &&
7748 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7749 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7750 kvm_mmu_zap_collapsible_sptes(kvm, new);
7751
c972f3b1 7752 /*
88178fd4 7753 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7754 *
88178fd4
KH		 7755 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7756 * been zapped so no dirty logging staff is needed for old slot. For
7757 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7758 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7759 *
7760 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7761 */
88178fd4 7762 if (change != KVM_MR_DELETE)
f36f3f28 7763 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7764}
1d737c8a 7765
2df72e9b 7766void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7767{
6ca18b69 7768 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7769}
7770
2df72e9b
MT		 7771void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7772 struct kvm_memory_slot *slot)
7773{
6ca18b69 7774 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7775}
7776
1d737c8a
ZX		 7777int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7778{
b6b8a145
JK		 7779 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7780 kvm_x86_ops->check_nested_events(vcpu, false);
7781
af585b92
GN		 7782 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7783 !vcpu->arch.apf.halted)
7784 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7785 || kvm_apic_has_events(vcpu)
6aef266c 7786 || vcpu->arch.pv.pv_unhalted
7460fb4a 7787 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7788 (kvm_arch_interrupt_allowed(vcpu) &&
7789 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7790}
5736199a 7791
b6d33834 7792int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7793{
b6d33834 7794 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7795}
78646121
GN		 7796
7797int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7798{
7799 return kvm_x86_ops->interrupt_allowed(vcpu);
7800}
229456fc 7801
82b32774 7802unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7803{
82b32774
NA		 7804 if (is_64_bit_mode(vcpu))
7805 return kvm_rip_read(vcpu);
7806 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7807 kvm_rip_read(vcpu));
7808}
7809EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7810
82b32774
NA		 7811bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7812{
7813 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7814}
7815EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7816
94fe45da
JK		 7817unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7818{
7819 unsigned long rflags;
7820
7821 rflags = kvm_x86_ops->get_rflags(vcpu);
7822 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7823 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7824 return rflags;
7825}
7826EXPORT_SYMBOL_GPL(kvm_get_rflags);
7827
6addfc42 7828static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7829{
7830 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7831 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7832 rflags |= X86_EFLAGS_TF;
94fe45da 7833 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7834}
7835
7836void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7837{
7838 __kvm_set_rflags(vcpu, rflags);
3842d135 7839 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7840}
7841EXPORT_SYMBOL_GPL(kvm_set_rflags);
7842
56028d08
GN		 7843void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7844{
7845 int r;
7846
fb67e14f 7847 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7848 work->wakeup_all)
56028d08
GN		 7849 return;
7850
7851 r = kvm_mmu_reload(vcpu);
7852 if (unlikely(r))
7853 return;
7854
fb67e14f
XG		 7855 if (!vcpu->arch.mmu.direct_map &&
7856 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7857 return;
7858
56028d08
GN		 7859 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7860}
7861
af585b92
GN		 7862static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7863{
7864 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7865}
7866
7867static inline u32 kvm_async_pf_next_probe(u32 key)
7868{
7869 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7870}
7871
7872static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7873{
7874 u32 key = kvm_async_pf_hash_fn(gfn);
7875
7876 while (vcpu->arch.apf.gfns[key] != ~0)
7877 key = kvm_async_pf_next_probe(key);
7878
7879 vcpu->arch.apf.gfns[key] = gfn;
7880}
7881
7882static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7883{
7884 int i;
7885 u32 key = kvm_async_pf_hash_fn(gfn);
7886
7887 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7888 (vcpu->arch.apf.gfns[key] != gfn &&
7889 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7890 key = kvm_async_pf_next_probe(key);
7891
7892 return key;
7893}
7894
7895bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7896{
7897 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7898}
7899
7900static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7901{
7902 u32 i, j, k;
7903
7904 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7905 while (true) {
7906 vcpu->arch.apf.gfns[i] = ~0;
7907 do {
7908 j = kvm_async_pf_next_probe(j);
7909 if (vcpu->arch.apf.gfns[j] == ~0)
7910 return;
7911 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7912 /*
7913 * k lies cyclically in ]i,j]
7914 * | i.k.j |
7915 * |....j i.k.| or |.k..j i...|
7916 */
7917 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7918 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7919 i = j;
7920 }
7921}
7922
7c90705b
GN		 7923static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7924{
7925
7926 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7927 sizeof(val));
7928}
7929
af585b92
GN		 7930void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7931 struct kvm_async_pf *work)
7932{
6389ee94
AK		 7933 struct x86_exception fault;
7934
7c90705b 7935 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7936 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7937
7938 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7939 (vcpu->arch.apf.send_user_only &&
7940 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7941 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7942 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7943 fault.vector = PF_VECTOR;
7944 fault.error_code_valid = true;
7945 fault.error_code = 0;
7946 fault.nested_page_fault = false;
7947 fault.address = work->arch.token;
7948 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7949 }
af585b92
GN		 7950}
7951
7952void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7953 struct kvm_async_pf *work)
7954{
6389ee94
AK		 7955 struct x86_exception fault;
7956
7c90705b 7957 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7958 if (work->wakeup_all)
7c90705b
GN		 7959 work->arch.token = ~0; /* broadcast wakeup */
7960 else
7961 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7962
7963 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7964 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7965 fault.vector = PF_VECTOR;
7966 fault.error_code_valid = true;
7967 fault.error_code = 0;
7968 fault.nested_page_fault = false;
7969 fault.address = work->arch.token;
7970 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7971 }
e6d53e3b 7972 vcpu->arch.apf.halted = false;
a4fa1635 7973 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7974}
7975
7976bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7977{
7978 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7979 return true;
7980 else
7981 return !kvm_event_needs_reinjection(vcpu) &&
7982 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7983}
7984
5544eb9b
PB		 7985void kvm_arch_start_assignment(struct kvm *kvm)
7986{
7987 atomic_inc(&kvm->arch.assigned_device_count);
7988}
7989EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
7990
7991void kvm_arch_end_assignment(struct kvm *kvm)
7992{
7993 atomic_dec(&kvm->arch.assigned_device_count);
7994}
7995EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
7996
7997bool kvm_arch_has_assigned_device(struct kvm *kvm)
7998{
7999 return atomic_read(&kvm->arch.assigned_device_count);
8000}
8001EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8002
e0f0bbc5
AW		 8003void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8004{
8005 atomic_inc(&kvm->arch.noncoherent_dma_count);
8006}
8007EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8008
8009void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8010{
8011 atomic_dec(&kvm->arch.noncoherent_dma_count);
8012}
8013EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8014
8015bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8016{
8017 return atomic_read(&kvm->arch.noncoherent_dma_count);
8018}
8019EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8020
229456fc
MT		 8021EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8022EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8023EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8024EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8025EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8026EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8027EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8028EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8029EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8030EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8031EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8032EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8033EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8034EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8035EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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