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KVM: x86 emulator: vendor specific instructions
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
db8fcefa 337void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 338{
db8fcefa
AP		 339 if (err)
340 kvm_inject_gp(vcpu, 0);
341 else
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
343}
344EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 345
6389ee94 346void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 347{
348 ++vcpu->stat.pf_guest;
6389ee94
AK		 349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 351}
352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
3842d135 363 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 364 vcpu->arch.nmi_pending = 1;
365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
9f8fe504
AK		 476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 522 kvm_read_cr3(vcpu)))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
e5f3f027
XG		 528 if ((cr0 ^ old_cr0) & X86_CR0_PG)
529 kvm_clear_async_pf_completion_queue(vcpu);
530
aad82703
SY		 531 if ((cr0 ^ old_cr0) & update_bits)
532 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 533 return 0;
534}
2d3ad1f4 535EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 536
2d3ad1f4 537void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 538{
49a9b07e 539 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 542
2acf923e
DC		 543int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
544{
545 u64 xcr0;
546
547 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
548 if (index != XCR_XFEATURE_ENABLED_MASK)
549 return 1;
550 xcr0 = xcr;
551 if (kvm_x86_ops->get_cpl(vcpu) != 0)
552 return 1;
553 if (!(xcr0 & XSTATE_FP))
554 return 1;
555 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
556 return 1;
557 if (xcr0 & ~host_xcr0)
558 return 1;
559 vcpu->arch.xcr0 = xcr0;
560 vcpu->guest_xcr0_loaded = 0;
561 return 0;
562}
563
564int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
565{
566 if (__kvm_set_xcr(vcpu, index, xcr)) {
567 kvm_inject_gp(vcpu, 0);
568 return 1;
569 }
570 return 0;
571}
572EXPORT_SYMBOL_GPL(kvm_set_xcr);
573
574static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
580}
581
582static void update_cpuid(struct kvm_vcpu *vcpu)
583{
584 struct kvm_cpuid_entry2 *best;
585
586 best = kvm_find_cpuid_entry(vcpu, 1, 0);
587 if (!best)
588 return;
589
590 /* Update OSXSAVE bit */
591 if (cpu_has_xsave && best->function == 0x1) {
592 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
593 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
594 best->ecx |= bit(X86_FEATURE_OSXSAVE);
595 }
596}
597
a83b29c6 598int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 599{
fc78f519 600 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 601 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
602
0f12244f
GN		 603 if (cr4 & CR4_RESERVED_BITS)
604 return 1;
a03490ed 605
2acf923e
DC		 606 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
607 return 1;
608
a03490ed 609 if (is_long_mode(vcpu)) {
0f12244f
GN		 610 if (!(cr4 & X86_CR4_PAE))
611 return 1;
a2edf57f
AK		 612 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
613 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 614 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
615 kvm_read_cr3(vcpu)))
0f12244f
GN		 616 return 1;
617
618 if (cr4 & X86_CR4_VMXE)
619 return 1;
a03490ed 620
a03490ed 621 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 622
aad82703
SY		 623 if ((cr4 ^ old_cr4) & pdptr_bits)
624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e
DC		 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627 update_cpuid(vcpu);
628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
0f12244f
GN		 642 if (cr3 & CR3_L_MODE_RESERVED_BITS)
643 return 1;
a03490ed
CO		 644 } else {
645 if (is_pae(vcpu)) {
0f12244f
GN		 646 if (cr3 & CR3_PAE_RESERVED_BITS)
647 return 1;
ff03a073
JR		 648 if (is_paging(vcpu) &&
649 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 650 return 1;
a03490ed
CO		 651 }
652 /*
653 * We don't check reserved bits in nonpae mode, because
654 * this isn't enforced, and VMware depends on this.
655 */
656 }
657
a03490ed
CO		 658 /*
659 * Does the new cr3 value map to physical memory? (Note, we
660 * catch an invalid cr3 even in real-mode, because it would
661 * cause trouble later on when we turn on paging anyway.)
662 *
663 * A real CPU would silently accept an invalid cr3 and would
664 * attempt to use it - with largely undefined (and often hard
665 * to debug) behavior on the guest side.
666 */
667 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 668 return 1;
669 vcpu->arch.cr3 = cr3;
aff48baa 670 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 671 vcpu->arch.mmu.new_cr3(vcpu);
672 return 0;
673}
2d3ad1f4 674EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 675
eea1cff9 676int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 677{
0f12244f
GN		 678 if (cr8 & CR8_RESERVED_BITS)
679 return 1;
a03490ed
CO		 680 if (irqchip_in_kernel(vcpu->kvm))
681 kvm_lapic_set_tpr(vcpu, cr8);
682 else
ad312c7c 683 vcpu->arch.cr8 = cr8;
0f12244f
GN		 684 return 0;
685}
2d3ad1f4 686EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 687
2d3ad1f4 688unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 689{
690 if (irqchip_in_kernel(vcpu->kvm))
691 return kvm_lapic_get_cr8(vcpu);
692 else
ad312c7c 693 return vcpu->arch.cr8;
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 696
338dbc97 697static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 698{
699 switch (dr) {
700 case 0 ... 3:
701 vcpu->arch.db[dr] = val;
702 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
703 vcpu->arch.eff_db[dr] = val;
704 break;
705 case 4:
338dbc97
GN		 706 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
707 return 1; /* #UD */
020df079
GN		 708 /* fall through */
709 case 6:
338dbc97
GN		 710 if (val & 0xffffffff00000000ULL)
711 return -1; /* #GP */
020df079
GN		 712 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
713 break;
714 case 5:
338dbc97
GN		 715 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
716 return 1; /* #UD */
020df079
GN		 717 /* fall through */
718 default: /* 7 */
338dbc97
GN		 719 if (val & 0xffffffff00000000ULL)
720 return -1; /* #GP */
020df079
GN		 721 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
722 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
723 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
724 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
725 }
726 break;
727 }
728
729 return 0;
730}
338dbc97
GN		 731
732int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
733{
734 int res;
735
736 res = __kvm_set_dr(vcpu, dr, val);
737 if (res > 0)
738 kvm_queue_exception(vcpu, UD_VECTOR);
739 else if (res < 0)
740 kvm_inject_gp(vcpu, 0);
741
742 return res;
743}
020df079
GN		 744EXPORT_SYMBOL_GPL(kvm_set_dr);
745
338dbc97 746static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 747{
748 switch (dr) {
749 case 0 ... 3:
750 *val = vcpu->arch.db[dr];
751 break;
752 case 4:
338dbc97 753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 754 return 1;
020df079
GN		 755 /* fall through */
756 case 6:
757 *val = vcpu->arch.dr6;
758 break;
759 case 5:
338dbc97 760 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 761 return 1;
020df079
GN		 762 /* fall through */
763 default: /* 7 */
764 *val = vcpu->arch.dr7;
765 break;
766 }
767
768 return 0;
769}
338dbc97
GN		 770
771int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
772{
773 if (_kvm_get_dr(vcpu, dr, val)) {
774 kvm_queue_exception(vcpu, UD_VECTOR);
775 return 1;
776 }
777 return 0;
778}
020df079
GN		 779EXPORT_SYMBOL_GPL(kvm_get_dr);
780
043405e1
CO		 781/*
782 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
783 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
784 *
785 * This list is modified at module load time to reflect the
e3267cbb
GC		 786 * capabilities of the host cpu. This capabilities test skips MSRs that are
787 * kvm-specific. Those are put in the beginning of the list.
043405e1 788 */
e3267cbb 789
344d9588 790#define KVM_SAVE_MSRS_BEGIN 8
043405e1 791static u32 msrs_to_save[] = {
e3267cbb 792 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 793 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 794 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 795 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 796 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 797 MSR_STAR,
043405e1
CO		 798#ifdef CONFIG_X86_64
799 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
800#endif
e90aa41e 801 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 802};
803
804static unsigned num_msrs_to_save;
805
806static u32 emulated_msrs[] = {
807 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 808 MSR_IA32_MCG_STATUS,
809 MSR_IA32_MCG_CTL,
043405e1
CO		 810};
811
b69e8cae 812static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 813{
aad82703
SY		 814 u64 old_efer = vcpu->arch.efer;
815
b69e8cae
RJ		 816 if (efer & efer_reserved_bits)
817 return 1;
15c4a640
CO		 818
819 if (is_paging(vcpu)
b69e8cae
RJ		 820 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
821 return 1;
15c4a640 822
1b2fd70c
AG		 823 if (efer & EFER_FFXSR) {
824 struct kvm_cpuid_entry2 *feat;
825
826 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 827 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
828 return 1;
1b2fd70c
AG		 829 }
830
d8017474
AG		 831 if (efer & EFER_SVME) {
832 struct kvm_cpuid_entry2 *feat;
833
834 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 835 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
836 return 1;
d8017474
AG		 837 }
838
15c4a640 839 efer &= ~EFER_LMA;
f6801dff 840 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 841
a3d204e2
SY		 842 kvm_x86_ops->set_efer(vcpu, efer);
843
9645bb56 844 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 845
aad82703
SY		 846 /* Update reserved bits */
847 if ((efer ^ old_efer) & EFER_NX)
848 kvm_mmu_reset_context(vcpu);
849
b69e8cae 850 return 0;
15c4a640
CO		 851}
852
f2b4b7dd
JR		 853void kvm_enable_efer_bits(u64 mask)
854{
855 efer_reserved_bits &= ~mask;
856}
857EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
858
859
15c4a640
CO		 860/*
861 * Writes msr value into into the appropriate "register".
862 * Returns 0 on success, non-0 otherwise.
863 * Assumes vcpu_load() was already called.
864 */
865int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
866{
867 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
868}
869
313a3dc7
CO		 870/*
871 * Adapt set_msr() to msr_io()'s calling convention
872 */
873static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
874{
875 return kvm_set_msr(vcpu, index, *data);
876}
877
18068523
GOC		 878static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
879{
9ed3c444
AK		 880 int version;
881 int r;
50d0a0f9 882 struct pvclock_wall_clock wc;
923de3cf 883 struct timespec boot;
18068523
GOC		 884
885 if (!wall_clock)
886 return;
887
9ed3c444
AK		 888 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
889 if (r)
890 return;
891
892 if (version & 1)
893 ++version; /* first time write, random junk */
894
895 ++version;
18068523 896
18068523
GOC		 897 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
898
50d0a0f9
GH		 899 /*
900 * The guest calculates current wall clock time by adding
34c238a1 901 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 902 * wall clock specified here. guest system time equals host
903 * system time for us, thus we must fill in host boot time here.
904 */
923de3cf 905 getboottime(&boot);
50d0a0f9
GH		 906
907 wc.sec = boot.tv_sec;
908 wc.nsec = boot.tv_nsec;
909 wc.version = version;
18068523
GOC		 910
911 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
912
913 version++;
914 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 915}
916
50d0a0f9
GH		 917static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
918{
919 uint32_t quotient, remainder;
920
921 /* Don't try to replace with do_div(), this one calculates
922 * "(dividend << 32) / divisor" */
923 __asm__ ( "divl %4"
924 : "=a" (quotient), "=d" (remainder)
925 : "0" (0), "1" (dividend), "r" (divisor) );
926 return quotient;
927}
928
5f4e3f88
ZA		 929static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
930 s8 *pshift, u32 *pmultiplier)
50d0a0f9 931{
5f4e3f88 932 uint64_t scaled64;
50d0a0f9
GH		 933 int32_t shift = 0;
934 uint64_t tps64;
935 uint32_t tps32;
936
5f4e3f88
ZA		 937 tps64 = base_khz * 1000LL;
938 scaled64 = scaled_khz * 1000LL;
50933623 939 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 940 tps64 >>= 1;
941 shift--;
942 }
943
944 tps32 = (uint32_t)tps64;
50933623
JK		 945 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
946 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 947 scaled64 >>= 1;
948 else
949 tps32 <<= 1;
50d0a0f9
GH		 950 shift++;
951 }
952
5f4e3f88
ZA		 953 *pshift = shift;
954 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 955
5f4e3f88
ZA		 956 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
957 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 958}
959
759379dd
ZA		 960static inline u64 get_kernel_ns(void)
961{
962 struct timespec ts;
963
964 WARN_ON(preemptible());
965 ktime_get_ts(&ts);
966 monotonic_to_bootbased(&ts);
967 return timespec_to_ns(&ts);
50d0a0f9
GH		 968}
969
c8076604 970static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 971unsigned long max_tsc_khz;
c8076604 972
8cfdc000
ZA		 973static inline int kvm_tsc_changes_freq(void)
974{
975 int cpu = get_cpu();
976 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
977 cpufreq_quick_get(cpu) != 0;
978 put_cpu();
979 return ret;
980}
981
759379dd
ZA		 982static inline u64 nsec_to_cycles(u64 nsec)
983{
217fc9cf
AK		 984 u64 ret;
985
759379dd
ZA		 986 WARN_ON(preemptible());
987 if (kvm_tsc_changes_freq())
988 printk_once(KERN_WARNING
989 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
0a3aee0d 990 ret = nsec * __this_cpu_read(cpu_tsc_khz);
217fc9cf
AK		 991 do_div(ret, USEC_PER_SEC);
992 return ret;
759379dd
ZA		 993}
994
c285545f
ZA		 995static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
996{
997 /* Compute a scale to convert nanoseconds in TSC cycles */
998 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
999 &kvm->arch.virtual_tsc_shift,
1000 &kvm->arch.virtual_tsc_mult);
1001 kvm->arch.virtual_tsc_khz = this_tsc_khz;
1002}
1003
1004static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1005{
1006 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1007 vcpu->kvm->arch.virtual_tsc_mult,
1008 vcpu->kvm->arch.virtual_tsc_shift);
1009 tsc += vcpu->arch.last_tsc_write;
1010 return tsc;
1011}
1012
99e3e30a
ZA		 1013void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1014{
1015 struct kvm *kvm = vcpu->kvm;
f38e098f 1016 u64 offset, ns, elapsed;
99e3e30a 1017 unsigned long flags;
46543ba4 1018 s64 sdiff;
99e3e30a
ZA		 1019
1020 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1021 offset = data - native_read_tsc();
759379dd 1022 ns = get_kernel_ns();
f38e098f 1023 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1024 sdiff = data - kvm->arch.last_tsc_write;
1025 if (sdiff < 0)
1026 sdiff = -sdiff;
f38e098f
ZA		 1027
1028 /*
46543ba4 1029 * Special case: close write to TSC within 5 seconds of
f38e098f 1030 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1031 * The 5 seconds is to accomodate host load / swapping as
1032 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1033 *
1034 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1035 * or make a best guest using elapsed value.
f38e098f 1036 */
46543ba4
ZA		 1037 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1038 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1039 if (!check_tsc_unstable()) {
1040 offset = kvm->arch.last_tsc_offset;
1041 pr_debug("kvm: matched tsc offset for %llu\n", data);
1042 } else {
759379dd
ZA		 1043 u64 delta = nsec_to_cycles(elapsed);
1044 offset += delta;
1045 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1046 }
1047 ns = kvm->arch.last_tsc_nsec;
1048 }
1049 kvm->arch.last_tsc_nsec = ns;
1050 kvm->arch.last_tsc_write = data;
1051 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1052 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1053 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1054
1055 /* Reset of TSC must disable overshoot protection below */
1056 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1057 vcpu->arch.last_tsc_write = data;
1058 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1059}
1060EXPORT_SYMBOL_GPL(kvm_write_tsc);
1061
34c238a1 1062static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1063{
18068523
GOC		 1064 unsigned long flags;
1065 struct kvm_vcpu_arch *vcpu = &v->arch;
1066 void *shared_kaddr;
463656c0 1067 unsigned long this_tsc_khz;
1d5f066e
ZA		 1068 s64 kernel_ns, max_kernel_ns;
1069 u64 tsc_timestamp;
18068523 1070
18068523
GOC		 1071 /* Keep irq disabled to prevent changes to the clock */
1072 local_irq_save(flags);
1d5f066e 1073 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1074 kernel_ns = get_kernel_ns();
0a3aee0d 1075 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
18068523 1076
8cfdc000 1077 if (unlikely(this_tsc_khz == 0)) {
c285545f 1078 local_irq_restore(flags);
34c238a1 1079 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1080 return 1;
1081 }
18068523 1082
c285545f
ZA		 1083 /*
1084 * We may have to catch up the TSC to match elapsed wall clock
1085 * time for two reasons, even if kvmclock is used.
1086 * 1) CPU could have been running below the maximum TSC rate
1087 * 2) Broken TSC compensation resets the base at each VCPU
1088 * entry to avoid unknown leaps of TSC even when running
1089 * again on the same CPU. This may cause apparent elapsed
1090 * time to disappear, and the guest to stand still or run
1091 * very slowly.
1092 */
1093 if (vcpu->tsc_catchup) {
1094 u64 tsc = compute_guest_tsc(v, kernel_ns);
1095 if (tsc > tsc_timestamp) {
1096 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1097 tsc_timestamp = tsc;
1098 }
50d0a0f9
GH		 1099 }
1100
18068523
GOC		 1101 local_irq_restore(flags);
1102
c285545f
ZA		 1103 if (!vcpu->time_page)
1104 return 0;
18068523 1105
1d5f066e
ZA		 1106 /*
1107 * Time as measured by the TSC may go backwards when resetting the base
1108 * tsc_timestamp. The reason for this is that the TSC resolution is
1109 * higher than the resolution of the other clock scales. Thus, many
1110 * possible measurments of the TSC correspond to one measurement of any
1111 * other clock, and so a spread of values is possible. This is not a
1112 * problem for the computation of the nanosecond clock; with TSC rates
1113 * around 1GHZ, there can only be a few cycles which correspond to one
1114 * nanosecond value, and any path through this code will inevitably
1115 * take longer than that. However, with the kernel_ns value itself,
1116 * the precision may be much lower, down to HZ granularity. If the
1117 * first sampling of TSC against kernel_ns ends in the low part of the
1118 * range, and the second in the high end of the range, we can get:
1119 *
1120 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1121 *
1122 * As the sampling errors potentially range in the thousands of cycles,
1123 * it is possible such a time value has already been observed by the
1124 * guest. To protect against this, we must compute the system time as
1125 * observed by the guest and ensure the new system time is greater.
1126 */
1127 max_kernel_ns = 0;
1128 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1129 max_kernel_ns = vcpu->last_guest_tsc -
1130 vcpu->hv_clock.tsc_timestamp;
1131 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1132 vcpu->hv_clock.tsc_to_system_mul,
1133 vcpu->hv_clock.tsc_shift);
1134 max_kernel_ns += vcpu->last_kernel_ns;
1135 }
afbcf7ab 1136
e48672fa 1137 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1138 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1139 &vcpu->hv_clock.tsc_shift,
1140 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1141 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1142 }
1143
1d5f066e
ZA		 1144 if (max_kernel_ns > kernel_ns)
1145 kernel_ns = max_kernel_ns;
1146
8cfdc000 1147 /* With all the info we got, fill in the values */
1d5f066e 1148 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1149 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1150 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1151 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1152 vcpu->hv_clock.flags = 0;
1153
18068523
GOC		 1154 /*
1155 * The interface expects us to write an even number signaling that the
1156 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1157 * state, we just increase by 2 at the end.
18068523 1158 */
50d0a0f9 1159 vcpu->hv_clock.version += 2;
18068523
GOC		 1160
1161 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1162
1163 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1164 sizeof(vcpu->hv_clock));
18068523
GOC		 1165
1166 kunmap_atomic(shared_kaddr, KM_USER0);
1167
1168 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1169 return 0;
c8076604
GH		 1170}
1171
9ba075a6
AK		 1172static bool msr_mtrr_valid(unsigned msr)
1173{
1174 switch (msr) {
1175 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1176 case MSR_MTRRfix64K_00000:
1177 case MSR_MTRRfix16K_80000:
1178 case MSR_MTRRfix16K_A0000:
1179 case MSR_MTRRfix4K_C0000:
1180 case MSR_MTRRfix4K_C8000:
1181 case MSR_MTRRfix4K_D0000:
1182 case MSR_MTRRfix4K_D8000:
1183 case MSR_MTRRfix4K_E0000:
1184 case MSR_MTRRfix4K_E8000:
1185 case MSR_MTRRfix4K_F0000:
1186 case MSR_MTRRfix4K_F8000:
1187 case MSR_MTRRdefType:
1188 case MSR_IA32_CR_PAT:
1189 return true;
1190 case 0x2f8:
1191 return true;
1192 }
1193 return false;
1194}
1195
d6289b93
MT		 1196static bool valid_pat_type(unsigned t)
1197{
1198 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1199}
1200
1201static bool valid_mtrr_type(unsigned t)
1202{
1203 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1204}
1205
1206static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1207{
1208 int i;
1209
1210 if (!msr_mtrr_valid(msr))
1211 return false;
1212
1213 if (msr == MSR_IA32_CR_PAT) {
1214 for (i = 0; i < 8; i++)
1215 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1216 return false;
1217 return true;
1218 } else if (msr == MSR_MTRRdefType) {
1219 if (data & ~0xcff)
1220 return false;
1221 return valid_mtrr_type(data & 0xff);
1222 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1223 for (i = 0; i < 8 ; i++)
1224 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1225 return false;
1226 return true;
1227 }
1228
1229 /* variable MTRRs */
1230 return valid_mtrr_type(data & 0xff);
1231}
1232
9ba075a6
AK		 1233static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1234{
0bed3b56
SY		 1235 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1236
d6289b93 1237 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1238 return 1;
1239
0bed3b56
SY		 1240 if (msr == MSR_MTRRdefType) {
1241 vcpu->arch.mtrr_state.def_type = data;
1242 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1243 } else if (msr == MSR_MTRRfix64K_00000)
1244 p[0] = data;
1245 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1246 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1247 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1248 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1249 else if (msr == MSR_IA32_CR_PAT)
1250 vcpu->arch.pat = data;
1251 else { /* Variable MTRRs */
1252 int idx, is_mtrr_mask;
1253 u64 *pt;
1254
1255 idx = (msr - 0x200) / 2;
1256 is_mtrr_mask = msr - 0x200 - 2 * idx;
1257 if (!is_mtrr_mask)
1258 pt =
1259 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1260 else
1261 pt =
1262 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1263 *pt = data;
1264 }
1265
1266 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1267 return 0;
1268}
15c4a640 1269
890ca9ae 1270static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1271{
890ca9ae
HY		 1272 u64 mcg_cap = vcpu->arch.mcg_cap;
1273 unsigned bank_num = mcg_cap & 0xff;
1274
15c4a640 1275 switch (msr) {
15c4a640 1276 case MSR_IA32_MCG_STATUS:
890ca9ae 1277 vcpu->arch.mcg_status = data;
15c4a640 1278 break;
c7ac679c 1279 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1280 if (!(mcg_cap & MCG_CTL_P))
1281 return 1;
1282 if (data != 0 && data != ~(u64)0)
1283 return -1;
1284 vcpu->arch.mcg_ctl = data;
1285 break;
1286 default:
1287 if (msr >= MSR_IA32_MC0_CTL &&
1288 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1289 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1290 /* only 0 or all 1s can be written to IA32_MCi_CTL
1291 * some Linux kernels though clear bit 10 in bank 4 to
1292 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1293 * this to avoid an uncatched #GP in the guest
1294 */
890ca9ae 1295 if ((offset & 0x3) == 0 &&
114be429 1296 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1297 return -1;
1298 vcpu->arch.mce_banks[offset] = data;
1299 break;
1300 }
1301 return 1;
1302 }
1303 return 0;
1304}
1305
ffde22ac
ES		 1306static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1307{
1308 struct kvm *kvm = vcpu->kvm;
1309 int lm = is_long_mode(vcpu);
1310 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1311 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1312 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1313 : kvm->arch.xen_hvm_config.blob_size_32;
1314 u32 page_num = data & ~PAGE_MASK;
1315 u64 page_addr = data & PAGE_MASK;
1316 u8 *page;
1317 int r;
1318
1319 r = -E2BIG;
1320 if (page_num >= blob_size)
1321 goto out;
1322 r = -ENOMEM;
1323 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1324 if (!page)
1325 goto out;
1326 r = -EFAULT;
1327 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1328 goto out_free;
1329 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1330 goto out_free;
1331 r = 0;
1332out_free:
1333 kfree(page);
1334out:
1335 return r;
1336}
1337
55cd8e5a
GN		 1338static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1339{
1340 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1341}
1342
1343static bool kvm_hv_msr_partition_wide(u32 msr)
1344{
1345 bool r = false;
1346 switch (msr) {
1347 case HV_X64_MSR_GUEST_OS_ID:
1348 case HV_X64_MSR_HYPERCALL:
1349 r = true;
1350 break;
1351 }
1352
1353 return r;
1354}
1355
1356static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1357{
1358 struct kvm *kvm = vcpu->kvm;
1359
1360 switch (msr) {
1361 case HV_X64_MSR_GUEST_OS_ID:
1362 kvm->arch.hv_guest_os_id = data;
1363 /* setting guest os id to zero disables hypercall page */
1364 if (!kvm->arch.hv_guest_os_id)
1365 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1366 break;
1367 case HV_X64_MSR_HYPERCALL: {
1368 u64 gfn;
1369 unsigned long addr;
1370 u8 instructions[4];
1371
1372 /* if guest os id is not set hypercall should remain disabled */
1373 if (!kvm->arch.hv_guest_os_id)
1374 break;
1375 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1376 kvm->arch.hv_hypercall = data;
1377 break;
1378 }
1379 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1380 addr = gfn_to_hva(kvm, gfn);
1381 if (kvm_is_error_hva(addr))
1382 return 1;
1383 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1384 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1385 if (copy_to_user((void __user *)addr, instructions, 4))
1386 return 1;
1387 kvm->arch.hv_hypercall = data;
1388 break;
1389 }
1390 default:
1391 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1392 "data 0x%llx\n", msr, data);
1393 return 1;
1394 }
1395 return 0;
1396}
1397
1398static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1399{
10388a07
GN		 1400 switch (msr) {
1401 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1402 unsigned long addr;
55cd8e5a 1403
10388a07
GN		 1404 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1405 vcpu->arch.hv_vapic = data;
1406 break;
1407 }
1408 addr = gfn_to_hva(vcpu->kvm, data >>
1409 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1410 if (kvm_is_error_hva(addr))
1411 return 1;
1412 if (clear_user((void __user *)addr, PAGE_SIZE))
1413 return 1;
1414 vcpu->arch.hv_vapic = data;
1415 break;
1416 }
1417 case HV_X64_MSR_EOI:
1418 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1419 case HV_X64_MSR_ICR:
1420 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1421 case HV_X64_MSR_TPR:
1422 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1423 default:
1424 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1425 "data 0x%llx\n", msr, data);
1426 return 1;
1427 }
1428
1429 return 0;
55cd8e5a
GN		 1430}
1431
344d9588
GN		 1432static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1433{
1434 gpa_t gpa = data & ~0x3f;
1435
6adba527
GN		 1436 /* Bits 2:5 are resrved, Should be zero */
1437 if (data & 0x3c)
344d9588
GN		 1438 return 1;
1439
1440 vcpu->arch.apf.msr_val = data;
1441
1442 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1443 kvm_clear_async_pf_completion_queue(vcpu);
1444 kvm_async_pf_hash_reset(vcpu);
1445 return 0;
1446 }
1447
1448 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1449 return 1;
1450
6adba527 1451 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1452 kvm_async_pf_wakeup_all(vcpu);
1453 return 0;
1454}
1455
12f9a48f
GC		 1456static void kvmclock_reset(struct kvm_vcpu *vcpu)
1457{
1458 if (vcpu->arch.time_page) {
1459 kvm_release_page_dirty(vcpu->arch.time_page);
1460 vcpu->arch.time_page = NULL;
1461 }
1462}
1463
15c4a640
CO		 1464int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1465{
1466 switch (msr) {
15c4a640 1467 case MSR_EFER:
b69e8cae 1468 return set_efer(vcpu, data);
8f1589d9
AP		 1469 case MSR_K7_HWCR:
1470 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1471 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1472 if (data != 0) {
1473 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1474 data);
1475 return 1;
1476 }
15c4a640 1477 break;
f7c6d140
AP		 1478 case MSR_FAM10H_MMIO_CONF_BASE:
1479 if (data != 0) {
1480 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1481 "0x%llx\n", data);
1482 return 1;
1483 }
15c4a640 1484 break;
c323c0e5 1485 case MSR_AMD64_NB_CFG:
c7ac679c 1486 break;
b5e2fec0
AG		 1487 case MSR_IA32_DEBUGCTLMSR:
1488 if (!data) {
1489 /* We support the non-activated case already */
1490 break;
1491 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1492 /* Values other than LBR and BTF are vendor-specific,
1493 thus reserved and should throw a #GP */
1494 return 1;
1495 }
1496 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1497 __func__, data);
1498 break;
15c4a640
CO		 1499 case MSR_IA32_UCODE_REV:
1500 case MSR_IA32_UCODE_WRITE:
61a6bd67 1501 case MSR_VM_HSAVE_PA:
6098ca93 1502 case MSR_AMD64_PATCH_LOADER:
15c4a640 1503 break;
9ba075a6
AK		 1504 case 0x200 ... 0x2ff:
1505 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1506 case MSR_IA32_APICBASE:
1507 kvm_set_apic_base(vcpu, data);
1508 break;
0105d1a5
GN		 1509 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1510 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1511 case MSR_IA32_MISC_ENABLE:
ad312c7c 1512 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1513 break;
11c6bffa 1514 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1515 case MSR_KVM_WALL_CLOCK:
1516 vcpu->kvm->arch.wall_clock = data;
1517 kvm_write_wall_clock(vcpu->kvm, data);
1518 break;
11c6bffa 1519 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1520 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1521 kvmclock_reset(vcpu);
18068523
GOC		 1522
1523 vcpu->arch.time = data;
c285545f 1524 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1525
1526 /* we verify if the enable bit is set... */
1527 if (!(data & 1))
1528 break;
1529
1530 /* ...but clean it before doing the actual write */
1531 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1532
18068523
GOC		 1533 vcpu->arch.time_page =
1534 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1535
1536 if (is_error_page(vcpu->arch.time_page)) {
1537 kvm_release_page_clean(vcpu->arch.time_page);
1538 vcpu->arch.time_page = NULL;
1539 }
18068523
GOC		 1540 break;
1541 }
344d9588
GN		 1542 case MSR_KVM_ASYNC_PF_EN:
1543 if (kvm_pv_enable_async_pf(vcpu, data))
1544 return 1;
1545 break;
890ca9ae
HY		 1546 case MSR_IA32_MCG_CTL:
1547 case MSR_IA32_MCG_STATUS:
1548 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1549 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1550
1551 /* Performance counters are not protected by a CPUID bit,
1552 * so we should check all of them in the generic path for the sake of
1553 * cross vendor migration.
1554 * Writing a zero into the event select MSRs disables them,
1555 * which we perfectly emulate ;-). Any other value should be at least
1556 * reported, some guests depend on them.
1557 */
1558 case MSR_P6_EVNTSEL0:
1559 case MSR_P6_EVNTSEL1:
1560 case MSR_K7_EVNTSEL0:
1561 case MSR_K7_EVNTSEL1:
1562 case MSR_K7_EVNTSEL2:
1563 case MSR_K7_EVNTSEL3:
1564 if (data != 0)
1565 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1566 "0x%x data 0x%llx\n", msr, data);
1567 break;
1568 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1569 * so we ignore writes to make it happy.
1570 */
1571 case MSR_P6_PERFCTR0:
1572 case MSR_P6_PERFCTR1:
1573 case MSR_K7_PERFCTR0:
1574 case MSR_K7_PERFCTR1:
1575 case MSR_K7_PERFCTR2:
1576 case MSR_K7_PERFCTR3:
1577 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1578 "0x%x data 0x%llx\n", msr, data);
1579 break;
84e0cefa
JS		 1580 case MSR_K7_CLK_CTL:
1581 /*
1582 * Ignore all writes to this no longer documented MSR.
1583 * Writes are only relevant for old K7 processors,
1584 * all pre-dating SVM, but a recommended workaround from
1585 * AMD for these chips. It is possible to speicify the
1586 * affected processor models on the command line, hence
1587 * the need to ignore the workaround.
1588 */
1589 break;
55cd8e5a
GN		 1590 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1591 if (kvm_hv_msr_partition_wide(msr)) {
1592 int r;
1593 mutex_lock(&vcpu->kvm->lock);
1594 r = set_msr_hyperv_pw(vcpu, msr, data);
1595 mutex_unlock(&vcpu->kvm->lock);
1596 return r;
1597 } else
1598 return set_msr_hyperv(vcpu, msr, data);
1599 break;
91c9c3ed 1600 case MSR_IA32_BBL_CR_CTL3:
1601 /* Drop writes to this legacy MSR -- see rdmsr
1602 * counterpart for further detail.
1603 */
1604 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1605 break;
15c4a640 1606 default:
ffde22ac
ES		 1607 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1608 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1609 if (!ignore_msrs) {
1610 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1611 msr, data);
1612 return 1;
1613 } else {
1614 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1615 msr, data);
1616 break;
1617 }
15c4a640
CO		 1618 }
1619 return 0;
1620}
1621EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1622
1623
1624/*
1625 * Reads an msr value (of 'msr_index') into 'pdata'.
1626 * Returns 0 on success, non-0 otherwise.
1627 * Assumes vcpu_load() was already called.
1628 */
1629int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1630{
1631 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1632}
1633
9ba075a6
AK		 1634static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1635{
0bed3b56
SY		 1636 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1637
9ba075a6
AK		 1638 if (!msr_mtrr_valid(msr))
1639 return 1;
1640
0bed3b56
SY		 1641 if (msr == MSR_MTRRdefType)
1642 *pdata = vcpu->arch.mtrr_state.def_type +
1643 (vcpu->arch.mtrr_state.enabled << 10);
1644 else if (msr == MSR_MTRRfix64K_00000)
1645 *pdata = p[0];
1646 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1647 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1648 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1649 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1650 else if (msr == MSR_IA32_CR_PAT)
1651 *pdata = vcpu->arch.pat;
1652 else { /* Variable MTRRs */
1653 int idx, is_mtrr_mask;
1654 u64 *pt;
1655
1656 idx = (msr - 0x200) / 2;
1657 is_mtrr_mask = msr - 0x200 - 2 * idx;
1658 if (!is_mtrr_mask)
1659 pt =
1660 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1661 else
1662 pt =
1663 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1664 *pdata = *pt;
1665 }
1666
9ba075a6
AK		 1667 return 0;
1668}
1669
890ca9ae 1670static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1671{
1672 u64 data;
890ca9ae
HY		 1673 u64 mcg_cap = vcpu->arch.mcg_cap;
1674 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1675
1676 switch (msr) {
15c4a640
CO		 1677 case MSR_IA32_P5_MC_ADDR:
1678 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1679 data = 0;
1680 break;
15c4a640 1681 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1682 data = vcpu->arch.mcg_cap;
1683 break;
c7ac679c 1684 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1685 if (!(mcg_cap & MCG_CTL_P))
1686 return 1;
1687 data = vcpu->arch.mcg_ctl;
1688 break;
1689 case MSR_IA32_MCG_STATUS:
1690 data = vcpu->arch.mcg_status;
1691 break;
1692 default:
1693 if (msr >= MSR_IA32_MC0_CTL &&
1694 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1695 u32 offset = msr - MSR_IA32_MC0_CTL;
1696 data = vcpu->arch.mce_banks[offset];
1697 break;
1698 }
1699 return 1;
1700 }
1701 *pdata = data;
1702 return 0;
1703}
1704
55cd8e5a
GN		 1705static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1706{
1707 u64 data = 0;
1708 struct kvm *kvm = vcpu->kvm;
1709
1710 switch (msr) {
1711 case HV_X64_MSR_GUEST_OS_ID:
1712 data = kvm->arch.hv_guest_os_id;
1713 break;
1714 case HV_X64_MSR_HYPERCALL:
1715 data = kvm->arch.hv_hypercall;
1716 break;
1717 default:
1718 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1719 return 1;
1720 }
1721
1722 *pdata = data;
1723 return 0;
1724}
1725
1726static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1727{
1728 u64 data = 0;
1729
1730 switch (msr) {
1731 case HV_X64_MSR_VP_INDEX: {
1732 int r;
1733 struct kvm_vcpu *v;
1734 kvm_for_each_vcpu(r, v, vcpu->kvm)
1735 if (v == vcpu)
1736 data = r;
1737 break;
1738 }
10388a07
GN		 1739 case HV_X64_MSR_EOI:
1740 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1741 case HV_X64_MSR_ICR:
1742 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1743 case HV_X64_MSR_TPR:
1744 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1745 default:
1746 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1747 return 1;
1748 }
1749 *pdata = data;
1750 return 0;
1751}
1752
890ca9ae
HY		 1753int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1754{
1755 u64 data;
1756
1757 switch (msr) {
890ca9ae 1758 case MSR_IA32_PLATFORM_ID:
15c4a640 1759 case MSR_IA32_UCODE_REV:
15c4a640 1760 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1761 case MSR_IA32_DEBUGCTLMSR:
1762 case MSR_IA32_LASTBRANCHFROMIP:
1763 case MSR_IA32_LASTBRANCHTOIP:
1764 case MSR_IA32_LASTINTFROMIP:
1765 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1766 case MSR_K8_SYSCFG:
1767 case MSR_K7_HWCR:
61a6bd67 1768 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1769 case MSR_P6_PERFCTR0:
1770 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1771 case MSR_P6_EVNTSEL0:
1772 case MSR_P6_EVNTSEL1:
9e699624 1773 case MSR_K7_EVNTSEL0:
1f3ee616 1774 case MSR_K7_PERFCTR0:
1fdbd48c 1775 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1776 case MSR_AMD64_NB_CFG:
f7c6d140 1777 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1778 data = 0;
1779 break;
9ba075a6
AK		 1780 case MSR_MTRRcap:
1781 data = 0x500 | KVM_NR_VAR_MTRR;
1782 break;
1783 case 0x200 ... 0x2ff:
1784 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1785 case 0xcd: /* fsb frequency */
1786 data = 3;
1787 break;
7b914098
JS		 1788 /*
1789 * MSR_EBC_FREQUENCY_ID
1790 * Conservative value valid for even the basic CPU models.
1791 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1792 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1793 * and 266MHz for model 3, or 4. Set Core Clock
1794 * Frequency to System Bus Frequency Ratio to 1 (bits
1795 * 31:24) even though these are only valid for CPU
1796 * models > 2, however guests may end up dividing or
1797 * multiplying by zero otherwise.
1798 */
1799 case MSR_EBC_FREQUENCY_ID:
1800 data = 1 << 24;
1801 break;
15c4a640
CO		 1802 case MSR_IA32_APICBASE:
1803 data = kvm_get_apic_base(vcpu);
1804 break;
0105d1a5
GN		 1805 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1806 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1807 break;
15c4a640 1808 case MSR_IA32_MISC_ENABLE:
ad312c7c 1809 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1810 break;
847f0ad8
AG		 1811 case MSR_IA32_PERF_STATUS:
1812 /* TSC increment by tick */
1813 data = 1000ULL;
1814 /* CPU multiplier */
1815 data |= (((uint64_t)4ULL) << 40);
1816 break;
15c4a640 1817 case MSR_EFER:
f6801dff 1818 data = vcpu->arch.efer;
15c4a640 1819 break;
18068523 1820 case MSR_KVM_WALL_CLOCK:
11c6bffa 1821 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1822 data = vcpu->kvm->arch.wall_clock;
1823 break;
1824 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1825 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1826 data = vcpu->arch.time;
1827 break;
344d9588
GN		 1828 case MSR_KVM_ASYNC_PF_EN:
1829 data = vcpu->arch.apf.msr_val;
1830 break;
890ca9ae
HY		 1831 case MSR_IA32_P5_MC_ADDR:
1832 case MSR_IA32_P5_MC_TYPE:
1833 case MSR_IA32_MCG_CAP:
1834 case MSR_IA32_MCG_CTL:
1835 case MSR_IA32_MCG_STATUS:
1836 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1837 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1838 case MSR_K7_CLK_CTL:
1839 /*
1840 * Provide expected ramp-up count for K7. All other
1841 * are set to zero, indicating minimum divisors for
1842 * every field.
1843 *
1844 * This prevents guest kernels on AMD host with CPU
1845 * type 6, model 8 and higher from exploding due to
1846 * the rdmsr failing.
1847 */
1848 data = 0x20000000;
1849 break;
55cd8e5a
GN		 1850 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1851 if (kvm_hv_msr_partition_wide(msr)) {
1852 int r;
1853 mutex_lock(&vcpu->kvm->lock);
1854 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1855 mutex_unlock(&vcpu->kvm->lock);
1856 return r;
1857 } else
1858 return get_msr_hyperv(vcpu, msr, pdata);
1859 break;
91c9c3ed 1860 case MSR_IA32_BBL_CR_CTL3:
1861 /* This legacy MSR exists but isn't fully documented in current
1862 * silicon. It is however accessed by winxp in very narrow
1863 * scenarios where it sets bit #19, itself documented as
1864 * a "reserved" bit. Best effort attempt to source coherent
1865 * read data here should the balance of the register be
1866 * interpreted by the guest:
1867 *
1868 * L2 cache control register 3: 64GB range, 256KB size,
1869 * enabled, latency 0x1, configured
1870 */
1871 data = 0xbe702111;
1872 break;
15c4a640 1873 default:
ed85c068
AP		 1874 if (!ignore_msrs) {
1875 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1876 return 1;
1877 } else {
1878 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1879 data = 0;
1880 }
1881 break;
15c4a640
CO		 1882 }
1883 *pdata = data;
1884 return 0;
1885}
1886EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1887
313a3dc7
CO		 1888/*
1889 * Read or write a bunch of msrs. All parameters are kernel addresses.
1890 *
1891 * @return number of msrs set successfully.
1892 */
1893static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1894 struct kvm_msr_entry *entries,
1895 int (*do_msr)(struct kvm_vcpu *vcpu,
1896 unsigned index, u64 *data))
1897{
f656ce01 1898 int i, idx;
313a3dc7 1899
f656ce01 1900 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1901 for (i = 0; i < msrs->nmsrs; ++i)
1902 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1903 break;
f656ce01 1904 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1905
313a3dc7
CO		 1906 return i;
1907}
1908
1909/*
1910 * Read or write a bunch of msrs. Parameters are user addresses.
1911 *
1912 * @return number of msrs set successfully.
1913 */
1914static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1915 int (*do_msr)(struct kvm_vcpu *vcpu,
1916 unsigned index, u64 *data),
1917 int writeback)
1918{
1919 struct kvm_msrs msrs;
1920 struct kvm_msr_entry *entries;
1921 int r, n;
1922 unsigned size;
1923
1924 r = -EFAULT;
1925 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1926 goto out;
1927
1928 r = -E2BIG;
1929 if (msrs.nmsrs >= MAX_IO_MSRS)
1930 goto out;
1931
1932 r = -ENOMEM;
1933 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1934 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1935 if (!entries)
1936 goto out;
1937
1938 r = -EFAULT;
1939 if (copy_from_user(entries, user_msrs->entries, size))
1940 goto out_free;
1941
1942 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1943 if (r < 0)
1944 goto out_free;
1945
1946 r = -EFAULT;
1947 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1948 goto out_free;
1949
1950 r = n;
1951
1952out_free:
7a73c028 1953 kfree(entries);
313a3dc7
CO		 1954out:
1955 return r;
1956}
1957
018d00d2
ZX		 1958int kvm_dev_ioctl_check_extension(long ext)
1959{
1960 int r;
1961
1962 switch (ext) {
1963 case KVM_CAP_IRQCHIP:
1964 case KVM_CAP_HLT:
1965 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1966 case KVM_CAP_SET_TSS_ADDR:
07716717 1967 case KVM_CAP_EXT_CPUID:
c8076604 1968 case KVM_CAP_CLOCKSOURCE:
7837699f 1969 case KVM_CAP_PIT:
a28e4f5a 1970 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1971 case KVM_CAP_MP_STATE:
ed848624 1972 case KVM_CAP_SYNC_MMU:
a355c85c 1973 case KVM_CAP_USER_NMI:
52d939a0 1974 case KVM_CAP_REINJECT_CONTROL:
4925663a 1975 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1976 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1977 case KVM_CAP_IRQFD:
d34e6b17 1978 case KVM_CAP_IOEVENTFD:
c5ff41ce 1979 case KVM_CAP_PIT2:
e9f42757 1980 case KVM_CAP_PIT_STATE2:
b927a3ce 1981 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1982 case KVM_CAP_XEN_HVM:
afbcf7ab 1983 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1984 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1985 case KVM_CAP_HYPERV:
10388a07 1986 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1987 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1988 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1989 case KVM_CAP_DEBUGREGS:
d2be1651 1990 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1991 case KVM_CAP_XSAVE:
344d9588 1992 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1993 r = 1;
1994 break;
542472b5
LV		 1995 case KVM_CAP_COALESCED_MMIO:
1996 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1997 break;
774ead3a
AK		 1998 case KVM_CAP_VAPIC:
1999 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2000 break;
f725230a
AK		 2001 case KVM_CAP_NR_VCPUS:
2002 r = KVM_MAX_VCPUS;
2003 break;
a988b910
AK		 2004 case KVM_CAP_NR_MEMSLOTS:
2005 r = KVM_MEMORY_SLOTS;
2006 break;
a68a6a72
MT		 2007 case KVM_CAP_PV_MMU: /* obsolete */
2008 r = 0;
2f333bcb 2009 break;
62c476c7 2010 case KVM_CAP_IOMMU:
19de40a8 2011 r = iommu_found();
62c476c7 2012 break;
890ca9ae
HY		 2013 case KVM_CAP_MCE:
2014 r = KVM_MAX_MCE_BANKS;
2015 break;
2d5b5a66
SY		 2016 case KVM_CAP_XCRS:
2017 r = cpu_has_xsave;
2018 break;
018d00d2
ZX		 2019 default:
2020 r = 0;
2021 break;
2022 }
2023 return r;
2024
2025}
2026
043405e1
CO		 2027long kvm_arch_dev_ioctl(struct file *filp,
2028 unsigned int ioctl, unsigned long arg)
2029{
2030 void __user *argp = (void __user *)arg;
2031 long r;
2032
2033 switch (ioctl) {
2034 case KVM_GET_MSR_INDEX_LIST: {
2035 struct kvm_msr_list __user *user_msr_list = argp;
2036 struct kvm_msr_list msr_list;
2037 unsigned n;
2038
2039 r = -EFAULT;
2040 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2041 goto out;
2042 n = msr_list.nmsrs;
2043 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2044 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2045 goto out;
2046 r = -E2BIG;
e125e7b6 2047 if (n < msr_list.nmsrs)
043405e1
CO		 2048 goto out;
2049 r = -EFAULT;
2050 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2051 num_msrs_to_save * sizeof(u32)))
2052 goto out;
e125e7b6 2053 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2054 &emulated_msrs,
2055 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2056 goto out;
2057 r = 0;
2058 break;
2059 }
674eea0f
AK		 2060 case KVM_GET_SUPPORTED_CPUID: {
2061 struct kvm_cpuid2 __user *cpuid_arg = argp;
2062 struct kvm_cpuid2 cpuid;
2063
2064 r = -EFAULT;
2065 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2066 goto out;
2067 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2068 cpuid_arg->entries);
674eea0f
AK		 2069 if (r)
2070 goto out;
2071
2072 r = -EFAULT;
2073 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2074 goto out;
2075 r = 0;
2076 break;
2077 }
890ca9ae
HY		 2078 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2079 u64 mce_cap;
2080
2081 mce_cap = KVM_MCE_CAP_SUPPORTED;
2082 r = -EFAULT;
2083 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2084 goto out;
2085 r = 0;
2086 break;
2087 }
043405e1
CO		 2088 default:
2089 r = -EINVAL;
2090 }
2091out:
2092 return r;
2093}
2094
f5f48ee1
SY		 2095static void wbinvd_ipi(void *garbage)
2096{
2097 wbinvd();
2098}
2099
2100static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2101{
2102 return vcpu->kvm->arch.iommu_domain &&
2103 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2104}
2105
313a3dc7
CO		 2106void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2107{
f5f48ee1
SY		 2108 /* Address WBINVD may be executed by guest */
2109 if (need_emulate_wbinvd(vcpu)) {
2110 if (kvm_x86_ops->has_wbinvd_exit())
2111 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2112 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2113 smp_call_function_single(vcpu->cpu,
2114 wbinvd_ipi, NULL, 1);
2115 }
2116
313a3dc7 2117 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2118 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2119 /* Make sure TSC doesn't go backwards */
2120 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2121 native_read_tsc() - vcpu->arch.last_host_tsc;
2122 if (tsc_delta < 0)
2123 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2124 if (check_tsc_unstable()) {
e48672fa 2125 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2126 vcpu->arch.tsc_catchup = 1;
2127 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2128 }
2129 if (vcpu->cpu != cpu)
2130 kvm_migrate_timers(vcpu);
e48672fa 2131 vcpu->cpu = cpu;
6b7d7e76 2132 }
313a3dc7
CO		 2133}
2134
2135void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2136{
02daab21 2137 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2138 kvm_put_guest_fpu(vcpu);
e48672fa 2139 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2140}
2141
07716717 2142static int is_efer_nx(void)
313a3dc7 2143{
e286e86e 2144 unsigned long long efer = 0;
313a3dc7 2145
e286e86e 2146 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2147 return efer & EFER_NX;
2148}
2149
2150static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2151{
2152 int i;
2153 struct kvm_cpuid_entry2 *e, *entry;
2154
313a3dc7 2155 entry = NULL;
ad312c7c
ZX		 2156 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2157 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2158 if (e->function == 0x80000001) {
2159 entry = e;
2160 break;
2161 }
2162 }
07716717 2163 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2164 entry->edx &= ~(1 << 20);
2165 printk(KERN_INFO "kvm: guest NX capability removed\n");
2166 }
2167}
2168
07716717 2169/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2170static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2171 struct kvm_cpuid *cpuid,
2172 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2173{
2174 int r, i;
2175 struct kvm_cpuid_entry *cpuid_entries;
2176
2177 r = -E2BIG;
2178 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2179 goto out;
2180 r = -ENOMEM;
2181 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2182 if (!cpuid_entries)
2183 goto out;
2184 r = -EFAULT;
2185 if (copy_from_user(cpuid_entries, entries,
2186 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2187 goto out_free;
2188 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2189 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2190 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2191 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2192 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2193 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2194 vcpu->arch.cpuid_entries[i].index = 0;
2195 vcpu->arch.cpuid_entries[i].flags = 0;
2196 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2197 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2198 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2199 }
2200 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2201 cpuid_fix_nx_cap(vcpu);
2202 r = 0;
fc61b800 2203 kvm_apic_set_version(vcpu);
0e851880 2204 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2205 update_cpuid(vcpu);
07716717
DK		 2206
2207out_free:
2208 vfree(cpuid_entries);
2209out:
2210 return r;
2211}
2212
2213static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2214 struct kvm_cpuid2 *cpuid,
2215 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2216{
2217 int r;
2218
2219 r = -E2BIG;
2220 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2221 goto out;
2222 r = -EFAULT;
ad312c7c 2223 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2224 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2225 goto out;
ad312c7c 2226 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2227 kvm_apic_set_version(vcpu);
0e851880 2228 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2229 update_cpuid(vcpu);
313a3dc7
CO		 2230 return 0;
2231
2232out:
2233 return r;
2234}
2235
07716717 2236static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2237 struct kvm_cpuid2 *cpuid,
2238 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2239{
2240 int r;
2241
2242 r = -E2BIG;
ad312c7c 2243 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2244 goto out;
2245 r = -EFAULT;
ad312c7c 2246 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2247 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2248 goto out;
2249 return 0;
2250
2251out:
ad312c7c 2252 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2253 return r;
2254}
2255
945ee35e
AK		 2256static void cpuid_mask(u32 *word, int wordnum)
2257{
2258 *word &= boot_cpu_data.x86_capability[wordnum];
2259}
2260
07716717 2261static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2262 u32 index)
07716717
DK		 2263{
2264 entry->function = function;
2265 entry->index = index;
2266 cpuid_count(entry->function, entry->index,
19355475 2267 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2268 entry->flags = 0;
2269}
2270
7faa4ee1
AK		 2271#define F(x) bit(X86_FEATURE_##x)
2272
07716717
DK		 2273static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2274 u32 index, int *nent, int maxnent)
2275{
7faa4ee1 2276 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2277#ifdef CONFIG_X86_64
17cc3935
SY		 2278 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2279 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2280 unsigned f_lm = F(LM);
2281#else
17cc3935 2282 unsigned f_gbpages = 0;
7faa4ee1 2283 unsigned f_lm = 0;
07716717 2284#endif
4e47c7a6 2285 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2286
2287 /* cpuid 1.edx */
2288 const u32 kvm_supported_word0_x86_features =
2289 F(FPU) | F(VME) | F(DE) | F(PSE) |
2290 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2291 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2292 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2293 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2294 0 /* Reserved, DS, ACPI */ | F(MMX) |
2295 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2296 0 /* HTT, TM, Reserved, PBE */;
2297 /* cpuid 0x80000001.edx */
2298 const u32 kvm_supported_word1_x86_features =
2299 F(FPU) | F(VME) | F(DE) | F(PSE) |
2300 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2301 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2302 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2303 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2304 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2305 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2306 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2307 /* cpuid 1.ecx */
2308 const u32 kvm_supported_word4_x86_features =
6c3f6041 2309 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2310 0 /* DS-CPL, VMX, SMX, EST */ |
2311 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2312 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2313 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2314 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2315 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2316 F(F16C);
7faa4ee1 2317 /* cpuid 0x80000001.ecx */
07716717 2318 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2319 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2320 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2321 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2322 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2323
19355475 2324 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2325 get_cpu();
2326 do_cpuid_1_ent(entry, function, index);
2327 ++*nent;
2328
2329 switch (function) {
2330 case 0:
2acf923e 2331 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2332 break;
2333 case 1:
2334 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2335 cpuid_mask(&entry->edx, 0);
7faa4ee1 2336 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2337 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2338 /* we support x2apic emulation even if host does not support
2339 * it since we emulate x2apic in software */
2340 entry->ecx |= F(X2APIC);
07716717
DK		 2341 break;
2342 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2343 * may return different values. This forces us to get_cpu() before
2344 * issuing the first command, and also to emulate this annoying behavior
2345 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2346 case 2: {
2347 int t, times = entry->eax & 0xff;
2348
2349 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2350 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2351 for (t = 1; t < times && *nent < maxnent; ++t) {
2352 do_cpuid_1_ent(&entry[t], function, 0);
2353 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2354 ++*nent;
2355 }
2356 break;
2357 }
2358 /* function 4 and 0xb have additional index. */
2359 case 4: {
14af3f3c 2360 int i, cache_type;
07716717
DK		 2361
2362 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2363 /* read more entries until cache_type is zero */
14af3f3c
HH		 2364 for (i = 1; *nent < maxnent; ++i) {
2365 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2366 if (!cache_type)
2367 break;
14af3f3c
HH		 2368 do_cpuid_1_ent(&entry[i], function, i);
2369 entry[i].flags |=
07716717
DK		 2370 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2371 ++*nent;
2372 }
2373 break;
2374 }
2375 case 0xb: {
14af3f3c 2376 int i, level_type;
07716717
DK		 2377
2378 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2379 /* read more entries until level_type is zero */
14af3f3c 2380 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2381 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2382 if (!level_type)
2383 break;
14af3f3c
HH		 2384 do_cpuid_1_ent(&entry[i], function, i);
2385 entry[i].flags |=
07716717
DK		 2386 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2387 ++*nent;
2388 }
2389 break;
2390 }
2acf923e
DC		 2391 case 0xd: {
2392 int i;
2393
2394 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2395 for (i = 1; *nent < maxnent; ++i) {
2396 if (entry[i - 1].eax == 0 && i != 2)
2397 break;
2398 do_cpuid_1_ent(&entry[i], function, i);
2399 entry[i].flags |=
2400 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2401 ++*nent;
2402 }
2403 break;
2404 }
84478c82
GC		 2405 case KVM_CPUID_SIGNATURE: {
2406 char signature[12] = "KVMKVMKVM\0\0";
2407 u32 *sigptr = (u32 *)signature;
2408 entry->eax = 0;
2409 entry->ebx = sigptr[0];
2410 entry->ecx = sigptr[1];
2411 entry->edx = sigptr[2];
2412 break;
2413 }
2414 case KVM_CPUID_FEATURES:
2415 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2416 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2417 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2418 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2419 entry->ebx = 0;
2420 entry->ecx = 0;
2421 entry->edx = 0;
2422 break;
07716717
DK		 2423 case 0x80000000:
2424 entry->eax = min(entry->eax, 0x8000001a);
2425 break;
2426 case 0x80000001:
2427 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2428 cpuid_mask(&entry->edx, 1);
07716717 2429 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2430 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2431 break;
2432 }
d4330ef2
JR		 2433
2434 kvm_x86_ops->set_supported_cpuid(function, entry);
2435
07716717
DK		 2436 put_cpu();
2437}
2438
7faa4ee1
AK		 2439#undef F
2440
674eea0f 2441static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2442 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2443{
2444 struct kvm_cpuid_entry2 *cpuid_entries;
2445 int limit, nent = 0, r = -E2BIG;
2446 u32 func;
2447
2448 if (cpuid->nent < 1)
2449 goto out;
6a544355
AK		 2450 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2451 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2452 r = -ENOMEM;
2453 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2454 if (!cpuid_entries)
2455 goto out;
2456
2457 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2458 limit = cpuid_entries[0].eax;
2459 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2460 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2461 &nent, cpuid->nent);
07716717
DK		 2462 r = -E2BIG;
2463 if (nent >= cpuid->nent)
2464 goto out_free;
2465
2466 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2467 limit = cpuid_entries[nent - 1].eax;
2468 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2469 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2470 &nent, cpuid->nent);
84478c82
GC		 2471
2472
2473
2474 r = -E2BIG;
2475 if (nent >= cpuid->nent)
2476 goto out_free;
2477
2478 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2479 cpuid->nent);
2480
2481 r = -E2BIG;
2482 if (nent >= cpuid->nent)
2483 goto out_free;
2484
2485 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2486 cpuid->nent);
2487
cb007648
MM		 2488 r = -E2BIG;
2489 if (nent >= cpuid->nent)
2490 goto out_free;
2491
07716717
DK		 2492 r = -EFAULT;
2493 if (copy_to_user(entries, cpuid_entries,
19355475 2494 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2495 goto out_free;
2496 cpuid->nent = nent;
2497 r = 0;
2498
2499out_free:
2500 vfree(cpuid_entries);
2501out:
2502 return r;
2503}
2504
313a3dc7
CO		 2505static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2506 struct kvm_lapic_state *s)
2507{
ad312c7c 2508 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2509
2510 return 0;
2511}
2512
2513static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2514 struct kvm_lapic_state *s)
2515{
ad312c7c 2516 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2517 kvm_apic_post_state_restore(vcpu);
cb142eb7 2518 update_cr8_intercept(vcpu);
313a3dc7
CO		 2519
2520 return 0;
2521}
2522
f77bc6a4
ZX		 2523static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2524 struct kvm_interrupt *irq)
2525{
2526 if (irq->irq < 0 || irq->irq >= 256)
2527 return -EINVAL;
2528 if (irqchip_in_kernel(vcpu->kvm))
2529 return -ENXIO;
f77bc6a4 2530
66fd3f7f 2531 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2532 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2533
f77bc6a4
ZX		 2534 return 0;
2535}
2536
c4abb7c9
JK		 2537static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2538{
c4abb7c9 2539 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2540
2541 return 0;
2542}
2543
b209749f
AK		 2544static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2545 struct kvm_tpr_access_ctl *tac)
2546{
2547 if (tac->flags)
2548 return -EINVAL;
2549 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2550 return 0;
2551}
2552
890ca9ae
HY		 2553static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2554 u64 mcg_cap)
2555{
2556 int r;
2557 unsigned bank_num = mcg_cap & 0xff, bank;
2558
2559 r = -EINVAL;
a9e38c3e 2560 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2561 goto out;
2562 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2563 goto out;
2564 r = 0;
2565 vcpu->arch.mcg_cap = mcg_cap;
2566 /* Init IA32_MCG_CTL to all 1s */
2567 if (mcg_cap & MCG_CTL_P)
2568 vcpu->arch.mcg_ctl = ~(u64)0;
2569 /* Init IA32_MCi_CTL to all 1s */
2570 for (bank = 0; bank < bank_num; bank++)
2571 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2572out:
2573 return r;
2574}
2575
2576static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2577 struct kvm_x86_mce *mce)
2578{
2579 u64 mcg_cap = vcpu->arch.mcg_cap;
2580 unsigned bank_num = mcg_cap & 0xff;
2581 u64 *banks = vcpu->arch.mce_banks;
2582
2583 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2584 return -EINVAL;
2585 /*
2586 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2587 * reporting is disabled
2588 */
2589 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2590 vcpu->arch.mcg_ctl != ~(u64)0)
2591 return 0;
2592 banks += 4 * mce->bank;
2593 /*
2594 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2595 * reporting is disabled for the bank
2596 */
2597 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2598 return 0;
2599 if (mce->status & MCI_STATUS_UC) {
2600 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2601 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2602 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2603 return 0;
2604 }
2605 if (banks[1] & MCI_STATUS_VAL)
2606 mce->status |= MCI_STATUS_OVER;
2607 banks[2] = mce->addr;
2608 banks[3] = mce->misc;
2609 vcpu->arch.mcg_status = mce->mcg_status;
2610 banks[1] = mce->status;
2611 kvm_queue_exception(vcpu, MC_VECTOR);
2612 } else if (!(banks[1] & MCI_STATUS_VAL)
2613 || !(banks[1] & MCI_STATUS_UC)) {
2614 if (banks[1] & MCI_STATUS_VAL)
2615 mce->status |= MCI_STATUS_OVER;
2616 banks[2] = mce->addr;
2617 banks[3] = mce->misc;
2618 banks[1] = mce->status;
2619 } else
2620 banks[1] |= MCI_STATUS_OVER;
2621 return 0;
2622}
2623
3cfc3092
JK		 2624static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2625 struct kvm_vcpu_events *events)
2626{
03b82a30
JK		 2627 events->exception.injected =
2628 vcpu->arch.exception.pending &&
2629 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2630 events->exception.nr = vcpu->arch.exception.nr;
2631 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2632 events->exception.pad = 0;
3cfc3092
JK		 2633 events->exception.error_code = vcpu->arch.exception.error_code;
2634
03b82a30
JK		 2635 events->interrupt.injected =
2636 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2637 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2638 events->interrupt.soft = 0;
48005f64
JK		 2639 events->interrupt.shadow =
2640 kvm_x86_ops->get_interrupt_shadow(vcpu,
2641 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2642
2643 events->nmi.injected = vcpu->arch.nmi_injected;
2644 events->nmi.pending = vcpu->arch.nmi_pending;
2645 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2646 events->nmi.pad = 0;
3cfc3092
JK		 2647
2648 events->sipi_vector = vcpu->arch.sipi_vector;
2649
dab4b911 2650 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2651 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2652 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2653 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2654}
2655
2656static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2657 struct kvm_vcpu_events *events)
2658{
dab4b911 2659 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2660 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2661 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2662 return -EINVAL;
2663
3cfc3092
JK		 2664 vcpu->arch.exception.pending = events->exception.injected;
2665 vcpu->arch.exception.nr = events->exception.nr;
2666 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2667 vcpu->arch.exception.error_code = events->exception.error_code;
2668
2669 vcpu->arch.interrupt.pending = events->interrupt.injected;
2670 vcpu->arch.interrupt.nr = events->interrupt.nr;
2671 vcpu->arch.interrupt.soft = events->interrupt.soft;
2672 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2673 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2674 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2675 kvm_x86_ops->set_interrupt_shadow(vcpu,
2676 events->interrupt.shadow);
3cfc3092
JK		 2677
2678 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2679 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2680 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2681 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2682
dab4b911
JK		 2683 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2684 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2685
3842d135
AK		 2686 kvm_make_request(KVM_REQ_EVENT, vcpu);
2687
3cfc3092
JK		 2688 return 0;
2689}
2690
a1efbe77
JK		 2691static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2692 struct kvm_debugregs *dbgregs)
2693{
a1efbe77
JK		 2694 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2695 dbgregs->dr6 = vcpu->arch.dr6;
2696 dbgregs->dr7 = vcpu->arch.dr7;
2697 dbgregs->flags = 0;
97e69aa6 2698 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2699}
2700
2701static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2702 struct kvm_debugregs *dbgregs)
2703{
2704 if (dbgregs->flags)
2705 return -EINVAL;
2706
a1efbe77
JK		 2707 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2708 vcpu->arch.dr6 = dbgregs->dr6;
2709 vcpu->arch.dr7 = dbgregs->dr7;
2710
a1efbe77
JK		 2711 return 0;
2712}
2713
2d5b5a66
SY		 2714static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2715 struct kvm_xsave *guest_xsave)
2716{
2717 if (cpu_has_xsave)
2718 memcpy(guest_xsave->region,
2719 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2720 xstate_size);
2d5b5a66
SY		 2721 else {
2722 memcpy(guest_xsave->region,
2723 &vcpu->arch.guest_fpu.state->fxsave,
2724 sizeof(struct i387_fxsave_struct));
2725 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2726 XSTATE_FPSSE;
2727 }
2728}
2729
2730static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2731 struct kvm_xsave *guest_xsave)
2732{
2733 u64 xstate_bv =
2734 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2735
2736 if (cpu_has_xsave)
2737 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2738 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2739 else {
2740 if (xstate_bv & ~XSTATE_FPSSE)
2741 return -EINVAL;
2742 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2743 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2744 }
2745 return 0;
2746}
2747
2748static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2749 struct kvm_xcrs *guest_xcrs)
2750{
2751 if (!cpu_has_xsave) {
2752 guest_xcrs->nr_xcrs = 0;
2753 return;
2754 }
2755
2756 guest_xcrs->nr_xcrs = 1;
2757 guest_xcrs->flags = 0;
2758 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2759 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2760}
2761
2762static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2763 struct kvm_xcrs *guest_xcrs)
2764{
2765 int i, r = 0;
2766
2767 if (!cpu_has_xsave)
2768 return -EINVAL;
2769
2770 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2771 return -EINVAL;
2772
2773 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2774 /* Only support XCR0 currently */
2775 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2776 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2777 guest_xcrs->xcrs[0].value);
2778 break;
2779 }
2780 if (r)
2781 r = -EINVAL;
2782 return r;
2783}
2784
313a3dc7
CO		 2785long kvm_arch_vcpu_ioctl(struct file *filp,
2786 unsigned int ioctl, unsigned long arg)
2787{
2788 struct kvm_vcpu *vcpu = filp->private_data;
2789 void __user *argp = (void __user *)arg;
2790 int r;
d1ac91d8
AK		 2791 union {
2792 struct kvm_lapic_state *lapic;
2793 struct kvm_xsave *xsave;
2794 struct kvm_xcrs *xcrs;
2795 void *buffer;
2796 } u;
2797
2798 u.buffer = NULL;
313a3dc7
CO		 2799 switch (ioctl) {
2800 case KVM_GET_LAPIC: {
2204ae3c
MT		 2801 r = -EINVAL;
2802 if (!vcpu->arch.apic)
2803 goto out;
d1ac91d8 2804 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2805
b772ff36 2806 r = -ENOMEM;
d1ac91d8 2807 if (!u.lapic)
b772ff36 2808 goto out;
d1ac91d8 2809 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2810 if (r)
2811 goto out;
2812 r = -EFAULT;
d1ac91d8 2813 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2814 goto out;
2815 r = 0;
2816 break;
2817 }
2818 case KVM_SET_LAPIC: {
2204ae3c
MT		 2819 r = -EINVAL;
2820 if (!vcpu->arch.apic)
2821 goto out;
d1ac91d8 2822 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2823 r = -ENOMEM;
d1ac91d8 2824 if (!u.lapic)
b772ff36 2825 goto out;
313a3dc7 2826 r = -EFAULT;
d1ac91d8 2827 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2828 goto out;
d1ac91d8 2829 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2830 if (r)
2831 goto out;
2832 r = 0;
2833 break;
2834 }
f77bc6a4
ZX		 2835 case KVM_INTERRUPT: {
2836 struct kvm_interrupt irq;
2837
2838 r = -EFAULT;
2839 if (copy_from_user(&irq, argp, sizeof irq))
2840 goto out;
2841 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2842 if (r)
2843 goto out;
2844 r = 0;
2845 break;
2846 }
c4abb7c9
JK		 2847 case KVM_NMI: {
2848 r = kvm_vcpu_ioctl_nmi(vcpu);
2849 if (r)
2850 goto out;
2851 r = 0;
2852 break;
2853 }
313a3dc7
CO		 2854 case KVM_SET_CPUID: {
2855 struct kvm_cpuid __user *cpuid_arg = argp;
2856 struct kvm_cpuid cpuid;
2857
2858 r = -EFAULT;
2859 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2860 goto out;
2861 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2862 if (r)
2863 goto out;
2864 break;
2865 }
07716717
DK		 2866 case KVM_SET_CPUID2: {
2867 struct kvm_cpuid2 __user *cpuid_arg = argp;
2868 struct kvm_cpuid2 cpuid;
2869
2870 r = -EFAULT;
2871 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2872 goto out;
2873 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2874 cpuid_arg->entries);
07716717
DK		 2875 if (r)
2876 goto out;
2877 break;
2878 }
2879 case KVM_GET_CPUID2: {
2880 struct kvm_cpuid2 __user *cpuid_arg = argp;
2881 struct kvm_cpuid2 cpuid;
2882
2883 r = -EFAULT;
2884 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2885 goto out;
2886 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2887 cpuid_arg->entries);
07716717
DK		 2888 if (r)
2889 goto out;
2890 r = -EFAULT;
2891 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2892 goto out;
2893 r = 0;
2894 break;
2895 }
313a3dc7
CO		 2896 case KVM_GET_MSRS:
2897 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2898 break;
2899 case KVM_SET_MSRS:
2900 r = msr_io(vcpu, argp, do_set_msr, 0);
2901 break;
b209749f
AK		 2902 case KVM_TPR_ACCESS_REPORTING: {
2903 struct kvm_tpr_access_ctl tac;
2904
2905 r = -EFAULT;
2906 if (copy_from_user(&tac, argp, sizeof tac))
2907 goto out;
2908 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2909 if (r)
2910 goto out;
2911 r = -EFAULT;
2912 if (copy_to_user(argp, &tac, sizeof tac))
2913 goto out;
2914 r = 0;
2915 break;
2916 };
b93463aa
AK		 2917 case KVM_SET_VAPIC_ADDR: {
2918 struct kvm_vapic_addr va;
2919
2920 r = -EINVAL;
2921 if (!irqchip_in_kernel(vcpu->kvm))
2922 goto out;
2923 r = -EFAULT;
2924 if (copy_from_user(&va, argp, sizeof va))
2925 goto out;
2926 r = 0;
2927 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2928 break;
2929 }
890ca9ae
HY		 2930 case KVM_X86_SETUP_MCE: {
2931 u64 mcg_cap;
2932
2933 r = -EFAULT;
2934 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2935 goto out;
2936 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2937 break;
2938 }
2939 case KVM_X86_SET_MCE: {
2940 struct kvm_x86_mce mce;
2941
2942 r = -EFAULT;
2943 if (copy_from_user(&mce, argp, sizeof mce))
2944 goto out;
2945 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2946 break;
2947 }
3cfc3092
JK		 2948 case KVM_GET_VCPU_EVENTS: {
2949 struct kvm_vcpu_events events;
2950
2951 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2952
2953 r = -EFAULT;
2954 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2955 break;
2956 r = 0;
2957 break;
2958 }
2959 case KVM_SET_VCPU_EVENTS: {
2960 struct kvm_vcpu_events events;
2961
2962 r = -EFAULT;
2963 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2964 break;
2965
2966 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2967 break;
2968 }
a1efbe77
JK		 2969 case KVM_GET_DEBUGREGS: {
2970 struct kvm_debugregs dbgregs;
2971
2972 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2973
2974 r = -EFAULT;
2975 if (copy_to_user(argp, &dbgregs,
2976 sizeof(struct kvm_debugregs)))
2977 break;
2978 r = 0;
2979 break;
2980 }
2981 case KVM_SET_DEBUGREGS: {
2982 struct kvm_debugregs dbgregs;
2983
2984 r = -EFAULT;
2985 if (copy_from_user(&dbgregs, argp,
2986 sizeof(struct kvm_debugregs)))
2987 break;
2988
2989 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2990 break;
2991 }
2d5b5a66 2992 case KVM_GET_XSAVE: {
d1ac91d8 2993 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2994 r = -ENOMEM;
d1ac91d8 2995 if (!u.xsave)
2d5b5a66
SY		 2996 break;
2997
d1ac91d8 2998 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2999
3000 r = -EFAULT;
d1ac91d8 3001 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3002 break;
3003 r = 0;
3004 break;
3005 }
3006 case KVM_SET_XSAVE: {
d1ac91d8 3007 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3008 r = -ENOMEM;
d1ac91d8 3009 if (!u.xsave)
2d5b5a66
SY		 3010 break;
3011
3012 r = -EFAULT;
d1ac91d8 3013 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3014 break;
3015
d1ac91d8 3016 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3017 break;
3018 }
3019 case KVM_GET_XCRS: {
d1ac91d8 3020 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3021 r = -ENOMEM;
d1ac91d8 3022 if (!u.xcrs)
2d5b5a66
SY		 3023 break;
3024
d1ac91d8 3025 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3026
3027 r = -EFAULT;
d1ac91d8 3028 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3029 sizeof(struct kvm_xcrs)))
3030 break;
3031 r = 0;
3032 break;
3033 }
3034 case KVM_SET_XCRS: {
d1ac91d8 3035 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3036 r = -ENOMEM;
d1ac91d8 3037 if (!u.xcrs)
2d5b5a66
SY		 3038 break;
3039
3040 r = -EFAULT;
d1ac91d8 3041 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3042 sizeof(struct kvm_xcrs)))
3043 break;
3044
d1ac91d8 3045 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3046 break;
3047 }
313a3dc7
CO		 3048 default:
3049 r = -EINVAL;
3050 }
3051out:
d1ac91d8 3052 kfree(u.buffer);
313a3dc7
CO		 3053 return r;
3054}
3055
1fe779f8
CO		 3056static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3057{
3058 int ret;
3059
3060 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3061 return -1;
3062 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3063 return ret;
3064}
3065
b927a3ce
SY		 3066static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3067 u64 ident_addr)
3068{
3069 kvm->arch.ept_identity_map_addr = ident_addr;
3070 return 0;
3071}
3072
1fe779f8
CO		 3073static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3074 u32 kvm_nr_mmu_pages)
3075{
3076 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3077 return -EINVAL;
3078
79fac95e 3079 mutex_lock(&kvm->slots_lock);
7c8a83b7 3080 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3081
3082 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3083 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3084
7c8a83b7 3085 spin_unlock(&kvm->mmu_lock);
79fac95e 3086 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3087 return 0;
3088}
3089
3090static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3091{
39de71ec 3092 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3093}
3094
1fe779f8
CO		 3095static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3096{
3097 int r;
3098
3099 r = 0;
3100 switch (chip->chip_id) {
3101 case KVM_IRQCHIP_PIC_MASTER:
3102 memcpy(&chip->chip.pic,
3103 &pic_irqchip(kvm)->pics[0],
3104 sizeof(struct kvm_pic_state));
3105 break;
3106 case KVM_IRQCHIP_PIC_SLAVE:
3107 memcpy(&chip->chip.pic,
3108 &pic_irqchip(kvm)->pics[1],
3109 sizeof(struct kvm_pic_state));
3110 break;
3111 case KVM_IRQCHIP_IOAPIC:
eba0226b 3112 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3113 break;
3114 default:
3115 r = -EINVAL;
3116 break;
3117 }
3118 return r;
3119}
3120
3121static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3122{
3123 int r;
3124
3125 r = 0;
3126 switch (chip->chip_id) {
3127 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3128 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3129 memcpy(&pic_irqchip(kvm)->pics[0],
3130 &chip->chip.pic,
3131 sizeof(struct kvm_pic_state));
f4f51050 3132 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3133 break;
3134 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3135 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3136 memcpy(&pic_irqchip(kvm)->pics[1],
3137 &chip->chip.pic,
3138 sizeof(struct kvm_pic_state));
f4f51050 3139 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3140 break;
3141 case KVM_IRQCHIP_IOAPIC:
eba0226b 3142 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3143 break;
3144 default:
3145 r = -EINVAL;
3146 break;
3147 }
3148 kvm_pic_update_irq(pic_irqchip(kvm));
3149 return r;
3150}
3151
e0f63cb9
SY		 3152static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3153{
3154 int r = 0;
3155
894a9c55 3156 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3157 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3158 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3159 return r;
3160}
3161
3162static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3163{
3164 int r = 0;
3165
894a9c55 3166 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3167 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3168 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3169 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3170 return r;
3171}
3172
3173static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3174{
3175 int r = 0;
3176
3177 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3178 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3179 sizeof(ps->channels));
3180 ps->flags = kvm->arch.vpit->pit_state.flags;
3181 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3182 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3183 return r;
3184}
3185
3186static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3187{
3188 int r = 0, start = 0;
3189 u32 prev_legacy, cur_legacy;
3190 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3191 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3192 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3193 if (!prev_legacy && cur_legacy)
3194 start = 1;
3195 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3196 sizeof(kvm->arch.vpit->pit_state.channels));
3197 kvm->arch.vpit->pit_state.flags = ps->flags;
3198 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3199 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3200 return r;
3201}
3202
52d939a0
MT		 3203static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3204 struct kvm_reinject_control *control)
3205{
3206 if (!kvm->arch.vpit)
3207 return -ENXIO;
894a9c55 3208 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3209 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3210 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3211 return 0;
3212}
3213
5bb064dc
ZX		 3214/*
3215 * Get (and clear) the dirty memory log for a memory slot.
3216 */
3217int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3218 struct kvm_dirty_log *log)
3219{
87bf6e7d 3220 int r, i;
5bb064dc 3221 struct kvm_memory_slot *memslot;
87bf6e7d 3222 unsigned long n;
b050b015 3223 unsigned long is_dirty = 0;
5bb064dc 3224
79fac95e 3225 mutex_lock(&kvm->slots_lock);
5bb064dc 3226
b050b015
MT		 3227 r = -EINVAL;
3228 if (log->slot >= KVM_MEMORY_SLOTS)
3229 goto out;
3230
3231 memslot = &kvm->memslots->memslots[log->slot];
3232 r = -ENOENT;
3233 if (!memslot->dirty_bitmap)
3234 goto out;
3235
87bf6e7d 3236 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3237
b050b015
MT		 3238 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3239 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3240
3241 /* If nothing is dirty, don't bother messing with page tables. */
3242 if (is_dirty) {
b050b015 3243 struct kvm_memslots *slots, *old_slots;
914ebccd 3244 unsigned long *dirty_bitmap;
b050b015 3245
515a0127
TY		 3246 dirty_bitmap = memslot->dirty_bitmap_head;
3247 if (memslot->dirty_bitmap == dirty_bitmap)
3248 dirty_bitmap += n / sizeof(long);
914ebccd 3249 memset(dirty_bitmap, 0, n);
b050b015 3250
914ebccd
TY		 3251 r = -ENOMEM;
3252 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3253 if (!slots)
914ebccd 3254 goto out;
b050b015
MT		 3255 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3256 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3257 slots->generation++;
b050b015
MT		 3258
3259 old_slots = kvm->memslots;
3260 rcu_assign_pointer(kvm->memslots, slots);
3261 synchronize_srcu_expedited(&kvm->srcu);
3262 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3263 kfree(old_slots);
914ebccd 3264
edde99ce
MT		 3265 spin_lock(&kvm->mmu_lock);
3266 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3267 spin_unlock(&kvm->mmu_lock);
3268
914ebccd 3269 r = -EFAULT;
515a0127 3270 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3271 goto out;
914ebccd
TY		 3272 } else {
3273 r = -EFAULT;
3274 if (clear_user(log->dirty_bitmap, n))
3275 goto out;
5bb064dc 3276 }
b050b015 3277
5bb064dc
ZX		 3278 r = 0;
3279out:
79fac95e 3280 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3281 return r;
3282}
3283
1fe779f8
CO		 3284long kvm_arch_vm_ioctl(struct file *filp,
3285 unsigned int ioctl, unsigned long arg)
3286{
3287 struct kvm *kvm = filp->private_data;
3288 void __user *argp = (void __user *)arg;
367e1319 3289 int r = -ENOTTY;
f0d66275
DH		 3290 /*
3291 * This union makes it completely explicit to gcc-3.x
3292 * that these two variables' stack usage should be
3293 * combined, not added together.
3294 */
3295 union {
3296 struct kvm_pit_state ps;
e9f42757 3297 struct kvm_pit_state2 ps2;
c5ff41ce 3298 struct kvm_pit_config pit_config;
f0d66275 3299 } u;
1fe779f8
CO		 3300
3301 switch (ioctl) {
3302 case KVM_SET_TSS_ADDR:
3303 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3304 if (r < 0)
3305 goto out;
3306 break;
b927a3ce
SY		 3307 case KVM_SET_IDENTITY_MAP_ADDR: {
3308 u64 ident_addr;
3309
3310 r = -EFAULT;
3311 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3312 goto out;
3313 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3314 if (r < 0)
3315 goto out;
3316 break;
3317 }
1fe779f8
CO		 3318 case KVM_SET_NR_MMU_PAGES:
3319 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3320 if (r)
3321 goto out;
3322 break;
3323 case KVM_GET_NR_MMU_PAGES:
3324 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3325 break;
3ddea128
MT		 3326 case KVM_CREATE_IRQCHIP: {
3327 struct kvm_pic *vpic;
3328
3329 mutex_lock(&kvm->lock);
3330 r = -EEXIST;
3331 if (kvm->arch.vpic)
3332 goto create_irqchip_unlock;
1fe779f8 3333 r = -ENOMEM;
3ddea128
MT		 3334 vpic = kvm_create_pic(kvm);
3335 if (vpic) {
1fe779f8
CO		 3336 r = kvm_ioapic_init(kvm);
3337 if (r) {
175504cd 3338 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3339 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3340 &vpic->dev);
175504cd 3341 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3342 kfree(vpic);
3343 goto create_irqchip_unlock;
1fe779f8
CO		 3344 }
3345 } else
3ddea128
MT		 3346 goto create_irqchip_unlock;
3347 smp_wmb();
3348 kvm->arch.vpic = vpic;
3349 smp_wmb();
399ec807
AK		 3350 r = kvm_setup_default_irq_routing(kvm);
3351 if (r) {
175504cd 3352 mutex_lock(&kvm->slots_lock);
3ddea128 3353 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3354 kvm_ioapic_destroy(kvm);
3355 kvm_destroy_pic(kvm);
3ddea128 3356 mutex_unlock(&kvm->irq_lock);
175504cd 3357 mutex_unlock(&kvm->slots_lock);
399ec807 3358 }
3ddea128
MT		 3359 create_irqchip_unlock:
3360 mutex_unlock(&kvm->lock);
1fe779f8 3361 break;
3ddea128 3362 }
7837699f 3363 case KVM_CREATE_PIT:
c5ff41ce
JK		 3364 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3365 goto create_pit;
3366 case KVM_CREATE_PIT2:
3367 r = -EFAULT;
3368 if (copy_from_user(&u.pit_config, argp,
3369 sizeof(struct kvm_pit_config)))
3370 goto out;
3371 create_pit:
79fac95e 3372 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3373 r = -EEXIST;
3374 if (kvm->arch.vpit)
3375 goto create_pit_unlock;
7837699f 3376 r = -ENOMEM;
c5ff41ce 3377 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3378 if (kvm->arch.vpit)
3379 r = 0;
269e05e4 3380 create_pit_unlock:
79fac95e 3381 mutex_unlock(&kvm->slots_lock);
7837699f 3382 break;
4925663a 3383 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3384 case KVM_IRQ_LINE: {
3385 struct kvm_irq_level irq_event;
3386
3387 r = -EFAULT;
3388 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3389 goto out;
160d2f6c 3390 r = -ENXIO;
1fe779f8 3391 if (irqchip_in_kernel(kvm)) {
4925663a 3392 __s32 status;
4925663a
GN		 3393 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3394 irq_event.irq, irq_event.level);
4925663a 3395 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3396 r = -EFAULT;
4925663a
GN		 3397 irq_event.status = status;
3398 if (copy_to_user(argp, &irq_event,
3399 sizeof irq_event))
3400 goto out;
3401 }
1fe779f8
CO		 3402 r = 0;
3403 }
3404 break;
3405 }
3406 case KVM_GET_IRQCHIP: {
3407 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3408 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3409
f0d66275
DH		 3410 r = -ENOMEM;
3411 if (!chip)
1fe779f8 3412 goto out;
f0d66275
DH		 3413 r = -EFAULT;
3414 if (copy_from_user(chip, argp, sizeof *chip))
3415 goto get_irqchip_out;
1fe779f8
CO		 3416 r = -ENXIO;
3417 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3418 goto get_irqchip_out;
3419 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3420 if (r)
f0d66275 3421 goto get_irqchip_out;
1fe779f8 3422 r = -EFAULT;
f0d66275
DH		 3423 if (copy_to_user(argp, chip, sizeof *chip))
3424 goto get_irqchip_out;
1fe779f8 3425 r = 0;
f0d66275
DH		 3426 get_irqchip_out:
3427 kfree(chip);
3428 if (r)
3429 goto out;
1fe779f8
CO		 3430 break;
3431 }
3432 case KVM_SET_IRQCHIP: {
3433 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3434 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3435
f0d66275
DH		 3436 r = -ENOMEM;
3437 if (!chip)
1fe779f8 3438 goto out;
f0d66275
DH		 3439 r = -EFAULT;
3440 if (copy_from_user(chip, argp, sizeof *chip))
3441 goto set_irqchip_out;
1fe779f8
CO		 3442 r = -ENXIO;
3443 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3444 goto set_irqchip_out;
3445 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3446 if (r)
f0d66275 3447 goto set_irqchip_out;
1fe779f8 3448 r = 0;
f0d66275
DH		 3449 set_irqchip_out:
3450 kfree(chip);
3451 if (r)
3452 goto out;
1fe779f8
CO		 3453 break;
3454 }
e0f63cb9 3455 case KVM_GET_PIT: {
e0f63cb9 3456 r = -EFAULT;
f0d66275 3457 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3458 goto out;
3459 r = -ENXIO;
3460 if (!kvm->arch.vpit)
3461 goto out;
f0d66275 3462 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3463 if (r)
3464 goto out;
3465 r = -EFAULT;
f0d66275 3466 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3467 goto out;
3468 r = 0;
3469 break;
3470 }
3471 case KVM_SET_PIT: {
e0f63cb9 3472 r = -EFAULT;
f0d66275 3473 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3474 goto out;
3475 r = -ENXIO;
3476 if (!kvm->arch.vpit)
3477 goto out;
f0d66275 3478 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3479 if (r)
3480 goto out;
3481 r = 0;
3482 break;
3483 }
e9f42757
BK		 3484 case KVM_GET_PIT2: {
3485 r = -ENXIO;
3486 if (!kvm->arch.vpit)
3487 goto out;
3488 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3489 if (r)
3490 goto out;
3491 r = -EFAULT;
3492 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3493 goto out;
3494 r = 0;
3495 break;
3496 }
3497 case KVM_SET_PIT2: {
3498 r = -EFAULT;
3499 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3500 goto out;
3501 r = -ENXIO;
3502 if (!kvm->arch.vpit)
3503 goto out;
3504 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3505 if (r)
3506 goto out;
3507 r = 0;
3508 break;
3509 }
52d939a0
MT		 3510 case KVM_REINJECT_CONTROL: {
3511 struct kvm_reinject_control control;
3512 r = -EFAULT;
3513 if (copy_from_user(&control, argp, sizeof(control)))
3514 goto out;
3515 r = kvm_vm_ioctl_reinject(kvm, &control);
3516 if (r)
3517 goto out;
3518 r = 0;
3519 break;
3520 }
ffde22ac
ES		 3521 case KVM_XEN_HVM_CONFIG: {
3522 r = -EFAULT;
3523 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3524 sizeof(struct kvm_xen_hvm_config)))
3525 goto out;
3526 r = -EINVAL;
3527 if (kvm->arch.xen_hvm_config.flags)
3528 goto out;
3529 r = 0;
3530 break;
3531 }
afbcf7ab 3532 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3533 struct kvm_clock_data user_ns;
3534 u64 now_ns;
3535 s64 delta;
3536
3537 r = -EFAULT;
3538 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3539 goto out;
3540
3541 r = -EINVAL;
3542 if (user_ns.flags)
3543 goto out;
3544
3545 r = 0;
395c6b0a 3546 local_irq_disable();
759379dd 3547 now_ns = get_kernel_ns();
afbcf7ab 3548 delta = user_ns.clock - now_ns;
395c6b0a 3549 local_irq_enable();
afbcf7ab
GC		 3550 kvm->arch.kvmclock_offset = delta;
3551 break;
3552 }
3553 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3554 struct kvm_clock_data user_ns;
3555 u64 now_ns;
3556
395c6b0a 3557 local_irq_disable();
759379dd 3558 now_ns = get_kernel_ns();
afbcf7ab 3559 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3560 local_irq_enable();
afbcf7ab 3561 user_ns.flags = 0;
97e69aa6 3562 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3563
3564 r = -EFAULT;
3565 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3566 goto out;
3567 r = 0;
3568 break;
3569 }
3570
1fe779f8
CO		 3571 default:
3572 ;
3573 }
3574out:
3575 return r;
3576}
3577
a16b043c 3578static void kvm_init_msr_list(void)
043405e1
CO		 3579{
3580 u32 dummy[2];
3581 unsigned i, j;
3582
e3267cbb
GC		 3583 /* skip the first msrs in the list. KVM-specific */
3584 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3585 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3586 continue;
3587 if (j < i)
3588 msrs_to_save[j] = msrs_to_save[i];
3589 j++;
3590 }
3591 num_msrs_to_save = j;
3592}
3593
bda9020e
MT		 3594static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3595 const void *v)
bbd9b64e 3596{
bda9020e
MT		 3597 if (vcpu->arch.apic &&
3598 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3599 return 0;
bbd9b64e 3600
e93f8a0f 3601 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3602}
3603
bda9020e 3604static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3605{
bda9020e
MT		 3606 if (vcpu->arch.apic &&
3607 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3608 return 0;
bbd9b64e 3609
e93f8a0f 3610 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3611}
3612
2dafc6c2
GN		 3613static void kvm_set_segment(struct kvm_vcpu *vcpu,
3614 struct kvm_segment *var, int seg)
3615{
3616 kvm_x86_ops->set_segment(vcpu, var, seg);
3617}
3618
3619void kvm_get_segment(struct kvm_vcpu *vcpu,
3620 struct kvm_segment *var, int seg)
3621{
3622 kvm_x86_ops->get_segment(vcpu, var, seg);
3623}
3624
c30a358d
JR		 3625static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3626{
3627 return gpa;
3628}
3629
02f59dc9
JR		 3630static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3631{
3632 gpa_t t_gpa;
ab9ae313 3633 struct x86_exception exception;
02f59dc9
JR		 3634
3635 BUG_ON(!mmu_is_nested(vcpu));
3636
3637 /* NPT walks are always user-walks */
3638 access |= PFERR_USER_MASK;
ab9ae313 3639 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3640
3641 return t_gpa;
3642}
3643
ab9ae313
AK		 3644gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3645 struct x86_exception *exception)
1871c602
GN		 3646{
3647 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3648 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3649}
3650
ab9ae313
AK		 3651 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3652 struct x86_exception *exception)
1871c602
GN		 3653{
3654 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3655 access |= PFERR_FETCH_MASK;
ab9ae313 3656 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3657}
3658
ab9ae313
AK		 3659gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3660 struct x86_exception *exception)
1871c602
GN		 3661{
3662 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3663 access |= PFERR_WRITE_MASK;
ab9ae313 3664 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3665}
3666
3667/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3668gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3669 struct x86_exception *exception)
1871c602 3670{
ab9ae313 3671 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3672}
3673
3674static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3675 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3676 struct x86_exception *exception)
bbd9b64e
CO		 3677{
3678 void *data = val;
10589a46 3679 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3680
3681 while (bytes) {
14dfe855 3682 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3683 exception);
bbd9b64e 3684 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3685 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3686 int ret;
3687
bcc55cba 3688 if (gpa == UNMAPPED_GVA)
ab9ae313 3689 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3690 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3691 if (ret < 0) {
c3cd7ffa 3692 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3693 goto out;
3694 }
bbd9b64e 3695
77c2002e
IE		 3696 bytes -= toread;
3697 data += toread;
3698 addr += toread;
bbd9b64e 3699 }
10589a46 3700out:
10589a46 3701 return r;
bbd9b64e 3702}
77c2002e 3703
1871c602
GN		 3704/* used for instruction fetching */
3705static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3706 struct kvm_vcpu *vcpu,
3707 struct x86_exception *exception)
1871c602
GN		 3708{
3709 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3710 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3711 access | PFERR_FETCH_MASK,
3712 exception);
1871c602
GN		 3713}
3714
3715static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3716 struct kvm_vcpu *vcpu,
3717 struct x86_exception *exception)
1871c602
GN		 3718{
3719 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3720 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3721 exception);
1871c602
GN		 3722}
3723
3724static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3725 struct kvm_vcpu *vcpu,
3726 struct x86_exception *exception)
1871c602 3727{
bcc55cba 3728 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3729}
3730
7972995b 3731static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3732 unsigned int bytes,
7972995b 3733 struct kvm_vcpu *vcpu,
bcc55cba 3734 struct x86_exception *exception)
77c2002e
IE		 3735{
3736 void *data = val;
3737 int r = X86EMUL_CONTINUE;
3738
3739 while (bytes) {
14dfe855
JR		 3740 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3741 PFERR_WRITE_MASK,
ab9ae313 3742 exception);
77c2002e
IE		 3743 unsigned offset = addr & (PAGE_SIZE-1);
3744 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3745 int ret;
3746
bcc55cba 3747 if (gpa == UNMAPPED_GVA)
ab9ae313 3748 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3749 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3750 if (ret < 0) {
c3cd7ffa 3751 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3752 goto out;
3753 }
3754
3755 bytes -= towrite;
3756 data += towrite;
3757 addr += towrite;
3758 }
3759out:
3760 return r;
3761}
3762
bbd9b64e
CO		 3763static int emulator_read_emulated(unsigned long addr,
3764 void *val,
3765 unsigned int bytes,
bcc55cba 3766 struct x86_exception *exception,
bbd9b64e
CO		 3767 struct kvm_vcpu *vcpu)
3768{
bbd9b64e
CO		 3769 gpa_t gpa;
3770
3771 if (vcpu->mmio_read_completed) {
3772 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3773 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3774 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3775 vcpu->mmio_read_completed = 0;
3776 return X86EMUL_CONTINUE;
3777 }
3778
ab9ae313 3779 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3780
8fe681e9 3781 if (gpa == UNMAPPED_GVA)
1871c602 3782 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3783
3784 /* For APIC access vmexit */
3785 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3786 goto mmio;
3787
bcc55cba
AK		 3788 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3789 == X86EMUL_CONTINUE)
bbd9b64e 3790 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3791
3792mmio:
3793 /*
3794 * Is this MMIO handled locally?
3795 */
aec51dc4
AK		 3796 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3797 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3798 return X86EMUL_CONTINUE;
3799 }
aec51dc4
AK		 3800
3801 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3802
3803 vcpu->mmio_needed = 1;
411c35b7
GN		 3804 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3805 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3806 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3807 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3808
c3cd7ffa 3809 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3810}
3811
3200f405 3812int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3813 const void *val, int bytes)
bbd9b64e
CO		 3814{
3815 int ret;
3816
3817 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3818 if (ret < 0)
bbd9b64e 3819 return 0;
ad218f85 3820 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3821 return 1;
3822}
3823
3824static int emulator_write_emulated_onepage(unsigned long addr,
3825 const void *val,
3826 unsigned int bytes,
bcc55cba 3827 struct x86_exception *exception,
bbd9b64e
CO		 3828 struct kvm_vcpu *vcpu)
3829{
10589a46
MT		 3830 gpa_t gpa;
3831
ab9ae313 3832 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3833
8fe681e9 3834 if (gpa == UNMAPPED_GVA)
bbd9b64e 3835 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3836
3837 /* For APIC access vmexit */
3838 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3839 goto mmio;
3840
3841 if (emulator_write_phys(vcpu, gpa, val, bytes))
3842 return X86EMUL_CONTINUE;
3843
3844mmio:
aec51dc4 3845 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3846 /*
3847 * Is this MMIO handled locally?
3848 */
bda9020e 3849 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3850 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3851
3852 vcpu->mmio_needed = 1;
411c35b7
GN		 3853 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3854 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3855 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3856 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3857 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3858
3859 return X86EMUL_CONTINUE;
3860}
3861
3862int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3863 const void *val,
3864 unsigned int bytes,
bcc55cba 3865 struct x86_exception *exception,
8f6abd06 3866 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3867{
3868 /* Crossing a page boundary? */
3869 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3870 int rc, now;
3871
3872 now = -addr & ~PAGE_MASK;
bcc55cba 3873 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3874 vcpu);
bbd9b64e
CO		 3875 if (rc != X86EMUL_CONTINUE)
3876 return rc;
3877 addr += now;
3878 val += now;
3879 bytes -= now;
3880 }
bcc55cba 3881 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3882 vcpu);
bbd9b64e 3883}
bbd9b64e 3884
daea3e73
AK		 3885#define CMPXCHG_TYPE(t, ptr, old, new) \
3886 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3887
3888#ifdef CONFIG_X86_64
3889# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3890#else
3891# define CMPXCHG64(ptr, old, new) \
9749a6c0 3892 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3893#endif
3894
bbd9b64e
CO		 3895static int emulator_cmpxchg_emulated(unsigned long addr,
3896 const void *old,
3897 const void *new,
3898 unsigned int bytes,
bcc55cba 3899 struct x86_exception *exception,
bbd9b64e
CO		 3900 struct kvm_vcpu *vcpu)
3901{
daea3e73
AK		 3902 gpa_t gpa;
3903 struct page *page;
3904 char *kaddr;
3905 bool exchanged;
2bacc55c 3906
daea3e73
AK		 3907 /* guests cmpxchg8b have to be emulated atomically */
3908 if (bytes > 8 || (bytes & (bytes - 1)))
3909 goto emul_write;
10589a46 3910
daea3e73 3911 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3912
daea3e73
AK		 3913 if (gpa == UNMAPPED_GVA ||
3914 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3915 goto emul_write;
2bacc55c 3916
daea3e73
AK		 3917 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3918 goto emul_write;
72dc67a6 3919
daea3e73 3920 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3921 if (is_error_page(page)) {
3922 kvm_release_page_clean(page);
3923 goto emul_write;
3924 }
72dc67a6 3925
daea3e73
AK		 3926 kaddr = kmap_atomic(page, KM_USER0);
3927 kaddr += offset_in_page(gpa);
3928 switch (bytes) {
3929 case 1:
3930 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3931 break;
3932 case 2:
3933 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3934 break;
3935 case 4:
3936 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3937 break;
3938 case 8:
3939 exchanged = CMPXCHG64(kaddr, old, new);
3940 break;
3941 default:
3942 BUG();
2bacc55c 3943 }
daea3e73
AK		 3944 kunmap_atomic(kaddr, KM_USER0);
3945 kvm_release_page_dirty(page);
3946
3947 if (!exchanged)
3948 return X86EMUL_CMPXCHG_FAILED;
3949
8f6abd06
GN		 3950 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3951
3952 return X86EMUL_CONTINUE;
4a5f48f6 3953
3200f405 3954emul_write:
daea3e73 3955 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3956
bcc55cba 3957 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 3958}
3959
cf8f70bf
GN		 3960static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3961{
3962 /* TODO: String I/O for in kernel device */
3963 int r;
3964
3965 if (vcpu->arch.pio.in)
3966 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3967 vcpu->arch.pio.size, pd);
3968 else
3969 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3970 vcpu->arch.pio.port, vcpu->arch.pio.size,
3971 pd);
3972 return r;
3973}
3974
3975
3976static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3977 unsigned int count, struct kvm_vcpu *vcpu)
3978{
7972995b 3979 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3980 goto data_avail;
3981
61cfab2e 3982 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 3983
3984 vcpu->arch.pio.port = port;
3985 vcpu->arch.pio.in = 1;
7972995b 3986 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3987 vcpu->arch.pio.size = size;
3988
3989 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3990 data_avail:
3991 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3992 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3993 return 1;
3994 }
3995
3996 vcpu->run->exit_reason = KVM_EXIT_IO;
3997 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3998 vcpu->run->io.size = size;
3999 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4000 vcpu->run->io.count = count;
4001 vcpu->run->io.port = port;
4002
4003 return 0;
4004}
4005
4006static int emulator_pio_out_emulated(int size, unsigned short port,
4007 const void *val, unsigned int count,
4008 struct kvm_vcpu *vcpu)
4009{
61cfab2e 4010 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4011
4012 vcpu->arch.pio.port = port;
4013 vcpu->arch.pio.in = 0;
7972995b 4014 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4015 vcpu->arch.pio.size = size;
4016
4017 memcpy(vcpu->arch.pio_data, val, size * count);
4018
4019 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4020 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4021 return 1;
4022 }
4023
4024 vcpu->run->exit_reason = KVM_EXIT_IO;
4025 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4026 vcpu->run->io.size = size;
4027 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4028 vcpu->run->io.count = count;
4029 vcpu->run->io.port = port;
4030
4031 return 0;
4032}
4033
bbd9b64e
CO		 4034static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4035{
4036 return kvm_x86_ops->get_segment_base(vcpu, seg);
4037}
4038
4039int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4040{
a7052897 4041 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4042 return X86EMUL_CONTINUE;
4043}
4044
f5f48ee1
SY		 4045int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4046{
4047 if (!need_emulate_wbinvd(vcpu))
4048 return X86EMUL_CONTINUE;
4049
4050 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4051 int cpu = get_cpu();
4052
4053 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4054 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4055 wbinvd_ipi, NULL, 1);
2eec7343 4056 put_cpu();
f5f48ee1 4057 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4058 } else
4059 wbinvd();
f5f48ee1
SY		 4060 return X86EMUL_CONTINUE;
4061}
4062EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4063
bbd9b64e
CO		 4064int emulate_clts(struct kvm_vcpu *vcpu)
4065{
4d4ec087 4066 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4067 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4068 return X86EMUL_CONTINUE;
4069}
4070
35aa5375 4071int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4072{
338dbc97 4073 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4074}
4075
35aa5375 4076int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4077{
338dbc97
GN		 4078
4079 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4080}
4081
52a46617 4082static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4083{
52a46617 4084 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4085}
4086
52a46617 4087static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4088{
52a46617
GN		 4089 unsigned long value;
4090
4091 switch (cr) {
4092 case 0:
4093 value = kvm_read_cr0(vcpu);
4094 break;
4095 case 2:
4096 value = vcpu->arch.cr2;
4097 break;
4098 case 3:
9f8fe504 4099 value = kvm_read_cr3(vcpu);
52a46617
GN		 4100 break;
4101 case 4:
4102 value = kvm_read_cr4(vcpu);
4103 break;
4104 case 8:
4105 value = kvm_get_cr8(vcpu);
4106 break;
4107 default:
4108 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4109 return 0;
4110 }
4111
4112 return value;
4113}
4114
0f12244f 4115static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4116{
0f12244f
GN		 4117 int res = 0;
4118
52a46617
GN		 4119 switch (cr) {
4120 case 0:
49a9b07e 4121 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4122 break;
4123 case 2:
4124 vcpu->arch.cr2 = val;
4125 break;
4126 case 3:
2390218b 4127 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4128 break;
4129 case 4:
a83b29c6 4130 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4131 break;
4132 case 8:
eea1cff9 4133 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4134 break;
4135 default:
4136 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4137 res = -1;
52a46617 4138 }
0f12244f
GN		 4139
4140 return res;
52a46617
GN		 4141}
4142
9c537244
GN		 4143static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4144{
4145 return kvm_x86_ops->get_cpl(vcpu);
4146}
4147
2dafc6c2
GN		 4148static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4149{
4150 kvm_x86_ops->get_gdt(vcpu, dt);
4151}
4152
160ce1f1
MG		 4153static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4154{
4155 kvm_x86_ops->get_idt(vcpu, dt);
4156}
4157
5951c442
GN		 4158static unsigned long emulator_get_cached_segment_base(int seg,
4159 struct kvm_vcpu *vcpu)
4160{
4161 return get_segment_base(vcpu, seg);
4162}
4163
2dafc6c2
GN		 4164static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4165 struct kvm_vcpu *vcpu)
4166{
4167 struct kvm_segment var;
4168
4169 kvm_get_segment(vcpu, &var, seg);
4170
4171 if (var.unusable)
4172 return false;
4173
4174 if (var.g)
4175 var.limit >>= 12;
4176 set_desc_limit(desc, var.limit);
4177 set_desc_base(desc, (unsigned long)var.base);
4178 desc->type = var.type;
4179 desc->s = var.s;
4180 desc->dpl = var.dpl;
4181 desc->p = var.present;
4182 desc->avl = var.avl;
4183 desc->l = var.l;
4184 desc->d = var.db;
4185 desc->g = var.g;
4186
4187 return true;
4188}
4189
4190static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4191 struct kvm_vcpu *vcpu)
4192{
4193 struct kvm_segment var;
4194
4195 /* needed to preserve selector */
4196 kvm_get_segment(vcpu, &var, seg);
4197
4198 var.base = get_desc_base(desc);
4199 var.limit = get_desc_limit(desc);
4200 if (desc->g)
4201 var.limit = (var.limit << 12) | 0xfff;
4202 var.type = desc->type;
4203 var.present = desc->p;
4204 var.dpl = desc->dpl;
4205 var.db = desc->d;
4206 var.s = desc->s;
4207 var.l = desc->l;
4208 var.g = desc->g;
4209 var.avl = desc->avl;
4210 var.present = desc->p;
4211 var.unusable = !var.present;
4212 var.padding = 0;
4213
4214 kvm_set_segment(vcpu, &var, seg);
4215 return;
4216}
4217
4218static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4219{
4220 struct kvm_segment kvm_seg;
4221
4222 kvm_get_segment(vcpu, &kvm_seg, seg);
4223 return kvm_seg.selector;
4224}
4225
4226static void emulator_set_segment_selector(u16 sel, int seg,
4227 struct kvm_vcpu *vcpu)
4228{
4229 struct kvm_segment kvm_seg;
4230
4231 kvm_get_segment(vcpu, &kvm_seg, seg);
4232 kvm_seg.selector = sel;
4233 kvm_set_segment(vcpu, &kvm_seg, seg);
4234}
4235
14af3f3c 4236static struct x86_emulate_ops emulate_ops = {
1871c602 4237 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4238 .write_std = kvm_write_guest_virt_system,
1871c602 4239 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4240 .read_emulated = emulator_read_emulated,
4241 .write_emulated = emulator_write_emulated,
4242 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4243 .pio_in_emulated = emulator_pio_in_emulated,
4244 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4245 .get_cached_descriptor = emulator_get_cached_descriptor,
4246 .set_cached_descriptor = emulator_set_cached_descriptor,
4247 .get_segment_selector = emulator_get_segment_selector,
4248 .set_segment_selector = emulator_set_segment_selector,
5951c442 4249 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4250 .get_gdt = emulator_get_gdt,
160ce1f1 4251 .get_idt = emulator_get_idt,
52a46617
GN		 4252 .get_cr = emulator_get_cr,
4253 .set_cr = emulator_set_cr,
9c537244 4254 .cpl = emulator_get_cpl,
35aa5375
GN		 4255 .get_dr = emulator_get_dr,
4256 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4257 .set_msr = kvm_set_msr,
4258 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4259};
4260
5fdbf976
MT		 4261static void cache_all_regs(struct kvm_vcpu *vcpu)
4262{
4263 kvm_register_read(vcpu, VCPU_REGS_RAX);
4264 kvm_register_read(vcpu, VCPU_REGS_RSP);
4265 kvm_register_read(vcpu, VCPU_REGS_RIP);
4266 vcpu->arch.regs_dirty = ~0;
4267}
4268
95cb2295
GN		 4269static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4270{
4271 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4272 /*
4273 * an sti; sti; sequence only disable interrupts for the first
4274 * instruction. So, if the last instruction, be it emulated or
4275 * not, left the system with the INT_STI flag enabled, it
4276 * means that the last instruction is an sti. We should not
4277 * leave the flag on in this case. The same goes for mov ss
4278 */
4279 if (!(int_shadow & mask))
4280 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4281}
4282
54b8486f
GN		 4283static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4284{
4285 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4286 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4287 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4288 else if (ctxt->exception.error_code_valid)
4289 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4290 ctxt->exception.error_code);
54b8486f 4291 else
da9cb575 4292 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4293}
4294
8ec4722d
MG		 4295static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4296{
4297 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4298 int cs_db, cs_l;
4299
4300 cache_all_regs(vcpu);
4301
4302 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4303
4304 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4305 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4306 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4307 vcpu->arch.emulate_ctxt.mode =
4308 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4309 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4310 ? X86EMUL_MODE_VM86 : cs_l
4311 ? X86EMUL_MODE_PROT64 : cs_db
4312 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4313 memset(c, 0, sizeof(struct decode_cache));
4314 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4315}
4316
63995653
MG		 4317int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4318{
4319 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4320 int ret;
4321
4322 init_emulate_ctxt(vcpu);
4323
4324 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4325 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4326 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4327 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4328
4329 if (ret != X86EMUL_CONTINUE)
4330 return EMULATE_FAIL;
4331
4332 vcpu->arch.emulate_ctxt.eip = c->eip;
4333 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4334 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4335 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4336
4337 if (irq == NMI_VECTOR)
4338 vcpu->arch.nmi_pending = false;
4339 else
4340 vcpu->arch.interrupt.pending = false;
4341
4342 return EMULATE_DONE;
4343}
4344EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4345
6d77dbfc
GN		 4346static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4347{
fc3a9157
JR		 4348 int r = EMULATE_DONE;
4349
6d77dbfc
GN		 4350 ++vcpu->stat.insn_emulation_fail;
4351 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4352 if (!is_guest_mode(vcpu)) {
4353 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4354 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4355 vcpu->run->internal.ndata = 0;
4356 r = EMULATE_FAIL;
4357 }
6d77dbfc 4358 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4359
4360 return r;
6d77dbfc
GN		 4361}
4362
a6f177ef
GN		 4363static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4364{
4365 gpa_t gpa;
4366
68be0803
GN		 4367 if (tdp_enabled)
4368 return false;
4369
a6f177ef
GN		 4370 /*
4371 * if emulation was due to access to shadowed page table
4372 * and it failed try to unshadow page and re-entetr the
4373 * guest to let CPU execute the instruction.
4374 */
4375 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4376 return true;
4377
4378 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4379
4380 if (gpa == UNMAPPED_GVA)
4381 return true; /* let cpu generate fault */
4382
4383 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4384 return true;
4385
4386 return false;
4387}
4388
51d8b661
AP		 4389int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4390 unsigned long cr2,
dc25e89e
AP		 4391 int emulation_type,
4392 void *insn,
4393 int insn_len)
bbd9b64e 4394{
95cb2295 4395 int r;
4d2179e1 4396 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4397
26eef70c 4398 kvm_clear_exception_queue(vcpu);
ad312c7c 4399 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4400 /*
56e82318 4401 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4402 * instead of direct ->regs accesses, can save hundred cycles
4403 * on Intel for instructions that don't read/change RSP, for
4404 * for example.
4405 */
4406 cache_all_regs(vcpu);
bbd9b64e 4407
571008da 4408 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4409 init_emulate_ctxt(vcpu);
95cb2295 4410 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4411 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4412 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4413
dc25e89e 4414 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4415
e46479f8 4416 trace_kvm_emulate_insn_start(vcpu);
571008da 4417
0cb5762e
AP		 4418 /* Only allow emulation of specific instructions on #UD
4419 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4420 if (emulation_type & EMULTYPE_TRAP_UD) {
4421 if (!c->twobyte)
4422 return EMULATE_FAIL;
4423 switch (c->b) {
4424 case 0x01: /* VMMCALL */
4425 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4426 return EMULATE_FAIL;
4427 break;
4428 case 0x34: /* sysenter */
4429 case 0x35: /* sysexit */
4430 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4431 return EMULATE_FAIL;
4432 break;
4433 case 0x05: /* syscall */
4434 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4435 return EMULATE_FAIL;
4436 break;
4437 default:
4438 return EMULATE_FAIL;
4439 }
4440
4441 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4442 return EMULATE_FAIL;
4443 }
571008da 4444
f2b5756b 4445 ++vcpu->stat.insn_emulation;
bbd9b64e 4446 if (r) {
a6f177ef 4447 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4448 return EMULATE_DONE;
6d77dbfc
GN		 4449 if (emulation_type & EMULTYPE_SKIP)
4450 return EMULATE_FAIL;
4451 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4452 }
4453 }
4454
ba8afb6b
GN		 4455 if (emulation_type & EMULTYPE_SKIP) {
4456 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4457 return EMULATE_DONE;
4458 }
4459
4d2179e1
GN		 4460 /* this is needed for vmware backdor interface to work since it
4461 changes registers values during IO operation */
4462 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4463
5cd21917 4464restart:
9aabc88f 4465 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4466
d2ddd1c4 4467 if (r == EMULATION_FAILED) {
a6f177ef 4468 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4469 return EMULATE_DONE;
4470
6d77dbfc 4471 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4472 }
4473
da9cb575 4474 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4475 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4476 r = EMULATE_DONE;
4477 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4478 if (!vcpu->arch.pio.in)
4479 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4480 r = EMULATE_DO_MMIO;
4481 } else if (vcpu->mmio_needed) {
3457e419
GN		 4482 if (vcpu->mmio_is_write)
4483 vcpu->mmio_needed = 0;
e85d28f8 4484 r = EMULATE_DO_MMIO;
d2ddd1c4 4485 } else if (r == EMULATION_RESTART)
5cd21917 4486 goto restart;
d2ddd1c4
GN		 4487 else
4488 r = EMULATE_DONE;
f850e2e6 4489
e85d28f8
GN		 4490 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4491 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4492 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4493 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4494 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4495
4496 return r;
de7d789a 4497}
51d8b661 4498EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4499
cf8f70bf 4500int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4501{
cf8f70bf
GN		 4502 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4503 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4504 /* do not return to emulator after return from userspace */
7972995b 4505 vcpu->arch.pio.count = 0;
de7d789a
CO		 4506 return ret;
4507}
cf8f70bf 4508EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4509
8cfdc000
ZA		 4510static void tsc_bad(void *info)
4511{
0a3aee0d 4512 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4513}
4514
4515static void tsc_khz_changed(void *data)
c8076604 4516{
8cfdc000
ZA		 4517 struct cpufreq_freqs *freq = data;
4518 unsigned long khz = 0;
4519
4520 if (data)
4521 khz = freq->new;
4522 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4523 khz = cpufreq_quick_get(raw_smp_processor_id());
4524 if (!khz)
4525 khz = tsc_khz;
0a3aee0d 4526 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4527}
4528
c8076604
GH		 4529static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4530 void *data)
4531{
4532 struct cpufreq_freqs *freq = data;
4533 struct kvm *kvm;
4534 struct kvm_vcpu *vcpu;
4535 int i, send_ipi = 0;
4536
8cfdc000
ZA		 4537 /*
4538 * We allow guests to temporarily run on slowing clocks,
4539 * provided we notify them after, or to run on accelerating
4540 * clocks, provided we notify them before. Thus time never
4541 * goes backwards.
4542 *
4543 * However, we have a problem. We can't atomically update
4544 * the frequency of a given CPU from this function; it is
4545 * merely a notifier, which can be called from any CPU.
4546 * Changing the TSC frequency at arbitrary points in time
4547 * requires a recomputation of local variables related to
4548 * the TSC for each VCPU. We must flag these local variables
4549 * to be updated and be sure the update takes place with the
4550 * new frequency before any guests proceed.
4551 *
4552 * Unfortunately, the combination of hotplug CPU and frequency
4553 * change creates an intractable locking scenario; the order
4554 * of when these callouts happen is undefined with respect to
4555 * CPU hotplug, and they can race with each other. As such,
4556 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4557 * undefined; you can actually have a CPU frequency change take
4558 * place in between the computation of X and the setting of the
4559 * variable. To protect against this problem, all updates of
4560 * the per_cpu tsc_khz variable are done in an interrupt
4561 * protected IPI, and all callers wishing to update the value
4562 * must wait for a synchronous IPI to complete (which is trivial
4563 * if the caller is on the CPU already). This establishes the
4564 * necessary total order on variable updates.
4565 *
4566 * Note that because a guest time update may take place
4567 * anytime after the setting of the VCPU's request bit, the
4568 * correct TSC value must be set before the request. However,
4569 * to ensure the update actually makes it to any guest which
4570 * starts running in hardware virtualization between the set
4571 * and the acquisition of the spinlock, we must also ping the
4572 * CPU after setting the request bit.
4573 *
4574 */
4575
c8076604
GH		 4576 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4577 return 0;
4578 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4579 return 0;
8cfdc000
ZA		 4580
4581 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4582
4583 spin_lock(&kvm_lock);
4584 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4585 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4586 if (vcpu->cpu != freq->cpu)
4587 continue;
c285545f 4588 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4589 if (vcpu->cpu != smp_processor_id())
8cfdc000 4590 send_ipi = 1;
c8076604
GH		 4591 }
4592 }
4593 spin_unlock(&kvm_lock);
4594
4595 if (freq->old < freq->new && send_ipi) {
4596 /*
4597 * We upscale the frequency. Must make the guest
4598 * doesn't see old kvmclock values while running with
4599 * the new frequency, otherwise we risk the guest sees
4600 * time go backwards.
4601 *
4602 * In case we update the frequency for another cpu
4603 * (which might be in guest context) send an interrupt
4604 * to kick the cpu out of guest context. Next time
4605 * guest context is entered kvmclock will be updated,
4606 * so the guest will not see stale values.
4607 */
8cfdc000 4608 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4609 }
4610 return 0;
4611}
4612
4613static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4614 .notifier_call = kvmclock_cpufreq_notifier
4615};
4616
4617static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4618 unsigned long action, void *hcpu)
4619{
4620 unsigned int cpu = (unsigned long)hcpu;
4621
4622 switch (action) {
4623 case CPU_ONLINE:
4624 case CPU_DOWN_FAILED:
4625 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4626 break;
4627 case CPU_DOWN_PREPARE:
4628 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4629 break;
4630 }
4631 return NOTIFY_OK;
4632}
4633
4634static struct notifier_block kvmclock_cpu_notifier_block = {
4635 .notifier_call = kvmclock_cpu_notifier,
4636 .priority = -INT_MAX
c8076604
GH		 4637};
4638
b820cc0c
ZA		 4639static void kvm_timer_init(void)
4640{
4641 int cpu;
4642
c285545f 4643 max_tsc_khz = tsc_khz;
8cfdc000 4644 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4645 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4646#ifdef CONFIG_CPU_FREQ
4647 struct cpufreq_policy policy;
4648 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4649 cpu = get_cpu();
4650 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4651 if (policy.cpuinfo.max_freq)
4652 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4653 put_cpu();
c285545f 4654#endif
b820cc0c
ZA		 4655 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4656 CPUFREQ_TRANSITION_NOTIFIER);
4657 }
c285545f 4658 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4659 for_each_online_cpu(cpu)
4660 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4661}
4662
ff9d07a0
ZY		 4663static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4664
4665static int kvm_is_in_guest(void)
4666{
4667 return percpu_read(current_vcpu) != NULL;
4668}
4669
4670static int kvm_is_user_mode(void)
4671{
4672 int user_mode = 3;
dcf46b94 4673
ff9d07a0
ZY		 4674 if (percpu_read(current_vcpu))
4675 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4676
ff9d07a0
ZY		 4677 return user_mode != 0;
4678}
4679
4680static unsigned long kvm_get_guest_ip(void)
4681{
4682 unsigned long ip = 0;
dcf46b94 4683
ff9d07a0
ZY		 4684 if (percpu_read(current_vcpu))
4685 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4686
ff9d07a0
ZY		 4687 return ip;
4688}
4689
4690static struct perf_guest_info_callbacks kvm_guest_cbs = {
4691 .is_in_guest = kvm_is_in_guest,
4692 .is_user_mode = kvm_is_user_mode,
4693 .get_guest_ip = kvm_get_guest_ip,
4694};
4695
4696void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4697{
4698 percpu_write(current_vcpu, vcpu);
4699}
4700EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4701
4702void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4703{
4704 percpu_write(current_vcpu, NULL);
4705}
4706EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4707
f8c16bba 4708int kvm_arch_init(void *opaque)
043405e1 4709{
b820cc0c 4710 int r;
f8c16bba
ZX		 4711 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4712
f8c16bba
ZX		 4713 if (kvm_x86_ops) {
4714 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4715 r = -EEXIST;
4716 goto out;
f8c16bba
ZX		 4717 }
4718
4719 if (!ops->cpu_has_kvm_support()) {
4720 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4721 r = -EOPNOTSUPP;
4722 goto out;
f8c16bba
ZX		 4723 }
4724 if (ops->disabled_by_bios()) {
4725 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4726 r = -EOPNOTSUPP;
4727 goto out;
f8c16bba
ZX		 4728 }
4729
97db56ce
AK		 4730 r = kvm_mmu_module_init();
4731 if (r)
4732 goto out;
4733
4734 kvm_init_msr_list();
4735
f8c16bba 4736 kvm_x86_ops = ops;
56c6d28a 4737 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4738 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4739 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4740
b820cc0c 4741 kvm_timer_init();
c8076604 4742
ff9d07a0
ZY		 4743 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4744
2acf923e
DC		 4745 if (cpu_has_xsave)
4746 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4747
f8c16bba 4748 return 0;
56c6d28a
ZX		 4749
4750out:
56c6d28a 4751 return r;
043405e1 4752}
8776e519 4753
f8c16bba
ZX		 4754void kvm_arch_exit(void)
4755{
ff9d07a0
ZY		 4756 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4757
888d256e
JK		 4758 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4759 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4760 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4761 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4762 kvm_x86_ops = NULL;
56c6d28a
ZX		 4763 kvm_mmu_module_exit();
4764}
f8c16bba 4765
8776e519
HB		 4766int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4767{
4768 ++vcpu->stat.halt_exits;
4769 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4770 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4771 return 1;
4772 } else {
4773 vcpu->run->exit_reason = KVM_EXIT_HLT;
4774 return 0;
4775 }
4776}
4777EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4778
2f333bcb
MT		 4779static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4780 unsigned long a1)
4781{
4782 if (is_long_mode(vcpu))
4783 return a0;
4784 else
4785 return a0 | ((gpa_t)a1 << 32);
4786}
4787
55cd8e5a
GN		 4788int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4789{
4790 u64 param, ingpa, outgpa, ret;
4791 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4792 bool fast, longmode;
4793 int cs_db, cs_l;
4794
4795 /*
4796 * hypercall generates UD from non zero cpl and real mode
4797 * per HYPER-V spec
4798 */
3eeb3288 4799 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4800 kvm_queue_exception(vcpu, UD_VECTOR);
4801 return 0;
4802 }
4803
4804 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4805 longmode = is_long_mode(vcpu) && cs_l == 1;
4806
4807 if (!longmode) {
ccd46936
GN		 4808 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4809 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4810 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4811 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4812 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4813 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4814 }
4815#ifdef CONFIG_X86_64
4816 else {
4817 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4818 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4819 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4820 }
4821#endif
4822
4823 code = param & 0xffff;
4824 fast = (param >> 16) & 0x1;
4825 rep_cnt = (param >> 32) & 0xfff;
4826 rep_idx = (param >> 48) & 0xfff;
4827
4828 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4829
c25bc163
GN		 4830 switch (code) {
4831 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4832 kvm_vcpu_on_spin(vcpu);
4833 break;
4834 default:
4835 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4836 break;
4837 }
55cd8e5a
GN		 4838
4839 ret = res | (((u64)rep_done & 0xfff) << 32);
4840 if (longmode) {
4841 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4842 } else {
4843 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4844 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4845 }
4846
4847 return 1;
4848}
4849
8776e519
HB		 4850int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4851{
4852 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4853 int r = 1;
8776e519 4854
55cd8e5a
GN		 4855 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4856 return kvm_hv_hypercall(vcpu);
4857
5fdbf976
MT		 4858 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4859 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4860 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4861 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4862 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4863
229456fc 4864 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4865
8776e519
HB		 4866 if (!is_long_mode(vcpu)) {
4867 nr &= 0xFFFFFFFF;
4868 a0 &= 0xFFFFFFFF;
4869 a1 &= 0xFFFFFFFF;
4870 a2 &= 0xFFFFFFFF;
4871 a3 &= 0xFFFFFFFF;
4872 }
4873
07708c4a
JK		 4874 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4875 ret = -KVM_EPERM;
4876 goto out;
4877 }
4878
8776e519 4879 switch (nr) {
b93463aa
AK		 4880 case KVM_HC_VAPIC_POLL_IRQ:
4881 ret = 0;
4882 break;
2f333bcb
MT		 4883 case KVM_HC_MMU_OP:
4884 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4885 break;
8776e519
HB		 4886 default:
4887 ret = -KVM_ENOSYS;
4888 break;
4889 }
07708c4a 4890out:
5fdbf976 4891 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4892 ++vcpu->stat.hypercalls;
2f333bcb 4893 return r;
8776e519
HB		 4894}
4895EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4896
4897int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4898{
4899 char instruction[3];
5fdbf976 4900 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4901
8776e519
HB		 4902 /*
4903 * Blow out the MMU to ensure that no other VCPU has an active mapping
4904 * to ensure that the updated hypercall appears atomically across all
4905 * VCPUs.
4906 */
4907 kvm_mmu_zap_all(vcpu->kvm);
4908
8776e519 4909 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4910
8fe681e9 4911 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4912}
4913
8776e519
HB		 4914void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4915{
89a27f4d 4916 struct desc_ptr dt = { limit, base };
8776e519
HB		 4917
4918 kvm_x86_ops->set_gdt(vcpu, &dt);
4919}
4920
4921void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4922{
89a27f4d 4923 struct desc_ptr dt = { limit, base };
8776e519
HB		 4924
4925 kvm_x86_ops->set_idt(vcpu, &dt);
4926}
4927
07716717
DK		 4928static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4929{
ad312c7c
ZX		 4930 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4931 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4932
4933 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4934 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4935 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4936 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4937 if (ej->function == e->function) {
4938 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4939 return j;
4940 }
4941 }
4942 return 0; /* silence gcc, even though control never reaches here */
4943}
4944
4945/* find an entry with matching function, matching index (if needed), and that
4946 * should be read next (if it's stateful) */
4947static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4948 u32 function, u32 index)
4949{
4950 if (e->function != function)
4951 return 0;
4952 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4953 return 0;
4954 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4955 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4956 return 0;
4957 return 1;
4958}
4959
d8017474
AG		 4960struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4961 u32 function, u32 index)
8776e519
HB		 4962{
4963 int i;
d8017474 4964 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4965
ad312c7c 4966 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4967 struct kvm_cpuid_entry2 *e;
4968
ad312c7c 4969 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4970 if (is_matching_cpuid_entry(e, function, index)) {
4971 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4972 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4973 best = e;
4974 break;
4975 }
4976 /*
4977 * Both basic or both extended?
4978 */
4979 if (((e->function ^ function) & 0x80000000) == 0)
4980 if (!best || e->function > best->function)
4981 best = e;
4982 }
d8017474
AG		 4983 return best;
4984}
0e851880 4985EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4986
82725b20
DE		 4987int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4988{
4989 struct kvm_cpuid_entry2 *best;
4990
f7a71197
AK		 4991 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4992 if (!best || best->eax < 0x80000008)
4993 goto not_found;
82725b20
DE		 4994 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4995 if (best)
4996 return best->eax & 0xff;
f7a71197 4997not_found:
82725b20
DE		 4998 return 36;
4999}
5000
d8017474
AG		 5001void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5002{
5003 u32 function, index;
5004 struct kvm_cpuid_entry2 *best;
5005
5006 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5007 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5008 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5009 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5010 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5011 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5012 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 5013 if (best) {
5fdbf976
MT		 5014 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5015 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5016 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5017 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5018 }
8776e519 5019 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5020 trace_kvm_cpuid(function,
5021 kvm_register_read(vcpu, VCPU_REGS_RAX),
5022 kvm_register_read(vcpu, VCPU_REGS_RBX),
5023 kvm_register_read(vcpu, VCPU_REGS_RCX),
5024 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5025}
5026EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5027
b6c7a5dc
HB		 5028/*
5029 * Check if userspace requested an interrupt window, and that the
5030 * interrupt window is open.
5031 *
5032 * No need to exit to userspace if we already have an interrupt queued.
5033 */
851ba692 5034static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5035{
8061823a 5036 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5037 vcpu->run->request_interrupt_window &&
5df56646 5038 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5039}
5040
851ba692 5041static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5042{
851ba692
AK		 5043 struct kvm_run *kvm_run = vcpu->run;
5044
91586a3b 5045 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5046 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5047 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5048 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5049 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5050 else
b6c7a5dc 5051 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5052 kvm_arch_interrupt_allowed(vcpu) &&
5053 !kvm_cpu_has_interrupt(vcpu) &&
5054 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5055}
5056
b93463aa
AK		 5057static void vapic_enter(struct kvm_vcpu *vcpu)
5058{
5059 struct kvm_lapic *apic = vcpu->arch.apic;
5060 struct page *page;
5061
5062 if (!apic || !apic->vapic_addr)
5063 return;
5064
5065 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5066
5067 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5068}
5069
5070static void vapic_exit(struct kvm_vcpu *vcpu)
5071{
5072 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5073 int idx;
b93463aa
AK		 5074
5075 if (!apic || !apic->vapic_addr)
5076 return;
5077
f656ce01 5078 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5079 kvm_release_page_dirty(apic->vapic_page);
5080 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5081 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5082}
5083
95ba8273
GN		 5084static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5085{
5086 int max_irr, tpr;
5087
5088 if (!kvm_x86_ops->update_cr8_intercept)
5089 return;
5090
88c808fd
AK		 5091 if (!vcpu->arch.apic)
5092 return;
5093
8db3baa2
GN		 5094 if (!vcpu->arch.apic->vapic_addr)
5095 max_irr = kvm_lapic_find_highest_irr(vcpu);
5096 else
5097 max_irr = -1;
95ba8273
GN		 5098
5099 if (max_irr != -1)
5100 max_irr >>= 4;
5101
5102 tpr = kvm_lapic_get_cr8(vcpu);
5103
5104 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5105}
5106
851ba692 5107static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5108{
5109 /* try to reinject previous events if any */
b59bb7bd 5110 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5111 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5112 vcpu->arch.exception.has_error_code,
5113 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5114 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5115 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5116 vcpu->arch.exception.error_code,
5117 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5118 return;
5119 }
5120
95ba8273
GN		 5121 if (vcpu->arch.nmi_injected) {
5122 kvm_x86_ops->set_nmi(vcpu);
5123 return;
5124 }
5125
5126 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5127 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5128 return;
5129 }
5130
5131 /* try to inject new event if pending */
5132 if (vcpu->arch.nmi_pending) {
5133 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5134 vcpu->arch.nmi_pending = false;
5135 vcpu->arch.nmi_injected = true;
5136 kvm_x86_ops->set_nmi(vcpu);
5137 }
5138 } else if (kvm_cpu_has_interrupt(vcpu)) {
5139 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5140 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5141 false);
5142 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5143 }
5144 }
5145}
5146
2acf923e
DC		 5147static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5148{
5149 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5150 !vcpu->guest_xcr0_loaded) {
5151 /* kvm_set_xcr() also depends on this */
5152 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5153 vcpu->guest_xcr0_loaded = 1;
5154 }
5155}
5156
5157static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5158{
5159 if (vcpu->guest_xcr0_loaded) {
5160 if (vcpu->arch.xcr0 != host_xcr0)
5161 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5162 vcpu->guest_xcr0_loaded = 0;
5163 }
5164}
5165
851ba692 5166static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5167{
5168 int r;
6a8b1d13 5169 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5170 vcpu->run->request_interrupt_window;
b6c7a5dc 5171
3e007509 5172 if (vcpu->requests) {
a8eeb04a 5173 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5174 kvm_mmu_unload(vcpu);
a8eeb04a 5175 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5176 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5177 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5178 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5179 if (unlikely(r))
5180 goto out;
5181 }
a8eeb04a 5182 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5183 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5184 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5185 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5186 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5187 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5188 r = 0;
5189 goto out;
5190 }
a8eeb04a 5191 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5192 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5193 r = 0;
5194 goto out;
5195 }
a8eeb04a 5196 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5197 vcpu->fpu_active = 0;
5198 kvm_x86_ops->fpu_deactivate(vcpu);
5199 }
af585b92
GN		 5200 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5201 /* Page is swapped out. Do synthetic halt */
5202 vcpu->arch.apf.halted = true;
5203 r = 1;
5204 goto out;
5205 }
2f52d58c 5206 }
b93463aa 5207
3e007509
AK		 5208 r = kvm_mmu_reload(vcpu);
5209 if (unlikely(r))
5210 goto out;
5211
b463a6f7
AK		 5212 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5213 inject_pending_event(vcpu);
5214
5215 /* enable NMI/IRQ window open exits if needed */
5216 if (vcpu->arch.nmi_pending)
5217 kvm_x86_ops->enable_nmi_window(vcpu);
5218 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5219 kvm_x86_ops->enable_irq_window(vcpu);
5220
5221 if (kvm_lapic_enabled(vcpu)) {
5222 update_cr8_intercept(vcpu);
5223 kvm_lapic_sync_to_vapic(vcpu);
5224 }
5225 }
5226
b6c7a5dc
HB		 5227 preempt_disable();
5228
5229 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5230 if (vcpu->fpu_active)
5231 kvm_load_guest_fpu(vcpu);
2acf923e 5232 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5233
6b7e2d09
XG		 5234 vcpu->mode = IN_GUEST_MODE;
5235
5236 /* We should set ->mode before check ->requests,
5237 * see the comment in make_all_cpus_request.
5238 */
5239 smp_mb();
b6c7a5dc 5240
d94e1dc9 5241 local_irq_disable();
32f88400 5242
6b7e2d09 5243 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5244 || need_resched() || signal_pending(current)) {
6b7e2d09 5245 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5246 smp_wmb();
6c142801
AK		 5247 local_irq_enable();
5248 preempt_enable();
b463a6f7 5249 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5250 r = 1;
5251 goto out;
5252 }
5253
f656ce01 5254 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5255
b6c7a5dc
HB		 5256 kvm_guest_enter();
5257
42dbaa5a 5258 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5259 set_debugreg(0, 7);
5260 set_debugreg(vcpu->arch.eff_db[0], 0);
5261 set_debugreg(vcpu->arch.eff_db[1], 1);
5262 set_debugreg(vcpu->arch.eff_db[2], 2);
5263 set_debugreg(vcpu->arch.eff_db[3], 3);
5264 }
b6c7a5dc 5265
229456fc 5266 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5267 kvm_x86_ops->run(vcpu);
b6c7a5dc 5268
24f1e32c
FW		 5269 /*
5270 * If the guest has used debug registers, at least dr7
5271 * will be disabled while returning to the host.
5272 * If we don't have active breakpoints in the host, we don't
5273 * care about the messed up debug address registers. But if
5274 * we have some of them active, restore the old state.
5275 */
59d8eb53 5276 if (hw_breakpoint_active())
24f1e32c 5277 hw_breakpoint_restore();
42dbaa5a 5278
1d5f066e
ZA		 5279 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5280
6b7e2d09 5281 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5282 smp_wmb();
b6c7a5dc
HB		 5283 local_irq_enable();
5284
5285 ++vcpu->stat.exits;
5286
5287 /*
5288 * We must have an instruction between local_irq_enable() and
5289 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5290 * the interrupt shadow. The stat.exits increment will do nicely.
5291 * But we need to prevent reordering, hence this barrier():
5292 */
5293 barrier();
5294
5295 kvm_guest_exit();
5296
5297 preempt_enable();
5298
f656ce01 5299 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5300
b6c7a5dc
HB		 5301 /*
5302 * Profile KVM exit RIPs:
5303 */
5304 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5305 unsigned long rip = kvm_rip_read(vcpu);
5306 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5307 }
5308
298101da 5309
b93463aa
AK		 5310 kvm_lapic_sync_from_vapic(vcpu);
5311
851ba692 5312 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5313out:
5314 return r;
5315}
b6c7a5dc 5316
09cec754 5317
851ba692 5318static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5319{
5320 int r;
f656ce01 5321 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5322
5323 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5324 pr_debug("vcpu %d received sipi with vector # %x\n",
5325 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5326 kvm_lapic_reset(vcpu);
5f179287 5327 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5328 if (r)
5329 return r;
5330 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5331 }
5332
f656ce01 5333 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5334 vapic_enter(vcpu);
5335
5336 r = 1;
5337 while (r > 0) {
af585b92
GN		 5338 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5339 !vcpu->arch.apf.halted)
851ba692 5340 r = vcpu_enter_guest(vcpu);
d7690175 5341 else {
f656ce01 5342 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5343 kvm_vcpu_block(vcpu);
f656ce01 5344 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5345 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5346 {
5347 switch(vcpu->arch.mp_state) {
5348 case KVM_MP_STATE_HALTED:
d7690175 5349 vcpu->arch.mp_state =
09cec754
GN		 5350 KVM_MP_STATE_RUNNABLE;
5351 case KVM_MP_STATE_RUNNABLE:
af585b92 5352 vcpu->arch.apf.halted = false;
09cec754
GN		 5353 break;
5354 case KVM_MP_STATE_SIPI_RECEIVED:
5355 default:
5356 r = -EINTR;
5357 break;
5358 }
5359 }
d7690175
MT		 5360 }
5361
09cec754
GN		 5362 if (r <= 0)
5363 break;
5364
5365 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5366 if (kvm_cpu_has_pending_timer(vcpu))
5367 kvm_inject_pending_timer_irqs(vcpu);
5368
851ba692 5369 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5370 r = -EINTR;
851ba692 5371 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5372 ++vcpu->stat.request_irq_exits;
5373 }
af585b92
GN		 5374
5375 kvm_check_async_pf_completion(vcpu);
5376
09cec754
GN		 5377 if (signal_pending(current)) {
5378 r = -EINTR;
851ba692 5379 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5380 ++vcpu->stat.signal_exits;
5381 }
5382 if (need_resched()) {
f656ce01 5383 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5384 kvm_resched(vcpu);
f656ce01 5385 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5386 }
b6c7a5dc
HB		 5387 }
5388
f656ce01 5389 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5390
b93463aa
AK		 5391 vapic_exit(vcpu);
5392
b6c7a5dc
HB		 5393 return r;
5394}
5395
5396int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5397{
5398 int r;
5399 sigset_t sigsaved;
5400
e5c30142
AK		 5401 if (!tsk_used_math(current) && init_fpu(current))
5402 return -ENOMEM;
5403
ac9f6dc0
AK		 5404 if (vcpu->sigset_active)
5405 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5406
a4535290 5407 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5408 kvm_vcpu_block(vcpu);
d7690175 5409 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5410 r = -EAGAIN;
5411 goto out;
b6c7a5dc
HB		 5412 }
5413
b6c7a5dc 5414 /* re-sync apic's tpr */
eea1cff9
AP		 5415 if (!irqchip_in_kernel(vcpu->kvm)) {
5416 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5417 r = -EINVAL;
5418 goto out;
5419 }
5420 }
b6c7a5dc 5421
d2ddd1c4 5422 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5423 if (vcpu->mmio_needed) {
5424 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5425 vcpu->mmio_read_completed = 1;
5426 vcpu->mmio_needed = 0;
b6c7a5dc 5427 }
f656ce01 5428 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
51d8b661 5429 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
f656ce01 5430 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5431 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5432 r = 0;
5433 goto out;
5434 }
5435 }
5fdbf976
MT		 5436 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5437 kvm_register_write(vcpu, VCPU_REGS_RAX,
5438 kvm_run->hypercall.ret);
b6c7a5dc 5439
851ba692 5440 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5441
5442out:
f1d86e46 5443 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5444 if (vcpu->sigset_active)
5445 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5446
b6c7a5dc
HB		 5447 return r;
5448}
5449
5450int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5451{
5fdbf976
MT		 5452 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5453 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5454 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5455 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5456 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5457 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5458 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5459 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5460#ifdef CONFIG_X86_64
5fdbf976
MT		 5461 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5462 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5463 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5464 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5465 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5466 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5467 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5468 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5469#endif
5470
5fdbf976 5471 regs->rip = kvm_rip_read(vcpu);
91586a3b 5472 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5473
b6c7a5dc
HB		 5474 return 0;
5475}
5476
5477int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5478{
5fdbf976
MT		 5479 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5480 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5481 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5482 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5483 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5484 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5485 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5486 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5487#ifdef CONFIG_X86_64
5fdbf976
MT		 5488 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5489 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5490 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5491 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5492 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5493 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5494 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5495 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5496#endif
5497
5fdbf976 5498 kvm_rip_write(vcpu, regs->rip);
91586a3b 5499 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5500
b4f14abd
JK		 5501 vcpu->arch.exception.pending = false;
5502
3842d135
AK		 5503 kvm_make_request(KVM_REQ_EVENT, vcpu);
5504
b6c7a5dc
HB		 5505 return 0;
5506}
5507
b6c7a5dc
HB		 5508void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5509{
5510 struct kvm_segment cs;
5511
3e6e0aab 5512 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5513 *db = cs.db;
5514 *l = cs.l;
5515}
5516EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5517
5518int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5519 struct kvm_sregs *sregs)
5520{
89a27f4d 5521 struct desc_ptr dt;
b6c7a5dc 5522
3e6e0aab
GT		 5523 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5524 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5525 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5526 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5527 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5528 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5529
3e6e0aab
GT		 5530 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5531 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5532
5533 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5534 sregs->idt.limit = dt.size;
5535 sregs->idt.base = dt.address;
b6c7a5dc 5536 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5537 sregs->gdt.limit = dt.size;
5538 sregs->gdt.base = dt.address;
b6c7a5dc 5539
4d4ec087 5540 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5541 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5542 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5543 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5544 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5545 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5546 sregs->apic_base = kvm_get_apic_base(vcpu);
5547
923c61bb 5548 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5549
36752c9b 5550 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5551 set_bit(vcpu->arch.interrupt.nr,
5552 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5553
b6c7a5dc
HB		 5554 return 0;
5555}
5556
62d9f0db
MT		 5557int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5558 struct kvm_mp_state *mp_state)
5559{
62d9f0db 5560 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5561 return 0;
5562}
5563
5564int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5565 struct kvm_mp_state *mp_state)
5566{
62d9f0db 5567 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5568 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5569 return 0;
5570}
5571
e269fb21
JK		 5572int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5573 bool has_error_code, u32 error_code)
b6c7a5dc 5574{
4d2179e1 5575 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5576 int ret;
e01c2426 5577
8ec4722d 5578 init_emulate_ctxt(vcpu);
c697518a 5579
9aabc88f 5580 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5581 tss_selector, reason, has_error_code,
5582 error_code);
c697518a 5583
c697518a 5584 if (ret)
19d04437 5585 return EMULATE_FAIL;
37817f29 5586
4d2179e1 5587 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5588 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5589 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5590 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5591 return EMULATE_DONE;
37817f29
IE		 5592}
5593EXPORT_SYMBOL_GPL(kvm_task_switch);
5594
b6c7a5dc
HB		 5595int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5596 struct kvm_sregs *sregs)
5597{
5598 int mmu_reset_needed = 0;
63f42e02 5599 int pending_vec, max_bits, idx;
89a27f4d 5600 struct desc_ptr dt;
b6c7a5dc 5601
89a27f4d
GN		 5602 dt.size = sregs->idt.limit;
5603 dt.address = sregs->idt.base;
b6c7a5dc 5604 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5605 dt.size = sregs->gdt.limit;
5606 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5607 kvm_x86_ops->set_gdt(vcpu, &dt);
5608
ad312c7c 5609 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5610 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5611 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5612 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5613
2d3ad1f4 5614 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5615
f6801dff 5616 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5617 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5618 kvm_set_apic_base(vcpu, sregs->apic_base);
5619
4d4ec087 5620 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5621 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5622 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5623
fc78f519 5624 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5625 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5626 if (sregs->cr4 & X86_CR4_OSXSAVE)
5627 update_cpuid(vcpu);
63f42e02
XG		 5628
5629 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5630 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5631 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5632 mmu_reset_needed = 1;
5633 }
63f42e02 5634 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5635
5636 if (mmu_reset_needed)
5637 kvm_mmu_reset_context(vcpu);
5638
923c61bb
GN		 5639 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5640 pending_vec = find_first_bit(
5641 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5642 if (pending_vec < max_bits) {
66fd3f7f 5643 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5644 pr_debug("Set back pending irq %d\n", pending_vec);
5645 if (irqchip_in_kernel(vcpu->kvm))
5646 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5647 }
5648
3e6e0aab
GT		 5649 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5650 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5651 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5652 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5653 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5654 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5655
3e6e0aab
GT		 5656 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5657 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5658
5f0269f5
ME		 5659 update_cr8_intercept(vcpu);
5660
9c3e4aab 5661 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5662 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5663 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5664 !is_protmode(vcpu))
9c3e4aab
MT		 5665 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5666
3842d135
AK		 5667 kvm_make_request(KVM_REQ_EVENT, vcpu);
5668
b6c7a5dc
HB		 5669 return 0;
5670}
5671
d0bfb940
JK		 5672int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5673 struct kvm_guest_debug *dbg)
b6c7a5dc 5674{
355be0b9 5675 unsigned long rflags;
ae675ef0 5676 int i, r;
b6c7a5dc 5677
4f926bf2
JK		 5678 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5679 r = -EBUSY;
5680 if (vcpu->arch.exception.pending)
2122ff5e 5681 goto out;
4f926bf2
JK		 5682 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5683 kvm_queue_exception(vcpu, DB_VECTOR);
5684 else
5685 kvm_queue_exception(vcpu, BP_VECTOR);
5686 }
5687
91586a3b
JK		 5688 /*
5689 * Read rflags as long as potentially injected trace flags are still
5690 * filtered out.
5691 */
5692 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5693
5694 vcpu->guest_debug = dbg->control;
5695 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5696 vcpu->guest_debug = 0;
5697
5698 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5699 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5700 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5701 vcpu->arch.switch_db_regs =
5702 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5703 } else {
5704 for (i = 0; i < KVM_NR_DB_REGS; i++)
5705 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5706 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5707 }
5708
f92653ee
JK		 5709 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5710 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5711 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5712
91586a3b
JK		 5713 /*
5714 * Trigger an rflags update that will inject or remove the trace
5715 * flags.
5716 */
5717 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5718
355be0b9 5719 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5720
4f926bf2 5721 r = 0;
d0bfb940 5722
2122ff5e 5723out:
b6c7a5dc
HB		 5724
5725 return r;
5726}
5727
8b006791
ZX		 5728/*
5729 * Translate a guest virtual address to a guest physical address.
5730 */
5731int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5732 struct kvm_translation *tr)
5733{
5734 unsigned long vaddr = tr->linear_address;
5735 gpa_t gpa;
f656ce01 5736 int idx;
8b006791 5737
f656ce01 5738 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5739 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5740 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5741 tr->physical_address = gpa;
5742 tr->valid = gpa != UNMAPPED_GVA;
5743 tr->writeable = 1;
5744 tr->usermode = 0;
8b006791
ZX		 5745
5746 return 0;
5747}
5748
d0752060
HB		 5749int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5750{
98918833
SY		 5751 struct i387_fxsave_struct *fxsave =
5752 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5753
d0752060
HB		 5754 memcpy(fpu->fpr, fxsave->st_space, 128);
5755 fpu->fcw = fxsave->cwd;
5756 fpu->fsw = fxsave->swd;
5757 fpu->ftwx = fxsave->twd;
5758 fpu->last_opcode = fxsave->fop;
5759 fpu->last_ip = fxsave->rip;
5760 fpu->last_dp = fxsave->rdp;
5761 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5762
d0752060
HB		 5763 return 0;
5764}
5765
5766int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5767{
98918833
SY		 5768 struct i387_fxsave_struct *fxsave =
5769 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5770
d0752060
HB		 5771 memcpy(fxsave->st_space, fpu->fpr, 128);
5772 fxsave->cwd = fpu->fcw;
5773 fxsave->swd = fpu->fsw;
5774 fxsave->twd = fpu->ftwx;
5775 fxsave->fop = fpu->last_opcode;
5776 fxsave->rip = fpu->last_ip;
5777 fxsave->rdp = fpu->last_dp;
5778 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5779
d0752060
HB		 5780 return 0;
5781}
5782
10ab25cd 5783int fx_init(struct kvm_vcpu *vcpu)
d0752060 5784{
10ab25cd
JK		 5785 int err;
5786
5787 err = fpu_alloc(&vcpu->arch.guest_fpu);
5788 if (err)
5789 return err;
5790
98918833 5791 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5792
2acf923e
DC		 5793 /*
5794 * Ensure guest xcr0 is valid for loading
5795 */
5796 vcpu->arch.xcr0 = XSTATE_FP;
5797
ad312c7c 5798 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5799
5800 return 0;
d0752060
HB		 5801}
5802EXPORT_SYMBOL_GPL(fx_init);
5803
98918833
SY		 5804static void fx_free(struct kvm_vcpu *vcpu)
5805{
5806 fpu_free(&vcpu->arch.guest_fpu);
5807}
5808
d0752060
HB		 5809void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5810{
2608d7a1 5811 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5812 return;
5813
2acf923e
DC		 5814 /*
5815 * Restore all possible states in the guest,
5816 * and assume host would use all available bits.
5817 * Guest xcr0 would be loaded later.
5818 */
5819 kvm_put_guest_xcr0(vcpu);
d0752060 5820 vcpu->guest_fpu_loaded = 1;
7cf30855 5821 unlazy_fpu(current);
98918833 5822 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5823 trace_kvm_fpu(1);
d0752060 5824}
d0752060
HB		 5825
5826void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5827{
2acf923e
DC		 5828 kvm_put_guest_xcr0(vcpu);
5829
d0752060
HB		 5830 if (!vcpu->guest_fpu_loaded)
5831 return;
5832
5833 vcpu->guest_fpu_loaded = 0;
98918833 5834 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5835 ++vcpu->stat.fpu_reload;
a8eeb04a 5836 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5837 trace_kvm_fpu(0);
d0752060 5838}
e9b11c17
ZX		 5839
5840void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5841{
12f9a48f 5842 kvmclock_reset(vcpu);
7f1ea208 5843
f5f48ee1 5844 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5845 fx_free(vcpu);
e9b11c17
ZX		 5846 kvm_x86_ops->vcpu_free(vcpu);
5847}
5848
5849struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5850 unsigned int id)
5851{
6755bae8
ZA		 5852 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5853 printk_once(KERN_WARNING
5854 "kvm: SMP vm created on host with unstable TSC; "
5855 "guest TSC will not be reliable\n");
26e5215f
AK		 5856 return kvm_x86_ops->vcpu_create(kvm, id);
5857}
e9b11c17 5858
26e5215f
AK		 5859int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5860{
5861 int r;
e9b11c17 5862
0bed3b56 5863 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5864 vcpu_load(vcpu);
5865 r = kvm_arch_vcpu_reset(vcpu);
5866 if (r == 0)
5867 r = kvm_mmu_setup(vcpu);
5868 vcpu_put(vcpu);
5869 if (r < 0)
5870 goto free_vcpu;
5871
26e5215f 5872 return 0;
e9b11c17
ZX		 5873free_vcpu:
5874 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5875 return r;
e9b11c17
ZX		 5876}
5877
d40ccc62 5878void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5879{
344d9588
GN		 5880 vcpu->arch.apf.msr_val = 0;
5881
e9b11c17
ZX		 5882 vcpu_load(vcpu);
5883 kvm_mmu_unload(vcpu);
5884 vcpu_put(vcpu);
5885
98918833 5886 fx_free(vcpu);
e9b11c17
ZX		 5887 kvm_x86_ops->vcpu_free(vcpu);
5888}
5889
5890int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5891{
448fa4a9
JK		 5892 vcpu->arch.nmi_pending = false;
5893 vcpu->arch.nmi_injected = false;
5894
42dbaa5a
JK		 5895 vcpu->arch.switch_db_regs = 0;
5896 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5897 vcpu->arch.dr6 = DR6_FIXED_1;
5898 vcpu->arch.dr7 = DR7_FIXED_1;
5899
3842d135 5900 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5901 vcpu->arch.apf.msr_val = 0;
3842d135 5902
12f9a48f
GC		 5903 kvmclock_reset(vcpu);
5904
af585b92
GN		 5905 kvm_clear_async_pf_completion_queue(vcpu);
5906 kvm_async_pf_hash_reset(vcpu);
5907 vcpu->arch.apf.halted = false;
3842d135 5908
e9b11c17
ZX		 5909 return kvm_x86_ops->vcpu_reset(vcpu);
5910}
5911
10474ae8 5912int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5913{
ca84d1a2
ZA		 5914 struct kvm *kvm;
5915 struct kvm_vcpu *vcpu;
5916 int i;
18863bdd
AK		 5917
5918 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5919 list_for_each_entry(kvm, &vm_list, vm_list)
5920 kvm_for_each_vcpu(i, vcpu, kvm)
5921 if (vcpu->cpu == smp_processor_id())
c285545f 5922 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5923 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5924}
5925
5926void kvm_arch_hardware_disable(void *garbage)
5927{
5928 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5929 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5930}
5931
5932int kvm_arch_hardware_setup(void)
5933{
5934 return kvm_x86_ops->hardware_setup();
5935}
5936
5937void kvm_arch_hardware_unsetup(void)
5938{
5939 kvm_x86_ops->hardware_unsetup();
5940}
5941
5942void kvm_arch_check_processor_compat(void *rtn)
5943{
5944 kvm_x86_ops->check_processor_compatibility(rtn);
5945}
5946
5947int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5948{
5949 struct page *page;
5950 struct kvm *kvm;
5951 int r;
5952
5953 BUG_ON(vcpu->kvm == NULL);
5954 kvm = vcpu->kvm;
5955
9aabc88f 5956 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5957 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5958 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5959 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5960 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5961 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5962 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5963 else
a4535290 5964 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5965
5966 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5967 if (!page) {
5968 r = -ENOMEM;
5969 goto fail;
5970 }
ad312c7c 5971 vcpu->arch.pio_data = page_address(page);
e9b11c17 5972
c285545f
ZA		 5973 if (!kvm->arch.virtual_tsc_khz)
5974 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5975
e9b11c17
ZX		 5976 r = kvm_mmu_create(vcpu);
5977 if (r < 0)
5978 goto fail_free_pio_data;
5979
5980 if (irqchip_in_kernel(kvm)) {
5981 r = kvm_create_lapic(vcpu);
5982 if (r < 0)
5983 goto fail_mmu_destroy;
5984 }
5985
890ca9ae
HY		 5986 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5987 GFP_KERNEL);
5988 if (!vcpu->arch.mce_banks) {
5989 r = -ENOMEM;
443c39bc 5990 goto fail_free_lapic;
890ca9ae
HY		 5991 }
5992 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5993
f5f48ee1
SY		 5994 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5995 goto fail_free_mce_banks;
5996
af585b92
GN		 5997 kvm_async_pf_hash_reset(vcpu);
5998
e9b11c17 5999 return 0;
f5f48ee1
SY		 6000fail_free_mce_banks:
6001 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6002fail_free_lapic:
6003 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6004fail_mmu_destroy:
6005 kvm_mmu_destroy(vcpu);
6006fail_free_pio_data:
ad312c7c 6007 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6008fail:
6009 return r;
6010}
6011
6012void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6013{
f656ce01
MT		 6014 int idx;
6015
36cb93fd 6016 kfree(vcpu->arch.mce_banks);
e9b11c17 6017 kvm_free_lapic(vcpu);
f656ce01 6018 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6019 kvm_mmu_destroy(vcpu);
f656ce01 6020 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6021 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6022}
d19a9cd2 6023
d89f5eff 6024int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6025{
f05e70ac 6026 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6027 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6028
5550af4d
SY		 6029 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6030 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6031
99e3e30a 6032 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6033
d89f5eff 6034 return 0;
d19a9cd2
ZX		 6035}
6036
6037static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6038{
6039 vcpu_load(vcpu);
6040 kvm_mmu_unload(vcpu);
6041 vcpu_put(vcpu);
6042}
6043
6044static void kvm_free_vcpus(struct kvm *kvm)
6045{
6046 unsigned int i;
988a2cae 6047 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6048
6049 /*
6050 * Unpin any mmu pages first.
6051 */
af585b92
GN		 6052 kvm_for_each_vcpu(i, vcpu, kvm) {
6053 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6054 kvm_unload_vcpu_mmu(vcpu);
af585b92 6055 }
988a2cae
GN		 6056 kvm_for_each_vcpu(i, vcpu, kvm)
6057 kvm_arch_vcpu_free(vcpu);
6058
6059 mutex_lock(&kvm->lock);
6060 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6061 kvm->vcpus[i] = NULL;
d19a9cd2 6062
988a2cae
GN		 6063 atomic_set(&kvm->online_vcpus, 0);
6064 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6065}
6066
ad8ba2cd
SY		 6067void kvm_arch_sync_events(struct kvm *kvm)
6068{
ba4cef31 6069 kvm_free_all_assigned_devices(kvm);
aea924f6 6070 kvm_free_pit(kvm);
ad8ba2cd
SY		 6071}
6072
d19a9cd2
ZX		 6073void kvm_arch_destroy_vm(struct kvm *kvm)
6074{
6eb55818 6075 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6076 kfree(kvm->arch.vpic);
6077 kfree(kvm->arch.vioapic);
d19a9cd2 6078 kvm_free_vcpus(kvm);
3d45830c
AK		 6079 if (kvm->arch.apic_access_page)
6080 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6081 if (kvm->arch.ept_identity_pagetable)
6082 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6083}
0de10343 6084
f7784b8e
MT		 6085int kvm_arch_prepare_memory_region(struct kvm *kvm,
6086 struct kvm_memory_slot *memslot,
0de10343 6087 struct kvm_memory_slot old,
f7784b8e 6088 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6089 int user_alloc)
6090{
f7784b8e 6091 int npages = memslot->npages;
7ac77099
AK		 6092 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6093
6094 /* Prevent internal slot pages from being moved by fork()/COW. */
6095 if (memslot->id >= KVM_MEMORY_SLOTS)
6096 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6097
6098 /*To keep backward compatibility with older userspace,
6099 *x86 needs to hanlde !user_alloc case.
6100 */
6101 if (!user_alloc) {
6102 if (npages && !old.rmap) {
604b38ac
AA		 6103 unsigned long userspace_addr;
6104
72dc67a6 6105 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6106 userspace_addr = do_mmap(NULL, 0,
6107 npages * PAGE_SIZE,
6108 PROT_READ | PROT_WRITE,
7ac77099 6109 map_flags,
604b38ac 6110 0);
72dc67a6 6111 up_write(&current->mm->mmap_sem);
0de10343 6112
604b38ac
AA		 6113 if (IS_ERR((void *)userspace_addr))
6114 return PTR_ERR((void *)userspace_addr);
6115
604b38ac 6116 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6117 }
6118 }
6119
f7784b8e
MT		 6120
6121 return 0;
6122}
6123
6124void kvm_arch_commit_memory_region(struct kvm *kvm,
6125 struct kvm_userspace_memory_region *mem,
6126 struct kvm_memory_slot old,
6127 int user_alloc)
6128{
6129
6130 int npages = mem->memory_size >> PAGE_SHIFT;
6131
6132 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6133 int ret;
6134
6135 down_write(&current->mm->mmap_sem);
6136 ret = do_munmap(current->mm, old.userspace_addr,
6137 old.npages * PAGE_SIZE);
6138 up_write(&current->mm->mmap_sem);
6139 if (ret < 0)
6140 printk(KERN_WARNING
6141 "kvm_vm_ioctl_set_memory_region: "
6142 "failed to munmap memory\n");
6143 }
6144
7c8a83b7 6145 spin_lock(&kvm->mmu_lock);
f05e70ac 6146 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6147 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6148 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6149 }
6150
6151 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6152 spin_unlock(&kvm->mmu_lock);
0de10343 6153}
1d737c8a 6154
34d4cb8f
MT		 6155void kvm_arch_flush_shadow(struct kvm *kvm)
6156{
6157 kvm_mmu_zap_all(kvm);
8986ecc0 6158 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6159}
6160
1d737c8a
ZX		 6161int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6162{
af585b92
GN		 6163 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6164 !vcpu->arch.apf.halted)
6165 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6166 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6167 || vcpu->arch.nmi_pending ||
6168 (kvm_arch_interrupt_allowed(vcpu) &&
6169 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6170}
5736199a 6171
5736199a
ZX		 6172void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6173{
32f88400
MT		 6174 int me;
6175 int cpu = vcpu->cpu;
5736199a
ZX		 6176
6177 if (waitqueue_active(&vcpu->wq)) {
6178 wake_up_interruptible(&vcpu->wq);
6179 ++vcpu->stat.halt_wakeup;
6180 }
32f88400
MT		 6181
6182 me = get_cpu();
6183 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6184 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6185 smp_send_reschedule(cpu);
e9571ed5 6186 put_cpu();
5736199a 6187}
78646121
GN		 6188
6189int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6190{
6191 return kvm_x86_ops->interrupt_allowed(vcpu);
6192}
229456fc 6193
f92653ee
JK		 6194bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6195{
6196 unsigned long current_rip = kvm_rip_read(vcpu) +
6197 get_segment_base(vcpu, VCPU_SREG_CS);
6198
6199 return current_rip == linear_rip;
6200}
6201EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6202
94fe45da
JK		 6203unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6204{
6205 unsigned long rflags;
6206
6207 rflags = kvm_x86_ops->get_rflags(vcpu);
6208 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6209 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6210 return rflags;
6211}
6212EXPORT_SYMBOL_GPL(kvm_get_rflags);
6213
6214void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6215{
6216 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6217 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6218 rflags |= X86_EFLAGS_TF;
94fe45da 6219 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6220 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6221}
6222EXPORT_SYMBOL_GPL(kvm_set_rflags);
6223
56028d08
GN		 6224void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6225{
6226 int r;
6227
fb67e14f 6228 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6229 is_error_page(work->page))
56028d08
GN		 6230 return;
6231
6232 r = kvm_mmu_reload(vcpu);
6233 if (unlikely(r))
6234 return;
6235
fb67e14f
XG		 6236 if (!vcpu->arch.mmu.direct_map &&
6237 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6238 return;
6239
56028d08
GN		 6240 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6241}
6242
af585b92
GN		 6243static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6244{
6245 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6246}
6247
6248static inline u32 kvm_async_pf_next_probe(u32 key)
6249{
6250 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6251}
6252
6253static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6254{
6255 u32 key = kvm_async_pf_hash_fn(gfn);
6256
6257 while (vcpu->arch.apf.gfns[key] != ~0)
6258 key = kvm_async_pf_next_probe(key);
6259
6260 vcpu->arch.apf.gfns[key] = gfn;
6261}
6262
6263static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6264{
6265 int i;
6266 u32 key = kvm_async_pf_hash_fn(gfn);
6267
6268 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6269 (vcpu->arch.apf.gfns[key] != gfn &&
6270 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6271 key = kvm_async_pf_next_probe(key);
6272
6273 return key;
6274}
6275
6276bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6277{
6278 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6279}
6280
6281static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6282{
6283 u32 i, j, k;
6284
6285 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6286 while (true) {
6287 vcpu->arch.apf.gfns[i] = ~0;
6288 do {
6289 j = kvm_async_pf_next_probe(j);
6290 if (vcpu->arch.apf.gfns[j] == ~0)
6291 return;
6292 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6293 /*
6294 * k lies cyclically in ]i,j]
6295 * | i.k.j |
6296 * |....j i.k.| or |.k..j i...|
6297 */
6298 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6299 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6300 i = j;
6301 }
6302}
6303
7c90705b
GN		 6304static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6305{
6306
6307 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6308 sizeof(val));
6309}
6310
af585b92
GN		 6311void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6312 struct kvm_async_pf *work)
6313{
6389ee94
AK		 6314 struct x86_exception fault;
6315
7c90705b 6316 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6317 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6318
6319 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6320 (vcpu->arch.apf.send_user_only &&
6321 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6322 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6323 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6324 fault.vector = PF_VECTOR;
6325 fault.error_code_valid = true;
6326 fault.error_code = 0;
6327 fault.nested_page_fault = false;
6328 fault.address = work->arch.token;
6329 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6330 }
af585b92
GN		 6331}
6332
6333void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6334 struct kvm_async_pf *work)
6335{
6389ee94
AK		 6336 struct x86_exception fault;
6337
7c90705b
GN		 6338 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6339 if (is_error_page(work->page))
6340 work->arch.token = ~0; /* broadcast wakeup */
6341 else
6342 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6343
6344 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6345 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6346 fault.vector = PF_VECTOR;
6347 fault.error_code_valid = true;
6348 fault.error_code = 0;
6349 fault.nested_page_fault = false;
6350 fault.address = work->arch.token;
6351 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6352 }
e6d53e3b 6353 vcpu->arch.apf.halted = false;
7c90705b
GN		 6354}
6355
6356bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6357{
6358 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6359 return true;
6360 else
6361 return !kvm_event_needs_reinjection(vcpu) &&
6362 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6363}
6364
229456fc
MT		 6365EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6366EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6367EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6368EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6369EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6370EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6371EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6372EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6373EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6374EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6375EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6376EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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