Commit | Line | Data |
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043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
043405e1 CO |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
13 | * Amit Shah <amit.shah@qumranet.com> |
14 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
15 | * |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
313a3dc7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
7837699f | 24 | #include "i8254.h" |
37817f29 | 25 | #include "tss.h" |
5fdbf976 | 26 | #include "kvm_cache_regs.h" |
26eef70c | 27 | #include "x86.h" |
313a3dc7 | 28 | |
18068523 | 29 | #include <linux/clocksource.h> |
4d5c5d0f | 30 | #include <linux/interrupt.h> |
313a3dc7 CO |
31 | #include <linux/kvm.h> |
32 | #include <linux/fs.h> | |
33 | #include <linux/vmalloc.h> | |
5fb76f9b | 34 | #include <linux/module.h> |
0de10343 | 35 | #include <linux/mman.h> |
2bacc55c | 36 | #include <linux/highmem.h> |
19de40a8 | 37 | #include <linux/iommu.h> |
62c476c7 | 38 | #include <linux/intel-iommu.h> |
c8076604 | 39 | #include <linux/cpufreq.h> |
18863bdd | 40 | #include <linux/user-return-notifier.h> |
a983fb23 | 41 | #include <linux/srcu.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
aec51dc4 | 43 | #include <trace/events/kvm.h> |
2ed152af | 44 | |
229456fc MT |
45 | #define CREATE_TRACE_POINTS |
46 | #include "trace.h" | |
043405e1 | 47 | |
24f1e32c | 48 | #include <asm/debugreg.h> |
043405e1 | 49 | #include <asm/uaccess.h> |
d825ed0a | 50 | #include <asm/msr.h> |
a5f61300 | 51 | #include <asm/desc.h> |
0bed3b56 | 52 | #include <asm/mtrr.h> |
890ca9ae | 53 | #include <asm/mce.h> |
043405e1 | 54 | |
313a3dc7 | 55 | #define MAX_IO_MSRS 256 |
a03490ed CO |
56 | #define CR0_RESERVED_BITS \ |
57 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
58 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
59 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
60 | #define CR4_RESERVED_BITS \ | |
61 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
62 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
63 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
64 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) | |
65 | ||
66 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
67 | |
68 | #define KVM_MAX_MCE_BANKS 32 | |
69 | #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P | |
70 | ||
50a37eb4 JR |
71 | /* EFER defaults: |
72 | * - enable syscall per default because its emulated by KVM | |
73 | * - enable LME and LMA per default on 64 bit KVM | |
74 | */ | |
75 | #ifdef CONFIG_X86_64 | |
76 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
77 | #else | |
78 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
79 | #endif | |
313a3dc7 | 80 | |
ba1389b7 AK |
81 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
82 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 83 | |
cb142eb7 | 84 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
85 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
86 | struct kvm_cpuid_entry2 __user *entries); | |
87 | ||
97896d04 | 88 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 89 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 90 | |
ed85c068 AP |
91 | int ignore_msrs = 0; |
92 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
93 | ||
18863bdd AK |
94 | #define KVM_NR_SHARED_MSRS 16 |
95 | ||
96 | struct kvm_shared_msrs_global { | |
97 | int nr; | |
2bf78fa7 | 98 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
99 | }; |
100 | ||
101 | struct kvm_shared_msrs { | |
102 | struct user_return_notifier urn; | |
103 | bool registered; | |
2bf78fa7 SY |
104 | struct kvm_shared_msr_values { |
105 | u64 host; | |
106 | u64 curr; | |
107 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
108 | }; |
109 | ||
110 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
111 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
112 | ||
417bc304 | 113 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
114 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
115 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
116 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
117 | { "invlpg", VCPU_STAT(invlpg) }, | |
118 | { "exits", VCPU_STAT(exits) }, | |
119 | { "io_exits", VCPU_STAT(io_exits) }, | |
120 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
121 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
122 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 123 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
124 | { "halt_exits", VCPU_STAT(halt_exits) }, |
125 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 126 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
127 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
128 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
129 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
130 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
131 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
132 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
133 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 134 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 135 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
136 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
137 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
138 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
139 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
140 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
141 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 142 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 143 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 144 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 145 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
146 | { NULL } |
147 | }; | |
148 | ||
18863bdd AK |
149 | static void kvm_on_user_return(struct user_return_notifier *urn) |
150 | { | |
151 | unsigned slot; | |
18863bdd AK |
152 | struct kvm_shared_msrs *locals |
153 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 154 | struct kvm_shared_msr_values *values; |
18863bdd AK |
155 | |
156 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
2bf78fa7 SY |
157 | values = &locals->values[slot]; |
158 | if (values->host != values->curr) { | |
159 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
160 | values->curr = values->host; | |
18863bdd AK |
161 | } |
162 | } | |
163 | locals->registered = false; | |
164 | user_return_notifier_unregister(urn); | |
165 | } | |
166 | ||
2bf78fa7 | 167 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 168 | { |
2bf78fa7 | 169 | struct kvm_shared_msrs *smsr; |
18863bdd AK |
170 | u64 value; |
171 | ||
2bf78fa7 SY |
172 | smsr = &__get_cpu_var(shared_msrs); |
173 | /* only read, and nobody should modify it at this time, | |
174 | * so don't need lock */ | |
175 | if (slot >= shared_msrs_global.nr) { | |
176 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
177 | return; | |
178 | } | |
179 | rdmsrl_safe(msr, &value); | |
180 | smsr->values[slot].host = value; | |
181 | smsr->values[slot].curr = value; | |
182 | } | |
183 | ||
184 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
185 | { | |
18863bdd AK |
186 | if (slot >= shared_msrs_global.nr) |
187 | shared_msrs_global.nr = slot + 1; | |
2bf78fa7 SY |
188 | shared_msrs_global.msrs[slot] = msr; |
189 | /* we need ensured the shared_msr_global have been updated */ | |
190 | smp_wmb(); | |
18863bdd AK |
191 | } |
192 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
193 | ||
194 | static void kvm_shared_msr_cpu_online(void) | |
195 | { | |
196 | unsigned i; | |
18863bdd AK |
197 | |
198 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 199 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
200 | } |
201 | ||
d5696725 | 202 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd AK |
203 | { |
204 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
205 | ||
2bf78fa7 | 206 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
18863bdd | 207 | return; |
2bf78fa7 SY |
208 | smsr->values[slot].curr = value; |
209 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
18863bdd AK |
210 | if (!smsr->registered) { |
211 | smsr->urn.on_user_return = kvm_on_user_return; | |
212 | user_return_notifier_register(&smsr->urn); | |
213 | smsr->registered = true; | |
214 | } | |
215 | } | |
216 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
217 | ||
3548bab5 AK |
218 | static void drop_user_return_notifiers(void *ignore) |
219 | { | |
220 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
221 | ||
222 | if (smsr->registered) | |
223 | kvm_on_user_return(&smsr->urn); | |
224 | } | |
225 | ||
6866b83e CO |
226 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
227 | { | |
228 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 229 | return vcpu->arch.apic_base; |
6866b83e | 230 | else |
ad312c7c | 231 | return vcpu->arch.apic_base; |
6866b83e CO |
232 | } |
233 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
234 | ||
235 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
236 | { | |
237 | /* TODO: reserve bits check */ | |
238 | if (irqchip_in_kernel(vcpu->kvm)) | |
239 | kvm_lapic_set_base(vcpu, data); | |
240 | else | |
ad312c7c | 241 | vcpu->arch.apic_base = data; |
6866b83e CO |
242 | } |
243 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
244 | ||
3fd28fce ED |
245 | #define EXCPT_BENIGN 0 |
246 | #define EXCPT_CONTRIBUTORY 1 | |
247 | #define EXCPT_PF 2 | |
248 | ||
249 | static int exception_class(int vector) | |
250 | { | |
251 | switch (vector) { | |
252 | case PF_VECTOR: | |
253 | return EXCPT_PF; | |
254 | case DE_VECTOR: | |
255 | case TS_VECTOR: | |
256 | case NP_VECTOR: | |
257 | case SS_VECTOR: | |
258 | case GP_VECTOR: | |
259 | return EXCPT_CONTRIBUTORY; | |
260 | default: | |
261 | break; | |
262 | } | |
263 | return EXCPT_BENIGN; | |
264 | } | |
265 | ||
266 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
267 | unsigned nr, bool has_error, u32 error_code) | |
268 | { | |
269 | u32 prev_nr; | |
270 | int class1, class2; | |
271 | ||
272 | if (!vcpu->arch.exception.pending) { | |
273 | queue: | |
274 | vcpu->arch.exception.pending = true; | |
275 | vcpu->arch.exception.has_error_code = has_error; | |
276 | vcpu->arch.exception.nr = nr; | |
277 | vcpu->arch.exception.error_code = error_code; | |
278 | return; | |
279 | } | |
280 | ||
281 | /* to check exception */ | |
282 | prev_nr = vcpu->arch.exception.nr; | |
283 | if (prev_nr == DF_VECTOR) { | |
284 | /* triple fault -> shutdown */ | |
285 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
286 | return; | |
287 | } | |
288 | class1 = exception_class(prev_nr); | |
289 | class2 = exception_class(nr); | |
290 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
291 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
292 | /* generate double fault per SDM Table 5-5 */ | |
293 | vcpu->arch.exception.pending = true; | |
294 | vcpu->arch.exception.has_error_code = true; | |
295 | vcpu->arch.exception.nr = DF_VECTOR; | |
296 | vcpu->arch.exception.error_code = 0; | |
297 | } else | |
298 | /* replace previous exception with a new one in a hope | |
299 | that instruction re-execution will regenerate lost | |
300 | exception */ | |
301 | goto queue; | |
302 | } | |
303 | ||
298101da AK |
304 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
305 | { | |
3fd28fce | 306 | kvm_multiple_exception(vcpu, nr, false, 0); |
298101da AK |
307 | } |
308 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
309 | ||
c3c91fee AK |
310 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, |
311 | u32 error_code) | |
312 | { | |
313 | ++vcpu->stat.pf_guest; | |
ad312c7c | 314 | vcpu->arch.cr2 = addr; |
c3c91fee AK |
315 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
316 | } | |
317 | ||
3419ffc8 SY |
318 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
319 | { | |
320 | vcpu->arch.nmi_pending = 1; | |
321 | } | |
322 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
323 | ||
298101da AK |
324 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
325 | { | |
3fd28fce | 326 | kvm_multiple_exception(vcpu, nr, true, error_code); |
298101da AK |
327 | } |
328 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
329 | ||
0a79b009 AK |
330 | /* |
331 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
332 | * a #GP and return false. | |
333 | */ | |
334 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 335 | { |
0a79b009 AK |
336 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
337 | return true; | |
338 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
339 | return false; | |
298101da | 340 | } |
0a79b009 | 341 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 342 | |
a03490ed CO |
343 | /* |
344 | * Load the pae pdptrs. Return true is they are all valid. | |
345 | */ | |
346 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
347 | { | |
348 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
349 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
350 | int i; | |
351 | int ret; | |
ad312c7c | 352 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 353 | |
a03490ed CO |
354 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
355 | offset * sizeof(u64), sizeof(pdpte)); | |
356 | if (ret < 0) { | |
357 | ret = 0; | |
358 | goto out; | |
359 | } | |
360 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 361 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 362 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
363 | ret = 0; |
364 | goto out; | |
365 | } | |
366 | } | |
367 | ret = 1; | |
368 | ||
ad312c7c | 369 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
6de4f3ad AK |
370 | __set_bit(VCPU_EXREG_PDPTR, |
371 | (unsigned long *)&vcpu->arch.regs_avail); | |
372 | __set_bit(VCPU_EXREG_PDPTR, | |
373 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 374 | out: |
a03490ed CO |
375 | |
376 | return ret; | |
377 | } | |
cc4b6871 | 378 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 379 | |
d835dfec AK |
380 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
381 | { | |
ad312c7c | 382 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
383 | bool changed = true; |
384 | int r; | |
385 | ||
386 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
387 | return false; | |
388 | ||
6de4f3ad AK |
389 | if (!test_bit(VCPU_EXREG_PDPTR, |
390 | (unsigned long *)&vcpu->arch.regs_avail)) | |
391 | return true; | |
392 | ||
ad312c7c | 393 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
394 | if (r < 0) |
395 | goto out; | |
ad312c7c | 396 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 397 | out: |
d835dfec AK |
398 | |
399 | return changed; | |
400 | } | |
401 | ||
2d3ad1f4 | 402 | void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 403 | { |
f9a48e6a AK |
404 | cr0 |= X86_CR0_ET; |
405 | ||
ab344828 GN |
406 | #ifdef CONFIG_X86_64 |
407 | if (cr0 & 0xffffffff00000000UL) { | |
c1a5d4f9 | 408 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
409 | return; |
410 | } | |
ab344828 GN |
411 | #endif |
412 | ||
413 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed CO |
414 | |
415 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) { | |
c1a5d4f9 | 416 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
417 | return; |
418 | } | |
419 | ||
420 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) { | |
c1a5d4f9 | 421 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
422 | return; |
423 | } | |
424 | ||
425 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
426 | #ifdef CONFIG_X86_64 | |
f6801dff | 427 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
428 | int cs_db, cs_l; |
429 | ||
430 | if (!is_pae(vcpu)) { | |
c1a5d4f9 | 431 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
432 | return; |
433 | } | |
434 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
435 | if (cs_l) { | |
c1a5d4f9 | 436 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
437 | return; |
438 | ||
439 | } | |
440 | } else | |
441 | #endif | |
ad312c7c | 442 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
c1a5d4f9 | 443 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
444 | return; |
445 | } | |
446 | ||
447 | } | |
448 | ||
449 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
a03490ed | 450 | |
a03490ed | 451 | kvm_mmu_reset_context(vcpu); |
a03490ed CO |
452 | return; |
453 | } | |
2d3ad1f4 | 454 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 455 | |
2d3ad1f4 | 456 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 457 | { |
4d4ec087 | 458 | kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f)); |
a03490ed | 459 | } |
2d3ad1f4 | 460 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 461 | |
2d3ad1f4 | 462 | void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 463 | { |
fc78f519 | 464 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
a2edf57f AK |
465 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; |
466 | ||
a03490ed | 467 | if (cr4 & CR4_RESERVED_BITS) { |
c1a5d4f9 | 468 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
469 | return; |
470 | } | |
471 | ||
472 | if (is_long_mode(vcpu)) { | |
473 | if (!(cr4 & X86_CR4_PAE)) { | |
c1a5d4f9 | 474 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
475 | return; |
476 | } | |
a2edf57f AK |
477 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
478 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
ad312c7c | 479 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
c1a5d4f9 | 480 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
481 | return; |
482 | } | |
483 | ||
484 | if (cr4 & X86_CR4_VMXE) { | |
c1a5d4f9 | 485 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
486 | return; |
487 | } | |
488 | kvm_x86_ops->set_cr4(vcpu, cr4); | |
ad312c7c | 489 | vcpu->arch.cr4 = cr4; |
5a41accd | 490 | vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled; |
a03490ed | 491 | kvm_mmu_reset_context(vcpu); |
a03490ed | 492 | } |
2d3ad1f4 | 493 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 494 | |
2d3ad1f4 | 495 | void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 496 | { |
ad312c7c | 497 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 498 | kvm_mmu_sync_roots(vcpu); |
d835dfec AK |
499 | kvm_mmu_flush_tlb(vcpu); |
500 | return; | |
501 | } | |
502 | ||
a03490ed CO |
503 | if (is_long_mode(vcpu)) { |
504 | if (cr3 & CR3_L_MODE_RESERVED_BITS) { | |
c1a5d4f9 | 505 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
506 | return; |
507 | } | |
508 | } else { | |
509 | if (is_pae(vcpu)) { | |
510 | if (cr3 & CR3_PAE_RESERVED_BITS) { | |
c1a5d4f9 | 511 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
512 | return; |
513 | } | |
514 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) { | |
c1a5d4f9 | 515 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
516 | return; |
517 | } | |
518 | } | |
519 | /* | |
520 | * We don't check reserved bits in nonpae mode, because | |
521 | * this isn't enforced, and VMware depends on this. | |
522 | */ | |
523 | } | |
524 | ||
a03490ed CO |
525 | /* |
526 | * Does the new cr3 value map to physical memory? (Note, we | |
527 | * catch an invalid cr3 even in real-mode, because it would | |
528 | * cause trouble later on when we turn on paging anyway.) | |
529 | * | |
530 | * A real CPU would silently accept an invalid cr3 and would | |
531 | * attempt to use it - with largely undefined (and often hard | |
532 | * to debug) behavior on the guest side. | |
533 | */ | |
534 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
c1a5d4f9 | 535 | kvm_inject_gp(vcpu, 0); |
a03490ed | 536 | else { |
ad312c7c ZX |
537 | vcpu->arch.cr3 = cr3; |
538 | vcpu->arch.mmu.new_cr3(vcpu); | |
a03490ed | 539 | } |
a03490ed | 540 | } |
2d3ad1f4 | 541 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 542 | |
2d3ad1f4 | 543 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed CO |
544 | { |
545 | if (cr8 & CR8_RESERVED_BITS) { | |
c1a5d4f9 | 546 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
547 | return; |
548 | } | |
549 | if (irqchip_in_kernel(vcpu->kvm)) | |
550 | kvm_lapic_set_tpr(vcpu, cr8); | |
551 | else | |
ad312c7c | 552 | vcpu->arch.cr8 = cr8; |
a03490ed | 553 | } |
2d3ad1f4 | 554 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 555 | |
2d3ad1f4 | 556 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
557 | { |
558 | if (irqchip_in_kernel(vcpu->kvm)) | |
559 | return kvm_lapic_get_cr8(vcpu); | |
560 | else | |
ad312c7c | 561 | return vcpu->arch.cr8; |
a03490ed | 562 | } |
2d3ad1f4 | 563 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 564 | |
d8017474 AG |
565 | static inline u32 bit(int bitno) |
566 | { | |
567 | return 1 << (bitno & 31); | |
568 | } | |
569 | ||
043405e1 CO |
570 | /* |
571 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
572 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
573 | * | |
574 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
575 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
576 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 577 | */ |
e3267cbb | 578 | |
10388a07 | 579 | #define KVM_SAVE_MSRS_BEGIN 5 |
043405e1 | 580 | static u32 msrs_to_save[] = { |
e3267cbb | 581 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
55cd8e5a | 582 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, |
10388a07 | 583 | HV_X64_MSR_APIC_ASSIST_PAGE, |
043405e1 CO |
584 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
585 | MSR_K6_STAR, | |
586 | #ifdef CONFIG_X86_64 | |
587 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
588 | #endif | |
e3267cbb | 589 | MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
590 | }; |
591 | ||
592 | static unsigned num_msrs_to_save; | |
593 | ||
594 | static u32 emulated_msrs[] = { | |
595 | MSR_IA32_MISC_ENABLE, | |
596 | }; | |
597 | ||
15c4a640 CO |
598 | static void set_efer(struct kvm_vcpu *vcpu, u64 efer) |
599 | { | |
f2b4b7dd | 600 | if (efer & efer_reserved_bits) { |
c1a5d4f9 | 601 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
602 | return; |
603 | } | |
604 | ||
605 | if (is_paging(vcpu) | |
f6801dff | 606 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) { |
c1a5d4f9 | 607 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
608 | return; |
609 | } | |
610 | ||
1b2fd70c AG |
611 | if (efer & EFER_FFXSR) { |
612 | struct kvm_cpuid_entry2 *feat; | |
613 | ||
614 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
615 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) { | |
1b2fd70c AG |
616 | kvm_inject_gp(vcpu, 0); |
617 | return; | |
618 | } | |
619 | } | |
620 | ||
d8017474 AG |
621 | if (efer & EFER_SVME) { |
622 | struct kvm_cpuid_entry2 *feat; | |
623 | ||
624 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
625 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) { | |
d8017474 AG |
626 | kvm_inject_gp(vcpu, 0); |
627 | return; | |
628 | } | |
629 | } | |
630 | ||
15c4a640 CO |
631 | kvm_x86_ops->set_efer(vcpu, efer); |
632 | ||
633 | efer &= ~EFER_LMA; | |
f6801dff | 634 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 635 | |
f6801dff | 636 | vcpu->arch.efer = efer; |
9645bb56 AK |
637 | |
638 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; | |
639 | kvm_mmu_reset_context(vcpu); | |
15c4a640 CO |
640 | } |
641 | ||
f2b4b7dd JR |
642 | void kvm_enable_efer_bits(u64 mask) |
643 | { | |
644 | efer_reserved_bits &= ~mask; | |
645 | } | |
646 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
647 | ||
648 | ||
15c4a640 CO |
649 | /* |
650 | * Writes msr value into into the appropriate "register". | |
651 | * Returns 0 on success, non-0 otherwise. | |
652 | * Assumes vcpu_load() was already called. | |
653 | */ | |
654 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
655 | { | |
656 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
657 | } | |
658 | ||
313a3dc7 CO |
659 | /* |
660 | * Adapt set_msr() to msr_io()'s calling convention | |
661 | */ | |
662 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
663 | { | |
664 | return kvm_set_msr(vcpu, index, *data); | |
665 | } | |
666 | ||
18068523 GOC |
667 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
668 | { | |
669 | static int version; | |
50d0a0f9 | 670 | struct pvclock_wall_clock wc; |
923de3cf | 671 | struct timespec boot; |
18068523 GOC |
672 | |
673 | if (!wall_clock) | |
674 | return; | |
675 | ||
676 | version++; | |
677 | ||
18068523 GOC |
678 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
679 | ||
50d0a0f9 GH |
680 | /* |
681 | * The guest calculates current wall clock time by adding | |
682 | * system time (updated by kvm_write_guest_time below) to the | |
683 | * wall clock specified here. guest system time equals host | |
684 | * system time for us, thus we must fill in host boot time here. | |
685 | */ | |
923de3cf | 686 | getboottime(&boot); |
50d0a0f9 GH |
687 | |
688 | wc.sec = boot.tv_sec; | |
689 | wc.nsec = boot.tv_nsec; | |
690 | wc.version = version; | |
18068523 GOC |
691 | |
692 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
693 | ||
694 | version++; | |
695 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
696 | } |
697 | ||
50d0a0f9 GH |
698 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
699 | { | |
700 | uint32_t quotient, remainder; | |
701 | ||
702 | /* Don't try to replace with do_div(), this one calculates | |
703 | * "(dividend << 32) / divisor" */ | |
704 | __asm__ ( "divl %4" | |
705 | : "=a" (quotient), "=d" (remainder) | |
706 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
707 | return quotient; | |
708 | } | |
709 | ||
710 | static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock) | |
711 | { | |
712 | uint64_t nsecs = 1000000000LL; | |
713 | int32_t shift = 0; | |
714 | uint64_t tps64; | |
715 | uint32_t tps32; | |
716 | ||
717 | tps64 = tsc_khz * 1000LL; | |
718 | while (tps64 > nsecs*2) { | |
719 | tps64 >>= 1; | |
720 | shift--; | |
721 | } | |
722 | ||
723 | tps32 = (uint32_t)tps64; | |
724 | while (tps32 <= (uint32_t)nsecs) { | |
725 | tps32 <<= 1; | |
726 | shift++; | |
727 | } | |
728 | ||
729 | hv_clock->tsc_shift = shift; | |
730 | hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32); | |
731 | ||
732 | pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n", | |
80a914dc | 733 | __func__, tsc_khz, hv_clock->tsc_shift, |
50d0a0f9 GH |
734 | hv_clock->tsc_to_system_mul); |
735 | } | |
736 | ||
c8076604 GH |
737 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
738 | ||
18068523 GOC |
739 | static void kvm_write_guest_time(struct kvm_vcpu *v) |
740 | { | |
741 | struct timespec ts; | |
742 | unsigned long flags; | |
743 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
744 | void *shared_kaddr; | |
463656c0 | 745 | unsigned long this_tsc_khz; |
18068523 GOC |
746 | |
747 | if ((!vcpu->time_page)) | |
748 | return; | |
749 | ||
463656c0 AK |
750 | this_tsc_khz = get_cpu_var(cpu_tsc_khz); |
751 | if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) { | |
752 | kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock); | |
753 | vcpu->hv_clock_tsc_khz = this_tsc_khz; | |
50d0a0f9 | 754 | } |
463656c0 | 755 | put_cpu_var(cpu_tsc_khz); |
50d0a0f9 | 756 | |
18068523 GOC |
757 | /* Keep irq disabled to prevent changes to the clock */ |
758 | local_irq_save(flags); | |
af24a4e4 | 759 | kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp); |
18068523 | 760 | ktime_get_ts(&ts); |
923de3cf | 761 | monotonic_to_bootbased(&ts); |
18068523 GOC |
762 | local_irq_restore(flags); |
763 | ||
764 | /* With all the info we got, fill in the values */ | |
765 | ||
766 | vcpu->hv_clock.system_time = ts.tv_nsec + | |
afbcf7ab GC |
767 | (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset; |
768 | ||
18068523 GOC |
769 | /* |
770 | * The interface expects us to write an even number signaling that the | |
771 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 772 | * state, we just increase by 2 at the end. |
18068523 | 773 | */ |
50d0a0f9 | 774 | vcpu->hv_clock.version += 2; |
18068523 GOC |
775 | |
776 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
777 | ||
778 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 779 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
780 | |
781 | kunmap_atomic(shared_kaddr, KM_USER0); | |
782 | ||
783 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
784 | } | |
785 | ||
c8076604 GH |
786 | static int kvm_request_guest_time_update(struct kvm_vcpu *v) |
787 | { | |
788 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
789 | ||
790 | if (!vcpu->time_page) | |
791 | return 0; | |
792 | set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests); | |
793 | return 1; | |
794 | } | |
795 | ||
9ba075a6 AK |
796 | static bool msr_mtrr_valid(unsigned msr) |
797 | { | |
798 | switch (msr) { | |
799 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
800 | case MSR_MTRRfix64K_00000: | |
801 | case MSR_MTRRfix16K_80000: | |
802 | case MSR_MTRRfix16K_A0000: | |
803 | case MSR_MTRRfix4K_C0000: | |
804 | case MSR_MTRRfix4K_C8000: | |
805 | case MSR_MTRRfix4K_D0000: | |
806 | case MSR_MTRRfix4K_D8000: | |
807 | case MSR_MTRRfix4K_E0000: | |
808 | case MSR_MTRRfix4K_E8000: | |
809 | case MSR_MTRRfix4K_F0000: | |
810 | case MSR_MTRRfix4K_F8000: | |
811 | case MSR_MTRRdefType: | |
812 | case MSR_IA32_CR_PAT: | |
813 | return true; | |
814 | case 0x2f8: | |
815 | return true; | |
816 | } | |
817 | return false; | |
818 | } | |
819 | ||
d6289b93 MT |
820 | static bool valid_pat_type(unsigned t) |
821 | { | |
822 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
823 | } | |
824 | ||
825 | static bool valid_mtrr_type(unsigned t) | |
826 | { | |
827 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
828 | } | |
829 | ||
830 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
831 | { | |
832 | int i; | |
833 | ||
834 | if (!msr_mtrr_valid(msr)) | |
835 | return false; | |
836 | ||
837 | if (msr == MSR_IA32_CR_PAT) { | |
838 | for (i = 0; i < 8; i++) | |
839 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
840 | return false; | |
841 | return true; | |
842 | } else if (msr == MSR_MTRRdefType) { | |
843 | if (data & ~0xcff) | |
844 | return false; | |
845 | return valid_mtrr_type(data & 0xff); | |
846 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
847 | for (i = 0; i < 8 ; i++) | |
848 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
849 | return false; | |
850 | return true; | |
851 | } | |
852 | ||
853 | /* variable MTRRs */ | |
854 | return valid_mtrr_type(data & 0xff); | |
855 | } | |
856 | ||
9ba075a6 AK |
857 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
858 | { | |
0bed3b56 SY |
859 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
860 | ||
d6289b93 | 861 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
862 | return 1; |
863 | ||
0bed3b56 SY |
864 | if (msr == MSR_MTRRdefType) { |
865 | vcpu->arch.mtrr_state.def_type = data; | |
866 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
867 | } else if (msr == MSR_MTRRfix64K_00000) | |
868 | p[0] = data; | |
869 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
870 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
871 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
872 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
873 | else if (msr == MSR_IA32_CR_PAT) | |
874 | vcpu->arch.pat = data; | |
875 | else { /* Variable MTRRs */ | |
876 | int idx, is_mtrr_mask; | |
877 | u64 *pt; | |
878 | ||
879 | idx = (msr - 0x200) / 2; | |
880 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
881 | if (!is_mtrr_mask) | |
882 | pt = | |
883 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
884 | else | |
885 | pt = | |
886 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
887 | *pt = data; | |
888 | } | |
889 | ||
890 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
891 | return 0; |
892 | } | |
15c4a640 | 893 | |
890ca9ae | 894 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 895 | { |
890ca9ae HY |
896 | u64 mcg_cap = vcpu->arch.mcg_cap; |
897 | unsigned bank_num = mcg_cap & 0xff; | |
898 | ||
15c4a640 | 899 | switch (msr) { |
15c4a640 | 900 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 901 | vcpu->arch.mcg_status = data; |
15c4a640 | 902 | break; |
c7ac679c | 903 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
904 | if (!(mcg_cap & MCG_CTL_P)) |
905 | return 1; | |
906 | if (data != 0 && data != ~(u64)0) | |
907 | return -1; | |
908 | vcpu->arch.mcg_ctl = data; | |
909 | break; | |
910 | default: | |
911 | if (msr >= MSR_IA32_MC0_CTL && | |
912 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
913 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
114be429 AP |
914 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
915 | * some Linux kernels though clear bit 10 in bank 4 to | |
916 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
917 | * this to avoid an uncatched #GP in the guest | |
918 | */ | |
890ca9ae | 919 | if ((offset & 0x3) == 0 && |
114be429 | 920 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae HY |
921 | return -1; |
922 | vcpu->arch.mce_banks[offset] = data; | |
923 | break; | |
924 | } | |
925 | return 1; | |
926 | } | |
927 | return 0; | |
928 | } | |
929 | ||
ffde22ac ES |
930 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
931 | { | |
932 | struct kvm *kvm = vcpu->kvm; | |
933 | int lm = is_long_mode(vcpu); | |
934 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
935 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
936 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
937 | : kvm->arch.xen_hvm_config.blob_size_32; | |
938 | u32 page_num = data & ~PAGE_MASK; | |
939 | u64 page_addr = data & PAGE_MASK; | |
940 | u8 *page; | |
941 | int r; | |
942 | ||
943 | r = -E2BIG; | |
944 | if (page_num >= blob_size) | |
945 | goto out; | |
946 | r = -ENOMEM; | |
947 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
948 | if (!page) | |
949 | goto out; | |
950 | r = -EFAULT; | |
951 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
952 | goto out_free; | |
953 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
954 | goto out_free; | |
955 | r = 0; | |
956 | out_free: | |
957 | kfree(page); | |
958 | out: | |
959 | return r; | |
960 | } | |
961 | ||
55cd8e5a GN |
962 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) |
963 | { | |
964 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
965 | } | |
966 | ||
967 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
968 | { | |
969 | bool r = false; | |
970 | switch (msr) { | |
971 | case HV_X64_MSR_GUEST_OS_ID: | |
972 | case HV_X64_MSR_HYPERCALL: | |
973 | r = true; | |
974 | break; | |
975 | } | |
976 | ||
977 | return r; | |
978 | } | |
979 | ||
980 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
981 | { | |
982 | struct kvm *kvm = vcpu->kvm; | |
983 | ||
984 | switch (msr) { | |
985 | case HV_X64_MSR_GUEST_OS_ID: | |
986 | kvm->arch.hv_guest_os_id = data; | |
987 | /* setting guest os id to zero disables hypercall page */ | |
988 | if (!kvm->arch.hv_guest_os_id) | |
989 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
990 | break; | |
991 | case HV_X64_MSR_HYPERCALL: { | |
992 | u64 gfn; | |
993 | unsigned long addr; | |
994 | u8 instructions[4]; | |
995 | ||
996 | /* if guest os id is not set hypercall should remain disabled */ | |
997 | if (!kvm->arch.hv_guest_os_id) | |
998 | break; | |
999 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1000 | kvm->arch.hv_hypercall = data; | |
1001 | break; | |
1002 | } | |
1003 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1004 | addr = gfn_to_hva(kvm, gfn); | |
1005 | if (kvm_is_error_hva(addr)) | |
1006 | return 1; | |
1007 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1008 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1009 | if (copy_to_user((void __user *)addr, instructions, 4)) | |
1010 | return 1; | |
1011 | kvm->arch.hv_hypercall = data; | |
1012 | break; | |
1013 | } | |
1014 | default: | |
1015 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1016 | "data 0x%llx\n", msr, data); | |
1017 | return 1; | |
1018 | } | |
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1023 | { | |
10388a07 GN |
1024 | switch (msr) { |
1025 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1026 | unsigned long addr; | |
55cd8e5a | 1027 | |
10388a07 GN |
1028 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { |
1029 | vcpu->arch.hv_vapic = data; | |
1030 | break; | |
1031 | } | |
1032 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1033 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1034 | if (kvm_is_error_hva(addr)) | |
1035 | return 1; | |
1036 | if (clear_user((void __user *)addr, PAGE_SIZE)) | |
1037 | return 1; | |
1038 | vcpu->arch.hv_vapic = data; | |
1039 | break; | |
1040 | } | |
1041 | case HV_X64_MSR_EOI: | |
1042 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1043 | case HV_X64_MSR_ICR: | |
1044 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1045 | case HV_X64_MSR_TPR: | |
1046 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1047 | default: | |
1048 | pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1049 | "data 0x%llx\n", msr, data); | |
1050 | return 1; | |
1051 | } | |
1052 | ||
1053 | return 0; | |
55cd8e5a GN |
1054 | } |
1055 | ||
15c4a640 CO |
1056 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
1057 | { | |
1058 | switch (msr) { | |
15c4a640 CO |
1059 | case MSR_EFER: |
1060 | set_efer(vcpu, data); | |
1061 | break; | |
8f1589d9 AP |
1062 | case MSR_K7_HWCR: |
1063 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 1064 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
8f1589d9 AP |
1065 | if (data != 0) { |
1066 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1067 | data); | |
1068 | return 1; | |
1069 | } | |
15c4a640 | 1070 | break; |
f7c6d140 AP |
1071 | case MSR_FAM10H_MMIO_CONF_BASE: |
1072 | if (data != 0) { | |
1073 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
1074 | "0x%llx\n", data); | |
1075 | return 1; | |
1076 | } | |
15c4a640 | 1077 | break; |
c323c0e5 | 1078 | case MSR_AMD64_NB_CFG: |
c7ac679c | 1079 | break; |
b5e2fec0 AG |
1080 | case MSR_IA32_DEBUGCTLMSR: |
1081 | if (!data) { | |
1082 | /* We support the non-activated case already */ | |
1083 | break; | |
1084 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
1085 | /* Values other than LBR and BTF are vendor-specific, | |
1086 | thus reserved and should throw a #GP */ | |
1087 | return 1; | |
1088 | } | |
1089 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1090 | __func__, data); | |
1091 | break; | |
15c4a640 CO |
1092 | case MSR_IA32_UCODE_REV: |
1093 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 1094 | case MSR_VM_HSAVE_PA: |
6098ca93 | 1095 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 1096 | break; |
9ba075a6 AK |
1097 | case 0x200 ... 0x2ff: |
1098 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
1099 | case MSR_IA32_APICBASE: |
1100 | kvm_set_apic_base(vcpu, data); | |
1101 | break; | |
0105d1a5 GN |
1102 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1103 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 1104 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1105 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1106 | break; |
18068523 GOC |
1107 | case MSR_KVM_WALL_CLOCK: |
1108 | vcpu->kvm->arch.wall_clock = data; | |
1109 | kvm_write_wall_clock(vcpu->kvm, data); | |
1110 | break; | |
1111 | case MSR_KVM_SYSTEM_TIME: { | |
1112 | if (vcpu->arch.time_page) { | |
1113 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1114 | vcpu->arch.time_page = NULL; | |
1115 | } | |
1116 | ||
1117 | vcpu->arch.time = data; | |
1118 | ||
1119 | /* we verify if the enable bit is set... */ | |
1120 | if (!(data & 1)) | |
1121 | break; | |
1122 | ||
1123 | /* ...but clean it before doing the actual write */ | |
1124 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1125 | ||
18068523 GOC |
1126 | vcpu->arch.time_page = |
1127 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1128 | |
1129 | if (is_error_page(vcpu->arch.time_page)) { | |
1130 | kvm_release_page_clean(vcpu->arch.time_page); | |
1131 | vcpu->arch.time_page = NULL; | |
1132 | } | |
1133 | ||
c8076604 | 1134 | kvm_request_guest_time_update(vcpu); |
18068523 GOC |
1135 | break; |
1136 | } | |
890ca9ae HY |
1137 | case MSR_IA32_MCG_CTL: |
1138 | case MSR_IA32_MCG_STATUS: | |
1139 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1140 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1141 | |
1142 | /* Performance counters are not protected by a CPUID bit, | |
1143 | * so we should check all of them in the generic path for the sake of | |
1144 | * cross vendor migration. | |
1145 | * Writing a zero into the event select MSRs disables them, | |
1146 | * which we perfectly emulate ;-). Any other value should be at least | |
1147 | * reported, some guests depend on them. | |
1148 | */ | |
1149 | case MSR_P6_EVNTSEL0: | |
1150 | case MSR_P6_EVNTSEL1: | |
1151 | case MSR_K7_EVNTSEL0: | |
1152 | case MSR_K7_EVNTSEL1: | |
1153 | case MSR_K7_EVNTSEL2: | |
1154 | case MSR_K7_EVNTSEL3: | |
1155 | if (data != 0) | |
1156 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1157 | "0x%x data 0x%llx\n", msr, data); | |
1158 | break; | |
1159 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1160 | * so we ignore writes to make it happy. | |
1161 | */ | |
1162 | case MSR_P6_PERFCTR0: | |
1163 | case MSR_P6_PERFCTR1: | |
1164 | case MSR_K7_PERFCTR0: | |
1165 | case MSR_K7_PERFCTR1: | |
1166 | case MSR_K7_PERFCTR2: | |
1167 | case MSR_K7_PERFCTR3: | |
1168 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1169 | "0x%x data 0x%llx\n", msr, data); | |
1170 | break; | |
55cd8e5a GN |
1171 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1172 | if (kvm_hv_msr_partition_wide(msr)) { | |
1173 | int r; | |
1174 | mutex_lock(&vcpu->kvm->lock); | |
1175 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
1176 | mutex_unlock(&vcpu->kvm->lock); | |
1177 | return r; | |
1178 | } else | |
1179 | return set_msr_hyperv(vcpu, msr, data); | |
1180 | break; | |
15c4a640 | 1181 | default: |
ffde22ac ES |
1182 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1183 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1184 | if (!ignore_msrs) { |
1185 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1186 | msr, data); | |
1187 | return 1; | |
1188 | } else { | |
1189 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1190 | msr, data); | |
1191 | break; | |
1192 | } | |
15c4a640 CO |
1193 | } |
1194 | return 0; | |
1195 | } | |
1196 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1197 | ||
1198 | ||
1199 | /* | |
1200 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1201 | * Returns 0 on success, non-0 otherwise. | |
1202 | * Assumes vcpu_load() was already called. | |
1203 | */ | |
1204 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1205 | { | |
1206 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1207 | } | |
1208 | ||
9ba075a6 AK |
1209 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1210 | { | |
0bed3b56 SY |
1211 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1212 | ||
9ba075a6 AK |
1213 | if (!msr_mtrr_valid(msr)) |
1214 | return 1; | |
1215 | ||
0bed3b56 SY |
1216 | if (msr == MSR_MTRRdefType) |
1217 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1218 | (vcpu->arch.mtrr_state.enabled << 10); | |
1219 | else if (msr == MSR_MTRRfix64K_00000) | |
1220 | *pdata = p[0]; | |
1221 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1222 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1223 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1224 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1225 | else if (msr == MSR_IA32_CR_PAT) | |
1226 | *pdata = vcpu->arch.pat; | |
1227 | else { /* Variable MTRRs */ | |
1228 | int idx, is_mtrr_mask; | |
1229 | u64 *pt; | |
1230 | ||
1231 | idx = (msr - 0x200) / 2; | |
1232 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1233 | if (!is_mtrr_mask) | |
1234 | pt = | |
1235 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1236 | else | |
1237 | pt = | |
1238 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1239 | *pdata = *pt; | |
1240 | } | |
1241 | ||
9ba075a6 AK |
1242 | return 0; |
1243 | } | |
1244 | ||
890ca9ae | 1245 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1246 | { |
1247 | u64 data; | |
890ca9ae HY |
1248 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1249 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1250 | |
1251 | switch (msr) { | |
15c4a640 CO |
1252 | case MSR_IA32_P5_MC_ADDR: |
1253 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1254 | data = 0; |
1255 | break; | |
15c4a640 | 1256 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1257 | data = vcpu->arch.mcg_cap; |
1258 | break; | |
c7ac679c | 1259 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1260 | if (!(mcg_cap & MCG_CTL_P)) |
1261 | return 1; | |
1262 | data = vcpu->arch.mcg_ctl; | |
1263 | break; | |
1264 | case MSR_IA32_MCG_STATUS: | |
1265 | data = vcpu->arch.mcg_status; | |
1266 | break; | |
1267 | default: | |
1268 | if (msr >= MSR_IA32_MC0_CTL && | |
1269 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1270 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1271 | data = vcpu->arch.mce_banks[offset]; | |
1272 | break; | |
1273 | } | |
1274 | return 1; | |
1275 | } | |
1276 | *pdata = data; | |
1277 | return 0; | |
1278 | } | |
1279 | ||
55cd8e5a GN |
1280 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1281 | { | |
1282 | u64 data = 0; | |
1283 | struct kvm *kvm = vcpu->kvm; | |
1284 | ||
1285 | switch (msr) { | |
1286 | case HV_X64_MSR_GUEST_OS_ID: | |
1287 | data = kvm->arch.hv_guest_os_id; | |
1288 | break; | |
1289 | case HV_X64_MSR_HYPERCALL: | |
1290 | data = kvm->arch.hv_hypercall; | |
1291 | break; | |
1292 | default: | |
1293 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1294 | return 1; | |
1295 | } | |
1296 | ||
1297 | *pdata = data; | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1302 | { | |
1303 | u64 data = 0; | |
1304 | ||
1305 | switch (msr) { | |
1306 | case HV_X64_MSR_VP_INDEX: { | |
1307 | int r; | |
1308 | struct kvm_vcpu *v; | |
1309 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
1310 | if (v == vcpu) | |
1311 | data = r; | |
1312 | break; | |
1313 | } | |
10388a07 GN |
1314 | case HV_X64_MSR_EOI: |
1315 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
1316 | case HV_X64_MSR_ICR: | |
1317 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
1318 | case HV_X64_MSR_TPR: | |
1319 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
55cd8e5a GN |
1320 | default: |
1321 | pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
1322 | return 1; | |
1323 | } | |
1324 | *pdata = data; | |
1325 | return 0; | |
1326 | } | |
1327 | ||
890ca9ae HY |
1328 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1329 | { | |
1330 | u64 data; | |
1331 | ||
1332 | switch (msr) { | |
890ca9ae | 1333 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1334 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1335 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1336 | case MSR_IA32_DEBUGCTLMSR: |
1337 | case MSR_IA32_LASTBRANCHFROMIP: | |
1338 | case MSR_IA32_LASTBRANCHTOIP: | |
1339 | case MSR_IA32_LASTINTFROMIP: | |
1340 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1341 | case MSR_K8_SYSCFG: |
1342 | case MSR_K7_HWCR: | |
61a6bd67 | 1343 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1344 | case MSR_P6_PERFCTR0: |
1345 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1346 | case MSR_P6_EVNTSEL0: |
1347 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1348 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1349 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1350 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1351 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1352 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1353 | data = 0; |
1354 | break; | |
9ba075a6 AK |
1355 | case MSR_MTRRcap: |
1356 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1357 | break; | |
1358 | case 0x200 ... 0x2ff: | |
1359 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1360 | case 0xcd: /* fsb frequency */ |
1361 | data = 3; | |
1362 | break; | |
1363 | case MSR_IA32_APICBASE: | |
1364 | data = kvm_get_apic_base(vcpu); | |
1365 | break; | |
0105d1a5 GN |
1366 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1367 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1368 | break; | |
15c4a640 | 1369 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1370 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1371 | break; |
847f0ad8 AG |
1372 | case MSR_IA32_PERF_STATUS: |
1373 | /* TSC increment by tick */ | |
1374 | data = 1000ULL; | |
1375 | /* CPU multiplier */ | |
1376 | data |= (((uint64_t)4ULL) << 40); | |
1377 | break; | |
15c4a640 | 1378 | case MSR_EFER: |
f6801dff | 1379 | data = vcpu->arch.efer; |
15c4a640 | 1380 | break; |
18068523 GOC |
1381 | case MSR_KVM_WALL_CLOCK: |
1382 | data = vcpu->kvm->arch.wall_clock; | |
1383 | break; | |
1384 | case MSR_KVM_SYSTEM_TIME: | |
1385 | data = vcpu->arch.time; | |
1386 | break; | |
890ca9ae HY |
1387 | case MSR_IA32_P5_MC_ADDR: |
1388 | case MSR_IA32_P5_MC_TYPE: | |
1389 | case MSR_IA32_MCG_CAP: | |
1390 | case MSR_IA32_MCG_CTL: | |
1391 | case MSR_IA32_MCG_STATUS: | |
1392 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1393 | return get_msr_mce(vcpu, msr, pdata); | |
55cd8e5a GN |
1394 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
1395 | if (kvm_hv_msr_partition_wide(msr)) { | |
1396 | int r; | |
1397 | mutex_lock(&vcpu->kvm->lock); | |
1398 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
1399 | mutex_unlock(&vcpu->kvm->lock); | |
1400 | return r; | |
1401 | } else | |
1402 | return get_msr_hyperv(vcpu, msr, pdata); | |
1403 | break; | |
15c4a640 | 1404 | default: |
ed85c068 AP |
1405 | if (!ignore_msrs) { |
1406 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1407 | return 1; | |
1408 | } else { | |
1409 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1410 | data = 0; | |
1411 | } | |
1412 | break; | |
15c4a640 CO |
1413 | } |
1414 | *pdata = data; | |
1415 | return 0; | |
1416 | } | |
1417 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1418 | ||
313a3dc7 CO |
1419 | /* |
1420 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1421 | * | |
1422 | * @return number of msrs set successfully. | |
1423 | */ | |
1424 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1425 | struct kvm_msr_entry *entries, | |
1426 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1427 | unsigned index, u64 *data)) | |
1428 | { | |
f656ce01 | 1429 | int i, idx; |
313a3dc7 CO |
1430 | |
1431 | vcpu_load(vcpu); | |
1432 | ||
f656ce01 | 1433 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
313a3dc7 CO |
1434 | for (i = 0; i < msrs->nmsrs; ++i) |
1435 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1436 | break; | |
f656ce01 | 1437 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 CO |
1438 | |
1439 | vcpu_put(vcpu); | |
1440 | ||
1441 | return i; | |
1442 | } | |
1443 | ||
1444 | /* | |
1445 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1446 | * | |
1447 | * @return number of msrs set successfully. | |
1448 | */ | |
1449 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1450 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1451 | unsigned index, u64 *data), | |
1452 | int writeback) | |
1453 | { | |
1454 | struct kvm_msrs msrs; | |
1455 | struct kvm_msr_entry *entries; | |
1456 | int r, n; | |
1457 | unsigned size; | |
1458 | ||
1459 | r = -EFAULT; | |
1460 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1461 | goto out; | |
1462 | ||
1463 | r = -E2BIG; | |
1464 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1465 | goto out; | |
1466 | ||
1467 | r = -ENOMEM; | |
1468 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
1469 | entries = vmalloc(size); | |
1470 | if (!entries) | |
1471 | goto out; | |
1472 | ||
1473 | r = -EFAULT; | |
1474 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1475 | goto out_free; | |
1476 | ||
1477 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1478 | if (r < 0) | |
1479 | goto out_free; | |
1480 | ||
1481 | r = -EFAULT; | |
1482 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1483 | goto out_free; | |
1484 | ||
1485 | r = n; | |
1486 | ||
1487 | out_free: | |
1488 | vfree(entries); | |
1489 | out: | |
1490 | return r; | |
1491 | } | |
1492 | ||
018d00d2 ZX |
1493 | int kvm_dev_ioctl_check_extension(long ext) |
1494 | { | |
1495 | int r; | |
1496 | ||
1497 | switch (ext) { | |
1498 | case KVM_CAP_IRQCHIP: | |
1499 | case KVM_CAP_HLT: | |
1500 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1501 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1502 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1503 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1504 | case KVM_CAP_PIT: |
a28e4f5a | 1505 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1506 | case KVM_CAP_MP_STATE: |
ed848624 | 1507 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1508 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1509 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1510 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1511 | case KVM_CAP_IRQFD: |
d34e6b17 | 1512 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1513 | case KVM_CAP_PIT2: |
e9f42757 | 1514 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1515 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1516 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1517 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1518 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 1519 | case KVM_CAP_HYPERV: |
10388a07 | 1520 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 1521 | case KVM_CAP_HYPERV_SPIN: |
ab9f4ecb | 1522 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 1523 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 1524 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
018d00d2 ZX |
1525 | r = 1; |
1526 | break; | |
542472b5 LV |
1527 | case KVM_CAP_COALESCED_MMIO: |
1528 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1529 | break; | |
774ead3a AK |
1530 | case KVM_CAP_VAPIC: |
1531 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1532 | break; | |
f725230a AK |
1533 | case KVM_CAP_NR_VCPUS: |
1534 | r = KVM_MAX_VCPUS; | |
1535 | break; | |
a988b910 AK |
1536 | case KVM_CAP_NR_MEMSLOTS: |
1537 | r = KVM_MEMORY_SLOTS; | |
1538 | break; | |
a68a6a72 MT |
1539 | case KVM_CAP_PV_MMU: /* obsolete */ |
1540 | r = 0; | |
2f333bcb | 1541 | break; |
62c476c7 | 1542 | case KVM_CAP_IOMMU: |
19de40a8 | 1543 | r = iommu_found(); |
62c476c7 | 1544 | break; |
890ca9ae HY |
1545 | case KVM_CAP_MCE: |
1546 | r = KVM_MAX_MCE_BANKS; | |
1547 | break; | |
018d00d2 ZX |
1548 | default: |
1549 | r = 0; | |
1550 | break; | |
1551 | } | |
1552 | return r; | |
1553 | ||
1554 | } | |
1555 | ||
043405e1 CO |
1556 | long kvm_arch_dev_ioctl(struct file *filp, |
1557 | unsigned int ioctl, unsigned long arg) | |
1558 | { | |
1559 | void __user *argp = (void __user *)arg; | |
1560 | long r; | |
1561 | ||
1562 | switch (ioctl) { | |
1563 | case KVM_GET_MSR_INDEX_LIST: { | |
1564 | struct kvm_msr_list __user *user_msr_list = argp; | |
1565 | struct kvm_msr_list msr_list; | |
1566 | unsigned n; | |
1567 | ||
1568 | r = -EFAULT; | |
1569 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
1570 | goto out; | |
1571 | n = msr_list.nmsrs; | |
1572 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
1573 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
1574 | goto out; | |
1575 | r = -E2BIG; | |
e125e7b6 | 1576 | if (n < msr_list.nmsrs) |
043405e1 CO |
1577 | goto out; |
1578 | r = -EFAULT; | |
1579 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
1580 | num_msrs_to_save * sizeof(u32))) | |
1581 | goto out; | |
e125e7b6 | 1582 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
1583 | &emulated_msrs, |
1584 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
1585 | goto out; | |
1586 | r = 0; | |
1587 | break; | |
1588 | } | |
674eea0f AK |
1589 | case KVM_GET_SUPPORTED_CPUID: { |
1590 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1591 | struct kvm_cpuid2 cpuid; | |
1592 | ||
1593 | r = -EFAULT; | |
1594 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1595 | goto out; | |
1596 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 1597 | cpuid_arg->entries); |
674eea0f AK |
1598 | if (r) |
1599 | goto out; | |
1600 | ||
1601 | r = -EFAULT; | |
1602 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1603 | goto out; | |
1604 | r = 0; | |
1605 | break; | |
1606 | } | |
890ca9ae HY |
1607 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
1608 | u64 mce_cap; | |
1609 | ||
1610 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
1611 | r = -EFAULT; | |
1612 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
1613 | goto out; | |
1614 | r = 0; | |
1615 | break; | |
1616 | } | |
043405e1 CO |
1617 | default: |
1618 | r = -EINVAL; | |
1619 | } | |
1620 | out: | |
1621 | return r; | |
1622 | } | |
1623 | ||
313a3dc7 CO |
1624 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1625 | { | |
1626 | kvm_x86_ops->vcpu_load(vcpu, cpu); | |
6b7d7e76 ZA |
1627 | if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) { |
1628 | unsigned long khz = cpufreq_quick_get(cpu); | |
1629 | if (!khz) | |
1630 | khz = tsc_khz; | |
1631 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
1632 | } | |
c8076604 | 1633 | kvm_request_guest_time_update(vcpu); |
313a3dc7 CO |
1634 | } |
1635 | ||
1636 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
1637 | { | |
9327fd11 | 1638 | kvm_put_guest_fpu(vcpu); |
02daab21 | 1639 | kvm_x86_ops->vcpu_put(vcpu); |
313a3dc7 CO |
1640 | } |
1641 | ||
07716717 | 1642 | static int is_efer_nx(void) |
313a3dc7 | 1643 | { |
e286e86e | 1644 | unsigned long long efer = 0; |
313a3dc7 | 1645 | |
e286e86e | 1646 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
1647 | return efer & EFER_NX; |
1648 | } | |
1649 | ||
1650 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
1651 | { | |
1652 | int i; | |
1653 | struct kvm_cpuid_entry2 *e, *entry; | |
1654 | ||
313a3dc7 | 1655 | entry = NULL; |
ad312c7c ZX |
1656 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
1657 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
1658 | if (e->function == 0x80000001) { |
1659 | entry = e; | |
1660 | break; | |
1661 | } | |
1662 | } | |
07716717 | 1663 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
1664 | entry->edx &= ~(1 << 20); |
1665 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
1666 | } | |
1667 | } | |
1668 | ||
07716717 | 1669 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
1670 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
1671 | struct kvm_cpuid *cpuid, | |
1672 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
1673 | { |
1674 | int r, i; | |
1675 | struct kvm_cpuid_entry *cpuid_entries; | |
1676 | ||
1677 | r = -E2BIG; | |
1678 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1679 | goto out; | |
1680 | r = -ENOMEM; | |
1681 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
1682 | if (!cpuid_entries) | |
1683 | goto out; | |
1684 | r = -EFAULT; | |
1685 | if (copy_from_user(cpuid_entries, entries, | |
1686 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
1687 | goto out_free; | |
1688 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
1689 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
1690 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
1691 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
1692 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
1693 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
1694 | vcpu->arch.cpuid_entries[i].index = 0; | |
1695 | vcpu->arch.cpuid_entries[i].flags = 0; | |
1696 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
1697 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
1698 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
1699 | } | |
1700 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
1701 | cpuid_fix_nx_cap(vcpu); |
1702 | r = 0; | |
fc61b800 | 1703 | kvm_apic_set_version(vcpu); |
0e851880 | 1704 | kvm_x86_ops->cpuid_update(vcpu); |
07716717 DK |
1705 | |
1706 | out_free: | |
1707 | vfree(cpuid_entries); | |
1708 | out: | |
1709 | return r; | |
1710 | } | |
1711 | ||
1712 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
1713 | struct kvm_cpuid2 *cpuid, |
1714 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
1715 | { |
1716 | int r; | |
1717 | ||
1718 | r = -E2BIG; | |
1719 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1720 | goto out; | |
1721 | r = -EFAULT; | |
ad312c7c | 1722 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 1723 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 1724 | goto out; |
ad312c7c | 1725 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 1726 | kvm_apic_set_version(vcpu); |
0e851880 | 1727 | kvm_x86_ops->cpuid_update(vcpu); |
313a3dc7 CO |
1728 | return 0; |
1729 | ||
1730 | out: | |
1731 | return r; | |
1732 | } | |
1733 | ||
07716717 | 1734 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
1735 | struct kvm_cpuid2 *cpuid, |
1736 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
1737 | { |
1738 | int r; | |
1739 | ||
1740 | r = -E2BIG; | |
ad312c7c | 1741 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
1742 | goto out; |
1743 | r = -EFAULT; | |
ad312c7c | 1744 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 1745 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1746 | goto out; |
1747 | return 0; | |
1748 | ||
1749 | out: | |
ad312c7c | 1750 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
1751 | return r; |
1752 | } | |
1753 | ||
07716717 | 1754 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 1755 | u32 index) |
07716717 DK |
1756 | { |
1757 | entry->function = function; | |
1758 | entry->index = index; | |
1759 | cpuid_count(entry->function, entry->index, | |
19355475 | 1760 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
1761 | entry->flags = 0; |
1762 | } | |
1763 | ||
7faa4ee1 AK |
1764 | #define F(x) bit(X86_FEATURE_##x) |
1765 | ||
07716717 DK |
1766 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
1767 | u32 index, int *nent, int maxnent) | |
1768 | { | |
7faa4ee1 | 1769 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
07716717 | 1770 | #ifdef CONFIG_X86_64 |
17cc3935 SY |
1771 | unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL) |
1772 | ? F(GBPAGES) : 0; | |
7faa4ee1 AK |
1773 | unsigned f_lm = F(LM); |
1774 | #else | |
17cc3935 | 1775 | unsigned f_gbpages = 0; |
7faa4ee1 | 1776 | unsigned f_lm = 0; |
07716717 | 1777 | #endif |
4e47c7a6 | 1778 | unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0; |
7faa4ee1 AK |
1779 | |
1780 | /* cpuid 1.edx */ | |
1781 | const u32 kvm_supported_word0_x86_features = | |
1782 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1783 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1784 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
1785 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1786 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
1787 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
1788 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
1789 | 0 /* HTT, TM, Reserved, PBE */; | |
1790 | /* cpuid 0x80000001.edx */ | |
1791 | const u32 kvm_supported_word1_x86_features = | |
1792 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1793 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1794 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
1795 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1796 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
1797 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
4e47c7a6 | 1798 | F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp | |
7faa4ee1 AK |
1799 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
1800 | /* cpuid 1.ecx */ | |
1801 | const u32 kvm_supported_word4_x86_features = | |
d149c731 AK |
1802 | F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ | |
1803 | 0 /* DS-CPL, VMX, SMX, EST */ | | |
1804 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
1805 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
1806 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 1807 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
d149c731 | 1808 | 0 /* Reserved, XSAVE, OSXSAVE */; |
7faa4ee1 | 1809 | /* cpuid 0x80000001.ecx */ |
07716717 | 1810 | const u32 kvm_supported_word6_x86_features = |
7faa4ee1 AK |
1811 | F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ | |
1812 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
1813 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) | | |
1814 | 0 /* SKINIT */ | 0 /* WDT */; | |
07716717 | 1815 | |
19355475 | 1816 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
1817 | get_cpu(); |
1818 | do_cpuid_1_ent(entry, function, index); | |
1819 | ++*nent; | |
1820 | ||
1821 | switch (function) { | |
1822 | case 0: | |
1823 | entry->eax = min(entry->eax, (u32)0xb); | |
1824 | break; | |
1825 | case 1: | |
1826 | entry->edx &= kvm_supported_word0_x86_features; | |
7faa4ee1 | 1827 | entry->ecx &= kvm_supported_word4_x86_features; |
0d1de2d9 GN |
1828 | /* we support x2apic emulation even if host does not support |
1829 | * it since we emulate x2apic in software */ | |
1830 | entry->ecx |= F(X2APIC); | |
07716717 DK |
1831 | break; |
1832 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
1833 | * may return different values. This forces us to get_cpu() before | |
1834 | * issuing the first command, and also to emulate this annoying behavior | |
1835 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
1836 | case 2: { | |
1837 | int t, times = entry->eax & 0xff; | |
1838 | ||
1839 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 1840 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
1841 | for (t = 1; t < times && *nent < maxnent; ++t) { |
1842 | do_cpuid_1_ent(&entry[t], function, 0); | |
1843 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
1844 | ++*nent; | |
1845 | } | |
1846 | break; | |
1847 | } | |
1848 | /* function 4 and 0xb have additional index. */ | |
1849 | case 4: { | |
14af3f3c | 1850 | int i, cache_type; |
07716717 DK |
1851 | |
1852 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1853 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
1854 | for (i = 1; *nent < maxnent; ++i) { |
1855 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
1856 | if (!cache_type) |
1857 | break; | |
14af3f3c HH |
1858 | do_cpuid_1_ent(&entry[i], function, i); |
1859 | entry[i].flags |= | |
07716717 DK |
1860 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1861 | ++*nent; | |
1862 | } | |
1863 | break; | |
1864 | } | |
1865 | case 0xb: { | |
14af3f3c | 1866 | int i, level_type; |
07716717 DK |
1867 | |
1868 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1869 | /* read more entries until level_type is zero */ | |
14af3f3c | 1870 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 1871 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
1872 | if (!level_type) |
1873 | break; | |
14af3f3c HH |
1874 | do_cpuid_1_ent(&entry[i], function, i); |
1875 | entry[i].flags |= | |
07716717 DK |
1876 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1877 | ++*nent; | |
1878 | } | |
1879 | break; | |
1880 | } | |
1881 | case 0x80000000: | |
1882 | entry->eax = min(entry->eax, 0x8000001a); | |
1883 | break; | |
1884 | case 0x80000001: | |
1885 | entry->edx &= kvm_supported_word1_x86_features; | |
1886 | entry->ecx &= kvm_supported_word6_x86_features; | |
1887 | break; | |
1888 | } | |
1889 | put_cpu(); | |
1890 | } | |
1891 | ||
7faa4ee1 AK |
1892 | #undef F |
1893 | ||
674eea0f | 1894 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 1895 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
1896 | { |
1897 | struct kvm_cpuid_entry2 *cpuid_entries; | |
1898 | int limit, nent = 0, r = -E2BIG; | |
1899 | u32 func; | |
1900 | ||
1901 | if (cpuid->nent < 1) | |
1902 | goto out; | |
6a544355 AK |
1903 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
1904 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
1905 | r = -ENOMEM; |
1906 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
1907 | if (!cpuid_entries) | |
1908 | goto out; | |
1909 | ||
1910 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
1911 | limit = cpuid_entries[0].eax; | |
1912 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
1913 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1914 | &nent, cpuid->nent); |
07716717 DK |
1915 | r = -E2BIG; |
1916 | if (nent >= cpuid->nent) | |
1917 | goto out_free; | |
1918 | ||
1919 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
1920 | limit = cpuid_entries[nent - 1].eax; | |
1921 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
1922 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1923 | &nent, cpuid->nent); |
cb007648 MM |
1924 | r = -E2BIG; |
1925 | if (nent >= cpuid->nent) | |
1926 | goto out_free; | |
1927 | ||
07716717 DK |
1928 | r = -EFAULT; |
1929 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 1930 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1931 | goto out_free; |
1932 | cpuid->nent = nent; | |
1933 | r = 0; | |
1934 | ||
1935 | out_free: | |
1936 | vfree(cpuid_entries); | |
1937 | out: | |
1938 | return r; | |
1939 | } | |
1940 | ||
313a3dc7 CO |
1941 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
1942 | struct kvm_lapic_state *s) | |
1943 | { | |
1944 | vcpu_load(vcpu); | |
ad312c7c | 1945 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
1946 | vcpu_put(vcpu); |
1947 | ||
1948 | return 0; | |
1949 | } | |
1950 | ||
1951 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
1952 | struct kvm_lapic_state *s) | |
1953 | { | |
1954 | vcpu_load(vcpu); | |
ad312c7c | 1955 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 1956 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 1957 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
1958 | vcpu_put(vcpu); |
1959 | ||
1960 | return 0; | |
1961 | } | |
1962 | ||
f77bc6a4 ZX |
1963 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
1964 | struct kvm_interrupt *irq) | |
1965 | { | |
1966 | if (irq->irq < 0 || irq->irq >= 256) | |
1967 | return -EINVAL; | |
1968 | if (irqchip_in_kernel(vcpu->kvm)) | |
1969 | return -ENXIO; | |
1970 | vcpu_load(vcpu); | |
1971 | ||
66fd3f7f | 1972 | kvm_queue_interrupt(vcpu, irq->irq, false); |
f77bc6a4 ZX |
1973 | |
1974 | vcpu_put(vcpu); | |
1975 | ||
1976 | return 0; | |
1977 | } | |
1978 | ||
c4abb7c9 JK |
1979 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
1980 | { | |
1981 | vcpu_load(vcpu); | |
1982 | kvm_inject_nmi(vcpu); | |
1983 | vcpu_put(vcpu); | |
1984 | ||
1985 | return 0; | |
1986 | } | |
1987 | ||
b209749f AK |
1988 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
1989 | struct kvm_tpr_access_ctl *tac) | |
1990 | { | |
1991 | if (tac->flags) | |
1992 | return -EINVAL; | |
1993 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
1994 | return 0; | |
1995 | } | |
1996 | ||
890ca9ae HY |
1997 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
1998 | u64 mcg_cap) | |
1999 | { | |
2000 | int r; | |
2001 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2002 | ||
2003 | r = -EINVAL; | |
a9e38c3e | 2004 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
2005 | goto out; |
2006 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2007 | goto out; | |
2008 | r = 0; | |
2009 | vcpu->arch.mcg_cap = mcg_cap; | |
2010 | /* Init IA32_MCG_CTL to all 1s */ | |
2011 | if (mcg_cap & MCG_CTL_P) | |
2012 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2013 | /* Init IA32_MCi_CTL to all 1s */ | |
2014 | for (bank = 0; bank < bank_num; bank++) | |
2015 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2016 | out: | |
2017 | return r; | |
2018 | } | |
2019 | ||
2020 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2021 | struct kvm_x86_mce *mce) | |
2022 | { | |
2023 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2024 | unsigned bank_num = mcg_cap & 0xff; | |
2025 | u64 *banks = vcpu->arch.mce_banks; | |
2026 | ||
2027 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2028 | return -EINVAL; | |
2029 | /* | |
2030 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2031 | * reporting is disabled | |
2032 | */ | |
2033 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2034 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2035 | return 0; | |
2036 | banks += 4 * mce->bank; | |
2037 | /* | |
2038 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2039 | * reporting is disabled for the bank | |
2040 | */ | |
2041 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2042 | return 0; | |
2043 | if (mce->status & MCI_STATUS_UC) { | |
2044 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 2045 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
890ca9ae HY |
2046 | printk(KERN_DEBUG "kvm: set_mce: " |
2047 | "injects mce exception while " | |
2048 | "previous one is in progress!\n"); | |
2049 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
2050 | return 0; | |
2051 | } | |
2052 | if (banks[1] & MCI_STATUS_VAL) | |
2053 | mce->status |= MCI_STATUS_OVER; | |
2054 | banks[2] = mce->addr; | |
2055 | banks[3] = mce->misc; | |
2056 | vcpu->arch.mcg_status = mce->mcg_status; | |
2057 | banks[1] = mce->status; | |
2058 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2059 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2060 | || !(banks[1] & MCI_STATUS_UC)) { | |
2061 | if (banks[1] & MCI_STATUS_VAL) | |
2062 | mce->status |= MCI_STATUS_OVER; | |
2063 | banks[2] = mce->addr; | |
2064 | banks[3] = mce->misc; | |
2065 | banks[1] = mce->status; | |
2066 | } else | |
2067 | banks[1] |= MCI_STATUS_OVER; | |
2068 | return 0; | |
2069 | } | |
2070 | ||
3cfc3092 JK |
2071 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
2072 | struct kvm_vcpu_events *events) | |
2073 | { | |
2074 | vcpu_load(vcpu); | |
2075 | ||
03b82a30 JK |
2076 | events->exception.injected = |
2077 | vcpu->arch.exception.pending && | |
2078 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
3cfc3092 JK |
2079 | events->exception.nr = vcpu->arch.exception.nr; |
2080 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
2081 | events->exception.error_code = vcpu->arch.exception.error_code; | |
2082 | ||
03b82a30 JK |
2083 | events->interrupt.injected = |
2084 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
3cfc3092 | 2085 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 2086 | events->interrupt.soft = 0; |
48005f64 JK |
2087 | events->interrupt.shadow = |
2088 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2089 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
3cfc3092 JK |
2090 | |
2091 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2092 | events->nmi.pending = vcpu->arch.nmi_pending; | |
2093 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
2094 | ||
2095 | events->sipi_vector = vcpu->arch.sipi_vector; | |
2096 | ||
dab4b911 | 2097 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2098 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2099 | | KVM_VCPUEVENT_VALID_SHADOW); | |
3cfc3092 JK |
2100 | |
2101 | vcpu_put(vcpu); | |
2102 | } | |
2103 | ||
2104 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2105 | struct kvm_vcpu_events *events) | |
2106 | { | |
dab4b911 | 2107 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 JK |
2108 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
2109 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
3cfc3092 JK |
2110 | return -EINVAL; |
2111 | ||
2112 | vcpu_load(vcpu); | |
2113 | ||
2114 | vcpu->arch.exception.pending = events->exception.injected; | |
2115 | vcpu->arch.exception.nr = events->exception.nr; | |
2116 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2117 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2118 | ||
2119 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2120 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2121 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
2122 | if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm)) | |
2123 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
48005f64 JK |
2124 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
2125 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2126 | events->interrupt.shadow); | |
3cfc3092 JK |
2127 | |
2128 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
2129 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
2130 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
2131 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
2132 | ||
dab4b911 JK |
2133 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR) |
2134 | vcpu->arch.sipi_vector = events->sipi_vector; | |
3cfc3092 JK |
2135 | |
2136 | vcpu_put(vcpu); | |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
a1efbe77 JK |
2141 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
2142 | struct kvm_debugregs *dbgregs) | |
2143 | { | |
2144 | vcpu_load(vcpu); | |
2145 | ||
2146 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); | |
2147 | dbgregs->dr6 = vcpu->arch.dr6; | |
2148 | dbgregs->dr7 = vcpu->arch.dr7; | |
2149 | dbgregs->flags = 0; | |
2150 | ||
2151 | vcpu_put(vcpu); | |
2152 | } | |
2153 | ||
2154 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2155 | struct kvm_debugregs *dbgregs) | |
2156 | { | |
2157 | if (dbgregs->flags) | |
2158 | return -EINVAL; | |
2159 | ||
2160 | vcpu_load(vcpu); | |
2161 | ||
2162 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); | |
2163 | vcpu->arch.dr6 = dbgregs->dr6; | |
2164 | vcpu->arch.dr7 = dbgregs->dr7; | |
2165 | ||
2166 | vcpu_put(vcpu); | |
2167 | ||
2168 | return 0; | |
2169 | } | |
2170 | ||
313a3dc7 CO |
2171 | long kvm_arch_vcpu_ioctl(struct file *filp, |
2172 | unsigned int ioctl, unsigned long arg) | |
2173 | { | |
2174 | struct kvm_vcpu *vcpu = filp->private_data; | |
2175 | void __user *argp = (void __user *)arg; | |
2176 | int r; | |
b772ff36 | 2177 | struct kvm_lapic_state *lapic = NULL; |
313a3dc7 CO |
2178 | |
2179 | switch (ioctl) { | |
2180 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
2181 | r = -EINVAL; |
2182 | if (!vcpu->arch.apic) | |
2183 | goto out; | |
b772ff36 | 2184 | lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 2185 | |
b772ff36 DH |
2186 | r = -ENOMEM; |
2187 | if (!lapic) | |
2188 | goto out; | |
2189 | r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic); | |
313a3dc7 CO |
2190 | if (r) |
2191 | goto out; | |
2192 | r = -EFAULT; | |
b772ff36 | 2193 | if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
2194 | goto out; |
2195 | r = 0; | |
2196 | break; | |
2197 | } | |
2198 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
2199 | r = -EINVAL; |
2200 | if (!vcpu->arch.apic) | |
2201 | goto out; | |
b772ff36 DH |
2202 | lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
2203 | r = -ENOMEM; | |
2204 | if (!lapic) | |
2205 | goto out; | |
313a3dc7 | 2206 | r = -EFAULT; |
b772ff36 | 2207 | if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 2208 | goto out; |
b772ff36 | 2209 | r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic); |
313a3dc7 CO |
2210 | if (r) |
2211 | goto out; | |
2212 | r = 0; | |
2213 | break; | |
2214 | } | |
f77bc6a4 ZX |
2215 | case KVM_INTERRUPT: { |
2216 | struct kvm_interrupt irq; | |
2217 | ||
2218 | r = -EFAULT; | |
2219 | if (copy_from_user(&irq, argp, sizeof irq)) | |
2220 | goto out; | |
2221 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
2222 | if (r) | |
2223 | goto out; | |
2224 | r = 0; | |
2225 | break; | |
2226 | } | |
c4abb7c9 JK |
2227 | case KVM_NMI: { |
2228 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2229 | if (r) | |
2230 | goto out; | |
2231 | r = 0; | |
2232 | break; | |
2233 | } | |
313a3dc7 CO |
2234 | case KVM_SET_CPUID: { |
2235 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2236 | struct kvm_cpuid cpuid; | |
2237 | ||
2238 | r = -EFAULT; | |
2239 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2240 | goto out; | |
2241 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2242 | if (r) | |
2243 | goto out; | |
2244 | break; | |
2245 | } | |
07716717 DK |
2246 | case KVM_SET_CPUID2: { |
2247 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2248 | struct kvm_cpuid2 cpuid; | |
2249 | ||
2250 | r = -EFAULT; | |
2251 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2252 | goto out; | |
2253 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2254 | cpuid_arg->entries); |
07716717 DK |
2255 | if (r) |
2256 | goto out; | |
2257 | break; | |
2258 | } | |
2259 | case KVM_GET_CPUID2: { | |
2260 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2261 | struct kvm_cpuid2 cpuid; | |
2262 | ||
2263 | r = -EFAULT; | |
2264 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2265 | goto out; | |
2266 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2267 | cpuid_arg->entries); |
07716717 DK |
2268 | if (r) |
2269 | goto out; | |
2270 | r = -EFAULT; | |
2271 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2272 | goto out; | |
2273 | r = 0; | |
2274 | break; | |
2275 | } | |
313a3dc7 CO |
2276 | case KVM_GET_MSRS: |
2277 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2278 | break; | |
2279 | case KVM_SET_MSRS: | |
2280 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2281 | break; | |
b209749f AK |
2282 | case KVM_TPR_ACCESS_REPORTING: { |
2283 | struct kvm_tpr_access_ctl tac; | |
2284 | ||
2285 | r = -EFAULT; | |
2286 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2287 | goto out; | |
2288 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2289 | if (r) | |
2290 | goto out; | |
2291 | r = -EFAULT; | |
2292 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2293 | goto out; | |
2294 | r = 0; | |
2295 | break; | |
2296 | }; | |
b93463aa AK |
2297 | case KVM_SET_VAPIC_ADDR: { |
2298 | struct kvm_vapic_addr va; | |
2299 | ||
2300 | r = -EINVAL; | |
2301 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2302 | goto out; | |
2303 | r = -EFAULT; | |
2304 | if (copy_from_user(&va, argp, sizeof va)) | |
2305 | goto out; | |
2306 | r = 0; | |
2307 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2308 | break; | |
2309 | } | |
890ca9ae HY |
2310 | case KVM_X86_SETUP_MCE: { |
2311 | u64 mcg_cap; | |
2312 | ||
2313 | r = -EFAULT; | |
2314 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2315 | goto out; | |
2316 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2317 | break; | |
2318 | } | |
2319 | case KVM_X86_SET_MCE: { | |
2320 | struct kvm_x86_mce mce; | |
2321 | ||
2322 | r = -EFAULT; | |
2323 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2324 | goto out; | |
2325 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2326 | break; | |
2327 | } | |
3cfc3092 JK |
2328 | case KVM_GET_VCPU_EVENTS: { |
2329 | struct kvm_vcpu_events events; | |
2330 | ||
2331 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2332 | ||
2333 | r = -EFAULT; | |
2334 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2335 | break; | |
2336 | r = 0; | |
2337 | break; | |
2338 | } | |
2339 | case KVM_SET_VCPU_EVENTS: { | |
2340 | struct kvm_vcpu_events events; | |
2341 | ||
2342 | r = -EFAULT; | |
2343 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2344 | break; | |
2345 | ||
2346 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2347 | break; | |
2348 | } | |
a1efbe77 JK |
2349 | case KVM_GET_DEBUGREGS: { |
2350 | struct kvm_debugregs dbgregs; | |
2351 | ||
2352 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
2353 | ||
2354 | r = -EFAULT; | |
2355 | if (copy_to_user(argp, &dbgregs, | |
2356 | sizeof(struct kvm_debugregs))) | |
2357 | break; | |
2358 | r = 0; | |
2359 | break; | |
2360 | } | |
2361 | case KVM_SET_DEBUGREGS: { | |
2362 | struct kvm_debugregs dbgregs; | |
2363 | ||
2364 | r = -EFAULT; | |
2365 | if (copy_from_user(&dbgregs, argp, | |
2366 | sizeof(struct kvm_debugregs))) | |
2367 | break; | |
2368 | ||
2369 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
2370 | break; | |
2371 | } | |
313a3dc7 CO |
2372 | default: |
2373 | r = -EINVAL; | |
2374 | } | |
2375 | out: | |
7a6ce84c | 2376 | kfree(lapic); |
313a3dc7 CO |
2377 | return r; |
2378 | } | |
2379 | ||
1fe779f8 CO |
2380 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
2381 | { | |
2382 | int ret; | |
2383 | ||
2384 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
2385 | return -1; | |
2386 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
2387 | return ret; | |
2388 | } | |
2389 | ||
b927a3ce SY |
2390 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
2391 | u64 ident_addr) | |
2392 | { | |
2393 | kvm->arch.ept_identity_map_addr = ident_addr; | |
2394 | return 0; | |
2395 | } | |
2396 | ||
1fe779f8 CO |
2397 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
2398 | u32 kvm_nr_mmu_pages) | |
2399 | { | |
2400 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
2401 | return -EINVAL; | |
2402 | ||
79fac95e | 2403 | mutex_lock(&kvm->slots_lock); |
7c8a83b7 | 2404 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
2405 | |
2406 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 2407 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 2408 | |
7c8a83b7 | 2409 | spin_unlock(&kvm->mmu_lock); |
79fac95e | 2410 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2411 | return 0; |
2412 | } | |
2413 | ||
2414 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
2415 | { | |
f05e70ac | 2416 | return kvm->arch.n_alloc_mmu_pages; |
1fe779f8 CO |
2417 | } |
2418 | ||
a983fb23 MT |
2419 | gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn) |
2420 | { | |
2421 | int i; | |
2422 | struct kvm_mem_alias *alias; | |
2423 | struct kvm_mem_aliases *aliases; | |
2424 | ||
2425 | aliases = rcu_dereference(kvm->arch.aliases); | |
2426 | ||
2427 | for (i = 0; i < aliases->naliases; ++i) { | |
2428 | alias = &aliases->aliases[i]; | |
2429 | if (alias->flags & KVM_ALIAS_INVALID) | |
2430 | continue; | |
2431 | if (gfn >= alias->base_gfn | |
2432 | && gfn < alias->base_gfn + alias->npages) | |
2433 | return alias->target_gfn + gfn - alias->base_gfn; | |
2434 | } | |
2435 | return gfn; | |
2436 | } | |
2437 | ||
e9f85cde ZX |
2438 | gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) |
2439 | { | |
2440 | int i; | |
2441 | struct kvm_mem_alias *alias; | |
a983fb23 MT |
2442 | struct kvm_mem_aliases *aliases; |
2443 | ||
2444 | aliases = rcu_dereference(kvm->arch.aliases); | |
e9f85cde | 2445 | |
fef9cce0 MT |
2446 | for (i = 0; i < aliases->naliases; ++i) { |
2447 | alias = &aliases->aliases[i]; | |
e9f85cde ZX |
2448 | if (gfn >= alias->base_gfn |
2449 | && gfn < alias->base_gfn + alias->npages) | |
2450 | return alias->target_gfn + gfn - alias->base_gfn; | |
2451 | } | |
2452 | return gfn; | |
2453 | } | |
2454 | ||
1fe779f8 CO |
2455 | /* |
2456 | * Set a new alias region. Aliases map a portion of physical memory into | |
2457 | * another portion. This is useful for memory windows, for example the PC | |
2458 | * VGA region. | |
2459 | */ | |
2460 | static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm, | |
2461 | struct kvm_memory_alias *alias) | |
2462 | { | |
2463 | int r, n; | |
2464 | struct kvm_mem_alias *p; | |
a983fb23 | 2465 | struct kvm_mem_aliases *aliases, *old_aliases; |
1fe779f8 CO |
2466 | |
2467 | r = -EINVAL; | |
2468 | /* General sanity checks */ | |
2469 | if (alias->memory_size & (PAGE_SIZE - 1)) | |
2470 | goto out; | |
2471 | if (alias->guest_phys_addr & (PAGE_SIZE - 1)) | |
2472 | goto out; | |
2473 | if (alias->slot >= KVM_ALIAS_SLOTS) | |
2474 | goto out; | |
2475 | if (alias->guest_phys_addr + alias->memory_size | |
2476 | < alias->guest_phys_addr) | |
2477 | goto out; | |
2478 | if (alias->target_phys_addr + alias->memory_size | |
2479 | < alias->target_phys_addr) | |
2480 | goto out; | |
2481 | ||
a983fb23 MT |
2482 | r = -ENOMEM; |
2483 | aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL); | |
2484 | if (!aliases) | |
2485 | goto out; | |
2486 | ||
79fac95e | 2487 | mutex_lock(&kvm->slots_lock); |
1fe779f8 | 2488 | |
a983fb23 MT |
2489 | /* invalidate any gfn reference in case of deletion/shrinking */ |
2490 | memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases)); | |
2491 | aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID; | |
2492 | old_aliases = kvm->arch.aliases; | |
2493 | rcu_assign_pointer(kvm->arch.aliases, aliases); | |
2494 | synchronize_srcu_expedited(&kvm->srcu); | |
2495 | kvm_mmu_zap_all(kvm); | |
2496 | kfree(old_aliases); | |
2497 | ||
2498 | r = -ENOMEM; | |
2499 | aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL); | |
2500 | if (!aliases) | |
2501 | goto out_unlock; | |
2502 | ||
2503 | memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases)); | |
fef9cce0 MT |
2504 | |
2505 | p = &aliases->aliases[alias->slot]; | |
1fe779f8 CO |
2506 | p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT; |
2507 | p->npages = alias->memory_size >> PAGE_SHIFT; | |
2508 | p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT; | |
a983fb23 | 2509 | p->flags &= ~(KVM_ALIAS_INVALID); |
1fe779f8 CO |
2510 | |
2511 | for (n = KVM_ALIAS_SLOTS; n > 0; --n) | |
fef9cce0 | 2512 | if (aliases->aliases[n - 1].npages) |
1fe779f8 | 2513 | break; |
fef9cce0 | 2514 | aliases->naliases = n; |
1fe779f8 | 2515 | |
a983fb23 MT |
2516 | old_aliases = kvm->arch.aliases; |
2517 | rcu_assign_pointer(kvm->arch.aliases, aliases); | |
2518 | synchronize_srcu_expedited(&kvm->srcu); | |
2519 | kfree(old_aliases); | |
2520 | r = 0; | |
1fe779f8 | 2521 | |
a983fb23 | 2522 | out_unlock: |
79fac95e | 2523 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
2524 | out: |
2525 | return r; | |
2526 | } | |
2527 | ||
2528 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2529 | { | |
2530 | int r; | |
2531 | ||
2532 | r = 0; | |
2533 | switch (chip->chip_id) { | |
2534 | case KVM_IRQCHIP_PIC_MASTER: | |
2535 | memcpy(&chip->chip.pic, | |
2536 | &pic_irqchip(kvm)->pics[0], | |
2537 | sizeof(struct kvm_pic_state)); | |
2538 | break; | |
2539 | case KVM_IRQCHIP_PIC_SLAVE: | |
2540 | memcpy(&chip->chip.pic, | |
2541 | &pic_irqchip(kvm)->pics[1], | |
2542 | sizeof(struct kvm_pic_state)); | |
2543 | break; | |
2544 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2545 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2546 | break; |
2547 | default: | |
2548 | r = -EINVAL; | |
2549 | break; | |
2550 | } | |
2551 | return r; | |
2552 | } | |
2553 | ||
2554 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2555 | { | |
2556 | int r; | |
2557 | ||
2558 | r = 0; | |
2559 | switch (chip->chip_id) { | |
2560 | case KVM_IRQCHIP_PIC_MASTER: | |
fa8273e9 | 2561 | raw_spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2562 | memcpy(&pic_irqchip(kvm)->pics[0], |
2563 | &chip->chip.pic, | |
2564 | sizeof(struct kvm_pic_state)); | |
fa8273e9 | 2565 | raw_spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2566 | break; |
2567 | case KVM_IRQCHIP_PIC_SLAVE: | |
fa8273e9 | 2568 | raw_spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2569 | memcpy(&pic_irqchip(kvm)->pics[1], |
2570 | &chip->chip.pic, | |
2571 | sizeof(struct kvm_pic_state)); | |
fa8273e9 | 2572 | raw_spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2573 | break; |
2574 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2575 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2576 | break; |
2577 | default: | |
2578 | r = -EINVAL; | |
2579 | break; | |
2580 | } | |
2581 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
2582 | return r; | |
2583 | } | |
2584 | ||
e0f63cb9 SY |
2585 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
2586 | { | |
2587 | int r = 0; | |
2588 | ||
894a9c55 | 2589 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2590 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 2591 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2592 | return r; |
2593 | } | |
2594 | ||
2595 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
2596 | { | |
2597 | int r = 0; | |
2598 | ||
894a9c55 | 2599 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2600 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
2601 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
2602 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2603 | return r; | |
2604 | } | |
2605 | ||
2606 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2607 | { | |
2608 | int r = 0; | |
2609 | ||
2610 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2611 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
2612 | sizeof(ps->channels)); | |
2613 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
2614 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2615 | return r; | |
2616 | } | |
2617 | ||
2618 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2619 | { | |
2620 | int r = 0, start = 0; | |
2621 | u32 prev_legacy, cur_legacy; | |
2622 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2623 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2624 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2625 | if (!prev_legacy && cur_legacy) | |
2626 | start = 1; | |
2627 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
2628 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
2629 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
2630 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 2631 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2632 | return r; |
2633 | } | |
2634 | ||
52d939a0 MT |
2635 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
2636 | struct kvm_reinject_control *control) | |
2637 | { | |
2638 | if (!kvm->arch.vpit) | |
2639 | return -ENXIO; | |
894a9c55 | 2640 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 2641 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 2642 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
2643 | return 0; |
2644 | } | |
2645 | ||
5bb064dc ZX |
2646 | /* |
2647 | * Get (and clear) the dirty memory log for a memory slot. | |
2648 | */ | |
2649 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
2650 | struct kvm_dirty_log *log) | |
2651 | { | |
87bf6e7d | 2652 | int r, i; |
5bb064dc | 2653 | struct kvm_memory_slot *memslot; |
87bf6e7d | 2654 | unsigned long n; |
b050b015 MT |
2655 | unsigned long is_dirty = 0; |
2656 | unsigned long *dirty_bitmap = NULL; | |
5bb064dc | 2657 | |
79fac95e | 2658 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 2659 | |
b050b015 MT |
2660 | r = -EINVAL; |
2661 | if (log->slot >= KVM_MEMORY_SLOTS) | |
2662 | goto out; | |
2663 | ||
2664 | memslot = &kvm->memslots->memslots[log->slot]; | |
2665 | r = -ENOENT; | |
2666 | if (!memslot->dirty_bitmap) | |
2667 | goto out; | |
2668 | ||
87bf6e7d | 2669 | n = kvm_dirty_bitmap_bytes(memslot); |
b050b015 MT |
2670 | |
2671 | r = -ENOMEM; | |
2672 | dirty_bitmap = vmalloc(n); | |
2673 | if (!dirty_bitmap) | |
5bb064dc | 2674 | goto out; |
b050b015 MT |
2675 | memset(dirty_bitmap, 0, n); |
2676 | ||
2677 | for (i = 0; !is_dirty && i < n/sizeof(long); i++) | |
2678 | is_dirty = memslot->dirty_bitmap[i]; | |
5bb064dc ZX |
2679 | |
2680 | /* If nothing is dirty, don't bother messing with page tables. */ | |
2681 | if (is_dirty) { | |
b050b015 MT |
2682 | struct kvm_memslots *slots, *old_slots; |
2683 | ||
7c8a83b7 | 2684 | spin_lock(&kvm->mmu_lock); |
5bb064dc | 2685 | kvm_mmu_slot_remove_write_access(kvm, log->slot); |
7c8a83b7 | 2686 | spin_unlock(&kvm->mmu_lock); |
b050b015 MT |
2687 | |
2688 | slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL); | |
2689 | if (!slots) | |
2690 | goto out_free; | |
2691 | ||
2692 | memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots)); | |
2693 | slots->memslots[log->slot].dirty_bitmap = dirty_bitmap; | |
2694 | ||
2695 | old_slots = kvm->memslots; | |
2696 | rcu_assign_pointer(kvm->memslots, slots); | |
2697 | synchronize_srcu_expedited(&kvm->srcu); | |
2698 | dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap; | |
2699 | kfree(old_slots); | |
5bb064dc | 2700 | } |
b050b015 | 2701 | |
5bb064dc | 2702 | r = 0; |
b050b015 MT |
2703 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) |
2704 | r = -EFAULT; | |
2705 | out_free: | |
2706 | vfree(dirty_bitmap); | |
5bb064dc | 2707 | out: |
79fac95e | 2708 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
2709 | return r; |
2710 | } | |
2711 | ||
1fe779f8 CO |
2712 | long kvm_arch_vm_ioctl(struct file *filp, |
2713 | unsigned int ioctl, unsigned long arg) | |
2714 | { | |
2715 | struct kvm *kvm = filp->private_data; | |
2716 | void __user *argp = (void __user *)arg; | |
367e1319 | 2717 | int r = -ENOTTY; |
f0d66275 DH |
2718 | /* |
2719 | * This union makes it completely explicit to gcc-3.x | |
2720 | * that these two variables' stack usage should be | |
2721 | * combined, not added together. | |
2722 | */ | |
2723 | union { | |
2724 | struct kvm_pit_state ps; | |
e9f42757 | 2725 | struct kvm_pit_state2 ps2; |
f0d66275 | 2726 | struct kvm_memory_alias alias; |
c5ff41ce | 2727 | struct kvm_pit_config pit_config; |
f0d66275 | 2728 | } u; |
1fe779f8 CO |
2729 | |
2730 | switch (ioctl) { | |
2731 | case KVM_SET_TSS_ADDR: | |
2732 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
2733 | if (r < 0) | |
2734 | goto out; | |
2735 | break; | |
b927a3ce SY |
2736 | case KVM_SET_IDENTITY_MAP_ADDR: { |
2737 | u64 ident_addr; | |
2738 | ||
2739 | r = -EFAULT; | |
2740 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
2741 | goto out; | |
2742 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
2743 | if (r < 0) | |
2744 | goto out; | |
2745 | break; | |
2746 | } | |
1fe779f8 CO |
2747 | case KVM_SET_MEMORY_REGION: { |
2748 | struct kvm_memory_region kvm_mem; | |
2749 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2750 | ||
2751 | r = -EFAULT; | |
2752 | if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem)) | |
2753 | goto out; | |
2754 | kvm_userspace_mem.slot = kvm_mem.slot; | |
2755 | kvm_userspace_mem.flags = kvm_mem.flags; | |
2756 | kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr; | |
2757 | kvm_userspace_mem.memory_size = kvm_mem.memory_size; | |
2758 | r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2759 | if (r) | |
2760 | goto out; | |
2761 | break; | |
2762 | } | |
2763 | case KVM_SET_NR_MMU_PAGES: | |
2764 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
2765 | if (r) | |
2766 | goto out; | |
2767 | break; | |
2768 | case KVM_GET_NR_MMU_PAGES: | |
2769 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
2770 | break; | |
f0d66275 | 2771 | case KVM_SET_MEMORY_ALIAS: |
1fe779f8 | 2772 | r = -EFAULT; |
f0d66275 | 2773 | if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias))) |
1fe779f8 | 2774 | goto out; |
f0d66275 | 2775 | r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias); |
1fe779f8 CO |
2776 | if (r) |
2777 | goto out; | |
2778 | break; | |
3ddea128 MT |
2779 | case KVM_CREATE_IRQCHIP: { |
2780 | struct kvm_pic *vpic; | |
2781 | ||
2782 | mutex_lock(&kvm->lock); | |
2783 | r = -EEXIST; | |
2784 | if (kvm->arch.vpic) | |
2785 | goto create_irqchip_unlock; | |
1fe779f8 | 2786 | r = -ENOMEM; |
3ddea128 MT |
2787 | vpic = kvm_create_pic(kvm); |
2788 | if (vpic) { | |
1fe779f8 CO |
2789 | r = kvm_ioapic_init(kvm); |
2790 | if (r) { | |
72bb2fcd WY |
2791 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, |
2792 | &vpic->dev); | |
3ddea128 MT |
2793 | kfree(vpic); |
2794 | goto create_irqchip_unlock; | |
1fe779f8 CO |
2795 | } |
2796 | } else | |
3ddea128 MT |
2797 | goto create_irqchip_unlock; |
2798 | smp_wmb(); | |
2799 | kvm->arch.vpic = vpic; | |
2800 | smp_wmb(); | |
399ec807 AK |
2801 | r = kvm_setup_default_irq_routing(kvm); |
2802 | if (r) { | |
3ddea128 | 2803 | mutex_lock(&kvm->irq_lock); |
72bb2fcd WY |
2804 | kvm_ioapic_destroy(kvm); |
2805 | kvm_destroy_pic(kvm); | |
3ddea128 | 2806 | mutex_unlock(&kvm->irq_lock); |
399ec807 | 2807 | } |
3ddea128 MT |
2808 | create_irqchip_unlock: |
2809 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 2810 | break; |
3ddea128 | 2811 | } |
7837699f | 2812 | case KVM_CREATE_PIT: |
c5ff41ce JK |
2813 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
2814 | goto create_pit; | |
2815 | case KVM_CREATE_PIT2: | |
2816 | r = -EFAULT; | |
2817 | if (copy_from_user(&u.pit_config, argp, | |
2818 | sizeof(struct kvm_pit_config))) | |
2819 | goto out; | |
2820 | create_pit: | |
79fac95e | 2821 | mutex_lock(&kvm->slots_lock); |
269e05e4 AK |
2822 | r = -EEXIST; |
2823 | if (kvm->arch.vpit) | |
2824 | goto create_pit_unlock; | |
7837699f | 2825 | r = -ENOMEM; |
c5ff41ce | 2826 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
2827 | if (kvm->arch.vpit) |
2828 | r = 0; | |
269e05e4 | 2829 | create_pit_unlock: |
79fac95e | 2830 | mutex_unlock(&kvm->slots_lock); |
7837699f | 2831 | break; |
4925663a | 2832 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
2833 | case KVM_IRQ_LINE: { |
2834 | struct kvm_irq_level irq_event; | |
2835 | ||
2836 | r = -EFAULT; | |
2837 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
2838 | goto out; | |
160d2f6c | 2839 | r = -ENXIO; |
1fe779f8 | 2840 | if (irqchip_in_kernel(kvm)) { |
4925663a | 2841 | __s32 status; |
4925663a GN |
2842 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
2843 | irq_event.irq, irq_event.level); | |
4925663a | 2844 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
160d2f6c | 2845 | r = -EFAULT; |
4925663a GN |
2846 | irq_event.status = status; |
2847 | if (copy_to_user(argp, &irq_event, | |
2848 | sizeof irq_event)) | |
2849 | goto out; | |
2850 | } | |
1fe779f8 CO |
2851 | r = 0; |
2852 | } | |
2853 | break; | |
2854 | } | |
2855 | case KVM_GET_IRQCHIP: { | |
2856 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2857 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2858 | |
f0d66275 DH |
2859 | r = -ENOMEM; |
2860 | if (!chip) | |
1fe779f8 | 2861 | goto out; |
f0d66275 DH |
2862 | r = -EFAULT; |
2863 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2864 | goto get_irqchip_out; | |
1fe779f8 CO |
2865 | r = -ENXIO; |
2866 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2867 | goto get_irqchip_out; |
2868 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 2869 | if (r) |
f0d66275 | 2870 | goto get_irqchip_out; |
1fe779f8 | 2871 | r = -EFAULT; |
f0d66275 DH |
2872 | if (copy_to_user(argp, chip, sizeof *chip)) |
2873 | goto get_irqchip_out; | |
1fe779f8 | 2874 | r = 0; |
f0d66275 DH |
2875 | get_irqchip_out: |
2876 | kfree(chip); | |
2877 | if (r) | |
2878 | goto out; | |
1fe779f8 CO |
2879 | break; |
2880 | } | |
2881 | case KVM_SET_IRQCHIP: { | |
2882 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2883 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2884 | |
f0d66275 DH |
2885 | r = -ENOMEM; |
2886 | if (!chip) | |
1fe779f8 | 2887 | goto out; |
f0d66275 DH |
2888 | r = -EFAULT; |
2889 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2890 | goto set_irqchip_out; | |
1fe779f8 CO |
2891 | r = -ENXIO; |
2892 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2893 | goto set_irqchip_out; |
2894 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 2895 | if (r) |
f0d66275 | 2896 | goto set_irqchip_out; |
1fe779f8 | 2897 | r = 0; |
f0d66275 DH |
2898 | set_irqchip_out: |
2899 | kfree(chip); | |
2900 | if (r) | |
2901 | goto out; | |
1fe779f8 CO |
2902 | break; |
2903 | } | |
e0f63cb9 | 2904 | case KVM_GET_PIT: { |
e0f63cb9 | 2905 | r = -EFAULT; |
f0d66275 | 2906 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2907 | goto out; |
2908 | r = -ENXIO; | |
2909 | if (!kvm->arch.vpit) | |
2910 | goto out; | |
f0d66275 | 2911 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
2912 | if (r) |
2913 | goto out; | |
2914 | r = -EFAULT; | |
f0d66275 | 2915 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2916 | goto out; |
2917 | r = 0; | |
2918 | break; | |
2919 | } | |
2920 | case KVM_SET_PIT: { | |
e0f63cb9 | 2921 | r = -EFAULT; |
f0d66275 | 2922 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
2923 | goto out; |
2924 | r = -ENXIO; | |
2925 | if (!kvm->arch.vpit) | |
2926 | goto out; | |
f0d66275 | 2927 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
2928 | if (r) |
2929 | goto out; | |
2930 | r = 0; | |
2931 | break; | |
2932 | } | |
e9f42757 BK |
2933 | case KVM_GET_PIT2: { |
2934 | r = -ENXIO; | |
2935 | if (!kvm->arch.vpit) | |
2936 | goto out; | |
2937 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
2938 | if (r) | |
2939 | goto out; | |
2940 | r = -EFAULT; | |
2941 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
2942 | goto out; | |
2943 | r = 0; | |
2944 | break; | |
2945 | } | |
2946 | case KVM_SET_PIT2: { | |
2947 | r = -EFAULT; | |
2948 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
2949 | goto out; | |
2950 | r = -ENXIO; | |
2951 | if (!kvm->arch.vpit) | |
2952 | goto out; | |
2953 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
2954 | if (r) | |
2955 | goto out; | |
2956 | r = 0; | |
2957 | break; | |
2958 | } | |
52d939a0 MT |
2959 | case KVM_REINJECT_CONTROL: { |
2960 | struct kvm_reinject_control control; | |
2961 | r = -EFAULT; | |
2962 | if (copy_from_user(&control, argp, sizeof(control))) | |
2963 | goto out; | |
2964 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
2965 | if (r) | |
2966 | goto out; | |
2967 | r = 0; | |
2968 | break; | |
2969 | } | |
ffde22ac ES |
2970 | case KVM_XEN_HVM_CONFIG: { |
2971 | r = -EFAULT; | |
2972 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
2973 | sizeof(struct kvm_xen_hvm_config))) | |
2974 | goto out; | |
2975 | r = -EINVAL; | |
2976 | if (kvm->arch.xen_hvm_config.flags) | |
2977 | goto out; | |
2978 | r = 0; | |
2979 | break; | |
2980 | } | |
afbcf7ab GC |
2981 | case KVM_SET_CLOCK: { |
2982 | struct timespec now; | |
2983 | struct kvm_clock_data user_ns; | |
2984 | u64 now_ns; | |
2985 | s64 delta; | |
2986 | ||
2987 | r = -EFAULT; | |
2988 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
2989 | goto out; | |
2990 | ||
2991 | r = -EINVAL; | |
2992 | if (user_ns.flags) | |
2993 | goto out; | |
2994 | ||
2995 | r = 0; | |
2996 | ktime_get_ts(&now); | |
2997 | now_ns = timespec_to_ns(&now); | |
2998 | delta = user_ns.clock - now_ns; | |
2999 | kvm->arch.kvmclock_offset = delta; | |
3000 | break; | |
3001 | } | |
3002 | case KVM_GET_CLOCK: { | |
3003 | struct timespec now; | |
3004 | struct kvm_clock_data user_ns; | |
3005 | u64 now_ns; | |
3006 | ||
3007 | ktime_get_ts(&now); | |
3008 | now_ns = timespec_to_ns(&now); | |
3009 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; | |
3010 | user_ns.flags = 0; | |
3011 | ||
3012 | r = -EFAULT; | |
3013 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3014 | goto out; | |
3015 | r = 0; | |
3016 | break; | |
3017 | } | |
3018 | ||
1fe779f8 CO |
3019 | default: |
3020 | ; | |
3021 | } | |
3022 | out: | |
3023 | return r; | |
3024 | } | |
3025 | ||
a16b043c | 3026 | static void kvm_init_msr_list(void) |
043405e1 CO |
3027 | { |
3028 | u32 dummy[2]; | |
3029 | unsigned i, j; | |
3030 | ||
e3267cbb GC |
3031 | /* skip the first msrs in the list. KVM-specific */ |
3032 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
3033 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
3034 | continue; | |
3035 | if (j < i) | |
3036 | msrs_to_save[j] = msrs_to_save[i]; | |
3037 | j++; | |
3038 | } | |
3039 | num_msrs_to_save = j; | |
3040 | } | |
3041 | ||
bda9020e MT |
3042 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
3043 | const void *v) | |
bbd9b64e | 3044 | { |
bda9020e MT |
3045 | if (vcpu->arch.apic && |
3046 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v)) | |
3047 | return 0; | |
bbd9b64e | 3048 | |
e93f8a0f | 3049 | return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3050 | } |
3051 | ||
bda9020e | 3052 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 3053 | { |
bda9020e MT |
3054 | if (vcpu->arch.apic && |
3055 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v)) | |
3056 | return 0; | |
bbd9b64e | 3057 | |
e93f8a0f | 3058 | return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v); |
bbd9b64e CO |
3059 | } |
3060 | ||
1871c602 GN |
3061 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) |
3062 | { | |
3063 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3064 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error); | |
3065 | } | |
3066 | ||
3067 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3068 | { | |
3069 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3070 | access |= PFERR_FETCH_MASK; | |
3071 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error); | |
3072 | } | |
3073 | ||
3074 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3075 | { | |
3076 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3077 | access |= PFERR_WRITE_MASK; | |
3078 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error); | |
3079 | } | |
3080 | ||
3081 | /* uses this to access any guest's mapped memory without checking CPL */ | |
3082 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error) | |
3083 | { | |
3084 | return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error); | |
3085 | } | |
3086 | ||
3087 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3088 | struct kvm_vcpu *vcpu, u32 access, | |
3089 | u32 *error) | |
bbd9b64e CO |
3090 | { |
3091 | void *data = val; | |
10589a46 | 3092 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
3093 | |
3094 | while (bytes) { | |
1871c602 | 3095 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error); |
bbd9b64e | 3096 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 3097 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
3098 | int ret; |
3099 | ||
10589a46 MT |
3100 | if (gpa == UNMAPPED_GVA) { |
3101 | r = X86EMUL_PROPAGATE_FAULT; | |
3102 | goto out; | |
3103 | } | |
77c2002e | 3104 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 MT |
3105 | if (ret < 0) { |
3106 | r = X86EMUL_UNHANDLEABLE; | |
3107 | goto out; | |
3108 | } | |
bbd9b64e | 3109 | |
77c2002e IE |
3110 | bytes -= toread; |
3111 | data += toread; | |
3112 | addr += toread; | |
bbd9b64e | 3113 | } |
10589a46 | 3114 | out: |
10589a46 | 3115 | return r; |
bbd9b64e | 3116 | } |
77c2002e | 3117 | |
1871c602 GN |
3118 | /* used for instruction fetching */ |
3119 | static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3120 | struct kvm_vcpu *vcpu, u32 *error) | |
3121 | { | |
3122 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3123 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, | |
3124 | access | PFERR_FETCH_MASK, error); | |
3125 | } | |
3126 | ||
3127 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, | |
3128 | struct kvm_vcpu *vcpu, u32 *error) | |
3129 | { | |
3130 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3131 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, | |
3132 | error); | |
3133 | } | |
3134 | ||
3135 | static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes, | |
3136 | struct kvm_vcpu *vcpu, u32 *error) | |
3137 | { | |
3138 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error); | |
3139 | } | |
3140 | ||
cded19f3 | 3141 | static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes, |
1871c602 | 3142 | struct kvm_vcpu *vcpu, u32 *error) |
77c2002e IE |
3143 | { |
3144 | void *data = val; | |
3145 | int r = X86EMUL_CONTINUE; | |
3146 | ||
3147 | while (bytes) { | |
1871c602 | 3148 | gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error); |
77c2002e IE |
3149 | unsigned offset = addr & (PAGE_SIZE-1); |
3150 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3151 | int ret; | |
3152 | ||
3153 | if (gpa == UNMAPPED_GVA) { | |
3154 | r = X86EMUL_PROPAGATE_FAULT; | |
3155 | goto out; | |
3156 | } | |
3157 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
3158 | if (ret < 0) { | |
3159 | r = X86EMUL_UNHANDLEABLE; | |
3160 | goto out; | |
3161 | } | |
3162 | ||
3163 | bytes -= towrite; | |
3164 | data += towrite; | |
3165 | addr += towrite; | |
3166 | } | |
3167 | out: | |
3168 | return r; | |
3169 | } | |
3170 | ||
bbd9b64e | 3171 | |
bbd9b64e CO |
3172 | static int emulator_read_emulated(unsigned long addr, |
3173 | void *val, | |
3174 | unsigned int bytes, | |
3175 | struct kvm_vcpu *vcpu) | |
3176 | { | |
bbd9b64e | 3177 | gpa_t gpa; |
1871c602 | 3178 | u32 error_code; |
bbd9b64e CO |
3179 | |
3180 | if (vcpu->mmio_read_completed) { | |
3181 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
3182 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
3183 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
3184 | vcpu->mmio_read_completed = 0; |
3185 | return X86EMUL_CONTINUE; | |
3186 | } | |
3187 | ||
1871c602 GN |
3188 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code); |
3189 | ||
3190 | if (gpa == UNMAPPED_GVA) { | |
3191 | kvm_inject_page_fault(vcpu, addr, error_code); | |
3192 | return X86EMUL_PROPAGATE_FAULT; | |
3193 | } | |
bbd9b64e CO |
3194 | |
3195 | /* For APIC access vmexit */ | |
3196 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3197 | goto mmio; | |
3198 | ||
1871c602 | 3199 | if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL) |
77c2002e | 3200 | == X86EMUL_CONTINUE) |
bbd9b64e | 3201 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3202 | |
3203 | mmio: | |
3204 | /* | |
3205 | * Is this MMIO handled locally? | |
3206 | */ | |
aec51dc4 AK |
3207 | if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) { |
3208 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val); | |
bbd9b64e CO |
3209 | return X86EMUL_CONTINUE; |
3210 | } | |
aec51dc4 AK |
3211 | |
3212 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
3213 | |
3214 | vcpu->mmio_needed = 1; | |
3215 | vcpu->mmio_phys_addr = gpa; | |
3216 | vcpu->mmio_size = bytes; | |
3217 | vcpu->mmio_is_write = 0; | |
3218 | ||
3219 | return X86EMUL_UNHANDLEABLE; | |
3220 | } | |
3221 | ||
3200f405 | 3222 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 3223 | const void *val, int bytes) |
bbd9b64e CO |
3224 | { |
3225 | int ret; | |
3226 | ||
3227 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 3228 | if (ret < 0) |
bbd9b64e | 3229 | return 0; |
ad218f85 | 3230 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
3231 | return 1; |
3232 | } | |
3233 | ||
3234 | static int emulator_write_emulated_onepage(unsigned long addr, | |
3235 | const void *val, | |
3236 | unsigned int bytes, | |
3237 | struct kvm_vcpu *vcpu) | |
3238 | { | |
10589a46 | 3239 | gpa_t gpa; |
1871c602 | 3240 | u32 error_code; |
10589a46 | 3241 | |
1871c602 | 3242 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code); |
bbd9b64e CO |
3243 | |
3244 | if (gpa == UNMAPPED_GVA) { | |
1871c602 | 3245 | kvm_inject_page_fault(vcpu, addr, error_code); |
bbd9b64e CO |
3246 | return X86EMUL_PROPAGATE_FAULT; |
3247 | } | |
3248 | ||
3249 | /* For APIC access vmexit */ | |
3250 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3251 | goto mmio; | |
3252 | ||
3253 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
3254 | return X86EMUL_CONTINUE; | |
3255 | ||
3256 | mmio: | |
aec51dc4 | 3257 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
3258 | /* |
3259 | * Is this MMIO handled locally? | |
3260 | */ | |
bda9020e | 3261 | if (!vcpu_mmio_write(vcpu, gpa, bytes, val)) |
bbd9b64e | 3262 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
3263 | |
3264 | vcpu->mmio_needed = 1; | |
3265 | vcpu->mmio_phys_addr = gpa; | |
3266 | vcpu->mmio_size = bytes; | |
3267 | vcpu->mmio_is_write = 1; | |
3268 | memcpy(vcpu->mmio_data, val, bytes); | |
3269 | ||
3270 | return X86EMUL_CONTINUE; | |
3271 | } | |
3272 | ||
3273 | int emulator_write_emulated(unsigned long addr, | |
3274 | const void *val, | |
3275 | unsigned int bytes, | |
3276 | struct kvm_vcpu *vcpu) | |
3277 | { | |
3278 | /* Crossing a page boundary? */ | |
3279 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
3280 | int rc, now; | |
3281 | ||
3282 | now = -addr & ~PAGE_MASK; | |
3283 | rc = emulator_write_emulated_onepage(addr, val, now, vcpu); | |
3284 | if (rc != X86EMUL_CONTINUE) | |
3285 | return rc; | |
3286 | addr += now; | |
3287 | val += now; | |
3288 | bytes -= now; | |
3289 | } | |
3290 | return emulator_write_emulated_onepage(addr, val, bytes, vcpu); | |
3291 | } | |
3292 | EXPORT_SYMBOL_GPL(emulator_write_emulated); | |
3293 | ||
daea3e73 AK |
3294 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
3295 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
3296 | ||
3297 | #ifdef CONFIG_X86_64 | |
3298 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
3299 | #else | |
3300 | # define CMPXCHG64(ptr, old, new) \ | |
3301 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u *)(new)) == *(u64 *)(old)) | |
3302 | #endif | |
3303 | ||
bbd9b64e CO |
3304 | static int emulator_cmpxchg_emulated(unsigned long addr, |
3305 | const void *old, | |
3306 | const void *new, | |
3307 | unsigned int bytes, | |
3308 | struct kvm_vcpu *vcpu) | |
3309 | { | |
daea3e73 AK |
3310 | gpa_t gpa; |
3311 | struct page *page; | |
3312 | char *kaddr; | |
3313 | bool exchanged; | |
2bacc55c | 3314 | |
daea3e73 AK |
3315 | /* guests cmpxchg8b have to be emulated atomically */ |
3316 | if (bytes > 8 || (bytes & (bytes - 1))) | |
3317 | goto emul_write; | |
10589a46 | 3318 | |
daea3e73 | 3319 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 3320 | |
daea3e73 AK |
3321 | if (gpa == UNMAPPED_GVA || |
3322 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
3323 | goto emul_write; | |
2bacc55c | 3324 | |
daea3e73 AK |
3325 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
3326 | goto emul_write; | |
72dc67a6 | 3327 | |
daea3e73 | 3328 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 | 3329 | |
daea3e73 AK |
3330 | kaddr = kmap_atomic(page, KM_USER0); |
3331 | kaddr += offset_in_page(gpa); | |
3332 | switch (bytes) { | |
3333 | case 1: | |
3334 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
3335 | break; | |
3336 | case 2: | |
3337 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
3338 | break; | |
3339 | case 4: | |
3340 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
3341 | break; | |
3342 | case 8: | |
3343 | exchanged = CMPXCHG64(kaddr, old, new); | |
3344 | break; | |
3345 | default: | |
3346 | BUG(); | |
2bacc55c | 3347 | } |
daea3e73 AK |
3348 | kunmap_atomic(kaddr, KM_USER0); |
3349 | kvm_release_page_dirty(page); | |
3350 | ||
3351 | if (!exchanged) | |
3352 | return X86EMUL_CMPXCHG_FAILED; | |
3353 | ||
3200f405 | 3354 | emul_write: |
daea3e73 | 3355 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 3356 | |
bbd9b64e CO |
3357 | return emulator_write_emulated(addr, new, bytes, vcpu); |
3358 | } | |
3359 | ||
3360 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
3361 | { | |
3362 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
3363 | } | |
3364 | ||
3365 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
3366 | { | |
a7052897 | 3367 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
3368 | return X86EMUL_CONTINUE; |
3369 | } | |
3370 | ||
3371 | int emulate_clts(struct kvm_vcpu *vcpu) | |
3372 | { | |
4d4ec087 | 3373 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
6b52d186 | 3374 | kvm_x86_ops->fpu_activate(vcpu); |
bbd9b64e CO |
3375 | return X86EMUL_CONTINUE; |
3376 | } | |
3377 | ||
3378 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) | |
3379 | { | |
c76de350 | 3380 | return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest); |
bbd9b64e CO |
3381 | } |
3382 | ||
3383 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) | |
3384 | { | |
3385 | unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U; | |
bbd9b64e | 3386 | |
c76de350 | 3387 | return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask); |
bbd9b64e CO |
3388 | } |
3389 | ||
3390 | void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) | |
3391 | { | |
bbd9b64e | 3392 | u8 opcodes[4]; |
5fdbf976 | 3393 | unsigned long rip = kvm_rip_read(vcpu); |
bbd9b64e CO |
3394 | unsigned long rip_linear; |
3395 | ||
f76c710d | 3396 | if (!printk_ratelimit()) |
bbd9b64e CO |
3397 | return; |
3398 | ||
25be4608 GC |
3399 | rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS); |
3400 | ||
1871c602 | 3401 | kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL); |
bbd9b64e CO |
3402 | |
3403 | printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n", | |
3404 | context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]); | |
bbd9b64e CO |
3405 | } |
3406 | EXPORT_SYMBOL_GPL(kvm_report_emulation_failure); | |
3407 | ||
14af3f3c | 3408 | static struct x86_emulate_ops emulate_ops = { |
1871c602 GN |
3409 | .read_std = kvm_read_guest_virt_system, |
3410 | .fetch = kvm_fetch_guest_virt, | |
bbd9b64e CO |
3411 | .read_emulated = emulator_read_emulated, |
3412 | .write_emulated = emulator_write_emulated, | |
3413 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3414 | }; | |
3415 | ||
5fdbf976 MT |
3416 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
3417 | { | |
3418 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3419 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3420 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
3421 | vcpu->arch.regs_dirty = ~0; | |
3422 | } | |
3423 | ||
bbd9b64e | 3424 | int emulate_instruction(struct kvm_vcpu *vcpu, |
bbd9b64e CO |
3425 | unsigned long cr2, |
3426 | u16 error_code, | |
571008da | 3427 | int emulation_type) |
bbd9b64e | 3428 | { |
310b5d30 | 3429 | int r, shadow_mask; |
571008da | 3430 | struct decode_cache *c; |
851ba692 | 3431 | struct kvm_run *run = vcpu->run; |
bbd9b64e | 3432 | |
26eef70c | 3433 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 3434 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 3435 | /* |
56e82318 | 3436 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
3437 | * instead of direct ->regs accesses, can save hundred cycles |
3438 | * on Intel for instructions that don't read/change RSP, for | |
3439 | * for example. | |
3440 | */ | |
3441 | cache_all_regs(vcpu); | |
bbd9b64e CO |
3442 | |
3443 | vcpu->mmio_is_write = 0; | |
ad312c7c | 3444 | vcpu->arch.pio.string = 0; |
bbd9b64e | 3445 | |
571008da | 3446 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
bbd9b64e CO |
3447 | int cs_db, cs_l; |
3448 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
3449 | ||
ad312c7c | 3450 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
83bf0002 | 3451 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); |
ad312c7c | 3452 | vcpu->arch.emulate_ctxt.mode = |
a0044755 | 3453 | (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : |
ad312c7c | 3454 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) |
a0044755 | 3455 | ? X86EMUL_MODE_VM86 : cs_l |
bbd9b64e CO |
3456 | ? X86EMUL_MODE_PROT64 : cs_db |
3457 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
3458 | ||
ad312c7c | 3459 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
571008da | 3460 | |
0cb5762e AP |
3461 | /* Only allow emulation of specific instructions on #UD |
3462 | * (namely VMMCALL, sysenter, sysexit, syscall)*/ | |
571008da | 3463 | c = &vcpu->arch.emulate_ctxt.decode; |
0cb5762e AP |
3464 | if (emulation_type & EMULTYPE_TRAP_UD) { |
3465 | if (!c->twobyte) | |
3466 | return EMULATE_FAIL; | |
3467 | switch (c->b) { | |
3468 | case 0x01: /* VMMCALL */ | |
3469 | if (c->modrm_mod != 3 || c->modrm_rm != 1) | |
3470 | return EMULATE_FAIL; | |
3471 | break; | |
3472 | case 0x34: /* sysenter */ | |
3473 | case 0x35: /* sysexit */ | |
3474 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
3475 | return EMULATE_FAIL; | |
3476 | break; | |
3477 | case 0x05: /* syscall */ | |
3478 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
3479 | return EMULATE_FAIL; | |
3480 | break; | |
3481 | default: | |
3482 | return EMULATE_FAIL; | |
3483 | } | |
3484 | ||
3485 | if (!(c->modrm_reg == 0 || c->modrm_reg == 3)) | |
3486 | return EMULATE_FAIL; | |
3487 | } | |
571008da | 3488 | |
f2b5756b | 3489 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 3490 | if (r) { |
f2b5756b | 3491 | ++vcpu->stat.insn_emulation_fail; |
bbd9b64e CO |
3492 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) |
3493 | return EMULATE_DONE; | |
3494 | return EMULATE_FAIL; | |
3495 | } | |
3496 | } | |
3497 | ||
ba8afb6b GN |
3498 | if (emulation_type & EMULTYPE_SKIP) { |
3499 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
3500 | return EMULATE_DONE; | |
3501 | } | |
3502 | ||
ad312c7c | 3503 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
310b5d30 GC |
3504 | shadow_mask = vcpu->arch.emulate_ctxt.interruptibility; |
3505 | ||
3506 | if (r == 0) | |
3507 | kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask); | |
bbd9b64e | 3508 | |
ad312c7c | 3509 | if (vcpu->arch.pio.string) |
bbd9b64e CO |
3510 | return EMULATE_DO_MMIO; |
3511 | ||
112592da | 3512 | if (r || vcpu->mmio_is_write) { |
bbd9b64e CO |
3513 | run->exit_reason = KVM_EXIT_MMIO; |
3514 | run->mmio.phys_addr = vcpu->mmio_phys_addr; | |
3515 | memcpy(run->mmio.data, vcpu->mmio_data, 8); | |
3516 | run->mmio.len = vcpu->mmio_size; | |
3517 | run->mmio.is_write = vcpu->mmio_is_write; | |
3518 | } | |
3519 | ||
3520 | if (r) { | |
3521 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) | |
3522 | return EMULATE_DONE; | |
3523 | if (!vcpu->mmio_needed) { | |
3524 | kvm_report_emulation_failure(vcpu, "mmio"); | |
3525 | return EMULATE_FAIL; | |
3526 | } | |
3527 | return EMULATE_DO_MMIO; | |
3528 | } | |
3529 | ||
83bf0002 | 3530 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
bbd9b64e CO |
3531 | |
3532 | if (vcpu->mmio_is_write) { | |
3533 | vcpu->mmio_needed = 0; | |
3534 | return EMULATE_DO_MMIO; | |
3535 | } | |
3536 | ||
3537 | return EMULATE_DONE; | |
3538 | } | |
3539 | EXPORT_SYMBOL_GPL(emulate_instruction); | |
3540 | ||
de7d789a CO |
3541 | static int pio_copy_data(struct kvm_vcpu *vcpu) |
3542 | { | |
ad312c7c | 3543 | void *p = vcpu->arch.pio_data; |
0f346074 | 3544 | gva_t q = vcpu->arch.pio.guest_gva; |
de7d789a | 3545 | unsigned bytes; |
0f346074 | 3546 | int ret; |
1871c602 | 3547 | u32 error_code; |
de7d789a | 3548 | |
ad312c7c ZX |
3549 | bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count; |
3550 | if (vcpu->arch.pio.in) | |
1871c602 | 3551 | ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code); |
de7d789a | 3552 | else |
1871c602 GN |
3553 | ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code); |
3554 | ||
3555 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
3556 | kvm_inject_page_fault(vcpu, q, error_code); | |
3557 | ||
0f346074 | 3558 | return ret; |
de7d789a CO |
3559 | } |
3560 | ||
3561 | int complete_pio(struct kvm_vcpu *vcpu) | |
3562 | { | |
ad312c7c | 3563 | struct kvm_pio_request *io = &vcpu->arch.pio; |
de7d789a CO |
3564 | long delta; |
3565 | int r; | |
5fdbf976 | 3566 | unsigned long val; |
de7d789a CO |
3567 | |
3568 | if (!io->string) { | |
5fdbf976 MT |
3569 | if (io->in) { |
3570 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3571 | memcpy(&val, vcpu->arch.pio_data, io->size); | |
3572 | kvm_register_write(vcpu, VCPU_REGS_RAX, val); | |
3573 | } | |
de7d789a CO |
3574 | } else { |
3575 | if (io->in) { | |
3576 | r = pio_copy_data(vcpu); | |
5fdbf976 | 3577 | if (r) |
1871c602 | 3578 | goto out; |
de7d789a CO |
3579 | } |
3580 | ||
3581 | delta = 1; | |
3582 | if (io->rep) { | |
3583 | delta *= io->cur_count; | |
3584 | /* | |
3585 | * The size of the register should really depend on | |
3586 | * current address size. | |
3587 | */ | |
5fdbf976 MT |
3588 | val = kvm_register_read(vcpu, VCPU_REGS_RCX); |
3589 | val -= delta; | |
3590 | kvm_register_write(vcpu, VCPU_REGS_RCX, val); | |
de7d789a CO |
3591 | } |
3592 | if (io->down) | |
3593 | delta = -delta; | |
3594 | delta *= io->size; | |
5fdbf976 MT |
3595 | if (io->in) { |
3596 | val = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
3597 | val += delta; | |
3598 | kvm_register_write(vcpu, VCPU_REGS_RDI, val); | |
3599 | } else { | |
3600 | val = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3601 | val += delta; | |
3602 | kvm_register_write(vcpu, VCPU_REGS_RSI, val); | |
3603 | } | |
de7d789a | 3604 | } |
1871c602 | 3605 | out: |
de7d789a CO |
3606 | io->count -= io->cur_count; |
3607 | io->cur_count = 0; | |
3608 | ||
3609 | return 0; | |
3610 | } | |
3611 | ||
bda9020e | 3612 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
de7d789a CO |
3613 | { |
3614 | /* TODO: String I/O for in kernel device */ | |
bda9020e | 3615 | int r; |
de7d789a | 3616 | |
ad312c7c | 3617 | if (vcpu->arch.pio.in) |
e93f8a0f | 3618 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, |
bda9020e | 3619 | vcpu->arch.pio.size, pd); |
de7d789a | 3620 | else |
e93f8a0f MT |
3621 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, |
3622 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
3623 | pd); | |
bda9020e | 3624 | return r; |
de7d789a CO |
3625 | } |
3626 | ||
bda9020e | 3627 | static int pio_string_write(struct kvm_vcpu *vcpu) |
de7d789a | 3628 | { |
ad312c7c ZX |
3629 | struct kvm_pio_request *io = &vcpu->arch.pio; |
3630 | void *pd = vcpu->arch.pio_data; | |
bda9020e | 3631 | int i, r = 0; |
de7d789a | 3632 | |
de7d789a | 3633 | for (i = 0; i < io->cur_count; i++) { |
e93f8a0f | 3634 | if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, |
bda9020e MT |
3635 | io->port, io->size, pd)) { |
3636 | r = -EOPNOTSUPP; | |
3637 | break; | |
3638 | } | |
de7d789a CO |
3639 | pd += io->size; |
3640 | } | |
bda9020e | 3641 | return r; |
de7d789a CO |
3642 | } |
3643 | ||
851ba692 | 3644 | int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port) |
de7d789a | 3645 | { |
5fdbf976 | 3646 | unsigned long val; |
de7d789a | 3647 | |
f850e2e6 GN |
3648 | trace_kvm_pio(!in, port, size, 1); |
3649 | ||
de7d789a CO |
3650 | vcpu->run->exit_reason = KVM_EXIT_IO; |
3651 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 3652 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 3653 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
3654 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1; |
3655 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
3656 | vcpu->arch.pio.in = in; | |
3657 | vcpu->arch.pio.string = 0; | |
3658 | vcpu->arch.pio.down = 0; | |
ad312c7c | 3659 | vcpu->arch.pio.rep = 0; |
de7d789a | 3660 | |
1976d2d2 TY |
3661 | if (!vcpu->arch.pio.in) { |
3662 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3663 | memcpy(vcpu->arch.pio_data, &val, 4); | |
3664 | } | |
de7d789a | 3665 | |
bda9020e | 3666 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { |
de7d789a CO |
3667 | complete_pio(vcpu); |
3668 | return 1; | |
3669 | } | |
3670 | return 0; | |
3671 | } | |
3672 | EXPORT_SYMBOL_GPL(kvm_emulate_pio); | |
3673 | ||
851ba692 | 3674 | int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in, |
de7d789a CO |
3675 | int size, unsigned long count, int down, |
3676 | gva_t address, int rep, unsigned port) | |
3677 | { | |
3678 | unsigned now, in_page; | |
0f346074 | 3679 | int ret = 0; |
de7d789a | 3680 | |
f850e2e6 GN |
3681 | trace_kvm_pio(!in, port, size, count); |
3682 | ||
de7d789a CO |
3683 | vcpu->run->exit_reason = KVM_EXIT_IO; |
3684 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 3685 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 3686 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
3687 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count; |
3688 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
3689 | vcpu->arch.pio.in = in; | |
3690 | vcpu->arch.pio.string = 1; | |
3691 | vcpu->arch.pio.down = down; | |
ad312c7c | 3692 | vcpu->arch.pio.rep = rep; |
de7d789a CO |
3693 | |
3694 | if (!count) { | |
3695 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
3696 | return 1; | |
3697 | } | |
3698 | ||
3699 | if (!down) | |
3700 | in_page = PAGE_SIZE - offset_in_page(address); | |
3701 | else | |
3702 | in_page = offset_in_page(address) + size; | |
3703 | now = min(count, (unsigned long)in_page / size); | |
0f346074 | 3704 | if (!now) |
de7d789a | 3705 | now = 1; |
de7d789a CO |
3706 | if (down) { |
3707 | /* | |
3708 | * String I/O in reverse. Yuck. Kill the guest, fix later. | |
3709 | */ | |
3710 | pr_unimpl(vcpu, "guest string pio down\n"); | |
c1a5d4f9 | 3711 | kvm_inject_gp(vcpu, 0); |
de7d789a CO |
3712 | return 1; |
3713 | } | |
3714 | vcpu->run->io.count = now; | |
ad312c7c | 3715 | vcpu->arch.pio.cur_count = now; |
de7d789a | 3716 | |
ad312c7c | 3717 | if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count) |
de7d789a CO |
3718 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
3719 | ||
0f346074 | 3720 | vcpu->arch.pio.guest_gva = address; |
de7d789a | 3721 | |
ad312c7c | 3722 | if (!vcpu->arch.pio.in) { |
de7d789a CO |
3723 | /* string PIO write */ |
3724 | ret = pio_copy_data(vcpu); | |
1871c602 | 3725 | if (ret == X86EMUL_PROPAGATE_FAULT) |
0f346074 | 3726 | return 1; |
bda9020e | 3727 | if (ret == 0 && !pio_string_write(vcpu)) { |
de7d789a | 3728 | complete_pio(vcpu); |
ad312c7c | 3729 | if (vcpu->arch.pio.count == 0) |
de7d789a CO |
3730 | ret = 1; |
3731 | } | |
bda9020e MT |
3732 | } |
3733 | /* no string PIO read support yet */ | |
de7d789a CO |
3734 | |
3735 | return ret; | |
3736 | } | |
3737 | EXPORT_SYMBOL_GPL(kvm_emulate_pio_string); | |
3738 | ||
c8076604 GH |
3739 | static void bounce_off(void *info) |
3740 | { | |
3741 | /* nothing */ | |
3742 | } | |
3743 | ||
c8076604 GH |
3744 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
3745 | void *data) | |
3746 | { | |
3747 | struct cpufreq_freqs *freq = data; | |
3748 | struct kvm *kvm; | |
3749 | struct kvm_vcpu *vcpu; | |
3750 | int i, send_ipi = 0; | |
3751 | ||
c8076604 GH |
3752 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
3753 | return 0; | |
3754 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
3755 | return 0; | |
0cca7907 | 3756 | per_cpu(cpu_tsc_khz, freq->cpu) = freq->new; |
c8076604 GH |
3757 | |
3758 | spin_lock(&kvm_lock); | |
3759 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
988a2cae | 3760 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
3761 | if (vcpu->cpu != freq->cpu) |
3762 | continue; | |
3763 | if (!kvm_request_guest_time_update(vcpu)) | |
3764 | continue; | |
3765 | if (vcpu->cpu != smp_processor_id()) | |
3766 | send_ipi++; | |
3767 | } | |
3768 | } | |
3769 | spin_unlock(&kvm_lock); | |
3770 | ||
3771 | if (freq->old < freq->new && send_ipi) { | |
3772 | /* | |
3773 | * We upscale the frequency. Must make the guest | |
3774 | * doesn't see old kvmclock values while running with | |
3775 | * the new frequency, otherwise we risk the guest sees | |
3776 | * time go backwards. | |
3777 | * | |
3778 | * In case we update the frequency for another cpu | |
3779 | * (which might be in guest context) send an interrupt | |
3780 | * to kick the cpu out of guest context. Next time | |
3781 | * guest context is entered kvmclock will be updated, | |
3782 | * so the guest will not see stale values. | |
3783 | */ | |
3784 | smp_call_function_single(freq->cpu, bounce_off, NULL, 1); | |
3785 | } | |
3786 | return 0; | |
3787 | } | |
3788 | ||
3789 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
3790 | .notifier_call = kvmclock_cpufreq_notifier | |
3791 | }; | |
3792 | ||
b820cc0c ZA |
3793 | static void kvm_timer_init(void) |
3794 | { | |
3795 | int cpu; | |
3796 | ||
b820cc0c | 3797 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
b820cc0c ZA |
3798 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
3799 | CPUFREQ_TRANSITION_NOTIFIER); | |
6b7d7e76 ZA |
3800 | for_each_online_cpu(cpu) { |
3801 | unsigned long khz = cpufreq_get(cpu); | |
3802 | if (!khz) | |
3803 | khz = tsc_khz; | |
3804 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
3805 | } | |
0cca7907 ZA |
3806 | } else { |
3807 | for_each_possible_cpu(cpu) | |
3808 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
b820cc0c ZA |
3809 | } |
3810 | } | |
3811 | ||
f8c16bba | 3812 | int kvm_arch_init(void *opaque) |
043405e1 | 3813 | { |
b820cc0c | 3814 | int r; |
f8c16bba ZX |
3815 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
3816 | ||
f8c16bba ZX |
3817 | if (kvm_x86_ops) { |
3818 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
3819 | r = -EEXIST; |
3820 | goto out; | |
f8c16bba ZX |
3821 | } |
3822 | ||
3823 | if (!ops->cpu_has_kvm_support()) { | |
3824 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
3825 | r = -EOPNOTSUPP; |
3826 | goto out; | |
f8c16bba ZX |
3827 | } |
3828 | if (ops->disabled_by_bios()) { | |
3829 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
3830 | r = -EOPNOTSUPP; |
3831 | goto out; | |
f8c16bba ZX |
3832 | } |
3833 | ||
97db56ce AK |
3834 | r = kvm_mmu_module_init(); |
3835 | if (r) | |
3836 | goto out; | |
3837 | ||
3838 | kvm_init_msr_list(); | |
3839 | ||
f8c16bba | 3840 | kvm_x86_ops = ops; |
56c6d28a | 3841 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e SY |
3842 | kvm_mmu_set_base_ptes(PT_PRESENT_MASK); |
3843 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
4b12f0de | 3844 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 3845 | |
b820cc0c | 3846 | kvm_timer_init(); |
c8076604 | 3847 | |
f8c16bba | 3848 | return 0; |
56c6d28a ZX |
3849 | |
3850 | out: | |
56c6d28a | 3851 | return r; |
043405e1 | 3852 | } |
8776e519 | 3853 | |
f8c16bba ZX |
3854 | void kvm_arch_exit(void) |
3855 | { | |
888d256e JK |
3856 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
3857 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
3858 | CPUFREQ_TRANSITION_NOTIFIER); | |
f8c16bba | 3859 | kvm_x86_ops = NULL; |
56c6d28a ZX |
3860 | kvm_mmu_module_exit(); |
3861 | } | |
f8c16bba | 3862 | |
8776e519 HB |
3863 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
3864 | { | |
3865 | ++vcpu->stat.halt_exits; | |
3866 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 3867 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
3868 | return 1; |
3869 | } else { | |
3870 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
3871 | return 0; | |
3872 | } | |
3873 | } | |
3874 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
3875 | ||
2f333bcb MT |
3876 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
3877 | unsigned long a1) | |
3878 | { | |
3879 | if (is_long_mode(vcpu)) | |
3880 | return a0; | |
3881 | else | |
3882 | return a0 | ((gpa_t)a1 << 32); | |
3883 | } | |
3884 | ||
55cd8e5a GN |
3885 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) |
3886 | { | |
3887 | u64 param, ingpa, outgpa, ret; | |
3888 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
3889 | bool fast, longmode; | |
3890 | int cs_db, cs_l; | |
3891 | ||
3892 | /* | |
3893 | * hypercall generates UD from non zero cpl and real mode | |
3894 | * per HYPER-V spec | |
3895 | */ | |
3eeb3288 | 3896 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { |
55cd8e5a GN |
3897 | kvm_queue_exception(vcpu, UD_VECTOR); |
3898 | return 0; | |
3899 | } | |
3900 | ||
3901 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
3902 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
3903 | ||
3904 | if (!longmode) { | |
ccd46936 GN |
3905 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | |
3906 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
3907 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
3908 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
3909 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
3910 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
55cd8e5a GN |
3911 | } |
3912 | #ifdef CONFIG_X86_64 | |
3913 | else { | |
3914 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3915 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3916 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
3917 | } | |
3918 | #endif | |
3919 | ||
3920 | code = param & 0xffff; | |
3921 | fast = (param >> 16) & 0x1; | |
3922 | rep_cnt = (param >> 32) & 0xfff; | |
3923 | rep_idx = (param >> 48) & 0xfff; | |
3924 | ||
3925 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
3926 | ||
c25bc163 GN |
3927 | switch (code) { |
3928 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
3929 | kvm_vcpu_on_spin(vcpu); | |
3930 | break; | |
3931 | default: | |
3932 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
3933 | break; | |
3934 | } | |
55cd8e5a GN |
3935 | |
3936 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
3937 | if (longmode) { | |
3938 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
3939 | } else { | |
3940 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
3941 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
3942 | } | |
3943 | ||
3944 | return 1; | |
3945 | } | |
3946 | ||
8776e519 HB |
3947 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
3948 | { | |
3949 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 3950 | int r = 1; |
8776e519 | 3951 | |
55cd8e5a GN |
3952 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
3953 | return kvm_hv_hypercall(vcpu); | |
3954 | ||
5fdbf976 MT |
3955 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3956 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3957 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3958 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3959 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 3960 | |
229456fc | 3961 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 3962 | |
8776e519 HB |
3963 | if (!is_long_mode(vcpu)) { |
3964 | nr &= 0xFFFFFFFF; | |
3965 | a0 &= 0xFFFFFFFF; | |
3966 | a1 &= 0xFFFFFFFF; | |
3967 | a2 &= 0xFFFFFFFF; | |
3968 | a3 &= 0xFFFFFFFF; | |
3969 | } | |
3970 | ||
07708c4a JK |
3971 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
3972 | ret = -KVM_EPERM; | |
3973 | goto out; | |
3974 | } | |
3975 | ||
8776e519 | 3976 | switch (nr) { |
b93463aa AK |
3977 | case KVM_HC_VAPIC_POLL_IRQ: |
3978 | ret = 0; | |
3979 | break; | |
2f333bcb MT |
3980 | case KVM_HC_MMU_OP: |
3981 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
3982 | break; | |
8776e519 HB |
3983 | default: |
3984 | ret = -KVM_ENOSYS; | |
3985 | break; | |
3986 | } | |
07708c4a | 3987 | out: |
5fdbf976 | 3988 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 3989 | ++vcpu->stat.hypercalls; |
2f333bcb | 3990 | return r; |
8776e519 HB |
3991 | } |
3992 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
3993 | ||
3994 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
3995 | { | |
3996 | char instruction[3]; | |
5fdbf976 | 3997 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 3998 | |
8776e519 HB |
3999 | /* |
4000 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
4001 | * to ensure that the updated hypercall appears atomically across all | |
4002 | * VCPUs. | |
4003 | */ | |
4004 | kvm_mmu_zap_all(vcpu->kvm); | |
4005 | ||
8776e519 | 4006 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 4007 | |
7edcface | 4008 | return emulator_write_emulated(rip, instruction, 3, vcpu); |
8776e519 HB |
4009 | } |
4010 | ||
4011 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) | |
4012 | { | |
4013 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; | |
4014 | } | |
4015 | ||
4016 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
4017 | { | |
89a27f4d | 4018 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4019 | |
4020 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4021 | } | |
4022 | ||
4023 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
4024 | { | |
89a27f4d | 4025 | struct desc_ptr dt = { limit, base }; |
8776e519 HB |
4026 | |
4027 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4028 | } | |
4029 | ||
4030 | void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, | |
4031 | unsigned long *rflags) | |
4032 | { | |
2d3ad1f4 | 4033 | kvm_lmsw(vcpu, msw); |
91586a3b | 4034 | *rflags = kvm_get_rflags(vcpu); |
8776e519 HB |
4035 | } |
4036 | ||
4037 | unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr) | |
4038 | { | |
54e445ca JR |
4039 | unsigned long value; |
4040 | ||
8776e519 HB |
4041 | switch (cr) { |
4042 | case 0: | |
4d4ec087 | 4043 | value = kvm_read_cr0(vcpu); |
54e445ca | 4044 | break; |
8776e519 | 4045 | case 2: |
54e445ca JR |
4046 | value = vcpu->arch.cr2; |
4047 | break; | |
8776e519 | 4048 | case 3: |
54e445ca JR |
4049 | value = vcpu->arch.cr3; |
4050 | break; | |
8776e519 | 4051 | case 4: |
fc78f519 | 4052 | value = kvm_read_cr4(vcpu); |
54e445ca | 4053 | break; |
152ff9be | 4054 | case 8: |
54e445ca JR |
4055 | value = kvm_get_cr8(vcpu); |
4056 | break; | |
8776e519 | 4057 | default: |
b8688d51 | 4058 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
4059 | return 0; |
4060 | } | |
54e445ca JR |
4061 | |
4062 | return value; | |
8776e519 HB |
4063 | } |
4064 | ||
4065 | void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val, | |
4066 | unsigned long *rflags) | |
4067 | { | |
4068 | switch (cr) { | |
4069 | case 0: | |
4d4ec087 | 4070 | kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
91586a3b | 4071 | *rflags = kvm_get_rflags(vcpu); |
8776e519 HB |
4072 | break; |
4073 | case 2: | |
ad312c7c | 4074 | vcpu->arch.cr2 = val; |
8776e519 HB |
4075 | break; |
4076 | case 3: | |
2d3ad1f4 | 4077 | kvm_set_cr3(vcpu, val); |
8776e519 HB |
4078 | break; |
4079 | case 4: | |
fc78f519 | 4080 | kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
8776e519 | 4081 | break; |
152ff9be | 4082 | case 8: |
2d3ad1f4 | 4083 | kvm_set_cr8(vcpu, val & 0xfUL); |
152ff9be | 4084 | break; |
8776e519 | 4085 | default: |
b8688d51 | 4086 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
4087 | } |
4088 | } | |
4089 | ||
07716717 DK |
4090 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
4091 | { | |
ad312c7c ZX |
4092 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
4093 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
4094 | |
4095 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4096 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 4097 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 4098 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
4099 | if (ej->function == e->function) { |
4100 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
4101 | return j; | |
4102 | } | |
4103 | } | |
4104 | return 0; /* silence gcc, even though control never reaches here */ | |
4105 | } | |
4106 | ||
4107 | /* find an entry with matching function, matching index (if needed), and that | |
4108 | * should be read next (if it's stateful) */ | |
4109 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
4110 | u32 function, u32 index) | |
4111 | { | |
4112 | if (e->function != function) | |
4113 | return 0; | |
4114 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
4115 | return 0; | |
4116 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 4117 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
4118 | return 0; |
4119 | return 1; | |
4120 | } | |
4121 | ||
d8017474 AG |
4122 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
4123 | u32 function, u32 index) | |
8776e519 HB |
4124 | { |
4125 | int i; | |
d8017474 | 4126 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 4127 | |
ad312c7c | 4128 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
4129 | struct kvm_cpuid_entry2 *e; |
4130 | ||
ad312c7c | 4131 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
4132 | if (is_matching_cpuid_entry(e, function, index)) { |
4133 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
4134 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
4135 | best = e; |
4136 | break; | |
4137 | } | |
4138 | /* | |
4139 | * Both basic or both extended? | |
4140 | */ | |
4141 | if (((e->function ^ function) & 0x80000000) == 0) | |
4142 | if (!best || e->function > best->function) | |
4143 | best = e; | |
4144 | } | |
d8017474 AG |
4145 | return best; |
4146 | } | |
0e851880 | 4147 | EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); |
d8017474 | 4148 | |
82725b20 DE |
4149 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
4150 | { | |
4151 | struct kvm_cpuid_entry2 *best; | |
4152 | ||
4153 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
4154 | if (best) | |
4155 | return best->eax & 0xff; | |
4156 | return 36; | |
4157 | } | |
4158 | ||
d8017474 AG |
4159 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
4160 | { | |
4161 | u32 function, index; | |
4162 | struct kvm_cpuid_entry2 *best; | |
4163 | ||
4164 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
4165 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4166 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
4167 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
4168 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
4169 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
4170 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 4171 | if (best) { |
5fdbf976 MT |
4172 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
4173 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
4174 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
4175 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 4176 | } |
8776e519 | 4177 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
4178 | trace_kvm_cpuid(function, |
4179 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
4180 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
4181 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
4182 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
4183 | } |
4184 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 4185 | |
b6c7a5dc HB |
4186 | /* |
4187 | * Check if userspace requested an interrupt window, and that the | |
4188 | * interrupt window is open. | |
4189 | * | |
4190 | * No need to exit to userspace if we already have an interrupt queued. | |
4191 | */ | |
851ba692 | 4192 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4193 | { |
8061823a | 4194 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 4195 | vcpu->run->request_interrupt_window && |
5df56646 | 4196 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
4197 | } |
4198 | ||
851ba692 | 4199 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 4200 | { |
851ba692 AK |
4201 | struct kvm_run *kvm_run = vcpu->run; |
4202 | ||
91586a3b | 4203 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 4204 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 4205 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 4206 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 4207 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 4208 | else |
b6c7a5dc | 4209 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
4210 | kvm_arch_interrupt_allowed(vcpu) && |
4211 | !kvm_cpu_has_interrupt(vcpu) && | |
4212 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
4213 | } |
4214 | ||
b93463aa AK |
4215 | static void vapic_enter(struct kvm_vcpu *vcpu) |
4216 | { | |
4217 | struct kvm_lapic *apic = vcpu->arch.apic; | |
4218 | struct page *page; | |
4219 | ||
4220 | if (!apic || !apic->vapic_addr) | |
4221 | return; | |
4222 | ||
4223 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
4224 | |
4225 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
4226 | } |
4227 | ||
4228 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
4229 | { | |
4230 | struct kvm_lapic *apic = vcpu->arch.apic; | |
f656ce01 | 4231 | int idx; |
b93463aa AK |
4232 | |
4233 | if (!apic || !apic->vapic_addr) | |
4234 | return; | |
4235 | ||
f656ce01 | 4236 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
b93463aa AK |
4237 | kvm_release_page_dirty(apic->vapic_page); |
4238 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f656ce01 | 4239 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4240 | } |
4241 | ||
95ba8273 GN |
4242 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
4243 | { | |
4244 | int max_irr, tpr; | |
4245 | ||
4246 | if (!kvm_x86_ops->update_cr8_intercept) | |
4247 | return; | |
4248 | ||
88c808fd AK |
4249 | if (!vcpu->arch.apic) |
4250 | return; | |
4251 | ||
8db3baa2 GN |
4252 | if (!vcpu->arch.apic->vapic_addr) |
4253 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
4254 | else | |
4255 | max_irr = -1; | |
95ba8273 GN |
4256 | |
4257 | if (max_irr != -1) | |
4258 | max_irr >>= 4; | |
4259 | ||
4260 | tpr = kvm_lapic_get_cr8(vcpu); | |
4261 | ||
4262 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
4263 | } | |
4264 | ||
851ba692 | 4265 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
4266 | { |
4267 | /* try to reinject previous events if any */ | |
b59bb7bd | 4268 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
4269 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
4270 | vcpu->arch.exception.has_error_code, | |
4271 | vcpu->arch.exception.error_code); | |
b59bb7bd GN |
4272 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
4273 | vcpu->arch.exception.has_error_code, | |
4274 | vcpu->arch.exception.error_code); | |
4275 | return; | |
4276 | } | |
4277 | ||
95ba8273 GN |
4278 | if (vcpu->arch.nmi_injected) { |
4279 | kvm_x86_ops->set_nmi(vcpu); | |
4280 | return; | |
4281 | } | |
4282 | ||
4283 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 4284 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
4285 | return; |
4286 | } | |
4287 | ||
4288 | /* try to inject new event if pending */ | |
4289 | if (vcpu->arch.nmi_pending) { | |
4290 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
4291 | vcpu->arch.nmi_pending = false; | |
4292 | vcpu->arch.nmi_injected = true; | |
4293 | kvm_x86_ops->set_nmi(vcpu); | |
4294 | } | |
4295 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
4296 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
4297 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
4298 | false); | |
4299 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
4300 | } |
4301 | } | |
4302 | } | |
4303 | ||
851ba692 | 4304 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
4305 | { |
4306 | int r; | |
6a8b1d13 | 4307 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 4308 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 4309 | |
2e53d63a MT |
4310 | if (vcpu->requests) |
4311 | if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) | |
4312 | kvm_mmu_unload(vcpu); | |
4313 | ||
b6c7a5dc HB |
4314 | r = kvm_mmu_reload(vcpu); |
4315 | if (unlikely(r)) | |
4316 | goto out; | |
4317 | ||
2f52d58c AK |
4318 | if (vcpu->requests) { |
4319 | if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests)) | |
2f599714 | 4320 | __kvm_migrate_timers(vcpu); |
c8076604 GH |
4321 | if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests)) |
4322 | kvm_write_guest_time(vcpu); | |
4731d4c7 MT |
4323 | if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests)) |
4324 | kvm_mmu_sync_roots(vcpu); | |
d4acf7e7 MT |
4325 | if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests)) |
4326 | kvm_x86_ops->tlb_flush(vcpu); | |
b93463aa AK |
4327 | if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS, |
4328 | &vcpu->requests)) { | |
851ba692 | 4329 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
4330 | r = 0; |
4331 | goto out; | |
4332 | } | |
71c4dfaf | 4333 | if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) { |
851ba692 | 4334 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
4335 | r = 0; |
4336 | goto out; | |
4337 | } | |
02daab21 AK |
4338 | if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) { |
4339 | vcpu->fpu_active = 0; | |
4340 | kvm_x86_ops->fpu_deactivate(vcpu); | |
4341 | } | |
2f52d58c | 4342 | } |
b93463aa | 4343 | |
b6c7a5dc HB |
4344 | preempt_disable(); |
4345 | ||
4346 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
2608d7a1 AK |
4347 | if (vcpu->fpu_active) |
4348 | kvm_load_guest_fpu(vcpu); | |
b6c7a5dc HB |
4349 | |
4350 | local_irq_disable(); | |
4351 | ||
32f88400 MT |
4352 | clear_bit(KVM_REQ_KICK, &vcpu->requests); |
4353 | smp_mb__after_clear_bit(); | |
4354 | ||
d7690175 | 4355 | if (vcpu->requests || need_resched() || signal_pending(current)) { |
c7f0f24b | 4356 | set_bit(KVM_REQ_KICK, &vcpu->requests); |
6c142801 AK |
4357 | local_irq_enable(); |
4358 | preempt_enable(); | |
4359 | r = 1; | |
4360 | goto out; | |
4361 | } | |
4362 | ||
851ba692 | 4363 | inject_pending_event(vcpu); |
b6c7a5dc | 4364 | |
6a8b1d13 GN |
4365 | /* enable NMI/IRQ window open exits if needed */ |
4366 | if (vcpu->arch.nmi_pending) | |
4367 | kvm_x86_ops->enable_nmi_window(vcpu); | |
4368 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
4369 | kvm_x86_ops->enable_irq_window(vcpu); | |
4370 | ||
95ba8273 | 4371 | if (kvm_lapic_enabled(vcpu)) { |
8db3baa2 GN |
4372 | update_cr8_intercept(vcpu); |
4373 | kvm_lapic_sync_to_vapic(vcpu); | |
95ba8273 | 4374 | } |
b93463aa | 4375 | |
f656ce01 | 4376 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
3200f405 | 4377 | |
b6c7a5dc HB |
4378 | kvm_guest_enter(); |
4379 | ||
42dbaa5a | 4380 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
4381 | set_debugreg(0, 7); |
4382 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
4383 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
4384 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
4385 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
4386 | } | |
b6c7a5dc | 4387 | |
229456fc | 4388 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 4389 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 4390 | |
24f1e32c FW |
4391 | /* |
4392 | * If the guest has used debug registers, at least dr7 | |
4393 | * will be disabled while returning to the host. | |
4394 | * If we don't have active breakpoints in the host, we don't | |
4395 | * care about the messed up debug address registers. But if | |
4396 | * we have some of them active, restore the old state. | |
4397 | */ | |
59d8eb53 | 4398 | if (hw_breakpoint_active()) |
24f1e32c | 4399 | hw_breakpoint_restore(); |
42dbaa5a | 4400 | |
32f88400 | 4401 | set_bit(KVM_REQ_KICK, &vcpu->requests); |
b6c7a5dc HB |
4402 | local_irq_enable(); |
4403 | ||
4404 | ++vcpu->stat.exits; | |
4405 | ||
4406 | /* | |
4407 | * We must have an instruction between local_irq_enable() and | |
4408 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
4409 | * the interrupt shadow. The stat.exits increment will do nicely. | |
4410 | * But we need to prevent reordering, hence this barrier(): | |
4411 | */ | |
4412 | barrier(); | |
4413 | ||
4414 | kvm_guest_exit(); | |
4415 | ||
4416 | preempt_enable(); | |
4417 | ||
f656ce01 | 4418 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 4419 | |
b6c7a5dc HB |
4420 | /* |
4421 | * Profile KVM exit RIPs: | |
4422 | */ | |
4423 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
4424 | unsigned long rip = kvm_rip_read(vcpu); |
4425 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
4426 | } |
4427 | ||
298101da | 4428 | |
b93463aa AK |
4429 | kvm_lapic_sync_from_vapic(vcpu); |
4430 | ||
851ba692 | 4431 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
4432 | out: |
4433 | return r; | |
4434 | } | |
b6c7a5dc | 4435 | |
09cec754 | 4436 | |
851ba692 | 4437 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
4438 | { |
4439 | int r; | |
f656ce01 | 4440 | struct kvm *kvm = vcpu->kvm; |
d7690175 MT |
4441 | |
4442 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
4443 | pr_debug("vcpu %d received sipi with vector # %x\n", |
4444 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 4445 | kvm_lapic_reset(vcpu); |
5f179287 | 4446 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
4447 | if (r) |
4448 | return r; | |
4449 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
4450 | } |
4451 | ||
f656ce01 | 4452 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 MT |
4453 | vapic_enter(vcpu); |
4454 | ||
4455 | r = 1; | |
4456 | while (r > 0) { | |
af2152f5 | 4457 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
851ba692 | 4458 | r = vcpu_enter_guest(vcpu); |
d7690175 | 4459 | else { |
f656ce01 | 4460 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
d7690175 | 4461 | kvm_vcpu_block(vcpu); |
f656ce01 | 4462 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 4463 | if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests)) |
09cec754 GN |
4464 | { |
4465 | switch(vcpu->arch.mp_state) { | |
4466 | case KVM_MP_STATE_HALTED: | |
d7690175 | 4467 | vcpu->arch.mp_state = |
09cec754 GN |
4468 | KVM_MP_STATE_RUNNABLE; |
4469 | case KVM_MP_STATE_RUNNABLE: | |
4470 | break; | |
4471 | case KVM_MP_STATE_SIPI_RECEIVED: | |
4472 | default: | |
4473 | r = -EINTR; | |
4474 | break; | |
4475 | } | |
4476 | } | |
d7690175 MT |
4477 | } |
4478 | ||
09cec754 GN |
4479 | if (r <= 0) |
4480 | break; | |
4481 | ||
4482 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
4483 | if (kvm_cpu_has_pending_timer(vcpu)) | |
4484 | kvm_inject_pending_timer_irqs(vcpu); | |
4485 | ||
851ba692 | 4486 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 4487 | r = -EINTR; |
851ba692 | 4488 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4489 | ++vcpu->stat.request_irq_exits; |
4490 | } | |
4491 | if (signal_pending(current)) { | |
4492 | r = -EINTR; | |
851ba692 | 4493 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4494 | ++vcpu->stat.signal_exits; |
4495 | } | |
4496 | if (need_resched()) { | |
f656ce01 | 4497 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
09cec754 | 4498 | kvm_resched(vcpu); |
f656ce01 | 4499 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 4500 | } |
b6c7a5dc HB |
4501 | } |
4502 | ||
f656ce01 | 4503 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
851ba692 | 4504 | post_kvm_run_save(vcpu); |
b6c7a5dc | 4505 | |
b93463aa AK |
4506 | vapic_exit(vcpu); |
4507 | ||
b6c7a5dc HB |
4508 | return r; |
4509 | } | |
4510 | ||
4511 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
4512 | { | |
4513 | int r; | |
4514 | sigset_t sigsaved; | |
4515 | ||
4516 | vcpu_load(vcpu); | |
4517 | ||
ac9f6dc0 AK |
4518 | if (vcpu->sigset_active) |
4519 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
4520 | ||
a4535290 | 4521 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 4522 | kvm_vcpu_block(vcpu); |
d7690175 | 4523 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
4524 | r = -EAGAIN; |
4525 | goto out; | |
b6c7a5dc HB |
4526 | } |
4527 | ||
b6c7a5dc HB |
4528 | /* re-sync apic's tpr */ |
4529 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 4530 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 4531 | |
ad312c7c | 4532 | if (vcpu->arch.pio.cur_count) { |
7567cae1 | 4533 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
b6c7a5dc | 4534 | r = complete_pio(vcpu); |
7567cae1 | 4535 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
4536 | if (r) |
4537 | goto out; | |
4538 | } | |
b6c7a5dc HB |
4539 | if (vcpu->mmio_needed) { |
4540 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
4541 | vcpu->mmio_read_completed = 1; | |
4542 | vcpu->mmio_needed = 0; | |
3200f405 | 4543 | |
f656ce01 | 4544 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
851ba692 | 4545 | r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0, |
571008da | 4546 | EMULTYPE_NO_DECODE); |
f656ce01 | 4547 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
4548 | if (r == EMULATE_DO_MMIO) { |
4549 | /* | |
4550 | * Read-modify-write. Back to userspace. | |
4551 | */ | |
4552 | r = 0; | |
4553 | goto out; | |
4554 | } | |
4555 | } | |
5fdbf976 MT |
4556 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
4557 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
4558 | kvm_run->hypercall.ret); | |
b6c7a5dc | 4559 | |
851ba692 | 4560 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
4561 | |
4562 | out: | |
4563 | if (vcpu->sigset_active) | |
4564 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
4565 | ||
4566 | vcpu_put(vcpu); | |
4567 | return r; | |
4568 | } | |
4569 | ||
4570 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4571 | { | |
4572 | vcpu_load(vcpu); | |
4573 | ||
5fdbf976 MT |
4574 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4575 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4576 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4577 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4578 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4579 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
4580 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4581 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 4582 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4583 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
4584 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
4585 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
4586 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
4587 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
4588 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
4589 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
4590 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
4591 | #endif |
4592 | ||
5fdbf976 | 4593 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 4594 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc HB |
4595 | |
4596 | vcpu_put(vcpu); | |
4597 | ||
4598 | return 0; | |
4599 | } | |
4600 | ||
4601 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4602 | { | |
4603 | vcpu_load(vcpu); | |
4604 | ||
5fdbf976 MT |
4605 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
4606 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
4607 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
4608 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
4609 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
4610 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
4611 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
4612 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 4613 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4614 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
4615 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
4616 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
4617 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
4618 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
4619 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
4620 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
4621 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
4622 | #endif |
4623 | ||
5fdbf976 | 4624 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 4625 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 4626 | |
b4f14abd JK |
4627 | vcpu->arch.exception.pending = false; |
4628 | ||
b6c7a5dc HB |
4629 | vcpu_put(vcpu); |
4630 | ||
4631 | return 0; | |
4632 | } | |
4633 | ||
3e6e0aab GT |
4634 | void kvm_get_segment(struct kvm_vcpu *vcpu, |
4635 | struct kvm_segment *var, int seg) | |
b6c7a5dc | 4636 | { |
14af3f3c | 4637 | kvm_x86_ops->get_segment(vcpu, var, seg); |
b6c7a5dc HB |
4638 | } |
4639 | ||
4640 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
4641 | { | |
4642 | struct kvm_segment cs; | |
4643 | ||
3e6e0aab | 4644 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
4645 | *db = cs.db; |
4646 | *l = cs.l; | |
4647 | } | |
4648 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
4649 | ||
4650 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
4651 | struct kvm_sregs *sregs) | |
4652 | { | |
89a27f4d | 4653 | struct desc_ptr dt; |
b6c7a5dc HB |
4654 | |
4655 | vcpu_load(vcpu); | |
4656 | ||
3e6e0aab GT |
4657 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
4658 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
4659 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
4660 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
4661 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
4662 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 4663 | |
3e6e0aab GT |
4664 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
4665 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
4666 | |
4667 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
4668 | sregs->idt.limit = dt.size; |
4669 | sregs->idt.base = dt.address; | |
b6c7a5dc | 4670 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
4671 | sregs->gdt.limit = dt.size; |
4672 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 4673 | |
4d4ec087 | 4674 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c ZX |
4675 | sregs->cr2 = vcpu->arch.cr2; |
4676 | sregs->cr3 = vcpu->arch.cr3; | |
fc78f519 | 4677 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 4678 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 4679 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
4680 | sregs->apic_base = kvm_get_apic_base(vcpu); |
4681 | ||
923c61bb | 4682 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 4683 | |
36752c9b | 4684 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
4685 | set_bit(vcpu->arch.interrupt.nr, |
4686 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 4687 | |
b6c7a5dc HB |
4688 | vcpu_put(vcpu); |
4689 | ||
4690 | return 0; | |
4691 | } | |
4692 | ||
62d9f0db MT |
4693 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
4694 | struct kvm_mp_state *mp_state) | |
4695 | { | |
4696 | vcpu_load(vcpu); | |
4697 | mp_state->mp_state = vcpu->arch.mp_state; | |
4698 | vcpu_put(vcpu); | |
4699 | return 0; | |
4700 | } | |
4701 | ||
4702 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
4703 | struct kvm_mp_state *mp_state) | |
4704 | { | |
4705 | vcpu_load(vcpu); | |
4706 | vcpu->arch.mp_state = mp_state->mp_state; | |
4707 | vcpu_put(vcpu); | |
4708 | return 0; | |
4709 | } | |
4710 | ||
3e6e0aab | 4711 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
b6c7a5dc HB |
4712 | struct kvm_segment *var, int seg) |
4713 | { | |
14af3f3c | 4714 | kvm_x86_ops->set_segment(vcpu, var, seg); |
b6c7a5dc HB |
4715 | } |
4716 | ||
37817f29 IE |
4717 | static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector, |
4718 | struct kvm_segment *kvm_desct) | |
4719 | { | |
46a359e7 AM |
4720 | kvm_desct->base = get_desc_base(seg_desc); |
4721 | kvm_desct->limit = get_desc_limit(seg_desc); | |
c93cd3a5 MT |
4722 | if (seg_desc->g) { |
4723 | kvm_desct->limit <<= 12; | |
4724 | kvm_desct->limit |= 0xfff; | |
4725 | } | |
37817f29 IE |
4726 | kvm_desct->selector = selector; |
4727 | kvm_desct->type = seg_desc->type; | |
4728 | kvm_desct->present = seg_desc->p; | |
4729 | kvm_desct->dpl = seg_desc->dpl; | |
4730 | kvm_desct->db = seg_desc->d; | |
4731 | kvm_desct->s = seg_desc->s; | |
4732 | kvm_desct->l = seg_desc->l; | |
4733 | kvm_desct->g = seg_desc->g; | |
4734 | kvm_desct->avl = seg_desc->avl; | |
4735 | if (!selector) | |
4736 | kvm_desct->unusable = 1; | |
4737 | else | |
4738 | kvm_desct->unusable = 0; | |
4739 | kvm_desct->padding = 0; | |
4740 | } | |
4741 | ||
b8222ad2 AS |
4742 | static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu, |
4743 | u16 selector, | |
89a27f4d | 4744 | struct desc_ptr *dtable) |
37817f29 IE |
4745 | { |
4746 | if (selector & 1 << 2) { | |
4747 | struct kvm_segment kvm_seg; | |
4748 | ||
3e6e0aab | 4749 | kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR); |
37817f29 IE |
4750 | |
4751 | if (kvm_seg.unusable) | |
89a27f4d | 4752 | dtable->size = 0; |
37817f29 | 4753 | else |
89a27f4d GN |
4754 | dtable->size = kvm_seg.limit; |
4755 | dtable->address = kvm_seg.base; | |
37817f29 IE |
4756 | } |
4757 | else | |
4758 | kvm_x86_ops->get_gdt(vcpu, dtable); | |
4759 | } | |
4760 | ||
4761 | /* allowed just for 8 bytes segments */ | |
4762 | static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
4763 | struct desc_struct *seg_desc) | |
4764 | { | |
89a27f4d | 4765 | struct desc_ptr dtable; |
37817f29 | 4766 | u16 index = selector >> 3; |
6f550484 TY |
4767 | int ret; |
4768 | u32 err; | |
4769 | gva_t addr; | |
37817f29 | 4770 | |
b8222ad2 | 4771 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 | 4772 | |
89a27f4d | 4773 | if (dtable.size < index * 8 + 7) { |
37817f29 | 4774 | kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc); |
c125c607 | 4775 | return X86EMUL_PROPAGATE_FAULT; |
37817f29 | 4776 | } |
6f550484 TY |
4777 | addr = dtable.base + index * 8; |
4778 | ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc), | |
4779 | vcpu, &err); | |
4780 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
4781 | kvm_inject_page_fault(vcpu, addr, err); | |
4782 | ||
4783 | return ret; | |
37817f29 IE |
4784 | } |
4785 | ||
4786 | /* allowed just for 8 bytes segments */ | |
4787 | static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
4788 | struct desc_struct *seg_desc) | |
4789 | { | |
89a27f4d | 4790 | struct desc_ptr dtable; |
37817f29 IE |
4791 | u16 index = selector >> 3; |
4792 | ||
b8222ad2 | 4793 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 | 4794 | |
89a27f4d | 4795 | if (dtable.size < index * 8 + 7) |
37817f29 | 4796 | return 1; |
89a27f4d | 4797 | return kvm_write_guest_virt(dtable.address + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL); |
1871c602 GN |
4798 | } |
4799 | ||
4800 | static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu, | |
4801 | struct desc_struct *seg_desc) | |
4802 | { | |
4803 | u32 base_addr = get_desc_base(seg_desc); | |
4804 | ||
4805 | return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL); | |
37817f29 IE |
4806 | } |
4807 | ||
1871c602 | 4808 | static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu, |
37817f29 IE |
4809 | struct desc_struct *seg_desc) |
4810 | { | |
46a359e7 | 4811 | u32 base_addr = get_desc_base(seg_desc); |
37817f29 | 4812 | |
1871c602 | 4813 | return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL); |
37817f29 IE |
4814 | } |
4815 | ||
37817f29 IE |
4816 | static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg) |
4817 | { | |
4818 | struct kvm_segment kvm_seg; | |
4819 | ||
3e6e0aab | 4820 | kvm_get_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
4821 | return kvm_seg.selector; |
4822 | } | |
4823 | ||
2259e3a7 | 4824 | static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg) |
f4bbd9aa AK |
4825 | { |
4826 | struct kvm_segment segvar = { | |
4827 | .base = selector << 4, | |
4828 | .limit = 0xffff, | |
4829 | .selector = selector, | |
4830 | .type = 3, | |
4831 | .present = 1, | |
4832 | .dpl = 3, | |
4833 | .db = 0, | |
4834 | .s = 1, | |
4835 | .l = 0, | |
4836 | .g = 0, | |
4837 | .avl = 0, | |
4838 | .unusable = 0, | |
4839 | }; | |
4840 | kvm_x86_ops->set_segment(vcpu, &segvar, seg); | |
c697518a | 4841 | return X86EMUL_CONTINUE; |
f4bbd9aa AK |
4842 | } |
4843 | ||
c0c7c04b AL |
4844 | static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg) |
4845 | { | |
4846 | return (seg != VCPU_SREG_LDTR) && | |
4847 | (seg != VCPU_SREG_TR) && | |
91586a3b | 4848 | (kvm_get_rflags(vcpu) & X86_EFLAGS_VM); |
c0c7c04b AL |
4849 | } |
4850 | ||
c697518a | 4851 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg) |
37817f29 IE |
4852 | { |
4853 | struct kvm_segment kvm_seg; | |
e01c2426 | 4854 | struct desc_struct seg_desc; |
c697518a GN |
4855 | u8 dpl, rpl, cpl; |
4856 | unsigned err_vec = GP_VECTOR; | |
4857 | u32 err_code = 0; | |
4858 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
4859 | int ret; | |
37817f29 | 4860 | |
3eeb3288 | 4861 | if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu)) |
f4bbd9aa | 4862 | return kvm_load_realmode_segment(vcpu, selector, seg); |
e01c2426 | 4863 | |
c697518a GN |
4864 | /* NULL selector is not valid for TR, CS and SS */ |
4865 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
4866 | && null_selector) | |
4867 | goto exception; | |
4868 | ||
4869 | /* TR should be in GDT only */ | |
4870 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
4871 | goto exception; | |
4872 | ||
4873 | ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc); | |
4874 | if (ret) | |
4875 | return ret; | |
4876 | ||
e01c2426 | 4877 | seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg); |
cb84b55f | 4878 | |
c697518a GN |
4879 | if (null_selector) { /* for NULL selector skip all following checks */ |
4880 | kvm_seg.unusable = 1; | |
4881 | goto load; | |
4882 | } | |
37817f29 | 4883 | |
c697518a GN |
4884 | err_code = selector & 0xfffc; |
4885 | err_vec = GP_VECTOR; | |
37817f29 | 4886 | |
c697518a GN |
4887 | /* can't load system descriptor into segment selecor */ |
4888 | if (seg <= VCPU_SREG_GS && !kvm_seg.s) | |
4889 | goto exception; | |
4890 | ||
4891 | if (!kvm_seg.present) { | |
4892 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
4893 | goto exception; | |
4894 | } | |
4895 | ||
4896 | rpl = selector & 3; | |
4897 | dpl = kvm_seg.dpl; | |
4898 | cpl = kvm_x86_ops->get_cpl(vcpu); | |
4899 | ||
4900 | switch (seg) { | |
4901 | case VCPU_SREG_SS: | |
4902 | /* | |
4903 | * segment is not a writable data segment or segment | |
4904 | * selector's RPL != CPL or segment selector's RPL != CPL | |
4905 | */ | |
4906 | if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl) | |
4907 | goto exception; | |
4908 | break; | |
4909 | case VCPU_SREG_CS: | |
4910 | if (!(kvm_seg.type & 8)) | |
4911 | goto exception; | |
4912 | ||
4913 | if (kvm_seg.type & 4) { | |
4914 | /* conforming */ | |
4915 | if (dpl > cpl) | |
4916 | goto exception; | |
4917 | } else { | |
4918 | /* nonconforming */ | |
4919 | if (rpl > cpl || dpl != cpl) | |
4920 | goto exception; | |
4921 | } | |
4922 | /* CS(RPL) <- CPL */ | |
4923 | selector = (selector & 0xfffc) | cpl; | |
4924 | break; | |
4925 | case VCPU_SREG_TR: | |
4926 | if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9)) | |
4927 | goto exception; | |
4928 | break; | |
4929 | case VCPU_SREG_LDTR: | |
4930 | if (kvm_seg.s || kvm_seg.type != 2) | |
4931 | goto exception; | |
4932 | break; | |
4933 | default: /* DS, ES, FS, or GS */ | |
4934 | /* | |
4935 | * segment is not a data or readable code segment or | |
4936 | * ((segment is a data or nonconforming code segment) | |
4937 | * and (both RPL and CPL > DPL)) | |
4938 | */ | |
4939 | if ((kvm_seg.type & 0xa) == 0x8 || | |
4940 | (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl))) | |
4941 | goto exception; | |
4942 | break; | |
4943 | } | |
4944 | ||
4945 | if (!kvm_seg.unusable && kvm_seg.s) { | |
e01c2426 | 4946 | /* mark segment as accessed */ |
c697518a | 4947 | kvm_seg.type |= 1; |
e01c2426 GN |
4948 | seg_desc.type |= 1; |
4949 | save_guest_segment_descriptor(vcpu, selector, &seg_desc); | |
4950 | } | |
c697518a GN |
4951 | load: |
4952 | kvm_set_segment(vcpu, &kvm_seg, seg); | |
4953 | return X86EMUL_CONTINUE; | |
4954 | exception: | |
4955 | kvm_queue_exception_e(vcpu, err_vec, err_code); | |
4956 | return X86EMUL_PROPAGATE_FAULT; | |
37817f29 IE |
4957 | } |
4958 | ||
4959 | static void save_state_to_tss32(struct kvm_vcpu *vcpu, | |
4960 | struct tss_segment_32 *tss) | |
4961 | { | |
4962 | tss->cr3 = vcpu->arch.cr3; | |
5fdbf976 | 4963 | tss->eip = kvm_rip_read(vcpu); |
91586a3b | 4964 | tss->eflags = kvm_get_rflags(vcpu); |
5fdbf976 MT |
4965 | tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4966 | tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4967 | tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4968 | tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4969 | tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4970 | tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
4971 | tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4972 | tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
4973 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); |
4974 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
4975 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
4976 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
4977 | tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS); | |
4978 | tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS); | |
4979 | tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
4980 | } |
4981 | ||
c697518a GN |
4982 | static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg) |
4983 | { | |
4984 | struct kvm_segment kvm_seg; | |
4985 | kvm_get_segment(vcpu, &kvm_seg, seg); | |
4986 | kvm_seg.selector = sel; | |
4987 | kvm_set_segment(vcpu, &kvm_seg, seg); | |
4988 | } | |
4989 | ||
37817f29 IE |
4990 | static int load_state_from_tss32(struct kvm_vcpu *vcpu, |
4991 | struct tss_segment_32 *tss) | |
4992 | { | |
4993 | kvm_set_cr3(vcpu, tss->cr3); | |
4994 | ||
5fdbf976 | 4995 | kvm_rip_write(vcpu, tss->eip); |
91586a3b | 4996 | kvm_set_rflags(vcpu, tss->eflags | 2); |
37817f29 | 4997 | |
5fdbf976 MT |
4998 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax); |
4999 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx); | |
5000 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx); | |
5001 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx); | |
5002 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp); | |
5003 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp); | |
5004 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi); | |
5005 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi); | |
37817f29 | 5006 | |
c697518a GN |
5007 | /* |
5008 | * SDM says that segment selectors are loaded before segment | |
5009 | * descriptors | |
5010 | */ | |
5011 | kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR); | |
5012 | kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES); | |
5013 | kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS); | |
5014 | kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS); | |
5015 | kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS); | |
5016 | kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS); | |
5017 | kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS); | |
5018 | ||
5019 | /* | |
5020 | * Now load segment descriptors. If fault happenes at this stage | |
5021 | * it is handled in a context of new task | |
5022 | */ | |
5023 | if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR)) | |
37817f29 IE |
5024 | return 1; |
5025 | ||
c697518a | 5026 | if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES)) |
37817f29 IE |
5027 | return 1; |
5028 | ||
c697518a | 5029 | if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS)) |
37817f29 IE |
5030 | return 1; |
5031 | ||
c697518a | 5032 | if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS)) |
37817f29 IE |
5033 | return 1; |
5034 | ||
c697518a | 5035 | if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS)) |
37817f29 IE |
5036 | return 1; |
5037 | ||
c697518a | 5038 | if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS)) |
37817f29 IE |
5039 | return 1; |
5040 | ||
c697518a | 5041 | if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS)) |
37817f29 IE |
5042 | return 1; |
5043 | return 0; | |
5044 | } | |
5045 | ||
5046 | static void save_state_to_tss16(struct kvm_vcpu *vcpu, | |
5047 | struct tss_segment_16 *tss) | |
5048 | { | |
5fdbf976 | 5049 | tss->ip = kvm_rip_read(vcpu); |
91586a3b | 5050 | tss->flag = kvm_get_rflags(vcpu); |
5fdbf976 MT |
5051 | tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
5052 | tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5053 | tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5054 | tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5055 | tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
5056 | tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
5057 | tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5058 | tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
5059 | |
5060 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); | |
5061 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
5062 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
5063 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
5064 | tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
5065 | } |
5066 | ||
5067 | static int load_state_from_tss16(struct kvm_vcpu *vcpu, | |
5068 | struct tss_segment_16 *tss) | |
5069 | { | |
5fdbf976 | 5070 | kvm_rip_write(vcpu, tss->ip); |
91586a3b | 5071 | kvm_set_rflags(vcpu, tss->flag | 2); |
5fdbf976 MT |
5072 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax); |
5073 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx); | |
5074 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx); | |
5075 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx); | |
5076 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp); | |
5077 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp); | |
5078 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si); | |
5079 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di); | |
37817f29 | 5080 | |
c697518a GN |
5081 | /* |
5082 | * SDM says that segment selectors are loaded before segment | |
5083 | * descriptors | |
5084 | */ | |
5085 | kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR); | |
5086 | kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES); | |
5087 | kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS); | |
5088 | kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS); | |
5089 | kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS); | |
5090 | ||
5091 | /* | |
5092 | * Now load segment descriptors. If fault happenes at this stage | |
5093 | * it is handled in a context of new task | |
5094 | */ | |
5095 | if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR)) | |
37817f29 IE |
5096 | return 1; |
5097 | ||
c697518a | 5098 | if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES)) |
37817f29 IE |
5099 | return 1; |
5100 | ||
c697518a | 5101 | if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS)) |
37817f29 IE |
5102 | return 1; |
5103 | ||
c697518a | 5104 | if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS)) |
37817f29 IE |
5105 | return 1; |
5106 | ||
c697518a | 5107 | if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS)) |
37817f29 IE |
5108 | return 1; |
5109 | return 0; | |
5110 | } | |
5111 | ||
8b2cf73c | 5112 | static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 GN |
5113 | u16 old_tss_sel, u32 old_tss_base, |
5114 | struct desc_struct *nseg_desc) | |
37817f29 IE |
5115 | { |
5116 | struct tss_segment_16 tss_segment_16; | |
5117 | int ret = 0; | |
5118 | ||
34198bf8 MT |
5119 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
5120 | sizeof tss_segment_16)) | |
37817f29 IE |
5121 | goto out; |
5122 | ||
5123 | save_state_to_tss16(vcpu, &tss_segment_16); | |
37817f29 | 5124 | |
34198bf8 MT |
5125 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
5126 | sizeof tss_segment_16)) | |
37817f29 | 5127 | goto out; |
34198bf8 | 5128 | |
1871c602 | 5129 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc), |
34198bf8 MT |
5130 | &tss_segment_16, sizeof tss_segment_16)) |
5131 | goto out; | |
5132 | ||
b237ac37 GN |
5133 | if (old_tss_sel != 0xffff) { |
5134 | tss_segment_16.prev_task_link = old_tss_sel; | |
5135 | ||
5136 | if (kvm_write_guest(vcpu->kvm, | |
1871c602 | 5137 | get_tss_base_addr_write(vcpu, nseg_desc), |
b237ac37 GN |
5138 | &tss_segment_16.prev_task_link, |
5139 | sizeof tss_segment_16.prev_task_link)) | |
5140 | goto out; | |
5141 | } | |
5142 | ||
37817f29 IE |
5143 | if (load_state_from_tss16(vcpu, &tss_segment_16)) |
5144 | goto out; | |
5145 | ||
5146 | ret = 1; | |
5147 | out: | |
5148 | return ret; | |
5149 | } | |
5150 | ||
8b2cf73c | 5151 | static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 | 5152 | u16 old_tss_sel, u32 old_tss_base, |
37817f29 IE |
5153 | struct desc_struct *nseg_desc) |
5154 | { | |
5155 | struct tss_segment_32 tss_segment_32; | |
5156 | int ret = 0; | |
5157 | ||
34198bf8 MT |
5158 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
5159 | sizeof tss_segment_32)) | |
37817f29 IE |
5160 | goto out; |
5161 | ||
5162 | save_state_to_tss32(vcpu, &tss_segment_32); | |
37817f29 | 5163 | |
34198bf8 MT |
5164 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
5165 | sizeof tss_segment_32)) | |
5166 | goto out; | |
5167 | ||
1871c602 | 5168 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc), |
34198bf8 | 5169 | &tss_segment_32, sizeof tss_segment_32)) |
37817f29 | 5170 | goto out; |
34198bf8 | 5171 | |
b237ac37 GN |
5172 | if (old_tss_sel != 0xffff) { |
5173 | tss_segment_32.prev_task_link = old_tss_sel; | |
5174 | ||
5175 | if (kvm_write_guest(vcpu->kvm, | |
1871c602 | 5176 | get_tss_base_addr_write(vcpu, nseg_desc), |
b237ac37 GN |
5177 | &tss_segment_32.prev_task_link, |
5178 | sizeof tss_segment_32.prev_task_link)) | |
5179 | goto out; | |
5180 | } | |
5181 | ||
37817f29 IE |
5182 | if (load_state_from_tss32(vcpu, &tss_segment_32)) |
5183 | goto out; | |
5184 | ||
5185 | ret = 1; | |
5186 | out: | |
5187 | return ret; | |
5188 | } | |
5189 | ||
5190 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason) | |
5191 | { | |
5192 | struct kvm_segment tr_seg; | |
5193 | struct desc_struct cseg_desc; | |
5194 | struct desc_struct nseg_desc; | |
5195 | int ret = 0; | |
34198bf8 MT |
5196 | u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR); |
5197 | u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR); | |
e8861cfe | 5198 | u32 desc_limit; |
37817f29 | 5199 | |
1871c602 | 5200 | old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL); |
37817f29 | 5201 | |
34198bf8 MT |
5202 | /* FIXME: Handle errors. Failure to read either TSS or their |
5203 | * descriptors should generate a pagefault. | |
5204 | */ | |
37817f29 IE |
5205 | if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc)) |
5206 | goto out; | |
5207 | ||
34198bf8 | 5208 | if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc)) |
37817f29 IE |
5209 | goto out; |
5210 | ||
37817f29 IE |
5211 | if (reason != TASK_SWITCH_IRET) { |
5212 | int cpl; | |
5213 | ||
5214 | cpl = kvm_x86_ops->get_cpl(vcpu); | |
5215 | if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) { | |
5216 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
5217 | return 1; | |
5218 | } | |
5219 | } | |
5220 | ||
e8861cfe JK |
5221 | desc_limit = get_desc_limit(&nseg_desc); |
5222 | if (!nseg_desc.p || | |
5223 | ((desc_limit < 0x67 && (nseg_desc.type & 8)) || | |
5224 | desc_limit < 0x2b)) { | |
37817f29 IE |
5225 | kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc); |
5226 | return 1; | |
5227 | } | |
5228 | ||
5229 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
3fe913e7 | 5230 | cseg_desc.type &= ~(1 << 1); //clear the B flag |
34198bf8 | 5231 | save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc); |
37817f29 IE |
5232 | } |
5233 | ||
5234 | if (reason == TASK_SWITCH_IRET) { | |
91586a3b JK |
5235 | u32 eflags = kvm_get_rflags(vcpu); |
5236 | kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT); | |
37817f29 IE |
5237 | } |
5238 | ||
b237ac37 GN |
5239 | /* set back link to prev task only if NT bit is set in eflags |
5240 | note that old_tss_sel is not used afetr this point */ | |
5241 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
5242 | old_tss_sel = 0xffff; | |
5243 | ||
37817f29 | 5244 | if (nseg_desc.type & 8) |
b237ac37 GN |
5245 | ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel, |
5246 | old_tss_base, &nseg_desc); | |
37817f29 | 5247 | else |
b237ac37 GN |
5248 | ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel, |
5249 | old_tss_base, &nseg_desc); | |
37817f29 IE |
5250 | |
5251 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) { | |
91586a3b JK |
5252 | u32 eflags = kvm_get_rflags(vcpu); |
5253 | kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT); | |
37817f29 IE |
5254 | } |
5255 | ||
5256 | if (reason != TASK_SWITCH_IRET) { | |
3fe913e7 | 5257 | nseg_desc.type |= (1 << 1); |
37817f29 IE |
5258 | save_guest_segment_descriptor(vcpu, tss_selector, |
5259 | &nseg_desc); | |
5260 | } | |
5261 | ||
4d4ec087 | 5262 | kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS); |
37817f29 IE |
5263 | seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg); |
5264 | tr_seg.type = 11; | |
3e6e0aab | 5265 | kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR); |
37817f29 | 5266 | out: |
37817f29 IE |
5267 | return ret; |
5268 | } | |
5269 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
5270 | ||
b6c7a5dc HB |
5271 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
5272 | struct kvm_sregs *sregs) | |
5273 | { | |
5274 | int mmu_reset_needed = 0; | |
923c61bb | 5275 | int pending_vec, max_bits; |
89a27f4d | 5276 | struct desc_ptr dt; |
b6c7a5dc HB |
5277 | |
5278 | vcpu_load(vcpu); | |
5279 | ||
89a27f4d GN |
5280 | dt.size = sregs->idt.limit; |
5281 | dt.address = sregs->idt.base; | |
b6c7a5dc | 5282 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
5283 | dt.size = sregs->gdt.limit; |
5284 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
5285 | kvm_x86_ops->set_gdt(vcpu, &dt); |
5286 | ||
ad312c7c ZX |
5287 | vcpu->arch.cr2 = sregs->cr2; |
5288 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
dc7e795e | 5289 | vcpu->arch.cr3 = sregs->cr3; |
b6c7a5dc | 5290 | |
2d3ad1f4 | 5291 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 5292 | |
f6801dff | 5293 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 5294 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
5295 | kvm_set_apic_base(vcpu, sregs->apic_base); |
5296 | ||
4d4ec087 | 5297 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 5298 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 5299 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 5300 | |
fc78f519 | 5301 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b6c7a5dc | 5302 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
7c93be44 | 5303 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
ad312c7c | 5304 | load_pdptrs(vcpu, vcpu->arch.cr3); |
7c93be44 MT |
5305 | mmu_reset_needed = 1; |
5306 | } | |
b6c7a5dc HB |
5307 | |
5308 | if (mmu_reset_needed) | |
5309 | kvm_mmu_reset_context(vcpu); | |
5310 | ||
923c61bb GN |
5311 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
5312 | pending_vec = find_first_bit( | |
5313 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
5314 | if (pending_vec < max_bits) { | |
66fd3f7f | 5315 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb GN |
5316 | pr_debug("Set back pending irq %d\n", pending_vec); |
5317 | if (irqchip_in_kernel(vcpu->kvm)) | |
5318 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
b6c7a5dc HB |
5319 | } |
5320 | ||
3e6e0aab GT |
5321 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
5322 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
5323 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
5324 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
5325 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
5326 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 5327 | |
3e6e0aab GT |
5328 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
5329 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 5330 | |
5f0269f5 ME |
5331 | update_cr8_intercept(vcpu); |
5332 | ||
9c3e4aab | 5333 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 5334 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 5335 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 5336 | !is_protmode(vcpu)) |
9c3e4aab MT |
5337 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
5338 | ||
b6c7a5dc HB |
5339 | vcpu_put(vcpu); |
5340 | ||
5341 | return 0; | |
5342 | } | |
5343 | ||
d0bfb940 JK |
5344 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
5345 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 5346 | { |
355be0b9 | 5347 | unsigned long rflags; |
ae675ef0 | 5348 | int i, r; |
b6c7a5dc HB |
5349 | |
5350 | vcpu_load(vcpu); | |
5351 | ||
4f926bf2 JK |
5352 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
5353 | r = -EBUSY; | |
5354 | if (vcpu->arch.exception.pending) | |
5355 | goto unlock_out; | |
5356 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) | |
5357 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5358 | else | |
5359 | kvm_queue_exception(vcpu, BP_VECTOR); | |
5360 | } | |
5361 | ||
91586a3b JK |
5362 | /* |
5363 | * Read rflags as long as potentially injected trace flags are still | |
5364 | * filtered out. | |
5365 | */ | |
5366 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
5367 | |
5368 | vcpu->guest_debug = dbg->control; | |
5369 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
5370 | vcpu->guest_debug = 0; | |
5371 | ||
5372 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
5373 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
5374 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
5375 | vcpu->arch.switch_db_regs = | |
5376 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
5377 | } else { | |
5378 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
5379 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
5380 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
5381 | } | |
5382 | ||
f92653ee JK |
5383 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
5384 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
5385 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 5386 | |
91586a3b JK |
5387 | /* |
5388 | * Trigger an rflags update that will inject or remove the trace | |
5389 | * flags. | |
5390 | */ | |
5391 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 5392 | |
355be0b9 | 5393 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
b6c7a5dc | 5394 | |
4f926bf2 | 5395 | r = 0; |
d0bfb940 | 5396 | |
4f926bf2 | 5397 | unlock_out: |
b6c7a5dc HB |
5398 | vcpu_put(vcpu); |
5399 | ||
5400 | return r; | |
5401 | } | |
5402 | ||
d0752060 HB |
5403 | /* |
5404 | * fxsave fpu state. Taken from x86_64/processor.h. To be killed when | |
5405 | * we have asm/x86/processor.h | |
5406 | */ | |
5407 | struct fxsave { | |
5408 | u16 cwd; | |
5409 | u16 swd; | |
5410 | u16 twd; | |
5411 | u16 fop; | |
5412 | u64 rip; | |
5413 | u64 rdp; | |
5414 | u32 mxcsr; | |
5415 | u32 mxcsr_mask; | |
5416 | u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ | |
5417 | #ifdef CONFIG_X86_64 | |
5418 | u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ | |
5419 | #else | |
5420 | u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ | |
5421 | #endif | |
5422 | }; | |
5423 | ||
8b006791 ZX |
5424 | /* |
5425 | * Translate a guest virtual address to a guest physical address. | |
5426 | */ | |
5427 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
5428 | struct kvm_translation *tr) | |
5429 | { | |
5430 | unsigned long vaddr = tr->linear_address; | |
5431 | gpa_t gpa; | |
f656ce01 | 5432 | int idx; |
8b006791 ZX |
5433 | |
5434 | vcpu_load(vcpu); | |
f656ce01 | 5435 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 5436 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 5437 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
5438 | tr->physical_address = gpa; |
5439 | tr->valid = gpa != UNMAPPED_GVA; | |
5440 | tr->writeable = 1; | |
5441 | tr->usermode = 0; | |
8b006791 ZX |
5442 | vcpu_put(vcpu); |
5443 | ||
5444 | return 0; | |
5445 | } | |
5446 | ||
d0752060 HB |
5447 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
5448 | { | |
ad312c7c | 5449 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
5450 | |
5451 | vcpu_load(vcpu); | |
5452 | ||
5453 | memcpy(fpu->fpr, fxsave->st_space, 128); | |
5454 | fpu->fcw = fxsave->cwd; | |
5455 | fpu->fsw = fxsave->swd; | |
5456 | fpu->ftwx = fxsave->twd; | |
5457 | fpu->last_opcode = fxsave->fop; | |
5458 | fpu->last_ip = fxsave->rip; | |
5459 | fpu->last_dp = fxsave->rdp; | |
5460 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
5461 | ||
5462 | vcpu_put(vcpu); | |
5463 | ||
5464 | return 0; | |
5465 | } | |
5466 | ||
5467 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
5468 | { | |
ad312c7c | 5469 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
5470 | |
5471 | vcpu_load(vcpu); | |
5472 | ||
5473 | memcpy(fxsave->st_space, fpu->fpr, 128); | |
5474 | fxsave->cwd = fpu->fcw; | |
5475 | fxsave->swd = fpu->fsw; | |
5476 | fxsave->twd = fpu->ftwx; | |
5477 | fxsave->fop = fpu->last_opcode; | |
5478 | fxsave->rip = fpu->last_ip; | |
5479 | fxsave->rdp = fpu->last_dp; | |
5480 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
5481 | ||
5482 | vcpu_put(vcpu); | |
5483 | ||
5484 | return 0; | |
5485 | } | |
5486 | ||
5487 | void fx_init(struct kvm_vcpu *vcpu) | |
5488 | { | |
5489 | unsigned after_mxcsr_mask; | |
5490 | ||
bc1a34f1 AA |
5491 | /* |
5492 | * Touch the fpu the first time in non atomic context as if | |
5493 | * this is the first fpu instruction the exception handler | |
5494 | * will fire before the instruction returns and it'll have to | |
5495 | * allocate ram with GFP_KERNEL. | |
5496 | */ | |
5497 | if (!used_math()) | |
d6e88aec | 5498 | kvm_fx_save(&vcpu->arch.host_fx_image); |
bc1a34f1 | 5499 | |
d0752060 HB |
5500 | /* Initialize guest FPU by resetting ours and saving into guest's */ |
5501 | preempt_disable(); | |
d6e88aec AK |
5502 | kvm_fx_save(&vcpu->arch.host_fx_image); |
5503 | kvm_fx_finit(); | |
5504 | kvm_fx_save(&vcpu->arch.guest_fx_image); | |
5505 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
d0752060 HB |
5506 | preempt_enable(); |
5507 | ||
ad312c7c | 5508 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 5509 | after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space); |
ad312c7c ZX |
5510 | vcpu->arch.guest_fx_image.mxcsr = 0x1f80; |
5511 | memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask, | |
d0752060 HB |
5512 | 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask); |
5513 | } | |
5514 | EXPORT_SYMBOL_GPL(fx_init); | |
5515 | ||
5516 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
5517 | { | |
2608d7a1 | 5518 | if (vcpu->guest_fpu_loaded) |
d0752060 HB |
5519 | return; |
5520 | ||
5521 | vcpu->guest_fpu_loaded = 1; | |
d6e88aec AK |
5522 | kvm_fx_save(&vcpu->arch.host_fx_image); |
5523 | kvm_fx_restore(&vcpu->arch.guest_fx_image); | |
0c04851c | 5524 | trace_kvm_fpu(1); |
d0752060 | 5525 | } |
d0752060 HB |
5526 | |
5527 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
5528 | { | |
5529 | if (!vcpu->guest_fpu_loaded) | |
5530 | return; | |
5531 | ||
5532 | vcpu->guest_fpu_loaded = 0; | |
d6e88aec AK |
5533 | kvm_fx_save(&vcpu->arch.guest_fx_image); |
5534 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
f096ed85 | 5535 | ++vcpu->stat.fpu_reload; |
02daab21 | 5536 | set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests); |
0c04851c | 5537 | trace_kvm_fpu(0); |
d0752060 | 5538 | } |
e9b11c17 ZX |
5539 | |
5540 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
5541 | { | |
7f1ea208 JR |
5542 | if (vcpu->arch.time_page) { |
5543 | kvm_release_page_dirty(vcpu->arch.time_page); | |
5544 | vcpu->arch.time_page = NULL; | |
5545 | } | |
5546 | ||
e9b11c17 ZX |
5547 | kvm_x86_ops->vcpu_free(vcpu); |
5548 | } | |
5549 | ||
5550 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
5551 | unsigned int id) | |
5552 | { | |
26e5215f AK |
5553 | return kvm_x86_ops->vcpu_create(kvm, id); |
5554 | } | |
e9b11c17 | 5555 | |
26e5215f AK |
5556 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
5557 | { | |
5558 | int r; | |
e9b11c17 ZX |
5559 | |
5560 | /* We do fxsave: this must be aligned. */ | |
ad312c7c | 5561 | BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF); |
e9b11c17 | 5562 | |
0bed3b56 | 5563 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
5564 | vcpu_load(vcpu); |
5565 | r = kvm_arch_vcpu_reset(vcpu); | |
5566 | if (r == 0) | |
5567 | r = kvm_mmu_setup(vcpu); | |
5568 | vcpu_put(vcpu); | |
5569 | if (r < 0) | |
5570 | goto free_vcpu; | |
5571 | ||
26e5215f | 5572 | return 0; |
e9b11c17 ZX |
5573 | free_vcpu: |
5574 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 5575 | return r; |
e9b11c17 ZX |
5576 | } |
5577 | ||
d40ccc62 | 5578 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
5579 | { |
5580 | vcpu_load(vcpu); | |
5581 | kvm_mmu_unload(vcpu); | |
5582 | vcpu_put(vcpu); | |
5583 | ||
5584 | kvm_x86_ops->vcpu_free(vcpu); | |
5585 | } | |
5586 | ||
5587 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
5588 | { | |
448fa4a9 JK |
5589 | vcpu->arch.nmi_pending = false; |
5590 | vcpu->arch.nmi_injected = false; | |
5591 | ||
42dbaa5a JK |
5592 | vcpu->arch.switch_db_regs = 0; |
5593 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
5594 | vcpu->arch.dr6 = DR6_FIXED_1; | |
5595 | vcpu->arch.dr7 = DR7_FIXED_1; | |
5596 | ||
e9b11c17 ZX |
5597 | return kvm_x86_ops->vcpu_reset(vcpu); |
5598 | } | |
5599 | ||
10474ae8 | 5600 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 5601 | { |
0cca7907 ZA |
5602 | /* |
5603 | * Since this may be called from a hotplug notifcation, | |
5604 | * we can't get the CPU frequency directly. | |
5605 | */ | |
5606 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { | |
5607 | int cpu = raw_smp_processor_id(); | |
5608 | per_cpu(cpu_tsc_khz, cpu) = 0; | |
5609 | } | |
18863bdd AK |
5610 | |
5611 | kvm_shared_msr_cpu_online(); | |
5612 | ||
10474ae8 | 5613 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5614 | } |
5615 | ||
5616 | void kvm_arch_hardware_disable(void *garbage) | |
5617 | { | |
5618 | kvm_x86_ops->hardware_disable(garbage); | |
3548bab5 | 5619 | drop_user_return_notifiers(garbage); |
e9b11c17 ZX |
5620 | } |
5621 | ||
5622 | int kvm_arch_hardware_setup(void) | |
5623 | { | |
5624 | return kvm_x86_ops->hardware_setup(); | |
5625 | } | |
5626 | ||
5627 | void kvm_arch_hardware_unsetup(void) | |
5628 | { | |
5629 | kvm_x86_ops->hardware_unsetup(); | |
5630 | } | |
5631 | ||
5632 | void kvm_arch_check_processor_compat(void *rtn) | |
5633 | { | |
5634 | kvm_x86_ops->check_processor_compatibility(rtn); | |
5635 | } | |
5636 | ||
5637 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
5638 | { | |
5639 | struct page *page; | |
5640 | struct kvm *kvm; | |
5641 | int r; | |
5642 | ||
5643 | BUG_ON(vcpu->kvm == NULL); | |
5644 | kvm = vcpu->kvm; | |
5645 | ||
ad312c7c | 5646 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c5af89b6 | 5647 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 5648 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 5649 | else |
a4535290 | 5650 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
5651 | |
5652 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
5653 | if (!page) { | |
5654 | r = -ENOMEM; | |
5655 | goto fail; | |
5656 | } | |
ad312c7c | 5657 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
5658 | |
5659 | r = kvm_mmu_create(vcpu); | |
5660 | if (r < 0) | |
5661 | goto fail_free_pio_data; | |
5662 | ||
5663 | if (irqchip_in_kernel(kvm)) { | |
5664 | r = kvm_create_lapic(vcpu); | |
5665 | if (r < 0) | |
5666 | goto fail_mmu_destroy; | |
5667 | } | |
5668 | ||
890ca9ae HY |
5669 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
5670 | GFP_KERNEL); | |
5671 | if (!vcpu->arch.mce_banks) { | |
5672 | r = -ENOMEM; | |
443c39bc | 5673 | goto fail_free_lapic; |
890ca9ae HY |
5674 | } |
5675 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
5676 | ||
e9b11c17 | 5677 | return 0; |
443c39bc WY |
5678 | fail_free_lapic: |
5679 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
5680 | fail_mmu_destroy: |
5681 | kvm_mmu_destroy(vcpu); | |
5682 | fail_free_pio_data: | |
ad312c7c | 5683 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
5684 | fail: |
5685 | return r; | |
5686 | } | |
5687 | ||
5688 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
5689 | { | |
f656ce01 MT |
5690 | int idx; |
5691 | ||
36cb93fd | 5692 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 5693 | kvm_free_lapic(vcpu); |
f656ce01 | 5694 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 5695 | kvm_mmu_destroy(vcpu); |
f656ce01 | 5696 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 5697 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 5698 | } |
d19a9cd2 ZX |
5699 | |
5700 | struct kvm *kvm_arch_create_vm(void) | |
5701 | { | |
5702 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
5703 | ||
5704 | if (!kvm) | |
5705 | return ERR_PTR(-ENOMEM); | |
5706 | ||
fef9cce0 MT |
5707 | kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL); |
5708 | if (!kvm->arch.aliases) { | |
5709 | kfree(kvm); | |
5710 | return ERR_PTR(-ENOMEM); | |
5711 | } | |
5712 | ||
f05e70ac | 5713 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 5714 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 5715 | |
5550af4d SY |
5716 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
5717 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
5718 | ||
53f658b3 MT |
5719 | rdtscll(kvm->arch.vm_init_tsc); |
5720 | ||
d19a9cd2 ZX |
5721 | return kvm; |
5722 | } | |
5723 | ||
5724 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
5725 | { | |
5726 | vcpu_load(vcpu); | |
5727 | kvm_mmu_unload(vcpu); | |
5728 | vcpu_put(vcpu); | |
5729 | } | |
5730 | ||
5731 | static void kvm_free_vcpus(struct kvm *kvm) | |
5732 | { | |
5733 | unsigned int i; | |
988a2cae | 5734 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
5735 | |
5736 | /* | |
5737 | * Unpin any mmu pages first. | |
5738 | */ | |
988a2cae GN |
5739 | kvm_for_each_vcpu(i, vcpu, kvm) |
5740 | kvm_unload_vcpu_mmu(vcpu); | |
5741 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5742 | kvm_arch_vcpu_free(vcpu); | |
5743 | ||
5744 | mutex_lock(&kvm->lock); | |
5745 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
5746 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 5747 | |
988a2cae GN |
5748 | atomic_set(&kvm->online_vcpus, 0); |
5749 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
5750 | } |
5751 | ||
ad8ba2cd SY |
5752 | void kvm_arch_sync_events(struct kvm *kvm) |
5753 | { | |
ba4cef31 | 5754 | kvm_free_all_assigned_devices(kvm); |
ad8ba2cd SY |
5755 | } |
5756 | ||
d19a9cd2 ZX |
5757 | void kvm_arch_destroy_vm(struct kvm *kvm) |
5758 | { | |
6eb55818 | 5759 | kvm_iommu_unmap_guest(kvm); |
7837699f | 5760 | kvm_free_pit(kvm); |
d7deeeb0 ZX |
5761 | kfree(kvm->arch.vpic); |
5762 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
5763 | kvm_free_vcpus(kvm); |
5764 | kvm_free_physmem(kvm); | |
3d45830c AK |
5765 | if (kvm->arch.apic_access_page) |
5766 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
5767 | if (kvm->arch.ept_identity_pagetable) |
5768 | put_page(kvm->arch.ept_identity_pagetable); | |
64749204 | 5769 | cleanup_srcu_struct(&kvm->srcu); |
fef9cce0 | 5770 | kfree(kvm->arch.aliases); |
d19a9cd2 ZX |
5771 | kfree(kvm); |
5772 | } | |
0de10343 | 5773 | |
f7784b8e MT |
5774 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
5775 | struct kvm_memory_slot *memslot, | |
0de10343 | 5776 | struct kvm_memory_slot old, |
f7784b8e | 5777 | struct kvm_userspace_memory_region *mem, |
0de10343 ZX |
5778 | int user_alloc) |
5779 | { | |
f7784b8e | 5780 | int npages = memslot->npages; |
0de10343 ZX |
5781 | |
5782 | /*To keep backward compatibility with older userspace, | |
5783 | *x86 needs to hanlde !user_alloc case. | |
5784 | */ | |
5785 | if (!user_alloc) { | |
5786 | if (npages && !old.rmap) { | |
604b38ac AA |
5787 | unsigned long userspace_addr; |
5788 | ||
72dc67a6 | 5789 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
5790 | userspace_addr = do_mmap(NULL, 0, |
5791 | npages * PAGE_SIZE, | |
5792 | PROT_READ | PROT_WRITE, | |
acee3c04 | 5793 | MAP_PRIVATE | MAP_ANONYMOUS, |
604b38ac | 5794 | 0); |
72dc67a6 | 5795 | up_write(¤t->mm->mmap_sem); |
0de10343 | 5796 | |
604b38ac AA |
5797 | if (IS_ERR((void *)userspace_addr)) |
5798 | return PTR_ERR((void *)userspace_addr); | |
5799 | ||
604b38ac | 5800 | memslot->userspace_addr = userspace_addr; |
0de10343 ZX |
5801 | } |
5802 | } | |
5803 | ||
f7784b8e MT |
5804 | |
5805 | return 0; | |
5806 | } | |
5807 | ||
5808 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
5809 | struct kvm_userspace_memory_region *mem, | |
5810 | struct kvm_memory_slot old, | |
5811 | int user_alloc) | |
5812 | { | |
5813 | ||
5814 | int npages = mem->memory_size >> PAGE_SHIFT; | |
5815 | ||
5816 | if (!user_alloc && !old.user_alloc && old.rmap && !npages) { | |
5817 | int ret; | |
5818 | ||
5819 | down_write(¤t->mm->mmap_sem); | |
5820 | ret = do_munmap(current->mm, old.userspace_addr, | |
5821 | old.npages * PAGE_SIZE); | |
5822 | up_write(¤t->mm->mmap_sem); | |
5823 | if (ret < 0) | |
5824 | printk(KERN_WARNING | |
5825 | "kvm_vm_ioctl_set_memory_region: " | |
5826 | "failed to munmap memory\n"); | |
5827 | } | |
5828 | ||
7c8a83b7 | 5829 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 5830 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
5831 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
5832 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
5833 | } | |
5834 | ||
5835 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 5836 | spin_unlock(&kvm->mmu_lock); |
0de10343 | 5837 | } |
1d737c8a | 5838 | |
34d4cb8f MT |
5839 | void kvm_arch_flush_shadow(struct kvm *kvm) |
5840 | { | |
5841 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 5842 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
5843 | } |
5844 | ||
1d737c8a ZX |
5845 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
5846 | { | |
a4535290 | 5847 | return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE |
a1b37100 GN |
5848 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
5849 | || vcpu->arch.nmi_pending || | |
5850 | (kvm_arch_interrupt_allowed(vcpu) && | |
5851 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 5852 | } |
5736199a | 5853 | |
5736199a ZX |
5854 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
5855 | { | |
32f88400 MT |
5856 | int me; |
5857 | int cpu = vcpu->cpu; | |
5736199a ZX |
5858 | |
5859 | if (waitqueue_active(&vcpu->wq)) { | |
5860 | wake_up_interruptible(&vcpu->wq); | |
5861 | ++vcpu->stat.halt_wakeup; | |
5862 | } | |
32f88400 MT |
5863 | |
5864 | me = get_cpu(); | |
5865 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
5866 | if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests)) | |
5867 | smp_send_reschedule(cpu); | |
e9571ed5 | 5868 | put_cpu(); |
5736199a | 5869 | } |
78646121 GN |
5870 | |
5871 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
5872 | { | |
5873 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
5874 | } | |
229456fc | 5875 | |
f92653ee JK |
5876 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
5877 | { | |
5878 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
5879 | get_segment_base(vcpu, VCPU_SREG_CS); | |
5880 | ||
5881 | return current_rip == linear_rip; | |
5882 | } | |
5883 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
5884 | ||
94fe45da JK |
5885 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
5886 | { | |
5887 | unsigned long rflags; | |
5888 | ||
5889 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
5890 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 5891 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
5892 | return rflags; |
5893 | } | |
5894 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
5895 | ||
5896 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
5897 | { | |
5898 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 5899 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 5900 | rflags |= X86_EFLAGS_TF; |
94fe45da JK |
5901 | kvm_x86_ops->set_rflags(vcpu, rflags); |
5902 | } | |
5903 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
5904 | ||
229456fc MT |
5905 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
5906 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
5907 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
5908 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
5909 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 5910 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 5911 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 5912 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 5913 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 5914 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 5915 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 5916 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |