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KVM: move complete_insn_gp() into x86.c
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
db8fcefa
AP		 337void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
338{
339 if (err)
340 kvm_inject_gp(vcpu, 0);
341 else
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
343}
344EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
345
6389ee94 346void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 347{
348 ++vcpu->stat.pf_guest;
6389ee94
AK		 349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 351}
352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
3842d135 363 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 364 vcpu->arch.nmi_pending = 1;
365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
3d06b8bf
JR		 476 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
477 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073
JR		 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
522 vcpu->arch.cr3))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
e5f3f027
XG		 528 if ((cr0 ^ old_cr0) & X86_CR0_PG)
529 kvm_clear_async_pf_completion_queue(vcpu);
530
aad82703
SY		 531 if ((cr0 ^ old_cr0) & update_bits)
532 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 533 return 0;
534}
2d3ad1f4 535EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 536
2d3ad1f4 537void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 538{
49a9b07e 539 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 542
2acf923e
DC		 543int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
544{
545 u64 xcr0;
546
547 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
548 if (index != XCR_XFEATURE_ENABLED_MASK)
549 return 1;
550 xcr0 = xcr;
551 if (kvm_x86_ops->get_cpl(vcpu) != 0)
552 return 1;
553 if (!(xcr0 & XSTATE_FP))
554 return 1;
555 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
556 return 1;
557 if (xcr0 & ~host_xcr0)
558 return 1;
559 vcpu->arch.xcr0 = xcr0;
560 vcpu->guest_xcr0_loaded = 0;
561 return 0;
562}
563
564int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
565{
566 if (__kvm_set_xcr(vcpu, index, xcr)) {
567 kvm_inject_gp(vcpu, 0);
568 return 1;
569 }
570 return 0;
571}
572EXPORT_SYMBOL_GPL(kvm_set_xcr);
573
574static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
580}
581
582static void update_cpuid(struct kvm_vcpu *vcpu)
583{
584 struct kvm_cpuid_entry2 *best;
585
586 best = kvm_find_cpuid_entry(vcpu, 1, 0);
587 if (!best)
588 return;
589
590 /* Update OSXSAVE bit */
591 if (cpu_has_xsave && best->function == 0x1) {
592 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
593 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
594 best->ecx |= bit(X86_FEATURE_OSXSAVE);
595 }
596}
597
a83b29c6 598int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 599{
fc78f519 600 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 601 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
602
0f12244f
GN		 603 if (cr4 & CR4_RESERVED_BITS)
604 return 1;
a03490ed 605
2acf923e
DC		 606 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
607 return 1;
608
a03490ed 609 if (is_long_mode(vcpu)) {
0f12244f
GN		 610 if (!(cr4 & X86_CR4_PAE))
611 return 1;
a2edf57f
AK		 612 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
613 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 614 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 615 return 1;
616
617 if (cr4 & X86_CR4_VMXE)
618 return 1;
a03490ed 619
a03490ed 620 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 621
aad82703
SY		 622 if ((cr4 ^ old_cr4) & pdptr_bits)
623 kvm_mmu_reset_context(vcpu);
0f12244f 624
2acf923e
DC		 625 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
626 update_cpuid(vcpu);
627
0f12244f
GN		 628 return 0;
629}
2d3ad1f4 630EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 631
2390218b 632int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 633{
ad312c7c 634 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 635 kvm_mmu_sync_roots(vcpu);
d835dfec 636 kvm_mmu_flush_tlb(vcpu);
0f12244f 637 return 0;
d835dfec
AK		 638 }
639
a03490ed 640 if (is_long_mode(vcpu)) {
0f12244f
GN		 641 if (cr3 & CR3_L_MODE_RESERVED_BITS)
642 return 1;
a03490ed
CO		 643 } else {
644 if (is_pae(vcpu)) {
0f12244f
GN		 645 if (cr3 & CR3_PAE_RESERVED_BITS)
646 return 1;
ff03a073
JR		 647 if (is_paging(vcpu) &&
648 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 649 return 1;
a03490ed
CO		 650 }
651 /*
652 * We don't check reserved bits in nonpae mode, because
653 * this isn't enforced, and VMware depends on this.
654 */
655 }
656
a03490ed
CO		 657 /*
658 * Does the new cr3 value map to physical memory? (Note, we
659 * catch an invalid cr3 even in real-mode, because it would
660 * cause trouble later on when we turn on paging anyway.)
661 *
662 * A real CPU would silently accept an invalid cr3 and would
663 * attempt to use it - with largely undefined (and often hard
664 * to debug) behavior on the guest side.
665 */
666 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 667 return 1;
668 vcpu->arch.cr3 = cr3;
669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 673
eea1cff9 674int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 675{
0f12244f
GN		 676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
a03490ed
CO		 678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
ad312c7c 681 vcpu->arch.cr8 = cr8;
0f12244f
GN		 682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 685
2d3ad1f4 686unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 687{
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
ad312c7c 691 return vcpu->arch.cr8;
a03490ed 692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 694
338dbc97 695static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 696{
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
338dbc97
GN		 704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
020df079
GN		 706 /* fall through */
707 case 6:
338dbc97
GN		 708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
020df079
GN		 710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
338dbc97
GN		 713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
020df079
GN		 715 /* fall through */
716 default: /* 7 */
338dbc97
GN		 717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
020df079
GN		 719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728}
338dbc97
GN		 729
730int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731{
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741}
020df079
GN		 742EXPORT_SYMBOL_GPL(kvm_set_dr);
743
338dbc97 744static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 745{
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
338dbc97 751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 752 return 1;
020df079
GN		 753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
338dbc97 758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 759 return 1;
020df079
GN		 760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770{
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776}
020df079
GN		 777EXPORT_SYMBOL_GPL(kvm_get_dr);
778
043405e1
CO		 779/*
780 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
781 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
782 *
783 * This list is modified at module load time to reflect the
e3267cbb
GC		 784 * capabilities of the host cpu. This capabilities test skips MSRs that are
785 * kvm-specific. Those are put in the beginning of the list.
043405e1 786 */
e3267cbb 787
344d9588 788#define KVM_SAVE_MSRS_BEGIN 8
043405e1 789static u32 msrs_to_save[] = {
e3267cbb 790 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 791 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 792 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 793 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 794 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 795 MSR_STAR,
043405e1
CO		 796#ifdef CONFIG_X86_64
797 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
798#endif
e90aa41e 799 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 800};
801
802static unsigned num_msrs_to_save;
803
804static u32 emulated_msrs[] = {
805 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 806 MSR_IA32_MCG_STATUS,
807 MSR_IA32_MCG_CTL,
043405e1
CO		 808};
809
b69e8cae 810static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 811{
aad82703
SY		 812 u64 old_efer = vcpu->arch.efer;
813
b69e8cae
RJ		 814 if (efer & efer_reserved_bits)
815 return 1;
15c4a640
CO		 816
817 if (is_paging(vcpu)
b69e8cae
RJ		 818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 return 1;
15c4a640 820
1b2fd70c
AG		 821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
826 return 1;
1b2fd70c
AG		 827 }
828
d8017474
AG		 829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
831
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
834 return 1;
d8017474
AG		 835 }
836
15c4a640 837 efer &= ~EFER_LMA;
f6801dff 838 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 839
a3d204e2
SY		 840 kvm_x86_ops->set_efer(vcpu, efer);
841
9645bb56 842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 843
aad82703
SY		 844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
847
b69e8cae 848 return 0;
15c4a640
CO		 849}
850
f2b4b7dd
JR		 851void kvm_enable_efer_bits(u64 mask)
852{
853 efer_reserved_bits &= ~mask;
854}
855EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
856
857
15c4a640
CO		 858/*
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
862 */
863int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864{
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
866}
867
313a3dc7
CO		 868/*
869 * Adapt set_msr() to msr_io()'s calling convention
870 */
871static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872{
873 return kvm_set_msr(vcpu, index, *data);
874}
875
18068523
GOC		 876static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
877{
9ed3c444
AK		 878 int version;
879 int r;
50d0a0f9 880 struct pvclock_wall_clock wc;
923de3cf 881 struct timespec boot;
18068523
GOC		 882
883 if (!wall_clock)
884 return;
885
9ed3c444
AK		 886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 if (r)
888 return;
889
890 if (version & 1)
891 ++version; /* first time write, random junk */
892
893 ++version;
18068523 894
18068523
GOC		 895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
896
50d0a0f9
GH		 897 /*
898 * The guest calculates current wall clock time by adding
34c238a1 899 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
902 */
923de3cf 903 getboottime(&boot);
50d0a0f9
GH		 904
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
18068523
GOC		 908
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
910
911 version++;
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 913}
914
50d0a0f9
GH		 915static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916{
917 uint32_t quotient, remainder;
918
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
921 __asm__ ( "divl %4"
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
924 return quotient;
925}
926
5f4e3f88
ZA		 927static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
50d0a0f9 929{
5f4e3f88 930 uint64_t scaled64;
50d0a0f9
GH		 931 int32_t shift = 0;
932 uint64_t tps64;
933 uint32_t tps32;
934
5f4e3f88
ZA		 935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
50933623 937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
50933623
JK		 943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 945 scaled64 >>= 1;
946 else
947 tps32 <<= 1;
50d0a0f9
GH		 948 shift++;
949 }
950
5f4e3f88
ZA		 951 *pshift = shift;
952 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 953
5f4e3f88
ZA		 954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 956}
957
759379dd
ZA		 958static inline u64 get_kernel_ns(void)
959{
960 struct timespec ts;
961
962 WARN_ON(preemptible());
963 ktime_get_ts(&ts);
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
50d0a0f9
GH		 966}
967
c8076604 968static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 969unsigned long max_tsc_khz;
c8076604 970
8cfdc000
ZA		 971static inline int kvm_tsc_changes_freq(void)
972{
973 int cpu = get_cpu();
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
976 put_cpu();
977 return ret;
978}
979
759379dd
ZA		 980static inline u64 nsec_to_cycles(u64 nsec)
981{
217fc9cf
AK		 982 u64 ret;
983
759379dd
ZA		 984 WARN_ON(preemptible());
985 if (kvm_tsc_changes_freq())
986 printk_once(KERN_WARNING
987 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 988 ret = nsec * __get_cpu_var(cpu_tsc_khz);
989 do_div(ret, USEC_PER_SEC);
990 return ret;
759379dd
ZA		 991}
992
c285545f
ZA		 993static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
994{
995 /* Compute a scale to convert nanoseconds in TSC cycles */
996 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
997 &kvm->arch.virtual_tsc_shift,
998 &kvm->arch.virtual_tsc_mult);
999 kvm->arch.virtual_tsc_khz = this_tsc_khz;
1000}
1001
1002static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1003{
1004 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1005 vcpu->kvm->arch.virtual_tsc_mult,
1006 vcpu->kvm->arch.virtual_tsc_shift);
1007 tsc += vcpu->arch.last_tsc_write;
1008 return tsc;
1009}
1010
99e3e30a
ZA		 1011void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1012{
1013 struct kvm *kvm = vcpu->kvm;
f38e098f 1014 u64 offset, ns, elapsed;
99e3e30a 1015 unsigned long flags;
46543ba4 1016 s64 sdiff;
99e3e30a
ZA		 1017
1018 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1019 offset = data - native_read_tsc();
759379dd 1020 ns = get_kernel_ns();
f38e098f 1021 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1022 sdiff = data - kvm->arch.last_tsc_write;
1023 if (sdiff < 0)
1024 sdiff = -sdiff;
f38e098f
ZA		 1025
1026 /*
46543ba4 1027 * Special case: close write to TSC within 5 seconds of
f38e098f 1028 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1029 * The 5 seconds is to accomodate host load / swapping as
1030 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1031 *
1032 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1033 * or make a best guest using elapsed value.
f38e098f 1034 */
46543ba4
ZA		 1035 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1036 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1037 if (!check_tsc_unstable()) {
1038 offset = kvm->arch.last_tsc_offset;
1039 pr_debug("kvm: matched tsc offset for %llu\n", data);
1040 } else {
759379dd
ZA		 1041 u64 delta = nsec_to_cycles(elapsed);
1042 offset += delta;
1043 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1044 }
1045 ns = kvm->arch.last_tsc_nsec;
1046 }
1047 kvm->arch.last_tsc_nsec = ns;
1048 kvm->arch.last_tsc_write = data;
1049 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1050 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1051 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1052
1053 /* Reset of TSC must disable overshoot protection below */
1054 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1055 vcpu->arch.last_tsc_write = data;
1056 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1057}
1058EXPORT_SYMBOL_GPL(kvm_write_tsc);
1059
34c238a1 1060static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1061{
18068523
GOC		 1062 unsigned long flags;
1063 struct kvm_vcpu_arch *vcpu = &v->arch;
1064 void *shared_kaddr;
463656c0 1065 unsigned long this_tsc_khz;
1d5f066e
ZA		 1066 s64 kernel_ns, max_kernel_ns;
1067 u64 tsc_timestamp;
18068523 1068
18068523
GOC		 1069 /* Keep irq disabled to prevent changes to the clock */
1070 local_irq_save(flags);
1d5f066e 1071 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1072 kernel_ns = get_kernel_ns();
8cfdc000 1073 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1074
8cfdc000 1075 if (unlikely(this_tsc_khz == 0)) {
c285545f 1076 local_irq_restore(flags);
34c238a1 1077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1078 return 1;
1079 }
18068523 1080
c285545f
ZA		 1081 /*
1082 * We may have to catch up the TSC to match elapsed wall clock
1083 * time for two reasons, even if kvmclock is used.
1084 * 1) CPU could have been running below the maximum TSC rate
1085 * 2) Broken TSC compensation resets the base at each VCPU
1086 * entry to avoid unknown leaps of TSC even when running
1087 * again on the same CPU. This may cause apparent elapsed
1088 * time to disappear, and the guest to stand still or run
1089 * very slowly.
1090 */
1091 if (vcpu->tsc_catchup) {
1092 u64 tsc = compute_guest_tsc(v, kernel_ns);
1093 if (tsc > tsc_timestamp) {
1094 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1095 tsc_timestamp = tsc;
1096 }
50d0a0f9
GH		 1097 }
1098
18068523
GOC		 1099 local_irq_restore(flags);
1100
c285545f
ZA		 1101 if (!vcpu->time_page)
1102 return 0;
18068523 1103
1d5f066e
ZA		 1104 /*
1105 * Time as measured by the TSC may go backwards when resetting the base
1106 * tsc_timestamp. The reason for this is that the TSC resolution is
1107 * higher than the resolution of the other clock scales. Thus, many
1108 * possible measurments of the TSC correspond to one measurement of any
1109 * other clock, and so a spread of values is possible. This is not a
1110 * problem for the computation of the nanosecond clock; with TSC rates
1111 * around 1GHZ, there can only be a few cycles which correspond to one
1112 * nanosecond value, and any path through this code will inevitably
1113 * take longer than that. However, with the kernel_ns value itself,
1114 * the precision may be much lower, down to HZ granularity. If the
1115 * first sampling of TSC against kernel_ns ends in the low part of the
1116 * range, and the second in the high end of the range, we can get:
1117 *
1118 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1119 *
1120 * As the sampling errors potentially range in the thousands of cycles,
1121 * it is possible such a time value has already been observed by the
1122 * guest. To protect against this, we must compute the system time as
1123 * observed by the guest and ensure the new system time is greater.
1124 */
1125 max_kernel_ns = 0;
1126 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1127 max_kernel_ns = vcpu->last_guest_tsc -
1128 vcpu->hv_clock.tsc_timestamp;
1129 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1130 vcpu->hv_clock.tsc_to_system_mul,
1131 vcpu->hv_clock.tsc_shift);
1132 max_kernel_ns += vcpu->last_kernel_ns;
1133 }
afbcf7ab 1134
e48672fa 1135 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1136 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1137 &vcpu->hv_clock.tsc_shift,
1138 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1139 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1140 }
1141
1d5f066e
ZA		 1142 if (max_kernel_ns > kernel_ns)
1143 kernel_ns = max_kernel_ns;
1144
8cfdc000 1145 /* With all the info we got, fill in the values */
1d5f066e 1146 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1147 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1148 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1149 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1150 vcpu->hv_clock.flags = 0;
1151
18068523
GOC		 1152 /*
1153 * The interface expects us to write an even number signaling that the
1154 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1155 * state, we just increase by 2 at the end.
18068523 1156 */
50d0a0f9 1157 vcpu->hv_clock.version += 2;
18068523
GOC		 1158
1159 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1160
1161 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1162 sizeof(vcpu->hv_clock));
18068523
GOC		 1163
1164 kunmap_atomic(shared_kaddr, KM_USER0);
1165
1166 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1167 return 0;
c8076604
GH		 1168}
1169
9ba075a6
AK		 1170static bool msr_mtrr_valid(unsigned msr)
1171{
1172 switch (msr) {
1173 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1174 case MSR_MTRRfix64K_00000:
1175 case MSR_MTRRfix16K_80000:
1176 case MSR_MTRRfix16K_A0000:
1177 case MSR_MTRRfix4K_C0000:
1178 case MSR_MTRRfix4K_C8000:
1179 case MSR_MTRRfix4K_D0000:
1180 case MSR_MTRRfix4K_D8000:
1181 case MSR_MTRRfix4K_E0000:
1182 case MSR_MTRRfix4K_E8000:
1183 case MSR_MTRRfix4K_F0000:
1184 case MSR_MTRRfix4K_F8000:
1185 case MSR_MTRRdefType:
1186 case MSR_IA32_CR_PAT:
1187 return true;
1188 case 0x2f8:
1189 return true;
1190 }
1191 return false;
1192}
1193
d6289b93
MT		 1194static bool valid_pat_type(unsigned t)
1195{
1196 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1197}
1198
1199static bool valid_mtrr_type(unsigned t)
1200{
1201 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1202}
1203
1204static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1205{
1206 int i;
1207
1208 if (!msr_mtrr_valid(msr))
1209 return false;
1210
1211 if (msr == MSR_IA32_CR_PAT) {
1212 for (i = 0; i < 8; i++)
1213 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1214 return false;
1215 return true;
1216 } else if (msr == MSR_MTRRdefType) {
1217 if (data & ~0xcff)
1218 return false;
1219 return valid_mtrr_type(data & 0xff);
1220 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1221 for (i = 0; i < 8 ; i++)
1222 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1223 return false;
1224 return true;
1225 }
1226
1227 /* variable MTRRs */
1228 return valid_mtrr_type(data & 0xff);
1229}
1230
9ba075a6
AK		 1231static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1232{
0bed3b56
SY		 1233 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1234
d6289b93 1235 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1236 return 1;
1237
0bed3b56
SY		 1238 if (msr == MSR_MTRRdefType) {
1239 vcpu->arch.mtrr_state.def_type = data;
1240 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1241 } else if (msr == MSR_MTRRfix64K_00000)
1242 p[0] = data;
1243 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1244 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1245 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1246 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1247 else if (msr == MSR_IA32_CR_PAT)
1248 vcpu->arch.pat = data;
1249 else { /* Variable MTRRs */
1250 int idx, is_mtrr_mask;
1251 u64 *pt;
1252
1253 idx = (msr - 0x200) / 2;
1254 is_mtrr_mask = msr - 0x200 - 2 * idx;
1255 if (!is_mtrr_mask)
1256 pt =
1257 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1258 else
1259 pt =
1260 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1261 *pt = data;
1262 }
1263
1264 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1265 return 0;
1266}
15c4a640 1267
890ca9ae 1268static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1269{
890ca9ae
HY		 1270 u64 mcg_cap = vcpu->arch.mcg_cap;
1271 unsigned bank_num = mcg_cap & 0xff;
1272
15c4a640 1273 switch (msr) {
15c4a640 1274 case MSR_IA32_MCG_STATUS:
890ca9ae 1275 vcpu->arch.mcg_status = data;
15c4a640 1276 break;
c7ac679c 1277 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1278 if (!(mcg_cap & MCG_CTL_P))
1279 return 1;
1280 if (data != 0 && data != ~(u64)0)
1281 return -1;
1282 vcpu->arch.mcg_ctl = data;
1283 break;
1284 default:
1285 if (msr >= MSR_IA32_MC0_CTL &&
1286 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1287 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1288 /* only 0 or all 1s can be written to IA32_MCi_CTL
1289 * some Linux kernels though clear bit 10 in bank 4 to
1290 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1291 * this to avoid an uncatched #GP in the guest
1292 */
890ca9ae 1293 if ((offset & 0x3) == 0 &&
114be429 1294 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1295 return -1;
1296 vcpu->arch.mce_banks[offset] = data;
1297 break;
1298 }
1299 return 1;
1300 }
1301 return 0;
1302}
1303
ffde22ac
ES		 1304static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1305{
1306 struct kvm *kvm = vcpu->kvm;
1307 int lm = is_long_mode(vcpu);
1308 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1309 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1310 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1311 : kvm->arch.xen_hvm_config.blob_size_32;
1312 u32 page_num = data & ~PAGE_MASK;
1313 u64 page_addr = data & PAGE_MASK;
1314 u8 *page;
1315 int r;
1316
1317 r = -E2BIG;
1318 if (page_num >= blob_size)
1319 goto out;
1320 r = -ENOMEM;
1321 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1322 if (!page)
1323 goto out;
1324 r = -EFAULT;
1325 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1326 goto out_free;
1327 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1328 goto out_free;
1329 r = 0;
1330out_free:
1331 kfree(page);
1332out:
1333 return r;
1334}
1335
55cd8e5a
GN		 1336static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1337{
1338 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1339}
1340
1341static bool kvm_hv_msr_partition_wide(u32 msr)
1342{
1343 bool r = false;
1344 switch (msr) {
1345 case HV_X64_MSR_GUEST_OS_ID:
1346 case HV_X64_MSR_HYPERCALL:
1347 r = true;
1348 break;
1349 }
1350
1351 return r;
1352}
1353
1354static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1355{
1356 struct kvm *kvm = vcpu->kvm;
1357
1358 switch (msr) {
1359 case HV_X64_MSR_GUEST_OS_ID:
1360 kvm->arch.hv_guest_os_id = data;
1361 /* setting guest os id to zero disables hypercall page */
1362 if (!kvm->arch.hv_guest_os_id)
1363 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1364 break;
1365 case HV_X64_MSR_HYPERCALL: {
1366 u64 gfn;
1367 unsigned long addr;
1368 u8 instructions[4];
1369
1370 /* if guest os id is not set hypercall should remain disabled */
1371 if (!kvm->arch.hv_guest_os_id)
1372 break;
1373 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1374 kvm->arch.hv_hypercall = data;
1375 break;
1376 }
1377 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1378 addr = gfn_to_hva(kvm, gfn);
1379 if (kvm_is_error_hva(addr))
1380 return 1;
1381 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1382 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1383 if (copy_to_user((void __user *)addr, instructions, 4))
1384 return 1;
1385 kvm->arch.hv_hypercall = data;
1386 break;
1387 }
1388 default:
1389 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1390 "data 0x%llx\n", msr, data);
1391 return 1;
1392 }
1393 return 0;
1394}
1395
1396static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1397{
10388a07
GN		 1398 switch (msr) {
1399 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1400 unsigned long addr;
55cd8e5a 1401
10388a07
GN		 1402 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1403 vcpu->arch.hv_vapic = data;
1404 break;
1405 }
1406 addr = gfn_to_hva(vcpu->kvm, data >>
1407 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1408 if (kvm_is_error_hva(addr))
1409 return 1;
1410 if (clear_user((void __user *)addr, PAGE_SIZE))
1411 return 1;
1412 vcpu->arch.hv_vapic = data;
1413 break;
1414 }
1415 case HV_X64_MSR_EOI:
1416 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1417 case HV_X64_MSR_ICR:
1418 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1419 case HV_X64_MSR_TPR:
1420 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1421 default:
1422 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1423 "data 0x%llx\n", msr, data);
1424 return 1;
1425 }
1426
1427 return 0;
55cd8e5a
GN		 1428}
1429
344d9588
GN		 1430static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1431{
1432 gpa_t gpa = data & ~0x3f;
1433
6adba527
GN		 1434 /* Bits 2:5 are resrved, Should be zero */
1435 if (data & 0x3c)
344d9588
GN		 1436 return 1;
1437
1438 vcpu->arch.apf.msr_val = data;
1439
1440 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1441 kvm_clear_async_pf_completion_queue(vcpu);
1442 kvm_async_pf_hash_reset(vcpu);
1443 return 0;
1444 }
1445
1446 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1447 return 1;
1448
6adba527 1449 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1450 kvm_async_pf_wakeup_all(vcpu);
1451 return 0;
1452}
1453
15c4a640
CO		 1454int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1455{
1456 switch (msr) {
15c4a640 1457 case MSR_EFER:
b69e8cae 1458 return set_efer(vcpu, data);
8f1589d9
AP		 1459 case MSR_K7_HWCR:
1460 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1461 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1462 if (data != 0) {
1463 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1464 data);
1465 return 1;
1466 }
15c4a640 1467 break;
f7c6d140
AP		 1468 case MSR_FAM10H_MMIO_CONF_BASE:
1469 if (data != 0) {
1470 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1471 "0x%llx\n", data);
1472 return 1;
1473 }
15c4a640 1474 break;
c323c0e5 1475 case MSR_AMD64_NB_CFG:
c7ac679c 1476 break;
b5e2fec0
AG		 1477 case MSR_IA32_DEBUGCTLMSR:
1478 if (!data) {
1479 /* We support the non-activated case already */
1480 break;
1481 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1482 /* Values other than LBR and BTF are vendor-specific,
1483 thus reserved and should throw a #GP */
1484 return 1;
1485 }
1486 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1487 __func__, data);
1488 break;
15c4a640
CO		 1489 case MSR_IA32_UCODE_REV:
1490 case MSR_IA32_UCODE_WRITE:
61a6bd67 1491 case MSR_VM_HSAVE_PA:
6098ca93 1492 case MSR_AMD64_PATCH_LOADER:
15c4a640 1493 break;
9ba075a6
AK		 1494 case 0x200 ... 0x2ff:
1495 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1496 case MSR_IA32_APICBASE:
1497 kvm_set_apic_base(vcpu, data);
1498 break;
0105d1a5
GN		 1499 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1500 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1501 case MSR_IA32_MISC_ENABLE:
ad312c7c 1502 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1503 break;
11c6bffa 1504 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1505 case MSR_KVM_WALL_CLOCK:
1506 vcpu->kvm->arch.wall_clock = data;
1507 kvm_write_wall_clock(vcpu->kvm, data);
1508 break;
11c6bffa 1509 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1510 case MSR_KVM_SYSTEM_TIME: {
1511 if (vcpu->arch.time_page) {
1512 kvm_release_page_dirty(vcpu->arch.time_page);
1513 vcpu->arch.time_page = NULL;
1514 }
1515
1516 vcpu->arch.time = data;
c285545f 1517 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1518
1519 /* we verify if the enable bit is set... */
1520 if (!(data & 1))
1521 break;
1522
1523 /* ...but clean it before doing the actual write */
1524 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1525
18068523
GOC		 1526 vcpu->arch.time_page =
1527 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1528
1529 if (is_error_page(vcpu->arch.time_page)) {
1530 kvm_release_page_clean(vcpu->arch.time_page);
1531 vcpu->arch.time_page = NULL;
1532 }
18068523
GOC		 1533 break;
1534 }
344d9588
GN		 1535 case MSR_KVM_ASYNC_PF_EN:
1536 if (kvm_pv_enable_async_pf(vcpu, data))
1537 return 1;
1538 break;
890ca9ae
HY		 1539 case MSR_IA32_MCG_CTL:
1540 case MSR_IA32_MCG_STATUS:
1541 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1542 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1543
1544 /* Performance counters are not protected by a CPUID bit,
1545 * so we should check all of them in the generic path for the sake of
1546 * cross vendor migration.
1547 * Writing a zero into the event select MSRs disables them,
1548 * which we perfectly emulate ;-). Any other value should be at least
1549 * reported, some guests depend on them.
1550 */
1551 case MSR_P6_EVNTSEL0:
1552 case MSR_P6_EVNTSEL1:
1553 case MSR_K7_EVNTSEL0:
1554 case MSR_K7_EVNTSEL1:
1555 case MSR_K7_EVNTSEL2:
1556 case MSR_K7_EVNTSEL3:
1557 if (data != 0)
1558 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1559 "0x%x data 0x%llx\n", msr, data);
1560 break;
1561 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1562 * so we ignore writes to make it happy.
1563 */
1564 case MSR_P6_PERFCTR0:
1565 case MSR_P6_PERFCTR1:
1566 case MSR_K7_PERFCTR0:
1567 case MSR_K7_PERFCTR1:
1568 case MSR_K7_PERFCTR2:
1569 case MSR_K7_PERFCTR3:
1570 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1571 "0x%x data 0x%llx\n", msr, data);
1572 break;
84e0cefa
JS		 1573 case MSR_K7_CLK_CTL:
1574 /*
1575 * Ignore all writes to this no longer documented MSR.
1576 * Writes are only relevant for old K7 processors,
1577 * all pre-dating SVM, but a recommended workaround from
1578 * AMD for these chips. It is possible to speicify the
1579 * affected processor models on the command line, hence
1580 * the need to ignore the workaround.
1581 */
1582 break;
55cd8e5a
GN		 1583 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1584 if (kvm_hv_msr_partition_wide(msr)) {
1585 int r;
1586 mutex_lock(&vcpu->kvm->lock);
1587 r = set_msr_hyperv_pw(vcpu, msr, data);
1588 mutex_unlock(&vcpu->kvm->lock);
1589 return r;
1590 } else
1591 return set_msr_hyperv(vcpu, msr, data);
1592 break;
15c4a640 1593 default:
ffde22ac
ES		 1594 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1595 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1596 if (!ignore_msrs) {
1597 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1598 msr, data);
1599 return 1;
1600 } else {
1601 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1602 msr, data);
1603 break;
1604 }
15c4a640
CO		 1605 }
1606 return 0;
1607}
1608EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1609
1610
1611/*
1612 * Reads an msr value (of 'msr_index') into 'pdata'.
1613 * Returns 0 on success, non-0 otherwise.
1614 * Assumes vcpu_load() was already called.
1615 */
1616int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1617{
1618 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1619}
1620
9ba075a6
AK		 1621static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1622{
0bed3b56
SY		 1623 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1624
9ba075a6
AK		 1625 if (!msr_mtrr_valid(msr))
1626 return 1;
1627
0bed3b56
SY		 1628 if (msr == MSR_MTRRdefType)
1629 *pdata = vcpu->arch.mtrr_state.def_type +
1630 (vcpu->arch.mtrr_state.enabled << 10);
1631 else if (msr == MSR_MTRRfix64K_00000)
1632 *pdata = p[0];
1633 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1634 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1635 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1636 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1637 else if (msr == MSR_IA32_CR_PAT)
1638 *pdata = vcpu->arch.pat;
1639 else { /* Variable MTRRs */
1640 int idx, is_mtrr_mask;
1641 u64 *pt;
1642
1643 idx = (msr - 0x200) / 2;
1644 is_mtrr_mask = msr - 0x200 - 2 * idx;
1645 if (!is_mtrr_mask)
1646 pt =
1647 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1648 else
1649 pt =
1650 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1651 *pdata = *pt;
1652 }
1653
9ba075a6
AK		 1654 return 0;
1655}
1656
890ca9ae 1657static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1658{
1659 u64 data;
890ca9ae
HY		 1660 u64 mcg_cap = vcpu->arch.mcg_cap;
1661 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1662
1663 switch (msr) {
15c4a640
CO		 1664 case MSR_IA32_P5_MC_ADDR:
1665 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1666 data = 0;
1667 break;
15c4a640 1668 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1669 data = vcpu->arch.mcg_cap;
1670 break;
c7ac679c 1671 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1672 if (!(mcg_cap & MCG_CTL_P))
1673 return 1;
1674 data = vcpu->arch.mcg_ctl;
1675 break;
1676 case MSR_IA32_MCG_STATUS:
1677 data = vcpu->arch.mcg_status;
1678 break;
1679 default:
1680 if (msr >= MSR_IA32_MC0_CTL &&
1681 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1682 u32 offset = msr - MSR_IA32_MC0_CTL;
1683 data = vcpu->arch.mce_banks[offset];
1684 break;
1685 }
1686 return 1;
1687 }
1688 *pdata = data;
1689 return 0;
1690}
1691
55cd8e5a
GN		 1692static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1693{
1694 u64 data = 0;
1695 struct kvm *kvm = vcpu->kvm;
1696
1697 switch (msr) {
1698 case HV_X64_MSR_GUEST_OS_ID:
1699 data = kvm->arch.hv_guest_os_id;
1700 break;
1701 case HV_X64_MSR_HYPERCALL:
1702 data = kvm->arch.hv_hypercall;
1703 break;
1704 default:
1705 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1706 return 1;
1707 }
1708
1709 *pdata = data;
1710 return 0;
1711}
1712
1713static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1714{
1715 u64 data = 0;
1716
1717 switch (msr) {
1718 case HV_X64_MSR_VP_INDEX: {
1719 int r;
1720 struct kvm_vcpu *v;
1721 kvm_for_each_vcpu(r, v, vcpu->kvm)
1722 if (v == vcpu)
1723 data = r;
1724 break;
1725 }
10388a07
GN		 1726 case HV_X64_MSR_EOI:
1727 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1728 case HV_X64_MSR_ICR:
1729 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1730 case HV_X64_MSR_TPR:
1731 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1732 default:
1733 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1734 return 1;
1735 }
1736 *pdata = data;
1737 return 0;
1738}
1739
890ca9ae
HY		 1740int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1741{
1742 u64 data;
1743
1744 switch (msr) {
890ca9ae 1745 case MSR_IA32_PLATFORM_ID:
15c4a640 1746 case MSR_IA32_UCODE_REV:
15c4a640 1747 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1748 case MSR_IA32_DEBUGCTLMSR:
1749 case MSR_IA32_LASTBRANCHFROMIP:
1750 case MSR_IA32_LASTBRANCHTOIP:
1751 case MSR_IA32_LASTINTFROMIP:
1752 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1753 case MSR_K8_SYSCFG:
1754 case MSR_K7_HWCR:
61a6bd67 1755 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1756 case MSR_P6_PERFCTR0:
1757 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1758 case MSR_P6_EVNTSEL0:
1759 case MSR_P6_EVNTSEL1:
9e699624 1760 case MSR_K7_EVNTSEL0:
1f3ee616 1761 case MSR_K7_PERFCTR0:
1fdbd48c 1762 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1763 case MSR_AMD64_NB_CFG:
f7c6d140 1764 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1765 data = 0;
1766 break;
9ba075a6
AK		 1767 case MSR_MTRRcap:
1768 data = 0x500 | KVM_NR_VAR_MTRR;
1769 break;
1770 case 0x200 ... 0x2ff:
1771 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1772 case 0xcd: /* fsb frequency */
1773 data = 3;
1774 break;
7b914098
JS		 1775 /*
1776 * MSR_EBC_FREQUENCY_ID
1777 * Conservative value valid for even the basic CPU models.
1778 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1779 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1780 * and 266MHz for model 3, or 4. Set Core Clock
1781 * Frequency to System Bus Frequency Ratio to 1 (bits
1782 * 31:24) even though these are only valid for CPU
1783 * models > 2, however guests may end up dividing or
1784 * multiplying by zero otherwise.
1785 */
1786 case MSR_EBC_FREQUENCY_ID:
1787 data = 1 << 24;
1788 break;
15c4a640
CO		 1789 case MSR_IA32_APICBASE:
1790 data = kvm_get_apic_base(vcpu);
1791 break;
0105d1a5
GN		 1792 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1793 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1794 break;
15c4a640 1795 case MSR_IA32_MISC_ENABLE:
ad312c7c 1796 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1797 break;
847f0ad8
AG		 1798 case MSR_IA32_PERF_STATUS:
1799 /* TSC increment by tick */
1800 data = 1000ULL;
1801 /* CPU multiplier */
1802 data |= (((uint64_t)4ULL) << 40);
1803 break;
15c4a640 1804 case MSR_EFER:
f6801dff 1805 data = vcpu->arch.efer;
15c4a640 1806 break;
18068523 1807 case MSR_KVM_WALL_CLOCK:
11c6bffa 1808 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1809 data = vcpu->kvm->arch.wall_clock;
1810 break;
1811 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1812 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1813 data = vcpu->arch.time;
1814 break;
344d9588
GN		 1815 case MSR_KVM_ASYNC_PF_EN:
1816 data = vcpu->arch.apf.msr_val;
1817 break;
890ca9ae
HY		 1818 case MSR_IA32_P5_MC_ADDR:
1819 case MSR_IA32_P5_MC_TYPE:
1820 case MSR_IA32_MCG_CAP:
1821 case MSR_IA32_MCG_CTL:
1822 case MSR_IA32_MCG_STATUS:
1823 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1824 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1825 case MSR_K7_CLK_CTL:
1826 /*
1827 * Provide expected ramp-up count for K7. All other
1828 * are set to zero, indicating minimum divisors for
1829 * every field.
1830 *
1831 * This prevents guest kernels on AMD host with CPU
1832 * type 6, model 8 and higher from exploding due to
1833 * the rdmsr failing.
1834 */
1835 data = 0x20000000;
1836 break;
55cd8e5a
GN		 1837 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1838 if (kvm_hv_msr_partition_wide(msr)) {
1839 int r;
1840 mutex_lock(&vcpu->kvm->lock);
1841 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1842 mutex_unlock(&vcpu->kvm->lock);
1843 return r;
1844 } else
1845 return get_msr_hyperv(vcpu, msr, pdata);
1846 break;
15c4a640 1847 default:
ed85c068
AP		 1848 if (!ignore_msrs) {
1849 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1850 return 1;
1851 } else {
1852 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1853 data = 0;
1854 }
1855 break;
15c4a640
CO		 1856 }
1857 *pdata = data;
1858 return 0;
1859}
1860EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1861
313a3dc7
CO		 1862/*
1863 * Read or write a bunch of msrs. All parameters are kernel addresses.
1864 *
1865 * @return number of msrs set successfully.
1866 */
1867static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1868 struct kvm_msr_entry *entries,
1869 int (*do_msr)(struct kvm_vcpu *vcpu,
1870 unsigned index, u64 *data))
1871{
f656ce01 1872 int i, idx;
313a3dc7 1873
f656ce01 1874 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1875 for (i = 0; i < msrs->nmsrs; ++i)
1876 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1877 break;
f656ce01 1878 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1879
313a3dc7
CO		 1880 return i;
1881}
1882
1883/*
1884 * Read or write a bunch of msrs. Parameters are user addresses.
1885 *
1886 * @return number of msrs set successfully.
1887 */
1888static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1889 int (*do_msr)(struct kvm_vcpu *vcpu,
1890 unsigned index, u64 *data),
1891 int writeback)
1892{
1893 struct kvm_msrs msrs;
1894 struct kvm_msr_entry *entries;
1895 int r, n;
1896 unsigned size;
1897
1898 r = -EFAULT;
1899 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1900 goto out;
1901
1902 r = -E2BIG;
1903 if (msrs.nmsrs >= MAX_IO_MSRS)
1904 goto out;
1905
1906 r = -ENOMEM;
1907 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1908 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1909 if (!entries)
1910 goto out;
1911
1912 r = -EFAULT;
1913 if (copy_from_user(entries, user_msrs->entries, size))
1914 goto out_free;
1915
1916 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1917 if (r < 0)
1918 goto out_free;
1919
1920 r = -EFAULT;
1921 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1922 goto out_free;
1923
1924 r = n;
1925
1926out_free:
7a73c028 1927 kfree(entries);
313a3dc7
CO		 1928out:
1929 return r;
1930}
1931
018d00d2
ZX		 1932int kvm_dev_ioctl_check_extension(long ext)
1933{
1934 int r;
1935
1936 switch (ext) {
1937 case KVM_CAP_IRQCHIP:
1938 case KVM_CAP_HLT:
1939 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1940 case KVM_CAP_SET_TSS_ADDR:
07716717 1941 case KVM_CAP_EXT_CPUID:
c8076604 1942 case KVM_CAP_CLOCKSOURCE:
7837699f 1943 case KVM_CAP_PIT:
a28e4f5a 1944 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1945 case KVM_CAP_MP_STATE:
ed848624 1946 case KVM_CAP_SYNC_MMU:
a355c85c 1947 case KVM_CAP_USER_NMI:
52d939a0 1948 case KVM_CAP_REINJECT_CONTROL:
4925663a 1949 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1950 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1951 case KVM_CAP_IRQFD:
d34e6b17 1952 case KVM_CAP_IOEVENTFD:
c5ff41ce 1953 case KVM_CAP_PIT2:
e9f42757 1954 case KVM_CAP_PIT_STATE2:
b927a3ce 1955 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1956 case KVM_CAP_XEN_HVM:
afbcf7ab 1957 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1958 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1959 case KVM_CAP_HYPERV:
10388a07 1960 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1961 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1962 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1963 case KVM_CAP_DEBUGREGS:
d2be1651 1964 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1965 case KVM_CAP_XSAVE:
344d9588 1966 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1967 r = 1;
1968 break;
542472b5
LV		 1969 case KVM_CAP_COALESCED_MMIO:
1970 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1971 break;
774ead3a
AK		 1972 case KVM_CAP_VAPIC:
1973 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1974 break;
f725230a
AK		 1975 case KVM_CAP_NR_VCPUS:
1976 r = KVM_MAX_VCPUS;
1977 break;
a988b910
AK		 1978 case KVM_CAP_NR_MEMSLOTS:
1979 r = KVM_MEMORY_SLOTS;
1980 break;
a68a6a72
MT		 1981 case KVM_CAP_PV_MMU: /* obsolete */
1982 r = 0;
2f333bcb 1983 break;
62c476c7 1984 case KVM_CAP_IOMMU:
19de40a8 1985 r = iommu_found();
62c476c7 1986 break;
890ca9ae
HY		 1987 case KVM_CAP_MCE:
1988 r = KVM_MAX_MCE_BANKS;
1989 break;
2d5b5a66
SY		 1990 case KVM_CAP_XCRS:
1991 r = cpu_has_xsave;
1992 break;
018d00d2
ZX		 1993 default:
1994 r = 0;
1995 break;
1996 }
1997 return r;
1998
1999}
2000
043405e1
CO		 2001long kvm_arch_dev_ioctl(struct file *filp,
2002 unsigned int ioctl, unsigned long arg)
2003{
2004 void __user *argp = (void __user *)arg;
2005 long r;
2006
2007 switch (ioctl) {
2008 case KVM_GET_MSR_INDEX_LIST: {
2009 struct kvm_msr_list __user *user_msr_list = argp;
2010 struct kvm_msr_list msr_list;
2011 unsigned n;
2012
2013 r = -EFAULT;
2014 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2015 goto out;
2016 n = msr_list.nmsrs;
2017 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2018 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2019 goto out;
2020 r = -E2BIG;
e125e7b6 2021 if (n < msr_list.nmsrs)
043405e1
CO		 2022 goto out;
2023 r = -EFAULT;
2024 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2025 num_msrs_to_save * sizeof(u32)))
2026 goto out;
e125e7b6 2027 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2028 &emulated_msrs,
2029 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2030 goto out;
2031 r = 0;
2032 break;
2033 }
674eea0f
AK		 2034 case KVM_GET_SUPPORTED_CPUID: {
2035 struct kvm_cpuid2 __user *cpuid_arg = argp;
2036 struct kvm_cpuid2 cpuid;
2037
2038 r = -EFAULT;
2039 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2040 goto out;
2041 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2042 cpuid_arg->entries);
674eea0f
AK		 2043 if (r)
2044 goto out;
2045
2046 r = -EFAULT;
2047 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2048 goto out;
2049 r = 0;
2050 break;
2051 }
890ca9ae
HY		 2052 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2053 u64 mce_cap;
2054
2055 mce_cap = KVM_MCE_CAP_SUPPORTED;
2056 r = -EFAULT;
2057 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2058 goto out;
2059 r = 0;
2060 break;
2061 }
043405e1
CO		 2062 default:
2063 r = -EINVAL;
2064 }
2065out:
2066 return r;
2067}
2068
f5f48ee1
SY		 2069static void wbinvd_ipi(void *garbage)
2070{
2071 wbinvd();
2072}
2073
2074static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2075{
2076 return vcpu->kvm->arch.iommu_domain &&
2077 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2078}
2079
313a3dc7
CO		 2080void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2081{
f5f48ee1
SY		 2082 /* Address WBINVD may be executed by guest */
2083 if (need_emulate_wbinvd(vcpu)) {
2084 if (kvm_x86_ops->has_wbinvd_exit())
2085 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2086 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2087 smp_call_function_single(vcpu->cpu,
2088 wbinvd_ipi, NULL, 1);
2089 }
2090
313a3dc7 2091 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2092 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2093 /* Make sure TSC doesn't go backwards */
2094 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2095 native_read_tsc() - vcpu->arch.last_host_tsc;
2096 if (tsc_delta < 0)
2097 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2098 if (check_tsc_unstable()) {
e48672fa 2099 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2100 vcpu->arch.tsc_catchup = 1;
2101 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2102 }
2103 if (vcpu->cpu != cpu)
2104 kvm_migrate_timers(vcpu);
e48672fa 2105 vcpu->cpu = cpu;
6b7d7e76 2106 }
313a3dc7
CO		 2107}
2108
2109void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2110{
02daab21 2111 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2112 kvm_put_guest_fpu(vcpu);
e48672fa 2113 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2114}
2115
07716717 2116static int is_efer_nx(void)
313a3dc7 2117{
e286e86e 2118 unsigned long long efer = 0;
313a3dc7 2119
e286e86e 2120 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2121 return efer & EFER_NX;
2122}
2123
2124static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2125{
2126 int i;
2127 struct kvm_cpuid_entry2 *e, *entry;
2128
313a3dc7 2129 entry = NULL;
ad312c7c
ZX		 2130 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2131 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2132 if (e->function == 0x80000001) {
2133 entry = e;
2134 break;
2135 }
2136 }
07716717 2137 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2138 entry->edx &= ~(1 << 20);
2139 printk(KERN_INFO "kvm: guest NX capability removed\n");
2140 }
2141}
2142
07716717 2143/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2144static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2145 struct kvm_cpuid *cpuid,
2146 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2147{
2148 int r, i;
2149 struct kvm_cpuid_entry *cpuid_entries;
2150
2151 r = -E2BIG;
2152 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2153 goto out;
2154 r = -ENOMEM;
2155 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2156 if (!cpuid_entries)
2157 goto out;
2158 r = -EFAULT;
2159 if (copy_from_user(cpuid_entries, entries,
2160 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2161 goto out_free;
2162 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2163 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2164 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2165 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2166 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2167 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2168 vcpu->arch.cpuid_entries[i].index = 0;
2169 vcpu->arch.cpuid_entries[i].flags = 0;
2170 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2171 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2172 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2173 }
2174 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2175 cpuid_fix_nx_cap(vcpu);
2176 r = 0;
fc61b800 2177 kvm_apic_set_version(vcpu);
0e851880 2178 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2179 update_cpuid(vcpu);
07716717
DK		 2180
2181out_free:
2182 vfree(cpuid_entries);
2183out:
2184 return r;
2185}
2186
2187static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2188 struct kvm_cpuid2 *cpuid,
2189 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2190{
2191 int r;
2192
2193 r = -E2BIG;
2194 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2195 goto out;
2196 r = -EFAULT;
ad312c7c 2197 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2198 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2199 goto out;
ad312c7c 2200 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2201 kvm_apic_set_version(vcpu);
0e851880 2202 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2203 update_cpuid(vcpu);
313a3dc7
CO		 2204 return 0;
2205
2206out:
2207 return r;
2208}
2209
07716717 2210static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2211 struct kvm_cpuid2 *cpuid,
2212 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2213{
2214 int r;
2215
2216 r = -E2BIG;
ad312c7c 2217 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2218 goto out;
2219 r = -EFAULT;
ad312c7c 2220 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2221 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2222 goto out;
2223 return 0;
2224
2225out:
ad312c7c 2226 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2227 return r;
2228}
2229
945ee35e
AK		 2230static void cpuid_mask(u32 *word, int wordnum)
2231{
2232 *word &= boot_cpu_data.x86_capability[wordnum];
2233}
2234
07716717 2235static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2236 u32 index)
07716717
DK		 2237{
2238 entry->function = function;
2239 entry->index = index;
2240 cpuid_count(entry->function, entry->index,
19355475 2241 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2242 entry->flags = 0;
2243}
2244
7faa4ee1
AK		 2245#define F(x) bit(X86_FEATURE_##x)
2246
07716717
DK		 2247static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2248 u32 index, int *nent, int maxnent)
2249{
7faa4ee1 2250 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2251#ifdef CONFIG_X86_64
17cc3935
SY		 2252 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2253 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2254 unsigned f_lm = F(LM);
2255#else
17cc3935 2256 unsigned f_gbpages = 0;
7faa4ee1 2257 unsigned f_lm = 0;
07716717 2258#endif
4e47c7a6 2259 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2260
2261 /* cpuid 1.edx */
2262 const u32 kvm_supported_word0_x86_features =
2263 F(FPU) | F(VME) | F(DE) | F(PSE) |
2264 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2265 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2266 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2267 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2268 0 /* Reserved, DS, ACPI */ | F(MMX) |
2269 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2270 0 /* HTT, TM, Reserved, PBE */;
2271 /* cpuid 0x80000001.edx */
2272 const u32 kvm_supported_word1_x86_features =
2273 F(FPU) | F(VME) | F(DE) | F(PSE) |
2274 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2275 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2276 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2277 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2278 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2279 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2280 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2281 /* cpuid 1.ecx */
2282 const u32 kvm_supported_word4_x86_features =
6c3f6041 2283 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2284 0 /* DS-CPL, VMX, SMX, EST */ |
2285 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2286 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2287 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2288 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2289 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2290 F(F16C);
7faa4ee1 2291 /* cpuid 0x80000001.ecx */
07716717 2292 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2293 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2294 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2295 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2296 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2297
19355475 2298 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2299 get_cpu();
2300 do_cpuid_1_ent(entry, function, index);
2301 ++*nent;
2302
2303 switch (function) {
2304 case 0:
2acf923e 2305 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2306 break;
2307 case 1:
2308 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2309 cpuid_mask(&entry->edx, 0);
7faa4ee1 2310 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2311 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2312 /* we support x2apic emulation even if host does not support
2313 * it since we emulate x2apic in software */
2314 entry->ecx |= F(X2APIC);
07716717
DK		 2315 break;
2316 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2317 * may return different values. This forces us to get_cpu() before
2318 * issuing the first command, and also to emulate this annoying behavior
2319 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2320 case 2: {
2321 int t, times = entry->eax & 0xff;
2322
2323 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2324 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2325 for (t = 1; t < times && *nent < maxnent; ++t) {
2326 do_cpuid_1_ent(&entry[t], function, 0);
2327 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2328 ++*nent;
2329 }
2330 break;
2331 }
2332 /* function 4 and 0xb have additional index. */
2333 case 4: {
14af3f3c 2334 int i, cache_type;
07716717
DK		 2335
2336 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2337 /* read more entries until cache_type is zero */
14af3f3c
HH		 2338 for (i = 1; *nent < maxnent; ++i) {
2339 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2340 if (!cache_type)
2341 break;
14af3f3c
HH		 2342 do_cpuid_1_ent(&entry[i], function, i);
2343 entry[i].flags |=
07716717
DK		 2344 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2345 ++*nent;
2346 }
2347 break;
2348 }
2349 case 0xb: {
14af3f3c 2350 int i, level_type;
07716717
DK		 2351
2352 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2353 /* read more entries until level_type is zero */
14af3f3c 2354 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2355 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2356 if (!level_type)
2357 break;
14af3f3c
HH		 2358 do_cpuid_1_ent(&entry[i], function, i);
2359 entry[i].flags |=
07716717
DK		 2360 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2361 ++*nent;
2362 }
2363 break;
2364 }
2acf923e
DC		 2365 case 0xd: {
2366 int i;
2367
2368 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2369 for (i = 1; *nent < maxnent; ++i) {
2370 if (entry[i - 1].eax == 0 && i != 2)
2371 break;
2372 do_cpuid_1_ent(&entry[i], function, i);
2373 entry[i].flags |=
2374 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2375 ++*nent;
2376 }
2377 break;
2378 }
84478c82
GC		 2379 case KVM_CPUID_SIGNATURE: {
2380 char signature[12] = "KVMKVMKVM\0\0";
2381 u32 *sigptr = (u32 *)signature;
2382 entry->eax = 0;
2383 entry->ebx = sigptr[0];
2384 entry->ecx = sigptr[1];
2385 entry->edx = sigptr[2];
2386 break;
2387 }
2388 case KVM_CPUID_FEATURES:
2389 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2390 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2391 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2392 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2393 entry->ebx = 0;
2394 entry->ecx = 0;
2395 entry->edx = 0;
2396 break;
07716717
DK		 2397 case 0x80000000:
2398 entry->eax = min(entry->eax, 0x8000001a);
2399 break;
2400 case 0x80000001:
2401 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2402 cpuid_mask(&entry->edx, 1);
07716717 2403 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2404 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2405 break;
2406 }
d4330ef2
JR		 2407
2408 kvm_x86_ops->set_supported_cpuid(function, entry);
2409
07716717
DK		 2410 put_cpu();
2411}
2412
7faa4ee1
AK		 2413#undef F
2414
674eea0f 2415static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2416 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2417{
2418 struct kvm_cpuid_entry2 *cpuid_entries;
2419 int limit, nent = 0, r = -E2BIG;
2420 u32 func;
2421
2422 if (cpuid->nent < 1)
2423 goto out;
6a544355
AK		 2424 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2425 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2426 r = -ENOMEM;
2427 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2428 if (!cpuid_entries)
2429 goto out;
2430
2431 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2432 limit = cpuid_entries[0].eax;
2433 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2434 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2435 &nent, cpuid->nent);
07716717
DK		 2436 r = -E2BIG;
2437 if (nent >= cpuid->nent)
2438 goto out_free;
2439
2440 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2441 limit = cpuid_entries[nent - 1].eax;
2442 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2443 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2444 &nent, cpuid->nent);
84478c82
GC		 2445
2446
2447
2448 r = -E2BIG;
2449 if (nent >= cpuid->nent)
2450 goto out_free;
2451
2452 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2453 cpuid->nent);
2454
2455 r = -E2BIG;
2456 if (nent >= cpuid->nent)
2457 goto out_free;
2458
2459 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2460 cpuid->nent);
2461
cb007648
MM		 2462 r = -E2BIG;
2463 if (nent >= cpuid->nent)
2464 goto out_free;
2465
07716717
DK		 2466 r = -EFAULT;
2467 if (copy_to_user(entries, cpuid_entries,
19355475 2468 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2469 goto out_free;
2470 cpuid->nent = nent;
2471 r = 0;
2472
2473out_free:
2474 vfree(cpuid_entries);
2475out:
2476 return r;
2477}
2478
313a3dc7
CO		 2479static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2480 struct kvm_lapic_state *s)
2481{
ad312c7c 2482 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2483
2484 return 0;
2485}
2486
2487static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2488 struct kvm_lapic_state *s)
2489{
ad312c7c 2490 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2491 kvm_apic_post_state_restore(vcpu);
cb142eb7 2492 update_cr8_intercept(vcpu);
313a3dc7
CO		 2493
2494 return 0;
2495}
2496
f77bc6a4
ZX		 2497static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2498 struct kvm_interrupt *irq)
2499{
2500 if (irq->irq < 0 || irq->irq >= 256)
2501 return -EINVAL;
2502 if (irqchip_in_kernel(vcpu->kvm))
2503 return -ENXIO;
f77bc6a4 2504
66fd3f7f 2505 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2506 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2507
f77bc6a4
ZX		 2508 return 0;
2509}
2510
c4abb7c9
JK		 2511static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2512{
c4abb7c9 2513 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2514
2515 return 0;
2516}
2517
b209749f
AK		 2518static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2519 struct kvm_tpr_access_ctl *tac)
2520{
2521 if (tac->flags)
2522 return -EINVAL;
2523 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2524 return 0;
2525}
2526
890ca9ae
HY		 2527static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2528 u64 mcg_cap)
2529{
2530 int r;
2531 unsigned bank_num = mcg_cap & 0xff, bank;
2532
2533 r = -EINVAL;
a9e38c3e 2534 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2535 goto out;
2536 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2537 goto out;
2538 r = 0;
2539 vcpu->arch.mcg_cap = mcg_cap;
2540 /* Init IA32_MCG_CTL to all 1s */
2541 if (mcg_cap & MCG_CTL_P)
2542 vcpu->arch.mcg_ctl = ~(u64)0;
2543 /* Init IA32_MCi_CTL to all 1s */
2544 for (bank = 0; bank < bank_num; bank++)
2545 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2546out:
2547 return r;
2548}
2549
2550static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2551 struct kvm_x86_mce *mce)
2552{
2553 u64 mcg_cap = vcpu->arch.mcg_cap;
2554 unsigned bank_num = mcg_cap & 0xff;
2555 u64 *banks = vcpu->arch.mce_banks;
2556
2557 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2558 return -EINVAL;
2559 /*
2560 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2561 * reporting is disabled
2562 */
2563 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2564 vcpu->arch.mcg_ctl != ~(u64)0)
2565 return 0;
2566 banks += 4 * mce->bank;
2567 /*
2568 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2569 * reporting is disabled for the bank
2570 */
2571 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2572 return 0;
2573 if (mce->status & MCI_STATUS_UC) {
2574 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2575 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2576 printk(KERN_DEBUG "kvm: set_mce: "
2577 "injects mce exception while "
2578 "previous one is in progress!\n");
a8eeb04a 2579 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2580 return 0;
2581 }
2582 if (banks[1] & MCI_STATUS_VAL)
2583 mce->status |= MCI_STATUS_OVER;
2584 banks[2] = mce->addr;
2585 banks[3] = mce->misc;
2586 vcpu->arch.mcg_status = mce->mcg_status;
2587 banks[1] = mce->status;
2588 kvm_queue_exception(vcpu, MC_VECTOR);
2589 } else if (!(banks[1] & MCI_STATUS_VAL)
2590 || !(banks[1] & MCI_STATUS_UC)) {
2591 if (banks[1] & MCI_STATUS_VAL)
2592 mce->status |= MCI_STATUS_OVER;
2593 banks[2] = mce->addr;
2594 banks[3] = mce->misc;
2595 banks[1] = mce->status;
2596 } else
2597 banks[1] |= MCI_STATUS_OVER;
2598 return 0;
2599}
2600
3cfc3092
JK		 2601static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2602 struct kvm_vcpu_events *events)
2603{
03b82a30
JK		 2604 events->exception.injected =
2605 vcpu->arch.exception.pending &&
2606 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2607 events->exception.nr = vcpu->arch.exception.nr;
2608 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2609 events->exception.pad = 0;
3cfc3092
JK		 2610 events->exception.error_code = vcpu->arch.exception.error_code;
2611
03b82a30
JK		 2612 events->interrupt.injected =
2613 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2614 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2615 events->interrupt.soft = 0;
48005f64
JK		 2616 events->interrupt.shadow =
2617 kvm_x86_ops->get_interrupt_shadow(vcpu,
2618 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2619
2620 events->nmi.injected = vcpu->arch.nmi_injected;
2621 events->nmi.pending = vcpu->arch.nmi_pending;
2622 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2623 events->nmi.pad = 0;
3cfc3092
JK		 2624
2625 events->sipi_vector = vcpu->arch.sipi_vector;
2626
dab4b911 2627 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2628 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2629 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2630 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2631}
2632
2633static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2634 struct kvm_vcpu_events *events)
2635{
dab4b911 2636 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2637 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2638 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2639 return -EINVAL;
2640
3cfc3092
JK		 2641 vcpu->arch.exception.pending = events->exception.injected;
2642 vcpu->arch.exception.nr = events->exception.nr;
2643 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2644 vcpu->arch.exception.error_code = events->exception.error_code;
2645
2646 vcpu->arch.interrupt.pending = events->interrupt.injected;
2647 vcpu->arch.interrupt.nr = events->interrupt.nr;
2648 vcpu->arch.interrupt.soft = events->interrupt.soft;
2649 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2650 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2651 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2652 kvm_x86_ops->set_interrupt_shadow(vcpu,
2653 events->interrupt.shadow);
3cfc3092
JK		 2654
2655 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2656 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2657 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2658 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2659
dab4b911
JK		 2660 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2661 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2662
3842d135
AK		 2663 kvm_make_request(KVM_REQ_EVENT, vcpu);
2664
3cfc3092
JK		 2665 return 0;
2666}
2667
a1efbe77
JK		 2668static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2669 struct kvm_debugregs *dbgregs)
2670{
a1efbe77
JK		 2671 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2672 dbgregs->dr6 = vcpu->arch.dr6;
2673 dbgregs->dr7 = vcpu->arch.dr7;
2674 dbgregs->flags = 0;
97e69aa6 2675 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2676}
2677
2678static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2679 struct kvm_debugregs *dbgregs)
2680{
2681 if (dbgregs->flags)
2682 return -EINVAL;
2683
a1efbe77
JK		 2684 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2685 vcpu->arch.dr6 = dbgregs->dr6;
2686 vcpu->arch.dr7 = dbgregs->dr7;
2687
a1efbe77
JK		 2688 return 0;
2689}
2690
2d5b5a66
SY		 2691static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2692 struct kvm_xsave *guest_xsave)
2693{
2694 if (cpu_has_xsave)
2695 memcpy(guest_xsave->region,
2696 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2697 xstate_size);
2d5b5a66
SY		 2698 else {
2699 memcpy(guest_xsave->region,
2700 &vcpu->arch.guest_fpu.state->fxsave,
2701 sizeof(struct i387_fxsave_struct));
2702 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2703 XSTATE_FPSSE;
2704 }
2705}
2706
2707static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2708 struct kvm_xsave *guest_xsave)
2709{
2710 u64 xstate_bv =
2711 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2712
2713 if (cpu_has_xsave)
2714 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2715 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2716 else {
2717 if (xstate_bv & ~XSTATE_FPSSE)
2718 return -EINVAL;
2719 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2720 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2721 }
2722 return 0;
2723}
2724
2725static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2726 struct kvm_xcrs *guest_xcrs)
2727{
2728 if (!cpu_has_xsave) {
2729 guest_xcrs->nr_xcrs = 0;
2730 return;
2731 }
2732
2733 guest_xcrs->nr_xcrs = 1;
2734 guest_xcrs->flags = 0;
2735 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2736 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2737}
2738
2739static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2740 struct kvm_xcrs *guest_xcrs)
2741{
2742 int i, r = 0;
2743
2744 if (!cpu_has_xsave)
2745 return -EINVAL;
2746
2747 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2748 return -EINVAL;
2749
2750 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2751 /* Only support XCR0 currently */
2752 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2753 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2754 guest_xcrs->xcrs[0].value);
2755 break;
2756 }
2757 if (r)
2758 r = -EINVAL;
2759 return r;
2760}
2761
313a3dc7
CO		 2762long kvm_arch_vcpu_ioctl(struct file *filp,
2763 unsigned int ioctl, unsigned long arg)
2764{
2765 struct kvm_vcpu *vcpu = filp->private_data;
2766 void __user *argp = (void __user *)arg;
2767 int r;
d1ac91d8
AK		 2768 union {
2769 struct kvm_lapic_state *lapic;
2770 struct kvm_xsave *xsave;
2771 struct kvm_xcrs *xcrs;
2772 void *buffer;
2773 } u;
2774
2775 u.buffer = NULL;
313a3dc7
CO		 2776 switch (ioctl) {
2777 case KVM_GET_LAPIC: {
2204ae3c
MT		 2778 r = -EINVAL;
2779 if (!vcpu->arch.apic)
2780 goto out;
d1ac91d8 2781 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2782
b772ff36 2783 r = -ENOMEM;
d1ac91d8 2784 if (!u.lapic)
b772ff36 2785 goto out;
d1ac91d8 2786 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2787 if (r)
2788 goto out;
2789 r = -EFAULT;
d1ac91d8 2790 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2791 goto out;
2792 r = 0;
2793 break;
2794 }
2795 case KVM_SET_LAPIC: {
2204ae3c
MT		 2796 r = -EINVAL;
2797 if (!vcpu->arch.apic)
2798 goto out;
d1ac91d8 2799 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2800 r = -ENOMEM;
d1ac91d8 2801 if (!u.lapic)
b772ff36 2802 goto out;
313a3dc7 2803 r = -EFAULT;
d1ac91d8 2804 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2805 goto out;
d1ac91d8 2806 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2807 if (r)
2808 goto out;
2809 r = 0;
2810 break;
2811 }
f77bc6a4
ZX		 2812 case KVM_INTERRUPT: {
2813 struct kvm_interrupt irq;
2814
2815 r = -EFAULT;
2816 if (copy_from_user(&irq, argp, sizeof irq))
2817 goto out;
2818 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2819 if (r)
2820 goto out;
2821 r = 0;
2822 break;
2823 }
c4abb7c9
JK		 2824 case KVM_NMI: {
2825 r = kvm_vcpu_ioctl_nmi(vcpu);
2826 if (r)
2827 goto out;
2828 r = 0;
2829 break;
2830 }
313a3dc7
CO		 2831 case KVM_SET_CPUID: {
2832 struct kvm_cpuid __user *cpuid_arg = argp;
2833 struct kvm_cpuid cpuid;
2834
2835 r = -EFAULT;
2836 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2837 goto out;
2838 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2839 if (r)
2840 goto out;
2841 break;
2842 }
07716717
DK		 2843 case KVM_SET_CPUID2: {
2844 struct kvm_cpuid2 __user *cpuid_arg = argp;
2845 struct kvm_cpuid2 cpuid;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2849 goto out;
2850 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2851 cpuid_arg->entries);
07716717
DK		 2852 if (r)
2853 goto out;
2854 break;
2855 }
2856 case KVM_GET_CPUID2: {
2857 struct kvm_cpuid2 __user *cpuid_arg = argp;
2858 struct kvm_cpuid2 cpuid;
2859
2860 r = -EFAULT;
2861 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2862 goto out;
2863 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2864 cpuid_arg->entries);
07716717
DK		 2865 if (r)
2866 goto out;
2867 r = -EFAULT;
2868 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2869 goto out;
2870 r = 0;
2871 break;
2872 }
313a3dc7
CO		 2873 case KVM_GET_MSRS:
2874 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2875 break;
2876 case KVM_SET_MSRS:
2877 r = msr_io(vcpu, argp, do_set_msr, 0);
2878 break;
b209749f
AK		 2879 case KVM_TPR_ACCESS_REPORTING: {
2880 struct kvm_tpr_access_ctl tac;
2881
2882 r = -EFAULT;
2883 if (copy_from_user(&tac, argp, sizeof tac))
2884 goto out;
2885 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2886 if (r)
2887 goto out;
2888 r = -EFAULT;
2889 if (copy_to_user(argp, &tac, sizeof tac))
2890 goto out;
2891 r = 0;
2892 break;
2893 };
b93463aa
AK		 2894 case KVM_SET_VAPIC_ADDR: {
2895 struct kvm_vapic_addr va;
2896
2897 r = -EINVAL;
2898 if (!irqchip_in_kernel(vcpu->kvm))
2899 goto out;
2900 r = -EFAULT;
2901 if (copy_from_user(&va, argp, sizeof va))
2902 goto out;
2903 r = 0;
2904 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2905 break;
2906 }
890ca9ae
HY		 2907 case KVM_X86_SETUP_MCE: {
2908 u64 mcg_cap;
2909
2910 r = -EFAULT;
2911 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2912 goto out;
2913 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2914 break;
2915 }
2916 case KVM_X86_SET_MCE: {
2917 struct kvm_x86_mce mce;
2918
2919 r = -EFAULT;
2920 if (copy_from_user(&mce, argp, sizeof mce))
2921 goto out;
2922 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2923 break;
2924 }
3cfc3092
JK		 2925 case KVM_GET_VCPU_EVENTS: {
2926 struct kvm_vcpu_events events;
2927
2928 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2929
2930 r = -EFAULT;
2931 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2932 break;
2933 r = 0;
2934 break;
2935 }
2936 case KVM_SET_VCPU_EVENTS: {
2937 struct kvm_vcpu_events events;
2938
2939 r = -EFAULT;
2940 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2941 break;
2942
2943 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2944 break;
2945 }
a1efbe77
JK		 2946 case KVM_GET_DEBUGREGS: {
2947 struct kvm_debugregs dbgregs;
2948
2949 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2950
2951 r = -EFAULT;
2952 if (copy_to_user(argp, &dbgregs,
2953 sizeof(struct kvm_debugregs)))
2954 break;
2955 r = 0;
2956 break;
2957 }
2958 case KVM_SET_DEBUGREGS: {
2959 struct kvm_debugregs dbgregs;
2960
2961 r = -EFAULT;
2962 if (copy_from_user(&dbgregs, argp,
2963 sizeof(struct kvm_debugregs)))
2964 break;
2965
2966 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2967 break;
2968 }
2d5b5a66 2969 case KVM_GET_XSAVE: {
d1ac91d8 2970 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2971 r = -ENOMEM;
d1ac91d8 2972 if (!u.xsave)
2d5b5a66
SY		 2973 break;
2974
d1ac91d8 2975 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2976
2977 r = -EFAULT;
d1ac91d8 2978 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2979 break;
2980 r = 0;
2981 break;
2982 }
2983 case KVM_SET_XSAVE: {
d1ac91d8 2984 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2985 r = -ENOMEM;
d1ac91d8 2986 if (!u.xsave)
2d5b5a66
SY		 2987 break;
2988
2989 r = -EFAULT;
d1ac91d8 2990 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2991 break;
2992
d1ac91d8 2993 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2994 break;
2995 }
2996 case KVM_GET_XCRS: {
d1ac91d8 2997 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2998 r = -ENOMEM;
d1ac91d8 2999 if (!u.xcrs)
2d5b5a66
SY		 3000 break;
3001
d1ac91d8 3002 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3003
3004 r = -EFAULT;
d1ac91d8 3005 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3006 sizeof(struct kvm_xcrs)))
3007 break;
3008 r = 0;
3009 break;
3010 }
3011 case KVM_SET_XCRS: {
d1ac91d8 3012 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3013 r = -ENOMEM;
d1ac91d8 3014 if (!u.xcrs)
2d5b5a66
SY		 3015 break;
3016
3017 r = -EFAULT;
d1ac91d8 3018 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3019 sizeof(struct kvm_xcrs)))
3020 break;
3021
d1ac91d8 3022 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3023 break;
3024 }
313a3dc7
CO		 3025 default:
3026 r = -EINVAL;
3027 }
3028out:
d1ac91d8 3029 kfree(u.buffer);
313a3dc7
CO		 3030 return r;
3031}
3032
1fe779f8
CO		 3033static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3034{
3035 int ret;
3036
3037 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3038 return -1;
3039 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3040 return ret;
3041}
3042
b927a3ce
SY		 3043static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3044 u64 ident_addr)
3045{
3046 kvm->arch.ept_identity_map_addr = ident_addr;
3047 return 0;
3048}
3049
1fe779f8
CO		 3050static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3051 u32 kvm_nr_mmu_pages)
3052{
3053 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3054 return -EINVAL;
3055
79fac95e 3056 mutex_lock(&kvm->slots_lock);
7c8a83b7 3057 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3058
3059 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3060 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3061
7c8a83b7 3062 spin_unlock(&kvm->mmu_lock);
79fac95e 3063 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3064 return 0;
3065}
3066
3067static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3068{
39de71ec 3069 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3070}
3071
1fe779f8
CO		 3072static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3073{
3074 int r;
3075
3076 r = 0;
3077 switch (chip->chip_id) {
3078 case KVM_IRQCHIP_PIC_MASTER:
3079 memcpy(&chip->chip.pic,
3080 &pic_irqchip(kvm)->pics[0],
3081 sizeof(struct kvm_pic_state));
3082 break;
3083 case KVM_IRQCHIP_PIC_SLAVE:
3084 memcpy(&chip->chip.pic,
3085 &pic_irqchip(kvm)->pics[1],
3086 sizeof(struct kvm_pic_state));
3087 break;
3088 case KVM_IRQCHIP_IOAPIC:
eba0226b 3089 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3090 break;
3091 default:
3092 r = -EINVAL;
3093 break;
3094 }
3095 return r;
3096}
3097
3098static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3099{
3100 int r;
3101
3102 r = 0;
3103 switch (chip->chip_id) {
3104 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3105 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3106 memcpy(&pic_irqchip(kvm)->pics[0],
3107 &chip->chip.pic,
3108 sizeof(struct kvm_pic_state));
f4f51050 3109 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3110 break;
3111 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3112 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3113 memcpy(&pic_irqchip(kvm)->pics[1],
3114 &chip->chip.pic,
3115 sizeof(struct kvm_pic_state));
f4f51050 3116 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3117 break;
3118 case KVM_IRQCHIP_IOAPIC:
eba0226b 3119 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3120 break;
3121 default:
3122 r = -EINVAL;
3123 break;
3124 }
3125 kvm_pic_update_irq(pic_irqchip(kvm));
3126 return r;
3127}
3128
e0f63cb9
SY		 3129static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3130{
3131 int r = 0;
3132
894a9c55 3133 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3134 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3135 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3136 return r;
3137}
3138
3139static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3140{
3141 int r = 0;
3142
894a9c55 3143 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3144 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3145 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3146 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3147 return r;
3148}
3149
3150static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3151{
3152 int r = 0;
3153
3154 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3155 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3156 sizeof(ps->channels));
3157 ps->flags = kvm->arch.vpit->pit_state.flags;
3158 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3159 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3160 return r;
3161}
3162
3163static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3164{
3165 int r = 0, start = 0;
3166 u32 prev_legacy, cur_legacy;
3167 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3168 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3169 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3170 if (!prev_legacy && cur_legacy)
3171 start = 1;
3172 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3173 sizeof(kvm->arch.vpit->pit_state.channels));
3174 kvm->arch.vpit->pit_state.flags = ps->flags;
3175 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3176 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3177 return r;
3178}
3179
52d939a0
MT		 3180static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3181 struct kvm_reinject_control *control)
3182{
3183 if (!kvm->arch.vpit)
3184 return -ENXIO;
894a9c55 3185 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3186 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3187 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3188 return 0;
3189}
3190
5bb064dc
ZX		 3191/*
3192 * Get (and clear) the dirty memory log for a memory slot.
3193 */
3194int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3195 struct kvm_dirty_log *log)
3196{
87bf6e7d 3197 int r, i;
5bb064dc 3198 struct kvm_memory_slot *memslot;
87bf6e7d 3199 unsigned long n;
b050b015 3200 unsigned long is_dirty = 0;
5bb064dc 3201
79fac95e 3202 mutex_lock(&kvm->slots_lock);
5bb064dc 3203
b050b015
MT		 3204 r = -EINVAL;
3205 if (log->slot >= KVM_MEMORY_SLOTS)
3206 goto out;
3207
3208 memslot = &kvm->memslots->memslots[log->slot];
3209 r = -ENOENT;
3210 if (!memslot->dirty_bitmap)
3211 goto out;
3212
87bf6e7d 3213 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3214
b050b015
MT		 3215 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3216 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3217
3218 /* If nothing is dirty, don't bother messing with page tables. */
3219 if (is_dirty) {
b050b015 3220 struct kvm_memslots *slots, *old_slots;
914ebccd 3221 unsigned long *dirty_bitmap;
b050b015 3222
515a0127
TY		 3223 dirty_bitmap = memslot->dirty_bitmap_head;
3224 if (memslot->dirty_bitmap == dirty_bitmap)
3225 dirty_bitmap += n / sizeof(long);
914ebccd 3226 memset(dirty_bitmap, 0, n);
b050b015 3227
914ebccd
TY		 3228 r = -ENOMEM;
3229 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3230 if (!slots)
914ebccd 3231 goto out;
b050b015
MT		 3232 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3233 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3234 slots->generation++;
b050b015
MT		 3235
3236 old_slots = kvm->memslots;
3237 rcu_assign_pointer(kvm->memslots, slots);
3238 synchronize_srcu_expedited(&kvm->srcu);
3239 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3240 kfree(old_slots);
914ebccd 3241
edde99ce
MT		 3242 spin_lock(&kvm->mmu_lock);
3243 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3244 spin_unlock(&kvm->mmu_lock);
3245
914ebccd 3246 r = -EFAULT;
515a0127 3247 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3248 goto out;
914ebccd
TY		 3249 } else {
3250 r = -EFAULT;
3251 if (clear_user(log->dirty_bitmap, n))
3252 goto out;
5bb064dc 3253 }
b050b015 3254
5bb064dc
ZX		 3255 r = 0;
3256out:
79fac95e 3257 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3258 return r;
3259}
3260
1fe779f8
CO		 3261long kvm_arch_vm_ioctl(struct file *filp,
3262 unsigned int ioctl, unsigned long arg)
3263{
3264 struct kvm *kvm = filp->private_data;
3265 void __user *argp = (void __user *)arg;
367e1319 3266 int r = -ENOTTY;
f0d66275
DH		 3267 /*
3268 * This union makes it completely explicit to gcc-3.x
3269 * that these two variables' stack usage should be
3270 * combined, not added together.
3271 */
3272 union {
3273 struct kvm_pit_state ps;
e9f42757 3274 struct kvm_pit_state2 ps2;
c5ff41ce 3275 struct kvm_pit_config pit_config;
f0d66275 3276 } u;
1fe779f8
CO		 3277
3278 switch (ioctl) {
3279 case KVM_SET_TSS_ADDR:
3280 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3281 if (r < 0)
3282 goto out;
3283 break;
b927a3ce
SY		 3284 case KVM_SET_IDENTITY_MAP_ADDR: {
3285 u64 ident_addr;
3286
3287 r = -EFAULT;
3288 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3289 goto out;
3290 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3291 if (r < 0)
3292 goto out;
3293 break;
3294 }
1fe779f8
CO		 3295 case KVM_SET_NR_MMU_PAGES:
3296 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3297 if (r)
3298 goto out;
3299 break;
3300 case KVM_GET_NR_MMU_PAGES:
3301 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3302 break;
3ddea128
MT		 3303 case KVM_CREATE_IRQCHIP: {
3304 struct kvm_pic *vpic;
3305
3306 mutex_lock(&kvm->lock);
3307 r = -EEXIST;
3308 if (kvm->arch.vpic)
3309 goto create_irqchip_unlock;
1fe779f8 3310 r = -ENOMEM;
3ddea128
MT		 3311 vpic = kvm_create_pic(kvm);
3312 if (vpic) {
1fe779f8
CO		 3313 r = kvm_ioapic_init(kvm);
3314 if (r) {
175504cd 3315 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3316 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3317 &vpic->dev);
175504cd 3318 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3319 kfree(vpic);
3320 goto create_irqchip_unlock;
1fe779f8
CO		 3321 }
3322 } else
3ddea128
MT		 3323 goto create_irqchip_unlock;
3324 smp_wmb();
3325 kvm->arch.vpic = vpic;
3326 smp_wmb();
399ec807
AK		 3327 r = kvm_setup_default_irq_routing(kvm);
3328 if (r) {
175504cd 3329 mutex_lock(&kvm->slots_lock);
3ddea128 3330 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3331 kvm_ioapic_destroy(kvm);
3332 kvm_destroy_pic(kvm);
3ddea128 3333 mutex_unlock(&kvm->irq_lock);
175504cd 3334 mutex_unlock(&kvm->slots_lock);
399ec807 3335 }
3ddea128
MT		 3336 create_irqchip_unlock:
3337 mutex_unlock(&kvm->lock);
1fe779f8 3338 break;
3ddea128 3339 }
7837699f 3340 case KVM_CREATE_PIT:
c5ff41ce
JK		 3341 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3342 goto create_pit;
3343 case KVM_CREATE_PIT2:
3344 r = -EFAULT;
3345 if (copy_from_user(&u.pit_config, argp,
3346 sizeof(struct kvm_pit_config)))
3347 goto out;
3348 create_pit:
79fac95e 3349 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3350 r = -EEXIST;
3351 if (kvm->arch.vpit)
3352 goto create_pit_unlock;
7837699f 3353 r = -ENOMEM;
c5ff41ce 3354 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3355 if (kvm->arch.vpit)
3356 r = 0;
269e05e4 3357 create_pit_unlock:
79fac95e 3358 mutex_unlock(&kvm->slots_lock);
7837699f 3359 break;
4925663a 3360 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3361 case KVM_IRQ_LINE: {
3362 struct kvm_irq_level irq_event;
3363
3364 r = -EFAULT;
3365 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3366 goto out;
160d2f6c 3367 r = -ENXIO;
1fe779f8 3368 if (irqchip_in_kernel(kvm)) {
4925663a 3369 __s32 status;
4925663a
GN		 3370 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3371 irq_event.irq, irq_event.level);
4925663a 3372 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3373 r = -EFAULT;
4925663a
GN		 3374 irq_event.status = status;
3375 if (copy_to_user(argp, &irq_event,
3376 sizeof irq_event))
3377 goto out;
3378 }
1fe779f8
CO		 3379 r = 0;
3380 }
3381 break;
3382 }
3383 case KVM_GET_IRQCHIP: {
3384 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3385 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3386
f0d66275
DH		 3387 r = -ENOMEM;
3388 if (!chip)
1fe779f8 3389 goto out;
f0d66275
DH		 3390 r = -EFAULT;
3391 if (copy_from_user(chip, argp, sizeof *chip))
3392 goto get_irqchip_out;
1fe779f8
CO		 3393 r = -ENXIO;
3394 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3395 goto get_irqchip_out;
3396 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3397 if (r)
f0d66275 3398 goto get_irqchip_out;
1fe779f8 3399 r = -EFAULT;
f0d66275
DH		 3400 if (copy_to_user(argp, chip, sizeof *chip))
3401 goto get_irqchip_out;
1fe779f8 3402 r = 0;
f0d66275
DH		 3403 get_irqchip_out:
3404 kfree(chip);
3405 if (r)
3406 goto out;
1fe779f8
CO		 3407 break;
3408 }
3409 case KVM_SET_IRQCHIP: {
3410 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3411 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3412
f0d66275
DH		 3413 r = -ENOMEM;
3414 if (!chip)
1fe779f8 3415 goto out;
f0d66275
DH		 3416 r = -EFAULT;
3417 if (copy_from_user(chip, argp, sizeof *chip))
3418 goto set_irqchip_out;
1fe779f8
CO		 3419 r = -ENXIO;
3420 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3421 goto set_irqchip_out;
3422 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3423 if (r)
f0d66275 3424 goto set_irqchip_out;
1fe779f8 3425 r = 0;
f0d66275
DH		 3426 set_irqchip_out:
3427 kfree(chip);
3428 if (r)
3429 goto out;
1fe779f8
CO		 3430 break;
3431 }
e0f63cb9 3432 case KVM_GET_PIT: {
e0f63cb9 3433 r = -EFAULT;
f0d66275 3434 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3435 goto out;
3436 r = -ENXIO;
3437 if (!kvm->arch.vpit)
3438 goto out;
f0d66275 3439 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3440 if (r)
3441 goto out;
3442 r = -EFAULT;
f0d66275 3443 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3444 goto out;
3445 r = 0;
3446 break;
3447 }
3448 case KVM_SET_PIT: {
e0f63cb9 3449 r = -EFAULT;
f0d66275 3450 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3451 goto out;
3452 r = -ENXIO;
3453 if (!kvm->arch.vpit)
3454 goto out;
f0d66275 3455 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3456 if (r)
3457 goto out;
3458 r = 0;
3459 break;
3460 }
e9f42757
BK		 3461 case KVM_GET_PIT2: {
3462 r = -ENXIO;
3463 if (!kvm->arch.vpit)
3464 goto out;
3465 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3466 if (r)
3467 goto out;
3468 r = -EFAULT;
3469 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3470 goto out;
3471 r = 0;
3472 break;
3473 }
3474 case KVM_SET_PIT2: {
3475 r = -EFAULT;
3476 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3477 goto out;
3478 r = -ENXIO;
3479 if (!kvm->arch.vpit)
3480 goto out;
3481 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3482 if (r)
3483 goto out;
3484 r = 0;
3485 break;
3486 }
52d939a0
MT		 3487 case KVM_REINJECT_CONTROL: {
3488 struct kvm_reinject_control control;
3489 r = -EFAULT;
3490 if (copy_from_user(&control, argp, sizeof(control)))
3491 goto out;
3492 r = kvm_vm_ioctl_reinject(kvm, &control);
3493 if (r)
3494 goto out;
3495 r = 0;
3496 break;
3497 }
ffde22ac
ES		 3498 case KVM_XEN_HVM_CONFIG: {
3499 r = -EFAULT;
3500 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3501 sizeof(struct kvm_xen_hvm_config)))
3502 goto out;
3503 r = -EINVAL;
3504 if (kvm->arch.xen_hvm_config.flags)
3505 goto out;
3506 r = 0;
3507 break;
3508 }
afbcf7ab 3509 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3510 struct kvm_clock_data user_ns;
3511 u64 now_ns;
3512 s64 delta;
3513
3514 r = -EFAULT;
3515 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3516 goto out;
3517
3518 r = -EINVAL;
3519 if (user_ns.flags)
3520 goto out;
3521
3522 r = 0;
395c6b0a 3523 local_irq_disable();
759379dd 3524 now_ns = get_kernel_ns();
afbcf7ab 3525 delta = user_ns.clock - now_ns;
395c6b0a 3526 local_irq_enable();
afbcf7ab
GC		 3527 kvm->arch.kvmclock_offset = delta;
3528 break;
3529 }
3530 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3531 struct kvm_clock_data user_ns;
3532 u64 now_ns;
3533
395c6b0a 3534 local_irq_disable();
759379dd 3535 now_ns = get_kernel_ns();
afbcf7ab 3536 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3537 local_irq_enable();
afbcf7ab 3538 user_ns.flags = 0;
97e69aa6 3539 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3540
3541 r = -EFAULT;
3542 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3543 goto out;
3544 r = 0;
3545 break;
3546 }
3547
1fe779f8
CO		 3548 default:
3549 ;
3550 }
3551out:
3552 return r;
3553}
3554
a16b043c 3555static void kvm_init_msr_list(void)
043405e1
CO		 3556{
3557 u32 dummy[2];
3558 unsigned i, j;
3559
e3267cbb
GC		 3560 /* skip the first msrs in the list. KVM-specific */
3561 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3562 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3563 continue;
3564 if (j < i)
3565 msrs_to_save[j] = msrs_to_save[i];
3566 j++;
3567 }
3568 num_msrs_to_save = j;
3569}
3570
bda9020e
MT		 3571static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3572 const void *v)
bbd9b64e 3573{
bda9020e
MT		 3574 if (vcpu->arch.apic &&
3575 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3576 return 0;
bbd9b64e 3577
e93f8a0f 3578 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3579}
3580
bda9020e 3581static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3582{
bda9020e
MT		 3583 if (vcpu->arch.apic &&
3584 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3585 return 0;
bbd9b64e 3586
e93f8a0f 3587 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3588}
3589
2dafc6c2
GN		 3590static void kvm_set_segment(struct kvm_vcpu *vcpu,
3591 struct kvm_segment *var, int seg)
3592{
3593 kvm_x86_ops->set_segment(vcpu, var, seg);
3594}
3595
3596void kvm_get_segment(struct kvm_vcpu *vcpu,
3597 struct kvm_segment *var, int seg)
3598{
3599 kvm_x86_ops->get_segment(vcpu, var, seg);
3600}
3601
c30a358d
JR		 3602static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3603{
3604 return gpa;
3605}
3606
02f59dc9
JR		 3607static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3608{
3609 gpa_t t_gpa;
ab9ae313 3610 struct x86_exception exception;
02f59dc9
JR		 3611
3612 BUG_ON(!mmu_is_nested(vcpu));
3613
3614 /* NPT walks are always user-walks */
3615 access |= PFERR_USER_MASK;
ab9ae313 3616 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3617
3618 return t_gpa;
3619}
3620
ab9ae313
AK		 3621gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3622 struct x86_exception *exception)
1871c602
GN		 3623{
3624 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3625 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3626}
3627
ab9ae313
AK		 3628 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3629 struct x86_exception *exception)
1871c602
GN		 3630{
3631 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3632 access |= PFERR_FETCH_MASK;
ab9ae313 3633 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3634}
3635
ab9ae313
AK		 3636gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3637 struct x86_exception *exception)
1871c602
GN		 3638{
3639 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3640 access |= PFERR_WRITE_MASK;
ab9ae313 3641 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3642}
3643
3644/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3645gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3646 struct x86_exception *exception)
bcc55cba 3647{
ab9ae313 3648 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
bcc55cba
AK		 3649}
3650
1871c602
GN		 3651static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3652 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3653 struct x86_exception *exception)
bbd9b64e
CO		 3654{
3655 void *data = val;
10589a46 3656 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3657
3658 while (bytes) {
14dfe855 3659 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3660 exception);
bbd9b64e 3661 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3662 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3663 int ret;
3664
bcc55cba 3665 if (gpa == UNMAPPED_GVA)
ab9ae313 3666 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3667 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3668 if (ret < 0) {
c3cd7ffa 3669 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3670 goto out;
3671 }
bbd9b64e 3672
77c2002e
IE		 3673 bytes -= toread;
3674 data += toread;
3675 addr += toread;
bbd9b64e 3676 }
10589a46 3677out:
10589a46 3678 return r;
bbd9b64e 3679}
77c2002e 3680
1871c602
GN		 3681/* used for instruction fetching */
3682static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3683 struct kvm_vcpu *vcpu,
3684 struct x86_exception *exception)
1871c602
GN		 3685{
3686 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3687 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3688 access | PFERR_FETCH_MASK,
3689 exception);
1871c602
GN		 3690}
3691
3692static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3693 struct kvm_vcpu *vcpu,
3694 struct x86_exception *exception)
1871c602
GN		 3695{
3696 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3697 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3698 exception);
1871c602
GN		 3699}
3700
3701static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3702 struct kvm_vcpu *vcpu,
3703 struct x86_exception *exception)
1871c602 3704{
bcc55cba 3705 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3706}
3707
7972995b 3708static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3709 unsigned int bytes,
7972995b 3710 struct kvm_vcpu *vcpu,
bcc55cba 3711 struct x86_exception *exception)
77c2002e
IE		 3712{
3713 void *data = val;
3714 int r = X86EMUL_CONTINUE;
3715
3716 while (bytes) {
14dfe855
JR		 3717 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3718 PFERR_WRITE_MASK,
ab9ae313 3719 exception);
77c2002e
IE		 3720 unsigned offset = addr & (PAGE_SIZE-1);
3721 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3722 int ret;
3723
bcc55cba 3724 if (gpa == UNMAPPED_GVA)
ab9ae313 3725 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3726 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3727 if (ret < 0) {
c3cd7ffa 3728 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3729 goto out;
3730 }
3731
3732 bytes -= towrite;
3733 data += towrite;
3734 addr += towrite;
3735 }
3736out:
3737 return r;
3738}
3739
bbd9b64e
CO		 3740static int emulator_read_emulated(unsigned long addr,
3741 void *val,
3742 unsigned int bytes,
bcc55cba 3743 struct x86_exception *exception,
bbd9b64e
CO		 3744 struct kvm_vcpu *vcpu)
3745{
bbd9b64e
CO		 3746 gpa_t gpa;
3747
3748 if (vcpu->mmio_read_completed) {
3749 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3750 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3751 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3752 vcpu->mmio_read_completed = 0;
3753 return X86EMUL_CONTINUE;
3754 }
3755
ab9ae313 3756 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3757
8fe681e9 3758 if (gpa == UNMAPPED_GVA)
ab9ae313 3759 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3760
3761 /* For APIC access vmexit */
3762 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3763 goto mmio;
3764
bcc55cba
AK		 3765 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3766 == X86EMUL_CONTINUE)
bbd9b64e 3767 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3768
3769mmio:
3770 /*
3771 * Is this MMIO handled locally?
3772 */
aec51dc4
AK		 3773 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3774 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3775 return X86EMUL_CONTINUE;
3776 }
aec51dc4
AK		 3777
3778 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3779
3780 vcpu->mmio_needed = 1;
411c35b7
GN		 3781 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3782 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3783 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3784 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3785
c3cd7ffa 3786 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3787}
3788
3200f405 3789int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3790 const void *val, int bytes)
bbd9b64e
CO		 3791{
3792 int ret;
3793
3794 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3795 if (ret < 0)
bbd9b64e 3796 return 0;
ad218f85 3797 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3798 return 1;
3799}
3800
3801static int emulator_write_emulated_onepage(unsigned long addr,
3802 const void *val,
3803 unsigned int bytes,
bcc55cba 3804 struct x86_exception *exception,
bbd9b64e
CO		 3805 struct kvm_vcpu *vcpu)
3806{
10589a46
MT		 3807 gpa_t gpa;
3808
ab9ae313 3809 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3810
8fe681e9 3811 if (gpa == UNMAPPED_GVA)
ab9ae313 3812 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3813
3814 /* For APIC access vmexit */
3815 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3816 goto mmio;
3817
3818 if (emulator_write_phys(vcpu, gpa, val, bytes))
3819 return X86EMUL_CONTINUE;
3820
3821mmio:
aec51dc4 3822 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3823 /*
3824 * Is this MMIO handled locally?
3825 */
bda9020e 3826 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3827 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3828
3829 vcpu->mmio_needed = 1;
411c35b7
GN		 3830 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3831 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3832 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3833 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3834 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3835
3836 return X86EMUL_CONTINUE;
3837}
3838
3839int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3840 const void *val,
3841 unsigned int bytes,
bcc55cba 3842 struct x86_exception *exception,
8f6abd06 3843 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3844{
3845 /* Crossing a page boundary? */
3846 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3847 int rc, now;
3848
3849 now = -addr & ~PAGE_MASK;
bcc55cba 3850 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3851 vcpu);
bbd9b64e
CO		 3852 if (rc != X86EMUL_CONTINUE)
3853 return rc;
3854 addr += now;
3855 val += now;
3856 bytes -= now;
3857 }
bcc55cba 3858 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3859 vcpu);
bbd9b64e 3860}
bbd9b64e 3861
daea3e73
AK		 3862#define CMPXCHG_TYPE(t, ptr, old, new) \
3863 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3864
3865#ifdef CONFIG_X86_64
3866# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3867#else
3868# define CMPXCHG64(ptr, old, new) \
9749a6c0 3869 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3870#endif
3871
bbd9b64e
CO		 3872static int emulator_cmpxchg_emulated(unsigned long addr,
3873 const void *old,
3874 const void *new,
3875 unsigned int bytes,
bcc55cba 3876 struct x86_exception *exception,
bbd9b64e
CO		 3877 struct kvm_vcpu *vcpu)
3878{
daea3e73
AK		 3879 gpa_t gpa;
3880 struct page *page;
3881 char *kaddr;
3882 bool exchanged;
2bacc55c 3883
daea3e73
AK		 3884 /* guests cmpxchg8b have to be emulated atomically */
3885 if (bytes > 8 || (bytes & (bytes - 1)))
3886 goto emul_write;
10589a46 3887
daea3e73 3888 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3889
daea3e73
AK		 3890 if (gpa == UNMAPPED_GVA ||
3891 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3892 goto emul_write;
2bacc55c 3893
daea3e73
AK		 3894 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3895 goto emul_write;
72dc67a6 3896
daea3e73 3897 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3898 if (is_error_page(page)) {
3899 kvm_release_page_clean(page);
3900 goto emul_write;
3901 }
72dc67a6 3902
daea3e73
AK		 3903 kaddr = kmap_atomic(page, KM_USER0);
3904 kaddr += offset_in_page(gpa);
3905 switch (bytes) {
3906 case 1:
3907 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3908 break;
3909 case 2:
3910 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3911 break;
3912 case 4:
3913 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3914 break;
3915 case 8:
3916 exchanged = CMPXCHG64(kaddr, old, new);
3917 break;
3918 default:
3919 BUG();
2bacc55c 3920 }
daea3e73
AK		 3921 kunmap_atomic(kaddr, KM_USER0);
3922 kvm_release_page_dirty(page);
3923
3924 if (!exchanged)
3925 return X86EMUL_CMPXCHG_FAILED;
3926
8f6abd06
GN		 3927 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3928
3929 return X86EMUL_CONTINUE;
4a5f48f6 3930
3200f405 3931emul_write:
daea3e73 3932 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3933
bcc55cba 3934 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 3935}
3936
cf8f70bf
GN		 3937static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3938{
3939 /* TODO: String I/O for in kernel device */
3940 int r;
3941
3942 if (vcpu->arch.pio.in)
3943 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3944 vcpu->arch.pio.size, pd);
3945 else
3946 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3947 vcpu->arch.pio.port, vcpu->arch.pio.size,
3948 pd);
3949 return r;
3950}
3951
3952
3953static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3954 unsigned int count, struct kvm_vcpu *vcpu)
3955{
7972995b 3956 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3957 goto data_avail;
3958
61cfab2e 3959 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 3960
3961 vcpu->arch.pio.port = port;
3962 vcpu->arch.pio.in = 1;
7972995b 3963 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3964 vcpu->arch.pio.size = size;
3965
3966 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3967 data_avail:
3968 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3969 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3970 return 1;
3971 }
3972
3973 vcpu->run->exit_reason = KVM_EXIT_IO;
3974 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3975 vcpu->run->io.size = size;
3976 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3977 vcpu->run->io.count = count;
3978 vcpu->run->io.port = port;
3979
3980 return 0;
3981}
3982
3983static int emulator_pio_out_emulated(int size, unsigned short port,
3984 const void *val, unsigned int count,
3985 struct kvm_vcpu *vcpu)
3986{
61cfab2e 3987 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 3988
3989 vcpu->arch.pio.port = port;
3990 vcpu->arch.pio.in = 0;
7972995b 3991 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3992 vcpu->arch.pio.size = size;
3993
3994 memcpy(vcpu->arch.pio_data, val, size * count);
3995
3996 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3997 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3998 return 1;
3999 }
4000
4001 vcpu->run->exit_reason = KVM_EXIT_IO;
4002 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4003 vcpu->run->io.size = size;
4004 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4005 vcpu->run->io.count = count;
4006 vcpu->run->io.port = port;
4007
4008 return 0;
4009}
4010
bbd9b64e
CO		 4011static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4012{
4013 return kvm_x86_ops->get_segment_base(vcpu, seg);
4014}
4015
4016int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4017{
a7052897 4018 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4019 return X86EMUL_CONTINUE;
4020}
4021
f5f48ee1
SY		 4022int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4023{
4024 if (!need_emulate_wbinvd(vcpu))
4025 return X86EMUL_CONTINUE;
4026
4027 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4028 int cpu = get_cpu();
4029
4030 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4031 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4032 wbinvd_ipi, NULL, 1);
2eec7343 4033 put_cpu();
f5f48ee1 4034 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4035 } else
4036 wbinvd();
f5f48ee1
SY		 4037 return X86EMUL_CONTINUE;
4038}
4039EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4040
bbd9b64e
CO		 4041int emulate_clts(struct kvm_vcpu *vcpu)
4042{
4d4ec087 4043 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4044 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4045 return X86EMUL_CONTINUE;
4046}
4047
35aa5375 4048int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4049{
338dbc97 4050 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4051}
4052
35aa5375 4053int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4054{
338dbc97
GN		 4055
4056 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4057}
4058
52a46617 4059static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4060{
52a46617 4061 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4062}
4063
52a46617 4064static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4065{
52a46617
GN		 4066 unsigned long value;
4067
4068 switch (cr) {
4069 case 0:
4070 value = kvm_read_cr0(vcpu);
4071 break;
4072 case 2:
4073 value = vcpu->arch.cr2;
4074 break;
4075 case 3:
4076 value = vcpu->arch.cr3;
4077 break;
4078 case 4:
4079 value = kvm_read_cr4(vcpu);
4080 break;
4081 case 8:
4082 value = kvm_get_cr8(vcpu);
4083 break;
4084 default:
4085 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4086 return 0;
4087 }
4088
4089 return value;
4090}
4091
0f12244f 4092static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4093{
0f12244f
GN		 4094 int res = 0;
4095
52a46617
GN		 4096 switch (cr) {
4097 case 0:
49a9b07e 4098 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4099 break;
4100 case 2:
4101 vcpu->arch.cr2 = val;
4102 break;
4103 case 3:
2390218b 4104 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4105 break;
4106 case 4:
a83b29c6 4107 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4108 break;
4109 case 8:
eea1cff9 4110 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4111 break;
4112 default:
4113 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4114 res = -1;
52a46617 4115 }
0f12244f
GN		 4116
4117 return res;
52a46617
GN		 4118}
4119
9c537244
GN		 4120static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4121{
4122 return kvm_x86_ops->get_cpl(vcpu);
4123}
4124
2dafc6c2
GN		 4125static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4126{
4127 kvm_x86_ops->get_gdt(vcpu, dt);
4128}
4129
160ce1f1
MG		 4130static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4131{
4132 kvm_x86_ops->get_idt(vcpu, dt);
4133}
4134
5951c442
GN		 4135static unsigned long emulator_get_cached_segment_base(int seg,
4136 struct kvm_vcpu *vcpu)
4137{
4138 return get_segment_base(vcpu, seg);
4139}
4140
2dafc6c2
GN		 4141static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4142 struct kvm_vcpu *vcpu)
4143{
4144 struct kvm_segment var;
4145
4146 kvm_get_segment(vcpu, &var, seg);
4147
4148 if (var.unusable)
4149 return false;
4150
4151 if (var.g)
4152 var.limit >>= 12;
4153 set_desc_limit(desc, var.limit);
4154 set_desc_base(desc, (unsigned long)var.base);
4155 desc->type = var.type;
4156 desc->s = var.s;
4157 desc->dpl = var.dpl;
4158 desc->p = var.present;
4159 desc->avl = var.avl;
4160 desc->l = var.l;
4161 desc->d = var.db;
4162 desc->g = var.g;
4163
4164 return true;
4165}
4166
4167static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4168 struct kvm_vcpu *vcpu)
4169{
4170 struct kvm_segment var;
4171
4172 /* needed to preserve selector */
4173 kvm_get_segment(vcpu, &var, seg);
4174
4175 var.base = get_desc_base(desc);
4176 var.limit = get_desc_limit(desc);
4177 if (desc->g)
4178 var.limit = (var.limit << 12) | 0xfff;
4179 var.type = desc->type;
4180 var.present = desc->p;
4181 var.dpl = desc->dpl;
4182 var.db = desc->d;
4183 var.s = desc->s;
4184 var.l = desc->l;
4185 var.g = desc->g;
4186 var.avl = desc->avl;
4187 var.present = desc->p;
4188 var.unusable = !var.present;
4189 var.padding = 0;
4190
4191 kvm_set_segment(vcpu, &var, seg);
4192 return;
4193}
4194
4195static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4196{
4197 struct kvm_segment kvm_seg;
4198
4199 kvm_get_segment(vcpu, &kvm_seg, seg);
4200 return kvm_seg.selector;
4201}
4202
4203static void emulator_set_segment_selector(u16 sel, int seg,
4204 struct kvm_vcpu *vcpu)
4205{
4206 struct kvm_segment kvm_seg;
4207
4208 kvm_get_segment(vcpu, &kvm_seg, seg);
4209 kvm_seg.selector = sel;
4210 kvm_set_segment(vcpu, &kvm_seg, seg);
4211}
4212
14af3f3c 4213static struct x86_emulate_ops emulate_ops = {
1871c602 4214 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4215 .write_std = kvm_write_guest_virt_system,
1871c602 4216 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4217 .read_emulated = emulator_read_emulated,
4218 .write_emulated = emulator_write_emulated,
4219 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4220 .pio_in_emulated = emulator_pio_in_emulated,
4221 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4222 .get_cached_descriptor = emulator_get_cached_descriptor,
4223 .set_cached_descriptor = emulator_set_cached_descriptor,
4224 .get_segment_selector = emulator_get_segment_selector,
4225 .set_segment_selector = emulator_set_segment_selector,
5951c442 4226 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4227 .get_gdt = emulator_get_gdt,
160ce1f1 4228 .get_idt = emulator_get_idt,
52a46617
GN		 4229 .get_cr = emulator_get_cr,
4230 .set_cr = emulator_set_cr,
9c537244 4231 .cpl = emulator_get_cpl,
35aa5375
GN		 4232 .get_dr = emulator_get_dr,
4233 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4234 .set_msr = kvm_set_msr,
4235 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4236};
4237
5fdbf976
MT		 4238static void cache_all_regs(struct kvm_vcpu *vcpu)
4239{
4240 kvm_register_read(vcpu, VCPU_REGS_RAX);
4241 kvm_register_read(vcpu, VCPU_REGS_RSP);
4242 kvm_register_read(vcpu, VCPU_REGS_RIP);
4243 vcpu->arch.regs_dirty = ~0;
4244}
4245
95cb2295
GN		 4246static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4247{
4248 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4249 /*
4250 * an sti; sti; sequence only disable interrupts for the first
4251 * instruction. So, if the last instruction, be it emulated or
4252 * not, left the system with the INT_STI flag enabled, it
4253 * means that the last instruction is an sti. We should not
4254 * leave the flag on in this case. The same goes for mov ss
4255 */
4256 if (!(int_shadow & mask))
4257 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4258}
4259
54b8486f
GN		 4260static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4261{
4262 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4263 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4264 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4265 else if (ctxt->exception.error_code_valid)
4266 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4267 ctxt->exception.error_code);
54b8486f 4268 else
da9cb575 4269 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4270}
4271
8ec4722d
MG		 4272static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4273{
4274 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4275 int cs_db, cs_l;
4276
4277 cache_all_regs(vcpu);
4278
4279 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4280
4281 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4282 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4283 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4284 vcpu->arch.emulate_ctxt.mode =
4285 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4286 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4287 ? X86EMUL_MODE_VM86 : cs_l
4288 ? X86EMUL_MODE_PROT64 : cs_db
4289 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4290 memset(c, 0, sizeof(struct decode_cache));
4291 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4292}
4293
63995653
MG		 4294int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4295{
4296 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4297 int ret;
4298
4299 init_emulate_ctxt(vcpu);
4300
4301 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4302 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4303 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4304 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4305
4306 if (ret != X86EMUL_CONTINUE)
4307 return EMULATE_FAIL;
4308
4309 vcpu->arch.emulate_ctxt.eip = c->eip;
4310 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4311 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4312 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4313
4314 if (irq == NMI_VECTOR)
4315 vcpu->arch.nmi_pending = false;
4316 else
4317 vcpu->arch.interrupt.pending = false;
4318
4319 return EMULATE_DONE;
4320}
4321EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4322
6d77dbfc
GN		 4323static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4324{
fc3a9157
JR		 4325 int r = EMULATE_DONE;
4326
6d77dbfc
GN		 4327 ++vcpu->stat.insn_emulation_fail;
4328 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4329 if (!is_guest_mode(vcpu)) {
4330 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4331 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4332 vcpu->run->internal.ndata = 0;
4333 r = EMULATE_FAIL;
4334 }
6d77dbfc 4335 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4336
4337 return r;
6d77dbfc
GN		 4338}
4339
a6f177ef
GN		 4340static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4341{
4342 gpa_t gpa;
4343
68be0803
GN		 4344 if (tdp_enabled)
4345 return false;
4346
a6f177ef
GN		 4347 /*
4348 * if emulation was due to access to shadowed page table
4349 * and it failed try to unshadow page and re-entetr the
4350 * guest to let CPU execute the instruction.
4351 */
4352 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4353 return true;
4354
4355 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4356
4357 if (gpa == UNMAPPED_GVA)
4358 return true; /* let cpu generate fault */
4359
4360 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4361 return true;
4362
4363 return false;
4364}
4365
bbd9b64e 4366int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4367 unsigned long cr2,
4368 u16 error_code,
571008da 4369 int emulation_type)
bbd9b64e 4370{
95cb2295 4371 int r;
4d2179e1 4372 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4373
26eef70c 4374 kvm_clear_exception_queue(vcpu);
ad312c7c 4375 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4376 /*
56e82318 4377 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4378 * instead of direct ->regs accesses, can save hundred cycles
4379 * on Intel for instructions that don't read/change RSP, for
4380 * for example.
4381 */
4382 cache_all_regs(vcpu);
bbd9b64e 4383
571008da 4384 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4385 init_emulate_ctxt(vcpu);
95cb2295 4386 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4387 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4388 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4389
9aabc88f 4390 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4391 if (r == X86EMUL_PROPAGATE_FAULT)
4392 goto done;
bbd9b64e 4393
e46479f8 4394 trace_kvm_emulate_insn_start(vcpu);
571008da 4395
0cb5762e
AP		 4396 /* Only allow emulation of specific instructions on #UD
4397 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4398 if (emulation_type & EMULTYPE_TRAP_UD) {
4399 if (!c->twobyte)
4400 return EMULATE_FAIL;
4401 switch (c->b) {
4402 case 0x01: /* VMMCALL */
4403 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4404 return EMULATE_FAIL;
4405 break;
4406 case 0x34: /* sysenter */
4407 case 0x35: /* sysexit */
4408 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4409 return EMULATE_FAIL;
4410 break;
4411 case 0x05: /* syscall */
4412 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4413 return EMULATE_FAIL;
4414 break;
4415 default:
4416 return EMULATE_FAIL;
4417 }
4418
4419 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4420 return EMULATE_FAIL;
4421 }
571008da 4422
f2b5756b 4423 ++vcpu->stat.insn_emulation;
bbd9b64e 4424 if (r) {
a6f177ef 4425 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4426 return EMULATE_DONE;
6d77dbfc
GN		 4427 if (emulation_type & EMULTYPE_SKIP)
4428 return EMULATE_FAIL;
4429 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4430 }
4431 }
4432
ba8afb6b
GN		 4433 if (emulation_type & EMULTYPE_SKIP) {
4434 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4435 return EMULATE_DONE;
4436 }
4437
4d2179e1
GN		 4438 /* this is needed for vmware backdor interface to work since it
4439 changes registers values during IO operation */
4440 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4441
5cd21917 4442restart:
9aabc88f 4443 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4444
d2ddd1c4 4445 if (r == EMULATION_FAILED) {
a6f177ef 4446 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4447 return EMULATE_DONE;
4448
6d77dbfc 4449 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4450 }
4451
d47f00a6 4452done:
da9cb575 4453 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4454 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4455 r = EMULATE_DONE;
4456 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4457 if (!vcpu->arch.pio.in)
4458 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4459 r = EMULATE_DO_MMIO;
4460 } else if (vcpu->mmio_needed) {
3457e419
GN		 4461 if (vcpu->mmio_is_write)
4462 vcpu->mmio_needed = 0;
e85d28f8 4463 r = EMULATE_DO_MMIO;
d2ddd1c4 4464 } else if (r == EMULATION_RESTART)
5cd21917 4465 goto restart;
d2ddd1c4
GN		 4466 else
4467 r = EMULATE_DONE;
f850e2e6 4468
e85d28f8
GN		 4469 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4470 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4471 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4472 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4473 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4474
4475 return r;
de7d789a 4476}
bbd9b64e 4477EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4478
cf8f70bf 4479int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4480{
cf8f70bf
GN		 4481 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4482 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4483 /* do not return to emulator after return from userspace */
7972995b 4484 vcpu->arch.pio.count = 0;
de7d789a
CO		 4485 return ret;
4486}
cf8f70bf 4487EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4488
8cfdc000
ZA		 4489static void tsc_bad(void *info)
4490{
4491 __get_cpu_var(cpu_tsc_khz) = 0;
4492}
4493
4494static void tsc_khz_changed(void *data)
c8076604 4495{
8cfdc000
ZA		 4496 struct cpufreq_freqs *freq = data;
4497 unsigned long khz = 0;
4498
4499 if (data)
4500 khz = freq->new;
4501 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4502 khz = cpufreq_quick_get(raw_smp_processor_id());
4503 if (!khz)
4504 khz = tsc_khz;
4505 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4506}
4507
c8076604
GH		 4508static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4509 void *data)
4510{
4511 struct cpufreq_freqs *freq = data;
4512 struct kvm *kvm;
4513 struct kvm_vcpu *vcpu;
4514 int i, send_ipi = 0;
4515
8cfdc000
ZA		 4516 /*
4517 * We allow guests to temporarily run on slowing clocks,
4518 * provided we notify them after, or to run on accelerating
4519 * clocks, provided we notify them before. Thus time never
4520 * goes backwards.
4521 *
4522 * However, we have a problem. We can't atomically update
4523 * the frequency of a given CPU from this function; it is
4524 * merely a notifier, which can be called from any CPU.
4525 * Changing the TSC frequency at arbitrary points in time
4526 * requires a recomputation of local variables related to
4527 * the TSC for each VCPU. We must flag these local variables
4528 * to be updated and be sure the update takes place with the
4529 * new frequency before any guests proceed.
4530 *
4531 * Unfortunately, the combination of hotplug CPU and frequency
4532 * change creates an intractable locking scenario; the order
4533 * of when these callouts happen is undefined with respect to
4534 * CPU hotplug, and they can race with each other. As such,
4535 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4536 * undefined; you can actually have a CPU frequency change take
4537 * place in between the computation of X and the setting of the
4538 * variable. To protect against this problem, all updates of
4539 * the per_cpu tsc_khz variable are done in an interrupt
4540 * protected IPI, and all callers wishing to update the value
4541 * must wait for a synchronous IPI to complete (which is trivial
4542 * if the caller is on the CPU already). This establishes the
4543 * necessary total order on variable updates.
4544 *
4545 * Note that because a guest time update may take place
4546 * anytime after the setting of the VCPU's request bit, the
4547 * correct TSC value must be set before the request. However,
4548 * to ensure the update actually makes it to any guest which
4549 * starts running in hardware virtualization between the set
4550 * and the acquisition of the spinlock, we must also ping the
4551 * CPU after setting the request bit.
4552 *
4553 */
4554
c8076604
GH		 4555 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4556 return 0;
4557 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4558 return 0;
8cfdc000
ZA		 4559
4560 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4561
4562 spin_lock(&kvm_lock);
4563 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4564 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4565 if (vcpu->cpu != freq->cpu)
4566 continue;
c285545f 4567 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4568 if (vcpu->cpu != smp_processor_id())
8cfdc000 4569 send_ipi = 1;
c8076604
GH		 4570 }
4571 }
4572 spin_unlock(&kvm_lock);
4573
4574 if (freq->old < freq->new && send_ipi) {
4575 /*
4576 * We upscale the frequency. Must make the guest
4577 * doesn't see old kvmclock values while running with
4578 * the new frequency, otherwise we risk the guest sees
4579 * time go backwards.
4580 *
4581 * In case we update the frequency for another cpu
4582 * (which might be in guest context) send an interrupt
4583 * to kick the cpu out of guest context. Next time
4584 * guest context is entered kvmclock will be updated,
4585 * so the guest will not see stale values.
4586 */
8cfdc000 4587 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4588 }
4589 return 0;
4590}
4591
4592static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4593 .notifier_call = kvmclock_cpufreq_notifier
4594};
4595
4596static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4597 unsigned long action, void *hcpu)
4598{
4599 unsigned int cpu = (unsigned long)hcpu;
4600
4601 switch (action) {
4602 case CPU_ONLINE:
4603 case CPU_DOWN_FAILED:
4604 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4605 break;
4606 case CPU_DOWN_PREPARE:
4607 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4608 break;
4609 }
4610 return NOTIFY_OK;
4611}
4612
4613static struct notifier_block kvmclock_cpu_notifier_block = {
4614 .notifier_call = kvmclock_cpu_notifier,
4615 .priority = -INT_MAX
c8076604
GH		 4616};
4617
b820cc0c
ZA		 4618static void kvm_timer_init(void)
4619{
4620 int cpu;
4621
c285545f 4622 max_tsc_khz = tsc_khz;
8cfdc000 4623 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4624 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4625#ifdef CONFIG_CPU_FREQ
4626 struct cpufreq_policy policy;
4627 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4628 cpu = get_cpu();
4629 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4630 if (policy.cpuinfo.max_freq)
4631 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4632 put_cpu();
c285545f 4633#endif
b820cc0c
ZA		 4634 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4635 CPUFREQ_TRANSITION_NOTIFIER);
4636 }
c285545f 4637 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4638 for_each_online_cpu(cpu)
4639 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4640}
4641
ff9d07a0
ZY		 4642static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4643
4644static int kvm_is_in_guest(void)
4645{
4646 return percpu_read(current_vcpu) != NULL;
4647}
4648
4649static int kvm_is_user_mode(void)
4650{
4651 int user_mode = 3;
dcf46b94 4652
ff9d07a0
ZY		 4653 if (percpu_read(current_vcpu))
4654 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4655
ff9d07a0
ZY		 4656 return user_mode != 0;
4657}
4658
4659static unsigned long kvm_get_guest_ip(void)
4660{
4661 unsigned long ip = 0;
dcf46b94 4662
ff9d07a0
ZY		 4663 if (percpu_read(current_vcpu))
4664 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4665
ff9d07a0
ZY		 4666 return ip;
4667}
4668
4669static struct perf_guest_info_callbacks kvm_guest_cbs = {
4670 .is_in_guest = kvm_is_in_guest,
4671 .is_user_mode = kvm_is_user_mode,
4672 .get_guest_ip = kvm_get_guest_ip,
4673};
4674
4675void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4676{
4677 percpu_write(current_vcpu, vcpu);
4678}
4679EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4680
4681void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4682{
4683 percpu_write(current_vcpu, NULL);
4684}
4685EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4686
f8c16bba 4687int kvm_arch_init(void *opaque)
043405e1 4688{
b820cc0c 4689 int r;
f8c16bba
ZX		 4690 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4691
f8c16bba
ZX		 4692 if (kvm_x86_ops) {
4693 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4694 r = -EEXIST;
4695 goto out;
f8c16bba
ZX		 4696 }
4697
4698 if (!ops->cpu_has_kvm_support()) {
4699 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4700 r = -EOPNOTSUPP;
4701 goto out;
f8c16bba
ZX		 4702 }
4703 if (ops->disabled_by_bios()) {
4704 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4705 r = -EOPNOTSUPP;
4706 goto out;
f8c16bba
ZX		 4707 }
4708
97db56ce
AK		 4709 r = kvm_mmu_module_init();
4710 if (r)
4711 goto out;
4712
4713 kvm_init_msr_list();
4714
f8c16bba 4715 kvm_x86_ops = ops;
56c6d28a 4716 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4717 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4718 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4719
b820cc0c 4720 kvm_timer_init();
c8076604 4721
ff9d07a0
ZY		 4722 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4723
2acf923e
DC		 4724 if (cpu_has_xsave)
4725 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4726
f8c16bba 4727 return 0;
56c6d28a
ZX		 4728
4729out:
56c6d28a 4730 return r;
043405e1 4731}
8776e519 4732
f8c16bba
ZX		 4733void kvm_arch_exit(void)
4734{
ff9d07a0
ZY		 4735 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4736
888d256e
JK		 4737 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4738 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4739 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4740 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4741 kvm_x86_ops = NULL;
56c6d28a
ZX		 4742 kvm_mmu_module_exit();
4743}
f8c16bba 4744
8776e519
HB		 4745int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4746{
4747 ++vcpu->stat.halt_exits;
4748 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4749 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4750 return 1;
4751 } else {
4752 vcpu->run->exit_reason = KVM_EXIT_HLT;
4753 return 0;
4754 }
4755}
4756EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4757
2f333bcb
MT		 4758static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4759 unsigned long a1)
4760{
4761 if (is_long_mode(vcpu))
4762 return a0;
4763 else
4764 return a0 | ((gpa_t)a1 << 32);
4765}
4766
55cd8e5a
GN		 4767int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4768{
4769 u64 param, ingpa, outgpa, ret;
4770 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4771 bool fast, longmode;
4772 int cs_db, cs_l;
4773
4774 /*
4775 * hypercall generates UD from non zero cpl and real mode
4776 * per HYPER-V spec
4777 */
3eeb3288 4778 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4779 kvm_queue_exception(vcpu, UD_VECTOR);
4780 return 0;
4781 }
4782
4783 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4784 longmode = is_long_mode(vcpu) && cs_l == 1;
4785
4786 if (!longmode) {
ccd46936
GN		 4787 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4788 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4789 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4790 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4791 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4792 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4793 }
4794#ifdef CONFIG_X86_64
4795 else {
4796 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4797 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4798 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4799 }
4800#endif
4801
4802 code = param & 0xffff;
4803 fast = (param >> 16) & 0x1;
4804 rep_cnt = (param >> 32) & 0xfff;
4805 rep_idx = (param >> 48) & 0xfff;
4806
4807 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4808
c25bc163
GN		 4809 switch (code) {
4810 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4811 kvm_vcpu_on_spin(vcpu);
4812 break;
4813 default:
4814 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4815 break;
4816 }
55cd8e5a
GN		 4817
4818 ret = res | (((u64)rep_done & 0xfff) << 32);
4819 if (longmode) {
4820 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4821 } else {
4822 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4823 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4824 }
4825
4826 return 1;
4827}
4828
8776e519
HB		 4829int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4830{
4831 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4832 int r = 1;
8776e519 4833
55cd8e5a
GN		 4834 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4835 return kvm_hv_hypercall(vcpu);
4836
5fdbf976
MT		 4837 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4838 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4839 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4840 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4841 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4842
229456fc 4843 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4844
8776e519
HB		 4845 if (!is_long_mode(vcpu)) {
4846 nr &= 0xFFFFFFFF;
4847 a0 &= 0xFFFFFFFF;
4848 a1 &= 0xFFFFFFFF;
4849 a2 &= 0xFFFFFFFF;
4850 a3 &= 0xFFFFFFFF;
4851 }
4852
07708c4a
JK		 4853 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4854 ret = -KVM_EPERM;
4855 goto out;
4856 }
4857
8776e519 4858 switch (nr) {
b93463aa
AK		 4859 case KVM_HC_VAPIC_POLL_IRQ:
4860 ret = 0;
4861 break;
2f333bcb
MT		 4862 case KVM_HC_MMU_OP:
4863 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4864 break;
8776e519
HB		 4865 default:
4866 ret = -KVM_ENOSYS;
4867 break;
4868 }
07708c4a 4869out:
5fdbf976 4870 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4871 ++vcpu->stat.hypercalls;
2f333bcb 4872 return r;
8776e519
HB		 4873}
4874EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4875
4876int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4877{
4878 char instruction[3];
5fdbf976 4879 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4880
8776e519
HB		 4881 /*
4882 * Blow out the MMU to ensure that no other VCPU has an active mapping
4883 * to ensure that the updated hypercall appears atomically across all
4884 * VCPUs.
4885 */
4886 kvm_mmu_zap_all(vcpu->kvm);
4887
8776e519 4888 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4889
8fe681e9 4890 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4891}
4892
8776e519
HB		 4893void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4894{
89a27f4d 4895 struct desc_ptr dt = { limit, base };
8776e519
HB		 4896
4897 kvm_x86_ops->set_gdt(vcpu, &dt);
4898}
4899
4900void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4901{
89a27f4d 4902 struct desc_ptr dt = { limit, base };
8776e519
HB		 4903
4904 kvm_x86_ops->set_idt(vcpu, &dt);
4905}
4906
07716717
DK		 4907static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4908{
ad312c7c
ZX		 4909 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4910 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4911
4912 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4913 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4914 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4915 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4916 if (ej->function == e->function) {
4917 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4918 return j;
4919 }
4920 }
4921 return 0; /* silence gcc, even though control never reaches here */
4922}
4923
4924/* find an entry with matching function, matching index (if needed), and that
4925 * should be read next (if it's stateful) */
4926static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4927 u32 function, u32 index)
4928{
4929 if (e->function != function)
4930 return 0;
4931 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4932 return 0;
4933 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4934 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4935 return 0;
4936 return 1;
4937}
4938
d8017474
AG		 4939struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4940 u32 function, u32 index)
8776e519
HB		 4941{
4942 int i;
d8017474 4943 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4944
ad312c7c 4945 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4946 struct kvm_cpuid_entry2 *e;
4947
ad312c7c 4948 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4949 if (is_matching_cpuid_entry(e, function, index)) {
4950 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4951 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4952 best = e;
4953 break;
4954 }
4955 /*
4956 * Both basic or both extended?
4957 */
4958 if (((e->function ^ function) & 0x80000000) == 0)
4959 if (!best || e->function > best->function)
4960 best = e;
4961 }
d8017474
AG		 4962 return best;
4963}
0e851880 4964EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4965
82725b20
DE		 4966int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4967{
4968 struct kvm_cpuid_entry2 *best;
4969
f7a71197
AK		 4970 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4971 if (!best || best->eax < 0x80000008)
4972 goto not_found;
82725b20
DE		 4973 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4974 if (best)
4975 return best->eax & 0xff;
f7a71197 4976not_found:
82725b20
DE		 4977 return 36;
4978}
4979
d8017474
AG		 4980void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4981{
4982 u32 function, index;
4983 struct kvm_cpuid_entry2 *best;
4984
4985 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4986 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4987 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4988 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4989 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4990 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4991 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4992 if (best) {
5fdbf976
MT		 4993 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4994 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4995 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4996 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4997 }
8776e519 4998 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4999 trace_kvm_cpuid(function,
5000 kvm_register_read(vcpu, VCPU_REGS_RAX),
5001 kvm_register_read(vcpu, VCPU_REGS_RBX),
5002 kvm_register_read(vcpu, VCPU_REGS_RCX),
5003 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5004}
5005EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5006
b6c7a5dc
HB		 5007/*
5008 * Check if userspace requested an interrupt window, and that the
5009 * interrupt window is open.
5010 *
5011 * No need to exit to userspace if we already have an interrupt queued.
5012 */
851ba692 5013static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5014{
8061823a 5015 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5016 vcpu->run->request_interrupt_window &&
5df56646 5017 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5018}
5019
851ba692 5020static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5021{
851ba692
AK		 5022 struct kvm_run *kvm_run = vcpu->run;
5023
91586a3b 5024 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5025 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5026 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5027 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5028 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5029 else
b6c7a5dc 5030 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5031 kvm_arch_interrupt_allowed(vcpu) &&
5032 !kvm_cpu_has_interrupt(vcpu) &&
5033 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5034}
5035
b93463aa
AK		 5036static void vapic_enter(struct kvm_vcpu *vcpu)
5037{
5038 struct kvm_lapic *apic = vcpu->arch.apic;
5039 struct page *page;
5040
5041 if (!apic || !apic->vapic_addr)
5042 return;
5043
5044 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5045
5046 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5047}
5048
5049static void vapic_exit(struct kvm_vcpu *vcpu)
5050{
5051 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5052 int idx;
b93463aa
AK		 5053
5054 if (!apic || !apic->vapic_addr)
5055 return;
5056
f656ce01 5057 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5058 kvm_release_page_dirty(apic->vapic_page);
5059 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5060 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5061}
5062
95ba8273
GN		 5063static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5064{
5065 int max_irr, tpr;
5066
5067 if (!kvm_x86_ops->update_cr8_intercept)
5068 return;
5069
88c808fd
AK		 5070 if (!vcpu->arch.apic)
5071 return;
5072
8db3baa2
GN		 5073 if (!vcpu->arch.apic->vapic_addr)
5074 max_irr = kvm_lapic_find_highest_irr(vcpu);
5075 else
5076 max_irr = -1;
95ba8273
GN		 5077
5078 if (max_irr != -1)
5079 max_irr >>= 4;
5080
5081 tpr = kvm_lapic_get_cr8(vcpu);
5082
5083 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5084}
5085
851ba692 5086static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5087{
5088 /* try to reinject previous events if any */
b59bb7bd 5089 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5090 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5091 vcpu->arch.exception.has_error_code,
5092 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5093 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5094 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5095 vcpu->arch.exception.error_code,
5096 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5097 return;
5098 }
5099
95ba8273
GN		 5100 if (vcpu->arch.nmi_injected) {
5101 kvm_x86_ops->set_nmi(vcpu);
5102 return;
5103 }
5104
5105 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5106 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5107 return;
5108 }
5109
5110 /* try to inject new event if pending */
5111 if (vcpu->arch.nmi_pending) {
5112 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5113 vcpu->arch.nmi_pending = false;
5114 vcpu->arch.nmi_injected = true;
5115 kvm_x86_ops->set_nmi(vcpu);
5116 }
5117 } else if (kvm_cpu_has_interrupt(vcpu)) {
5118 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5119 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5120 false);
5121 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5122 }
5123 }
5124}
5125
2acf923e
DC		 5126static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5127{
5128 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5129 !vcpu->guest_xcr0_loaded) {
5130 /* kvm_set_xcr() also depends on this */
5131 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5132 vcpu->guest_xcr0_loaded = 1;
5133 }
5134}
5135
5136static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5137{
5138 if (vcpu->guest_xcr0_loaded) {
5139 if (vcpu->arch.xcr0 != host_xcr0)
5140 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5141 vcpu->guest_xcr0_loaded = 0;
5142 }
5143}
5144
851ba692 5145static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5146{
5147 int r;
6a8b1d13 5148 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5149 vcpu->run->request_interrupt_window;
b6c7a5dc 5150
3e007509 5151 if (vcpu->requests) {
a8eeb04a 5152 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5153 kvm_mmu_unload(vcpu);
a8eeb04a 5154 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5155 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5156 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5157 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5158 if (unlikely(r))
5159 goto out;
5160 }
a8eeb04a 5161 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5162 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5163 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5164 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5165 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5166 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5167 r = 0;
5168 goto out;
5169 }
a8eeb04a 5170 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5171 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5172 r = 0;
5173 goto out;
5174 }
a8eeb04a 5175 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5176 vcpu->fpu_active = 0;
5177 kvm_x86_ops->fpu_deactivate(vcpu);
5178 }
af585b92
GN		 5179 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5180 /* Page is swapped out. Do synthetic halt */
5181 vcpu->arch.apf.halted = true;
5182 r = 1;
5183 goto out;
5184 }
2f52d58c 5185 }
b93463aa 5186
3e007509
AK		 5187 r = kvm_mmu_reload(vcpu);
5188 if (unlikely(r))
5189 goto out;
5190
b463a6f7
AK		 5191 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5192 inject_pending_event(vcpu);
5193
5194 /* enable NMI/IRQ window open exits if needed */
5195 if (vcpu->arch.nmi_pending)
5196 kvm_x86_ops->enable_nmi_window(vcpu);
5197 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5198 kvm_x86_ops->enable_irq_window(vcpu);
5199
5200 if (kvm_lapic_enabled(vcpu)) {
5201 update_cr8_intercept(vcpu);
5202 kvm_lapic_sync_to_vapic(vcpu);
5203 }
5204 }
5205
b6c7a5dc
HB		 5206 preempt_disable();
5207
5208 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5209 if (vcpu->fpu_active)
5210 kvm_load_guest_fpu(vcpu);
2acf923e 5211 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5212
d94e1dc9
AK		 5213 atomic_set(&vcpu->guest_mode, 1);
5214 smp_wmb();
b6c7a5dc 5215
d94e1dc9 5216 local_irq_disable();
32f88400 5217
d94e1dc9
AK		 5218 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5219 || need_resched() || signal_pending(current)) {
5220 atomic_set(&vcpu->guest_mode, 0);
5221 smp_wmb();
6c142801
AK		 5222 local_irq_enable();
5223 preempt_enable();
b463a6f7 5224 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5225 r = 1;
5226 goto out;
5227 }
5228
f656ce01 5229 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5230
b6c7a5dc
HB		 5231 kvm_guest_enter();
5232
42dbaa5a 5233 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5234 set_debugreg(0, 7);
5235 set_debugreg(vcpu->arch.eff_db[0], 0);
5236 set_debugreg(vcpu->arch.eff_db[1], 1);
5237 set_debugreg(vcpu->arch.eff_db[2], 2);
5238 set_debugreg(vcpu->arch.eff_db[3], 3);
5239 }
b6c7a5dc 5240
229456fc 5241 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5242 kvm_x86_ops->run(vcpu);
b6c7a5dc 5243
24f1e32c
FW		 5244 /*
5245 * If the guest has used debug registers, at least dr7
5246 * will be disabled while returning to the host.
5247 * If we don't have active breakpoints in the host, we don't
5248 * care about the messed up debug address registers. But if
5249 * we have some of them active, restore the old state.
5250 */
59d8eb53 5251 if (hw_breakpoint_active())
24f1e32c 5252 hw_breakpoint_restore();
42dbaa5a 5253
1d5f066e
ZA		 5254 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5255
d94e1dc9
AK		 5256 atomic_set(&vcpu->guest_mode, 0);
5257 smp_wmb();
b6c7a5dc
HB		 5258 local_irq_enable();
5259
5260 ++vcpu->stat.exits;
5261
5262 /*
5263 * We must have an instruction between local_irq_enable() and
5264 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5265 * the interrupt shadow. The stat.exits increment will do nicely.
5266 * But we need to prevent reordering, hence this barrier():
5267 */
5268 barrier();
5269
5270 kvm_guest_exit();
5271
5272 preempt_enable();
5273
f656ce01 5274 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5275
b6c7a5dc
HB		 5276 /*
5277 * Profile KVM exit RIPs:
5278 */
5279 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5280 unsigned long rip = kvm_rip_read(vcpu);
5281 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5282 }
5283
298101da 5284
b93463aa
AK		 5285 kvm_lapic_sync_from_vapic(vcpu);
5286
851ba692 5287 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5288out:
5289 return r;
5290}
b6c7a5dc 5291
09cec754 5292
851ba692 5293static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5294{
5295 int r;
f656ce01 5296 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5297
5298 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5299 pr_debug("vcpu %d received sipi with vector # %x\n",
5300 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5301 kvm_lapic_reset(vcpu);
5f179287 5302 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5303 if (r)
5304 return r;
5305 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5306 }
5307
f656ce01 5308 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5309 vapic_enter(vcpu);
5310
5311 r = 1;
5312 while (r > 0) {
af585b92
GN		 5313 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5314 !vcpu->arch.apf.halted)
851ba692 5315 r = vcpu_enter_guest(vcpu);
d7690175 5316 else {
f656ce01 5317 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5318 kvm_vcpu_block(vcpu);
f656ce01 5319 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5320 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5321 {
5322 switch(vcpu->arch.mp_state) {
5323 case KVM_MP_STATE_HALTED:
d7690175 5324 vcpu->arch.mp_state =
09cec754
GN		 5325 KVM_MP_STATE_RUNNABLE;
5326 case KVM_MP_STATE_RUNNABLE:
af585b92 5327 vcpu->arch.apf.halted = false;
09cec754
GN		 5328 break;
5329 case KVM_MP_STATE_SIPI_RECEIVED:
5330 default:
5331 r = -EINTR;
5332 break;
5333 }
5334 }
d7690175
MT		 5335 }
5336
09cec754
GN		 5337 if (r <= 0)
5338 break;
5339
5340 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5341 if (kvm_cpu_has_pending_timer(vcpu))
5342 kvm_inject_pending_timer_irqs(vcpu);
5343
851ba692 5344 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5345 r = -EINTR;
851ba692 5346 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5347 ++vcpu->stat.request_irq_exits;
5348 }
af585b92
GN		 5349
5350 kvm_check_async_pf_completion(vcpu);
5351
09cec754
GN		 5352 if (signal_pending(current)) {
5353 r = -EINTR;
851ba692 5354 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5355 ++vcpu->stat.signal_exits;
5356 }
5357 if (need_resched()) {
f656ce01 5358 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5359 kvm_resched(vcpu);
f656ce01 5360 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5361 }
b6c7a5dc
HB		 5362 }
5363
f656ce01 5364 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5365
b93463aa
AK		 5366 vapic_exit(vcpu);
5367
b6c7a5dc
HB		 5368 return r;
5369}
5370
5371int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5372{
5373 int r;
5374 sigset_t sigsaved;
5375
ac9f6dc0
AK		 5376 if (vcpu->sigset_active)
5377 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5378
a4535290 5379 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5380 kvm_vcpu_block(vcpu);
d7690175 5381 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5382 r = -EAGAIN;
5383 goto out;
b6c7a5dc
HB		 5384 }
5385
b6c7a5dc 5386 /* re-sync apic's tpr */
eea1cff9
AP		 5387 if (!irqchip_in_kernel(vcpu->kvm)) {
5388 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5389 r = -EINVAL;
5390 goto out;
5391 }
5392 }
b6c7a5dc 5393
d2ddd1c4 5394 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5395 if (vcpu->mmio_needed) {
5396 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5397 vcpu->mmio_read_completed = 1;
5398 vcpu->mmio_needed = 0;
b6c7a5dc 5399 }
f656ce01 5400 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5401 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5402 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5403 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5404 r = 0;
5405 goto out;
5406 }
5407 }
5fdbf976
MT		 5408 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5409 kvm_register_write(vcpu, VCPU_REGS_RAX,
5410 kvm_run->hypercall.ret);
b6c7a5dc 5411
851ba692 5412 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5413
5414out:
f1d86e46 5415 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5416 if (vcpu->sigset_active)
5417 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5418
b6c7a5dc
HB		 5419 return r;
5420}
5421
5422int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5423{
5fdbf976
MT		 5424 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5425 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5426 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5427 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5428 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5429 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5430 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5431 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5432#ifdef CONFIG_X86_64
5fdbf976
MT		 5433 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5434 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5435 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5436 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5437 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5438 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5439 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5440 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5441#endif
5442
5fdbf976 5443 regs->rip = kvm_rip_read(vcpu);
91586a3b 5444 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5445
b6c7a5dc
HB		 5446 return 0;
5447}
5448
5449int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5450{
5fdbf976
MT		 5451 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5452 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5453 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5454 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5455 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5456 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5457 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5458 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5459#ifdef CONFIG_X86_64
5fdbf976
MT		 5460 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5461 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5462 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5463 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5464 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5465 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5466 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5467 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5468#endif
5469
5fdbf976 5470 kvm_rip_write(vcpu, regs->rip);
91586a3b 5471 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5472
b4f14abd
JK		 5473 vcpu->arch.exception.pending = false;
5474
3842d135
AK		 5475 kvm_make_request(KVM_REQ_EVENT, vcpu);
5476
b6c7a5dc
HB		 5477 return 0;
5478}
5479
b6c7a5dc
HB		 5480void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5481{
5482 struct kvm_segment cs;
5483
3e6e0aab 5484 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5485 *db = cs.db;
5486 *l = cs.l;
5487}
5488EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5489
5490int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5491 struct kvm_sregs *sregs)
5492{
89a27f4d 5493 struct desc_ptr dt;
b6c7a5dc 5494
3e6e0aab
GT		 5495 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5496 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5497 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5498 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5499 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5500 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5501
3e6e0aab
GT		 5502 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5503 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5504
5505 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5506 sregs->idt.limit = dt.size;
5507 sregs->idt.base = dt.address;
b6c7a5dc 5508 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5509 sregs->gdt.limit = dt.size;
5510 sregs->gdt.base = dt.address;
b6c7a5dc 5511
4d4ec087 5512 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5513 sregs->cr2 = vcpu->arch.cr2;
5514 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5515 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5516 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5517 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5518 sregs->apic_base = kvm_get_apic_base(vcpu);
5519
923c61bb 5520 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5521
36752c9b 5522 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5523 set_bit(vcpu->arch.interrupt.nr,
5524 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5525
b6c7a5dc
HB		 5526 return 0;
5527}
5528
62d9f0db
MT		 5529int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5530 struct kvm_mp_state *mp_state)
5531{
62d9f0db 5532 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5533 return 0;
5534}
5535
5536int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5537 struct kvm_mp_state *mp_state)
5538{
62d9f0db 5539 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5540 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5541 return 0;
5542}
5543
e269fb21
JK		 5544int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5545 bool has_error_code, u32 error_code)
b6c7a5dc 5546{
4d2179e1 5547 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5548 int ret;
e01c2426 5549
8ec4722d 5550 init_emulate_ctxt(vcpu);
c697518a 5551
9aabc88f 5552 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5553 tss_selector, reason, has_error_code,
5554 error_code);
c697518a 5555
c697518a 5556 if (ret)
19d04437 5557 return EMULATE_FAIL;
37817f29 5558
4d2179e1 5559 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5560 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5561 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5562 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5563 return EMULATE_DONE;
37817f29
IE		 5564}
5565EXPORT_SYMBOL_GPL(kvm_task_switch);
5566
b6c7a5dc
HB		 5567int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5568 struct kvm_sregs *sregs)
5569{
5570 int mmu_reset_needed = 0;
923c61bb 5571 int pending_vec, max_bits;
89a27f4d 5572 struct desc_ptr dt;
b6c7a5dc 5573
89a27f4d
GN		 5574 dt.size = sregs->idt.limit;
5575 dt.address = sregs->idt.base;
b6c7a5dc 5576 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5577 dt.size = sregs->gdt.limit;
5578 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5579 kvm_x86_ops->set_gdt(vcpu, &dt);
5580
ad312c7c
ZX		 5581 vcpu->arch.cr2 = sregs->cr2;
5582 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5583 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5584
2d3ad1f4 5585 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5586
f6801dff 5587 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5588 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5589 kvm_set_apic_base(vcpu, sregs->apic_base);
5590
4d4ec087 5591 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5592 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5593 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5594
fc78f519 5595 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5596 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5597 if (sregs->cr4 & X86_CR4_OSXSAVE)
5598 update_cpuid(vcpu);
7c93be44 5599 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5600 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5601 mmu_reset_needed = 1;
5602 }
b6c7a5dc
HB		 5603
5604 if (mmu_reset_needed)
5605 kvm_mmu_reset_context(vcpu);
5606
923c61bb
GN		 5607 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5608 pending_vec = find_first_bit(
5609 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5610 if (pending_vec < max_bits) {
66fd3f7f 5611 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5612 pr_debug("Set back pending irq %d\n", pending_vec);
5613 if (irqchip_in_kernel(vcpu->kvm))
5614 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5615 }
5616
3e6e0aab
GT		 5617 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5618 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5619 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5620 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5621 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5622 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5623
3e6e0aab
GT		 5624 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5625 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5626
5f0269f5
ME		 5627 update_cr8_intercept(vcpu);
5628
9c3e4aab 5629 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5630 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5631 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5632 !is_protmode(vcpu))
9c3e4aab
MT		 5633 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5634
3842d135
AK		 5635 kvm_make_request(KVM_REQ_EVENT, vcpu);
5636
b6c7a5dc
HB		 5637 return 0;
5638}
5639
d0bfb940
JK		 5640int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5641 struct kvm_guest_debug *dbg)
b6c7a5dc 5642{
355be0b9 5643 unsigned long rflags;
ae675ef0 5644 int i, r;
b6c7a5dc 5645
4f926bf2
JK		 5646 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5647 r = -EBUSY;
5648 if (vcpu->arch.exception.pending)
2122ff5e 5649 goto out;
4f926bf2
JK		 5650 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5651 kvm_queue_exception(vcpu, DB_VECTOR);
5652 else
5653 kvm_queue_exception(vcpu, BP_VECTOR);
5654 }
5655
91586a3b
JK		 5656 /*
5657 * Read rflags as long as potentially injected trace flags are still
5658 * filtered out.
5659 */
5660 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5661
5662 vcpu->guest_debug = dbg->control;
5663 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5664 vcpu->guest_debug = 0;
5665
5666 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5667 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5668 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5669 vcpu->arch.switch_db_regs =
5670 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5671 } else {
5672 for (i = 0; i < KVM_NR_DB_REGS; i++)
5673 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5674 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5675 }
5676
f92653ee
JK		 5677 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5678 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5679 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5680
91586a3b
JK		 5681 /*
5682 * Trigger an rflags update that will inject or remove the trace
5683 * flags.
5684 */
5685 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5686
355be0b9 5687 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5688
4f926bf2 5689 r = 0;
d0bfb940 5690
2122ff5e 5691out:
b6c7a5dc
HB		 5692
5693 return r;
5694}
5695
8b006791
ZX		 5696/*
5697 * Translate a guest virtual address to a guest physical address.
5698 */
5699int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5700 struct kvm_translation *tr)
5701{
5702 unsigned long vaddr = tr->linear_address;
5703 gpa_t gpa;
f656ce01 5704 int idx;
8b006791 5705
f656ce01 5706 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5707 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5708 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5709 tr->physical_address = gpa;
5710 tr->valid = gpa != UNMAPPED_GVA;
5711 tr->writeable = 1;
5712 tr->usermode = 0;
8b006791
ZX		 5713
5714 return 0;
5715}
5716
d0752060
HB		 5717int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5718{
98918833
SY		 5719 struct i387_fxsave_struct *fxsave =
5720 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5721
d0752060
HB		 5722 memcpy(fpu->fpr, fxsave->st_space, 128);
5723 fpu->fcw = fxsave->cwd;
5724 fpu->fsw = fxsave->swd;
5725 fpu->ftwx = fxsave->twd;
5726 fpu->last_opcode = fxsave->fop;
5727 fpu->last_ip = fxsave->rip;
5728 fpu->last_dp = fxsave->rdp;
5729 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5730
d0752060
HB		 5731 return 0;
5732}
5733
5734int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5735{
98918833
SY		 5736 struct i387_fxsave_struct *fxsave =
5737 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5738
d0752060
HB		 5739 memcpy(fxsave->st_space, fpu->fpr, 128);
5740 fxsave->cwd = fpu->fcw;
5741 fxsave->swd = fpu->fsw;
5742 fxsave->twd = fpu->ftwx;
5743 fxsave->fop = fpu->last_opcode;
5744 fxsave->rip = fpu->last_ip;
5745 fxsave->rdp = fpu->last_dp;
5746 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5747
d0752060
HB		 5748 return 0;
5749}
5750
10ab25cd 5751int fx_init(struct kvm_vcpu *vcpu)
d0752060 5752{
10ab25cd
JK		 5753 int err;
5754
5755 err = fpu_alloc(&vcpu->arch.guest_fpu);
5756 if (err)
5757 return err;
5758
98918833 5759 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5760
2acf923e
DC		 5761 /*
5762 * Ensure guest xcr0 is valid for loading
5763 */
5764 vcpu->arch.xcr0 = XSTATE_FP;
5765
ad312c7c 5766 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5767
5768 return 0;
d0752060
HB		 5769}
5770EXPORT_SYMBOL_GPL(fx_init);
5771
98918833
SY		 5772static void fx_free(struct kvm_vcpu *vcpu)
5773{
5774 fpu_free(&vcpu->arch.guest_fpu);
5775}
5776
d0752060
HB		 5777void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5778{
2608d7a1 5779 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5780 return;
5781
2acf923e
DC		 5782 /*
5783 * Restore all possible states in the guest,
5784 * and assume host would use all available bits.
5785 * Guest xcr0 would be loaded later.
5786 */
5787 kvm_put_guest_xcr0(vcpu);
d0752060 5788 vcpu->guest_fpu_loaded = 1;
7cf30855 5789 unlazy_fpu(current);
98918833 5790 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5791 trace_kvm_fpu(1);
d0752060 5792}
d0752060
HB		 5793
5794void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5795{
2acf923e
DC		 5796 kvm_put_guest_xcr0(vcpu);
5797
d0752060
HB		 5798 if (!vcpu->guest_fpu_loaded)
5799 return;
5800
5801 vcpu->guest_fpu_loaded = 0;
98918833 5802 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5803 ++vcpu->stat.fpu_reload;
a8eeb04a 5804 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5805 trace_kvm_fpu(0);
d0752060 5806}
e9b11c17
ZX		 5807
5808void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5809{
7f1ea208
JR		 5810 if (vcpu->arch.time_page) {
5811 kvm_release_page_dirty(vcpu->arch.time_page);
5812 vcpu->arch.time_page = NULL;
5813 }
5814
f5f48ee1 5815 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5816 fx_free(vcpu);
e9b11c17
ZX		 5817 kvm_x86_ops->vcpu_free(vcpu);
5818}
5819
5820struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5821 unsigned int id)
5822{
6755bae8
ZA		 5823 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5824 printk_once(KERN_WARNING
5825 "kvm: SMP vm created on host with unstable TSC; "
5826 "guest TSC will not be reliable\n");
26e5215f
AK		 5827 return kvm_x86_ops->vcpu_create(kvm, id);
5828}
e9b11c17 5829
26e5215f
AK		 5830int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5831{
5832 int r;
e9b11c17 5833
0bed3b56 5834 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5835 vcpu_load(vcpu);
5836 r = kvm_arch_vcpu_reset(vcpu);
5837 if (r == 0)
5838 r = kvm_mmu_setup(vcpu);
5839 vcpu_put(vcpu);
5840 if (r < 0)
5841 goto free_vcpu;
5842
26e5215f 5843 return 0;
e9b11c17
ZX		 5844free_vcpu:
5845 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5846 return r;
e9b11c17
ZX		 5847}
5848
d40ccc62 5849void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5850{
344d9588
GN		 5851 vcpu->arch.apf.msr_val = 0;
5852
e9b11c17
ZX		 5853 vcpu_load(vcpu);
5854 kvm_mmu_unload(vcpu);
5855 vcpu_put(vcpu);
5856
98918833 5857 fx_free(vcpu);
e9b11c17
ZX		 5858 kvm_x86_ops->vcpu_free(vcpu);
5859}
5860
5861int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5862{
448fa4a9
JK		 5863 vcpu->arch.nmi_pending = false;
5864 vcpu->arch.nmi_injected = false;
5865
42dbaa5a
JK		 5866 vcpu->arch.switch_db_regs = 0;
5867 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5868 vcpu->arch.dr6 = DR6_FIXED_1;
5869 vcpu->arch.dr7 = DR7_FIXED_1;
5870
3842d135 5871 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5872 vcpu->arch.apf.msr_val = 0;
3842d135 5873
af585b92
GN		 5874 kvm_clear_async_pf_completion_queue(vcpu);
5875 kvm_async_pf_hash_reset(vcpu);
5876 vcpu->arch.apf.halted = false;
5877
e9b11c17
ZX		 5878 return kvm_x86_ops->vcpu_reset(vcpu);
5879}
5880
10474ae8 5881int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5882{
ca84d1a2
ZA		 5883 struct kvm *kvm;
5884 struct kvm_vcpu *vcpu;
5885 int i;
18863bdd
AK		 5886
5887 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5888 list_for_each_entry(kvm, &vm_list, vm_list)
5889 kvm_for_each_vcpu(i, vcpu, kvm)
5890 if (vcpu->cpu == smp_processor_id())
c285545f 5891 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5892 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5893}
5894
5895void kvm_arch_hardware_disable(void *garbage)
5896{
5897 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5898 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5899}
5900
5901int kvm_arch_hardware_setup(void)
5902{
5903 return kvm_x86_ops->hardware_setup();
5904}
5905
5906void kvm_arch_hardware_unsetup(void)
5907{
5908 kvm_x86_ops->hardware_unsetup();
5909}
5910
5911void kvm_arch_check_processor_compat(void *rtn)
5912{
5913 kvm_x86_ops->check_processor_compatibility(rtn);
5914}
5915
5916int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5917{
5918 struct page *page;
5919 struct kvm *kvm;
5920 int r;
5921
5922 BUG_ON(vcpu->kvm == NULL);
5923 kvm = vcpu->kvm;
5924
9aabc88f 5925 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5926 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5927 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5928 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5929 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5930 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5931 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5932 else
a4535290 5933 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5934
5935 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5936 if (!page) {
5937 r = -ENOMEM;
5938 goto fail;
5939 }
ad312c7c 5940 vcpu->arch.pio_data = page_address(page);
e9b11c17 5941
c285545f
ZA		 5942 if (!kvm->arch.virtual_tsc_khz)
5943 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5944
e9b11c17
ZX		 5945 r = kvm_mmu_create(vcpu);
5946 if (r < 0)
5947 goto fail_free_pio_data;
5948
5949 if (irqchip_in_kernel(kvm)) {
5950 r = kvm_create_lapic(vcpu);
5951 if (r < 0)
5952 goto fail_mmu_destroy;
5953 }
5954
890ca9ae
HY		 5955 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5956 GFP_KERNEL);
5957 if (!vcpu->arch.mce_banks) {
5958 r = -ENOMEM;
443c39bc 5959 goto fail_free_lapic;
890ca9ae
HY		 5960 }
5961 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5962
f5f48ee1
SY		 5963 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5964 goto fail_free_mce_banks;
5965
af585b92
GN		 5966 kvm_async_pf_hash_reset(vcpu);
5967
e9b11c17 5968 return 0;
f5f48ee1
SY		 5969fail_free_mce_banks:
5970 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5971fail_free_lapic:
5972 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5973fail_mmu_destroy:
5974 kvm_mmu_destroy(vcpu);
5975fail_free_pio_data:
ad312c7c 5976 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5977fail:
5978 return r;
5979}
5980
5981void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5982{
f656ce01
MT		 5983 int idx;
5984
36cb93fd 5985 kfree(vcpu->arch.mce_banks);
e9b11c17 5986 kvm_free_lapic(vcpu);
f656ce01 5987 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5988 kvm_mmu_destroy(vcpu);
f656ce01 5989 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5990 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5991}
d19a9cd2 5992
d89f5eff 5993int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 5994{
f05e70ac 5995 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5996 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5997
5550af4d
SY		 5998 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5999 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6000
99e3e30a 6001 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6002
d89f5eff 6003 return 0;
d19a9cd2
ZX		 6004}
6005
6006static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6007{
6008 vcpu_load(vcpu);
6009 kvm_mmu_unload(vcpu);
6010 vcpu_put(vcpu);
6011}
6012
6013static void kvm_free_vcpus(struct kvm *kvm)
6014{
6015 unsigned int i;
988a2cae 6016 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6017
6018 /*
6019 * Unpin any mmu pages first.
6020 */
af585b92
GN		 6021 kvm_for_each_vcpu(i, vcpu, kvm) {
6022 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6023 kvm_unload_vcpu_mmu(vcpu);
af585b92 6024 }
988a2cae
GN		 6025 kvm_for_each_vcpu(i, vcpu, kvm)
6026 kvm_arch_vcpu_free(vcpu);
6027
6028 mutex_lock(&kvm->lock);
6029 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6030 kvm->vcpus[i] = NULL;
d19a9cd2 6031
988a2cae
GN		 6032 atomic_set(&kvm->online_vcpus, 0);
6033 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6034}
6035
ad8ba2cd
SY		 6036void kvm_arch_sync_events(struct kvm *kvm)
6037{
ba4cef31 6038 kvm_free_all_assigned_devices(kvm);
aea924f6 6039 kvm_free_pit(kvm);
ad8ba2cd
SY		 6040}
6041
d19a9cd2
ZX		 6042void kvm_arch_destroy_vm(struct kvm *kvm)
6043{
6eb55818 6044 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6045 kfree(kvm->arch.vpic);
6046 kfree(kvm->arch.vioapic);
d19a9cd2 6047 kvm_free_vcpus(kvm);
3d45830c
AK		 6048 if (kvm->arch.apic_access_page)
6049 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6050 if (kvm->arch.ept_identity_pagetable)
6051 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6052}
0de10343 6053
f7784b8e
MT		 6054int kvm_arch_prepare_memory_region(struct kvm *kvm,
6055 struct kvm_memory_slot *memslot,
0de10343 6056 struct kvm_memory_slot old,
f7784b8e 6057 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6058 int user_alloc)
6059{
f7784b8e 6060 int npages = memslot->npages;
7ac77099
AK		 6061 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6062
6063 /* Prevent internal slot pages from being moved by fork()/COW. */
6064 if (memslot->id >= KVM_MEMORY_SLOTS)
6065 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6066
6067 /*To keep backward compatibility with older userspace,
6068 *x86 needs to hanlde !user_alloc case.
6069 */
6070 if (!user_alloc) {
6071 if (npages && !old.rmap) {
604b38ac
AA		 6072 unsigned long userspace_addr;
6073
72dc67a6 6074 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6075 userspace_addr = do_mmap(NULL, 0,
6076 npages * PAGE_SIZE,
6077 PROT_READ | PROT_WRITE,
7ac77099 6078 map_flags,
604b38ac 6079 0);
72dc67a6 6080 up_write(&current->mm->mmap_sem);
0de10343 6081
604b38ac
AA		 6082 if (IS_ERR((void *)userspace_addr))
6083 return PTR_ERR((void *)userspace_addr);
6084
604b38ac 6085 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6086 }
6087 }
6088
f7784b8e
MT		 6089
6090 return 0;
6091}
6092
6093void kvm_arch_commit_memory_region(struct kvm *kvm,
6094 struct kvm_userspace_memory_region *mem,
6095 struct kvm_memory_slot old,
6096 int user_alloc)
6097{
6098
6099 int npages = mem->memory_size >> PAGE_SHIFT;
6100
6101 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6102 int ret;
6103
6104 down_write(&current->mm->mmap_sem);
6105 ret = do_munmap(current->mm, old.userspace_addr,
6106 old.npages * PAGE_SIZE);
6107 up_write(&current->mm->mmap_sem);
6108 if (ret < 0)
6109 printk(KERN_WARNING
6110 "kvm_vm_ioctl_set_memory_region: "
6111 "failed to munmap memory\n");
6112 }
6113
7c8a83b7 6114 spin_lock(&kvm->mmu_lock);
f05e70ac 6115 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6116 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6117 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6118 }
6119
6120 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6121 spin_unlock(&kvm->mmu_lock);
0de10343 6122}
1d737c8a 6123
34d4cb8f
MT		 6124void kvm_arch_flush_shadow(struct kvm *kvm)
6125{
6126 kvm_mmu_zap_all(kvm);
8986ecc0 6127 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6128}
6129
1d737c8a
ZX		 6130int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6131{
af585b92
GN		 6132 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6133 !vcpu->arch.apf.halted)
6134 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6135 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6136 || vcpu->arch.nmi_pending ||
6137 (kvm_arch_interrupt_allowed(vcpu) &&
6138 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6139}
5736199a 6140
5736199a
ZX		 6141void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6142{
32f88400
MT		 6143 int me;
6144 int cpu = vcpu->cpu;
5736199a
ZX		 6145
6146 if (waitqueue_active(&vcpu->wq)) {
6147 wake_up_interruptible(&vcpu->wq);
6148 ++vcpu->stat.halt_wakeup;
6149 }
32f88400
MT		 6150
6151 me = get_cpu();
6152 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6153 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6154 smp_send_reschedule(cpu);
e9571ed5 6155 put_cpu();
5736199a 6156}
78646121
GN		 6157
6158int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6159{
6160 return kvm_x86_ops->interrupt_allowed(vcpu);
6161}
229456fc 6162
f92653ee
JK		 6163bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6164{
6165 unsigned long current_rip = kvm_rip_read(vcpu) +
6166 get_segment_base(vcpu, VCPU_SREG_CS);
6167
6168 return current_rip == linear_rip;
6169}
6170EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6171
94fe45da
JK		 6172unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6173{
6174 unsigned long rflags;
6175
6176 rflags = kvm_x86_ops->get_rflags(vcpu);
6177 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6178 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6179 return rflags;
6180}
6181EXPORT_SYMBOL_GPL(kvm_get_rflags);
6182
6183void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6184{
6185 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6186 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6187 rflags |= X86_EFLAGS_TF;
94fe45da 6188 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6189 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6190}
6191EXPORT_SYMBOL_GPL(kvm_set_rflags);
6192
56028d08
GN		 6193void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6194{
6195 int r;
6196
fb67e14f 6197 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6198 is_error_page(work->page))
56028d08
GN		 6199 return;
6200
6201 r = kvm_mmu_reload(vcpu);
6202 if (unlikely(r))
6203 return;
6204
fb67e14f
XG		 6205 if (!vcpu->arch.mmu.direct_map &&
6206 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6207 return;
6208
56028d08
GN		 6209 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6210}
6211
af585b92
GN		 6212static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6213{
6214 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6215}
6216
6217static inline u32 kvm_async_pf_next_probe(u32 key)
6218{
6219 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6220}
6221
6222static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6223{
6224 u32 key = kvm_async_pf_hash_fn(gfn);
6225
6226 while (vcpu->arch.apf.gfns[key] != ~0)
6227 key = kvm_async_pf_next_probe(key);
6228
6229 vcpu->arch.apf.gfns[key] = gfn;
6230}
6231
6232static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6233{
6234 int i;
6235 u32 key = kvm_async_pf_hash_fn(gfn);
6236
6237 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6238 (vcpu->arch.apf.gfns[key] != gfn &&
6239 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6240 key = kvm_async_pf_next_probe(key);
6241
6242 return key;
6243}
6244
6245bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6246{
6247 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6248}
6249
6250static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6251{
6252 u32 i, j, k;
6253
6254 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6255 while (true) {
6256 vcpu->arch.apf.gfns[i] = ~0;
6257 do {
6258 j = kvm_async_pf_next_probe(j);
6259 if (vcpu->arch.apf.gfns[j] == ~0)
6260 return;
6261 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6262 /*
6263 * k lies cyclically in ]i,j]
6264 * | i.k.j |
6265 * |....j i.k.| or |.k..j i...|
6266 */
6267 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6268 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6269 i = j;
6270 }
6271}
6272
7c90705b
GN		 6273static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6274{
6275
6276 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6277 sizeof(val));
6278}
6279
af585b92
GN		 6280void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6281 struct kvm_async_pf *work)
6282{
6389ee94
AK		 6283 struct x86_exception fault;
6284
7c90705b 6285 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6286 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6287
6288 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6289 (vcpu->arch.apf.send_user_only &&
6290 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6291 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6292 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6293 fault.vector = PF_VECTOR;
6294 fault.error_code_valid = true;
6295 fault.error_code = 0;
6296 fault.nested_page_fault = false;
6297 fault.address = work->arch.token;
6298 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6299 }
af585b92
GN		 6300}
6301
6302void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6303 struct kvm_async_pf *work)
6304{
6389ee94
AK		 6305 struct x86_exception fault;
6306
7c90705b
GN		 6307 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6308 if (is_error_page(work->page))
6309 work->arch.token = ~0; /* broadcast wakeup */
6310 else
6311 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6312
6313 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6314 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6315 fault.vector = PF_VECTOR;
6316 fault.error_code_valid = true;
6317 fault.error_code = 0;
6318 fault.nested_page_fault = false;
6319 fault.address = work->arch.token;
6320 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6321 }
e6d53e3b 6322 vcpu->arch.apf.halted = false;
7c90705b
GN		 6323}
6324
6325bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6326{
6327 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6328 return true;
6329 else
6330 return !kvm_event_needs_reinjection(vcpu) &&
6331 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6332}
6333
229456fc
MT		 6334EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6335EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6336EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6337EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6338EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6339EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6340EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6341EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6342EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6343EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6344EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6345EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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