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KVM: document memory barriers for kvm->vcpus/kvm->online_vcpus
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
aec51dc4 54#include <trace/events/kvm.h>
2ed152af 55
229456fc
MT		 56#define CREATE_TRACE_POINTS
57#include "trace.h"
043405e1 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 225 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 226 if (slot >= shared_msrs_global.nr)
227 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 228}
229EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
230
231static void kvm_shared_msr_cpu_online(void)
232{
233 unsigned i;
18863bdd
AK		 234
235 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 236 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 237}
238
8b3c3104 239int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 240{
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 243 int err;
18863bdd 244
2bf78fa7 245 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 246 return 0;
2bf78fa7 247 smsr->values[slot].curr = value;
8b3c3104
AH		 248 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
249 if (err)
250 return 1;
251
18863bdd
AK		 252 if (!smsr->registered) {
253 smsr->urn.on_user_return = kvm_on_user_return;
254 user_return_notifier_register(&smsr->urn);
255 smsr->registered = true;
256 }
8b3c3104 257 return 0;
18863bdd
AK		 258}
259EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
260
13a34e06 261static void drop_user_return_notifiers(void)
3548bab5 262{
013f6a5d
MT		 263 unsigned int cpu = smp_processor_id();
264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 265
266 if (smsr->registered)
267 kvm_on_user_return(&smsr->urn);
268}
269
6866b83e
CO		 270u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
271{
8a5a87d9 272 return vcpu->arch.apic_base;
6866b83e
CO		 273}
274EXPORT_SYMBOL_GPL(kvm_get_apic_base);
275
58cb628d
JK		 276int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
277{
278 u64 old_state = vcpu->arch.apic_base &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 new_state = msr_info->data &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
283 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
284
285 if (!msr_info->host_initiated &&
286 ((msr_info->data & reserved_bits) != 0 ||
287 new_state == X2APIC_ENABLE ||
288 (new_state == MSR_IA32_APICBASE_ENABLE &&
289 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
290 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
291 old_state == 0)))
292 return 1;
293
294 kvm_lapic_set_base(vcpu, msr_info->data);
295 return 0;
6866b83e
CO		 296}
297EXPORT_SYMBOL_GPL(kvm_set_apic_base);
298
2605fc21 299asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 300{
301 /* Fault while not rebooting. We want the trace. */
302 BUG();
303}
304EXPORT_SYMBOL_GPL(kvm_spurious_fault);
305
3fd28fce
ED		 306#define EXCPT_BENIGN 0
307#define EXCPT_CONTRIBUTORY 1
308#define EXCPT_PF 2
309
310static int exception_class(int vector)
311{
312 switch (vector) {
313 case PF_VECTOR:
314 return EXCPT_PF;
315 case DE_VECTOR:
316 case TS_VECTOR:
317 case NP_VECTOR:
318 case SS_VECTOR:
319 case GP_VECTOR:
320 return EXCPT_CONTRIBUTORY;
321 default:
322 break;
323 }
324 return EXCPT_BENIGN;
325}
326
d6e8c854
NA		 327#define EXCPT_FAULT 0
328#define EXCPT_TRAP 1
329#define EXCPT_ABORT 2
330#define EXCPT_INTERRUPT 3
331
332static int exception_type(int vector)
333{
334 unsigned int mask;
335
336 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
337 return EXCPT_INTERRUPT;
338
339 mask = 1 << vector;
340
341 /* #DB is trap, as instruction watchpoints are handled elsewhere */
342 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
343 return EXCPT_TRAP;
344
345 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
346 return EXCPT_ABORT;
347
348 /* Reserved exceptions will result in fault */
349 return EXCPT_FAULT;
350}
351
3fd28fce 352static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 353 unsigned nr, bool has_error, u32 error_code,
354 bool reinject)
3fd28fce
ED		 355{
356 u32 prev_nr;
357 int class1, class2;
358
3842d135
AK		 359 kvm_make_request(KVM_REQ_EVENT, vcpu);
360
3fd28fce
ED		 361 if (!vcpu->arch.exception.pending) {
362 queue:
3ffb2468
NA		 363 if (has_error && !is_protmode(vcpu))
364 has_error = false;
3fd28fce
ED		 365 vcpu->arch.exception.pending = true;
366 vcpu->arch.exception.has_error_code = has_error;
367 vcpu->arch.exception.nr = nr;
368 vcpu->arch.exception.error_code = error_code;
3f0fd292 369 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 370 return;
371 }
372
373 /* to check exception */
374 prev_nr = vcpu->arch.exception.nr;
375 if (prev_nr == DF_VECTOR) {
376 /* triple fault -> shutdown */
a8eeb04a 377 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 378 return;
379 }
380 class1 = exception_class(prev_nr);
381 class2 = exception_class(nr);
382 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
383 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
384 /* generate double fault per SDM Table 5-5 */
385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = true;
387 vcpu->arch.exception.nr = DF_VECTOR;
388 vcpu->arch.exception.error_code = 0;
389 } else
390 /* replace previous exception with a new one in a hope
391 that instruction re-execution will regenerate lost
392 exception */
393 goto queue;
394}
395
298101da
AK		 396void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
397{
ce7ddec4 398 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 399}
400EXPORT_SYMBOL_GPL(kvm_queue_exception);
401
ce7ddec4
JR		 402void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
403{
404 kvm_multiple_exception(vcpu, nr, false, 0, true);
405}
406EXPORT_SYMBOL_GPL(kvm_requeue_exception);
407
db8fcefa 408void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 409{
db8fcefa
AP		 410 if (err)
411 kvm_inject_gp(vcpu, 0);
412 else
413 kvm_x86_ops->skip_emulated_instruction(vcpu);
414}
415EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 416
6389ee94 417void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 418{
419 ++vcpu->stat.pf_guest;
6389ee94
AK		 420 vcpu->arch.cr2 = fault->address;
421 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 422}
27d6c865 423EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 424
ef54bcfe 425static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 426{
6389ee94
AK		 427 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
428 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 429 else
6389ee94 430 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 431
432 return fault->nested_page_fault;
d4f8cf66
JR		 433}
434
3419ffc8
SY		 435void kvm_inject_nmi(struct kvm_vcpu *vcpu)
436{
7460fb4a
AK		 437 atomic_inc(&vcpu->arch.nmi_queued);
438 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 439}
440EXPORT_SYMBOL_GPL(kvm_inject_nmi);
441
298101da
AK		 442void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
443{
ce7ddec4 444 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 445}
446EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
447
ce7ddec4
JR		 448void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
449{
450 kvm_multiple_exception(vcpu, nr, true, error_code, true);
451}
452EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
453
0a79b009
AK		 454/*
455 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
456 * a #GP and return false.
457 */
458bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 459{
0a79b009
AK		 460 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
461 return true;
462 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
463 return false;
298101da 464}
0a79b009 465EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 466
16f8a6f9
NA		 467bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
468{
469 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
470 return true;
471
472 kvm_queue_exception(vcpu, UD_VECTOR);
473 return false;
474}
475EXPORT_SYMBOL_GPL(kvm_require_dr);
476
ec92fe44
JR		 477/*
478 * This function will be used to read from the physical memory of the currently
54bf36aa 479 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 480 * can read from guest physical or from the guest's guest physical memory.
481 */
482int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
483 gfn_t ngfn, void *data, int offset, int len,
484 u32 access)
485{
54987b7a 486 struct x86_exception exception;
ec92fe44
JR		 487 gfn_t real_gfn;
488 gpa_t ngpa;
489
490 ngpa = gfn_to_gpa(ngfn);
54987b7a 491 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 492 if (real_gfn == UNMAPPED_GVA)
493 return -EFAULT;
494
495 real_gfn = gpa_to_gfn(real_gfn);
496
54bf36aa 497 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 498}
499EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
500
69b0049a 501static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 502 void *data, int offset, int len, u32 access)
503{
504 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
505 data, offset, len, access);
506}
507
a03490ed
CO		 508/*
509 * Load the pae pdptrs. Return true is they are all valid.
510 */
ff03a073 511int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 512{
513 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
514 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
515 int i;
516 int ret;
ff03a073 517 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 518
ff03a073
JR		 519 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
520 offset * sizeof(u64), sizeof(pdpte),
521 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 522 if (ret < 0) {
523 ret = 0;
524 goto out;
525 }
526 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 527 if (is_present_gpte(pdpte[i]) &&
20c466b5 528 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 529 ret = 0;
530 goto out;
531 }
532 }
533 ret = 1;
534
ff03a073 535 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_avail);
538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 540out:
a03490ed
CO		 541
542 return ret;
543}
cc4b6871 544EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 545
d835dfec
AK		 546static bool pdptrs_changed(struct kvm_vcpu *vcpu)
547{
ff03a073 548 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 549 bool changed = true;
3d06b8bf
JR		 550 int offset;
551 gfn_t gfn;
d835dfec
AK		 552 int r;
553
554 if (is_long_mode(vcpu) || !is_pae(vcpu))
555 return false;
556
6de4f3ad
AK		 557 if (!test_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail))
559 return true;
560
9f8fe504
AK		 561 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
562 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 563 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
564 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 565 if (r < 0)
566 goto out;
ff03a073 567 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 568out:
d835dfec
AK		 569
570 return changed;
571}
572
49a9b07e 573int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 574{
aad82703 575 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 576 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 577
f9a48e6a
AK		 578 cr0 |= X86_CR0_ET;
579
ab344828 580#ifdef CONFIG_X86_64
0f12244f
GN		 581 if (cr0 & 0xffffffff00000000UL)
582 return 1;
ab344828
GN		 583#endif
584
585 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 586
0f12244f
GN		 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588 return 1;
a03490ed 589
0f12244f
GN		 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591 return 1;
a03490ed
CO		 592
593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594#ifdef CONFIG_X86_64
f6801dff 595 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 596 int cs_db, cs_l;
597
0f12244f
GN		 598 if (!is_pae(vcpu))
599 return 1;
a03490ed 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 601 if (cs_l)
602 return 1;
a03490ed
CO		 603 } else
604#endif
ff03a073 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 606 kvm_read_cr3(vcpu)))
0f12244f 607 return 1;
a03490ed
CO		 608 }
609
ad756a16
MJ		 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611 return 1;
612
a03490ed 613 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 614
d170c419 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 616 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 617 kvm_async_pf_hash_reset(vcpu);
618 }
e5f3f027 619
aad82703
SY		 620 if ((cr0 ^ old_cr0) & update_bits)
621 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 622
623 if ((cr0 ^ old_cr0) & X86_CR0_CD)
624 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
625
0f12244f
GN		 626 return 0;
627}
2d3ad1f4 628EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 629
2d3ad1f4 630void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 631{
49a9b07e 632 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 633}
2d3ad1f4 634EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 635
42bdf991
MT		 636static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
637{
638 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
639 !vcpu->guest_xcr0_loaded) {
640 /* kvm_set_xcr() also depends on this */
641 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
642 vcpu->guest_xcr0_loaded = 1;
643 }
644}
645
646static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
647{
648 if (vcpu->guest_xcr0_loaded) {
649 if (vcpu->arch.xcr0 != host_xcr0)
650 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
651 vcpu->guest_xcr0_loaded = 0;
652 }
653}
654
69b0049a 655static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 656{
56c103ec
LJ		 657 u64 xcr0 = xcr;
658 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 659 u64 valid_bits;
2acf923e
DC		 660
661 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
662 if (index != XCR_XFEATURE_ENABLED_MASK)
663 return 1;
2acf923e
DC		 664 if (!(xcr0 & XSTATE_FP))
665 return 1;
666 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
667 return 1;
46c34cb0
PB		 668
669 /*
670 * Do not allow the guest to set bits that we do not support
671 * saving. However, xcr0 bit 0 is always set, even if the
672 * emulated CPU does not support XSAVE (see fx_init).
673 */
674 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
675 if (xcr0 & ~valid_bits)
2acf923e 676 return 1;
46c34cb0 677
390bd528
LJ		 678 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
679 return 1;
680
612263b3
CP		 681 if (xcr0 & XSTATE_AVX512) {
682 if (!(xcr0 & XSTATE_YMM))
683 return 1;
684 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
685 return 1;
686 }
42bdf991 687 kvm_put_guest_xcr0(vcpu);
2acf923e 688 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 689
690 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
691 kvm_update_cpuid(vcpu);
2acf923e
DC		 692 return 0;
693}
694
695int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
696{
764bcbc5
Z		 697 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
698 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 699 kvm_inject_gp(vcpu, 0);
700 return 1;
701 }
702 return 0;
703}
704EXPORT_SYMBOL_GPL(kvm_set_xcr);
705
a83b29c6 706int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 707{
fc78f519 708 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 709 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
710 X86_CR4_SMEP | X86_CR4_SMAP;
711
0f12244f
GN		 712 if (cr4 & CR4_RESERVED_BITS)
713 return 1;
a03490ed 714
2acf923e
DC		 715 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
716 return 1;
717
c68b734f
YW		 718 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
719 return 1;
720
97ec8c06
FW		 721 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
722 return 1;
723
afcbf13f 724 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 725 return 1;
726
a03490ed 727 if (is_long_mode(vcpu)) {
0f12244f
GN		 728 if (!(cr4 & X86_CR4_PAE))
729 return 1;
a2edf57f
AK		 730 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
731 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 732 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
733 kvm_read_cr3(vcpu)))
0f12244f
GN		 734 return 1;
735
ad756a16
MJ		 736 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
737 if (!guest_cpuid_has_pcid(vcpu))
738 return 1;
739
740 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
741 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
742 return 1;
743 }
744
5e1746d6 745 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 746 return 1;
a03490ed 747
ad756a16
MJ		 748 if (((cr4 ^ old_cr4) & pdptr_bits) ||
749 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 750 kvm_mmu_reset_context(vcpu);
0f12244f 751
2acf923e 752 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 753 kvm_update_cpuid(vcpu);
2acf923e 754
0f12244f
GN		 755 return 0;
756}
2d3ad1f4 757EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 758
2390218b 759int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 760{
ac146235 761#ifdef CONFIG_X86_64
9d88fca7 762 cr3 &= ~CR3_PCID_INVD;
ac146235 763#endif
9d88fca7 764
9f8fe504 765 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 766 kvm_mmu_sync_roots(vcpu);
77c3913b 767 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 768 return 0;
d835dfec
AK		 769 }
770
a03490ed 771 if (is_long_mode(vcpu)) {
d9f89b88
JK		 772 if (cr3 & CR3_L_MODE_RESERVED_BITS)
773 return 1;
774 } else if (is_pae(vcpu) && is_paging(vcpu) &&
775 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 776 return 1;
a03490ed 777
0f12244f 778 vcpu->arch.cr3 = cr3;
aff48baa 779 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 780 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 784
eea1cff9 785int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 786{
0f12244f
GN		 787 if (cr8 & CR8_RESERVED_BITS)
788 return 1;
a03490ed
CO		 789 if (irqchip_in_kernel(vcpu->kvm))
790 kvm_lapic_set_tpr(vcpu, cr8);
791 else
ad312c7c 792 vcpu->arch.cr8 = cr8;
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 796
2d3ad1f4 797unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 798{
799 if (irqchip_in_kernel(vcpu->kvm))
800 return kvm_lapic_get_cr8(vcpu);
801 else
ad312c7c 802 return vcpu->arch.cr8;
a03490ed 803}
2d3ad1f4 804EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 805
ae561ede
NA		 806static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
807{
808 int i;
809
810 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
811 for (i = 0; i < KVM_NR_DB_REGS; i++)
812 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
813 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
814 }
815}
816
73aaf249
JK		 817static void kvm_update_dr6(struct kvm_vcpu *vcpu)
818{
819 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
820 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
821}
822
c8639010
JK		 823static void kvm_update_dr7(struct kvm_vcpu *vcpu)
824{
825 unsigned long dr7;
826
827 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
828 dr7 = vcpu->arch.guest_debug_dr7;
829 else
830 dr7 = vcpu->arch.dr7;
831 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 832 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
833 if (dr7 & DR7_BP_EN_MASK)
834 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 835}
836
6f43ed01
NA		 837static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
838{
839 u64 fixed = DR6_FIXED_1;
840
841 if (!guest_cpuid_has_rtm(vcpu))
842 fixed |= DR6_RTM;
843 return fixed;
844}
845
338dbc97 846static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 847{
848 switch (dr) {
849 case 0 ... 3:
850 vcpu->arch.db[dr] = val;
851 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
852 vcpu->arch.eff_db[dr] = val;
853 break;
854 case 4:
020df079
GN		 855 /* fall through */
856 case 6:
338dbc97
GN		 857 if (val & 0xffffffff00000000ULL)
858 return -1; /* #GP */
6f43ed01 859 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 860 kvm_update_dr6(vcpu);
020df079
GN		 861 break;
862 case 5:
020df079
GN		 863 /* fall through */
864 default: /* 7 */
338dbc97
GN		 865 if (val & 0xffffffff00000000ULL)
866 return -1; /* #GP */
020df079 867 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 868 kvm_update_dr7(vcpu);
020df079
GN		 869 break;
870 }
871
872 return 0;
873}
338dbc97
GN		 874
875int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
876{
16f8a6f9 877 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 878 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 879 return 1;
880 }
881 return 0;
338dbc97 882}
020df079
GN		 883EXPORT_SYMBOL_GPL(kvm_set_dr);
884
16f8a6f9 885int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 886{
887 switch (dr) {
888 case 0 ... 3:
889 *val = vcpu->arch.db[dr];
890 break;
891 case 4:
020df079
GN		 892 /* fall through */
893 case 6:
73aaf249
JK		 894 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
895 *val = vcpu->arch.dr6;
896 else
897 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 898 break;
899 case 5:
020df079
GN		 900 /* fall through */
901 default: /* 7 */
902 *val = vcpu->arch.dr7;
903 break;
904 }
338dbc97
GN		 905 return 0;
906}
020df079
GN		 907EXPORT_SYMBOL_GPL(kvm_get_dr);
908
022cd0e8
AK		 909bool kvm_rdpmc(struct kvm_vcpu *vcpu)
910{
911 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
912 u64 data;
913 int err;
914
c6702c9d 915 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 916 if (err)
917 return err;
918 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
919 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
920 return err;
921}
922EXPORT_SYMBOL_GPL(kvm_rdpmc);
923
043405e1
CO		 924/*
925 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
926 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
927 *
928 * This list is modified at module load time to reflect the
e3267cbb 929 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 930 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
931 * may depend on host virtualization features rather than host cpu features.
043405e1 932 */
e3267cbb 933
043405e1
CO		 934static u32 msrs_to_save[] = {
935 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 936 MSR_STAR,
043405e1
CO		 937#ifdef CONFIG_X86_64
938 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
939#endif
b3897a49 940 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 941 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 942};
943
944static unsigned num_msrs_to_save;
945
62ef68bb
PB		 946static u32 emulated_msrs[] = {
947 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
948 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
949 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
950 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 951 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
952 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
62ef68bb
PB		 953 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
954 MSR_KVM_PV_EOI_EN,
955
ba904635 956 MSR_IA32_TSC_ADJUST,
a3e06bbe 957 MSR_IA32_TSCDEADLINE,
043405e1 958 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 959 MSR_IA32_MCG_STATUS,
960 MSR_IA32_MCG_CTL,
64d60670 961 MSR_IA32_SMBASE,
043405e1
CO		 962};
963
62ef68bb
PB		 964static unsigned num_emulated_msrs;
965
384bb783 966bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 967{
b69e8cae 968 if (efer & efer_reserved_bits)
384bb783 969 return false;
15c4a640 970
1b2fd70c
AG		 971 if (efer & EFER_FFXSR) {
972 struct kvm_cpuid_entry2 *feat;
973
974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 975 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 976 return false;
1b2fd70c
AG		 977 }
978
d8017474
AG		 979 if (efer & EFER_SVME) {
980 struct kvm_cpuid_entry2 *feat;
981
982 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 983 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 984 return false;
d8017474
AG		 985 }
986
384bb783
JK		 987 return true;
988}
989EXPORT_SYMBOL_GPL(kvm_valid_efer);
990
991static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
992{
993 u64 old_efer = vcpu->arch.efer;
994
995 if (!kvm_valid_efer(vcpu, efer))
996 return 1;
997
998 if (is_paging(vcpu)
999 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1000 return 1;
1001
15c4a640 1002 efer &= ~EFER_LMA;
f6801dff 1003 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1004
a3d204e2
SY		 1005 kvm_x86_ops->set_efer(vcpu, efer);
1006
aad82703
SY		 1007 /* Update reserved bits */
1008 if ((efer ^ old_efer) & EFER_NX)
1009 kvm_mmu_reset_context(vcpu);
1010
b69e8cae 1011 return 0;
15c4a640
CO		 1012}
1013
f2b4b7dd
JR		 1014void kvm_enable_efer_bits(u64 mask)
1015{
1016 efer_reserved_bits &= ~mask;
1017}
1018EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1019
15c4a640
CO		 1020/*
1021 * Writes msr value into into the appropriate "register".
1022 * Returns 0 on success, non-0 otherwise.
1023 * Assumes vcpu_load() was already called.
1024 */
8fe8ab46 1025int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1026{
854e8bb1
NA		 1027 switch (msr->index) {
1028 case MSR_FS_BASE:
1029 case MSR_GS_BASE:
1030 case MSR_KERNEL_GS_BASE:
1031 case MSR_CSTAR:
1032 case MSR_LSTAR:
1033 if (is_noncanonical_address(msr->data))
1034 return 1;
1035 break;
1036 case MSR_IA32_SYSENTER_EIP:
1037 case MSR_IA32_SYSENTER_ESP:
1038 /*
1039 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1040 * non-canonical address is written on Intel but not on
1041 * AMD (which ignores the top 32-bits, because it does
1042 * not implement 64-bit SYSENTER).
1043 *
1044 * 64-bit code should hence be able to write a non-canonical
1045 * value on AMD. Making the address canonical ensures that
1046 * vmentry does not fail on Intel after writing a non-canonical
1047 * value, and that something deterministic happens if the guest
1048 * invokes 64-bit SYSENTER.
1049 */
1050 msr->data = get_canonical(msr->data);
1051 }
8fe8ab46 1052 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1053}
854e8bb1 1054EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1055
313a3dc7
CO		 1056/*
1057 * Adapt set_msr() to msr_io()'s calling convention
1058 */
609e36d3
PB		 1059static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1060{
1061 struct msr_data msr;
1062 int r;
1063
1064 msr.index = index;
1065 msr.host_initiated = true;
1066 r = kvm_get_msr(vcpu, &msr);
1067 if (r)
1068 return r;
1069
1070 *data = msr.data;
1071 return 0;
1072}
1073
313a3dc7
CO		 1074static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1075{
8fe8ab46
WA		 1076 struct msr_data msr;
1077
1078 msr.data = *data;
1079 msr.index = index;
1080 msr.host_initiated = true;
1081 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1082}
1083
16e8d74d
MT		 1084#ifdef CONFIG_X86_64
1085struct pvclock_gtod_data {
1086 seqcount_t seq;
1087
1088 struct { /* extract of a clocksource struct */
1089 int vclock_mode;
1090 cycle_t cycle_last;
1091 cycle_t mask;
1092 u32 mult;
1093 u32 shift;
1094 } clock;
1095
cbcf2dd3
TG		 1096 u64 boot_ns;
1097 u64 nsec_base;
16e8d74d
MT		 1098};
1099
1100static struct pvclock_gtod_data pvclock_gtod_data;
1101
1102static void update_pvclock_gtod(struct timekeeper *tk)
1103{
1104 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1105 u64 boot_ns;
1106
876e7881 1107 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1108
1109 write_seqcount_begin(&vdata->seq);
1110
1111 /* copy pvclock gtod data */
876e7881
PZ		 1112 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1113 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1114 vdata->clock.mask = tk->tkr_mono.mask;
1115 vdata->clock.mult = tk->tkr_mono.mult;
1116 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1117
cbcf2dd3 1118 vdata->boot_ns = boot_ns;
876e7881 1119 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1120
1121 write_seqcount_end(&vdata->seq);
1122}
1123#endif
1124
bab5bb39
NK		 1125void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1126{
1127 /*
1128 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1129 * vcpu_enter_guest. This function is only called from
1130 * the physical CPU that is running vcpu.
1131 */
1132 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1133}
16e8d74d 1134
18068523
GOC		 1135static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1136{
9ed3c444
AK		 1137 int version;
1138 int r;
50d0a0f9 1139 struct pvclock_wall_clock wc;
923de3cf 1140 struct timespec boot;
18068523
GOC		 1141
1142 if (!wall_clock)
1143 return;
1144
9ed3c444
AK		 1145 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1146 if (r)
1147 return;
1148
1149 if (version & 1)
1150 ++version; /* first time write, random junk */
1151
1152 ++version;
18068523 1153
18068523
GOC		 1154 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1155
50d0a0f9
GH		 1156 /*
1157 * The guest calculates current wall clock time by adding
34c238a1 1158 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1159 * wall clock specified here. guest system time equals host
1160 * system time for us, thus we must fill in host boot time here.
1161 */
923de3cf 1162 getboottime(&boot);
50d0a0f9 1163
4b648665
BR		 1164 if (kvm->arch.kvmclock_offset) {
1165 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1166 boot = timespec_sub(boot, ts);
1167 }
50d0a0f9
GH		 1168 wc.sec = boot.tv_sec;
1169 wc.nsec = boot.tv_nsec;
1170 wc.version = version;
18068523
GOC		 1171
1172 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1173
1174 version++;
1175 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1176}
1177
50d0a0f9
GH		 1178static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1179{
1180 uint32_t quotient, remainder;
1181
1182 /* Don't try to replace with do_div(), this one calculates
1183 * "(dividend << 32) / divisor" */
1184 __asm__ ( "divl %4"
1185 : "=a" (quotient), "=d" (remainder)
1186 : "0" (0), "1" (dividend), "r" (divisor) );
1187 return quotient;
1188}
1189
5f4e3f88
ZA		 1190static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1191 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1192{
5f4e3f88 1193 uint64_t scaled64;
50d0a0f9
GH		 1194 int32_t shift = 0;
1195 uint64_t tps64;
1196 uint32_t tps32;
1197
5f4e3f88
ZA		 1198 tps64 = base_khz * 1000LL;
1199 scaled64 = scaled_khz * 1000LL;
50933623 1200 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1201 tps64 >>= 1;
1202 shift--;
1203 }
1204
1205 tps32 = (uint32_t)tps64;
50933623
JK		 1206 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1207 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1208 scaled64 >>= 1;
1209 else
1210 tps32 <<= 1;
50d0a0f9
GH		 1211 shift++;
1212 }
1213
5f4e3f88
ZA		 1214 *pshift = shift;
1215 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1216
5f4e3f88
ZA		 1217 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1218 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1219}
1220
d828199e 1221#ifdef CONFIG_X86_64
16e8d74d 1222static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1223#endif
16e8d74d 1224
c8076604 1225static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1226static unsigned long max_tsc_khz;
c8076604 1227
cc578287 1228static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1229{
cc578287
ZA		 1230 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1231 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1232}
1233
cc578287 1234static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1235{
cc578287
ZA		 1236 u64 v = (u64)khz * (1000000 + ppm);
1237 do_div(v, 1000000);
1238 return v;
1e993611
JR		 1239}
1240
cc578287 1241static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1242{
cc578287
ZA		 1243 u32 thresh_lo, thresh_hi;
1244 int use_scaling = 0;
217fc9cf 1245
03ba32ca
MT		 1246 /* tsc_khz can be zero if TSC calibration fails */
1247 if (this_tsc_khz == 0)
1248 return;
1249
c285545f
ZA		 1250 /* Compute a scale to convert nanoseconds in TSC cycles */
1251 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1252 &vcpu->arch.virtual_tsc_shift,
1253 &vcpu->arch.virtual_tsc_mult);
1254 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1255
1256 /*
1257 * Compute the variation in TSC rate which is acceptable
1258 * within the range of tolerance and decide if the
1259 * rate being applied is within that bounds of the hardware
1260 * rate. If so, no scaling or compensation need be done.
1261 */
1262 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1263 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1264 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1265 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1266 use_scaling = 1;
1267 }
1268 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1269}
1270
1271static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1272{
e26101b1 1273 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1274 vcpu->arch.virtual_tsc_mult,
1275 vcpu->arch.virtual_tsc_shift);
e26101b1 1276 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1277 return tsc;
1278}
1279
69b0049a 1280static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1281{
1282#ifdef CONFIG_X86_64
1283 bool vcpus_matched;
b48aa97e
MT		 1284 struct kvm_arch *ka = &vcpu->kvm->arch;
1285 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1286
1287 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1288 atomic_read(&vcpu->kvm->online_vcpus));
1289
7f187922
MT		 1290 /*
1291 * Once the masterclock is enabled, always perform request in
1292 * order to update it.
1293 *
1294 * In order to enable masterclock, the host clocksource must be TSC
1295 * and the vcpus need to have matched TSCs. When that happens,
1296 * perform request to enable masterclock.
1297 */
1298 if (ka->use_master_clock ||
1299 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1300 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1301
1302 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1303 atomic_read(&vcpu->kvm->online_vcpus),
1304 ka->use_master_clock, gtod->clock.vclock_mode);
1305#endif
1306}
1307
ba904635
WA		 1308static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1309{
1310 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1311 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1312}
1313
8fe8ab46 1314void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1315{
1316 struct kvm *kvm = vcpu->kvm;
f38e098f 1317 u64 offset, ns, elapsed;
99e3e30a 1318 unsigned long flags;
02626b6a 1319 s64 usdiff;
b48aa97e 1320 bool matched;
0d3da0d2 1321 bool already_matched;
8fe8ab46 1322 u64 data = msr->data;
99e3e30a 1323
038f8c11 1324 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1325 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1326 ns = get_kernel_ns();
f38e098f 1327 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1328
03ba32ca 1329 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1330 int faulted = 0;
1331
03ba32ca
MT		 1332 /* n.b - signed multiplication and division required */
1333 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1334#ifdef CONFIG_X86_64
03ba32ca 1335 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1336#else
03ba32ca 1337 /* do_div() only does unsigned */
8915aa27
MT		 1338 asm("1: idivl %[divisor]\n"
1339 "2: xor %%edx, %%edx\n"
1340 " movl $0, %[faulted]\n"
1341 "3:\n"
1342 ".section .fixup,\"ax\"\n"
1343 "4: movl $1, %[faulted]\n"
1344 " jmp 3b\n"
1345 ".previous\n"
1346
1347 _ASM_EXTABLE(1b, 4b)
1348
1349 : "=A"(usdiff), [faulted] "=r" (faulted)
1350 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1351
5d3cb0f6 1352#endif
03ba32ca
MT		 1353 do_div(elapsed, 1000);
1354 usdiff -= elapsed;
1355 if (usdiff < 0)
1356 usdiff = -usdiff;
8915aa27
MT		 1357
1358 /* idivl overflow => difference is larger than USEC_PER_SEC */
1359 if (faulted)
1360 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1361 } else
1362 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1363
1364 /*
5d3cb0f6
ZA		 1365 * Special case: TSC write with a small delta (1 second) of virtual
1366 * cycle time against real time is interpreted as an attempt to
1367 * synchronize the CPU.
1368 *
1369 * For a reliable TSC, we can match TSC offsets, and for an unstable
1370 * TSC, we add elapsed time in this computation. We could let the
1371 * compensation code attempt to catch up if we fall behind, but
1372 * it's better to try to match offsets from the beginning.
1373 */
02626b6a 1374 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1375 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1376 if (!check_tsc_unstable()) {
e26101b1 1377 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1378 pr_debug("kvm: matched tsc offset for %llu\n", data);
1379 } else {
857e4099 1380 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1381 data += delta;
1382 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1383 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1384 }
b48aa97e 1385 matched = true;
0d3da0d2 1386 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1387 } else {
1388 /*
1389 * We split periods of matched TSC writes into generations.
1390 * For each generation, we track the original measured
1391 * nanosecond time, offset, and write, so if TSCs are in
1392 * sync, we can match exact offset, and if not, we can match
4a969980 1393 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1394 *
1395 * These values are tracked in kvm->arch.cur_xxx variables.
1396 */
1397 kvm->arch.cur_tsc_generation++;
1398 kvm->arch.cur_tsc_nsec = ns;
1399 kvm->arch.cur_tsc_write = data;
1400 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1401 matched = false;
0d3da0d2 1402 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1403 kvm->arch.cur_tsc_generation, data);
f38e098f 1404 }
e26101b1
ZA		 1405
1406 /*
1407 * We also track th most recent recorded KHZ, write and time to
1408 * allow the matching interval to be extended at each write.
1409 */
f38e098f
ZA		 1410 kvm->arch.last_tsc_nsec = ns;
1411 kvm->arch.last_tsc_write = data;
5d3cb0f6 1412 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1413
b183aa58 1414 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1415
1416 /* Keep track of which generation this VCPU has synchronized to */
1417 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1418 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1419 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1420
ba904635
WA		 1421 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1422 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1423 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1424 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1425
1426 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1427 if (!matched) {
b48aa97e 1428 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1429 } else if (!already_matched) {
1430 kvm->arch.nr_vcpus_matched_tsc++;
1431 }
b48aa97e
MT		 1432
1433 kvm_track_tsc_matching(vcpu);
1434 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1435}
e26101b1 1436
99e3e30a
ZA		 1437EXPORT_SYMBOL_GPL(kvm_write_tsc);
1438
d828199e
MT		 1439#ifdef CONFIG_X86_64
1440
1441static cycle_t read_tsc(void)
1442{
1443 cycle_t ret;
1444 u64 last;
1445
1446 /*
1447 * Empirically, a fence (of type that depends on the CPU)
1448 * before rdtsc is enough to ensure that rdtsc is ordered
1449 * with respect to loads. The various CPU manuals are unclear
1450 * as to whether rdtsc can be reordered with later loads,
1451 * but no one has ever seen it happen.
1452 */
1453 rdtsc_barrier();
1454 ret = (cycle_t)vget_cycles();
1455
1456 last = pvclock_gtod_data.clock.cycle_last;
1457
1458 if (likely(ret >= last))
1459 return ret;
1460
1461 /*
1462 * GCC likes to generate cmov here, but this branch is extremely
1463 * predictable (it's just a funciton of time and the likely is
1464 * very likely) and there's a data dependence, so force GCC
1465 * to generate a branch instead. I don't barrier() because
1466 * we don't actually need a barrier, and if this function
1467 * ever gets inlined it will generate worse code.
1468 */
1469 asm volatile ("");
1470 return last;
1471}
1472
1473static inline u64 vgettsc(cycle_t *cycle_now)
1474{
1475 long v;
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477
1478 *cycle_now = read_tsc();
1479
1480 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1481 return v * gtod->clock.mult;
1482}
1483
cbcf2dd3 1484static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1485{
cbcf2dd3 1486 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1487 unsigned long seq;
d828199e 1488 int mode;
cbcf2dd3 1489 u64 ns;
d828199e 1490
d828199e
MT		 1491 do {
1492 seq = read_seqcount_begin(&gtod->seq);
1493 mode = gtod->clock.vclock_mode;
cbcf2dd3 1494 ns = gtod->nsec_base;
d828199e
MT		 1495 ns += vgettsc(cycle_now);
1496 ns >>= gtod->clock.shift;
cbcf2dd3 1497 ns += gtod->boot_ns;
d828199e 1498 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1499 *t = ns;
d828199e
MT		 1500
1501 return mode;
1502}
1503
1504/* returns true if host is using tsc clocksource */
1505static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1506{
d828199e
MT		 1507 /* checked again under seqlock below */
1508 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1509 return false;
1510
cbcf2dd3 1511 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1512}
1513#endif
1514
1515/*
1516 *
b48aa97e
MT		 1517 * Assuming a stable TSC across physical CPUS, and a stable TSC
1518 * across virtual CPUs, the following condition is possible.
1519 * Each numbered line represents an event visible to both
d828199e
MT		 1520 * CPUs at the next numbered event.
1521 *
1522 * "timespecX" represents host monotonic time. "tscX" represents
1523 * RDTSC value.
1524 *
1525 * VCPU0 on CPU0 | VCPU1 on CPU1
1526 *
1527 * 1. read timespec0,tsc0
1528 * 2. | timespec1 = timespec0 + N
1529 * | tsc1 = tsc0 + M
1530 * 3. transition to guest | transition to guest
1531 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1532 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1533 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1534 *
1535 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1536 *
1537 * - ret0 < ret1
1538 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1539 * ...
1540 * - 0 < N - M => M < N
1541 *
1542 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1543 * always the case (the difference between two distinct xtime instances
1544 * might be smaller then the difference between corresponding TSC reads,
1545 * when updating guest vcpus pvclock areas).
1546 *
1547 * To avoid that problem, do not allow visibility of distinct
1548 * system_timestamp/tsc_timestamp values simultaneously: use a master
1549 * copy of host monotonic time values. Update that master copy
1550 * in lockstep.
1551 *
b48aa97e 1552 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1553 *
1554 */
1555
1556static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1557{
1558#ifdef CONFIG_X86_64
1559 struct kvm_arch *ka = &kvm->arch;
1560 int vclock_mode;
b48aa97e
MT		 1561 bool host_tsc_clocksource, vcpus_matched;
1562
1563 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1564 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1565
1566 /*
1567 * If the host uses TSC clock, then passthrough TSC as stable
1568 * to the guest.
1569 */
b48aa97e 1570 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1571 &ka->master_kernel_ns,
1572 &ka->master_cycle_now);
1573
16a96021 1574 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1575 && !backwards_tsc_observed
1576 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1577
d828199e
MT		 1578 if (ka->use_master_clock)
1579 atomic_set(&kvm_guest_has_master_clock, 1);
1580
1581 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1582 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1583 vcpus_matched);
d828199e
MT		 1584#endif
1585}
1586
2e762ff7
MT		 1587static void kvm_gen_update_masterclock(struct kvm *kvm)
1588{
1589#ifdef CONFIG_X86_64
1590 int i;
1591 struct kvm_vcpu *vcpu;
1592 struct kvm_arch *ka = &kvm->arch;
1593
1594 spin_lock(&ka->pvclock_gtod_sync_lock);
1595 kvm_make_mclock_inprogress_request(kvm);
1596 /* no guest entries from this point */
1597 pvclock_update_vm_gtod_copy(kvm);
1598
1599 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1600 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1601
1602 /* guest entries allowed */
1603 kvm_for_each_vcpu(i, vcpu, kvm)
1604 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1605
1606 spin_unlock(&ka->pvclock_gtod_sync_lock);
1607#endif
1608}
1609
34c238a1 1610static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1611{
d828199e 1612 unsigned long flags, this_tsc_khz;
18068523 1613 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1614 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1615 s64 kernel_ns;
d828199e 1616 u64 tsc_timestamp, host_tsc;
0b79459b 1617 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1618 u8 pvclock_flags;
d828199e
MT		 1619 bool use_master_clock;
1620
1621 kernel_ns = 0;
1622 host_tsc = 0;
18068523 1623
d828199e
MT		 1624 /*
1625 * If the host uses TSC clock, then passthrough TSC as stable
1626 * to the guest.
1627 */
1628 spin_lock(&ka->pvclock_gtod_sync_lock);
1629 use_master_clock = ka->use_master_clock;
1630 if (use_master_clock) {
1631 host_tsc = ka->master_cycle_now;
1632 kernel_ns = ka->master_kernel_ns;
1633 }
1634 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1635
1636 /* Keep irq disabled to prevent changes to the clock */
1637 local_irq_save(flags);
89cbc767 1638 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1639 if (unlikely(this_tsc_khz == 0)) {
1640 local_irq_restore(flags);
1641 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1642 return 1;
1643 }
d828199e
MT		 1644 if (!use_master_clock) {
1645 host_tsc = native_read_tsc();
1646 kernel_ns = get_kernel_ns();
1647 }
1648
1649 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1650
c285545f
ZA		 1651 /*
1652 * We may have to catch up the TSC to match elapsed wall clock
1653 * time for two reasons, even if kvmclock is used.
1654 * 1) CPU could have been running below the maximum TSC rate
1655 * 2) Broken TSC compensation resets the base at each VCPU
1656 * entry to avoid unknown leaps of TSC even when running
1657 * again on the same CPU. This may cause apparent elapsed
1658 * time to disappear, and the guest to stand still or run
1659 * very slowly.
1660 */
1661 if (vcpu->tsc_catchup) {
1662 u64 tsc = compute_guest_tsc(v, kernel_ns);
1663 if (tsc > tsc_timestamp) {
f1e2b260 1664 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1665 tsc_timestamp = tsc;
1666 }
50d0a0f9
GH		 1667 }
1668
18068523
GOC		 1669 local_irq_restore(flags);
1670
0b79459b 1671 if (!vcpu->pv_time_enabled)
c285545f 1672 return 0;
18068523 1673
e48672fa 1674 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1675 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1676 &vcpu->hv_clock.tsc_shift,
1677 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1678 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1679 }
1680
1681 /* With all the info we got, fill in the values */
1d5f066e 1682 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1683 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1684 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1685
09a0c3f1
OH		 1686 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1687 &guest_hv_clock, sizeof(guest_hv_clock))))
1688 return 0;
1689
5dca0d91
RK		 1690 /* This VCPU is paused, but it's legal for a guest to read another
1691 * VCPU's kvmclock, so we really have to follow the specification where
1692 * it says that version is odd if data is being modified, and even after
1693 * it is consistent.
1694 *
1695 * Version field updates must be kept separate. This is because
1696 * kvm_write_guest_cached might use a "rep movs" instruction, and
1697 * writes within a string instruction are weakly ordered. So there
1698 * are three writes overall.
1699 *
1700 * As a small optimization, only write the version field in the first
1701 * and third write. The vcpu->pv_time cache is still valid, because the
1702 * version field is the first in the struct.
18068523 1703 */
5dca0d91
RK		 1704 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1705
1706 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1707 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1708 &vcpu->hv_clock,
1709 sizeof(vcpu->hv_clock.version));
1710
1711 smp_wmb();
78c0337a
MT		 1712
1713 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1714 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1715
1716 if (vcpu->pvclock_set_guest_stopped_request) {
1717 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1718 vcpu->pvclock_set_guest_stopped_request = false;
1719 }
1720
b7e60c5a
MT		 1721 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1722
d828199e
MT		 1723 /* If the host uses TSC clocksource, then it is stable */
1724 if (use_master_clock)
1725 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1726
78c0337a
MT		 1727 vcpu->hv_clock.flags = pvclock_flags;
1728
ce1a5e60
DM		 1729 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1730
0b79459b
AH		 1731 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1732 &vcpu->hv_clock,
1733 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1734
1735 smp_wmb();
1736
1737 vcpu->hv_clock.version++;
1738 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1739 &vcpu->hv_clock,
1740 sizeof(vcpu->hv_clock.version));
8cfdc000 1741 return 0;
c8076604
GH		 1742}
1743
0061d53d
MT		 1744/*
1745 * kvmclock updates which are isolated to a given vcpu, such as
1746 * vcpu->cpu migration, should not allow system_timestamp from
1747 * the rest of the vcpus to remain static. Otherwise ntp frequency
1748 * correction applies to one vcpu's system_timestamp but not
1749 * the others.
1750 *
1751 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1752 * We need to rate-limit these requests though, as they can
1753 * considerably slow guests that have a large number of vcpus.
1754 * The time for a remote vcpu to update its kvmclock is bound
1755 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1756 */
1757
7e44e449
AJ		 1758#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1759
1760static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1761{
1762 int i;
7e44e449
AJ		 1763 struct delayed_work *dwork = to_delayed_work(work);
1764 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1765 kvmclock_update_work);
1766 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1767 struct kvm_vcpu *vcpu;
1768
1769 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1771 kvm_vcpu_kick(vcpu);
1772 }
1773}
1774
7e44e449
AJ		 1775static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1776{
1777 struct kvm *kvm = v->kvm;
1778
105b21bb 1779 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1780 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1781 KVMCLOCK_UPDATE_DELAY);
1782}
1783
332967a3
AJ		 1784#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1785
1786static void kvmclock_sync_fn(struct work_struct *work)
1787{
1788 struct delayed_work *dwork = to_delayed_work(work);
1789 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1790 kvmclock_sync_work);
1791 struct kvm *kvm = container_of(ka, struct kvm, arch);
1792
630994b3
MT		 1793 if (!kvmclock_periodic_sync)
1794 return;
1795
332967a3
AJ		 1796 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1797 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1798 KVMCLOCK_SYNC_PERIOD);
1799}
1800
890ca9ae 1801static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1802{
890ca9ae
HY		 1803 u64 mcg_cap = vcpu->arch.mcg_cap;
1804 unsigned bank_num = mcg_cap & 0xff;
1805
15c4a640 1806 switch (msr) {
15c4a640 1807 case MSR_IA32_MCG_STATUS:
890ca9ae 1808 vcpu->arch.mcg_status = data;
15c4a640 1809 break;
c7ac679c 1810 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1811 if (!(mcg_cap & MCG_CTL_P))
1812 return 1;
1813 if (data != 0 && data != ~(u64)0)
1814 return -1;
1815 vcpu->arch.mcg_ctl = data;
1816 break;
1817 default:
1818 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1819 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1820 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1821 /* only 0 or all 1s can be written to IA32_MCi_CTL
1822 * some Linux kernels though clear bit 10 in bank 4 to
1823 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1824 * this to avoid an uncatched #GP in the guest
1825 */
890ca9ae 1826 if ((offset & 0x3) == 0 &&
114be429 1827 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1828 return -1;
1829 vcpu->arch.mce_banks[offset] = data;
1830 break;
1831 }
1832 return 1;
1833 }
1834 return 0;
1835}
1836
ffde22ac
ES		 1837static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1838{
1839 struct kvm *kvm = vcpu->kvm;
1840 int lm = is_long_mode(vcpu);
1841 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1842 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1843 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1844 : kvm->arch.xen_hvm_config.blob_size_32;
1845 u32 page_num = data & ~PAGE_MASK;
1846 u64 page_addr = data & PAGE_MASK;
1847 u8 *page;
1848 int r;
1849
1850 r = -E2BIG;
1851 if (page_num >= blob_size)
1852 goto out;
1853 r = -ENOMEM;
ff5c2c03
SL		 1854 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1855 if (IS_ERR(page)) {
1856 r = PTR_ERR(page);
ffde22ac 1857 goto out;
ff5c2c03 1858 }
54bf36aa 1859 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1860 goto out_free;
1861 r = 0;
1862out_free:
1863 kfree(page);
1864out:
1865 return r;
1866}
1867
344d9588
GN		 1868static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1869{
1870 gpa_t gpa = data & ~0x3f;
1871
4a969980 1872 /* Bits 2:5 are reserved, Should be zero */
6adba527 1873 if (data & 0x3c)
344d9588
GN		 1874 return 1;
1875
1876 vcpu->arch.apf.msr_val = data;
1877
1878 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1879 kvm_clear_async_pf_completion_queue(vcpu);
1880 kvm_async_pf_hash_reset(vcpu);
1881 return 0;
1882 }
1883
8f964525
AH		 1884 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1885 sizeof(u32)))
344d9588
GN		 1886 return 1;
1887
6adba527 1888 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1889 kvm_async_pf_wakeup_all(vcpu);
1890 return 0;
1891}
1892
12f9a48f
GC		 1893static void kvmclock_reset(struct kvm_vcpu *vcpu)
1894{
0b79459b 1895 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1896}
1897
c9aaa895
GC		 1898static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1899{
1900 u64 delta;
1901
1902 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1903 return;
1904
1905 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1906 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1907 vcpu->arch.st.accum_steal = delta;
1908}
1909
1910static void record_steal_time(struct kvm_vcpu *vcpu)
1911{
1912 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1913 return;
1914
1915 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1916 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1917 return;
1918
1919 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1920 vcpu->arch.st.steal.version += 2;
1921 vcpu->arch.st.accum_steal = 0;
1922
1923 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1924 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1925}
1926
8fe8ab46 1927int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1928{
5753785f 1929 bool pr = false;
8fe8ab46
WA		 1930 u32 msr = msr_info->index;
1931 u64 data = msr_info->data;
5753785f 1932
15c4a640 1933 switch (msr) {
2e32b719
BP		 1934 case MSR_AMD64_NB_CFG:
1935 case MSR_IA32_UCODE_REV:
1936 case MSR_IA32_UCODE_WRITE:
1937 case MSR_VM_HSAVE_PA:
1938 case MSR_AMD64_PATCH_LOADER:
1939 case MSR_AMD64_BU_CFG2:
1940 break;
1941
15c4a640 1942 case MSR_EFER:
b69e8cae 1943 return set_efer(vcpu, data);
8f1589d9
AP		 1944 case MSR_K7_HWCR:
1945 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1946 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1947 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1948 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1949 if (data != 0) {
a737f256
CD		 1950 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1951 data);
8f1589d9
AP		 1952 return 1;
1953 }
15c4a640 1954 break;
f7c6d140
AP		 1955 case MSR_FAM10H_MMIO_CONF_BASE:
1956 if (data != 0) {
a737f256
CD		 1957 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1958 "0x%llx\n", data);
f7c6d140
AP		 1959 return 1;
1960 }
15c4a640 1961 break;
b5e2fec0
AG		 1962 case MSR_IA32_DEBUGCTLMSR:
1963 if (!data) {
1964 /* We support the non-activated case already */
1965 break;
1966 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1967 /* Values other than LBR and BTF are vendor-specific,
1968 thus reserved and should throw a #GP */
1969 return 1;
1970 }
a737f256
CD		 1971 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1972 __func__, data);
b5e2fec0 1973 break;
9ba075a6 1974 case 0x200 ... 0x2ff:
ff53604b 1975 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1976 case MSR_IA32_APICBASE:
58cb628d 1977 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1978 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1979 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1980 case MSR_IA32_TSCDEADLINE:
1981 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1982 break;
ba904635
WA		 1983 case MSR_IA32_TSC_ADJUST:
1984 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1985 if (!msr_info->host_initiated) {
d913b904 1986 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 1987 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1988 }
1989 vcpu->arch.ia32_tsc_adjust_msr = data;
1990 }
1991 break;
15c4a640 1992 case MSR_IA32_MISC_ENABLE:
ad312c7c 1993 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1994 break;
64d60670
PB		 1995 case MSR_IA32_SMBASE:
1996 if (!msr_info->host_initiated)
1997 return 1;
1998 vcpu->arch.smbase = data;
1999 break;
11c6bffa 2000 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2001 case MSR_KVM_WALL_CLOCK:
2002 vcpu->kvm->arch.wall_clock = data;
2003 kvm_write_wall_clock(vcpu->kvm, data);
2004 break;
11c6bffa 2005 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2006 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2007 u64 gpa_offset;
54750f2c
MT		 2008 struct kvm_arch *ka = &vcpu->kvm->arch;
2009
12f9a48f 2010 kvmclock_reset(vcpu);
18068523 2011
54750f2c
MT		 2012 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2013 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2014
2015 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2016 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2017 &vcpu->requests);
2018
2019 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2020
2021 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2022 }
2023
18068523 2024 vcpu->arch.time = data;
0061d53d 2025 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2026
2027 /* we verify if the enable bit is set... */
2028 if (!(data & 1))
2029 break;
2030
0b79459b 2031 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2032
0b79459b 2033 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2034 &vcpu->arch.pv_time, data & ~1ULL,
2035 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2036 vcpu->arch.pv_time_enabled = false;
2037 else
2038 vcpu->arch.pv_time_enabled = true;
32cad84f 2039
18068523
GOC		 2040 break;
2041 }
344d9588
GN		 2042 case MSR_KVM_ASYNC_PF_EN:
2043 if (kvm_pv_enable_async_pf(vcpu, data))
2044 return 1;
2045 break;
c9aaa895
GC		 2046 case MSR_KVM_STEAL_TIME:
2047
2048 if (unlikely(!sched_info_on()))
2049 return 1;
2050
2051 if (data & KVM_STEAL_RESERVED_MASK)
2052 return 1;
2053
2054 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2055 data & KVM_STEAL_VALID_BITS,
2056 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2057 return 1;
2058
2059 vcpu->arch.st.msr_val = data;
2060
2061 if (!(data & KVM_MSR_ENABLED))
2062 break;
2063
2064 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2065
2066 preempt_disable();
2067 accumulate_steal_time(vcpu);
2068 preempt_enable();
2069
2070 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2071
2072 break;
ae7a2a3f
MT		 2073 case MSR_KVM_PV_EOI_EN:
2074 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2075 return 1;
2076 break;
c9aaa895 2077
890ca9ae
HY		 2078 case MSR_IA32_MCG_CTL:
2079 case MSR_IA32_MCG_STATUS:
81760dcc 2080 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2081 return set_msr_mce(vcpu, msr, data);
71db6023 2082
6912ac32
WH		 2083 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2084 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2085 pr = true; /* fall through */
2086 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2087 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2088 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2089 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2090
2091 if (pr || data != 0)
a737f256
CD		 2092 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2093 "0x%x data 0x%llx\n", msr, data);
5753785f 2094 break;
84e0cefa
JS		 2095 case MSR_K7_CLK_CTL:
2096 /*
2097 * Ignore all writes to this no longer documented MSR.
2098 * Writes are only relevant for old K7 processors,
2099 * all pre-dating SVM, but a recommended workaround from
4a969980 2100 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2101 * affected processor models on the command line, hence
2102 * the need to ignore the workaround.
2103 */
2104 break;
55cd8e5a 2105 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2106 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2107 case HV_X64_MSR_CRASH_CTL:
2108 return kvm_hv_set_msr_common(vcpu, msr, data,
2109 msr_info->host_initiated);
91c9c3ed 2110 case MSR_IA32_BBL_CR_CTL3:
2111 /* Drop writes to this legacy MSR -- see rdmsr
2112 * counterpart for further detail.
2113 */
a737f256 2114 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2115 break;
2b036c6b
BO		 2116 case MSR_AMD64_OSVW_ID_LENGTH:
2117 if (!guest_cpuid_has_osvw(vcpu))
2118 return 1;
2119 vcpu->arch.osvw.length = data;
2120 break;
2121 case MSR_AMD64_OSVW_STATUS:
2122 if (!guest_cpuid_has_osvw(vcpu))
2123 return 1;
2124 vcpu->arch.osvw.status = data;
2125 break;
15c4a640 2126 default:
ffde22ac
ES		 2127 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2128 return xen_hvm_config(vcpu, data);
c6702c9d 2129 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2130 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2131 if (!ignore_msrs) {
a737f256
CD		 2132 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2133 msr, data);
ed85c068
AP		 2134 return 1;
2135 } else {
a737f256
CD		 2136 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2137 msr, data);
ed85c068
AP		 2138 break;
2139 }
15c4a640
CO		 2140 }
2141 return 0;
2142}
2143EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2144
2145
2146/*
2147 * Reads an msr value (of 'msr_index') into 'pdata'.
2148 * Returns 0 on success, non-0 otherwise.
2149 * Assumes vcpu_load() was already called.
2150 */
609e36d3 2151int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2152{
609e36d3 2153 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2154}
ff651cb6 2155EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2156
890ca9ae 2157static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2158{
2159 u64 data;
890ca9ae
HY		 2160 u64 mcg_cap = vcpu->arch.mcg_cap;
2161 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2162
2163 switch (msr) {
15c4a640
CO		 2164 case MSR_IA32_P5_MC_ADDR:
2165 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2166 data = 0;
2167 break;
15c4a640 2168 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2169 data = vcpu->arch.mcg_cap;
2170 break;
c7ac679c 2171 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2172 if (!(mcg_cap & MCG_CTL_P))
2173 return 1;
2174 data = vcpu->arch.mcg_ctl;
2175 break;
2176 case MSR_IA32_MCG_STATUS:
2177 data = vcpu->arch.mcg_status;
2178 break;
2179 default:
2180 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2181 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2182 u32 offset = msr - MSR_IA32_MC0_CTL;
2183 data = vcpu->arch.mce_banks[offset];
2184 break;
2185 }
2186 return 1;
2187 }
2188 *pdata = data;
2189 return 0;
2190}
2191
609e36d3 2192int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2193{
609e36d3 2194 switch (msr_info->index) {
890ca9ae 2195 case MSR_IA32_PLATFORM_ID:
15c4a640 2196 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2197 case MSR_IA32_DEBUGCTLMSR:
2198 case MSR_IA32_LASTBRANCHFROMIP:
2199 case MSR_IA32_LASTBRANCHTOIP:
2200 case MSR_IA32_LASTINTFROMIP:
2201 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2202 case MSR_K8_SYSCFG:
2203 case MSR_K7_HWCR:
61a6bd67 2204 case MSR_VM_HSAVE_PA:
1fdbd48c 2205 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2206 case MSR_AMD64_NB_CFG:
f7c6d140 2207 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2208 case MSR_AMD64_BU_CFG2:
609e36d3 2209 msr_info->data = 0;
15c4a640 2210 break;
6912ac32
WH		 2211 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2212 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2213 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2214 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2215 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2216 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2217 msr_info->data = 0;
5753785f 2218 break;
742bc670 2219 case MSR_IA32_UCODE_REV:
609e36d3 2220 msr_info->data = 0x100000000ULL;
742bc670 2221 break;
9ba075a6 2222 case MSR_MTRRcap:
9ba075a6 2223 case 0x200 ... 0x2ff:
ff53604b 2224 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2225 case 0xcd: /* fsb frequency */
609e36d3 2226 msr_info->data = 3;
15c4a640 2227 break;
7b914098
JS		 2228 /*
2229 * MSR_EBC_FREQUENCY_ID
2230 * Conservative value valid for even the basic CPU models.
2231 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2232 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2233 * and 266MHz for model 3, or 4. Set Core Clock
2234 * Frequency to System Bus Frequency Ratio to 1 (bits
2235 * 31:24) even though these are only valid for CPU
2236 * models > 2, however guests may end up dividing or
2237 * multiplying by zero otherwise.
2238 */
2239 case MSR_EBC_FREQUENCY_ID:
609e36d3 2240 msr_info->data = 1 << 24;
7b914098 2241 break;
15c4a640 2242 case MSR_IA32_APICBASE:
609e36d3 2243 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2244 break;
0105d1a5 2245 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2246 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2247 break;
a3e06bbe 2248 case MSR_IA32_TSCDEADLINE:
609e36d3 2249 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2250 break;
ba904635 2251 case MSR_IA32_TSC_ADJUST:
609e36d3 2252 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2253 break;
15c4a640 2254 case MSR_IA32_MISC_ENABLE:
609e36d3 2255 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2256 break;
64d60670
PB		 2257 case MSR_IA32_SMBASE:
2258 if (!msr_info->host_initiated)
2259 return 1;
2260 msr_info->data = vcpu->arch.smbase;
15c4a640 2261 break;
847f0ad8
AG		 2262 case MSR_IA32_PERF_STATUS:
2263 /* TSC increment by tick */
609e36d3 2264 msr_info->data = 1000ULL;
847f0ad8 2265 /* CPU multiplier */
b0996ae4 2266 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2267 break;
15c4a640 2268 case MSR_EFER:
609e36d3 2269 msr_info->data = vcpu->arch.efer;
15c4a640 2270 break;
18068523 2271 case MSR_KVM_WALL_CLOCK:
11c6bffa 2272 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2273 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2274 break;
2275 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2276 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2277 msr_info->data = vcpu->arch.time;
18068523 2278 break;
344d9588 2279 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2280 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2281 break;
c9aaa895 2282 case MSR_KVM_STEAL_TIME:
609e36d3 2283 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2284 break;
1d92128f 2285 case MSR_KVM_PV_EOI_EN:
609e36d3 2286 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2287 break;
890ca9ae
HY		 2288 case MSR_IA32_P5_MC_ADDR:
2289 case MSR_IA32_P5_MC_TYPE:
2290 case MSR_IA32_MCG_CAP:
2291 case MSR_IA32_MCG_CTL:
2292 case MSR_IA32_MCG_STATUS:
81760dcc 2293 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2294 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2295 case MSR_K7_CLK_CTL:
2296 /*
2297 * Provide expected ramp-up count for K7. All other
2298 * are set to zero, indicating minimum divisors for
2299 * every field.
2300 *
2301 * This prevents guest kernels on AMD host with CPU
2302 * type 6, model 8 and higher from exploding due to
2303 * the rdmsr failing.
2304 */
609e36d3 2305 msr_info->data = 0x20000000;
84e0cefa 2306 break;
55cd8e5a 2307 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2308 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2309 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2310 return kvm_hv_get_msr_common(vcpu,
2311 msr_info->index, &msr_info->data);
55cd8e5a 2312 break;
91c9c3ed 2313 case MSR_IA32_BBL_CR_CTL3:
2314 /* This legacy MSR exists but isn't fully documented in current
2315 * silicon. It is however accessed by winxp in very narrow
2316 * scenarios where it sets bit #19, itself documented as
2317 * a "reserved" bit. Best effort attempt to source coherent
2318 * read data here should the balance of the register be
2319 * interpreted by the guest:
2320 *
2321 * L2 cache control register 3: 64GB range, 256KB size,
2322 * enabled, latency 0x1, configured
2323 */
609e36d3 2324 msr_info->data = 0xbe702111;
91c9c3ed 2325 break;
2b036c6b
BO		 2326 case MSR_AMD64_OSVW_ID_LENGTH:
2327 if (!guest_cpuid_has_osvw(vcpu))
2328 return 1;
609e36d3 2329 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2330 break;
2331 case MSR_AMD64_OSVW_STATUS:
2332 if (!guest_cpuid_has_osvw(vcpu))
2333 return 1;
609e36d3 2334 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2335 break;
15c4a640 2336 default:
c6702c9d 2337 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2338 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2339 if (!ignore_msrs) {
609e36d3 2340 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2341 return 1;
2342 } else {
609e36d3
PB		 2343 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2344 msr_info->data = 0;
ed85c068
AP		 2345 }
2346 break;
15c4a640 2347 }
15c4a640
CO		 2348 return 0;
2349}
2350EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2351
313a3dc7
CO		 2352/*
2353 * Read or write a bunch of msrs. All parameters are kernel addresses.
2354 *
2355 * @return number of msrs set successfully.
2356 */
2357static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2358 struct kvm_msr_entry *entries,
2359 int (*do_msr)(struct kvm_vcpu *vcpu,
2360 unsigned index, u64 *data))
2361{
f656ce01 2362 int i, idx;
313a3dc7 2363
f656ce01 2364 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2365 for (i = 0; i < msrs->nmsrs; ++i)
2366 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2367 break;
f656ce01 2368 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2369
313a3dc7
CO		 2370 return i;
2371}
2372
2373/*
2374 * Read or write a bunch of msrs. Parameters are user addresses.
2375 *
2376 * @return number of msrs set successfully.
2377 */
2378static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2379 int (*do_msr)(struct kvm_vcpu *vcpu,
2380 unsigned index, u64 *data),
2381 int writeback)
2382{
2383 struct kvm_msrs msrs;
2384 struct kvm_msr_entry *entries;
2385 int r, n;
2386 unsigned size;
2387
2388 r = -EFAULT;
2389 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2390 goto out;
2391
2392 r = -E2BIG;
2393 if (msrs.nmsrs >= MAX_IO_MSRS)
2394 goto out;
2395
313a3dc7 2396 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2397 entries = memdup_user(user_msrs->entries, size);
2398 if (IS_ERR(entries)) {
2399 r = PTR_ERR(entries);
313a3dc7 2400 goto out;
ff5c2c03 2401 }
313a3dc7
CO		 2402
2403 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2404 if (r < 0)
2405 goto out_free;
2406
2407 r = -EFAULT;
2408 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2409 goto out_free;
2410
2411 r = n;
2412
2413out_free:
7a73c028 2414 kfree(entries);
313a3dc7
CO		 2415out:
2416 return r;
2417}
2418
784aa3d7 2419int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2420{
2421 int r;
2422
2423 switch (ext) {
2424 case KVM_CAP_IRQCHIP:
2425 case KVM_CAP_HLT:
2426 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2427 case KVM_CAP_SET_TSS_ADDR:
07716717 2428 case KVM_CAP_EXT_CPUID:
9c15bb1d 2429 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2430 case KVM_CAP_CLOCKSOURCE:
7837699f 2431 case KVM_CAP_PIT:
a28e4f5a 2432 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2433 case KVM_CAP_MP_STATE:
ed848624 2434 case KVM_CAP_SYNC_MMU:
a355c85c 2435 case KVM_CAP_USER_NMI:
52d939a0 2436 case KVM_CAP_REINJECT_CONTROL:
4925663a 2437 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2438 case KVM_CAP_IOEVENTFD:
f848a5a8 2439 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2440 case KVM_CAP_PIT2:
e9f42757 2441 case KVM_CAP_PIT_STATE2:
b927a3ce 2442 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2443 case KVM_CAP_XEN_HVM:
afbcf7ab 2444 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2445 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2446 case KVM_CAP_HYPERV:
10388a07 2447 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2448 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2449 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2450 case KVM_CAP_DEBUGREGS:
d2be1651 2451 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2452 case KVM_CAP_XSAVE:
344d9588 2453 case KVM_CAP_ASYNC_PF:
92a1f12d 2454 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2455 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2456 case KVM_CAP_READONLY_MEM:
5f66b620 2457 case KVM_CAP_HYPERV_TIME:
100943c5 2458 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2459 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2460 case KVM_CAP_ENABLE_CAP_VM:
2461 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2462 case KVM_CAP_SET_BOOT_CPU_ID:
2a5bab10
AW		 2463#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2464 case KVM_CAP_ASSIGN_DEV_IRQ:
2465 case KVM_CAP_PCI_2_3:
2466#endif
018d00d2
ZX		 2467 r = 1;
2468 break;
6d396b55
PB		 2469 case KVM_CAP_X86_SMM:
2470 /* SMBASE is usually relocated above 1M on modern chipsets,
2471 * and SMM handlers might indeed rely on 4G segment limits,
2472 * so do not report SMM to be available if real mode is
2473 * emulated via vm86 mode. Still, do not go to great lengths
2474 * to avoid userspace's usage of the feature, because it is a
2475 * fringe case that is not enabled except via specific settings
2476 * of the module parameters.
2477 */
2478 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2479 break;
542472b5
LV		 2480 case KVM_CAP_COALESCED_MMIO:
2481 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2482 break;
774ead3a
AK		 2483 case KVM_CAP_VAPIC:
2484 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2485 break;
f725230a 2486 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2487 r = KVM_SOFT_MAX_VCPUS;
2488 break;
2489 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2490 r = KVM_MAX_VCPUS;
2491 break;
a988b910 2492 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2493 r = KVM_USER_MEM_SLOTS;
a988b910 2494 break;
a68a6a72
MT		 2495 case KVM_CAP_PV_MMU: /* obsolete */
2496 r = 0;
2f333bcb 2497 break;
4cee4b72 2498#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2499 case KVM_CAP_IOMMU:
a1b60c1c 2500 r = iommu_present(&pci_bus_type);
62c476c7 2501 break;
4cee4b72 2502#endif
890ca9ae
HY		 2503 case KVM_CAP_MCE:
2504 r = KVM_MAX_MCE_BANKS;
2505 break;
2d5b5a66
SY		 2506 case KVM_CAP_XCRS:
2507 r = cpu_has_xsave;
2508 break;
92a1f12d
JR		 2509 case KVM_CAP_TSC_CONTROL:
2510 r = kvm_has_tsc_control;
2511 break;
018d00d2
ZX		 2512 default:
2513 r = 0;
2514 break;
2515 }
2516 return r;
2517
2518}
2519
043405e1
CO		 2520long kvm_arch_dev_ioctl(struct file *filp,
2521 unsigned int ioctl, unsigned long arg)
2522{
2523 void __user *argp = (void __user *)arg;
2524 long r;
2525
2526 switch (ioctl) {
2527 case KVM_GET_MSR_INDEX_LIST: {
2528 struct kvm_msr_list __user *user_msr_list = argp;
2529 struct kvm_msr_list msr_list;
2530 unsigned n;
2531
2532 r = -EFAULT;
2533 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2534 goto out;
2535 n = msr_list.nmsrs;
62ef68bb 2536 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2537 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2538 goto out;
2539 r = -E2BIG;
e125e7b6 2540 if (n < msr_list.nmsrs)
043405e1
CO		 2541 goto out;
2542 r = -EFAULT;
2543 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2544 num_msrs_to_save * sizeof(u32)))
2545 goto out;
e125e7b6 2546 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2547 &emulated_msrs,
62ef68bb 2548 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2549 goto out;
2550 r = 0;
2551 break;
2552 }
9c15bb1d
BP		 2553 case KVM_GET_SUPPORTED_CPUID:
2554 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2555 struct kvm_cpuid2 __user *cpuid_arg = argp;
2556 struct kvm_cpuid2 cpuid;
2557
2558 r = -EFAULT;
2559 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2560 goto out;
9c15bb1d
BP		 2561
2562 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2563 ioctl);
674eea0f
AK		 2564 if (r)
2565 goto out;
2566
2567 r = -EFAULT;
2568 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2569 goto out;
2570 r = 0;
2571 break;
2572 }
890ca9ae
HY		 2573 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2574 u64 mce_cap;
2575
2576 mce_cap = KVM_MCE_CAP_SUPPORTED;
2577 r = -EFAULT;
2578 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2579 goto out;
2580 r = 0;
2581 break;
2582 }
043405e1
CO		 2583 default:
2584 r = -EINVAL;
2585 }
2586out:
2587 return r;
2588}
2589
f5f48ee1
SY		 2590static void wbinvd_ipi(void *garbage)
2591{
2592 wbinvd();
2593}
2594
2595static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2596{
e0f0bbc5 2597 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2598}
2599
313a3dc7
CO		 2600void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2601{
f5f48ee1
SY		 2602 /* Address WBINVD may be executed by guest */
2603 if (need_emulate_wbinvd(vcpu)) {
2604 if (kvm_x86_ops->has_wbinvd_exit())
2605 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2606 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2607 smp_call_function_single(vcpu->cpu,
2608 wbinvd_ipi, NULL, 1);
2609 }
2610
313a3dc7 2611 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2612
0dd6a6ed
ZA		 2613 /* Apply any externally detected TSC adjustments (due to suspend) */
2614 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2615 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2616 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2617 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2618 }
8f6055cb 2619
48434c20 2620 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2621 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2622 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2623 if (tsc_delta < 0)
2624 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2625 if (check_tsc_unstable()) {
b183aa58
ZA		 2626 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2627 vcpu->arch.last_guest_tsc);
2628 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2629 vcpu->arch.tsc_catchup = 1;
c285545f 2630 }
d98d07ca
MT		 2631 /*
2632 * On a host with synchronized TSC, there is no need to update
2633 * kvmclock on vcpu->cpu migration
2634 */
2635 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2636 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2637 if (vcpu->cpu != cpu)
2638 kvm_migrate_timers(vcpu);
e48672fa 2639 vcpu->cpu = cpu;
6b7d7e76 2640 }
c9aaa895
GC		 2641
2642 accumulate_steal_time(vcpu);
2643 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2644}
2645
2646void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2647{
02daab21 2648 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2649 kvm_put_guest_fpu(vcpu);
6f526ec5 2650 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2651}
2652
313a3dc7
CO		 2653static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2654 struct kvm_lapic_state *s)
2655{
5a71785d 2656 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2657 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2658
2659 return 0;
2660}
2661
2662static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2663 struct kvm_lapic_state *s)
2664{
64eb0620 2665 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2666 update_cr8_intercept(vcpu);
313a3dc7
CO		 2667
2668 return 0;
2669}
2670
f77bc6a4
ZX		 2671static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2672 struct kvm_interrupt *irq)
2673{
02cdb50f 2674 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2675 return -EINVAL;
2676 if (irqchip_in_kernel(vcpu->kvm))
2677 return -ENXIO;
f77bc6a4 2678
66fd3f7f 2679 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2680 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2681
f77bc6a4
ZX		 2682 return 0;
2683}
2684
c4abb7c9
JK		 2685static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2686{
c4abb7c9 2687 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2688
2689 return 0;
2690}
2691
f077825a
PB		 2692static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2693{
64d60670
PB		 2694 kvm_make_request(KVM_REQ_SMI, vcpu);
2695
f077825a
PB		 2696 return 0;
2697}
2698
b209749f
AK		 2699static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2700 struct kvm_tpr_access_ctl *tac)
2701{
2702 if (tac->flags)
2703 return -EINVAL;
2704 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2705 return 0;
2706}
2707
890ca9ae
HY		 2708static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2709 u64 mcg_cap)
2710{
2711 int r;
2712 unsigned bank_num = mcg_cap & 0xff, bank;
2713
2714 r = -EINVAL;
a9e38c3e 2715 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2716 goto out;
2717 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2718 goto out;
2719 r = 0;
2720 vcpu->arch.mcg_cap = mcg_cap;
2721 /* Init IA32_MCG_CTL to all 1s */
2722 if (mcg_cap & MCG_CTL_P)
2723 vcpu->arch.mcg_ctl = ~(u64)0;
2724 /* Init IA32_MCi_CTL to all 1s */
2725 for (bank = 0; bank < bank_num; bank++)
2726 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2727out:
2728 return r;
2729}
2730
2731static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2732 struct kvm_x86_mce *mce)
2733{
2734 u64 mcg_cap = vcpu->arch.mcg_cap;
2735 unsigned bank_num = mcg_cap & 0xff;
2736 u64 *banks = vcpu->arch.mce_banks;
2737
2738 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2739 return -EINVAL;
2740 /*
2741 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2742 * reporting is disabled
2743 */
2744 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2745 vcpu->arch.mcg_ctl != ~(u64)0)
2746 return 0;
2747 banks += 4 * mce->bank;
2748 /*
2749 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2750 * reporting is disabled for the bank
2751 */
2752 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2753 return 0;
2754 if (mce->status & MCI_STATUS_UC) {
2755 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2756 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2757 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2758 return 0;
2759 }
2760 if (banks[1] & MCI_STATUS_VAL)
2761 mce->status |= MCI_STATUS_OVER;
2762 banks[2] = mce->addr;
2763 banks[3] = mce->misc;
2764 vcpu->arch.mcg_status = mce->mcg_status;
2765 banks[1] = mce->status;
2766 kvm_queue_exception(vcpu, MC_VECTOR);
2767 } else if (!(banks[1] & MCI_STATUS_VAL)
2768 || !(banks[1] & MCI_STATUS_UC)) {
2769 if (banks[1] & MCI_STATUS_VAL)
2770 mce->status |= MCI_STATUS_OVER;
2771 banks[2] = mce->addr;
2772 banks[3] = mce->misc;
2773 banks[1] = mce->status;
2774 } else
2775 banks[1] |= MCI_STATUS_OVER;
2776 return 0;
2777}
2778
3cfc3092
JK		 2779static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2780 struct kvm_vcpu_events *events)
2781{
7460fb4a 2782 process_nmi(vcpu);
03b82a30
JK		 2783 events->exception.injected =
2784 vcpu->arch.exception.pending &&
2785 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2786 events->exception.nr = vcpu->arch.exception.nr;
2787 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2788 events->exception.pad = 0;
3cfc3092
JK		 2789 events->exception.error_code = vcpu->arch.exception.error_code;
2790
03b82a30
JK		 2791 events->interrupt.injected =
2792 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2793 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2794 events->interrupt.soft = 0;
37ccdcbe 2795 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2796
2797 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2798 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2799 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2800 events->nmi.pad = 0;
3cfc3092 2801
66450a21 2802 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2803
f077825a
PB		 2804 events->smi.smm = is_smm(vcpu);
2805 events->smi.pending = vcpu->arch.smi_pending;
2806 events->smi.smm_inside_nmi =
2807 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2808 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2809
dab4b911 2810 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2811 | KVM_VCPUEVENT_VALID_SHADOW
2812 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2813 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2814}
2815
2816static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2817 struct kvm_vcpu_events *events)
2818{
dab4b911 2819 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2820 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2821 | KVM_VCPUEVENT_VALID_SHADOW
2822 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2823 return -EINVAL;
2824
7460fb4a 2825 process_nmi(vcpu);
3cfc3092
JK		 2826 vcpu->arch.exception.pending = events->exception.injected;
2827 vcpu->arch.exception.nr = events->exception.nr;
2828 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2829 vcpu->arch.exception.error_code = events->exception.error_code;
2830
2831 vcpu->arch.interrupt.pending = events->interrupt.injected;
2832 vcpu->arch.interrupt.nr = events->interrupt.nr;
2833 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2834 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2835 kvm_x86_ops->set_interrupt_shadow(vcpu,
2836 events->interrupt.shadow);
3cfc3092
JK		 2837
2838 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2839 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2840 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2841 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2842
66450a21
JK		 2843 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2844 kvm_vcpu_has_lapic(vcpu))
2845 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2846
f077825a
PB		 2847 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2848 if (events->smi.smm)
2849 vcpu->arch.hflags |= HF_SMM_MASK;
2850 else
2851 vcpu->arch.hflags &= ~HF_SMM_MASK;
2852 vcpu->arch.smi_pending = events->smi.pending;
2853 if (events->smi.smm_inside_nmi)
2854 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2855 else
2856 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2857 if (kvm_vcpu_has_lapic(vcpu)) {
2858 if (events->smi.latched_init)
2859 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2860 else
2861 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2862 }
2863 }
2864
3842d135
AK		 2865 kvm_make_request(KVM_REQ_EVENT, vcpu);
2866
3cfc3092
JK		 2867 return 0;
2868}
2869
a1efbe77
JK		 2870static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2871 struct kvm_debugregs *dbgregs)
2872{
73aaf249
JK		 2873 unsigned long val;
2874
a1efbe77 2875 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2876 kvm_get_dr(vcpu, 6, &val);
73aaf249 2877 dbgregs->dr6 = val;
a1efbe77
JK		 2878 dbgregs->dr7 = vcpu->arch.dr7;
2879 dbgregs->flags = 0;
97e69aa6 2880 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2881}
2882
2883static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2884 struct kvm_debugregs *dbgregs)
2885{
2886 if (dbgregs->flags)
2887 return -EINVAL;
2888
a1efbe77 2889 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2890 kvm_update_dr0123(vcpu);
a1efbe77 2891 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2892 kvm_update_dr6(vcpu);
a1efbe77 2893 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2894 kvm_update_dr7(vcpu);
a1efbe77 2895
a1efbe77
JK		 2896 return 0;
2897}
2898
df1daba7
PB		 2899#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2900
2901static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2902{
c47ada30 2903 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2904 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2905 u64 valid;
2906
2907 /*
2908 * Copy legacy XSAVE area, to avoid complications with CPUID
2909 * leaves 0 and 1 in the loop below.
2910 */
2911 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2912
2913 /* Set XSTATE_BV */
2914 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2915
2916 /*
2917 * Copy each region from the possibly compacted offset to the
2918 * non-compacted offset.
2919 */
2920 valid = xstate_bv & ~XSTATE_FPSSE;
2921 while (valid) {
2922 u64 feature = valid & -valid;
2923 int index = fls64(feature) - 1;
2924 void *src = get_xsave_addr(xsave, feature);
2925
2926 if (src) {
2927 u32 size, offset, ecx, edx;
2928 cpuid_count(XSTATE_CPUID, index,
2929 &size, &offset, &ecx, &edx);
2930 memcpy(dest + offset, src, size);
2931 }
2932
2933 valid -= feature;
2934 }
2935}
2936
2937static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2938{
c47ada30 2939 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2940 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2941 u64 valid;
2942
2943 /*
2944 * Copy legacy XSAVE area, to avoid complications with CPUID
2945 * leaves 0 and 1 in the loop below.
2946 */
2947 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2948
2949 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2950 xsave->header.xfeatures = xstate_bv;
df1daba7 2951 if (cpu_has_xsaves)
3a54450b 2952 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2953
2954 /*
2955 * Copy each region from the non-compacted offset to the
2956 * possibly compacted offset.
2957 */
2958 valid = xstate_bv & ~XSTATE_FPSSE;
2959 while (valid) {
2960 u64 feature = valid & -valid;
2961 int index = fls64(feature) - 1;
2962 void *dest = get_xsave_addr(xsave, feature);
2963
2964 if (dest) {
2965 u32 size, offset, ecx, edx;
2966 cpuid_count(XSTATE_CPUID, index,
2967 &size, &offset, &ecx, &edx);
2968 memcpy(dest, src + offset, size);
ee4100da 2969 }
df1daba7
PB		 2970
2971 valid -= feature;
2972 }
2973}
2974
2d5b5a66
SY		 2975static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2976 struct kvm_xsave *guest_xsave)
2977{
4344ee98 2978 if (cpu_has_xsave) {
df1daba7
PB		 2979 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2980 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2981 } else {
2d5b5a66 2982 memcpy(guest_xsave->region,
7366ed77 2983 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2984 sizeof(struct fxregs_state));
2d5b5a66
SY		 2985 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2986 XSTATE_FPSSE;
2987 }
2988}
2989
2990static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2991 struct kvm_xsave *guest_xsave)
2992{
2993 u64 xstate_bv =
2994 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2995
d7876f1b
PB		 2996 if (cpu_has_xsave) {
2997 /*
2998 * Here we allow setting states that are not present in
2999 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3000 * with old userspace.
3001 */
4ff41732 3002 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3003 return -EINVAL;
df1daba7 3004 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3005 } else {
2d5b5a66
SY		 3006 if (xstate_bv & ~XSTATE_FPSSE)
3007 return -EINVAL;
7366ed77 3008 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3009 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3010 }
3011 return 0;
3012}
3013
3014static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3015 struct kvm_xcrs *guest_xcrs)
3016{
3017 if (!cpu_has_xsave) {
3018 guest_xcrs->nr_xcrs = 0;
3019 return;
3020 }
3021
3022 guest_xcrs->nr_xcrs = 1;
3023 guest_xcrs->flags = 0;
3024 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3025 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3026}
3027
3028static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3029 struct kvm_xcrs *guest_xcrs)
3030{
3031 int i, r = 0;
3032
3033 if (!cpu_has_xsave)
3034 return -EINVAL;
3035
3036 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3037 return -EINVAL;
3038
3039 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3040 /* Only support XCR0 currently */
c67a04cb 3041 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3042 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3043 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3044 break;
3045 }
3046 if (r)
3047 r = -EINVAL;
3048 return r;
3049}
3050
1c0b28c2
EM		 3051/*
3052 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3053 * stopped by the hypervisor. This function will be called from the host only.
3054 * EINVAL is returned when the host attempts to set the flag for a guest that
3055 * does not support pv clocks.
3056 */
3057static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3058{
0b79459b 3059 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3060 return -EINVAL;
51d59c6b 3061 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3063 return 0;
3064}
3065
313a3dc7
CO		 3066long kvm_arch_vcpu_ioctl(struct file *filp,
3067 unsigned int ioctl, unsigned long arg)
3068{
3069 struct kvm_vcpu *vcpu = filp->private_data;
3070 void __user *argp = (void __user *)arg;
3071 int r;
d1ac91d8
AK		 3072 union {
3073 struct kvm_lapic_state *lapic;
3074 struct kvm_xsave *xsave;
3075 struct kvm_xcrs *xcrs;
3076 void *buffer;
3077 } u;
3078
3079 u.buffer = NULL;
313a3dc7
CO		 3080 switch (ioctl) {
3081 case KVM_GET_LAPIC: {
2204ae3c
MT		 3082 r = -EINVAL;
3083 if (!vcpu->arch.apic)
3084 goto out;
d1ac91d8 3085 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3086
b772ff36 3087 r = -ENOMEM;
d1ac91d8 3088 if (!u.lapic)
b772ff36 3089 goto out;
d1ac91d8 3090 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3091 if (r)
3092 goto out;
3093 r = -EFAULT;
d1ac91d8 3094 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3095 goto out;
3096 r = 0;
3097 break;
3098 }
3099 case KVM_SET_LAPIC: {
2204ae3c
MT		 3100 r = -EINVAL;
3101 if (!vcpu->arch.apic)
3102 goto out;
ff5c2c03 3103 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3104 if (IS_ERR(u.lapic))
3105 return PTR_ERR(u.lapic);
ff5c2c03 3106
d1ac91d8 3107 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3108 break;
3109 }
f77bc6a4
ZX		 3110 case KVM_INTERRUPT: {
3111 struct kvm_interrupt irq;
3112
3113 r = -EFAULT;
3114 if (copy_from_user(&irq, argp, sizeof irq))
3115 goto out;
3116 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3117 break;
3118 }
c4abb7c9
JK		 3119 case KVM_NMI: {
3120 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3121 break;
3122 }
f077825a
PB		 3123 case KVM_SMI: {
3124 r = kvm_vcpu_ioctl_smi(vcpu);
3125 break;
3126 }
313a3dc7
CO		 3127 case KVM_SET_CPUID: {
3128 struct kvm_cpuid __user *cpuid_arg = argp;
3129 struct kvm_cpuid cpuid;
3130
3131 r = -EFAULT;
3132 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3133 goto out;
3134 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3135 break;
3136 }
07716717
DK		 3137 case KVM_SET_CPUID2: {
3138 struct kvm_cpuid2 __user *cpuid_arg = argp;
3139 struct kvm_cpuid2 cpuid;
3140
3141 r = -EFAULT;
3142 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3143 goto out;
3144 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3145 cpuid_arg->entries);
07716717
DK		 3146 break;
3147 }
3148 case KVM_GET_CPUID2: {
3149 struct kvm_cpuid2 __user *cpuid_arg = argp;
3150 struct kvm_cpuid2 cpuid;
3151
3152 r = -EFAULT;
3153 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3154 goto out;
3155 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3156 cpuid_arg->entries);
07716717
DK		 3157 if (r)
3158 goto out;
3159 r = -EFAULT;
3160 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3161 goto out;
3162 r = 0;
3163 break;
3164 }
313a3dc7 3165 case KVM_GET_MSRS:
609e36d3 3166 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3167 break;
3168 case KVM_SET_MSRS:
3169 r = msr_io(vcpu, argp, do_set_msr, 0);
3170 break;
b209749f
AK		 3171 case KVM_TPR_ACCESS_REPORTING: {
3172 struct kvm_tpr_access_ctl tac;
3173
3174 r = -EFAULT;
3175 if (copy_from_user(&tac, argp, sizeof tac))
3176 goto out;
3177 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3178 if (r)
3179 goto out;
3180 r = -EFAULT;
3181 if (copy_to_user(argp, &tac, sizeof tac))
3182 goto out;
3183 r = 0;
3184 break;
3185 };
b93463aa
AK		 3186 case KVM_SET_VAPIC_ADDR: {
3187 struct kvm_vapic_addr va;
3188
3189 r = -EINVAL;
3190 if (!irqchip_in_kernel(vcpu->kvm))
3191 goto out;
3192 r = -EFAULT;
3193 if (copy_from_user(&va, argp, sizeof va))
3194 goto out;
fda4e2e8 3195 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3196 break;
3197 }
890ca9ae
HY		 3198 case KVM_X86_SETUP_MCE: {
3199 u64 mcg_cap;
3200
3201 r = -EFAULT;
3202 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3203 goto out;
3204 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3205 break;
3206 }
3207 case KVM_X86_SET_MCE: {
3208 struct kvm_x86_mce mce;
3209
3210 r = -EFAULT;
3211 if (copy_from_user(&mce, argp, sizeof mce))
3212 goto out;
3213 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3214 break;
3215 }
3cfc3092
JK		 3216 case KVM_GET_VCPU_EVENTS: {
3217 struct kvm_vcpu_events events;
3218
3219 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3220
3221 r = -EFAULT;
3222 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3223 break;
3224 r = 0;
3225 break;
3226 }
3227 case KVM_SET_VCPU_EVENTS: {
3228 struct kvm_vcpu_events events;
3229
3230 r = -EFAULT;
3231 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3232 break;
3233
3234 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3235 break;
3236 }
a1efbe77
JK		 3237 case KVM_GET_DEBUGREGS: {
3238 struct kvm_debugregs dbgregs;
3239
3240 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3241
3242 r = -EFAULT;
3243 if (copy_to_user(argp, &dbgregs,
3244 sizeof(struct kvm_debugregs)))
3245 break;
3246 r = 0;
3247 break;
3248 }
3249 case KVM_SET_DEBUGREGS: {
3250 struct kvm_debugregs dbgregs;
3251
3252 r = -EFAULT;
3253 if (copy_from_user(&dbgregs, argp,
3254 sizeof(struct kvm_debugregs)))
3255 break;
3256
3257 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3258 break;
3259 }
2d5b5a66 3260 case KVM_GET_XSAVE: {
d1ac91d8 3261 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3262 r = -ENOMEM;
d1ac91d8 3263 if (!u.xsave)
2d5b5a66
SY		 3264 break;
3265
d1ac91d8 3266 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3267
3268 r = -EFAULT;
d1ac91d8 3269 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3270 break;
3271 r = 0;
3272 break;
3273 }
3274 case KVM_SET_XSAVE: {
ff5c2c03 3275 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3276 if (IS_ERR(u.xsave))
3277 return PTR_ERR(u.xsave);
2d5b5a66 3278
d1ac91d8 3279 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3280 break;
3281 }
3282 case KVM_GET_XCRS: {
d1ac91d8 3283 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3284 r = -ENOMEM;
d1ac91d8 3285 if (!u.xcrs)
2d5b5a66
SY		 3286 break;
3287
d1ac91d8 3288 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3289
3290 r = -EFAULT;
d1ac91d8 3291 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3292 sizeof(struct kvm_xcrs)))
3293 break;
3294 r = 0;
3295 break;
3296 }
3297 case KVM_SET_XCRS: {
ff5c2c03 3298 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3299 if (IS_ERR(u.xcrs))
3300 return PTR_ERR(u.xcrs);
2d5b5a66 3301
d1ac91d8 3302 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3303 break;
3304 }
92a1f12d
JR		 3305 case KVM_SET_TSC_KHZ: {
3306 u32 user_tsc_khz;
3307
3308 r = -EINVAL;
92a1f12d
JR		 3309 user_tsc_khz = (u32)arg;
3310
3311 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3312 goto out;
3313
cc578287
ZA		 3314 if (user_tsc_khz == 0)
3315 user_tsc_khz = tsc_khz;
3316
3317 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3318
3319 r = 0;
3320 goto out;
3321 }
3322 case KVM_GET_TSC_KHZ: {
cc578287 3323 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3324 goto out;
3325 }
1c0b28c2
EM		 3326 case KVM_KVMCLOCK_CTRL: {
3327 r = kvm_set_guest_paused(vcpu);
3328 goto out;
3329 }
313a3dc7
CO		 3330 default:
3331 r = -EINVAL;
3332 }
3333out:
d1ac91d8 3334 kfree(u.buffer);
313a3dc7
CO		 3335 return r;
3336}
3337
5b1c1493
CO		 3338int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3339{
3340 return VM_FAULT_SIGBUS;
3341}
3342
1fe779f8
CO		 3343static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3344{
3345 int ret;
3346
3347 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3348 return -EINVAL;
1fe779f8
CO		 3349 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3350 return ret;
3351}
3352
b927a3ce
SY		 3353static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3354 u64 ident_addr)
3355{
3356 kvm->arch.ept_identity_map_addr = ident_addr;
3357 return 0;
3358}
3359
1fe779f8
CO		 3360static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3361 u32 kvm_nr_mmu_pages)
3362{
3363 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3364 return -EINVAL;
3365
79fac95e 3366 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3367
3368 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3369 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3370
79fac95e 3371 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3372 return 0;
3373}
3374
3375static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3376{
39de71ec 3377 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3378}
3379
1fe779f8
CO		 3380static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3381{
3382 int r;
3383
3384 r = 0;
3385 switch (chip->chip_id) {
3386 case KVM_IRQCHIP_PIC_MASTER:
3387 memcpy(&chip->chip.pic,
3388 &pic_irqchip(kvm)->pics[0],
3389 sizeof(struct kvm_pic_state));
3390 break;
3391 case KVM_IRQCHIP_PIC_SLAVE:
3392 memcpy(&chip->chip.pic,
3393 &pic_irqchip(kvm)->pics[1],
3394 sizeof(struct kvm_pic_state));
3395 break;
3396 case KVM_IRQCHIP_IOAPIC:
eba0226b 3397 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3398 break;
3399 default:
3400 r = -EINVAL;
3401 break;
3402 }
3403 return r;
3404}
3405
3406static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3407{
3408 int r;
3409
3410 r = 0;
3411 switch (chip->chip_id) {
3412 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3413 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3414 memcpy(&pic_irqchip(kvm)->pics[0],
3415 &chip->chip.pic,
3416 sizeof(struct kvm_pic_state));
f4f51050 3417 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3418 break;
3419 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3420 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3421 memcpy(&pic_irqchip(kvm)->pics[1],
3422 &chip->chip.pic,
3423 sizeof(struct kvm_pic_state));
f4f51050 3424 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3425 break;
3426 case KVM_IRQCHIP_IOAPIC:
eba0226b 3427 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3428 break;
3429 default:
3430 r = -EINVAL;
3431 break;
3432 }
3433 kvm_pic_update_irq(pic_irqchip(kvm));
3434 return r;
3435}
3436
e0f63cb9
SY		 3437static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3438{
3439 int r = 0;
3440
894a9c55 3441 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3442 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3443 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3444 return r;
3445}
3446
3447static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3448{
3449 int r = 0;
3450
894a9c55 3451 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3452 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3453 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3454 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3455 return r;
3456}
3457
3458static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3459{
3460 int r = 0;
3461
3462 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3463 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3464 sizeof(ps->channels));
3465 ps->flags = kvm->arch.vpit->pit_state.flags;
3466 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3467 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3468 return r;
3469}
3470
3471static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3472{
3473 int r = 0, start = 0;
3474 u32 prev_legacy, cur_legacy;
3475 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3476 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3477 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3478 if (!prev_legacy && cur_legacy)
3479 start = 1;
3480 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3481 sizeof(kvm->arch.vpit->pit_state.channels));
3482 kvm->arch.vpit->pit_state.flags = ps->flags;
3483 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3484 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3485 return r;
3486}
3487
52d939a0
MT		 3488static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3489 struct kvm_reinject_control *control)
3490{
3491 if (!kvm->arch.vpit)
3492 return -ENXIO;
894a9c55 3493 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3494 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3495 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3496 return 0;
3497}
3498
95d4c16c 3499/**
60c34612
TY		 3500 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3501 * @kvm: kvm instance
3502 * @log: slot id and address to which we copy the log
95d4c16c 3503 *
e108ff2f
PB		 3504 * Steps 1-4 below provide general overview of dirty page logging. See
3505 * kvm_get_dirty_log_protect() function description for additional details.
3506 *
3507 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3508 * always flush the TLB (step 4) even if previous step failed and the dirty
3509 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3510 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3511 * writes will be marked dirty for next log read.
95d4c16c 3512 *
60c34612
TY		 3513 * 1. Take a snapshot of the bit and clear it if needed.
3514 * 2. Write protect the corresponding page.
e108ff2f
PB		 3515 * 3. Copy the snapshot to the userspace.
3516 * 4. Flush TLB's if needed.
5bb064dc 3517 */
60c34612 3518int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3519{
60c34612 3520 bool is_dirty = false;
e108ff2f 3521 int r;
5bb064dc 3522
79fac95e 3523 mutex_lock(&kvm->slots_lock);
5bb064dc 3524
88178fd4
KH		 3525 /*
3526 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3527 */
3528 if (kvm_x86_ops->flush_log_dirty)
3529 kvm_x86_ops->flush_log_dirty(kvm);
3530
e108ff2f 3531 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3532
3533 /*
3534 * All the TLBs can be flushed out of mmu lock, see the comments in
3535 * kvm_mmu_slot_remove_write_access().
3536 */
e108ff2f 3537 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3538 if (is_dirty)
3539 kvm_flush_remote_tlbs(kvm);
3540
79fac95e 3541 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3542 return r;
3543}
3544
aa2fbe6d
YZ		 3545int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3546 bool line_status)
23d43cf9
CD		 3547{
3548 if (!irqchip_in_kernel(kvm))
3549 return -ENXIO;
3550
3551 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3552 irq_event->irq, irq_event->level,
3553 line_status);
23d43cf9
CD		 3554 return 0;
3555}
3556
90de4a18
NA		 3557static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3558 struct kvm_enable_cap *cap)
3559{
3560 int r;
3561
3562 if (cap->flags)
3563 return -EINVAL;
3564
3565 switch (cap->cap) {
3566 case KVM_CAP_DISABLE_QUIRKS:
3567 kvm->arch.disabled_quirks = cap->args[0];
3568 r = 0;
3569 break;
3570 default:
3571 r = -EINVAL;
3572 break;
3573 }
3574 return r;
3575}
3576
1fe779f8
CO		 3577long kvm_arch_vm_ioctl(struct file *filp,
3578 unsigned int ioctl, unsigned long arg)
3579{
3580 struct kvm *kvm = filp->private_data;
3581 void __user *argp = (void __user *)arg;
367e1319 3582 int r = -ENOTTY;
f0d66275
DH		 3583 /*
3584 * This union makes it completely explicit to gcc-3.x
3585 * that these two variables' stack usage should be
3586 * combined, not added together.
3587 */
3588 union {
3589 struct kvm_pit_state ps;
e9f42757 3590 struct kvm_pit_state2 ps2;
c5ff41ce 3591 struct kvm_pit_config pit_config;
f0d66275 3592 } u;
1fe779f8
CO		 3593
3594 switch (ioctl) {
3595 case KVM_SET_TSS_ADDR:
3596 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3597 break;
b927a3ce
SY		 3598 case KVM_SET_IDENTITY_MAP_ADDR: {
3599 u64 ident_addr;
3600
3601 r = -EFAULT;
3602 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3603 goto out;
3604 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3605 break;
3606 }
1fe779f8
CO		 3607 case KVM_SET_NR_MMU_PAGES:
3608 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3609 break;
3610 case KVM_GET_NR_MMU_PAGES:
3611 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3612 break;
3ddea128
MT		 3613 case KVM_CREATE_IRQCHIP: {
3614 struct kvm_pic *vpic;
3615
3616 mutex_lock(&kvm->lock);
3617 r = -EEXIST;
3618 if (kvm->arch.vpic)
3619 goto create_irqchip_unlock;
3e515705
AK		 3620 r = -EINVAL;
3621 if (atomic_read(&kvm->online_vcpus))
3622 goto create_irqchip_unlock;
1fe779f8 3623 r = -ENOMEM;
3ddea128
MT		 3624 vpic = kvm_create_pic(kvm);
3625 if (vpic) {
1fe779f8
CO		 3626 r = kvm_ioapic_init(kvm);
3627 if (r) {
175504cd 3628 mutex_lock(&kvm->slots_lock);
72bb2fcd 3629 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3630 &vpic->dev_master);
3631 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3632 &vpic->dev_slave);
3633 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3634 &vpic->dev_eclr);
175504cd 3635 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3636 kfree(vpic);
3637 goto create_irqchip_unlock;
1fe779f8
CO		 3638 }
3639 } else
3ddea128
MT		 3640 goto create_irqchip_unlock;
3641 smp_wmb();
3642 kvm->arch.vpic = vpic;
3643 smp_wmb();
399ec807
AK		 3644 r = kvm_setup_default_irq_routing(kvm);
3645 if (r) {
175504cd 3646 mutex_lock(&kvm->slots_lock);
3ddea128 3647 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3648 kvm_ioapic_destroy(kvm);
3649 kvm_destroy_pic(kvm);
3ddea128 3650 mutex_unlock(&kvm->irq_lock);
175504cd 3651 mutex_unlock(&kvm->slots_lock);
399ec807 3652 }
3ddea128
MT		 3653 create_irqchip_unlock:
3654 mutex_unlock(&kvm->lock);
1fe779f8 3655 break;
3ddea128 3656 }
7837699f 3657 case KVM_CREATE_PIT:
c5ff41ce
JK		 3658 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3659 goto create_pit;
3660 case KVM_CREATE_PIT2:
3661 r = -EFAULT;
3662 if (copy_from_user(&u.pit_config, argp,
3663 sizeof(struct kvm_pit_config)))
3664 goto out;
3665 create_pit:
79fac95e 3666 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3667 r = -EEXIST;
3668 if (kvm->arch.vpit)
3669 goto create_pit_unlock;
7837699f 3670 r = -ENOMEM;
c5ff41ce 3671 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3672 if (kvm->arch.vpit)
3673 r = 0;
269e05e4 3674 create_pit_unlock:
79fac95e 3675 mutex_unlock(&kvm->slots_lock);
7837699f 3676 break;
1fe779f8
CO		 3677 case KVM_GET_IRQCHIP: {
3678 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3679 struct kvm_irqchip *chip;
1fe779f8 3680
ff5c2c03
SL		 3681 chip = memdup_user(argp, sizeof(*chip));
3682 if (IS_ERR(chip)) {
3683 r = PTR_ERR(chip);
1fe779f8 3684 goto out;
ff5c2c03
SL		 3685 }
3686
1fe779f8
CO		 3687 r = -ENXIO;
3688 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3689 goto get_irqchip_out;
3690 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3691 if (r)
f0d66275 3692 goto get_irqchip_out;
1fe779f8 3693 r = -EFAULT;
f0d66275
DH		 3694 if (copy_to_user(argp, chip, sizeof *chip))
3695 goto get_irqchip_out;
1fe779f8 3696 r = 0;
f0d66275
DH		 3697 get_irqchip_out:
3698 kfree(chip);
1fe779f8
CO		 3699 break;
3700 }
3701 case KVM_SET_IRQCHIP: {
3702 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3703 struct kvm_irqchip *chip;
1fe779f8 3704
ff5c2c03
SL		 3705 chip = memdup_user(argp, sizeof(*chip));
3706 if (IS_ERR(chip)) {
3707 r = PTR_ERR(chip);
1fe779f8 3708 goto out;
ff5c2c03
SL		 3709 }
3710
1fe779f8
CO		 3711 r = -ENXIO;
3712 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3713 goto set_irqchip_out;
3714 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3715 if (r)
f0d66275 3716 goto set_irqchip_out;
1fe779f8 3717 r = 0;
f0d66275
DH		 3718 set_irqchip_out:
3719 kfree(chip);
1fe779f8
CO		 3720 break;
3721 }
e0f63cb9 3722 case KVM_GET_PIT: {
e0f63cb9 3723 r = -EFAULT;
f0d66275 3724 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3725 goto out;
3726 r = -ENXIO;
3727 if (!kvm->arch.vpit)
3728 goto out;
f0d66275 3729 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3730 if (r)
3731 goto out;
3732 r = -EFAULT;
f0d66275 3733 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3734 goto out;
3735 r = 0;
3736 break;
3737 }
3738 case KVM_SET_PIT: {
e0f63cb9 3739 r = -EFAULT;
f0d66275 3740 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3741 goto out;
3742 r = -ENXIO;
3743 if (!kvm->arch.vpit)
3744 goto out;
f0d66275 3745 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3746 break;
3747 }
e9f42757
BK		 3748 case KVM_GET_PIT2: {
3749 r = -ENXIO;
3750 if (!kvm->arch.vpit)
3751 goto out;
3752 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3753 if (r)
3754 goto out;
3755 r = -EFAULT;
3756 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3757 goto out;
3758 r = 0;
3759 break;
3760 }
3761 case KVM_SET_PIT2: {
3762 r = -EFAULT;
3763 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3764 goto out;
3765 r = -ENXIO;
3766 if (!kvm->arch.vpit)
3767 goto out;
3768 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3769 break;
3770 }
52d939a0
MT		 3771 case KVM_REINJECT_CONTROL: {
3772 struct kvm_reinject_control control;
3773 r = -EFAULT;
3774 if (copy_from_user(&control, argp, sizeof(control)))
3775 goto out;
3776 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3777 break;
3778 }
d71ba788
PB		 3779 case KVM_SET_BOOT_CPU_ID:
3780 r = 0;
3781 mutex_lock(&kvm->lock);
3782 if (atomic_read(&kvm->online_vcpus) != 0)
3783 r = -EBUSY;
3784 else
3785 kvm->arch.bsp_vcpu_id = arg;
3786 mutex_unlock(&kvm->lock);
3787 break;
ffde22ac
ES		 3788 case KVM_XEN_HVM_CONFIG: {
3789 r = -EFAULT;
3790 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3791 sizeof(struct kvm_xen_hvm_config)))
3792 goto out;
3793 r = -EINVAL;
3794 if (kvm->arch.xen_hvm_config.flags)
3795 goto out;
3796 r = 0;
3797 break;
3798 }
afbcf7ab 3799 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3800 struct kvm_clock_data user_ns;
3801 u64 now_ns;
3802 s64 delta;
3803
3804 r = -EFAULT;
3805 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3806 goto out;
3807
3808 r = -EINVAL;
3809 if (user_ns.flags)
3810 goto out;
3811
3812 r = 0;
395c6b0a 3813 local_irq_disable();
759379dd 3814 now_ns = get_kernel_ns();
afbcf7ab 3815 delta = user_ns.clock - now_ns;
395c6b0a 3816 local_irq_enable();
afbcf7ab 3817 kvm->arch.kvmclock_offset = delta;
2e762ff7 3818 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3819 break;
3820 }
3821 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3822 struct kvm_clock_data user_ns;
3823 u64 now_ns;
3824
395c6b0a 3825 local_irq_disable();
759379dd 3826 now_ns = get_kernel_ns();
afbcf7ab 3827 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3828 local_irq_enable();
afbcf7ab 3829 user_ns.flags = 0;
97e69aa6 3830 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3831
3832 r = -EFAULT;
3833 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3834 goto out;
3835 r = 0;
3836 break;
3837 }
90de4a18
NA		 3838 case KVM_ENABLE_CAP: {
3839 struct kvm_enable_cap cap;
afbcf7ab 3840
90de4a18
NA		 3841 r = -EFAULT;
3842 if (copy_from_user(&cap, argp, sizeof(cap)))
3843 goto out;
3844 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3845 break;
3846 }
1fe779f8 3847 default:
c274e03a 3848 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3849 }
3850out:
3851 return r;
3852}
3853
a16b043c 3854static void kvm_init_msr_list(void)
043405e1
CO		 3855{
3856 u32 dummy[2];
3857 unsigned i, j;
3858
62ef68bb 3859 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3860 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3861 continue;
93c4adc7
PB		 3862
3863 /*
3864 * Even MSRs that are valid in the host may not be exposed
3865 * to the guests in some cases. We could work around this
3866 * in VMX with the generic MSR save/load machinery, but it
3867 * is not really worthwhile since it will really only
3868 * happen with nested virtualization.
3869 */
3870 switch (msrs_to_save[i]) {
3871 case MSR_IA32_BNDCFGS:
3872 if (!kvm_x86_ops->mpx_supported())
3873 continue;
3874 break;
3875 default:
3876 break;
3877 }
3878
043405e1
CO		 3879 if (j < i)
3880 msrs_to_save[j] = msrs_to_save[i];
3881 j++;
3882 }
3883 num_msrs_to_save = j;
62ef68bb
PB		 3884
3885 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3886 switch (emulated_msrs[i]) {
6d396b55
PB		 3887 case MSR_IA32_SMBASE:
3888 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3889 continue;
3890 break;
62ef68bb
PB		 3891 default:
3892 break;
3893 }
3894
3895 if (j < i)
3896 emulated_msrs[j] = emulated_msrs[i];
3897 j++;
3898 }
3899 num_emulated_msrs = j;
043405e1
CO		 3900}
3901
bda9020e
MT		 3902static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3903 const void *v)
bbd9b64e 3904{
70252a10
AK		 3905 int handled = 0;
3906 int n;
3907
3908 do {
3909 n = min(len, 8);
3910 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3911 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3912 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3913 break;
3914 handled += n;
3915 addr += n;
3916 len -= n;
3917 v += n;
3918 } while (len);
bbd9b64e 3919
70252a10 3920 return handled;
bbd9b64e
CO		 3921}
3922
bda9020e 3923static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3924{
70252a10
AK		 3925 int handled = 0;
3926 int n;
3927
3928 do {
3929 n = min(len, 8);
3930 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3931 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3932 addr, n, v))
3933 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3934 break;
3935 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3936 handled += n;
3937 addr += n;
3938 len -= n;
3939 v += n;
3940 } while (len);
bbd9b64e 3941
70252a10 3942 return handled;
bbd9b64e
CO		 3943}
3944
2dafc6c2
GN		 3945static void kvm_set_segment(struct kvm_vcpu *vcpu,
3946 struct kvm_segment *var, int seg)
3947{
3948 kvm_x86_ops->set_segment(vcpu, var, seg);
3949}
3950
3951void kvm_get_segment(struct kvm_vcpu *vcpu,
3952 struct kvm_segment *var, int seg)
3953{
3954 kvm_x86_ops->get_segment(vcpu, var, seg);
3955}
3956
54987b7a
PB		 3957gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3958 struct x86_exception *exception)
02f59dc9
JR		 3959{
3960 gpa_t t_gpa;
02f59dc9
JR		 3961
3962 BUG_ON(!mmu_is_nested(vcpu));
3963
3964 /* NPT walks are always user-walks */
3965 access |= PFERR_USER_MASK;
54987b7a 3966 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3967
3968 return t_gpa;
3969}
3970
ab9ae313
AK		 3971gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3972 struct x86_exception *exception)
1871c602
GN		 3973{
3974 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3975 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3976}
3977
ab9ae313
AK		 3978 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3979 struct x86_exception *exception)
1871c602
GN		 3980{
3981 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3982 access |= PFERR_FETCH_MASK;
ab9ae313 3983 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3984}
3985
ab9ae313
AK		 3986gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3987 struct x86_exception *exception)
1871c602
GN		 3988{
3989 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3990 access |= PFERR_WRITE_MASK;
ab9ae313 3991 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3992}
3993
3994/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3995gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3996 struct x86_exception *exception)
1871c602 3997{
ab9ae313 3998 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3999}
4000
4001static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4002 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4003 struct x86_exception *exception)
bbd9b64e
CO		 4004{
4005 void *data = val;
10589a46 4006 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4007
4008 while (bytes) {
14dfe855 4009 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4010 exception);
bbd9b64e 4011 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4012 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4013 int ret;
4014
bcc55cba 4015 if (gpa == UNMAPPED_GVA)
ab9ae313 4016 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4017 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4018 offset, toread);
10589a46 4019 if (ret < 0) {
c3cd7ffa 4020 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4021 goto out;
4022 }
bbd9b64e 4023
77c2002e
IE		 4024 bytes -= toread;
4025 data += toread;
4026 addr += toread;
bbd9b64e 4027 }
10589a46 4028out:
10589a46 4029 return r;
bbd9b64e 4030}
77c2002e 4031
1871c602 4032/* used for instruction fetching */
0f65dd70
AK		 4033static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4034 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4035 struct x86_exception *exception)
1871c602 4036{
0f65dd70 4037 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4038 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4039 unsigned offset;
4040 int ret;
0f65dd70 4041
44583cba
PB		 4042 /* Inline kvm_read_guest_virt_helper for speed. */
4043 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4044 exception);
4045 if (unlikely(gpa == UNMAPPED_GVA))
4046 return X86EMUL_PROPAGATE_FAULT;
4047
4048 offset = addr & (PAGE_SIZE-1);
4049 if (WARN_ON(offset + bytes > PAGE_SIZE))
4050 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4051 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4052 offset, bytes);
44583cba
PB		 4053 if (unlikely(ret < 0))
4054 return X86EMUL_IO_NEEDED;
4055
4056 return X86EMUL_CONTINUE;
1871c602
GN		 4057}
4058
064aea77 4059int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4060 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4061 struct x86_exception *exception)
1871c602 4062{
0f65dd70 4063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4064 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4065
1871c602 4066 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4067 exception);
1871c602 4068}
064aea77 4069EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4070
0f65dd70
AK		 4071static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4072 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4073 struct x86_exception *exception)
1871c602 4074{
0f65dd70 4075 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4076 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4077}
4078
6a4d7550 4079int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4080 gva_t addr, void *val,
2dafc6c2 4081 unsigned int bytes,
bcc55cba 4082 struct x86_exception *exception)
77c2002e 4083{
0f65dd70 4084 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4085 void *data = val;
4086 int r = X86EMUL_CONTINUE;
4087
4088 while (bytes) {
14dfe855
JR		 4089 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4090 PFERR_WRITE_MASK,
ab9ae313 4091 exception);
77c2002e
IE		 4092 unsigned offset = addr & (PAGE_SIZE-1);
4093 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4094 int ret;
4095
bcc55cba 4096 if (gpa == UNMAPPED_GVA)
ab9ae313 4097 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4098 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4099 if (ret < 0) {
c3cd7ffa 4100 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4101 goto out;
4102 }
4103
4104 bytes -= towrite;
4105 data += towrite;
4106 addr += towrite;
4107 }
4108out:
4109 return r;
4110}
6a4d7550 4111EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4112
af7cc7d1
XG		 4113static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4114 gpa_t *gpa, struct x86_exception *exception,
4115 bool write)
4116{
97d64b78
AK		 4117 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4118 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4119
97d64b78 4120 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4121 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4122 vcpu->arch.access, access)) {
bebb106a
XG		 4123 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4124 (gva & (PAGE_SIZE - 1));
4f022648 4125 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4126 return 1;
4127 }
4128
af7cc7d1
XG		 4129 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4130
4131 if (*gpa == UNMAPPED_GVA)
4132 return -1;
4133
4134 /* For APIC access vmexit */
4135 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4136 return 1;
4137
4f022648
XG		 4138 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4139 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4140 return 1;
4f022648 4141 }
bebb106a 4142
af7cc7d1
XG		 4143 return 0;
4144}
4145
3200f405 4146int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4147 const void *val, int bytes)
bbd9b64e
CO		 4148{
4149 int ret;
4150
54bf36aa 4151 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4152 if (ret < 0)
bbd9b64e 4153 return 0;
f57f2ef5 4154 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4155 return 1;
4156}
4157
77d197b2
XG		 4158struct read_write_emulator_ops {
4159 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4160 int bytes);
4161 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4162 void *val, int bytes);
4163 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4164 int bytes, void *val);
4165 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4166 void *val, int bytes);
4167 bool write;
4168};
4169
4170static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4171{
4172 if (vcpu->mmio_read_completed) {
77d197b2 4173 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4174 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4175 vcpu->mmio_read_completed = 0;
4176 return 1;
4177 }
4178
4179 return 0;
4180}
4181
4182static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4183 void *val, int bytes)
4184{
54bf36aa 4185 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4186}
4187
4188static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4189 void *val, int bytes)
4190{
4191 return emulator_write_phys(vcpu, gpa, val, bytes);
4192}
4193
4194static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4195{
4196 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4197 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4198}
4199
4200static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4201 void *val, int bytes)
4202{
4203 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4204 return X86EMUL_IO_NEEDED;
4205}
4206
4207static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4208 void *val, int bytes)
4209{
f78146b0
AK		 4210 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4211
87da7e66 4212 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4213 return X86EMUL_CONTINUE;
4214}
4215
0fbe9b0b 4216static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4217 .read_write_prepare = read_prepare,
4218 .read_write_emulate = read_emulate,
4219 .read_write_mmio = vcpu_mmio_read,
4220 .read_write_exit_mmio = read_exit_mmio,
4221};
4222
0fbe9b0b 4223static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4224 .read_write_emulate = write_emulate,
4225 .read_write_mmio = write_mmio,
4226 .read_write_exit_mmio = write_exit_mmio,
4227 .write = true,
4228};
4229
22388a3c
XG		 4230static int emulator_read_write_onepage(unsigned long addr, void *val,
4231 unsigned int bytes,
4232 struct x86_exception *exception,
4233 struct kvm_vcpu *vcpu,
0fbe9b0b 4234 const struct read_write_emulator_ops *ops)
bbd9b64e 4235{
af7cc7d1
XG		 4236 gpa_t gpa;
4237 int handled, ret;
22388a3c 4238 bool write = ops->write;
f78146b0 4239 struct kvm_mmio_fragment *frag;
10589a46 4240
22388a3c 4241 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4242
af7cc7d1 4243 if (ret < 0)
bbd9b64e 4244 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4245
4246 /* For APIC access vmexit */
af7cc7d1 4247 if (ret)
bbd9b64e
CO		 4248 goto mmio;
4249
22388a3c 4250 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4251 return X86EMUL_CONTINUE;
4252
4253mmio:
4254 /*
4255 * Is this MMIO handled locally?
4256 */
22388a3c 4257 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4258 if (handled == bytes)
bbd9b64e 4259 return X86EMUL_CONTINUE;
bbd9b64e 4260
70252a10
AK		 4261 gpa += handled;
4262 bytes -= handled;
4263 val += handled;
4264
87da7e66
XG		 4265 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4266 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4267 frag->gpa = gpa;
4268 frag->data = val;
4269 frag->len = bytes;
f78146b0 4270 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4271}
4272
52eb5a6d
XL		 4273static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4274 unsigned long addr,
22388a3c
XG		 4275 void *val, unsigned int bytes,
4276 struct x86_exception *exception,
0fbe9b0b 4277 const struct read_write_emulator_ops *ops)
bbd9b64e 4278{
0f65dd70 4279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4280 gpa_t gpa;
4281 int rc;
4282
4283 if (ops->read_write_prepare &&
4284 ops->read_write_prepare(vcpu, val, bytes))
4285 return X86EMUL_CONTINUE;
4286
4287 vcpu->mmio_nr_fragments = 0;
0f65dd70 4288
bbd9b64e
CO		 4289 /* Crossing a page boundary? */
4290 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4291 int now;
bbd9b64e
CO		 4292
4293 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4294 rc = emulator_read_write_onepage(addr, val, now, exception,
4295 vcpu, ops);
4296
bbd9b64e
CO		 4297 if (rc != X86EMUL_CONTINUE)
4298 return rc;
4299 addr += now;
bac15531
NA		 4300 if (ctxt->mode != X86EMUL_MODE_PROT64)
4301 addr = (u32)addr;
bbd9b64e
CO		 4302 val += now;
4303 bytes -= now;
4304 }
22388a3c 4305
f78146b0
AK		 4306 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4307 vcpu, ops);
4308 if (rc != X86EMUL_CONTINUE)
4309 return rc;
4310
4311 if (!vcpu->mmio_nr_fragments)
4312 return rc;
4313
4314 gpa = vcpu->mmio_fragments[0].gpa;
4315
4316 vcpu->mmio_needed = 1;
4317 vcpu->mmio_cur_fragment = 0;
4318
87da7e66 4319 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4320 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4321 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4322 vcpu->run->mmio.phys_addr = gpa;
4323
4324 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4325}
4326
4327static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4328 unsigned long addr,
4329 void *val,
4330 unsigned int bytes,
4331 struct x86_exception *exception)
4332{
4333 return emulator_read_write(ctxt, addr, val, bytes,
4334 exception, &read_emultor);
4335}
4336
52eb5a6d 4337static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4338 unsigned long addr,
4339 const void *val,
4340 unsigned int bytes,
4341 struct x86_exception *exception)
4342{
4343 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4344 exception, &write_emultor);
bbd9b64e 4345}
bbd9b64e 4346
daea3e73
AK		 4347#define CMPXCHG_TYPE(t, ptr, old, new) \
4348 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4349
4350#ifdef CONFIG_X86_64
4351# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4352#else
4353# define CMPXCHG64(ptr, old, new) \
9749a6c0 4354 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4355#endif
4356
0f65dd70
AK		 4357static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4358 unsigned long addr,
bbd9b64e
CO		 4359 const void *old,
4360 const void *new,
4361 unsigned int bytes,
0f65dd70 4362 struct x86_exception *exception)
bbd9b64e 4363{
0f65dd70 4364 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4365 gpa_t gpa;
4366 struct page *page;
4367 char *kaddr;
4368 bool exchanged;
2bacc55c 4369
daea3e73
AK		 4370 /* guests cmpxchg8b have to be emulated atomically */
4371 if (bytes > 8 || (bytes & (bytes - 1)))
4372 goto emul_write;
10589a46 4373
daea3e73 4374 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4375
daea3e73
AK		 4376 if (gpa == UNMAPPED_GVA ||
4377 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4378 goto emul_write;
2bacc55c 4379
daea3e73
AK		 4380 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4381 goto emul_write;
72dc67a6 4382
54bf36aa 4383 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4384 if (is_error_page(page))
c19b8bd6 4385 goto emul_write;
72dc67a6 4386
8fd75e12 4387 kaddr = kmap_atomic(page);
daea3e73
AK		 4388 kaddr += offset_in_page(gpa);
4389 switch (bytes) {
4390 case 1:
4391 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4392 break;
4393 case 2:
4394 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4395 break;
4396 case 4:
4397 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4398 break;
4399 case 8:
4400 exchanged = CMPXCHG64(kaddr, old, new);
4401 break;
4402 default:
4403 BUG();
2bacc55c 4404 }
8fd75e12 4405 kunmap_atomic(kaddr);
daea3e73
AK		 4406 kvm_release_page_dirty(page);
4407
4408 if (!exchanged)
4409 return X86EMUL_CMPXCHG_FAILED;
4410
54bf36aa 4411 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4412 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4413
4414 return X86EMUL_CONTINUE;
4a5f48f6 4415
3200f405 4416emul_write:
daea3e73 4417 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4418
0f65dd70 4419 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4420}
4421
cf8f70bf
GN		 4422static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4423{
4424 /* TODO: String I/O for in kernel device */
4425 int r;
4426
4427 if (vcpu->arch.pio.in)
e32edf4f 4428 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4429 vcpu->arch.pio.size, pd);
4430 else
e32edf4f 4431 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4432 vcpu->arch.pio.port, vcpu->arch.pio.size,
4433 pd);
4434 return r;
4435}
4436
6f6fbe98
XG		 4437static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4438 unsigned short port, void *val,
4439 unsigned int count, bool in)
cf8f70bf 4440{
cf8f70bf 4441 vcpu->arch.pio.port = port;
6f6fbe98 4442 vcpu->arch.pio.in = in;
7972995b 4443 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4444 vcpu->arch.pio.size = size;
4445
4446 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4447 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4448 return 1;
4449 }
4450
4451 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4452 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4453 vcpu->run->io.size = size;
4454 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4455 vcpu->run->io.count = count;
4456 vcpu->run->io.port = port;
4457
4458 return 0;
4459}
4460
6f6fbe98
XG		 4461static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4462 int size, unsigned short port, void *val,
4463 unsigned int count)
cf8f70bf 4464{
ca1d4a9e 4465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4466 int ret;
ca1d4a9e 4467
6f6fbe98
XG		 4468 if (vcpu->arch.pio.count)
4469 goto data_avail;
cf8f70bf 4470
6f6fbe98
XG		 4471 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4472 if (ret) {
4473data_avail:
4474 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4475 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4476 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4477 return 1;
4478 }
4479
cf8f70bf
GN		 4480 return 0;
4481}
4482
6f6fbe98
XG		 4483static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4484 int size, unsigned short port,
4485 const void *val, unsigned int count)
4486{
4487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4488
4489 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4490 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4491 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4492}
4493
bbd9b64e
CO		 4494static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4495{
4496 return kvm_x86_ops->get_segment_base(vcpu, seg);
4497}
4498
3cb16fe7 4499static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4500{
3cb16fe7 4501 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4502}
4503
5cb56059 4504int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4505{
4506 if (!need_emulate_wbinvd(vcpu))
4507 return X86EMUL_CONTINUE;
4508
4509 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4510 int cpu = get_cpu();
4511
4512 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4513 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4514 wbinvd_ipi, NULL, 1);
2eec7343 4515 put_cpu();
f5f48ee1 4516 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4517 } else
4518 wbinvd();
f5f48ee1
SY		 4519 return X86EMUL_CONTINUE;
4520}
5cb56059
JS		 4521
4522int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4523{
4524 kvm_x86_ops->skip_emulated_instruction(vcpu);
4525 return kvm_emulate_wbinvd_noskip(vcpu);
4526}
f5f48ee1
SY		 4527EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4528
5cb56059
JS		 4529
4530
bcaf5cc5
AK		 4531static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4532{
5cb56059 4533 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4534}
4535
52eb5a6d
XL		 4536static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4537 unsigned long *dest)
bbd9b64e 4538{
16f8a6f9 4539 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4540}
4541
52eb5a6d
XL		 4542static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4543 unsigned long value)
bbd9b64e 4544{
338dbc97 4545
717746e3 4546 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4547}
4548
52a46617 4549static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4550{
52a46617 4551 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4552}
4553
717746e3 4554static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4555{
717746e3 4556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4557 unsigned long value;
4558
4559 switch (cr) {
4560 case 0:
4561 value = kvm_read_cr0(vcpu);
4562 break;
4563 case 2:
4564 value = vcpu->arch.cr2;
4565 break;
4566 case 3:
9f8fe504 4567 value = kvm_read_cr3(vcpu);
52a46617
GN		 4568 break;
4569 case 4:
4570 value = kvm_read_cr4(vcpu);
4571 break;
4572 case 8:
4573 value = kvm_get_cr8(vcpu);
4574 break;
4575 default:
a737f256 4576 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4577 return 0;
4578 }
4579
4580 return value;
4581}
4582
717746e3 4583static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4584{
717746e3 4585 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4586 int res = 0;
4587
52a46617
GN		 4588 switch (cr) {
4589 case 0:
49a9b07e 4590 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4591 break;
4592 case 2:
4593 vcpu->arch.cr2 = val;
4594 break;
4595 case 3:
2390218b 4596 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4597 break;
4598 case 4:
a83b29c6 4599 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4600 break;
4601 case 8:
eea1cff9 4602 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4603 break;
4604 default:
a737f256 4605 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4606 res = -1;
52a46617 4607 }
0f12244f
GN		 4608
4609 return res;
52a46617
GN		 4610}
4611
717746e3 4612static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4613{
717746e3 4614 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4615}
4616
4bff1e86 4617static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4618{
4bff1e86 4619 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4620}
4621
4bff1e86 4622static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4623{
4bff1e86 4624 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4625}
4626
1ac9d0cf
AK		 4627static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4628{
4629 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4630}
4631
4632static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4633{
4634 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4635}
4636
4bff1e86
AK		 4637static unsigned long emulator_get_cached_segment_base(
4638 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4639{
4bff1e86 4640 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4641}
4642
1aa36616
AK		 4643static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4644 struct desc_struct *desc, u32 *base3,
4645 int seg)
2dafc6c2
GN		 4646{
4647 struct kvm_segment var;
4648
4bff1e86 4649 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4650 *selector = var.selector;
2dafc6c2 4651
378a8b09
GN		 4652 if (var.unusable) {
4653 memset(desc, 0, sizeof(*desc));
2dafc6c2 4654 return false;
378a8b09 4655 }
2dafc6c2
GN		 4656
4657 if (var.g)
4658 var.limit >>= 12;
4659 set_desc_limit(desc, var.limit);
4660 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4661#ifdef CONFIG_X86_64
4662 if (base3)
4663 *base3 = var.base >> 32;
4664#endif
2dafc6c2
GN		 4665 desc->type = var.type;
4666 desc->s = var.s;
4667 desc->dpl = var.dpl;
4668 desc->p = var.present;
4669 desc->avl = var.avl;
4670 desc->l = var.l;
4671 desc->d = var.db;
4672 desc->g = var.g;
4673
4674 return true;
4675}
4676
1aa36616
AK		 4677static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4678 struct desc_struct *desc, u32 base3,
4679 int seg)
2dafc6c2 4680{
4bff1e86 4681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4682 struct kvm_segment var;
4683
1aa36616 4684 var.selector = selector;
2dafc6c2 4685 var.base = get_desc_base(desc);
5601d05b
GN		 4686#ifdef CONFIG_X86_64
4687 var.base |= ((u64)base3) << 32;
4688#endif
2dafc6c2
GN		 4689 var.limit = get_desc_limit(desc);
4690 if (desc->g)
4691 var.limit = (var.limit << 12) | 0xfff;
4692 var.type = desc->type;
2dafc6c2
GN		 4693 var.dpl = desc->dpl;
4694 var.db = desc->d;
4695 var.s = desc->s;
4696 var.l = desc->l;
4697 var.g = desc->g;
4698 var.avl = desc->avl;
4699 var.present = desc->p;
4700 var.unusable = !var.present;
4701 var.padding = 0;
4702
4703 kvm_set_segment(vcpu, &var, seg);
4704 return;
4705}
4706
717746e3
AK		 4707static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4708 u32 msr_index, u64 *pdata)
4709{
609e36d3
PB		 4710 struct msr_data msr;
4711 int r;
4712
4713 msr.index = msr_index;
4714 msr.host_initiated = false;
4715 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4716 if (r)
4717 return r;
4718
4719 *pdata = msr.data;
4720 return 0;
717746e3
AK		 4721}
4722
4723static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4724 u32 msr_index, u64 data)
4725{
8fe8ab46
WA		 4726 struct msr_data msr;
4727
4728 msr.data = data;
4729 msr.index = msr_index;
4730 msr.host_initiated = false;
4731 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4732}
4733
64d60670
PB		 4734static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4735{
4736 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4737
4738 return vcpu->arch.smbase;
4739}
4740
4741static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4742{
4743 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4744
4745 vcpu->arch.smbase = smbase;
4746}
4747
67f4d428
NA		 4748static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4749 u32 pmc)
4750{
c6702c9d 4751 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4752}
4753
222d21aa
AK		 4754static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4755 u32 pmc, u64 *pdata)
4756{
c6702c9d 4757 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4758}
4759
6c3287f7
AK		 4760static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4761{
4762 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4763}
4764
5037f6f3
AK		 4765static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4766{
4767 preempt_disable();
5197b808 4768 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4769 /*
4770 * CR0.TS may reference the host fpu state, not the guest fpu state,
4771 * so it may be clear at this point.
4772 */
4773 clts();
4774}
4775
4776static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4777{
4778 preempt_enable();
4779}
4780
2953538e 4781static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4782 struct x86_instruction_info *info,
c4f035c6
AK		 4783 enum x86_intercept_stage stage)
4784{
2953538e 4785 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4786}
4787
0017f93a 4788static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4789 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4790{
0017f93a 4791 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4792}
4793
dd856efa
AK		 4794static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4795{
4796 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4797}
4798
4799static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4800{
4801 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4802}
4803
801806d9
NA		 4804static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4805{
4806 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4807}
4808
0225fb50 4809static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4810 .read_gpr = emulator_read_gpr,
4811 .write_gpr = emulator_write_gpr,
1871c602 4812 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4813 .write_std = kvm_write_guest_virt_system,
1871c602 4814 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4815 .read_emulated = emulator_read_emulated,
4816 .write_emulated = emulator_write_emulated,
4817 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4818 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4819 .pio_in_emulated = emulator_pio_in_emulated,
4820 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4821 .get_segment = emulator_get_segment,
4822 .set_segment = emulator_set_segment,
5951c442 4823 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4824 .get_gdt = emulator_get_gdt,
160ce1f1 4825 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4826 .set_gdt = emulator_set_gdt,
4827 .set_idt = emulator_set_idt,
52a46617
GN		 4828 .get_cr = emulator_get_cr,
4829 .set_cr = emulator_set_cr,
9c537244 4830 .cpl = emulator_get_cpl,
35aa5375
GN		 4831 .get_dr = emulator_get_dr,
4832 .set_dr = emulator_set_dr,
64d60670
PB		 4833 .get_smbase = emulator_get_smbase,
4834 .set_smbase = emulator_set_smbase,
717746e3
AK		 4835 .set_msr = emulator_set_msr,
4836 .get_msr = emulator_get_msr,
67f4d428 4837 .check_pmc = emulator_check_pmc,
222d21aa 4838 .read_pmc = emulator_read_pmc,
6c3287f7 4839 .halt = emulator_halt,
bcaf5cc5 4840 .wbinvd = emulator_wbinvd,
d6aa1000 4841 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4842 .get_fpu = emulator_get_fpu,
4843 .put_fpu = emulator_put_fpu,
c4f035c6 4844 .intercept = emulator_intercept,
bdb42f5a 4845 .get_cpuid = emulator_get_cpuid,
801806d9 4846 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4847};
4848
95cb2295
GN		 4849static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4850{
37ccdcbe 4851 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4852 /*
4853 * an sti; sti; sequence only disable interrupts for the first
4854 * instruction. So, if the last instruction, be it emulated or
4855 * not, left the system with the INT_STI flag enabled, it
4856 * means that the last instruction is an sti. We should not
4857 * leave the flag on in this case. The same goes for mov ss
4858 */
37ccdcbe
PB		 4859 if (int_shadow & mask)
4860 mask = 0;
6addfc42 4861 if (unlikely(int_shadow || mask)) {
95cb2295 4862 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4863 if (!mask)
4864 kvm_make_request(KVM_REQ_EVENT, vcpu);
4865 }
95cb2295
GN		 4866}
4867
ef54bcfe 4868static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4869{
4870 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4871 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4872 return kvm_propagate_fault(vcpu, &ctxt->exception);
4873
4874 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4875 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4876 ctxt->exception.error_code);
54b8486f 4877 else
da9cb575 4878 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4879 return false;
54b8486f
GN		 4880}
4881
8ec4722d
MG		 4882static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4883{
adf52235 4884 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4885 int cs_db, cs_l;
4886
8ec4722d
MG		 4887 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4888
adf52235
TY		 4889 ctxt->eflags = kvm_get_rflags(vcpu);
4890 ctxt->eip = kvm_rip_read(vcpu);
4891 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4892 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4893 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4894 cs_db ? X86EMUL_MODE_PROT32 :
4895 X86EMUL_MODE_PROT16;
a584539b 4896 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4897 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4898 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4899 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4900
dd856efa 4901 init_decode_cache(ctxt);
7ae441ea 4902 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4903}
4904
71f9833b 4905int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4906{
9d74191a 4907 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4908 int ret;
4909
4910 init_emulate_ctxt(vcpu);
4911
9dac77fa
AK		 4912 ctxt->op_bytes = 2;
4913 ctxt->ad_bytes = 2;
4914 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4915 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4916
4917 if (ret != X86EMUL_CONTINUE)
4918 return EMULATE_FAIL;
4919
9dac77fa 4920 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4921 kvm_rip_write(vcpu, ctxt->eip);
4922 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4923
4924 if (irq == NMI_VECTOR)
7460fb4a 4925 vcpu->arch.nmi_pending = 0;
63995653
MG		 4926 else
4927 vcpu->arch.interrupt.pending = false;
4928
4929 return EMULATE_DONE;
4930}
4931EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4932
6d77dbfc
GN		 4933static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4934{
fc3a9157
JR		 4935 int r = EMULATE_DONE;
4936
6d77dbfc
GN		 4937 ++vcpu->stat.insn_emulation_fail;
4938 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4939 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4940 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4941 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4942 vcpu->run->internal.ndata = 0;
4943 r = EMULATE_FAIL;
4944 }
6d77dbfc 4945 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4946
4947 return r;
6d77dbfc
GN		 4948}
4949
93c05d3e 4950static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4951 bool write_fault_to_shadow_pgtable,
4952 int emulation_type)
a6f177ef 4953{
95b3cf69 4954 gpa_t gpa = cr2;
8e3d9d06 4955 pfn_t pfn;
a6f177ef 4956
991eebf9
GN		 4957 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4958 return false;
4959
95b3cf69
XG		 4960 if (!vcpu->arch.mmu.direct_map) {
4961 /*
4962 * Write permission should be allowed since only
4963 * write access need to be emulated.
4964 */
4965 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4966
95b3cf69
XG		 4967 /*
4968 * If the mapping is invalid in guest, let cpu retry
4969 * it to generate fault.
4970 */
4971 if (gpa == UNMAPPED_GVA)
4972 return true;
4973 }
a6f177ef 4974
8e3d9d06
XG		 4975 /*
4976 * Do not retry the unhandleable instruction if it faults on the
4977 * readonly host memory, otherwise it will goto a infinite loop:
4978 * retry instruction -> write #PF -> emulation fail -> retry
4979 * instruction -> ...
4980 */
4981 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4982
4983 /*
4984 * If the instruction failed on the error pfn, it can not be fixed,
4985 * report the error to userspace.
4986 */
4987 if (is_error_noslot_pfn(pfn))
4988 return false;
4989
4990 kvm_release_pfn_clean(pfn);
4991
4992 /* The instructions are well-emulated on direct mmu. */
4993 if (vcpu->arch.mmu.direct_map) {
4994 unsigned int indirect_shadow_pages;
4995
4996 spin_lock(&vcpu->kvm->mmu_lock);
4997 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4998 spin_unlock(&vcpu->kvm->mmu_lock);
4999
5000 if (indirect_shadow_pages)
5001 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5002
a6f177ef 5003 return true;
8e3d9d06 5004 }
a6f177ef 5005
95b3cf69
XG		 5006 /*
5007 * if emulation was due to access to shadowed page table
5008 * and it failed try to unshadow page and re-enter the
5009 * guest to let CPU execute the instruction.
5010 */
5011 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5012
5013 /*
5014 * If the access faults on its page table, it can not
5015 * be fixed by unprotecting shadow page and it should
5016 * be reported to userspace.
5017 */
5018 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5019}
5020
1cb3f3ae
XG		 5021static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5022 unsigned long cr2, int emulation_type)
5023{
5024 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5025 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5026
5027 last_retry_eip = vcpu->arch.last_retry_eip;
5028 last_retry_addr = vcpu->arch.last_retry_addr;
5029
5030 /*
5031 * If the emulation is caused by #PF and it is non-page_table
5032 * writing instruction, it means the VM-EXIT is caused by shadow
5033 * page protected, we can zap the shadow page and retry this
5034 * instruction directly.
5035 *
5036 * Note: if the guest uses a non-page-table modifying instruction
5037 * on the PDE that points to the instruction, then we will unmap
5038 * the instruction and go to an infinite loop. So, we cache the
5039 * last retried eip and the last fault address, if we meet the eip
5040 * and the address again, we can break out of the potential infinite
5041 * loop.
5042 */
5043 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5044
5045 if (!(emulation_type & EMULTYPE_RETRY))
5046 return false;
5047
5048 if (x86_page_table_writing_insn(ctxt))
5049 return false;
5050
5051 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5052 return false;
5053
5054 vcpu->arch.last_retry_eip = ctxt->eip;
5055 vcpu->arch.last_retry_addr = cr2;
5056
5057 if (!vcpu->arch.mmu.direct_map)
5058 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5059
22368028 5060 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5061
5062 return true;
5063}
5064
716d51ab
GN		 5065static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5066static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5067
64d60670 5068static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5069{
64d60670 5070 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5071 /* This is a good place to trace that we are exiting SMM. */
5072 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5073
64d60670
PB		 5074 if (unlikely(vcpu->arch.smi_pending)) {
5075 kvm_make_request(KVM_REQ_SMI, vcpu);
5076 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5077 } else {
5078 /* Process a latched INIT, if any. */
5079 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5080 }
5081 }
699023e2
PB		 5082
5083 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5084}
5085
5086static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5087{
5088 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5089
a584539b 5090 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5091
5092 if (changed & HF_SMM_MASK)
5093 kvm_smm_changed(vcpu);
a584539b
PB		 5094}
5095
4a1e10d5
PB		 5096static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5097 unsigned long *db)
5098{
5099 u32 dr6 = 0;
5100 int i;
5101 u32 enable, rwlen;
5102
5103 enable = dr7;
5104 rwlen = dr7 >> 16;
5105 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5106 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5107 dr6 |= (1 << i);
5108 return dr6;
5109}
5110
6addfc42 5111static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5112{
5113 struct kvm_run *kvm_run = vcpu->run;
5114
5115 /*
6addfc42
PB		 5116 * rflags is the old, "raw" value of the flags. The new value has
5117 * not been saved yet.
663f4c61
PB		 5118 *
5119 * This is correct even for TF set by the guest, because "the
5120 * processor will not generate this exception after the instruction
5121 * that sets the TF flag".
5122 */
663f4c61
PB		 5123 if (unlikely(rflags & X86_EFLAGS_TF)) {
5124 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5125 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5126 DR6_RTM;
663f4c61
PB		 5127 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5128 kvm_run->debug.arch.exception = DB_VECTOR;
5129 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5130 *r = EMULATE_USER_EXIT;
5131 } else {
5132 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5133 /*
5134 * "Certain debug exceptions may clear bit 0-3. The
5135 * remaining contents of the DR6 register are never
5136 * cleared by the processor".
5137 */
5138 vcpu->arch.dr6 &= ~15;
6f43ed01 5139 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5140 kvm_queue_exception(vcpu, DB_VECTOR);
5141 }
5142 }
5143}
5144
4a1e10d5
PB		 5145static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5146{
4a1e10d5
PB		 5147 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5148 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5149 struct kvm_run *kvm_run = vcpu->run;
5150 unsigned long eip = kvm_get_linear_rip(vcpu);
5151 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5152 vcpu->arch.guest_debug_dr7,
5153 vcpu->arch.eff_db);
5154
5155 if (dr6 != 0) {
6f43ed01 5156 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5157 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5158 kvm_run->debug.arch.exception = DB_VECTOR;
5159 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5160 *r = EMULATE_USER_EXIT;
5161 return true;
5162 }
5163 }
5164
4161a569
NA		 5165 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5166 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5167 unsigned long eip = kvm_get_linear_rip(vcpu);
5168 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5169 vcpu->arch.dr7,
5170 vcpu->arch.db);
5171
5172 if (dr6 != 0) {
5173 vcpu->arch.dr6 &= ~15;
6f43ed01 5174 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5175 kvm_queue_exception(vcpu, DB_VECTOR);
5176 *r = EMULATE_DONE;
5177 return true;
5178 }
5179 }
5180
5181 return false;
5182}
5183
51d8b661
AP		 5184int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5185 unsigned long cr2,
dc25e89e
AP		 5186 int emulation_type,
5187 void *insn,
5188 int insn_len)
bbd9b64e 5189{
95cb2295 5190 int r;
9d74191a 5191 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5192 bool writeback = true;
93c05d3e 5193 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5194
93c05d3e
XG		 5195 /*
5196 * Clear write_fault_to_shadow_pgtable here to ensure it is
5197 * never reused.
5198 */
5199 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5200 kvm_clear_exception_queue(vcpu);
8d7d8102 5201
571008da 5202 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5203 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5204
5205 /*
5206 * We will reenter on the same instruction since
5207 * we do not set complete_userspace_io. This does not
5208 * handle watchpoints yet, those would be handled in
5209 * the emulate_ops.
5210 */
5211 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5212 return r;
5213
9d74191a
TY		 5214 ctxt->interruptibility = 0;
5215 ctxt->have_exception = false;
e0ad0b47 5216 ctxt->exception.vector = -1;
9d74191a 5217 ctxt->perm_ok = false;
bbd9b64e 5218
b51e974f 5219 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5220
9d74191a 5221 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5222
e46479f8 5223 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5224 ++vcpu->stat.insn_emulation;
1d2887e2 5225 if (r != EMULATION_OK) {
4005996e
AK		 5226 if (emulation_type & EMULTYPE_TRAP_UD)
5227 return EMULATE_FAIL;
991eebf9
GN		 5228 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5229 emulation_type))
bbd9b64e 5230 return EMULATE_DONE;
6d77dbfc
GN		 5231 if (emulation_type & EMULTYPE_SKIP)
5232 return EMULATE_FAIL;
5233 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5234 }
5235 }
5236
ba8afb6b 5237 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5238 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5239 if (ctxt->eflags & X86_EFLAGS_RF)
5240 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5241 return EMULATE_DONE;
5242 }
5243
1cb3f3ae
XG		 5244 if (retry_instruction(ctxt, cr2, emulation_type))
5245 return EMULATE_DONE;
5246
7ae441ea 5247 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5248 changes registers values during IO operation */
7ae441ea
GN		 5249 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5250 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5251 emulator_invalidate_register_cache(ctxt);
7ae441ea 5252 }
4d2179e1 5253
5cd21917 5254restart:
9d74191a 5255 r = x86_emulate_insn(ctxt);
bbd9b64e 5256
775fde86
JR		 5257 if (r == EMULATION_INTERCEPTED)
5258 return EMULATE_DONE;
5259
d2ddd1c4 5260 if (r == EMULATION_FAILED) {
991eebf9
GN		 5261 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5262 emulation_type))
c3cd7ffa
GN		 5263 return EMULATE_DONE;
5264
6d77dbfc 5265 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5266 }
5267
9d74191a 5268 if (ctxt->have_exception) {
d2ddd1c4 5269 r = EMULATE_DONE;
ef54bcfe
PB		 5270 if (inject_emulated_exception(vcpu))
5271 return r;
d2ddd1c4 5272 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5273 if (!vcpu->arch.pio.in) {
5274 /* FIXME: return into emulator if single-stepping. */
3457e419 5275 vcpu->arch.pio.count = 0;
0912c977 5276 } else {
7ae441ea 5277 writeback = false;
716d51ab
GN		 5278 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5279 }
ac0a48c3 5280 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5281 } else if (vcpu->mmio_needed) {
5282 if (!vcpu->mmio_is_write)
5283 writeback = false;
ac0a48c3 5284 r = EMULATE_USER_EXIT;
716d51ab 5285 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5286 } else if (r == EMULATION_RESTART)
5cd21917 5287 goto restart;
d2ddd1c4
GN		 5288 else
5289 r = EMULATE_DONE;
f850e2e6 5290
7ae441ea 5291 if (writeback) {
6addfc42 5292 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5293 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5294 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5295 if (vcpu->arch.hflags != ctxt->emul_flags)
5296 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5297 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5298 if (r == EMULATE_DONE)
6addfc42 5299 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5300 if (!ctxt->have_exception ||
5301 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5302 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5303
5304 /*
5305 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5306 * do nothing, and it will be requested again as soon as
5307 * the shadow expires. But we still need to check here,
5308 * because POPF has no interrupt shadow.
5309 */
5310 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5311 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5312 } else
5313 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5314
5315 return r;
de7d789a 5316}
51d8b661 5317EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5318
cf8f70bf 5319int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5320{
cf8f70bf 5321 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5322 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5323 size, port, &val, 1);
cf8f70bf 5324 /* do not return to emulator after return from userspace */
7972995b 5325 vcpu->arch.pio.count = 0;
de7d789a
CO		 5326 return ret;
5327}
cf8f70bf 5328EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5329
8cfdc000
ZA		 5330static void tsc_bad(void *info)
5331{
0a3aee0d 5332 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5333}
5334
5335static void tsc_khz_changed(void *data)
c8076604 5336{
8cfdc000
ZA		 5337 struct cpufreq_freqs *freq = data;
5338 unsigned long khz = 0;
5339
5340 if (data)
5341 khz = freq->new;
5342 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5343 khz = cpufreq_quick_get(raw_smp_processor_id());
5344 if (!khz)
5345 khz = tsc_khz;
0a3aee0d 5346 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5347}
5348
c8076604
GH		 5349static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5350 void *data)
5351{
5352 struct cpufreq_freqs *freq = data;
5353 struct kvm *kvm;
5354 struct kvm_vcpu *vcpu;
5355 int i, send_ipi = 0;
5356
8cfdc000
ZA		 5357 /*
5358 * We allow guests to temporarily run on slowing clocks,
5359 * provided we notify them after, or to run on accelerating
5360 * clocks, provided we notify them before. Thus time never
5361 * goes backwards.
5362 *
5363 * However, we have a problem. We can't atomically update
5364 * the frequency of a given CPU from this function; it is
5365 * merely a notifier, which can be called from any CPU.
5366 * Changing the TSC frequency at arbitrary points in time
5367 * requires a recomputation of local variables related to
5368 * the TSC for each VCPU. We must flag these local variables
5369 * to be updated and be sure the update takes place with the
5370 * new frequency before any guests proceed.
5371 *
5372 * Unfortunately, the combination of hotplug CPU and frequency
5373 * change creates an intractable locking scenario; the order
5374 * of when these callouts happen is undefined with respect to
5375 * CPU hotplug, and they can race with each other. As such,
5376 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5377 * undefined; you can actually have a CPU frequency change take
5378 * place in between the computation of X and the setting of the
5379 * variable. To protect against this problem, all updates of
5380 * the per_cpu tsc_khz variable are done in an interrupt
5381 * protected IPI, and all callers wishing to update the value
5382 * must wait for a synchronous IPI to complete (which is trivial
5383 * if the caller is on the CPU already). This establishes the
5384 * necessary total order on variable updates.
5385 *
5386 * Note that because a guest time update may take place
5387 * anytime after the setting of the VCPU's request bit, the
5388 * correct TSC value must be set before the request. However,
5389 * to ensure the update actually makes it to any guest which
5390 * starts running in hardware virtualization between the set
5391 * and the acquisition of the spinlock, we must also ping the
5392 * CPU after setting the request bit.
5393 *
5394 */
5395
c8076604
GH		 5396 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5397 return 0;
5398 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5399 return 0;
8cfdc000
ZA		 5400
5401 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5402
2f303b74 5403 spin_lock(&kvm_lock);
c8076604 5404 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5405 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5406 if (vcpu->cpu != freq->cpu)
5407 continue;
c285545f 5408 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5409 if (vcpu->cpu != smp_processor_id())
8cfdc000 5410 send_ipi = 1;
c8076604
GH		 5411 }
5412 }
2f303b74 5413 spin_unlock(&kvm_lock);
c8076604
GH		 5414
5415 if (freq->old < freq->new && send_ipi) {
5416 /*
5417 * We upscale the frequency. Must make the guest
5418 * doesn't see old kvmclock values while running with
5419 * the new frequency, otherwise we risk the guest sees
5420 * time go backwards.
5421 *
5422 * In case we update the frequency for another cpu
5423 * (which might be in guest context) send an interrupt
5424 * to kick the cpu out of guest context. Next time
5425 * guest context is entered kvmclock will be updated,
5426 * so the guest will not see stale values.
5427 */
8cfdc000 5428 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5429 }
5430 return 0;
5431}
5432
5433static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5434 .notifier_call = kvmclock_cpufreq_notifier
5435};
5436
5437static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5438 unsigned long action, void *hcpu)
5439{
5440 unsigned int cpu = (unsigned long)hcpu;
5441
5442 switch (action) {
5443 case CPU_ONLINE:
5444 case CPU_DOWN_FAILED:
5445 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5446 break;
5447 case CPU_DOWN_PREPARE:
5448 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5449 break;
5450 }
5451 return NOTIFY_OK;
5452}
5453
5454static struct notifier_block kvmclock_cpu_notifier_block = {
5455 .notifier_call = kvmclock_cpu_notifier,
5456 .priority = -INT_MAX
c8076604
GH		 5457};
5458
b820cc0c
ZA		 5459static void kvm_timer_init(void)
5460{
5461 int cpu;
5462
c285545f 5463 max_tsc_khz = tsc_khz;
460dd42e
SB		 5464
5465 cpu_notifier_register_begin();
b820cc0c 5466 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5467#ifdef CONFIG_CPU_FREQ
5468 struct cpufreq_policy policy;
5469 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5470 cpu = get_cpu();
5471 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5472 if (policy.cpuinfo.max_freq)
5473 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5474 put_cpu();
c285545f 5475#endif
b820cc0c
ZA		 5476 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5477 CPUFREQ_TRANSITION_NOTIFIER);
5478 }
c285545f 5479 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5480 for_each_online_cpu(cpu)
5481 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5482
5483 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5484 cpu_notifier_register_done();
5485
b820cc0c
ZA		 5486}
5487
ff9d07a0
ZY		 5488static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5489
f5132b01 5490int kvm_is_in_guest(void)
ff9d07a0 5491{
086c9855 5492 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5493}
5494
5495static int kvm_is_user_mode(void)
5496{
5497 int user_mode = 3;
dcf46b94 5498
086c9855
AS		 5499 if (__this_cpu_read(current_vcpu))
5500 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5501
ff9d07a0
ZY		 5502 return user_mode != 0;
5503}
5504
5505static unsigned long kvm_get_guest_ip(void)
5506{
5507 unsigned long ip = 0;
dcf46b94 5508
086c9855
AS		 5509 if (__this_cpu_read(current_vcpu))
5510 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5511
ff9d07a0
ZY		 5512 return ip;
5513}
5514
5515static struct perf_guest_info_callbacks kvm_guest_cbs = {
5516 .is_in_guest = kvm_is_in_guest,
5517 .is_user_mode = kvm_is_user_mode,
5518 .get_guest_ip = kvm_get_guest_ip,
5519};
5520
5521void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5522{
086c9855 5523 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5524}
5525EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5526
5527void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5528{
086c9855 5529 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5530}
5531EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5532
ce88decf
XG		 5533static void kvm_set_mmio_spte_mask(void)
5534{
5535 u64 mask;
5536 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5537
5538 /*
5539 * Set the reserved bits and the present bit of an paging-structure
5540 * entry to generate page fault with PFER.RSV = 1.
5541 */
885032b9 5542 /* Mask the reserved physical address bits. */
d1431483 5543 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5544
5545 /* Bit 62 is always reserved for 32bit host. */
5546 mask |= 0x3ull << 62;
5547
5548 /* Set the present bit. */
ce88decf
XG		 5549 mask |= 1ull;
5550
5551#ifdef CONFIG_X86_64
5552 /*
5553 * If reserved bit is not supported, clear the present bit to disable
5554 * mmio page fault.
5555 */
5556 if (maxphyaddr == 52)
5557 mask &= ~1ull;
5558#endif
5559
5560 kvm_mmu_set_mmio_spte_mask(mask);
5561}
5562
16e8d74d
MT		 5563#ifdef CONFIG_X86_64
5564static void pvclock_gtod_update_fn(struct work_struct *work)
5565{
d828199e
MT		 5566 struct kvm *kvm;
5567
5568 struct kvm_vcpu *vcpu;
5569 int i;
5570
2f303b74 5571 spin_lock(&kvm_lock);
d828199e
MT		 5572 list_for_each_entry(kvm, &vm_list, vm_list)
5573 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5574 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5575 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5576 spin_unlock(&kvm_lock);
16e8d74d
MT		 5577}
5578
5579static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5580
5581/*
5582 * Notification about pvclock gtod data update.
5583 */
5584static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5585 void *priv)
5586{
5587 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5588 struct timekeeper *tk = priv;
5589
5590 update_pvclock_gtod(tk);
5591
5592 /* disable master clock if host does not trust, or does not
5593 * use, TSC clocksource
5594 */
5595 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5596 atomic_read(&kvm_guest_has_master_clock) != 0)
5597 queue_work(system_long_wq, &pvclock_gtod_work);
5598
5599 return 0;
5600}
5601
5602static struct notifier_block pvclock_gtod_notifier = {
5603 .notifier_call = pvclock_gtod_notify,
5604};
5605#endif
5606
f8c16bba 5607int kvm_arch_init(void *opaque)
043405e1 5608{
b820cc0c 5609 int r;
6b61edf7 5610 struct kvm_x86_ops *ops = opaque;
f8c16bba 5611
f8c16bba
ZX		 5612 if (kvm_x86_ops) {
5613 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5614 r = -EEXIST;
5615 goto out;
f8c16bba
ZX		 5616 }
5617
5618 if (!ops->cpu_has_kvm_support()) {
5619 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5620 r = -EOPNOTSUPP;
5621 goto out;
f8c16bba
ZX		 5622 }
5623 if (ops->disabled_by_bios()) {
5624 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5625 r = -EOPNOTSUPP;
5626 goto out;
f8c16bba
ZX		 5627 }
5628
013f6a5d
MT		 5629 r = -ENOMEM;
5630 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5631 if (!shared_msrs) {
5632 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5633 goto out;
5634 }
5635
97db56ce
AK		 5636 r = kvm_mmu_module_init();
5637 if (r)
013f6a5d 5638 goto out_free_percpu;
97db56ce 5639
ce88decf 5640 kvm_set_mmio_spte_mask();
97db56ce 5641
f8c16bba 5642 kvm_x86_ops = ops;
920c8377 5643
7b52345e 5644 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5645 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5646
b820cc0c 5647 kvm_timer_init();
c8076604 5648
ff9d07a0
ZY		 5649 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5650
2acf923e
DC		 5651 if (cpu_has_xsave)
5652 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5653
c5cc421b 5654 kvm_lapic_init();
16e8d74d
MT		 5655#ifdef CONFIG_X86_64
5656 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5657#endif
5658
f8c16bba 5659 return 0;
56c6d28a 5660
013f6a5d
MT		 5661out_free_percpu:
5662 free_percpu(shared_msrs);
56c6d28a 5663out:
56c6d28a 5664 return r;
043405e1 5665}
8776e519 5666
f8c16bba
ZX		 5667void kvm_arch_exit(void)
5668{
ff9d07a0
ZY		 5669 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5670
888d256e
JK		 5671 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5672 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5673 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5674 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5675#ifdef CONFIG_X86_64
5676 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5677#endif
f8c16bba 5678 kvm_x86_ops = NULL;
56c6d28a 5679 kvm_mmu_module_exit();
013f6a5d 5680 free_percpu(shared_msrs);
56c6d28a 5681}
f8c16bba 5682
5cb56059 5683int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5684{
5685 ++vcpu->stat.halt_exits;
5686 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5687 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5688 return 1;
5689 } else {
5690 vcpu->run->exit_reason = KVM_EXIT_HLT;
5691 return 0;
5692 }
5693}
5cb56059
JS		 5694EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5695
5696int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5697{
5698 kvm_x86_ops->skip_emulated_instruction(vcpu);
5699 return kvm_vcpu_halt(vcpu);
5700}
8776e519
HB		 5701EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5702
6aef266c
SV		 5703/*
5704 * kvm_pv_kick_cpu_op: Kick a vcpu.
5705 *
5706 * @apicid - apicid of vcpu to be kicked.
5707 */
5708static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5709{
24d2166b 5710 struct kvm_lapic_irq lapic_irq;
6aef266c 5711
24d2166b
R		 5712 lapic_irq.shorthand = 0;
5713 lapic_irq.dest_mode = 0;
5714 lapic_irq.dest_id = apicid;
93bbf0b8 5715 lapic_irq.msi_redir_hint = false;
6aef266c 5716
24d2166b 5717 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5718 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5719}
5720
8776e519
HB		 5721int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5722{
5723 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5724 int op_64_bit, r = 1;
8776e519 5725
5cb56059
JS		 5726 kvm_x86_ops->skip_emulated_instruction(vcpu);
5727
55cd8e5a
GN		 5728 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5729 return kvm_hv_hypercall(vcpu);
5730
5fdbf976
MT		 5731 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5732 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5733 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5734 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5735 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5736
229456fc 5737 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5738
a449c7aa
NA		 5739 op_64_bit = is_64_bit_mode(vcpu);
5740 if (!op_64_bit) {
8776e519
HB		 5741 nr &= 0xFFFFFFFF;
5742 a0 &= 0xFFFFFFFF;
5743 a1 &= 0xFFFFFFFF;
5744 a2 &= 0xFFFFFFFF;
5745 a3 &= 0xFFFFFFFF;
5746 }
5747
07708c4a
JK		 5748 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5749 ret = -KVM_EPERM;
5750 goto out;
5751 }
5752
8776e519 5753 switch (nr) {
b93463aa
AK		 5754 case KVM_HC_VAPIC_POLL_IRQ:
5755 ret = 0;
5756 break;
6aef266c
SV		 5757 case KVM_HC_KICK_CPU:
5758 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5759 ret = 0;
5760 break;
8776e519
HB		 5761 default:
5762 ret = -KVM_ENOSYS;
5763 break;
5764 }
07708c4a 5765out:
a449c7aa
NA		 5766 if (!op_64_bit)
5767 ret = (u32)ret;
5fdbf976 5768 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5769 ++vcpu->stat.hypercalls;
2f333bcb 5770 return r;
8776e519
HB		 5771}
5772EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5773
b6785def 5774static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5775{
d6aa1000 5776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5777 char instruction[3];
5fdbf976 5778 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5779
8776e519 5780 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5781
9d74191a 5782 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5783}
5784
b6c7a5dc
HB		 5785/*
5786 * Check if userspace requested an interrupt window, and that the
5787 * interrupt window is open.
5788 *
5789 * No need to exit to userspace if we already have an interrupt queued.
5790 */
851ba692 5791static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5792{
8061823a 5793 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5794 vcpu->run->request_interrupt_window &&
5df56646 5795 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5796}
5797
851ba692 5798static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5799{
851ba692
AK		 5800 struct kvm_run *kvm_run = vcpu->run;
5801
91586a3b 5802 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5803 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5804 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5805 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5806 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5807 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5808 else
b6c7a5dc 5809 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5810 kvm_arch_interrupt_allowed(vcpu) &&
5811 !kvm_cpu_has_interrupt(vcpu) &&
5812 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5813}
5814
95ba8273
GN		 5815static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5816{
5817 int max_irr, tpr;
5818
5819 if (!kvm_x86_ops->update_cr8_intercept)
5820 return;
5821
88c808fd
AK		 5822 if (!vcpu->arch.apic)
5823 return;
5824
8db3baa2
GN		 5825 if (!vcpu->arch.apic->vapic_addr)
5826 max_irr = kvm_lapic_find_highest_irr(vcpu);
5827 else
5828 max_irr = -1;
95ba8273
GN		 5829
5830 if (max_irr != -1)
5831 max_irr >>= 4;
5832
5833 tpr = kvm_lapic_get_cr8(vcpu);
5834
5835 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5836}
5837
b6b8a145 5838static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5839{
b6b8a145
JK		 5840 int r;
5841
95ba8273 5842 /* try to reinject previous events if any */
b59bb7bd 5843 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5844 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5845 vcpu->arch.exception.has_error_code,
5846 vcpu->arch.exception.error_code);
d6e8c854
NA		 5847
5848 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5849 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5850 X86_EFLAGS_RF);
5851
6bdf0662
NA		 5852 if (vcpu->arch.exception.nr == DB_VECTOR &&
5853 (vcpu->arch.dr7 & DR7_GD)) {
5854 vcpu->arch.dr7 &= ~DR7_GD;
5855 kvm_update_dr7(vcpu);
5856 }
5857
b59bb7bd
GN		 5858 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5859 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5860 vcpu->arch.exception.error_code,
5861 vcpu->arch.exception.reinject);
b6b8a145 5862 return 0;
b59bb7bd
GN		 5863 }
5864
95ba8273
GN		 5865 if (vcpu->arch.nmi_injected) {
5866 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5867 return 0;
95ba8273
GN		 5868 }
5869
5870 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5871 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5872 return 0;
5873 }
5874
5875 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5876 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5877 if (r != 0)
5878 return r;
95ba8273
GN		 5879 }
5880
5881 /* try to inject new event if pending */
5882 if (vcpu->arch.nmi_pending) {
5883 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5884 --vcpu->arch.nmi_pending;
95ba8273
GN		 5885 vcpu->arch.nmi_injected = true;
5886 kvm_x86_ops->set_nmi(vcpu);
5887 }
c7c9c56c 5888 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5889 /*
5890 * Because interrupts can be injected asynchronously, we are
5891 * calling check_nested_events again here to avoid a race condition.
5892 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5893 * proposal and current concerns. Perhaps we should be setting
5894 * KVM_REQ_EVENT only on certain events and not unconditionally?
5895 */
5896 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5897 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5898 if (r != 0)
5899 return r;
5900 }
95ba8273 5901 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5902 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5903 false);
5904 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5905 }
5906 }
b6b8a145 5907 return 0;
95ba8273
GN		 5908}
5909
7460fb4a
AK		 5910static void process_nmi(struct kvm_vcpu *vcpu)
5911{
5912 unsigned limit = 2;
5913
5914 /*
5915 * x86 is limited to one NMI running, and one NMI pending after it.
5916 * If an NMI is already in progress, limit further NMIs to just one.
5917 * Otherwise, allow two (and we'll inject the first one immediately).
5918 */
5919 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5920 limit = 1;
5921
5922 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5923 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5924 kvm_make_request(KVM_REQ_EVENT, vcpu);
5925}
5926
660a5d51
PB		 5927#define put_smstate(type, buf, offset, val) \
5928 *(type *)((buf) + (offset) - 0x7e00) = val
5929
5930static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5931{
5932 u32 flags = 0;
5933 flags |= seg->g << 23;
5934 flags |= seg->db << 22;
5935 flags |= seg->l << 21;
5936 flags |= seg->avl << 20;
5937 flags |= seg->present << 15;
5938 flags |= seg->dpl << 13;
5939 flags |= seg->s << 12;
5940 flags |= seg->type << 8;
5941 return flags;
5942}
5943
5944static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5945{
5946 struct kvm_segment seg;
5947 int offset;
5948
5949 kvm_get_segment(vcpu, &seg, n);
5950 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5951
5952 if (n < 3)
5953 offset = 0x7f84 + n * 12;
5954 else
5955 offset = 0x7f2c + (n - 3) * 12;
5956
5957 put_smstate(u32, buf, offset + 8, seg.base);
5958 put_smstate(u32, buf, offset + 4, seg.limit);
5959 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5960}
5961
5962static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5963{
5964 struct kvm_segment seg;
5965 int offset;
5966 u16 flags;
5967
5968 kvm_get_segment(vcpu, &seg, n);
5969 offset = 0x7e00 + n * 16;
5970
5971 flags = process_smi_get_segment_flags(&seg) >> 8;
5972 put_smstate(u16, buf, offset, seg.selector);
5973 put_smstate(u16, buf, offset + 2, flags);
5974 put_smstate(u32, buf, offset + 4, seg.limit);
5975 put_smstate(u64, buf, offset + 8, seg.base);
5976}
5977
5978static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
5979{
5980 struct desc_ptr dt;
5981 struct kvm_segment seg;
5982 unsigned long val;
5983 int i;
5984
5985 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
5986 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
5987 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
5988 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
5989
5990 for (i = 0; i < 8; i++)
5991 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
5992
5993 kvm_get_dr(vcpu, 6, &val);
5994 put_smstate(u32, buf, 0x7fcc, (u32)val);
5995 kvm_get_dr(vcpu, 7, &val);
5996 put_smstate(u32, buf, 0x7fc8, (u32)val);
5997
5998 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
5999 put_smstate(u32, buf, 0x7fc4, seg.selector);
6000 put_smstate(u32, buf, 0x7f64, seg.base);
6001 put_smstate(u32, buf, 0x7f60, seg.limit);
6002 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6003
6004 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6005 put_smstate(u32, buf, 0x7fc0, seg.selector);
6006 put_smstate(u32, buf, 0x7f80, seg.base);
6007 put_smstate(u32, buf, 0x7f7c, seg.limit);
6008 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6009
6010 kvm_x86_ops->get_gdt(vcpu, &dt);
6011 put_smstate(u32, buf, 0x7f74, dt.address);
6012 put_smstate(u32, buf, 0x7f70, dt.size);
6013
6014 kvm_x86_ops->get_idt(vcpu, &dt);
6015 put_smstate(u32, buf, 0x7f58, dt.address);
6016 put_smstate(u32, buf, 0x7f54, dt.size);
6017
6018 for (i = 0; i < 6; i++)
6019 process_smi_save_seg_32(vcpu, buf, i);
6020
6021 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6022
6023 /* revision id */
6024 put_smstate(u32, buf, 0x7efc, 0x00020000);
6025 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6026}
6027
6028static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6029{
6030#ifdef CONFIG_X86_64
6031 struct desc_ptr dt;
6032 struct kvm_segment seg;
6033 unsigned long val;
6034 int i;
6035
6036 for (i = 0; i < 16; i++)
6037 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6038
6039 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6040 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6041
6042 kvm_get_dr(vcpu, 6, &val);
6043 put_smstate(u64, buf, 0x7f68, val);
6044 kvm_get_dr(vcpu, 7, &val);
6045 put_smstate(u64, buf, 0x7f60, val);
6046
6047 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6048 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6049 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6050
6051 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6052
6053 /* revision id */
6054 put_smstate(u32, buf, 0x7efc, 0x00020064);
6055
6056 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6057
6058 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6059 put_smstate(u16, buf, 0x7e90, seg.selector);
6060 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6061 put_smstate(u32, buf, 0x7e94, seg.limit);
6062 put_smstate(u64, buf, 0x7e98, seg.base);
6063
6064 kvm_x86_ops->get_idt(vcpu, &dt);
6065 put_smstate(u32, buf, 0x7e84, dt.size);
6066 put_smstate(u64, buf, 0x7e88, dt.address);
6067
6068 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6069 put_smstate(u16, buf, 0x7e70, seg.selector);
6070 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6071 put_smstate(u32, buf, 0x7e74, seg.limit);
6072 put_smstate(u64, buf, 0x7e78, seg.base);
6073
6074 kvm_x86_ops->get_gdt(vcpu, &dt);
6075 put_smstate(u32, buf, 0x7e64, dt.size);
6076 put_smstate(u64, buf, 0x7e68, dt.address);
6077
6078 for (i = 0; i < 6; i++)
6079 process_smi_save_seg_64(vcpu, buf, i);
6080#else
6081 WARN_ON_ONCE(1);
6082#endif
6083}
6084
64d60670
PB		 6085static void process_smi(struct kvm_vcpu *vcpu)
6086{
660a5d51
PB		 6087 struct kvm_segment cs, ds;
6088 char buf[512];
6089 u32 cr0;
6090
64d60670
PB		 6091 if (is_smm(vcpu)) {
6092 vcpu->arch.smi_pending = true;
6093 return;
6094 }
6095
660a5d51
PB		 6096 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6097 vcpu->arch.hflags |= HF_SMM_MASK;
6098 memset(buf, 0, 512);
6099 if (guest_cpuid_has_longmode(vcpu))
6100 process_smi_save_state_64(vcpu, buf);
6101 else
6102 process_smi_save_state_32(vcpu, buf);
6103
54bf36aa 6104 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6105
6106 if (kvm_x86_ops->get_nmi_mask(vcpu))
6107 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6108 else
6109 kvm_x86_ops->set_nmi_mask(vcpu, true);
6110
6111 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6112 kvm_rip_write(vcpu, 0x8000);
6113
6114 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6115 kvm_x86_ops->set_cr0(vcpu, cr0);
6116 vcpu->arch.cr0 = cr0;
6117
6118 kvm_x86_ops->set_cr4(vcpu, 0);
6119
6120 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6121
6122 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6123 cs.base = vcpu->arch.smbase;
6124
6125 ds.selector = 0;
6126 ds.base = 0;
6127
6128 cs.limit = ds.limit = 0xffffffff;
6129 cs.type = ds.type = 0x3;
6130 cs.dpl = ds.dpl = 0;
6131 cs.db = ds.db = 0;
6132 cs.s = ds.s = 1;
6133 cs.l = ds.l = 0;
6134 cs.g = ds.g = 1;
6135 cs.avl = ds.avl = 0;
6136 cs.present = ds.present = 1;
6137 cs.unusable = ds.unusable = 0;
6138 cs.padding = ds.padding = 0;
6139
6140 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6141 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6142 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6143 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6144 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6145 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6146
6147 if (guest_cpuid_has_longmode(vcpu))
6148 kvm_x86_ops->set_efer(vcpu, 0);
6149
6150 kvm_update_cpuid(vcpu);
6151 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6152}
6153
3d81bc7e 6154static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6155{
6156 u64 eoi_exit_bitmap[4];
cf9e65b7 6157 u32 tmr[8];
c7c9c56c 6158
3d81bc7e
YZ		 6159 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6160 return;
c7c9c56c
YZ		 6161
6162 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6163 memset(tmr, 0, 32);
c7c9c56c 6164
cf9e65b7 6165 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6166 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6167 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6168}
6169
a70656b6
RK		 6170static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6171{
6172 ++vcpu->stat.tlb_flush;
6173 kvm_x86_ops->tlb_flush(vcpu);
6174}
6175
4256f43f
TC		 6176void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6177{
c24ae0dc
TC		 6178 struct page *page = NULL;
6179
f439ed27
PB		 6180 if (!irqchip_in_kernel(vcpu->kvm))
6181 return;
6182
4256f43f
TC		 6183 if (!kvm_x86_ops->set_apic_access_page_addr)
6184 return;
6185
c24ae0dc 6186 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6187 if (is_error_page(page))
6188 return;
c24ae0dc
TC		 6189 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6190
6191 /*
6192 * Do not pin apic access page in memory, the MMU notifier
6193 * will call us again if it is migrated or swapped out.
6194 */
6195 put_page(page);
4256f43f
TC		 6196}
6197EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6198
fe71557a
TC		 6199void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6200 unsigned long address)
6201{
c24ae0dc
TC		 6202 /*
6203 * The physical address of apic access page is stored in the VMCS.
6204 * Update it when it becomes invalid.
6205 */
6206 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6207 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6208}
6209
9357d939 6210/*
362c698f 6211 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6212 * exiting to the userspace. Otherwise, the value will be returned to the
6213 * userspace.
6214 */
851ba692 6215static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6216{
6217 int r;
6a8b1d13 6218 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6219 vcpu->run->request_interrupt_window;
730dca42 6220 bool req_immediate_exit = false;
b6c7a5dc 6221
3e007509 6222 if (vcpu->requests) {
a8eeb04a 6223 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6224 kvm_mmu_unload(vcpu);
a8eeb04a 6225 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6226 __kvm_migrate_timers(vcpu);
d828199e
MT		 6227 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6228 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6229 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6230 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6231 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6232 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6233 if (unlikely(r))
6234 goto out;
6235 }
a8eeb04a 6236 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6237 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6238 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6239 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6240 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6241 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6242 r = 0;
6243 goto out;
6244 }
a8eeb04a 6245 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6246 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6247 r = 0;
6248 goto out;
6249 }
a8eeb04a 6250 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6251 vcpu->fpu_active = 0;
6252 kvm_x86_ops->fpu_deactivate(vcpu);
6253 }
af585b92
GN		 6254 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6255 /* Page is swapped out. Do synthetic halt */
6256 vcpu->arch.apf.halted = true;
6257 r = 1;
6258 goto out;
6259 }
c9aaa895
GC		 6260 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6261 record_steal_time(vcpu);
64d60670
PB		 6262 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6263 process_smi(vcpu);
7460fb4a
AK		 6264 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6265 process_nmi(vcpu);
f5132b01 6266 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6267 kvm_pmu_handle_event(vcpu);
f5132b01 6268 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6269 kvm_pmu_deliver_pmi(vcpu);
3d81bc7e
YZ		 6270 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6271 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6272 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6273 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6274 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6275 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6276 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6277 r = 0;
6278 goto out;
6279 }
2f52d58c 6280 }
b93463aa 6281
b463a6f7 6282 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6283 kvm_apic_accept_events(vcpu);
6284 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6285 r = 1;
6286 goto out;
6287 }
6288
b6b8a145
JK		 6289 if (inject_pending_event(vcpu, req_int_win) != 0)
6290 req_immediate_exit = true;
b463a6f7 6291 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6292 else if (vcpu->arch.nmi_pending)
c9a7953f 6293 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6294 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6295 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6296
6297 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6298 /*
6299 * Update architecture specific hints for APIC
6300 * virtual interrupt delivery.
6301 */
6302 if (kvm_x86_ops->hwapic_irr_update)
6303 kvm_x86_ops->hwapic_irr_update(vcpu,
6304 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6305 update_cr8_intercept(vcpu);
6306 kvm_lapic_sync_to_vapic(vcpu);
6307 }
6308 }
6309
d8368af8
AK		 6310 r = kvm_mmu_reload(vcpu);
6311 if (unlikely(r)) {
d905c069 6312 goto cancel_injection;
d8368af8
AK		 6313 }
6314
b6c7a5dc
HB		 6315 preempt_disable();
6316
6317 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6318 if (vcpu->fpu_active)
6319 kvm_load_guest_fpu(vcpu);
2acf923e 6320 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6321
6b7e2d09
XG		 6322 vcpu->mode = IN_GUEST_MODE;
6323
01b71917
MT		 6324 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6325
6b7e2d09
XG		 6326 /* We should set ->mode before check ->requests,
6327 * see the comment in make_all_cpus_request.
6328 */
01b71917 6329 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6330
d94e1dc9 6331 local_irq_disable();
32f88400 6332
6b7e2d09 6333 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6334 || need_resched() || signal_pending(current)) {
6b7e2d09 6335 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6336 smp_wmb();
6c142801
AK		 6337 local_irq_enable();
6338 preempt_enable();
01b71917 6339 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6340 r = 1;
d905c069 6341 goto cancel_injection;
6c142801
AK		 6342 }
6343
d6185f20
NHE		 6344 if (req_immediate_exit)
6345 smp_send_reschedule(vcpu->cpu);
6346
ccf73aaf 6347 __kvm_guest_enter();
b6c7a5dc 6348
42dbaa5a 6349 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6350 set_debugreg(0, 7);
6351 set_debugreg(vcpu->arch.eff_db[0], 0);
6352 set_debugreg(vcpu->arch.eff_db[1], 1);
6353 set_debugreg(vcpu->arch.eff_db[2], 2);
6354 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6355 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6356 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6357 }
b6c7a5dc 6358
229456fc 6359 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6360 wait_lapic_expire(vcpu);
851ba692 6361 kvm_x86_ops->run(vcpu);
b6c7a5dc 6362
c77fb5fe
PB		 6363 /*
6364 * Do this here before restoring debug registers on the host. And
6365 * since we do this before handling the vmexit, a DR access vmexit
6366 * can (a) read the correct value of the debug registers, (b) set
6367 * KVM_DEBUGREG_WONT_EXIT again.
6368 */
6369 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6370 int i;
6371
6372 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6373 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6374 for (i = 0; i < KVM_NR_DB_REGS; i++)
6375 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6376 }
6377
24f1e32c
FW		 6378 /*
6379 * If the guest has used debug registers, at least dr7
6380 * will be disabled while returning to the host.
6381 * If we don't have active breakpoints in the host, we don't
6382 * care about the messed up debug address registers. But if
6383 * we have some of them active, restore the old state.
6384 */
59d8eb53 6385 if (hw_breakpoint_active())
24f1e32c 6386 hw_breakpoint_restore();
42dbaa5a 6387
886b470c
MT		 6388 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6389 native_read_tsc());
1d5f066e 6390
6b7e2d09 6391 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6392 smp_wmb();
a547c6db
YZ		 6393
6394 /* Interrupt is enabled by handle_external_intr() */
6395 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6396
6397 ++vcpu->stat.exits;
6398
6399 /*
6400 * We must have an instruction between local_irq_enable() and
6401 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6402 * the interrupt shadow. The stat.exits increment will do nicely.
6403 * But we need to prevent reordering, hence this barrier():
6404 */
6405 barrier();
6406
6407 kvm_guest_exit();
6408
6409 preempt_enable();
6410
f656ce01 6411 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6412
b6c7a5dc
HB		 6413 /*
6414 * Profile KVM exit RIPs:
6415 */
6416 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6417 unsigned long rip = kvm_rip_read(vcpu);
6418 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6419 }
6420
cc578287
ZA		 6421 if (unlikely(vcpu->arch.tsc_always_catchup))
6422 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6423
5cfb1d5a
MT		 6424 if (vcpu->arch.apic_attention)
6425 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6426
851ba692 6427 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6428 return r;
6429
6430cancel_injection:
6431 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6432 if (unlikely(vcpu->arch.apic_attention))
6433 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6434out:
6435 return r;
6436}
b6c7a5dc 6437
362c698f
PB		 6438static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6439{
9c8fd1ba
PB		 6440 if (!kvm_arch_vcpu_runnable(vcpu)) {
6441 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6442 kvm_vcpu_block(vcpu);
6443 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6444 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6445 return 1;
6446 }
362c698f
PB		 6447
6448 kvm_apic_accept_events(vcpu);
6449 switch(vcpu->arch.mp_state) {
6450 case KVM_MP_STATE_HALTED:
6451 vcpu->arch.pv.pv_unhalted = false;
6452 vcpu->arch.mp_state =
6453 KVM_MP_STATE_RUNNABLE;
6454 case KVM_MP_STATE_RUNNABLE:
6455 vcpu->arch.apf.halted = false;
6456 break;
6457 case KVM_MP_STATE_INIT_RECEIVED:
6458 break;
6459 default:
6460 return -EINTR;
6461 break;
6462 }
6463 return 1;
6464}
09cec754 6465
362c698f 6466static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6467{
6468 int r;
f656ce01 6469 struct kvm *kvm = vcpu->kvm;
d7690175 6470
f656ce01 6471 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6472
362c698f 6473 for (;;) {
af585b92
GN		 6474 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6475 !vcpu->arch.apf.halted)
851ba692 6476 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6477 else
6478 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6479 if (r <= 0)
6480 break;
6481
6482 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6483 if (kvm_cpu_has_pending_timer(vcpu))
6484 kvm_inject_pending_timer_irqs(vcpu);
6485
851ba692 6486 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6487 r = -EINTR;
851ba692 6488 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6489 ++vcpu->stat.request_irq_exits;
362c698f 6490 break;
09cec754 6491 }
af585b92
GN		 6492
6493 kvm_check_async_pf_completion(vcpu);
6494
09cec754
GN		 6495 if (signal_pending(current)) {
6496 r = -EINTR;
851ba692 6497 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6498 ++vcpu->stat.signal_exits;
362c698f 6499 break;
09cec754
GN		 6500 }
6501 if (need_resched()) {
f656ce01 6502 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6503 cond_resched();
f656ce01 6504 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6505 }
b6c7a5dc
HB		 6506 }
6507
f656ce01 6508 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6509
6510 return r;
6511}
6512
716d51ab
GN		 6513static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6514{
6515 int r;
6516 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6517 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6518 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6519 if (r != EMULATE_DONE)
6520 return 0;
6521 return 1;
6522}
6523
6524static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6525{
6526 BUG_ON(!vcpu->arch.pio.count);
6527
6528 return complete_emulated_io(vcpu);
6529}
6530
f78146b0
AK		 6531/*
6532 * Implements the following, as a state machine:
6533 *
6534 * read:
6535 * for each fragment
87da7e66
XG		 6536 * for each mmio piece in the fragment
6537 * write gpa, len
6538 * exit
6539 * copy data
f78146b0
AK		 6540 * execute insn
6541 *
6542 * write:
6543 * for each fragment
87da7e66
XG		 6544 * for each mmio piece in the fragment
6545 * write gpa, len
6546 * copy data
6547 * exit
f78146b0 6548 */
716d51ab 6549static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6550{
6551 struct kvm_run *run = vcpu->run;
f78146b0 6552 struct kvm_mmio_fragment *frag;
87da7e66 6553 unsigned len;
5287f194 6554
716d51ab 6555 BUG_ON(!vcpu->mmio_needed);
5287f194 6556
716d51ab 6557 /* Complete previous fragment */
87da7e66
XG		 6558 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6559 len = min(8u, frag->len);
716d51ab 6560 if (!vcpu->mmio_is_write)
87da7e66
XG		 6561 memcpy(frag->data, run->mmio.data, len);
6562
6563 if (frag->len <= 8) {
6564 /* Switch to the next fragment. */
6565 frag++;
6566 vcpu->mmio_cur_fragment++;
6567 } else {
6568 /* Go forward to the next mmio piece. */
6569 frag->data += len;
6570 frag->gpa += len;
6571 frag->len -= len;
6572 }
6573
a08d3b3b 6574 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6575 vcpu->mmio_needed = 0;
0912c977
PB		 6576
6577 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6578 if (vcpu->mmio_is_write)
716d51ab
GN		 6579 return 1;
6580 vcpu->mmio_read_completed = 1;
6581 return complete_emulated_io(vcpu);
6582 }
87da7e66 6583
716d51ab
GN		 6584 run->exit_reason = KVM_EXIT_MMIO;
6585 run->mmio.phys_addr = frag->gpa;
6586 if (vcpu->mmio_is_write)
87da7e66
XG		 6587 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6588 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6589 run->mmio.is_write = vcpu->mmio_is_write;
6590 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6591 return 0;
5287f194
AK		 6592}
6593
716d51ab 6594
b6c7a5dc
HB		 6595int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6596{
c5bedc68 6597 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6598 int r;
6599 sigset_t sigsaved;
6600
c4d72e2d 6601 fpu__activate_curr(fpu);
e5c30142 6602
ac9f6dc0
AK		 6603 if (vcpu->sigset_active)
6604 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6605
a4535290 6606 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6607 kvm_vcpu_block(vcpu);
66450a21 6608 kvm_apic_accept_events(vcpu);
d7690175 6609 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6610 r = -EAGAIN;
6611 goto out;
b6c7a5dc
HB		 6612 }
6613
b6c7a5dc 6614 /* re-sync apic's tpr */
eea1cff9
AP		 6615 if (!irqchip_in_kernel(vcpu->kvm)) {
6616 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6617 r = -EINVAL;
6618 goto out;
6619 }
6620 }
b6c7a5dc 6621
716d51ab
GN		 6622 if (unlikely(vcpu->arch.complete_userspace_io)) {
6623 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6624 vcpu->arch.complete_userspace_io = NULL;
6625 r = cui(vcpu);
6626 if (r <= 0)
6627 goto out;
6628 } else
6629 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6630
362c698f 6631 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6632
6633out:
f1d86e46 6634 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6635 if (vcpu->sigset_active)
6636 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6637
b6c7a5dc
HB		 6638 return r;
6639}
6640
6641int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6642{
7ae441ea
GN		 6643 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6644 /*
6645 * We are here if userspace calls get_regs() in the middle of
6646 * instruction emulation. Registers state needs to be copied
4a969980 6647 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6648 * that usually, but some bad designed PV devices (vmware
6649 * backdoor interface) need this to work
6650 */
dd856efa 6651 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6652 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6653 }
5fdbf976
MT		 6654 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6655 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6656 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6657 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6658 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6659 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6660 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6661 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6662#ifdef CONFIG_X86_64
5fdbf976
MT		 6663 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6664 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6665 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6666 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6667 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6668 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6669 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6670 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6671#endif
6672
5fdbf976 6673 regs->rip = kvm_rip_read(vcpu);
91586a3b 6674 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6675
b6c7a5dc
HB		 6676 return 0;
6677}
6678
6679int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6680{
7ae441ea
GN		 6681 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6682 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6683
5fdbf976
MT		 6684 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6685 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6686 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6687 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6688 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6689 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6690 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6691 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6692#ifdef CONFIG_X86_64
5fdbf976
MT		 6693 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6694 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6695 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6696 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6697 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6698 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6699 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6700 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6701#endif
6702
5fdbf976 6703 kvm_rip_write(vcpu, regs->rip);
91586a3b 6704 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6705
b4f14abd
JK		 6706 vcpu->arch.exception.pending = false;
6707
3842d135
AK		 6708 kvm_make_request(KVM_REQ_EVENT, vcpu);
6709
b6c7a5dc
HB		 6710 return 0;
6711}
6712
b6c7a5dc
HB		 6713void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6714{
6715 struct kvm_segment cs;
6716
3e6e0aab 6717 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6718 *db = cs.db;
6719 *l = cs.l;
6720}
6721EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6722
6723int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6724 struct kvm_sregs *sregs)
6725{
89a27f4d 6726 struct desc_ptr dt;
b6c7a5dc 6727
3e6e0aab
GT		 6728 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6729 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6730 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6731 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6732 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6733 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6734
3e6e0aab
GT		 6735 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6736 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6737
6738 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6739 sregs->idt.limit = dt.size;
6740 sregs->idt.base = dt.address;
b6c7a5dc 6741 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6742 sregs->gdt.limit = dt.size;
6743 sregs->gdt.base = dt.address;
b6c7a5dc 6744
4d4ec087 6745 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6746 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6747 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6748 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6749 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6750 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6751 sregs->apic_base = kvm_get_apic_base(vcpu);
6752
923c61bb 6753 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6754
36752c9b 6755 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6756 set_bit(vcpu->arch.interrupt.nr,
6757 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6758
b6c7a5dc
HB		 6759 return 0;
6760}
6761
62d9f0db
MT		 6762int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6763 struct kvm_mp_state *mp_state)
6764{
66450a21 6765 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6766 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6767 vcpu->arch.pv.pv_unhalted)
6768 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6769 else
6770 mp_state->mp_state = vcpu->arch.mp_state;
6771
62d9f0db
MT		 6772 return 0;
6773}
6774
6775int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6776 struct kvm_mp_state *mp_state)
6777{
66450a21
JK		 6778 if (!kvm_vcpu_has_lapic(vcpu) &&
6779 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6780 return -EINVAL;
6781
6782 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6783 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6784 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6785 } else
6786 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6787 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6788 return 0;
6789}
6790
7f3d35fd
KW		 6791int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6792 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6793{
9d74191a 6794 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6795 int ret;
e01c2426 6796
8ec4722d 6797 init_emulate_ctxt(vcpu);
c697518a 6798
7f3d35fd 6799 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6800 has_error_code, error_code);
c697518a 6801
c697518a 6802 if (ret)
19d04437 6803 return EMULATE_FAIL;
37817f29 6804
9d74191a
TY		 6805 kvm_rip_write(vcpu, ctxt->eip);
6806 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6807 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6808 return EMULATE_DONE;
37817f29
IE		 6809}
6810EXPORT_SYMBOL_GPL(kvm_task_switch);
6811
b6c7a5dc
HB		 6812int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6813 struct kvm_sregs *sregs)
6814{
58cb628d 6815 struct msr_data apic_base_msr;
b6c7a5dc 6816 int mmu_reset_needed = 0;
63f42e02 6817 int pending_vec, max_bits, idx;
89a27f4d 6818 struct desc_ptr dt;
b6c7a5dc 6819
6d1068b3
PM		 6820 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6821 return -EINVAL;
6822
89a27f4d
GN		 6823 dt.size = sregs->idt.limit;
6824 dt.address = sregs->idt.base;
b6c7a5dc 6825 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6826 dt.size = sregs->gdt.limit;
6827 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6828 kvm_x86_ops->set_gdt(vcpu, &dt);
6829
ad312c7c 6830 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6831 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6832 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6833 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6834
2d3ad1f4 6835 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6836
f6801dff 6837 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6838 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6839 apic_base_msr.data = sregs->apic_base;
6840 apic_base_msr.host_initiated = true;
6841 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6842
4d4ec087 6843 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6844 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6845 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6846
fc78f519 6847 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6848 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6849 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6850 kvm_update_cpuid(vcpu);
63f42e02
XG		 6851
6852 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6853 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6854 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6855 mmu_reset_needed = 1;
6856 }
63f42e02 6857 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6858
6859 if (mmu_reset_needed)
6860 kvm_mmu_reset_context(vcpu);
6861
a50abc3b 6862 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6863 pending_vec = find_first_bit(
6864 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6865 if (pending_vec < max_bits) {
66fd3f7f 6866 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6867 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6868 }
6869
3e6e0aab
GT		 6870 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6871 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6872 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6873 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6874 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6875 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6876
3e6e0aab
GT		 6877 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6878 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6879
5f0269f5
ME		 6880 update_cr8_intercept(vcpu);
6881
9c3e4aab 6882 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6883 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6884 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6885 !is_protmode(vcpu))
9c3e4aab
MT		 6886 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6887
3842d135
AK		 6888 kvm_make_request(KVM_REQ_EVENT, vcpu);
6889
b6c7a5dc
HB		 6890 return 0;
6891}
6892
d0bfb940
JK		 6893int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6894 struct kvm_guest_debug *dbg)
b6c7a5dc 6895{
355be0b9 6896 unsigned long rflags;
ae675ef0 6897 int i, r;
b6c7a5dc 6898
4f926bf2
JK		 6899 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6900 r = -EBUSY;
6901 if (vcpu->arch.exception.pending)
2122ff5e 6902 goto out;
4f926bf2
JK		 6903 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6904 kvm_queue_exception(vcpu, DB_VECTOR);
6905 else
6906 kvm_queue_exception(vcpu, BP_VECTOR);
6907 }
6908
91586a3b
JK		 6909 /*
6910 * Read rflags as long as potentially injected trace flags are still
6911 * filtered out.
6912 */
6913 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6914
6915 vcpu->guest_debug = dbg->control;
6916 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6917 vcpu->guest_debug = 0;
6918
6919 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6920 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6921 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6922 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6923 } else {
6924 for (i = 0; i < KVM_NR_DB_REGS; i++)
6925 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6926 }
c8639010 6927 kvm_update_dr7(vcpu);
ae675ef0 6928
f92653ee
JK		 6929 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6930 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6931 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6932
91586a3b
JK		 6933 /*
6934 * Trigger an rflags update that will inject or remove the trace
6935 * flags.
6936 */
6937 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6938
c8639010 6939 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6940
4f926bf2 6941 r = 0;
d0bfb940 6942
2122ff5e 6943out:
b6c7a5dc
HB		 6944
6945 return r;
6946}
6947
8b006791
ZX		 6948/*
6949 * Translate a guest virtual address to a guest physical address.
6950 */
6951int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6952 struct kvm_translation *tr)
6953{
6954 unsigned long vaddr = tr->linear_address;
6955 gpa_t gpa;
f656ce01 6956 int idx;
8b006791 6957
f656ce01 6958 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6959 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6960 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6961 tr->physical_address = gpa;
6962 tr->valid = gpa != UNMAPPED_GVA;
6963 tr->writeable = 1;
6964 tr->usermode = 0;
8b006791
ZX		 6965
6966 return 0;
6967}
6968
d0752060
HB		 6969int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6970{
c47ada30 6971 struct fxregs_state *fxsave =
7366ed77 6972 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6973
d0752060
HB		 6974 memcpy(fpu->fpr, fxsave->st_space, 128);
6975 fpu->fcw = fxsave->cwd;
6976 fpu->fsw = fxsave->swd;
6977 fpu->ftwx = fxsave->twd;
6978 fpu->last_opcode = fxsave->fop;
6979 fpu->last_ip = fxsave->rip;
6980 fpu->last_dp = fxsave->rdp;
6981 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6982
d0752060
HB		 6983 return 0;
6984}
6985
6986int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6987{
c47ada30 6988 struct fxregs_state *fxsave =
7366ed77 6989 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 6990
d0752060
HB		 6991 memcpy(fxsave->st_space, fpu->fpr, 128);
6992 fxsave->cwd = fpu->fcw;
6993 fxsave->swd = fpu->fsw;
6994 fxsave->twd = fpu->ftwx;
6995 fxsave->fop = fpu->last_opcode;
6996 fxsave->rip = fpu->last_ip;
6997 fxsave->rdp = fpu->last_dp;
6998 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6999
d0752060
HB		 7000 return 0;
7001}
7002
0ee6a517 7003static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7004{
bf935b0b 7005 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7006 if (cpu_has_xsaves)
7366ed77 7007 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7008 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7009
2acf923e
DC		 7010 /*
7011 * Ensure guest xcr0 is valid for loading
7012 */
7013 vcpu->arch.xcr0 = XSTATE_FP;
7014
ad312c7c 7015 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7016}
d0752060
HB		 7017
7018void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7019{
2608d7a1 7020 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7021 return;
7022
2acf923e
DC		 7023 /*
7024 * Restore all possible states in the guest,
7025 * and assume host would use all available bits.
7026 * Guest xcr0 would be loaded later.
7027 */
7028 kvm_put_guest_xcr0(vcpu);
d0752060 7029 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7030 __kernel_fpu_begin();
003e2e8b 7031 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7032 trace_kvm_fpu(1);
d0752060 7033}
d0752060
HB		 7034
7035void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7036{
2acf923e
DC		 7037 kvm_put_guest_xcr0(vcpu);
7038
653f52c3
RR		 7039 if (!vcpu->guest_fpu_loaded) {
7040 vcpu->fpu_counter = 0;
d0752060 7041 return;
653f52c3 7042 }
d0752060
HB		 7043
7044 vcpu->guest_fpu_loaded = 0;
4f836347 7045 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7046 __kernel_fpu_end();
f096ed85 7047 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7048 /*
7049 * If using eager FPU mode, or if the guest is a frequent user
7050 * of the FPU, just leave the FPU active for next time.
7051 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7052 * the FPU in bursts will revert to loading it on demand.
7053 */
a9b4fb7e 7054 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7055 if (++vcpu->fpu_counter < 5)
7056 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7057 }
0c04851c 7058 trace_kvm_fpu(0);
d0752060 7059}
e9b11c17
ZX		 7060
7061void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7062{
12f9a48f 7063 kvmclock_reset(vcpu);
7f1ea208 7064
f5f48ee1 7065 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7066 kvm_x86_ops->vcpu_free(vcpu);
7067}
7068
7069struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7070 unsigned int id)
7071{
c447e76b
LL		 7072 struct kvm_vcpu *vcpu;
7073
6755bae8
ZA		 7074 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7075 printk_once(KERN_WARNING
7076 "kvm: SMP vm created on host with unstable TSC; "
7077 "guest TSC will not be reliable\n");
c447e76b
LL		 7078
7079 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7080
c447e76b 7081 return vcpu;
26e5215f 7082}
e9b11c17 7083
26e5215f
AK		 7084int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7085{
7086 int r;
e9b11c17 7087
19efffa2 7088 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7089 r = vcpu_load(vcpu);
7090 if (r)
7091 return r;
d28bc9dd 7092 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7093 kvm_mmu_setup(vcpu);
e9b11c17 7094 vcpu_put(vcpu);
26e5215f 7095 return r;
e9b11c17
ZX		 7096}
7097
31928aa5 7098void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7099{
8fe8ab46 7100 struct msr_data msr;
332967a3 7101 struct kvm *kvm = vcpu->kvm;
42897d86 7102
31928aa5
DD		 7103 if (vcpu_load(vcpu))
7104 return;
8fe8ab46
WA		 7105 msr.data = 0x0;
7106 msr.index = MSR_IA32_TSC;
7107 msr.host_initiated = true;
7108 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7109 vcpu_put(vcpu);
7110
630994b3
MT		 7111 if (!kvmclock_periodic_sync)
7112 return;
7113
332967a3
AJ		 7114 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7115 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7116}
7117
d40ccc62 7118void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7119{
9fc77441 7120 int r;
344d9588
GN		 7121 vcpu->arch.apf.msr_val = 0;
7122
9fc77441
MT		 7123 r = vcpu_load(vcpu);
7124 BUG_ON(r);
e9b11c17
ZX		 7125 kvm_mmu_unload(vcpu);
7126 vcpu_put(vcpu);
7127
7128 kvm_x86_ops->vcpu_free(vcpu);
7129}
7130
d28bc9dd 7131void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7132{
e69fab5d
PB		 7133 vcpu->arch.hflags = 0;
7134
7460fb4a
AK		 7135 atomic_set(&vcpu->arch.nmi_queued, 0);
7136 vcpu->arch.nmi_pending = 0;
448fa4a9 7137 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7138 kvm_clear_interrupt_queue(vcpu);
7139 kvm_clear_exception_queue(vcpu);
448fa4a9 7140
42dbaa5a 7141 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7142 kvm_update_dr0123(vcpu);
6f43ed01 7143 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7144 kvm_update_dr6(vcpu);
42dbaa5a 7145 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7146 kvm_update_dr7(vcpu);
42dbaa5a 7147
1119022c
NA		 7148 vcpu->arch.cr2 = 0;
7149
3842d135 7150 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7151 vcpu->arch.apf.msr_val = 0;
c9aaa895 7152 vcpu->arch.st.msr_val = 0;
3842d135 7153
12f9a48f
GC		 7154 kvmclock_reset(vcpu);
7155
af585b92
GN		 7156 kvm_clear_async_pf_completion_queue(vcpu);
7157 kvm_async_pf_hash_reset(vcpu);
7158 vcpu->arch.apf.halted = false;
3842d135 7159
64d60670 7160 if (!init_event) {
d28bc9dd 7161 kvm_pmu_reset(vcpu);
64d60670
PB		 7162 vcpu->arch.smbase = 0x30000;
7163 }
f5132b01 7164
66f7b72e
JS		 7165 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7166 vcpu->arch.regs_avail = ~0;
7167 vcpu->arch.regs_dirty = ~0;
7168
d28bc9dd 7169 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7170}
7171
2b4a273b 7172void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7173{
7174 struct kvm_segment cs;
7175
7176 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7177 cs.selector = vector << 8;
7178 cs.base = vector << 12;
7179 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7180 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7181}
7182
13a34e06 7183int kvm_arch_hardware_enable(void)
e9b11c17 7184{
ca84d1a2
ZA		 7185 struct kvm *kvm;
7186 struct kvm_vcpu *vcpu;
7187 int i;
0dd6a6ed
ZA		 7188 int ret;
7189 u64 local_tsc;
7190 u64 max_tsc = 0;
7191 bool stable, backwards_tsc = false;
18863bdd
AK		 7192
7193 kvm_shared_msr_cpu_online();
13a34e06 7194 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7195 if (ret != 0)
7196 return ret;
7197
7198 local_tsc = native_read_tsc();
7199 stable = !check_tsc_unstable();
7200 list_for_each_entry(kvm, &vm_list, vm_list) {
7201 kvm_for_each_vcpu(i, vcpu, kvm) {
7202 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7203 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7204 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7205 backwards_tsc = true;
7206 if (vcpu->arch.last_host_tsc > max_tsc)
7207 max_tsc = vcpu->arch.last_host_tsc;
7208 }
7209 }
7210 }
7211
7212 /*
7213 * Sometimes, even reliable TSCs go backwards. This happens on
7214 * platforms that reset TSC during suspend or hibernate actions, but
7215 * maintain synchronization. We must compensate. Fortunately, we can
7216 * detect that condition here, which happens early in CPU bringup,
7217 * before any KVM threads can be running. Unfortunately, we can't
7218 * bring the TSCs fully up to date with real time, as we aren't yet far
7219 * enough into CPU bringup that we know how much real time has actually
7220 * elapsed; our helper function, get_kernel_ns() will be using boot
7221 * variables that haven't been updated yet.
7222 *
7223 * So we simply find the maximum observed TSC above, then record the
7224 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7225 * the adjustment will be applied. Note that we accumulate
7226 * adjustments, in case multiple suspend cycles happen before some VCPU
7227 * gets a chance to run again. In the event that no KVM threads get a
7228 * chance to run, we will miss the entire elapsed period, as we'll have
7229 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7230 * loose cycle time. This isn't too big a deal, since the loss will be
7231 * uniform across all VCPUs (not to mention the scenario is extremely
7232 * unlikely). It is possible that a second hibernate recovery happens
7233 * much faster than a first, causing the observed TSC here to be
7234 * smaller; this would require additional padding adjustment, which is
7235 * why we set last_host_tsc to the local tsc observed here.
7236 *
7237 * N.B. - this code below runs only on platforms with reliable TSC,
7238 * as that is the only way backwards_tsc is set above. Also note
7239 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7240 * have the same delta_cyc adjustment applied if backwards_tsc
7241 * is detected. Note further, this adjustment is only done once,
7242 * as we reset last_host_tsc on all VCPUs to stop this from being
7243 * called multiple times (one for each physical CPU bringup).
7244 *
4a969980 7245 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7246 * will be compensated by the logic in vcpu_load, which sets the TSC to
7247 * catchup mode. This will catchup all VCPUs to real time, but cannot
7248 * guarantee that they stay in perfect synchronization.
7249 */
7250 if (backwards_tsc) {
7251 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7252 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7253 list_for_each_entry(kvm, &vm_list, vm_list) {
7254 kvm_for_each_vcpu(i, vcpu, kvm) {
7255 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7256 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7257 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7258 }
7259
7260 /*
7261 * We have to disable TSC offset matching.. if you were
7262 * booting a VM while issuing an S4 host suspend....
7263 * you may have some problem. Solving this issue is
7264 * left as an exercise to the reader.
7265 */
7266 kvm->arch.last_tsc_nsec = 0;
7267 kvm->arch.last_tsc_write = 0;
7268 }
7269
7270 }
7271 return 0;
e9b11c17
ZX		 7272}
7273
13a34e06 7274void kvm_arch_hardware_disable(void)
e9b11c17 7275{
13a34e06
RK		 7276 kvm_x86_ops->hardware_disable();
7277 drop_user_return_notifiers();
e9b11c17
ZX		 7278}
7279
7280int kvm_arch_hardware_setup(void)
7281{
9e9c3fe4
NA		 7282 int r;
7283
7284 r = kvm_x86_ops->hardware_setup();
7285 if (r != 0)
7286 return r;
7287
7288 kvm_init_msr_list();
7289 return 0;
e9b11c17
ZX		 7290}
7291
7292void kvm_arch_hardware_unsetup(void)
7293{
7294 kvm_x86_ops->hardware_unsetup();
7295}
7296
7297void kvm_arch_check_processor_compat(void *rtn)
7298{
7299 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7300}
7301
7302bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7303{
7304 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7305}
7306EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7307
7308bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7309{
7310 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7311}
7312
3e515705
AK		 7313bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7314{
7315 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7316}
7317
54e9818f
GN		 7318struct static_key kvm_no_apic_vcpu __read_mostly;
7319
e9b11c17
ZX		 7320int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7321{
7322 struct page *page;
7323 struct kvm *kvm;
7324 int r;
7325
7326 BUG_ON(vcpu->kvm == NULL);
7327 kvm = vcpu->kvm;
7328
6aef266c 7329 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7330 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7331 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7332 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7333 else
a4535290 7334 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7335
7336 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7337 if (!page) {
7338 r = -ENOMEM;
7339 goto fail;
7340 }
ad312c7c 7341 vcpu->arch.pio_data = page_address(page);
e9b11c17 7342
cc578287 7343 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7344
e9b11c17
ZX		 7345 r = kvm_mmu_create(vcpu);
7346 if (r < 0)
7347 goto fail_free_pio_data;
7348
7349 if (irqchip_in_kernel(kvm)) {
7350 r = kvm_create_lapic(vcpu);
7351 if (r < 0)
7352 goto fail_mmu_destroy;
54e9818f
GN		 7353 } else
7354 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7355
890ca9ae
HY		 7356 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7357 GFP_KERNEL);
7358 if (!vcpu->arch.mce_banks) {
7359 r = -ENOMEM;
443c39bc 7360 goto fail_free_lapic;
890ca9ae
HY		 7361 }
7362 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7363
f1797359
WY		 7364 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7365 r = -ENOMEM;
f5f48ee1 7366 goto fail_free_mce_banks;
f1797359 7367 }
f5f48ee1 7368
0ee6a517 7369 fx_init(vcpu);
66f7b72e 7370
ba904635 7371 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7372 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7373
7374 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7375 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7376
5a4f55cd
EK		 7377 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7378
74545705
RK		 7379 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7380
af585b92 7381 kvm_async_pf_hash_reset(vcpu);
f5132b01 7382 kvm_pmu_init(vcpu);
af585b92 7383
e9b11c17 7384 return 0;
0ee6a517 7385
f5f48ee1
SY		 7386fail_free_mce_banks:
7387 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7388fail_free_lapic:
7389 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7390fail_mmu_destroy:
7391 kvm_mmu_destroy(vcpu);
7392fail_free_pio_data:
ad312c7c 7393 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7394fail:
7395 return r;
7396}
7397
7398void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7399{
f656ce01
MT		 7400 int idx;
7401
f5132b01 7402 kvm_pmu_destroy(vcpu);
36cb93fd 7403 kfree(vcpu->arch.mce_banks);
e9b11c17 7404 kvm_free_lapic(vcpu);
f656ce01 7405 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7406 kvm_mmu_destroy(vcpu);
f656ce01 7407 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7408 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7409 if (!irqchip_in_kernel(vcpu->kvm))
7410 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7411}
d19a9cd2 7412
e790d9ef
RK		 7413void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7414{
ae97a3b8 7415 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7416}
7417
e08b9637 7418int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7419{
e08b9637
CO		 7420 if (type)
7421 return -EINVAL;
7422
6ef768fa 7423 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7424 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7425 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7426 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7427 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7428
5550af4d
SY		 7429 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7430 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7431 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7432 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7433 &kvm->arch.irq_sources_bitmap);
5550af4d 7434
038f8c11 7435 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7436 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7437 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7438
7439 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7440
7e44e449 7441 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7442 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7443
d89f5eff 7444 return 0;
d19a9cd2
ZX		 7445}
7446
7447static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7448{
9fc77441
MT		 7449 int r;
7450 r = vcpu_load(vcpu);
7451 BUG_ON(r);
d19a9cd2
ZX		 7452 kvm_mmu_unload(vcpu);
7453 vcpu_put(vcpu);
7454}
7455
7456static void kvm_free_vcpus(struct kvm *kvm)
7457{
7458 unsigned int i;
988a2cae 7459 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7460
7461 /*
7462 * Unpin any mmu pages first.
7463 */
af585b92
GN		 7464 kvm_for_each_vcpu(i, vcpu, kvm) {
7465 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7466 kvm_unload_vcpu_mmu(vcpu);
af585b92 7467 }
988a2cae
GN		 7468 kvm_for_each_vcpu(i, vcpu, kvm)
7469 kvm_arch_vcpu_free(vcpu);
7470
7471 mutex_lock(&kvm->lock);
7472 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7473 kvm->vcpus[i] = NULL;
d19a9cd2 7474
988a2cae
GN		 7475 atomic_set(&kvm->online_vcpus, 0);
7476 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7477}
7478
ad8ba2cd
SY		 7479void kvm_arch_sync_events(struct kvm *kvm)
7480{
332967a3 7481 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7482 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7483 kvm_free_all_assigned_devices(kvm);
aea924f6 7484 kvm_free_pit(kvm);
ad8ba2cd
SY		 7485}
7486
9da0e4d5
PB		 7487int __x86_set_memory_region(struct kvm *kvm,
7488 const struct kvm_userspace_memory_region *mem)
7489{
7490 int i, r;
7491
7492 /* Called with kvm->slots_lock held. */
7493 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7494
7495 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7496 struct kvm_userspace_memory_region m = *mem;
7497
7498 m.slot |= i << 16;
7499 r = __kvm_set_memory_region(kvm, &m);
7500 if (r < 0)
7501 return r;
7502 }
7503
7504 return 0;
7505}
7506EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7507
7508int x86_set_memory_region(struct kvm *kvm,
7509 const struct kvm_userspace_memory_region *mem)
7510{
7511 int r;
7512
7513 mutex_lock(&kvm->slots_lock);
7514 r = __x86_set_memory_region(kvm, mem);
7515 mutex_unlock(&kvm->slots_lock);
7516
7517 return r;
7518}
7519EXPORT_SYMBOL_GPL(x86_set_memory_region);
7520
d19a9cd2
ZX		 7521void kvm_arch_destroy_vm(struct kvm *kvm)
7522{
27469d29
AH		 7523 if (current->mm == kvm->mm) {
7524 /*
7525 * Free memory regions allocated on behalf of userspace,
7526 * unless the the memory map has changed due to process exit
7527 * or fd copying.
7528 */
7529 struct kvm_userspace_memory_region mem;
7530 memset(&mem, 0, sizeof(mem));
7531 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7532 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7533
7534 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7535 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7536
7537 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7538 x86_set_memory_region(kvm, &mem);
27469d29 7539 }
6eb55818 7540 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7541 kfree(kvm->arch.vpic);
7542 kfree(kvm->arch.vioapic);
d19a9cd2 7543 kvm_free_vcpus(kvm);
1e08ec4a 7544 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7545}
0de10343 7546
5587027c 7547void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7548 struct kvm_memory_slot *dont)
7549{
7550 int i;
7551
d89cc617
TY		 7552 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7553 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7554 kvfree(free->arch.rmap[i]);
d89cc617 7555 free->arch.rmap[i] = NULL;
77d11309 7556 }
d89cc617
TY		 7557 if (i == 0)
7558 continue;
7559
7560 if (!dont || free->arch.lpage_info[i - 1] !=
7561 dont->arch.lpage_info[i - 1]) {
548ef284 7562 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7563 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7564 }
7565 }
7566}
7567
5587027c
AK		 7568int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7569 unsigned long npages)
db3fe4eb
TY		 7570{
7571 int i;
7572
d89cc617 7573 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7574 unsigned long ugfn;
7575 int lpages;
d89cc617 7576 int level = i + 1;
db3fe4eb
TY		 7577
7578 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7579 slot->base_gfn, level) + 1;
7580
d89cc617
TY		 7581 slot->arch.rmap[i] =
7582 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7583 if (!slot->arch.rmap[i])
77d11309 7584 goto out_free;
d89cc617
TY		 7585 if (i == 0)
7586 continue;
77d11309 7587
d89cc617
TY		 7588 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7589 sizeof(*slot->arch.lpage_info[i - 1]));
7590 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7591 goto out_free;
7592
7593 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7594 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7595 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7596 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7597 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7598 /*
7599 * If the gfn and userspace address are not aligned wrt each
7600 * other, or if explicitly asked to, disable large page
7601 * support for this slot
7602 */
7603 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7604 !kvm_largepages_enabled()) {
7605 unsigned long j;
7606
7607 for (j = 0; j < lpages; ++j)
d89cc617 7608 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7609 }
7610 }
7611
7612 return 0;
7613
7614out_free:
d89cc617 7615 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7616 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7617 slot->arch.rmap[i] = NULL;
7618 if (i == 0)
7619 continue;
7620
548ef284 7621 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7622 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7623 }
7624 return -ENOMEM;
7625}
7626
15f46015 7627void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7628{
e6dff7d1
TY		 7629 /*
7630 * memslots->generation has been incremented.
7631 * mmio generation may have reached its maximum value.
7632 */
54bf36aa 7633 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7634}
7635
f7784b8e
MT		 7636int kvm_arch_prepare_memory_region(struct kvm *kvm,
7637 struct kvm_memory_slot *memslot,
09170a49 7638 const struct kvm_userspace_memory_region *mem,
7b6195a9 7639 enum kvm_mr_change change)
0de10343 7640{
7a905b14
TY		 7641 /*
7642 * Only private memory slots need to be mapped here since
7643 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7644 */
7b6195a9 7645 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7646 unsigned long userspace_addr;
604b38ac 7647
7a905b14
TY		 7648 /*
7649 * MAP_SHARED to prevent internal slot pages from being moved
7650 * by fork()/COW.
7651 */
7b6195a9 7652 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7653 PROT_READ | PROT_WRITE,
7654 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7655
7a905b14
TY		 7656 if (IS_ERR((void *)userspace_addr))
7657 return PTR_ERR((void *)userspace_addr);
604b38ac 7658
7a905b14 7659 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7660 }
7661
f7784b8e
MT		 7662 return 0;
7663}
7664
88178fd4
KH		 7665static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7666 struct kvm_memory_slot *new)
7667{
7668 /* Still write protect RO slot */
7669 if (new->flags & KVM_MEM_READONLY) {
7670 kvm_mmu_slot_remove_write_access(kvm, new);
7671 return;
7672 }
7673
7674 /*
7675 * Call kvm_x86_ops dirty logging hooks when they are valid.
7676 *
7677 * kvm_x86_ops->slot_disable_log_dirty is called when:
7678 *
7679 * - KVM_MR_CREATE with dirty logging is disabled
7680 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7681 *
7682 * The reason is, in case of PML, we need to set D-bit for any slots
7683 * with dirty logging disabled in order to eliminate unnecessary GPA
7684 * logging in PML buffer (and potential PML buffer full VMEXT). This
7685 * guarantees leaving PML enabled during guest's lifetime won't have
7686 * any additonal overhead from PML when guest is running with dirty
7687 * logging disabled for memory slots.
7688 *
7689 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7690 * to dirty logging mode.
7691 *
7692 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7693 *
7694 * In case of write protect:
7695 *
7696 * Write protect all pages for dirty logging.
7697 *
7698 * All the sptes including the large sptes which point to this
7699 * slot are set to readonly. We can not create any new large
7700 * spte on this slot until the end of the logging.
7701 *
7702 * See the comments in fast_page_fault().
7703 */
7704 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7705 if (kvm_x86_ops->slot_enable_log_dirty)
7706 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7707 else
7708 kvm_mmu_slot_remove_write_access(kvm, new);
7709 } else {
7710 if (kvm_x86_ops->slot_disable_log_dirty)
7711 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7712 }
7713}
7714
f7784b8e 7715void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7716 const struct kvm_userspace_memory_region *mem,
8482644a 7717 const struct kvm_memory_slot *old,
f36f3f28 7718 const struct kvm_memory_slot *new,
8482644a 7719 enum kvm_mr_change change)
f7784b8e 7720{
8482644a 7721 int nr_mmu_pages = 0;
f7784b8e 7722
f36f3f28 7723 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7724 int ret;
7725
8482644a
TY		 7726 ret = vm_munmap(old->userspace_addr,
7727 old->npages * PAGE_SIZE);
f7784b8e
MT		 7728 if (ret < 0)
7729 printk(KERN_WARNING
7730 "kvm_vm_ioctl_set_memory_region: "
7731 "failed to munmap memory\n");
7732 }
7733
48c0e4e9
XG		 7734 if (!kvm->arch.n_requested_mmu_pages)
7735 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7736
48c0e4e9 7737 if (nr_mmu_pages)
0de10343 7738 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7739
3ea3b7fa
WL		 7740 /*
7741 * Dirty logging tracks sptes in 4k granularity, meaning that large
7742 * sptes have to be split. If live migration is successful, the guest
7743 * in the source machine will be destroyed and large sptes will be
7744 * created in the destination. However, if the guest continues to run
7745 * in the source machine (for example if live migration fails), small
7746 * sptes will remain around and cause bad performance.
7747 *
7748 * Scan sptes if dirty logging has been stopped, dropping those
7749 * which can be collapsed into a single large-page spte. Later
7750 * page faults will create the large-page sptes.
7751 */
7752 if ((change != KVM_MR_DELETE) &&
7753 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7754 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7755 kvm_mmu_zap_collapsible_sptes(kvm, new);
7756
c972f3b1 7757 /*
88178fd4 7758 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7759 *
88178fd4
KH		 7760 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7761 * been zapped so no dirty logging staff is needed for old slot. For
7762 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7763 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7764 *
7765 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7766 */
88178fd4 7767 if (change != KVM_MR_DELETE)
f36f3f28 7768 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7769}
1d737c8a 7770
2df72e9b 7771void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7772{
6ca18b69 7773 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7774}
7775
2df72e9b
MT		 7776void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7777 struct kvm_memory_slot *slot)
7778{
6ca18b69 7779 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7780}
7781
1d737c8a
ZX		 7782int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7783{
b6b8a145
JK		 7784 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7785 kvm_x86_ops->check_nested_events(vcpu, false);
7786
af585b92
GN		 7787 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7788 !vcpu->arch.apf.halted)
7789 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7790 || kvm_apic_has_events(vcpu)
6aef266c 7791 || vcpu->arch.pv.pv_unhalted
7460fb4a 7792 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7793 (kvm_arch_interrupt_allowed(vcpu) &&
7794 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7795}
5736199a 7796
b6d33834 7797int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7798{
b6d33834 7799 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7800}
78646121
GN		 7801
7802int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7803{
7804 return kvm_x86_ops->interrupt_allowed(vcpu);
7805}
229456fc 7806
82b32774 7807unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7808{
82b32774
NA		 7809 if (is_64_bit_mode(vcpu))
7810 return kvm_rip_read(vcpu);
7811 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7812 kvm_rip_read(vcpu));
7813}
7814EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7815
82b32774
NA		 7816bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7817{
7818 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7819}
7820EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7821
94fe45da
JK		 7822unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7823{
7824 unsigned long rflags;
7825
7826 rflags = kvm_x86_ops->get_rflags(vcpu);
7827 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7828 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7829 return rflags;
7830}
7831EXPORT_SYMBOL_GPL(kvm_get_rflags);
7832
6addfc42 7833static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7834{
7835 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7836 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7837 rflags |= X86_EFLAGS_TF;
94fe45da 7838 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7839}
7840
7841void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7842{
7843 __kvm_set_rflags(vcpu, rflags);
3842d135 7844 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7845}
7846EXPORT_SYMBOL_GPL(kvm_set_rflags);
7847
56028d08
GN		 7848void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7849{
7850 int r;
7851
fb67e14f 7852 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7853 work->wakeup_all)
56028d08
GN		 7854 return;
7855
7856 r = kvm_mmu_reload(vcpu);
7857 if (unlikely(r))
7858 return;
7859
fb67e14f
XG		 7860 if (!vcpu->arch.mmu.direct_map &&
7861 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7862 return;
7863
56028d08
GN		 7864 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7865}
7866
af585b92
GN		 7867static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7868{
7869 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7870}
7871
7872static inline u32 kvm_async_pf_next_probe(u32 key)
7873{
7874 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7875}
7876
7877static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7878{
7879 u32 key = kvm_async_pf_hash_fn(gfn);
7880
7881 while (vcpu->arch.apf.gfns[key] != ~0)
7882 key = kvm_async_pf_next_probe(key);
7883
7884 vcpu->arch.apf.gfns[key] = gfn;
7885}
7886
7887static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7888{
7889 int i;
7890 u32 key = kvm_async_pf_hash_fn(gfn);
7891
7892 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7893 (vcpu->arch.apf.gfns[key] != gfn &&
7894 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7895 key = kvm_async_pf_next_probe(key);
7896
7897 return key;
7898}
7899
7900bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7901{
7902 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7903}
7904
7905static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7906{
7907 u32 i, j, k;
7908
7909 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7910 while (true) {
7911 vcpu->arch.apf.gfns[i] = ~0;
7912 do {
7913 j = kvm_async_pf_next_probe(j);
7914 if (vcpu->arch.apf.gfns[j] == ~0)
7915 return;
7916 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7917 /*
7918 * k lies cyclically in ]i,j]
7919 * | i.k.j |
7920 * |....j i.k.| or |.k..j i...|
7921 */
7922 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7923 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7924 i = j;
7925 }
7926}
7927
7c90705b
GN		 7928static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7929{
7930
7931 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7932 sizeof(val));
7933}
7934
af585b92
GN		 7935void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7936 struct kvm_async_pf *work)
7937{
6389ee94
AK		 7938 struct x86_exception fault;
7939
7c90705b 7940 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7941 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7942
7943 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7944 (vcpu->arch.apf.send_user_only &&
7945 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7946 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7947 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7948 fault.vector = PF_VECTOR;
7949 fault.error_code_valid = true;
7950 fault.error_code = 0;
7951 fault.nested_page_fault = false;
7952 fault.address = work->arch.token;
7953 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7954 }
af585b92
GN		 7955}
7956
7957void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7958 struct kvm_async_pf *work)
7959{
6389ee94
AK		 7960 struct x86_exception fault;
7961
7c90705b 7962 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7963 if (work->wakeup_all)
7c90705b
GN		 7964 work->arch.token = ~0; /* broadcast wakeup */
7965 else
7966 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7967
7968 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7969 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7970 fault.vector = PF_VECTOR;
7971 fault.error_code_valid = true;
7972 fault.error_code = 0;
7973 fault.nested_page_fault = false;
7974 fault.address = work->arch.token;
7975 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7976 }
e6d53e3b 7977 vcpu->arch.apf.halted = false;
a4fa1635 7978 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7979}
7980
7981bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7982{
7983 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7984 return true;
7985 else
7986 return !kvm_event_needs_reinjection(vcpu) &&
7987 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7988}
7989
5544eb9b
PB		 7990void kvm_arch_start_assignment(struct kvm *kvm)
7991{
7992 atomic_inc(&kvm->arch.assigned_device_count);
7993}
7994EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
7995
7996void kvm_arch_end_assignment(struct kvm *kvm)
7997{
7998 atomic_dec(&kvm->arch.assigned_device_count);
7999}
8000EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8001
8002bool kvm_arch_has_assigned_device(struct kvm *kvm)
8003{
8004 return atomic_read(&kvm->arch.assigned_device_count);
8005}
8006EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8007
e0f0bbc5
AW		 8008void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8009{
8010 atomic_inc(&kvm->arch.noncoherent_dma_count);
8011}
8012EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8013
8014void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8015{
8016 atomic_dec(&kvm->arch.noncoherent_dma_count);
8017}
8018EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8019
8020bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8021{
8022 return atomic_read(&kvm->arch.noncoherent_dma_count);
8023}
8024EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8025
229456fc
MT		 8026EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8027EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8028EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8029EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8030EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8031EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8032EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8033EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8034EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8035EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8036EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8037EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8038EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8039EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8040EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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