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KVM: x86: clear hidden CPU state at reset time
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 225 if (slot >= shared_msrs_global.nr)
226 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 227 shared_msrs_global.msrs[slot] = msr;
228 /* we need ensured the shared_msr_global have been updated */
229 smp_wmb();
18863bdd
AK		 230}
231EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
232
233static void kvm_shared_msr_cpu_online(void)
234{
235 unsigned i;
18863bdd
AK		 236
237 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 238 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 239}
240
8b3c3104 241int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 242{
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 245 int err;
18863bdd 246
2bf78fa7 247 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 248 return 0;
2bf78fa7 249 smsr->values[slot].curr = value;
8b3c3104
AH		 250 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
251 if (err)
252 return 1;
253
18863bdd
AK		 254 if (!smsr->registered) {
255 smsr->urn.on_user_return = kvm_on_user_return;
256 user_return_notifier_register(&smsr->urn);
257 smsr->registered = true;
258 }
8b3c3104 259 return 0;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
262
13a34e06 263static void drop_user_return_notifiers(void)
3548bab5 264{
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 267
268 if (smsr->registered)
269 kvm_on_user_return(&smsr->urn);
270}
271
6866b83e
CO		 272u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
273{
8a5a87d9 274 return vcpu->arch.apic_base;
6866b83e
CO		 275}
276EXPORT_SYMBOL_GPL(kvm_get_apic_base);
277
58cb628d
JK		 278int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
279{
280 u64 old_state = vcpu->arch.apic_base &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 new_state = msr_info->data &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
285 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
286
287 if (!msr_info->host_initiated &&
288 ((msr_info->data & reserved_bits) != 0 ||
289 new_state == X2APIC_ENABLE ||
290 (new_state == MSR_IA32_APICBASE_ENABLE &&
291 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
292 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
293 old_state == 0)))
294 return 1;
295
296 kvm_lapic_set_base(vcpu, msr_info->data);
297 return 0;
6866b83e
CO		 298}
299EXPORT_SYMBOL_GPL(kvm_set_apic_base);
300
2605fc21 301asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 302{
303 /* Fault while not rebooting. We want the trace. */
304 BUG();
305}
306EXPORT_SYMBOL_GPL(kvm_spurious_fault);
307
3fd28fce
ED		 308#define EXCPT_BENIGN 0
309#define EXCPT_CONTRIBUTORY 1
310#define EXCPT_PF 2
311
312static int exception_class(int vector)
313{
314 switch (vector) {
315 case PF_VECTOR:
316 return EXCPT_PF;
317 case DE_VECTOR:
318 case TS_VECTOR:
319 case NP_VECTOR:
320 case SS_VECTOR:
321 case GP_VECTOR:
322 return EXCPT_CONTRIBUTORY;
323 default:
324 break;
325 }
326 return EXCPT_BENIGN;
327}
328
d6e8c854
NA		 329#define EXCPT_FAULT 0
330#define EXCPT_TRAP 1
331#define EXCPT_ABORT 2
332#define EXCPT_INTERRUPT 3
333
334static int exception_type(int vector)
335{
336 unsigned int mask;
337
338 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
339 return EXCPT_INTERRUPT;
340
341 mask = 1 << vector;
342
343 /* #DB is trap, as instruction watchpoints are handled elsewhere */
344 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
345 return EXCPT_TRAP;
346
347 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
348 return EXCPT_ABORT;
349
350 /* Reserved exceptions will result in fault */
351 return EXCPT_FAULT;
352}
353
3fd28fce 354static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 355 unsigned nr, bool has_error, u32 error_code,
356 bool reinject)
3fd28fce
ED		 357{
358 u32 prev_nr;
359 int class1, class2;
360
3842d135
AK		 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
362
3fd28fce
ED		 363 if (!vcpu->arch.exception.pending) {
364 queue:
3ffb2468
NA		 365 if (has_error && !is_protmode(vcpu))
366 has_error = false;
3fd28fce
ED		 367 vcpu->arch.exception.pending = true;
368 vcpu->arch.exception.has_error_code = has_error;
369 vcpu->arch.exception.nr = nr;
370 vcpu->arch.exception.error_code = error_code;
3f0fd292 371 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 372 return;
373 }
374
375 /* to check exception */
376 prev_nr = vcpu->arch.exception.nr;
377 if (prev_nr == DF_VECTOR) {
378 /* triple fault -> shutdown */
a8eeb04a 379 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 380 return;
381 }
382 class1 = exception_class(prev_nr);
383 class2 = exception_class(nr);
384 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
385 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
386 /* generate double fault per SDM Table 5-5 */
387 vcpu->arch.exception.pending = true;
388 vcpu->arch.exception.has_error_code = true;
389 vcpu->arch.exception.nr = DF_VECTOR;
390 vcpu->arch.exception.error_code = 0;
391 } else
392 /* replace previous exception with a new one in a hope
393 that instruction re-execution will regenerate lost
394 exception */
395 goto queue;
396}
397
298101da
AK		 398void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
399{
ce7ddec4 400 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 401}
402EXPORT_SYMBOL_GPL(kvm_queue_exception);
403
ce7ddec4
JR		 404void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
405{
406 kvm_multiple_exception(vcpu, nr, false, 0, true);
407}
408EXPORT_SYMBOL_GPL(kvm_requeue_exception);
409
db8fcefa 410void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 411{
db8fcefa
AP		 412 if (err)
413 kvm_inject_gp(vcpu, 0);
414 else
415 kvm_x86_ops->skip_emulated_instruction(vcpu);
416}
417EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 418
6389ee94 419void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 420{
421 ++vcpu->stat.pf_guest;
6389ee94
AK		 422 vcpu->arch.cr2 = fault->address;
423 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 424}
27d6c865 425EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 426
ef54bcfe 427static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 428{
6389ee94
AK		 429 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
430 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 431 else
6389ee94 432 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 433
434 return fault->nested_page_fault;
d4f8cf66
JR		 435}
436
3419ffc8
SY		 437void kvm_inject_nmi(struct kvm_vcpu *vcpu)
438{
7460fb4a
AK		 439 atomic_inc(&vcpu->arch.nmi_queued);
440 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 441}
442EXPORT_SYMBOL_GPL(kvm_inject_nmi);
443
298101da
AK		 444void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
445{
ce7ddec4 446 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 447}
448EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
449
ce7ddec4
JR		 450void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
451{
452 kvm_multiple_exception(vcpu, nr, true, error_code, true);
453}
454EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
455
0a79b009
AK		 456/*
457 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
458 * a #GP and return false.
459 */
460bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 461{
0a79b009
AK		 462 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
463 return true;
464 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
465 return false;
298101da 466}
0a79b009 467EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 468
16f8a6f9
NA		 469bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
470{
471 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
472 return true;
473
474 kvm_queue_exception(vcpu, UD_VECTOR);
475 return false;
476}
477EXPORT_SYMBOL_GPL(kvm_require_dr);
478
ec92fe44
JR		 479/*
480 * This function will be used to read from the physical memory of the currently
481 * running guest. The difference to kvm_read_guest_page is that this function
482 * can read from guest physical or from the guest's guest physical memory.
483 */
484int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
485 gfn_t ngfn, void *data, int offset, int len,
486 u32 access)
487{
54987b7a 488 struct x86_exception exception;
ec92fe44
JR		 489 gfn_t real_gfn;
490 gpa_t ngpa;
491
492 ngpa = gfn_to_gpa(ngfn);
54987b7a 493 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 494 if (real_gfn == UNMAPPED_GVA)
495 return -EFAULT;
496
497 real_gfn = gpa_to_gfn(real_gfn);
498
499 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
500}
501EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
502
69b0049a 503static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 504 void *data, int offset, int len, u32 access)
505{
506 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
507 data, offset, len, access);
508}
509
a03490ed
CO		 510/*
511 * Load the pae pdptrs. Return true is they are all valid.
512 */
ff03a073 513int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 514{
515 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
516 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
517 int i;
518 int ret;
ff03a073 519 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 520
ff03a073
JR		 521 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
522 offset * sizeof(u64), sizeof(pdpte),
523 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 524 if (ret < 0) {
525 ret = 0;
526 goto out;
527 }
528 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 529 if (is_present_gpte(pdpte[i]) &&
20c466b5 530 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 624 return 0;
625}
2d3ad1f4 626EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 627
2d3ad1f4 628void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 629{
49a9b07e 630 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 631}
2d3ad1f4 632EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 633
42bdf991
MT		 634static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
635{
636 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
637 !vcpu->guest_xcr0_loaded) {
638 /* kvm_set_xcr() also depends on this */
639 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
640 vcpu->guest_xcr0_loaded = 1;
641 }
642}
643
644static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
645{
646 if (vcpu->guest_xcr0_loaded) {
647 if (vcpu->arch.xcr0 != host_xcr0)
648 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
649 vcpu->guest_xcr0_loaded = 0;
650 }
651}
652
69b0049a 653static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 654{
56c103ec
LJ		 655 u64 xcr0 = xcr;
656 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 657 u64 valid_bits;
2acf923e
DC		 658
659 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
660 if (index != XCR_XFEATURE_ENABLED_MASK)
661 return 1;
2acf923e
DC		 662 if (!(xcr0 & XSTATE_FP))
663 return 1;
664 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
665 return 1;
46c34cb0
PB		 666
667 /*
668 * Do not allow the guest to set bits that we do not support
669 * saving. However, xcr0 bit 0 is always set, even if the
670 * emulated CPU does not support XSAVE (see fx_init).
671 */
672 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
673 if (xcr0 & ~valid_bits)
2acf923e 674 return 1;
46c34cb0 675
390bd528
LJ		 676 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
677 return 1;
678
612263b3
CP		 679 if (xcr0 & XSTATE_AVX512) {
680 if (!(xcr0 & XSTATE_YMM))
681 return 1;
682 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
683 return 1;
684 }
42bdf991 685 kvm_put_guest_xcr0(vcpu);
2acf923e 686 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 687
688 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
689 kvm_update_cpuid(vcpu);
2acf923e
DC		 690 return 0;
691}
692
693int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
694{
764bcbc5
Z		 695 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
696 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 697 kvm_inject_gp(vcpu, 0);
698 return 1;
699 }
700 return 0;
701}
702EXPORT_SYMBOL_GPL(kvm_set_xcr);
703
a83b29c6 704int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 705{
fc78f519 706 unsigned long old_cr4 = kvm_read_cr4(vcpu);
edc90b7d
XG		 707 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
708 X86_CR4_SMEP | X86_CR4_SMAP;
709
0f12244f
GN		 710 if (cr4 & CR4_RESERVED_BITS)
711 return 1;
a03490ed 712
2acf923e
DC		 713 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
714 return 1;
715
c68b734f
YW		 716 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
717 return 1;
718
97ec8c06
FW		 719 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
720 return 1;
721
afcbf13f 722 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 723 return 1;
724
a03490ed 725 if (is_long_mode(vcpu)) {
0f12244f
GN		 726 if (!(cr4 & X86_CR4_PAE))
727 return 1;
a2edf57f
AK		 728 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
729 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 730 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
731 kvm_read_cr3(vcpu)))
0f12244f
GN		 732 return 1;
733
ad756a16
MJ		 734 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
735 if (!guest_cpuid_has_pcid(vcpu))
736 return 1;
737
738 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
739 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
740 return 1;
741 }
742
5e1746d6 743 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 744 return 1;
a03490ed 745
ad756a16
MJ		 746 if (((cr4 ^ old_cr4) & pdptr_bits) ||
747 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 748 kvm_mmu_reset_context(vcpu);
0f12244f 749
2acf923e 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 751 kvm_update_cpuid(vcpu);
2acf923e 752
0f12244f
GN		 753 return 0;
754}
2d3ad1f4 755EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 756
2390218b 757int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 758{
ac146235 759#ifdef CONFIG_X86_64
9d88fca7 760 cr3 &= ~CR3_PCID_INVD;
ac146235 761#endif
9d88fca7 762
9f8fe504 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 764 kvm_mmu_sync_roots(vcpu);
77c3913b 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 766 return 0;
d835dfec
AK		 767 }
768
a03490ed 769 if (is_long_mode(vcpu)) {
d9f89b88
JK		 770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 774 return 1;
a03490ed 775
0f12244f 776 vcpu->arch.cr3 = cr3;
aff48baa 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 778 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 782
eea1cff9 783int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 784{
0f12244f
GN		 785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
a03490ed
CO		 787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
ad312c7c 790 vcpu->arch.cr8 = cr8;
0f12244f
GN		 791 return 0;
792}
2d3ad1f4 793EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 794
2d3ad1f4 795unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 796{
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
ad312c7c 800 return vcpu->arch.cr8;
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 803
ae561ede
NA		 804static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805{
806 int i;
807
808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809 for (i = 0; i < KVM_NR_DB_REGS; i++)
810 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 }
813}
814
73aaf249
JK		 815static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816{
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819}
820
c8639010
JK		 821static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822{
823 unsigned long dr7;
824
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 dr7 = vcpu->arch.guest_debug_dr7;
827 else
828 dr7 = vcpu->arch.dr7;
829 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831 if (dr7 & DR7_BP_EN_MASK)
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 833}
834
6f43ed01
NA		 835static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836{
837 u64 fixed = DR6_FIXED_1;
838
839 if (!guest_cpuid_has_rtm(vcpu))
840 fixed |= DR6_RTM;
841 return fixed;
842}
843
338dbc97 844static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 vcpu->arch.db[dr] = val;
849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850 vcpu->arch.eff_db[dr] = val;
851 break;
852 case 4:
020df079
GN		 853 /* fall through */
854 case 6:
338dbc97
GN		 855 if (val & 0xffffffff00000000ULL)
856 return -1; /* #GP */
6f43ed01 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 858 kvm_update_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
020df079
GN		 861 /* fall through */
862 default: /* 7 */
338dbc97
GN		 863 if (val & 0xffffffff00000000ULL)
864 return -1; /* #GP */
020df079 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 866 kvm_update_dr7(vcpu);
020df079
GN		 867 break;
868 }
869
870 return 0;
871}
338dbc97
GN		 872
873int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874{
16f8a6f9 875 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 876 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 877 return 1;
878 }
879 return 0;
338dbc97 880}
020df079
GN		 881EXPORT_SYMBOL_GPL(kvm_set_dr);
882
16f8a6f9 883int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 884{
885 switch (dr) {
886 case 0 ... 3:
887 *val = vcpu->arch.db[dr];
888 break;
889 case 4:
020df079
GN		 890 /* fall through */
891 case 6:
73aaf249
JK		 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893 *val = vcpu->arch.dr6;
894 else
895 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 896 break;
897 case 5:
020df079
GN		 898 /* fall through */
899 default: /* 7 */
900 *val = vcpu->arch.dr7;
901 break;
902 }
338dbc97
GN		 903 return 0;
904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_get_dr);
906
022cd0e8
AK		 907bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908{
909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 u64 data;
911 int err;
912
913 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914 if (err)
915 return err;
916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918 return err;
919}
920EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
043405e1
CO		 922/*
923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925 *
926 * This list is modified at module load time to reflect the
e3267cbb
GC		 927 * capabilities of the host cpu. This capabilities test skips MSRs that are
928 * kvm-specific. Those are put in the beginning of the list.
043405e1 929 */
e3267cbb 930
e984097b 931#define KVM_SAVE_MSRS_BEGIN 12
043405e1 932static u32 msrs_to_save[] = {
e3267cbb 933 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 934 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 935 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 936 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 937 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 938 MSR_KVM_PV_EOI_EN,
043405e1 939 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 940 MSR_STAR,
043405e1
CO		 941#ifdef CONFIG_X86_64
942 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
943#endif
b3897a49 944 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 945 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 946};
947
948static unsigned num_msrs_to_save;
949
f1d24831 950static const u32 emulated_msrs[] = {
ba904635 951 MSR_IA32_TSC_ADJUST,
a3e06bbe 952 MSR_IA32_TSCDEADLINE,
043405e1 953 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 954 MSR_IA32_MCG_STATUS,
955 MSR_IA32_MCG_CTL,
043405e1
CO		 956};
957
384bb783 958bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 959{
b69e8cae 960 if (efer & efer_reserved_bits)
384bb783 961 return false;
15c4a640 962
1b2fd70c
AG		 963 if (efer & EFER_FFXSR) {
964 struct kvm_cpuid_entry2 *feat;
965
966 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 967 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 968 return false;
1b2fd70c
AG		 969 }
970
d8017474
AG		 971 if (efer & EFER_SVME) {
972 struct kvm_cpuid_entry2 *feat;
973
974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 975 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 976 return false;
d8017474
AG		 977 }
978
384bb783
JK		 979 return true;
980}
981EXPORT_SYMBOL_GPL(kvm_valid_efer);
982
983static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
984{
985 u64 old_efer = vcpu->arch.efer;
986
987 if (!kvm_valid_efer(vcpu, efer))
988 return 1;
989
990 if (is_paging(vcpu)
991 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
992 return 1;
993
15c4a640 994 efer &= ~EFER_LMA;
f6801dff 995 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 996
a3d204e2
SY		 997 kvm_x86_ops->set_efer(vcpu, efer);
998
aad82703
SY		 999 /* Update reserved bits */
1000 if ((efer ^ old_efer) & EFER_NX)
1001 kvm_mmu_reset_context(vcpu);
1002
b69e8cae 1003 return 0;
15c4a640
CO		 1004}
1005
f2b4b7dd
JR		 1006void kvm_enable_efer_bits(u64 mask)
1007{
1008 efer_reserved_bits &= ~mask;
1009}
1010EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1011
15c4a640
CO		 1012/*
1013 * Writes msr value into into the appropriate "register".
1014 * Returns 0 on success, non-0 otherwise.
1015 * Assumes vcpu_load() was already called.
1016 */
8fe8ab46 1017int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1018{
854e8bb1
NA		 1019 switch (msr->index) {
1020 case MSR_FS_BASE:
1021 case MSR_GS_BASE:
1022 case MSR_KERNEL_GS_BASE:
1023 case MSR_CSTAR:
1024 case MSR_LSTAR:
1025 if (is_noncanonical_address(msr->data))
1026 return 1;
1027 break;
1028 case MSR_IA32_SYSENTER_EIP:
1029 case MSR_IA32_SYSENTER_ESP:
1030 /*
1031 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1032 * non-canonical address is written on Intel but not on
1033 * AMD (which ignores the top 32-bits, because it does
1034 * not implement 64-bit SYSENTER).
1035 *
1036 * 64-bit code should hence be able to write a non-canonical
1037 * value on AMD. Making the address canonical ensures that
1038 * vmentry does not fail on Intel after writing a non-canonical
1039 * value, and that something deterministic happens if the guest
1040 * invokes 64-bit SYSENTER.
1041 */
1042 msr->data = get_canonical(msr->data);
1043 }
8fe8ab46 1044 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1045}
854e8bb1 1046EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1047
313a3dc7
CO		 1048/*
1049 * Adapt set_msr() to msr_io()'s calling convention
1050 */
1051static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1052{
8fe8ab46
WA		 1053 struct msr_data msr;
1054
1055 msr.data = *data;
1056 msr.index = index;
1057 msr.host_initiated = true;
1058 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1059}
1060
16e8d74d
MT		 1061#ifdef CONFIG_X86_64
1062struct pvclock_gtod_data {
1063 seqcount_t seq;
1064
1065 struct { /* extract of a clocksource struct */
1066 int vclock_mode;
1067 cycle_t cycle_last;
1068 cycle_t mask;
1069 u32 mult;
1070 u32 shift;
1071 } clock;
1072
cbcf2dd3
TG		 1073 u64 boot_ns;
1074 u64 nsec_base;
16e8d74d
MT		 1075};
1076
1077static struct pvclock_gtod_data pvclock_gtod_data;
1078
1079static void update_pvclock_gtod(struct timekeeper *tk)
1080{
1081 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1082 u64 boot_ns;
1083
876e7881 1084 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1085
1086 write_seqcount_begin(&vdata->seq);
1087
1088 /* copy pvclock gtod data */
876e7881
PZ		 1089 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1090 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1091 vdata->clock.mask = tk->tkr_mono.mask;
1092 vdata->clock.mult = tk->tkr_mono.mult;
1093 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1094
cbcf2dd3 1095 vdata->boot_ns = boot_ns;
876e7881 1096 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1097
1098 write_seqcount_end(&vdata->seq);
1099}
1100#endif
1101
bab5bb39
NK		 1102void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1103{
1104 /*
1105 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1106 * vcpu_enter_guest. This function is only called from
1107 * the physical CPU that is running vcpu.
1108 */
1109 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1110}
16e8d74d 1111
18068523
GOC		 1112static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1113{
9ed3c444
AK		 1114 int version;
1115 int r;
50d0a0f9 1116 struct pvclock_wall_clock wc;
923de3cf 1117 struct timespec boot;
18068523
GOC		 1118
1119 if (!wall_clock)
1120 return;
1121
9ed3c444
AK		 1122 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1123 if (r)
1124 return;
1125
1126 if (version & 1)
1127 ++version; /* first time write, random junk */
1128
1129 ++version;
18068523 1130
18068523
GOC		 1131 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1132
50d0a0f9
GH		 1133 /*
1134 * The guest calculates current wall clock time by adding
34c238a1 1135 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1136 * wall clock specified here. guest system time equals host
1137 * system time for us, thus we must fill in host boot time here.
1138 */
923de3cf 1139 getboottime(&boot);
50d0a0f9 1140
4b648665
BR		 1141 if (kvm->arch.kvmclock_offset) {
1142 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1143 boot = timespec_sub(boot, ts);
1144 }
50d0a0f9
GH		 1145 wc.sec = boot.tv_sec;
1146 wc.nsec = boot.tv_nsec;
1147 wc.version = version;
18068523
GOC		 1148
1149 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1150
1151 version++;
1152 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1153}
1154
50d0a0f9
GH		 1155static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1156{
1157 uint32_t quotient, remainder;
1158
1159 /* Don't try to replace with do_div(), this one calculates
1160 * "(dividend << 32) / divisor" */
1161 __asm__ ( "divl %4"
1162 : "=a" (quotient), "=d" (remainder)
1163 : "0" (0), "1" (dividend), "r" (divisor) );
1164 return quotient;
1165}
1166
5f4e3f88
ZA		 1167static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1168 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1169{
5f4e3f88 1170 uint64_t scaled64;
50d0a0f9
GH		 1171 int32_t shift = 0;
1172 uint64_t tps64;
1173 uint32_t tps32;
1174
5f4e3f88
ZA		 1175 tps64 = base_khz * 1000LL;
1176 scaled64 = scaled_khz * 1000LL;
50933623 1177 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1178 tps64 >>= 1;
1179 shift--;
1180 }
1181
1182 tps32 = (uint32_t)tps64;
50933623
JK		 1183 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1184 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1185 scaled64 >>= 1;
1186 else
1187 tps32 <<= 1;
50d0a0f9
GH		 1188 shift++;
1189 }
1190
5f4e3f88
ZA		 1191 *pshift = shift;
1192 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1193
5f4e3f88
ZA		 1194 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1195 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1196}
1197
759379dd
ZA		 1198static inline u64 get_kernel_ns(void)
1199{
bb0b5812 1200 return ktime_get_boot_ns();
50d0a0f9
GH		 1201}
1202
d828199e 1203#ifdef CONFIG_X86_64
16e8d74d 1204static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1205#endif
16e8d74d 1206
c8076604 1207static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1208static unsigned long max_tsc_khz;
c8076604 1209
cc578287 1210static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1211{
cc578287
ZA		 1212 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1213 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1214}
1215
cc578287 1216static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1217{
cc578287
ZA		 1218 u64 v = (u64)khz * (1000000 + ppm);
1219 do_div(v, 1000000);
1220 return v;
1e993611
JR		 1221}
1222
cc578287 1223static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1224{
cc578287
ZA		 1225 u32 thresh_lo, thresh_hi;
1226 int use_scaling = 0;
217fc9cf 1227
03ba32ca
MT		 1228 /* tsc_khz can be zero if TSC calibration fails */
1229 if (this_tsc_khz == 0)
1230 return;
1231
c285545f
ZA		 1232 /* Compute a scale to convert nanoseconds in TSC cycles */
1233 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1234 &vcpu->arch.virtual_tsc_shift,
1235 &vcpu->arch.virtual_tsc_mult);
1236 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1237
1238 /*
1239 * Compute the variation in TSC rate which is acceptable
1240 * within the range of tolerance and decide if the
1241 * rate being applied is within that bounds of the hardware
1242 * rate. If so, no scaling or compensation need be done.
1243 */
1244 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1245 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1246 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1247 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1248 use_scaling = 1;
1249 }
1250 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1251}
1252
1253static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1254{
e26101b1 1255 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1256 vcpu->arch.virtual_tsc_mult,
1257 vcpu->arch.virtual_tsc_shift);
e26101b1 1258 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1259 return tsc;
1260}
1261
69b0049a 1262static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1263{
1264#ifdef CONFIG_X86_64
1265 bool vcpus_matched;
b48aa97e
MT		 1266 struct kvm_arch *ka = &vcpu->kvm->arch;
1267 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1268
1269 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1270 atomic_read(&vcpu->kvm->online_vcpus));
1271
7f187922
MT		 1272 /*
1273 * Once the masterclock is enabled, always perform request in
1274 * order to update it.
1275 *
1276 * In order to enable masterclock, the host clocksource must be TSC
1277 * and the vcpus need to have matched TSCs. When that happens,
1278 * perform request to enable masterclock.
1279 */
1280 if (ka->use_master_clock ||
1281 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1282 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1283
1284 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1285 atomic_read(&vcpu->kvm->online_vcpus),
1286 ka->use_master_clock, gtod->clock.vclock_mode);
1287#endif
1288}
1289
ba904635
WA		 1290static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1291{
1292 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1293 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1294}
1295
8fe8ab46 1296void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1297{
1298 struct kvm *kvm = vcpu->kvm;
f38e098f 1299 u64 offset, ns, elapsed;
99e3e30a 1300 unsigned long flags;
02626b6a 1301 s64 usdiff;
b48aa97e 1302 bool matched;
0d3da0d2 1303 bool already_matched;
8fe8ab46 1304 u64 data = msr->data;
99e3e30a 1305
038f8c11 1306 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1308 ns = get_kernel_ns();
f38e098f 1309 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1310
03ba32ca 1311 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1312 int faulted = 0;
1313
03ba32ca
MT		 1314 /* n.b - signed multiplication and division required */
1315 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1316#ifdef CONFIG_X86_64
03ba32ca 1317 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1318#else
03ba32ca 1319 /* do_div() only does unsigned */
8915aa27
MT		 1320 asm("1: idivl %[divisor]\n"
1321 "2: xor %%edx, %%edx\n"
1322 " movl $0, %[faulted]\n"
1323 "3:\n"
1324 ".section .fixup,\"ax\"\n"
1325 "4: movl $1, %[faulted]\n"
1326 " jmp 3b\n"
1327 ".previous\n"
1328
1329 _ASM_EXTABLE(1b, 4b)
1330
1331 : "=A"(usdiff), [faulted] "=r" (faulted)
1332 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1333
5d3cb0f6 1334#endif
03ba32ca
MT		 1335 do_div(elapsed, 1000);
1336 usdiff -= elapsed;
1337 if (usdiff < 0)
1338 usdiff = -usdiff;
8915aa27
MT		 1339
1340 /* idivl overflow => difference is larger than USEC_PER_SEC */
1341 if (faulted)
1342 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1343 } else
1344 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1345
1346 /*
5d3cb0f6
ZA		 1347 * Special case: TSC write with a small delta (1 second) of virtual
1348 * cycle time against real time is interpreted as an attempt to
1349 * synchronize the CPU.
1350 *
1351 * For a reliable TSC, we can match TSC offsets, and for an unstable
1352 * TSC, we add elapsed time in this computation. We could let the
1353 * compensation code attempt to catch up if we fall behind, but
1354 * it's better to try to match offsets from the beginning.
1355 */
02626b6a 1356 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1357 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1358 if (!check_tsc_unstable()) {
e26101b1 1359 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1360 pr_debug("kvm: matched tsc offset for %llu\n", data);
1361 } else {
857e4099 1362 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1363 data += delta;
1364 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1365 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1366 }
b48aa97e 1367 matched = true;
0d3da0d2 1368 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1369 } else {
1370 /*
1371 * We split periods of matched TSC writes into generations.
1372 * For each generation, we track the original measured
1373 * nanosecond time, offset, and write, so if TSCs are in
1374 * sync, we can match exact offset, and if not, we can match
4a969980 1375 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1376 *
1377 * These values are tracked in kvm->arch.cur_xxx variables.
1378 */
1379 kvm->arch.cur_tsc_generation++;
1380 kvm->arch.cur_tsc_nsec = ns;
1381 kvm->arch.cur_tsc_write = data;
1382 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1383 matched = false;
0d3da0d2 1384 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1385 kvm->arch.cur_tsc_generation, data);
f38e098f 1386 }
e26101b1
ZA		 1387
1388 /*
1389 * We also track th most recent recorded KHZ, write and time to
1390 * allow the matching interval to be extended at each write.
1391 */
f38e098f
ZA		 1392 kvm->arch.last_tsc_nsec = ns;
1393 kvm->arch.last_tsc_write = data;
5d3cb0f6 1394 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1395
b183aa58 1396 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1397
1398 /* Keep track of which generation this VCPU has synchronized to */
1399 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1400 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1401 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1402
ba904635
WA		 1403 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1404 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1405 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1406 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1407
1408 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1409 if (!matched) {
b48aa97e 1410 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1411 } else if (!already_matched) {
1412 kvm->arch.nr_vcpus_matched_tsc++;
1413 }
b48aa97e
MT		 1414
1415 kvm_track_tsc_matching(vcpu);
1416 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1417}
e26101b1 1418
99e3e30a
ZA		 1419EXPORT_SYMBOL_GPL(kvm_write_tsc);
1420
d828199e
MT		 1421#ifdef CONFIG_X86_64
1422
1423static cycle_t read_tsc(void)
1424{
1425 cycle_t ret;
1426 u64 last;
1427
1428 /*
1429 * Empirically, a fence (of type that depends on the CPU)
1430 * before rdtsc is enough to ensure that rdtsc is ordered
1431 * with respect to loads. The various CPU manuals are unclear
1432 * as to whether rdtsc can be reordered with later loads,
1433 * but no one has ever seen it happen.
1434 */
1435 rdtsc_barrier();
1436 ret = (cycle_t)vget_cycles();
1437
1438 last = pvclock_gtod_data.clock.cycle_last;
1439
1440 if (likely(ret >= last))
1441 return ret;
1442
1443 /*
1444 * GCC likes to generate cmov here, but this branch is extremely
1445 * predictable (it's just a funciton of time and the likely is
1446 * very likely) and there's a data dependence, so force GCC
1447 * to generate a branch instead. I don't barrier() because
1448 * we don't actually need a barrier, and if this function
1449 * ever gets inlined it will generate worse code.
1450 */
1451 asm volatile ("");
1452 return last;
1453}
1454
1455static inline u64 vgettsc(cycle_t *cycle_now)
1456{
1457 long v;
1458 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1459
1460 *cycle_now = read_tsc();
1461
1462 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1463 return v * gtod->clock.mult;
1464}
1465
cbcf2dd3 1466static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1467{
cbcf2dd3 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1469 unsigned long seq;
d828199e 1470 int mode;
cbcf2dd3 1471 u64 ns;
d828199e 1472
d828199e
MT		 1473 do {
1474 seq = read_seqcount_begin(&gtod->seq);
1475 mode = gtod->clock.vclock_mode;
cbcf2dd3 1476 ns = gtod->nsec_base;
d828199e
MT		 1477 ns += vgettsc(cycle_now);
1478 ns >>= gtod->clock.shift;
cbcf2dd3 1479 ns += gtod->boot_ns;
d828199e 1480 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1481 *t = ns;
d828199e
MT		 1482
1483 return mode;
1484}
1485
1486/* returns true if host is using tsc clocksource */
1487static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1488{
d828199e
MT		 1489 /* checked again under seqlock below */
1490 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1491 return false;
1492
cbcf2dd3 1493 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1494}
1495#endif
1496
1497/*
1498 *
b48aa97e
MT		 1499 * Assuming a stable TSC across physical CPUS, and a stable TSC
1500 * across virtual CPUs, the following condition is possible.
1501 * Each numbered line represents an event visible to both
d828199e
MT		 1502 * CPUs at the next numbered event.
1503 *
1504 * "timespecX" represents host monotonic time. "tscX" represents
1505 * RDTSC value.
1506 *
1507 * VCPU0 on CPU0 | VCPU1 on CPU1
1508 *
1509 * 1. read timespec0,tsc0
1510 * 2. | timespec1 = timespec0 + N
1511 * | tsc1 = tsc0 + M
1512 * 3. transition to guest | transition to guest
1513 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1514 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1515 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1516 *
1517 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1518 *
1519 * - ret0 < ret1
1520 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1521 * ...
1522 * - 0 < N - M => M < N
1523 *
1524 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1525 * always the case (the difference between two distinct xtime instances
1526 * might be smaller then the difference between corresponding TSC reads,
1527 * when updating guest vcpus pvclock areas).
1528 *
1529 * To avoid that problem, do not allow visibility of distinct
1530 * system_timestamp/tsc_timestamp values simultaneously: use a master
1531 * copy of host monotonic time values. Update that master copy
1532 * in lockstep.
1533 *
b48aa97e 1534 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1535 *
1536 */
1537
1538static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1539{
1540#ifdef CONFIG_X86_64
1541 struct kvm_arch *ka = &kvm->arch;
1542 int vclock_mode;
b48aa97e
MT		 1543 bool host_tsc_clocksource, vcpus_matched;
1544
1545 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1546 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1547
1548 /*
1549 * If the host uses TSC clock, then passthrough TSC as stable
1550 * to the guest.
1551 */
b48aa97e 1552 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1553 &ka->master_kernel_ns,
1554 &ka->master_cycle_now);
1555
16a96021 1556 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1557 && !backwards_tsc_observed
1558 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1559
d828199e
MT		 1560 if (ka->use_master_clock)
1561 atomic_set(&kvm_guest_has_master_clock, 1);
1562
1563 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1564 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1565 vcpus_matched);
d828199e
MT		 1566#endif
1567}
1568
2e762ff7
MT		 1569static void kvm_gen_update_masterclock(struct kvm *kvm)
1570{
1571#ifdef CONFIG_X86_64
1572 int i;
1573 struct kvm_vcpu *vcpu;
1574 struct kvm_arch *ka = &kvm->arch;
1575
1576 spin_lock(&ka->pvclock_gtod_sync_lock);
1577 kvm_make_mclock_inprogress_request(kvm);
1578 /* no guest entries from this point */
1579 pvclock_update_vm_gtod_copy(kvm);
1580
1581 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1582 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1583
1584 /* guest entries allowed */
1585 kvm_for_each_vcpu(i, vcpu, kvm)
1586 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1587
1588 spin_unlock(&ka->pvclock_gtod_sync_lock);
1589#endif
1590}
1591
34c238a1 1592static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1593{
d828199e 1594 unsigned long flags, this_tsc_khz;
18068523 1595 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1596 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1597 s64 kernel_ns;
d828199e 1598 u64 tsc_timestamp, host_tsc;
0b79459b 1599 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1600 u8 pvclock_flags;
d828199e
MT		 1601 bool use_master_clock;
1602
1603 kernel_ns = 0;
1604 host_tsc = 0;
18068523 1605
d828199e
MT		 1606 /*
1607 * If the host uses TSC clock, then passthrough TSC as stable
1608 * to the guest.
1609 */
1610 spin_lock(&ka->pvclock_gtod_sync_lock);
1611 use_master_clock = ka->use_master_clock;
1612 if (use_master_clock) {
1613 host_tsc = ka->master_cycle_now;
1614 kernel_ns = ka->master_kernel_ns;
1615 }
1616 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1617
1618 /* Keep irq disabled to prevent changes to the clock */
1619 local_irq_save(flags);
89cbc767 1620 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1621 if (unlikely(this_tsc_khz == 0)) {
1622 local_irq_restore(flags);
1623 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1624 return 1;
1625 }
d828199e
MT		 1626 if (!use_master_clock) {
1627 host_tsc = native_read_tsc();
1628 kernel_ns = get_kernel_ns();
1629 }
1630
1631 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1632
c285545f
ZA		 1633 /*
1634 * We may have to catch up the TSC to match elapsed wall clock
1635 * time for two reasons, even if kvmclock is used.
1636 * 1) CPU could have been running below the maximum TSC rate
1637 * 2) Broken TSC compensation resets the base at each VCPU
1638 * entry to avoid unknown leaps of TSC even when running
1639 * again on the same CPU. This may cause apparent elapsed
1640 * time to disappear, and the guest to stand still or run
1641 * very slowly.
1642 */
1643 if (vcpu->tsc_catchup) {
1644 u64 tsc = compute_guest_tsc(v, kernel_ns);
1645 if (tsc > tsc_timestamp) {
f1e2b260 1646 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1647 tsc_timestamp = tsc;
1648 }
50d0a0f9
GH		 1649 }
1650
18068523
GOC		 1651 local_irq_restore(flags);
1652
0b79459b 1653 if (!vcpu->pv_time_enabled)
c285545f 1654 return 0;
18068523 1655
e48672fa 1656 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1657 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1658 &vcpu->hv_clock.tsc_shift,
1659 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1660 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1661 }
1662
1663 /* With all the info we got, fill in the values */
1d5f066e 1664 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1665 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1666 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1667
09a0c3f1
OH		 1668 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1669 &guest_hv_clock, sizeof(guest_hv_clock))))
1670 return 0;
1671
5dca0d91
RK		 1672 /* This VCPU is paused, but it's legal for a guest to read another
1673 * VCPU's kvmclock, so we really have to follow the specification where
1674 * it says that version is odd if data is being modified, and even after
1675 * it is consistent.
1676 *
1677 * Version field updates must be kept separate. This is because
1678 * kvm_write_guest_cached might use a "rep movs" instruction, and
1679 * writes within a string instruction are weakly ordered. So there
1680 * are three writes overall.
1681 *
1682 * As a small optimization, only write the version field in the first
1683 * and third write. The vcpu->pv_time cache is still valid, because the
1684 * version field is the first in the struct.
18068523 1685 */
5dca0d91
RK		 1686 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1687
1688 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1689 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1690 &vcpu->hv_clock,
1691 sizeof(vcpu->hv_clock.version));
1692
1693 smp_wmb();
78c0337a
MT		 1694
1695 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1696 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1697
1698 if (vcpu->pvclock_set_guest_stopped_request) {
1699 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1700 vcpu->pvclock_set_guest_stopped_request = false;
1701 }
1702
b7e60c5a
MT		 1703 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1704
d828199e
MT		 1705 /* If the host uses TSC clocksource, then it is stable */
1706 if (use_master_clock)
1707 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1708
78c0337a
MT		 1709 vcpu->hv_clock.flags = pvclock_flags;
1710
ce1a5e60
DM		 1711 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1712
0b79459b
AH		 1713 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1714 &vcpu->hv_clock,
1715 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1716
1717 smp_wmb();
1718
1719 vcpu->hv_clock.version++;
1720 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1721 &vcpu->hv_clock,
1722 sizeof(vcpu->hv_clock.version));
8cfdc000 1723 return 0;
c8076604
GH		 1724}
1725
0061d53d
MT		 1726/*
1727 * kvmclock updates which are isolated to a given vcpu, such as
1728 * vcpu->cpu migration, should not allow system_timestamp from
1729 * the rest of the vcpus to remain static. Otherwise ntp frequency
1730 * correction applies to one vcpu's system_timestamp but not
1731 * the others.
1732 *
1733 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1734 * We need to rate-limit these requests though, as they can
1735 * considerably slow guests that have a large number of vcpus.
1736 * The time for a remote vcpu to update its kvmclock is bound
1737 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1738 */
1739
7e44e449
AJ		 1740#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1741
1742static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1743{
1744 int i;
7e44e449
AJ		 1745 struct delayed_work *dwork = to_delayed_work(work);
1746 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1747 kvmclock_update_work);
1748 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1749 struct kvm_vcpu *vcpu;
1750
1751 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1753 kvm_vcpu_kick(vcpu);
1754 }
1755}
1756
7e44e449
AJ		 1757static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1758{
1759 struct kvm *kvm = v->kvm;
1760
105b21bb 1761 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1762 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1763 KVMCLOCK_UPDATE_DELAY);
1764}
1765
332967a3
AJ		 1766#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1767
1768static void kvmclock_sync_fn(struct work_struct *work)
1769{
1770 struct delayed_work *dwork = to_delayed_work(work);
1771 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1772 kvmclock_sync_work);
1773 struct kvm *kvm = container_of(ka, struct kvm, arch);
1774
630994b3
MT		 1775 if (!kvmclock_periodic_sync)
1776 return;
1777
332967a3
AJ		 1778 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1779 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1780 KVMCLOCK_SYNC_PERIOD);
1781}
1782
9ba075a6
AK		 1783static bool msr_mtrr_valid(unsigned msr)
1784{
1785 switch (msr) {
1786 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1787 case MSR_MTRRfix64K_00000:
1788 case MSR_MTRRfix16K_80000:
1789 case MSR_MTRRfix16K_A0000:
1790 case MSR_MTRRfix4K_C0000:
1791 case MSR_MTRRfix4K_C8000:
1792 case MSR_MTRRfix4K_D0000:
1793 case MSR_MTRRfix4K_D8000:
1794 case MSR_MTRRfix4K_E0000:
1795 case MSR_MTRRfix4K_E8000:
1796 case MSR_MTRRfix4K_F0000:
1797 case MSR_MTRRfix4K_F8000:
1798 case MSR_MTRRdefType:
1799 case MSR_IA32_CR_PAT:
1800 return true;
1801 case 0x2f8:
1802 return true;
1803 }
1804 return false;
1805}
1806
d6289b93
MT		 1807static bool valid_pat_type(unsigned t)
1808{
1809 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1810}
1811
1812static bool valid_mtrr_type(unsigned t)
1813{
1814 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1815}
1816
4566654b 1817bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1818{
1819 int i;
fd275235 1820 u64 mask;
d6289b93
MT		 1821
1822 if (!msr_mtrr_valid(msr))
1823 return false;
1824
1825 if (msr == MSR_IA32_CR_PAT) {
1826 for (i = 0; i < 8; i++)
1827 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1828 return false;
1829 return true;
1830 } else if (msr == MSR_MTRRdefType) {
1831 if (data & ~0xcff)
1832 return false;
1833 return valid_mtrr_type(data & 0xff);
1834 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1835 for (i = 0; i < 8 ; i++)
1836 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1837 return false;
1838 return true;
1839 }
1840
1841 /* variable MTRRs */
adfb5d27
WL		 1842 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1843
fd275235 1844 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1845 if ((msr & 1) == 0) {
adfb5d27 1846 /* MTRR base */
d7a2a246
WL		 1847 if (!valid_mtrr_type(data & 0xff))
1848 return false;
1849 mask |= 0xf00;
1850 } else
1851 /* MTRR mask */
1852 mask |= 0x7ff;
1853 if (data & mask) {
1854 kvm_inject_gp(vcpu, 0);
1855 return false;
1856 }
1857
adfb5d27 1858 return true;
d6289b93 1859}
4566654b 1860EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1861
efdfe536
XG		 1862static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr)
1863{
1864 struct mtrr_state_type *mtrr_state = &vcpu->arch.mtrr_state;
1865 unsigned char mtrr_enabled = mtrr_state->enabled;
1866 gfn_t start, end, mask;
1867 int index;
1868 bool is_fixed = true;
1869
1870 if (msr == MSR_IA32_CR_PAT || !tdp_enabled ||
1871 !kvm_arch_has_noncoherent_dma(vcpu->kvm))
1872 return;
1873
1874 if (!(mtrr_enabled & 0x2) && msr != MSR_MTRRdefType)
1875 return;
1876
1877 switch (msr) {
1878 case MSR_MTRRfix64K_00000:
1879 start = 0x0;
1880 end = 0x80000;
1881 break;
1882 case MSR_MTRRfix16K_80000:
1883 start = 0x80000;
1884 end = 0xa0000;
1885 break;
1886 case MSR_MTRRfix16K_A0000:
1887 start = 0xa0000;
1888 end = 0xc0000;
1889 break;
1890 case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000:
1891 index = msr - MSR_MTRRfix4K_C0000;
1892 start = 0xc0000 + index * (32 << 10);
1893 end = start + (32 << 10);
1894 break;
1895 case MSR_MTRRdefType:
1896 is_fixed = false;
1897 start = 0x0;
1898 end = ~0ULL;
1899 break;
1900 default:
1901 /* variable range MTRRs. */
1902 is_fixed = false;
1903 index = (msr - 0x200) / 2;
1904 start = (((u64)mtrr_state->var_ranges[index].base_hi) << 32) +
1905 (mtrr_state->var_ranges[index].base_lo & PAGE_MASK);
1906 mask = (((u64)mtrr_state->var_ranges[index].mask_hi) << 32) +
1907 (mtrr_state->var_ranges[index].mask_lo & PAGE_MASK);
1908 mask |= ~0ULL << cpuid_maxphyaddr(vcpu);
1909
1910 end = ((start & mask) | ~mask) + 1;
1911 }
1912
1913 if (is_fixed && !(mtrr_enabled & 0x1))
1914 return;
1915
1916 kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end));
1917}
1918
9ba075a6
AK		 1919static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1920{
0bed3b56
SY		 1921 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1922
4566654b 1923 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1924 return 1;
1925
0bed3b56
SY		 1926 if (msr == MSR_MTRRdefType) {
1927 vcpu->arch.mtrr_state.def_type = data;
1928 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1929 } else if (msr == MSR_MTRRfix64K_00000)
1930 p[0] = data;
1931 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1932 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1933 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1934 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1935 else if (msr == MSR_IA32_CR_PAT)
1936 vcpu->arch.pat = data;
1937 else { /* Variable MTRRs */
1938 int idx, is_mtrr_mask;
1939 u64 *pt;
1940
1941 idx = (msr - 0x200) / 2;
1942 is_mtrr_mask = msr - 0x200 - 2 * idx;
1943 if (!is_mtrr_mask)
1944 pt =
1945 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1946 else
1947 pt =
1948 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1949 *pt = data;
1950 }
1951
efdfe536 1952 update_mtrr(vcpu, msr);
9ba075a6
AK		 1953 return 0;
1954}
15c4a640 1955
890ca9ae 1956static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1957{
890ca9ae
HY		 1958 u64 mcg_cap = vcpu->arch.mcg_cap;
1959 unsigned bank_num = mcg_cap & 0xff;
1960
15c4a640 1961 switch (msr) {
15c4a640 1962 case MSR_IA32_MCG_STATUS:
890ca9ae 1963 vcpu->arch.mcg_status = data;
15c4a640 1964 break;
c7ac679c 1965 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1966 if (!(mcg_cap & MCG_CTL_P))
1967 return 1;
1968 if (data != 0 && data != ~(u64)0)
1969 return -1;
1970 vcpu->arch.mcg_ctl = data;
1971 break;
1972 default:
1973 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1974 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1975 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1976 /* only 0 or all 1s can be written to IA32_MCi_CTL
1977 * some Linux kernels though clear bit 10 in bank 4 to
1978 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1979 * this to avoid an uncatched #GP in the guest
1980 */
890ca9ae 1981 if ((offset & 0x3) == 0 &&
114be429 1982 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1983 return -1;
1984 vcpu->arch.mce_banks[offset] = data;
1985 break;
1986 }
1987 return 1;
1988 }
1989 return 0;
1990}
1991
ffde22ac
ES		 1992static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1993{
1994 struct kvm *kvm = vcpu->kvm;
1995 int lm = is_long_mode(vcpu);
1996 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1997 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1998 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1999 : kvm->arch.xen_hvm_config.blob_size_32;
2000 u32 page_num = data & ~PAGE_MASK;
2001 u64 page_addr = data & PAGE_MASK;
2002 u8 *page;
2003 int r;
2004
2005 r = -E2BIG;
2006 if (page_num >= blob_size)
2007 goto out;
2008 r = -ENOMEM;
ff5c2c03
SL		 2009 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2010 if (IS_ERR(page)) {
2011 r = PTR_ERR(page);
ffde22ac 2012 goto out;
ff5c2c03 2013 }
ffde22ac
ES		 2014 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
2015 goto out_free;
2016 r = 0;
2017out_free:
2018 kfree(page);
2019out:
2020 return r;
2021}
2022
55cd8e5a
GN		 2023static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
2024{
2025 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
2026}
2027
2028static bool kvm_hv_msr_partition_wide(u32 msr)
2029{
2030 bool r = false;
2031 switch (msr) {
2032 case HV_X64_MSR_GUEST_OS_ID:
2033 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 2034 case HV_X64_MSR_REFERENCE_TSC:
2035 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 2036 r = true;
2037 break;
2038 }
2039
2040 return r;
2041}
2042
2043static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2044{
2045 struct kvm *kvm = vcpu->kvm;
2046
2047 switch (msr) {
2048 case HV_X64_MSR_GUEST_OS_ID:
2049 kvm->arch.hv_guest_os_id = data;
2050 /* setting guest os id to zero disables hypercall page */
2051 if (!kvm->arch.hv_guest_os_id)
2052 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
2053 break;
2054 case HV_X64_MSR_HYPERCALL: {
2055 u64 gfn;
2056 unsigned long addr;
2057 u8 instructions[4];
2058
2059 /* if guest os id is not set hypercall should remain disabled */
2060 if (!kvm->arch.hv_guest_os_id)
2061 break;
2062 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2063 kvm->arch.hv_hypercall = data;
2064 break;
2065 }
2066 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2067 addr = gfn_to_hva(kvm, gfn);
2068 if (kvm_is_error_hva(addr))
2069 return 1;
2070 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2071 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2072 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2073 return 1;
2074 kvm->arch.hv_hypercall = data;
b94b64c9 2075 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2076 break;
2077 }
e984097b
VR		 2078 case HV_X64_MSR_REFERENCE_TSC: {
2079 u64 gfn;
2080 HV_REFERENCE_TSC_PAGE tsc_ref;
2081 memset(&tsc_ref, 0, sizeof(tsc_ref));
2082 kvm->arch.hv_tsc_page = data;
2083 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2084 break;
2085 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2086 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2087 &tsc_ref, sizeof(tsc_ref)))
2088 return 1;
2089 mark_page_dirty(kvm, gfn);
2090 break;
2091 }
55cd8e5a 2092 default:
a737f256
CD		 2093 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2094 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2095 return 1;
2096 }
2097 return 0;
2098}
2099
2100static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2101{
10388a07
GN		 2102 switch (msr) {
2103 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2104 u64 gfn;
10388a07 2105 unsigned long addr;
55cd8e5a 2106
10388a07
GN		 2107 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2108 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2109 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2110 return 1;
10388a07
GN		 2111 break;
2112 }
b3af1e88
VR		 2113 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2114 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2115 if (kvm_is_error_hva(addr))
2116 return 1;
8b0cedff 2117 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2118 return 1;
2119 vcpu->arch.hv_vapic = data;
b3af1e88 2120 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2121 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2122 return 1;
10388a07
GN		 2123 break;
2124 }
2125 case HV_X64_MSR_EOI:
2126 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2127 case HV_X64_MSR_ICR:
2128 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2129 case HV_X64_MSR_TPR:
2130 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2131 default:
a737f256
CD		 2132 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2133 "data 0x%llx\n", msr, data);
10388a07
GN		 2134 return 1;
2135 }
2136
2137 return 0;
55cd8e5a
GN		 2138}
2139
344d9588
GN		 2140static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2141{
2142 gpa_t gpa = data & ~0x3f;
2143
4a969980 2144 /* Bits 2:5 are reserved, Should be zero */
6adba527 2145 if (data & 0x3c)
344d9588
GN		 2146 return 1;
2147
2148 vcpu->arch.apf.msr_val = data;
2149
2150 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2151 kvm_clear_async_pf_completion_queue(vcpu);
2152 kvm_async_pf_hash_reset(vcpu);
2153 return 0;
2154 }
2155
8f964525
AH		 2156 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2157 sizeof(u32)))
344d9588
GN		 2158 return 1;
2159
6adba527 2160 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2161 kvm_async_pf_wakeup_all(vcpu);
2162 return 0;
2163}
2164
12f9a48f
GC		 2165static void kvmclock_reset(struct kvm_vcpu *vcpu)
2166{
0b79459b 2167 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2168}
2169
c9aaa895
GC		 2170static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2171{
2172 u64 delta;
2173
2174 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2175 return;
2176
2177 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2178 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2179 vcpu->arch.st.accum_steal = delta;
2180}
2181
2182static void record_steal_time(struct kvm_vcpu *vcpu)
2183{
2184 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2185 return;
2186
2187 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2188 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2189 return;
2190
2191 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2192 vcpu->arch.st.steal.version += 2;
2193 vcpu->arch.st.accum_steal = 0;
2194
2195 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2196 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2197}
2198
8fe8ab46 2199int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2200{
5753785f 2201 bool pr = false;
8fe8ab46
WA		 2202 u32 msr = msr_info->index;
2203 u64 data = msr_info->data;
5753785f 2204
15c4a640 2205 switch (msr) {
2e32b719
BP		 2206 case MSR_AMD64_NB_CFG:
2207 case MSR_IA32_UCODE_REV:
2208 case MSR_IA32_UCODE_WRITE:
2209 case MSR_VM_HSAVE_PA:
2210 case MSR_AMD64_PATCH_LOADER:
2211 case MSR_AMD64_BU_CFG2:
2212 break;
2213
15c4a640 2214 case MSR_EFER:
b69e8cae 2215 return set_efer(vcpu, data);
8f1589d9
AP		 2216 case MSR_K7_HWCR:
2217 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2218 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2219 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2220 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2221 if (data != 0) {
a737f256
CD		 2222 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2223 data);
8f1589d9
AP		 2224 return 1;
2225 }
15c4a640 2226 break;
f7c6d140
AP		 2227 case MSR_FAM10H_MMIO_CONF_BASE:
2228 if (data != 0) {
a737f256
CD		 2229 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2230 "0x%llx\n", data);
f7c6d140
AP		 2231 return 1;
2232 }
15c4a640 2233 break;
b5e2fec0
AG		 2234 case MSR_IA32_DEBUGCTLMSR:
2235 if (!data) {
2236 /* We support the non-activated case already */
2237 break;
2238 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2239 /* Values other than LBR and BTF are vendor-specific,
2240 thus reserved and should throw a #GP */
2241 return 1;
2242 }
a737f256
CD		 2243 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2244 __func__, data);
b5e2fec0 2245 break;
9ba075a6
AK		 2246 case 0x200 ... 0x2ff:
2247 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2248 case MSR_IA32_APICBASE:
58cb628d 2249 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2250 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2251 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2252 case MSR_IA32_TSCDEADLINE:
2253 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2254 break;
ba904635
WA		 2255 case MSR_IA32_TSC_ADJUST:
2256 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2257 if (!msr_info->host_initiated) {
d913b904 2258 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2259 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2260 }
2261 vcpu->arch.ia32_tsc_adjust_msr = data;
2262 }
2263 break;
15c4a640 2264 case MSR_IA32_MISC_ENABLE:
ad312c7c 2265 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2266 break;
11c6bffa 2267 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2268 case MSR_KVM_WALL_CLOCK:
2269 vcpu->kvm->arch.wall_clock = data;
2270 kvm_write_wall_clock(vcpu->kvm, data);
2271 break;
11c6bffa 2272 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2273 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2274 u64 gpa_offset;
54750f2c
MT		 2275 struct kvm_arch *ka = &vcpu->kvm->arch;
2276
12f9a48f 2277 kvmclock_reset(vcpu);
18068523 2278
54750f2c
MT		 2279 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2280 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2281
2282 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2283 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2284 &vcpu->requests);
2285
2286 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2287
2288 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2289 }
2290
18068523 2291 vcpu->arch.time = data;
0061d53d 2292 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2293
2294 /* we verify if the enable bit is set... */
2295 if (!(data & 1))
2296 break;
2297
0b79459b 2298 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2299
0b79459b 2300 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2301 &vcpu->arch.pv_time, data & ~1ULL,
2302 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2303 vcpu->arch.pv_time_enabled = false;
2304 else
2305 vcpu->arch.pv_time_enabled = true;
32cad84f 2306
18068523
GOC		 2307 break;
2308 }
344d9588
GN		 2309 case MSR_KVM_ASYNC_PF_EN:
2310 if (kvm_pv_enable_async_pf(vcpu, data))
2311 return 1;
2312 break;
c9aaa895
GC		 2313 case MSR_KVM_STEAL_TIME:
2314
2315 if (unlikely(!sched_info_on()))
2316 return 1;
2317
2318 if (data & KVM_STEAL_RESERVED_MASK)
2319 return 1;
2320
2321 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2322 data & KVM_STEAL_VALID_BITS,
2323 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2324 return 1;
2325
2326 vcpu->arch.st.msr_val = data;
2327
2328 if (!(data & KVM_MSR_ENABLED))
2329 break;
2330
2331 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2332
2333 preempt_disable();
2334 accumulate_steal_time(vcpu);
2335 preempt_enable();
2336
2337 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2338
2339 break;
ae7a2a3f
MT		 2340 case MSR_KVM_PV_EOI_EN:
2341 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2342 return 1;
2343 break;
c9aaa895 2344
890ca9ae
HY		 2345 case MSR_IA32_MCG_CTL:
2346 case MSR_IA32_MCG_STATUS:
81760dcc 2347 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2348 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2349
2350 /* Performance counters are not protected by a CPUID bit,
2351 * so we should check all of them in the generic path for the sake of
2352 * cross vendor migration.
2353 * Writing a zero into the event select MSRs disables them,
2354 * which we perfectly emulate ;-). Any other value should be at least
2355 * reported, some guests depend on them.
2356 */
71db6023
AP		 2357 case MSR_K7_EVNTSEL0:
2358 case MSR_K7_EVNTSEL1:
2359 case MSR_K7_EVNTSEL2:
2360 case MSR_K7_EVNTSEL3:
2361 if (data != 0)
a737f256
CD		 2362 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2363 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2364 break;
2365 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2366 * so we ignore writes to make it happy.
2367 */
71db6023
AP		 2368 case MSR_K7_PERFCTR0:
2369 case MSR_K7_PERFCTR1:
2370 case MSR_K7_PERFCTR2:
2371 case MSR_K7_PERFCTR3:
a737f256
CD		 2372 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2373 "0x%x data 0x%llx\n", msr, data);
71db6023 2374 break;
5753785f
GN		 2375 case MSR_P6_PERFCTR0:
2376 case MSR_P6_PERFCTR1:
2377 pr = true;
2378 case MSR_P6_EVNTSEL0:
2379 case MSR_P6_EVNTSEL1:
2380 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2381 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2382
2383 if (pr || data != 0)
a737f256
CD		 2384 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2385 "0x%x data 0x%llx\n", msr, data);
5753785f 2386 break;
84e0cefa
JS		 2387 case MSR_K7_CLK_CTL:
2388 /*
2389 * Ignore all writes to this no longer documented MSR.
2390 * Writes are only relevant for old K7 processors,
2391 * all pre-dating SVM, but a recommended workaround from
4a969980 2392 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2393 * affected processor models on the command line, hence
2394 * the need to ignore the workaround.
2395 */
2396 break;
55cd8e5a
GN		 2397 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2398 if (kvm_hv_msr_partition_wide(msr)) {
2399 int r;
2400 mutex_lock(&vcpu->kvm->lock);
2401 r = set_msr_hyperv_pw(vcpu, msr, data);
2402 mutex_unlock(&vcpu->kvm->lock);
2403 return r;
2404 } else
2405 return set_msr_hyperv(vcpu, msr, data);
2406 break;
91c9c3ed 2407 case MSR_IA32_BBL_CR_CTL3:
2408 /* Drop writes to this legacy MSR -- see rdmsr
2409 * counterpart for further detail.
2410 */
a737f256 2411 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2412 break;
2b036c6b
BO		 2413 case MSR_AMD64_OSVW_ID_LENGTH:
2414 if (!guest_cpuid_has_osvw(vcpu))
2415 return 1;
2416 vcpu->arch.osvw.length = data;
2417 break;
2418 case MSR_AMD64_OSVW_STATUS:
2419 if (!guest_cpuid_has_osvw(vcpu))
2420 return 1;
2421 vcpu->arch.osvw.status = data;
2422 break;
15c4a640 2423 default:
ffde22ac
ES		 2424 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2425 return xen_hvm_config(vcpu, data);
f5132b01 2426 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2427 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2428 if (!ignore_msrs) {
a737f256
CD		 2429 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2430 msr, data);
ed85c068
AP		 2431 return 1;
2432 } else {
a737f256
CD		 2433 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2434 msr, data);
ed85c068
AP		 2435 break;
2436 }
15c4a640
CO		 2437 }
2438 return 0;
2439}
2440EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2441
2442
2443/*
2444 * Reads an msr value (of 'msr_index') into 'pdata'.
2445 * Returns 0 on success, non-0 otherwise.
2446 * Assumes vcpu_load() was already called.
2447 */
2448int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2449{
2450 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2451}
ff651cb6 2452EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2453
9ba075a6
AK		 2454static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2455{
0bed3b56
SY		 2456 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2457
9ba075a6
AK		 2458 if (!msr_mtrr_valid(msr))
2459 return 1;
2460
0bed3b56
SY		 2461 if (msr == MSR_MTRRdefType)
2462 *pdata = vcpu->arch.mtrr_state.def_type +
2463 (vcpu->arch.mtrr_state.enabled << 10);
2464 else if (msr == MSR_MTRRfix64K_00000)
2465 *pdata = p[0];
2466 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2467 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2468 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2469 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2470 else if (msr == MSR_IA32_CR_PAT)
2471 *pdata = vcpu->arch.pat;
2472 else { /* Variable MTRRs */
2473 int idx, is_mtrr_mask;
2474 u64 *pt;
2475
2476 idx = (msr - 0x200) / 2;
2477 is_mtrr_mask = msr - 0x200 - 2 * idx;
2478 if (!is_mtrr_mask)
2479 pt =
2480 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2481 else
2482 pt =
2483 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2484 *pdata = *pt;
2485 }
2486
9ba075a6
AK		 2487 return 0;
2488}
2489
890ca9ae 2490static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2491{
2492 u64 data;
890ca9ae
HY		 2493 u64 mcg_cap = vcpu->arch.mcg_cap;
2494 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2495
2496 switch (msr) {
15c4a640
CO		 2497 case MSR_IA32_P5_MC_ADDR:
2498 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2499 data = 0;
2500 break;
15c4a640 2501 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2502 data = vcpu->arch.mcg_cap;
2503 break;
c7ac679c 2504 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2505 if (!(mcg_cap & MCG_CTL_P))
2506 return 1;
2507 data = vcpu->arch.mcg_ctl;
2508 break;
2509 case MSR_IA32_MCG_STATUS:
2510 data = vcpu->arch.mcg_status;
2511 break;
2512 default:
2513 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2514 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2515 u32 offset = msr - MSR_IA32_MC0_CTL;
2516 data = vcpu->arch.mce_banks[offset];
2517 break;
2518 }
2519 return 1;
2520 }
2521 *pdata = data;
2522 return 0;
2523}
2524
55cd8e5a
GN		 2525static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2526{
2527 u64 data = 0;
2528 struct kvm *kvm = vcpu->kvm;
2529
2530 switch (msr) {
2531 case HV_X64_MSR_GUEST_OS_ID:
2532 data = kvm->arch.hv_guest_os_id;
2533 break;
2534 case HV_X64_MSR_HYPERCALL:
2535 data = kvm->arch.hv_hypercall;
2536 break;
e984097b
VR		 2537 case HV_X64_MSR_TIME_REF_COUNT: {
2538 data =
2539 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2540 break;
2541 }
2542 case HV_X64_MSR_REFERENCE_TSC:
2543 data = kvm->arch.hv_tsc_page;
2544 break;
55cd8e5a 2545 default:
a737f256 2546 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2547 return 1;
2548 }
2549
2550 *pdata = data;
2551 return 0;
2552}
2553
2554static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2555{
2556 u64 data = 0;
2557
2558 switch (msr) {
2559 case HV_X64_MSR_VP_INDEX: {
2560 int r;
2561 struct kvm_vcpu *v;
684851a1
TY		 2562 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2563 if (v == vcpu) {
55cd8e5a 2564 data = r;
684851a1
TY		 2565 break;
2566 }
2567 }
55cd8e5a
GN		 2568 break;
2569 }
10388a07
GN		 2570 case HV_X64_MSR_EOI:
2571 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2572 case HV_X64_MSR_ICR:
2573 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2574 case HV_X64_MSR_TPR:
2575 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2576 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2577 data = vcpu->arch.hv_vapic;
2578 break;
55cd8e5a 2579 default:
a737f256 2580 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2581 return 1;
2582 }
2583 *pdata = data;
2584 return 0;
2585}
2586
890ca9ae
HY		 2587int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2588{
2589 u64 data;
2590
2591 switch (msr) {
890ca9ae 2592 case MSR_IA32_PLATFORM_ID:
15c4a640 2593 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2594 case MSR_IA32_DEBUGCTLMSR:
2595 case MSR_IA32_LASTBRANCHFROMIP:
2596 case MSR_IA32_LASTBRANCHTOIP:
2597 case MSR_IA32_LASTINTFROMIP:
2598 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2599 case MSR_K8_SYSCFG:
2600 case MSR_K7_HWCR:
61a6bd67 2601 case MSR_VM_HSAVE_PA:
9e699624 2602 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2603 case MSR_K7_EVNTSEL1:
2604 case MSR_K7_EVNTSEL2:
2605 case MSR_K7_EVNTSEL3:
1f3ee616 2606 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2607 case MSR_K7_PERFCTR1:
2608 case MSR_K7_PERFCTR2:
2609 case MSR_K7_PERFCTR3:
1fdbd48c 2610 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2611 case MSR_AMD64_NB_CFG:
f7c6d140 2612 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2613 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2614 data = 0;
2615 break;
5753785f
GN		 2616 case MSR_P6_PERFCTR0:
2617 case MSR_P6_PERFCTR1:
2618 case MSR_P6_EVNTSEL0:
2619 case MSR_P6_EVNTSEL1:
2620 if (kvm_pmu_msr(vcpu, msr))
2621 return kvm_pmu_get_msr(vcpu, msr, pdata);
2622 data = 0;
2623 break;
742bc670
MT		 2624 case MSR_IA32_UCODE_REV:
2625 data = 0x100000000ULL;
2626 break;
9ba075a6
AK		 2627 case MSR_MTRRcap:
2628 data = 0x500 | KVM_NR_VAR_MTRR;
2629 break;
2630 case 0x200 ... 0x2ff:
2631 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2632 case 0xcd: /* fsb frequency */
2633 data = 3;
2634 break;
7b914098
JS		 2635 /*
2636 * MSR_EBC_FREQUENCY_ID
2637 * Conservative value valid for even the basic CPU models.
2638 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2639 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2640 * and 266MHz for model 3, or 4. Set Core Clock
2641 * Frequency to System Bus Frequency Ratio to 1 (bits
2642 * 31:24) even though these are only valid for CPU
2643 * models > 2, however guests may end up dividing or
2644 * multiplying by zero otherwise.
2645 */
2646 case MSR_EBC_FREQUENCY_ID:
2647 data = 1 << 24;
2648 break;
15c4a640
CO		 2649 case MSR_IA32_APICBASE:
2650 data = kvm_get_apic_base(vcpu);
2651 break;
0105d1a5
GN		 2652 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2653 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2654 break;
a3e06bbe
LJ		 2655 case MSR_IA32_TSCDEADLINE:
2656 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2657 break;
ba904635
WA		 2658 case MSR_IA32_TSC_ADJUST:
2659 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2660 break;
15c4a640 2661 case MSR_IA32_MISC_ENABLE:
ad312c7c 2662 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2663 break;
847f0ad8
AG		 2664 case MSR_IA32_PERF_STATUS:
2665 /* TSC increment by tick */
2666 data = 1000ULL;
2667 /* CPU multiplier */
2668 data |= (((uint64_t)4ULL) << 40);
2669 break;
15c4a640 2670 case MSR_EFER:
f6801dff 2671 data = vcpu->arch.efer;
15c4a640 2672 break;
18068523 2673 case MSR_KVM_WALL_CLOCK:
11c6bffa 2674 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2675 data = vcpu->kvm->arch.wall_clock;
2676 break;
2677 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2678 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2679 data = vcpu->arch.time;
2680 break;
344d9588
GN		 2681 case MSR_KVM_ASYNC_PF_EN:
2682 data = vcpu->arch.apf.msr_val;
2683 break;
c9aaa895
GC		 2684 case MSR_KVM_STEAL_TIME:
2685 data = vcpu->arch.st.msr_val;
2686 break;
1d92128f
MT		 2687 case MSR_KVM_PV_EOI_EN:
2688 data = vcpu->arch.pv_eoi.msr_val;
2689 break;
890ca9ae
HY		 2690 case MSR_IA32_P5_MC_ADDR:
2691 case MSR_IA32_P5_MC_TYPE:
2692 case MSR_IA32_MCG_CAP:
2693 case MSR_IA32_MCG_CTL:
2694 case MSR_IA32_MCG_STATUS:
81760dcc 2695 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2696 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2697 case MSR_K7_CLK_CTL:
2698 /*
2699 * Provide expected ramp-up count for K7. All other
2700 * are set to zero, indicating minimum divisors for
2701 * every field.
2702 *
2703 * This prevents guest kernels on AMD host with CPU
2704 * type 6, model 8 and higher from exploding due to
2705 * the rdmsr failing.
2706 */
2707 data = 0x20000000;
2708 break;
55cd8e5a
GN		 2709 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2710 if (kvm_hv_msr_partition_wide(msr)) {
2711 int r;
2712 mutex_lock(&vcpu->kvm->lock);
2713 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2714 mutex_unlock(&vcpu->kvm->lock);
2715 return r;
2716 } else
2717 return get_msr_hyperv(vcpu, msr, pdata);
2718 break;
91c9c3ed 2719 case MSR_IA32_BBL_CR_CTL3:
2720 /* This legacy MSR exists but isn't fully documented in current
2721 * silicon. It is however accessed by winxp in very narrow
2722 * scenarios where it sets bit #19, itself documented as
2723 * a "reserved" bit. Best effort attempt to source coherent
2724 * read data here should the balance of the register be
2725 * interpreted by the guest:
2726 *
2727 * L2 cache control register 3: 64GB range, 256KB size,
2728 * enabled, latency 0x1, configured
2729 */
2730 data = 0xbe702111;
2731 break;
2b036c6b
BO		 2732 case MSR_AMD64_OSVW_ID_LENGTH:
2733 if (!guest_cpuid_has_osvw(vcpu))
2734 return 1;
2735 data = vcpu->arch.osvw.length;
2736 break;
2737 case MSR_AMD64_OSVW_STATUS:
2738 if (!guest_cpuid_has_osvw(vcpu))
2739 return 1;
2740 data = vcpu->arch.osvw.status;
2741 break;
15c4a640 2742 default:
f5132b01
GN		 2743 if (kvm_pmu_msr(vcpu, msr))
2744 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2745 if (!ignore_msrs) {
a737f256 2746 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2747 return 1;
2748 } else {
a737f256 2749 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2750 data = 0;
2751 }
2752 break;
15c4a640
CO		 2753 }
2754 *pdata = data;
2755 return 0;
2756}
2757EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2758
313a3dc7
CO		 2759/*
2760 * Read or write a bunch of msrs. All parameters are kernel addresses.
2761 *
2762 * @return number of msrs set successfully.
2763 */
2764static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2765 struct kvm_msr_entry *entries,
2766 int (*do_msr)(struct kvm_vcpu *vcpu,
2767 unsigned index, u64 *data))
2768{
f656ce01 2769 int i, idx;
313a3dc7 2770
f656ce01 2771 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2772 for (i = 0; i < msrs->nmsrs; ++i)
2773 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2774 break;
f656ce01 2775 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2776
313a3dc7
CO		 2777 return i;
2778}
2779
2780/*
2781 * Read or write a bunch of msrs. Parameters are user addresses.
2782 *
2783 * @return number of msrs set successfully.
2784 */
2785static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2786 int (*do_msr)(struct kvm_vcpu *vcpu,
2787 unsigned index, u64 *data),
2788 int writeback)
2789{
2790 struct kvm_msrs msrs;
2791 struct kvm_msr_entry *entries;
2792 int r, n;
2793 unsigned size;
2794
2795 r = -EFAULT;
2796 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2797 goto out;
2798
2799 r = -E2BIG;
2800 if (msrs.nmsrs >= MAX_IO_MSRS)
2801 goto out;
2802
313a3dc7 2803 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2804 entries = memdup_user(user_msrs->entries, size);
2805 if (IS_ERR(entries)) {
2806 r = PTR_ERR(entries);
313a3dc7 2807 goto out;
ff5c2c03 2808 }
313a3dc7
CO		 2809
2810 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2811 if (r < 0)
2812 goto out_free;
2813
2814 r = -EFAULT;
2815 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2816 goto out_free;
2817
2818 r = n;
2819
2820out_free:
7a73c028 2821 kfree(entries);
313a3dc7
CO		 2822out:
2823 return r;
2824}
2825
784aa3d7 2826int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2827{
2828 int r;
2829
2830 switch (ext) {
2831 case KVM_CAP_IRQCHIP:
2832 case KVM_CAP_HLT:
2833 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2834 case KVM_CAP_SET_TSS_ADDR:
07716717 2835 case KVM_CAP_EXT_CPUID:
9c15bb1d 2836 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2837 case KVM_CAP_CLOCKSOURCE:
7837699f 2838 case KVM_CAP_PIT:
a28e4f5a 2839 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2840 case KVM_CAP_MP_STATE:
ed848624 2841 case KVM_CAP_SYNC_MMU:
a355c85c 2842 case KVM_CAP_USER_NMI:
52d939a0 2843 case KVM_CAP_REINJECT_CONTROL:
4925663a 2844 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2845 case KVM_CAP_IOEVENTFD:
f848a5a8 2846 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2847 case KVM_CAP_PIT2:
e9f42757 2848 case KVM_CAP_PIT_STATE2:
b927a3ce 2849 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2850 case KVM_CAP_XEN_HVM:
afbcf7ab 2851 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2852 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2853 case KVM_CAP_HYPERV:
10388a07 2854 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2855 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2856 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2857 case KVM_CAP_DEBUGREGS:
d2be1651 2858 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2859 case KVM_CAP_XSAVE:
344d9588 2860 case KVM_CAP_ASYNC_PF:
92a1f12d 2861 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2862 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2863 case KVM_CAP_READONLY_MEM:
5f66b620 2864 case KVM_CAP_HYPERV_TIME:
100943c5 2865 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2866 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2867 case KVM_CAP_ENABLE_CAP_VM:
2868 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2869#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2870 case KVM_CAP_ASSIGN_DEV_IRQ:
2871 case KVM_CAP_PCI_2_3:
2872#endif
018d00d2
ZX		 2873 r = 1;
2874 break;
542472b5
LV		 2875 case KVM_CAP_COALESCED_MMIO:
2876 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2877 break;
774ead3a
AK		 2878 case KVM_CAP_VAPIC:
2879 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2880 break;
f725230a 2881 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2882 r = KVM_SOFT_MAX_VCPUS;
2883 break;
2884 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2885 r = KVM_MAX_VCPUS;
2886 break;
a988b910 2887 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2888 r = KVM_USER_MEM_SLOTS;
a988b910 2889 break;
a68a6a72
MT		 2890 case KVM_CAP_PV_MMU: /* obsolete */
2891 r = 0;
2f333bcb 2892 break;
4cee4b72 2893#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2894 case KVM_CAP_IOMMU:
a1b60c1c 2895 r = iommu_present(&pci_bus_type);
62c476c7 2896 break;
4cee4b72 2897#endif
890ca9ae
HY		 2898 case KVM_CAP_MCE:
2899 r = KVM_MAX_MCE_BANKS;
2900 break;
2d5b5a66
SY		 2901 case KVM_CAP_XCRS:
2902 r = cpu_has_xsave;
2903 break;
92a1f12d
JR		 2904 case KVM_CAP_TSC_CONTROL:
2905 r = kvm_has_tsc_control;
2906 break;
018d00d2
ZX		 2907 default:
2908 r = 0;
2909 break;
2910 }
2911 return r;
2912
2913}
2914
043405e1
CO		 2915long kvm_arch_dev_ioctl(struct file *filp,
2916 unsigned int ioctl, unsigned long arg)
2917{
2918 void __user *argp = (void __user *)arg;
2919 long r;
2920
2921 switch (ioctl) {
2922 case KVM_GET_MSR_INDEX_LIST: {
2923 struct kvm_msr_list __user *user_msr_list = argp;
2924 struct kvm_msr_list msr_list;
2925 unsigned n;
2926
2927 r = -EFAULT;
2928 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2929 goto out;
2930 n = msr_list.nmsrs;
2931 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2932 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2933 goto out;
2934 r = -E2BIG;
e125e7b6 2935 if (n < msr_list.nmsrs)
043405e1
CO		 2936 goto out;
2937 r = -EFAULT;
2938 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2939 num_msrs_to_save * sizeof(u32)))
2940 goto out;
e125e7b6 2941 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2942 &emulated_msrs,
2943 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2944 goto out;
2945 r = 0;
2946 break;
2947 }
9c15bb1d
BP		 2948 case KVM_GET_SUPPORTED_CPUID:
2949 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2950 struct kvm_cpuid2 __user *cpuid_arg = argp;
2951 struct kvm_cpuid2 cpuid;
2952
2953 r = -EFAULT;
2954 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2955 goto out;
9c15bb1d
BP		 2956
2957 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2958 ioctl);
674eea0f
AK		 2959 if (r)
2960 goto out;
2961
2962 r = -EFAULT;
2963 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2964 goto out;
2965 r = 0;
2966 break;
2967 }
890ca9ae
HY		 2968 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2969 u64 mce_cap;
2970
2971 mce_cap = KVM_MCE_CAP_SUPPORTED;
2972 r = -EFAULT;
2973 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2974 goto out;
2975 r = 0;
2976 break;
2977 }
043405e1
CO		 2978 default:
2979 r = -EINVAL;
2980 }
2981out:
2982 return r;
2983}
2984
f5f48ee1
SY		 2985static void wbinvd_ipi(void *garbage)
2986{
2987 wbinvd();
2988}
2989
2990static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2991{
e0f0bbc5 2992 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2993}
2994
313a3dc7
CO		 2995void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2996{
f5f48ee1
SY		 2997 /* Address WBINVD may be executed by guest */
2998 if (need_emulate_wbinvd(vcpu)) {
2999 if (kvm_x86_ops->has_wbinvd_exit())
3000 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3001 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3002 smp_call_function_single(vcpu->cpu,
3003 wbinvd_ipi, NULL, 1);
3004 }
3005
313a3dc7 3006 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3007
0dd6a6ed
ZA		 3008 /* Apply any externally detected TSC adjustments (due to suspend) */
3009 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3010 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3011 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3012 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3013 }
8f6055cb 3014
48434c20 3015 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 3016 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3017 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3018 if (tsc_delta < 0)
3019 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 3020 if (check_tsc_unstable()) {
b183aa58
ZA		 3021 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
3022 vcpu->arch.last_guest_tsc);
3023 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 3024 vcpu->arch.tsc_catchup = 1;
c285545f 3025 }
d98d07ca
MT		 3026 /*
3027 * On a host with synchronized TSC, there is no need to update
3028 * kvmclock on vcpu->cpu migration
3029 */
3030 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3031 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 3032 if (vcpu->cpu != cpu)
3033 kvm_migrate_timers(vcpu);
e48672fa 3034 vcpu->cpu = cpu;
6b7d7e76 3035 }
c9aaa895
GC		 3036
3037 accumulate_steal_time(vcpu);
3038 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3039}
3040
3041void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3042{
02daab21 3043 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 3044 kvm_put_guest_fpu(vcpu);
6f526ec5 3045 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 3046}
3047
313a3dc7
CO		 3048static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3049 struct kvm_lapic_state *s)
3050{
5a71785d 3051 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 3052 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 3053
3054 return 0;
3055}
3056
3057static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3058 struct kvm_lapic_state *s)
3059{
64eb0620 3060 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 3061 update_cr8_intercept(vcpu);
313a3dc7
CO		 3062
3063 return 0;
3064}
3065
f77bc6a4
ZX		 3066static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3067 struct kvm_interrupt *irq)
3068{
02cdb50f 3069 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3070 return -EINVAL;
3071 if (irqchip_in_kernel(vcpu->kvm))
3072 return -ENXIO;
f77bc6a4 3073
66fd3f7f 3074 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3075 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3076
f77bc6a4
ZX		 3077 return 0;
3078}
3079
c4abb7c9
JK		 3080static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3081{
c4abb7c9 3082 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3083
3084 return 0;
3085}
3086
b209749f
AK		 3087static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3088 struct kvm_tpr_access_ctl *tac)
3089{
3090 if (tac->flags)
3091 return -EINVAL;
3092 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3093 return 0;
3094}
3095
890ca9ae
HY		 3096static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3097 u64 mcg_cap)
3098{
3099 int r;
3100 unsigned bank_num = mcg_cap & 0xff, bank;
3101
3102 r = -EINVAL;
a9e38c3e 3103 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3104 goto out;
3105 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3106 goto out;
3107 r = 0;
3108 vcpu->arch.mcg_cap = mcg_cap;
3109 /* Init IA32_MCG_CTL to all 1s */
3110 if (mcg_cap & MCG_CTL_P)
3111 vcpu->arch.mcg_ctl = ~(u64)0;
3112 /* Init IA32_MCi_CTL to all 1s */
3113 for (bank = 0; bank < bank_num; bank++)
3114 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3115out:
3116 return r;
3117}
3118
3119static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3120 struct kvm_x86_mce *mce)
3121{
3122 u64 mcg_cap = vcpu->arch.mcg_cap;
3123 unsigned bank_num = mcg_cap & 0xff;
3124 u64 *banks = vcpu->arch.mce_banks;
3125
3126 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3127 return -EINVAL;
3128 /*
3129 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3130 * reporting is disabled
3131 */
3132 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3133 vcpu->arch.mcg_ctl != ~(u64)0)
3134 return 0;
3135 banks += 4 * mce->bank;
3136 /*
3137 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3138 * reporting is disabled for the bank
3139 */
3140 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3141 return 0;
3142 if (mce->status & MCI_STATUS_UC) {
3143 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3144 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3145 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3146 return 0;
3147 }
3148 if (banks[1] & MCI_STATUS_VAL)
3149 mce->status |= MCI_STATUS_OVER;
3150 banks[2] = mce->addr;
3151 banks[3] = mce->misc;
3152 vcpu->arch.mcg_status = mce->mcg_status;
3153 banks[1] = mce->status;
3154 kvm_queue_exception(vcpu, MC_VECTOR);
3155 } else if (!(banks[1] & MCI_STATUS_VAL)
3156 || !(banks[1] & MCI_STATUS_UC)) {
3157 if (banks[1] & MCI_STATUS_VAL)
3158 mce->status |= MCI_STATUS_OVER;
3159 banks[2] = mce->addr;
3160 banks[3] = mce->misc;
3161 banks[1] = mce->status;
3162 } else
3163 banks[1] |= MCI_STATUS_OVER;
3164 return 0;
3165}
3166
3cfc3092
JK		 3167static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3168 struct kvm_vcpu_events *events)
3169{
7460fb4a 3170 process_nmi(vcpu);
03b82a30
JK		 3171 events->exception.injected =
3172 vcpu->arch.exception.pending &&
3173 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3174 events->exception.nr = vcpu->arch.exception.nr;
3175 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3176 events->exception.pad = 0;
3cfc3092
JK		 3177 events->exception.error_code = vcpu->arch.exception.error_code;
3178
03b82a30
JK		 3179 events->interrupt.injected =
3180 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3181 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3182 events->interrupt.soft = 0;
37ccdcbe 3183 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3184
3185 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3186 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3187 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3188 events->nmi.pad = 0;
3cfc3092 3189
66450a21 3190 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3191
dab4b911 3192 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3193 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3194 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3195}
3196
3197static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3198 struct kvm_vcpu_events *events)
3199{
dab4b911 3200 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3201 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3202 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3203 return -EINVAL;
3204
7460fb4a 3205 process_nmi(vcpu);
3cfc3092
JK		 3206 vcpu->arch.exception.pending = events->exception.injected;
3207 vcpu->arch.exception.nr = events->exception.nr;
3208 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3209 vcpu->arch.exception.error_code = events->exception.error_code;
3210
3211 vcpu->arch.interrupt.pending = events->interrupt.injected;
3212 vcpu->arch.interrupt.nr = events->interrupt.nr;
3213 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3214 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3215 kvm_x86_ops->set_interrupt_shadow(vcpu,
3216 events->interrupt.shadow);
3cfc3092
JK		 3217
3218 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3219 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3220 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3221 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3222
66450a21
JK		 3223 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3224 kvm_vcpu_has_lapic(vcpu))
3225 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3226
3842d135
AK		 3227 kvm_make_request(KVM_REQ_EVENT, vcpu);
3228
3cfc3092
JK		 3229 return 0;
3230}
3231
a1efbe77
JK		 3232static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3233 struct kvm_debugregs *dbgregs)
3234{
73aaf249
JK		 3235 unsigned long val;
3236
a1efbe77 3237 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3238 kvm_get_dr(vcpu, 6, &val);
73aaf249 3239 dbgregs->dr6 = val;
a1efbe77
JK		 3240 dbgregs->dr7 = vcpu->arch.dr7;
3241 dbgregs->flags = 0;
97e69aa6 3242 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3243}
3244
3245static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3246 struct kvm_debugregs *dbgregs)
3247{
3248 if (dbgregs->flags)
3249 return -EINVAL;
3250
a1efbe77 3251 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3252 kvm_update_dr0123(vcpu);
a1efbe77 3253 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3254 kvm_update_dr6(vcpu);
a1efbe77 3255 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3256 kvm_update_dr7(vcpu);
a1efbe77 3257
a1efbe77
JK		 3258 return 0;
3259}
3260
df1daba7
PB		 3261#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3262
3263static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3264{
3265 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3266 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3267 u64 valid;
3268
3269 /*
3270 * Copy legacy XSAVE area, to avoid complications with CPUID
3271 * leaves 0 and 1 in the loop below.
3272 */
3273 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3274
3275 /* Set XSTATE_BV */
3276 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3277
3278 /*
3279 * Copy each region from the possibly compacted offset to the
3280 * non-compacted offset.
3281 */
3282 valid = xstate_bv & ~XSTATE_FPSSE;
3283 while (valid) {
3284 u64 feature = valid & -valid;
3285 int index = fls64(feature) - 1;
3286 void *src = get_xsave_addr(xsave, feature);
3287
3288 if (src) {
3289 u32 size, offset, ecx, edx;
3290 cpuid_count(XSTATE_CPUID, index,
3291 &size, &offset, &ecx, &edx);
3292 memcpy(dest + offset, src, size);
3293 }
3294
3295 valid -= feature;
3296 }
3297}
3298
3299static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3300{
3301 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3302 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3303 u64 valid;
3304
3305 /*
3306 * Copy legacy XSAVE area, to avoid complications with CPUID
3307 * leaves 0 and 1 in the loop below.
3308 */
3309 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3310
3311 /* Set XSTATE_BV and possibly XCOMP_BV. */
3312 xsave->xsave_hdr.xstate_bv = xstate_bv;
3313 if (cpu_has_xsaves)
3314 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3315
3316 /*
3317 * Copy each region from the non-compacted offset to the
3318 * possibly compacted offset.
3319 */
3320 valid = xstate_bv & ~XSTATE_FPSSE;
3321 while (valid) {
3322 u64 feature = valid & -valid;
3323 int index = fls64(feature) - 1;
3324 void *dest = get_xsave_addr(xsave, feature);
3325
3326 if (dest) {
3327 u32 size, offset, ecx, edx;
3328 cpuid_count(XSTATE_CPUID, index,
3329 &size, &offset, &ecx, &edx);
3330 memcpy(dest, src + offset, size);
3331 } else
3332 WARN_ON_ONCE(1);
3333
3334 valid -= feature;
3335 }
3336}
3337
2d5b5a66
SY		 3338static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3339 struct kvm_xsave *guest_xsave)
3340{
4344ee98 3341 if (cpu_has_xsave) {
df1daba7
PB		 3342 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3343 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3344 } else {
2d5b5a66
SY		 3345 memcpy(guest_xsave->region,
3346 &vcpu->arch.guest_fpu.state->fxsave,
3347 sizeof(struct i387_fxsave_struct));
3348 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3349 XSTATE_FPSSE;
3350 }
3351}
3352
3353static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3354 struct kvm_xsave *guest_xsave)
3355{
3356 u64 xstate_bv =
3357 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3358
d7876f1b
PB		 3359 if (cpu_has_xsave) {
3360 /*
3361 * Here we allow setting states that are not present in
3362 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3363 * with old userspace.
3364 */
4ff41732 3365 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3366 return -EINVAL;
df1daba7 3367 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3368 } else {
2d5b5a66
SY		 3369 if (xstate_bv & ~XSTATE_FPSSE)
3370 return -EINVAL;
3371 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3372 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3373 }
3374 return 0;
3375}
3376
3377static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3378 struct kvm_xcrs *guest_xcrs)
3379{
3380 if (!cpu_has_xsave) {
3381 guest_xcrs->nr_xcrs = 0;
3382 return;
3383 }
3384
3385 guest_xcrs->nr_xcrs = 1;
3386 guest_xcrs->flags = 0;
3387 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3388 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3389}
3390
3391static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3392 struct kvm_xcrs *guest_xcrs)
3393{
3394 int i, r = 0;
3395
3396 if (!cpu_has_xsave)
3397 return -EINVAL;
3398
3399 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3400 return -EINVAL;
3401
3402 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3403 /* Only support XCR0 currently */
c67a04cb 3404 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3405 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3406 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3407 break;
3408 }
3409 if (r)
3410 r = -EINVAL;
3411 return r;
3412}
3413
1c0b28c2
EM		 3414/*
3415 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3416 * stopped by the hypervisor. This function will be called from the host only.
3417 * EINVAL is returned when the host attempts to set the flag for a guest that
3418 * does not support pv clocks.
3419 */
3420static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3421{
0b79459b 3422 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3423 return -EINVAL;
51d59c6b 3424 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3425 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3426 return 0;
3427}
3428
313a3dc7
CO		 3429long kvm_arch_vcpu_ioctl(struct file *filp,
3430 unsigned int ioctl, unsigned long arg)
3431{
3432 struct kvm_vcpu *vcpu = filp->private_data;
3433 void __user *argp = (void __user *)arg;
3434 int r;
d1ac91d8
AK		 3435 union {
3436 struct kvm_lapic_state *lapic;
3437 struct kvm_xsave *xsave;
3438 struct kvm_xcrs *xcrs;
3439 void *buffer;
3440 } u;
3441
3442 u.buffer = NULL;
313a3dc7
CO		 3443 switch (ioctl) {
3444 case KVM_GET_LAPIC: {
2204ae3c
MT		 3445 r = -EINVAL;
3446 if (!vcpu->arch.apic)
3447 goto out;
d1ac91d8 3448 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3449
b772ff36 3450 r = -ENOMEM;
d1ac91d8 3451 if (!u.lapic)
b772ff36 3452 goto out;
d1ac91d8 3453 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3454 if (r)
3455 goto out;
3456 r = -EFAULT;
d1ac91d8 3457 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3458 goto out;
3459 r = 0;
3460 break;
3461 }
3462 case KVM_SET_LAPIC: {
2204ae3c
MT		 3463 r = -EINVAL;
3464 if (!vcpu->arch.apic)
3465 goto out;
ff5c2c03 3466 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3467 if (IS_ERR(u.lapic))
3468 return PTR_ERR(u.lapic);
ff5c2c03 3469
d1ac91d8 3470 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3471 break;
3472 }
f77bc6a4
ZX		 3473 case KVM_INTERRUPT: {
3474 struct kvm_interrupt irq;
3475
3476 r = -EFAULT;
3477 if (copy_from_user(&irq, argp, sizeof irq))
3478 goto out;
3479 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3480 break;
3481 }
c4abb7c9
JK		 3482 case KVM_NMI: {
3483 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3484 break;
3485 }
313a3dc7
CO		 3486 case KVM_SET_CPUID: {
3487 struct kvm_cpuid __user *cpuid_arg = argp;
3488 struct kvm_cpuid cpuid;
3489
3490 r = -EFAULT;
3491 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3492 goto out;
3493 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3494 break;
3495 }
07716717
DK		 3496 case KVM_SET_CPUID2: {
3497 struct kvm_cpuid2 __user *cpuid_arg = argp;
3498 struct kvm_cpuid2 cpuid;
3499
3500 r = -EFAULT;
3501 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3502 goto out;
3503 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3504 cpuid_arg->entries);
07716717
DK		 3505 break;
3506 }
3507 case KVM_GET_CPUID2: {
3508 struct kvm_cpuid2 __user *cpuid_arg = argp;
3509 struct kvm_cpuid2 cpuid;
3510
3511 r = -EFAULT;
3512 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3513 goto out;
3514 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3515 cpuid_arg->entries);
07716717
DK		 3516 if (r)
3517 goto out;
3518 r = -EFAULT;
3519 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3520 goto out;
3521 r = 0;
3522 break;
3523 }
313a3dc7
CO		 3524 case KVM_GET_MSRS:
3525 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3526 break;
3527 case KVM_SET_MSRS:
3528 r = msr_io(vcpu, argp, do_set_msr, 0);
3529 break;
b209749f
AK		 3530 case KVM_TPR_ACCESS_REPORTING: {
3531 struct kvm_tpr_access_ctl tac;
3532
3533 r = -EFAULT;
3534 if (copy_from_user(&tac, argp, sizeof tac))
3535 goto out;
3536 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3537 if (r)
3538 goto out;
3539 r = -EFAULT;
3540 if (copy_to_user(argp, &tac, sizeof tac))
3541 goto out;
3542 r = 0;
3543 break;
3544 };
b93463aa
AK		 3545 case KVM_SET_VAPIC_ADDR: {
3546 struct kvm_vapic_addr va;
3547
3548 r = -EINVAL;
3549 if (!irqchip_in_kernel(vcpu->kvm))
3550 goto out;
3551 r = -EFAULT;
3552 if (copy_from_user(&va, argp, sizeof va))
3553 goto out;
fda4e2e8 3554 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3555 break;
3556 }
890ca9ae
HY		 3557 case KVM_X86_SETUP_MCE: {
3558 u64 mcg_cap;
3559
3560 r = -EFAULT;
3561 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3562 goto out;
3563 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3564 break;
3565 }
3566 case KVM_X86_SET_MCE: {
3567 struct kvm_x86_mce mce;
3568
3569 r = -EFAULT;
3570 if (copy_from_user(&mce, argp, sizeof mce))
3571 goto out;
3572 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3573 break;
3574 }
3cfc3092
JK		 3575 case KVM_GET_VCPU_EVENTS: {
3576 struct kvm_vcpu_events events;
3577
3578 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3579
3580 r = -EFAULT;
3581 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3582 break;
3583 r = 0;
3584 break;
3585 }
3586 case KVM_SET_VCPU_EVENTS: {
3587 struct kvm_vcpu_events events;
3588
3589 r = -EFAULT;
3590 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3591 break;
3592
3593 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3594 break;
3595 }
a1efbe77
JK		 3596 case KVM_GET_DEBUGREGS: {
3597 struct kvm_debugregs dbgregs;
3598
3599 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3600
3601 r = -EFAULT;
3602 if (copy_to_user(argp, &dbgregs,
3603 sizeof(struct kvm_debugregs)))
3604 break;
3605 r = 0;
3606 break;
3607 }
3608 case KVM_SET_DEBUGREGS: {
3609 struct kvm_debugregs dbgregs;
3610
3611 r = -EFAULT;
3612 if (copy_from_user(&dbgregs, argp,
3613 sizeof(struct kvm_debugregs)))
3614 break;
3615
3616 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3617 break;
3618 }
2d5b5a66 3619 case KVM_GET_XSAVE: {
d1ac91d8 3620 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3621 r = -ENOMEM;
d1ac91d8 3622 if (!u.xsave)
2d5b5a66
SY		 3623 break;
3624
d1ac91d8 3625 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3626
3627 r = -EFAULT;
d1ac91d8 3628 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3629 break;
3630 r = 0;
3631 break;
3632 }
3633 case KVM_SET_XSAVE: {
ff5c2c03 3634 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3635 if (IS_ERR(u.xsave))
3636 return PTR_ERR(u.xsave);
2d5b5a66 3637
d1ac91d8 3638 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3639 break;
3640 }
3641 case KVM_GET_XCRS: {
d1ac91d8 3642 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3643 r = -ENOMEM;
d1ac91d8 3644 if (!u.xcrs)
2d5b5a66
SY		 3645 break;
3646
d1ac91d8 3647 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3648
3649 r = -EFAULT;
d1ac91d8 3650 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3651 sizeof(struct kvm_xcrs)))
3652 break;
3653 r = 0;
3654 break;
3655 }
3656 case KVM_SET_XCRS: {
ff5c2c03 3657 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3658 if (IS_ERR(u.xcrs))
3659 return PTR_ERR(u.xcrs);
2d5b5a66 3660
d1ac91d8 3661 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3662 break;
3663 }
92a1f12d
JR		 3664 case KVM_SET_TSC_KHZ: {
3665 u32 user_tsc_khz;
3666
3667 r = -EINVAL;
92a1f12d
JR		 3668 user_tsc_khz = (u32)arg;
3669
3670 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3671 goto out;
3672
cc578287
ZA		 3673 if (user_tsc_khz == 0)
3674 user_tsc_khz = tsc_khz;
3675
3676 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3677
3678 r = 0;
3679 goto out;
3680 }
3681 case KVM_GET_TSC_KHZ: {
cc578287 3682 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3683 goto out;
3684 }
1c0b28c2
EM		 3685 case KVM_KVMCLOCK_CTRL: {
3686 r = kvm_set_guest_paused(vcpu);
3687 goto out;
3688 }
313a3dc7
CO		 3689 default:
3690 r = -EINVAL;
3691 }
3692out:
d1ac91d8 3693 kfree(u.buffer);
313a3dc7
CO		 3694 return r;
3695}
3696
5b1c1493
CO		 3697int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3698{
3699 return VM_FAULT_SIGBUS;
3700}
3701
1fe779f8
CO		 3702static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3703{
3704 int ret;
3705
3706 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3707 return -EINVAL;
1fe779f8
CO		 3708 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3709 return ret;
3710}
3711
b927a3ce
SY		 3712static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3713 u64 ident_addr)
3714{
3715 kvm->arch.ept_identity_map_addr = ident_addr;
3716 return 0;
3717}
3718
1fe779f8
CO		 3719static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3720 u32 kvm_nr_mmu_pages)
3721{
3722 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3723 return -EINVAL;
3724
79fac95e 3725 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3726
3727 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3728 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3729
79fac95e 3730 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3731 return 0;
3732}
3733
3734static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3735{
39de71ec 3736 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3737}
3738
1fe779f8
CO		 3739static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3740{
3741 int r;
3742
3743 r = 0;
3744 switch (chip->chip_id) {
3745 case KVM_IRQCHIP_PIC_MASTER:
3746 memcpy(&chip->chip.pic,
3747 &pic_irqchip(kvm)->pics[0],
3748 sizeof(struct kvm_pic_state));
3749 break;
3750 case KVM_IRQCHIP_PIC_SLAVE:
3751 memcpy(&chip->chip.pic,
3752 &pic_irqchip(kvm)->pics[1],
3753 sizeof(struct kvm_pic_state));
3754 break;
3755 case KVM_IRQCHIP_IOAPIC:
eba0226b 3756 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3757 break;
3758 default:
3759 r = -EINVAL;
3760 break;
3761 }
3762 return r;
3763}
3764
3765static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3766{
3767 int r;
3768
3769 r = 0;
3770 switch (chip->chip_id) {
3771 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3772 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3773 memcpy(&pic_irqchip(kvm)->pics[0],
3774 &chip->chip.pic,
3775 sizeof(struct kvm_pic_state));
f4f51050 3776 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3777 break;
3778 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3779 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3780 memcpy(&pic_irqchip(kvm)->pics[1],
3781 &chip->chip.pic,
3782 sizeof(struct kvm_pic_state));
f4f51050 3783 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3784 break;
3785 case KVM_IRQCHIP_IOAPIC:
eba0226b 3786 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3787 break;
3788 default:
3789 r = -EINVAL;
3790 break;
3791 }
3792 kvm_pic_update_irq(pic_irqchip(kvm));
3793 return r;
3794}
3795
e0f63cb9
SY		 3796static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3797{
3798 int r = 0;
3799
894a9c55 3800 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3801 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3802 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3803 return r;
3804}
3805
3806static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3807{
3808 int r = 0;
3809
894a9c55 3810 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3811 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3812 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3813 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3814 return r;
3815}
3816
3817static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3818{
3819 int r = 0;
3820
3821 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3822 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3823 sizeof(ps->channels));
3824 ps->flags = kvm->arch.vpit->pit_state.flags;
3825 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3826 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3827 return r;
3828}
3829
3830static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3831{
3832 int r = 0, start = 0;
3833 u32 prev_legacy, cur_legacy;
3834 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3835 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3836 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3837 if (!prev_legacy && cur_legacy)
3838 start = 1;
3839 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3840 sizeof(kvm->arch.vpit->pit_state.channels));
3841 kvm->arch.vpit->pit_state.flags = ps->flags;
3842 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3843 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3844 return r;
3845}
3846
52d939a0
MT		 3847static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3848 struct kvm_reinject_control *control)
3849{
3850 if (!kvm->arch.vpit)
3851 return -ENXIO;
894a9c55 3852 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3853 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3854 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3855 return 0;
3856}
3857
95d4c16c 3858/**
60c34612
TY		 3859 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3860 * @kvm: kvm instance
3861 * @log: slot id and address to which we copy the log
95d4c16c 3862 *
e108ff2f
PB		 3863 * Steps 1-4 below provide general overview of dirty page logging. See
3864 * kvm_get_dirty_log_protect() function description for additional details.
3865 *
3866 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3867 * always flush the TLB (step 4) even if previous step failed and the dirty
3868 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3869 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3870 * writes will be marked dirty for next log read.
95d4c16c 3871 *
60c34612
TY		 3872 * 1. Take a snapshot of the bit and clear it if needed.
3873 * 2. Write protect the corresponding page.
e108ff2f
PB		 3874 * 3. Copy the snapshot to the userspace.
3875 * 4. Flush TLB's if needed.
5bb064dc 3876 */
60c34612 3877int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3878{
60c34612 3879 bool is_dirty = false;
e108ff2f 3880 int r;
5bb064dc 3881
79fac95e 3882 mutex_lock(&kvm->slots_lock);
5bb064dc 3883
88178fd4
KH		 3884 /*
3885 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3886 */
3887 if (kvm_x86_ops->flush_log_dirty)
3888 kvm_x86_ops->flush_log_dirty(kvm);
3889
e108ff2f 3890 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3891
3892 /*
3893 * All the TLBs can be flushed out of mmu lock, see the comments in
3894 * kvm_mmu_slot_remove_write_access().
3895 */
e108ff2f 3896 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3897 if (is_dirty)
3898 kvm_flush_remote_tlbs(kvm);
3899
79fac95e 3900 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3901 return r;
3902}
3903
aa2fbe6d
YZ		 3904int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3905 bool line_status)
23d43cf9
CD		 3906{
3907 if (!irqchip_in_kernel(kvm))
3908 return -ENXIO;
3909
3910 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3911 irq_event->irq, irq_event->level,
3912 line_status);
23d43cf9
CD		 3913 return 0;
3914}
3915
90de4a18
NA		 3916static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3917 struct kvm_enable_cap *cap)
3918{
3919 int r;
3920
3921 if (cap->flags)
3922 return -EINVAL;
3923
3924 switch (cap->cap) {
3925 case KVM_CAP_DISABLE_QUIRKS:
3926 kvm->arch.disabled_quirks = cap->args[0];
3927 r = 0;
3928 break;
3929 default:
3930 r = -EINVAL;
3931 break;
3932 }
3933 return r;
3934}
3935
1fe779f8
CO		 3936long kvm_arch_vm_ioctl(struct file *filp,
3937 unsigned int ioctl, unsigned long arg)
3938{
3939 struct kvm *kvm = filp->private_data;
3940 void __user *argp = (void __user *)arg;
367e1319 3941 int r = -ENOTTY;
f0d66275
DH		 3942 /*
3943 * This union makes it completely explicit to gcc-3.x
3944 * that these two variables' stack usage should be
3945 * combined, not added together.
3946 */
3947 union {
3948 struct kvm_pit_state ps;
e9f42757 3949 struct kvm_pit_state2 ps2;
c5ff41ce 3950 struct kvm_pit_config pit_config;
f0d66275 3951 } u;
1fe779f8
CO		 3952
3953 switch (ioctl) {
3954 case KVM_SET_TSS_ADDR:
3955 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3956 break;
b927a3ce
SY		 3957 case KVM_SET_IDENTITY_MAP_ADDR: {
3958 u64 ident_addr;
3959
3960 r = -EFAULT;
3961 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3962 goto out;
3963 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3964 break;
3965 }
1fe779f8
CO		 3966 case KVM_SET_NR_MMU_PAGES:
3967 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3968 break;
3969 case KVM_GET_NR_MMU_PAGES:
3970 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3971 break;
3ddea128
MT		 3972 case KVM_CREATE_IRQCHIP: {
3973 struct kvm_pic *vpic;
3974
3975 mutex_lock(&kvm->lock);
3976 r = -EEXIST;
3977 if (kvm->arch.vpic)
3978 goto create_irqchip_unlock;
3e515705
AK		 3979 r = -EINVAL;
3980 if (atomic_read(&kvm->online_vcpus))
3981 goto create_irqchip_unlock;
1fe779f8 3982 r = -ENOMEM;
3ddea128
MT		 3983 vpic = kvm_create_pic(kvm);
3984 if (vpic) {
1fe779f8
CO		 3985 r = kvm_ioapic_init(kvm);
3986 if (r) {
175504cd 3987 mutex_lock(&kvm->slots_lock);
72bb2fcd 3988 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3989 &vpic->dev_master);
3990 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3991 &vpic->dev_slave);
3992 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3993 &vpic->dev_eclr);
175504cd 3994 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3995 kfree(vpic);
3996 goto create_irqchip_unlock;
1fe779f8
CO		 3997 }
3998 } else
3ddea128
MT		 3999 goto create_irqchip_unlock;
4000 smp_wmb();
4001 kvm->arch.vpic = vpic;
4002 smp_wmb();
399ec807
AK		 4003 r = kvm_setup_default_irq_routing(kvm);
4004 if (r) {
175504cd 4005 mutex_lock(&kvm->slots_lock);
3ddea128 4006 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 4007 kvm_ioapic_destroy(kvm);
4008 kvm_destroy_pic(kvm);
3ddea128 4009 mutex_unlock(&kvm->irq_lock);
175504cd 4010 mutex_unlock(&kvm->slots_lock);
399ec807 4011 }
3ddea128
MT		 4012 create_irqchip_unlock:
4013 mutex_unlock(&kvm->lock);
1fe779f8 4014 break;
3ddea128 4015 }
7837699f 4016 case KVM_CREATE_PIT:
c5ff41ce
JK		 4017 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4018 goto create_pit;
4019 case KVM_CREATE_PIT2:
4020 r = -EFAULT;
4021 if (copy_from_user(&u.pit_config, argp,
4022 sizeof(struct kvm_pit_config)))
4023 goto out;
4024 create_pit:
79fac95e 4025 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 4026 r = -EEXIST;
4027 if (kvm->arch.vpit)
4028 goto create_pit_unlock;
7837699f 4029 r = -ENOMEM;
c5ff41ce 4030 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4031 if (kvm->arch.vpit)
4032 r = 0;
269e05e4 4033 create_pit_unlock:
79fac95e 4034 mutex_unlock(&kvm->slots_lock);
7837699f 4035 break;
1fe779f8
CO		 4036 case KVM_GET_IRQCHIP: {
4037 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4038 struct kvm_irqchip *chip;
1fe779f8 4039
ff5c2c03
SL		 4040 chip = memdup_user(argp, sizeof(*chip));
4041 if (IS_ERR(chip)) {
4042 r = PTR_ERR(chip);
1fe779f8 4043 goto out;
ff5c2c03
SL		 4044 }
4045
1fe779f8
CO		 4046 r = -ENXIO;
4047 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4048 goto get_irqchip_out;
4049 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4050 if (r)
f0d66275 4051 goto get_irqchip_out;
1fe779f8 4052 r = -EFAULT;
f0d66275
DH		 4053 if (copy_to_user(argp, chip, sizeof *chip))
4054 goto get_irqchip_out;
1fe779f8 4055 r = 0;
f0d66275
DH		 4056 get_irqchip_out:
4057 kfree(chip);
1fe779f8
CO		 4058 break;
4059 }
4060 case KVM_SET_IRQCHIP: {
4061 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4062 struct kvm_irqchip *chip;
1fe779f8 4063
ff5c2c03
SL		 4064 chip = memdup_user(argp, sizeof(*chip));
4065 if (IS_ERR(chip)) {
4066 r = PTR_ERR(chip);
1fe779f8 4067 goto out;
ff5c2c03
SL		 4068 }
4069
1fe779f8
CO		 4070 r = -ENXIO;
4071 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4072 goto set_irqchip_out;
4073 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4074 if (r)
f0d66275 4075 goto set_irqchip_out;
1fe779f8 4076 r = 0;
f0d66275
DH		 4077 set_irqchip_out:
4078 kfree(chip);
1fe779f8
CO		 4079 break;
4080 }
e0f63cb9 4081 case KVM_GET_PIT: {
e0f63cb9 4082 r = -EFAULT;
f0d66275 4083 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4084 goto out;
4085 r = -ENXIO;
4086 if (!kvm->arch.vpit)
4087 goto out;
f0d66275 4088 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4089 if (r)
4090 goto out;
4091 r = -EFAULT;
f0d66275 4092 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4093 goto out;
4094 r = 0;
4095 break;
4096 }
4097 case KVM_SET_PIT: {
e0f63cb9 4098 r = -EFAULT;
f0d66275 4099 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4100 goto out;
4101 r = -ENXIO;
4102 if (!kvm->arch.vpit)
4103 goto out;
f0d66275 4104 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4105 break;
4106 }
e9f42757
BK		 4107 case KVM_GET_PIT2: {
4108 r = -ENXIO;
4109 if (!kvm->arch.vpit)
4110 goto out;
4111 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4112 if (r)
4113 goto out;
4114 r = -EFAULT;
4115 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4116 goto out;
4117 r = 0;
4118 break;
4119 }
4120 case KVM_SET_PIT2: {
4121 r = -EFAULT;
4122 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4123 goto out;
4124 r = -ENXIO;
4125 if (!kvm->arch.vpit)
4126 goto out;
4127 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4128 break;
4129 }
52d939a0
MT		 4130 case KVM_REINJECT_CONTROL: {
4131 struct kvm_reinject_control control;
4132 r = -EFAULT;
4133 if (copy_from_user(&control, argp, sizeof(control)))
4134 goto out;
4135 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4136 break;
4137 }
ffde22ac
ES		 4138 case KVM_XEN_HVM_CONFIG: {
4139 r = -EFAULT;
4140 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4141 sizeof(struct kvm_xen_hvm_config)))
4142 goto out;
4143 r = -EINVAL;
4144 if (kvm->arch.xen_hvm_config.flags)
4145 goto out;
4146 r = 0;
4147 break;
4148 }
afbcf7ab 4149 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4150 struct kvm_clock_data user_ns;
4151 u64 now_ns;
4152 s64 delta;
4153
4154 r = -EFAULT;
4155 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4156 goto out;
4157
4158 r = -EINVAL;
4159 if (user_ns.flags)
4160 goto out;
4161
4162 r = 0;
395c6b0a 4163 local_irq_disable();
759379dd 4164 now_ns = get_kernel_ns();
afbcf7ab 4165 delta = user_ns.clock - now_ns;
395c6b0a 4166 local_irq_enable();
afbcf7ab 4167 kvm->arch.kvmclock_offset = delta;
2e762ff7 4168 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4169 break;
4170 }
4171 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4172 struct kvm_clock_data user_ns;
4173 u64 now_ns;
4174
395c6b0a 4175 local_irq_disable();
759379dd 4176 now_ns = get_kernel_ns();
afbcf7ab 4177 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4178 local_irq_enable();
afbcf7ab 4179 user_ns.flags = 0;
97e69aa6 4180 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4181
4182 r = -EFAULT;
4183 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4184 goto out;
4185 r = 0;
4186 break;
4187 }
90de4a18
NA		 4188 case KVM_ENABLE_CAP: {
4189 struct kvm_enable_cap cap;
afbcf7ab 4190
90de4a18
NA		 4191 r = -EFAULT;
4192 if (copy_from_user(&cap, argp, sizeof(cap)))
4193 goto out;
4194 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4195 break;
4196 }
1fe779f8 4197 default:
c274e03a 4198 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4199 }
4200out:
4201 return r;
4202}
4203
a16b043c 4204static void kvm_init_msr_list(void)
043405e1
CO		 4205{
4206 u32 dummy[2];
4207 unsigned i, j;
4208
e3267cbb
GC		 4209 /* skip the first msrs in the list. KVM-specific */
4210 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4211 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4212 continue;
93c4adc7
PB		 4213
4214 /*
4215 * Even MSRs that are valid in the host may not be exposed
4216 * to the guests in some cases. We could work around this
4217 * in VMX with the generic MSR save/load machinery, but it
4218 * is not really worthwhile since it will really only
4219 * happen with nested virtualization.
4220 */
4221 switch (msrs_to_save[i]) {
4222 case MSR_IA32_BNDCFGS:
4223 if (!kvm_x86_ops->mpx_supported())
4224 continue;
4225 break;
4226 default:
4227 break;
4228 }
4229
043405e1
CO		 4230 if (j < i)
4231 msrs_to_save[j] = msrs_to_save[i];
4232 j++;
4233 }
4234 num_msrs_to_save = j;
4235}
4236
bda9020e
MT		 4237static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4238 const void *v)
bbd9b64e 4239{
70252a10
AK		 4240 int handled = 0;
4241 int n;
4242
4243 do {
4244 n = min(len, 8);
4245 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4246 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4247 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4248 break;
4249 handled += n;
4250 addr += n;
4251 len -= n;
4252 v += n;
4253 } while (len);
bbd9b64e 4254
70252a10 4255 return handled;
bbd9b64e
CO		 4256}
4257
bda9020e 4258static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4259{
70252a10
AK		 4260 int handled = 0;
4261 int n;
4262
4263 do {
4264 n = min(len, 8);
4265 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4266 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4267 addr, n, v))
4268 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4269 break;
4270 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4271 handled += n;
4272 addr += n;
4273 len -= n;
4274 v += n;
4275 } while (len);
bbd9b64e 4276
70252a10 4277 return handled;
bbd9b64e
CO		 4278}
4279
2dafc6c2
GN		 4280static void kvm_set_segment(struct kvm_vcpu *vcpu,
4281 struct kvm_segment *var, int seg)
4282{
4283 kvm_x86_ops->set_segment(vcpu, var, seg);
4284}
4285
4286void kvm_get_segment(struct kvm_vcpu *vcpu,
4287 struct kvm_segment *var, int seg)
4288{
4289 kvm_x86_ops->get_segment(vcpu, var, seg);
4290}
4291
54987b7a
PB		 4292gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4293 struct x86_exception *exception)
02f59dc9
JR		 4294{
4295 gpa_t t_gpa;
02f59dc9
JR		 4296
4297 BUG_ON(!mmu_is_nested(vcpu));
4298
4299 /* NPT walks are always user-walks */
4300 access |= PFERR_USER_MASK;
54987b7a 4301 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4302
4303 return t_gpa;
4304}
4305
ab9ae313
AK		 4306gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4307 struct x86_exception *exception)
1871c602
GN		 4308{
4309 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4310 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4311}
4312
ab9ae313
AK		 4313 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4314 struct x86_exception *exception)
1871c602
GN		 4315{
4316 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4317 access |= PFERR_FETCH_MASK;
ab9ae313 4318 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4319}
4320
ab9ae313
AK		 4321gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4322 struct x86_exception *exception)
1871c602
GN		 4323{
4324 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4325 access |= PFERR_WRITE_MASK;
ab9ae313 4326 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4327}
4328
4329/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4330gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4331 struct x86_exception *exception)
1871c602 4332{
ab9ae313 4333 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4334}
4335
4336static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4337 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4338 struct x86_exception *exception)
bbd9b64e
CO		 4339{
4340 void *data = val;
10589a46 4341 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4342
4343 while (bytes) {
14dfe855 4344 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4345 exception);
bbd9b64e 4346 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4347 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4348 int ret;
4349
bcc55cba 4350 if (gpa == UNMAPPED_GVA)
ab9ae313 4351 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4352 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4353 offset, toread);
10589a46 4354 if (ret < 0) {
c3cd7ffa 4355 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4356 goto out;
4357 }
bbd9b64e 4358
77c2002e
IE		 4359 bytes -= toread;
4360 data += toread;
4361 addr += toread;
bbd9b64e 4362 }
10589a46 4363out:
10589a46 4364 return r;
bbd9b64e 4365}
77c2002e 4366
1871c602 4367/* used for instruction fetching */
0f65dd70
AK		 4368static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4369 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4370 struct x86_exception *exception)
1871c602 4371{
0f65dd70 4372 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4373 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4374 unsigned offset;
4375 int ret;
0f65dd70 4376
44583cba
PB		 4377 /* Inline kvm_read_guest_virt_helper for speed. */
4378 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4379 exception);
4380 if (unlikely(gpa == UNMAPPED_GVA))
4381 return X86EMUL_PROPAGATE_FAULT;
4382
4383 offset = addr & (PAGE_SIZE-1);
4384 if (WARN_ON(offset + bytes > PAGE_SIZE))
4385 bytes = (unsigned)PAGE_SIZE - offset;
4386 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4387 offset, bytes);
4388 if (unlikely(ret < 0))
4389 return X86EMUL_IO_NEEDED;
4390
4391 return X86EMUL_CONTINUE;
1871c602
GN		 4392}
4393
064aea77 4394int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4395 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4396 struct x86_exception *exception)
1871c602 4397{
0f65dd70 4398 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4399 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4400
1871c602 4401 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4402 exception);
1871c602 4403}
064aea77 4404EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4405
0f65dd70
AK		 4406static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4407 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4408 struct x86_exception *exception)
1871c602 4409{
0f65dd70 4410 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4411 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4412}
4413
6a4d7550 4414int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4415 gva_t addr, void *val,
2dafc6c2 4416 unsigned int bytes,
bcc55cba 4417 struct x86_exception *exception)
77c2002e 4418{
0f65dd70 4419 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4420 void *data = val;
4421 int r = X86EMUL_CONTINUE;
4422
4423 while (bytes) {
14dfe855
JR		 4424 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4425 PFERR_WRITE_MASK,
ab9ae313 4426 exception);
77c2002e
IE		 4427 unsigned offset = addr & (PAGE_SIZE-1);
4428 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4429 int ret;
4430
bcc55cba 4431 if (gpa == UNMAPPED_GVA)
ab9ae313 4432 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4433 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4434 if (ret < 0) {
c3cd7ffa 4435 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4436 goto out;
4437 }
4438
4439 bytes -= towrite;
4440 data += towrite;
4441 addr += towrite;
4442 }
4443out:
4444 return r;
4445}
6a4d7550 4446EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4447
af7cc7d1
XG		 4448static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4449 gpa_t *gpa, struct x86_exception *exception,
4450 bool write)
4451{
97d64b78
AK		 4452 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4453 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4454
97d64b78 4455 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4456 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4457 vcpu->arch.access, access)) {
bebb106a
XG		 4458 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4459 (gva & (PAGE_SIZE - 1));
4f022648 4460 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4461 return 1;
4462 }
4463
af7cc7d1
XG		 4464 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4465
4466 if (*gpa == UNMAPPED_GVA)
4467 return -1;
4468
4469 /* For APIC access vmexit */
4470 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4471 return 1;
4472
4f022648
XG		 4473 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4474 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4475 return 1;
4f022648 4476 }
bebb106a 4477
af7cc7d1
XG		 4478 return 0;
4479}
4480
3200f405 4481int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4482 const void *val, int bytes)
bbd9b64e
CO		 4483{
4484 int ret;
4485
4486 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4487 if (ret < 0)
bbd9b64e 4488 return 0;
f57f2ef5 4489 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4490 return 1;
4491}
4492
77d197b2
XG		 4493struct read_write_emulator_ops {
4494 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4495 int bytes);
4496 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4497 void *val, int bytes);
4498 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4499 int bytes, void *val);
4500 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4501 void *val, int bytes);
4502 bool write;
4503};
4504
4505static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4506{
4507 if (vcpu->mmio_read_completed) {
77d197b2 4508 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4509 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4510 vcpu->mmio_read_completed = 0;
4511 return 1;
4512 }
4513
4514 return 0;
4515}
4516
4517static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4518 void *val, int bytes)
4519{
4520 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4521}
4522
4523static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4524 void *val, int bytes)
4525{
4526 return emulator_write_phys(vcpu, gpa, val, bytes);
4527}
4528
4529static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4530{
4531 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4532 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4533}
4534
4535static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4536 void *val, int bytes)
4537{
4538 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4539 return X86EMUL_IO_NEEDED;
4540}
4541
4542static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4543 void *val, int bytes)
4544{
f78146b0
AK		 4545 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4546
87da7e66 4547 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4548 return X86EMUL_CONTINUE;
4549}
4550
0fbe9b0b 4551static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4552 .read_write_prepare = read_prepare,
4553 .read_write_emulate = read_emulate,
4554 .read_write_mmio = vcpu_mmio_read,
4555 .read_write_exit_mmio = read_exit_mmio,
4556};
4557
0fbe9b0b 4558static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4559 .read_write_emulate = write_emulate,
4560 .read_write_mmio = write_mmio,
4561 .read_write_exit_mmio = write_exit_mmio,
4562 .write = true,
4563};
4564
22388a3c
XG		 4565static int emulator_read_write_onepage(unsigned long addr, void *val,
4566 unsigned int bytes,
4567 struct x86_exception *exception,
4568 struct kvm_vcpu *vcpu,
0fbe9b0b 4569 const struct read_write_emulator_ops *ops)
bbd9b64e 4570{
af7cc7d1
XG		 4571 gpa_t gpa;
4572 int handled, ret;
22388a3c 4573 bool write = ops->write;
f78146b0 4574 struct kvm_mmio_fragment *frag;
10589a46 4575
22388a3c 4576 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4577
af7cc7d1 4578 if (ret < 0)
bbd9b64e 4579 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4580
4581 /* For APIC access vmexit */
af7cc7d1 4582 if (ret)
bbd9b64e
CO		 4583 goto mmio;
4584
22388a3c 4585 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4586 return X86EMUL_CONTINUE;
4587
4588mmio:
4589 /*
4590 * Is this MMIO handled locally?
4591 */
22388a3c 4592 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4593 if (handled == bytes)
bbd9b64e 4594 return X86EMUL_CONTINUE;
bbd9b64e 4595
70252a10
AK		 4596 gpa += handled;
4597 bytes -= handled;
4598 val += handled;
4599
87da7e66
XG		 4600 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4601 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4602 frag->gpa = gpa;
4603 frag->data = val;
4604 frag->len = bytes;
f78146b0 4605 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4606}
4607
52eb5a6d
XL		 4608static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4609 unsigned long addr,
22388a3c
XG		 4610 void *val, unsigned int bytes,
4611 struct x86_exception *exception,
0fbe9b0b 4612 const struct read_write_emulator_ops *ops)
bbd9b64e 4613{
0f65dd70 4614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4615 gpa_t gpa;
4616 int rc;
4617
4618 if (ops->read_write_prepare &&
4619 ops->read_write_prepare(vcpu, val, bytes))
4620 return X86EMUL_CONTINUE;
4621
4622 vcpu->mmio_nr_fragments = 0;
0f65dd70 4623
bbd9b64e
CO		 4624 /* Crossing a page boundary? */
4625 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4626 int now;
bbd9b64e
CO		 4627
4628 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4629 rc = emulator_read_write_onepage(addr, val, now, exception,
4630 vcpu, ops);
4631
bbd9b64e
CO		 4632 if (rc != X86EMUL_CONTINUE)
4633 return rc;
4634 addr += now;
bac15531
NA		 4635 if (ctxt->mode != X86EMUL_MODE_PROT64)
4636 addr = (u32)addr;
bbd9b64e
CO		 4637 val += now;
4638 bytes -= now;
4639 }
22388a3c 4640
f78146b0
AK		 4641 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4642 vcpu, ops);
4643 if (rc != X86EMUL_CONTINUE)
4644 return rc;
4645
4646 if (!vcpu->mmio_nr_fragments)
4647 return rc;
4648
4649 gpa = vcpu->mmio_fragments[0].gpa;
4650
4651 vcpu->mmio_needed = 1;
4652 vcpu->mmio_cur_fragment = 0;
4653
87da7e66 4654 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4655 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4656 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4657 vcpu->run->mmio.phys_addr = gpa;
4658
4659 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4660}
4661
4662static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4663 unsigned long addr,
4664 void *val,
4665 unsigned int bytes,
4666 struct x86_exception *exception)
4667{
4668 return emulator_read_write(ctxt, addr, val, bytes,
4669 exception, &read_emultor);
4670}
4671
52eb5a6d 4672static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4673 unsigned long addr,
4674 const void *val,
4675 unsigned int bytes,
4676 struct x86_exception *exception)
4677{
4678 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4679 exception, &write_emultor);
bbd9b64e 4680}
bbd9b64e 4681
daea3e73
AK		 4682#define CMPXCHG_TYPE(t, ptr, old, new) \
4683 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4684
4685#ifdef CONFIG_X86_64
4686# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4687#else
4688# define CMPXCHG64(ptr, old, new) \
9749a6c0 4689 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4690#endif
4691
0f65dd70
AK		 4692static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4693 unsigned long addr,
bbd9b64e
CO		 4694 const void *old,
4695 const void *new,
4696 unsigned int bytes,
0f65dd70 4697 struct x86_exception *exception)
bbd9b64e 4698{
0f65dd70 4699 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4700 gpa_t gpa;
4701 struct page *page;
4702 char *kaddr;
4703 bool exchanged;
2bacc55c 4704
daea3e73
AK		 4705 /* guests cmpxchg8b have to be emulated atomically */
4706 if (bytes > 8 || (bytes & (bytes - 1)))
4707 goto emul_write;
10589a46 4708
daea3e73 4709 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4710
daea3e73
AK		 4711 if (gpa == UNMAPPED_GVA ||
4712 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4713 goto emul_write;
2bacc55c 4714
daea3e73
AK		 4715 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4716 goto emul_write;
72dc67a6 4717
daea3e73 4718 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4719 if (is_error_page(page))
c19b8bd6 4720 goto emul_write;
72dc67a6 4721
8fd75e12 4722 kaddr = kmap_atomic(page);
daea3e73
AK		 4723 kaddr += offset_in_page(gpa);
4724 switch (bytes) {
4725 case 1:
4726 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4727 break;
4728 case 2:
4729 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4730 break;
4731 case 4:
4732 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4733 break;
4734 case 8:
4735 exchanged = CMPXCHG64(kaddr, old, new);
4736 break;
4737 default:
4738 BUG();
2bacc55c 4739 }
8fd75e12 4740 kunmap_atomic(kaddr);
daea3e73
AK		 4741 kvm_release_page_dirty(page);
4742
4743 if (!exchanged)
4744 return X86EMUL_CMPXCHG_FAILED;
4745
d3714010 4746 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4747 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4748
4749 return X86EMUL_CONTINUE;
4a5f48f6 4750
3200f405 4751emul_write:
daea3e73 4752 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4753
0f65dd70 4754 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4755}
4756
cf8f70bf
GN		 4757static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4758{
4759 /* TODO: String I/O for in kernel device */
4760 int r;
4761
4762 if (vcpu->arch.pio.in)
e32edf4f 4763 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4764 vcpu->arch.pio.size, pd);
4765 else
e32edf4f 4766 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4767 vcpu->arch.pio.port, vcpu->arch.pio.size,
4768 pd);
4769 return r;
4770}
4771
6f6fbe98
XG		 4772static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4773 unsigned short port, void *val,
4774 unsigned int count, bool in)
cf8f70bf 4775{
cf8f70bf 4776 vcpu->arch.pio.port = port;
6f6fbe98 4777 vcpu->arch.pio.in = in;
7972995b 4778 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4779 vcpu->arch.pio.size = size;
4780
4781 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4782 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4783 return 1;
4784 }
4785
4786 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4787 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4788 vcpu->run->io.size = size;
4789 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4790 vcpu->run->io.count = count;
4791 vcpu->run->io.port = port;
4792
4793 return 0;
4794}
4795
6f6fbe98
XG		 4796static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4797 int size, unsigned short port, void *val,
4798 unsigned int count)
cf8f70bf 4799{
ca1d4a9e 4800 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4801 int ret;
ca1d4a9e 4802
6f6fbe98
XG		 4803 if (vcpu->arch.pio.count)
4804 goto data_avail;
cf8f70bf 4805
6f6fbe98
XG		 4806 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4807 if (ret) {
4808data_avail:
4809 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4810 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4811 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4812 return 1;
4813 }
4814
cf8f70bf
GN		 4815 return 0;
4816}
4817
6f6fbe98
XG		 4818static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4819 int size, unsigned short port,
4820 const void *val, unsigned int count)
4821{
4822 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4823
4824 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4825 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4826 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4827}
4828
bbd9b64e
CO		 4829static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4830{
4831 return kvm_x86_ops->get_segment_base(vcpu, seg);
4832}
4833
3cb16fe7 4834static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4835{
3cb16fe7 4836 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4837}
4838
5cb56059 4839int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4840{
4841 if (!need_emulate_wbinvd(vcpu))
4842 return X86EMUL_CONTINUE;
4843
4844 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4845 int cpu = get_cpu();
4846
4847 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4848 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4849 wbinvd_ipi, NULL, 1);
2eec7343 4850 put_cpu();
f5f48ee1 4851 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4852 } else
4853 wbinvd();
f5f48ee1
SY		 4854 return X86EMUL_CONTINUE;
4855}
5cb56059
JS		 4856
4857int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4858{
4859 kvm_x86_ops->skip_emulated_instruction(vcpu);
4860 return kvm_emulate_wbinvd_noskip(vcpu);
4861}
f5f48ee1
SY		 4862EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4863
5cb56059
JS		 4864
4865
bcaf5cc5
AK		 4866static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4867{
5cb56059 4868 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4869}
4870
52eb5a6d
XL		 4871static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4872 unsigned long *dest)
bbd9b64e 4873{
16f8a6f9 4874 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4875}
4876
52eb5a6d
XL		 4877static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4878 unsigned long value)
bbd9b64e 4879{
338dbc97 4880
717746e3 4881 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4882}
4883
52a46617 4884static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4885{
52a46617 4886 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4887}
4888
717746e3 4889static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4890{
717746e3 4891 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4892 unsigned long value;
4893
4894 switch (cr) {
4895 case 0:
4896 value = kvm_read_cr0(vcpu);
4897 break;
4898 case 2:
4899 value = vcpu->arch.cr2;
4900 break;
4901 case 3:
9f8fe504 4902 value = kvm_read_cr3(vcpu);
52a46617
GN		 4903 break;
4904 case 4:
4905 value = kvm_read_cr4(vcpu);
4906 break;
4907 case 8:
4908 value = kvm_get_cr8(vcpu);
4909 break;
4910 default:
a737f256 4911 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4912 return 0;
4913 }
4914
4915 return value;
4916}
4917
717746e3 4918static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4919{
717746e3 4920 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4921 int res = 0;
4922
52a46617
GN		 4923 switch (cr) {
4924 case 0:
49a9b07e 4925 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4926 break;
4927 case 2:
4928 vcpu->arch.cr2 = val;
4929 break;
4930 case 3:
2390218b 4931 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4932 break;
4933 case 4:
a83b29c6 4934 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4935 break;
4936 case 8:
eea1cff9 4937 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4938 break;
4939 default:
a737f256 4940 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4941 res = -1;
52a46617 4942 }
0f12244f
GN		 4943
4944 return res;
52a46617
GN		 4945}
4946
717746e3 4947static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4948{
717746e3 4949 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4950}
4951
4bff1e86 4952static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4953{
4bff1e86 4954 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4955}
4956
4bff1e86 4957static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4958{
4bff1e86 4959 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4960}
4961
1ac9d0cf
AK		 4962static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4963{
4964 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4965}
4966
4967static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4968{
4969 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4970}
4971
4bff1e86
AK		 4972static unsigned long emulator_get_cached_segment_base(
4973 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4974{
4bff1e86 4975 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4976}
4977
1aa36616
AK		 4978static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4979 struct desc_struct *desc, u32 *base3,
4980 int seg)
2dafc6c2
GN		 4981{
4982 struct kvm_segment var;
4983
4bff1e86 4984 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4985 *selector = var.selector;
2dafc6c2 4986
378a8b09
GN		 4987 if (var.unusable) {
4988 memset(desc, 0, sizeof(*desc));
2dafc6c2 4989 return false;
378a8b09 4990 }
2dafc6c2
GN		 4991
4992 if (var.g)
4993 var.limit >>= 12;
4994 set_desc_limit(desc, var.limit);
4995 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4996#ifdef CONFIG_X86_64
4997 if (base3)
4998 *base3 = var.base >> 32;
4999#endif
2dafc6c2
GN		 5000 desc->type = var.type;
5001 desc->s = var.s;
5002 desc->dpl = var.dpl;
5003 desc->p = var.present;
5004 desc->avl = var.avl;
5005 desc->l = var.l;
5006 desc->d = var.db;
5007 desc->g = var.g;
5008
5009 return true;
5010}
5011
1aa36616
AK		 5012static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5013 struct desc_struct *desc, u32 base3,
5014 int seg)
2dafc6c2 5015{
4bff1e86 5016 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5017 struct kvm_segment var;
5018
1aa36616 5019 var.selector = selector;
2dafc6c2 5020 var.base = get_desc_base(desc);
5601d05b
GN		 5021#ifdef CONFIG_X86_64
5022 var.base |= ((u64)base3) << 32;
5023#endif
2dafc6c2
GN		 5024 var.limit = get_desc_limit(desc);
5025 if (desc->g)
5026 var.limit = (var.limit << 12) | 0xfff;
5027 var.type = desc->type;
2dafc6c2
GN		 5028 var.dpl = desc->dpl;
5029 var.db = desc->d;
5030 var.s = desc->s;
5031 var.l = desc->l;
5032 var.g = desc->g;
5033 var.avl = desc->avl;
5034 var.present = desc->p;
5035 var.unusable = !var.present;
5036 var.padding = 0;
5037
5038 kvm_set_segment(vcpu, &var, seg);
5039 return;
5040}
5041
717746e3
AK		 5042static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5043 u32 msr_index, u64 *pdata)
5044{
5045 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
5046}
5047
5048static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5049 u32 msr_index, u64 data)
5050{
8fe8ab46
WA		 5051 struct msr_data msr;
5052
5053 msr.data = data;
5054 msr.index = msr_index;
5055 msr.host_initiated = false;
5056 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5057}
5058
67f4d428
NA		 5059static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5060 u32 pmc)
5061{
5062 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
5063}
5064
222d21aa
AK		 5065static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5066 u32 pmc, u64 *pdata)
5067{
5068 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
5069}
5070
6c3287f7
AK		 5071static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5072{
5073 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5074}
5075
5037f6f3
AK		 5076static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5077{
5078 preempt_disable();
5197b808 5079 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5080 /*
5081 * CR0.TS may reference the host fpu state, not the guest fpu state,
5082 * so it may be clear at this point.
5083 */
5084 clts();
5085}
5086
5087static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5088{
5089 preempt_enable();
5090}
5091
2953538e 5092static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5093 struct x86_instruction_info *info,
c4f035c6
AK		 5094 enum x86_intercept_stage stage)
5095{
2953538e 5096 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5097}
5098
0017f93a 5099static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5100 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5101{
0017f93a 5102 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5103}
5104
dd856efa
AK		 5105static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5106{
5107 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5108}
5109
5110static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5111{
5112 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5113}
5114
801806d9
NA		 5115static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5116{
5117 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5118}
5119
0225fb50 5120static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5121 .read_gpr = emulator_read_gpr,
5122 .write_gpr = emulator_write_gpr,
1871c602 5123 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5124 .write_std = kvm_write_guest_virt_system,
1871c602 5125 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5126 .read_emulated = emulator_read_emulated,
5127 .write_emulated = emulator_write_emulated,
5128 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5129 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5130 .pio_in_emulated = emulator_pio_in_emulated,
5131 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5132 .get_segment = emulator_get_segment,
5133 .set_segment = emulator_set_segment,
5951c442 5134 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5135 .get_gdt = emulator_get_gdt,
160ce1f1 5136 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5137 .set_gdt = emulator_set_gdt,
5138 .set_idt = emulator_set_idt,
52a46617
GN		 5139 .get_cr = emulator_get_cr,
5140 .set_cr = emulator_set_cr,
9c537244 5141 .cpl = emulator_get_cpl,
35aa5375
GN		 5142 .get_dr = emulator_get_dr,
5143 .set_dr = emulator_set_dr,
717746e3
AK		 5144 .set_msr = emulator_set_msr,
5145 .get_msr = emulator_get_msr,
67f4d428 5146 .check_pmc = emulator_check_pmc,
222d21aa 5147 .read_pmc = emulator_read_pmc,
6c3287f7 5148 .halt = emulator_halt,
bcaf5cc5 5149 .wbinvd = emulator_wbinvd,
d6aa1000 5150 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5151 .get_fpu = emulator_get_fpu,
5152 .put_fpu = emulator_put_fpu,
c4f035c6 5153 .intercept = emulator_intercept,
bdb42f5a 5154 .get_cpuid = emulator_get_cpuid,
801806d9 5155 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5156};
5157
95cb2295
GN		 5158static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5159{
37ccdcbe 5160 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5161 /*
5162 * an sti; sti; sequence only disable interrupts for the first
5163 * instruction. So, if the last instruction, be it emulated or
5164 * not, left the system with the INT_STI flag enabled, it
5165 * means that the last instruction is an sti. We should not
5166 * leave the flag on in this case. The same goes for mov ss
5167 */
37ccdcbe
PB		 5168 if (int_shadow & mask)
5169 mask = 0;
6addfc42 5170 if (unlikely(int_shadow || mask)) {
95cb2295 5171 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5172 if (!mask)
5173 kvm_make_request(KVM_REQ_EVENT, vcpu);
5174 }
95cb2295
GN		 5175}
5176
ef54bcfe 5177static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5178{
5179 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5180 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5181 return kvm_propagate_fault(vcpu, &ctxt->exception);
5182
5183 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5184 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5185 ctxt->exception.error_code);
54b8486f 5186 else
da9cb575 5187 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5188 return false;
54b8486f
GN		 5189}
5190
8ec4722d
MG		 5191static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5192{
adf52235 5193 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5194 int cs_db, cs_l;
5195
8ec4722d
MG		 5196 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5197
adf52235
TY		 5198 ctxt->eflags = kvm_get_rflags(vcpu);
5199 ctxt->eip = kvm_rip_read(vcpu);
5200 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5201 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5202 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5203 cs_db ? X86EMUL_MODE_PROT32 :
5204 X86EMUL_MODE_PROT16;
5205 ctxt->guest_mode = is_guest_mode(vcpu);
5206
dd856efa 5207 init_decode_cache(ctxt);
7ae441ea 5208 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5209}
5210
71f9833b 5211int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5212{
9d74191a 5213 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5214 int ret;
5215
5216 init_emulate_ctxt(vcpu);
5217
9dac77fa
AK		 5218 ctxt->op_bytes = 2;
5219 ctxt->ad_bytes = 2;
5220 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5221 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5222
5223 if (ret != X86EMUL_CONTINUE)
5224 return EMULATE_FAIL;
5225
9dac77fa 5226 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5227 kvm_rip_write(vcpu, ctxt->eip);
5228 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5229
5230 if (irq == NMI_VECTOR)
7460fb4a 5231 vcpu->arch.nmi_pending = 0;
63995653
MG		 5232 else
5233 vcpu->arch.interrupt.pending = false;
5234
5235 return EMULATE_DONE;
5236}
5237EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5238
6d77dbfc
GN		 5239static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5240{
fc3a9157
JR		 5241 int r = EMULATE_DONE;
5242
6d77dbfc
GN		 5243 ++vcpu->stat.insn_emulation_fail;
5244 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5245 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5246 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5247 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5248 vcpu->run->internal.ndata = 0;
5249 r = EMULATE_FAIL;
5250 }
6d77dbfc 5251 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5252
5253 return r;
6d77dbfc
GN		 5254}
5255
93c05d3e 5256static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5257 bool write_fault_to_shadow_pgtable,
5258 int emulation_type)
a6f177ef 5259{
95b3cf69 5260 gpa_t gpa = cr2;
8e3d9d06 5261 pfn_t pfn;
a6f177ef 5262
991eebf9
GN		 5263 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5264 return false;
5265
95b3cf69
XG		 5266 if (!vcpu->arch.mmu.direct_map) {
5267 /*
5268 * Write permission should be allowed since only
5269 * write access need to be emulated.
5270 */
5271 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5272
95b3cf69
XG		 5273 /*
5274 * If the mapping is invalid in guest, let cpu retry
5275 * it to generate fault.
5276 */
5277 if (gpa == UNMAPPED_GVA)
5278 return true;
5279 }
a6f177ef 5280
8e3d9d06
XG		 5281 /*
5282 * Do not retry the unhandleable instruction if it faults on the
5283 * readonly host memory, otherwise it will goto a infinite loop:
5284 * retry instruction -> write #PF -> emulation fail -> retry
5285 * instruction -> ...
5286 */
5287 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5288
5289 /*
5290 * If the instruction failed on the error pfn, it can not be fixed,
5291 * report the error to userspace.
5292 */
5293 if (is_error_noslot_pfn(pfn))
5294 return false;
5295
5296 kvm_release_pfn_clean(pfn);
5297
5298 /* The instructions are well-emulated on direct mmu. */
5299 if (vcpu->arch.mmu.direct_map) {
5300 unsigned int indirect_shadow_pages;
5301
5302 spin_lock(&vcpu->kvm->mmu_lock);
5303 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5304 spin_unlock(&vcpu->kvm->mmu_lock);
5305
5306 if (indirect_shadow_pages)
5307 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5308
a6f177ef 5309 return true;
8e3d9d06 5310 }
a6f177ef 5311
95b3cf69
XG		 5312 /*
5313 * if emulation was due to access to shadowed page table
5314 * and it failed try to unshadow page and re-enter the
5315 * guest to let CPU execute the instruction.
5316 */
5317 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5318
5319 /*
5320 * If the access faults on its page table, it can not
5321 * be fixed by unprotecting shadow page and it should
5322 * be reported to userspace.
5323 */
5324 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5325}
5326
1cb3f3ae
XG		 5327static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5328 unsigned long cr2, int emulation_type)
5329{
5330 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5331 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5332
5333 last_retry_eip = vcpu->arch.last_retry_eip;
5334 last_retry_addr = vcpu->arch.last_retry_addr;
5335
5336 /*
5337 * If the emulation is caused by #PF and it is non-page_table
5338 * writing instruction, it means the VM-EXIT is caused by shadow
5339 * page protected, we can zap the shadow page and retry this
5340 * instruction directly.
5341 *
5342 * Note: if the guest uses a non-page-table modifying instruction
5343 * on the PDE that points to the instruction, then we will unmap
5344 * the instruction and go to an infinite loop. So, we cache the
5345 * last retried eip and the last fault address, if we meet the eip
5346 * and the address again, we can break out of the potential infinite
5347 * loop.
5348 */
5349 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5350
5351 if (!(emulation_type & EMULTYPE_RETRY))
5352 return false;
5353
5354 if (x86_page_table_writing_insn(ctxt))
5355 return false;
5356
5357 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5358 return false;
5359
5360 vcpu->arch.last_retry_eip = ctxt->eip;
5361 vcpu->arch.last_retry_addr = cr2;
5362
5363 if (!vcpu->arch.mmu.direct_map)
5364 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5365
22368028 5366 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5367
5368 return true;
5369}
5370
716d51ab
GN		 5371static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5372static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5373
4a1e10d5
PB		 5374static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5375 unsigned long *db)
5376{
5377 u32 dr6 = 0;
5378 int i;
5379 u32 enable, rwlen;
5380
5381 enable = dr7;
5382 rwlen = dr7 >> 16;
5383 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5384 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5385 dr6 |= (1 << i);
5386 return dr6;
5387}
5388
6addfc42 5389static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5390{
5391 struct kvm_run *kvm_run = vcpu->run;
5392
5393 /*
6addfc42
PB		 5394 * rflags is the old, "raw" value of the flags. The new value has
5395 * not been saved yet.
663f4c61
PB		 5396 *
5397 * This is correct even for TF set by the guest, because "the
5398 * processor will not generate this exception after the instruction
5399 * that sets the TF flag".
5400 */
663f4c61
PB		 5401 if (unlikely(rflags & X86_EFLAGS_TF)) {
5402 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5403 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5404 DR6_RTM;
663f4c61
PB		 5405 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5406 kvm_run->debug.arch.exception = DB_VECTOR;
5407 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5408 *r = EMULATE_USER_EXIT;
5409 } else {
5410 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5411 /*
5412 * "Certain debug exceptions may clear bit 0-3. The
5413 * remaining contents of the DR6 register are never
5414 * cleared by the processor".
5415 */
5416 vcpu->arch.dr6 &= ~15;
6f43ed01 5417 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5418 kvm_queue_exception(vcpu, DB_VECTOR);
5419 }
5420 }
5421}
5422
4a1e10d5
PB		 5423static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5424{
4a1e10d5
PB		 5425 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5426 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5427 struct kvm_run *kvm_run = vcpu->run;
5428 unsigned long eip = kvm_get_linear_rip(vcpu);
5429 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5430 vcpu->arch.guest_debug_dr7,
5431 vcpu->arch.eff_db);
5432
5433 if (dr6 != 0) {
6f43ed01 5434 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5435 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5436 kvm_run->debug.arch.exception = DB_VECTOR;
5437 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5438 *r = EMULATE_USER_EXIT;
5439 return true;
5440 }
5441 }
5442
4161a569
NA		 5443 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5444 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5445 unsigned long eip = kvm_get_linear_rip(vcpu);
5446 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5447 vcpu->arch.dr7,
5448 vcpu->arch.db);
5449
5450 if (dr6 != 0) {
5451 vcpu->arch.dr6 &= ~15;
6f43ed01 5452 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5453 kvm_queue_exception(vcpu, DB_VECTOR);
5454 *r = EMULATE_DONE;
5455 return true;
5456 }
5457 }
5458
5459 return false;
5460}
5461
51d8b661
AP		 5462int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5463 unsigned long cr2,
dc25e89e
AP		 5464 int emulation_type,
5465 void *insn,
5466 int insn_len)
bbd9b64e 5467{
95cb2295 5468 int r;
9d74191a 5469 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5470 bool writeback = true;
93c05d3e 5471 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5472
93c05d3e
XG		 5473 /*
5474 * Clear write_fault_to_shadow_pgtable here to ensure it is
5475 * never reused.
5476 */
5477 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5478 kvm_clear_exception_queue(vcpu);
8d7d8102 5479
571008da 5480 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5481 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5482
5483 /*
5484 * We will reenter on the same instruction since
5485 * we do not set complete_userspace_io. This does not
5486 * handle watchpoints yet, those would be handled in
5487 * the emulate_ops.
5488 */
5489 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5490 return r;
5491
9d74191a
TY		 5492 ctxt->interruptibility = 0;
5493 ctxt->have_exception = false;
e0ad0b47 5494 ctxt->exception.vector = -1;
9d74191a 5495 ctxt->perm_ok = false;
bbd9b64e 5496
b51e974f 5497 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5498
9d74191a 5499 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5500
e46479f8 5501 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5502 ++vcpu->stat.insn_emulation;
1d2887e2 5503 if (r != EMULATION_OK) {
4005996e
AK		 5504 if (emulation_type & EMULTYPE_TRAP_UD)
5505 return EMULATE_FAIL;
991eebf9
GN		 5506 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5507 emulation_type))
bbd9b64e 5508 return EMULATE_DONE;
6d77dbfc
GN		 5509 if (emulation_type & EMULTYPE_SKIP)
5510 return EMULATE_FAIL;
5511 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5512 }
5513 }
5514
ba8afb6b 5515 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5516 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5517 if (ctxt->eflags & X86_EFLAGS_RF)
5518 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5519 return EMULATE_DONE;
5520 }
5521
1cb3f3ae
XG		 5522 if (retry_instruction(ctxt, cr2, emulation_type))
5523 return EMULATE_DONE;
5524
7ae441ea 5525 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5526 changes registers values during IO operation */
7ae441ea
GN		 5527 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5528 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5529 emulator_invalidate_register_cache(ctxt);
7ae441ea 5530 }
4d2179e1 5531
5cd21917 5532restart:
9d74191a 5533 r = x86_emulate_insn(ctxt);
bbd9b64e 5534
775fde86
JR		 5535 if (r == EMULATION_INTERCEPTED)
5536 return EMULATE_DONE;
5537
d2ddd1c4 5538 if (r == EMULATION_FAILED) {
991eebf9
GN		 5539 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5540 emulation_type))
c3cd7ffa
GN		 5541 return EMULATE_DONE;
5542
6d77dbfc 5543 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5544 }
5545
9d74191a 5546 if (ctxt->have_exception) {
d2ddd1c4 5547 r = EMULATE_DONE;
ef54bcfe
PB		 5548 if (inject_emulated_exception(vcpu))
5549 return r;
d2ddd1c4 5550 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5551 if (!vcpu->arch.pio.in) {
5552 /* FIXME: return into emulator if single-stepping. */
3457e419 5553 vcpu->arch.pio.count = 0;
0912c977 5554 } else {
7ae441ea 5555 writeback = false;
716d51ab
GN		 5556 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5557 }
ac0a48c3 5558 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5559 } else if (vcpu->mmio_needed) {
5560 if (!vcpu->mmio_is_write)
5561 writeback = false;
ac0a48c3 5562 r = EMULATE_USER_EXIT;
716d51ab 5563 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5564 } else if (r == EMULATION_RESTART)
5cd21917 5565 goto restart;
d2ddd1c4
GN		 5566 else
5567 r = EMULATE_DONE;
f850e2e6 5568
7ae441ea 5569 if (writeback) {
6addfc42 5570 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5571 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5572 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5573 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5574 if (r == EMULATE_DONE)
6addfc42 5575 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5576 if (!ctxt->have_exception ||
5577 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5578 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5579
5580 /*
5581 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5582 * do nothing, and it will be requested again as soon as
5583 * the shadow expires. But we still need to check here,
5584 * because POPF has no interrupt shadow.
5585 */
5586 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5587 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5588 } else
5589 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5590
5591 return r;
de7d789a 5592}
51d8b661 5593EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5594
cf8f70bf 5595int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5596{
cf8f70bf 5597 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5598 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5599 size, port, &val, 1);
cf8f70bf 5600 /* do not return to emulator after return from userspace */
7972995b 5601 vcpu->arch.pio.count = 0;
de7d789a
CO		 5602 return ret;
5603}
cf8f70bf 5604EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5605
8cfdc000
ZA		 5606static void tsc_bad(void *info)
5607{
0a3aee0d 5608 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5609}
5610
5611static void tsc_khz_changed(void *data)
c8076604 5612{
8cfdc000
ZA		 5613 struct cpufreq_freqs *freq = data;
5614 unsigned long khz = 0;
5615
5616 if (data)
5617 khz = freq->new;
5618 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5619 khz = cpufreq_quick_get(raw_smp_processor_id());
5620 if (!khz)
5621 khz = tsc_khz;
0a3aee0d 5622 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5623}
5624
c8076604
GH		 5625static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5626 void *data)
5627{
5628 struct cpufreq_freqs *freq = data;
5629 struct kvm *kvm;
5630 struct kvm_vcpu *vcpu;
5631 int i, send_ipi = 0;
5632
8cfdc000
ZA		 5633 /*
5634 * We allow guests to temporarily run on slowing clocks,
5635 * provided we notify them after, or to run on accelerating
5636 * clocks, provided we notify them before. Thus time never
5637 * goes backwards.
5638 *
5639 * However, we have a problem. We can't atomically update
5640 * the frequency of a given CPU from this function; it is
5641 * merely a notifier, which can be called from any CPU.
5642 * Changing the TSC frequency at arbitrary points in time
5643 * requires a recomputation of local variables related to
5644 * the TSC for each VCPU. We must flag these local variables
5645 * to be updated and be sure the update takes place with the
5646 * new frequency before any guests proceed.
5647 *
5648 * Unfortunately, the combination of hotplug CPU and frequency
5649 * change creates an intractable locking scenario; the order
5650 * of when these callouts happen is undefined with respect to
5651 * CPU hotplug, and they can race with each other. As such,
5652 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5653 * undefined; you can actually have a CPU frequency change take
5654 * place in between the computation of X and the setting of the
5655 * variable. To protect against this problem, all updates of
5656 * the per_cpu tsc_khz variable are done in an interrupt
5657 * protected IPI, and all callers wishing to update the value
5658 * must wait for a synchronous IPI to complete (which is trivial
5659 * if the caller is on the CPU already). This establishes the
5660 * necessary total order on variable updates.
5661 *
5662 * Note that because a guest time update may take place
5663 * anytime after the setting of the VCPU's request bit, the
5664 * correct TSC value must be set before the request. However,
5665 * to ensure the update actually makes it to any guest which
5666 * starts running in hardware virtualization between the set
5667 * and the acquisition of the spinlock, we must also ping the
5668 * CPU after setting the request bit.
5669 *
5670 */
5671
c8076604
GH		 5672 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5673 return 0;
5674 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5675 return 0;
8cfdc000
ZA		 5676
5677 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5678
2f303b74 5679 spin_lock(&kvm_lock);
c8076604 5680 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5681 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5682 if (vcpu->cpu != freq->cpu)
5683 continue;
c285545f 5684 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5685 if (vcpu->cpu != smp_processor_id())
8cfdc000 5686 send_ipi = 1;
c8076604
GH		 5687 }
5688 }
2f303b74 5689 spin_unlock(&kvm_lock);
c8076604
GH		 5690
5691 if (freq->old < freq->new && send_ipi) {
5692 /*
5693 * We upscale the frequency. Must make the guest
5694 * doesn't see old kvmclock values while running with
5695 * the new frequency, otherwise we risk the guest sees
5696 * time go backwards.
5697 *
5698 * In case we update the frequency for another cpu
5699 * (which might be in guest context) send an interrupt
5700 * to kick the cpu out of guest context. Next time
5701 * guest context is entered kvmclock will be updated,
5702 * so the guest will not see stale values.
5703 */
8cfdc000 5704 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5705 }
5706 return 0;
5707}
5708
5709static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5710 .notifier_call = kvmclock_cpufreq_notifier
5711};
5712
5713static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5714 unsigned long action, void *hcpu)
5715{
5716 unsigned int cpu = (unsigned long)hcpu;
5717
5718 switch (action) {
5719 case CPU_ONLINE:
5720 case CPU_DOWN_FAILED:
5721 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5722 break;
5723 case CPU_DOWN_PREPARE:
5724 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5725 break;
5726 }
5727 return NOTIFY_OK;
5728}
5729
5730static struct notifier_block kvmclock_cpu_notifier_block = {
5731 .notifier_call = kvmclock_cpu_notifier,
5732 .priority = -INT_MAX
c8076604
GH		 5733};
5734
b820cc0c
ZA		 5735static void kvm_timer_init(void)
5736{
5737 int cpu;
5738
c285545f 5739 max_tsc_khz = tsc_khz;
460dd42e
SB		 5740
5741 cpu_notifier_register_begin();
b820cc0c 5742 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5743#ifdef CONFIG_CPU_FREQ
5744 struct cpufreq_policy policy;
5745 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5746 cpu = get_cpu();
5747 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5748 if (policy.cpuinfo.max_freq)
5749 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5750 put_cpu();
c285545f 5751#endif
b820cc0c
ZA		 5752 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5753 CPUFREQ_TRANSITION_NOTIFIER);
5754 }
c285545f 5755 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5756 for_each_online_cpu(cpu)
5757 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5758
5759 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5760 cpu_notifier_register_done();
5761
b820cc0c
ZA		 5762}
5763
ff9d07a0
ZY		 5764static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5765
f5132b01 5766int kvm_is_in_guest(void)
ff9d07a0 5767{
086c9855 5768 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5769}
5770
5771static int kvm_is_user_mode(void)
5772{
5773 int user_mode = 3;
dcf46b94 5774
086c9855
AS		 5775 if (__this_cpu_read(current_vcpu))
5776 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5777
ff9d07a0
ZY		 5778 return user_mode != 0;
5779}
5780
5781static unsigned long kvm_get_guest_ip(void)
5782{
5783 unsigned long ip = 0;
dcf46b94 5784
086c9855
AS		 5785 if (__this_cpu_read(current_vcpu))
5786 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5787
ff9d07a0
ZY		 5788 return ip;
5789}
5790
5791static struct perf_guest_info_callbacks kvm_guest_cbs = {
5792 .is_in_guest = kvm_is_in_guest,
5793 .is_user_mode = kvm_is_user_mode,
5794 .get_guest_ip = kvm_get_guest_ip,
5795};
5796
5797void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5798{
086c9855 5799 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5800}
5801EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5802
5803void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5804{
086c9855 5805 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5806}
5807EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5808
ce88decf
XG		 5809static void kvm_set_mmio_spte_mask(void)
5810{
5811 u64 mask;
5812 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5813
5814 /*
5815 * Set the reserved bits and the present bit of an paging-structure
5816 * entry to generate page fault with PFER.RSV = 1.
5817 */
885032b9 5818 /* Mask the reserved physical address bits. */
d1431483 5819 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5820
5821 /* Bit 62 is always reserved for 32bit host. */
5822 mask |= 0x3ull << 62;
5823
5824 /* Set the present bit. */
ce88decf
XG		 5825 mask |= 1ull;
5826
5827#ifdef CONFIG_X86_64
5828 /*
5829 * If reserved bit is not supported, clear the present bit to disable
5830 * mmio page fault.
5831 */
5832 if (maxphyaddr == 52)
5833 mask &= ~1ull;
5834#endif
5835
5836 kvm_mmu_set_mmio_spte_mask(mask);
5837}
5838
16e8d74d
MT		 5839#ifdef CONFIG_X86_64
5840static void pvclock_gtod_update_fn(struct work_struct *work)
5841{
d828199e
MT		 5842 struct kvm *kvm;
5843
5844 struct kvm_vcpu *vcpu;
5845 int i;
5846
2f303b74 5847 spin_lock(&kvm_lock);
d828199e
MT		 5848 list_for_each_entry(kvm, &vm_list, vm_list)
5849 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5850 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5851 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5852 spin_unlock(&kvm_lock);
16e8d74d
MT		 5853}
5854
5855static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5856
5857/*
5858 * Notification about pvclock gtod data update.
5859 */
5860static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5861 void *priv)
5862{
5863 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5864 struct timekeeper *tk = priv;
5865
5866 update_pvclock_gtod(tk);
5867
5868 /* disable master clock if host does not trust, or does not
5869 * use, TSC clocksource
5870 */
5871 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5872 atomic_read(&kvm_guest_has_master_clock) != 0)
5873 queue_work(system_long_wq, &pvclock_gtod_work);
5874
5875 return 0;
5876}
5877
5878static struct notifier_block pvclock_gtod_notifier = {
5879 .notifier_call = pvclock_gtod_notify,
5880};
5881#endif
5882
f8c16bba 5883int kvm_arch_init(void *opaque)
043405e1 5884{
b820cc0c 5885 int r;
6b61edf7 5886 struct kvm_x86_ops *ops = opaque;
f8c16bba 5887
f8c16bba
ZX		 5888 if (kvm_x86_ops) {
5889 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5890 r = -EEXIST;
5891 goto out;
f8c16bba
ZX		 5892 }
5893
5894 if (!ops->cpu_has_kvm_support()) {
5895 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5896 r = -EOPNOTSUPP;
5897 goto out;
f8c16bba
ZX		 5898 }
5899 if (ops->disabled_by_bios()) {
5900 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5901 r = -EOPNOTSUPP;
5902 goto out;
f8c16bba
ZX		 5903 }
5904
013f6a5d
MT		 5905 r = -ENOMEM;
5906 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5907 if (!shared_msrs) {
5908 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5909 goto out;
5910 }
5911
97db56ce
AK		 5912 r = kvm_mmu_module_init();
5913 if (r)
013f6a5d 5914 goto out_free_percpu;
97db56ce 5915
ce88decf 5916 kvm_set_mmio_spte_mask();
97db56ce 5917
f8c16bba 5918 kvm_x86_ops = ops;
920c8377 5919
7b52345e 5920 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5921 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5922
b820cc0c 5923 kvm_timer_init();
c8076604 5924
ff9d07a0
ZY		 5925 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5926
2acf923e
DC		 5927 if (cpu_has_xsave)
5928 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5929
c5cc421b 5930 kvm_lapic_init();
16e8d74d
MT		 5931#ifdef CONFIG_X86_64
5932 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5933#endif
5934
f8c16bba 5935 return 0;
56c6d28a 5936
013f6a5d
MT		 5937out_free_percpu:
5938 free_percpu(shared_msrs);
56c6d28a 5939out:
56c6d28a 5940 return r;
043405e1 5941}
8776e519 5942
f8c16bba
ZX		 5943void kvm_arch_exit(void)
5944{
ff9d07a0
ZY		 5945 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5946
888d256e
JK		 5947 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5948 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5949 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5950 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5951#ifdef CONFIG_X86_64
5952 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5953#endif
f8c16bba 5954 kvm_x86_ops = NULL;
56c6d28a 5955 kvm_mmu_module_exit();
013f6a5d 5956 free_percpu(shared_msrs);
56c6d28a 5957}
f8c16bba 5958
5cb56059 5959int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5960{
5961 ++vcpu->stat.halt_exits;
5962 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5963 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5964 return 1;
5965 } else {
5966 vcpu->run->exit_reason = KVM_EXIT_HLT;
5967 return 0;
5968 }
5969}
5cb56059
JS		 5970EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5971
5972int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5973{
5974 kvm_x86_ops->skip_emulated_instruction(vcpu);
5975 return kvm_vcpu_halt(vcpu);
5976}
8776e519
HB		 5977EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5978
55cd8e5a
GN		 5979int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5980{
5981 u64 param, ingpa, outgpa, ret;
5982 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5983 bool fast, longmode;
55cd8e5a
GN		 5984
5985 /*
5986 * hypercall generates UD from non zero cpl and real mode
5987 * per HYPER-V spec
5988 */
3eeb3288 5989 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5990 kvm_queue_exception(vcpu, UD_VECTOR);
5991 return 0;
5992 }
5993
a449c7aa 5994 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5995
5996 if (!longmode) {
ccd46936
GN		 5997 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5998 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5999 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
6000 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
6001 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
6002 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 6003 }
6004#ifdef CONFIG_X86_64
6005 else {
6006 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
6007 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
6008 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
6009 }
6010#endif
6011
6012 code = param & 0xffff;
6013 fast = (param >> 16) & 0x1;
6014 rep_cnt = (param >> 32) & 0xfff;
6015 rep_idx = (param >> 48) & 0xfff;
6016
6017 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
6018
c25bc163
GN		 6019 switch (code) {
6020 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
6021 kvm_vcpu_on_spin(vcpu);
6022 break;
6023 default:
6024 res = HV_STATUS_INVALID_HYPERCALL_CODE;
6025 break;
6026 }
55cd8e5a
GN		 6027
6028 ret = res | (((u64)rep_done & 0xfff) << 32);
6029 if (longmode) {
6030 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6031 } else {
6032 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
6033 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
6034 }
6035
6036 return 1;
6037}
6038
6aef266c
SV		 6039/*
6040 * kvm_pv_kick_cpu_op: Kick a vcpu.
6041 *
6042 * @apicid - apicid of vcpu to be kicked.
6043 */
6044static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6045{
24d2166b 6046 struct kvm_lapic_irq lapic_irq;
6aef266c 6047
24d2166b
R		 6048 lapic_irq.shorthand = 0;
6049 lapic_irq.dest_mode = 0;
6050 lapic_irq.dest_id = apicid;
93bbf0b8 6051 lapic_irq.msi_redir_hint = false;
6aef266c 6052
24d2166b 6053 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6054 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6055}
6056
8776e519
HB		 6057int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6058{
6059 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6060 int op_64_bit, r = 1;
8776e519 6061
5cb56059
JS		 6062 kvm_x86_ops->skip_emulated_instruction(vcpu);
6063
55cd8e5a
GN		 6064 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6065 return kvm_hv_hypercall(vcpu);
6066
5fdbf976
MT		 6067 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6068 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6069 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6070 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6071 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6072
229456fc 6073 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6074
a449c7aa
NA		 6075 op_64_bit = is_64_bit_mode(vcpu);
6076 if (!op_64_bit) {
8776e519
HB		 6077 nr &= 0xFFFFFFFF;
6078 a0 &= 0xFFFFFFFF;
6079 a1 &= 0xFFFFFFFF;
6080 a2 &= 0xFFFFFFFF;
6081 a3 &= 0xFFFFFFFF;
6082 }
6083
07708c4a
JK		 6084 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6085 ret = -KVM_EPERM;
6086 goto out;
6087 }
6088
8776e519 6089 switch (nr) {
b93463aa
AK		 6090 case KVM_HC_VAPIC_POLL_IRQ:
6091 ret = 0;
6092 break;
6aef266c
SV		 6093 case KVM_HC_KICK_CPU:
6094 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6095 ret = 0;
6096 break;
8776e519
HB		 6097 default:
6098 ret = -KVM_ENOSYS;
6099 break;
6100 }
07708c4a 6101out:
a449c7aa
NA		 6102 if (!op_64_bit)
6103 ret = (u32)ret;
5fdbf976 6104 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6105 ++vcpu->stat.hypercalls;
2f333bcb 6106 return r;
8776e519
HB		 6107}
6108EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6109
b6785def 6110static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6111{
d6aa1000 6112 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6113 char instruction[3];
5fdbf976 6114 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6115
8776e519 6116 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6117
9d74191a 6118 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6119}
6120
b6c7a5dc
HB		 6121/*
6122 * Check if userspace requested an interrupt window, and that the
6123 * interrupt window is open.
6124 *
6125 * No need to exit to userspace if we already have an interrupt queued.
6126 */
851ba692 6127static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6128{
8061823a 6129 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6130 vcpu->run->request_interrupt_window &&
5df56646 6131 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6132}
6133
851ba692 6134static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6135{
851ba692
AK		 6136 struct kvm_run *kvm_run = vcpu->run;
6137
91586a3b 6138 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6139 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6140 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6141 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6142 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6143 else
b6c7a5dc 6144 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6145 kvm_arch_interrupt_allowed(vcpu) &&
6146 !kvm_cpu_has_interrupt(vcpu) &&
6147 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6148}
6149
95ba8273
GN		 6150static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6151{
6152 int max_irr, tpr;
6153
6154 if (!kvm_x86_ops->update_cr8_intercept)
6155 return;
6156
88c808fd
AK		 6157 if (!vcpu->arch.apic)
6158 return;
6159
8db3baa2
GN		 6160 if (!vcpu->arch.apic->vapic_addr)
6161 max_irr = kvm_lapic_find_highest_irr(vcpu);
6162 else
6163 max_irr = -1;
95ba8273
GN		 6164
6165 if (max_irr != -1)
6166 max_irr >>= 4;
6167
6168 tpr = kvm_lapic_get_cr8(vcpu);
6169
6170 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6171}
6172
b6b8a145 6173static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6174{
b6b8a145
JK		 6175 int r;
6176
95ba8273 6177 /* try to reinject previous events if any */
b59bb7bd 6178 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6179 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6180 vcpu->arch.exception.has_error_code,
6181 vcpu->arch.exception.error_code);
d6e8c854
NA		 6182
6183 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6184 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6185 X86_EFLAGS_RF);
6186
6bdf0662
NA		 6187 if (vcpu->arch.exception.nr == DB_VECTOR &&
6188 (vcpu->arch.dr7 & DR7_GD)) {
6189 vcpu->arch.dr7 &= ~DR7_GD;
6190 kvm_update_dr7(vcpu);
6191 }
6192
b59bb7bd
GN		 6193 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6194 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6195 vcpu->arch.exception.error_code,
6196 vcpu->arch.exception.reinject);
b6b8a145 6197 return 0;
b59bb7bd
GN		 6198 }
6199
95ba8273
GN		 6200 if (vcpu->arch.nmi_injected) {
6201 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6202 return 0;
95ba8273
GN		 6203 }
6204
6205 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6206 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6207 return 0;
6208 }
6209
6210 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6211 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6212 if (r != 0)
6213 return r;
95ba8273
GN		 6214 }
6215
6216 /* try to inject new event if pending */
6217 if (vcpu->arch.nmi_pending) {
6218 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6219 --vcpu->arch.nmi_pending;
95ba8273
GN		 6220 vcpu->arch.nmi_injected = true;
6221 kvm_x86_ops->set_nmi(vcpu);
6222 }
c7c9c56c 6223 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6224 /*
6225 * Because interrupts can be injected asynchronously, we are
6226 * calling check_nested_events again here to avoid a race condition.
6227 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6228 * proposal and current concerns. Perhaps we should be setting
6229 * KVM_REQ_EVENT only on certain events and not unconditionally?
6230 */
6231 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6232 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6233 if (r != 0)
6234 return r;
6235 }
95ba8273 6236 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6237 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6238 false);
6239 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6240 }
6241 }
b6b8a145 6242 return 0;
95ba8273
GN		 6243}
6244
7460fb4a
AK		 6245static void process_nmi(struct kvm_vcpu *vcpu)
6246{
6247 unsigned limit = 2;
6248
6249 /*
6250 * x86 is limited to one NMI running, and one NMI pending after it.
6251 * If an NMI is already in progress, limit further NMIs to just one.
6252 * Otherwise, allow two (and we'll inject the first one immediately).
6253 */
6254 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6255 limit = 1;
6256
6257 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6258 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6259 kvm_make_request(KVM_REQ_EVENT, vcpu);
6260}
6261
3d81bc7e 6262static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6263{
6264 u64 eoi_exit_bitmap[4];
cf9e65b7 6265 u32 tmr[8];
c7c9c56c 6266
3d81bc7e
YZ		 6267 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6268 return;
c7c9c56c
YZ		 6269
6270 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6271 memset(tmr, 0, 32);
c7c9c56c 6272
cf9e65b7 6273 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6274 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6275 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6276}
6277
a70656b6
RK		 6278static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6279{
6280 ++vcpu->stat.tlb_flush;
6281 kvm_x86_ops->tlb_flush(vcpu);
6282}
6283
4256f43f
TC		 6284void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6285{
c24ae0dc
TC		 6286 struct page *page = NULL;
6287
f439ed27
PB		 6288 if (!irqchip_in_kernel(vcpu->kvm))
6289 return;
6290
4256f43f
TC		 6291 if (!kvm_x86_ops->set_apic_access_page_addr)
6292 return;
6293
c24ae0dc 6294 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6295 if (is_error_page(page))
6296 return;
c24ae0dc
TC		 6297 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6298
6299 /*
6300 * Do not pin apic access page in memory, the MMU notifier
6301 * will call us again if it is migrated or swapped out.
6302 */
6303 put_page(page);
4256f43f
TC		 6304}
6305EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6306
fe71557a
TC		 6307void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6308 unsigned long address)
6309{
c24ae0dc
TC		 6310 /*
6311 * The physical address of apic access page is stored in the VMCS.
6312 * Update it when it becomes invalid.
6313 */
6314 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6315 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6316}
6317
9357d939 6318/*
362c698f 6319 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6320 * exiting to the userspace. Otherwise, the value will be returned to the
6321 * userspace.
6322 */
851ba692 6323static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6324{
6325 int r;
6a8b1d13 6326 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6327 vcpu->run->request_interrupt_window;
730dca42 6328 bool req_immediate_exit = false;
b6c7a5dc 6329
3e007509 6330 if (vcpu->requests) {
a8eeb04a 6331 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6332 kvm_mmu_unload(vcpu);
a8eeb04a 6333 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6334 __kvm_migrate_timers(vcpu);
d828199e
MT		 6335 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6336 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6337 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6338 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6339 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6340 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6341 if (unlikely(r))
6342 goto out;
6343 }
a8eeb04a 6344 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6345 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6346 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6347 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6348 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6349 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6350 r = 0;
6351 goto out;
6352 }
a8eeb04a 6353 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6354 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6355 r = 0;
6356 goto out;
6357 }
a8eeb04a 6358 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6359 vcpu->fpu_active = 0;
6360 kvm_x86_ops->fpu_deactivate(vcpu);
6361 }
af585b92
GN		 6362 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6363 /* Page is swapped out. Do synthetic halt */
6364 vcpu->arch.apf.halted = true;
6365 r = 1;
6366 goto out;
6367 }
c9aaa895
GC		 6368 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6369 record_steal_time(vcpu);
7460fb4a
AK		 6370 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6371 process_nmi(vcpu);
f5132b01
GN		 6372 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6373 kvm_handle_pmu_event(vcpu);
6374 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6375 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6376 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6377 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6378 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6379 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6380 }
b93463aa 6381
b463a6f7 6382 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6383 kvm_apic_accept_events(vcpu);
6384 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6385 r = 1;
6386 goto out;
6387 }
6388
b6b8a145
JK		 6389 if (inject_pending_event(vcpu, req_int_win) != 0)
6390 req_immediate_exit = true;
b463a6f7 6391 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6392 else if (vcpu->arch.nmi_pending)
c9a7953f 6393 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6394 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6395 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6396
6397 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6398 /*
6399 * Update architecture specific hints for APIC
6400 * virtual interrupt delivery.
6401 */
6402 if (kvm_x86_ops->hwapic_irr_update)
6403 kvm_x86_ops->hwapic_irr_update(vcpu,
6404 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6405 update_cr8_intercept(vcpu);
6406 kvm_lapic_sync_to_vapic(vcpu);
6407 }
6408 }
6409
d8368af8
AK		 6410 r = kvm_mmu_reload(vcpu);
6411 if (unlikely(r)) {
d905c069 6412 goto cancel_injection;
d8368af8
AK		 6413 }
6414
b6c7a5dc
HB		 6415 preempt_disable();
6416
6417 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6418 if (vcpu->fpu_active)
6419 kvm_load_guest_fpu(vcpu);
2acf923e 6420 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6421
6b7e2d09
XG		 6422 vcpu->mode = IN_GUEST_MODE;
6423
01b71917
MT		 6424 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6425
6b7e2d09
XG		 6426 /* We should set ->mode before check ->requests,
6427 * see the comment in make_all_cpus_request.
6428 */
01b71917 6429 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6430
d94e1dc9 6431 local_irq_disable();
32f88400 6432
6b7e2d09 6433 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6434 || need_resched() || signal_pending(current)) {
6b7e2d09 6435 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6436 smp_wmb();
6c142801
AK		 6437 local_irq_enable();
6438 preempt_enable();
01b71917 6439 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6440 r = 1;
d905c069 6441 goto cancel_injection;
6c142801
AK		 6442 }
6443
d6185f20
NHE		 6444 if (req_immediate_exit)
6445 smp_send_reschedule(vcpu->cpu);
6446
ccf73aaf 6447 __kvm_guest_enter();
b6c7a5dc 6448
42dbaa5a 6449 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6450 set_debugreg(0, 7);
6451 set_debugreg(vcpu->arch.eff_db[0], 0);
6452 set_debugreg(vcpu->arch.eff_db[1], 1);
6453 set_debugreg(vcpu->arch.eff_db[2], 2);
6454 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6455 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6456 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6457 }
b6c7a5dc 6458
229456fc 6459 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6460 wait_lapic_expire(vcpu);
851ba692 6461 kvm_x86_ops->run(vcpu);
b6c7a5dc 6462
c77fb5fe
PB		 6463 /*
6464 * Do this here before restoring debug registers on the host. And
6465 * since we do this before handling the vmexit, a DR access vmexit
6466 * can (a) read the correct value of the debug registers, (b) set
6467 * KVM_DEBUGREG_WONT_EXIT again.
6468 */
6469 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6470 int i;
6471
6472 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6473 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6474 for (i = 0; i < KVM_NR_DB_REGS; i++)
6475 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6476 }
6477
24f1e32c
FW		 6478 /*
6479 * If the guest has used debug registers, at least dr7
6480 * will be disabled while returning to the host.
6481 * If we don't have active breakpoints in the host, we don't
6482 * care about the messed up debug address registers. But if
6483 * we have some of them active, restore the old state.
6484 */
59d8eb53 6485 if (hw_breakpoint_active())
24f1e32c 6486 hw_breakpoint_restore();
42dbaa5a 6487
886b470c
MT		 6488 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6489 native_read_tsc());
1d5f066e 6490
6b7e2d09 6491 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6492 smp_wmb();
a547c6db
YZ		 6493
6494 /* Interrupt is enabled by handle_external_intr() */
6495 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6496
6497 ++vcpu->stat.exits;
6498
6499 /*
6500 * We must have an instruction between local_irq_enable() and
6501 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6502 * the interrupt shadow. The stat.exits increment will do nicely.
6503 * But we need to prevent reordering, hence this barrier():
6504 */
6505 barrier();
6506
6507 kvm_guest_exit();
6508
6509 preempt_enable();
6510
f656ce01 6511 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6512
b6c7a5dc
HB		 6513 /*
6514 * Profile KVM exit RIPs:
6515 */
6516 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6517 unsigned long rip = kvm_rip_read(vcpu);
6518 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6519 }
6520
cc578287
ZA		 6521 if (unlikely(vcpu->arch.tsc_always_catchup))
6522 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6523
5cfb1d5a
MT		 6524 if (vcpu->arch.apic_attention)
6525 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6526
851ba692 6527 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6528 return r;
6529
6530cancel_injection:
6531 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6532 if (unlikely(vcpu->arch.apic_attention))
6533 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6534out:
6535 return r;
6536}
b6c7a5dc 6537
362c698f
PB		 6538static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6539{
9c8fd1ba
PB		 6540 if (!kvm_arch_vcpu_runnable(vcpu)) {
6541 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6542 kvm_vcpu_block(vcpu);
6543 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6544 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6545 return 1;
6546 }
362c698f
PB		 6547
6548 kvm_apic_accept_events(vcpu);
6549 switch(vcpu->arch.mp_state) {
6550 case KVM_MP_STATE_HALTED:
6551 vcpu->arch.pv.pv_unhalted = false;
6552 vcpu->arch.mp_state =
6553 KVM_MP_STATE_RUNNABLE;
6554 case KVM_MP_STATE_RUNNABLE:
6555 vcpu->arch.apf.halted = false;
6556 break;
6557 case KVM_MP_STATE_INIT_RECEIVED:
6558 break;
6559 default:
6560 return -EINTR;
6561 break;
6562 }
6563 return 1;
6564}
09cec754 6565
362c698f 6566static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6567{
6568 int r;
f656ce01 6569 struct kvm *kvm = vcpu->kvm;
d7690175 6570
f656ce01 6571 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6572
362c698f 6573 for (;;) {
af585b92
GN		 6574 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6575 !vcpu->arch.apf.halted)
851ba692 6576 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6577 else
6578 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6579 if (r <= 0)
6580 break;
6581
6582 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6583 if (kvm_cpu_has_pending_timer(vcpu))
6584 kvm_inject_pending_timer_irqs(vcpu);
6585
851ba692 6586 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6587 r = -EINTR;
851ba692 6588 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6589 ++vcpu->stat.request_irq_exits;
362c698f 6590 break;
09cec754 6591 }
af585b92
GN		 6592
6593 kvm_check_async_pf_completion(vcpu);
6594
09cec754
GN		 6595 if (signal_pending(current)) {
6596 r = -EINTR;
851ba692 6597 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6598 ++vcpu->stat.signal_exits;
362c698f 6599 break;
09cec754
GN		 6600 }
6601 if (need_resched()) {
f656ce01 6602 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6603 cond_resched();
f656ce01 6604 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6605 }
b6c7a5dc
HB		 6606 }
6607
f656ce01 6608 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6609
6610 return r;
6611}
6612
716d51ab
GN		 6613static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6614{
6615 int r;
6616 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6617 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6618 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6619 if (r != EMULATE_DONE)
6620 return 0;
6621 return 1;
6622}
6623
6624static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6625{
6626 BUG_ON(!vcpu->arch.pio.count);
6627
6628 return complete_emulated_io(vcpu);
6629}
6630
f78146b0
AK		 6631/*
6632 * Implements the following, as a state machine:
6633 *
6634 * read:
6635 * for each fragment
87da7e66
XG		 6636 * for each mmio piece in the fragment
6637 * write gpa, len
6638 * exit
6639 * copy data
f78146b0
AK		 6640 * execute insn
6641 *
6642 * write:
6643 * for each fragment
87da7e66
XG		 6644 * for each mmio piece in the fragment
6645 * write gpa, len
6646 * copy data
6647 * exit
f78146b0 6648 */
716d51ab 6649static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6650{
6651 struct kvm_run *run = vcpu->run;
f78146b0 6652 struct kvm_mmio_fragment *frag;
87da7e66 6653 unsigned len;
5287f194 6654
716d51ab 6655 BUG_ON(!vcpu->mmio_needed);
5287f194 6656
716d51ab 6657 /* Complete previous fragment */
87da7e66
XG		 6658 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6659 len = min(8u, frag->len);
716d51ab 6660 if (!vcpu->mmio_is_write)
87da7e66
XG		 6661 memcpy(frag->data, run->mmio.data, len);
6662
6663 if (frag->len <= 8) {
6664 /* Switch to the next fragment. */
6665 frag++;
6666 vcpu->mmio_cur_fragment++;
6667 } else {
6668 /* Go forward to the next mmio piece. */
6669 frag->data += len;
6670 frag->gpa += len;
6671 frag->len -= len;
6672 }
6673
a08d3b3b 6674 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6675 vcpu->mmio_needed = 0;
0912c977
PB		 6676
6677 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6678 if (vcpu->mmio_is_write)
716d51ab
GN		 6679 return 1;
6680 vcpu->mmio_read_completed = 1;
6681 return complete_emulated_io(vcpu);
6682 }
87da7e66 6683
716d51ab
GN		 6684 run->exit_reason = KVM_EXIT_MMIO;
6685 run->mmio.phys_addr = frag->gpa;
6686 if (vcpu->mmio_is_write)
87da7e66
XG		 6687 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6688 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6689 run->mmio.is_write = vcpu->mmio_is_write;
6690 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6691 return 0;
5287f194
AK		 6692}
6693
716d51ab 6694
b6c7a5dc
HB		 6695int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6696{
6697 int r;
6698 sigset_t sigsaved;
6699
e5c30142
AK		 6700 if (!tsk_used_math(current) && init_fpu(current))
6701 return -ENOMEM;
6702
ac9f6dc0
AK		 6703 if (vcpu->sigset_active)
6704 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6705
a4535290 6706 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6707 kvm_vcpu_block(vcpu);
66450a21 6708 kvm_apic_accept_events(vcpu);
d7690175 6709 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6710 r = -EAGAIN;
6711 goto out;
b6c7a5dc
HB		 6712 }
6713
b6c7a5dc 6714 /* re-sync apic's tpr */
eea1cff9
AP		 6715 if (!irqchip_in_kernel(vcpu->kvm)) {
6716 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6717 r = -EINVAL;
6718 goto out;
6719 }
6720 }
b6c7a5dc 6721
716d51ab
GN		 6722 if (unlikely(vcpu->arch.complete_userspace_io)) {
6723 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6724 vcpu->arch.complete_userspace_io = NULL;
6725 r = cui(vcpu);
6726 if (r <= 0)
6727 goto out;
6728 } else
6729 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6730
362c698f 6731 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6732
6733out:
f1d86e46 6734 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6735 if (vcpu->sigset_active)
6736 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6737
b6c7a5dc
HB		 6738 return r;
6739}
6740
6741int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6742{
7ae441ea
GN		 6743 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6744 /*
6745 * We are here if userspace calls get_regs() in the middle of
6746 * instruction emulation. Registers state needs to be copied
4a969980 6747 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6748 * that usually, but some bad designed PV devices (vmware
6749 * backdoor interface) need this to work
6750 */
dd856efa 6751 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6752 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6753 }
5fdbf976
MT		 6754 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6755 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6756 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6757 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6758 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6759 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6760 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6761 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6762#ifdef CONFIG_X86_64
5fdbf976
MT		 6763 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6764 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6765 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6766 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6767 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6768 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6769 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6770 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6771#endif
6772
5fdbf976 6773 regs->rip = kvm_rip_read(vcpu);
91586a3b 6774 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6775
b6c7a5dc
HB		 6776 return 0;
6777}
6778
6779int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6780{
7ae441ea
GN		 6781 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6782 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6783
5fdbf976
MT		 6784 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6785 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6786 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6787 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6788 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6789 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6790 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6791 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6792#ifdef CONFIG_X86_64
5fdbf976
MT		 6793 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6794 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6795 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6796 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6797 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6798 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6799 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6800 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6801#endif
6802
5fdbf976 6803 kvm_rip_write(vcpu, regs->rip);
91586a3b 6804 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6805
b4f14abd
JK		 6806 vcpu->arch.exception.pending = false;
6807
3842d135
AK		 6808 kvm_make_request(KVM_REQ_EVENT, vcpu);
6809
b6c7a5dc
HB		 6810 return 0;
6811}
6812
b6c7a5dc
HB		 6813void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6814{
6815 struct kvm_segment cs;
6816
3e6e0aab 6817 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6818 *db = cs.db;
6819 *l = cs.l;
6820}
6821EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6822
6823int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6824 struct kvm_sregs *sregs)
6825{
89a27f4d 6826 struct desc_ptr dt;
b6c7a5dc 6827
3e6e0aab
GT		 6828 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6829 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6830 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6831 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6832 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6833 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6834
3e6e0aab
GT		 6835 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6836 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6837
6838 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6839 sregs->idt.limit = dt.size;
6840 sregs->idt.base = dt.address;
b6c7a5dc 6841 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6842 sregs->gdt.limit = dt.size;
6843 sregs->gdt.base = dt.address;
b6c7a5dc 6844
4d4ec087 6845 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6846 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6847 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6848 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6849 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6850 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6851 sregs->apic_base = kvm_get_apic_base(vcpu);
6852
923c61bb 6853 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6854
36752c9b 6855 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6856 set_bit(vcpu->arch.interrupt.nr,
6857 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6858
b6c7a5dc
HB		 6859 return 0;
6860}
6861
62d9f0db
MT		 6862int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6863 struct kvm_mp_state *mp_state)
6864{
66450a21 6865 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6866 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6867 vcpu->arch.pv.pv_unhalted)
6868 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6869 else
6870 mp_state->mp_state = vcpu->arch.mp_state;
6871
62d9f0db
MT		 6872 return 0;
6873}
6874
6875int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6876 struct kvm_mp_state *mp_state)
6877{
66450a21
JK		 6878 if (!kvm_vcpu_has_lapic(vcpu) &&
6879 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6880 return -EINVAL;
6881
6882 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6883 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6884 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6885 } else
6886 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6887 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6888 return 0;
6889}
6890
7f3d35fd
KW		 6891int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6892 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6893{
9d74191a 6894 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6895 int ret;
e01c2426 6896
8ec4722d 6897 init_emulate_ctxt(vcpu);
c697518a 6898
7f3d35fd 6899 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6900 has_error_code, error_code);
c697518a 6901
c697518a 6902 if (ret)
19d04437 6903 return EMULATE_FAIL;
37817f29 6904
9d74191a
TY		 6905 kvm_rip_write(vcpu, ctxt->eip);
6906 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6907 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6908 return EMULATE_DONE;
37817f29
IE		 6909}
6910EXPORT_SYMBOL_GPL(kvm_task_switch);
6911
b6c7a5dc
HB		 6912int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6913 struct kvm_sregs *sregs)
6914{
58cb628d 6915 struct msr_data apic_base_msr;
b6c7a5dc 6916 int mmu_reset_needed = 0;
63f42e02 6917 int pending_vec, max_bits, idx;
89a27f4d 6918 struct desc_ptr dt;
b6c7a5dc 6919
6d1068b3
PM		 6920 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6921 return -EINVAL;
6922
89a27f4d
GN		 6923 dt.size = sregs->idt.limit;
6924 dt.address = sregs->idt.base;
b6c7a5dc 6925 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6926 dt.size = sregs->gdt.limit;
6927 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6928 kvm_x86_ops->set_gdt(vcpu, &dt);
6929
ad312c7c 6930 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6931 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6932 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6933 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6934
2d3ad1f4 6935 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6936
f6801dff 6937 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6938 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6939 apic_base_msr.data = sregs->apic_base;
6940 apic_base_msr.host_initiated = true;
6941 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6942
4d4ec087 6943 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6944 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6945 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6946
fc78f519 6947 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6948 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6949 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6950 kvm_update_cpuid(vcpu);
63f42e02
XG		 6951
6952 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6953 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6954 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6955 mmu_reset_needed = 1;
6956 }
63f42e02 6957 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6958
6959 if (mmu_reset_needed)
6960 kvm_mmu_reset_context(vcpu);
6961
a50abc3b 6962 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6963 pending_vec = find_first_bit(
6964 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6965 if (pending_vec < max_bits) {
66fd3f7f 6966 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6967 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6968 }
6969
3e6e0aab
GT		 6970 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6971 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6972 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6973 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6974 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6975 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6976
3e6e0aab
GT		 6977 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6978 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6979
5f0269f5
ME		 6980 update_cr8_intercept(vcpu);
6981
9c3e4aab 6982 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6983 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6984 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6985 !is_protmode(vcpu))
9c3e4aab
MT		 6986 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6987
3842d135
AK		 6988 kvm_make_request(KVM_REQ_EVENT, vcpu);
6989
b6c7a5dc
HB		 6990 return 0;
6991}
6992
d0bfb940
JK		 6993int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6994 struct kvm_guest_debug *dbg)
b6c7a5dc 6995{
355be0b9 6996 unsigned long rflags;
ae675ef0 6997 int i, r;
b6c7a5dc 6998
4f926bf2
JK		 6999 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7000 r = -EBUSY;
7001 if (vcpu->arch.exception.pending)
2122ff5e 7002 goto out;
4f926bf2
JK		 7003 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7004 kvm_queue_exception(vcpu, DB_VECTOR);
7005 else
7006 kvm_queue_exception(vcpu, BP_VECTOR);
7007 }
7008
91586a3b
JK		 7009 /*
7010 * Read rflags as long as potentially injected trace flags are still
7011 * filtered out.
7012 */
7013 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7014
7015 vcpu->guest_debug = dbg->control;
7016 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7017 vcpu->guest_debug = 0;
7018
7019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7020 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7021 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7022 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7023 } else {
7024 for (i = 0; i < KVM_NR_DB_REGS; i++)
7025 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7026 }
c8639010 7027 kvm_update_dr7(vcpu);
ae675ef0 7028
f92653ee
JK		 7029 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7030 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7031 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7032
91586a3b
JK		 7033 /*
7034 * Trigger an rflags update that will inject or remove the trace
7035 * flags.
7036 */
7037 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7038
c8639010 7039 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7040
4f926bf2 7041 r = 0;
d0bfb940 7042
2122ff5e 7043out:
b6c7a5dc
HB		 7044
7045 return r;
7046}
7047
8b006791
ZX		 7048/*
7049 * Translate a guest virtual address to a guest physical address.
7050 */
7051int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7052 struct kvm_translation *tr)
7053{
7054 unsigned long vaddr = tr->linear_address;
7055 gpa_t gpa;
f656ce01 7056 int idx;
8b006791 7057
f656ce01 7058 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7059 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7060 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7061 tr->physical_address = gpa;
7062 tr->valid = gpa != UNMAPPED_GVA;
7063 tr->writeable = 1;
7064 tr->usermode = 0;
8b006791
ZX		 7065
7066 return 0;
7067}
7068
d0752060
HB		 7069int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7070{
98918833
SY		 7071 struct i387_fxsave_struct *fxsave =
7072 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7073
d0752060
HB		 7074 memcpy(fpu->fpr, fxsave->st_space, 128);
7075 fpu->fcw = fxsave->cwd;
7076 fpu->fsw = fxsave->swd;
7077 fpu->ftwx = fxsave->twd;
7078 fpu->last_opcode = fxsave->fop;
7079 fpu->last_ip = fxsave->rip;
7080 fpu->last_dp = fxsave->rdp;
7081 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7082
d0752060
HB		 7083 return 0;
7084}
7085
7086int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7087{
98918833
SY		 7088 struct i387_fxsave_struct *fxsave =
7089 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7090
d0752060
HB		 7091 memcpy(fxsave->st_space, fpu->fpr, 128);
7092 fxsave->cwd = fpu->fcw;
7093 fxsave->swd = fpu->fsw;
7094 fxsave->twd = fpu->ftwx;
7095 fxsave->fop = fpu->last_opcode;
7096 fxsave->rip = fpu->last_ip;
7097 fxsave->rdp = fpu->last_dp;
7098 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7099
d0752060
HB		 7100 return 0;
7101}
7102
d28bc9dd 7103int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7104{
10ab25cd
JK		 7105 int err;
7106
7107 err = fpu_alloc(&vcpu->arch.guest_fpu);
7108 if (err)
7109 return err;
7110
d28bc9dd
NA		 7111 if (!init_event)
7112 fpu_finit(&vcpu->arch.guest_fpu);
7113
df1daba7
PB		 7114 if (cpu_has_xsaves)
7115 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7116 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7117
2acf923e
DC		 7118 /*
7119 * Ensure guest xcr0 is valid for loading
7120 */
7121 vcpu->arch.xcr0 = XSTATE_FP;
7122
ad312c7c 7123 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7124
7125 return 0;
d0752060
HB		 7126}
7127EXPORT_SYMBOL_GPL(fx_init);
7128
98918833
SY		 7129static void fx_free(struct kvm_vcpu *vcpu)
7130{
7131 fpu_free(&vcpu->arch.guest_fpu);
7132}
7133
d0752060
HB		 7134void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7135{
2608d7a1 7136 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7137 return;
7138
2acf923e
DC		 7139 /*
7140 * Restore all possible states in the guest,
7141 * and assume host would use all available bits.
7142 * Guest xcr0 would be loaded later.
7143 */
7144 kvm_put_guest_xcr0(vcpu);
d0752060 7145 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7146 __kernel_fpu_begin();
98918833 7147 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7148 trace_kvm_fpu(1);
d0752060 7149}
d0752060
HB		 7150
7151void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7152{
2acf923e
DC		 7153 kvm_put_guest_xcr0(vcpu);
7154
653f52c3
RR		 7155 if (!vcpu->guest_fpu_loaded) {
7156 vcpu->fpu_counter = 0;
d0752060 7157 return;
653f52c3 7158 }
d0752060
HB		 7159
7160 vcpu->guest_fpu_loaded = 0;
98918833 7161 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7162 __kernel_fpu_end();
f096ed85 7163 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7164 /*
7165 * If using eager FPU mode, or if the guest is a frequent user
7166 * of the FPU, just leave the FPU active for next time.
7167 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7168 * the FPU in bursts will revert to loading it on demand.
7169 */
a9b4fb7e 7170 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7171 if (++vcpu->fpu_counter < 5)
7172 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7173 }
0c04851c 7174 trace_kvm_fpu(0);
d0752060 7175}
e9b11c17
ZX		 7176
7177void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7178{
12f9a48f 7179 kvmclock_reset(vcpu);
7f1ea208 7180
f5f48ee1 7181 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7182 fx_free(vcpu);
e9b11c17
ZX		 7183 kvm_x86_ops->vcpu_free(vcpu);
7184}
7185
7186struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7187 unsigned int id)
7188{
c447e76b
LL		 7189 struct kvm_vcpu *vcpu;
7190
6755bae8
ZA		 7191 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7192 printk_once(KERN_WARNING
7193 "kvm: SMP vm created on host with unstable TSC; "
7194 "guest TSC will not be reliable\n");
c447e76b
LL		 7195
7196 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7197
7198 /*
7199 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7200 * deactivated soon if it doesn't.
7201 */
7202 kvm_x86_ops->fpu_activate(vcpu);
7203 return vcpu;
26e5215f 7204}
e9b11c17 7205
26e5215f
AK		 7206int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7207{
7208 int r;
e9b11c17 7209
0bed3b56 7210 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7211 r = vcpu_load(vcpu);
7212 if (r)
7213 return r;
d28bc9dd 7214 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7215 kvm_mmu_setup(vcpu);
e9b11c17 7216 vcpu_put(vcpu);
e9b11c17 7217
26e5215f 7218 return r;
e9b11c17
ZX		 7219}
7220
31928aa5 7221void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7222{
8fe8ab46 7223 struct msr_data msr;
332967a3 7224 struct kvm *kvm = vcpu->kvm;
42897d86 7225
31928aa5
DD		 7226 if (vcpu_load(vcpu))
7227 return;
8fe8ab46
WA		 7228 msr.data = 0x0;
7229 msr.index = MSR_IA32_TSC;
7230 msr.host_initiated = true;
7231 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7232 vcpu_put(vcpu);
7233
630994b3
MT		 7234 if (!kvmclock_periodic_sync)
7235 return;
7236
332967a3
AJ		 7237 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7238 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7239}
7240
d40ccc62 7241void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7242{
9fc77441 7243 int r;
344d9588
GN		 7244 vcpu->arch.apf.msr_val = 0;
7245
9fc77441
MT		 7246 r = vcpu_load(vcpu);
7247 BUG_ON(r);
e9b11c17
ZX		 7248 kvm_mmu_unload(vcpu);
7249 vcpu_put(vcpu);
7250
98918833 7251 fx_free(vcpu);
e9b11c17
ZX		 7252 kvm_x86_ops->vcpu_free(vcpu);
7253}
7254
d28bc9dd 7255void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7256{
e69fab5d
PB		 7257 vcpu->arch.hflags = 0;
7258
7460fb4a
AK		 7259 atomic_set(&vcpu->arch.nmi_queued, 0);
7260 vcpu->arch.nmi_pending = 0;
448fa4a9 7261 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7262 kvm_clear_interrupt_queue(vcpu);
7263 kvm_clear_exception_queue(vcpu);
448fa4a9 7264
42dbaa5a 7265 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7266 kvm_update_dr0123(vcpu);
6f43ed01 7267 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7268 kvm_update_dr6(vcpu);
42dbaa5a 7269 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7270 kvm_update_dr7(vcpu);
42dbaa5a 7271
1119022c
NA		 7272 vcpu->arch.cr2 = 0;
7273
3842d135 7274 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7275 vcpu->arch.apf.msr_val = 0;
c9aaa895 7276 vcpu->arch.st.msr_val = 0;
3842d135 7277
12f9a48f
GC		 7278 kvmclock_reset(vcpu);
7279
af585b92
GN		 7280 kvm_clear_async_pf_completion_queue(vcpu);
7281 kvm_async_pf_hash_reset(vcpu);
7282 vcpu->arch.apf.halted = false;
3842d135 7283
d28bc9dd
NA		 7284 if (!init_event)
7285 kvm_pmu_reset(vcpu);
f5132b01 7286
66f7b72e
JS		 7287 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7288 vcpu->arch.regs_avail = ~0;
7289 vcpu->arch.regs_dirty = ~0;
7290
d28bc9dd 7291 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7292}
7293
2b4a273b 7294void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7295{
7296 struct kvm_segment cs;
7297
7298 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7299 cs.selector = vector << 8;
7300 cs.base = vector << 12;
7301 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7302 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7303}
7304
13a34e06 7305int kvm_arch_hardware_enable(void)
e9b11c17 7306{
ca84d1a2
ZA		 7307 struct kvm *kvm;
7308 struct kvm_vcpu *vcpu;
7309 int i;
0dd6a6ed
ZA		 7310 int ret;
7311 u64 local_tsc;
7312 u64 max_tsc = 0;
7313 bool stable, backwards_tsc = false;
18863bdd
AK		 7314
7315 kvm_shared_msr_cpu_online();
13a34e06 7316 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7317 if (ret != 0)
7318 return ret;
7319
7320 local_tsc = native_read_tsc();
7321 stable = !check_tsc_unstable();
7322 list_for_each_entry(kvm, &vm_list, vm_list) {
7323 kvm_for_each_vcpu(i, vcpu, kvm) {
7324 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7325 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7326 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7327 backwards_tsc = true;
7328 if (vcpu->arch.last_host_tsc > max_tsc)
7329 max_tsc = vcpu->arch.last_host_tsc;
7330 }
7331 }
7332 }
7333
7334 /*
7335 * Sometimes, even reliable TSCs go backwards. This happens on
7336 * platforms that reset TSC during suspend or hibernate actions, but
7337 * maintain synchronization. We must compensate. Fortunately, we can
7338 * detect that condition here, which happens early in CPU bringup,
7339 * before any KVM threads can be running. Unfortunately, we can't
7340 * bring the TSCs fully up to date with real time, as we aren't yet far
7341 * enough into CPU bringup that we know how much real time has actually
7342 * elapsed; our helper function, get_kernel_ns() will be using boot
7343 * variables that haven't been updated yet.
7344 *
7345 * So we simply find the maximum observed TSC above, then record the
7346 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7347 * the adjustment will be applied. Note that we accumulate
7348 * adjustments, in case multiple suspend cycles happen before some VCPU
7349 * gets a chance to run again. In the event that no KVM threads get a
7350 * chance to run, we will miss the entire elapsed period, as we'll have
7351 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7352 * loose cycle time. This isn't too big a deal, since the loss will be
7353 * uniform across all VCPUs (not to mention the scenario is extremely
7354 * unlikely). It is possible that a second hibernate recovery happens
7355 * much faster than a first, causing the observed TSC here to be
7356 * smaller; this would require additional padding adjustment, which is
7357 * why we set last_host_tsc to the local tsc observed here.
7358 *
7359 * N.B. - this code below runs only on platforms with reliable TSC,
7360 * as that is the only way backwards_tsc is set above. Also note
7361 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7362 * have the same delta_cyc adjustment applied if backwards_tsc
7363 * is detected. Note further, this adjustment is only done once,
7364 * as we reset last_host_tsc on all VCPUs to stop this from being
7365 * called multiple times (one for each physical CPU bringup).
7366 *
4a969980 7367 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7368 * will be compensated by the logic in vcpu_load, which sets the TSC to
7369 * catchup mode. This will catchup all VCPUs to real time, but cannot
7370 * guarantee that they stay in perfect synchronization.
7371 */
7372 if (backwards_tsc) {
7373 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7374 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7375 list_for_each_entry(kvm, &vm_list, vm_list) {
7376 kvm_for_each_vcpu(i, vcpu, kvm) {
7377 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7378 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7379 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7380 }
7381
7382 /*
7383 * We have to disable TSC offset matching.. if you were
7384 * booting a VM while issuing an S4 host suspend....
7385 * you may have some problem. Solving this issue is
7386 * left as an exercise to the reader.
7387 */
7388 kvm->arch.last_tsc_nsec = 0;
7389 kvm->arch.last_tsc_write = 0;
7390 }
7391
7392 }
7393 return 0;
e9b11c17
ZX		 7394}
7395
13a34e06 7396void kvm_arch_hardware_disable(void)
e9b11c17 7397{
13a34e06
RK		 7398 kvm_x86_ops->hardware_disable();
7399 drop_user_return_notifiers();
e9b11c17
ZX		 7400}
7401
7402int kvm_arch_hardware_setup(void)
7403{
9e9c3fe4
NA		 7404 int r;
7405
7406 r = kvm_x86_ops->hardware_setup();
7407 if (r != 0)
7408 return r;
7409
7410 kvm_init_msr_list();
7411 return 0;
e9b11c17
ZX		 7412}
7413
7414void kvm_arch_hardware_unsetup(void)
7415{
7416 kvm_x86_ops->hardware_unsetup();
7417}
7418
7419void kvm_arch_check_processor_compat(void *rtn)
7420{
7421 kvm_x86_ops->check_processor_compatibility(rtn);
7422}
7423
3e515705
AK		 7424bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7425{
7426 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7427}
7428
54e9818f
GN		 7429struct static_key kvm_no_apic_vcpu __read_mostly;
7430
e9b11c17
ZX		 7431int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7432{
7433 struct page *page;
7434 struct kvm *kvm;
7435 int r;
7436
7437 BUG_ON(vcpu->kvm == NULL);
7438 kvm = vcpu->kvm;
7439
6aef266c 7440 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7441 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7442 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7443 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7444 else
a4535290 7445 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7446
7447 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7448 if (!page) {
7449 r = -ENOMEM;
7450 goto fail;
7451 }
ad312c7c 7452 vcpu->arch.pio_data = page_address(page);
e9b11c17 7453
cc578287 7454 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7455
e9b11c17
ZX		 7456 r = kvm_mmu_create(vcpu);
7457 if (r < 0)
7458 goto fail_free_pio_data;
7459
7460 if (irqchip_in_kernel(kvm)) {
7461 r = kvm_create_lapic(vcpu);
7462 if (r < 0)
7463 goto fail_mmu_destroy;
54e9818f
GN		 7464 } else
7465 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7466
890ca9ae
HY		 7467 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7468 GFP_KERNEL);
7469 if (!vcpu->arch.mce_banks) {
7470 r = -ENOMEM;
443c39bc 7471 goto fail_free_lapic;
890ca9ae
HY		 7472 }
7473 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7474
f1797359
WY		 7475 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7476 r = -ENOMEM;
f5f48ee1 7477 goto fail_free_mce_banks;
f1797359 7478 }
f5f48ee1 7479
d28bc9dd 7480 r = fx_init(vcpu, false);
66f7b72e
JS		 7481 if (r)
7482 goto fail_free_wbinvd_dirty_mask;
7483
ba904635 7484 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7485 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7486
7487 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7488 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7489
5a4f55cd
EK		 7490 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7491
74545705
RK		 7492 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7493
af585b92 7494 kvm_async_pf_hash_reset(vcpu);
f5132b01 7495 kvm_pmu_init(vcpu);
af585b92 7496
e9b11c17 7497 return 0;
66f7b72e
JS		 7498fail_free_wbinvd_dirty_mask:
7499 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7500fail_free_mce_banks:
7501 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7502fail_free_lapic:
7503 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7504fail_mmu_destroy:
7505 kvm_mmu_destroy(vcpu);
7506fail_free_pio_data:
ad312c7c 7507 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7508fail:
7509 return r;
7510}
7511
7512void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7513{
f656ce01
MT		 7514 int idx;
7515
f5132b01 7516 kvm_pmu_destroy(vcpu);
36cb93fd 7517 kfree(vcpu->arch.mce_banks);
e9b11c17 7518 kvm_free_lapic(vcpu);
f656ce01 7519 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7520 kvm_mmu_destroy(vcpu);
f656ce01 7521 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7522 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7523 if (!irqchip_in_kernel(vcpu->kvm))
7524 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7525}
d19a9cd2 7526
e790d9ef
RK		 7527void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7528{
ae97a3b8 7529 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7530}
7531
e08b9637 7532int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7533{
e08b9637
CO		 7534 if (type)
7535 return -EINVAL;
7536
6ef768fa 7537 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7538 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7539 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7540 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7541 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7542
5550af4d
SY		 7543 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7544 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7545 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7546 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7547 &kvm->arch.irq_sources_bitmap);
5550af4d 7548
038f8c11 7549 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7550 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7551 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7552
7553 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7554
7e44e449 7555 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7556 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7557
d89f5eff 7558 return 0;
d19a9cd2
ZX		 7559}
7560
7561static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7562{
9fc77441
MT		 7563 int r;
7564 r = vcpu_load(vcpu);
7565 BUG_ON(r);
d19a9cd2
ZX		 7566 kvm_mmu_unload(vcpu);
7567 vcpu_put(vcpu);
7568}
7569
7570static void kvm_free_vcpus(struct kvm *kvm)
7571{
7572 unsigned int i;
988a2cae 7573 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7574
7575 /*
7576 * Unpin any mmu pages first.
7577 */
af585b92
GN		 7578 kvm_for_each_vcpu(i, vcpu, kvm) {
7579 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7580 kvm_unload_vcpu_mmu(vcpu);
af585b92 7581 }
988a2cae
GN		 7582 kvm_for_each_vcpu(i, vcpu, kvm)
7583 kvm_arch_vcpu_free(vcpu);
7584
7585 mutex_lock(&kvm->lock);
7586 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7587 kvm->vcpus[i] = NULL;
d19a9cd2 7588
988a2cae
GN		 7589 atomic_set(&kvm->online_vcpus, 0);
7590 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7591}
7592
ad8ba2cd
SY		 7593void kvm_arch_sync_events(struct kvm *kvm)
7594{
332967a3 7595 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7596 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7597 kvm_free_all_assigned_devices(kvm);
aea924f6 7598 kvm_free_pit(kvm);
ad8ba2cd
SY		 7599}
7600
d19a9cd2
ZX		 7601void kvm_arch_destroy_vm(struct kvm *kvm)
7602{
27469d29
AH		 7603 if (current->mm == kvm->mm) {
7604 /*
7605 * Free memory regions allocated on behalf of userspace,
7606 * unless the the memory map has changed due to process exit
7607 * or fd copying.
7608 */
7609 struct kvm_userspace_memory_region mem;
7610 memset(&mem, 0, sizeof(mem));
7611 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7612 kvm_set_memory_region(kvm, &mem);
7613
7614 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7615 kvm_set_memory_region(kvm, &mem);
7616
7617 mem.slot = TSS_PRIVATE_MEMSLOT;
7618 kvm_set_memory_region(kvm, &mem);
7619 }
6eb55818 7620 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7621 kfree(kvm->arch.vpic);
7622 kfree(kvm->arch.vioapic);
d19a9cd2 7623 kvm_free_vcpus(kvm);
1e08ec4a 7624 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7625}
0de10343 7626
5587027c 7627void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7628 struct kvm_memory_slot *dont)
7629{
7630 int i;
7631
d89cc617
TY		 7632 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7633 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7634 kvfree(free->arch.rmap[i]);
d89cc617 7635 free->arch.rmap[i] = NULL;
77d11309 7636 }
d89cc617
TY		 7637 if (i == 0)
7638 continue;
7639
7640 if (!dont || free->arch.lpage_info[i - 1] !=
7641 dont->arch.lpage_info[i - 1]) {
548ef284 7642 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7643 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7644 }
7645 }
7646}
7647
5587027c
AK		 7648int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7649 unsigned long npages)
db3fe4eb
TY		 7650{
7651 int i;
7652
d89cc617 7653 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7654 unsigned long ugfn;
7655 int lpages;
d89cc617 7656 int level = i + 1;
db3fe4eb
TY		 7657
7658 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7659 slot->base_gfn, level) + 1;
7660
d89cc617
TY		 7661 slot->arch.rmap[i] =
7662 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7663 if (!slot->arch.rmap[i])
77d11309 7664 goto out_free;
d89cc617
TY		 7665 if (i == 0)
7666 continue;
77d11309 7667
d89cc617
TY		 7668 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7669 sizeof(*slot->arch.lpage_info[i - 1]));
7670 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7671 goto out_free;
7672
7673 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7674 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7675 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7676 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7677 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7678 /*
7679 * If the gfn and userspace address are not aligned wrt each
7680 * other, or if explicitly asked to, disable large page
7681 * support for this slot
7682 */
7683 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7684 !kvm_largepages_enabled()) {
7685 unsigned long j;
7686
7687 for (j = 0; j < lpages; ++j)
d89cc617 7688 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7689 }
7690 }
7691
7692 return 0;
7693
7694out_free:
d89cc617 7695 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7696 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7697 slot->arch.rmap[i] = NULL;
7698 if (i == 0)
7699 continue;
7700
548ef284 7701 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7702 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7703 }
7704 return -ENOMEM;
7705}
7706
15f46015 7707void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7708{
e6dff7d1
TY		 7709 /*
7710 * memslots->generation has been incremented.
7711 * mmio generation may have reached its maximum value.
7712 */
7713 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7714}
7715
f7784b8e
MT		 7716int kvm_arch_prepare_memory_region(struct kvm *kvm,
7717 struct kvm_memory_slot *memslot,
09170a49 7718 const struct kvm_userspace_memory_region *mem,
7b6195a9 7719 enum kvm_mr_change change)
0de10343 7720{
7a905b14
TY		 7721 /*
7722 * Only private memory slots need to be mapped here since
7723 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7724 */
7b6195a9 7725 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7726 unsigned long userspace_addr;
604b38ac 7727
7a905b14
TY		 7728 /*
7729 * MAP_SHARED to prevent internal slot pages from being moved
7730 * by fork()/COW.
7731 */
7b6195a9 7732 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7733 PROT_READ | PROT_WRITE,
7734 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7735
7a905b14
TY		 7736 if (IS_ERR((void *)userspace_addr))
7737 return PTR_ERR((void *)userspace_addr);
604b38ac 7738
7a905b14 7739 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7740 }
7741
f7784b8e
MT		 7742 return 0;
7743}
7744
88178fd4
KH		 7745static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7746 struct kvm_memory_slot *new)
7747{
7748 /* Still write protect RO slot */
7749 if (new->flags & KVM_MEM_READONLY) {
7750 kvm_mmu_slot_remove_write_access(kvm, new);
7751 return;
7752 }
7753
7754 /*
7755 * Call kvm_x86_ops dirty logging hooks when they are valid.
7756 *
7757 * kvm_x86_ops->slot_disable_log_dirty is called when:
7758 *
7759 * - KVM_MR_CREATE with dirty logging is disabled
7760 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7761 *
7762 * The reason is, in case of PML, we need to set D-bit for any slots
7763 * with dirty logging disabled in order to eliminate unnecessary GPA
7764 * logging in PML buffer (and potential PML buffer full VMEXT). This
7765 * guarantees leaving PML enabled during guest's lifetime won't have
7766 * any additonal overhead from PML when guest is running with dirty
7767 * logging disabled for memory slots.
7768 *
7769 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7770 * to dirty logging mode.
7771 *
7772 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7773 *
7774 * In case of write protect:
7775 *
7776 * Write protect all pages for dirty logging.
7777 *
7778 * All the sptes including the large sptes which point to this
7779 * slot are set to readonly. We can not create any new large
7780 * spte on this slot until the end of the logging.
7781 *
7782 * See the comments in fast_page_fault().
7783 */
7784 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7785 if (kvm_x86_ops->slot_enable_log_dirty)
7786 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7787 else
7788 kvm_mmu_slot_remove_write_access(kvm, new);
7789 } else {
7790 if (kvm_x86_ops->slot_disable_log_dirty)
7791 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7792 }
7793}
7794
f7784b8e 7795void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7796 const struct kvm_userspace_memory_region *mem,
8482644a 7797 const struct kvm_memory_slot *old,
f36f3f28 7798 const struct kvm_memory_slot *new,
8482644a 7799 enum kvm_mr_change change)
f7784b8e 7800{
8482644a 7801 int nr_mmu_pages = 0;
f7784b8e 7802
f36f3f28 7803 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7804 int ret;
7805
8482644a
TY		 7806 ret = vm_munmap(old->userspace_addr,
7807 old->npages * PAGE_SIZE);
f7784b8e
MT		 7808 if (ret < 0)
7809 printk(KERN_WARNING
7810 "kvm_vm_ioctl_set_memory_region: "
7811 "failed to munmap memory\n");
7812 }
7813
48c0e4e9
XG		 7814 if (!kvm->arch.n_requested_mmu_pages)
7815 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7816
48c0e4e9 7817 if (nr_mmu_pages)
0de10343 7818 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7819
3ea3b7fa
WL		 7820 /*
7821 * Dirty logging tracks sptes in 4k granularity, meaning that large
7822 * sptes have to be split. If live migration is successful, the guest
7823 * in the source machine will be destroyed and large sptes will be
7824 * created in the destination. However, if the guest continues to run
7825 * in the source machine (for example if live migration fails), small
7826 * sptes will remain around and cause bad performance.
7827 *
7828 * Scan sptes if dirty logging has been stopped, dropping those
7829 * which can be collapsed into a single large-page spte. Later
7830 * page faults will create the large-page sptes.
7831 */
7832 if ((change != KVM_MR_DELETE) &&
7833 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7834 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7835 kvm_mmu_zap_collapsible_sptes(kvm, new);
7836
c972f3b1 7837 /*
88178fd4 7838 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7839 *
88178fd4
KH		 7840 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7841 * been zapped so no dirty logging staff is needed for old slot. For
7842 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7843 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7844 *
7845 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7846 */
88178fd4 7847 if (change != KVM_MR_DELETE)
f36f3f28 7848 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7849}
1d737c8a 7850
2df72e9b 7851void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7852{
6ca18b69 7853 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7854}
7855
2df72e9b
MT		 7856void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7857 struct kvm_memory_slot *slot)
7858{
6ca18b69 7859 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7860}
7861
1d737c8a
ZX		 7862int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7863{
b6b8a145
JK		 7864 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7865 kvm_x86_ops->check_nested_events(vcpu, false);
7866
af585b92
GN		 7867 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7868 !vcpu->arch.apf.halted)
7869 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7870 || kvm_apic_has_events(vcpu)
6aef266c 7871 || vcpu->arch.pv.pv_unhalted
7460fb4a 7872 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7873 (kvm_arch_interrupt_allowed(vcpu) &&
7874 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7875}
5736199a 7876
b6d33834 7877int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7878{
b6d33834 7879 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7880}
78646121
GN		 7881
7882int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7883{
7884 return kvm_x86_ops->interrupt_allowed(vcpu);
7885}
229456fc 7886
82b32774 7887unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7888{
82b32774
NA		 7889 if (is_64_bit_mode(vcpu))
7890 return kvm_rip_read(vcpu);
7891 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7892 kvm_rip_read(vcpu));
7893}
7894EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7895
82b32774
NA		 7896bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7897{
7898 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7899}
7900EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7901
94fe45da
JK		 7902unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7903{
7904 unsigned long rflags;
7905
7906 rflags = kvm_x86_ops->get_rflags(vcpu);
7907 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7908 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7909 return rflags;
7910}
7911EXPORT_SYMBOL_GPL(kvm_get_rflags);
7912
6addfc42 7913static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7914{
7915 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7916 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7917 rflags |= X86_EFLAGS_TF;
94fe45da 7918 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7919}
7920
7921void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7922{
7923 __kvm_set_rflags(vcpu, rflags);
3842d135 7924 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7925}
7926EXPORT_SYMBOL_GPL(kvm_set_rflags);
7927
56028d08
GN		 7928void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7929{
7930 int r;
7931
fb67e14f 7932 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7933 work->wakeup_all)
56028d08
GN		 7934 return;
7935
7936 r = kvm_mmu_reload(vcpu);
7937 if (unlikely(r))
7938 return;
7939
fb67e14f
XG		 7940 if (!vcpu->arch.mmu.direct_map &&
7941 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7942 return;
7943
56028d08
GN		 7944 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7945}
7946
af585b92
GN		 7947static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7948{
7949 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7950}
7951
7952static inline u32 kvm_async_pf_next_probe(u32 key)
7953{
7954 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7955}
7956
7957static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7958{
7959 u32 key = kvm_async_pf_hash_fn(gfn);
7960
7961 while (vcpu->arch.apf.gfns[key] != ~0)
7962 key = kvm_async_pf_next_probe(key);
7963
7964 vcpu->arch.apf.gfns[key] = gfn;
7965}
7966
7967static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7968{
7969 int i;
7970 u32 key = kvm_async_pf_hash_fn(gfn);
7971
7972 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7973 (vcpu->arch.apf.gfns[key] != gfn &&
7974 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7975 key = kvm_async_pf_next_probe(key);
7976
7977 return key;
7978}
7979
7980bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7981{
7982 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7983}
7984
7985static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7986{
7987 u32 i, j, k;
7988
7989 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7990 while (true) {
7991 vcpu->arch.apf.gfns[i] = ~0;
7992 do {
7993 j = kvm_async_pf_next_probe(j);
7994 if (vcpu->arch.apf.gfns[j] == ~0)
7995 return;
7996 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7997 /*
7998 * k lies cyclically in ]i,j]
7999 * | i.k.j |
8000 * |....j i.k.| or |.k..j i...|
8001 */
8002 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8003 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8004 i = j;
8005 }
8006}
8007
7c90705b
GN		 8008static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8009{
8010
8011 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8012 sizeof(val));
8013}
8014
af585b92
GN		 8015void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8016 struct kvm_async_pf *work)
8017{
6389ee94
AK		 8018 struct x86_exception fault;
8019
7c90705b 8020 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8021 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8022
8023 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8024 (vcpu->arch.apf.send_user_only &&
8025 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8026 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8027 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8028 fault.vector = PF_VECTOR;
8029 fault.error_code_valid = true;
8030 fault.error_code = 0;
8031 fault.nested_page_fault = false;
8032 fault.address = work->arch.token;
8033 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8034 }
af585b92
GN		 8035}
8036
8037void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8038 struct kvm_async_pf *work)
8039{
6389ee94
AK		 8040 struct x86_exception fault;
8041
7c90705b 8042 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8043 if (work->wakeup_all)
7c90705b
GN		 8044 work->arch.token = ~0; /* broadcast wakeup */
8045 else
8046 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8047
8048 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8049 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8050 fault.vector = PF_VECTOR;
8051 fault.error_code_valid = true;
8052 fault.error_code = 0;
8053 fault.nested_page_fault = false;
8054 fault.address = work->arch.token;
8055 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8056 }
e6d53e3b 8057 vcpu->arch.apf.halted = false;
a4fa1635 8058 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8059}
8060
8061bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8062{
8063 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8064 return true;
8065 else
8066 return !kvm_event_needs_reinjection(vcpu) &&
8067 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8068}
8069
e0f0bbc5
AW		 8070void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8071{
8072 atomic_inc(&kvm->arch.noncoherent_dma_count);
8073}
8074EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8075
8076void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8077{
8078 atomic_dec(&kvm->arch.noncoherent_dma_count);
8079}
8080EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8081
8082bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8083{
8084 return atomic_read(&kvm->arch.noncoherent_dma_count);
8085}
8086EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8087
229456fc
MT		 8088EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8089EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8090EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8091EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8092EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8093EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8094EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8095EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8096EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8097EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8098EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8099EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8100EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8101EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8102EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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