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KVM: x86: Access to LDT/GDT that wraparound is incorrect
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
92a1f12d
JR		 102bool kvm_has_tsc_control;
103EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104u32 kvm_max_guest_tsc_khz;
105EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
cc578287
ZA		 107/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108static u32 tsc_tolerance_ppm = 250;
109module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
d0659d94
MT		 111/* lapic timer advance (tscdeadline mode only) in nanoseconds */
112unsigned int lapic_timer_advance_ns = 0;
113module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
16a96021
MT		 115static bool backwards_tsc_observed = false;
116
18863bdd
AK		 117#define KVM_NR_SHARED_MSRS 16
118
119struct kvm_shared_msrs_global {
120 int nr;
2bf78fa7 121 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 122};
123
124struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
2bf78fa7
SY		 127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 131};
132
133static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 134static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 135
417bc304 136struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 147 { "halt_exits", VCPU_STAT(halt_exits) },
148 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 149 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 150 { "request_irq", VCPU_STAT(request_irq_exits) },
151 { "irq_exits", VCPU_STAT(irq_exits) },
152 { "host_state_reload", VCPU_STAT(host_state_reload) },
153 { "efer_reload", VCPU_STAT(efer_reload) },
154 { "fpu_reload", VCPU_STAT(fpu_reload) },
155 { "insn_emulation", VCPU_STAT(insn_emulation) },
156 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 157 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 158 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 159 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
160 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
161 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
162 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
163 { "mmu_flooded", VM_STAT(mmu_flooded) },
164 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 165 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 166 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 167 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 168 { "largepages", VM_STAT(lpages) },
417bc304
HB		 169 { NULL }
170};
171
2acf923e
DC		 172u64 __read_mostly host_xcr0;
173
b6785def 174static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 175
af585b92
GN		 176static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
177{
178 int i;
179 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
180 vcpu->arch.apf.gfns[i] = ~0;
181}
182
18863bdd
AK		 183static void kvm_on_user_return(struct user_return_notifier *urn)
184{
185 unsigned slot;
18863bdd
AK		 186 struct kvm_shared_msrs *locals
187 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 188 struct kvm_shared_msr_values *values;
18863bdd
AK		 189
190 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 191 values = &locals->values[slot];
192 if (values->host != values->curr) {
193 wrmsrl(shared_msrs_global.msrs[slot], values->host);
194 values->curr = values->host;
18863bdd
AK		 195 }
196 }
197 locals->registered = false;
198 user_return_notifier_unregister(urn);
199}
200
2bf78fa7 201static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 202{
18863bdd 203 u64 value;
013f6a5d
MT		 204 unsigned int cpu = smp_processor_id();
205 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 206
2bf78fa7
SY		 207 /* only read, and nobody should modify it at this time,
208 * so don't need lock */
209 if (slot >= shared_msrs_global.nr) {
210 printk(KERN_ERR "kvm: invalid MSR slot!");
211 return;
212 }
213 rdmsrl_safe(msr, &value);
214 smsr->values[slot].host = value;
215 smsr->values[slot].curr = value;
216}
217
218void kvm_define_shared_msr(unsigned slot, u32 msr)
219{
0123be42 220 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 221 if (slot >= shared_msrs_global.nr)
222 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 223 shared_msrs_global.msrs[slot] = msr;
224 /* we need ensured the shared_msr_global have been updated */
225 smp_wmb();
18863bdd
AK		 226}
227EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
228
229static void kvm_shared_msr_cpu_online(void)
230{
231 unsigned i;
18863bdd
AK		 232
233 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 234 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 235}
236
8b3c3104 237int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 238{
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 241 int err;
18863bdd 242
2bf78fa7 243 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 244 return 0;
2bf78fa7 245 smsr->values[slot].curr = value;
8b3c3104
AH		 246 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
247 if (err)
248 return 1;
249
18863bdd
AK		 250 if (!smsr->registered) {
251 smsr->urn.on_user_return = kvm_on_user_return;
252 user_return_notifier_register(&smsr->urn);
253 smsr->registered = true;
254 }
8b3c3104 255 return 0;
18863bdd
AK		 256}
257EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
258
13a34e06 259static void drop_user_return_notifiers(void)
3548bab5 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 263
264 if (smsr->registered)
265 kvm_on_user_return(&smsr->urn);
266}
267
6866b83e
CO		 268u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
269{
8a5a87d9 270 return vcpu->arch.apic_base;
6866b83e
CO		 271}
272EXPORT_SYMBOL_GPL(kvm_get_apic_base);
273
58cb628d
JK		 274int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
275{
276 u64 old_state = vcpu->arch.apic_base &
277 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
278 u64 new_state = msr_info->data &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
281 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
282
283 if (!msr_info->host_initiated &&
284 ((msr_info->data & reserved_bits) != 0 ||
285 new_state == X2APIC_ENABLE ||
286 (new_state == MSR_IA32_APICBASE_ENABLE &&
287 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
288 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
289 old_state == 0)))
290 return 1;
291
292 kvm_lapic_set_base(vcpu, msr_info->data);
293 return 0;
6866b83e
CO		 294}
295EXPORT_SYMBOL_GPL(kvm_set_apic_base);
296
2605fc21 297asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 298{
299 /* Fault while not rebooting. We want the trace. */
300 BUG();
301}
302EXPORT_SYMBOL_GPL(kvm_spurious_fault);
303
3fd28fce
ED		 304#define EXCPT_BENIGN 0
305#define EXCPT_CONTRIBUTORY 1
306#define EXCPT_PF 2
307
308static int exception_class(int vector)
309{
310 switch (vector) {
311 case PF_VECTOR:
312 return EXCPT_PF;
313 case DE_VECTOR:
314 case TS_VECTOR:
315 case NP_VECTOR:
316 case SS_VECTOR:
317 case GP_VECTOR:
318 return EXCPT_CONTRIBUTORY;
319 default:
320 break;
321 }
322 return EXCPT_BENIGN;
323}
324
d6e8c854
NA		 325#define EXCPT_FAULT 0
326#define EXCPT_TRAP 1
327#define EXCPT_ABORT 2
328#define EXCPT_INTERRUPT 3
329
330static int exception_type(int vector)
331{
332 unsigned int mask;
333
334 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
335 return EXCPT_INTERRUPT;
336
337 mask = 1 << vector;
338
339 /* #DB is trap, as instruction watchpoints are handled elsewhere */
340 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
341 return EXCPT_TRAP;
342
343 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
344 return EXCPT_ABORT;
345
346 /* Reserved exceptions will result in fault */
347 return EXCPT_FAULT;
348}
349
3fd28fce 350static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 351 unsigned nr, bool has_error, u32 error_code,
352 bool reinject)
3fd28fce
ED		 353{
354 u32 prev_nr;
355 int class1, class2;
356
3842d135
AK		 357 kvm_make_request(KVM_REQ_EVENT, vcpu);
358
3fd28fce
ED		 359 if (!vcpu->arch.exception.pending) {
360 queue:
3ffb2468
NA		 361 if (has_error && !is_protmode(vcpu))
362 has_error = false;
3fd28fce
ED		 363 vcpu->arch.exception.pending = true;
364 vcpu->arch.exception.has_error_code = has_error;
365 vcpu->arch.exception.nr = nr;
366 vcpu->arch.exception.error_code = error_code;
3f0fd292 367 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 368 return;
369 }
370
371 /* to check exception */
372 prev_nr = vcpu->arch.exception.nr;
373 if (prev_nr == DF_VECTOR) {
374 /* triple fault -> shutdown */
a8eeb04a 375 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 376 return;
377 }
378 class1 = exception_class(prev_nr);
379 class2 = exception_class(nr);
380 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
381 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
382 /* generate double fault per SDM Table 5-5 */
383 vcpu->arch.exception.pending = true;
384 vcpu->arch.exception.has_error_code = true;
385 vcpu->arch.exception.nr = DF_VECTOR;
386 vcpu->arch.exception.error_code = 0;
387 } else
388 /* replace previous exception with a new one in a hope
389 that instruction re-execution will regenerate lost
390 exception */
391 goto queue;
392}
393
298101da
AK		 394void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
395{
ce7ddec4 396 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 397}
398EXPORT_SYMBOL_GPL(kvm_queue_exception);
399
ce7ddec4
JR		 400void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
401{
402 kvm_multiple_exception(vcpu, nr, false, 0, true);
403}
404EXPORT_SYMBOL_GPL(kvm_requeue_exception);
405
db8fcefa 406void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 407{
db8fcefa
AP		 408 if (err)
409 kvm_inject_gp(vcpu, 0);
410 else
411 kvm_x86_ops->skip_emulated_instruction(vcpu);
412}
413EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 414
6389ee94 415void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 416{
417 ++vcpu->stat.pf_guest;
6389ee94
AK		 418 vcpu->arch.cr2 = fault->address;
419 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 420}
27d6c865 421EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 422
ef54bcfe 423static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 424{
6389ee94
AK		 425 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
426 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 427 else
6389ee94 428 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 429
430 return fault->nested_page_fault;
d4f8cf66
JR		 431}
432
3419ffc8
SY		 433void kvm_inject_nmi(struct kvm_vcpu *vcpu)
434{
7460fb4a
AK		 435 atomic_inc(&vcpu->arch.nmi_queued);
436 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 437}
438EXPORT_SYMBOL_GPL(kvm_inject_nmi);
439
298101da
AK		 440void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
441{
ce7ddec4 442 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 443}
444EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
445
ce7ddec4
JR		 446void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
447{
448 kvm_multiple_exception(vcpu, nr, true, error_code, true);
449}
450EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
451
0a79b009
AK		 452/*
453 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
454 * a #GP and return false.
455 */
456bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 457{
0a79b009
AK		 458 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
459 return true;
460 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
461 return false;
298101da 462}
0a79b009 463EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 464
16f8a6f9
NA		 465bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
466{
467 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
468 return true;
469
470 kvm_queue_exception(vcpu, UD_VECTOR);
471 return false;
472}
473EXPORT_SYMBOL_GPL(kvm_require_dr);
474
ec92fe44
JR		 475/*
476 * This function will be used to read from the physical memory of the currently
477 * running guest. The difference to kvm_read_guest_page is that this function
478 * can read from guest physical or from the guest's guest physical memory.
479 */
480int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
481 gfn_t ngfn, void *data, int offset, int len,
482 u32 access)
483{
54987b7a 484 struct x86_exception exception;
ec92fe44
JR		 485 gfn_t real_gfn;
486 gpa_t ngpa;
487
488 ngpa = gfn_to_gpa(ngfn);
54987b7a 489 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 490 if (real_gfn == UNMAPPED_GVA)
491 return -EFAULT;
492
493 real_gfn = gpa_to_gfn(real_gfn);
494
495 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
496}
497EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
498
3d06b8bf
JR		 499int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
500 void *data, int offset, int len, u32 access)
501{
502 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
503 data, offset, len, access);
504}
505
a03490ed
CO		 506/*
507 * Load the pae pdptrs. Return true is they are all valid.
508 */
ff03a073 509int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 510{
511 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
512 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
513 int i;
514 int ret;
ff03a073 515 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 516
ff03a073
JR		 517 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
518 offset * sizeof(u64), sizeof(pdpte),
519 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 520 if (ret < 0) {
521 ret = 0;
522 goto out;
523 }
524 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 525 if (is_present_gpte(pdpte[i]) &&
20c466b5 526 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 527 ret = 0;
528 goto out;
529 }
530 }
531 ret = 1;
532
ff03a073 533 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 534 __set_bit(VCPU_EXREG_PDPTR,
535 (unsigned long *)&vcpu->arch.regs_avail);
536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 538out:
a03490ed
CO		 539
540 return ret;
541}
cc4b6871 542EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 543
d835dfec
AK		 544static bool pdptrs_changed(struct kvm_vcpu *vcpu)
545{
ff03a073 546 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 547 bool changed = true;
3d06b8bf
JR		 548 int offset;
549 gfn_t gfn;
d835dfec
AK		 550 int r;
551
552 if (is_long_mode(vcpu) || !is_pae(vcpu))
553 return false;
554
6de4f3ad
AK		 555 if (!test_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_avail))
557 return true;
558
9f8fe504
AK		 559 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
560 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 561 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
562 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 563 if (r < 0)
564 goto out;
ff03a073 565 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 566out:
d835dfec
AK		 567
568 return changed;
569}
570
49a9b07e 571int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 572{
aad82703
SY		 573 unsigned long old_cr0 = kvm_read_cr0(vcpu);
574 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
575 X86_CR0_CD | X86_CR0_NW;
576
f9a48e6a
AK		 577 cr0 |= X86_CR0_ET;
578
ab344828 579#ifdef CONFIG_X86_64
0f12244f
GN		 580 if (cr0 & 0xffffffff00000000UL)
581 return 1;
ab344828
GN		 582#endif
583
584 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 585
0f12244f
GN		 586 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
587 return 1;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
590 return 1;
a03490ed
CO		 591
592 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
593#ifdef CONFIG_X86_64
f6801dff 594 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 595 int cs_db, cs_l;
596
0f12244f
GN		 597 if (!is_pae(vcpu))
598 return 1;
a03490ed 599 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 600 if (cs_l)
601 return 1;
a03490ed
CO		 602 } else
603#endif
ff03a073 604 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 605 kvm_read_cr3(vcpu)))
0f12244f 606 return 1;
a03490ed
CO		 607 }
608
ad756a16
MJ		 609 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
610 return 1;
611
a03490ed 612 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 613
d170c419 614 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 615 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 616 kvm_async_pf_hash_reset(vcpu);
617 }
e5f3f027 618
aad82703
SY		 619 if ((cr0 ^ old_cr0) & update_bits)
620 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 621 return 0;
622}
2d3ad1f4 623EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 624
2d3ad1f4 625void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 626{
49a9b07e 627 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 630
42bdf991
MT		 631static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
632{
633 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
634 !vcpu->guest_xcr0_loaded) {
635 /* kvm_set_xcr() also depends on this */
636 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
637 vcpu->guest_xcr0_loaded = 1;
638 }
639}
640
641static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
642{
643 if (vcpu->guest_xcr0_loaded) {
644 if (vcpu->arch.xcr0 != host_xcr0)
645 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
646 vcpu->guest_xcr0_loaded = 0;
647 }
648}
649
2acf923e
DC		 650int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
651{
56c103ec
LJ		 652 u64 xcr0 = xcr;
653 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 654 u64 valid_bits;
2acf923e
DC		 655
656 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
657 if (index != XCR_XFEATURE_ENABLED_MASK)
658 return 1;
2acf923e
DC		 659 if (!(xcr0 & XSTATE_FP))
660 return 1;
661 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
662 return 1;
46c34cb0
PB		 663
664 /*
665 * Do not allow the guest to set bits that we do not support
666 * saving. However, xcr0 bit 0 is always set, even if the
667 * emulated CPU does not support XSAVE (see fx_init).
668 */
669 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
670 if (xcr0 & ~valid_bits)
2acf923e 671 return 1;
46c34cb0 672
390bd528
LJ		 673 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
674 return 1;
675
612263b3
CP		 676 if (xcr0 & XSTATE_AVX512) {
677 if (!(xcr0 & XSTATE_YMM))
678 return 1;
679 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
680 return 1;
681 }
42bdf991 682 kvm_put_guest_xcr0(vcpu);
2acf923e 683 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 684
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
2acf923e
DC		 687 return 0;
688}
689
690int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
691{
764bcbc5
Z		 692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 694 kvm_inject_gp(vcpu, 0);
695 return 1;
696 }
697 return 0;
698}
699EXPORT_SYMBOL_GPL(kvm_set_xcr);
700
a83b29c6 701int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 702{
fc78f519 703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
705 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 706 if (cr4 & CR4_RESERVED_BITS)
707 return 1;
a03490ed 708
2acf923e
DC		 709 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
710 return 1;
711
c68b734f
YW		 712 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
713 return 1;
714
97ec8c06
FW		 715 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
716 return 1;
717
afcbf13f 718 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 719 return 1;
720
a03490ed 721 if (is_long_mode(vcpu)) {
0f12244f
GN		 722 if (!(cr4 & X86_CR4_PAE))
723 return 1;
a2edf57f
AK		 724 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
725 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 726 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
727 kvm_read_cr3(vcpu)))
0f12244f
GN		 728 return 1;
729
ad756a16
MJ		 730 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
731 if (!guest_cpuid_has_pcid(vcpu))
732 return 1;
733
734 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
735 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
736 return 1;
737 }
738
5e1746d6 739 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 740 return 1;
a03490ed 741
ad756a16
MJ		 742 if (((cr4 ^ old_cr4) & pdptr_bits) ||
743 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 744 kvm_mmu_reset_context(vcpu);
0f12244f 745
97ec8c06
FW		 746 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
747 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
748
2acf923e 749 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 750 kvm_update_cpuid(vcpu);
2acf923e 751
0f12244f
GN		 752 return 0;
753}
2d3ad1f4 754EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 755
2390218b 756int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 757{
ac146235 758#ifdef CONFIG_X86_64
9d88fca7 759 cr3 &= ~CR3_PCID_INVD;
ac146235 760#endif
9d88fca7 761
9f8fe504 762 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 763 kvm_mmu_sync_roots(vcpu);
77c3913b 764 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 765 return 0;
d835dfec
AK		 766 }
767
a03490ed 768 if (is_long_mode(vcpu)) {
d9f89b88
JK		 769 if (cr3 & CR3_L_MODE_RESERVED_BITS)
770 return 1;
771 } else if (is_pae(vcpu) && is_paging(vcpu) &&
772 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 773 return 1;
a03490ed 774
0f12244f 775 vcpu->arch.cr3 = cr3;
aff48baa 776 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 777 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 778 return 0;
779}
2d3ad1f4 780EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 781
eea1cff9 782int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 783{
0f12244f
GN		 784 if (cr8 & CR8_RESERVED_BITS)
785 return 1;
a03490ed
CO		 786 if (irqchip_in_kernel(vcpu->kvm))
787 kvm_lapic_set_tpr(vcpu, cr8);
788 else
ad312c7c 789 vcpu->arch.cr8 = cr8;
0f12244f
GN		 790 return 0;
791}
2d3ad1f4 792EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 793
2d3ad1f4 794unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 795{
796 if (irqchip_in_kernel(vcpu->kvm))
797 return kvm_lapic_get_cr8(vcpu);
798 else
ad312c7c 799 return vcpu->arch.cr8;
a03490ed 800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 802
73aaf249
JK		 803static void kvm_update_dr6(struct kvm_vcpu *vcpu)
804{
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
807}
808
c8639010
JK		 809static void kvm_update_dr7(struct kvm_vcpu *vcpu)
810{
811 unsigned long dr7;
812
813 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
814 dr7 = vcpu->arch.guest_debug_dr7;
815 else
816 dr7 = vcpu->arch.dr7;
817 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 818 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
819 if (dr7 & DR7_BP_EN_MASK)
820 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 821}
822
6f43ed01
NA		 823static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
824{
825 u64 fixed = DR6_FIXED_1;
826
827 if (!guest_cpuid_has_rtm(vcpu))
828 fixed |= DR6_RTM;
829 return fixed;
830}
831
338dbc97 832static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 833{
834 switch (dr) {
835 case 0 ... 3:
836 vcpu->arch.db[dr] = val;
837 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
838 vcpu->arch.eff_db[dr] = val;
839 break;
840 case 4:
020df079
GN		 841 /* fall through */
842 case 6:
338dbc97
GN		 843 if (val & 0xffffffff00000000ULL)
844 return -1; /* #GP */
6f43ed01 845 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 846 kvm_update_dr6(vcpu);
020df079
GN		 847 break;
848 case 5:
020df079
GN		 849 /* fall through */
850 default: /* 7 */
338dbc97
GN		 851 if (val & 0xffffffff00000000ULL)
852 return -1; /* #GP */
020df079 853 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 854 kvm_update_dr7(vcpu);
020df079
GN		 855 break;
856 }
857
858 return 0;
859}
338dbc97
GN		 860
861int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
862{
16f8a6f9 863 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 864 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 865 return 1;
866 }
867 return 0;
338dbc97 868}
020df079
GN		 869EXPORT_SYMBOL_GPL(kvm_set_dr);
870
16f8a6f9 871int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 872{
873 switch (dr) {
874 case 0 ... 3:
875 *val = vcpu->arch.db[dr];
876 break;
877 case 4:
020df079
GN		 878 /* fall through */
879 case 6:
73aaf249
JK		 880 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
881 *val = vcpu->arch.dr6;
882 else
883 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 884 break;
885 case 5:
020df079
GN		 886 /* fall through */
887 default: /* 7 */
888 *val = vcpu->arch.dr7;
889 break;
890 }
338dbc97
GN		 891 return 0;
892}
020df079
GN		 893EXPORT_SYMBOL_GPL(kvm_get_dr);
894
022cd0e8
AK		 895bool kvm_rdpmc(struct kvm_vcpu *vcpu)
896{
897 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
898 u64 data;
899 int err;
900
901 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
902 if (err)
903 return err;
904 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
905 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
906 return err;
907}
908EXPORT_SYMBOL_GPL(kvm_rdpmc);
909
043405e1
CO		 910/*
911 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
912 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
913 *
914 * This list is modified at module load time to reflect the
e3267cbb
GC		 915 * capabilities of the host cpu. This capabilities test skips MSRs that are
916 * kvm-specific. Those are put in the beginning of the list.
043405e1 917 */
e3267cbb 918
e984097b 919#define KVM_SAVE_MSRS_BEGIN 12
043405e1 920static u32 msrs_to_save[] = {
e3267cbb 921 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 922 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 923 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 924 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 925 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 926 MSR_KVM_PV_EOI_EN,
043405e1 927 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 928 MSR_STAR,
043405e1
CO		 929#ifdef CONFIG_X86_64
930 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
931#endif
b3897a49 932 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 933 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 934};
935
936static unsigned num_msrs_to_save;
937
f1d24831 938static const u32 emulated_msrs[] = {
ba904635 939 MSR_IA32_TSC_ADJUST,
a3e06bbe 940 MSR_IA32_TSCDEADLINE,
043405e1 941 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 942 MSR_IA32_MCG_STATUS,
943 MSR_IA32_MCG_CTL,
043405e1
CO		 944};
945
384bb783 946bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 947{
b69e8cae 948 if (efer & efer_reserved_bits)
384bb783 949 return false;
15c4a640 950
1b2fd70c
AG		 951 if (efer & EFER_FFXSR) {
952 struct kvm_cpuid_entry2 *feat;
953
954 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 955 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 956 return false;
1b2fd70c
AG		 957 }
958
d8017474
AG		 959 if (efer & EFER_SVME) {
960 struct kvm_cpuid_entry2 *feat;
961
962 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 963 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 964 return false;
d8017474
AG		 965 }
966
384bb783
JK		 967 return true;
968}
969EXPORT_SYMBOL_GPL(kvm_valid_efer);
970
971static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
972{
973 u64 old_efer = vcpu->arch.efer;
974
975 if (!kvm_valid_efer(vcpu, efer))
976 return 1;
977
978 if (is_paging(vcpu)
979 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
980 return 1;
981
15c4a640 982 efer &= ~EFER_LMA;
f6801dff 983 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 984
a3d204e2
SY		 985 kvm_x86_ops->set_efer(vcpu, efer);
986
aad82703
SY		 987 /* Update reserved bits */
988 if ((efer ^ old_efer) & EFER_NX)
989 kvm_mmu_reset_context(vcpu);
990
b69e8cae 991 return 0;
15c4a640
CO		 992}
993
f2b4b7dd
JR		 994void kvm_enable_efer_bits(u64 mask)
995{
996 efer_reserved_bits &= ~mask;
997}
998EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
999
15c4a640
CO		 1000/*
1001 * Writes msr value into into the appropriate "register".
1002 * Returns 0 on success, non-0 otherwise.
1003 * Assumes vcpu_load() was already called.
1004 */
8fe8ab46 1005int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1006{
854e8bb1
NA		 1007 switch (msr->index) {
1008 case MSR_FS_BASE:
1009 case MSR_GS_BASE:
1010 case MSR_KERNEL_GS_BASE:
1011 case MSR_CSTAR:
1012 case MSR_LSTAR:
1013 if (is_noncanonical_address(msr->data))
1014 return 1;
1015 break;
1016 case MSR_IA32_SYSENTER_EIP:
1017 case MSR_IA32_SYSENTER_ESP:
1018 /*
1019 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1020 * non-canonical address is written on Intel but not on
1021 * AMD (which ignores the top 32-bits, because it does
1022 * not implement 64-bit SYSENTER).
1023 *
1024 * 64-bit code should hence be able to write a non-canonical
1025 * value on AMD. Making the address canonical ensures that
1026 * vmentry does not fail on Intel after writing a non-canonical
1027 * value, and that something deterministic happens if the guest
1028 * invokes 64-bit SYSENTER.
1029 */
1030 msr->data = get_canonical(msr->data);
1031 }
8fe8ab46 1032 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1033}
854e8bb1 1034EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1035
313a3dc7
CO		 1036/*
1037 * Adapt set_msr() to msr_io()'s calling convention
1038 */
1039static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1040{
8fe8ab46
WA		 1041 struct msr_data msr;
1042
1043 msr.data = *data;
1044 msr.index = index;
1045 msr.host_initiated = true;
1046 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1047}
1048
16e8d74d
MT		 1049#ifdef CONFIG_X86_64
1050struct pvclock_gtod_data {
1051 seqcount_t seq;
1052
1053 struct { /* extract of a clocksource struct */
1054 int vclock_mode;
1055 cycle_t cycle_last;
1056 cycle_t mask;
1057 u32 mult;
1058 u32 shift;
1059 } clock;
1060
cbcf2dd3
TG		 1061 u64 boot_ns;
1062 u64 nsec_base;
16e8d74d
MT		 1063};
1064
1065static struct pvclock_gtod_data pvclock_gtod_data;
1066
1067static void update_pvclock_gtod(struct timekeeper *tk)
1068{
1069 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1070 u64 boot_ns;
1071
d28ede83 1072 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1073
1074 write_seqcount_begin(&vdata->seq);
1075
1076 /* copy pvclock gtod data */
d28ede83
TG		 1077 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1078 vdata->clock.cycle_last = tk->tkr.cycle_last;
1079 vdata->clock.mask = tk->tkr.mask;
1080 vdata->clock.mult = tk->tkr.mult;
1081 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1082
cbcf2dd3 1083 vdata->boot_ns = boot_ns;
d28ede83 1084 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1085
1086 write_seqcount_end(&vdata->seq);
1087}
1088#endif
1089
1090
18068523
GOC		 1091static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1092{
9ed3c444
AK		 1093 int version;
1094 int r;
50d0a0f9 1095 struct pvclock_wall_clock wc;
923de3cf 1096 struct timespec boot;
18068523
GOC		 1097
1098 if (!wall_clock)
1099 return;
1100
9ed3c444
AK		 1101 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1102 if (r)
1103 return;
1104
1105 if (version & 1)
1106 ++version; /* first time write, random junk */
1107
1108 ++version;
18068523 1109
18068523
GOC		 1110 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1111
50d0a0f9
GH		 1112 /*
1113 * The guest calculates current wall clock time by adding
34c238a1 1114 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1115 * wall clock specified here. guest system time equals host
1116 * system time for us, thus we must fill in host boot time here.
1117 */
923de3cf 1118 getboottime(&boot);
50d0a0f9 1119
4b648665
BR		 1120 if (kvm->arch.kvmclock_offset) {
1121 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1122 boot = timespec_sub(boot, ts);
1123 }
50d0a0f9
GH		 1124 wc.sec = boot.tv_sec;
1125 wc.nsec = boot.tv_nsec;
1126 wc.version = version;
18068523
GOC		 1127
1128 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1129
1130 version++;
1131 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1132}
1133
50d0a0f9
GH		 1134static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1135{
1136 uint32_t quotient, remainder;
1137
1138 /* Don't try to replace with do_div(), this one calculates
1139 * "(dividend << 32) / divisor" */
1140 __asm__ ( "divl %4"
1141 : "=a" (quotient), "=d" (remainder)
1142 : "0" (0), "1" (dividend), "r" (divisor) );
1143 return quotient;
1144}
1145
5f4e3f88
ZA		 1146static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1147 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1148{
5f4e3f88 1149 uint64_t scaled64;
50d0a0f9
GH		 1150 int32_t shift = 0;
1151 uint64_t tps64;
1152 uint32_t tps32;
1153
5f4e3f88
ZA		 1154 tps64 = base_khz * 1000LL;
1155 scaled64 = scaled_khz * 1000LL;
50933623 1156 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1157 tps64 >>= 1;
1158 shift--;
1159 }
1160
1161 tps32 = (uint32_t)tps64;
50933623
JK		 1162 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1163 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1164 scaled64 >>= 1;
1165 else
1166 tps32 <<= 1;
50d0a0f9
GH		 1167 shift++;
1168 }
1169
5f4e3f88
ZA		 1170 *pshift = shift;
1171 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1172
5f4e3f88
ZA		 1173 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1174 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1175}
1176
759379dd
ZA		 1177static inline u64 get_kernel_ns(void)
1178{
bb0b5812 1179 return ktime_get_boot_ns();
50d0a0f9
GH		 1180}
1181
d828199e 1182#ifdef CONFIG_X86_64
16e8d74d 1183static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1184#endif
16e8d74d 1185
c8076604 1186static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1187unsigned long max_tsc_khz;
c8076604 1188
cc578287 1189static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1190{
cc578287
ZA		 1191 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1192 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1193}
1194
cc578287 1195static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1196{
cc578287
ZA		 1197 u64 v = (u64)khz * (1000000 + ppm);
1198 do_div(v, 1000000);
1199 return v;
1e993611
JR		 1200}
1201
cc578287 1202static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1203{
cc578287
ZA		 1204 u32 thresh_lo, thresh_hi;
1205 int use_scaling = 0;
217fc9cf 1206
03ba32ca
MT		 1207 /* tsc_khz can be zero if TSC calibration fails */
1208 if (this_tsc_khz == 0)
1209 return;
1210
c285545f
ZA		 1211 /* Compute a scale to convert nanoseconds in TSC cycles */
1212 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1213 &vcpu->arch.virtual_tsc_shift,
1214 &vcpu->arch.virtual_tsc_mult);
1215 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1216
1217 /*
1218 * Compute the variation in TSC rate which is acceptable
1219 * within the range of tolerance and decide if the
1220 * rate being applied is within that bounds of the hardware
1221 * rate. If so, no scaling or compensation need be done.
1222 */
1223 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1224 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1225 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1226 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1227 use_scaling = 1;
1228 }
1229 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1230}
1231
1232static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1233{
e26101b1 1234 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1235 vcpu->arch.virtual_tsc_mult,
1236 vcpu->arch.virtual_tsc_shift);
e26101b1 1237 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1238 return tsc;
1239}
1240
b48aa97e
MT		 1241void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1242{
1243#ifdef CONFIG_X86_64
1244 bool vcpus_matched;
b48aa97e
MT		 1245 struct kvm_arch *ka = &vcpu->kvm->arch;
1246 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1247
1248 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1249 atomic_read(&vcpu->kvm->online_vcpus));
1250
7f187922
MT		 1251 /*
1252 * Once the masterclock is enabled, always perform request in
1253 * order to update it.
1254 *
1255 * In order to enable masterclock, the host clocksource must be TSC
1256 * and the vcpus need to have matched TSCs. When that happens,
1257 * perform request to enable masterclock.
1258 */
1259 if (ka->use_master_clock ||
1260 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1261 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1262
1263 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1264 atomic_read(&vcpu->kvm->online_vcpus),
1265 ka->use_master_clock, gtod->clock.vclock_mode);
1266#endif
1267}
1268
ba904635
WA		 1269static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1270{
1271 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1272 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1273}
1274
8fe8ab46 1275void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1276{
1277 struct kvm *kvm = vcpu->kvm;
f38e098f 1278 u64 offset, ns, elapsed;
99e3e30a 1279 unsigned long flags;
02626b6a 1280 s64 usdiff;
b48aa97e 1281 bool matched;
0d3da0d2 1282 bool already_matched;
8fe8ab46 1283 u64 data = msr->data;
99e3e30a 1284
038f8c11 1285 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1286 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1287 ns = get_kernel_ns();
f38e098f 1288 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1289
03ba32ca 1290 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1291 int faulted = 0;
1292
03ba32ca
MT		 1293 /* n.b - signed multiplication and division required */
1294 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1295#ifdef CONFIG_X86_64
03ba32ca 1296 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1297#else
03ba32ca 1298 /* do_div() only does unsigned */
8915aa27
MT		 1299 asm("1: idivl %[divisor]\n"
1300 "2: xor %%edx, %%edx\n"
1301 " movl $0, %[faulted]\n"
1302 "3:\n"
1303 ".section .fixup,\"ax\"\n"
1304 "4: movl $1, %[faulted]\n"
1305 " jmp 3b\n"
1306 ".previous\n"
1307
1308 _ASM_EXTABLE(1b, 4b)
1309
1310 : "=A"(usdiff), [faulted] "=r" (faulted)
1311 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1312
5d3cb0f6 1313#endif
03ba32ca
MT		 1314 do_div(elapsed, 1000);
1315 usdiff -= elapsed;
1316 if (usdiff < 0)
1317 usdiff = -usdiff;
8915aa27
MT		 1318
1319 /* idivl overflow => difference is larger than USEC_PER_SEC */
1320 if (faulted)
1321 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1322 } else
1323 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1324
1325 /*
5d3cb0f6
ZA		 1326 * Special case: TSC write with a small delta (1 second) of virtual
1327 * cycle time against real time is interpreted as an attempt to
1328 * synchronize the CPU.
1329 *
1330 * For a reliable TSC, we can match TSC offsets, and for an unstable
1331 * TSC, we add elapsed time in this computation. We could let the
1332 * compensation code attempt to catch up if we fall behind, but
1333 * it's better to try to match offsets from the beginning.
1334 */
02626b6a 1335 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1336 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1337 if (!check_tsc_unstable()) {
e26101b1 1338 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1339 pr_debug("kvm: matched tsc offset for %llu\n", data);
1340 } else {
857e4099 1341 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1342 data += delta;
1343 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1344 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1345 }
b48aa97e 1346 matched = true;
0d3da0d2 1347 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1348 } else {
1349 /*
1350 * We split periods of matched TSC writes into generations.
1351 * For each generation, we track the original measured
1352 * nanosecond time, offset, and write, so if TSCs are in
1353 * sync, we can match exact offset, and if not, we can match
4a969980 1354 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1355 *
1356 * These values are tracked in kvm->arch.cur_xxx variables.
1357 */
1358 kvm->arch.cur_tsc_generation++;
1359 kvm->arch.cur_tsc_nsec = ns;
1360 kvm->arch.cur_tsc_write = data;
1361 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1362 matched = false;
0d3da0d2 1363 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1364 kvm->arch.cur_tsc_generation, data);
f38e098f 1365 }
e26101b1
ZA		 1366
1367 /*
1368 * We also track th most recent recorded KHZ, write and time to
1369 * allow the matching interval to be extended at each write.
1370 */
f38e098f
ZA		 1371 kvm->arch.last_tsc_nsec = ns;
1372 kvm->arch.last_tsc_write = data;
5d3cb0f6 1373 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1374
b183aa58 1375 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1376
1377 /* Keep track of which generation this VCPU has synchronized to */
1378 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1379 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1380 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1381
ba904635
WA		 1382 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1383 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1384 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1385 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1386
1387 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1388 if (!matched) {
b48aa97e 1389 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1390 } else if (!already_matched) {
1391 kvm->arch.nr_vcpus_matched_tsc++;
1392 }
b48aa97e
MT		 1393
1394 kvm_track_tsc_matching(vcpu);
1395 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1396}
e26101b1 1397
99e3e30a
ZA		 1398EXPORT_SYMBOL_GPL(kvm_write_tsc);
1399
d828199e
MT		 1400#ifdef CONFIG_X86_64
1401
1402static cycle_t read_tsc(void)
1403{
1404 cycle_t ret;
1405 u64 last;
1406
1407 /*
1408 * Empirically, a fence (of type that depends on the CPU)
1409 * before rdtsc is enough to ensure that rdtsc is ordered
1410 * with respect to loads. The various CPU manuals are unclear
1411 * as to whether rdtsc can be reordered with later loads,
1412 * but no one has ever seen it happen.
1413 */
1414 rdtsc_barrier();
1415 ret = (cycle_t)vget_cycles();
1416
1417 last = pvclock_gtod_data.clock.cycle_last;
1418
1419 if (likely(ret >= last))
1420 return ret;
1421
1422 /*
1423 * GCC likes to generate cmov here, but this branch is extremely
1424 * predictable (it's just a funciton of time and the likely is
1425 * very likely) and there's a data dependence, so force GCC
1426 * to generate a branch instead. I don't barrier() because
1427 * we don't actually need a barrier, and if this function
1428 * ever gets inlined it will generate worse code.
1429 */
1430 asm volatile ("");
1431 return last;
1432}
1433
1434static inline u64 vgettsc(cycle_t *cycle_now)
1435{
1436 long v;
1437 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1438
1439 *cycle_now = read_tsc();
1440
1441 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1442 return v * gtod->clock.mult;
1443}
1444
cbcf2dd3 1445static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1446{
cbcf2dd3 1447 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1448 unsigned long seq;
d828199e 1449 int mode;
cbcf2dd3 1450 u64 ns;
d828199e 1451
d828199e
MT		 1452 do {
1453 seq = read_seqcount_begin(&gtod->seq);
1454 mode = gtod->clock.vclock_mode;
cbcf2dd3 1455 ns = gtod->nsec_base;
d828199e
MT		 1456 ns += vgettsc(cycle_now);
1457 ns >>= gtod->clock.shift;
cbcf2dd3 1458 ns += gtod->boot_ns;
d828199e 1459 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1460 *t = ns;
d828199e
MT		 1461
1462 return mode;
1463}
1464
1465/* returns true if host is using tsc clocksource */
1466static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1467{
d828199e
MT		 1468 /* checked again under seqlock below */
1469 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1470 return false;
1471
cbcf2dd3 1472 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1473}
1474#endif
1475
1476/*
1477 *
b48aa97e
MT		 1478 * Assuming a stable TSC across physical CPUS, and a stable TSC
1479 * across virtual CPUs, the following condition is possible.
1480 * Each numbered line represents an event visible to both
d828199e
MT		 1481 * CPUs at the next numbered event.
1482 *
1483 * "timespecX" represents host monotonic time. "tscX" represents
1484 * RDTSC value.
1485 *
1486 * VCPU0 on CPU0 | VCPU1 on CPU1
1487 *
1488 * 1. read timespec0,tsc0
1489 * 2. | timespec1 = timespec0 + N
1490 * | tsc1 = tsc0 + M
1491 * 3. transition to guest | transition to guest
1492 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1493 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1494 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1495 *
1496 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1497 *
1498 * - ret0 < ret1
1499 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1500 * ...
1501 * - 0 < N - M => M < N
1502 *
1503 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1504 * always the case (the difference between two distinct xtime instances
1505 * might be smaller then the difference between corresponding TSC reads,
1506 * when updating guest vcpus pvclock areas).
1507 *
1508 * To avoid that problem, do not allow visibility of distinct
1509 * system_timestamp/tsc_timestamp values simultaneously: use a master
1510 * copy of host monotonic time values. Update that master copy
1511 * in lockstep.
1512 *
b48aa97e 1513 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1514 *
1515 */
1516
1517static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1518{
1519#ifdef CONFIG_X86_64
1520 struct kvm_arch *ka = &kvm->arch;
1521 int vclock_mode;
b48aa97e
MT		 1522 bool host_tsc_clocksource, vcpus_matched;
1523
1524 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1525 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1526
1527 /*
1528 * If the host uses TSC clock, then passthrough TSC as stable
1529 * to the guest.
1530 */
b48aa97e 1531 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1532 &ka->master_kernel_ns,
1533 &ka->master_cycle_now);
1534
16a96021
MT		 1535 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1536 && !backwards_tsc_observed;
b48aa97e 1537
d828199e
MT		 1538 if (ka->use_master_clock)
1539 atomic_set(&kvm_guest_has_master_clock, 1);
1540
1541 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1542 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1543 vcpus_matched);
d828199e
MT		 1544#endif
1545}
1546
2e762ff7
MT		 1547static void kvm_gen_update_masterclock(struct kvm *kvm)
1548{
1549#ifdef CONFIG_X86_64
1550 int i;
1551 struct kvm_vcpu *vcpu;
1552 struct kvm_arch *ka = &kvm->arch;
1553
1554 spin_lock(&ka->pvclock_gtod_sync_lock);
1555 kvm_make_mclock_inprogress_request(kvm);
1556 /* no guest entries from this point */
1557 pvclock_update_vm_gtod_copy(kvm);
1558
1559 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1560 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1561
1562 /* guest entries allowed */
1563 kvm_for_each_vcpu(i, vcpu, kvm)
1564 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1565
1566 spin_unlock(&ka->pvclock_gtod_sync_lock);
1567#endif
1568}
1569
34c238a1 1570static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1571{
d828199e 1572 unsigned long flags, this_tsc_khz;
18068523 1573 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1574 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1575 s64 kernel_ns;
d828199e 1576 u64 tsc_timestamp, host_tsc;
0b79459b 1577 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1578 u8 pvclock_flags;
d828199e
MT		 1579 bool use_master_clock;
1580
1581 kernel_ns = 0;
1582 host_tsc = 0;
18068523 1583
d828199e
MT		 1584 /*
1585 * If the host uses TSC clock, then passthrough TSC as stable
1586 * to the guest.
1587 */
1588 spin_lock(&ka->pvclock_gtod_sync_lock);
1589 use_master_clock = ka->use_master_clock;
1590 if (use_master_clock) {
1591 host_tsc = ka->master_cycle_now;
1592 kernel_ns = ka->master_kernel_ns;
1593 }
1594 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1595
1596 /* Keep irq disabled to prevent changes to the clock */
1597 local_irq_save(flags);
89cbc767 1598 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1599 if (unlikely(this_tsc_khz == 0)) {
1600 local_irq_restore(flags);
1601 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1602 return 1;
1603 }
d828199e
MT		 1604 if (!use_master_clock) {
1605 host_tsc = native_read_tsc();
1606 kernel_ns = get_kernel_ns();
1607 }
1608
1609 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1610
c285545f
ZA		 1611 /*
1612 * We may have to catch up the TSC to match elapsed wall clock
1613 * time for two reasons, even if kvmclock is used.
1614 * 1) CPU could have been running below the maximum TSC rate
1615 * 2) Broken TSC compensation resets the base at each VCPU
1616 * entry to avoid unknown leaps of TSC even when running
1617 * again on the same CPU. This may cause apparent elapsed
1618 * time to disappear, and the guest to stand still or run
1619 * very slowly.
1620 */
1621 if (vcpu->tsc_catchup) {
1622 u64 tsc = compute_guest_tsc(v, kernel_ns);
1623 if (tsc > tsc_timestamp) {
f1e2b260 1624 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1625 tsc_timestamp = tsc;
1626 }
50d0a0f9
GH		 1627 }
1628
18068523
GOC		 1629 local_irq_restore(flags);
1630
0b79459b 1631 if (!vcpu->pv_time_enabled)
c285545f 1632 return 0;
18068523 1633
e48672fa 1634 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1635 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1636 &vcpu->hv_clock.tsc_shift,
1637 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1638 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1639 }
1640
1641 /* With all the info we got, fill in the values */
1d5f066e 1642 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1643 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1644 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1645
09a0c3f1
OH		 1646 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1647 &guest_hv_clock, sizeof(guest_hv_clock))))
1648 return 0;
1649
18068523
GOC		 1650 /*
1651 * The interface expects us to write an even number signaling that the
1652 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1653 * state, we just increase by 2 at the end.
18068523 1654 */
09a0c3f1 1655 vcpu->hv_clock.version = guest_hv_clock.version + 2;
78c0337a
MT		 1656
1657 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1658 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1659
1660 if (vcpu->pvclock_set_guest_stopped_request) {
1661 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1662 vcpu->pvclock_set_guest_stopped_request = false;
1663 }
1664
d828199e
MT		 1665 /* If the host uses TSC clocksource, then it is stable */
1666 if (use_master_clock)
1667 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1668
78c0337a
MT		 1669 vcpu->hv_clock.flags = pvclock_flags;
1670
ce1a5e60
DM		 1671 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1672
0b79459b
AH		 1673 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1674 &vcpu->hv_clock,
1675 sizeof(vcpu->hv_clock));
8cfdc000 1676 return 0;
c8076604
GH		 1677}
1678
0061d53d
MT		 1679/*
1680 * kvmclock updates which are isolated to a given vcpu, such as
1681 * vcpu->cpu migration, should not allow system_timestamp from
1682 * the rest of the vcpus to remain static. Otherwise ntp frequency
1683 * correction applies to one vcpu's system_timestamp but not
1684 * the others.
1685 *
1686 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1687 * We need to rate-limit these requests though, as they can
1688 * considerably slow guests that have a large number of vcpus.
1689 * The time for a remote vcpu to update its kvmclock is bound
1690 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1691 */
1692
7e44e449
AJ		 1693#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1694
1695static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1696{
1697 int i;
7e44e449
AJ		 1698 struct delayed_work *dwork = to_delayed_work(work);
1699 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1700 kvmclock_update_work);
1701 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1702 struct kvm_vcpu *vcpu;
1703
1704 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1705 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1706 kvm_vcpu_kick(vcpu);
1707 }
1708}
1709
7e44e449
AJ		 1710static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1711{
1712 struct kvm *kvm = v->kvm;
1713
105b21bb 1714 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1715 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1716 KVMCLOCK_UPDATE_DELAY);
1717}
1718
332967a3
AJ		 1719#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1720
1721static void kvmclock_sync_fn(struct work_struct *work)
1722{
1723 struct delayed_work *dwork = to_delayed_work(work);
1724 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1725 kvmclock_sync_work);
1726 struct kvm *kvm = container_of(ka, struct kvm, arch);
1727
1728 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1729 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1730 KVMCLOCK_SYNC_PERIOD);
1731}
1732
9ba075a6
AK		 1733static bool msr_mtrr_valid(unsigned msr)
1734{
1735 switch (msr) {
1736 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1737 case MSR_MTRRfix64K_00000:
1738 case MSR_MTRRfix16K_80000:
1739 case MSR_MTRRfix16K_A0000:
1740 case MSR_MTRRfix4K_C0000:
1741 case MSR_MTRRfix4K_C8000:
1742 case MSR_MTRRfix4K_D0000:
1743 case MSR_MTRRfix4K_D8000:
1744 case MSR_MTRRfix4K_E0000:
1745 case MSR_MTRRfix4K_E8000:
1746 case MSR_MTRRfix4K_F0000:
1747 case MSR_MTRRfix4K_F8000:
1748 case MSR_MTRRdefType:
1749 case MSR_IA32_CR_PAT:
1750 return true;
1751 case 0x2f8:
1752 return true;
1753 }
1754 return false;
1755}
1756
d6289b93
MT		 1757static bool valid_pat_type(unsigned t)
1758{
1759 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1760}
1761
1762static bool valid_mtrr_type(unsigned t)
1763{
1764 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1765}
1766
4566654b 1767bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1768{
1769 int i;
fd275235 1770 u64 mask;
d6289b93
MT		 1771
1772 if (!msr_mtrr_valid(msr))
1773 return false;
1774
1775 if (msr == MSR_IA32_CR_PAT) {
1776 for (i = 0; i < 8; i++)
1777 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1778 return false;
1779 return true;
1780 } else if (msr == MSR_MTRRdefType) {
1781 if (data & ~0xcff)
1782 return false;
1783 return valid_mtrr_type(data & 0xff);
1784 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1785 for (i = 0; i < 8 ; i++)
1786 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1787 return false;
1788 return true;
1789 }
1790
1791 /* variable MTRRs */
adfb5d27
WL		 1792 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1793
fd275235 1794 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1795 if ((msr & 1) == 0) {
adfb5d27 1796 /* MTRR base */
d7a2a246
WL		 1797 if (!valid_mtrr_type(data & 0xff))
1798 return false;
1799 mask |= 0xf00;
1800 } else
1801 /* MTRR mask */
1802 mask |= 0x7ff;
1803 if (data & mask) {
1804 kvm_inject_gp(vcpu, 0);
1805 return false;
1806 }
1807
adfb5d27 1808 return true;
d6289b93 1809}
4566654b 1810EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1811
9ba075a6
AK		 1812static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1813{
0bed3b56
SY		 1814 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1815
4566654b 1816 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1817 return 1;
1818
0bed3b56
SY		 1819 if (msr == MSR_MTRRdefType) {
1820 vcpu->arch.mtrr_state.def_type = data;
1821 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1822 } else if (msr == MSR_MTRRfix64K_00000)
1823 p[0] = data;
1824 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1825 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1826 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1827 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1828 else if (msr == MSR_IA32_CR_PAT)
1829 vcpu->arch.pat = data;
1830 else { /* Variable MTRRs */
1831 int idx, is_mtrr_mask;
1832 u64 *pt;
1833
1834 idx = (msr - 0x200) / 2;
1835 is_mtrr_mask = msr - 0x200 - 2 * idx;
1836 if (!is_mtrr_mask)
1837 pt =
1838 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1839 else
1840 pt =
1841 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1842 *pt = data;
1843 }
1844
1845 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1846 return 0;
1847}
15c4a640 1848
890ca9ae 1849static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1850{
890ca9ae
HY		 1851 u64 mcg_cap = vcpu->arch.mcg_cap;
1852 unsigned bank_num = mcg_cap & 0xff;
1853
15c4a640 1854 switch (msr) {
15c4a640 1855 case MSR_IA32_MCG_STATUS:
890ca9ae 1856 vcpu->arch.mcg_status = data;
15c4a640 1857 break;
c7ac679c 1858 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1859 if (!(mcg_cap & MCG_CTL_P))
1860 return 1;
1861 if (data != 0 && data != ~(u64)0)
1862 return -1;
1863 vcpu->arch.mcg_ctl = data;
1864 break;
1865 default:
1866 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1867 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1868 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1869 /* only 0 or all 1s can be written to IA32_MCi_CTL
1870 * some Linux kernels though clear bit 10 in bank 4 to
1871 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1872 * this to avoid an uncatched #GP in the guest
1873 */
890ca9ae 1874 if ((offset & 0x3) == 0 &&
114be429 1875 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1876 return -1;
1877 vcpu->arch.mce_banks[offset] = data;
1878 break;
1879 }
1880 return 1;
1881 }
1882 return 0;
1883}
1884
ffde22ac
ES		 1885static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1886{
1887 struct kvm *kvm = vcpu->kvm;
1888 int lm = is_long_mode(vcpu);
1889 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1890 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1891 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1892 : kvm->arch.xen_hvm_config.blob_size_32;
1893 u32 page_num = data & ~PAGE_MASK;
1894 u64 page_addr = data & PAGE_MASK;
1895 u8 *page;
1896 int r;
1897
1898 r = -E2BIG;
1899 if (page_num >= blob_size)
1900 goto out;
1901 r = -ENOMEM;
ff5c2c03
SL		 1902 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1903 if (IS_ERR(page)) {
1904 r = PTR_ERR(page);
ffde22ac 1905 goto out;
ff5c2c03 1906 }
ffde22ac
ES		 1907 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1908 goto out_free;
1909 r = 0;
1910out_free:
1911 kfree(page);
1912out:
1913 return r;
1914}
1915
55cd8e5a
GN		 1916static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1917{
1918 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1919}
1920
1921static bool kvm_hv_msr_partition_wide(u32 msr)
1922{
1923 bool r = false;
1924 switch (msr) {
1925 case HV_X64_MSR_GUEST_OS_ID:
1926 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1927 case HV_X64_MSR_REFERENCE_TSC:
1928 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1929 r = true;
1930 break;
1931 }
1932
1933 return r;
1934}
1935
1936static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1937{
1938 struct kvm *kvm = vcpu->kvm;
1939
1940 switch (msr) {
1941 case HV_X64_MSR_GUEST_OS_ID:
1942 kvm->arch.hv_guest_os_id = data;
1943 /* setting guest os id to zero disables hypercall page */
1944 if (!kvm->arch.hv_guest_os_id)
1945 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1946 break;
1947 case HV_X64_MSR_HYPERCALL: {
1948 u64 gfn;
1949 unsigned long addr;
1950 u8 instructions[4];
1951
1952 /* if guest os id is not set hypercall should remain disabled */
1953 if (!kvm->arch.hv_guest_os_id)
1954 break;
1955 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1956 kvm->arch.hv_hypercall = data;
1957 break;
1958 }
1959 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1960 addr = gfn_to_hva(kvm, gfn);
1961 if (kvm_is_error_hva(addr))
1962 return 1;
1963 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1964 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1965 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1966 return 1;
1967 kvm->arch.hv_hypercall = data;
b94b64c9 1968 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1969 break;
1970 }
e984097b
VR		 1971 case HV_X64_MSR_REFERENCE_TSC: {
1972 u64 gfn;
1973 HV_REFERENCE_TSC_PAGE tsc_ref;
1974 memset(&tsc_ref, 0, sizeof(tsc_ref));
1975 kvm->arch.hv_tsc_page = data;
1976 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1977 break;
1978 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1979 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1980 &tsc_ref, sizeof(tsc_ref)))
1981 return 1;
1982 mark_page_dirty(kvm, gfn);
1983 break;
1984 }
55cd8e5a 1985 default:
a737f256
CD		 1986 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1987 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1988 return 1;
1989 }
1990 return 0;
1991}
1992
1993static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1994{
10388a07
GN		 1995 switch (msr) {
1996 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1997 u64 gfn;
10388a07 1998 unsigned long addr;
55cd8e5a 1999
10388a07
GN		 2000 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2001 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2002 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2003 return 1;
10388a07
GN		 2004 break;
2005 }
b3af1e88
VR		 2006 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2007 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2008 if (kvm_is_error_hva(addr))
2009 return 1;
8b0cedff 2010 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2011 return 1;
2012 vcpu->arch.hv_vapic = data;
b3af1e88 2013 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2014 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2015 return 1;
10388a07
GN		 2016 break;
2017 }
2018 case HV_X64_MSR_EOI:
2019 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2020 case HV_X64_MSR_ICR:
2021 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2022 case HV_X64_MSR_TPR:
2023 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2024 default:
a737f256
CD		 2025 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2026 "data 0x%llx\n", msr, data);
10388a07
GN		 2027 return 1;
2028 }
2029
2030 return 0;
55cd8e5a
GN		 2031}
2032
344d9588
GN		 2033static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2034{
2035 gpa_t gpa = data & ~0x3f;
2036
4a969980 2037 /* Bits 2:5 are reserved, Should be zero */
6adba527 2038 if (data & 0x3c)
344d9588
GN		 2039 return 1;
2040
2041 vcpu->arch.apf.msr_val = data;
2042
2043 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2044 kvm_clear_async_pf_completion_queue(vcpu);
2045 kvm_async_pf_hash_reset(vcpu);
2046 return 0;
2047 }
2048
8f964525
AH		 2049 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2050 sizeof(u32)))
344d9588
GN		 2051 return 1;
2052
6adba527 2053 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2054 kvm_async_pf_wakeup_all(vcpu);
2055 return 0;
2056}
2057
12f9a48f
GC		 2058static void kvmclock_reset(struct kvm_vcpu *vcpu)
2059{
0b79459b 2060 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2061}
2062
c9aaa895
GC		 2063static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2064{
2065 u64 delta;
2066
2067 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2068 return;
2069
2070 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2071 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2072 vcpu->arch.st.accum_steal = delta;
2073}
2074
2075static void record_steal_time(struct kvm_vcpu *vcpu)
2076{
2077 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2078 return;
2079
2080 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2081 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2082 return;
2083
2084 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2085 vcpu->arch.st.steal.version += 2;
2086 vcpu->arch.st.accum_steal = 0;
2087
2088 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2089 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2090}
2091
8fe8ab46 2092int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2093{
5753785f 2094 bool pr = false;
8fe8ab46
WA		 2095 u32 msr = msr_info->index;
2096 u64 data = msr_info->data;
5753785f 2097
15c4a640 2098 switch (msr) {
2e32b719
BP		 2099 case MSR_AMD64_NB_CFG:
2100 case MSR_IA32_UCODE_REV:
2101 case MSR_IA32_UCODE_WRITE:
2102 case MSR_VM_HSAVE_PA:
2103 case MSR_AMD64_PATCH_LOADER:
2104 case MSR_AMD64_BU_CFG2:
2105 break;
2106
15c4a640 2107 case MSR_EFER:
b69e8cae 2108 return set_efer(vcpu, data);
8f1589d9
AP		 2109 case MSR_K7_HWCR:
2110 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2111 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2112 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2113 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2114 if (data != 0) {
a737f256
CD		 2115 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2116 data);
8f1589d9
AP		 2117 return 1;
2118 }
15c4a640 2119 break;
f7c6d140
AP		 2120 case MSR_FAM10H_MMIO_CONF_BASE:
2121 if (data != 0) {
a737f256
CD		 2122 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2123 "0x%llx\n", data);
f7c6d140
AP		 2124 return 1;
2125 }
15c4a640 2126 break;
b5e2fec0
AG		 2127 case MSR_IA32_DEBUGCTLMSR:
2128 if (!data) {
2129 /* We support the non-activated case already */
2130 break;
2131 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2132 /* Values other than LBR and BTF are vendor-specific,
2133 thus reserved and should throw a #GP */
2134 return 1;
2135 }
a737f256
CD		 2136 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2137 __func__, data);
b5e2fec0 2138 break;
9ba075a6
AK		 2139 case 0x200 ... 0x2ff:
2140 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2141 case MSR_IA32_APICBASE:
58cb628d 2142 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2143 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2144 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2145 case MSR_IA32_TSCDEADLINE:
2146 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2147 break;
ba904635
WA		 2148 case MSR_IA32_TSC_ADJUST:
2149 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2150 if (!msr_info->host_initiated) {
d913b904 2151 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2152 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2153 }
2154 vcpu->arch.ia32_tsc_adjust_msr = data;
2155 }
2156 break;
15c4a640 2157 case MSR_IA32_MISC_ENABLE:
ad312c7c 2158 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2159 break;
11c6bffa 2160 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2161 case MSR_KVM_WALL_CLOCK:
2162 vcpu->kvm->arch.wall_clock = data;
2163 kvm_write_wall_clock(vcpu->kvm, data);
2164 break;
11c6bffa 2165 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2166 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2167 u64 gpa_offset;
12f9a48f 2168 kvmclock_reset(vcpu);
18068523
GOC		 2169
2170 vcpu->arch.time = data;
0061d53d 2171 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2172
2173 /* we verify if the enable bit is set... */
2174 if (!(data & 1))
2175 break;
2176
0b79459b 2177 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2178
0b79459b 2179 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2180 &vcpu->arch.pv_time, data & ~1ULL,
2181 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2182 vcpu->arch.pv_time_enabled = false;
2183 else
2184 vcpu->arch.pv_time_enabled = true;
32cad84f 2185
18068523
GOC		 2186 break;
2187 }
344d9588
GN		 2188 case MSR_KVM_ASYNC_PF_EN:
2189 if (kvm_pv_enable_async_pf(vcpu, data))
2190 return 1;
2191 break;
c9aaa895
GC		 2192 case MSR_KVM_STEAL_TIME:
2193
2194 if (unlikely(!sched_info_on()))
2195 return 1;
2196
2197 if (data & KVM_STEAL_RESERVED_MASK)
2198 return 1;
2199
2200 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2201 data & KVM_STEAL_VALID_BITS,
2202 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2203 return 1;
2204
2205 vcpu->arch.st.msr_val = data;
2206
2207 if (!(data & KVM_MSR_ENABLED))
2208 break;
2209
2210 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2211
2212 preempt_disable();
2213 accumulate_steal_time(vcpu);
2214 preempt_enable();
2215
2216 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2217
2218 break;
ae7a2a3f
MT		 2219 case MSR_KVM_PV_EOI_EN:
2220 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2221 return 1;
2222 break;
c9aaa895 2223
890ca9ae
HY		 2224 case MSR_IA32_MCG_CTL:
2225 case MSR_IA32_MCG_STATUS:
81760dcc 2226 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2227 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2228
2229 /* Performance counters are not protected by a CPUID bit,
2230 * so we should check all of them in the generic path for the sake of
2231 * cross vendor migration.
2232 * Writing a zero into the event select MSRs disables them,
2233 * which we perfectly emulate ;-). Any other value should be at least
2234 * reported, some guests depend on them.
2235 */
71db6023
AP		 2236 case MSR_K7_EVNTSEL0:
2237 case MSR_K7_EVNTSEL1:
2238 case MSR_K7_EVNTSEL2:
2239 case MSR_K7_EVNTSEL3:
2240 if (data != 0)
a737f256
CD		 2241 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2242 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2243 break;
2244 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2245 * so we ignore writes to make it happy.
2246 */
71db6023
AP		 2247 case MSR_K7_PERFCTR0:
2248 case MSR_K7_PERFCTR1:
2249 case MSR_K7_PERFCTR2:
2250 case MSR_K7_PERFCTR3:
a737f256
CD		 2251 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2252 "0x%x data 0x%llx\n", msr, data);
71db6023 2253 break;
5753785f
GN		 2254 case MSR_P6_PERFCTR0:
2255 case MSR_P6_PERFCTR1:
2256 pr = true;
2257 case MSR_P6_EVNTSEL0:
2258 case MSR_P6_EVNTSEL1:
2259 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2260 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2261
2262 if (pr || data != 0)
a737f256
CD		 2263 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2264 "0x%x data 0x%llx\n", msr, data);
5753785f 2265 break;
84e0cefa
JS		 2266 case MSR_K7_CLK_CTL:
2267 /*
2268 * Ignore all writes to this no longer documented MSR.
2269 * Writes are only relevant for old K7 processors,
2270 * all pre-dating SVM, but a recommended workaround from
4a969980 2271 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2272 * affected processor models on the command line, hence
2273 * the need to ignore the workaround.
2274 */
2275 break;
55cd8e5a
GN		 2276 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2277 if (kvm_hv_msr_partition_wide(msr)) {
2278 int r;
2279 mutex_lock(&vcpu->kvm->lock);
2280 r = set_msr_hyperv_pw(vcpu, msr, data);
2281 mutex_unlock(&vcpu->kvm->lock);
2282 return r;
2283 } else
2284 return set_msr_hyperv(vcpu, msr, data);
2285 break;
91c9c3ed 2286 case MSR_IA32_BBL_CR_CTL3:
2287 /* Drop writes to this legacy MSR -- see rdmsr
2288 * counterpart for further detail.
2289 */
a737f256 2290 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2291 break;
2b036c6b
BO		 2292 case MSR_AMD64_OSVW_ID_LENGTH:
2293 if (!guest_cpuid_has_osvw(vcpu))
2294 return 1;
2295 vcpu->arch.osvw.length = data;
2296 break;
2297 case MSR_AMD64_OSVW_STATUS:
2298 if (!guest_cpuid_has_osvw(vcpu))
2299 return 1;
2300 vcpu->arch.osvw.status = data;
2301 break;
15c4a640 2302 default:
ffde22ac
ES		 2303 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2304 return xen_hvm_config(vcpu, data);
f5132b01 2305 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2306 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2307 if (!ignore_msrs) {
a737f256
CD		 2308 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2309 msr, data);
ed85c068
AP		 2310 return 1;
2311 } else {
a737f256
CD		 2312 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2313 msr, data);
ed85c068
AP		 2314 break;
2315 }
15c4a640
CO		 2316 }
2317 return 0;
2318}
2319EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2320
2321
2322/*
2323 * Reads an msr value (of 'msr_index') into 'pdata'.
2324 * Returns 0 on success, non-0 otherwise.
2325 * Assumes vcpu_load() was already called.
2326 */
2327int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2328{
2329 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2330}
ff651cb6 2331EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2332
9ba075a6
AK		 2333static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2334{
0bed3b56
SY		 2335 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2336
9ba075a6
AK		 2337 if (!msr_mtrr_valid(msr))
2338 return 1;
2339
0bed3b56
SY		 2340 if (msr == MSR_MTRRdefType)
2341 *pdata = vcpu->arch.mtrr_state.def_type +
2342 (vcpu->arch.mtrr_state.enabled << 10);
2343 else if (msr == MSR_MTRRfix64K_00000)
2344 *pdata = p[0];
2345 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2346 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2347 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2348 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2349 else if (msr == MSR_IA32_CR_PAT)
2350 *pdata = vcpu->arch.pat;
2351 else { /* Variable MTRRs */
2352 int idx, is_mtrr_mask;
2353 u64 *pt;
2354
2355 idx = (msr - 0x200) / 2;
2356 is_mtrr_mask = msr - 0x200 - 2 * idx;
2357 if (!is_mtrr_mask)
2358 pt =
2359 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2360 else
2361 pt =
2362 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2363 *pdata = *pt;
2364 }
2365
9ba075a6
AK		 2366 return 0;
2367}
2368
890ca9ae 2369static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2370{
2371 u64 data;
890ca9ae
HY		 2372 u64 mcg_cap = vcpu->arch.mcg_cap;
2373 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2374
2375 switch (msr) {
15c4a640
CO		 2376 case MSR_IA32_P5_MC_ADDR:
2377 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2378 data = 0;
2379 break;
15c4a640 2380 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2381 data = vcpu->arch.mcg_cap;
2382 break;
c7ac679c 2383 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2384 if (!(mcg_cap & MCG_CTL_P))
2385 return 1;
2386 data = vcpu->arch.mcg_ctl;
2387 break;
2388 case MSR_IA32_MCG_STATUS:
2389 data = vcpu->arch.mcg_status;
2390 break;
2391 default:
2392 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2393 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2394 u32 offset = msr - MSR_IA32_MC0_CTL;
2395 data = vcpu->arch.mce_banks[offset];
2396 break;
2397 }
2398 return 1;
2399 }
2400 *pdata = data;
2401 return 0;
2402}
2403
55cd8e5a
GN		 2404static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2405{
2406 u64 data = 0;
2407 struct kvm *kvm = vcpu->kvm;
2408
2409 switch (msr) {
2410 case HV_X64_MSR_GUEST_OS_ID:
2411 data = kvm->arch.hv_guest_os_id;
2412 break;
2413 case HV_X64_MSR_HYPERCALL:
2414 data = kvm->arch.hv_hypercall;
2415 break;
e984097b
VR		 2416 case HV_X64_MSR_TIME_REF_COUNT: {
2417 data =
2418 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2419 break;
2420 }
2421 case HV_X64_MSR_REFERENCE_TSC:
2422 data = kvm->arch.hv_tsc_page;
2423 break;
55cd8e5a 2424 default:
a737f256 2425 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2426 return 1;
2427 }
2428
2429 *pdata = data;
2430 return 0;
2431}
2432
2433static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2434{
2435 u64 data = 0;
2436
2437 switch (msr) {
2438 case HV_X64_MSR_VP_INDEX: {
2439 int r;
2440 struct kvm_vcpu *v;
684851a1
TY		 2441 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2442 if (v == vcpu) {
55cd8e5a 2443 data = r;
684851a1
TY		 2444 break;
2445 }
2446 }
55cd8e5a
GN		 2447 break;
2448 }
10388a07
GN		 2449 case HV_X64_MSR_EOI:
2450 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2451 case HV_X64_MSR_ICR:
2452 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2453 case HV_X64_MSR_TPR:
2454 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2455 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2456 data = vcpu->arch.hv_vapic;
2457 break;
55cd8e5a 2458 default:
a737f256 2459 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2460 return 1;
2461 }
2462 *pdata = data;
2463 return 0;
2464}
2465
890ca9ae
HY		 2466int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2467{
2468 u64 data;
2469
2470 switch (msr) {
890ca9ae 2471 case MSR_IA32_PLATFORM_ID:
15c4a640 2472 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2473 case MSR_IA32_DEBUGCTLMSR:
2474 case MSR_IA32_LASTBRANCHFROMIP:
2475 case MSR_IA32_LASTBRANCHTOIP:
2476 case MSR_IA32_LASTINTFROMIP:
2477 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2478 case MSR_K8_SYSCFG:
2479 case MSR_K7_HWCR:
61a6bd67 2480 case MSR_VM_HSAVE_PA:
9e699624 2481 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2482 case MSR_K7_EVNTSEL1:
2483 case MSR_K7_EVNTSEL2:
2484 case MSR_K7_EVNTSEL3:
1f3ee616 2485 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2486 case MSR_K7_PERFCTR1:
2487 case MSR_K7_PERFCTR2:
2488 case MSR_K7_PERFCTR3:
1fdbd48c 2489 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2490 case MSR_AMD64_NB_CFG:
f7c6d140 2491 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2492 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2493 data = 0;
2494 break;
5753785f
GN		 2495 case MSR_P6_PERFCTR0:
2496 case MSR_P6_PERFCTR1:
2497 case MSR_P6_EVNTSEL0:
2498 case MSR_P6_EVNTSEL1:
2499 if (kvm_pmu_msr(vcpu, msr))
2500 return kvm_pmu_get_msr(vcpu, msr, pdata);
2501 data = 0;
2502 break;
742bc670
MT		 2503 case MSR_IA32_UCODE_REV:
2504 data = 0x100000000ULL;
2505 break;
9ba075a6
AK		 2506 case MSR_MTRRcap:
2507 data = 0x500 | KVM_NR_VAR_MTRR;
2508 break;
2509 case 0x200 ... 0x2ff:
2510 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2511 case 0xcd: /* fsb frequency */
2512 data = 3;
2513 break;
7b914098
JS		 2514 /*
2515 * MSR_EBC_FREQUENCY_ID
2516 * Conservative value valid for even the basic CPU models.
2517 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2518 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2519 * and 266MHz for model 3, or 4. Set Core Clock
2520 * Frequency to System Bus Frequency Ratio to 1 (bits
2521 * 31:24) even though these are only valid for CPU
2522 * models > 2, however guests may end up dividing or
2523 * multiplying by zero otherwise.
2524 */
2525 case MSR_EBC_FREQUENCY_ID:
2526 data = 1 << 24;
2527 break;
15c4a640
CO		 2528 case MSR_IA32_APICBASE:
2529 data = kvm_get_apic_base(vcpu);
2530 break;
0105d1a5
GN		 2531 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2532 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2533 break;
a3e06bbe
LJ		 2534 case MSR_IA32_TSCDEADLINE:
2535 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2536 break;
ba904635
WA		 2537 case MSR_IA32_TSC_ADJUST:
2538 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2539 break;
15c4a640 2540 case MSR_IA32_MISC_ENABLE:
ad312c7c 2541 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2542 break;
847f0ad8
AG		 2543 case MSR_IA32_PERF_STATUS:
2544 /* TSC increment by tick */
2545 data = 1000ULL;
2546 /* CPU multiplier */
2547 data |= (((uint64_t)4ULL) << 40);
2548 break;
15c4a640 2549 case MSR_EFER:
f6801dff 2550 data = vcpu->arch.efer;
15c4a640 2551 break;
18068523 2552 case MSR_KVM_WALL_CLOCK:
11c6bffa 2553 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2554 data = vcpu->kvm->arch.wall_clock;
2555 break;
2556 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2557 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2558 data = vcpu->arch.time;
2559 break;
344d9588
GN		 2560 case MSR_KVM_ASYNC_PF_EN:
2561 data = vcpu->arch.apf.msr_val;
2562 break;
c9aaa895
GC		 2563 case MSR_KVM_STEAL_TIME:
2564 data = vcpu->arch.st.msr_val;
2565 break;
1d92128f
MT		 2566 case MSR_KVM_PV_EOI_EN:
2567 data = vcpu->arch.pv_eoi.msr_val;
2568 break;
890ca9ae
HY		 2569 case MSR_IA32_P5_MC_ADDR:
2570 case MSR_IA32_P5_MC_TYPE:
2571 case MSR_IA32_MCG_CAP:
2572 case MSR_IA32_MCG_CTL:
2573 case MSR_IA32_MCG_STATUS:
81760dcc 2574 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2575 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2576 case MSR_K7_CLK_CTL:
2577 /*
2578 * Provide expected ramp-up count for K7. All other
2579 * are set to zero, indicating minimum divisors for
2580 * every field.
2581 *
2582 * This prevents guest kernels on AMD host with CPU
2583 * type 6, model 8 and higher from exploding due to
2584 * the rdmsr failing.
2585 */
2586 data = 0x20000000;
2587 break;
55cd8e5a
GN		 2588 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2589 if (kvm_hv_msr_partition_wide(msr)) {
2590 int r;
2591 mutex_lock(&vcpu->kvm->lock);
2592 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2593 mutex_unlock(&vcpu->kvm->lock);
2594 return r;
2595 } else
2596 return get_msr_hyperv(vcpu, msr, pdata);
2597 break;
91c9c3ed 2598 case MSR_IA32_BBL_CR_CTL3:
2599 /* This legacy MSR exists but isn't fully documented in current
2600 * silicon. It is however accessed by winxp in very narrow
2601 * scenarios where it sets bit #19, itself documented as
2602 * a "reserved" bit. Best effort attempt to source coherent
2603 * read data here should the balance of the register be
2604 * interpreted by the guest:
2605 *
2606 * L2 cache control register 3: 64GB range, 256KB size,
2607 * enabled, latency 0x1, configured
2608 */
2609 data = 0xbe702111;
2610 break;
2b036c6b
BO		 2611 case MSR_AMD64_OSVW_ID_LENGTH:
2612 if (!guest_cpuid_has_osvw(vcpu))
2613 return 1;
2614 data = vcpu->arch.osvw.length;
2615 break;
2616 case MSR_AMD64_OSVW_STATUS:
2617 if (!guest_cpuid_has_osvw(vcpu))
2618 return 1;
2619 data = vcpu->arch.osvw.status;
2620 break;
15c4a640 2621 default:
f5132b01
GN		 2622 if (kvm_pmu_msr(vcpu, msr))
2623 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2624 if (!ignore_msrs) {
a737f256 2625 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2626 return 1;
2627 } else {
a737f256 2628 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2629 data = 0;
2630 }
2631 break;
15c4a640
CO		 2632 }
2633 *pdata = data;
2634 return 0;
2635}
2636EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2637
313a3dc7
CO		 2638/*
2639 * Read or write a bunch of msrs. All parameters are kernel addresses.
2640 *
2641 * @return number of msrs set successfully.
2642 */
2643static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2644 struct kvm_msr_entry *entries,
2645 int (*do_msr)(struct kvm_vcpu *vcpu,
2646 unsigned index, u64 *data))
2647{
f656ce01 2648 int i, idx;
313a3dc7 2649
f656ce01 2650 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2651 for (i = 0; i < msrs->nmsrs; ++i)
2652 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2653 break;
f656ce01 2654 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2655
313a3dc7
CO		 2656 return i;
2657}
2658
2659/*
2660 * Read or write a bunch of msrs. Parameters are user addresses.
2661 *
2662 * @return number of msrs set successfully.
2663 */
2664static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2665 int (*do_msr)(struct kvm_vcpu *vcpu,
2666 unsigned index, u64 *data),
2667 int writeback)
2668{
2669 struct kvm_msrs msrs;
2670 struct kvm_msr_entry *entries;
2671 int r, n;
2672 unsigned size;
2673
2674 r = -EFAULT;
2675 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2676 goto out;
2677
2678 r = -E2BIG;
2679 if (msrs.nmsrs >= MAX_IO_MSRS)
2680 goto out;
2681
313a3dc7 2682 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2683 entries = memdup_user(user_msrs->entries, size);
2684 if (IS_ERR(entries)) {
2685 r = PTR_ERR(entries);
313a3dc7 2686 goto out;
ff5c2c03 2687 }
313a3dc7
CO		 2688
2689 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2690 if (r < 0)
2691 goto out_free;
2692
2693 r = -EFAULT;
2694 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2695 goto out_free;
2696
2697 r = n;
2698
2699out_free:
7a73c028 2700 kfree(entries);
313a3dc7
CO		 2701out:
2702 return r;
2703}
2704
784aa3d7 2705int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2706{
2707 int r;
2708
2709 switch (ext) {
2710 case KVM_CAP_IRQCHIP:
2711 case KVM_CAP_HLT:
2712 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2713 case KVM_CAP_SET_TSS_ADDR:
07716717 2714 case KVM_CAP_EXT_CPUID:
9c15bb1d 2715 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2716 case KVM_CAP_CLOCKSOURCE:
7837699f 2717 case KVM_CAP_PIT:
a28e4f5a 2718 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2719 case KVM_CAP_MP_STATE:
ed848624 2720 case KVM_CAP_SYNC_MMU:
a355c85c 2721 case KVM_CAP_USER_NMI:
52d939a0 2722 case KVM_CAP_REINJECT_CONTROL:
4925663a 2723 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2724 case KVM_CAP_IRQFD:
d34e6b17 2725 case KVM_CAP_IOEVENTFD:
f848a5a8 2726 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2727 case KVM_CAP_PIT2:
e9f42757 2728 case KVM_CAP_PIT_STATE2:
b927a3ce 2729 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2730 case KVM_CAP_XEN_HVM:
afbcf7ab 2731 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2732 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2733 case KVM_CAP_HYPERV:
10388a07 2734 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2735 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2736 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2737 case KVM_CAP_DEBUGREGS:
d2be1651 2738 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2739 case KVM_CAP_XSAVE:
344d9588 2740 case KVM_CAP_ASYNC_PF:
92a1f12d 2741 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2742 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2743 case KVM_CAP_READONLY_MEM:
5f66b620 2744 case KVM_CAP_HYPERV_TIME:
100943c5 2745 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2746#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2747 case KVM_CAP_ASSIGN_DEV_IRQ:
2748 case KVM_CAP_PCI_2_3:
2749#endif
018d00d2
ZX		 2750 r = 1;
2751 break;
542472b5
LV		 2752 case KVM_CAP_COALESCED_MMIO:
2753 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2754 break;
774ead3a
AK		 2755 case KVM_CAP_VAPIC:
2756 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2757 break;
f725230a 2758 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2759 r = KVM_SOFT_MAX_VCPUS;
2760 break;
2761 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2762 r = KVM_MAX_VCPUS;
2763 break;
a988b910 2764 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2765 r = KVM_USER_MEM_SLOTS;
a988b910 2766 break;
a68a6a72
MT		 2767 case KVM_CAP_PV_MMU: /* obsolete */
2768 r = 0;
2f333bcb 2769 break;
4cee4b72 2770#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2771 case KVM_CAP_IOMMU:
a1b60c1c 2772 r = iommu_present(&pci_bus_type);
62c476c7 2773 break;
4cee4b72 2774#endif
890ca9ae
HY		 2775 case KVM_CAP_MCE:
2776 r = KVM_MAX_MCE_BANKS;
2777 break;
2d5b5a66
SY		 2778 case KVM_CAP_XCRS:
2779 r = cpu_has_xsave;
2780 break;
92a1f12d
JR		 2781 case KVM_CAP_TSC_CONTROL:
2782 r = kvm_has_tsc_control;
2783 break;
4d25a066
JK		 2784 case KVM_CAP_TSC_DEADLINE_TIMER:
2785 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2786 break;
018d00d2
ZX		 2787 default:
2788 r = 0;
2789 break;
2790 }
2791 return r;
2792
2793}
2794
043405e1
CO		 2795long kvm_arch_dev_ioctl(struct file *filp,
2796 unsigned int ioctl, unsigned long arg)
2797{
2798 void __user *argp = (void __user *)arg;
2799 long r;
2800
2801 switch (ioctl) {
2802 case KVM_GET_MSR_INDEX_LIST: {
2803 struct kvm_msr_list __user *user_msr_list = argp;
2804 struct kvm_msr_list msr_list;
2805 unsigned n;
2806
2807 r = -EFAULT;
2808 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2809 goto out;
2810 n = msr_list.nmsrs;
2811 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2812 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2813 goto out;
2814 r = -E2BIG;
e125e7b6 2815 if (n < msr_list.nmsrs)
043405e1
CO		 2816 goto out;
2817 r = -EFAULT;
2818 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2819 num_msrs_to_save * sizeof(u32)))
2820 goto out;
e125e7b6 2821 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2822 &emulated_msrs,
2823 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2824 goto out;
2825 r = 0;
2826 break;
2827 }
9c15bb1d
BP		 2828 case KVM_GET_SUPPORTED_CPUID:
2829 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2830 struct kvm_cpuid2 __user *cpuid_arg = argp;
2831 struct kvm_cpuid2 cpuid;
2832
2833 r = -EFAULT;
2834 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2835 goto out;
9c15bb1d
BP		 2836
2837 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2838 ioctl);
674eea0f
AK		 2839 if (r)
2840 goto out;
2841
2842 r = -EFAULT;
2843 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2844 goto out;
2845 r = 0;
2846 break;
2847 }
890ca9ae
HY		 2848 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2849 u64 mce_cap;
2850
2851 mce_cap = KVM_MCE_CAP_SUPPORTED;
2852 r = -EFAULT;
2853 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2854 goto out;
2855 r = 0;
2856 break;
2857 }
043405e1
CO		 2858 default:
2859 r = -EINVAL;
2860 }
2861out:
2862 return r;
2863}
2864
f5f48ee1
SY		 2865static void wbinvd_ipi(void *garbage)
2866{
2867 wbinvd();
2868}
2869
2870static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2871{
e0f0bbc5 2872 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2873}
2874
313a3dc7
CO		 2875void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2876{
f5f48ee1
SY		 2877 /* Address WBINVD may be executed by guest */
2878 if (need_emulate_wbinvd(vcpu)) {
2879 if (kvm_x86_ops->has_wbinvd_exit())
2880 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2881 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2882 smp_call_function_single(vcpu->cpu,
2883 wbinvd_ipi, NULL, 1);
2884 }
2885
313a3dc7 2886 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2887
0dd6a6ed
ZA		 2888 /* Apply any externally detected TSC adjustments (due to suspend) */
2889 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2890 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2891 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2892 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2893 }
8f6055cb 2894
48434c20 2895 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2896 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2897 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2898 if (tsc_delta < 0)
2899 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2900 if (check_tsc_unstable()) {
b183aa58
ZA		 2901 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2902 vcpu->arch.last_guest_tsc);
2903 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2904 vcpu->arch.tsc_catchup = 1;
c285545f 2905 }
d98d07ca
MT		 2906 /*
2907 * On a host with synchronized TSC, there is no need to update
2908 * kvmclock on vcpu->cpu migration
2909 */
2910 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2911 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2912 if (vcpu->cpu != cpu)
2913 kvm_migrate_timers(vcpu);
e48672fa 2914 vcpu->cpu = cpu;
6b7d7e76 2915 }
c9aaa895
GC		 2916
2917 accumulate_steal_time(vcpu);
2918 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2919}
2920
2921void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2922{
02daab21 2923 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2924 kvm_put_guest_fpu(vcpu);
6f526ec5 2925 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2926}
2927
313a3dc7
CO		 2928static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2929 struct kvm_lapic_state *s)
2930{
5a71785d 2931 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2932 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2933
2934 return 0;
2935}
2936
2937static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2938 struct kvm_lapic_state *s)
2939{
64eb0620 2940 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2941 update_cr8_intercept(vcpu);
313a3dc7
CO		 2942
2943 return 0;
2944}
2945
f77bc6a4
ZX		 2946static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2947 struct kvm_interrupt *irq)
2948{
02cdb50f 2949 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2950 return -EINVAL;
2951 if (irqchip_in_kernel(vcpu->kvm))
2952 return -ENXIO;
f77bc6a4 2953
66fd3f7f 2954 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2955 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2956
f77bc6a4
ZX		 2957 return 0;
2958}
2959
c4abb7c9
JK		 2960static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2961{
c4abb7c9 2962 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2963
2964 return 0;
2965}
2966
b209749f
AK		 2967static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2968 struct kvm_tpr_access_ctl *tac)
2969{
2970 if (tac->flags)
2971 return -EINVAL;
2972 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2973 return 0;
2974}
2975
890ca9ae
HY		 2976static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2977 u64 mcg_cap)
2978{
2979 int r;
2980 unsigned bank_num = mcg_cap & 0xff, bank;
2981
2982 r = -EINVAL;
a9e38c3e 2983 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2984 goto out;
2985 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2986 goto out;
2987 r = 0;
2988 vcpu->arch.mcg_cap = mcg_cap;
2989 /* Init IA32_MCG_CTL to all 1s */
2990 if (mcg_cap & MCG_CTL_P)
2991 vcpu->arch.mcg_ctl = ~(u64)0;
2992 /* Init IA32_MCi_CTL to all 1s */
2993 for (bank = 0; bank < bank_num; bank++)
2994 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2995out:
2996 return r;
2997}
2998
2999static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3000 struct kvm_x86_mce *mce)
3001{
3002 u64 mcg_cap = vcpu->arch.mcg_cap;
3003 unsigned bank_num = mcg_cap & 0xff;
3004 u64 *banks = vcpu->arch.mce_banks;
3005
3006 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3007 return -EINVAL;
3008 /*
3009 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3010 * reporting is disabled
3011 */
3012 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3013 vcpu->arch.mcg_ctl != ~(u64)0)
3014 return 0;
3015 banks += 4 * mce->bank;
3016 /*
3017 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3018 * reporting is disabled for the bank
3019 */
3020 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3021 return 0;
3022 if (mce->status & MCI_STATUS_UC) {
3023 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3024 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3025 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3026 return 0;
3027 }
3028 if (banks[1] & MCI_STATUS_VAL)
3029 mce->status |= MCI_STATUS_OVER;
3030 banks[2] = mce->addr;
3031 banks[3] = mce->misc;
3032 vcpu->arch.mcg_status = mce->mcg_status;
3033 banks[1] = mce->status;
3034 kvm_queue_exception(vcpu, MC_VECTOR);
3035 } else if (!(banks[1] & MCI_STATUS_VAL)
3036 || !(banks[1] & MCI_STATUS_UC)) {
3037 if (banks[1] & MCI_STATUS_VAL)
3038 mce->status |= MCI_STATUS_OVER;
3039 banks[2] = mce->addr;
3040 banks[3] = mce->misc;
3041 banks[1] = mce->status;
3042 } else
3043 banks[1] |= MCI_STATUS_OVER;
3044 return 0;
3045}
3046
3cfc3092
JK		 3047static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3048 struct kvm_vcpu_events *events)
3049{
7460fb4a 3050 process_nmi(vcpu);
03b82a30
JK		 3051 events->exception.injected =
3052 vcpu->arch.exception.pending &&
3053 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3054 events->exception.nr = vcpu->arch.exception.nr;
3055 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3056 events->exception.pad = 0;
3cfc3092
JK		 3057 events->exception.error_code = vcpu->arch.exception.error_code;
3058
03b82a30
JK		 3059 events->interrupt.injected =
3060 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3061 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3062 events->interrupt.soft = 0;
37ccdcbe 3063 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3064
3065 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3066 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3067 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3068 events->nmi.pad = 0;
3cfc3092 3069
66450a21 3070 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3071
dab4b911 3072 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3073 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3074 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3075}
3076
3077static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3078 struct kvm_vcpu_events *events)
3079{
dab4b911 3080 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3081 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3082 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3083 return -EINVAL;
3084
7460fb4a 3085 process_nmi(vcpu);
3cfc3092
JK		 3086 vcpu->arch.exception.pending = events->exception.injected;
3087 vcpu->arch.exception.nr = events->exception.nr;
3088 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3089 vcpu->arch.exception.error_code = events->exception.error_code;
3090
3091 vcpu->arch.interrupt.pending = events->interrupt.injected;
3092 vcpu->arch.interrupt.nr = events->interrupt.nr;
3093 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3094 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3095 kvm_x86_ops->set_interrupt_shadow(vcpu,
3096 events->interrupt.shadow);
3cfc3092
JK		 3097
3098 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3099 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3100 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3101 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3102
66450a21
JK		 3103 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3104 kvm_vcpu_has_lapic(vcpu))
3105 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3106
3842d135
AK		 3107 kvm_make_request(KVM_REQ_EVENT, vcpu);
3108
3cfc3092
JK		 3109 return 0;
3110}
3111
a1efbe77
JK		 3112static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3113 struct kvm_debugregs *dbgregs)
3114{
73aaf249
JK		 3115 unsigned long val;
3116
a1efbe77 3117 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3118 kvm_get_dr(vcpu, 6, &val);
73aaf249 3119 dbgregs->dr6 = val;
a1efbe77
JK		 3120 dbgregs->dr7 = vcpu->arch.dr7;
3121 dbgregs->flags = 0;
97e69aa6 3122 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3123}
3124
3125static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3126 struct kvm_debugregs *dbgregs)
3127{
3128 if (dbgregs->flags)
3129 return -EINVAL;
3130
a1efbe77
JK		 3131 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3132 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3133 kvm_update_dr6(vcpu);
a1efbe77 3134 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3135 kvm_update_dr7(vcpu);
a1efbe77 3136
a1efbe77
JK		 3137 return 0;
3138}
3139
df1daba7
PB		 3140#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3141
3142static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3143{
3144 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3145 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3146 u64 valid;
3147
3148 /*
3149 * Copy legacy XSAVE area, to avoid complications with CPUID
3150 * leaves 0 and 1 in the loop below.
3151 */
3152 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3153
3154 /* Set XSTATE_BV */
3155 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3156
3157 /*
3158 * Copy each region from the possibly compacted offset to the
3159 * non-compacted offset.
3160 */
3161 valid = xstate_bv & ~XSTATE_FPSSE;
3162 while (valid) {
3163 u64 feature = valid & -valid;
3164 int index = fls64(feature) - 1;
3165 void *src = get_xsave_addr(xsave, feature);
3166
3167 if (src) {
3168 u32 size, offset, ecx, edx;
3169 cpuid_count(XSTATE_CPUID, index,
3170 &size, &offset, &ecx, &edx);
3171 memcpy(dest + offset, src, size);
3172 }
3173
3174 valid -= feature;
3175 }
3176}
3177
3178static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3179{
3180 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3181 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3182 u64 valid;
3183
3184 /*
3185 * Copy legacy XSAVE area, to avoid complications with CPUID
3186 * leaves 0 and 1 in the loop below.
3187 */
3188 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3189
3190 /* Set XSTATE_BV and possibly XCOMP_BV. */
3191 xsave->xsave_hdr.xstate_bv = xstate_bv;
3192 if (cpu_has_xsaves)
3193 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3194
3195 /*
3196 * Copy each region from the non-compacted offset to the
3197 * possibly compacted offset.
3198 */
3199 valid = xstate_bv & ~XSTATE_FPSSE;
3200 while (valid) {
3201 u64 feature = valid & -valid;
3202 int index = fls64(feature) - 1;
3203 void *dest = get_xsave_addr(xsave, feature);
3204
3205 if (dest) {
3206 u32 size, offset, ecx, edx;
3207 cpuid_count(XSTATE_CPUID, index,
3208 &size, &offset, &ecx, &edx);
3209 memcpy(dest, src + offset, size);
3210 } else
3211 WARN_ON_ONCE(1);
3212
3213 valid -= feature;
3214 }
3215}
3216
2d5b5a66
SY		 3217static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3218 struct kvm_xsave *guest_xsave)
3219{
4344ee98 3220 if (cpu_has_xsave) {
df1daba7
PB		 3221 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3222 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3223 } else {
2d5b5a66
SY		 3224 memcpy(guest_xsave->region,
3225 &vcpu->arch.guest_fpu.state->fxsave,
3226 sizeof(struct i387_fxsave_struct));
3227 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3228 XSTATE_FPSSE;
3229 }
3230}
3231
3232static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3233 struct kvm_xsave *guest_xsave)
3234{
3235 u64 xstate_bv =
3236 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3237
d7876f1b
PB		 3238 if (cpu_has_xsave) {
3239 /*
3240 * Here we allow setting states that are not present in
3241 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3242 * with old userspace.
3243 */
4ff41732 3244 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3245 return -EINVAL;
df1daba7 3246 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3247 } else {
2d5b5a66
SY		 3248 if (xstate_bv & ~XSTATE_FPSSE)
3249 return -EINVAL;
3250 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3251 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3252 }
3253 return 0;
3254}
3255
3256static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3257 struct kvm_xcrs *guest_xcrs)
3258{
3259 if (!cpu_has_xsave) {
3260 guest_xcrs->nr_xcrs = 0;
3261 return;
3262 }
3263
3264 guest_xcrs->nr_xcrs = 1;
3265 guest_xcrs->flags = 0;
3266 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3267 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3268}
3269
3270static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3271 struct kvm_xcrs *guest_xcrs)
3272{
3273 int i, r = 0;
3274
3275 if (!cpu_has_xsave)
3276 return -EINVAL;
3277
3278 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3279 return -EINVAL;
3280
3281 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3282 /* Only support XCR0 currently */
c67a04cb 3283 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3284 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3285 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3286 break;
3287 }
3288 if (r)
3289 r = -EINVAL;
3290 return r;
3291}
3292
1c0b28c2
EM		 3293/*
3294 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3295 * stopped by the hypervisor. This function will be called from the host only.
3296 * EINVAL is returned when the host attempts to set the flag for a guest that
3297 * does not support pv clocks.
3298 */
3299static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3300{
0b79459b 3301 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3302 return -EINVAL;
51d59c6b 3303 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3304 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3305 return 0;
3306}
3307
313a3dc7
CO		 3308long kvm_arch_vcpu_ioctl(struct file *filp,
3309 unsigned int ioctl, unsigned long arg)
3310{
3311 struct kvm_vcpu *vcpu = filp->private_data;
3312 void __user *argp = (void __user *)arg;
3313 int r;
d1ac91d8
AK		 3314 union {
3315 struct kvm_lapic_state *lapic;
3316 struct kvm_xsave *xsave;
3317 struct kvm_xcrs *xcrs;
3318 void *buffer;
3319 } u;
3320
3321 u.buffer = NULL;
313a3dc7
CO		 3322 switch (ioctl) {
3323 case KVM_GET_LAPIC: {
2204ae3c
MT		 3324 r = -EINVAL;
3325 if (!vcpu->arch.apic)
3326 goto out;
d1ac91d8 3327 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3328
b772ff36 3329 r = -ENOMEM;
d1ac91d8 3330 if (!u.lapic)
b772ff36 3331 goto out;
d1ac91d8 3332 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3333 if (r)
3334 goto out;
3335 r = -EFAULT;
d1ac91d8 3336 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3337 goto out;
3338 r = 0;
3339 break;
3340 }
3341 case KVM_SET_LAPIC: {
2204ae3c
MT		 3342 r = -EINVAL;
3343 if (!vcpu->arch.apic)
3344 goto out;
ff5c2c03 3345 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3346 if (IS_ERR(u.lapic))
3347 return PTR_ERR(u.lapic);
ff5c2c03 3348
d1ac91d8 3349 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3350 break;
3351 }
f77bc6a4
ZX		 3352 case KVM_INTERRUPT: {
3353 struct kvm_interrupt irq;
3354
3355 r = -EFAULT;
3356 if (copy_from_user(&irq, argp, sizeof irq))
3357 goto out;
3358 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3359 break;
3360 }
c4abb7c9
JK		 3361 case KVM_NMI: {
3362 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3363 break;
3364 }
313a3dc7
CO		 3365 case KVM_SET_CPUID: {
3366 struct kvm_cpuid __user *cpuid_arg = argp;
3367 struct kvm_cpuid cpuid;
3368
3369 r = -EFAULT;
3370 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3371 goto out;
3372 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3373 break;
3374 }
07716717
DK		 3375 case KVM_SET_CPUID2: {
3376 struct kvm_cpuid2 __user *cpuid_arg = argp;
3377 struct kvm_cpuid2 cpuid;
3378
3379 r = -EFAULT;
3380 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3381 goto out;
3382 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3383 cpuid_arg->entries);
07716717
DK		 3384 break;
3385 }
3386 case KVM_GET_CPUID2: {
3387 struct kvm_cpuid2 __user *cpuid_arg = argp;
3388 struct kvm_cpuid2 cpuid;
3389
3390 r = -EFAULT;
3391 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3392 goto out;
3393 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3394 cpuid_arg->entries);
07716717
DK		 3395 if (r)
3396 goto out;
3397 r = -EFAULT;
3398 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3399 goto out;
3400 r = 0;
3401 break;
3402 }
313a3dc7
CO		 3403 case KVM_GET_MSRS:
3404 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3405 break;
3406 case KVM_SET_MSRS:
3407 r = msr_io(vcpu, argp, do_set_msr, 0);
3408 break;
b209749f
AK		 3409 case KVM_TPR_ACCESS_REPORTING: {
3410 struct kvm_tpr_access_ctl tac;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&tac, argp, sizeof tac))
3414 goto out;
3415 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3416 if (r)
3417 goto out;
3418 r = -EFAULT;
3419 if (copy_to_user(argp, &tac, sizeof tac))
3420 goto out;
3421 r = 0;
3422 break;
3423 };
b93463aa
AK		 3424 case KVM_SET_VAPIC_ADDR: {
3425 struct kvm_vapic_addr va;
3426
3427 r = -EINVAL;
3428 if (!irqchip_in_kernel(vcpu->kvm))
3429 goto out;
3430 r = -EFAULT;
3431 if (copy_from_user(&va, argp, sizeof va))
3432 goto out;
fda4e2e8 3433 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3434 break;
3435 }
890ca9ae
HY		 3436 case KVM_X86_SETUP_MCE: {
3437 u64 mcg_cap;
3438
3439 r = -EFAULT;
3440 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3441 goto out;
3442 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3443 break;
3444 }
3445 case KVM_X86_SET_MCE: {
3446 struct kvm_x86_mce mce;
3447
3448 r = -EFAULT;
3449 if (copy_from_user(&mce, argp, sizeof mce))
3450 goto out;
3451 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3452 break;
3453 }
3cfc3092
JK		 3454 case KVM_GET_VCPU_EVENTS: {
3455 struct kvm_vcpu_events events;
3456
3457 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3458
3459 r = -EFAULT;
3460 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3461 break;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_SET_VCPU_EVENTS: {
3466 struct kvm_vcpu_events events;
3467
3468 r = -EFAULT;
3469 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3470 break;
3471
3472 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3473 break;
3474 }
a1efbe77
JK		 3475 case KVM_GET_DEBUGREGS: {
3476 struct kvm_debugregs dbgregs;
3477
3478 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3479
3480 r = -EFAULT;
3481 if (copy_to_user(argp, &dbgregs,
3482 sizeof(struct kvm_debugregs)))
3483 break;
3484 r = 0;
3485 break;
3486 }
3487 case KVM_SET_DEBUGREGS: {
3488 struct kvm_debugregs dbgregs;
3489
3490 r = -EFAULT;
3491 if (copy_from_user(&dbgregs, argp,
3492 sizeof(struct kvm_debugregs)))
3493 break;
3494
3495 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3496 break;
3497 }
2d5b5a66 3498 case KVM_GET_XSAVE: {
d1ac91d8 3499 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3500 r = -ENOMEM;
d1ac91d8 3501 if (!u.xsave)
2d5b5a66
SY		 3502 break;
3503
d1ac91d8 3504 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3505
3506 r = -EFAULT;
d1ac91d8 3507 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3508 break;
3509 r = 0;
3510 break;
3511 }
3512 case KVM_SET_XSAVE: {
ff5c2c03 3513 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3514 if (IS_ERR(u.xsave))
3515 return PTR_ERR(u.xsave);
2d5b5a66 3516
d1ac91d8 3517 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3518 break;
3519 }
3520 case KVM_GET_XCRS: {
d1ac91d8 3521 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3522 r = -ENOMEM;
d1ac91d8 3523 if (!u.xcrs)
2d5b5a66
SY		 3524 break;
3525
d1ac91d8 3526 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3527
3528 r = -EFAULT;
d1ac91d8 3529 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3530 sizeof(struct kvm_xcrs)))
3531 break;
3532 r = 0;
3533 break;
3534 }
3535 case KVM_SET_XCRS: {
ff5c2c03 3536 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3537 if (IS_ERR(u.xcrs))
3538 return PTR_ERR(u.xcrs);
2d5b5a66 3539
d1ac91d8 3540 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3541 break;
3542 }
92a1f12d
JR		 3543 case KVM_SET_TSC_KHZ: {
3544 u32 user_tsc_khz;
3545
3546 r = -EINVAL;
92a1f12d
JR		 3547 user_tsc_khz = (u32)arg;
3548
3549 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3550 goto out;
3551
cc578287
ZA		 3552 if (user_tsc_khz == 0)
3553 user_tsc_khz = tsc_khz;
3554
3555 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3556
3557 r = 0;
3558 goto out;
3559 }
3560 case KVM_GET_TSC_KHZ: {
cc578287 3561 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3562 goto out;
3563 }
1c0b28c2
EM		 3564 case KVM_KVMCLOCK_CTRL: {
3565 r = kvm_set_guest_paused(vcpu);
3566 goto out;
3567 }
313a3dc7
CO		 3568 default:
3569 r = -EINVAL;
3570 }
3571out:
d1ac91d8 3572 kfree(u.buffer);
313a3dc7
CO		 3573 return r;
3574}
3575
5b1c1493
CO		 3576int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3577{
3578 return VM_FAULT_SIGBUS;
3579}
3580
1fe779f8
CO		 3581static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3582{
3583 int ret;
3584
3585 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3586 return -EINVAL;
1fe779f8
CO		 3587 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3588 return ret;
3589}
3590
b927a3ce
SY		 3591static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3592 u64 ident_addr)
3593{
3594 kvm->arch.ept_identity_map_addr = ident_addr;
3595 return 0;
3596}
3597
1fe779f8
CO		 3598static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3599 u32 kvm_nr_mmu_pages)
3600{
3601 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3602 return -EINVAL;
3603
79fac95e 3604 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3605
3606 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3607 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3608
79fac95e 3609 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3610 return 0;
3611}
3612
3613static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3614{
39de71ec 3615 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3616}
3617
1fe779f8
CO		 3618static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3619{
3620 int r;
3621
3622 r = 0;
3623 switch (chip->chip_id) {
3624 case KVM_IRQCHIP_PIC_MASTER:
3625 memcpy(&chip->chip.pic,
3626 &pic_irqchip(kvm)->pics[0],
3627 sizeof(struct kvm_pic_state));
3628 break;
3629 case KVM_IRQCHIP_PIC_SLAVE:
3630 memcpy(&chip->chip.pic,
3631 &pic_irqchip(kvm)->pics[1],
3632 sizeof(struct kvm_pic_state));
3633 break;
3634 case KVM_IRQCHIP_IOAPIC:
eba0226b 3635 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3636 break;
3637 default:
3638 r = -EINVAL;
3639 break;
3640 }
3641 return r;
3642}
3643
3644static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3645{
3646 int r;
3647
3648 r = 0;
3649 switch (chip->chip_id) {
3650 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3651 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3652 memcpy(&pic_irqchip(kvm)->pics[0],
3653 &chip->chip.pic,
3654 sizeof(struct kvm_pic_state));
f4f51050 3655 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3656 break;
3657 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3658 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3659 memcpy(&pic_irqchip(kvm)->pics[1],
3660 &chip->chip.pic,
3661 sizeof(struct kvm_pic_state));
f4f51050 3662 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3663 break;
3664 case KVM_IRQCHIP_IOAPIC:
eba0226b 3665 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3666 break;
3667 default:
3668 r = -EINVAL;
3669 break;
3670 }
3671 kvm_pic_update_irq(pic_irqchip(kvm));
3672 return r;
3673}
3674
e0f63cb9
SY		 3675static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3676{
3677 int r = 0;
3678
894a9c55 3679 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3680 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3681 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3682 return r;
3683}
3684
3685static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3686{
3687 int r = 0;
3688
894a9c55 3689 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3690 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3691 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3692 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3693 return r;
3694}
3695
3696static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3697{
3698 int r = 0;
3699
3700 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3701 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3702 sizeof(ps->channels));
3703 ps->flags = kvm->arch.vpit->pit_state.flags;
3704 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3705 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3706 return r;
3707}
3708
3709static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3710{
3711 int r = 0, start = 0;
3712 u32 prev_legacy, cur_legacy;
3713 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3714 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3715 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3716 if (!prev_legacy && cur_legacy)
3717 start = 1;
3718 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3719 sizeof(kvm->arch.vpit->pit_state.channels));
3720 kvm->arch.vpit->pit_state.flags = ps->flags;
3721 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3722 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3723 return r;
3724}
3725
52d939a0
MT		 3726static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3727 struct kvm_reinject_control *control)
3728{
3729 if (!kvm->arch.vpit)
3730 return -ENXIO;
894a9c55 3731 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3732 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3733 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3734 return 0;
3735}
3736
95d4c16c 3737/**
60c34612
TY		 3738 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3739 * @kvm: kvm instance
3740 * @log: slot id and address to which we copy the log
95d4c16c 3741 *
60c34612
TY		 3742 * We need to keep it in mind that VCPU threads can write to the bitmap
3743 * concurrently. So, to avoid losing data, we keep the following order for
3744 * each bit:
95d4c16c 3745 *
60c34612
TY		 3746 * 1. Take a snapshot of the bit and clear it if needed.
3747 * 2. Write protect the corresponding page.
3748 * 3. Flush TLB's if needed.
3749 * 4. Copy the snapshot to the userspace.
95d4c16c 3750 *
60c34612
TY		 3751 * Between 2 and 3, the guest may write to the page using the remaining TLB
3752 * entry. This is not a problem because the page will be reported dirty at
3753 * step 4 using the snapshot taken before and step 3 ensures that successive
3754 * writes will be logged for the next call.
5bb064dc 3755 */
60c34612 3756int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3757{
7850ac54 3758 int r;
5bb064dc 3759 struct kvm_memory_slot *memslot;
60c34612
TY		 3760 unsigned long n, i;
3761 unsigned long *dirty_bitmap;
3762 unsigned long *dirty_bitmap_buffer;
3763 bool is_dirty = false;
5bb064dc 3764
79fac95e 3765 mutex_lock(&kvm->slots_lock);
5bb064dc 3766
b050b015 3767 r = -EINVAL;
bbacc0c1 3768 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3769 goto out;
3770
28a37544 3771 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3772
3773 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3774 r = -ENOENT;
60c34612 3775 if (!dirty_bitmap)
b050b015
MT		 3776 goto out;
3777
87bf6e7d 3778 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3779
60c34612
TY		 3780 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3781 memset(dirty_bitmap_buffer, 0, n);
b050b015 3782
60c34612 3783 spin_lock(&kvm->mmu_lock);
b050b015 3784
60c34612
TY		 3785 for (i = 0; i < n / sizeof(long); i++) {
3786 unsigned long mask;
3787 gfn_t offset;
cdfca7b3 3788
60c34612
TY		 3789 if (!dirty_bitmap[i])
3790 continue;
b050b015 3791
60c34612 3792 is_dirty = true;
914ebccd 3793
60c34612
TY		 3794 mask = xchg(&dirty_bitmap[i], 0);
3795 dirty_bitmap_buffer[i] = mask;
edde99ce 3796
60c34612
TY		 3797 offset = i * BITS_PER_LONG;
3798 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3799 }
60c34612
TY		 3800
3801 spin_unlock(&kvm->mmu_lock);
3802
198c74f4
XG		 3803 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3804 lockdep_assert_held(&kvm->slots_lock);
3805
3806 /*
3807 * All the TLBs can be flushed out of mmu lock, see the comments in
3808 * kvm_mmu_slot_remove_write_access().
3809 */
3810 if (is_dirty)
3811 kvm_flush_remote_tlbs(kvm);
3812
60c34612
TY		 3813 r = -EFAULT;
3814 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3815 goto out;
b050b015 3816
5bb064dc
ZX		 3817 r = 0;
3818out:
79fac95e 3819 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3820 return r;
3821}
3822
aa2fbe6d
YZ		 3823int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3824 bool line_status)
23d43cf9
CD		 3825{
3826 if (!irqchip_in_kernel(kvm))
3827 return -ENXIO;
3828
3829 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3830 irq_event->irq, irq_event->level,
3831 line_status);
23d43cf9
CD		 3832 return 0;
3833}
3834
1fe779f8
CO		 3835long kvm_arch_vm_ioctl(struct file *filp,
3836 unsigned int ioctl, unsigned long arg)
3837{
3838 struct kvm *kvm = filp->private_data;
3839 void __user *argp = (void __user *)arg;
367e1319 3840 int r = -ENOTTY;
f0d66275
DH		 3841 /*
3842 * This union makes it completely explicit to gcc-3.x
3843 * that these two variables' stack usage should be
3844 * combined, not added together.
3845 */
3846 union {
3847 struct kvm_pit_state ps;
e9f42757 3848 struct kvm_pit_state2 ps2;
c5ff41ce 3849 struct kvm_pit_config pit_config;
f0d66275 3850 } u;
1fe779f8
CO		 3851
3852 switch (ioctl) {
3853 case KVM_SET_TSS_ADDR:
3854 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3855 break;
b927a3ce
SY		 3856 case KVM_SET_IDENTITY_MAP_ADDR: {
3857 u64 ident_addr;
3858
3859 r = -EFAULT;
3860 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3861 goto out;
3862 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3863 break;
3864 }
1fe779f8
CO		 3865 case KVM_SET_NR_MMU_PAGES:
3866 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3867 break;
3868 case KVM_GET_NR_MMU_PAGES:
3869 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3870 break;
3ddea128
MT		 3871 case KVM_CREATE_IRQCHIP: {
3872 struct kvm_pic *vpic;
3873
3874 mutex_lock(&kvm->lock);
3875 r = -EEXIST;
3876 if (kvm->arch.vpic)
3877 goto create_irqchip_unlock;
3e515705
AK		 3878 r = -EINVAL;
3879 if (atomic_read(&kvm->online_vcpus))
3880 goto create_irqchip_unlock;
1fe779f8 3881 r = -ENOMEM;
3ddea128
MT		 3882 vpic = kvm_create_pic(kvm);
3883 if (vpic) {
1fe779f8
CO		 3884 r = kvm_ioapic_init(kvm);
3885 if (r) {
175504cd 3886 mutex_lock(&kvm->slots_lock);
72bb2fcd 3887 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3888 &vpic->dev_master);
3889 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3890 &vpic->dev_slave);
3891 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3892 &vpic->dev_eclr);
175504cd 3893 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3894 kfree(vpic);
3895 goto create_irqchip_unlock;
1fe779f8
CO		 3896 }
3897 } else
3ddea128
MT		 3898 goto create_irqchip_unlock;
3899 smp_wmb();
3900 kvm->arch.vpic = vpic;
3901 smp_wmb();
399ec807
AK		 3902 r = kvm_setup_default_irq_routing(kvm);
3903 if (r) {
175504cd 3904 mutex_lock(&kvm->slots_lock);
3ddea128 3905 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3906 kvm_ioapic_destroy(kvm);
3907 kvm_destroy_pic(kvm);
3ddea128 3908 mutex_unlock(&kvm->irq_lock);
175504cd 3909 mutex_unlock(&kvm->slots_lock);
399ec807 3910 }
3ddea128
MT		 3911 create_irqchip_unlock:
3912 mutex_unlock(&kvm->lock);
1fe779f8 3913 break;
3ddea128 3914 }
7837699f 3915 case KVM_CREATE_PIT:
c5ff41ce
JK		 3916 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3917 goto create_pit;
3918 case KVM_CREATE_PIT2:
3919 r = -EFAULT;
3920 if (copy_from_user(&u.pit_config, argp,
3921 sizeof(struct kvm_pit_config)))
3922 goto out;
3923 create_pit:
79fac95e 3924 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3925 r = -EEXIST;
3926 if (kvm->arch.vpit)
3927 goto create_pit_unlock;
7837699f 3928 r = -ENOMEM;
c5ff41ce 3929 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3930 if (kvm->arch.vpit)
3931 r = 0;
269e05e4 3932 create_pit_unlock:
79fac95e 3933 mutex_unlock(&kvm->slots_lock);
7837699f 3934 break;
1fe779f8
CO		 3935 case KVM_GET_IRQCHIP: {
3936 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3937 struct kvm_irqchip *chip;
1fe779f8 3938
ff5c2c03
SL		 3939 chip = memdup_user(argp, sizeof(*chip));
3940 if (IS_ERR(chip)) {
3941 r = PTR_ERR(chip);
1fe779f8 3942 goto out;
ff5c2c03
SL		 3943 }
3944
1fe779f8
CO		 3945 r = -ENXIO;
3946 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3947 goto get_irqchip_out;
3948 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3949 if (r)
f0d66275 3950 goto get_irqchip_out;
1fe779f8 3951 r = -EFAULT;
f0d66275
DH		 3952 if (copy_to_user(argp, chip, sizeof *chip))
3953 goto get_irqchip_out;
1fe779f8 3954 r = 0;
f0d66275
DH		 3955 get_irqchip_out:
3956 kfree(chip);
1fe779f8
CO		 3957 break;
3958 }
3959 case KVM_SET_IRQCHIP: {
3960 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3961 struct kvm_irqchip *chip;
1fe779f8 3962
ff5c2c03
SL		 3963 chip = memdup_user(argp, sizeof(*chip));
3964 if (IS_ERR(chip)) {
3965 r = PTR_ERR(chip);
1fe779f8 3966 goto out;
ff5c2c03
SL		 3967 }
3968
1fe779f8
CO		 3969 r = -ENXIO;
3970 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3971 goto set_irqchip_out;
3972 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3973 if (r)
f0d66275 3974 goto set_irqchip_out;
1fe779f8 3975 r = 0;
f0d66275
DH		 3976 set_irqchip_out:
3977 kfree(chip);
1fe779f8
CO		 3978 break;
3979 }
e0f63cb9 3980 case KVM_GET_PIT: {
e0f63cb9 3981 r = -EFAULT;
f0d66275 3982 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3983 goto out;
3984 r = -ENXIO;
3985 if (!kvm->arch.vpit)
3986 goto out;
f0d66275 3987 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3988 if (r)
3989 goto out;
3990 r = -EFAULT;
f0d66275 3991 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3992 goto out;
3993 r = 0;
3994 break;
3995 }
3996 case KVM_SET_PIT: {
e0f63cb9 3997 r = -EFAULT;
f0d66275 3998 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3999 goto out;
4000 r = -ENXIO;
4001 if (!kvm->arch.vpit)
4002 goto out;
f0d66275 4003 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4004 break;
4005 }
e9f42757
BK		 4006 case KVM_GET_PIT2: {
4007 r = -ENXIO;
4008 if (!kvm->arch.vpit)
4009 goto out;
4010 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4011 if (r)
4012 goto out;
4013 r = -EFAULT;
4014 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4015 goto out;
4016 r = 0;
4017 break;
4018 }
4019 case KVM_SET_PIT2: {
4020 r = -EFAULT;
4021 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4022 goto out;
4023 r = -ENXIO;
4024 if (!kvm->arch.vpit)
4025 goto out;
4026 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4027 break;
4028 }
52d939a0
MT		 4029 case KVM_REINJECT_CONTROL: {
4030 struct kvm_reinject_control control;
4031 r = -EFAULT;
4032 if (copy_from_user(&control, argp, sizeof(control)))
4033 goto out;
4034 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4035 break;
4036 }
ffde22ac
ES		 4037 case KVM_XEN_HVM_CONFIG: {
4038 r = -EFAULT;
4039 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4040 sizeof(struct kvm_xen_hvm_config)))
4041 goto out;
4042 r = -EINVAL;
4043 if (kvm->arch.xen_hvm_config.flags)
4044 goto out;
4045 r = 0;
4046 break;
4047 }
afbcf7ab 4048 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4049 struct kvm_clock_data user_ns;
4050 u64 now_ns;
4051 s64 delta;
4052
4053 r = -EFAULT;
4054 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4055 goto out;
4056
4057 r = -EINVAL;
4058 if (user_ns.flags)
4059 goto out;
4060
4061 r = 0;
395c6b0a 4062 local_irq_disable();
759379dd 4063 now_ns = get_kernel_ns();
afbcf7ab 4064 delta = user_ns.clock - now_ns;
395c6b0a 4065 local_irq_enable();
afbcf7ab 4066 kvm->arch.kvmclock_offset = delta;
2e762ff7 4067 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4068 break;
4069 }
4070 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4071 struct kvm_clock_data user_ns;
4072 u64 now_ns;
4073
395c6b0a 4074 local_irq_disable();
759379dd 4075 now_ns = get_kernel_ns();
afbcf7ab 4076 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4077 local_irq_enable();
afbcf7ab 4078 user_ns.flags = 0;
97e69aa6 4079 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4080
4081 r = -EFAULT;
4082 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4083 goto out;
4084 r = 0;
4085 break;
4086 }
4087
1fe779f8 4088 default:
c274e03a 4089 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4090 }
4091out:
4092 return r;
4093}
4094
a16b043c 4095static void kvm_init_msr_list(void)
043405e1
CO		 4096{
4097 u32 dummy[2];
4098 unsigned i, j;
4099
e3267cbb
GC		 4100 /* skip the first msrs in the list. KVM-specific */
4101 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4102 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4103 continue;
93c4adc7
PB		 4104
4105 /*
4106 * Even MSRs that are valid in the host may not be exposed
4107 * to the guests in some cases. We could work around this
4108 * in VMX with the generic MSR save/load machinery, but it
4109 * is not really worthwhile since it will really only
4110 * happen with nested virtualization.
4111 */
4112 switch (msrs_to_save[i]) {
4113 case MSR_IA32_BNDCFGS:
4114 if (!kvm_x86_ops->mpx_supported())
4115 continue;
4116 break;
4117 default:
4118 break;
4119 }
4120
043405e1
CO		 4121 if (j < i)
4122 msrs_to_save[j] = msrs_to_save[i];
4123 j++;
4124 }
4125 num_msrs_to_save = j;
4126}
4127
bda9020e
MT		 4128static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4129 const void *v)
bbd9b64e 4130{
70252a10
AK		 4131 int handled = 0;
4132 int n;
4133
4134 do {
4135 n = min(len, 8);
4136 if (!(vcpu->arch.apic &&
4137 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4138 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4139 break;
4140 handled += n;
4141 addr += n;
4142 len -= n;
4143 v += n;
4144 } while (len);
bbd9b64e 4145
70252a10 4146 return handled;
bbd9b64e
CO		 4147}
4148
bda9020e 4149static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4150{
70252a10
AK		 4151 int handled = 0;
4152 int n;
4153
4154 do {
4155 n = min(len, 8);
4156 if (!(vcpu->arch.apic &&
4157 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4158 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4159 break;
4160 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4161 handled += n;
4162 addr += n;
4163 len -= n;
4164 v += n;
4165 } while (len);
bbd9b64e 4166
70252a10 4167 return handled;
bbd9b64e
CO		 4168}
4169
2dafc6c2
GN		 4170static void kvm_set_segment(struct kvm_vcpu *vcpu,
4171 struct kvm_segment *var, int seg)
4172{
4173 kvm_x86_ops->set_segment(vcpu, var, seg);
4174}
4175
4176void kvm_get_segment(struct kvm_vcpu *vcpu,
4177 struct kvm_segment *var, int seg)
4178{
4179 kvm_x86_ops->get_segment(vcpu, var, seg);
4180}
4181
54987b7a
PB		 4182gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4183 struct x86_exception *exception)
02f59dc9
JR		 4184{
4185 gpa_t t_gpa;
02f59dc9
JR		 4186
4187 BUG_ON(!mmu_is_nested(vcpu));
4188
4189 /* NPT walks are always user-walks */
4190 access |= PFERR_USER_MASK;
54987b7a 4191 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4192
4193 return t_gpa;
4194}
4195
ab9ae313
AK		 4196gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4197 struct x86_exception *exception)
1871c602
GN		 4198{
4199 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4200 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4201}
4202
ab9ae313
AK		 4203 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4204 struct x86_exception *exception)
1871c602
GN		 4205{
4206 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4207 access |= PFERR_FETCH_MASK;
ab9ae313 4208 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4209}
4210
ab9ae313
AK		 4211gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4212 struct x86_exception *exception)
1871c602
GN		 4213{
4214 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4215 access |= PFERR_WRITE_MASK;
ab9ae313 4216 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4217}
4218
4219/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4220gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4221 struct x86_exception *exception)
1871c602 4222{
ab9ae313 4223 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4224}
4225
4226static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4227 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4228 struct x86_exception *exception)
bbd9b64e
CO		 4229{
4230 void *data = val;
10589a46 4231 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4232
4233 while (bytes) {
14dfe855 4234 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4235 exception);
bbd9b64e 4236 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4237 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4238 int ret;
4239
bcc55cba 4240 if (gpa == UNMAPPED_GVA)
ab9ae313 4241 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4242 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4243 offset, toread);
10589a46 4244 if (ret < 0) {
c3cd7ffa 4245 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4246 goto out;
4247 }
bbd9b64e 4248
77c2002e
IE		 4249 bytes -= toread;
4250 data += toread;
4251 addr += toread;
bbd9b64e 4252 }
10589a46 4253out:
10589a46 4254 return r;
bbd9b64e 4255}
77c2002e 4256
1871c602 4257/* used for instruction fetching */
0f65dd70
AK		 4258static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4259 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4260 struct x86_exception *exception)
1871c602 4261{
0f65dd70 4262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4263 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4264 unsigned offset;
4265 int ret;
0f65dd70 4266
44583cba
PB		 4267 /* Inline kvm_read_guest_virt_helper for speed. */
4268 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4269 exception);
4270 if (unlikely(gpa == UNMAPPED_GVA))
4271 return X86EMUL_PROPAGATE_FAULT;
4272
4273 offset = addr & (PAGE_SIZE-1);
4274 if (WARN_ON(offset + bytes > PAGE_SIZE))
4275 bytes = (unsigned)PAGE_SIZE - offset;
4276 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4277 offset, bytes);
4278 if (unlikely(ret < 0))
4279 return X86EMUL_IO_NEEDED;
4280
4281 return X86EMUL_CONTINUE;
1871c602
GN		 4282}
4283
064aea77 4284int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4285 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4286 struct x86_exception *exception)
1871c602 4287{
0f65dd70 4288 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4289 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4290
1871c602 4291 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4292 exception);
1871c602 4293}
064aea77 4294EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4295
0f65dd70
AK		 4296static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4297 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4298 struct x86_exception *exception)
1871c602 4299{
0f65dd70 4300 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4301 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4302}
4303
6a4d7550 4304int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4305 gva_t addr, void *val,
2dafc6c2 4306 unsigned int bytes,
bcc55cba 4307 struct x86_exception *exception)
77c2002e 4308{
0f65dd70 4309 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4310 void *data = val;
4311 int r = X86EMUL_CONTINUE;
4312
4313 while (bytes) {
14dfe855
JR		 4314 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4315 PFERR_WRITE_MASK,
ab9ae313 4316 exception);
77c2002e
IE		 4317 unsigned offset = addr & (PAGE_SIZE-1);
4318 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4319 int ret;
4320
bcc55cba 4321 if (gpa == UNMAPPED_GVA)
ab9ae313 4322 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4323 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4324 if (ret < 0) {
c3cd7ffa 4325 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4326 goto out;
4327 }
4328
4329 bytes -= towrite;
4330 data += towrite;
4331 addr += towrite;
4332 }
4333out:
4334 return r;
4335}
6a4d7550 4336EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4337
af7cc7d1
XG		 4338static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4339 gpa_t *gpa, struct x86_exception *exception,
4340 bool write)
4341{
97d64b78
AK		 4342 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4343 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4344
97d64b78 4345 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4346 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4347 vcpu->arch.access, access)) {
bebb106a
XG		 4348 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4349 (gva & (PAGE_SIZE - 1));
4f022648 4350 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4351 return 1;
4352 }
4353
af7cc7d1
XG		 4354 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4355
4356 if (*gpa == UNMAPPED_GVA)
4357 return -1;
4358
4359 /* For APIC access vmexit */
4360 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4361 return 1;
4362
4f022648
XG		 4363 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4364 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4365 return 1;
4f022648 4366 }
bebb106a 4367
af7cc7d1
XG		 4368 return 0;
4369}
4370
3200f405 4371int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4372 const void *val, int bytes)
bbd9b64e
CO		 4373{
4374 int ret;
4375
4376 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4377 if (ret < 0)
bbd9b64e 4378 return 0;
f57f2ef5 4379 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4380 return 1;
4381}
4382
77d197b2
XG		 4383struct read_write_emulator_ops {
4384 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4385 int bytes);
4386 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4387 void *val, int bytes);
4388 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4389 int bytes, void *val);
4390 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4391 void *val, int bytes);
4392 bool write;
4393};
4394
4395static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4396{
4397 if (vcpu->mmio_read_completed) {
77d197b2 4398 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4399 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4400 vcpu->mmio_read_completed = 0;
4401 return 1;
4402 }
4403
4404 return 0;
4405}
4406
4407static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 void *val, int bytes)
4409{
4410 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4411}
4412
4413static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4414 void *val, int bytes)
4415{
4416 return emulator_write_phys(vcpu, gpa, val, bytes);
4417}
4418
4419static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4420{
4421 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4422 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4423}
4424
4425static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4426 void *val, int bytes)
4427{
4428 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4429 return X86EMUL_IO_NEEDED;
4430}
4431
4432static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4433 void *val, int bytes)
4434{
f78146b0
AK		 4435 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4436
87da7e66 4437 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4438 return X86EMUL_CONTINUE;
4439}
4440
0fbe9b0b 4441static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4442 .read_write_prepare = read_prepare,
4443 .read_write_emulate = read_emulate,
4444 .read_write_mmio = vcpu_mmio_read,
4445 .read_write_exit_mmio = read_exit_mmio,
4446};
4447
0fbe9b0b 4448static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4449 .read_write_emulate = write_emulate,
4450 .read_write_mmio = write_mmio,
4451 .read_write_exit_mmio = write_exit_mmio,
4452 .write = true,
4453};
4454
22388a3c
XG		 4455static int emulator_read_write_onepage(unsigned long addr, void *val,
4456 unsigned int bytes,
4457 struct x86_exception *exception,
4458 struct kvm_vcpu *vcpu,
0fbe9b0b 4459 const struct read_write_emulator_ops *ops)
bbd9b64e 4460{
af7cc7d1
XG		 4461 gpa_t gpa;
4462 int handled, ret;
22388a3c 4463 bool write = ops->write;
f78146b0 4464 struct kvm_mmio_fragment *frag;
10589a46 4465
22388a3c 4466 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4467
af7cc7d1 4468 if (ret < 0)
bbd9b64e 4469 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4470
4471 /* For APIC access vmexit */
af7cc7d1 4472 if (ret)
bbd9b64e
CO		 4473 goto mmio;
4474
22388a3c 4475 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4476 return X86EMUL_CONTINUE;
4477
4478mmio:
4479 /*
4480 * Is this MMIO handled locally?
4481 */
22388a3c 4482 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4483 if (handled == bytes)
bbd9b64e 4484 return X86EMUL_CONTINUE;
bbd9b64e 4485
70252a10
AK		 4486 gpa += handled;
4487 bytes -= handled;
4488 val += handled;
4489
87da7e66
XG		 4490 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4491 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4492 frag->gpa = gpa;
4493 frag->data = val;
4494 frag->len = bytes;
f78146b0 4495 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4496}
4497
22388a3c
XG		 4498int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4499 void *val, unsigned int bytes,
4500 struct x86_exception *exception,
0fbe9b0b 4501 const struct read_write_emulator_ops *ops)
bbd9b64e 4502{
0f65dd70 4503 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4504 gpa_t gpa;
4505 int rc;
4506
4507 if (ops->read_write_prepare &&
4508 ops->read_write_prepare(vcpu, val, bytes))
4509 return X86EMUL_CONTINUE;
4510
4511 vcpu->mmio_nr_fragments = 0;
0f65dd70 4512
bbd9b64e
CO		 4513 /* Crossing a page boundary? */
4514 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4515 int now;
bbd9b64e
CO		 4516
4517 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4518 rc = emulator_read_write_onepage(addr, val, now, exception,
4519 vcpu, ops);
4520
bbd9b64e
CO		 4521 if (rc != X86EMUL_CONTINUE)
4522 return rc;
4523 addr += now;
4524 val += now;
4525 bytes -= now;
4526 }
22388a3c 4527
f78146b0
AK		 4528 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4529 vcpu, ops);
4530 if (rc != X86EMUL_CONTINUE)
4531 return rc;
4532
4533 if (!vcpu->mmio_nr_fragments)
4534 return rc;
4535
4536 gpa = vcpu->mmio_fragments[0].gpa;
4537
4538 vcpu->mmio_needed = 1;
4539 vcpu->mmio_cur_fragment = 0;
4540
87da7e66 4541 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4542 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4543 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4544 vcpu->run->mmio.phys_addr = gpa;
4545
4546 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4547}
4548
4549static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4550 unsigned long addr,
4551 void *val,
4552 unsigned int bytes,
4553 struct x86_exception *exception)
4554{
4555 return emulator_read_write(ctxt, addr, val, bytes,
4556 exception, &read_emultor);
4557}
4558
4559int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4560 unsigned long addr,
4561 const void *val,
4562 unsigned int bytes,
4563 struct x86_exception *exception)
4564{
4565 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4566 exception, &write_emultor);
bbd9b64e 4567}
bbd9b64e 4568
daea3e73
AK		 4569#define CMPXCHG_TYPE(t, ptr, old, new) \
4570 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4571
4572#ifdef CONFIG_X86_64
4573# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4574#else
4575# define CMPXCHG64(ptr, old, new) \
9749a6c0 4576 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4577#endif
4578
0f65dd70
AK		 4579static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4580 unsigned long addr,
bbd9b64e
CO		 4581 const void *old,
4582 const void *new,
4583 unsigned int bytes,
0f65dd70 4584 struct x86_exception *exception)
bbd9b64e 4585{
0f65dd70 4586 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4587 gpa_t gpa;
4588 struct page *page;
4589 char *kaddr;
4590 bool exchanged;
2bacc55c 4591
daea3e73
AK		 4592 /* guests cmpxchg8b have to be emulated atomically */
4593 if (bytes > 8 || (bytes & (bytes - 1)))
4594 goto emul_write;
10589a46 4595
daea3e73 4596 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4597
daea3e73
AK		 4598 if (gpa == UNMAPPED_GVA ||
4599 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4600 goto emul_write;
2bacc55c 4601
daea3e73
AK		 4602 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4603 goto emul_write;
72dc67a6 4604
daea3e73 4605 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4606 if (is_error_page(page))
c19b8bd6 4607 goto emul_write;
72dc67a6 4608
8fd75e12 4609 kaddr = kmap_atomic(page);
daea3e73
AK		 4610 kaddr += offset_in_page(gpa);
4611 switch (bytes) {
4612 case 1:
4613 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4614 break;
4615 case 2:
4616 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4617 break;
4618 case 4:
4619 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4620 break;
4621 case 8:
4622 exchanged = CMPXCHG64(kaddr, old, new);
4623 break;
4624 default:
4625 BUG();
2bacc55c 4626 }
8fd75e12 4627 kunmap_atomic(kaddr);
daea3e73
AK		 4628 kvm_release_page_dirty(page);
4629
4630 if (!exchanged)
4631 return X86EMUL_CMPXCHG_FAILED;
4632
d3714010 4633 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4634 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4635
4636 return X86EMUL_CONTINUE;
4a5f48f6 4637
3200f405 4638emul_write:
daea3e73 4639 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4640
0f65dd70 4641 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4642}
4643
cf8f70bf
GN		 4644static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4645{
4646 /* TODO: String I/O for in kernel device */
4647 int r;
4648
4649 if (vcpu->arch.pio.in)
4650 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4651 vcpu->arch.pio.size, pd);
4652 else
4653 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4654 vcpu->arch.pio.port, vcpu->arch.pio.size,
4655 pd);
4656 return r;
4657}
4658
6f6fbe98
XG		 4659static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4660 unsigned short port, void *val,
4661 unsigned int count, bool in)
cf8f70bf 4662{
cf8f70bf 4663 vcpu->arch.pio.port = port;
6f6fbe98 4664 vcpu->arch.pio.in = in;
7972995b 4665 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4666 vcpu->arch.pio.size = size;
4667
4668 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4669 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4670 return 1;
4671 }
4672
4673 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4674 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4675 vcpu->run->io.size = size;
4676 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4677 vcpu->run->io.count = count;
4678 vcpu->run->io.port = port;
4679
4680 return 0;
4681}
4682
6f6fbe98
XG		 4683static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4684 int size, unsigned short port, void *val,
4685 unsigned int count)
cf8f70bf 4686{
ca1d4a9e 4687 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4688 int ret;
ca1d4a9e 4689
6f6fbe98
XG		 4690 if (vcpu->arch.pio.count)
4691 goto data_avail;
cf8f70bf 4692
6f6fbe98
XG		 4693 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4694 if (ret) {
4695data_avail:
4696 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4697 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4698 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4699 return 1;
4700 }
4701
cf8f70bf
GN		 4702 return 0;
4703}
4704
6f6fbe98
XG		 4705static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4706 int size, unsigned short port,
4707 const void *val, unsigned int count)
4708{
4709 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4710
4711 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4712 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4713 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4714}
4715
bbd9b64e
CO		 4716static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4717{
4718 return kvm_x86_ops->get_segment_base(vcpu, seg);
4719}
4720
3cb16fe7 4721static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4722{
3cb16fe7 4723 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4724}
4725
f5f48ee1
SY		 4726int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4727{
4728 if (!need_emulate_wbinvd(vcpu))
4729 return X86EMUL_CONTINUE;
4730
4731 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4732 int cpu = get_cpu();
4733
4734 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4735 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4736 wbinvd_ipi, NULL, 1);
2eec7343 4737 put_cpu();
f5f48ee1 4738 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4739 } else
4740 wbinvd();
f5f48ee1
SY		 4741 return X86EMUL_CONTINUE;
4742}
4743EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4744
bcaf5cc5
AK		 4745static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4746{
4747 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4748}
4749
717746e3 4750int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4751{
16f8a6f9 4752 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4753}
4754
717746e3 4755int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4756{
338dbc97 4757
717746e3 4758 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4759}
4760
52a46617 4761static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4762{
52a46617 4763 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4764}
4765
717746e3 4766static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4767{
717746e3 4768 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4769 unsigned long value;
4770
4771 switch (cr) {
4772 case 0:
4773 value = kvm_read_cr0(vcpu);
4774 break;
4775 case 2:
4776 value = vcpu->arch.cr2;
4777 break;
4778 case 3:
9f8fe504 4779 value = kvm_read_cr3(vcpu);
52a46617
GN		 4780 break;
4781 case 4:
4782 value = kvm_read_cr4(vcpu);
4783 break;
4784 case 8:
4785 value = kvm_get_cr8(vcpu);
4786 break;
4787 default:
a737f256 4788 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4789 return 0;
4790 }
4791
4792 return value;
4793}
4794
717746e3 4795static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4796{
717746e3 4797 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4798 int res = 0;
4799
52a46617
GN		 4800 switch (cr) {
4801 case 0:
49a9b07e 4802 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4803 break;
4804 case 2:
4805 vcpu->arch.cr2 = val;
4806 break;
4807 case 3:
2390218b 4808 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4809 break;
4810 case 4:
a83b29c6 4811 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4812 break;
4813 case 8:
eea1cff9 4814 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4815 break;
4816 default:
a737f256 4817 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4818 res = -1;
52a46617 4819 }
0f12244f
GN		 4820
4821 return res;
52a46617
GN		 4822}
4823
717746e3 4824static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4825{
717746e3 4826 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4827}
4828
4bff1e86 4829static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4830{
4bff1e86 4831 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4832}
4833
4bff1e86 4834static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4835{
4bff1e86 4836 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4837}
4838
1ac9d0cf
AK		 4839static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4840{
4841 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4842}
4843
4844static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4845{
4846 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4847}
4848
4bff1e86
AK		 4849static unsigned long emulator_get_cached_segment_base(
4850 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4851{
4bff1e86 4852 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4853}
4854
1aa36616
AK		 4855static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4856 struct desc_struct *desc, u32 *base3,
4857 int seg)
2dafc6c2
GN		 4858{
4859 struct kvm_segment var;
4860
4bff1e86 4861 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4862 *selector = var.selector;
2dafc6c2 4863
378a8b09
GN		 4864 if (var.unusable) {
4865 memset(desc, 0, sizeof(*desc));
2dafc6c2 4866 return false;
378a8b09 4867 }
2dafc6c2
GN		 4868
4869 if (var.g)
4870 var.limit >>= 12;
4871 set_desc_limit(desc, var.limit);
4872 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4873#ifdef CONFIG_X86_64
4874 if (base3)
4875 *base3 = var.base >> 32;
4876#endif
2dafc6c2
GN		 4877 desc->type = var.type;
4878 desc->s = var.s;
4879 desc->dpl = var.dpl;
4880 desc->p = var.present;
4881 desc->avl = var.avl;
4882 desc->l = var.l;
4883 desc->d = var.db;
4884 desc->g = var.g;
4885
4886 return true;
4887}
4888
1aa36616
AK		 4889static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4890 struct desc_struct *desc, u32 base3,
4891 int seg)
2dafc6c2 4892{
4bff1e86 4893 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4894 struct kvm_segment var;
4895
1aa36616 4896 var.selector = selector;
2dafc6c2 4897 var.base = get_desc_base(desc);
5601d05b
GN		 4898#ifdef CONFIG_X86_64
4899 var.base |= ((u64)base3) << 32;
4900#endif
2dafc6c2
GN		 4901 var.limit = get_desc_limit(desc);
4902 if (desc->g)
4903 var.limit = (var.limit << 12) | 0xfff;
4904 var.type = desc->type;
2dafc6c2
GN		 4905 var.dpl = desc->dpl;
4906 var.db = desc->d;
4907 var.s = desc->s;
4908 var.l = desc->l;
4909 var.g = desc->g;
4910 var.avl = desc->avl;
4911 var.present = desc->p;
4912 var.unusable = !var.present;
4913 var.padding = 0;
4914
4915 kvm_set_segment(vcpu, &var, seg);
4916 return;
4917}
4918
717746e3
AK		 4919static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4920 u32 msr_index, u64 *pdata)
4921{
4922 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4923}
4924
4925static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4926 u32 msr_index, u64 data)
4927{
8fe8ab46
WA		 4928 struct msr_data msr;
4929
4930 msr.data = data;
4931 msr.index = msr_index;
4932 msr.host_initiated = false;
4933 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4934}
4935
67f4d428
NA		 4936static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4937 u32 pmc)
4938{
4939 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4940}
4941
222d21aa
AK		 4942static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4943 u32 pmc, u64 *pdata)
4944{
4945 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4946}
4947
6c3287f7
AK		 4948static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4949{
4950 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4951}
4952
5037f6f3
AK		 4953static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4954{
4955 preempt_disable();
5197b808 4956 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4957 /*
4958 * CR0.TS may reference the host fpu state, not the guest fpu state,
4959 * so it may be clear at this point.
4960 */
4961 clts();
4962}
4963
4964static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4965{
4966 preempt_enable();
4967}
4968
2953538e 4969static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4970 struct x86_instruction_info *info,
c4f035c6
AK		 4971 enum x86_intercept_stage stage)
4972{
2953538e 4973 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4974}
4975
0017f93a 4976static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4977 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4978{
0017f93a 4979 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4980}
4981
dd856efa
AK		 4982static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4983{
4984 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4985}
4986
4987static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4988{
4989 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4990}
4991
0225fb50 4992static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4993 .read_gpr = emulator_read_gpr,
4994 .write_gpr = emulator_write_gpr,
1871c602 4995 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4996 .write_std = kvm_write_guest_virt_system,
1871c602 4997 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4998 .read_emulated = emulator_read_emulated,
4999 .write_emulated = emulator_write_emulated,
5000 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5001 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5002 .pio_in_emulated = emulator_pio_in_emulated,
5003 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5004 .get_segment = emulator_get_segment,
5005 .set_segment = emulator_set_segment,
5951c442 5006 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5007 .get_gdt = emulator_get_gdt,
160ce1f1 5008 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5009 .set_gdt = emulator_set_gdt,
5010 .set_idt = emulator_set_idt,
52a46617
GN		 5011 .get_cr = emulator_get_cr,
5012 .set_cr = emulator_set_cr,
9c537244 5013 .cpl = emulator_get_cpl,
35aa5375
GN		 5014 .get_dr = emulator_get_dr,
5015 .set_dr = emulator_set_dr,
717746e3
AK		 5016 .set_msr = emulator_set_msr,
5017 .get_msr = emulator_get_msr,
67f4d428 5018 .check_pmc = emulator_check_pmc,
222d21aa 5019 .read_pmc = emulator_read_pmc,
6c3287f7 5020 .halt = emulator_halt,
bcaf5cc5 5021 .wbinvd = emulator_wbinvd,
d6aa1000 5022 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5023 .get_fpu = emulator_get_fpu,
5024 .put_fpu = emulator_put_fpu,
c4f035c6 5025 .intercept = emulator_intercept,
bdb42f5a 5026 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 5027};
5028
95cb2295
GN		 5029static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5030{
37ccdcbe 5031 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5032 /*
5033 * an sti; sti; sequence only disable interrupts for the first
5034 * instruction. So, if the last instruction, be it emulated or
5035 * not, left the system with the INT_STI flag enabled, it
5036 * means that the last instruction is an sti. We should not
5037 * leave the flag on in this case. The same goes for mov ss
5038 */
37ccdcbe
PB		 5039 if (int_shadow & mask)
5040 mask = 0;
6addfc42 5041 if (unlikely(int_shadow || mask)) {
95cb2295 5042 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5043 if (!mask)
5044 kvm_make_request(KVM_REQ_EVENT, vcpu);
5045 }
95cb2295
GN		 5046}
5047
ef54bcfe 5048static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5049{
5050 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5051 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5052 return kvm_propagate_fault(vcpu, &ctxt->exception);
5053
5054 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5055 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5056 ctxt->exception.error_code);
54b8486f 5057 else
da9cb575 5058 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5059 return false;
54b8486f
GN		 5060}
5061
8ec4722d
MG		 5062static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5063{
adf52235 5064 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5065 int cs_db, cs_l;
5066
8ec4722d
MG		 5067 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5068
adf52235
TY		 5069 ctxt->eflags = kvm_get_rflags(vcpu);
5070 ctxt->eip = kvm_rip_read(vcpu);
5071 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5072 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5073 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5074 cs_db ? X86EMUL_MODE_PROT32 :
5075 X86EMUL_MODE_PROT16;
5076 ctxt->guest_mode = is_guest_mode(vcpu);
5077
dd856efa 5078 init_decode_cache(ctxt);
7ae441ea 5079 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5080}
5081
71f9833b 5082int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5083{
9d74191a 5084 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5085 int ret;
5086
5087 init_emulate_ctxt(vcpu);
5088
9dac77fa
AK		 5089 ctxt->op_bytes = 2;
5090 ctxt->ad_bytes = 2;
5091 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5092 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5093
5094 if (ret != X86EMUL_CONTINUE)
5095 return EMULATE_FAIL;
5096
9dac77fa 5097 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5098 kvm_rip_write(vcpu, ctxt->eip);
5099 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5100
5101 if (irq == NMI_VECTOR)
7460fb4a 5102 vcpu->arch.nmi_pending = 0;
63995653
MG		 5103 else
5104 vcpu->arch.interrupt.pending = false;
5105
5106 return EMULATE_DONE;
5107}
5108EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5109
6d77dbfc
GN		 5110static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5111{
fc3a9157
JR		 5112 int r = EMULATE_DONE;
5113
6d77dbfc
GN		 5114 ++vcpu->stat.insn_emulation_fail;
5115 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5116 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5117 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5118 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5119 vcpu->run->internal.ndata = 0;
5120 r = EMULATE_FAIL;
5121 }
6d77dbfc 5122 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5123
5124 return r;
6d77dbfc
GN		 5125}
5126
93c05d3e 5127static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5128 bool write_fault_to_shadow_pgtable,
5129 int emulation_type)
a6f177ef 5130{
95b3cf69 5131 gpa_t gpa = cr2;
8e3d9d06 5132 pfn_t pfn;
a6f177ef 5133
991eebf9
GN		 5134 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5135 return false;
5136
95b3cf69
XG		 5137 if (!vcpu->arch.mmu.direct_map) {
5138 /*
5139 * Write permission should be allowed since only
5140 * write access need to be emulated.
5141 */
5142 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5143
95b3cf69
XG		 5144 /*
5145 * If the mapping is invalid in guest, let cpu retry
5146 * it to generate fault.
5147 */
5148 if (gpa == UNMAPPED_GVA)
5149 return true;
5150 }
a6f177ef 5151
8e3d9d06
XG		 5152 /*
5153 * Do not retry the unhandleable instruction if it faults on the
5154 * readonly host memory, otherwise it will goto a infinite loop:
5155 * retry instruction -> write #PF -> emulation fail -> retry
5156 * instruction -> ...
5157 */
5158 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5159
5160 /*
5161 * If the instruction failed on the error pfn, it can not be fixed,
5162 * report the error to userspace.
5163 */
5164 if (is_error_noslot_pfn(pfn))
5165 return false;
5166
5167 kvm_release_pfn_clean(pfn);
5168
5169 /* The instructions are well-emulated on direct mmu. */
5170 if (vcpu->arch.mmu.direct_map) {
5171 unsigned int indirect_shadow_pages;
5172
5173 spin_lock(&vcpu->kvm->mmu_lock);
5174 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5175 spin_unlock(&vcpu->kvm->mmu_lock);
5176
5177 if (indirect_shadow_pages)
5178 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5179
a6f177ef 5180 return true;
8e3d9d06 5181 }
a6f177ef 5182
95b3cf69
XG		 5183 /*
5184 * if emulation was due to access to shadowed page table
5185 * and it failed try to unshadow page and re-enter the
5186 * guest to let CPU execute the instruction.
5187 */
5188 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5189
5190 /*
5191 * If the access faults on its page table, it can not
5192 * be fixed by unprotecting shadow page and it should
5193 * be reported to userspace.
5194 */
5195 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5196}
5197
1cb3f3ae
XG		 5198static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5199 unsigned long cr2, int emulation_type)
5200{
5201 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5202 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5203
5204 last_retry_eip = vcpu->arch.last_retry_eip;
5205 last_retry_addr = vcpu->arch.last_retry_addr;
5206
5207 /*
5208 * If the emulation is caused by #PF and it is non-page_table
5209 * writing instruction, it means the VM-EXIT is caused by shadow
5210 * page protected, we can zap the shadow page and retry this
5211 * instruction directly.
5212 *
5213 * Note: if the guest uses a non-page-table modifying instruction
5214 * on the PDE that points to the instruction, then we will unmap
5215 * the instruction and go to an infinite loop. So, we cache the
5216 * last retried eip and the last fault address, if we meet the eip
5217 * and the address again, we can break out of the potential infinite
5218 * loop.
5219 */
5220 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5221
5222 if (!(emulation_type & EMULTYPE_RETRY))
5223 return false;
5224
5225 if (x86_page_table_writing_insn(ctxt))
5226 return false;
5227
5228 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5229 return false;
5230
5231 vcpu->arch.last_retry_eip = ctxt->eip;
5232 vcpu->arch.last_retry_addr = cr2;
5233
5234 if (!vcpu->arch.mmu.direct_map)
5235 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5236
22368028 5237 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5238
5239 return true;
5240}
5241
716d51ab
GN		 5242static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5243static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5244
4a1e10d5
PB		 5245static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5246 unsigned long *db)
5247{
5248 u32 dr6 = 0;
5249 int i;
5250 u32 enable, rwlen;
5251
5252 enable = dr7;
5253 rwlen = dr7 >> 16;
5254 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5255 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5256 dr6 |= (1 << i);
5257 return dr6;
5258}
5259
6addfc42 5260static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5261{
5262 struct kvm_run *kvm_run = vcpu->run;
5263
5264 /*
6addfc42
PB		 5265 * rflags is the old, "raw" value of the flags. The new value has
5266 * not been saved yet.
663f4c61
PB		 5267 *
5268 * This is correct even for TF set by the guest, because "the
5269 * processor will not generate this exception after the instruction
5270 * that sets the TF flag".
5271 */
663f4c61
PB		 5272 if (unlikely(rflags & X86_EFLAGS_TF)) {
5273 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5274 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5275 DR6_RTM;
663f4c61
PB		 5276 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5277 kvm_run->debug.arch.exception = DB_VECTOR;
5278 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5279 *r = EMULATE_USER_EXIT;
5280 } else {
5281 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5282 /*
5283 * "Certain debug exceptions may clear bit 0-3. The
5284 * remaining contents of the DR6 register are never
5285 * cleared by the processor".
5286 */
5287 vcpu->arch.dr6 &= ~15;
6f43ed01 5288 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5289 kvm_queue_exception(vcpu, DB_VECTOR);
5290 }
5291 }
5292}
5293
4a1e10d5
PB		 5294static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5295{
4a1e10d5
PB		 5296 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5297 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5298 struct kvm_run *kvm_run = vcpu->run;
5299 unsigned long eip = kvm_get_linear_rip(vcpu);
5300 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5301 vcpu->arch.guest_debug_dr7,
5302 vcpu->arch.eff_db);
5303
5304 if (dr6 != 0) {
6f43ed01 5305 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5306 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5307 kvm_run->debug.arch.exception = DB_VECTOR;
5308 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5309 *r = EMULATE_USER_EXIT;
5310 return true;
5311 }
5312 }
5313
4161a569
NA		 5314 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5315 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5316 unsigned long eip = kvm_get_linear_rip(vcpu);
5317 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5318 vcpu->arch.dr7,
5319 vcpu->arch.db);
5320
5321 if (dr6 != 0) {
5322 vcpu->arch.dr6 &= ~15;
6f43ed01 5323 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5324 kvm_queue_exception(vcpu, DB_VECTOR);
5325 *r = EMULATE_DONE;
5326 return true;
5327 }
5328 }
5329
5330 return false;
5331}
5332
51d8b661
AP		 5333int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5334 unsigned long cr2,
dc25e89e
AP		 5335 int emulation_type,
5336 void *insn,
5337 int insn_len)
bbd9b64e 5338{
95cb2295 5339 int r;
9d74191a 5340 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5341 bool writeback = true;
93c05d3e 5342 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5343
93c05d3e
XG		 5344 /*
5345 * Clear write_fault_to_shadow_pgtable here to ensure it is
5346 * never reused.
5347 */
5348 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5349 kvm_clear_exception_queue(vcpu);
8d7d8102 5350
571008da 5351 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5352 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5353
5354 /*
5355 * We will reenter on the same instruction since
5356 * we do not set complete_userspace_io. This does not
5357 * handle watchpoints yet, those would be handled in
5358 * the emulate_ops.
5359 */
5360 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5361 return r;
5362
9d74191a
TY		 5363 ctxt->interruptibility = 0;
5364 ctxt->have_exception = false;
e0ad0b47 5365 ctxt->exception.vector = -1;
9d74191a 5366 ctxt->perm_ok = false;
bbd9b64e 5367
b51e974f 5368 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5369
9d74191a 5370 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5371
e46479f8 5372 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5373 ++vcpu->stat.insn_emulation;
1d2887e2 5374 if (r != EMULATION_OK) {
4005996e
AK		 5375 if (emulation_type & EMULTYPE_TRAP_UD)
5376 return EMULATE_FAIL;
991eebf9
GN		 5377 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5378 emulation_type))
bbd9b64e 5379 return EMULATE_DONE;
6d77dbfc
GN		 5380 if (emulation_type & EMULTYPE_SKIP)
5381 return EMULATE_FAIL;
5382 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5383 }
5384 }
5385
ba8afb6b 5386 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5387 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5388 if (ctxt->eflags & X86_EFLAGS_RF)
5389 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5390 return EMULATE_DONE;
5391 }
5392
1cb3f3ae
XG		 5393 if (retry_instruction(ctxt, cr2, emulation_type))
5394 return EMULATE_DONE;
5395
7ae441ea 5396 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5397 changes registers values during IO operation */
7ae441ea
GN		 5398 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5399 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5400 emulator_invalidate_register_cache(ctxt);
7ae441ea 5401 }
4d2179e1 5402
5cd21917 5403restart:
9d74191a 5404 r = x86_emulate_insn(ctxt);
bbd9b64e 5405
775fde86
JR		 5406 if (r == EMULATION_INTERCEPTED)
5407 return EMULATE_DONE;
5408
d2ddd1c4 5409 if (r == EMULATION_FAILED) {
991eebf9
GN		 5410 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5411 emulation_type))
c3cd7ffa
GN		 5412 return EMULATE_DONE;
5413
6d77dbfc 5414 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5415 }
5416
9d74191a 5417 if (ctxt->have_exception) {
d2ddd1c4 5418 r = EMULATE_DONE;
ef54bcfe
PB		 5419 if (inject_emulated_exception(vcpu))
5420 return r;
d2ddd1c4 5421 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5422 if (!vcpu->arch.pio.in) {
5423 /* FIXME: return into emulator if single-stepping. */
3457e419 5424 vcpu->arch.pio.count = 0;
0912c977 5425 } else {
7ae441ea 5426 writeback = false;
716d51ab
GN		 5427 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5428 }
ac0a48c3 5429 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5430 } else if (vcpu->mmio_needed) {
5431 if (!vcpu->mmio_is_write)
5432 writeback = false;
ac0a48c3 5433 r = EMULATE_USER_EXIT;
716d51ab 5434 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5435 } else if (r == EMULATION_RESTART)
5cd21917 5436 goto restart;
d2ddd1c4
GN		 5437 else
5438 r = EMULATE_DONE;
f850e2e6 5439
7ae441ea 5440 if (writeback) {
6addfc42 5441 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5442 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5443 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5444 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5445 if (r == EMULATE_DONE)
6addfc42 5446 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5447 if (!ctxt->have_exception ||
5448 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5449 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5450
5451 /*
5452 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5453 * do nothing, and it will be requested again as soon as
5454 * the shadow expires. But we still need to check here,
5455 * because POPF has no interrupt shadow.
5456 */
5457 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5458 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5459 } else
5460 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5461
5462 return r;
de7d789a 5463}
51d8b661 5464EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5465
cf8f70bf 5466int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5467{
cf8f70bf 5468 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5469 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5470 size, port, &val, 1);
cf8f70bf 5471 /* do not return to emulator after return from userspace */
7972995b 5472 vcpu->arch.pio.count = 0;
de7d789a
CO		 5473 return ret;
5474}
cf8f70bf 5475EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5476
8cfdc000
ZA		 5477static void tsc_bad(void *info)
5478{
0a3aee0d 5479 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5480}
5481
5482static void tsc_khz_changed(void *data)
c8076604 5483{
8cfdc000
ZA		 5484 struct cpufreq_freqs *freq = data;
5485 unsigned long khz = 0;
5486
5487 if (data)
5488 khz = freq->new;
5489 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5490 khz = cpufreq_quick_get(raw_smp_processor_id());
5491 if (!khz)
5492 khz = tsc_khz;
0a3aee0d 5493 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5494}
5495
c8076604
GH		 5496static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5497 void *data)
5498{
5499 struct cpufreq_freqs *freq = data;
5500 struct kvm *kvm;
5501 struct kvm_vcpu *vcpu;
5502 int i, send_ipi = 0;
5503
8cfdc000
ZA		 5504 /*
5505 * We allow guests to temporarily run on slowing clocks,
5506 * provided we notify them after, or to run on accelerating
5507 * clocks, provided we notify them before. Thus time never
5508 * goes backwards.
5509 *
5510 * However, we have a problem. We can't atomically update
5511 * the frequency of a given CPU from this function; it is
5512 * merely a notifier, which can be called from any CPU.
5513 * Changing the TSC frequency at arbitrary points in time
5514 * requires a recomputation of local variables related to
5515 * the TSC for each VCPU. We must flag these local variables
5516 * to be updated and be sure the update takes place with the
5517 * new frequency before any guests proceed.
5518 *
5519 * Unfortunately, the combination of hotplug CPU and frequency
5520 * change creates an intractable locking scenario; the order
5521 * of when these callouts happen is undefined with respect to
5522 * CPU hotplug, and they can race with each other. As such,
5523 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5524 * undefined; you can actually have a CPU frequency change take
5525 * place in between the computation of X and the setting of the
5526 * variable. To protect against this problem, all updates of
5527 * the per_cpu tsc_khz variable are done in an interrupt
5528 * protected IPI, and all callers wishing to update the value
5529 * must wait for a synchronous IPI to complete (which is trivial
5530 * if the caller is on the CPU already). This establishes the
5531 * necessary total order on variable updates.
5532 *
5533 * Note that because a guest time update may take place
5534 * anytime after the setting of the VCPU's request bit, the
5535 * correct TSC value must be set before the request. However,
5536 * to ensure the update actually makes it to any guest which
5537 * starts running in hardware virtualization between the set
5538 * and the acquisition of the spinlock, we must also ping the
5539 * CPU after setting the request bit.
5540 *
5541 */
5542
c8076604
GH		 5543 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5544 return 0;
5545 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5546 return 0;
8cfdc000
ZA		 5547
5548 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5549
2f303b74 5550 spin_lock(&kvm_lock);
c8076604 5551 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5552 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5553 if (vcpu->cpu != freq->cpu)
5554 continue;
c285545f 5555 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5556 if (vcpu->cpu != smp_processor_id())
8cfdc000 5557 send_ipi = 1;
c8076604
GH		 5558 }
5559 }
2f303b74 5560 spin_unlock(&kvm_lock);
c8076604
GH		 5561
5562 if (freq->old < freq->new && send_ipi) {
5563 /*
5564 * We upscale the frequency. Must make the guest
5565 * doesn't see old kvmclock values while running with
5566 * the new frequency, otherwise we risk the guest sees
5567 * time go backwards.
5568 *
5569 * In case we update the frequency for another cpu
5570 * (which might be in guest context) send an interrupt
5571 * to kick the cpu out of guest context. Next time
5572 * guest context is entered kvmclock will be updated,
5573 * so the guest will not see stale values.
5574 */
8cfdc000 5575 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5576 }
5577 return 0;
5578}
5579
5580static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5581 .notifier_call = kvmclock_cpufreq_notifier
5582};
5583
5584static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5585 unsigned long action, void *hcpu)
5586{
5587 unsigned int cpu = (unsigned long)hcpu;
5588
5589 switch (action) {
5590 case CPU_ONLINE:
5591 case CPU_DOWN_FAILED:
5592 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5593 break;
5594 case CPU_DOWN_PREPARE:
5595 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5596 break;
5597 }
5598 return NOTIFY_OK;
5599}
5600
5601static struct notifier_block kvmclock_cpu_notifier_block = {
5602 .notifier_call = kvmclock_cpu_notifier,
5603 .priority = -INT_MAX
c8076604
GH		 5604};
5605
b820cc0c
ZA		 5606static void kvm_timer_init(void)
5607{
5608 int cpu;
5609
c285545f 5610 max_tsc_khz = tsc_khz;
460dd42e
SB		 5611
5612 cpu_notifier_register_begin();
b820cc0c 5613 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5614#ifdef CONFIG_CPU_FREQ
5615 struct cpufreq_policy policy;
5616 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5617 cpu = get_cpu();
5618 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5619 if (policy.cpuinfo.max_freq)
5620 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5621 put_cpu();
c285545f 5622#endif
b820cc0c
ZA		 5623 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5624 CPUFREQ_TRANSITION_NOTIFIER);
5625 }
c285545f 5626 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5627 for_each_online_cpu(cpu)
5628 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5629
5630 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5631 cpu_notifier_register_done();
5632
b820cc0c
ZA		 5633}
5634
ff9d07a0
ZY		 5635static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5636
f5132b01 5637int kvm_is_in_guest(void)
ff9d07a0 5638{
086c9855 5639 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5640}
5641
5642static int kvm_is_user_mode(void)
5643{
5644 int user_mode = 3;
dcf46b94 5645
086c9855
AS		 5646 if (__this_cpu_read(current_vcpu))
5647 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5648
ff9d07a0
ZY		 5649 return user_mode != 0;
5650}
5651
5652static unsigned long kvm_get_guest_ip(void)
5653{
5654 unsigned long ip = 0;
dcf46b94 5655
086c9855
AS		 5656 if (__this_cpu_read(current_vcpu))
5657 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5658
ff9d07a0
ZY		 5659 return ip;
5660}
5661
5662static struct perf_guest_info_callbacks kvm_guest_cbs = {
5663 .is_in_guest = kvm_is_in_guest,
5664 .is_user_mode = kvm_is_user_mode,
5665 .get_guest_ip = kvm_get_guest_ip,
5666};
5667
5668void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5669{
086c9855 5670 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5671}
5672EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5673
5674void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5675{
086c9855 5676 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5677}
5678EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5679
ce88decf
XG		 5680static void kvm_set_mmio_spte_mask(void)
5681{
5682 u64 mask;
5683 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5684
5685 /*
5686 * Set the reserved bits and the present bit of an paging-structure
5687 * entry to generate page fault with PFER.RSV = 1.
5688 */
885032b9 5689 /* Mask the reserved physical address bits. */
d1431483 5690 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5691
5692 /* Bit 62 is always reserved for 32bit host. */
5693 mask |= 0x3ull << 62;
5694
5695 /* Set the present bit. */
ce88decf
XG		 5696 mask |= 1ull;
5697
5698#ifdef CONFIG_X86_64
5699 /*
5700 * If reserved bit is not supported, clear the present bit to disable
5701 * mmio page fault.
5702 */
5703 if (maxphyaddr == 52)
5704 mask &= ~1ull;
5705#endif
5706
5707 kvm_mmu_set_mmio_spte_mask(mask);
5708}
5709
16e8d74d
MT		 5710#ifdef CONFIG_X86_64
5711static void pvclock_gtod_update_fn(struct work_struct *work)
5712{
d828199e
MT		 5713 struct kvm *kvm;
5714
5715 struct kvm_vcpu *vcpu;
5716 int i;
5717
2f303b74 5718 spin_lock(&kvm_lock);
d828199e
MT		 5719 list_for_each_entry(kvm, &vm_list, vm_list)
5720 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5721 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5722 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5723 spin_unlock(&kvm_lock);
16e8d74d
MT		 5724}
5725
5726static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5727
5728/*
5729 * Notification about pvclock gtod data update.
5730 */
5731static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5732 void *priv)
5733{
5734 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5735 struct timekeeper *tk = priv;
5736
5737 update_pvclock_gtod(tk);
5738
5739 /* disable master clock if host does not trust, or does not
5740 * use, TSC clocksource
5741 */
5742 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5743 atomic_read(&kvm_guest_has_master_clock) != 0)
5744 queue_work(system_long_wq, &pvclock_gtod_work);
5745
5746 return 0;
5747}
5748
5749static struct notifier_block pvclock_gtod_notifier = {
5750 .notifier_call = pvclock_gtod_notify,
5751};
5752#endif
5753
f8c16bba 5754int kvm_arch_init(void *opaque)
043405e1 5755{
b820cc0c 5756 int r;
6b61edf7 5757 struct kvm_x86_ops *ops = opaque;
f8c16bba 5758
f8c16bba
ZX		 5759 if (kvm_x86_ops) {
5760 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5761 r = -EEXIST;
5762 goto out;
f8c16bba
ZX		 5763 }
5764
5765 if (!ops->cpu_has_kvm_support()) {
5766 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5767 r = -EOPNOTSUPP;
5768 goto out;
f8c16bba
ZX		 5769 }
5770 if (ops->disabled_by_bios()) {
5771 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5772 r = -EOPNOTSUPP;
5773 goto out;
f8c16bba
ZX		 5774 }
5775
013f6a5d
MT		 5776 r = -ENOMEM;
5777 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5778 if (!shared_msrs) {
5779 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5780 goto out;
5781 }
5782
97db56ce
AK		 5783 r = kvm_mmu_module_init();
5784 if (r)
013f6a5d 5785 goto out_free_percpu;
97db56ce 5786
ce88decf 5787 kvm_set_mmio_spte_mask();
97db56ce 5788
f8c16bba 5789 kvm_x86_ops = ops;
920c8377
PB		 5790 kvm_init_msr_list();
5791
7b52345e 5792 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5793 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5794
b820cc0c 5795 kvm_timer_init();
c8076604 5796
ff9d07a0
ZY		 5797 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5798
2acf923e
DC		 5799 if (cpu_has_xsave)
5800 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5801
c5cc421b 5802 kvm_lapic_init();
16e8d74d
MT		 5803#ifdef CONFIG_X86_64
5804 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5805#endif
5806
f8c16bba 5807 return 0;
56c6d28a 5808
013f6a5d
MT		 5809out_free_percpu:
5810 free_percpu(shared_msrs);
56c6d28a 5811out:
56c6d28a 5812 return r;
043405e1 5813}
8776e519 5814
f8c16bba
ZX		 5815void kvm_arch_exit(void)
5816{
ff9d07a0
ZY		 5817 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5818
888d256e
JK		 5819 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5820 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5821 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5822 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5823#ifdef CONFIG_X86_64
5824 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5825#endif
f8c16bba 5826 kvm_x86_ops = NULL;
56c6d28a 5827 kvm_mmu_module_exit();
013f6a5d 5828 free_percpu(shared_msrs);
56c6d28a 5829}
f8c16bba 5830
8776e519
HB		 5831int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5832{
5833 ++vcpu->stat.halt_exits;
5834 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5835 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5836 return 1;
5837 } else {
5838 vcpu->run->exit_reason = KVM_EXIT_HLT;
5839 return 0;
5840 }
5841}
5842EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5843
55cd8e5a
GN		 5844int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5845{
5846 u64 param, ingpa, outgpa, ret;
5847 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5848 bool fast, longmode;
55cd8e5a
GN		 5849
5850 /*
5851 * hypercall generates UD from non zero cpl and real mode
5852 * per HYPER-V spec
5853 */
3eeb3288 5854 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5855 kvm_queue_exception(vcpu, UD_VECTOR);
5856 return 0;
5857 }
5858
a449c7aa 5859 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5860
5861 if (!longmode) {
ccd46936
GN		 5862 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5863 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5864 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5865 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5866 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5867 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5868 }
5869#ifdef CONFIG_X86_64
5870 else {
5871 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5872 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5873 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5874 }
5875#endif
5876
5877 code = param & 0xffff;
5878 fast = (param >> 16) & 0x1;
5879 rep_cnt = (param >> 32) & 0xfff;
5880 rep_idx = (param >> 48) & 0xfff;
5881
5882 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5883
c25bc163
GN		 5884 switch (code) {
5885 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5886 kvm_vcpu_on_spin(vcpu);
5887 break;
5888 default:
5889 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5890 break;
5891 }
55cd8e5a
GN		 5892
5893 ret = res | (((u64)rep_done & 0xfff) << 32);
5894 if (longmode) {
5895 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5896 } else {
5897 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5898 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5899 }
5900
5901 return 1;
5902}
5903
6aef266c
SV		 5904/*
5905 * kvm_pv_kick_cpu_op: Kick a vcpu.
5906 *
5907 * @apicid - apicid of vcpu to be kicked.
5908 */
5909static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5910{
24d2166b 5911 struct kvm_lapic_irq lapic_irq;
6aef266c 5912
24d2166b
R		 5913 lapic_irq.shorthand = 0;
5914 lapic_irq.dest_mode = 0;
5915 lapic_irq.dest_id = apicid;
6aef266c 5916
24d2166b
R		 5917 lapic_irq.delivery_mode = APIC_DM_REMRD;
5918 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5919}
5920
8776e519
HB		 5921int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5922{
5923 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5924 int op_64_bit, r = 1;
8776e519 5925
55cd8e5a
GN		 5926 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5927 return kvm_hv_hypercall(vcpu);
5928
5fdbf976
MT		 5929 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5930 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5931 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5932 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5933 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5934
229456fc 5935 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5936
a449c7aa
NA		 5937 op_64_bit = is_64_bit_mode(vcpu);
5938 if (!op_64_bit) {
8776e519
HB		 5939 nr &= 0xFFFFFFFF;
5940 a0 &= 0xFFFFFFFF;
5941 a1 &= 0xFFFFFFFF;
5942 a2 &= 0xFFFFFFFF;
5943 a3 &= 0xFFFFFFFF;
5944 }
5945
07708c4a
JK		 5946 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5947 ret = -KVM_EPERM;
5948 goto out;
5949 }
5950
8776e519 5951 switch (nr) {
b93463aa
AK		 5952 case KVM_HC_VAPIC_POLL_IRQ:
5953 ret = 0;
5954 break;
6aef266c
SV		 5955 case KVM_HC_KICK_CPU:
5956 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5957 ret = 0;
5958 break;
8776e519
HB		 5959 default:
5960 ret = -KVM_ENOSYS;
5961 break;
5962 }
07708c4a 5963out:
a449c7aa
NA		 5964 if (!op_64_bit)
5965 ret = (u32)ret;
5fdbf976 5966 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5967 ++vcpu->stat.hypercalls;
2f333bcb 5968 return r;
8776e519
HB		 5969}
5970EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5971
b6785def 5972static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5973{
d6aa1000 5974 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5975 char instruction[3];
5fdbf976 5976 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5977
8776e519 5978 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5979
9d74191a 5980 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5981}
5982
b6c7a5dc
HB		 5983/*
5984 * Check if userspace requested an interrupt window, and that the
5985 * interrupt window is open.
5986 *
5987 * No need to exit to userspace if we already have an interrupt queued.
5988 */
851ba692 5989static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5990{
8061823a 5991 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5992 vcpu->run->request_interrupt_window &&
5df56646 5993 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5994}
5995
851ba692 5996static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5997{
851ba692
AK		 5998 struct kvm_run *kvm_run = vcpu->run;
5999
91586a3b 6000 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6001 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6002 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6003 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6004 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6005 else
b6c7a5dc 6006 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6007 kvm_arch_interrupt_allowed(vcpu) &&
6008 !kvm_cpu_has_interrupt(vcpu) &&
6009 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6010}
6011
95ba8273
GN		 6012static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6013{
6014 int max_irr, tpr;
6015
6016 if (!kvm_x86_ops->update_cr8_intercept)
6017 return;
6018
88c808fd
AK		 6019 if (!vcpu->arch.apic)
6020 return;
6021
8db3baa2
GN		 6022 if (!vcpu->arch.apic->vapic_addr)
6023 max_irr = kvm_lapic_find_highest_irr(vcpu);
6024 else
6025 max_irr = -1;
95ba8273
GN		 6026
6027 if (max_irr != -1)
6028 max_irr >>= 4;
6029
6030 tpr = kvm_lapic_get_cr8(vcpu);
6031
6032 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6033}
6034
b6b8a145 6035static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6036{
b6b8a145
JK		 6037 int r;
6038
95ba8273 6039 /* try to reinject previous events if any */
b59bb7bd 6040 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6041 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6042 vcpu->arch.exception.has_error_code,
6043 vcpu->arch.exception.error_code);
d6e8c854
NA		 6044
6045 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6046 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6047 X86_EFLAGS_RF);
6048
6bdf0662
NA		 6049 if (vcpu->arch.exception.nr == DB_VECTOR &&
6050 (vcpu->arch.dr7 & DR7_GD)) {
6051 vcpu->arch.dr7 &= ~DR7_GD;
6052 kvm_update_dr7(vcpu);
6053 }
6054
b59bb7bd
GN		 6055 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6056 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6057 vcpu->arch.exception.error_code,
6058 vcpu->arch.exception.reinject);
b6b8a145 6059 return 0;
b59bb7bd
GN		 6060 }
6061
95ba8273
GN		 6062 if (vcpu->arch.nmi_injected) {
6063 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6064 return 0;
95ba8273
GN		 6065 }
6066
6067 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6068 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6069 return 0;
6070 }
6071
6072 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6073 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6074 if (r != 0)
6075 return r;
95ba8273
GN		 6076 }
6077
6078 /* try to inject new event if pending */
6079 if (vcpu->arch.nmi_pending) {
6080 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6081 --vcpu->arch.nmi_pending;
95ba8273
GN		 6082 vcpu->arch.nmi_injected = true;
6083 kvm_x86_ops->set_nmi(vcpu);
6084 }
c7c9c56c 6085 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6086 /*
6087 * Because interrupts can be injected asynchronously, we are
6088 * calling check_nested_events again here to avoid a race condition.
6089 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6090 * proposal and current concerns. Perhaps we should be setting
6091 * KVM_REQ_EVENT only on certain events and not unconditionally?
6092 */
6093 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6094 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6095 if (r != 0)
6096 return r;
6097 }
95ba8273 6098 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6099 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6100 false);
6101 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6102 }
6103 }
b6b8a145 6104 return 0;
95ba8273
GN		 6105}
6106
7460fb4a
AK		 6107static void process_nmi(struct kvm_vcpu *vcpu)
6108{
6109 unsigned limit = 2;
6110
6111 /*
6112 * x86 is limited to one NMI running, and one NMI pending after it.
6113 * If an NMI is already in progress, limit further NMIs to just one.
6114 * Otherwise, allow two (and we'll inject the first one immediately).
6115 */
6116 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6117 limit = 1;
6118
6119 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6120 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6121 kvm_make_request(KVM_REQ_EVENT, vcpu);
6122}
6123
3d81bc7e 6124static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6125{
6126 u64 eoi_exit_bitmap[4];
cf9e65b7 6127 u32 tmr[8];
c7c9c56c 6128
3d81bc7e
YZ		 6129 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6130 return;
c7c9c56c
YZ		 6131
6132 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6133 memset(tmr, 0, 32);
c7c9c56c 6134
cf9e65b7 6135 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6136 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6137 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6138}
6139
a70656b6
RK		 6140static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6141{
6142 ++vcpu->stat.tlb_flush;
6143 kvm_x86_ops->tlb_flush(vcpu);
6144}
6145
4256f43f
TC		 6146void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6147{
c24ae0dc
TC		 6148 struct page *page = NULL;
6149
f439ed27
PB		 6150 if (!irqchip_in_kernel(vcpu->kvm))
6151 return;
6152
4256f43f
TC		 6153 if (!kvm_x86_ops->set_apic_access_page_addr)
6154 return;
6155
c24ae0dc
TC		 6156 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6157 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6158
6159 /*
6160 * Do not pin apic access page in memory, the MMU notifier
6161 * will call us again if it is migrated or swapped out.
6162 */
6163 put_page(page);
4256f43f
TC		 6164}
6165EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6166
fe71557a
TC		 6167void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6168 unsigned long address)
6169{
c24ae0dc
TC		 6170 /*
6171 * The physical address of apic access page is stored in the VMCS.
6172 * Update it when it becomes invalid.
6173 */
6174 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6175 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6176}
6177
9357d939
TY		 6178/*
6179 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6180 * exiting to the userspace. Otherwise, the value will be returned to the
6181 * userspace.
6182 */
851ba692 6183static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6184{
6185 int r;
6a8b1d13 6186 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6187 vcpu->run->request_interrupt_window;
730dca42 6188 bool req_immediate_exit = false;
b6c7a5dc 6189
3e007509 6190 if (vcpu->requests) {
a8eeb04a 6191 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6192 kvm_mmu_unload(vcpu);
a8eeb04a 6193 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6194 __kvm_migrate_timers(vcpu);
d828199e
MT		 6195 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6196 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6197 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6198 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6199 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6200 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6201 if (unlikely(r))
6202 goto out;
6203 }
a8eeb04a 6204 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6205 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6206 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6207 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6208 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6209 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6210 r = 0;
6211 goto out;
6212 }
a8eeb04a 6213 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6214 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6215 r = 0;
6216 goto out;
6217 }
a8eeb04a 6218 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6219 vcpu->fpu_active = 0;
6220 kvm_x86_ops->fpu_deactivate(vcpu);
6221 }
af585b92
GN		 6222 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6223 /* Page is swapped out. Do synthetic halt */
6224 vcpu->arch.apf.halted = true;
6225 r = 1;
6226 goto out;
6227 }
c9aaa895
GC		 6228 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6229 record_steal_time(vcpu);
7460fb4a
AK		 6230 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6231 process_nmi(vcpu);
f5132b01
GN		 6232 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6233 kvm_handle_pmu_event(vcpu);
6234 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6235 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6236 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6237 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6238 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6239 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6240 }
b93463aa 6241
b463a6f7 6242 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6243 kvm_apic_accept_events(vcpu);
6244 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6245 r = 1;
6246 goto out;
6247 }
6248
b6b8a145
JK		 6249 if (inject_pending_event(vcpu, req_int_win) != 0)
6250 req_immediate_exit = true;
b463a6f7 6251 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6252 else if (vcpu->arch.nmi_pending)
c9a7953f 6253 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6254 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6255 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6256
6257 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6258 /*
6259 * Update architecture specific hints for APIC
6260 * virtual interrupt delivery.
6261 */
6262 if (kvm_x86_ops->hwapic_irr_update)
6263 kvm_x86_ops->hwapic_irr_update(vcpu,
6264 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6265 update_cr8_intercept(vcpu);
6266 kvm_lapic_sync_to_vapic(vcpu);
6267 }
6268 }
6269
d8368af8
AK		 6270 r = kvm_mmu_reload(vcpu);
6271 if (unlikely(r)) {
d905c069 6272 goto cancel_injection;
d8368af8
AK		 6273 }
6274
b6c7a5dc
HB		 6275 preempt_disable();
6276
6277 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6278 if (vcpu->fpu_active)
6279 kvm_load_guest_fpu(vcpu);
2acf923e 6280 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6281
6b7e2d09
XG		 6282 vcpu->mode = IN_GUEST_MODE;
6283
01b71917
MT		 6284 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6285
6b7e2d09
XG		 6286 /* We should set ->mode before check ->requests,
6287 * see the comment in make_all_cpus_request.
6288 */
01b71917 6289 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6290
d94e1dc9 6291 local_irq_disable();
32f88400 6292
6b7e2d09 6293 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6294 || need_resched() || signal_pending(current)) {
6b7e2d09 6295 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6296 smp_wmb();
6c142801
AK		 6297 local_irq_enable();
6298 preempt_enable();
01b71917 6299 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6300 r = 1;
d905c069 6301 goto cancel_injection;
6c142801
AK		 6302 }
6303
d6185f20
NHE		 6304 if (req_immediate_exit)
6305 smp_send_reschedule(vcpu->cpu);
6306
b6c7a5dc
HB		 6307 kvm_guest_enter();
6308
42dbaa5a 6309 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6310 set_debugreg(0, 7);
6311 set_debugreg(vcpu->arch.eff_db[0], 0);
6312 set_debugreg(vcpu->arch.eff_db[1], 1);
6313 set_debugreg(vcpu->arch.eff_db[2], 2);
6314 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6315 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6316 }
b6c7a5dc 6317
229456fc 6318 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6319 wait_lapic_expire(vcpu);
851ba692 6320 kvm_x86_ops->run(vcpu);
b6c7a5dc 6321
c77fb5fe
PB		 6322 /*
6323 * Do this here before restoring debug registers on the host. And
6324 * since we do this before handling the vmexit, a DR access vmexit
6325 * can (a) read the correct value of the debug registers, (b) set
6326 * KVM_DEBUGREG_WONT_EXIT again.
6327 */
6328 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6329 int i;
6330
6331 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6332 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6333 for (i = 0; i < KVM_NR_DB_REGS; i++)
6334 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6335 }
6336
24f1e32c
FW		 6337 /*
6338 * If the guest has used debug registers, at least dr7
6339 * will be disabled while returning to the host.
6340 * If we don't have active breakpoints in the host, we don't
6341 * care about the messed up debug address registers. But if
6342 * we have some of them active, restore the old state.
6343 */
59d8eb53 6344 if (hw_breakpoint_active())
24f1e32c 6345 hw_breakpoint_restore();
42dbaa5a 6346
886b470c
MT		 6347 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6348 native_read_tsc());
1d5f066e 6349
6b7e2d09 6350 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6351 smp_wmb();
a547c6db
YZ		 6352
6353 /* Interrupt is enabled by handle_external_intr() */
6354 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6355
6356 ++vcpu->stat.exits;
6357
6358 /*
6359 * We must have an instruction between local_irq_enable() and
6360 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6361 * the interrupt shadow. The stat.exits increment will do nicely.
6362 * But we need to prevent reordering, hence this barrier():
6363 */
6364 barrier();
6365
6366 kvm_guest_exit();
6367
6368 preempt_enable();
6369
f656ce01 6370 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6371
b6c7a5dc
HB		 6372 /*
6373 * Profile KVM exit RIPs:
6374 */
6375 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6376 unsigned long rip = kvm_rip_read(vcpu);
6377 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6378 }
6379
cc578287
ZA		 6380 if (unlikely(vcpu->arch.tsc_always_catchup))
6381 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6382
5cfb1d5a
MT		 6383 if (vcpu->arch.apic_attention)
6384 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6385
851ba692 6386 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6387 return r;
6388
6389cancel_injection:
6390 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6391 if (unlikely(vcpu->arch.apic_attention))
6392 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6393out:
6394 return r;
6395}
b6c7a5dc 6396
09cec754 6397
851ba692 6398static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6399{
6400 int r;
f656ce01 6401 struct kvm *kvm = vcpu->kvm;
d7690175 6402
f656ce01 6403 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6404
6405 r = 1;
6406 while (r > 0) {
af585b92
GN		 6407 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6408 !vcpu->arch.apf.halted)
851ba692 6409 r = vcpu_enter_guest(vcpu);
d7690175 6410 else {
f656ce01 6411 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6412 kvm_vcpu_block(vcpu);
f656ce01 6413 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6414 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6415 kvm_apic_accept_events(vcpu);
09cec754
GN		 6416 switch(vcpu->arch.mp_state) {
6417 case KVM_MP_STATE_HALTED:
6aef266c 6418 vcpu->arch.pv.pv_unhalted = false;
d7690175 6419 vcpu->arch.mp_state =
09cec754
GN		 6420 KVM_MP_STATE_RUNNABLE;
6421 case KVM_MP_STATE_RUNNABLE:
af585b92 6422 vcpu->arch.apf.halted = false;
09cec754 6423 break;
66450a21
JK		 6424 case KVM_MP_STATE_INIT_RECEIVED:
6425 break;
09cec754
GN		 6426 default:
6427 r = -EINTR;
6428 break;
6429 }
6430 }
d7690175
MT		 6431 }
6432
09cec754
GN		 6433 if (r <= 0)
6434 break;
6435
6436 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6437 if (kvm_cpu_has_pending_timer(vcpu))
6438 kvm_inject_pending_timer_irqs(vcpu);
6439
851ba692 6440 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6441 r = -EINTR;
851ba692 6442 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6443 ++vcpu->stat.request_irq_exits;
6444 }
af585b92
GN		 6445
6446 kvm_check_async_pf_completion(vcpu);
6447
09cec754
GN		 6448 if (signal_pending(current)) {
6449 r = -EINTR;
851ba692 6450 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6451 ++vcpu->stat.signal_exits;
6452 }
6453 if (need_resched()) {
f656ce01 6454 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6455 cond_resched();
f656ce01 6456 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6457 }
b6c7a5dc
HB		 6458 }
6459
f656ce01 6460 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6461
6462 return r;
6463}
6464
716d51ab
GN		 6465static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6466{
6467 int r;
6468 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6469 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6470 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6471 if (r != EMULATE_DONE)
6472 return 0;
6473 return 1;
6474}
6475
6476static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6477{
6478 BUG_ON(!vcpu->arch.pio.count);
6479
6480 return complete_emulated_io(vcpu);
6481}
6482
f78146b0
AK		 6483/*
6484 * Implements the following, as a state machine:
6485 *
6486 * read:
6487 * for each fragment
87da7e66
XG		 6488 * for each mmio piece in the fragment
6489 * write gpa, len
6490 * exit
6491 * copy data
f78146b0
AK		 6492 * execute insn
6493 *
6494 * write:
6495 * for each fragment
87da7e66
XG		 6496 * for each mmio piece in the fragment
6497 * write gpa, len
6498 * copy data
6499 * exit
f78146b0 6500 */
716d51ab 6501static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6502{
6503 struct kvm_run *run = vcpu->run;
f78146b0 6504 struct kvm_mmio_fragment *frag;
87da7e66 6505 unsigned len;
5287f194 6506
716d51ab 6507 BUG_ON(!vcpu->mmio_needed);
5287f194 6508
716d51ab 6509 /* Complete previous fragment */
87da7e66
XG		 6510 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6511 len = min(8u, frag->len);
716d51ab 6512 if (!vcpu->mmio_is_write)
87da7e66
XG		 6513 memcpy(frag->data, run->mmio.data, len);
6514
6515 if (frag->len <= 8) {
6516 /* Switch to the next fragment. */
6517 frag++;
6518 vcpu->mmio_cur_fragment++;
6519 } else {
6520 /* Go forward to the next mmio piece. */
6521 frag->data += len;
6522 frag->gpa += len;
6523 frag->len -= len;
6524 }
6525
a08d3b3b 6526 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6527 vcpu->mmio_needed = 0;
0912c977
PB		 6528
6529 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6530 if (vcpu->mmio_is_write)
716d51ab
GN		 6531 return 1;
6532 vcpu->mmio_read_completed = 1;
6533 return complete_emulated_io(vcpu);
6534 }
87da7e66 6535
716d51ab
GN		 6536 run->exit_reason = KVM_EXIT_MMIO;
6537 run->mmio.phys_addr = frag->gpa;
6538 if (vcpu->mmio_is_write)
87da7e66
XG		 6539 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6540 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6541 run->mmio.is_write = vcpu->mmio_is_write;
6542 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6543 return 0;
5287f194
AK		 6544}
6545
716d51ab 6546
b6c7a5dc
HB		 6547int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6548{
6549 int r;
6550 sigset_t sigsaved;
6551
e5c30142
AK		 6552 if (!tsk_used_math(current) && init_fpu(current))
6553 return -ENOMEM;
6554
ac9f6dc0
AK		 6555 if (vcpu->sigset_active)
6556 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6557
a4535290 6558 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6559 kvm_vcpu_block(vcpu);
66450a21 6560 kvm_apic_accept_events(vcpu);
d7690175 6561 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6562 r = -EAGAIN;
6563 goto out;
b6c7a5dc
HB		 6564 }
6565
b6c7a5dc 6566 /* re-sync apic's tpr */
eea1cff9
AP		 6567 if (!irqchip_in_kernel(vcpu->kvm)) {
6568 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6569 r = -EINVAL;
6570 goto out;
6571 }
6572 }
b6c7a5dc 6573
716d51ab
GN		 6574 if (unlikely(vcpu->arch.complete_userspace_io)) {
6575 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6576 vcpu->arch.complete_userspace_io = NULL;
6577 r = cui(vcpu);
6578 if (r <= 0)
6579 goto out;
6580 } else
6581 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6582
851ba692 6583 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6584
6585out:
f1d86e46 6586 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6587 if (vcpu->sigset_active)
6588 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6589
b6c7a5dc
HB		 6590 return r;
6591}
6592
6593int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6594{
7ae441ea
GN		 6595 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6596 /*
6597 * We are here if userspace calls get_regs() in the middle of
6598 * instruction emulation. Registers state needs to be copied
4a969980 6599 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6600 * that usually, but some bad designed PV devices (vmware
6601 * backdoor interface) need this to work
6602 */
dd856efa 6603 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6604 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6605 }
5fdbf976
MT		 6606 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6607 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6608 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6609 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6610 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6611 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6612 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6613 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6614#ifdef CONFIG_X86_64
5fdbf976
MT		 6615 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6616 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6617 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6618 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6619 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6620 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6621 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6622 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6623#endif
6624
5fdbf976 6625 regs->rip = kvm_rip_read(vcpu);
91586a3b 6626 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6627
b6c7a5dc
HB		 6628 return 0;
6629}
6630
6631int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6632{
7ae441ea
GN		 6633 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6634 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6635
5fdbf976
MT		 6636 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6637 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6638 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6639 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6640 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6641 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6642 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6643 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6644#ifdef CONFIG_X86_64
5fdbf976
MT		 6645 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6646 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6647 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6648 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6649 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6650 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6651 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6652 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6653#endif
6654
5fdbf976 6655 kvm_rip_write(vcpu, regs->rip);
91586a3b 6656 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6657
b4f14abd
JK		 6658 vcpu->arch.exception.pending = false;
6659
3842d135
AK		 6660 kvm_make_request(KVM_REQ_EVENT, vcpu);
6661
b6c7a5dc
HB		 6662 return 0;
6663}
6664
b6c7a5dc
HB		 6665void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6666{
6667 struct kvm_segment cs;
6668
3e6e0aab 6669 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6670 *db = cs.db;
6671 *l = cs.l;
6672}
6673EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6674
6675int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6676 struct kvm_sregs *sregs)
6677{
89a27f4d 6678 struct desc_ptr dt;
b6c7a5dc 6679
3e6e0aab
GT		 6680 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6681 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6682 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6683 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6684 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6685 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6686
3e6e0aab
GT		 6687 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6688 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6689
6690 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6691 sregs->idt.limit = dt.size;
6692 sregs->idt.base = dt.address;
b6c7a5dc 6693 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6694 sregs->gdt.limit = dt.size;
6695 sregs->gdt.base = dt.address;
b6c7a5dc 6696
4d4ec087 6697 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6698 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6699 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6700 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6701 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6702 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6703 sregs->apic_base = kvm_get_apic_base(vcpu);
6704
923c61bb 6705 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6706
36752c9b 6707 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6708 set_bit(vcpu->arch.interrupt.nr,
6709 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6710
b6c7a5dc
HB		 6711 return 0;
6712}
6713
62d9f0db
MT		 6714int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6715 struct kvm_mp_state *mp_state)
6716{
66450a21 6717 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6718 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6719 vcpu->arch.pv.pv_unhalted)
6720 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6721 else
6722 mp_state->mp_state = vcpu->arch.mp_state;
6723
62d9f0db
MT		 6724 return 0;
6725}
6726
6727int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6728 struct kvm_mp_state *mp_state)
6729{
66450a21
JK		 6730 if (!kvm_vcpu_has_lapic(vcpu) &&
6731 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6732 return -EINVAL;
6733
6734 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6735 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6736 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6737 } else
6738 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6739 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6740 return 0;
6741}
6742
7f3d35fd
KW		 6743int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6744 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6745{
9d74191a 6746 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6747 int ret;
e01c2426 6748
8ec4722d 6749 init_emulate_ctxt(vcpu);
c697518a 6750
7f3d35fd 6751 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6752 has_error_code, error_code);
c697518a 6753
c697518a 6754 if (ret)
19d04437 6755 return EMULATE_FAIL;
37817f29 6756
9d74191a
TY		 6757 kvm_rip_write(vcpu, ctxt->eip);
6758 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6759 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6760 return EMULATE_DONE;
37817f29
IE		 6761}
6762EXPORT_SYMBOL_GPL(kvm_task_switch);
6763
b6c7a5dc
HB		 6764int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6765 struct kvm_sregs *sregs)
6766{
58cb628d 6767 struct msr_data apic_base_msr;
b6c7a5dc 6768 int mmu_reset_needed = 0;
63f42e02 6769 int pending_vec, max_bits, idx;
89a27f4d 6770 struct desc_ptr dt;
b6c7a5dc 6771
6d1068b3
PM		 6772 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6773 return -EINVAL;
6774
89a27f4d
GN		 6775 dt.size = sregs->idt.limit;
6776 dt.address = sregs->idt.base;
b6c7a5dc 6777 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6778 dt.size = sregs->gdt.limit;
6779 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6780 kvm_x86_ops->set_gdt(vcpu, &dt);
6781
ad312c7c 6782 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6783 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6784 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6785 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6786
2d3ad1f4 6787 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6788
f6801dff 6789 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6790 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6791 apic_base_msr.data = sregs->apic_base;
6792 apic_base_msr.host_initiated = true;
6793 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6794
4d4ec087 6795 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6796 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6797 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6798
fc78f519 6799 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6800 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6801 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6802 kvm_update_cpuid(vcpu);
63f42e02
XG		 6803
6804 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6805 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6806 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6807 mmu_reset_needed = 1;
6808 }
63f42e02 6809 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6810
6811 if (mmu_reset_needed)
6812 kvm_mmu_reset_context(vcpu);
6813
a50abc3b 6814 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6815 pending_vec = find_first_bit(
6816 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6817 if (pending_vec < max_bits) {
66fd3f7f 6818 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6819 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6820 }
6821
3e6e0aab
GT		 6822 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6823 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6824 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6825 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6826 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6827 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6828
3e6e0aab
GT		 6829 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6830 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6831
5f0269f5
ME		 6832 update_cr8_intercept(vcpu);
6833
9c3e4aab 6834 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6835 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6836 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6837 !is_protmode(vcpu))
9c3e4aab
MT		 6838 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6839
3842d135
AK		 6840 kvm_make_request(KVM_REQ_EVENT, vcpu);
6841
b6c7a5dc
HB		 6842 return 0;
6843}
6844
d0bfb940
JK		 6845int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6846 struct kvm_guest_debug *dbg)
b6c7a5dc 6847{
355be0b9 6848 unsigned long rflags;
ae675ef0 6849 int i, r;
b6c7a5dc 6850
4f926bf2
JK		 6851 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6852 r = -EBUSY;
6853 if (vcpu->arch.exception.pending)
2122ff5e 6854 goto out;
4f926bf2
JK		 6855 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6856 kvm_queue_exception(vcpu, DB_VECTOR);
6857 else
6858 kvm_queue_exception(vcpu, BP_VECTOR);
6859 }
6860
91586a3b
JK		 6861 /*
6862 * Read rflags as long as potentially injected trace flags are still
6863 * filtered out.
6864 */
6865 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6866
6867 vcpu->guest_debug = dbg->control;
6868 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6869 vcpu->guest_debug = 0;
6870
6871 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6872 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6873 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6874 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6875 } else {
6876 for (i = 0; i < KVM_NR_DB_REGS; i++)
6877 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6878 }
c8639010 6879 kvm_update_dr7(vcpu);
ae675ef0 6880
f92653ee
JK		 6881 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6882 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6883 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6884
91586a3b
JK		 6885 /*
6886 * Trigger an rflags update that will inject or remove the trace
6887 * flags.
6888 */
6889 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6890
c8639010 6891 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6892
4f926bf2 6893 r = 0;
d0bfb940 6894
2122ff5e 6895out:
b6c7a5dc
HB		 6896
6897 return r;
6898}
6899
8b006791
ZX		 6900/*
6901 * Translate a guest virtual address to a guest physical address.
6902 */
6903int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6904 struct kvm_translation *tr)
6905{
6906 unsigned long vaddr = tr->linear_address;
6907 gpa_t gpa;
f656ce01 6908 int idx;
8b006791 6909
f656ce01 6910 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6911 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6912 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6913 tr->physical_address = gpa;
6914 tr->valid = gpa != UNMAPPED_GVA;
6915 tr->writeable = 1;
6916 tr->usermode = 0;
8b006791
ZX		 6917
6918 return 0;
6919}
6920
d0752060
HB		 6921int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6922{
98918833
SY		 6923 struct i387_fxsave_struct *fxsave =
6924 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6925
d0752060
HB		 6926 memcpy(fpu->fpr, fxsave->st_space, 128);
6927 fpu->fcw = fxsave->cwd;
6928 fpu->fsw = fxsave->swd;
6929 fpu->ftwx = fxsave->twd;
6930 fpu->last_opcode = fxsave->fop;
6931 fpu->last_ip = fxsave->rip;
6932 fpu->last_dp = fxsave->rdp;
6933 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6934
d0752060
HB		 6935 return 0;
6936}
6937
6938int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6939{
98918833
SY		 6940 struct i387_fxsave_struct *fxsave =
6941 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6942
d0752060
HB		 6943 memcpy(fxsave->st_space, fpu->fpr, 128);
6944 fxsave->cwd = fpu->fcw;
6945 fxsave->swd = fpu->fsw;
6946 fxsave->twd = fpu->ftwx;
6947 fxsave->fop = fpu->last_opcode;
6948 fxsave->rip = fpu->last_ip;
6949 fxsave->rdp = fpu->last_dp;
6950 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6951
d0752060
HB		 6952 return 0;
6953}
6954
10ab25cd 6955int fx_init(struct kvm_vcpu *vcpu)
d0752060 6956{
10ab25cd
JK		 6957 int err;
6958
6959 err = fpu_alloc(&vcpu->arch.guest_fpu);
6960 if (err)
6961 return err;
6962
98918833 6963 fpu_finit(&vcpu->arch.guest_fpu);
df1daba7
PB		 6964 if (cpu_has_xsaves)
6965 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
6966 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 6967
2acf923e
DC		 6968 /*
6969 * Ensure guest xcr0 is valid for loading
6970 */
6971 vcpu->arch.xcr0 = XSTATE_FP;
6972
ad312c7c 6973 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6974
6975 return 0;
d0752060
HB		 6976}
6977EXPORT_SYMBOL_GPL(fx_init);
6978
98918833
SY		 6979static void fx_free(struct kvm_vcpu *vcpu)
6980{
6981 fpu_free(&vcpu->arch.guest_fpu);
6982}
6983
d0752060
HB		 6984void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6985{
2608d7a1 6986 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6987 return;
6988
2acf923e
DC		 6989 /*
6990 * Restore all possible states in the guest,
6991 * and assume host would use all available bits.
6992 * Guest xcr0 would be loaded later.
6993 */
6994 kvm_put_guest_xcr0(vcpu);
d0752060 6995 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6996 __kernel_fpu_begin();
98918833 6997 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6998 trace_kvm_fpu(1);
d0752060 6999}
d0752060
HB		 7000
7001void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7002{
2acf923e
DC		 7003 kvm_put_guest_xcr0(vcpu);
7004
d0752060
HB		 7005 if (!vcpu->guest_fpu_loaded)
7006 return;
7007
7008 vcpu->guest_fpu_loaded = 0;
98918833 7009 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7010 __kernel_fpu_end();
f096ed85 7011 ++vcpu->stat.fpu_reload;
a8eeb04a 7012 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 7013 trace_kvm_fpu(0);
d0752060 7014}
e9b11c17
ZX		 7015
7016void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7017{
12f9a48f 7018 kvmclock_reset(vcpu);
7f1ea208 7019
f5f48ee1 7020 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7021 fx_free(vcpu);
e9b11c17
ZX		 7022 kvm_x86_ops->vcpu_free(vcpu);
7023}
7024
7025struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7026 unsigned int id)
7027{
6755bae8
ZA		 7028 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7029 printk_once(KERN_WARNING
7030 "kvm: SMP vm created on host with unstable TSC; "
7031 "guest TSC will not be reliable\n");
26e5215f
AK		 7032 return kvm_x86_ops->vcpu_create(kvm, id);
7033}
e9b11c17 7034
26e5215f
AK		 7035int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7036{
7037 int r;
e9b11c17 7038
0bed3b56 7039 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7040 r = vcpu_load(vcpu);
7041 if (r)
7042 return r;
57f252f2 7043 kvm_vcpu_reset(vcpu);
8a3c1a33 7044 kvm_mmu_setup(vcpu);
e9b11c17 7045 vcpu_put(vcpu);
e9b11c17 7046
26e5215f 7047 return r;
e9b11c17
ZX		 7048}
7049
42897d86
MT		 7050int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7051{
7052 int r;
8fe8ab46 7053 struct msr_data msr;
332967a3 7054 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 7055
7056 r = vcpu_load(vcpu);
7057 if (r)
7058 return r;
8fe8ab46
WA		 7059 msr.data = 0x0;
7060 msr.index = MSR_IA32_TSC;
7061 msr.host_initiated = true;
7062 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7063 vcpu_put(vcpu);
7064
332967a3
AJ		 7065 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7066 KVMCLOCK_SYNC_PERIOD);
7067
42897d86
MT		 7068 return r;
7069}
7070
d40ccc62 7071void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7072{
9fc77441 7073 int r;
344d9588
GN		 7074 vcpu->arch.apf.msr_val = 0;
7075
9fc77441
MT		 7076 r = vcpu_load(vcpu);
7077 BUG_ON(r);
e9b11c17
ZX		 7078 kvm_mmu_unload(vcpu);
7079 vcpu_put(vcpu);
7080
98918833 7081 fx_free(vcpu);
e9b11c17
ZX		 7082 kvm_x86_ops->vcpu_free(vcpu);
7083}
7084
66450a21 7085void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 7086{
7460fb4a
AK		 7087 atomic_set(&vcpu->arch.nmi_queued, 0);
7088 vcpu->arch.nmi_pending = 0;
448fa4a9 7089 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7090 kvm_clear_interrupt_queue(vcpu);
7091 kvm_clear_exception_queue(vcpu);
448fa4a9 7092
42dbaa5a 7093 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 7094 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7095 kvm_update_dr6(vcpu);
42dbaa5a 7096 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7097 kvm_update_dr7(vcpu);
42dbaa5a 7098
3842d135 7099 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7100 vcpu->arch.apf.msr_val = 0;
c9aaa895 7101 vcpu->arch.st.msr_val = 0;
3842d135 7102
12f9a48f
GC		 7103 kvmclock_reset(vcpu);
7104
af585b92
GN		 7105 kvm_clear_async_pf_completion_queue(vcpu);
7106 kvm_async_pf_hash_reset(vcpu);
7107 vcpu->arch.apf.halted = false;
3842d135 7108
f5132b01
GN		 7109 kvm_pmu_reset(vcpu);
7110
66f7b72e
JS		 7111 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7112 vcpu->arch.regs_avail = ~0;
7113 vcpu->arch.regs_dirty = ~0;
7114
57f252f2 7115 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7116}
7117
2b4a273b 7118void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7119{
7120 struct kvm_segment cs;
7121
7122 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7123 cs.selector = vector << 8;
7124 cs.base = vector << 12;
7125 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7126 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7127}
7128
13a34e06 7129int kvm_arch_hardware_enable(void)
e9b11c17 7130{
ca84d1a2
ZA		 7131 struct kvm *kvm;
7132 struct kvm_vcpu *vcpu;
7133 int i;
0dd6a6ed
ZA		 7134 int ret;
7135 u64 local_tsc;
7136 u64 max_tsc = 0;
7137 bool stable, backwards_tsc = false;
18863bdd
AK		 7138
7139 kvm_shared_msr_cpu_online();
13a34e06 7140 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7141 if (ret != 0)
7142 return ret;
7143
7144 local_tsc = native_read_tsc();
7145 stable = !check_tsc_unstable();
7146 list_for_each_entry(kvm, &vm_list, vm_list) {
7147 kvm_for_each_vcpu(i, vcpu, kvm) {
7148 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7149 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7150 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7151 backwards_tsc = true;
7152 if (vcpu->arch.last_host_tsc > max_tsc)
7153 max_tsc = vcpu->arch.last_host_tsc;
7154 }
7155 }
7156 }
7157
7158 /*
7159 * Sometimes, even reliable TSCs go backwards. This happens on
7160 * platforms that reset TSC during suspend or hibernate actions, but
7161 * maintain synchronization. We must compensate. Fortunately, we can
7162 * detect that condition here, which happens early in CPU bringup,
7163 * before any KVM threads can be running. Unfortunately, we can't
7164 * bring the TSCs fully up to date with real time, as we aren't yet far
7165 * enough into CPU bringup that we know how much real time has actually
7166 * elapsed; our helper function, get_kernel_ns() will be using boot
7167 * variables that haven't been updated yet.
7168 *
7169 * So we simply find the maximum observed TSC above, then record the
7170 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7171 * the adjustment will be applied. Note that we accumulate
7172 * adjustments, in case multiple suspend cycles happen before some VCPU
7173 * gets a chance to run again. In the event that no KVM threads get a
7174 * chance to run, we will miss the entire elapsed period, as we'll have
7175 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7176 * loose cycle time. This isn't too big a deal, since the loss will be
7177 * uniform across all VCPUs (not to mention the scenario is extremely
7178 * unlikely). It is possible that a second hibernate recovery happens
7179 * much faster than a first, causing the observed TSC here to be
7180 * smaller; this would require additional padding adjustment, which is
7181 * why we set last_host_tsc to the local tsc observed here.
7182 *
7183 * N.B. - this code below runs only on platforms with reliable TSC,
7184 * as that is the only way backwards_tsc is set above. Also note
7185 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7186 * have the same delta_cyc adjustment applied if backwards_tsc
7187 * is detected. Note further, this adjustment is only done once,
7188 * as we reset last_host_tsc on all VCPUs to stop this from being
7189 * called multiple times (one for each physical CPU bringup).
7190 *
4a969980 7191 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7192 * will be compensated by the logic in vcpu_load, which sets the TSC to
7193 * catchup mode. This will catchup all VCPUs to real time, but cannot
7194 * guarantee that they stay in perfect synchronization.
7195 */
7196 if (backwards_tsc) {
7197 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7198 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7199 list_for_each_entry(kvm, &vm_list, vm_list) {
7200 kvm_for_each_vcpu(i, vcpu, kvm) {
7201 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7202 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7203 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7204 }
7205
7206 /*
7207 * We have to disable TSC offset matching.. if you were
7208 * booting a VM while issuing an S4 host suspend....
7209 * you may have some problem. Solving this issue is
7210 * left as an exercise to the reader.
7211 */
7212 kvm->arch.last_tsc_nsec = 0;
7213 kvm->arch.last_tsc_write = 0;
7214 }
7215
7216 }
7217 return 0;
e9b11c17
ZX		 7218}
7219
13a34e06 7220void kvm_arch_hardware_disable(void)
e9b11c17 7221{
13a34e06
RK		 7222 kvm_x86_ops->hardware_disable();
7223 drop_user_return_notifiers();
e9b11c17
ZX		 7224}
7225
7226int kvm_arch_hardware_setup(void)
7227{
7228 return kvm_x86_ops->hardware_setup();
7229}
7230
7231void kvm_arch_hardware_unsetup(void)
7232{
7233 kvm_x86_ops->hardware_unsetup();
7234}
7235
7236void kvm_arch_check_processor_compat(void *rtn)
7237{
7238 kvm_x86_ops->check_processor_compatibility(rtn);
7239}
7240
3e515705
AK		 7241bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7242{
7243 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7244}
7245
54e9818f
GN		 7246struct static_key kvm_no_apic_vcpu __read_mostly;
7247
e9b11c17
ZX		 7248int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7249{
7250 struct page *page;
7251 struct kvm *kvm;
7252 int r;
7253
7254 BUG_ON(vcpu->kvm == NULL);
7255 kvm = vcpu->kvm;
7256
6aef266c 7257 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7258 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7259 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7260 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7261 else
a4535290 7262 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7263
7264 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7265 if (!page) {
7266 r = -ENOMEM;
7267 goto fail;
7268 }
ad312c7c 7269 vcpu->arch.pio_data = page_address(page);
e9b11c17 7270
cc578287 7271 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7272
e9b11c17
ZX		 7273 r = kvm_mmu_create(vcpu);
7274 if (r < 0)
7275 goto fail_free_pio_data;
7276
7277 if (irqchip_in_kernel(kvm)) {
7278 r = kvm_create_lapic(vcpu);
7279 if (r < 0)
7280 goto fail_mmu_destroy;
54e9818f
GN		 7281 } else
7282 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7283
890ca9ae
HY		 7284 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7285 GFP_KERNEL);
7286 if (!vcpu->arch.mce_banks) {
7287 r = -ENOMEM;
443c39bc 7288 goto fail_free_lapic;
890ca9ae
HY		 7289 }
7290 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7291
f1797359
WY		 7292 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7293 r = -ENOMEM;
f5f48ee1 7294 goto fail_free_mce_banks;
f1797359 7295 }
f5f48ee1 7296
66f7b72e
JS		 7297 r = fx_init(vcpu);
7298 if (r)
7299 goto fail_free_wbinvd_dirty_mask;
7300
ba904635 7301 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7302 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7303
7304 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7305 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7306
af585b92 7307 kvm_async_pf_hash_reset(vcpu);
f5132b01 7308 kvm_pmu_init(vcpu);
af585b92 7309
e9b11c17 7310 return 0;
66f7b72e
JS		 7311fail_free_wbinvd_dirty_mask:
7312 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7313fail_free_mce_banks:
7314 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7315fail_free_lapic:
7316 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7317fail_mmu_destroy:
7318 kvm_mmu_destroy(vcpu);
7319fail_free_pio_data:
ad312c7c 7320 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7321fail:
7322 return r;
7323}
7324
7325void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7326{
f656ce01
MT		 7327 int idx;
7328
f5132b01 7329 kvm_pmu_destroy(vcpu);
36cb93fd 7330 kfree(vcpu->arch.mce_banks);
e9b11c17 7331 kvm_free_lapic(vcpu);
f656ce01 7332 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7333 kvm_mmu_destroy(vcpu);
f656ce01 7334 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7335 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7336 if (!irqchip_in_kernel(vcpu->kvm))
7337 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7338}
d19a9cd2 7339
e790d9ef
RK		 7340void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7341{
ae97a3b8 7342 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7343}
7344
e08b9637 7345int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7346{
e08b9637
CO		 7347 if (type)
7348 return -EINVAL;
7349
6ef768fa 7350 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7351 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7352 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7353 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7354 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7355
5550af4d
SY		 7356 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7357 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7358 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7359 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7360 &kvm->arch.irq_sources_bitmap);
5550af4d 7361
038f8c11 7362 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7363 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7364 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7365
7366 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7367
7e44e449 7368 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7369 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7370
d89f5eff 7371 return 0;
d19a9cd2
ZX		 7372}
7373
7374static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7375{
9fc77441
MT		 7376 int r;
7377 r = vcpu_load(vcpu);
7378 BUG_ON(r);
d19a9cd2
ZX		 7379 kvm_mmu_unload(vcpu);
7380 vcpu_put(vcpu);
7381}
7382
7383static void kvm_free_vcpus(struct kvm *kvm)
7384{
7385 unsigned int i;
988a2cae 7386 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7387
7388 /*
7389 * Unpin any mmu pages first.
7390 */
af585b92
GN		 7391 kvm_for_each_vcpu(i, vcpu, kvm) {
7392 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7393 kvm_unload_vcpu_mmu(vcpu);
af585b92 7394 }
988a2cae
GN		 7395 kvm_for_each_vcpu(i, vcpu, kvm)
7396 kvm_arch_vcpu_free(vcpu);
7397
7398 mutex_lock(&kvm->lock);
7399 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7400 kvm->vcpus[i] = NULL;
d19a9cd2 7401
988a2cae
GN		 7402 atomic_set(&kvm->online_vcpus, 0);
7403 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7404}
7405
ad8ba2cd
SY		 7406void kvm_arch_sync_events(struct kvm *kvm)
7407{
332967a3 7408 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7409 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7410 kvm_free_all_assigned_devices(kvm);
aea924f6 7411 kvm_free_pit(kvm);
ad8ba2cd
SY		 7412}
7413
d19a9cd2
ZX		 7414void kvm_arch_destroy_vm(struct kvm *kvm)
7415{
27469d29
AH		 7416 if (current->mm == kvm->mm) {
7417 /*
7418 * Free memory regions allocated on behalf of userspace,
7419 * unless the the memory map has changed due to process exit
7420 * or fd copying.
7421 */
7422 struct kvm_userspace_memory_region mem;
7423 memset(&mem, 0, sizeof(mem));
7424 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7425 kvm_set_memory_region(kvm, &mem);
7426
7427 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7428 kvm_set_memory_region(kvm, &mem);
7429
7430 mem.slot = TSS_PRIVATE_MEMSLOT;
7431 kvm_set_memory_region(kvm, &mem);
7432 }
6eb55818 7433 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7434 kfree(kvm->arch.vpic);
7435 kfree(kvm->arch.vioapic);
d19a9cd2 7436 kvm_free_vcpus(kvm);
1e08ec4a 7437 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7438}
0de10343 7439
5587027c 7440void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7441 struct kvm_memory_slot *dont)
7442{
7443 int i;
7444
d89cc617
TY		 7445 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7446 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7447 kvm_kvfree(free->arch.rmap[i]);
7448 free->arch.rmap[i] = NULL;
77d11309 7449 }
d89cc617
TY		 7450 if (i == 0)
7451 continue;
7452
7453 if (!dont || free->arch.lpage_info[i - 1] !=
7454 dont->arch.lpage_info[i - 1]) {
7455 kvm_kvfree(free->arch.lpage_info[i - 1]);
7456 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7457 }
7458 }
7459}
7460
5587027c
AK		 7461int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7462 unsigned long npages)
db3fe4eb
TY		 7463{
7464 int i;
7465
d89cc617 7466 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7467 unsigned long ugfn;
7468 int lpages;
d89cc617 7469 int level = i + 1;
db3fe4eb
TY		 7470
7471 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7472 slot->base_gfn, level) + 1;
7473
d89cc617
TY		 7474 slot->arch.rmap[i] =
7475 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7476 if (!slot->arch.rmap[i])
77d11309 7477 goto out_free;
d89cc617
TY		 7478 if (i == 0)
7479 continue;
77d11309 7480
d89cc617
TY		 7481 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7482 sizeof(*slot->arch.lpage_info[i - 1]));
7483 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7484 goto out_free;
7485
7486 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7487 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7488 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7489 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7490 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7491 /*
7492 * If the gfn and userspace address are not aligned wrt each
7493 * other, or if explicitly asked to, disable large page
7494 * support for this slot
7495 */
7496 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7497 !kvm_largepages_enabled()) {
7498 unsigned long j;
7499
7500 for (j = 0; j < lpages; ++j)
d89cc617 7501 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7502 }
7503 }
7504
7505 return 0;
7506
7507out_free:
d89cc617
TY		 7508 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7509 kvm_kvfree(slot->arch.rmap[i]);
7510 slot->arch.rmap[i] = NULL;
7511 if (i == 0)
7512 continue;
7513
7514 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7515 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7516 }
7517 return -ENOMEM;
7518}
7519
e59dbe09
TY		 7520void kvm_arch_memslots_updated(struct kvm *kvm)
7521{
e6dff7d1
TY		 7522 /*
7523 * memslots->generation has been incremented.
7524 * mmio generation may have reached its maximum value.
7525 */
7526 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7527}
7528
f7784b8e
MT		 7529int kvm_arch_prepare_memory_region(struct kvm *kvm,
7530 struct kvm_memory_slot *memslot,
f7784b8e 7531 struct kvm_userspace_memory_region *mem,
7b6195a9 7532 enum kvm_mr_change change)
0de10343 7533{
7a905b14
TY		 7534 /*
7535 * Only private memory slots need to be mapped here since
7536 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7537 */
7b6195a9 7538 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7539 unsigned long userspace_addr;
604b38ac 7540
7a905b14
TY		 7541 /*
7542 * MAP_SHARED to prevent internal slot pages from being moved
7543 * by fork()/COW.
7544 */
7b6195a9 7545 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7546 PROT_READ | PROT_WRITE,
7547 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7548
7a905b14
TY		 7549 if (IS_ERR((void *)userspace_addr))
7550 return PTR_ERR((void *)userspace_addr);
604b38ac 7551
7a905b14 7552 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7553 }
7554
f7784b8e
MT		 7555 return 0;
7556}
7557
7558void kvm_arch_commit_memory_region(struct kvm *kvm,
7559 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7560 const struct kvm_memory_slot *old,
7561 enum kvm_mr_change change)
f7784b8e
MT		 7562{
7563
8482644a 7564 int nr_mmu_pages = 0;
f7784b8e 7565
8482644a 7566 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7567 int ret;
7568
8482644a
TY		 7569 ret = vm_munmap(old->userspace_addr,
7570 old->npages * PAGE_SIZE);
f7784b8e
MT		 7571 if (ret < 0)
7572 printk(KERN_WARNING
7573 "kvm_vm_ioctl_set_memory_region: "
7574 "failed to munmap memory\n");
7575 }
7576
48c0e4e9
XG		 7577 if (!kvm->arch.n_requested_mmu_pages)
7578 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7579
48c0e4e9 7580 if (nr_mmu_pages)
0de10343 7581 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7582 /*
7583 * Write protect all pages for dirty logging.
c126d94f
XG		 7584 *
7585 * All the sptes including the large sptes which point to this
7586 * slot are set to readonly. We can not create any new large
7587 * spte on this slot until the end of the logging.
7588 *
7589 * See the comments in fast_page_fault().
c972f3b1 7590 */
8482644a 7591 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7592 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7593}
1d737c8a 7594
2df72e9b 7595void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7596{
6ca18b69 7597 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7598}
7599
2df72e9b
MT		 7600void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7601 struct kvm_memory_slot *slot)
7602{
6ca18b69 7603 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7604}
7605
1d737c8a
ZX		 7606int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7607{
b6b8a145
JK		 7608 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7609 kvm_x86_ops->check_nested_events(vcpu, false);
7610
af585b92
GN		 7611 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7612 !vcpu->arch.apf.halted)
7613 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7614 || kvm_apic_has_events(vcpu)
6aef266c 7615 || vcpu->arch.pv.pv_unhalted
7460fb4a 7616 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7617 (kvm_arch_interrupt_allowed(vcpu) &&
7618 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7619}
5736199a 7620
b6d33834 7621int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7622{
b6d33834 7623 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7624}
78646121
GN		 7625
7626int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7627{
7628 return kvm_x86_ops->interrupt_allowed(vcpu);
7629}
229456fc 7630
82b32774 7631unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7632{
82b32774
NA		 7633 if (is_64_bit_mode(vcpu))
7634 return kvm_rip_read(vcpu);
7635 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7636 kvm_rip_read(vcpu));
7637}
7638EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7639
82b32774
NA		 7640bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7641{
7642 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7643}
7644EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7645
94fe45da
JK		 7646unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7647{
7648 unsigned long rflags;
7649
7650 rflags = kvm_x86_ops->get_rflags(vcpu);
7651 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7652 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7653 return rflags;
7654}
7655EXPORT_SYMBOL_GPL(kvm_get_rflags);
7656
6addfc42 7657static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7658{
7659 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7660 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7661 rflags |= X86_EFLAGS_TF;
94fe45da 7662 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7663}
7664
7665void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7666{
7667 __kvm_set_rflags(vcpu, rflags);
3842d135 7668 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7669}
7670EXPORT_SYMBOL_GPL(kvm_set_rflags);
7671
56028d08
GN		 7672void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7673{
7674 int r;
7675
fb67e14f 7676 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7677 work->wakeup_all)
56028d08
GN		 7678 return;
7679
7680 r = kvm_mmu_reload(vcpu);
7681 if (unlikely(r))
7682 return;
7683
fb67e14f
XG		 7684 if (!vcpu->arch.mmu.direct_map &&
7685 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7686 return;
7687
56028d08
GN		 7688 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7689}
7690
af585b92
GN		 7691static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7692{
7693 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7694}
7695
7696static inline u32 kvm_async_pf_next_probe(u32 key)
7697{
7698 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7699}
7700
7701static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7702{
7703 u32 key = kvm_async_pf_hash_fn(gfn);
7704
7705 while (vcpu->arch.apf.gfns[key] != ~0)
7706 key = kvm_async_pf_next_probe(key);
7707
7708 vcpu->arch.apf.gfns[key] = gfn;
7709}
7710
7711static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7712{
7713 int i;
7714 u32 key = kvm_async_pf_hash_fn(gfn);
7715
7716 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7717 (vcpu->arch.apf.gfns[key] != gfn &&
7718 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7719 key = kvm_async_pf_next_probe(key);
7720
7721 return key;
7722}
7723
7724bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7725{
7726 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7727}
7728
7729static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7730{
7731 u32 i, j, k;
7732
7733 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7734 while (true) {
7735 vcpu->arch.apf.gfns[i] = ~0;
7736 do {
7737 j = kvm_async_pf_next_probe(j);
7738 if (vcpu->arch.apf.gfns[j] == ~0)
7739 return;
7740 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7741 /*
7742 * k lies cyclically in ]i,j]
7743 * | i.k.j |
7744 * |....j i.k.| or |.k..j i...|
7745 */
7746 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7747 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7748 i = j;
7749 }
7750}
7751
7c90705b
GN		 7752static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7753{
7754
7755 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7756 sizeof(val));
7757}
7758
af585b92
GN		 7759void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7760 struct kvm_async_pf *work)
7761{
6389ee94
AK		 7762 struct x86_exception fault;
7763
7c90705b 7764 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7765 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7766
7767 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7768 (vcpu->arch.apf.send_user_only &&
7769 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7770 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7771 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7772 fault.vector = PF_VECTOR;
7773 fault.error_code_valid = true;
7774 fault.error_code = 0;
7775 fault.nested_page_fault = false;
7776 fault.address = work->arch.token;
7777 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7778 }
af585b92
GN		 7779}
7780
7781void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7782 struct kvm_async_pf *work)
7783{
6389ee94
AK		 7784 struct x86_exception fault;
7785
7c90705b 7786 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7787 if (work->wakeup_all)
7c90705b
GN		 7788 work->arch.token = ~0; /* broadcast wakeup */
7789 else
7790 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7791
7792 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7793 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7794 fault.vector = PF_VECTOR;
7795 fault.error_code_valid = true;
7796 fault.error_code = 0;
7797 fault.nested_page_fault = false;
7798 fault.address = work->arch.token;
7799 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7800 }
e6d53e3b 7801 vcpu->arch.apf.halted = false;
a4fa1635 7802 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7803}
7804
7805bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7806{
7807 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7808 return true;
7809 else
7810 return !kvm_event_needs_reinjection(vcpu) &&
7811 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7812}
7813
e0f0bbc5
AW		 7814void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7815{
7816 atomic_inc(&kvm->arch.noncoherent_dma_count);
7817}
7818EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7819
7820void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7821{
7822 atomic_dec(&kvm->arch.noncoherent_dma_count);
7823}
7824EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7825
7826bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7827{
7828 return atomic_read(&kvm->arch.noncoherent_dma_count);
7829}
7830EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7831
229456fc
MT		 7832EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7833EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7834EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7835EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7836EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7837EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7838EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7839EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7840EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7841EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7842EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7845EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux kernel - Deliverables
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