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KVM: x86: API changes for SMM support
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 225 if (slot >= shared_msrs_global.nr)
226 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 227 shared_msrs_global.msrs[slot] = msr;
228 /* we need ensured the shared_msr_global have been updated */
229 smp_wmb();
18863bdd
AK		 230}
231EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
232
233static void kvm_shared_msr_cpu_online(void)
234{
235 unsigned i;
18863bdd
AK		 236
237 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 238 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 239}
240
8b3c3104 241int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 242{
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 245 int err;
18863bdd 246
2bf78fa7 247 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 248 return 0;
2bf78fa7 249 smsr->values[slot].curr = value;
8b3c3104
AH		 250 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
251 if (err)
252 return 1;
253
18863bdd
AK		 254 if (!smsr->registered) {
255 smsr->urn.on_user_return = kvm_on_user_return;
256 user_return_notifier_register(&smsr->urn);
257 smsr->registered = true;
258 }
8b3c3104 259 return 0;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
262
13a34e06 263static void drop_user_return_notifiers(void)
3548bab5 264{
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 267
268 if (smsr->registered)
269 kvm_on_user_return(&smsr->urn);
270}
271
6866b83e
CO		 272u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
273{
8a5a87d9 274 return vcpu->arch.apic_base;
6866b83e
CO		 275}
276EXPORT_SYMBOL_GPL(kvm_get_apic_base);
277
58cb628d
JK		 278int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
279{
280 u64 old_state = vcpu->arch.apic_base &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 new_state = msr_info->data &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
285 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
286
287 if (!msr_info->host_initiated &&
288 ((msr_info->data & reserved_bits) != 0 ||
289 new_state == X2APIC_ENABLE ||
290 (new_state == MSR_IA32_APICBASE_ENABLE &&
291 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
292 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
293 old_state == 0)))
294 return 1;
295
296 kvm_lapic_set_base(vcpu, msr_info->data);
297 return 0;
6866b83e
CO		 298}
299EXPORT_SYMBOL_GPL(kvm_set_apic_base);
300
2605fc21 301asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 302{
303 /* Fault while not rebooting. We want the trace. */
304 BUG();
305}
306EXPORT_SYMBOL_GPL(kvm_spurious_fault);
307
3fd28fce
ED		 308#define EXCPT_BENIGN 0
309#define EXCPT_CONTRIBUTORY 1
310#define EXCPT_PF 2
311
312static int exception_class(int vector)
313{
314 switch (vector) {
315 case PF_VECTOR:
316 return EXCPT_PF;
317 case DE_VECTOR:
318 case TS_VECTOR:
319 case NP_VECTOR:
320 case SS_VECTOR:
321 case GP_VECTOR:
322 return EXCPT_CONTRIBUTORY;
323 default:
324 break;
325 }
326 return EXCPT_BENIGN;
327}
328
d6e8c854
NA		 329#define EXCPT_FAULT 0
330#define EXCPT_TRAP 1
331#define EXCPT_ABORT 2
332#define EXCPT_INTERRUPT 3
333
334static int exception_type(int vector)
335{
336 unsigned int mask;
337
338 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
339 return EXCPT_INTERRUPT;
340
341 mask = 1 << vector;
342
343 /* #DB is trap, as instruction watchpoints are handled elsewhere */
344 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
345 return EXCPT_TRAP;
346
347 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
348 return EXCPT_ABORT;
349
350 /* Reserved exceptions will result in fault */
351 return EXCPT_FAULT;
352}
353
3fd28fce 354static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 355 unsigned nr, bool has_error, u32 error_code,
356 bool reinject)
3fd28fce
ED		 357{
358 u32 prev_nr;
359 int class1, class2;
360
3842d135
AK		 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
362
3fd28fce
ED		 363 if (!vcpu->arch.exception.pending) {
364 queue:
3ffb2468
NA		 365 if (has_error && !is_protmode(vcpu))
366 has_error = false;
3fd28fce
ED		 367 vcpu->arch.exception.pending = true;
368 vcpu->arch.exception.has_error_code = has_error;
369 vcpu->arch.exception.nr = nr;
370 vcpu->arch.exception.error_code = error_code;
3f0fd292 371 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 372 return;
373 }
374
375 /* to check exception */
376 prev_nr = vcpu->arch.exception.nr;
377 if (prev_nr == DF_VECTOR) {
378 /* triple fault -> shutdown */
a8eeb04a 379 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 380 return;
381 }
382 class1 = exception_class(prev_nr);
383 class2 = exception_class(nr);
384 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
385 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
386 /* generate double fault per SDM Table 5-5 */
387 vcpu->arch.exception.pending = true;
388 vcpu->arch.exception.has_error_code = true;
389 vcpu->arch.exception.nr = DF_VECTOR;
390 vcpu->arch.exception.error_code = 0;
391 } else
392 /* replace previous exception with a new one in a hope
393 that instruction re-execution will regenerate lost
394 exception */
395 goto queue;
396}
397
298101da
AK		 398void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
399{
ce7ddec4 400 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 401}
402EXPORT_SYMBOL_GPL(kvm_queue_exception);
403
ce7ddec4
JR		 404void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
405{
406 kvm_multiple_exception(vcpu, nr, false, 0, true);
407}
408EXPORT_SYMBOL_GPL(kvm_requeue_exception);
409
db8fcefa 410void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 411{
db8fcefa
AP		 412 if (err)
413 kvm_inject_gp(vcpu, 0);
414 else
415 kvm_x86_ops->skip_emulated_instruction(vcpu);
416}
417EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 418
6389ee94 419void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 420{
421 ++vcpu->stat.pf_guest;
6389ee94
AK		 422 vcpu->arch.cr2 = fault->address;
423 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 424}
27d6c865 425EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 426
ef54bcfe 427static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 428{
6389ee94
AK		 429 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
430 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 431 else
6389ee94 432 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 433
434 return fault->nested_page_fault;
d4f8cf66
JR		 435}
436
3419ffc8
SY		 437void kvm_inject_nmi(struct kvm_vcpu *vcpu)
438{
7460fb4a
AK		 439 atomic_inc(&vcpu->arch.nmi_queued);
440 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 441}
442EXPORT_SYMBOL_GPL(kvm_inject_nmi);
443
298101da
AK		 444void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
445{
ce7ddec4 446 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 447}
448EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
449
ce7ddec4
JR		 450void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
451{
452 kvm_multiple_exception(vcpu, nr, true, error_code, true);
453}
454EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
455
0a79b009
AK		 456/*
457 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
458 * a #GP and return false.
459 */
460bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 461{
0a79b009
AK		 462 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
463 return true;
464 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
465 return false;
298101da 466}
0a79b009 467EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 468
16f8a6f9
NA		 469bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
470{
471 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
472 return true;
473
474 kvm_queue_exception(vcpu, UD_VECTOR);
475 return false;
476}
477EXPORT_SYMBOL_GPL(kvm_require_dr);
478
ec92fe44
JR		 479/*
480 * This function will be used to read from the physical memory of the currently
481 * running guest. The difference to kvm_read_guest_page is that this function
482 * can read from guest physical or from the guest's guest physical memory.
483 */
484int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
485 gfn_t ngfn, void *data, int offset, int len,
486 u32 access)
487{
54987b7a 488 struct x86_exception exception;
ec92fe44
JR		 489 gfn_t real_gfn;
490 gpa_t ngpa;
491
492 ngpa = gfn_to_gpa(ngfn);
54987b7a 493 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 494 if (real_gfn == UNMAPPED_GVA)
495 return -EFAULT;
496
497 real_gfn = gpa_to_gfn(real_gfn);
498
499 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
500}
501EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
502
69b0049a 503static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 504 void *data, int offset, int len, u32 access)
505{
506 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
507 data, offset, len, access);
508}
509
a03490ed
CO		 510/*
511 * Load the pae pdptrs. Return true is they are all valid.
512 */
ff03a073 513int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 514{
515 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
516 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
517 int i;
518 int ret;
ff03a073 519 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 520
ff03a073
JR		 521 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
522 offset * sizeof(u64), sizeof(pdpte),
523 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 524 if (ret < 0) {
525 ret = 0;
526 goto out;
527 }
528 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 529 if (is_present_gpte(pdpte[i]) &&
20c466b5 530 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 624 return 0;
625}
2d3ad1f4 626EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 627
2d3ad1f4 628void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 629{
49a9b07e 630 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 631}
2d3ad1f4 632EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 633
42bdf991
MT		 634static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
635{
636 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
637 !vcpu->guest_xcr0_loaded) {
638 /* kvm_set_xcr() also depends on this */
639 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
640 vcpu->guest_xcr0_loaded = 1;
641 }
642}
643
644static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
645{
646 if (vcpu->guest_xcr0_loaded) {
647 if (vcpu->arch.xcr0 != host_xcr0)
648 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
649 vcpu->guest_xcr0_loaded = 0;
650 }
651}
652
69b0049a 653static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 654{
56c103ec
LJ		 655 u64 xcr0 = xcr;
656 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 657 u64 valid_bits;
2acf923e
DC		 658
659 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
660 if (index != XCR_XFEATURE_ENABLED_MASK)
661 return 1;
2acf923e
DC		 662 if (!(xcr0 & XSTATE_FP))
663 return 1;
664 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
665 return 1;
46c34cb0
PB		 666
667 /*
668 * Do not allow the guest to set bits that we do not support
669 * saving. However, xcr0 bit 0 is always set, even if the
670 * emulated CPU does not support XSAVE (see fx_init).
671 */
672 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
673 if (xcr0 & ~valid_bits)
2acf923e 674 return 1;
46c34cb0 675
390bd528
LJ		 676 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
677 return 1;
678
612263b3
CP		 679 if (xcr0 & XSTATE_AVX512) {
680 if (!(xcr0 & XSTATE_YMM))
681 return 1;
682 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
683 return 1;
684 }
42bdf991 685 kvm_put_guest_xcr0(vcpu);
2acf923e 686 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 687
688 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
689 kvm_update_cpuid(vcpu);
2acf923e
DC		 690 return 0;
691}
692
693int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
694{
764bcbc5
Z		 695 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
696 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 697 kvm_inject_gp(vcpu, 0);
698 return 1;
699 }
700 return 0;
701}
702EXPORT_SYMBOL_GPL(kvm_set_xcr);
703
a83b29c6 704int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 705{
fc78f519 706 unsigned long old_cr4 = kvm_read_cr4(vcpu);
edc90b7d
XG		 707 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
708 X86_CR4_SMEP | X86_CR4_SMAP;
709
0f12244f
GN		 710 if (cr4 & CR4_RESERVED_BITS)
711 return 1;
a03490ed 712
2acf923e
DC		 713 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
714 return 1;
715
c68b734f
YW		 716 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
717 return 1;
718
97ec8c06
FW		 719 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
720 return 1;
721
afcbf13f 722 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 723 return 1;
724
a03490ed 725 if (is_long_mode(vcpu)) {
0f12244f
GN		 726 if (!(cr4 & X86_CR4_PAE))
727 return 1;
a2edf57f
AK		 728 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
729 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 730 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
731 kvm_read_cr3(vcpu)))
0f12244f
GN		 732 return 1;
733
ad756a16
MJ		 734 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
735 if (!guest_cpuid_has_pcid(vcpu))
736 return 1;
737
738 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
739 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
740 return 1;
741 }
742
5e1746d6 743 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 744 return 1;
a03490ed 745
ad756a16
MJ		 746 if (((cr4 ^ old_cr4) & pdptr_bits) ||
747 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 748 kvm_mmu_reset_context(vcpu);
0f12244f 749
2acf923e 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 751 kvm_update_cpuid(vcpu);
2acf923e 752
0f12244f
GN		 753 return 0;
754}
2d3ad1f4 755EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 756
2390218b 757int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 758{
ac146235 759#ifdef CONFIG_X86_64
9d88fca7 760 cr3 &= ~CR3_PCID_INVD;
ac146235 761#endif
9d88fca7 762
9f8fe504 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 764 kvm_mmu_sync_roots(vcpu);
77c3913b 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 766 return 0;
d835dfec
AK		 767 }
768
a03490ed 769 if (is_long_mode(vcpu)) {
d9f89b88
JK		 770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 774 return 1;
a03490ed 775
0f12244f 776 vcpu->arch.cr3 = cr3;
aff48baa 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 778 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 782
eea1cff9 783int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 784{
0f12244f
GN		 785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
a03490ed
CO		 787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
ad312c7c 790 vcpu->arch.cr8 = cr8;
0f12244f
GN		 791 return 0;
792}
2d3ad1f4 793EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 794
2d3ad1f4 795unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 796{
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
ad312c7c 800 return vcpu->arch.cr8;
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 803
ae561ede
NA		 804static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805{
806 int i;
807
808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809 for (i = 0; i < KVM_NR_DB_REGS; i++)
810 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 }
813}
814
73aaf249
JK		 815static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816{
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819}
820
c8639010
JK		 821static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822{
823 unsigned long dr7;
824
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 dr7 = vcpu->arch.guest_debug_dr7;
827 else
828 dr7 = vcpu->arch.dr7;
829 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831 if (dr7 & DR7_BP_EN_MASK)
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 833}
834
6f43ed01
NA		 835static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836{
837 u64 fixed = DR6_FIXED_1;
838
839 if (!guest_cpuid_has_rtm(vcpu))
840 fixed |= DR6_RTM;
841 return fixed;
842}
843
338dbc97 844static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 vcpu->arch.db[dr] = val;
849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850 vcpu->arch.eff_db[dr] = val;
851 break;
852 case 4:
020df079
GN		 853 /* fall through */
854 case 6:
338dbc97
GN		 855 if (val & 0xffffffff00000000ULL)
856 return -1; /* #GP */
6f43ed01 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 858 kvm_update_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
020df079
GN		 861 /* fall through */
862 default: /* 7 */
338dbc97
GN		 863 if (val & 0xffffffff00000000ULL)
864 return -1; /* #GP */
020df079 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 866 kvm_update_dr7(vcpu);
020df079
GN		 867 break;
868 }
869
870 return 0;
871}
338dbc97
GN		 872
873int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874{
16f8a6f9 875 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 876 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 877 return 1;
878 }
879 return 0;
338dbc97 880}
020df079
GN		 881EXPORT_SYMBOL_GPL(kvm_set_dr);
882
16f8a6f9 883int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 884{
885 switch (dr) {
886 case 0 ... 3:
887 *val = vcpu->arch.db[dr];
888 break;
889 case 4:
020df079
GN		 890 /* fall through */
891 case 6:
73aaf249
JK		 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893 *val = vcpu->arch.dr6;
894 else
895 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 896 break;
897 case 5:
020df079
GN		 898 /* fall through */
899 default: /* 7 */
900 *val = vcpu->arch.dr7;
901 break;
902 }
338dbc97
GN		 903 return 0;
904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_get_dr);
906
022cd0e8
AK		 907bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908{
909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 u64 data;
911 int err;
912
913 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914 if (err)
915 return err;
916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918 return err;
919}
920EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
043405e1
CO		 922/*
923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925 *
926 * This list is modified at module load time to reflect the
e3267cbb 927 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 928 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
929 * may depend on host virtualization features rather than host cpu features.
043405e1 930 */
e3267cbb 931
043405e1
CO		 932static u32 msrs_to_save[] = {
933 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 934 MSR_STAR,
043405e1
CO		 935#ifdef CONFIG_X86_64
936 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
937#endif
b3897a49 938 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 939 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 940};
941
942static unsigned num_msrs_to_save;
943
62ef68bb
PB		 944static u32 emulated_msrs[] = {
945 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
946 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
947 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
948 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
949 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
950 MSR_KVM_PV_EOI_EN,
951
ba904635 952 MSR_IA32_TSC_ADJUST,
a3e06bbe 953 MSR_IA32_TSCDEADLINE,
043405e1 954 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 955 MSR_IA32_MCG_STATUS,
956 MSR_IA32_MCG_CTL,
043405e1
CO		 957};
958
62ef68bb
PB		 959static unsigned num_emulated_msrs;
960
384bb783 961bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 962{
b69e8cae 963 if (efer & efer_reserved_bits)
384bb783 964 return false;
15c4a640 965
1b2fd70c
AG		 966 if (efer & EFER_FFXSR) {
967 struct kvm_cpuid_entry2 *feat;
968
969 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 970 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 971 return false;
1b2fd70c
AG		 972 }
973
d8017474
AG		 974 if (efer & EFER_SVME) {
975 struct kvm_cpuid_entry2 *feat;
976
977 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 978 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 979 return false;
d8017474
AG		 980 }
981
384bb783
JK		 982 return true;
983}
984EXPORT_SYMBOL_GPL(kvm_valid_efer);
985
986static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
987{
988 u64 old_efer = vcpu->arch.efer;
989
990 if (!kvm_valid_efer(vcpu, efer))
991 return 1;
992
993 if (is_paging(vcpu)
994 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
995 return 1;
996
15c4a640 997 efer &= ~EFER_LMA;
f6801dff 998 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 999
a3d204e2
SY		 1000 kvm_x86_ops->set_efer(vcpu, efer);
1001
aad82703
SY		 1002 /* Update reserved bits */
1003 if ((efer ^ old_efer) & EFER_NX)
1004 kvm_mmu_reset_context(vcpu);
1005
b69e8cae 1006 return 0;
15c4a640
CO		 1007}
1008
f2b4b7dd
JR		 1009void kvm_enable_efer_bits(u64 mask)
1010{
1011 efer_reserved_bits &= ~mask;
1012}
1013EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1014
15c4a640
CO		 1015/*
1016 * Writes msr value into into the appropriate "register".
1017 * Returns 0 on success, non-0 otherwise.
1018 * Assumes vcpu_load() was already called.
1019 */
8fe8ab46 1020int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1021{
854e8bb1
NA		 1022 switch (msr->index) {
1023 case MSR_FS_BASE:
1024 case MSR_GS_BASE:
1025 case MSR_KERNEL_GS_BASE:
1026 case MSR_CSTAR:
1027 case MSR_LSTAR:
1028 if (is_noncanonical_address(msr->data))
1029 return 1;
1030 break;
1031 case MSR_IA32_SYSENTER_EIP:
1032 case MSR_IA32_SYSENTER_ESP:
1033 /*
1034 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1035 * non-canonical address is written on Intel but not on
1036 * AMD (which ignores the top 32-bits, because it does
1037 * not implement 64-bit SYSENTER).
1038 *
1039 * 64-bit code should hence be able to write a non-canonical
1040 * value on AMD. Making the address canonical ensures that
1041 * vmentry does not fail on Intel after writing a non-canonical
1042 * value, and that something deterministic happens if the guest
1043 * invokes 64-bit SYSENTER.
1044 */
1045 msr->data = get_canonical(msr->data);
1046 }
8fe8ab46 1047 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1048}
854e8bb1 1049EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1050
313a3dc7
CO		 1051/*
1052 * Adapt set_msr() to msr_io()'s calling convention
1053 */
609e36d3
PB		 1054static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1055{
1056 struct msr_data msr;
1057 int r;
1058
1059 msr.index = index;
1060 msr.host_initiated = true;
1061 r = kvm_get_msr(vcpu, &msr);
1062 if (r)
1063 return r;
1064
1065 *data = msr.data;
1066 return 0;
1067}
1068
313a3dc7
CO		 1069static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1070{
8fe8ab46
WA		 1071 struct msr_data msr;
1072
1073 msr.data = *data;
1074 msr.index = index;
1075 msr.host_initiated = true;
1076 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1077}
1078
16e8d74d
MT		 1079#ifdef CONFIG_X86_64
1080struct pvclock_gtod_data {
1081 seqcount_t seq;
1082
1083 struct { /* extract of a clocksource struct */
1084 int vclock_mode;
1085 cycle_t cycle_last;
1086 cycle_t mask;
1087 u32 mult;
1088 u32 shift;
1089 } clock;
1090
cbcf2dd3
TG		 1091 u64 boot_ns;
1092 u64 nsec_base;
16e8d74d
MT		 1093};
1094
1095static struct pvclock_gtod_data pvclock_gtod_data;
1096
1097static void update_pvclock_gtod(struct timekeeper *tk)
1098{
1099 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1100 u64 boot_ns;
1101
876e7881 1102 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1103
1104 write_seqcount_begin(&vdata->seq);
1105
1106 /* copy pvclock gtod data */
876e7881
PZ		 1107 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1108 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1109 vdata->clock.mask = tk->tkr_mono.mask;
1110 vdata->clock.mult = tk->tkr_mono.mult;
1111 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1112
cbcf2dd3 1113 vdata->boot_ns = boot_ns;
876e7881 1114 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1115
1116 write_seqcount_end(&vdata->seq);
1117}
1118#endif
1119
bab5bb39
NK		 1120void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1121{
1122 /*
1123 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1124 * vcpu_enter_guest. This function is only called from
1125 * the physical CPU that is running vcpu.
1126 */
1127 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1128}
16e8d74d 1129
18068523
GOC		 1130static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1131{
9ed3c444
AK		 1132 int version;
1133 int r;
50d0a0f9 1134 struct pvclock_wall_clock wc;
923de3cf 1135 struct timespec boot;
18068523
GOC		 1136
1137 if (!wall_clock)
1138 return;
1139
9ed3c444
AK		 1140 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1141 if (r)
1142 return;
1143
1144 if (version & 1)
1145 ++version; /* first time write, random junk */
1146
1147 ++version;
18068523 1148
18068523
GOC		 1149 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1150
50d0a0f9
GH		 1151 /*
1152 * The guest calculates current wall clock time by adding
34c238a1 1153 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1154 * wall clock specified here. guest system time equals host
1155 * system time for us, thus we must fill in host boot time here.
1156 */
923de3cf 1157 getboottime(&boot);
50d0a0f9 1158
4b648665
BR		 1159 if (kvm->arch.kvmclock_offset) {
1160 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1161 boot = timespec_sub(boot, ts);
1162 }
50d0a0f9
GH		 1163 wc.sec = boot.tv_sec;
1164 wc.nsec = boot.tv_nsec;
1165 wc.version = version;
18068523
GOC		 1166
1167 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1168
1169 version++;
1170 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1171}
1172
50d0a0f9
GH		 1173static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1174{
1175 uint32_t quotient, remainder;
1176
1177 /* Don't try to replace with do_div(), this one calculates
1178 * "(dividend << 32) / divisor" */
1179 __asm__ ( "divl %4"
1180 : "=a" (quotient), "=d" (remainder)
1181 : "0" (0), "1" (dividend), "r" (divisor) );
1182 return quotient;
1183}
1184
5f4e3f88
ZA		 1185static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1186 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1187{
5f4e3f88 1188 uint64_t scaled64;
50d0a0f9
GH		 1189 int32_t shift = 0;
1190 uint64_t tps64;
1191 uint32_t tps32;
1192
5f4e3f88
ZA		 1193 tps64 = base_khz * 1000LL;
1194 scaled64 = scaled_khz * 1000LL;
50933623 1195 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1196 tps64 >>= 1;
1197 shift--;
1198 }
1199
1200 tps32 = (uint32_t)tps64;
50933623
JK		 1201 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1202 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1203 scaled64 >>= 1;
1204 else
1205 tps32 <<= 1;
50d0a0f9
GH		 1206 shift++;
1207 }
1208
5f4e3f88
ZA		 1209 *pshift = shift;
1210 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1211
5f4e3f88
ZA		 1212 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1213 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1214}
1215
759379dd
ZA		 1216static inline u64 get_kernel_ns(void)
1217{
bb0b5812 1218 return ktime_get_boot_ns();
50d0a0f9
GH		 1219}
1220
d828199e 1221#ifdef CONFIG_X86_64
16e8d74d 1222static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1223#endif
16e8d74d 1224
c8076604 1225static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1226static unsigned long max_tsc_khz;
c8076604 1227
cc578287 1228static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1229{
cc578287
ZA		 1230 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1231 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1232}
1233
cc578287 1234static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1235{
cc578287
ZA		 1236 u64 v = (u64)khz * (1000000 + ppm);
1237 do_div(v, 1000000);
1238 return v;
1e993611
JR		 1239}
1240
cc578287 1241static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1242{
cc578287
ZA		 1243 u32 thresh_lo, thresh_hi;
1244 int use_scaling = 0;
217fc9cf 1245
03ba32ca
MT		 1246 /* tsc_khz can be zero if TSC calibration fails */
1247 if (this_tsc_khz == 0)
1248 return;
1249
c285545f
ZA		 1250 /* Compute a scale to convert nanoseconds in TSC cycles */
1251 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1252 &vcpu->arch.virtual_tsc_shift,
1253 &vcpu->arch.virtual_tsc_mult);
1254 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1255
1256 /*
1257 * Compute the variation in TSC rate which is acceptable
1258 * within the range of tolerance and decide if the
1259 * rate being applied is within that bounds of the hardware
1260 * rate. If so, no scaling or compensation need be done.
1261 */
1262 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1263 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1264 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1265 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1266 use_scaling = 1;
1267 }
1268 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1269}
1270
1271static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1272{
e26101b1 1273 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1274 vcpu->arch.virtual_tsc_mult,
1275 vcpu->arch.virtual_tsc_shift);
e26101b1 1276 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1277 return tsc;
1278}
1279
69b0049a 1280static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1281{
1282#ifdef CONFIG_X86_64
1283 bool vcpus_matched;
b48aa97e
MT		 1284 struct kvm_arch *ka = &vcpu->kvm->arch;
1285 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1286
1287 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1288 atomic_read(&vcpu->kvm->online_vcpus));
1289
7f187922
MT		 1290 /*
1291 * Once the masterclock is enabled, always perform request in
1292 * order to update it.
1293 *
1294 * In order to enable masterclock, the host clocksource must be TSC
1295 * and the vcpus need to have matched TSCs. When that happens,
1296 * perform request to enable masterclock.
1297 */
1298 if (ka->use_master_clock ||
1299 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1300 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1301
1302 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1303 atomic_read(&vcpu->kvm->online_vcpus),
1304 ka->use_master_clock, gtod->clock.vclock_mode);
1305#endif
1306}
1307
ba904635
WA		 1308static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1309{
1310 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1311 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1312}
1313
8fe8ab46 1314void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1315{
1316 struct kvm *kvm = vcpu->kvm;
f38e098f 1317 u64 offset, ns, elapsed;
99e3e30a 1318 unsigned long flags;
02626b6a 1319 s64 usdiff;
b48aa97e 1320 bool matched;
0d3da0d2 1321 bool already_matched;
8fe8ab46 1322 u64 data = msr->data;
99e3e30a 1323
038f8c11 1324 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1325 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1326 ns = get_kernel_ns();
f38e098f 1327 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1328
03ba32ca 1329 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1330 int faulted = 0;
1331
03ba32ca
MT		 1332 /* n.b - signed multiplication and division required */
1333 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1334#ifdef CONFIG_X86_64
03ba32ca 1335 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1336#else
03ba32ca 1337 /* do_div() only does unsigned */
8915aa27
MT		 1338 asm("1: idivl %[divisor]\n"
1339 "2: xor %%edx, %%edx\n"
1340 " movl $0, %[faulted]\n"
1341 "3:\n"
1342 ".section .fixup,\"ax\"\n"
1343 "4: movl $1, %[faulted]\n"
1344 " jmp 3b\n"
1345 ".previous\n"
1346
1347 _ASM_EXTABLE(1b, 4b)
1348
1349 : "=A"(usdiff), [faulted] "=r" (faulted)
1350 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1351
5d3cb0f6 1352#endif
03ba32ca
MT		 1353 do_div(elapsed, 1000);
1354 usdiff -= elapsed;
1355 if (usdiff < 0)
1356 usdiff = -usdiff;
8915aa27
MT		 1357
1358 /* idivl overflow => difference is larger than USEC_PER_SEC */
1359 if (faulted)
1360 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1361 } else
1362 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1363
1364 /*
5d3cb0f6
ZA		 1365 * Special case: TSC write with a small delta (1 second) of virtual
1366 * cycle time against real time is interpreted as an attempt to
1367 * synchronize the CPU.
1368 *
1369 * For a reliable TSC, we can match TSC offsets, and for an unstable
1370 * TSC, we add elapsed time in this computation. We could let the
1371 * compensation code attempt to catch up if we fall behind, but
1372 * it's better to try to match offsets from the beginning.
1373 */
02626b6a 1374 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1375 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1376 if (!check_tsc_unstable()) {
e26101b1 1377 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1378 pr_debug("kvm: matched tsc offset for %llu\n", data);
1379 } else {
857e4099 1380 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1381 data += delta;
1382 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1383 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1384 }
b48aa97e 1385 matched = true;
0d3da0d2 1386 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1387 } else {
1388 /*
1389 * We split periods of matched TSC writes into generations.
1390 * For each generation, we track the original measured
1391 * nanosecond time, offset, and write, so if TSCs are in
1392 * sync, we can match exact offset, and if not, we can match
4a969980 1393 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1394 *
1395 * These values are tracked in kvm->arch.cur_xxx variables.
1396 */
1397 kvm->arch.cur_tsc_generation++;
1398 kvm->arch.cur_tsc_nsec = ns;
1399 kvm->arch.cur_tsc_write = data;
1400 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1401 matched = false;
0d3da0d2 1402 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1403 kvm->arch.cur_tsc_generation, data);
f38e098f 1404 }
e26101b1
ZA		 1405
1406 /*
1407 * We also track th most recent recorded KHZ, write and time to
1408 * allow the matching interval to be extended at each write.
1409 */
f38e098f
ZA		 1410 kvm->arch.last_tsc_nsec = ns;
1411 kvm->arch.last_tsc_write = data;
5d3cb0f6 1412 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1413
b183aa58 1414 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1415
1416 /* Keep track of which generation this VCPU has synchronized to */
1417 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1418 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1419 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1420
ba904635
WA		 1421 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1422 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1423 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1424 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1425
1426 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1427 if (!matched) {
b48aa97e 1428 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1429 } else if (!already_matched) {
1430 kvm->arch.nr_vcpus_matched_tsc++;
1431 }
b48aa97e
MT		 1432
1433 kvm_track_tsc_matching(vcpu);
1434 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1435}
e26101b1 1436
99e3e30a
ZA		 1437EXPORT_SYMBOL_GPL(kvm_write_tsc);
1438
d828199e
MT		 1439#ifdef CONFIG_X86_64
1440
1441static cycle_t read_tsc(void)
1442{
1443 cycle_t ret;
1444 u64 last;
1445
1446 /*
1447 * Empirically, a fence (of type that depends on the CPU)
1448 * before rdtsc is enough to ensure that rdtsc is ordered
1449 * with respect to loads. The various CPU manuals are unclear
1450 * as to whether rdtsc can be reordered with later loads,
1451 * but no one has ever seen it happen.
1452 */
1453 rdtsc_barrier();
1454 ret = (cycle_t)vget_cycles();
1455
1456 last = pvclock_gtod_data.clock.cycle_last;
1457
1458 if (likely(ret >= last))
1459 return ret;
1460
1461 /*
1462 * GCC likes to generate cmov here, but this branch is extremely
1463 * predictable (it's just a funciton of time and the likely is
1464 * very likely) and there's a data dependence, so force GCC
1465 * to generate a branch instead. I don't barrier() because
1466 * we don't actually need a barrier, and if this function
1467 * ever gets inlined it will generate worse code.
1468 */
1469 asm volatile ("");
1470 return last;
1471}
1472
1473static inline u64 vgettsc(cycle_t *cycle_now)
1474{
1475 long v;
1476 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1477
1478 *cycle_now = read_tsc();
1479
1480 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1481 return v * gtod->clock.mult;
1482}
1483
cbcf2dd3 1484static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1485{
cbcf2dd3 1486 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1487 unsigned long seq;
d828199e 1488 int mode;
cbcf2dd3 1489 u64 ns;
d828199e 1490
d828199e
MT		 1491 do {
1492 seq = read_seqcount_begin(&gtod->seq);
1493 mode = gtod->clock.vclock_mode;
cbcf2dd3 1494 ns = gtod->nsec_base;
d828199e
MT		 1495 ns += vgettsc(cycle_now);
1496 ns >>= gtod->clock.shift;
cbcf2dd3 1497 ns += gtod->boot_ns;
d828199e 1498 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1499 *t = ns;
d828199e
MT		 1500
1501 return mode;
1502}
1503
1504/* returns true if host is using tsc clocksource */
1505static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1506{
d828199e
MT		 1507 /* checked again under seqlock below */
1508 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1509 return false;
1510
cbcf2dd3 1511 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1512}
1513#endif
1514
1515/*
1516 *
b48aa97e
MT		 1517 * Assuming a stable TSC across physical CPUS, and a stable TSC
1518 * across virtual CPUs, the following condition is possible.
1519 * Each numbered line represents an event visible to both
d828199e
MT		 1520 * CPUs at the next numbered event.
1521 *
1522 * "timespecX" represents host monotonic time. "tscX" represents
1523 * RDTSC value.
1524 *
1525 * VCPU0 on CPU0 | VCPU1 on CPU1
1526 *
1527 * 1. read timespec0,tsc0
1528 * 2. | timespec1 = timespec0 + N
1529 * | tsc1 = tsc0 + M
1530 * 3. transition to guest | transition to guest
1531 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1532 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1533 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1534 *
1535 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1536 *
1537 * - ret0 < ret1
1538 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1539 * ...
1540 * - 0 < N - M => M < N
1541 *
1542 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1543 * always the case (the difference between two distinct xtime instances
1544 * might be smaller then the difference between corresponding TSC reads,
1545 * when updating guest vcpus pvclock areas).
1546 *
1547 * To avoid that problem, do not allow visibility of distinct
1548 * system_timestamp/tsc_timestamp values simultaneously: use a master
1549 * copy of host monotonic time values. Update that master copy
1550 * in lockstep.
1551 *
b48aa97e 1552 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1553 *
1554 */
1555
1556static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1557{
1558#ifdef CONFIG_X86_64
1559 struct kvm_arch *ka = &kvm->arch;
1560 int vclock_mode;
b48aa97e
MT		 1561 bool host_tsc_clocksource, vcpus_matched;
1562
1563 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1564 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1565
1566 /*
1567 * If the host uses TSC clock, then passthrough TSC as stable
1568 * to the guest.
1569 */
b48aa97e 1570 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1571 &ka->master_kernel_ns,
1572 &ka->master_cycle_now);
1573
16a96021 1574 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1575 && !backwards_tsc_observed
1576 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1577
d828199e
MT		 1578 if (ka->use_master_clock)
1579 atomic_set(&kvm_guest_has_master_clock, 1);
1580
1581 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1582 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1583 vcpus_matched);
d828199e
MT		 1584#endif
1585}
1586
2e762ff7
MT		 1587static void kvm_gen_update_masterclock(struct kvm *kvm)
1588{
1589#ifdef CONFIG_X86_64
1590 int i;
1591 struct kvm_vcpu *vcpu;
1592 struct kvm_arch *ka = &kvm->arch;
1593
1594 spin_lock(&ka->pvclock_gtod_sync_lock);
1595 kvm_make_mclock_inprogress_request(kvm);
1596 /* no guest entries from this point */
1597 pvclock_update_vm_gtod_copy(kvm);
1598
1599 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1600 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1601
1602 /* guest entries allowed */
1603 kvm_for_each_vcpu(i, vcpu, kvm)
1604 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1605
1606 spin_unlock(&ka->pvclock_gtod_sync_lock);
1607#endif
1608}
1609
34c238a1 1610static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1611{
d828199e 1612 unsigned long flags, this_tsc_khz;
18068523 1613 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1614 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1615 s64 kernel_ns;
d828199e 1616 u64 tsc_timestamp, host_tsc;
0b79459b 1617 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1618 u8 pvclock_flags;
d828199e
MT		 1619 bool use_master_clock;
1620
1621 kernel_ns = 0;
1622 host_tsc = 0;
18068523 1623
d828199e
MT		 1624 /*
1625 * If the host uses TSC clock, then passthrough TSC as stable
1626 * to the guest.
1627 */
1628 spin_lock(&ka->pvclock_gtod_sync_lock);
1629 use_master_clock = ka->use_master_clock;
1630 if (use_master_clock) {
1631 host_tsc = ka->master_cycle_now;
1632 kernel_ns = ka->master_kernel_ns;
1633 }
1634 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1635
1636 /* Keep irq disabled to prevent changes to the clock */
1637 local_irq_save(flags);
89cbc767 1638 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1639 if (unlikely(this_tsc_khz == 0)) {
1640 local_irq_restore(flags);
1641 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1642 return 1;
1643 }
d828199e
MT		 1644 if (!use_master_clock) {
1645 host_tsc = native_read_tsc();
1646 kernel_ns = get_kernel_ns();
1647 }
1648
1649 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1650
c285545f
ZA		 1651 /*
1652 * We may have to catch up the TSC to match elapsed wall clock
1653 * time for two reasons, even if kvmclock is used.
1654 * 1) CPU could have been running below the maximum TSC rate
1655 * 2) Broken TSC compensation resets the base at each VCPU
1656 * entry to avoid unknown leaps of TSC even when running
1657 * again on the same CPU. This may cause apparent elapsed
1658 * time to disappear, and the guest to stand still or run
1659 * very slowly.
1660 */
1661 if (vcpu->tsc_catchup) {
1662 u64 tsc = compute_guest_tsc(v, kernel_ns);
1663 if (tsc > tsc_timestamp) {
f1e2b260 1664 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1665 tsc_timestamp = tsc;
1666 }
50d0a0f9
GH		 1667 }
1668
18068523
GOC		 1669 local_irq_restore(flags);
1670
0b79459b 1671 if (!vcpu->pv_time_enabled)
c285545f 1672 return 0;
18068523 1673
e48672fa 1674 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1675 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1676 &vcpu->hv_clock.tsc_shift,
1677 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1678 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1679 }
1680
1681 /* With all the info we got, fill in the values */
1d5f066e 1682 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1683 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1684 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1685
09a0c3f1
OH		 1686 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1687 &guest_hv_clock, sizeof(guest_hv_clock))))
1688 return 0;
1689
5dca0d91
RK		 1690 /* This VCPU is paused, but it's legal for a guest to read another
1691 * VCPU's kvmclock, so we really have to follow the specification where
1692 * it says that version is odd if data is being modified, and even after
1693 * it is consistent.
1694 *
1695 * Version field updates must be kept separate. This is because
1696 * kvm_write_guest_cached might use a "rep movs" instruction, and
1697 * writes within a string instruction are weakly ordered. So there
1698 * are three writes overall.
1699 *
1700 * As a small optimization, only write the version field in the first
1701 * and third write. The vcpu->pv_time cache is still valid, because the
1702 * version field is the first in the struct.
18068523 1703 */
5dca0d91
RK		 1704 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1705
1706 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1707 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1708 &vcpu->hv_clock,
1709 sizeof(vcpu->hv_clock.version));
1710
1711 smp_wmb();
78c0337a
MT		 1712
1713 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1714 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1715
1716 if (vcpu->pvclock_set_guest_stopped_request) {
1717 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1718 vcpu->pvclock_set_guest_stopped_request = false;
1719 }
1720
b7e60c5a
MT		 1721 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1722
d828199e
MT		 1723 /* If the host uses TSC clocksource, then it is stable */
1724 if (use_master_clock)
1725 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1726
78c0337a
MT		 1727 vcpu->hv_clock.flags = pvclock_flags;
1728
ce1a5e60
DM		 1729 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1730
0b79459b
AH		 1731 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1732 &vcpu->hv_clock,
1733 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1734
1735 smp_wmb();
1736
1737 vcpu->hv_clock.version++;
1738 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1739 &vcpu->hv_clock,
1740 sizeof(vcpu->hv_clock.version));
8cfdc000 1741 return 0;
c8076604
GH		 1742}
1743
0061d53d
MT		 1744/*
1745 * kvmclock updates which are isolated to a given vcpu, such as
1746 * vcpu->cpu migration, should not allow system_timestamp from
1747 * the rest of the vcpus to remain static. Otherwise ntp frequency
1748 * correction applies to one vcpu's system_timestamp but not
1749 * the others.
1750 *
1751 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1752 * We need to rate-limit these requests though, as they can
1753 * considerably slow guests that have a large number of vcpus.
1754 * The time for a remote vcpu to update its kvmclock is bound
1755 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1756 */
1757
7e44e449
AJ		 1758#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1759
1760static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1761{
1762 int i;
7e44e449
AJ		 1763 struct delayed_work *dwork = to_delayed_work(work);
1764 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1765 kvmclock_update_work);
1766 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1767 struct kvm_vcpu *vcpu;
1768
1769 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1771 kvm_vcpu_kick(vcpu);
1772 }
1773}
1774
7e44e449
AJ		 1775static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1776{
1777 struct kvm *kvm = v->kvm;
1778
105b21bb 1779 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1780 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1781 KVMCLOCK_UPDATE_DELAY);
1782}
1783
332967a3
AJ		 1784#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1785
1786static void kvmclock_sync_fn(struct work_struct *work)
1787{
1788 struct delayed_work *dwork = to_delayed_work(work);
1789 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1790 kvmclock_sync_work);
1791 struct kvm *kvm = container_of(ka, struct kvm, arch);
1792
630994b3
MT		 1793 if (!kvmclock_periodic_sync)
1794 return;
1795
332967a3
AJ		 1796 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1797 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1798 KVMCLOCK_SYNC_PERIOD);
1799}
1800
9ba075a6
AK		 1801static bool msr_mtrr_valid(unsigned msr)
1802{
1803 switch (msr) {
1804 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1805 case MSR_MTRRfix64K_00000:
1806 case MSR_MTRRfix16K_80000:
1807 case MSR_MTRRfix16K_A0000:
1808 case MSR_MTRRfix4K_C0000:
1809 case MSR_MTRRfix4K_C8000:
1810 case MSR_MTRRfix4K_D0000:
1811 case MSR_MTRRfix4K_D8000:
1812 case MSR_MTRRfix4K_E0000:
1813 case MSR_MTRRfix4K_E8000:
1814 case MSR_MTRRfix4K_F0000:
1815 case MSR_MTRRfix4K_F8000:
1816 case MSR_MTRRdefType:
1817 case MSR_IA32_CR_PAT:
1818 return true;
1819 case 0x2f8:
1820 return true;
1821 }
1822 return false;
1823}
1824
d6289b93
MT		 1825static bool valid_pat_type(unsigned t)
1826{
1827 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1828}
1829
1830static bool valid_mtrr_type(unsigned t)
1831{
1832 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1833}
1834
4566654b 1835bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1836{
1837 int i;
fd275235 1838 u64 mask;
d6289b93
MT		 1839
1840 if (!msr_mtrr_valid(msr))
1841 return false;
1842
1843 if (msr == MSR_IA32_CR_PAT) {
1844 for (i = 0; i < 8; i++)
1845 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1846 return false;
1847 return true;
1848 } else if (msr == MSR_MTRRdefType) {
1849 if (data & ~0xcff)
1850 return false;
1851 return valid_mtrr_type(data & 0xff);
1852 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1853 for (i = 0; i < 8 ; i++)
1854 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1855 return false;
1856 return true;
1857 }
1858
1859 /* variable MTRRs */
adfb5d27
WL		 1860 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1861
fd275235 1862 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1863 if ((msr & 1) == 0) {
adfb5d27 1864 /* MTRR base */
d7a2a246
WL		 1865 if (!valid_mtrr_type(data & 0xff))
1866 return false;
1867 mask |= 0xf00;
1868 } else
1869 /* MTRR mask */
1870 mask |= 0x7ff;
1871 if (data & mask) {
1872 kvm_inject_gp(vcpu, 0);
1873 return false;
1874 }
1875
adfb5d27 1876 return true;
d6289b93 1877}
4566654b 1878EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1879
efdfe536
XG		 1880static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr)
1881{
1882 struct mtrr_state_type *mtrr_state = &vcpu->arch.mtrr_state;
1883 unsigned char mtrr_enabled = mtrr_state->enabled;
1884 gfn_t start, end, mask;
1885 int index;
1886 bool is_fixed = true;
1887
1888 if (msr == MSR_IA32_CR_PAT || !tdp_enabled ||
1889 !kvm_arch_has_noncoherent_dma(vcpu->kvm))
1890 return;
1891
1892 if (!(mtrr_enabled & 0x2) && msr != MSR_MTRRdefType)
1893 return;
1894
1895 switch (msr) {
1896 case MSR_MTRRfix64K_00000:
1897 start = 0x0;
1898 end = 0x80000;
1899 break;
1900 case MSR_MTRRfix16K_80000:
1901 start = 0x80000;
1902 end = 0xa0000;
1903 break;
1904 case MSR_MTRRfix16K_A0000:
1905 start = 0xa0000;
1906 end = 0xc0000;
1907 break;
1908 case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000:
1909 index = msr - MSR_MTRRfix4K_C0000;
1910 start = 0xc0000 + index * (32 << 10);
1911 end = start + (32 << 10);
1912 break;
1913 case MSR_MTRRdefType:
1914 is_fixed = false;
1915 start = 0x0;
1916 end = ~0ULL;
1917 break;
1918 default:
1919 /* variable range MTRRs. */
1920 is_fixed = false;
1921 index = (msr - 0x200) / 2;
1922 start = (((u64)mtrr_state->var_ranges[index].base_hi) << 32) +
1923 (mtrr_state->var_ranges[index].base_lo & PAGE_MASK);
1924 mask = (((u64)mtrr_state->var_ranges[index].mask_hi) << 32) +
1925 (mtrr_state->var_ranges[index].mask_lo & PAGE_MASK);
1926 mask |= ~0ULL << cpuid_maxphyaddr(vcpu);
1927
1928 end = ((start & mask) | ~mask) + 1;
1929 }
1930
1931 if (is_fixed && !(mtrr_enabled & 0x1))
1932 return;
1933
1934 kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end));
1935}
1936
9ba075a6
AK		 1937static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1938{
0bed3b56
SY		 1939 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1940
4566654b 1941 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1942 return 1;
1943
0bed3b56
SY		 1944 if (msr == MSR_MTRRdefType) {
1945 vcpu->arch.mtrr_state.def_type = data;
1946 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1947 } else if (msr == MSR_MTRRfix64K_00000)
1948 p[0] = data;
1949 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1950 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1951 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1952 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1953 else if (msr == MSR_IA32_CR_PAT)
1954 vcpu->arch.pat = data;
1955 else { /* Variable MTRRs */
1956 int idx, is_mtrr_mask;
1957 u64 *pt;
1958
1959 idx = (msr - 0x200) / 2;
1960 is_mtrr_mask = msr - 0x200 - 2 * idx;
1961 if (!is_mtrr_mask)
1962 pt =
1963 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1964 else
1965 pt =
1966 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1967 *pt = data;
1968 }
1969
efdfe536 1970 update_mtrr(vcpu, msr);
9ba075a6
AK		 1971 return 0;
1972}
15c4a640 1973
890ca9ae 1974static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1975{
890ca9ae
HY		 1976 u64 mcg_cap = vcpu->arch.mcg_cap;
1977 unsigned bank_num = mcg_cap & 0xff;
1978
15c4a640 1979 switch (msr) {
15c4a640 1980 case MSR_IA32_MCG_STATUS:
890ca9ae 1981 vcpu->arch.mcg_status = data;
15c4a640 1982 break;
c7ac679c 1983 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1984 if (!(mcg_cap & MCG_CTL_P))
1985 return 1;
1986 if (data != 0 && data != ~(u64)0)
1987 return -1;
1988 vcpu->arch.mcg_ctl = data;
1989 break;
1990 default:
1991 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1992 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1993 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1994 /* only 0 or all 1s can be written to IA32_MCi_CTL
1995 * some Linux kernels though clear bit 10 in bank 4 to
1996 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1997 * this to avoid an uncatched #GP in the guest
1998 */
890ca9ae 1999 if ((offset & 0x3) == 0 &&
114be429 2000 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2001 return -1;
2002 vcpu->arch.mce_banks[offset] = data;
2003 break;
2004 }
2005 return 1;
2006 }
2007 return 0;
2008}
2009
ffde22ac
ES		 2010static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2011{
2012 struct kvm *kvm = vcpu->kvm;
2013 int lm = is_long_mode(vcpu);
2014 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2015 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2016 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2017 : kvm->arch.xen_hvm_config.blob_size_32;
2018 u32 page_num = data & ~PAGE_MASK;
2019 u64 page_addr = data & PAGE_MASK;
2020 u8 *page;
2021 int r;
2022
2023 r = -E2BIG;
2024 if (page_num >= blob_size)
2025 goto out;
2026 r = -ENOMEM;
ff5c2c03
SL		 2027 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2028 if (IS_ERR(page)) {
2029 r = PTR_ERR(page);
ffde22ac 2030 goto out;
ff5c2c03 2031 }
ffde22ac
ES		 2032 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
2033 goto out_free;
2034 r = 0;
2035out_free:
2036 kfree(page);
2037out:
2038 return r;
2039}
2040
55cd8e5a
GN		 2041static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
2042{
2043 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
2044}
2045
2046static bool kvm_hv_msr_partition_wide(u32 msr)
2047{
2048 bool r = false;
2049 switch (msr) {
2050 case HV_X64_MSR_GUEST_OS_ID:
2051 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 2052 case HV_X64_MSR_REFERENCE_TSC:
2053 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 2054 r = true;
2055 break;
2056 }
2057
2058 return r;
2059}
2060
2061static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2062{
2063 struct kvm *kvm = vcpu->kvm;
2064
2065 switch (msr) {
2066 case HV_X64_MSR_GUEST_OS_ID:
2067 kvm->arch.hv_guest_os_id = data;
2068 /* setting guest os id to zero disables hypercall page */
2069 if (!kvm->arch.hv_guest_os_id)
2070 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
2071 break;
2072 case HV_X64_MSR_HYPERCALL: {
2073 u64 gfn;
2074 unsigned long addr;
2075 u8 instructions[4];
2076
2077 /* if guest os id is not set hypercall should remain disabled */
2078 if (!kvm->arch.hv_guest_os_id)
2079 break;
2080 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2081 kvm->arch.hv_hypercall = data;
2082 break;
2083 }
2084 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2085 addr = gfn_to_hva(kvm, gfn);
2086 if (kvm_is_error_hva(addr))
2087 return 1;
2088 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2089 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2090 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2091 return 1;
2092 kvm->arch.hv_hypercall = data;
b94b64c9 2093 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2094 break;
2095 }
e984097b
VR		 2096 case HV_X64_MSR_REFERENCE_TSC: {
2097 u64 gfn;
2098 HV_REFERENCE_TSC_PAGE tsc_ref;
2099 memset(&tsc_ref, 0, sizeof(tsc_ref));
2100 kvm->arch.hv_tsc_page = data;
2101 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2102 break;
2103 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2104 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2105 &tsc_ref, sizeof(tsc_ref)))
2106 return 1;
2107 mark_page_dirty(kvm, gfn);
2108 break;
2109 }
55cd8e5a 2110 default:
a737f256
CD		 2111 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2112 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2113 return 1;
2114 }
2115 return 0;
2116}
2117
2118static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2119{
10388a07
GN		 2120 switch (msr) {
2121 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2122 u64 gfn;
10388a07 2123 unsigned long addr;
55cd8e5a 2124
10388a07
GN		 2125 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2126 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2127 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2128 return 1;
10388a07
GN		 2129 break;
2130 }
b3af1e88
VR		 2131 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2132 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2133 if (kvm_is_error_hva(addr))
2134 return 1;
8b0cedff 2135 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2136 return 1;
2137 vcpu->arch.hv_vapic = data;
b3af1e88 2138 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2139 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2140 return 1;
10388a07
GN		 2141 break;
2142 }
2143 case HV_X64_MSR_EOI:
2144 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2145 case HV_X64_MSR_ICR:
2146 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2147 case HV_X64_MSR_TPR:
2148 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2149 default:
a737f256
CD		 2150 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2151 "data 0x%llx\n", msr, data);
10388a07
GN		 2152 return 1;
2153 }
2154
2155 return 0;
55cd8e5a
GN		 2156}
2157
344d9588
GN		 2158static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2159{
2160 gpa_t gpa = data & ~0x3f;
2161
4a969980 2162 /* Bits 2:5 are reserved, Should be zero */
6adba527 2163 if (data & 0x3c)
344d9588
GN		 2164 return 1;
2165
2166 vcpu->arch.apf.msr_val = data;
2167
2168 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2169 kvm_clear_async_pf_completion_queue(vcpu);
2170 kvm_async_pf_hash_reset(vcpu);
2171 return 0;
2172 }
2173
8f964525
AH		 2174 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2175 sizeof(u32)))
344d9588
GN		 2176 return 1;
2177
6adba527 2178 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2179 kvm_async_pf_wakeup_all(vcpu);
2180 return 0;
2181}
2182
12f9a48f
GC		 2183static void kvmclock_reset(struct kvm_vcpu *vcpu)
2184{
0b79459b 2185 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2186}
2187
c9aaa895
GC		 2188static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2189{
2190 u64 delta;
2191
2192 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2193 return;
2194
2195 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2196 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2197 vcpu->arch.st.accum_steal = delta;
2198}
2199
2200static void record_steal_time(struct kvm_vcpu *vcpu)
2201{
2202 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2203 return;
2204
2205 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2206 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2207 return;
2208
2209 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2210 vcpu->arch.st.steal.version += 2;
2211 vcpu->arch.st.accum_steal = 0;
2212
2213 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2214 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2215}
2216
8fe8ab46 2217int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2218{
5753785f 2219 bool pr = false;
8fe8ab46
WA		 2220 u32 msr = msr_info->index;
2221 u64 data = msr_info->data;
5753785f 2222
15c4a640 2223 switch (msr) {
2e32b719
BP		 2224 case MSR_AMD64_NB_CFG:
2225 case MSR_IA32_UCODE_REV:
2226 case MSR_IA32_UCODE_WRITE:
2227 case MSR_VM_HSAVE_PA:
2228 case MSR_AMD64_PATCH_LOADER:
2229 case MSR_AMD64_BU_CFG2:
2230 break;
2231
15c4a640 2232 case MSR_EFER:
b69e8cae 2233 return set_efer(vcpu, data);
8f1589d9
AP		 2234 case MSR_K7_HWCR:
2235 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2236 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2237 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2238 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2239 if (data != 0) {
a737f256
CD		 2240 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2241 data);
8f1589d9
AP		 2242 return 1;
2243 }
15c4a640 2244 break;
f7c6d140
AP		 2245 case MSR_FAM10H_MMIO_CONF_BASE:
2246 if (data != 0) {
a737f256
CD		 2247 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2248 "0x%llx\n", data);
f7c6d140
AP		 2249 return 1;
2250 }
15c4a640 2251 break;
b5e2fec0
AG		 2252 case MSR_IA32_DEBUGCTLMSR:
2253 if (!data) {
2254 /* We support the non-activated case already */
2255 break;
2256 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2257 /* Values other than LBR and BTF are vendor-specific,
2258 thus reserved and should throw a #GP */
2259 return 1;
2260 }
a737f256
CD		 2261 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2262 __func__, data);
b5e2fec0 2263 break;
9ba075a6
AK		 2264 case 0x200 ... 0x2ff:
2265 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2266 case MSR_IA32_APICBASE:
58cb628d 2267 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2268 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2269 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2270 case MSR_IA32_TSCDEADLINE:
2271 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2272 break;
ba904635
WA		 2273 case MSR_IA32_TSC_ADJUST:
2274 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2275 if (!msr_info->host_initiated) {
d913b904 2276 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2277 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2278 }
2279 vcpu->arch.ia32_tsc_adjust_msr = data;
2280 }
2281 break;
15c4a640 2282 case MSR_IA32_MISC_ENABLE:
ad312c7c 2283 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2284 break;
11c6bffa 2285 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2286 case MSR_KVM_WALL_CLOCK:
2287 vcpu->kvm->arch.wall_clock = data;
2288 kvm_write_wall_clock(vcpu->kvm, data);
2289 break;
11c6bffa 2290 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2291 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2292 u64 gpa_offset;
54750f2c
MT		 2293 struct kvm_arch *ka = &vcpu->kvm->arch;
2294
12f9a48f 2295 kvmclock_reset(vcpu);
18068523 2296
54750f2c
MT		 2297 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2298 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2299
2300 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2301 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2302 &vcpu->requests);
2303
2304 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2305
2306 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2307 }
2308
18068523 2309 vcpu->arch.time = data;
0061d53d 2310 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2311
2312 /* we verify if the enable bit is set... */
2313 if (!(data & 1))
2314 break;
2315
0b79459b 2316 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2317
0b79459b 2318 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2319 &vcpu->arch.pv_time, data & ~1ULL,
2320 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2321 vcpu->arch.pv_time_enabled = false;
2322 else
2323 vcpu->arch.pv_time_enabled = true;
32cad84f 2324
18068523
GOC		 2325 break;
2326 }
344d9588
GN		 2327 case MSR_KVM_ASYNC_PF_EN:
2328 if (kvm_pv_enable_async_pf(vcpu, data))
2329 return 1;
2330 break;
c9aaa895
GC		 2331 case MSR_KVM_STEAL_TIME:
2332
2333 if (unlikely(!sched_info_on()))
2334 return 1;
2335
2336 if (data & KVM_STEAL_RESERVED_MASK)
2337 return 1;
2338
2339 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2340 data & KVM_STEAL_VALID_BITS,
2341 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2342 return 1;
2343
2344 vcpu->arch.st.msr_val = data;
2345
2346 if (!(data & KVM_MSR_ENABLED))
2347 break;
2348
2349 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2350
2351 preempt_disable();
2352 accumulate_steal_time(vcpu);
2353 preempt_enable();
2354
2355 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2356
2357 break;
ae7a2a3f
MT		 2358 case MSR_KVM_PV_EOI_EN:
2359 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2360 return 1;
2361 break;
c9aaa895 2362
890ca9ae
HY		 2363 case MSR_IA32_MCG_CTL:
2364 case MSR_IA32_MCG_STATUS:
81760dcc 2365 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2366 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2367
2368 /* Performance counters are not protected by a CPUID bit,
2369 * so we should check all of them in the generic path for the sake of
2370 * cross vendor migration.
2371 * Writing a zero into the event select MSRs disables them,
2372 * which we perfectly emulate ;-). Any other value should be at least
2373 * reported, some guests depend on them.
2374 */
71db6023
AP		 2375 case MSR_K7_EVNTSEL0:
2376 case MSR_K7_EVNTSEL1:
2377 case MSR_K7_EVNTSEL2:
2378 case MSR_K7_EVNTSEL3:
2379 if (data != 0)
a737f256
CD		 2380 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2381 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2382 break;
2383 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2384 * so we ignore writes to make it happy.
2385 */
71db6023
AP		 2386 case MSR_K7_PERFCTR0:
2387 case MSR_K7_PERFCTR1:
2388 case MSR_K7_PERFCTR2:
2389 case MSR_K7_PERFCTR3:
a737f256
CD		 2390 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2391 "0x%x data 0x%llx\n", msr, data);
71db6023 2392 break;
5753785f
GN		 2393 case MSR_P6_PERFCTR0:
2394 case MSR_P6_PERFCTR1:
2395 pr = true;
2396 case MSR_P6_EVNTSEL0:
2397 case MSR_P6_EVNTSEL1:
2398 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2399 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2400
2401 if (pr || data != 0)
a737f256
CD		 2402 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2403 "0x%x data 0x%llx\n", msr, data);
5753785f 2404 break;
84e0cefa
JS		 2405 case MSR_K7_CLK_CTL:
2406 /*
2407 * Ignore all writes to this no longer documented MSR.
2408 * Writes are only relevant for old K7 processors,
2409 * all pre-dating SVM, but a recommended workaround from
4a969980 2410 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2411 * affected processor models on the command line, hence
2412 * the need to ignore the workaround.
2413 */
2414 break;
55cd8e5a
GN		 2415 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2416 if (kvm_hv_msr_partition_wide(msr)) {
2417 int r;
2418 mutex_lock(&vcpu->kvm->lock);
2419 r = set_msr_hyperv_pw(vcpu, msr, data);
2420 mutex_unlock(&vcpu->kvm->lock);
2421 return r;
2422 } else
2423 return set_msr_hyperv(vcpu, msr, data);
2424 break;
91c9c3ed 2425 case MSR_IA32_BBL_CR_CTL3:
2426 /* Drop writes to this legacy MSR -- see rdmsr
2427 * counterpart for further detail.
2428 */
a737f256 2429 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2430 break;
2b036c6b
BO		 2431 case MSR_AMD64_OSVW_ID_LENGTH:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
2434 vcpu->arch.osvw.length = data;
2435 break;
2436 case MSR_AMD64_OSVW_STATUS:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
2439 vcpu->arch.osvw.status = data;
2440 break;
15c4a640 2441 default:
ffde22ac
ES		 2442 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2443 return xen_hvm_config(vcpu, data);
f5132b01 2444 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2445 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2446 if (!ignore_msrs) {
a737f256
CD		 2447 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2448 msr, data);
ed85c068
AP		 2449 return 1;
2450 } else {
a737f256
CD		 2451 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2452 msr, data);
ed85c068
AP		 2453 break;
2454 }
15c4a640
CO		 2455 }
2456 return 0;
2457}
2458EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2459
2460
2461/*
2462 * Reads an msr value (of 'msr_index') into 'pdata'.
2463 * Returns 0 on success, non-0 otherwise.
2464 * Assumes vcpu_load() was already called.
2465 */
609e36d3 2466int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2467{
609e36d3 2468 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2469}
ff651cb6 2470EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2471
9ba075a6
AK		 2472static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2473{
0bed3b56
SY		 2474 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2475
9ba075a6
AK		 2476 if (!msr_mtrr_valid(msr))
2477 return 1;
2478
0bed3b56
SY		 2479 if (msr == MSR_MTRRdefType)
2480 *pdata = vcpu->arch.mtrr_state.def_type +
2481 (vcpu->arch.mtrr_state.enabled << 10);
2482 else if (msr == MSR_MTRRfix64K_00000)
2483 *pdata = p[0];
2484 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2485 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2486 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2487 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2488 else if (msr == MSR_IA32_CR_PAT)
2489 *pdata = vcpu->arch.pat;
2490 else { /* Variable MTRRs */
2491 int idx, is_mtrr_mask;
2492 u64 *pt;
2493
2494 idx = (msr - 0x200) / 2;
2495 is_mtrr_mask = msr - 0x200 - 2 * idx;
2496 if (!is_mtrr_mask)
2497 pt =
2498 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2499 else
2500 pt =
2501 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2502 *pdata = *pt;
2503 }
2504
9ba075a6
AK		 2505 return 0;
2506}
2507
890ca9ae 2508static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2509{
2510 u64 data;
890ca9ae
HY		 2511 u64 mcg_cap = vcpu->arch.mcg_cap;
2512 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2513
2514 switch (msr) {
15c4a640
CO		 2515 case MSR_IA32_P5_MC_ADDR:
2516 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2517 data = 0;
2518 break;
15c4a640 2519 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2520 data = vcpu->arch.mcg_cap;
2521 break;
c7ac679c 2522 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2523 if (!(mcg_cap & MCG_CTL_P))
2524 return 1;
2525 data = vcpu->arch.mcg_ctl;
2526 break;
2527 case MSR_IA32_MCG_STATUS:
2528 data = vcpu->arch.mcg_status;
2529 break;
2530 default:
2531 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2532 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2533 u32 offset = msr - MSR_IA32_MC0_CTL;
2534 data = vcpu->arch.mce_banks[offset];
2535 break;
2536 }
2537 return 1;
2538 }
2539 *pdata = data;
2540 return 0;
2541}
2542
55cd8e5a
GN		 2543static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2544{
2545 u64 data = 0;
2546 struct kvm *kvm = vcpu->kvm;
2547
2548 switch (msr) {
2549 case HV_X64_MSR_GUEST_OS_ID:
2550 data = kvm->arch.hv_guest_os_id;
2551 break;
2552 case HV_X64_MSR_HYPERCALL:
2553 data = kvm->arch.hv_hypercall;
2554 break;
e984097b
VR		 2555 case HV_X64_MSR_TIME_REF_COUNT: {
2556 data =
2557 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2558 break;
2559 }
2560 case HV_X64_MSR_REFERENCE_TSC:
2561 data = kvm->arch.hv_tsc_page;
2562 break;
55cd8e5a 2563 default:
a737f256 2564 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2565 return 1;
2566 }
2567
2568 *pdata = data;
2569 return 0;
2570}
2571
2572static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2573{
2574 u64 data = 0;
2575
2576 switch (msr) {
2577 case HV_X64_MSR_VP_INDEX: {
2578 int r;
2579 struct kvm_vcpu *v;
684851a1
TY		 2580 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2581 if (v == vcpu) {
55cd8e5a 2582 data = r;
684851a1
TY		 2583 break;
2584 }
2585 }
55cd8e5a
GN		 2586 break;
2587 }
10388a07
GN		 2588 case HV_X64_MSR_EOI:
2589 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2590 case HV_X64_MSR_ICR:
2591 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2592 case HV_X64_MSR_TPR:
2593 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2594 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2595 data = vcpu->arch.hv_vapic;
2596 break;
55cd8e5a 2597 default:
a737f256 2598 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2599 return 1;
2600 }
2601 *pdata = data;
2602 return 0;
2603}
2604
609e36d3 2605int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae
HY		 2606{
2607 u64 data;
2608
609e36d3 2609 switch (msr_info->index) {
890ca9ae 2610 case MSR_IA32_PLATFORM_ID:
15c4a640 2611 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2612 case MSR_IA32_DEBUGCTLMSR:
2613 case MSR_IA32_LASTBRANCHFROMIP:
2614 case MSR_IA32_LASTBRANCHTOIP:
2615 case MSR_IA32_LASTINTFROMIP:
2616 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2617 case MSR_K8_SYSCFG:
2618 case MSR_K7_HWCR:
61a6bd67 2619 case MSR_VM_HSAVE_PA:
9e699624 2620 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2621 case MSR_K7_EVNTSEL1:
2622 case MSR_K7_EVNTSEL2:
2623 case MSR_K7_EVNTSEL3:
1f3ee616 2624 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2625 case MSR_K7_PERFCTR1:
2626 case MSR_K7_PERFCTR2:
2627 case MSR_K7_PERFCTR3:
1fdbd48c 2628 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2629 case MSR_AMD64_NB_CFG:
f7c6d140 2630 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2631 case MSR_AMD64_BU_CFG2:
609e36d3 2632 msr_info->data = 0;
15c4a640 2633 break;
5753785f
GN		 2634 case MSR_P6_PERFCTR0:
2635 case MSR_P6_PERFCTR1:
2636 case MSR_P6_EVNTSEL0:
2637 case MSR_P6_EVNTSEL1:
609e36d3
PB		 2638 if (kvm_pmu_msr(vcpu, msr_info->index))
2639 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2640 msr_info->data = 0;
5753785f 2641 break;
742bc670 2642 case MSR_IA32_UCODE_REV:
609e36d3 2643 msr_info->data = 0x100000000ULL;
742bc670 2644 break;
9ba075a6 2645 case MSR_MTRRcap:
609e36d3 2646 msr_info->data = 0x500 | KVM_NR_VAR_MTRR;
9ba075a6
AK		 2647 break;
2648 case 0x200 ... 0x2ff:
609e36d3 2649 return get_msr_mtrr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2650 case 0xcd: /* fsb frequency */
609e36d3 2651 msr_info->data = 3;
15c4a640 2652 break;
7b914098
JS		 2653 /*
2654 * MSR_EBC_FREQUENCY_ID
2655 * Conservative value valid for even the basic CPU models.
2656 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2657 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2658 * and 266MHz for model 3, or 4. Set Core Clock
2659 * Frequency to System Bus Frequency Ratio to 1 (bits
2660 * 31:24) even though these are only valid for CPU
2661 * models > 2, however guests may end up dividing or
2662 * multiplying by zero otherwise.
2663 */
2664 case MSR_EBC_FREQUENCY_ID:
609e36d3 2665 msr_info->data = 1 << 24;
7b914098 2666 break;
15c4a640 2667 case MSR_IA32_APICBASE:
609e36d3 2668 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2669 break;
0105d1a5 2670 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2671 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2672 break;
a3e06bbe 2673 case MSR_IA32_TSCDEADLINE:
609e36d3 2674 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2675 break;
ba904635 2676 case MSR_IA32_TSC_ADJUST:
609e36d3 2677 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2678 break;
15c4a640 2679 case MSR_IA32_MISC_ENABLE:
609e36d3 2680 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2681 break;
847f0ad8
AG		 2682 case MSR_IA32_PERF_STATUS:
2683 /* TSC increment by tick */
609e36d3 2684 msr_info->data = 1000ULL;
847f0ad8
AG		 2685 /* CPU multiplier */
2686 data |= (((uint64_t)4ULL) << 40);
2687 break;
15c4a640 2688 case MSR_EFER:
609e36d3 2689 msr_info->data = vcpu->arch.efer;
15c4a640 2690 break;
18068523 2691 case MSR_KVM_WALL_CLOCK:
11c6bffa 2692 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2693 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2694 break;
2695 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2696 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2697 msr_info->data = vcpu->arch.time;
18068523 2698 break;
344d9588 2699 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2700 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2701 break;
c9aaa895 2702 case MSR_KVM_STEAL_TIME:
609e36d3 2703 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2704 break;
1d92128f 2705 case MSR_KVM_PV_EOI_EN:
609e36d3 2706 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2707 break;
890ca9ae
HY		 2708 case MSR_IA32_P5_MC_ADDR:
2709 case MSR_IA32_P5_MC_TYPE:
2710 case MSR_IA32_MCG_CAP:
2711 case MSR_IA32_MCG_CTL:
2712 case MSR_IA32_MCG_STATUS:
81760dcc 2713 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2714 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2715 case MSR_K7_CLK_CTL:
2716 /*
2717 * Provide expected ramp-up count for K7. All other
2718 * are set to zero, indicating minimum divisors for
2719 * every field.
2720 *
2721 * This prevents guest kernels on AMD host with CPU
2722 * type 6, model 8 and higher from exploding due to
2723 * the rdmsr failing.
2724 */
609e36d3 2725 msr_info->data = 0x20000000;
84e0cefa 2726 break;
55cd8e5a 2727 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
609e36d3 2728 if (kvm_hv_msr_partition_wide(msr_info->index)) {
55cd8e5a
GN		 2729 int r;
2730 mutex_lock(&vcpu->kvm->lock);
609e36d3 2731 r = get_msr_hyperv_pw(vcpu, msr_info->index, &msr_info->data);
55cd8e5a
GN		 2732 mutex_unlock(&vcpu->kvm->lock);
2733 return r;
2734 } else
609e36d3 2735 return get_msr_hyperv(vcpu, msr_info->index, &msr_info->data);
55cd8e5a 2736 break;
91c9c3ed 2737 case MSR_IA32_BBL_CR_CTL3:
2738 /* This legacy MSR exists but isn't fully documented in current
2739 * silicon. It is however accessed by winxp in very narrow
2740 * scenarios where it sets bit #19, itself documented as
2741 * a "reserved" bit. Best effort attempt to source coherent
2742 * read data here should the balance of the register be
2743 * interpreted by the guest:
2744 *
2745 * L2 cache control register 3: 64GB range, 256KB size,
2746 * enabled, latency 0x1, configured
2747 */
609e36d3 2748 msr_info->data = 0xbe702111;
91c9c3ed 2749 break;
2b036c6b
BO		 2750 case MSR_AMD64_OSVW_ID_LENGTH:
2751 if (!guest_cpuid_has_osvw(vcpu))
2752 return 1;
609e36d3 2753 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2754 break;
2755 case MSR_AMD64_OSVW_STATUS:
2756 if (!guest_cpuid_has_osvw(vcpu))
2757 return 1;
609e36d3 2758 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2759 break;
15c4a640 2760 default:
609e36d3
PB		 2761 if (kvm_pmu_msr(vcpu, msr_info->index))
2762 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2763 if (!ignore_msrs) {
609e36d3 2764 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2765 return 1;
2766 } else {
609e36d3
PB		 2767 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2768 msr_info->data = 0;
ed85c068
AP		 2769 }
2770 break;
15c4a640 2771 }
15c4a640
CO		 2772 return 0;
2773}
2774EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2775
313a3dc7
CO		 2776/*
2777 * Read or write a bunch of msrs. All parameters are kernel addresses.
2778 *
2779 * @return number of msrs set successfully.
2780 */
2781static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2782 struct kvm_msr_entry *entries,
2783 int (*do_msr)(struct kvm_vcpu *vcpu,
2784 unsigned index, u64 *data))
2785{
f656ce01 2786 int i, idx;
313a3dc7 2787
f656ce01 2788 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2789 for (i = 0; i < msrs->nmsrs; ++i)
2790 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2791 break;
f656ce01 2792 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2793
313a3dc7
CO		 2794 return i;
2795}
2796
2797/*
2798 * Read or write a bunch of msrs. Parameters are user addresses.
2799 *
2800 * @return number of msrs set successfully.
2801 */
2802static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2803 int (*do_msr)(struct kvm_vcpu *vcpu,
2804 unsigned index, u64 *data),
2805 int writeback)
2806{
2807 struct kvm_msrs msrs;
2808 struct kvm_msr_entry *entries;
2809 int r, n;
2810 unsigned size;
2811
2812 r = -EFAULT;
2813 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2814 goto out;
2815
2816 r = -E2BIG;
2817 if (msrs.nmsrs >= MAX_IO_MSRS)
2818 goto out;
2819
313a3dc7 2820 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2821 entries = memdup_user(user_msrs->entries, size);
2822 if (IS_ERR(entries)) {
2823 r = PTR_ERR(entries);
313a3dc7 2824 goto out;
ff5c2c03 2825 }
313a3dc7
CO		 2826
2827 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2828 if (r < 0)
2829 goto out_free;
2830
2831 r = -EFAULT;
2832 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2833 goto out_free;
2834
2835 r = n;
2836
2837out_free:
7a73c028 2838 kfree(entries);
313a3dc7
CO		 2839out:
2840 return r;
2841}
2842
784aa3d7 2843int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2844{
2845 int r;
2846
2847 switch (ext) {
2848 case KVM_CAP_IRQCHIP:
2849 case KVM_CAP_HLT:
2850 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2851 case KVM_CAP_SET_TSS_ADDR:
07716717 2852 case KVM_CAP_EXT_CPUID:
9c15bb1d 2853 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2854 case KVM_CAP_CLOCKSOURCE:
7837699f 2855 case KVM_CAP_PIT:
a28e4f5a 2856 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2857 case KVM_CAP_MP_STATE:
ed848624 2858 case KVM_CAP_SYNC_MMU:
a355c85c 2859 case KVM_CAP_USER_NMI:
52d939a0 2860 case KVM_CAP_REINJECT_CONTROL:
4925663a 2861 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2862 case KVM_CAP_IOEVENTFD:
f848a5a8 2863 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2864 case KVM_CAP_PIT2:
e9f42757 2865 case KVM_CAP_PIT_STATE2:
b927a3ce 2866 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2867 case KVM_CAP_XEN_HVM:
afbcf7ab 2868 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2869 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2870 case KVM_CAP_HYPERV:
10388a07 2871 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2872 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2873 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2874 case KVM_CAP_DEBUGREGS:
d2be1651 2875 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2876 case KVM_CAP_XSAVE:
344d9588 2877 case KVM_CAP_ASYNC_PF:
92a1f12d 2878 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2879 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2880 case KVM_CAP_READONLY_MEM:
5f66b620 2881 case KVM_CAP_HYPERV_TIME:
100943c5 2882 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2883 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2884 case KVM_CAP_ENABLE_CAP_VM:
2885 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2886#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2887 case KVM_CAP_ASSIGN_DEV_IRQ:
2888 case KVM_CAP_PCI_2_3:
2889#endif
018d00d2
ZX		 2890 r = 1;
2891 break;
542472b5
LV		 2892 case KVM_CAP_COALESCED_MMIO:
2893 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2894 break;
774ead3a
AK		 2895 case KVM_CAP_VAPIC:
2896 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2897 break;
f725230a 2898 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2899 r = KVM_SOFT_MAX_VCPUS;
2900 break;
2901 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2902 r = KVM_MAX_VCPUS;
2903 break;
a988b910 2904 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2905 r = KVM_USER_MEM_SLOTS;
a988b910 2906 break;
a68a6a72
MT		 2907 case KVM_CAP_PV_MMU: /* obsolete */
2908 r = 0;
2f333bcb 2909 break;
4cee4b72 2910#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2911 case KVM_CAP_IOMMU:
a1b60c1c 2912 r = iommu_present(&pci_bus_type);
62c476c7 2913 break;
4cee4b72 2914#endif
890ca9ae
HY		 2915 case KVM_CAP_MCE:
2916 r = KVM_MAX_MCE_BANKS;
2917 break;
2d5b5a66
SY		 2918 case KVM_CAP_XCRS:
2919 r = cpu_has_xsave;
2920 break;
92a1f12d
JR		 2921 case KVM_CAP_TSC_CONTROL:
2922 r = kvm_has_tsc_control;
2923 break;
018d00d2
ZX		 2924 default:
2925 r = 0;
2926 break;
2927 }
2928 return r;
2929
2930}
2931
043405e1
CO		 2932long kvm_arch_dev_ioctl(struct file *filp,
2933 unsigned int ioctl, unsigned long arg)
2934{
2935 void __user *argp = (void __user *)arg;
2936 long r;
2937
2938 switch (ioctl) {
2939 case KVM_GET_MSR_INDEX_LIST: {
2940 struct kvm_msr_list __user *user_msr_list = argp;
2941 struct kvm_msr_list msr_list;
2942 unsigned n;
2943
2944 r = -EFAULT;
2945 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2946 goto out;
2947 n = msr_list.nmsrs;
62ef68bb 2948 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2949 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2950 goto out;
2951 r = -E2BIG;
e125e7b6 2952 if (n < msr_list.nmsrs)
043405e1
CO		 2953 goto out;
2954 r = -EFAULT;
2955 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2956 num_msrs_to_save * sizeof(u32)))
2957 goto out;
e125e7b6 2958 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2959 &emulated_msrs,
62ef68bb 2960 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2961 goto out;
2962 r = 0;
2963 break;
2964 }
9c15bb1d
BP		 2965 case KVM_GET_SUPPORTED_CPUID:
2966 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2967 struct kvm_cpuid2 __user *cpuid_arg = argp;
2968 struct kvm_cpuid2 cpuid;
2969
2970 r = -EFAULT;
2971 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2972 goto out;
9c15bb1d
BP		 2973
2974 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2975 ioctl);
674eea0f
AK		 2976 if (r)
2977 goto out;
2978
2979 r = -EFAULT;
2980 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2981 goto out;
2982 r = 0;
2983 break;
2984 }
890ca9ae
HY		 2985 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2986 u64 mce_cap;
2987
2988 mce_cap = KVM_MCE_CAP_SUPPORTED;
2989 r = -EFAULT;
2990 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2991 goto out;
2992 r = 0;
2993 break;
2994 }
043405e1
CO		 2995 default:
2996 r = -EINVAL;
2997 }
2998out:
2999 return r;
3000}
3001
f5f48ee1
SY		 3002static void wbinvd_ipi(void *garbage)
3003{
3004 wbinvd();
3005}
3006
3007static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3008{
e0f0bbc5 3009 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3010}
3011
313a3dc7
CO		 3012void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3013{
f5f48ee1
SY		 3014 /* Address WBINVD may be executed by guest */
3015 if (need_emulate_wbinvd(vcpu)) {
3016 if (kvm_x86_ops->has_wbinvd_exit())
3017 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3018 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3019 smp_call_function_single(vcpu->cpu,
3020 wbinvd_ipi, NULL, 1);
3021 }
3022
313a3dc7 3023 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3024
0dd6a6ed
ZA		 3025 /* Apply any externally detected TSC adjustments (due to suspend) */
3026 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3027 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3028 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3030 }
8f6055cb 3031
48434c20 3032 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 3033 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3034 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3035 if (tsc_delta < 0)
3036 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 3037 if (check_tsc_unstable()) {
b183aa58
ZA		 3038 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
3039 vcpu->arch.last_guest_tsc);
3040 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 3041 vcpu->arch.tsc_catchup = 1;
c285545f 3042 }
d98d07ca
MT		 3043 /*
3044 * On a host with synchronized TSC, there is no need to update
3045 * kvmclock on vcpu->cpu migration
3046 */
3047 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3048 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 3049 if (vcpu->cpu != cpu)
3050 kvm_migrate_timers(vcpu);
e48672fa 3051 vcpu->cpu = cpu;
6b7d7e76 3052 }
c9aaa895
GC		 3053
3054 accumulate_steal_time(vcpu);
3055 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3056}
3057
3058void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3059{
02daab21 3060 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 3061 kvm_put_guest_fpu(vcpu);
6f526ec5 3062 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 3063}
3064
313a3dc7
CO		 3065static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3066 struct kvm_lapic_state *s)
3067{
5a71785d 3068 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 3069 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 3070
3071 return 0;
3072}
3073
3074static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3075 struct kvm_lapic_state *s)
3076{
64eb0620 3077 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 3078 update_cr8_intercept(vcpu);
313a3dc7
CO		 3079
3080 return 0;
3081}
3082
f77bc6a4
ZX		 3083static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3084 struct kvm_interrupt *irq)
3085{
02cdb50f 3086 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3087 return -EINVAL;
3088 if (irqchip_in_kernel(vcpu->kvm))
3089 return -ENXIO;
f77bc6a4 3090
66fd3f7f 3091 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3092 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3093
f77bc6a4
ZX		 3094 return 0;
3095}
3096
c4abb7c9
JK		 3097static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3098{
c4abb7c9 3099 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3100
3101 return 0;
3102}
3103
f077825a
PB		 3104static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3105{
3106 return 0;
3107}
3108
b209749f
AK		 3109static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3110 struct kvm_tpr_access_ctl *tac)
3111{
3112 if (tac->flags)
3113 return -EINVAL;
3114 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3115 return 0;
3116}
3117
890ca9ae
HY		 3118static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3119 u64 mcg_cap)
3120{
3121 int r;
3122 unsigned bank_num = mcg_cap & 0xff, bank;
3123
3124 r = -EINVAL;
a9e38c3e 3125 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3126 goto out;
3127 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3128 goto out;
3129 r = 0;
3130 vcpu->arch.mcg_cap = mcg_cap;
3131 /* Init IA32_MCG_CTL to all 1s */
3132 if (mcg_cap & MCG_CTL_P)
3133 vcpu->arch.mcg_ctl = ~(u64)0;
3134 /* Init IA32_MCi_CTL to all 1s */
3135 for (bank = 0; bank < bank_num; bank++)
3136 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3137out:
3138 return r;
3139}
3140
3141static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3142 struct kvm_x86_mce *mce)
3143{
3144 u64 mcg_cap = vcpu->arch.mcg_cap;
3145 unsigned bank_num = mcg_cap & 0xff;
3146 u64 *banks = vcpu->arch.mce_banks;
3147
3148 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3149 return -EINVAL;
3150 /*
3151 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3152 * reporting is disabled
3153 */
3154 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3155 vcpu->arch.mcg_ctl != ~(u64)0)
3156 return 0;
3157 banks += 4 * mce->bank;
3158 /*
3159 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3160 * reporting is disabled for the bank
3161 */
3162 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3163 return 0;
3164 if (mce->status & MCI_STATUS_UC) {
3165 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3166 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3167 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3168 return 0;
3169 }
3170 if (banks[1] & MCI_STATUS_VAL)
3171 mce->status |= MCI_STATUS_OVER;
3172 banks[2] = mce->addr;
3173 banks[3] = mce->misc;
3174 vcpu->arch.mcg_status = mce->mcg_status;
3175 banks[1] = mce->status;
3176 kvm_queue_exception(vcpu, MC_VECTOR);
3177 } else if (!(banks[1] & MCI_STATUS_VAL)
3178 || !(banks[1] & MCI_STATUS_UC)) {
3179 if (banks[1] & MCI_STATUS_VAL)
3180 mce->status |= MCI_STATUS_OVER;
3181 banks[2] = mce->addr;
3182 banks[3] = mce->misc;
3183 banks[1] = mce->status;
3184 } else
3185 banks[1] |= MCI_STATUS_OVER;
3186 return 0;
3187}
3188
3cfc3092
JK		 3189static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3190 struct kvm_vcpu_events *events)
3191{
7460fb4a 3192 process_nmi(vcpu);
03b82a30
JK		 3193 events->exception.injected =
3194 vcpu->arch.exception.pending &&
3195 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3196 events->exception.nr = vcpu->arch.exception.nr;
3197 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3198 events->exception.pad = 0;
3cfc3092
JK		 3199 events->exception.error_code = vcpu->arch.exception.error_code;
3200
03b82a30
JK		 3201 events->interrupt.injected =
3202 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3203 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3204 events->interrupt.soft = 0;
37ccdcbe 3205 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3206
3207 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3208 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3209 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3210 events->nmi.pad = 0;
3cfc3092 3211
66450a21 3212 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3213
f077825a
PB		 3214 events->smi.smm = is_smm(vcpu);
3215 events->smi.pending = vcpu->arch.smi_pending;
3216 events->smi.smm_inside_nmi =
3217 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3218 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3219
dab4b911 3220 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3221 | KVM_VCPUEVENT_VALID_SHADOW
3222 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3223 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3224}
3225
3226static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3227 struct kvm_vcpu_events *events)
3228{
dab4b911 3229 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3230 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3231 | KVM_VCPUEVENT_VALID_SHADOW
3232 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3233 return -EINVAL;
3234
7460fb4a 3235 process_nmi(vcpu);
3cfc3092
JK		 3236 vcpu->arch.exception.pending = events->exception.injected;
3237 vcpu->arch.exception.nr = events->exception.nr;
3238 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3239 vcpu->arch.exception.error_code = events->exception.error_code;
3240
3241 vcpu->arch.interrupt.pending = events->interrupt.injected;
3242 vcpu->arch.interrupt.nr = events->interrupt.nr;
3243 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3244 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3245 kvm_x86_ops->set_interrupt_shadow(vcpu,
3246 events->interrupt.shadow);
3cfc3092
JK		 3247
3248 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3249 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3250 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3251 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3252
66450a21
JK		 3253 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3254 kvm_vcpu_has_lapic(vcpu))
3255 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3256
f077825a
PB		 3257 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3258 if (events->smi.smm)
3259 vcpu->arch.hflags |= HF_SMM_MASK;
3260 else
3261 vcpu->arch.hflags &= ~HF_SMM_MASK;
3262 vcpu->arch.smi_pending = events->smi.pending;
3263 if (events->smi.smm_inside_nmi)
3264 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3265 else
3266 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3267 if (kvm_vcpu_has_lapic(vcpu)) {
3268 if (events->smi.latched_init)
3269 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3270 else
3271 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3272 }
3273 }
3274
3842d135
AK		 3275 kvm_make_request(KVM_REQ_EVENT, vcpu);
3276
3cfc3092
JK		 3277 return 0;
3278}
3279
a1efbe77
JK		 3280static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3281 struct kvm_debugregs *dbgregs)
3282{
73aaf249
JK		 3283 unsigned long val;
3284
a1efbe77 3285 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3286 kvm_get_dr(vcpu, 6, &val);
73aaf249 3287 dbgregs->dr6 = val;
a1efbe77
JK		 3288 dbgregs->dr7 = vcpu->arch.dr7;
3289 dbgregs->flags = 0;
97e69aa6 3290 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3291}
3292
3293static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3294 struct kvm_debugregs *dbgregs)
3295{
3296 if (dbgregs->flags)
3297 return -EINVAL;
3298
a1efbe77 3299 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3300 kvm_update_dr0123(vcpu);
a1efbe77 3301 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3302 kvm_update_dr6(vcpu);
a1efbe77 3303 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3304 kvm_update_dr7(vcpu);
a1efbe77 3305
a1efbe77
JK		 3306 return 0;
3307}
3308
df1daba7
PB		 3309#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3310
3311static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3312{
3313 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3314 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3315 u64 valid;
3316
3317 /*
3318 * Copy legacy XSAVE area, to avoid complications with CPUID
3319 * leaves 0 and 1 in the loop below.
3320 */
3321 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3322
3323 /* Set XSTATE_BV */
3324 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3325
3326 /*
3327 * Copy each region from the possibly compacted offset to the
3328 * non-compacted offset.
3329 */
3330 valid = xstate_bv & ~XSTATE_FPSSE;
3331 while (valid) {
3332 u64 feature = valid & -valid;
3333 int index = fls64(feature) - 1;
3334 void *src = get_xsave_addr(xsave, feature);
3335
3336 if (src) {
3337 u32 size, offset, ecx, edx;
3338 cpuid_count(XSTATE_CPUID, index,
3339 &size, &offset, &ecx, &edx);
3340 memcpy(dest + offset, src, size);
3341 }
3342
3343 valid -= feature;
3344 }
3345}
3346
3347static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3348{
3349 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3350 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3351 u64 valid;
3352
3353 /*
3354 * Copy legacy XSAVE area, to avoid complications with CPUID
3355 * leaves 0 and 1 in the loop below.
3356 */
3357 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3358
3359 /* Set XSTATE_BV and possibly XCOMP_BV. */
3360 xsave->xsave_hdr.xstate_bv = xstate_bv;
3361 if (cpu_has_xsaves)
3362 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3363
3364 /*
3365 * Copy each region from the non-compacted offset to the
3366 * possibly compacted offset.
3367 */
3368 valid = xstate_bv & ~XSTATE_FPSSE;
3369 while (valid) {
3370 u64 feature = valid & -valid;
3371 int index = fls64(feature) - 1;
3372 void *dest = get_xsave_addr(xsave, feature);
3373
3374 if (dest) {
3375 u32 size, offset, ecx, edx;
3376 cpuid_count(XSTATE_CPUID, index,
3377 &size, &offset, &ecx, &edx);
3378 memcpy(dest, src + offset, size);
3379 } else
3380 WARN_ON_ONCE(1);
3381
3382 valid -= feature;
3383 }
3384}
3385
2d5b5a66
SY		 3386static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3387 struct kvm_xsave *guest_xsave)
3388{
4344ee98 3389 if (cpu_has_xsave) {
df1daba7
PB		 3390 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3391 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3392 } else {
2d5b5a66
SY		 3393 memcpy(guest_xsave->region,
3394 &vcpu->arch.guest_fpu.state->fxsave,
3395 sizeof(struct i387_fxsave_struct));
3396 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3397 XSTATE_FPSSE;
3398 }
3399}
3400
3401static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3402 struct kvm_xsave *guest_xsave)
3403{
3404 u64 xstate_bv =
3405 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3406
d7876f1b
PB		 3407 if (cpu_has_xsave) {
3408 /*
3409 * Here we allow setting states that are not present in
3410 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3411 * with old userspace.
3412 */
4ff41732 3413 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3414 return -EINVAL;
df1daba7 3415 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3416 } else {
2d5b5a66
SY		 3417 if (xstate_bv & ~XSTATE_FPSSE)
3418 return -EINVAL;
3419 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3420 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3421 }
3422 return 0;
3423}
3424
3425static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3426 struct kvm_xcrs *guest_xcrs)
3427{
3428 if (!cpu_has_xsave) {
3429 guest_xcrs->nr_xcrs = 0;
3430 return;
3431 }
3432
3433 guest_xcrs->nr_xcrs = 1;
3434 guest_xcrs->flags = 0;
3435 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3436 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3437}
3438
3439static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3440 struct kvm_xcrs *guest_xcrs)
3441{
3442 int i, r = 0;
3443
3444 if (!cpu_has_xsave)
3445 return -EINVAL;
3446
3447 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3448 return -EINVAL;
3449
3450 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3451 /* Only support XCR0 currently */
c67a04cb 3452 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3453 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3454 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3455 break;
3456 }
3457 if (r)
3458 r = -EINVAL;
3459 return r;
3460}
3461
1c0b28c2
EM		 3462/*
3463 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3464 * stopped by the hypervisor. This function will be called from the host only.
3465 * EINVAL is returned when the host attempts to set the flag for a guest that
3466 * does not support pv clocks.
3467 */
3468static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3469{
0b79459b 3470 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3471 return -EINVAL;
51d59c6b 3472 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3473 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3474 return 0;
3475}
3476
313a3dc7
CO		 3477long kvm_arch_vcpu_ioctl(struct file *filp,
3478 unsigned int ioctl, unsigned long arg)
3479{
3480 struct kvm_vcpu *vcpu = filp->private_data;
3481 void __user *argp = (void __user *)arg;
3482 int r;
d1ac91d8
AK		 3483 union {
3484 struct kvm_lapic_state *lapic;
3485 struct kvm_xsave *xsave;
3486 struct kvm_xcrs *xcrs;
3487 void *buffer;
3488 } u;
3489
3490 u.buffer = NULL;
313a3dc7
CO		 3491 switch (ioctl) {
3492 case KVM_GET_LAPIC: {
2204ae3c
MT		 3493 r = -EINVAL;
3494 if (!vcpu->arch.apic)
3495 goto out;
d1ac91d8 3496 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3497
b772ff36 3498 r = -ENOMEM;
d1ac91d8 3499 if (!u.lapic)
b772ff36 3500 goto out;
d1ac91d8 3501 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3502 if (r)
3503 goto out;
3504 r = -EFAULT;
d1ac91d8 3505 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3506 goto out;
3507 r = 0;
3508 break;
3509 }
3510 case KVM_SET_LAPIC: {
2204ae3c
MT		 3511 r = -EINVAL;
3512 if (!vcpu->arch.apic)
3513 goto out;
ff5c2c03 3514 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3515 if (IS_ERR(u.lapic))
3516 return PTR_ERR(u.lapic);
ff5c2c03 3517
d1ac91d8 3518 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3519 break;
3520 }
f77bc6a4
ZX		 3521 case KVM_INTERRUPT: {
3522 struct kvm_interrupt irq;
3523
3524 r = -EFAULT;
3525 if (copy_from_user(&irq, argp, sizeof irq))
3526 goto out;
3527 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3528 break;
3529 }
c4abb7c9
JK		 3530 case KVM_NMI: {
3531 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3532 break;
3533 }
f077825a
PB		 3534 case KVM_SMI: {
3535 r = kvm_vcpu_ioctl_smi(vcpu);
3536 break;
3537 }
313a3dc7
CO		 3538 case KVM_SET_CPUID: {
3539 struct kvm_cpuid __user *cpuid_arg = argp;
3540 struct kvm_cpuid cpuid;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3544 goto out;
3545 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3546 break;
3547 }
07716717
DK		 3548 case KVM_SET_CPUID2: {
3549 struct kvm_cpuid2 __user *cpuid_arg = argp;
3550 struct kvm_cpuid2 cpuid;
3551
3552 r = -EFAULT;
3553 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3554 goto out;
3555 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3556 cpuid_arg->entries);
07716717
DK		 3557 break;
3558 }
3559 case KVM_GET_CPUID2: {
3560 struct kvm_cpuid2 __user *cpuid_arg = argp;
3561 struct kvm_cpuid2 cpuid;
3562
3563 r = -EFAULT;
3564 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3565 goto out;
3566 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3567 cpuid_arg->entries);
07716717
DK		 3568 if (r)
3569 goto out;
3570 r = -EFAULT;
3571 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3572 goto out;
3573 r = 0;
3574 break;
3575 }
313a3dc7 3576 case KVM_GET_MSRS:
609e36d3 3577 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3578 break;
3579 case KVM_SET_MSRS:
3580 r = msr_io(vcpu, argp, do_set_msr, 0);
3581 break;
b209749f
AK		 3582 case KVM_TPR_ACCESS_REPORTING: {
3583 struct kvm_tpr_access_ctl tac;
3584
3585 r = -EFAULT;
3586 if (copy_from_user(&tac, argp, sizeof tac))
3587 goto out;
3588 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3589 if (r)
3590 goto out;
3591 r = -EFAULT;
3592 if (copy_to_user(argp, &tac, sizeof tac))
3593 goto out;
3594 r = 0;
3595 break;
3596 };
b93463aa
AK		 3597 case KVM_SET_VAPIC_ADDR: {
3598 struct kvm_vapic_addr va;
3599
3600 r = -EINVAL;
3601 if (!irqchip_in_kernel(vcpu->kvm))
3602 goto out;
3603 r = -EFAULT;
3604 if (copy_from_user(&va, argp, sizeof va))
3605 goto out;
fda4e2e8 3606 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3607 break;
3608 }
890ca9ae
HY		 3609 case KVM_X86_SETUP_MCE: {
3610 u64 mcg_cap;
3611
3612 r = -EFAULT;
3613 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3614 goto out;
3615 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3616 break;
3617 }
3618 case KVM_X86_SET_MCE: {
3619 struct kvm_x86_mce mce;
3620
3621 r = -EFAULT;
3622 if (copy_from_user(&mce, argp, sizeof mce))
3623 goto out;
3624 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3625 break;
3626 }
3cfc3092
JK		 3627 case KVM_GET_VCPU_EVENTS: {
3628 struct kvm_vcpu_events events;
3629
3630 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3631
3632 r = -EFAULT;
3633 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3634 break;
3635 r = 0;
3636 break;
3637 }
3638 case KVM_SET_VCPU_EVENTS: {
3639 struct kvm_vcpu_events events;
3640
3641 r = -EFAULT;
3642 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3643 break;
3644
3645 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3646 break;
3647 }
a1efbe77
JK		 3648 case KVM_GET_DEBUGREGS: {
3649 struct kvm_debugregs dbgregs;
3650
3651 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3652
3653 r = -EFAULT;
3654 if (copy_to_user(argp, &dbgregs,
3655 sizeof(struct kvm_debugregs)))
3656 break;
3657 r = 0;
3658 break;
3659 }
3660 case KVM_SET_DEBUGREGS: {
3661 struct kvm_debugregs dbgregs;
3662
3663 r = -EFAULT;
3664 if (copy_from_user(&dbgregs, argp,
3665 sizeof(struct kvm_debugregs)))
3666 break;
3667
3668 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3669 break;
3670 }
2d5b5a66 3671 case KVM_GET_XSAVE: {
d1ac91d8 3672 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3673 r = -ENOMEM;
d1ac91d8 3674 if (!u.xsave)
2d5b5a66
SY		 3675 break;
3676
d1ac91d8 3677 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3678
3679 r = -EFAULT;
d1ac91d8 3680 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3681 break;
3682 r = 0;
3683 break;
3684 }
3685 case KVM_SET_XSAVE: {
ff5c2c03 3686 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3687 if (IS_ERR(u.xsave))
3688 return PTR_ERR(u.xsave);
2d5b5a66 3689
d1ac91d8 3690 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3691 break;
3692 }
3693 case KVM_GET_XCRS: {
d1ac91d8 3694 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3695 r = -ENOMEM;
d1ac91d8 3696 if (!u.xcrs)
2d5b5a66
SY		 3697 break;
3698
d1ac91d8 3699 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3700
3701 r = -EFAULT;
d1ac91d8 3702 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3703 sizeof(struct kvm_xcrs)))
3704 break;
3705 r = 0;
3706 break;
3707 }
3708 case KVM_SET_XCRS: {
ff5c2c03 3709 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3710 if (IS_ERR(u.xcrs))
3711 return PTR_ERR(u.xcrs);
2d5b5a66 3712
d1ac91d8 3713 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3714 break;
3715 }
92a1f12d
JR		 3716 case KVM_SET_TSC_KHZ: {
3717 u32 user_tsc_khz;
3718
3719 r = -EINVAL;
92a1f12d
JR		 3720 user_tsc_khz = (u32)arg;
3721
3722 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3723 goto out;
3724
cc578287
ZA		 3725 if (user_tsc_khz == 0)
3726 user_tsc_khz = tsc_khz;
3727
3728 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3729
3730 r = 0;
3731 goto out;
3732 }
3733 case KVM_GET_TSC_KHZ: {
cc578287 3734 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3735 goto out;
3736 }
1c0b28c2
EM		 3737 case KVM_KVMCLOCK_CTRL: {
3738 r = kvm_set_guest_paused(vcpu);
3739 goto out;
3740 }
313a3dc7
CO		 3741 default:
3742 r = -EINVAL;
3743 }
3744out:
d1ac91d8 3745 kfree(u.buffer);
313a3dc7
CO		 3746 return r;
3747}
3748
5b1c1493
CO		 3749int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3750{
3751 return VM_FAULT_SIGBUS;
3752}
3753
1fe779f8
CO		 3754static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3755{
3756 int ret;
3757
3758 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3759 return -EINVAL;
1fe779f8
CO		 3760 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3761 return ret;
3762}
3763
b927a3ce
SY		 3764static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3765 u64 ident_addr)
3766{
3767 kvm->arch.ept_identity_map_addr = ident_addr;
3768 return 0;
3769}
3770
1fe779f8
CO		 3771static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3772 u32 kvm_nr_mmu_pages)
3773{
3774 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3775 return -EINVAL;
3776
79fac95e 3777 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3778
3779 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3780 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3781
79fac95e 3782 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3783 return 0;
3784}
3785
3786static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3787{
39de71ec 3788 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3789}
3790
1fe779f8
CO		 3791static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3792{
3793 int r;
3794
3795 r = 0;
3796 switch (chip->chip_id) {
3797 case KVM_IRQCHIP_PIC_MASTER:
3798 memcpy(&chip->chip.pic,
3799 &pic_irqchip(kvm)->pics[0],
3800 sizeof(struct kvm_pic_state));
3801 break;
3802 case KVM_IRQCHIP_PIC_SLAVE:
3803 memcpy(&chip->chip.pic,
3804 &pic_irqchip(kvm)->pics[1],
3805 sizeof(struct kvm_pic_state));
3806 break;
3807 case KVM_IRQCHIP_IOAPIC:
eba0226b 3808 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3809 break;
3810 default:
3811 r = -EINVAL;
3812 break;
3813 }
3814 return r;
3815}
3816
3817static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3818{
3819 int r;
3820
3821 r = 0;
3822 switch (chip->chip_id) {
3823 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3824 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3825 memcpy(&pic_irqchip(kvm)->pics[0],
3826 &chip->chip.pic,
3827 sizeof(struct kvm_pic_state));
f4f51050 3828 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3829 break;
3830 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3831 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3832 memcpy(&pic_irqchip(kvm)->pics[1],
3833 &chip->chip.pic,
3834 sizeof(struct kvm_pic_state));
f4f51050 3835 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3836 break;
3837 case KVM_IRQCHIP_IOAPIC:
eba0226b 3838 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3839 break;
3840 default:
3841 r = -EINVAL;
3842 break;
3843 }
3844 kvm_pic_update_irq(pic_irqchip(kvm));
3845 return r;
3846}
3847
e0f63cb9
SY		 3848static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3849{
3850 int r = 0;
3851
894a9c55 3852 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3853 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3854 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3855 return r;
3856}
3857
3858static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3859{
3860 int r = 0;
3861
894a9c55 3862 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3863 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3864 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3865 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3866 return r;
3867}
3868
3869static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3870{
3871 int r = 0;
3872
3873 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3874 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3875 sizeof(ps->channels));
3876 ps->flags = kvm->arch.vpit->pit_state.flags;
3877 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3878 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3879 return r;
3880}
3881
3882static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3883{
3884 int r = 0, start = 0;
3885 u32 prev_legacy, cur_legacy;
3886 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3887 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3888 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3889 if (!prev_legacy && cur_legacy)
3890 start = 1;
3891 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3892 sizeof(kvm->arch.vpit->pit_state.channels));
3893 kvm->arch.vpit->pit_state.flags = ps->flags;
3894 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3895 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3896 return r;
3897}
3898
52d939a0
MT		 3899static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3900 struct kvm_reinject_control *control)
3901{
3902 if (!kvm->arch.vpit)
3903 return -ENXIO;
894a9c55 3904 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3905 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3906 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3907 return 0;
3908}
3909
95d4c16c 3910/**
60c34612
TY		 3911 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3912 * @kvm: kvm instance
3913 * @log: slot id and address to which we copy the log
95d4c16c 3914 *
e108ff2f
PB		 3915 * Steps 1-4 below provide general overview of dirty page logging. See
3916 * kvm_get_dirty_log_protect() function description for additional details.
3917 *
3918 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3919 * always flush the TLB (step 4) even if previous step failed and the dirty
3920 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3921 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3922 * writes will be marked dirty for next log read.
95d4c16c 3923 *
60c34612
TY		 3924 * 1. Take a snapshot of the bit and clear it if needed.
3925 * 2. Write protect the corresponding page.
e108ff2f
PB		 3926 * 3. Copy the snapshot to the userspace.
3927 * 4. Flush TLB's if needed.
5bb064dc 3928 */
60c34612 3929int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3930{
60c34612 3931 bool is_dirty = false;
e108ff2f 3932 int r;
5bb064dc 3933
79fac95e 3934 mutex_lock(&kvm->slots_lock);
5bb064dc 3935
88178fd4
KH		 3936 /*
3937 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3938 */
3939 if (kvm_x86_ops->flush_log_dirty)
3940 kvm_x86_ops->flush_log_dirty(kvm);
3941
e108ff2f 3942 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3943
3944 /*
3945 * All the TLBs can be flushed out of mmu lock, see the comments in
3946 * kvm_mmu_slot_remove_write_access().
3947 */
e108ff2f 3948 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3949 if (is_dirty)
3950 kvm_flush_remote_tlbs(kvm);
3951
79fac95e 3952 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3953 return r;
3954}
3955
aa2fbe6d
YZ		 3956int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3957 bool line_status)
23d43cf9
CD		 3958{
3959 if (!irqchip_in_kernel(kvm))
3960 return -ENXIO;
3961
3962 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3963 irq_event->irq, irq_event->level,
3964 line_status);
23d43cf9
CD		 3965 return 0;
3966}
3967
90de4a18
NA		 3968static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3969 struct kvm_enable_cap *cap)
3970{
3971 int r;
3972
3973 if (cap->flags)
3974 return -EINVAL;
3975
3976 switch (cap->cap) {
3977 case KVM_CAP_DISABLE_QUIRKS:
3978 kvm->arch.disabled_quirks = cap->args[0];
3979 r = 0;
3980 break;
3981 default:
3982 r = -EINVAL;
3983 break;
3984 }
3985 return r;
3986}
3987
1fe779f8
CO		 3988long kvm_arch_vm_ioctl(struct file *filp,
3989 unsigned int ioctl, unsigned long arg)
3990{
3991 struct kvm *kvm = filp->private_data;
3992 void __user *argp = (void __user *)arg;
367e1319 3993 int r = -ENOTTY;
f0d66275
DH		 3994 /*
3995 * This union makes it completely explicit to gcc-3.x
3996 * that these two variables' stack usage should be
3997 * combined, not added together.
3998 */
3999 union {
4000 struct kvm_pit_state ps;
e9f42757 4001 struct kvm_pit_state2 ps2;
c5ff41ce 4002 struct kvm_pit_config pit_config;
f0d66275 4003 } u;
1fe779f8
CO		 4004
4005 switch (ioctl) {
4006 case KVM_SET_TSS_ADDR:
4007 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4008 break;
b927a3ce
SY		 4009 case KVM_SET_IDENTITY_MAP_ADDR: {
4010 u64 ident_addr;
4011
4012 r = -EFAULT;
4013 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4014 goto out;
4015 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4016 break;
4017 }
1fe779f8
CO		 4018 case KVM_SET_NR_MMU_PAGES:
4019 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4020 break;
4021 case KVM_GET_NR_MMU_PAGES:
4022 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4023 break;
3ddea128
MT		 4024 case KVM_CREATE_IRQCHIP: {
4025 struct kvm_pic *vpic;
4026
4027 mutex_lock(&kvm->lock);
4028 r = -EEXIST;
4029 if (kvm->arch.vpic)
4030 goto create_irqchip_unlock;
3e515705
AK		 4031 r = -EINVAL;
4032 if (atomic_read(&kvm->online_vcpus))
4033 goto create_irqchip_unlock;
1fe779f8 4034 r = -ENOMEM;
3ddea128
MT		 4035 vpic = kvm_create_pic(kvm);
4036 if (vpic) {
1fe779f8
CO		 4037 r = kvm_ioapic_init(kvm);
4038 if (r) {
175504cd 4039 mutex_lock(&kvm->slots_lock);
72bb2fcd 4040 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 4041 &vpic->dev_master);
4042 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
4043 &vpic->dev_slave);
4044 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
4045 &vpic->dev_eclr);
175504cd 4046 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 4047 kfree(vpic);
4048 goto create_irqchip_unlock;
1fe779f8
CO		 4049 }
4050 } else
3ddea128
MT		 4051 goto create_irqchip_unlock;
4052 smp_wmb();
4053 kvm->arch.vpic = vpic;
4054 smp_wmb();
399ec807
AK		 4055 r = kvm_setup_default_irq_routing(kvm);
4056 if (r) {
175504cd 4057 mutex_lock(&kvm->slots_lock);
3ddea128 4058 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 4059 kvm_ioapic_destroy(kvm);
4060 kvm_destroy_pic(kvm);
3ddea128 4061 mutex_unlock(&kvm->irq_lock);
175504cd 4062 mutex_unlock(&kvm->slots_lock);
399ec807 4063 }
3ddea128
MT		 4064 create_irqchip_unlock:
4065 mutex_unlock(&kvm->lock);
1fe779f8 4066 break;
3ddea128 4067 }
7837699f 4068 case KVM_CREATE_PIT:
c5ff41ce
JK		 4069 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4070 goto create_pit;
4071 case KVM_CREATE_PIT2:
4072 r = -EFAULT;
4073 if (copy_from_user(&u.pit_config, argp,
4074 sizeof(struct kvm_pit_config)))
4075 goto out;
4076 create_pit:
79fac95e 4077 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 4078 r = -EEXIST;
4079 if (kvm->arch.vpit)
4080 goto create_pit_unlock;
7837699f 4081 r = -ENOMEM;
c5ff41ce 4082 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4083 if (kvm->arch.vpit)
4084 r = 0;
269e05e4 4085 create_pit_unlock:
79fac95e 4086 mutex_unlock(&kvm->slots_lock);
7837699f 4087 break;
1fe779f8
CO		 4088 case KVM_GET_IRQCHIP: {
4089 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4090 struct kvm_irqchip *chip;
1fe779f8 4091
ff5c2c03
SL		 4092 chip = memdup_user(argp, sizeof(*chip));
4093 if (IS_ERR(chip)) {
4094 r = PTR_ERR(chip);
1fe779f8 4095 goto out;
ff5c2c03
SL		 4096 }
4097
1fe779f8
CO		 4098 r = -ENXIO;
4099 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4100 goto get_irqchip_out;
4101 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4102 if (r)
f0d66275 4103 goto get_irqchip_out;
1fe779f8 4104 r = -EFAULT;
f0d66275
DH		 4105 if (copy_to_user(argp, chip, sizeof *chip))
4106 goto get_irqchip_out;
1fe779f8 4107 r = 0;
f0d66275
DH		 4108 get_irqchip_out:
4109 kfree(chip);
1fe779f8
CO		 4110 break;
4111 }
4112 case KVM_SET_IRQCHIP: {
4113 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4114 struct kvm_irqchip *chip;
1fe779f8 4115
ff5c2c03
SL		 4116 chip = memdup_user(argp, sizeof(*chip));
4117 if (IS_ERR(chip)) {
4118 r = PTR_ERR(chip);
1fe779f8 4119 goto out;
ff5c2c03
SL		 4120 }
4121
1fe779f8
CO		 4122 r = -ENXIO;
4123 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4124 goto set_irqchip_out;
4125 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4126 if (r)
f0d66275 4127 goto set_irqchip_out;
1fe779f8 4128 r = 0;
f0d66275
DH		 4129 set_irqchip_out:
4130 kfree(chip);
1fe779f8
CO		 4131 break;
4132 }
e0f63cb9 4133 case KVM_GET_PIT: {
e0f63cb9 4134 r = -EFAULT;
f0d66275 4135 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4136 goto out;
4137 r = -ENXIO;
4138 if (!kvm->arch.vpit)
4139 goto out;
f0d66275 4140 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4141 if (r)
4142 goto out;
4143 r = -EFAULT;
f0d66275 4144 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4145 goto out;
4146 r = 0;
4147 break;
4148 }
4149 case KVM_SET_PIT: {
e0f63cb9 4150 r = -EFAULT;
f0d66275 4151 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4152 goto out;
4153 r = -ENXIO;
4154 if (!kvm->arch.vpit)
4155 goto out;
f0d66275 4156 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4157 break;
4158 }
e9f42757
BK		 4159 case KVM_GET_PIT2: {
4160 r = -ENXIO;
4161 if (!kvm->arch.vpit)
4162 goto out;
4163 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4164 if (r)
4165 goto out;
4166 r = -EFAULT;
4167 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4168 goto out;
4169 r = 0;
4170 break;
4171 }
4172 case KVM_SET_PIT2: {
4173 r = -EFAULT;
4174 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4175 goto out;
4176 r = -ENXIO;
4177 if (!kvm->arch.vpit)
4178 goto out;
4179 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4180 break;
4181 }
52d939a0
MT		 4182 case KVM_REINJECT_CONTROL: {
4183 struct kvm_reinject_control control;
4184 r = -EFAULT;
4185 if (copy_from_user(&control, argp, sizeof(control)))
4186 goto out;
4187 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4188 break;
4189 }
ffde22ac
ES		 4190 case KVM_XEN_HVM_CONFIG: {
4191 r = -EFAULT;
4192 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4193 sizeof(struct kvm_xen_hvm_config)))
4194 goto out;
4195 r = -EINVAL;
4196 if (kvm->arch.xen_hvm_config.flags)
4197 goto out;
4198 r = 0;
4199 break;
4200 }
afbcf7ab 4201 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4202 struct kvm_clock_data user_ns;
4203 u64 now_ns;
4204 s64 delta;
4205
4206 r = -EFAULT;
4207 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4208 goto out;
4209
4210 r = -EINVAL;
4211 if (user_ns.flags)
4212 goto out;
4213
4214 r = 0;
395c6b0a 4215 local_irq_disable();
759379dd 4216 now_ns = get_kernel_ns();
afbcf7ab 4217 delta = user_ns.clock - now_ns;
395c6b0a 4218 local_irq_enable();
afbcf7ab 4219 kvm->arch.kvmclock_offset = delta;
2e762ff7 4220 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4221 break;
4222 }
4223 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4224 struct kvm_clock_data user_ns;
4225 u64 now_ns;
4226
395c6b0a 4227 local_irq_disable();
759379dd 4228 now_ns = get_kernel_ns();
afbcf7ab 4229 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4230 local_irq_enable();
afbcf7ab 4231 user_ns.flags = 0;
97e69aa6 4232 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4233
4234 r = -EFAULT;
4235 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4236 goto out;
4237 r = 0;
4238 break;
4239 }
90de4a18
NA		 4240 case KVM_ENABLE_CAP: {
4241 struct kvm_enable_cap cap;
afbcf7ab 4242
90de4a18
NA		 4243 r = -EFAULT;
4244 if (copy_from_user(&cap, argp, sizeof(cap)))
4245 goto out;
4246 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4247 break;
4248 }
1fe779f8 4249 default:
c274e03a 4250 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4251 }
4252out:
4253 return r;
4254}
4255
a16b043c 4256static void kvm_init_msr_list(void)
043405e1
CO		 4257{
4258 u32 dummy[2];
4259 unsigned i, j;
4260
62ef68bb 4261 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4262 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4263 continue;
93c4adc7
PB		 4264
4265 /*
4266 * Even MSRs that are valid in the host may not be exposed
4267 * to the guests in some cases. We could work around this
4268 * in VMX with the generic MSR save/load machinery, but it
4269 * is not really worthwhile since it will really only
4270 * happen with nested virtualization.
4271 */
4272 switch (msrs_to_save[i]) {
4273 case MSR_IA32_BNDCFGS:
4274 if (!kvm_x86_ops->mpx_supported())
4275 continue;
4276 break;
4277 default:
4278 break;
4279 }
4280
043405e1
CO		 4281 if (j < i)
4282 msrs_to_save[j] = msrs_to_save[i];
4283 j++;
4284 }
4285 num_msrs_to_save = j;
62ef68bb
PB		 4286
4287 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4288 switch (emulated_msrs[i]) {
4289 default:
4290 break;
4291 }
4292
4293 if (j < i)
4294 emulated_msrs[j] = emulated_msrs[i];
4295 j++;
4296 }
4297 num_emulated_msrs = j;
043405e1
CO		 4298}
4299
bda9020e
MT		 4300static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4301 const void *v)
bbd9b64e 4302{
70252a10
AK		 4303 int handled = 0;
4304 int n;
4305
4306 do {
4307 n = min(len, 8);
4308 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4309 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4310 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4311 break;
4312 handled += n;
4313 addr += n;
4314 len -= n;
4315 v += n;
4316 } while (len);
bbd9b64e 4317
70252a10 4318 return handled;
bbd9b64e
CO		 4319}
4320
bda9020e 4321static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4322{
70252a10
AK		 4323 int handled = 0;
4324 int n;
4325
4326 do {
4327 n = min(len, 8);
4328 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4329 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4330 addr, n, v))
4331 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4332 break;
4333 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4334 handled += n;
4335 addr += n;
4336 len -= n;
4337 v += n;
4338 } while (len);
bbd9b64e 4339
70252a10 4340 return handled;
bbd9b64e
CO		 4341}
4342
2dafc6c2
GN		 4343static void kvm_set_segment(struct kvm_vcpu *vcpu,
4344 struct kvm_segment *var, int seg)
4345{
4346 kvm_x86_ops->set_segment(vcpu, var, seg);
4347}
4348
4349void kvm_get_segment(struct kvm_vcpu *vcpu,
4350 struct kvm_segment *var, int seg)
4351{
4352 kvm_x86_ops->get_segment(vcpu, var, seg);
4353}
4354
54987b7a
PB		 4355gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4356 struct x86_exception *exception)
02f59dc9
JR		 4357{
4358 gpa_t t_gpa;
02f59dc9
JR		 4359
4360 BUG_ON(!mmu_is_nested(vcpu));
4361
4362 /* NPT walks are always user-walks */
4363 access |= PFERR_USER_MASK;
54987b7a 4364 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4365
4366 return t_gpa;
4367}
4368
ab9ae313
AK		 4369gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4370 struct x86_exception *exception)
1871c602
GN		 4371{
4372 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4373 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4374}
4375
ab9ae313
AK		 4376 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4377 struct x86_exception *exception)
1871c602
GN		 4378{
4379 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4380 access |= PFERR_FETCH_MASK;
ab9ae313 4381 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4382}
4383
ab9ae313
AK		 4384gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4385 struct x86_exception *exception)
1871c602
GN		 4386{
4387 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4388 access |= PFERR_WRITE_MASK;
ab9ae313 4389 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4390}
4391
4392/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4393gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4394 struct x86_exception *exception)
1871c602 4395{
ab9ae313 4396 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4397}
4398
4399static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4400 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4401 struct x86_exception *exception)
bbd9b64e
CO		 4402{
4403 void *data = val;
10589a46 4404 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4405
4406 while (bytes) {
14dfe855 4407 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4408 exception);
bbd9b64e 4409 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4410 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4411 int ret;
4412
bcc55cba 4413 if (gpa == UNMAPPED_GVA)
ab9ae313 4414 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4415 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4416 offset, toread);
10589a46 4417 if (ret < 0) {
c3cd7ffa 4418 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4419 goto out;
4420 }
bbd9b64e 4421
77c2002e
IE		 4422 bytes -= toread;
4423 data += toread;
4424 addr += toread;
bbd9b64e 4425 }
10589a46 4426out:
10589a46 4427 return r;
bbd9b64e 4428}
77c2002e 4429
1871c602 4430/* used for instruction fetching */
0f65dd70
AK		 4431static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4432 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4433 struct x86_exception *exception)
1871c602 4434{
0f65dd70 4435 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4436 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4437 unsigned offset;
4438 int ret;
0f65dd70 4439
44583cba
PB		 4440 /* Inline kvm_read_guest_virt_helper for speed. */
4441 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4442 exception);
4443 if (unlikely(gpa == UNMAPPED_GVA))
4444 return X86EMUL_PROPAGATE_FAULT;
4445
4446 offset = addr & (PAGE_SIZE-1);
4447 if (WARN_ON(offset + bytes > PAGE_SIZE))
4448 bytes = (unsigned)PAGE_SIZE - offset;
4449 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4450 offset, bytes);
4451 if (unlikely(ret < 0))
4452 return X86EMUL_IO_NEEDED;
4453
4454 return X86EMUL_CONTINUE;
1871c602
GN		 4455}
4456
064aea77 4457int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4458 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4459 struct x86_exception *exception)
1871c602 4460{
0f65dd70 4461 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4462 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4463
1871c602 4464 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4465 exception);
1871c602 4466}
064aea77 4467EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4468
0f65dd70
AK		 4469static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4470 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4471 struct x86_exception *exception)
1871c602 4472{
0f65dd70 4473 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4474 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4475}
4476
6a4d7550 4477int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4478 gva_t addr, void *val,
2dafc6c2 4479 unsigned int bytes,
bcc55cba 4480 struct x86_exception *exception)
77c2002e 4481{
0f65dd70 4482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4483 void *data = val;
4484 int r = X86EMUL_CONTINUE;
4485
4486 while (bytes) {
14dfe855
JR		 4487 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4488 PFERR_WRITE_MASK,
ab9ae313 4489 exception);
77c2002e
IE		 4490 unsigned offset = addr & (PAGE_SIZE-1);
4491 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4492 int ret;
4493
bcc55cba 4494 if (gpa == UNMAPPED_GVA)
ab9ae313 4495 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4496 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4497 if (ret < 0) {
c3cd7ffa 4498 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4499 goto out;
4500 }
4501
4502 bytes -= towrite;
4503 data += towrite;
4504 addr += towrite;
4505 }
4506out:
4507 return r;
4508}
6a4d7550 4509EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4510
af7cc7d1
XG		 4511static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4512 gpa_t *gpa, struct x86_exception *exception,
4513 bool write)
4514{
97d64b78
AK		 4515 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4516 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4517
97d64b78 4518 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4519 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4520 vcpu->arch.access, access)) {
bebb106a
XG		 4521 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4522 (gva & (PAGE_SIZE - 1));
4f022648 4523 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4524 return 1;
4525 }
4526
af7cc7d1
XG		 4527 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4528
4529 if (*gpa == UNMAPPED_GVA)
4530 return -1;
4531
4532 /* For APIC access vmexit */
4533 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4534 return 1;
4535
4f022648
XG		 4536 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4537 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4538 return 1;
4f022648 4539 }
bebb106a 4540
af7cc7d1
XG		 4541 return 0;
4542}
4543
3200f405 4544int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4545 const void *val, int bytes)
bbd9b64e
CO		 4546{
4547 int ret;
4548
4549 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4550 if (ret < 0)
bbd9b64e 4551 return 0;
f57f2ef5 4552 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4553 return 1;
4554}
4555
77d197b2
XG		 4556struct read_write_emulator_ops {
4557 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4558 int bytes);
4559 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4560 void *val, int bytes);
4561 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4562 int bytes, void *val);
4563 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4564 void *val, int bytes);
4565 bool write;
4566};
4567
4568static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4569{
4570 if (vcpu->mmio_read_completed) {
77d197b2 4571 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4572 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4573 vcpu->mmio_read_completed = 0;
4574 return 1;
4575 }
4576
4577 return 0;
4578}
4579
4580static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4581 void *val, int bytes)
4582{
4583 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4584}
4585
4586static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4587 void *val, int bytes)
4588{
4589 return emulator_write_phys(vcpu, gpa, val, bytes);
4590}
4591
4592static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4593{
4594 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4595 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4596}
4597
4598static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4599 void *val, int bytes)
4600{
4601 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4602 return X86EMUL_IO_NEEDED;
4603}
4604
4605static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4606 void *val, int bytes)
4607{
f78146b0
AK		 4608 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4609
87da7e66 4610 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4611 return X86EMUL_CONTINUE;
4612}
4613
0fbe9b0b 4614static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4615 .read_write_prepare = read_prepare,
4616 .read_write_emulate = read_emulate,
4617 .read_write_mmio = vcpu_mmio_read,
4618 .read_write_exit_mmio = read_exit_mmio,
4619};
4620
0fbe9b0b 4621static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4622 .read_write_emulate = write_emulate,
4623 .read_write_mmio = write_mmio,
4624 .read_write_exit_mmio = write_exit_mmio,
4625 .write = true,
4626};
4627
22388a3c
XG		 4628static int emulator_read_write_onepage(unsigned long addr, void *val,
4629 unsigned int bytes,
4630 struct x86_exception *exception,
4631 struct kvm_vcpu *vcpu,
0fbe9b0b 4632 const struct read_write_emulator_ops *ops)
bbd9b64e 4633{
af7cc7d1
XG		 4634 gpa_t gpa;
4635 int handled, ret;
22388a3c 4636 bool write = ops->write;
f78146b0 4637 struct kvm_mmio_fragment *frag;
10589a46 4638
22388a3c 4639 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4640
af7cc7d1 4641 if (ret < 0)
bbd9b64e 4642 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4643
4644 /* For APIC access vmexit */
af7cc7d1 4645 if (ret)
bbd9b64e
CO		 4646 goto mmio;
4647
22388a3c 4648 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4649 return X86EMUL_CONTINUE;
4650
4651mmio:
4652 /*
4653 * Is this MMIO handled locally?
4654 */
22388a3c 4655 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4656 if (handled == bytes)
bbd9b64e 4657 return X86EMUL_CONTINUE;
bbd9b64e 4658
70252a10
AK		 4659 gpa += handled;
4660 bytes -= handled;
4661 val += handled;
4662
87da7e66
XG		 4663 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4664 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4665 frag->gpa = gpa;
4666 frag->data = val;
4667 frag->len = bytes;
f78146b0 4668 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4669}
4670
52eb5a6d
XL		 4671static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4672 unsigned long addr,
22388a3c
XG		 4673 void *val, unsigned int bytes,
4674 struct x86_exception *exception,
0fbe9b0b 4675 const struct read_write_emulator_ops *ops)
bbd9b64e 4676{
0f65dd70 4677 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4678 gpa_t gpa;
4679 int rc;
4680
4681 if (ops->read_write_prepare &&
4682 ops->read_write_prepare(vcpu, val, bytes))
4683 return X86EMUL_CONTINUE;
4684
4685 vcpu->mmio_nr_fragments = 0;
0f65dd70 4686
bbd9b64e
CO		 4687 /* Crossing a page boundary? */
4688 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4689 int now;
bbd9b64e
CO		 4690
4691 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4692 rc = emulator_read_write_onepage(addr, val, now, exception,
4693 vcpu, ops);
4694
bbd9b64e
CO		 4695 if (rc != X86EMUL_CONTINUE)
4696 return rc;
4697 addr += now;
bac15531
NA		 4698 if (ctxt->mode != X86EMUL_MODE_PROT64)
4699 addr = (u32)addr;
bbd9b64e
CO		 4700 val += now;
4701 bytes -= now;
4702 }
22388a3c 4703
f78146b0
AK		 4704 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4705 vcpu, ops);
4706 if (rc != X86EMUL_CONTINUE)
4707 return rc;
4708
4709 if (!vcpu->mmio_nr_fragments)
4710 return rc;
4711
4712 gpa = vcpu->mmio_fragments[0].gpa;
4713
4714 vcpu->mmio_needed = 1;
4715 vcpu->mmio_cur_fragment = 0;
4716
87da7e66 4717 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4718 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4719 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4720 vcpu->run->mmio.phys_addr = gpa;
4721
4722 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4723}
4724
4725static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4726 unsigned long addr,
4727 void *val,
4728 unsigned int bytes,
4729 struct x86_exception *exception)
4730{
4731 return emulator_read_write(ctxt, addr, val, bytes,
4732 exception, &read_emultor);
4733}
4734
52eb5a6d 4735static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4736 unsigned long addr,
4737 const void *val,
4738 unsigned int bytes,
4739 struct x86_exception *exception)
4740{
4741 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4742 exception, &write_emultor);
bbd9b64e 4743}
bbd9b64e 4744
daea3e73
AK		 4745#define CMPXCHG_TYPE(t, ptr, old, new) \
4746 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4747
4748#ifdef CONFIG_X86_64
4749# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4750#else
4751# define CMPXCHG64(ptr, old, new) \
9749a6c0 4752 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4753#endif
4754
0f65dd70
AK		 4755static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4756 unsigned long addr,
bbd9b64e
CO		 4757 const void *old,
4758 const void *new,
4759 unsigned int bytes,
0f65dd70 4760 struct x86_exception *exception)
bbd9b64e 4761{
0f65dd70 4762 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4763 gpa_t gpa;
4764 struct page *page;
4765 char *kaddr;
4766 bool exchanged;
2bacc55c 4767
daea3e73
AK		 4768 /* guests cmpxchg8b have to be emulated atomically */
4769 if (bytes > 8 || (bytes & (bytes - 1)))
4770 goto emul_write;
10589a46 4771
daea3e73 4772 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4773
daea3e73
AK		 4774 if (gpa == UNMAPPED_GVA ||
4775 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4776 goto emul_write;
2bacc55c 4777
daea3e73
AK		 4778 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4779 goto emul_write;
72dc67a6 4780
daea3e73 4781 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4782 if (is_error_page(page))
c19b8bd6 4783 goto emul_write;
72dc67a6 4784
8fd75e12 4785 kaddr = kmap_atomic(page);
daea3e73
AK		 4786 kaddr += offset_in_page(gpa);
4787 switch (bytes) {
4788 case 1:
4789 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4790 break;
4791 case 2:
4792 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4793 break;
4794 case 4:
4795 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4796 break;
4797 case 8:
4798 exchanged = CMPXCHG64(kaddr, old, new);
4799 break;
4800 default:
4801 BUG();
2bacc55c 4802 }
8fd75e12 4803 kunmap_atomic(kaddr);
daea3e73
AK		 4804 kvm_release_page_dirty(page);
4805
4806 if (!exchanged)
4807 return X86EMUL_CMPXCHG_FAILED;
4808
d3714010 4809 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4810 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4811
4812 return X86EMUL_CONTINUE;
4a5f48f6 4813
3200f405 4814emul_write:
daea3e73 4815 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4816
0f65dd70 4817 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4818}
4819
cf8f70bf
GN		 4820static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4821{
4822 /* TODO: String I/O for in kernel device */
4823 int r;
4824
4825 if (vcpu->arch.pio.in)
e32edf4f 4826 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4827 vcpu->arch.pio.size, pd);
4828 else
e32edf4f 4829 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4830 vcpu->arch.pio.port, vcpu->arch.pio.size,
4831 pd);
4832 return r;
4833}
4834
6f6fbe98
XG		 4835static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4836 unsigned short port, void *val,
4837 unsigned int count, bool in)
cf8f70bf 4838{
cf8f70bf 4839 vcpu->arch.pio.port = port;
6f6fbe98 4840 vcpu->arch.pio.in = in;
7972995b 4841 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4842 vcpu->arch.pio.size = size;
4843
4844 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4845 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4846 return 1;
4847 }
4848
4849 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4850 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4851 vcpu->run->io.size = size;
4852 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4853 vcpu->run->io.count = count;
4854 vcpu->run->io.port = port;
4855
4856 return 0;
4857}
4858
6f6fbe98
XG		 4859static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4860 int size, unsigned short port, void *val,
4861 unsigned int count)
cf8f70bf 4862{
ca1d4a9e 4863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4864 int ret;
ca1d4a9e 4865
6f6fbe98
XG		 4866 if (vcpu->arch.pio.count)
4867 goto data_avail;
cf8f70bf 4868
6f6fbe98
XG		 4869 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4870 if (ret) {
4871data_avail:
4872 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4873 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4874 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4875 return 1;
4876 }
4877
cf8f70bf
GN		 4878 return 0;
4879}
4880
6f6fbe98
XG		 4881static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4882 int size, unsigned short port,
4883 const void *val, unsigned int count)
4884{
4885 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4886
4887 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4888 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4889 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4890}
4891
bbd9b64e
CO		 4892static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4893{
4894 return kvm_x86_ops->get_segment_base(vcpu, seg);
4895}
4896
3cb16fe7 4897static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4898{
3cb16fe7 4899 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4900}
4901
5cb56059 4902int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4903{
4904 if (!need_emulate_wbinvd(vcpu))
4905 return X86EMUL_CONTINUE;
4906
4907 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4908 int cpu = get_cpu();
4909
4910 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4911 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4912 wbinvd_ipi, NULL, 1);
2eec7343 4913 put_cpu();
f5f48ee1 4914 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4915 } else
4916 wbinvd();
f5f48ee1
SY		 4917 return X86EMUL_CONTINUE;
4918}
5cb56059
JS		 4919
4920int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4921{
4922 kvm_x86_ops->skip_emulated_instruction(vcpu);
4923 return kvm_emulate_wbinvd_noskip(vcpu);
4924}
f5f48ee1
SY		 4925EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4926
5cb56059
JS		 4927
4928
bcaf5cc5
AK		 4929static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4930{
5cb56059 4931 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4932}
4933
52eb5a6d
XL		 4934static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4935 unsigned long *dest)
bbd9b64e 4936{
16f8a6f9 4937 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4938}
4939
52eb5a6d
XL		 4940static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4941 unsigned long value)
bbd9b64e 4942{
338dbc97 4943
717746e3 4944 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4945}
4946
52a46617 4947static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4948{
52a46617 4949 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4950}
4951
717746e3 4952static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4953{
717746e3 4954 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4955 unsigned long value;
4956
4957 switch (cr) {
4958 case 0:
4959 value = kvm_read_cr0(vcpu);
4960 break;
4961 case 2:
4962 value = vcpu->arch.cr2;
4963 break;
4964 case 3:
9f8fe504 4965 value = kvm_read_cr3(vcpu);
52a46617
GN		 4966 break;
4967 case 4:
4968 value = kvm_read_cr4(vcpu);
4969 break;
4970 case 8:
4971 value = kvm_get_cr8(vcpu);
4972 break;
4973 default:
a737f256 4974 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4975 return 0;
4976 }
4977
4978 return value;
4979}
4980
717746e3 4981static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4982{
717746e3 4983 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4984 int res = 0;
4985
52a46617
GN		 4986 switch (cr) {
4987 case 0:
49a9b07e 4988 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4989 break;
4990 case 2:
4991 vcpu->arch.cr2 = val;
4992 break;
4993 case 3:
2390218b 4994 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4995 break;
4996 case 4:
a83b29c6 4997 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4998 break;
4999 case 8:
eea1cff9 5000 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5001 break;
5002 default:
a737f256 5003 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5004 res = -1;
52a46617 5005 }
0f12244f
GN		 5006
5007 return res;
52a46617
GN		 5008}
5009
717746e3 5010static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5011{
717746e3 5012 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5013}
5014
4bff1e86 5015static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5016{
4bff1e86 5017 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5018}
5019
4bff1e86 5020static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5021{
4bff1e86 5022 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5023}
5024
1ac9d0cf
AK		 5025static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5026{
5027 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5028}
5029
5030static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5031{
5032 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5033}
5034
4bff1e86
AK		 5035static unsigned long emulator_get_cached_segment_base(
5036 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5037{
4bff1e86 5038 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5039}
5040
1aa36616
AK		 5041static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5042 struct desc_struct *desc, u32 *base3,
5043 int seg)
2dafc6c2
GN		 5044{
5045 struct kvm_segment var;
5046
4bff1e86 5047 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5048 *selector = var.selector;
2dafc6c2 5049
378a8b09
GN		 5050 if (var.unusable) {
5051 memset(desc, 0, sizeof(*desc));
2dafc6c2 5052 return false;
378a8b09 5053 }
2dafc6c2
GN		 5054
5055 if (var.g)
5056 var.limit >>= 12;
5057 set_desc_limit(desc, var.limit);
5058 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5059#ifdef CONFIG_X86_64
5060 if (base3)
5061 *base3 = var.base >> 32;
5062#endif
2dafc6c2
GN		 5063 desc->type = var.type;
5064 desc->s = var.s;
5065 desc->dpl = var.dpl;
5066 desc->p = var.present;
5067 desc->avl = var.avl;
5068 desc->l = var.l;
5069 desc->d = var.db;
5070 desc->g = var.g;
5071
5072 return true;
5073}
5074
1aa36616
AK		 5075static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5076 struct desc_struct *desc, u32 base3,
5077 int seg)
2dafc6c2 5078{
4bff1e86 5079 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5080 struct kvm_segment var;
5081
1aa36616 5082 var.selector = selector;
2dafc6c2 5083 var.base = get_desc_base(desc);
5601d05b
GN		 5084#ifdef CONFIG_X86_64
5085 var.base |= ((u64)base3) << 32;
5086#endif
2dafc6c2
GN		 5087 var.limit = get_desc_limit(desc);
5088 if (desc->g)
5089 var.limit = (var.limit << 12) | 0xfff;
5090 var.type = desc->type;
2dafc6c2
GN		 5091 var.dpl = desc->dpl;
5092 var.db = desc->d;
5093 var.s = desc->s;
5094 var.l = desc->l;
5095 var.g = desc->g;
5096 var.avl = desc->avl;
5097 var.present = desc->p;
5098 var.unusable = !var.present;
5099 var.padding = 0;
5100
5101 kvm_set_segment(vcpu, &var, seg);
5102 return;
5103}
5104
717746e3
AK		 5105static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5106 u32 msr_index, u64 *pdata)
5107{
609e36d3
PB		 5108 struct msr_data msr;
5109 int r;
5110
5111 msr.index = msr_index;
5112 msr.host_initiated = false;
5113 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5114 if (r)
5115 return r;
5116
5117 *pdata = msr.data;
5118 return 0;
717746e3
AK		 5119}
5120
5121static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5122 u32 msr_index, u64 data)
5123{
8fe8ab46
WA		 5124 struct msr_data msr;
5125
5126 msr.data = data;
5127 msr.index = msr_index;
5128 msr.host_initiated = false;
5129 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5130}
5131
67f4d428
NA		 5132static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5133 u32 pmc)
5134{
5135 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
5136}
5137
222d21aa
AK		 5138static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5139 u32 pmc, u64 *pdata)
5140{
5141 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
5142}
5143
6c3287f7
AK		 5144static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5145{
5146 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5147}
5148
5037f6f3
AK		 5149static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5150{
5151 preempt_disable();
5197b808 5152 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5153 /*
5154 * CR0.TS may reference the host fpu state, not the guest fpu state,
5155 * so it may be clear at this point.
5156 */
5157 clts();
5158}
5159
5160static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5161{
5162 preempt_enable();
5163}
5164
2953538e 5165static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5166 struct x86_instruction_info *info,
c4f035c6
AK		 5167 enum x86_intercept_stage stage)
5168{
2953538e 5169 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5170}
5171
0017f93a 5172static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5173 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5174{
0017f93a 5175 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5176}
5177
dd856efa
AK		 5178static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5179{
5180 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5181}
5182
5183static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5184{
5185 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5186}
5187
801806d9
NA		 5188static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5189{
5190 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5191}
5192
0225fb50 5193static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5194 .read_gpr = emulator_read_gpr,
5195 .write_gpr = emulator_write_gpr,
1871c602 5196 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5197 .write_std = kvm_write_guest_virt_system,
1871c602 5198 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5199 .read_emulated = emulator_read_emulated,
5200 .write_emulated = emulator_write_emulated,
5201 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5202 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5203 .pio_in_emulated = emulator_pio_in_emulated,
5204 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5205 .get_segment = emulator_get_segment,
5206 .set_segment = emulator_set_segment,
5951c442 5207 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5208 .get_gdt = emulator_get_gdt,
160ce1f1 5209 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5210 .set_gdt = emulator_set_gdt,
5211 .set_idt = emulator_set_idt,
52a46617
GN		 5212 .get_cr = emulator_get_cr,
5213 .set_cr = emulator_set_cr,
9c537244 5214 .cpl = emulator_get_cpl,
35aa5375
GN		 5215 .get_dr = emulator_get_dr,
5216 .set_dr = emulator_set_dr,
717746e3
AK		 5217 .set_msr = emulator_set_msr,
5218 .get_msr = emulator_get_msr,
67f4d428 5219 .check_pmc = emulator_check_pmc,
222d21aa 5220 .read_pmc = emulator_read_pmc,
6c3287f7 5221 .halt = emulator_halt,
bcaf5cc5 5222 .wbinvd = emulator_wbinvd,
d6aa1000 5223 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5224 .get_fpu = emulator_get_fpu,
5225 .put_fpu = emulator_put_fpu,
c4f035c6 5226 .intercept = emulator_intercept,
bdb42f5a 5227 .get_cpuid = emulator_get_cpuid,
801806d9 5228 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5229};
5230
95cb2295
GN		 5231static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5232{
37ccdcbe 5233 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5234 /*
5235 * an sti; sti; sequence only disable interrupts for the first
5236 * instruction. So, if the last instruction, be it emulated or
5237 * not, left the system with the INT_STI flag enabled, it
5238 * means that the last instruction is an sti. We should not
5239 * leave the flag on in this case. The same goes for mov ss
5240 */
37ccdcbe
PB		 5241 if (int_shadow & mask)
5242 mask = 0;
6addfc42 5243 if (unlikely(int_shadow || mask)) {
95cb2295 5244 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5245 if (!mask)
5246 kvm_make_request(KVM_REQ_EVENT, vcpu);
5247 }
95cb2295
GN		 5248}
5249
ef54bcfe 5250static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5251{
5252 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5253 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5254 return kvm_propagate_fault(vcpu, &ctxt->exception);
5255
5256 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5257 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5258 ctxt->exception.error_code);
54b8486f 5259 else
da9cb575 5260 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5261 return false;
54b8486f
GN		 5262}
5263
8ec4722d
MG		 5264static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5265{
adf52235 5266 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5267 int cs_db, cs_l;
5268
8ec4722d
MG		 5269 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5270
adf52235
TY		 5271 ctxt->eflags = kvm_get_rflags(vcpu);
5272 ctxt->eip = kvm_rip_read(vcpu);
5273 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5274 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5275 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5276 cs_db ? X86EMUL_MODE_PROT32 :
5277 X86EMUL_MODE_PROT16;
a584539b
PB		 5278 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5279 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5280
dd856efa 5281 init_decode_cache(ctxt);
7ae441ea 5282 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5283}
5284
71f9833b 5285int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5286{
9d74191a 5287 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5288 int ret;
5289
5290 init_emulate_ctxt(vcpu);
5291
9dac77fa
AK		 5292 ctxt->op_bytes = 2;
5293 ctxt->ad_bytes = 2;
5294 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5295 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5296
5297 if (ret != X86EMUL_CONTINUE)
5298 return EMULATE_FAIL;
5299
9dac77fa 5300 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5301 kvm_rip_write(vcpu, ctxt->eip);
5302 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5303
5304 if (irq == NMI_VECTOR)
7460fb4a 5305 vcpu->arch.nmi_pending = 0;
63995653
MG		 5306 else
5307 vcpu->arch.interrupt.pending = false;
5308
5309 return EMULATE_DONE;
5310}
5311EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5312
6d77dbfc
GN		 5313static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5314{
fc3a9157
JR		 5315 int r = EMULATE_DONE;
5316
6d77dbfc
GN		 5317 ++vcpu->stat.insn_emulation_fail;
5318 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5319 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5320 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5321 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5322 vcpu->run->internal.ndata = 0;
5323 r = EMULATE_FAIL;
5324 }
6d77dbfc 5325 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5326
5327 return r;
6d77dbfc
GN		 5328}
5329
93c05d3e 5330static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5331 bool write_fault_to_shadow_pgtable,
5332 int emulation_type)
a6f177ef 5333{
95b3cf69 5334 gpa_t gpa = cr2;
8e3d9d06 5335 pfn_t pfn;
a6f177ef 5336
991eebf9
GN		 5337 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5338 return false;
5339
95b3cf69
XG		 5340 if (!vcpu->arch.mmu.direct_map) {
5341 /*
5342 * Write permission should be allowed since only
5343 * write access need to be emulated.
5344 */
5345 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5346
95b3cf69
XG		 5347 /*
5348 * If the mapping is invalid in guest, let cpu retry
5349 * it to generate fault.
5350 */
5351 if (gpa == UNMAPPED_GVA)
5352 return true;
5353 }
a6f177ef 5354
8e3d9d06
XG		 5355 /*
5356 * Do not retry the unhandleable instruction if it faults on the
5357 * readonly host memory, otherwise it will goto a infinite loop:
5358 * retry instruction -> write #PF -> emulation fail -> retry
5359 * instruction -> ...
5360 */
5361 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5362
5363 /*
5364 * If the instruction failed on the error pfn, it can not be fixed,
5365 * report the error to userspace.
5366 */
5367 if (is_error_noslot_pfn(pfn))
5368 return false;
5369
5370 kvm_release_pfn_clean(pfn);
5371
5372 /* The instructions are well-emulated on direct mmu. */
5373 if (vcpu->arch.mmu.direct_map) {
5374 unsigned int indirect_shadow_pages;
5375
5376 spin_lock(&vcpu->kvm->mmu_lock);
5377 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5378 spin_unlock(&vcpu->kvm->mmu_lock);
5379
5380 if (indirect_shadow_pages)
5381 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5382
a6f177ef 5383 return true;
8e3d9d06 5384 }
a6f177ef 5385
95b3cf69
XG		 5386 /*
5387 * if emulation was due to access to shadowed page table
5388 * and it failed try to unshadow page and re-enter the
5389 * guest to let CPU execute the instruction.
5390 */
5391 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5392
5393 /*
5394 * If the access faults on its page table, it can not
5395 * be fixed by unprotecting shadow page and it should
5396 * be reported to userspace.
5397 */
5398 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5399}
5400
1cb3f3ae
XG		 5401static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5402 unsigned long cr2, int emulation_type)
5403{
5404 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5405 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5406
5407 last_retry_eip = vcpu->arch.last_retry_eip;
5408 last_retry_addr = vcpu->arch.last_retry_addr;
5409
5410 /*
5411 * If the emulation is caused by #PF and it is non-page_table
5412 * writing instruction, it means the VM-EXIT is caused by shadow
5413 * page protected, we can zap the shadow page and retry this
5414 * instruction directly.
5415 *
5416 * Note: if the guest uses a non-page-table modifying instruction
5417 * on the PDE that points to the instruction, then we will unmap
5418 * the instruction and go to an infinite loop. So, we cache the
5419 * last retried eip and the last fault address, if we meet the eip
5420 * and the address again, we can break out of the potential infinite
5421 * loop.
5422 */
5423 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5424
5425 if (!(emulation_type & EMULTYPE_RETRY))
5426 return false;
5427
5428 if (x86_page_table_writing_insn(ctxt))
5429 return false;
5430
5431 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5432 return false;
5433
5434 vcpu->arch.last_retry_eip = ctxt->eip;
5435 vcpu->arch.last_retry_addr = cr2;
5436
5437 if (!vcpu->arch.mmu.direct_map)
5438 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5439
22368028 5440 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5441
5442 return true;
5443}
5444
716d51ab
GN		 5445static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5446static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5447
a584539b
PB		 5448void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5449{
5450 vcpu->arch.hflags = emul_flags;
5451}
5452
4a1e10d5
PB		 5453static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5454 unsigned long *db)
5455{
5456 u32 dr6 = 0;
5457 int i;
5458 u32 enable, rwlen;
5459
5460 enable = dr7;
5461 rwlen = dr7 >> 16;
5462 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5463 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5464 dr6 |= (1 << i);
5465 return dr6;
5466}
5467
6addfc42 5468static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5469{
5470 struct kvm_run *kvm_run = vcpu->run;
5471
5472 /*
6addfc42
PB		 5473 * rflags is the old, "raw" value of the flags. The new value has
5474 * not been saved yet.
663f4c61
PB		 5475 *
5476 * This is correct even for TF set by the guest, because "the
5477 * processor will not generate this exception after the instruction
5478 * that sets the TF flag".
5479 */
663f4c61
PB		 5480 if (unlikely(rflags & X86_EFLAGS_TF)) {
5481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5482 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5483 DR6_RTM;
663f4c61
PB		 5484 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5485 kvm_run->debug.arch.exception = DB_VECTOR;
5486 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5487 *r = EMULATE_USER_EXIT;
5488 } else {
5489 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5490 /*
5491 * "Certain debug exceptions may clear bit 0-3. The
5492 * remaining contents of the DR6 register are never
5493 * cleared by the processor".
5494 */
5495 vcpu->arch.dr6 &= ~15;
6f43ed01 5496 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5497 kvm_queue_exception(vcpu, DB_VECTOR);
5498 }
5499 }
5500}
5501
4a1e10d5
PB		 5502static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5503{
4a1e10d5
PB		 5504 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5505 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5506 struct kvm_run *kvm_run = vcpu->run;
5507 unsigned long eip = kvm_get_linear_rip(vcpu);
5508 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5509 vcpu->arch.guest_debug_dr7,
5510 vcpu->arch.eff_db);
5511
5512 if (dr6 != 0) {
6f43ed01 5513 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5514 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5515 kvm_run->debug.arch.exception = DB_VECTOR;
5516 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5517 *r = EMULATE_USER_EXIT;
5518 return true;
5519 }
5520 }
5521
4161a569
NA		 5522 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5523 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5524 unsigned long eip = kvm_get_linear_rip(vcpu);
5525 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5526 vcpu->arch.dr7,
5527 vcpu->arch.db);
5528
5529 if (dr6 != 0) {
5530 vcpu->arch.dr6 &= ~15;
6f43ed01 5531 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5532 kvm_queue_exception(vcpu, DB_VECTOR);
5533 *r = EMULATE_DONE;
5534 return true;
5535 }
5536 }
5537
5538 return false;
5539}
5540
51d8b661
AP		 5541int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5542 unsigned long cr2,
dc25e89e
AP		 5543 int emulation_type,
5544 void *insn,
5545 int insn_len)
bbd9b64e 5546{
95cb2295 5547 int r;
9d74191a 5548 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5549 bool writeback = true;
93c05d3e 5550 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5551
93c05d3e
XG		 5552 /*
5553 * Clear write_fault_to_shadow_pgtable here to ensure it is
5554 * never reused.
5555 */
5556 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5557 kvm_clear_exception_queue(vcpu);
8d7d8102 5558
571008da 5559 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5560 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5561
5562 /*
5563 * We will reenter on the same instruction since
5564 * we do not set complete_userspace_io. This does not
5565 * handle watchpoints yet, those would be handled in
5566 * the emulate_ops.
5567 */
5568 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5569 return r;
5570
9d74191a
TY		 5571 ctxt->interruptibility = 0;
5572 ctxt->have_exception = false;
e0ad0b47 5573 ctxt->exception.vector = -1;
9d74191a 5574 ctxt->perm_ok = false;
bbd9b64e 5575
b51e974f 5576 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5577
9d74191a 5578 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5579
e46479f8 5580 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5581 ++vcpu->stat.insn_emulation;
1d2887e2 5582 if (r != EMULATION_OK) {
4005996e
AK		 5583 if (emulation_type & EMULTYPE_TRAP_UD)
5584 return EMULATE_FAIL;
991eebf9
GN		 5585 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5586 emulation_type))
bbd9b64e 5587 return EMULATE_DONE;
6d77dbfc
GN		 5588 if (emulation_type & EMULTYPE_SKIP)
5589 return EMULATE_FAIL;
5590 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5591 }
5592 }
5593
ba8afb6b 5594 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5595 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5596 if (ctxt->eflags & X86_EFLAGS_RF)
5597 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5598 return EMULATE_DONE;
5599 }
5600
1cb3f3ae
XG		 5601 if (retry_instruction(ctxt, cr2, emulation_type))
5602 return EMULATE_DONE;
5603
7ae441ea 5604 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5605 changes registers values during IO operation */
7ae441ea
GN		 5606 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5607 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5608 emulator_invalidate_register_cache(ctxt);
7ae441ea 5609 }
4d2179e1 5610
5cd21917 5611restart:
9d74191a 5612 r = x86_emulate_insn(ctxt);
bbd9b64e 5613
775fde86
JR		 5614 if (r == EMULATION_INTERCEPTED)
5615 return EMULATE_DONE;
5616
d2ddd1c4 5617 if (r == EMULATION_FAILED) {
991eebf9
GN		 5618 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5619 emulation_type))
c3cd7ffa
GN		 5620 return EMULATE_DONE;
5621
6d77dbfc 5622 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5623 }
5624
9d74191a 5625 if (ctxt->have_exception) {
d2ddd1c4 5626 r = EMULATE_DONE;
ef54bcfe
PB		 5627 if (inject_emulated_exception(vcpu))
5628 return r;
d2ddd1c4 5629 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5630 if (!vcpu->arch.pio.in) {
5631 /* FIXME: return into emulator if single-stepping. */
3457e419 5632 vcpu->arch.pio.count = 0;
0912c977 5633 } else {
7ae441ea 5634 writeback = false;
716d51ab
GN		 5635 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5636 }
ac0a48c3 5637 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5638 } else if (vcpu->mmio_needed) {
5639 if (!vcpu->mmio_is_write)
5640 writeback = false;
ac0a48c3 5641 r = EMULATE_USER_EXIT;
716d51ab 5642 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5643 } else if (r == EMULATION_RESTART)
5cd21917 5644 goto restart;
d2ddd1c4
GN		 5645 else
5646 r = EMULATE_DONE;
f850e2e6 5647
7ae441ea 5648 if (writeback) {
6addfc42 5649 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5650 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5651 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5652 if (vcpu->arch.hflags != ctxt->emul_flags)
5653 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5654 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5655 if (r == EMULATE_DONE)
6addfc42 5656 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5657 if (!ctxt->have_exception ||
5658 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5659 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5660
5661 /*
5662 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5663 * do nothing, and it will be requested again as soon as
5664 * the shadow expires. But we still need to check here,
5665 * because POPF has no interrupt shadow.
5666 */
5667 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5668 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5669 } else
5670 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5671
5672 return r;
de7d789a 5673}
51d8b661 5674EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5675
cf8f70bf 5676int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5677{
cf8f70bf 5678 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5679 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5680 size, port, &val, 1);
cf8f70bf 5681 /* do not return to emulator after return from userspace */
7972995b 5682 vcpu->arch.pio.count = 0;
de7d789a
CO		 5683 return ret;
5684}
cf8f70bf 5685EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5686
8cfdc000
ZA		 5687static void tsc_bad(void *info)
5688{
0a3aee0d 5689 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5690}
5691
5692static void tsc_khz_changed(void *data)
c8076604 5693{
8cfdc000
ZA		 5694 struct cpufreq_freqs *freq = data;
5695 unsigned long khz = 0;
5696
5697 if (data)
5698 khz = freq->new;
5699 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5700 khz = cpufreq_quick_get(raw_smp_processor_id());
5701 if (!khz)
5702 khz = tsc_khz;
0a3aee0d 5703 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5704}
5705
c8076604
GH		 5706static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5707 void *data)
5708{
5709 struct cpufreq_freqs *freq = data;
5710 struct kvm *kvm;
5711 struct kvm_vcpu *vcpu;
5712 int i, send_ipi = 0;
5713
8cfdc000
ZA		 5714 /*
5715 * We allow guests to temporarily run on slowing clocks,
5716 * provided we notify them after, or to run on accelerating
5717 * clocks, provided we notify them before. Thus time never
5718 * goes backwards.
5719 *
5720 * However, we have a problem. We can't atomically update
5721 * the frequency of a given CPU from this function; it is
5722 * merely a notifier, which can be called from any CPU.
5723 * Changing the TSC frequency at arbitrary points in time
5724 * requires a recomputation of local variables related to
5725 * the TSC for each VCPU. We must flag these local variables
5726 * to be updated and be sure the update takes place with the
5727 * new frequency before any guests proceed.
5728 *
5729 * Unfortunately, the combination of hotplug CPU and frequency
5730 * change creates an intractable locking scenario; the order
5731 * of when these callouts happen is undefined with respect to
5732 * CPU hotplug, and they can race with each other. As such,
5733 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5734 * undefined; you can actually have a CPU frequency change take
5735 * place in between the computation of X and the setting of the
5736 * variable. To protect against this problem, all updates of
5737 * the per_cpu tsc_khz variable are done in an interrupt
5738 * protected IPI, and all callers wishing to update the value
5739 * must wait for a synchronous IPI to complete (which is trivial
5740 * if the caller is on the CPU already). This establishes the
5741 * necessary total order on variable updates.
5742 *
5743 * Note that because a guest time update may take place
5744 * anytime after the setting of the VCPU's request bit, the
5745 * correct TSC value must be set before the request. However,
5746 * to ensure the update actually makes it to any guest which
5747 * starts running in hardware virtualization between the set
5748 * and the acquisition of the spinlock, we must also ping the
5749 * CPU after setting the request bit.
5750 *
5751 */
5752
c8076604
GH		 5753 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5754 return 0;
5755 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5756 return 0;
8cfdc000
ZA		 5757
5758 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5759
2f303b74 5760 spin_lock(&kvm_lock);
c8076604 5761 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5762 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5763 if (vcpu->cpu != freq->cpu)
5764 continue;
c285545f 5765 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5766 if (vcpu->cpu != smp_processor_id())
8cfdc000 5767 send_ipi = 1;
c8076604
GH		 5768 }
5769 }
2f303b74 5770 spin_unlock(&kvm_lock);
c8076604
GH		 5771
5772 if (freq->old < freq->new && send_ipi) {
5773 /*
5774 * We upscale the frequency. Must make the guest
5775 * doesn't see old kvmclock values while running with
5776 * the new frequency, otherwise we risk the guest sees
5777 * time go backwards.
5778 *
5779 * In case we update the frequency for another cpu
5780 * (which might be in guest context) send an interrupt
5781 * to kick the cpu out of guest context. Next time
5782 * guest context is entered kvmclock will be updated,
5783 * so the guest will not see stale values.
5784 */
8cfdc000 5785 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5786 }
5787 return 0;
5788}
5789
5790static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5791 .notifier_call = kvmclock_cpufreq_notifier
5792};
5793
5794static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5795 unsigned long action, void *hcpu)
5796{
5797 unsigned int cpu = (unsigned long)hcpu;
5798
5799 switch (action) {
5800 case CPU_ONLINE:
5801 case CPU_DOWN_FAILED:
5802 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5803 break;
5804 case CPU_DOWN_PREPARE:
5805 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5806 break;
5807 }
5808 return NOTIFY_OK;
5809}
5810
5811static struct notifier_block kvmclock_cpu_notifier_block = {
5812 .notifier_call = kvmclock_cpu_notifier,
5813 .priority = -INT_MAX
c8076604
GH		 5814};
5815
b820cc0c
ZA		 5816static void kvm_timer_init(void)
5817{
5818 int cpu;
5819
c285545f 5820 max_tsc_khz = tsc_khz;
460dd42e
SB		 5821
5822 cpu_notifier_register_begin();
b820cc0c 5823 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5824#ifdef CONFIG_CPU_FREQ
5825 struct cpufreq_policy policy;
5826 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5827 cpu = get_cpu();
5828 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5829 if (policy.cpuinfo.max_freq)
5830 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5831 put_cpu();
c285545f 5832#endif
b820cc0c
ZA		 5833 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5834 CPUFREQ_TRANSITION_NOTIFIER);
5835 }
c285545f 5836 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5837 for_each_online_cpu(cpu)
5838 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5839
5840 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5841 cpu_notifier_register_done();
5842
b820cc0c
ZA		 5843}
5844
ff9d07a0
ZY		 5845static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5846
f5132b01 5847int kvm_is_in_guest(void)
ff9d07a0 5848{
086c9855 5849 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5850}
5851
5852static int kvm_is_user_mode(void)
5853{
5854 int user_mode = 3;
dcf46b94 5855
086c9855
AS		 5856 if (__this_cpu_read(current_vcpu))
5857 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5858
ff9d07a0
ZY		 5859 return user_mode != 0;
5860}
5861
5862static unsigned long kvm_get_guest_ip(void)
5863{
5864 unsigned long ip = 0;
dcf46b94 5865
086c9855
AS		 5866 if (__this_cpu_read(current_vcpu))
5867 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5868
ff9d07a0
ZY		 5869 return ip;
5870}
5871
5872static struct perf_guest_info_callbacks kvm_guest_cbs = {
5873 .is_in_guest = kvm_is_in_guest,
5874 .is_user_mode = kvm_is_user_mode,
5875 .get_guest_ip = kvm_get_guest_ip,
5876};
5877
5878void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5879{
086c9855 5880 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5881}
5882EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5883
5884void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5885{
086c9855 5886 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5887}
5888EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5889
ce88decf
XG		 5890static void kvm_set_mmio_spte_mask(void)
5891{
5892 u64 mask;
5893 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5894
5895 /*
5896 * Set the reserved bits and the present bit of an paging-structure
5897 * entry to generate page fault with PFER.RSV = 1.
5898 */
885032b9 5899 /* Mask the reserved physical address bits. */
d1431483 5900 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5901
5902 /* Bit 62 is always reserved for 32bit host. */
5903 mask |= 0x3ull << 62;
5904
5905 /* Set the present bit. */
ce88decf
XG		 5906 mask |= 1ull;
5907
5908#ifdef CONFIG_X86_64
5909 /*
5910 * If reserved bit is not supported, clear the present bit to disable
5911 * mmio page fault.
5912 */
5913 if (maxphyaddr == 52)
5914 mask &= ~1ull;
5915#endif
5916
5917 kvm_mmu_set_mmio_spte_mask(mask);
5918}
5919
16e8d74d
MT		 5920#ifdef CONFIG_X86_64
5921static void pvclock_gtod_update_fn(struct work_struct *work)
5922{
d828199e
MT		 5923 struct kvm *kvm;
5924
5925 struct kvm_vcpu *vcpu;
5926 int i;
5927
2f303b74 5928 spin_lock(&kvm_lock);
d828199e
MT		 5929 list_for_each_entry(kvm, &vm_list, vm_list)
5930 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5931 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5932 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5933 spin_unlock(&kvm_lock);
16e8d74d
MT		 5934}
5935
5936static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5937
5938/*
5939 * Notification about pvclock gtod data update.
5940 */
5941static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5942 void *priv)
5943{
5944 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5945 struct timekeeper *tk = priv;
5946
5947 update_pvclock_gtod(tk);
5948
5949 /* disable master clock if host does not trust, or does not
5950 * use, TSC clocksource
5951 */
5952 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5953 atomic_read(&kvm_guest_has_master_clock) != 0)
5954 queue_work(system_long_wq, &pvclock_gtod_work);
5955
5956 return 0;
5957}
5958
5959static struct notifier_block pvclock_gtod_notifier = {
5960 .notifier_call = pvclock_gtod_notify,
5961};
5962#endif
5963
f8c16bba 5964int kvm_arch_init(void *opaque)
043405e1 5965{
b820cc0c 5966 int r;
6b61edf7 5967 struct kvm_x86_ops *ops = opaque;
f8c16bba 5968
f8c16bba
ZX		 5969 if (kvm_x86_ops) {
5970 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5971 r = -EEXIST;
5972 goto out;
f8c16bba
ZX		 5973 }
5974
5975 if (!ops->cpu_has_kvm_support()) {
5976 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5977 r = -EOPNOTSUPP;
5978 goto out;
f8c16bba
ZX		 5979 }
5980 if (ops->disabled_by_bios()) {
5981 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5982 r = -EOPNOTSUPP;
5983 goto out;
f8c16bba
ZX		 5984 }
5985
013f6a5d
MT		 5986 r = -ENOMEM;
5987 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5988 if (!shared_msrs) {
5989 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5990 goto out;
5991 }
5992
97db56ce
AK		 5993 r = kvm_mmu_module_init();
5994 if (r)
013f6a5d 5995 goto out_free_percpu;
97db56ce 5996
ce88decf 5997 kvm_set_mmio_spte_mask();
97db56ce 5998
f8c16bba 5999 kvm_x86_ops = ops;
920c8377 6000
7b52345e 6001 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 6002 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 6003
b820cc0c 6004 kvm_timer_init();
c8076604 6005
ff9d07a0
ZY		 6006 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6007
2acf923e
DC		 6008 if (cpu_has_xsave)
6009 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6010
c5cc421b 6011 kvm_lapic_init();
16e8d74d
MT		 6012#ifdef CONFIG_X86_64
6013 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6014#endif
6015
f8c16bba 6016 return 0;
56c6d28a 6017
013f6a5d
MT		 6018out_free_percpu:
6019 free_percpu(shared_msrs);
56c6d28a 6020out:
56c6d28a 6021 return r;
043405e1 6022}
8776e519 6023
f8c16bba
ZX		 6024void kvm_arch_exit(void)
6025{
ff9d07a0
ZY		 6026 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6027
888d256e
JK		 6028 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6029 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6030 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 6031 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 6032#ifdef CONFIG_X86_64
6033 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6034#endif
f8c16bba 6035 kvm_x86_ops = NULL;
56c6d28a 6036 kvm_mmu_module_exit();
013f6a5d 6037 free_percpu(shared_msrs);
56c6d28a 6038}
f8c16bba 6039
5cb56059 6040int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6041{
6042 ++vcpu->stat.halt_exits;
6043 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 6044 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6045 return 1;
6046 } else {
6047 vcpu->run->exit_reason = KVM_EXIT_HLT;
6048 return 0;
6049 }
6050}
5cb56059
JS		 6051EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6052
6053int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6054{
6055 kvm_x86_ops->skip_emulated_instruction(vcpu);
6056 return kvm_vcpu_halt(vcpu);
6057}
8776e519
HB		 6058EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6059
55cd8e5a
GN		 6060int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
6061{
6062 u64 param, ingpa, outgpa, ret;
6063 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
6064 bool fast, longmode;
55cd8e5a
GN		 6065
6066 /*
6067 * hypercall generates UD from non zero cpl and real mode
6068 * per HYPER-V spec
6069 */
3eeb3288 6070 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 6071 kvm_queue_exception(vcpu, UD_VECTOR);
6072 return 0;
6073 }
6074
a449c7aa 6075 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 6076
6077 if (!longmode) {
ccd46936
GN		 6078 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
6079 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
6080 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
6081 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
6082 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
6083 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 6084 }
6085#ifdef CONFIG_X86_64
6086 else {
6087 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
6088 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
6089 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
6090 }
6091#endif
6092
6093 code = param & 0xffff;
6094 fast = (param >> 16) & 0x1;
6095 rep_cnt = (param >> 32) & 0xfff;
6096 rep_idx = (param >> 48) & 0xfff;
6097
6098 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
6099
c25bc163
GN		 6100 switch (code) {
6101 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
6102 kvm_vcpu_on_spin(vcpu);
6103 break;
6104 default:
6105 res = HV_STATUS_INVALID_HYPERCALL_CODE;
6106 break;
6107 }
55cd8e5a
GN		 6108
6109 ret = res | (((u64)rep_done & 0xfff) << 32);
6110 if (longmode) {
6111 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6112 } else {
6113 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
6114 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
6115 }
6116
6117 return 1;
6118}
6119
6aef266c
SV		 6120/*
6121 * kvm_pv_kick_cpu_op: Kick a vcpu.
6122 *
6123 * @apicid - apicid of vcpu to be kicked.
6124 */
6125static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6126{
24d2166b 6127 struct kvm_lapic_irq lapic_irq;
6aef266c 6128
24d2166b
R		 6129 lapic_irq.shorthand = 0;
6130 lapic_irq.dest_mode = 0;
6131 lapic_irq.dest_id = apicid;
93bbf0b8 6132 lapic_irq.msi_redir_hint = false;
6aef266c 6133
24d2166b 6134 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6135 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6136}
6137
8776e519
HB		 6138int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6139{
6140 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6141 int op_64_bit, r = 1;
8776e519 6142
5cb56059
JS		 6143 kvm_x86_ops->skip_emulated_instruction(vcpu);
6144
55cd8e5a
GN		 6145 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6146 return kvm_hv_hypercall(vcpu);
6147
5fdbf976
MT		 6148 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6149 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6150 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6151 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6152 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6153
229456fc 6154 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6155
a449c7aa
NA		 6156 op_64_bit = is_64_bit_mode(vcpu);
6157 if (!op_64_bit) {
8776e519
HB		 6158 nr &= 0xFFFFFFFF;
6159 a0 &= 0xFFFFFFFF;
6160 a1 &= 0xFFFFFFFF;
6161 a2 &= 0xFFFFFFFF;
6162 a3 &= 0xFFFFFFFF;
6163 }
6164
07708c4a
JK		 6165 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6166 ret = -KVM_EPERM;
6167 goto out;
6168 }
6169
8776e519 6170 switch (nr) {
b93463aa
AK		 6171 case KVM_HC_VAPIC_POLL_IRQ:
6172 ret = 0;
6173 break;
6aef266c
SV		 6174 case KVM_HC_KICK_CPU:
6175 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6176 ret = 0;
6177 break;
8776e519
HB		 6178 default:
6179 ret = -KVM_ENOSYS;
6180 break;
6181 }
07708c4a 6182out:
a449c7aa
NA		 6183 if (!op_64_bit)
6184 ret = (u32)ret;
5fdbf976 6185 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6186 ++vcpu->stat.hypercalls;
2f333bcb 6187 return r;
8776e519
HB		 6188}
6189EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6190
b6785def 6191static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6192{
d6aa1000 6193 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6194 char instruction[3];
5fdbf976 6195 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6196
8776e519 6197 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6198
9d74191a 6199 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6200}
6201
b6c7a5dc
HB		 6202/*
6203 * Check if userspace requested an interrupt window, and that the
6204 * interrupt window is open.
6205 *
6206 * No need to exit to userspace if we already have an interrupt queued.
6207 */
851ba692 6208static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6209{
8061823a 6210 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6211 vcpu->run->request_interrupt_window &&
5df56646 6212 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6213}
6214
851ba692 6215static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6216{
851ba692
AK		 6217 struct kvm_run *kvm_run = vcpu->run;
6218
91586a3b 6219 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6220 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6221 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6222 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6223 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6224 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6225 else
b6c7a5dc 6226 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6227 kvm_arch_interrupt_allowed(vcpu) &&
6228 !kvm_cpu_has_interrupt(vcpu) &&
6229 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6230}
6231
95ba8273
GN		 6232static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6233{
6234 int max_irr, tpr;
6235
6236 if (!kvm_x86_ops->update_cr8_intercept)
6237 return;
6238
88c808fd
AK		 6239 if (!vcpu->arch.apic)
6240 return;
6241
8db3baa2
GN		 6242 if (!vcpu->arch.apic->vapic_addr)
6243 max_irr = kvm_lapic_find_highest_irr(vcpu);
6244 else
6245 max_irr = -1;
95ba8273
GN		 6246
6247 if (max_irr != -1)
6248 max_irr >>= 4;
6249
6250 tpr = kvm_lapic_get_cr8(vcpu);
6251
6252 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6253}
6254
b6b8a145 6255static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6256{
b6b8a145
JK		 6257 int r;
6258
95ba8273 6259 /* try to reinject previous events if any */
b59bb7bd 6260 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6261 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6262 vcpu->arch.exception.has_error_code,
6263 vcpu->arch.exception.error_code);
d6e8c854
NA		 6264
6265 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6266 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6267 X86_EFLAGS_RF);
6268
6bdf0662
NA		 6269 if (vcpu->arch.exception.nr == DB_VECTOR &&
6270 (vcpu->arch.dr7 & DR7_GD)) {
6271 vcpu->arch.dr7 &= ~DR7_GD;
6272 kvm_update_dr7(vcpu);
6273 }
6274
b59bb7bd
GN		 6275 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6276 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6277 vcpu->arch.exception.error_code,
6278 vcpu->arch.exception.reinject);
b6b8a145 6279 return 0;
b59bb7bd
GN		 6280 }
6281
95ba8273
GN		 6282 if (vcpu->arch.nmi_injected) {
6283 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6284 return 0;
95ba8273
GN		 6285 }
6286
6287 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6288 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6289 return 0;
6290 }
6291
6292 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6293 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6294 if (r != 0)
6295 return r;
95ba8273
GN		 6296 }
6297
6298 /* try to inject new event if pending */
6299 if (vcpu->arch.nmi_pending) {
6300 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6301 --vcpu->arch.nmi_pending;
95ba8273
GN		 6302 vcpu->arch.nmi_injected = true;
6303 kvm_x86_ops->set_nmi(vcpu);
6304 }
c7c9c56c 6305 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6306 /*
6307 * Because interrupts can be injected asynchronously, we are
6308 * calling check_nested_events again here to avoid a race condition.
6309 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6310 * proposal and current concerns. Perhaps we should be setting
6311 * KVM_REQ_EVENT only on certain events and not unconditionally?
6312 */
6313 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6314 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6315 if (r != 0)
6316 return r;
6317 }
95ba8273 6318 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6319 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6320 false);
6321 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6322 }
6323 }
b6b8a145 6324 return 0;
95ba8273
GN		 6325}
6326
7460fb4a
AK		 6327static void process_nmi(struct kvm_vcpu *vcpu)
6328{
6329 unsigned limit = 2;
6330
6331 /*
6332 * x86 is limited to one NMI running, and one NMI pending after it.
6333 * If an NMI is already in progress, limit further NMIs to just one.
6334 * Otherwise, allow two (and we'll inject the first one immediately).
6335 */
6336 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6337 limit = 1;
6338
6339 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6340 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6341 kvm_make_request(KVM_REQ_EVENT, vcpu);
6342}
6343
3d81bc7e 6344static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6345{
6346 u64 eoi_exit_bitmap[4];
cf9e65b7 6347 u32 tmr[8];
c7c9c56c 6348
3d81bc7e
YZ		 6349 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6350 return;
c7c9c56c
YZ		 6351
6352 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6353 memset(tmr, 0, 32);
c7c9c56c 6354
cf9e65b7 6355 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6356 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6357 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6358}
6359
a70656b6
RK		 6360static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6361{
6362 ++vcpu->stat.tlb_flush;
6363 kvm_x86_ops->tlb_flush(vcpu);
6364}
6365
4256f43f
TC		 6366void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6367{
c24ae0dc
TC		 6368 struct page *page = NULL;
6369
f439ed27
PB		 6370 if (!irqchip_in_kernel(vcpu->kvm))
6371 return;
6372
4256f43f
TC		 6373 if (!kvm_x86_ops->set_apic_access_page_addr)
6374 return;
6375
c24ae0dc 6376 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6377 if (is_error_page(page))
6378 return;
c24ae0dc
TC		 6379 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6380
6381 /*
6382 * Do not pin apic access page in memory, the MMU notifier
6383 * will call us again if it is migrated or swapped out.
6384 */
6385 put_page(page);
4256f43f
TC		 6386}
6387EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6388
fe71557a
TC		 6389void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6390 unsigned long address)
6391{
c24ae0dc
TC		 6392 /*
6393 * The physical address of apic access page is stored in the VMCS.
6394 * Update it when it becomes invalid.
6395 */
6396 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6397 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6398}
6399
9357d939 6400/*
362c698f 6401 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6402 * exiting to the userspace. Otherwise, the value will be returned to the
6403 * userspace.
6404 */
851ba692 6405static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6406{
6407 int r;
6a8b1d13 6408 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6409 vcpu->run->request_interrupt_window;
730dca42 6410 bool req_immediate_exit = false;
b6c7a5dc 6411
3e007509 6412 if (vcpu->requests) {
a8eeb04a 6413 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6414 kvm_mmu_unload(vcpu);
a8eeb04a 6415 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6416 __kvm_migrate_timers(vcpu);
d828199e
MT		 6417 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6418 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6419 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6420 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6421 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6422 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6423 if (unlikely(r))
6424 goto out;
6425 }
a8eeb04a 6426 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6427 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6428 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6429 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6430 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6431 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6432 r = 0;
6433 goto out;
6434 }
a8eeb04a 6435 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6436 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6437 r = 0;
6438 goto out;
6439 }
a8eeb04a 6440 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6441 vcpu->fpu_active = 0;
6442 kvm_x86_ops->fpu_deactivate(vcpu);
6443 }
af585b92
GN		 6444 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6445 /* Page is swapped out. Do synthetic halt */
6446 vcpu->arch.apf.halted = true;
6447 r = 1;
6448 goto out;
6449 }
c9aaa895
GC		 6450 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6451 record_steal_time(vcpu);
7460fb4a
AK		 6452 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6453 process_nmi(vcpu);
f5132b01
GN		 6454 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6455 kvm_handle_pmu_event(vcpu);
6456 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6457 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6458 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6459 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6460 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6461 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6462 }
b93463aa 6463
b463a6f7 6464 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6465 kvm_apic_accept_events(vcpu);
6466 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6467 r = 1;
6468 goto out;
6469 }
6470
b6b8a145
JK		 6471 if (inject_pending_event(vcpu, req_int_win) != 0)
6472 req_immediate_exit = true;
b463a6f7 6473 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6474 else if (vcpu->arch.nmi_pending)
c9a7953f 6475 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6476 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6477 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6478
6479 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6480 /*
6481 * Update architecture specific hints for APIC
6482 * virtual interrupt delivery.
6483 */
6484 if (kvm_x86_ops->hwapic_irr_update)
6485 kvm_x86_ops->hwapic_irr_update(vcpu,
6486 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6487 update_cr8_intercept(vcpu);
6488 kvm_lapic_sync_to_vapic(vcpu);
6489 }
6490 }
6491
d8368af8
AK		 6492 r = kvm_mmu_reload(vcpu);
6493 if (unlikely(r)) {
d905c069 6494 goto cancel_injection;
d8368af8
AK		 6495 }
6496
b6c7a5dc
HB		 6497 preempt_disable();
6498
6499 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6500 if (vcpu->fpu_active)
6501 kvm_load_guest_fpu(vcpu);
2acf923e 6502 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6503
6b7e2d09
XG		 6504 vcpu->mode = IN_GUEST_MODE;
6505
01b71917
MT		 6506 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6507
6b7e2d09
XG		 6508 /* We should set ->mode before check ->requests,
6509 * see the comment in make_all_cpus_request.
6510 */
01b71917 6511 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6512
d94e1dc9 6513 local_irq_disable();
32f88400 6514
6b7e2d09 6515 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6516 || need_resched() || signal_pending(current)) {
6b7e2d09 6517 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6518 smp_wmb();
6c142801
AK		 6519 local_irq_enable();
6520 preempt_enable();
01b71917 6521 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6522 r = 1;
d905c069 6523 goto cancel_injection;
6c142801
AK		 6524 }
6525
d6185f20
NHE		 6526 if (req_immediate_exit)
6527 smp_send_reschedule(vcpu->cpu);
6528
ccf73aaf 6529 __kvm_guest_enter();
b6c7a5dc 6530
42dbaa5a 6531 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6532 set_debugreg(0, 7);
6533 set_debugreg(vcpu->arch.eff_db[0], 0);
6534 set_debugreg(vcpu->arch.eff_db[1], 1);
6535 set_debugreg(vcpu->arch.eff_db[2], 2);
6536 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6537 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6538 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6539 }
b6c7a5dc 6540
229456fc 6541 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6542 wait_lapic_expire(vcpu);
851ba692 6543 kvm_x86_ops->run(vcpu);
b6c7a5dc 6544
c77fb5fe
PB		 6545 /*
6546 * Do this here before restoring debug registers on the host. And
6547 * since we do this before handling the vmexit, a DR access vmexit
6548 * can (a) read the correct value of the debug registers, (b) set
6549 * KVM_DEBUGREG_WONT_EXIT again.
6550 */
6551 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6552 int i;
6553
6554 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6555 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6556 for (i = 0; i < KVM_NR_DB_REGS; i++)
6557 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6558 }
6559
24f1e32c
FW		 6560 /*
6561 * If the guest has used debug registers, at least dr7
6562 * will be disabled while returning to the host.
6563 * If we don't have active breakpoints in the host, we don't
6564 * care about the messed up debug address registers. But if
6565 * we have some of them active, restore the old state.
6566 */
59d8eb53 6567 if (hw_breakpoint_active())
24f1e32c 6568 hw_breakpoint_restore();
42dbaa5a 6569
886b470c
MT		 6570 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6571 native_read_tsc());
1d5f066e 6572
6b7e2d09 6573 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6574 smp_wmb();
a547c6db
YZ		 6575
6576 /* Interrupt is enabled by handle_external_intr() */
6577 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6578
6579 ++vcpu->stat.exits;
6580
6581 /*
6582 * We must have an instruction between local_irq_enable() and
6583 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6584 * the interrupt shadow. The stat.exits increment will do nicely.
6585 * But we need to prevent reordering, hence this barrier():
6586 */
6587 barrier();
6588
6589 kvm_guest_exit();
6590
6591 preempt_enable();
6592
f656ce01 6593 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6594
b6c7a5dc
HB		 6595 /*
6596 * Profile KVM exit RIPs:
6597 */
6598 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6599 unsigned long rip = kvm_rip_read(vcpu);
6600 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6601 }
6602
cc578287
ZA		 6603 if (unlikely(vcpu->arch.tsc_always_catchup))
6604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6605
5cfb1d5a
MT		 6606 if (vcpu->arch.apic_attention)
6607 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6608
851ba692 6609 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6610 return r;
6611
6612cancel_injection:
6613 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6614 if (unlikely(vcpu->arch.apic_attention))
6615 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6616out:
6617 return r;
6618}
b6c7a5dc 6619
362c698f
PB		 6620static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6621{
9c8fd1ba
PB		 6622 if (!kvm_arch_vcpu_runnable(vcpu)) {
6623 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6624 kvm_vcpu_block(vcpu);
6625 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6626 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6627 return 1;
6628 }
362c698f
PB		 6629
6630 kvm_apic_accept_events(vcpu);
6631 switch(vcpu->arch.mp_state) {
6632 case KVM_MP_STATE_HALTED:
6633 vcpu->arch.pv.pv_unhalted = false;
6634 vcpu->arch.mp_state =
6635 KVM_MP_STATE_RUNNABLE;
6636 case KVM_MP_STATE_RUNNABLE:
6637 vcpu->arch.apf.halted = false;
6638 break;
6639 case KVM_MP_STATE_INIT_RECEIVED:
6640 break;
6641 default:
6642 return -EINTR;
6643 break;
6644 }
6645 return 1;
6646}
09cec754 6647
362c698f 6648static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6649{
6650 int r;
f656ce01 6651 struct kvm *kvm = vcpu->kvm;
d7690175 6652
f656ce01 6653 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6654
362c698f 6655 for (;;) {
af585b92
GN		 6656 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6657 !vcpu->arch.apf.halted)
851ba692 6658 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6659 else
6660 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6661 if (r <= 0)
6662 break;
6663
6664 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6665 if (kvm_cpu_has_pending_timer(vcpu))
6666 kvm_inject_pending_timer_irqs(vcpu);
6667
851ba692 6668 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6669 r = -EINTR;
851ba692 6670 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6671 ++vcpu->stat.request_irq_exits;
362c698f 6672 break;
09cec754 6673 }
af585b92
GN		 6674
6675 kvm_check_async_pf_completion(vcpu);
6676
09cec754
GN		 6677 if (signal_pending(current)) {
6678 r = -EINTR;
851ba692 6679 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6680 ++vcpu->stat.signal_exits;
362c698f 6681 break;
09cec754
GN		 6682 }
6683 if (need_resched()) {
f656ce01 6684 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6685 cond_resched();
f656ce01 6686 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6687 }
b6c7a5dc
HB		 6688 }
6689
f656ce01 6690 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6691
6692 return r;
6693}
6694
716d51ab
GN		 6695static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6696{
6697 int r;
6698 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6699 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6700 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6701 if (r != EMULATE_DONE)
6702 return 0;
6703 return 1;
6704}
6705
6706static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6707{
6708 BUG_ON(!vcpu->arch.pio.count);
6709
6710 return complete_emulated_io(vcpu);
6711}
6712
f78146b0
AK		 6713/*
6714 * Implements the following, as a state machine:
6715 *
6716 * read:
6717 * for each fragment
87da7e66
XG		 6718 * for each mmio piece in the fragment
6719 * write gpa, len
6720 * exit
6721 * copy data
f78146b0
AK		 6722 * execute insn
6723 *
6724 * write:
6725 * for each fragment
87da7e66
XG		 6726 * for each mmio piece in the fragment
6727 * write gpa, len
6728 * copy data
6729 * exit
f78146b0 6730 */
716d51ab 6731static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6732{
6733 struct kvm_run *run = vcpu->run;
f78146b0 6734 struct kvm_mmio_fragment *frag;
87da7e66 6735 unsigned len;
5287f194 6736
716d51ab 6737 BUG_ON(!vcpu->mmio_needed);
5287f194 6738
716d51ab 6739 /* Complete previous fragment */
87da7e66
XG		 6740 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6741 len = min(8u, frag->len);
716d51ab 6742 if (!vcpu->mmio_is_write)
87da7e66
XG		 6743 memcpy(frag->data, run->mmio.data, len);
6744
6745 if (frag->len <= 8) {
6746 /* Switch to the next fragment. */
6747 frag++;
6748 vcpu->mmio_cur_fragment++;
6749 } else {
6750 /* Go forward to the next mmio piece. */
6751 frag->data += len;
6752 frag->gpa += len;
6753 frag->len -= len;
6754 }
6755
a08d3b3b 6756 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6757 vcpu->mmio_needed = 0;
0912c977
PB		 6758
6759 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6760 if (vcpu->mmio_is_write)
716d51ab
GN		 6761 return 1;
6762 vcpu->mmio_read_completed = 1;
6763 return complete_emulated_io(vcpu);
6764 }
87da7e66 6765
716d51ab
GN		 6766 run->exit_reason = KVM_EXIT_MMIO;
6767 run->mmio.phys_addr = frag->gpa;
6768 if (vcpu->mmio_is_write)
87da7e66
XG		 6769 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6770 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6771 run->mmio.is_write = vcpu->mmio_is_write;
6772 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6773 return 0;
5287f194
AK		 6774}
6775
716d51ab 6776
b6c7a5dc
HB		 6777int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6778{
6779 int r;
6780 sigset_t sigsaved;
6781
e5c30142
AK		 6782 if (!tsk_used_math(current) && init_fpu(current))
6783 return -ENOMEM;
6784
ac9f6dc0
AK		 6785 if (vcpu->sigset_active)
6786 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6787
a4535290 6788 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6789 kvm_vcpu_block(vcpu);
66450a21 6790 kvm_apic_accept_events(vcpu);
d7690175 6791 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6792 r = -EAGAIN;
6793 goto out;
b6c7a5dc
HB		 6794 }
6795
b6c7a5dc 6796 /* re-sync apic's tpr */
eea1cff9
AP		 6797 if (!irqchip_in_kernel(vcpu->kvm)) {
6798 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6799 r = -EINVAL;
6800 goto out;
6801 }
6802 }
b6c7a5dc 6803
716d51ab
GN		 6804 if (unlikely(vcpu->arch.complete_userspace_io)) {
6805 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6806 vcpu->arch.complete_userspace_io = NULL;
6807 r = cui(vcpu);
6808 if (r <= 0)
6809 goto out;
6810 } else
6811 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6812
362c698f 6813 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6814
6815out:
f1d86e46 6816 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6817 if (vcpu->sigset_active)
6818 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6819
b6c7a5dc
HB		 6820 return r;
6821}
6822
6823int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6824{
7ae441ea
GN		 6825 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6826 /*
6827 * We are here if userspace calls get_regs() in the middle of
6828 * instruction emulation. Registers state needs to be copied
4a969980 6829 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6830 * that usually, but some bad designed PV devices (vmware
6831 * backdoor interface) need this to work
6832 */
dd856efa 6833 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6834 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6835 }
5fdbf976
MT		 6836 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6837 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6838 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6839 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6840 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6841 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6842 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6843 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6844#ifdef CONFIG_X86_64
5fdbf976
MT		 6845 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6846 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6847 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6848 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6849 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6850 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6851 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6852 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6853#endif
6854
5fdbf976 6855 regs->rip = kvm_rip_read(vcpu);
91586a3b 6856 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6857
b6c7a5dc
HB		 6858 return 0;
6859}
6860
6861int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6862{
7ae441ea
GN		 6863 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6864 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6865
5fdbf976
MT		 6866 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6867 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6868 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6869 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6870 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6871 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6872 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6873 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6874#ifdef CONFIG_X86_64
5fdbf976
MT		 6875 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6876 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6877 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6878 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6879 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6880 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6881 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6882 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6883#endif
6884
5fdbf976 6885 kvm_rip_write(vcpu, regs->rip);
91586a3b 6886 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6887
b4f14abd
JK		 6888 vcpu->arch.exception.pending = false;
6889
3842d135
AK		 6890 kvm_make_request(KVM_REQ_EVENT, vcpu);
6891
b6c7a5dc
HB		 6892 return 0;
6893}
6894
b6c7a5dc
HB		 6895void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6896{
6897 struct kvm_segment cs;
6898
3e6e0aab 6899 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6900 *db = cs.db;
6901 *l = cs.l;
6902}
6903EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6904
6905int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6906 struct kvm_sregs *sregs)
6907{
89a27f4d 6908 struct desc_ptr dt;
b6c7a5dc 6909
3e6e0aab
GT		 6910 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6911 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6912 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6913 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6914 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6915 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6916
3e6e0aab
GT		 6917 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6918 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6919
6920 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6921 sregs->idt.limit = dt.size;
6922 sregs->idt.base = dt.address;
b6c7a5dc 6923 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6924 sregs->gdt.limit = dt.size;
6925 sregs->gdt.base = dt.address;
b6c7a5dc 6926
4d4ec087 6927 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6928 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6929 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6930 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6931 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6932 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6933 sregs->apic_base = kvm_get_apic_base(vcpu);
6934
923c61bb 6935 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6936
36752c9b 6937 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6938 set_bit(vcpu->arch.interrupt.nr,
6939 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6940
b6c7a5dc
HB		 6941 return 0;
6942}
6943
62d9f0db
MT		 6944int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6945 struct kvm_mp_state *mp_state)
6946{
66450a21 6947 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6948 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6949 vcpu->arch.pv.pv_unhalted)
6950 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6951 else
6952 mp_state->mp_state = vcpu->arch.mp_state;
6953
62d9f0db
MT		 6954 return 0;
6955}
6956
6957int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6958 struct kvm_mp_state *mp_state)
6959{
66450a21
JK		 6960 if (!kvm_vcpu_has_lapic(vcpu) &&
6961 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6962 return -EINVAL;
6963
6964 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6965 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6966 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6967 } else
6968 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6969 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6970 return 0;
6971}
6972
7f3d35fd
KW		 6973int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6974 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6975{
9d74191a 6976 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6977 int ret;
e01c2426 6978
8ec4722d 6979 init_emulate_ctxt(vcpu);
c697518a 6980
7f3d35fd 6981 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6982 has_error_code, error_code);
c697518a 6983
c697518a 6984 if (ret)
19d04437 6985 return EMULATE_FAIL;
37817f29 6986
9d74191a
TY		 6987 kvm_rip_write(vcpu, ctxt->eip);
6988 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6989 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6990 return EMULATE_DONE;
37817f29
IE		 6991}
6992EXPORT_SYMBOL_GPL(kvm_task_switch);
6993
b6c7a5dc
HB		 6994int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6995 struct kvm_sregs *sregs)
6996{
58cb628d 6997 struct msr_data apic_base_msr;
b6c7a5dc 6998 int mmu_reset_needed = 0;
63f42e02 6999 int pending_vec, max_bits, idx;
89a27f4d 7000 struct desc_ptr dt;
b6c7a5dc 7001
6d1068b3
PM		 7002 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7003 return -EINVAL;
7004
89a27f4d
GN		 7005 dt.size = sregs->idt.limit;
7006 dt.address = sregs->idt.base;
b6c7a5dc 7007 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7008 dt.size = sregs->gdt.limit;
7009 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7010 kvm_x86_ops->set_gdt(vcpu, &dt);
7011
ad312c7c 7012 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7013 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7014 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7015 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7016
2d3ad1f4 7017 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7018
f6801dff 7019 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7020 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7021 apic_base_msr.data = sregs->apic_base;
7022 apic_base_msr.host_initiated = true;
7023 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7024
4d4ec087 7025 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7026 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7027 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7028
fc78f519 7029 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7030 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7031 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7032 kvm_update_cpuid(vcpu);
63f42e02
XG		 7033
7034 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7035 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7036 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7037 mmu_reset_needed = 1;
7038 }
63f42e02 7039 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7040
7041 if (mmu_reset_needed)
7042 kvm_mmu_reset_context(vcpu);
7043
a50abc3b 7044 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7045 pending_vec = find_first_bit(
7046 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7047 if (pending_vec < max_bits) {
66fd3f7f 7048 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7049 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7050 }
7051
3e6e0aab
GT		 7052 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7053 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7054 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7055 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7056 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7057 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7058
3e6e0aab
GT		 7059 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7060 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7061
5f0269f5
ME		 7062 update_cr8_intercept(vcpu);
7063
9c3e4aab 7064 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7065 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7066 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7067 !is_protmode(vcpu))
9c3e4aab
MT		 7068 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7069
3842d135
AK		 7070 kvm_make_request(KVM_REQ_EVENT, vcpu);
7071
b6c7a5dc
HB		 7072 return 0;
7073}
7074
d0bfb940
JK		 7075int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7076 struct kvm_guest_debug *dbg)
b6c7a5dc 7077{
355be0b9 7078 unsigned long rflags;
ae675ef0 7079 int i, r;
b6c7a5dc 7080
4f926bf2
JK		 7081 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7082 r = -EBUSY;
7083 if (vcpu->arch.exception.pending)
2122ff5e 7084 goto out;
4f926bf2
JK		 7085 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7086 kvm_queue_exception(vcpu, DB_VECTOR);
7087 else
7088 kvm_queue_exception(vcpu, BP_VECTOR);
7089 }
7090
91586a3b
JK		 7091 /*
7092 * Read rflags as long as potentially injected trace flags are still
7093 * filtered out.
7094 */
7095 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7096
7097 vcpu->guest_debug = dbg->control;
7098 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7099 vcpu->guest_debug = 0;
7100
7101 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7102 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7103 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7104 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7105 } else {
7106 for (i = 0; i < KVM_NR_DB_REGS; i++)
7107 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7108 }
c8639010 7109 kvm_update_dr7(vcpu);
ae675ef0 7110
f92653ee
JK		 7111 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7112 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7113 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7114
91586a3b
JK		 7115 /*
7116 * Trigger an rflags update that will inject or remove the trace
7117 * flags.
7118 */
7119 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7120
c8639010 7121 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7122
4f926bf2 7123 r = 0;
d0bfb940 7124
2122ff5e 7125out:
b6c7a5dc
HB		 7126
7127 return r;
7128}
7129
8b006791
ZX		 7130/*
7131 * Translate a guest virtual address to a guest physical address.
7132 */
7133int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7134 struct kvm_translation *tr)
7135{
7136 unsigned long vaddr = tr->linear_address;
7137 gpa_t gpa;
f656ce01 7138 int idx;
8b006791 7139
f656ce01 7140 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7141 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7142 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7143 tr->physical_address = gpa;
7144 tr->valid = gpa != UNMAPPED_GVA;
7145 tr->writeable = 1;
7146 tr->usermode = 0;
8b006791
ZX		 7147
7148 return 0;
7149}
7150
d0752060
HB		 7151int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7152{
98918833
SY		 7153 struct i387_fxsave_struct *fxsave =
7154 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7155
d0752060
HB		 7156 memcpy(fpu->fpr, fxsave->st_space, 128);
7157 fpu->fcw = fxsave->cwd;
7158 fpu->fsw = fxsave->swd;
7159 fpu->ftwx = fxsave->twd;
7160 fpu->last_opcode = fxsave->fop;
7161 fpu->last_ip = fxsave->rip;
7162 fpu->last_dp = fxsave->rdp;
7163 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7164
d0752060
HB		 7165 return 0;
7166}
7167
7168int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7169{
98918833
SY		 7170 struct i387_fxsave_struct *fxsave =
7171 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7172
d0752060
HB		 7173 memcpy(fxsave->st_space, fpu->fpr, 128);
7174 fxsave->cwd = fpu->fcw;
7175 fxsave->swd = fpu->fsw;
7176 fxsave->twd = fpu->ftwx;
7177 fxsave->fop = fpu->last_opcode;
7178 fxsave->rip = fpu->last_ip;
7179 fxsave->rdp = fpu->last_dp;
7180 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7181
d0752060
HB		 7182 return 0;
7183}
7184
d28bc9dd 7185int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7186{
10ab25cd
JK		 7187 int err;
7188
7189 err = fpu_alloc(&vcpu->arch.guest_fpu);
7190 if (err)
7191 return err;
7192
d28bc9dd
NA		 7193 if (!init_event)
7194 fpu_finit(&vcpu->arch.guest_fpu);
7195
df1daba7
PB		 7196 if (cpu_has_xsaves)
7197 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7198 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7199
2acf923e
DC		 7200 /*
7201 * Ensure guest xcr0 is valid for loading
7202 */
7203 vcpu->arch.xcr0 = XSTATE_FP;
7204
ad312c7c 7205 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7206
7207 return 0;
d0752060
HB		 7208}
7209EXPORT_SYMBOL_GPL(fx_init);
7210
98918833
SY		 7211static void fx_free(struct kvm_vcpu *vcpu)
7212{
7213 fpu_free(&vcpu->arch.guest_fpu);
7214}
7215
d0752060
HB		 7216void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7217{
2608d7a1 7218 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7219 return;
7220
2acf923e
DC		 7221 /*
7222 * Restore all possible states in the guest,
7223 * and assume host would use all available bits.
7224 * Guest xcr0 would be loaded later.
7225 */
7226 kvm_put_guest_xcr0(vcpu);
d0752060 7227 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7228 __kernel_fpu_begin();
98918833 7229 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7230 trace_kvm_fpu(1);
d0752060 7231}
d0752060
HB		 7232
7233void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7234{
2acf923e
DC		 7235 kvm_put_guest_xcr0(vcpu);
7236
653f52c3
RR		 7237 if (!vcpu->guest_fpu_loaded) {
7238 vcpu->fpu_counter = 0;
d0752060 7239 return;
653f52c3 7240 }
d0752060
HB		 7241
7242 vcpu->guest_fpu_loaded = 0;
98918833 7243 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7244 __kernel_fpu_end();
f096ed85 7245 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7246 /*
7247 * If using eager FPU mode, or if the guest is a frequent user
7248 * of the FPU, just leave the FPU active for next time.
7249 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7250 * the FPU in bursts will revert to loading it on demand.
7251 */
a9b4fb7e 7252 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7253 if (++vcpu->fpu_counter < 5)
7254 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7255 }
0c04851c 7256 trace_kvm_fpu(0);
d0752060 7257}
e9b11c17
ZX		 7258
7259void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7260{
12f9a48f 7261 kvmclock_reset(vcpu);
7f1ea208 7262
f5f48ee1 7263 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7264 fx_free(vcpu);
e9b11c17
ZX		 7265 kvm_x86_ops->vcpu_free(vcpu);
7266}
7267
7268struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7269 unsigned int id)
7270{
c447e76b
LL		 7271 struct kvm_vcpu *vcpu;
7272
6755bae8
ZA		 7273 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7274 printk_once(KERN_WARNING
7275 "kvm: SMP vm created on host with unstable TSC; "
7276 "guest TSC will not be reliable\n");
c447e76b
LL		 7277
7278 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7279
7280 /*
7281 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7282 * deactivated soon if it doesn't.
7283 */
7284 kvm_x86_ops->fpu_activate(vcpu);
7285 return vcpu;
26e5215f 7286}
e9b11c17 7287
26e5215f
AK		 7288int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7289{
7290 int r;
e9b11c17 7291
0bed3b56 7292 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7293 r = vcpu_load(vcpu);
7294 if (r)
7295 return r;
d28bc9dd 7296 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7297 kvm_mmu_setup(vcpu);
e9b11c17 7298 vcpu_put(vcpu);
e9b11c17 7299
26e5215f 7300 return r;
e9b11c17
ZX		 7301}
7302
31928aa5 7303void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7304{
8fe8ab46 7305 struct msr_data msr;
332967a3 7306 struct kvm *kvm = vcpu->kvm;
42897d86 7307
31928aa5
DD		 7308 if (vcpu_load(vcpu))
7309 return;
8fe8ab46
WA		 7310 msr.data = 0x0;
7311 msr.index = MSR_IA32_TSC;
7312 msr.host_initiated = true;
7313 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7314 vcpu_put(vcpu);
7315
630994b3
MT		 7316 if (!kvmclock_periodic_sync)
7317 return;
7318
332967a3
AJ		 7319 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7320 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7321}
7322
d40ccc62 7323void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7324{
9fc77441 7325 int r;
344d9588
GN		 7326 vcpu->arch.apf.msr_val = 0;
7327
9fc77441
MT		 7328 r = vcpu_load(vcpu);
7329 BUG_ON(r);
e9b11c17
ZX		 7330 kvm_mmu_unload(vcpu);
7331 vcpu_put(vcpu);
7332
98918833 7333 fx_free(vcpu);
e9b11c17
ZX		 7334 kvm_x86_ops->vcpu_free(vcpu);
7335}
7336
d28bc9dd 7337void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7338{
e69fab5d
PB		 7339 vcpu->arch.hflags = 0;
7340
7460fb4a
AK		 7341 atomic_set(&vcpu->arch.nmi_queued, 0);
7342 vcpu->arch.nmi_pending = 0;
448fa4a9 7343 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7344 kvm_clear_interrupt_queue(vcpu);
7345 kvm_clear_exception_queue(vcpu);
448fa4a9 7346
42dbaa5a 7347 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7348 kvm_update_dr0123(vcpu);
6f43ed01 7349 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7350 kvm_update_dr6(vcpu);
42dbaa5a 7351 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7352 kvm_update_dr7(vcpu);
42dbaa5a 7353
1119022c
NA		 7354 vcpu->arch.cr2 = 0;
7355
3842d135 7356 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7357 vcpu->arch.apf.msr_val = 0;
c9aaa895 7358 vcpu->arch.st.msr_val = 0;
3842d135 7359
12f9a48f
GC		 7360 kvmclock_reset(vcpu);
7361
af585b92
GN		 7362 kvm_clear_async_pf_completion_queue(vcpu);
7363 kvm_async_pf_hash_reset(vcpu);
7364 vcpu->arch.apf.halted = false;
3842d135 7365
d28bc9dd
NA		 7366 if (!init_event)
7367 kvm_pmu_reset(vcpu);
f5132b01 7368
66f7b72e
JS		 7369 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7370 vcpu->arch.regs_avail = ~0;
7371 vcpu->arch.regs_dirty = ~0;
7372
d28bc9dd 7373 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7374}
7375
2b4a273b 7376void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7377{
7378 struct kvm_segment cs;
7379
7380 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7381 cs.selector = vector << 8;
7382 cs.base = vector << 12;
7383 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7384 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7385}
7386
13a34e06 7387int kvm_arch_hardware_enable(void)
e9b11c17 7388{
ca84d1a2
ZA		 7389 struct kvm *kvm;
7390 struct kvm_vcpu *vcpu;
7391 int i;
0dd6a6ed
ZA		 7392 int ret;
7393 u64 local_tsc;
7394 u64 max_tsc = 0;
7395 bool stable, backwards_tsc = false;
18863bdd
AK		 7396
7397 kvm_shared_msr_cpu_online();
13a34e06 7398 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7399 if (ret != 0)
7400 return ret;
7401
7402 local_tsc = native_read_tsc();
7403 stable = !check_tsc_unstable();
7404 list_for_each_entry(kvm, &vm_list, vm_list) {
7405 kvm_for_each_vcpu(i, vcpu, kvm) {
7406 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7407 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7408 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7409 backwards_tsc = true;
7410 if (vcpu->arch.last_host_tsc > max_tsc)
7411 max_tsc = vcpu->arch.last_host_tsc;
7412 }
7413 }
7414 }
7415
7416 /*
7417 * Sometimes, even reliable TSCs go backwards. This happens on
7418 * platforms that reset TSC during suspend or hibernate actions, but
7419 * maintain synchronization. We must compensate. Fortunately, we can
7420 * detect that condition here, which happens early in CPU bringup,
7421 * before any KVM threads can be running. Unfortunately, we can't
7422 * bring the TSCs fully up to date with real time, as we aren't yet far
7423 * enough into CPU bringup that we know how much real time has actually
7424 * elapsed; our helper function, get_kernel_ns() will be using boot
7425 * variables that haven't been updated yet.
7426 *
7427 * So we simply find the maximum observed TSC above, then record the
7428 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7429 * the adjustment will be applied. Note that we accumulate
7430 * adjustments, in case multiple suspend cycles happen before some VCPU
7431 * gets a chance to run again. In the event that no KVM threads get a
7432 * chance to run, we will miss the entire elapsed period, as we'll have
7433 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7434 * loose cycle time. This isn't too big a deal, since the loss will be
7435 * uniform across all VCPUs (not to mention the scenario is extremely
7436 * unlikely). It is possible that a second hibernate recovery happens
7437 * much faster than a first, causing the observed TSC here to be
7438 * smaller; this would require additional padding adjustment, which is
7439 * why we set last_host_tsc to the local tsc observed here.
7440 *
7441 * N.B. - this code below runs only on platforms with reliable TSC,
7442 * as that is the only way backwards_tsc is set above. Also note
7443 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7444 * have the same delta_cyc adjustment applied if backwards_tsc
7445 * is detected. Note further, this adjustment is only done once,
7446 * as we reset last_host_tsc on all VCPUs to stop this from being
7447 * called multiple times (one for each physical CPU bringup).
7448 *
4a969980 7449 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7450 * will be compensated by the logic in vcpu_load, which sets the TSC to
7451 * catchup mode. This will catchup all VCPUs to real time, but cannot
7452 * guarantee that they stay in perfect synchronization.
7453 */
7454 if (backwards_tsc) {
7455 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7456 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7457 list_for_each_entry(kvm, &vm_list, vm_list) {
7458 kvm_for_each_vcpu(i, vcpu, kvm) {
7459 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7460 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7461 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7462 }
7463
7464 /*
7465 * We have to disable TSC offset matching.. if you were
7466 * booting a VM while issuing an S4 host suspend....
7467 * you may have some problem. Solving this issue is
7468 * left as an exercise to the reader.
7469 */
7470 kvm->arch.last_tsc_nsec = 0;
7471 kvm->arch.last_tsc_write = 0;
7472 }
7473
7474 }
7475 return 0;
e9b11c17
ZX		 7476}
7477
13a34e06 7478void kvm_arch_hardware_disable(void)
e9b11c17 7479{
13a34e06
RK		 7480 kvm_x86_ops->hardware_disable();
7481 drop_user_return_notifiers();
e9b11c17
ZX		 7482}
7483
7484int kvm_arch_hardware_setup(void)
7485{
9e9c3fe4
NA		 7486 int r;
7487
7488 r = kvm_x86_ops->hardware_setup();
7489 if (r != 0)
7490 return r;
7491
7492 kvm_init_msr_list();
7493 return 0;
e9b11c17
ZX		 7494}
7495
7496void kvm_arch_hardware_unsetup(void)
7497{
7498 kvm_x86_ops->hardware_unsetup();
7499}
7500
7501void kvm_arch_check_processor_compat(void *rtn)
7502{
7503 kvm_x86_ops->check_processor_compatibility(rtn);
7504}
7505
3e515705
AK		 7506bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7507{
7508 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7509}
7510
54e9818f
GN		 7511struct static_key kvm_no_apic_vcpu __read_mostly;
7512
e9b11c17
ZX		 7513int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7514{
7515 struct page *page;
7516 struct kvm *kvm;
7517 int r;
7518
7519 BUG_ON(vcpu->kvm == NULL);
7520 kvm = vcpu->kvm;
7521
6aef266c 7522 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7523 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7524 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7525 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7526 else
a4535290 7527 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7528
7529 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7530 if (!page) {
7531 r = -ENOMEM;
7532 goto fail;
7533 }
ad312c7c 7534 vcpu->arch.pio_data = page_address(page);
e9b11c17 7535
cc578287 7536 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7537
e9b11c17
ZX		 7538 r = kvm_mmu_create(vcpu);
7539 if (r < 0)
7540 goto fail_free_pio_data;
7541
7542 if (irqchip_in_kernel(kvm)) {
7543 r = kvm_create_lapic(vcpu);
7544 if (r < 0)
7545 goto fail_mmu_destroy;
54e9818f
GN		 7546 } else
7547 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7548
890ca9ae
HY		 7549 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7550 GFP_KERNEL);
7551 if (!vcpu->arch.mce_banks) {
7552 r = -ENOMEM;
443c39bc 7553 goto fail_free_lapic;
890ca9ae
HY		 7554 }
7555 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7556
f1797359
WY		 7557 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7558 r = -ENOMEM;
f5f48ee1 7559 goto fail_free_mce_banks;
f1797359 7560 }
f5f48ee1 7561
d28bc9dd 7562 r = fx_init(vcpu, false);
66f7b72e
JS		 7563 if (r)
7564 goto fail_free_wbinvd_dirty_mask;
7565
ba904635 7566 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7567 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7568
7569 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7570 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7571
5a4f55cd
EK		 7572 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7573
74545705
RK		 7574 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7575
af585b92 7576 kvm_async_pf_hash_reset(vcpu);
f5132b01 7577 kvm_pmu_init(vcpu);
af585b92 7578
e9b11c17 7579 return 0;
66f7b72e
JS		 7580fail_free_wbinvd_dirty_mask:
7581 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7582fail_free_mce_banks:
7583 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7584fail_free_lapic:
7585 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7586fail_mmu_destroy:
7587 kvm_mmu_destroy(vcpu);
7588fail_free_pio_data:
ad312c7c 7589 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7590fail:
7591 return r;
7592}
7593
7594void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7595{
f656ce01
MT		 7596 int idx;
7597
f5132b01 7598 kvm_pmu_destroy(vcpu);
36cb93fd 7599 kfree(vcpu->arch.mce_banks);
e9b11c17 7600 kvm_free_lapic(vcpu);
f656ce01 7601 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7602 kvm_mmu_destroy(vcpu);
f656ce01 7603 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7604 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7605 if (!irqchip_in_kernel(vcpu->kvm))
7606 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7607}
d19a9cd2 7608
e790d9ef
RK		 7609void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7610{
ae97a3b8 7611 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7612}
7613
e08b9637 7614int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7615{
e08b9637
CO		 7616 if (type)
7617 return -EINVAL;
7618
6ef768fa 7619 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7620 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7621 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7622 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7623 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7624
5550af4d
SY		 7625 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7626 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7627 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7628 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7629 &kvm->arch.irq_sources_bitmap);
5550af4d 7630
038f8c11 7631 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7632 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7633 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7634
7635 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7636
7e44e449 7637 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7638 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7639
d89f5eff 7640 return 0;
d19a9cd2
ZX		 7641}
7642
7643static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7644{
9fc77441
MT		 7645 int r;
7646 r = vcpu_load(vcpu);
7647 BUG_ON(r);
d19a9cd2
ZX		 7648 kvm_mmu_unload(vcpu);
7649 vcpu_put(vcpu);
7650}
7651
7652static void kvm_free_vcpus(struct kvm *kvm)
7653{
7654 unsigned int i;
988a2cae 7655 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7656
7657 /*
7658 * Unpin any mmu pages first.
7659 */
af585b92
GN		 7660 kvm_for_each_vcpu(i, vcpu, kvm) {
7661 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7662 kvm_unload_vcpu_mmu(vcpu);
af585b92 7663 }
988a2cae
GN		 7664 kvm_for_each_vcpu(i, vcpu, kvm)
7665 kvm_arch_vcpu_free(vcpu);
7666
7667 mutex_lock(&kvm->lock);
7668 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7669 kvm->vcpus[i] = NULL;
d19a9cd2 7670
988a2cae
GN		 7671 atomic_set(&kvm->online_vcpus, 0);
7672 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7673}
7674
ad8ba2cd
SY		 7675void kvm_arch_sync_events(struct kvm *kvm)
7676{
332967a3 7677 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7678 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7679 kvm_free_all_assigned_devices(kvm);
aea924f6 7680 kvm_free_pit(kvm);
ad8ba2cd
SY		 7681}
7682
d19a9cd2
ZX		 7683void kvm_arch_destroy_vm(struct kvm *kvm)
7684{
27469d29
AH		 7685 if (current->mm == kvm->mm) {
7686 /*
7687 * Free memory regions allocated on behalf of userspace,
7688 * unless the the memory map has changed due to process exit
7689 * or fd copying.
7690 */
7691 struct kvm_userspace_memory_region mem;
7692 memset(&mem, 0, sizeof(mem));
7693 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7694 kvm_set_memory_region(kvm, &mem);
7695
7696 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7697 kvm_set_memory_region(kvm, &mem);
7698
7699 mem.slot = TSS_PRIVATE_MEMSLOT;
7700 kvm_set_memory_region(kvm, &mem);
7701 }
6eb55818 7702 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7703 kfree(kvm->arch.vpic);
7704 kfree(kvm->arch.vioapic);
d19a9cd2 7705 kvm_free_vcpus(kvm);
1e08ec4a 7706 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7707}
0de10343 7708
5587027c 7709void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7710 struct kvm_memory_slot *dont)
7711{
7712 int i;
7713
d89cc617
TY		 7714 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7715 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7716 kvfree(free->arch.rmap[i]);
d89cc617 7717 free->arch.rmap[i] = NULL;
77d11309 7718 }
d89cc617
TY		 7719 if (i == 0)
7720 continue;
7721
7722 if (!dont || free->arch.lpage_info[i - 1] !=
7723 dont->arch.lpage_info[i - 1]) {
548ef284 7724 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7725 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7726 }
7727 }
7728}
7729
5587027c
AK		 7730int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7731 unsigned long npages)
db3fe4eb
TY		 7732{
7733 int i;
7734
d89cc617 7735 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7736 unsigned long ugfn;
7737 int lpages;
d89cc617 7738 int level = i + 1;
db3fe4eb
TY		 7739
7740 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7741 slot->base_gfn, level) + 1;
7742
d89cc617
TY		 7743 slot->arch.rmap[i] =
7744 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7745 if (!slot->arch.rmap[i])
77d11309 7746 goto out_free;
d89cc617
TY		 7747 if (i == 0)
7748 continue;
77d11309 7749
d89cc617
TY		 7750 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7751 sizeof(*slot->arch.lpage_info[i - 1]));
7752 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7753 goto out_free;
7754
7755 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7756 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7757 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7758 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7759 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7760 /*
7761 * If the gfn and userspace address are not aligned wrt each
7762 * other, or if explicitly asked to, disable large page
7763 * support for this slot
7764 */
7765 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7766 !kvm_largepages_enabled()) {
7767 unsigned long j;
7768
7769 for (j = 0; j < lpages; ++j)
d89cc617 7770 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7771 }
7772 }
7773
7774 return 0;
7775
7776out_free:
d89cc617 7777 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7778 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7779 slot->arch.rmap[i] = NULL;
7780 if (i == 0)
7781 continue;
7782
548ef284 7783 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7784 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7785 }
7786 return -ENOMEM;
7787}
7788
15f46015 7789void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7790{
e6dff7d1
TY		 7791 /*
7792 * memslots->generation has been incremented.
7793 * mmio generation may have reached its maximum value.
7794 */
7795 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7796}
7797
f7784b8e
MT		 7798int kvm_arch_prepare_memory_region(struct kvm *kvm,
7799 struct kvm_memory_slot *memslot,
09170a49 7800 const struct kvm_userspace_memory_region *mem,
7b6195a9 7801 enum kvm_mr_change change)
0de10343 7802{
7a905b14
TY		 7803 /*
7804 * Only private memory slots need to be mapped here since
7805 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7806 */
7b6195a9 7807 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7808 unsigned long userspace_addr;
604b38ac 7809
7a905b14
TY		 7810 /*
7811 * MAP_SHARED to prevent internal slot pages from being moved
7812 * by fork()/COW.
7813 */
7b6195a9 7814 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7815 PROT_READ | PROT_WRITE,
7816 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7817
7a905b14
TY		 7818 if (IS_ERR((void *)userspace_addr))
7819 return PTR_ERR((void *)userspace_addr);
604b38ac 7820
7a905b14 7821 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7822 }
7823
f7784b8e
MT		 7824 return 0;
7825}
7826
88178fd4
KH		 7827static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7828 struct kvm_memory_slot *new)
7829{
7830 /* Still write protect RO slot */
7831 if (new->flags & KVM_MEM_READONLY) {
7832 kvm_mmu_slot_remove_write_access(kvm, new);
7833 return;
7834 }
7835
7836 /*
7837 * Call kvm_x86_ops dirty logging hooks when they are valid.
7838 *
7839 * kvm_x86_ops->slot_disable_log_dirty is called when:
7840 *
7841 * - KVM_MR_CREATE with dirty logging is disabled
7842 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7843 *
7844 * The reason is, in case of PML, we need to set D-bit for any slots
7845 * with dirty logging disabled in order to eliminate unnecessary GPA
7846 * logging in PML buffer (and potential PML buffer full VMEXT). This
7847 * guarantees leaving PML enabled during guest's lifetime won't have
7848 * any additonal overhead from PML when guest is running with dirty
7849 * logging disabled for memory slots.
7850 *
7851 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7852 * to dirty logging mode.
7853 *
7854 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7855 *
7856 * In case of write protect:
7857 *
7858 * Write protect all pages for dirty logging.
7859 *
7860 * All the sptes including the large sptes which point to this
7861 * slot are set to readonly. We can not create any new large
7862 * spte on this slot until the end of the logging.
7863 *
7864 * See the comments in fast_page_fault().
7865 */
7866 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7867 if (kvm_x86_ops->slot_enable_log_dirty)
7868 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7869 else
7870 kvm_mmu_slot_remove_write_access(kvm, new);
7871 } else {
7872 if (kvm_x86_ops->slot_disable_log_dirty)
7873 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7874 }
7875}
7876
f7784b8e 7877void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7878 const struct kvm_userspace_memory_region *mem,
8482644a 7879 const struct kvm_memory_slot *old,
f36f3f28 7880 const struct kvm_memory_slot *new,
8482644a 7881 enum kvm_mr_change change)
f7784b8e 7882{
8482644a 7883 int nr_mmu_pages = 0;
f7784b8e 7884
f36f3f28 7885 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7886 int ret;
7887
8482644a
TY		 7888 ret = vm_munmap(old->userspace_addr,
7889 old->npages * PAGE_SIZE);
f7784b8e
MT		 7890 if (ret < 0)
7891 printk(KERN_WARNING
7892 "kvm_vm_ioctl_set_memory_region: "
7893 "failed to munmap memory\n");
7894 }
7895
48c0e4e9
XG		 7896 if (!kvm->arch.n_requested_mmu_pages)
7897 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7898
48c0e4e9 7899 if (nr_mmu_pages)
0de10343 7900 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7901
3ea3b7fa
WL		 7902 /*
7903 * Dirty logging tracks sptes in 4k granularity, meaning that large
7904 * sptes have to be split. If live migration is successful, the guest
7905 * in the source machine will be destroyed and large sptes will be
7906 * created in the destination. However, if the guest continues to run
7907 * in the source machine (for example if live migration fails), small
7908 * sptes will remain around and cause bad performance.
7909 *
7910 * Scan sptes if dirty logging has been stopped, dropping those
7911 * which can be collapsed into a single large-page spte. Later
7912 * page faults will create the large-page sptes.
7913 */
7914 if ((change != KVM_MR_DELETE) &&
7915 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7916 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7917 kvm_mmu_zap_collapsible_sptes(kvm, new);
7918
c972f3b1 7919 /*
88178fd4 7920 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7921 *
88178fd4
KH		 7922 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7923 * been zapped so no dirty logging staff is needed for old slot. For
7924 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7925 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7926 *
7927 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7928 */
88178fd4 7929 if (change != KVM_MR_DELETE)
f36f3f28 7930 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7931}
1d737c8a 7932
2df72e9b 7933void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7934{
6ca18b69 7935 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7936}
7937
2df72e9b
MT		 7938void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7939 struct kvm_memory_slot *slot)
7940{
6ca18b69 7941 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7942}
7943
1d737c8a
ZX		 7944int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7945{
b6b8a145
JK		 7946 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7947 kvm_x86_ops->check_nested_events(vcpu, false);
7948
af585b92
GN		 7949 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7950 !vcpu->arch.apf.halted)
7951 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7952 || kvm_apic_has_events(vcpu)
6aef266c 7953 || vcpu->arch.pv.pv_unhalted
7460fb4a 7954 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7955 (kvm_arch_interrupt_allowed(vcpu) &&
7956 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7957}
5736199a 7958
b6d33834 7959int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7960{
b6d33834 7961 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7962}
78646121
GN		 7963
7964int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7965{
7966 return kvm_x86_ops->interrupt_allowed(vcpu);
7967}
229456fc 7968
82b32774 7969unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7970{
82b32774
NA		 7971 if (is_64_bit_mode(vcpu))
7972 return kvm_rip_read(vcpu);
7973 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7974 kvm_rip_read(vcpu));
7975}
7976EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7977
82b32774
NA		 7978bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7979{
7980 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7981}
7982EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7983
94fe45da
JK		 7984unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7985{
7986 unsigned long rflags;
7987
7988 rflags = kvm_x86_ops->get_rflags(vcpu);
7989 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7990 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7991 return rflags;
7992}
7993EXPORT_SYMBOL_GPL(kvm_get_rflags);
7994
6addfc42 7995static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7996{
7997 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7998 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7999 rflags |= X86_EFLAGS_TF;
94fe45da 8000 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8001}
8002
8003void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8004{
8005 __kvm_set_rflags(vcpu, rflags);
3842d135 8006 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8007}
8008EXPORT_SYMBOL_GPL(kvm_set_rflags);
8009
56028d08
GN		 8010void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8011{
8012 int r;
8013
fb67e14f 8014 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8015 work->wakeup_all)
56028d08
GN		 8016 return;
8017
8018 r = kvm_mmu_reload(vcpu);
8019 if (unlikely(r))
8020 return;
8021
fb67e14f
XG		 8022 if (!vcpu->arch.mmu.direct_map &&
8023 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8024 return;
8025
56028d08
GN		 8026 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8027}
8028
af585b92
GN		 8029static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8030{
8031 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8032}
8033
8034static inline u32 kvm_async_pf_next_probe(u32 key)
8035{
8036 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8037}
8038
8039static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8040{
8041 u32 key = kvm_async_pf_hash_fn(gfn);
8042
8043 while (vcpu->arch.apf.gfns[key] != ~0)
8044 key = kvm_async_pf_next_probe(key);
8045
8046 vcpu->arch.apf.gfns[key] = gfn;
8047}
8048
8049static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8050{
8051 int i;
8052 u32 key = kvm_async_pf_hash_fn(gfn);
8053
8054 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8055 (vcpu->arch.apf.gfns[key] != gfn &&
8056 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8057 key = kvm_async_pf_next_probe(key);
8058
8059 return key;
8060}
8061
8062bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8063{
8064 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8065}
8066
8067static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8068{
8069 u32 i, j, k;
8070
8071 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8072 while (true) {
8073 vcpu->arch.apf.gfns[i] = ~0;
8074 do {
8075 j = kvm_async_pf_next_probe(j);
8076 if (vcpu->arch.apf.gfns[j] == ~0)
8077 return;
8078 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8079 /*
8080 * k lies cyclically in ]i,j]
8081 * | i.k.j |
8082 * |....j i.k.| or |.k..j i...|
8083 */
8084 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8085 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8086 i = j;
8087 }
8088}
8089
7c90705b
GN		 8090static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8091{
8092
8093 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8094 sizeof(val));
8095}
8096
af585b92
GN		 8097void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8098 struct kvm_async_pf *work)
8099{
6389ee94
AK		 8100 struct x86_exception fault;
8101
7c90705b 8102 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8103 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8104
8105 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8106 (vcpu->arch.apf.send_user_only &&
8107 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8108 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8109 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8110 fault.vector = PF_VECTOR;
8111 fault.error_code_valid = true;
8112 fault.error_code = 0;
8113 fault.nested_page_fault = false;
8114 fault.address = work->arch.token;
8115 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8116 }
af585b92
GN		 8117}
8118
8119void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8120 struct kvm_async_pf *work)
8121{
6389ee94
AK		 8122 struct x86_exception fault;
8123
7c90705b 8124 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8125 if (work->wakeup_all)
7c90705b
GN		 8126 work->arch.token = ~0; /* broadcast wakeup */
8127 else
8128 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8129
8130 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8131 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8132 fault.vector = PF_VECTOR;
8133 fault.error_code_valid = true;
8134 fault.error_code = 0;
8135 fault.nested_page_fault = false;
8136 fault.address = work->arch.token;
8137 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8138 }
e6d53e3b 8139 vcpu->arch.apf.halted = false;
a4fa1635 8140 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8141}
8142
8143bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8144{
8145 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8146 return true;
8147 else
8148 return !kvm_event_needs_reinjection(vcpu) &&
8149 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8150}
8151
e0f0bbc5
AW		 8152void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8153{
8154 atomic_inc(&kvm->arch.noncoherent_dma_count);
8155}
8156EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8157
8158void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8159{
8160 atomic_dec(&kvm->arch.noncoherent_dma_count);
8161}
8162EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8163
8164bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8165{
8166 return atomic_read(&kvm->arch.noncoherent_dma_count);
8167}
8168EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8169
229456fc
MT		 8170EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8171EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8172EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8173EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8174EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8175EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8176EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8177EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8178EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8179EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8180EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8181EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8182EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8183EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8184EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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