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KVM: MMU: collapse TLB flushes when zap all pages
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
18863bdd 192 u64 value;
013f6a5d
MT		 193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 195
2bf78fa7
SY		 196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 226{
013f6a5d
MT		 227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 229
2bf78fa7 230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 231 return;
2bf78fa7
SY		 232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239}
240EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
3548bab5
AK		 242static void drop_user_return_notifiers(void *ignore)
243{
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
e3ba45b8
GL		 264asmlinkage void kvm_spurious_fault(void)
265{
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268}
269EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
3fd28fce
ED		 295{
296 u32 prev_nr;
297 int class1, class2;
298
3842d135
AK		 299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
3fd28fce
ED		 301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
3f0fd292 307 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
a8eeb04a 315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332}
333
298101da
AK		 334void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
ce7ddec4
JR		 340void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341{
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
db8fcefa 346void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 347{
db8fcefa
AP		 348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352}
353EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 354
6389ee94 355void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 356{
357 ++vcpu->stat.pf_guest;
6389ee94
AK		 358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 360}
27d6c865 361EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 362
6389ee94 363void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 364{
6389ee94
AK		 365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 367 else
6389ee94 368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 369}
370
3419ffc8
SY		 371void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372{
7460fb4a
AK		 373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 375}
376EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
298101da
AK		 378void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
ce7ddec4 380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 381}
382EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
ce7ddec4
JR		 384void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385{
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387}
388EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
0a79b009
AK		 390/*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 395{
0a79b009
AK		 396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
298101da 400}
0a79b009 401EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 402
ec92fe44
JR		 403/*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411{
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423}
424EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
3d06b8bf
JR		 426int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428{
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431}
432
a03490ed
CO		 433/*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
ff03a073 436int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 437{
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
ff03a073 442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 443
ff03a073
JR		 444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 452 if (is_present_gpte(pdpte[i]) &&
20c466b5 453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
ff03a073 460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 465out:
a03490ed
CO		 466
467 return ret;
468}
cc4b6871 469EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 470
d835dfec
AK		 471static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472{
ff03a073 473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 474 bool changed = true;
3d06b8bf
JR		 475 int offset;
476 gfn_t gfn;
d835dfec
AK		 477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
6de4f3ad
AK		 482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
9f8fe504
AK		 486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 490 if (r < 0)
491 goto out;
ff03a073 492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 493out:
d835dfec
AK		 494
495 return changed;
496}
497
49a9b07e 498int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 499{
aad82703
SY		 500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
f9a48e6a
AK		 504 cr0 |= X86_CR0_ET;
505
ab344828 506#ifdef CONFIG_X86_64
0f12244f
GN		 507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
ab344828
GN		 509#endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 512
0f12244f
GN		 513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
a03490ed
CO		 518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520#ifdef CONFIG_X86_64
f6801dff 521 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 522 int cs_db, cs_l;
523
0f12244f
GN		 524 if (!is_pae(vcpu))
525 return 1;
a03490ed 526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 527 if (cs_l)
528 return 1;
a03490ed
CO		 529 } else
530#endif
ff03a073 531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 532 kvm_read_cr3(vcpu)))
0f12244f 533 return 1;
a03490ed
CO		 534 }
535
ad756a16
MJ		 536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
a03490ed 539 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 540
d170c419 541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 542 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 543 kvm_async_pf_hash_reset(vcpu);
544 }
e5f3f027 545
aad82703
SY		 546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 548 return 0;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
49a9b07e 554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 555}
2d3ad1f4 556EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 557
42bdf991
MT		 558static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
559{
560 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
561 !vcpu->guest_xcr0_loaded) {
562 /* kvm_set_xcr() also depends on this */
563 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
564 vcpu->guest_xcr0_loaded = 1;
565 }
566}
567
568static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
569{
570 if (vcpu->guest_xcr0_loaded) {
571 if (vcpu->arch.xcr0 != host_xcr0)
572 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
573 vcpu->guest_xcr0_loaded = 0;
574 }
575}
576
2acf923e
DC		 577int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
578{
579 u64 xcr0;
580
581 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
582 if (index != XCR_XFEATURE_ENABLED_MASK)
583 return 1;
584 xcr0 = xcr;
585 if (kvm_x86_ops->get_cpl(vcpu) != 0)
586 return 1;
587 if (!(xcr0 & XSTATE_FP))
588 return 1;
589 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
590 return 1;
591 if (xcr0 & ~host_xcr0)
592 return 1;
42bdf991 593 kvm_put_guest_xcr0(vcpu);
2acf923e 594 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 595 return 0;
596}
597
598int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
599{
600 if (__kvm_set_xcr(vcpu, index, xcr)) {
601 kvm_inject_gp(vcpu, 0);
602 return 1;
603 }
604 return 0;
605}
606EXPORT_SYMBOL_GPL(kvm_set_xcr);
607
a83b29c6 608int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 609{
fc78f519 610 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 611 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
612 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 613 if (cr4 & CR4_RESERVED_BITS)
614 return 1;
a03490ed 615
2acf923e
DC		 616 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
617 return 1;
618
c68b734f
YW		 619 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
620 return 1;
621
74dc2b4f
YW		 622 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
623 return 1;
624
a03490ed 625 if (is_long_mode(vcpu)) {
0f12244f
GN		 626 if (!(cr4 & X86_CR4_PAE))
627 return 1;
a2edf57f
AK		 628 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
629 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 630 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
631 kvm_read_cr3(vcpu)))
0f12244f
GN		 632 return 1;
633
ad756a16
MJ		 634 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
635 if (!guest_cpuid_has_pcid(vcpu))
636 return 1;
637
638 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
639 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
640 return 1;
641 }
642
5e1746d6 643 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 644 return 1;
a03490ed 645
ad756a16
MJ		 646 if (((cr4 ^ old_cr4) & pdptr_bits) ||
647 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 648 kvm_mmu_reset_context(vcpu);
0f12244f 649
2acf923e 650 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 651 kvm_update_cpuid(vcpu);
2acf923e 652
0f12244f
GN		 653 return 0;
654}
2d3ad1f4 655EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 656
2390218b 657int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 658{
9f8fe504 659 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 660 kvm_mmu_sync_roots(vcpu);
d835dfec 661 kvm_mmu_flush_tlb(vcpu);
0f12244f 662 return 0;
d835dfec
AK		 663 }
664
a03490ed 665 if (is_long_mode(vcpu)) {
471842ec 666 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 667 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
668 return 1;
669 } else
670 if (cr3 & CR3_L_MODE_RESERVED_BITS)
671 return 1;
a03490ed
CO		 672 } else {
673 if (is_pae(vcpu)) {
0f12244f
GN		 674 if (cr3 & CR3_PAE_RESERVED_BITS)
675 return 1;
ff03a073
JR		 676 if (is_paging(vcpu) &&
677 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 678 return 1;
a03490ed
CO		 679 }
680 /*
681 * We don't check reserved bits in nonpae mode, because
682 * this isn't enforced, and VMware depends on this.
683 */
684 }
685
a03490ed
CO		 686 /*
687 * Does the new cr3 value map to physical memory? (Note, we
688 * catch an invalid cr3 even in real-mode, because it would
689 * cause trouble later on when we turn on paging anyway.)
690 *
691 * A real CPU would silently accept an invalid cr3 and would
692 * attempt to use it - with largely undefined (and often hard
693 * to debug) behavior on the guest side.
694 */
695 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 696 return 1;
697 vcpu->arch.cr3 = cr3;
aff48baa 698 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 699 vcpu->arch.mmu.new_cr3(vcpu);
700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 703
eea1cff9 704int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 705{
0f12244f
GN		 706 if (cr8 & CR8_RESERVED_BITS)
707 return 1;
a03490ed
CO		 708 if (irqchip_in_kernel(vcpu->kvm))
709 kvm_lapic_set_tpr(vcpu, cr8);
710 else
ad312c7c 711 vcpu->arch.cr8 = cr8;
0f12244f
GN		 712 return 0;
713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 715
2d3ad1f4 716unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 717{
718 if (irqchip_in_kernel(vcpu->kvm))
719 return kvm_lapic_get_cr8(vcpu);
720 else
ad312c7c 721 return vcpu->arch.cr8;
a03490ed 722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 724
c8639010
JK		 725static void kvm_update_dr7(struct kvm_vcpu *vcpu)
726{
727 unsigned long dr7;
728
729 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730 dr7 = vcpu->arch.guest_debug_dr7;
731 else
732 dr7 = vcpu->arch.dr7;
733 kvm_x86_ops->set_dr7(vcpu, dr7);
734 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
735}
736
338dbc97 737static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 738{
739 switch (dr) {
740 case 0 ... 3:
741 vcpu->arch.db[dr] = val;
742 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743 vcpu->arch.eff_db[dr] = val;
744 break;
745 case 4:
338dbc97
GN		 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747 return 1; /* #UD */
020df079
GN		 748 /* fall through */
749 case 6:
338dbc97
GN		 750 if (val & 0xffffffff00000000ULL)
751 return -1; /* #GP */
020df079
GN		 752 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
753 break;
754 case 5:
338dbc97
GN		 755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
756 return 1; /* #UD */
020df079
GN		 757 /* fall through */
758 default: /* 7 */
338dbc97
GN		 759 if (val & 0xffffffff00000000ULL)
760 return -1; /* #GP */
020df079 761 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 762 kvm_update_dr7(vcpu);
020df079
GN		 763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
770{
771 int res;
772
773 res = __kvm_set_dr(vcpu, dr, val);
774 if (res > 0)
775 kvm_queue_exception(vcpu, UD_VECTOR);
776 else if (res < 0)
777 kvm_inject_gp(vcpu, 0);
778
779 return res;
780}
020df079
GN		 781EXPORT_SYMBOL_GPL(kvm_set_dr);
782
338dbc97 783static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 784{
785 switch (dr) {
786 case 0 ... 3:
787 *val = vcpu->arch.db[dr];
788 break;
789 case 4:
338dbc97 790 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 791 return 1;
020df079
GN		 792 /* fall through */
793 case 6:
794 *val = vcpu->arch.dr6;
795 break;
796 case 5:
338dbc97 797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 798 return 1;
020df079
GN		 799 /* fall through */
800 default: /* 7 */
801 *val = vcpu->arch.dr7;
802 break;
803 }
804
805 return 0;
806}
338dbc97
GN		 807
808int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809{
810 if (_kvm_get_dr(vcpu, dr, val)) {
811 kvm_queue_exception(vcpu, UD_VECTOR);
812 return 1;
813 }
814 return 0;
815}
020df079
GN		 816EXPORT_SYMBOL_GPL(kvm_get_dr);
817
022cd0e8
AK		 818bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819{
820 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
821 u64 data;
822 int err;
823
824 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
825 if (err)
826 return err;
827 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
829 return err;
830}
831EXPORT_SYMBOL_GPL(kvm_rdpmc);
832
043405e1
CO		 833/*
834 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836 *
837 * This list is modified at module load time to reflect the
e3267cbb
GC		 838 * capabilities of the host cpu. This capabilities test skips MSRs that are
839 * kvm-specific. Those are put in the beginning of the list.
043405e1 840 */
e3267cbb 841
439793d4 842#define KVM_SAVE_MSRS_BEGIN 10
043405e1 843static u32 msrs_to_save[] = {
e3267cbb 844 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 845 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 846 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 847 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 848 MSR_KVM_PV_EOI_EN,
043405e1 849 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 850 MSR_STAR,
043405e1
CO		 851#ifdef CONFIG_X86_64
852 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
853#endif
e90aa41e 854 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 855};
856
857static unsigned num_msrs_to_save;
858
f1d24831 859static const u32 emulated_msrs[] = {
ba904635 860 MSR_IA32_TSC_ADJUST,
a3e06bbe 861 MSR_IA32_TSCDEADLINE,
043405e1 862 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 863 MSR_IA32_MCG_STATUS,
864 MSR_IA32_MCG_CTL,
043405e1
CO		 865};
866
384bb783 867bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 868{
b69e8cae 869 if (efer & efer_reserved_bits)
384bb783 870 return false;
15c4a640 871
1b2fd70c
AG		 872 if (efer & EFER_FFXSR) {
873 struct kvm_cpuid_entry2 *feat;
874
875 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 876 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 877 return false;
1b2fd70c
AG		 878 }
879
d8017474
AG		 880 if (efer & EFER_SVME) {
881 struct kvm_cpuid_entry2 *feat;
882
883 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 884 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 885 return false;
d8017474
AG		 886 }
887
384bb783
JK		 888 return true;
889}
890EXPORT_SYMBOL_GPL(kvm_valid_efer);
891
892static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
893{
894 u64 old_efer = vcpu->arch.efer;
895
896 if (!kvm_valid_efer(vcpu, efer))
897 return 1;
898
899 if (is_paging(vcpu)
900 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
901 return 1;
902
15c4a640 903 efer &= ~EFER_LMA;
f6801dff 904 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 905
a3d204e2
SY		 906 kvm_x86_ops->set_efer(vcpu, efer);
907
aad82703
SY		 908 /* Update reserved bits */
909 if ((efer ^ old_efer) & EFER_NX)
910 kvm_mmu_reset_context(vcpu);
911
b69e8cae 912 return 0;
15c4a640
CO		 913}
914
f2b4b7dd
JR		 915void kvm_enable_efer_bits(u64 mask)
916{
917 efer_reserved_bits &= ~mask;
918}
919EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
920
921
15c4a640
CO		 922/*
923 * Writes msr value into into the appropriate "register".
924 * Returns 0 on success, non-0 otherwise.
925 * Assumes vcpu_load() was already called.
926 */
8fe8ab46 927int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 928{
8fe8ab46 929 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 930}
931
313a3dc7
CO		 932/*
933 * Adapt set_msr() to msr_io()'s calling convention
934 */
935static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
936{
8fe8ab46
WA		 937 struct msr_data msr;
938
939 msr.data = *data;
940 msr.index = index;
941 msr.host_initiated = true;
942 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 943}
944
16e8d74d
MT		 945#ifdef CONFIG_X86_64
946struct pvclock_gtod_data {
947 seqcount_t seq;
948
949 struct { /* extract of a clocksource struct */
950 int vclock_mode;
951 cycle_t cycle_last;
952 cycle_t mask;
953 u32 mult;
954 u32 shift;
955 } clock;
956
957 /* open coded 'struct timespec' */
958 u64 monotonic_time_snsec;
959 time_t monotonic_time_sec;
960};
961
962static struct pvclock_gtod_data pvclock_gtod_data;
963
964static void update_pvclock_gtod(struct timekeeper *tk)
965{
966 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
967
968 write_seqcount_begin(&vdata->seq);
969
970 /* copy pvclock gtod data */
971 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
972 vdata->clock.cycle_last = tk->clock->cycle_last;
973 vdata->clock.mask = tk->clock->mask;
974 vdata->clock.mult = tk->mult;
975 vdata->clock.shift = tk->shift;
976
977 vdata->monotonic_time_sec = tk->xtime_sec
978 + tk->wall_to_monotonic.tv_sec;
979 vdata->monotonic_time_snsec = tk->xtime_nsec
980 + (tk->wall_to_monotonic.tv_nsec
981 << tk->shift);
982 while (vdata->monotonic_time_snsec >=
983 (((u64)NSEC_PER_SEC) << tk->shift)) {
984 vdata->monotonic_time_snsec -=
985 ((u64)NSEC_PER_SEC) << tk->shift;
986 vdata->monotonic_time_sec++;
987 }
988
989 write_seqcount_end(&vdata->seq);
990}
991#endif
992
993
18068523
GOC		 994static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
995{
9ed3c444
AK		 996 int version;
997 int r;
50d0a0f9 998 struct pvclock_wall_clock wc;
923de3cf 999 struct timespec boot;
18068523
GOC		 1000
1001 if (!wall_clock)
1002 return;
1003
9ed3c444
AK		 1004 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1005 if (r)
1006 return;
1007
1008 if (version & 1)
1009 ++version; /* first time write, random junk */
1010
1011 ++version;
18068523 1012
18068523
GOC		 1013 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1014
50d0a0f9
GH		 1015 /*
1016 * The guest calculates current wall clock time by adding
34c238a1 1017 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1018 * wall clock specified here. guest system time equals host
1019 * system time for us, thus we must fill in host boot time here.
1020 */
923de3cf 1021 getboottime(&boot);
50d0a0f9 1022
4b648665
BR		 1023 if (kvm->arch.kvmclock_offset) {
1024 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1025 boot = timespec_sub(boot, ts);
1026 }
50d0a0f9
GH		 1027 wc.sec = boot.tv_sec;
1028 wc.nsec = boot.tv_nsec;
1029 wc.version = version;
18068523
GOC		 1030
1031 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1032
1033 version++;
1034 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1035}
1036
50d0a0f9
GH		 1037static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1038{
1039 uint32_t quotient, remainder;
1040
1041 /* Don't try to replace with do_div(), this one calculates
1042 * "(dividend << 32) / divisor" */
1043 __asm__ ( "divl %4"
1044 : "=a" (quotient), "=d" (remainder)
1045 : "0" (0), "1" (dividend), "r" (divisor) );
1046 return quotient;
1047}
1048
5f4e3f88
ZA		 1049static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1050 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1051{
5f4e3f88 1052 uint64_t scaled64;
50d0a0f9
GH		 1053 int32_t shift = 0;
1054 uint64_t tps64;
1055 uint32_t tps32;
1056
5f4e3f88
ZA		 1057 tps64 = base_khz * 1000LL;
1058 scaled64 = scaled_khz * 1000LL;
50933623 1059 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1060 tps64 >>= 1;
1061 shift--;
1062 }
1063
1064 tps32 = (uint32_t)tps64;
50933623
JK		 1065 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1066 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1067 scaled64 >>= 1;
1068 else
1069 tps32 <<= 1;
50d0a0f9
GH		 1070 shift++;
1071 }
1072
5f4e3f88
ZA		 1073 *pshift = shift;
1074 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1075
5f4e3f88
ZA		 1076 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1077 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1078}
1079
759379dd
ZA		 1080static inline u64 get_kernel_ns(void)
1081{
1082 struct timespec ts;
1083
1084 WARN_ON(preemptible());
1085 ktime_get_ts(&ts);
1086 monotonic_to_bootbased(&ts);
1087 return timespec_to_ns(&ts);
50d0a0f9
GH		 1088}
1089
d828199e 1090#ifdef CONFIG_X86_64
16e8d74d 1091static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1092#endif
16e8d74d 1093
c8076604 1094static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1095unsigned long max_tsc_khz;
c8076604 1096
cc578287 1097static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1098{
cc578287
ZA		 1099 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1100 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1101}
1102
cc578287 1103static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1104{
cc578287
ZA		 1105 u64 v = (u64)khz * (1000000 + ppm);
1106 do_div(v, 1000000);
1107 return v;
1e993611
JR		 1108}
1109
cc578287 1110static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1111{
cc578287
ZA		 1112 u32 thresh_lo, thresh_hi;
1113 int use_scaling = 0;
217fc9cf 1114
03ba32ca
MT		 1115 /* tsc_khz can be zero if TSC calibration fails */
1116 if (this_tsc_khz == 0)
1117 return;
1118
c285545f
ZA		 1119 /* Compute a scale to convert nanoseconds in TSC cycles */
1120 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1121 &vcpu->arch.virtual_tsc_shift,
1122 &vcpu->arch.virtual_tsc_mult);
1123 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1124
1125 /*
1126 * Compute the variation in TSC rate which is acceptable
1127 * within the range of tolerance and decide if the
1128 * rate being applied is within that bounds of the hardware
1129 * rate. If so, no scaling or compensation need be done.
1130 */
1131 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1132 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1133 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1134 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1135 use_scaling = 1;
1136 }
1137 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1138}
1139
1140static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1141{
e26101b1 1142 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1143 vcpu->arch.virtual_tsc_mult,
1144 vcpu->arch.virtual_tsc_shift);
e26101b1 1145 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1146 return tsc;
1147}
1148
b48aa97e
MT		 1149void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1150{
1151#ifdef CONFIG_X86_64
1152 bool vcpus_matched;
1153 bool do_request = false;
1154 struct kvm_arch *ka = &vcpu->kvm->arch;
1155 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1156
1157 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1158 atomic_read(&vcpu->kvm->online_vcpus));
1159
1160 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1161 if (!ka->use_master_clock)
1162 do_request = 1;
1163
1164 if (!vcpus_matched && ka->use_master_clock)
1165 do_request = 1;
1166
1167 if (do_request)
1168 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1169
1170 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1171 atomic_read(&vcpu->kvm->online_vcpus),
1172 ka->use_master_clock, gtod->clock.vclock_mode);
1173#endif
1174}
1175
ba904635
WA		 1176static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1177{
1178 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1179 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1180}
1181
8fe8ab46 1182void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1183{
1184 struct kvm *kvm = vcpu->kvm;
f38e098f 1185 u64 offset, ns, elapsed;
99e3e30a 1186 unsigned long flags;
02626b6a 1187 s64 usdiff;
b48aa97e 1188 bool matched;
8fe8ab46 1189 u64 data = msr->data;
99e3e30a 1190
038f8c11 1191 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1192 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1193 ns = get_kernel_ns();
f38e098f 1194 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1195
03ba32ca
MT		 1196 if (vcpu->arch.virtual_tsc_khz) {
1197 /* n.b - signed multiplication and division required */
1198 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1199#ifdef CONFIG_X86_64
03ba32ca 1200 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1201#else
03ba32ca
MT		 1202 /* do_div() only does unsigned */
1203 asm("idivl %2; xor %%edx, %%edx"
1204 : "=A"(usdiff)
1205 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1206#endif
03ba32ca
MT		 1207 do_div(elapsed, 1000);
1208 usdiff -= elapsed;
1209 if (usdiff < 0)
1210 usdiff = -usdiff;
1211 } else
1212 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1213
1214 /*
5d3cb0f6
ZA		 1215 * Special case: TSC write with a small delta (1 second) of virtual
1216 * cycle time against real time is interpreted as an attempt to
1217 * synchronize the CPU.
1218 *
1219 * For a reliable TSC, we can match TSC offsets, and for an unstable
1220 * TSC, we add elapsed time in this computation. We could let the
1221 * compensation code attempt to catch up if we fall behind, but
1222 * it's better to try to match offsets from the beginning.
1223 */
02626b6a 1224 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1225 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1226 if (!check_tsc_unstable()) {
e26101b1 1227 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1228 pr_debug("kvm: matched tsc offset for %llu\n", data);
1229 } else {
857e4099 1230 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1231 data += delta;
1232 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1233 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1234 }
b48aa97e 1235 matched = true;
e26101b1
ZA		 1236 } else {
1237 /*
1238 * We split periods of matched TSC writes into generations.
1239 * For each generation, we track the original measured
1240 * nanosecond time, offset, and write, so if TSCs are in
1241 * sync, we can match exact offset, and if not, we can match
4a969980 1242 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1243 *
1244 * These values are tracked in kvm->arch.cur_xxx variables.
1245 */
1246 kvm->arch.cur_tsc_generation++;
1247 kvm->arch.cur_tsc_nsec = ns;
1248 kvm->arch.cur_tsc_write = data;
1249 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1250 matched = false;
e26101b1
ZA		 1251 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1252 kvm->arch.cur_tsc_generation, data);
f38e098f 1253 }
e26101b1
ZA		 1254
1255 /*
1256 * We also track th most recent recorded KHZ, write and time to
1257 * allow the matching interval to be extended at each write.
1258 */
f38e098f
ZA		 1259 kvm->arch.last_tsc_nsec = ns;
1260 kvm->arch.last_tsc_write = data;
5d3cb0f6 1261 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1262
1263 /* Reset of TSC must disable overshoot protection below */
1264 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1265 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1266
1267 /* Keep track of which generation this VCPU has synchronized to */
1268 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1269 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1270 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1271
ba904635
WA		 1272 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1273 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1274 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1275 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1276
1277 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1278 if (matched)
1279 kvm->arch.nr_vcpus_matched_tsc++;
1280 else
1281 kvm->arch.nr_vcpus_matched_tsc = 0;
1282
1283 kvm_track_tsc_matching(vcpu);
1284 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1285}
e26101b1 1286
99e3e30a
ZA		 1287EXPORT_SYMBOL_GPL(kvm_write_tsc);
1288
d828199e
MT		 1289#ifdef CONFIG_X86_64
1290
1291static cycle_t read_tsc(void)
1292{
1293 cycle_t ret;
1294 u64 last;
1295
1296 /*
1297 * Empirically, a fence (of type that depends on the CPU)
1298 * before rdtsc is enough to ensure that rdtsc is ordered
1299 * with respect to loads. The various CPU manuals are unclear
1300 * as to whether rdtsc can be reordered with later loads,
1301 * but no one has ever seen it happen.
1302 */
1303 rdtsc_barrier();
1304 ret = (cycle_t)vget_cycles();
1305
1306 last = pvclock_gtod_data.clock.cycle_last;
1307
1308 if (likely(ret >= last))
1309 return ret;
1310
1311 /*
1312 * GCC likes to generate cmov here, but this branch is extremely
1313 * predictable (it's just a funciton of time and the likely is
1314 * very likely) and there's a data dependence, so force GCC
1315 * to generate a branch instead. I don't barrier() because
1316 * we don't actually need a barrier, and if this function
1317 * ever gets inlined it will generate worse code.
1318 */
1319 asm volatile ("");
1320 return last;
1321}
1322
1323static inline u64 vgettsc(cycle_t *cycle_now)
1324{
1325 long v;
1326 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1327
1328 *cycle_now = read_tsc();
1329
1330 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1331 return v * gtod->clock.mult;
1332}
1333
1334static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1335{
1336 unsigned long seq;
1337 u64 ns;
1338 int mode;
1339 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1340
1341 ts->tv_nsec = 0;
1342 do {
1343 seq = read_seqcount_begin(&gtod->seq);
1344 mode = gtod->clock.vclock_mode;
1345 ts->tv_sec = gtod->monotonic_time_sec;
1346 ns = gtod->monotonic_time_snsec;
1347 ns += vgettsc(cycle_now);
1348 ns >>= gtod->clock.shift;
1349 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1350 timespec_add_ns(ts, ns);
1351
1352 return mode;
1353}
1354
1355/* returns true if host is using tsc clocksource */
1356static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1357{
1358 struct timespec ts;
1359
1360 /* checked again under seqlock below */
1361 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1362 return false;
1363
1364 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1365 return false;
1366
1367 monotonic_to_bootbased(&ts);
1368 *kernel_ns = timespec_to_ns(&ts);
1369
1370 return true;
1371}
1372#endif
1373
1374/*
1375 *
b48aa97e
MT		 1376 * Assuming a stable TSC across physical CPUS, and a stable TSC
1377 * across virtual CPUs, the following condition is possible.
1378 * Each numbered line represents an event visible to both
d828199e
MT		 1379 * CPUs at the next numbered event.
1380 *
1381 * "timespecX" represents host monotonic time. "tscX" represents
1382 * RDTSC value.
1383 *
1384 * VCPU0 on CPU0 | VCPU1 on CPU1
1385 *
1386 * 1. read timespec0,tsc0
1387 * 2. | timespec1 = timespec0 + N
1388 * | tsc1 = tsc0 + M
1389 * 3. transition to guest | transition to guest
1390 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1391 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1392 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1393 *
1394 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1395 *
1396 * - ret0 < ret1
1397 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1398 * ...
1399 * - 0 < N - M => M < N
1400 *
1401 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1402 * always the case (the difference between two distinct xtime instances
1403 * might be smaller then the difference between corresponding TSC reads,
1404 * when updating guest vcpus pvclock areas).
1405 *
1406 * To avoid that problem, do not allow visibility of distinct
1407 * system_timestamp/tsc_timestamp values simultaneously: use a master
1408 * copy of host monotonic time values. Update that master copy
1409 * in lockstep.
1410 *
b48aa97e 1411 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1412 *
1413 */
1414
1415static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1416{
1417#ifdef CONFIG_X86_64
1418 struct kvm_arch *ka = &kvm->arch;
1419 int vclock_mode;
b48aa97e
MT		 1420 bool host_tsc_clocksource, vcpus_matched;
1421
1422 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1423 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1424
1425 /*
1426 * If the host uses TSC clock, then passthrough TSC as stable
1427 * to the guest.
1428 */
b48aa97e 1429 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1430 &ka->master_kernel_ns,
1431 &ka->master_cycle_now);
1432
b48aa97e
MT		 1433 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1434
d828199e
MT		 1435 if (ka->use_master_clock)
1436 atomic_set(&kvm_guest_has_master_clock, 1);
1437
1438 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1439 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1440 vcpus_matched);
d828199e
MT		 1441#endif
1442}
1443
34c238a1 1444static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1445{
d828199e 1446 unsigned long flags, this_tsc_khz;
18068523 1447 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1448 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1449 s64 kernel_ns, max_kernel_ns;
d828199e 1450 u64 tsc_timestamp, host_tsc;
0b79459b 1451 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1452 u8 pvclock_flags;
d828199e
MT		 1453 bool use_master_clock;
1454
1455 kernel_ns = 0;
1456 host_tsc = 0;
18068523 1457
d828199e
MT		 1458 /*
1459 * If the host uses TSC clock, then passthrough TSC as stable
1460 * to the guest.
1461 */
1462 spin_lock(&ka->pvclock_gtod_sync_lock);
1463 use_master_clock = ka->use_master_clock;
1464 if (use_master_clock) {
1465 host_tsc = ka->master_cycle_now;
1466 kernel_ns = ka->master_kernel_ns;
1467 }
1468 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1469
1470 /* Keep irq disabled to prevent changes to the clock */
1471 local_irq_save(flags);
1472 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1473 if (unlikely(this_tsc_khz == 0)) {
1474 local_irq_restore(flags);
1475 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1476 return 1;
1477 }
d828199e
MT		 1478 if (!use_master_clock) {
1479 host_tsc = native_read_tsc();
1480 kernel_ns = get_kernel_ns();
1481 }
1482
1483 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1484
c285545f
ZA		 1485 /*
1486 * We may have to catch up the TSC to match elapsed wall clock
1487 * time for two reasons, even if kvmclock is used.
1488 * 1) CPU could have been running below the maximum TSC rate
1489 * 2) Broken TSC compensation resets the base at each VCPU
1490 * entry to avoid unknown leaps of TSC even when running
1491 * again on the same CPU. This may cause apparent elapsed
1492 * time to disappear, and the guest to stand still or run
1493 * very slowly.
1494 */
1495 if (vcpu->tsc_catchup) {
1496 u64 tsc = compute_guest_tsc(v, kernel_ns);
1497 if (tsc > tsc_timestamp) {
f1e2b260 1498 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1499 tsc_timestamp = tsc;
1500 }
50d0a0f9
GH		 1501 }
1502
18068523
GOC		 1503 local_irq_restore(flags);
1504
0b79459b 1505 if (!vcpu->pv_time_enabled)
c285545f 1506 return 0;
18068523 1507
1d5f066e
ZA		 1508 /*
1509 * Time as measured by the TSC may go backwards when resetting the base
1510 * tsc_timestamp. The reason for this is that the TSC resolution is
1511 * higher than the resolution of the other clock scales. Thus, many
1512 * possible measurments of the TSC correspond to one measurement of any
1513 * other clock, and so a spread of values is possible. This is not a
1514 * problem for the computation of the nanosecond clock; with TSC rates
1515 * around 1GHZ, there can only be a few cycles which correspond to one
1516 * nanosecond value, and any path through this code will inevitably
1517 * take longer than that. However, with the kernel_ns value itself,
1518 * the precision may be much lower, down to HZ granularity. If the
1519 * first sampling of TSC against kernel_ns ends in the low part of the
1520 * range, and the second in the high end of the range, we can get:
1521 *
1522 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1523 *
1524 * As the sampling errors potentially range in the thousands of cycles,
1525 * it is possible such a time value has already been observed by the
1526 * guest. To protect against this, we must compute the system time as
1527 * observed by the guest and ensure the new system time is greater.
1528 */
1529 max_kernel_ns = 0;
b183aa58 1530 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1531 max_kernel_ns = vcpu->last_guest_tsc -
1532 vcpu->hv_clock.tsc_timestamp;
1533 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1534 vcpu->hv_clock.tsc_to_system_mul,
1535 vcpu->hv_clock.tsc_shift);
1536 max_kernel_ns += vcpu->last_kernel_ns;
1537 }
afbcf7ab 1538
e48672fa 1539 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1540 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1541 &vcpu->hv_clock.tsc_shift,
1542 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1543 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1544 }
1545
d828199e
MT		 1546 /* with a master <monotonic time, tsc value> tuple,
1547 * pvclock clock reads always increase at the (scaled) rate
1548 * of guest TSC - no need to deal with sampling errors.
1549 */
1550 if (!use_master_clock) {
1551 if (max_kernel_ns > kernel_ns)
1552 kernel_ns = max_kernel_ns;
1553 }
8cfdc000 1554 /* With all the info we got, fill in the values */
1d5f066e 1555 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1556 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1557 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1558 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1559
18068523
GOC		 1560 /*
1561 * The interface expects us to write an even number signaling that the
1562 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1563 * state, we just increase by 2 at the end.
18068523 1564 */
50d0a0f9 1565 vcpu->hv_clock.version += 2;
18068523 1566
0b79459b
AH		 1567 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1568 &guest_hv_clock, sizeof(guest_hv_clock))))
1569 return 0;
78c0337a
MT		 1570
1571 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1572 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1573
1574 if (vcpu->pvclock_set_guest_stopped_request) {
1575 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1576 vcpu->pvclock_set_guest_stopped_request = false;
1577 }
1578
d828199e
MT		 1579 /* If the host uses TSC clocksource, then it is stable */
1580 if (use_master_clock)
1581 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1582
78c0337a
MT		 1583 vcpu->hv_clock.flags = pvclock_flags;
1584
0b79459b
AH		 1585 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1586 &vcpu->hv_clock,
1587 sizeof(vcpu->hv_clock));
8cfdc000 1588 return 0;
c8076604
GH		 1589}
1590
0061d53d
MT		 1591/*
1592 * kvmclock updates which are isolated to a given vcpu, such as
1593 * vcpu->cpu migration, should not allow system_timestamp from
1594 * the rest of the vcpus to remain static. Otherwise ntp frequency
1595 * correction applies to one vcpu's system_timestamp but not
1596 * the others.
1597 *
1598 * So in those cases, request a kvmclock update for all vcpus.
1599 * The worst case for a remote vcpu to update its kvmclock
1600 * is then bounded by maximum nohz sleep latency.
1601 */
1602
1603static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1604{
1605 int i;
1606 struct kvm *kvm = v->kvm;
1607 struct kvm_vcpu *vcpu;
1608
1609 kvm_for_each_vcpu(i, vcpu, kvm) {
1610 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1611 kvm_vcpu_kick(vcpu);
1612 }
1613}
1614
9ba075a6
AK		 1615static bool msr_mtrr_valid(unsigned msr)
1616{
1617 switch (msr) {
1618 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1619 case MSR_MTRRfix64K_00000:
1620 case MSR_MTRRfix16K_80000:
1621 case MSR_MTRRfix16K_A0000:
1622 case MSR_MTRRfix4K_C0000:
1623 case MSR_MTRRfix4K_C8000:
1624 case MSR_MTRRfix4K_D0000:
1625 case MSR_MTRRfix4K_D8000:
1626 case MSR_MTRRfix4K_E0000:
1627 case MSR_MTRRfix4K_E8000:
1628 case MSR_MTRRfix4K_F0000:
1629 case MSR_MTRRfix4K_F8000:
1630 case MSR_MTRRdefType:
1631 case MSR_IA32_CR_PAT:
1632 return true;
1633 case 0x2f8:
1634 return true;
1635 }
1636 return false;
1637}
1638
d6289b93
MT		 1639static bool valid_pat_type(unsigned t)
1640{
1641 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1642}
1643
1644static bool valid_mtrr_type(unsigned t)
1645{
1646 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1647}
1648
1649static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1650{
1651 int i;
1652
1653 if (!msr_mtrr_valid(msr))
1654 return false;
1655
1656 if (msr == MSR_IA32_CR_PAT) {
1657 for (i = 0; i < 8; i++)
1658 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1659 return false;
1660 return true;
1661 } else if (msr == MSR_MTRRdefType) {
1662 if (data & ~0xcff)
1663 return false;
1664 return valid_mtrr_type(data & 0xff);
1665 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1666 for (i = 0; i < 8 ; i++)
1667 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1668 return false;
1669 return true;
1670 }
1671
1672 /* variable MTRRs */
1673 return valid_mtrr_type(data & 0xff);
1674}
1675
9ba075a6
AK		 1676static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1677{
0bed3b56
SY		 1678 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1679
d6289b93 1680 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1681 return 1;
1682
0bed3b56
SY		 1683 if (msr == MSR_MTRRdefType) {
1684 vcpu->arch.mtrr_state.def_type = data;
1685 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1686 } else if (msr == MSR_MTRRfix64K_00000)
1687 p[0] = data;
1688 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1689 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1690 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1691 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1692 else if (msr == MSR_IA32_CR_PAT)
1693 vcpu->arch.pat = data;
1694 else { /* Variable MTRRs */
1695 int idx, is_mtrr_mask;
1696 u64 *pt;
1697
1698 idx = (msr - 0x200) / 2;
1699 is_mtrr_mask = msr - 0x200 - 2 * idx;
1700 if (!is_mtrr_mask)
1701 pt =
1702 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1703 else
1704 pt =
1705 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1706 *pt = data;
1707 }
1708
1709 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1710 return 0;
1711}
15c4a640 1712
890ca9ae 1713static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1714{
890ca9ae
HY		 1715 u64 mcg_cap = vcpu->arch.mcg_cap;
1716 unsigned bank_num = mcg_cap & 0xff;
1717
15c4a640 1718 switch (msr) {
15c4a640 1719 case MSR_IA32_MCG_STATUS:
890ca9ae 1720 vcpu->arch.mcg_status = data;
15c4a640 1721 break;
c7ac679c 1722 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1723 if (!(mcg_cap & MCG_CTL_P))
1724 return 1;
1725 if (data != 0 && data != ~(u64)0)
1726 return -1;
1727 vcpu->arch.mcg_ctl = data;
1728 break;
1729 default:
1730 if (msr >= MSR_IA32_MC0_CTL &&
1731 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1732 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1733 /* only 0 or all 1s can be written to IA32_MCi_CTL
1734 * some Linux kernels though clear bit 10 in bank 4 to
1735 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1736 * this to avoid an uncatched #GP in the guest
1737 */
890ca9ae 1738 if ((offset & 0x3) == 0 &&
114be429 1739 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1740 return -1;
1741 vcpu->arch.mce_banks[offset] = data;
1742 break;
1743 }
1744 return 1;
1745 }
1746 return 0;
1747}
1748
ffde22ac
ES		 1749static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1750{
1751 struct kvm *kvm = vcpu->kvm;
1752 int lm = is_long_mode(vcpu);
1753 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1754 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1755 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1756 : kvm->arch.xen_hvm_config.blob_size_32;
1757 u32 page_num = data & ~PAGE_MASK;
1758 u64 page_addr = data & PAGE_MASK;
1759 u8 *page;
1760 int r;
1761
1762 r = -E2BIG;
1763 if (page_num >= blob_size)
1764 goto out;
1765 r = -ENOMEM;
ff5c2c03
SL		 1766 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1767 if (IS_ERR(page)) {
1768 r = PTR_ERR(page);
ffde22ac 1769 goto out;
ff5c2c03 1770 }
ffde22ac
ES		 1771 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1772 goto out_free;
1773 r = 0;
1774out_free:
1775 kfree(page);
1776out:
1777 return r;
1778}
1779
55cd8e5a
GN		 1780static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1781{
1782 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1783}
1784
1785static bool kvm_hv_msr_partition_wide(u32 msr)
1786{
1787 bool r = false;
1788 switch (msr) {
1789 case HV_X64_MSR_GUEST_OS_ID:
1790 case HV_X64_MSR_HYPERCALL:
1791 r = true;
1792 break;
1793 }
1794
1795 return r;
1796}
1797
1798static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1799{
1800 struct kvm *kvm = vcpu->kvm;
1801
1802 switch (msr) {
1803 case HV_X64_MSR_GUEST_OS_ID:
1804 kvm->arch.hv_guest_os_id = data;
1805 /* setting guest os id to zero disables hypercall page */
1806 if (!kvm->arch.hv_guest_os_id)
1807 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1808 break;
1809 case HV_X64_MSR_HYPERCALL: {
1810 u64 gfn;
1811 unsigned long addr;
1812 u8 instructions[4];
1813
1814 /* if guest os id is not set hypercall should remain disabled */
1815 if (!kvm->arch.hv_guest_os_id)
1816 break;
1817 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1818 kvm->arch.hv_hypercall = data;
1819 break;
1820 }
1821 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1822 addr = gfn_to_hva(kvm, gfn);
1823 if (kvm_is_error_hva(addr))
1824 return 1;
1825 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1826 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1827 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1828 return 1;
1829 kvm->arch.hv_hypercall = data;
1830 break;
1831 }
1832 default:
a737f256
CD		 1833 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1834 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1835 return 1;
1836 }
1837 return 0;
1838}
1839
1840static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1841{
10388a07
GN		 1842 switch (msr) {
1843 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1844 unsigned long addr;
55cd8e5a 1845
10388a07
GN		 1846 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1847 vcpu->arch.hv_vapic = data;
1848 break;
1849 }
1850 addr = gfn_to_hva(vcpu->kvm, data >>
1851 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1852 if (kvm_is_error_hva(addr))
1853 return 1;
8b0cedff 1854 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1855 return 1;
1856 vcpu->arch.hv_vapic = data;
1857 break;
1858 }
1859 case HV_X64_MSR_EOI:
1860 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1861 case HV_X64_MSR_ICR:
1862 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1863 case HV_X64_MSR_TPR:
1864 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1865 default:
a737f256
CD		 1866 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1867 "data 0x%llx\n", msr, data);
10388a07
GN		 1868 return 1;
1869 }
1870
1871 return 0;
55cd8e5a
GN		 1872}
1873
344d9588
GN		 1874static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1875{
1876 gpa_t gpa = data & ~0x3f;
1877
4a969980 1878 /* Bits 2:5 are reserved, Should be zero */
6adba527 1879 if (data & 0x3c)
344d9588
GN		 1880 return 1;
1881
1882 vcpu->arch.apf.msr_val = data;
1883
1884 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1885 kvm_clear_async_pf_completion_queue(vcpu);
1886 kvm_async_pf_hash_reset(vcpu);
1887 return 0;
1888 }
1889
8f964525
AH		 1890 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1891 sizeof(u32)))
344d9588
GN		 1892 return 1;
1893
6adba527 1894 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1895 kvm_async_pf_wakeup_all(vcpu);
1896 return 0;
1897}
1898
12f9a48f
GC		 1899static void kvmclock_reset(struct kvm_vcpu *vcpu)
1900{
0b79459b 1901 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1902}
1903
c9aaa895
GC		 1904static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1905{
1906 u64 delta;
1907
1908 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1909 return;
1910
1911 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1912 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1913 vcpu->arch.st.accum_steal = delta;
1914}
1915
1916static void record_steal_time(struct kvm_vcpu *vcpu)
1917{
1918 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1919 return;
1920
1921 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1922 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1923 return;
1924
1925 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1926 vcpu->arch.st.steal.version += 2;
1927 vcpu->arch.st.accum_steal = 0;
1928
1929 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1930 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1931}
1932
8fe8ab46 1933int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1934{
5753785f 1935 bool pr = false;
8fe8ab46
WA		 1936 u32 msr = msr_info->index;
1937 u64 data = msr_info->data;
5753785f 1938
15c4a640 1939 switch (msr) {
2e32b719
BP		 1940 case MSR_AMD64_NB_CFG:
1941 case MSR_IA32_UCODE_REV:
1942 case MSR_IA32_UCODE_WRITE:
1943 case MSR_VM_HSAVE_PA:
1944 case MSR_AMD64_PATCH_LOADER:
1945 case MSR_AMD64_BU_CFG2:
1946 break;
1947
15c4a640 1948 case MSR_EFER:
b69e8cae 1949 return set_efer(vcpu, data);
8f1589d9
AP		 1950 case MSR_K7_HWCR:
1951 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1952 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1953 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1954 if (data != 0) {
a737f256
CD		 1955 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1956 data);
8f1589d9
AP		 1957 return 1;
1958 }
15c4a640 1959 break;
f7c6d140
AP		 1960 case MSR_FAM10H_MMIO_CONF_BASE:
1961 if (data != 0) {
a737f256
CD		 1962 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1963 "0x%llx\n", data);
f7c6d140
AP		 1964 return 1;
1965 }
15c4a640 1966 break;
b5e2fec0
AG		 1967 case MSR_IA32_DEBUGCTLMSR:
1968 if (!data) {
1969 /* We support the non-activated case already */
1970 break;
1971 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1972 /* Values other than LBR and BTF are vendor-specific,
1973 thus reserved and should throw a #GP */
1974 return 1;
1975 }
a737f256
CD		 1976 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1977 __func__, data);
b5e2fec0 1978 break;
9ba075a6
AK		 1979 case 0x200 ... 0x2ff:
1980 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1981 case MSR_IA32_APICBASE:
1982 kvm_set_apic_base(vcpu, data);
1983 break;
0105d1a5
GN		 1984 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1985 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1986 case MSR_IA32_TSCDEADLINE:
1987 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1988 break;
ba904635
WA		 1989 case MSR_IA32_TSC_ADJUST:
1990 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1991 if (!msr_info->host_initiated) {
1992 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1993 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1994 }
1995 vcpu->arch.ia32_tsc_adjust_msr = data;
1996 }
1997 break;
15c4a640 1998 case MSR_IA32_MISC_ENABLE:
ad312c7c 1999 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2000 break;
11c6bffa 2001 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2002 case MSR_KVM_WALL_CLOCK:
2003 vcpu->kvm->arch.wall_clock = data;
2004 kvm_write_wall_clock(vcpu->kvm, data);
2005 break;
11c6bffa 2006 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2007 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2008 u64 gpa_offset;
12f9a48f 2009 kvmclock_reset(vcpu);
18068523
GOC		 2010
2011 vcpu->arch.time = data;
0061d53d 2012 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2013
2014 /* we verify if the enable bit is set... */
2015 if (!(data & 1))
2016 break;
2017
0b79459b 2018 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2019
0b79459b 2020 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2021 &vcpu->arch.pv_time, data & ~1ULL,
2022 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2023 vcpu->arch.pv_time_enabled = false;
2024 else
2025 vcpu->arch.pv_time_enabled = true;
32cad84f 2026
18068523
GOC		 2027 break;
2028 }
344d9588
GN		 2029 case MSR_KVM_ASYNC_PF_EN:
2030 if (kvm_pv_enable_async_pf(vcpu, data))
2031 return 1;
2032 break;
c9aaa895
GC		 2033 case MSR_KVM_STEAL_TIME:
2034
2035 if (unlikely(!sched_info_on()))
2036 return 1;
2037
2038 if (data & KVM_STEAL_RESERVED_MASK)
2039 return 1;
2040
2041 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2042 data & KVM_STEAL_VALID_BITS,
2043 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2044 return 1;
2045
2046 vcpu->arch.st.msr_val = data;
2047
2048 if (!(data & KVM_MSR_ENABLED))
2049 break;
2050
2051 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2052
2053 preempt_disable();
2054 accumulate_steal_time(vcpu);
2055 preempt_enable();
2056
2057 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2058
2059 break;
ae7a2a3f
MT		 2060 case MSR_KVM_PV_EOI_EN:
2061 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2062 return 1;
2063 break;
c9aaa895 2064
890ca9ae
HY		 2065 case MSR_IA32_MCG_CTL:
2066 case MSR_IA32_MCG_STATUS:
2067 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2068 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2069
2070 /* Performance counters are not protected by a CPUID bit,
2071 * so we should check all of them in the generic path for the sake of
2072 * cross vendor migration.
2073 * Writing a zero into the event select MSRs disables them,
2074 * which we perfectly emulate ;-). Any other value should be at least
2075 * reported, some guests depend on them.
2076 */
71db6023
AP		 2077 case MSR_K7_EVNTSEL0:
2078 case MSR_K7_EVNTSEL1:
2079 case MSR_K7_EVNTSEL2:
2080 case MSR_K7_EVNTSEL3:
2081 if (data != 0)
a737f256
CD		 2082 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2083 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2084 break;
2085 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2086 * so we ignore writes to make it happy.
2087 */
71db6023
AP		 2088 case MSR_K7_PERFCTR0:
2089 case MSR_K7_PERFCTR1:
2090 case MSR_K7_PERFCTR2:
2091 case MSR_K7_PERFCTR3:
a737f256
CD		 2092 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2093 "0x%x data 0x%llx\n", msr, data);
71db6023 2094 break;
5753785f
GN		 2095 case MSR_P6_PERFCTR0:
2096 case MSR_P6_PERFCTR1:
2097 pr = true;
2098 case MSR_P6_EVNTSEL0:
2099 case MSR_P6_EVNTSEL1:
2100 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2101 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2102
2103 if (pr || data != 0)
a737f256
CD		 2104 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2105 "0x%x data 0x%llx\n", msr, data);
5753785f 2106 break;
84e0cefa
JS		 2107 case MSR_K7_CLK_CTL:
2108 /*
2109 * Ignore all writes to this no longer documented MSR.
2110 * Writes are only relevant for old K7 processors,
2111 * all pre-dating SVM, but a recommended workaround from
4a969980 2112 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2113 * affected processor models on the command line, hence
2114 * the need to ignore the workaround.
2115 */
2116 break;
55cd8e5a
GN		 2117 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2118 if (kvm_hv_msr_partition_wide(msr)) {
2119 int r;
2120 mutex_lock(&vcpu->kvm->lock);
2121 r = set_msr_hyperv_pw(vcpu, msr, data);
2122 mutex_unlock(&vcpu->kvm->lock);
2123 return r;
2124 } else
2125 return set_msr_hyperv(vcpu, msr, data);
2126 break;
91c9c3ed 2127 case MSR_IA32_BBL_CR_CTL3:
2128 /* Drop writes to this legacy MSR -- see rdmsr
2129 * counterpart for further detail.
2130 */
a737f256 2131 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2132 break;
2b036c6b
BO		 2133 case MSR_AMD64_OSVW_ID_LENGTH:
2134 if (!guest_cpuid_has_osvw(vcpu))
2135 return 1;
2136 vcpu->arch.osvw.length = data;
2137 break;
2138 case MSR_AMD64_OSVW_STATUS:
2139 if (!guest_cpuid_has_osvw(vcpu))
2140 return 1;
2141 vcpu->arch.osvw.status = data;
2142 break;
15c4a640 2143 default:
ffde22ac
ES		 2144 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2145 return xen_hvm_config(vcpu, data);
f5132b01 2146 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2147 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2148 if (!ignore_msrs) {
a737f256
CD		 2149 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2150 msr, data);
ed85c068
AP		 2151 return 1;
2152 } else {
a737f256
CD		 2153 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2154 msr, data);
ed85c068
AP		 2155 break;
2156 }
15c4a640
CO		 2157 }
2158 return 0;
2159}
2160EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2161
2162
2163/*
2164 * Reads an msr value (of 'msr_index') into 'pdata'.
2165 * Returns 0 on success, non-0 otherwise.
2166 * Assumes vcpu_load() was already called.
2167 */
2168int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2169{
2170 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2171}
2172
9ba075a6
AK		 2173static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2174{
0bed3b56
SY		 2175 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2176
9ba075a6
AK		 2177 if (!msr_mtrr_valid(msr))
2178 return 1;
2179
0bed3b56
SY		 2180 if (msr == MSR_MTRRdefType)
2181 *pdata = vcpu->arch.mtrr_state.def_type +
2182 (vcpu->arch.mtrr_state.enabled << 10);
2183 else if (msr == MSR_MTRRfix64K_00000)
2184 *pdata = p[0];
2185 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2186 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2187 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2188 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2189 else if (msr == MSR_IA32_CR_PAT)
2190 *pdata = vcpu->arch.pat;
2191 else { /* Variable MTRRs */
2192 int idx, is_mtrr_mask;
2193 u64 *pt;
2194
2195 idx = (msr - 0x200) / 2;
2196 is_mtrr_mask = msr - 0x200 - 2 * idx;
2197 if (!is_mtrr_mask)
2198 pt =
2199 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2200 else
2201 pt =
2202 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2203 *pdata = *pt;
2204 }
2205
9ba075a6
AK		 2206 return 0;
2207}
2208
890ca9ae 2209static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2210{
2211 u64 data;
890ca9ae
HY		 2212 u64 mcg_cap = vcpu->arch.mcg_cap;
2213 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2214
2215 switch (msr) {
15c4a640
CO		 2216 case MSR_IA32_P5_MC_ADDR:
2217 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2218 data = 0;
2219 break;
15c4a640 2220 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2221 data = vcpu->arch.mcg_cap;
2222 break;
c7ac679c 2223 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2224 if (!(mcg_cap & MCG_CTL_P))
2225 return 1;
2226 data = vcpu->arch.mcg_ctl;
2227 break;
2228 case MSR_IA32_MCG_STATUS:
2229 data = vcpu->arch.mcg_status;
2230 break;
2231 default:
2232 if (msr >= MSR_IA32_MC0_CTL &&
2233 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2234 u32 offset = msr - MSR_IA32_MC0_CTL;
2235 data = vcpu->arch.mce_banks[offset];
2236 break;
2237 }
2238 return 1;
2239 }
2240 *pdata = data;
2241 return 0;
2242}
2243
55cd8e5a
GN		 2244static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2245{
2246 u64 data = 0;
2247 struct kvm *kvm = vcpu->kvm;
2248
2249 switch (msr) {
2250 case HV_X64_MSR_GUEST_OS_ID:
2251 data = kvm->arch.hv_guest_os_id;
2252 break;
2253 case HV_X64_MSR_HYPERCALL:
2254 data = kvm->arch.hv_hypercall;
2255 break;
2256 default:
a737f256 2257 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2258 return 1;
2259 }
2260
2261 *pdata = data;
2262 return 0;
2263}
2264
2265static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2266{
2267 u64 data = 0;
2268
2269 switch (msr) {
2270 case HV_X64_MSR_VP_INDEX: {
2271 int r;
2272 struct kvm_vcpu *v;
2273 kvm_for_each_vcpu(r, v, vcpu->kvm)
2274 if (v == vcpu)
2275 data = r;
2276 break;
2277 }
10388a07
GN		 2278 case HV_X64_MSR_EOI:
2279 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2280 case HV_X64_MSR_ICR:
2281 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2282 case HV_X64_MSR_TPR:
2283 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2284 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2285 data = vcpu->arch.hv_vapic;
2286 break;
55cd8e5a 2287 default:
a737f256 2288 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2289 return 1;
2290 }
2291 *pdata = data;
2292 return 0;
2293}
2294
890ca9ae
HY		 2295int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2296{
2297 u64 data;
2298
2299 switch (msr) {
890ca9ae 2300 case MSR_IA32_PLATFORM_ID:
15c4a640 2301 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2302 case MSR_IA32_DEBUGCTLMSR:
2303 case MSR_IA32_LASTBRANCHFROMIP:
2304 case MSR_IA32_LASTBRANCHTOIP:
2305 case MSR_IA32_LASTINTFROMIP:
2306 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2307 case MSR_K8_SYSCFG:
2308 case MSR_K7_HWCR:
61a6bd67 2309 case MSR_VM_HSAVE_PA:
9e699624 2310 case MSR_K7_EVNTSEL0:
1f3ee616 2311 case MSR_K7_PERFCTR0:
1fdbd48c 2312 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2313 case MSR_AMD64_NB_CFG:
f7c6d140 2314 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2315 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2316 data = 0;
2317 break;
5753785f
GN		 2318 case MSR_P6_PERFCTR0:
2319 case MSR_P6_PERFCTR1:
2320 case MSR_P6_EVNTSEL0:
2321 case MSR_P6_EVNTSEL1:
2322 if (kvm_pmu_msr(vcpu, msr))
2323 return kvm_pmu_get_msr(vcpu, msr, pdata);
2324 data = 0;
2325 break;
742bc670
MT		 2326 case MSR_IA32_UCODE_REV:
2327 data = 0x100000000ULL;
2328 break;
9ba075a6
AK		 2329 case MSR_MTRRcap:
2330 data = 0x500 | KVM_NR_VAR_MTRR;
2331 break;
2332 case 0x200 ... 0x2ff:
2333 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2334 case 0xcd: /* fsb frequency */
2335 data = 3;
2336 break;
7b914098
JS		 2337 /*
2338 * MSR_EBC_FREQUENCY_ID
2339 * Conservative value valid for even the basic CPU models.
2340 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2341 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2342 * and 266MHz for model 3, or 4. Set Core Clock
2343 * Frequency to System Bus Frequency Ratio to 1 (bits
2344 * 31:24) even though these are only valid for CPU
2345 * models > 2, however guests may end up dividing or
2346 * multiplying by zero otherwise.
2347 */
2348 case MSR_EBC_FREQUENCY_ID:
2349 data = 1 << 24;
2350 break;
15c4a640
CO		 2351 case MSR_IA32_APICBASE:
2352 data = kvm_get_apic_base(vcpu);
2353 break;
0105d1a5
GN		 2354 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2355 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2356 break;
a3e06bbe
LJ		 2357 case MSR_IA32_TSCDEADLINE:
2358 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2359 break;
ba904635
WA		 2360 case MSR_IA32_TSC_ADJUST:
2361 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2362 break;
15c4a640 2363 case MSR_IA32_MISC_ENABLE:
ad312c7c 2364 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2365 break;
847f0ad8
AG		 2366 case MSR_IA32_PERF_STATUS:
2367 /* TSC increment by tick */
2368 data = 1000ULL;
2369 /* CPU multiplier */
2370 data |= (((uint64_t)4ULL) << 40);
2371 break;
15c4a640 2372 case MSR_EFER:
f6801dff 2373 data = vcpu->arch.efer;
15c4a640 2374 break;
18068523 2375 case MSR_KVM_WALL_CLOCK:
11c6bffa 2376 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2377 data = vcpu->kvm->arch.wall_clock;
2378 break;
2379 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2380 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2381 data = vcpu->arch.time;
2382 break;
344d9588
GN		 2383 case MSR_KVM_ASYNC_PF_EN:
2384 data = vcpu->arch.apf.msr_val;
2385 break;
c9aaa895
GC		 2386 case MSR_KVM_STEAL_TIME:
2387 data = vcpu->arch.st.msr_val;
2388 break;
1d92128f
MT		 2389 case MSR_KVM_PV_EOI_EN:
2390 data = vcpu->arch.pv_eoi.msr_val;
2391 break;
890ca9ae
HY		 2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
2394 case MSR_IA32_MCG_CAP:
2395 case MSR_IA32_MCG_CTL:
2396 case MSR_IA32_MCG_STATUS:
2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2398 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2399 case MSR_K7_CLK_CTL:
2400 /*
2401 * Provide expected ramp-up count for K7. All other
2402 * are set to zero, indicating minimum divisors for
2403 * every field.
2404 *
2405 * This prevents guest kernels on AMD host with CPU
2406 * type 6, model 8 and higher from exploding due to
2407 * the rdmsr failing.
2408 */
2409 data = 0x20000000;
2410 break;
55cd8e5a
GN		 2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2412 if (kvm_hv_msr_partition_wide(msr)) {
2413 int r;
2414 mutex_lock(&vcpu->kvm->lock);
2415 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2416 mutex_unlock(&vcpu->kvm->lock);
2417 return r;
2418 } else
2419 return get_msr_hyperv(vcpu, msr, pdata);
2420 break;
91c9c3ed 2421 case MSR_IA32_BBL_CR_CTL3:
2422 /* This legacy MSR exists but isn't fully documented in current
2423 * silicon. It is however accessed by winxp in very narrow
2424 * scenarios where it sets bit #19, itself documented as
2425 * a "reserved" bit. Best effort attempt to source coherent
2426 * read data here should the balance of the register be
2427 * interpreted by the guest:
2428 *
2429 * L2 cache control register 3: 64GB range, 256KB size,
2430 * enabled, latency 0x1, configured
2431 */
2432 data = 0xbe702111;
2433 break;
2b036c6b
BO		 2434 case MSR_AMD64_OSVW_ID_LENGTH:
2435 if (!guest_cpuid_has_osvw(vcpu))
2436 return 1;
2437 data = vcpu->arch.osvw.length;
2438 break;
2439 case MSR_AMD64_OSVW_STATUS:
2440 if (!guest_cpuid_has_osvw(vcpu))
2441 return 1;
2442 data = vcpu->arch.osvw.status;
2443 break;
15c4a640 2444 default:
f5132b01
GN		 2445 if (kvm_pmu_msr(vcpu, msr))
2446 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2447 if (!ignore_msrs) {
a737f256 2448 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2449 return 1;
2450 } else {
a737f256 2451 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2452 data = 0;
2453 }
2454 break;
15c4a640
CO		 2455 }
2456 *pdata = data;
2457 return 0;
2458}
2459EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2460
313a3dc7
CO		 2461/*
2462 * Read or write a bunch of msrs. All parameters are kernel addresses.
2463 *
2464 * @return number of msrs set successfully.
2465 */
2466static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2467 struct kvm_msr_entry *entries,
2468 int (*do_msr)(struct kvm_vcpu *vcpu,
2469 unsigned index, u64 *data))
2470{
f656ce01 2471 int i, idx;
313a3dc7 2472
f656ce01 2473 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2474 for (i = 0; i < msrs->nmsrs; ++i)
2475 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2476 break;
f656ce01 2477 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2478
313a3dc7
CO		 2479 return i;
2480}
2481
2482/*
2483 * Read or write a bunch of msrs. Parameters are user addresses.
2484 *
2485 * @return number of msrs set successfully.
2486 */
2487static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2488 int (*do_msr)(struct kvm_vcpu *vcpu,
2489 unsigned index, u64 *data),
2490 int writeback)
2491{
2492 struct kvm_msrs msrs;
2493 struct kvm_msr_entry *entries;
2494 int r, n;
2495 unsigned size;
2496
2497 r = -EFAULT;
2498 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2499 goto out;
2500
2501 r = -E2BIG;
2502 if (msrs.nmsrs >= MAX_IO_MSRS)
2503 goto out;
2504
313a3dc7 2505 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2506 entries = memdup_user(user_msrs->entries, size);
2507 if (IS_ERR(entries)) {
2508 r = PTR_ERR(entries);
313a3dc7 2509 goto out;
ff5c2c03 2510 }
313a3dc7
CO		 2511
2512 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2513 if (r < 0)
2514 goto out_free;
2515
2516 r = -EFAULT;
2517 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2518 goto out_free;
2519
2520 r = n;
2521
2522out_free:
7a73c028 2523 kfree(entries);
313a3dc7
CO		 2524out:
2525 return r;
2526}
2527
018d00d2
ZX		 2528int kvm_dev_ioctl_check_extension(long ext)
2529{
2530 int r;
2531
2532 switch (ext) {
2533 case KVM_CAP_IRQCHIP:
2534 case KVM_CAP_HLT:
2535 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2536 case KVM_CAP_SET_TSS_ADDR:
07716717 2537 case KVM_CAP_EXT_CPUID:
c8076604 2538 case KVM_CAP_CLOCKSOURCE:
7837699f 2539 case KVM_CAP_PIT:
a28e4f5a 2540 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2541 case KVM_CAP_MP_STATE:
ed848624 2542 case KVM_CAP_SYNC_MMU:
a355c85c 2543 case KVM_CAP_USER_NMI:
52d939a0 2544 case KVM_CAP_REINJECT_CONTROL:
4925663a 2545 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2546 case KVM_CAP_IRQFD:
d34e6b17 2547 case KVM_CAP_IOEVENTFD:
c5ff41ce 2548 case KVM_CAP_PIT2:
e9f42757 2549 case KVM_CAP_PIT_STATE2:
b927a3ce 2550 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2551 case KVM_CAP_XEN_HVM:
afbcf7ab 2552 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2553 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2554 case KVM_CAP_HYPERV:
10388a07 2555 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2556 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2557 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2558 case KVM_CAP_DEBUGREGS:
d2be1651 2559 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2560 case KVM_CAP_XSAVE:
344d9588 2561 case KVM_CAP_ASYNC_PF:
92a1f12d 2562 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2563 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2564 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2565#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2566 case KVM_CAP_ASSIGN_DEV_IRQ:
2567 case KVM_CAP_PCI_2_3:
2568#endif
018d00d2
ZX		 2569 r = 1;
2570 break;
542472b5
LV		 2571 case KVM_CAP_COALESCED_MMIO:
2572 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2573 break;
774ead3a
AK		 2574 case KVM_CAP_VAPIC:
2575 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2576 break;
f725230a 2577 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2578 r = KVM_SOFT_MAX_VCPUS;
2579 break;
2580 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2581 r = KVM_MAX_VCPUS;
2582 break;
a988b910 2583 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2584 r = KVM_USER_MEM_SLOTS;
a988b910 2585 break;
a68a6a72
MT		 2586 case KVM_CAP_PV_MMU: /* obsolete */
2587 r = 0;
2f333bcb 2588 break;
4cee4b72 2589#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2590 case KVM_CAP_IOMMU:
a1b60c1c 2591 r = iommu_present(&pci_bus_type);
62c476c7 2592 break;
4cee4b72 2593#endif
890ca9ae
HY		 2594 case KVM_CAP_MCE:
2595 r = KVM_MAX_MCE_BANKS;
2596 break;
2d5b5a66
SY		 2597 case KVM_CAP_XCRS:
2598 r = cpu_has_xsave;
2599 break;
92a1f12d
JR		 2600 case KVM_CAP_TSC_CONTROL:
2601 r = kvm_has_tsc_control;
2602 break;
4d25a066
JK		 2603 case KVM_CAP_TSC_DEADLINE_TIMER:
2604 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2605 break;
018d00d2
ZX		 2606 default:
2607 r = 0;
2608 break;
2609 }
2610 return r;
2611
2612}
2613
043405e1
CO		 2614long kvm_arch_dev_ioctl(struct file *filp,
2615 unsigned int ioctl, unsigned long arg)
2616{
2617 void __user *argp = (void __user *)arg;
2618 long r;
2619
2620 switch (ioctl) {
2621 case KVM_GET_MSR_INDEX_LIST: {
2622 struct kvm_msr_list __user *user_msr_list = argp;
2623 struct kvm_msr_list msr_list;
2624 unsigned n;
2625
2626 r = -EFAULT;
2627 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2628 goto out;
2629 n = msr_list.nmsrs;
2630 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2631 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2632 goto out;
2633 r = -E2BIG;
e125e7b6 2634 if (n < msr_list.nmsrs)
043405e1
CO		 2635 goto out;
2636 r = -EFAULT;
2637 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2638 num_msrs_to_save * sizeof(u32)))
2639 goto out;
e125e7b6 2640 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2641 &emulated_msrs,
2642 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2643 goto out;
2644 r = 0;
2645 break;
2646 }
674eea0f
AK		 2647 case KVM_GET_SUPPORTED_CPUID: {
2648 struct kvm_cpuid2 __user *cpuid_arg = argp;
2649 struct kvm_cpuid2 cpuid;
2650
2651 r = -EFAULT;
2652 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2653 goto out;
2654 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2655 cpuid_arg->entries);
674eea0f
AK		 2656 if (r)
2657 goto out;
2658
2659 r = -EFAULT;
2660 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2661 goto out;
2662 r = 0;
2663 break;
2664 }
890ca9ae
HY		 2665 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2666 u64 mce_cap;
2667
2668 mce_cap = KVM_MCE_CAP_SUPPORTED;
2669 r = -EFAULT;
2670 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2671 goto out;
2672 r = 0;
2673 break;
2674 }
043405e1
CO		 2675 default:
2676 r = -EINVAL;
2677 }
2678out:
2679 return r;
2680}
2681
f5f48ee1
SY		 2682static void wbinvd_ipi(void *garbage)
2683{
2684 wbinvd();
2685}
2686
2687static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2688{
2689 return vcpu->kvm->arch.iommu_domain &&
2690 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2691}
2692
313a3dc7
CO		 2693void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2694{
f5f48ee1
SY		 2695 /* Address WBINVD may be executed by guest */
2696 if (need_emulate_wbinvd(vcpu)) {
2697 if (kvm_x86_ops->has_wbinvd_exit())
2698 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2699 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2700 smp_call_function_single(vcpu->cpu,
2701 wbinvd_ipi, NULL, 1);
2702 }
2703
313a3dc7 2704 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2705
0dd6a6ed
ZA		 2706 /* Apply any externally detected TSC adjustments (due to suspend) */
2707 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2708 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2709 vcpu->arch.tsc_offset_adjustment = 0;
2710 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2711 }
8f6055cb 2712
48434c20 2713 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2714 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2715 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2716 if (tsc_delta < 0)
2717 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2718 if (check_tsc_unstable()) {
b183aa58
ZA		 2719 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2720 vcpu->arch.last_guest_tsc);
2721 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2722 vcpu->arch.tsc_catchup = 1;
c285545f 2723 }
d98d07ca
MT		 2724 /*
2725 * On a host with synchronized TSC, there is no need to update
2726 * kvmclock on vcpu->cpu migration
2727 */
2728 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2729 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2730 if (vcpu->cpu != cpu)
2731 kvm_migrate_timers(vcpu);
e48672fa 2732 vcpu->cpu = cpu;
6b7d7e76 2733 }
c9aaa895
GC		 2734
2735 accumulate_steal_time(vcpu);
2736 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2737}
2738
2739void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2740{
02daab21 2741 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2742 kvm_put_guest_fpu(vcpu);
6f526ec5 2743 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2744}
2745
313a3dc7
CO		 2746static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2747 struct kvm_lapic_state *s)
2748{
5a71785d 2749 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2750 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2751
2752 return 0;
2753}
2754
2755static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2756 struct kvm_lapic_state *s)
2757{
64eb0620 2758 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2759 update_cr8_intercept(vcpu);
313a3dc7
CO		 2760
2761 return 0;
2762}
2763
f77bc6a4
ZX		 2764static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2765 struct kvm_interrupt *irq)
2766{
02cdb50f 2767 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2768 return -EINVAL;
2769 if (irqchip_in_kernel(vcpu->kvm))
2770 return -ENXIO;
f77bc6a4 2771
66fd3f7f 2772 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2773 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2774
f77bc6a4
ZX		 2775 return 0;
2776}
2777
c4abb7c9
JK		 2778static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2779{
c4abb7c9 2780 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2781
2782 return 0;
2783}
2784
b209749f
AK		 2785static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2786 struct kvm_tpr_access_ctl *tac)
2787{
2788 if (tac->flags)
2789 return -EINVAL;
2790 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2791 return 0;
2792}
2793
890ca9ae
HY		 2794static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2795 u64 mcg_cap)
2796{
2797 int r;
2798 unsigned bank_num = mcg_cap & 0xff, bank;
2799
2800 r = -EINVAL;
a9e38c3e 2801 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2802 goto out;
2803 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2804 goto out;
2805 r = 0;
2806 vcpu->arch.mcg_cap = mcg_cap;
2807 /* Init IA32_MCG_CTL to all 1s */
2808 if (mcg_cap & MCG_CTL_P)
2809 vcpu->arch.mcg_ctl = ~(u64)0;
2810 /* Init IA32_MCi_CTL to all 1s */
2811 for (bank = 0; bank < bank_num; bank++)
2812 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2813out:
2814 return r;
2815}
2816
2817static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2818 struct kvm_x86_mce *mce)
2819{
2820 u64 mcg_cap = vcpu->arch.mcg_cap;
2821 unsigned bank_num = mcg_cap & 0xff;
2822 u64 *banks = vcpu->arch.mce_banks;
2823
2824 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2825 return -EINVAL;
2826 /*
2827 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2828 * reporting is disabled
2829 */
2830 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2831 vcpu->arch.mcg_ctl != ~(u64)0)
2832 return 0;
2833 banks += 4 * mce->bank;
2834 /*
2835 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2836 * reporting is disabled for the bank
2837 */
2838 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2839 return 0;
2840 if (mce->status & MCI_STATUS_UC) {
2841 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2842 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2843 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2844 return 0;
2845 }
2846 if (banks[1] & MCI_STATUS_VAL)
2847 mce->status |= MCI_STATUS_OVER;
2848 banks[2] = mce->addr;
2849 banks[3] = mce->misc;
2850 vcpu->arch.mcg_status = mce->mcg_status;
2851 banks[1] = mce->status;
2852 kvm_queue_exception(vcpu, MC_VECTOR);
2853 } else if (!(banks[1] & MCI_STATUS_VAL)
2854 || !(banks[1] & MCI_STATUS_UC)) {
2855 if (banks[1] & MCI_STATUS_VAL)
2856 mce->status |= MCI_STATUS_OVER;
2857 banks[2] = mce->addr;
2858 banks[3] = mce->misc;
2859 banks[1] = mce->status;
2860 } else
2861 banks[1] |= MCI_STATUS_OVER;
2862 return 0;
2863}
2864
3cfc3092
JK		 2865static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2866 struct kvm_vcpu_events *events)
2867{
7460fb4a 2868 process_nmi(vcpu);
03b82a30
JK		 2869 events->exception.injected =
2870 vcpu->arch.exception.pending &&
2871 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2872 events->exception.nr = vcpu->arch.exception.nr;
2873 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2874 events->exception.pad = 0;
3cfc3092
JK		 2875 events->exception.error_code = vcpu->arch.exception.error_code;
2876
03b82a30
JK		 2877 events->interrupt.injected =
2878 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2879 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2880 events->interrupt.soft = 0;
48005f64
JK		 2881 events->interrupt.shadow =
2882 kvm_x86_ops->get_interrupt_shadow(vcpu,
2883 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2884
2885 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2886 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2887 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2888 events->nmi.pad = 0;
3cfc3092 2889
66450a21 2890 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2891
dab4b911 2892 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2893 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2894 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2895}
2896
2897static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2898 struct kvm_vcpu_events *events)
2899{
dab4b911 2900 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2901 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2902 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2903 return -EINVAL;
2904
7460fb4a 2905 process_nmi(vcpu);
3cfc3092
JK		 2906 vcpu->arch.exception.pending = events->exception.injected;
2907 vcpu->arch.exception.nr = events->exception.nr;
2908 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2909 vcpu->arch.exception.error_code = events->exception.error_code;
2910
2911 vcpu->arch.interrupt.pending = events->interrupt.injected;
2912 vcpu->arch.interrupt.nr = events->interrupt.nr;
2913 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2914 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2915 kvm_x86_ops->set_interrupt_shadow(vcpu,
2916 events->interrupt.shadow);
3cfc3092
JK		 2917
2918 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2919 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2920 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2921 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2922
66450a21
JK		 2923 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2924 kvm_vcpu_has_lapic(vcpu))
2925 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2926
3842d135
AK		 2927 kvm_make_request(KVM_REQ_EVENT, vcpu);
2928
3cfc3092
JK		 2929 return 0;
2930}
2931
a1efbe77
JK		 2932static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2933 struct kvm_debugregs *dbgregs)
2934{
a1efbe77
JK		 2935 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2936 dbgregs->dr6 = vcpu->arch.dr6;
2937 dbgregs->dr7 = vcpu->arch.dr7;
2938 dbgregs->flags = 0;
97e69aa6 2939 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2940}
2941
2942static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2943 struct kvm_debugregs *dbgregs)
2944{
2945 if (dbgregs->flags)
2946 return -EINVAL;
2947
a1efbe77
JK		 2948 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2949 vcpu->arch.dr6 = dbgregs->dr6;
2950 vcpu->arch.dr7 = dbgregs->dr7;
2951
a1efbe77
JK		 2952 return 0;
2953}
2954
2d5b5a66
SY		 2955static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2956 struct kvm_xsave *guest_xsave)
2957{
2958 if (cpu_has_xsave)
2959 memcpy(guest_xsave->region,
2960 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2961 xstate_size);
2d5b5a66
SY		 2962 else {
2963 memcpy(guest_xsave->region,
2964 &vcpu->arch.guest_fpu.state->fxsave,
2965 sizeof(struct i387_fxsave_struct));
2966 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2967 XSTATE_FPSSE;
2968 }
2969}
2970
2971static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2972 struct kvm_xsave *guest_xsave)
2973{
2974 u64 xstate_bv =
2975 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2976
2977 if (cpu_has_xsave)
2978 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2979 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2980 else {
2981 if (xstate_bv & ~XSTATE_FPSSE)
2982 return -EINVAL;
2983 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2984 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2985 }
2986 return 0;
2987}
2988
2989static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2990 struct kvm_xcrs *guest_xcrs)
2991{
2992 if (!cpu_has_xsave) {
2993 guest_xcrs->nr_xcrs = 0;
2994 return;
2995 }
2996
2997 guest_xcrs->nr_xcrs = 1;
2998 guest_xcrs->flags = 0;
2999 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3000 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3001}
3002
3003static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3004 struct kvm_xcrs *guest_xcrs)
3005{
3006 int i, r = 0;
3007
3008 if (!cpu_has_xsave)
3009 return -EINVAL;
3010
3011 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3012 return -EINVAL;
3013
3014 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3015 /* Only support XCR0 currently */
3016 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3017 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3018 guest_xcrs->xcrs[0].value);
3019 break;
3020 }
3021 if (r)
3022 r = -EINVAL;
3023 return r;
3024}
3025
1c0b28c2
EM		 3026/*
3027 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3028 * stopped by the hypervisor. This function will be called from the host only.
3029 * EINVAL is returned when the host attempts to set the flag for a guest that
3030 * does not support pv clocks.
3031 */
3032static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3033{
0b79459b 3034 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3035 return -EINVAL;
51d59c6b 3036 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3037 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3038 return 0;
3039}
3040
313a3dc7
CO		 3041long kvm_arch_vcpu_ioctl(struct file *filp,
3042 unsigned int ioctl, unsigned long arg)
3043{
3044 struct kvm_vcpu *vcpu = filp->private_data;
3045 void __user *argp = (void __user *)arg;
3046 int r;
d1ac91d8
AK		 3047 union {
3048 struct kvm_lapic_state *lapic;
3049 struct kvm_xsave *xsave;
3050 struct kvm_xcrs *xcrs;
3051 void *buffer;
3052 } u;
3053
3054 u.buffer = NULL;
313a3dc7
CO		 3055 switch (ioctl) {
3056 case KVM_GET_LAPIC: {
2204ae3c
MT		 3057 r = -EINVAL;
3058 if (!vcpu->arch.apic)
3059 goto out;
d1ac91d8 3060 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3061
b772ff36 3062 r = -ENOMEM;
d1ac91d8 3063 if (!u.lapic)
b772ff36 3064 goto out;
d1ac91d8 3065 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3066 if (r)
3067 goto out;
3068 r = -EFAULT;
d1ac91d8 3069 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3070 goto out;
3071 r = 0;
3072 break;
3073 }
3074 case KVM_SET_LAPIC: {
2204ae3c
MT		 3075 r = -EINVAL;
3076 if (!vcpu->arch.apic)
3077 goto out;
ff5c2c03 3078 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3079 if (IS_ERR(u.lapic))
3080 return PTR_ERR(u.lapic);
ff5c2c03 3081
d1ac91d8 3082 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3083 break;
3084 }
f77bc6a4
ZX		 3085 case KVM_INTERRUPT: {
3086 struct kvm_interrupt irq;
3087
3088 r = -EFAULT;
3089 if (copy_from_user(&irq, argp, sizeof irq))
3090 goto out;
3091 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3092 break;
3093 }
c4abb7c9
JK		 3094 case KVM_NMI: {
3095 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3096 break;
3097 }
313a3dc7
CO		 3098 case KVM_SET_CPUID: {
3099 struct kvm_cpuid __user *cpuid_arg = argp;
3100 struct kvm_cpuid cpuid;
3101
3102 r = -EFAULT;
3103 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3104 goto out;
3105 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3106 break;
3107 }
07716717
DK		 3108 case KVM_SET_CPUID2: {
3109 struct kvm_cpuid2 __user *cpuid_arg = argp;
3110 struct kvm_cpuid2 cpuid;
3111
3112 r = -EFAULT;
3113 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3114 goto out;
3115 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3116 cpuid_arg->entries);
07716717
DK		 3117 break;
3118 }
3119 case KVM_GET_CPUID2: {
3120 struct kvm_cpuid2 __user *cpuid_arg = argp;
3121 struct kvm_cpuid2 cpuid;
3122
3123 r = -EFAULT;
3124 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3125 goto out;
3126 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3127 cpuid_arg->entries);
07716717
DK		 3128 if (r)
3129 goto out;
3130 r = -EFAULT;
3131 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3132 goto out;
3133 r = 0;
3134 break;
3135 }
313a3dc7
CO		 3136 case KVM_GET_MSRS:
3137 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3138 break;
3139 case KVM_SET_MSRS:
3140 r = msr_io(vcpu, argp, do_set_msr, 0);
3141 break;
b209749f
AK		 3142 case KVM_TPR_ACCESS_REPORTING: {
3143 struct kvm_tpr_access_ctl tac;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&tac, argp, sizeof tac))
3147 goto out;
3148 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3149 if (r)
3150 goto out;
3151 r = -EFAULT;
3152 if (copy_to_user(argp, &tac, sizeof tac))
3153 goto out;
3154 r = 0;
3155 break;
3156 };
b93463aa
AK		 3157 case KVM_SET_VAPIC_ADDR: {
3158 struct kvm_vapic_addr va;
3159
3160 r = -EINVAL;
3161 if (!irqchip_in_kernel(vcpu->kvm))
3162 goto out;
3163 r = -EFAULT;
3164 if (copy_from_user(&va, argp, sizeof va))
3165 goto out;
3166 r = 0;
3167 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3168 break;
3169 }
890ca9ae
HY		 3170 case KVM_X86_SETUP_MCE: {
3171 u64 mcg_cap;
3172
3173 r = -EFAULT;
3174 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3175 goto out;
3176 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3177 break;
3178 }
3179 case KVM_X86_SET_MCE: {
3180 struct kvm_x86_mce mce;
3181
3182 r = -EFAULT;
3183 if (copy_from_user(&mce, argp, sizeof mce))
3184 goto out;
3185 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3186 break;
3187 }
3cfc3092
JK		 3188 case KVM_GET_VCPU_EVENTS: {
3189 struct kvm_vcpu_events events;
3190
3191 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3192
3193 r = -EFAULT;
3194 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3195 break;
3196 r = 0;
3197 break;
3198 }
3199 case KVM_SET_VCPU_EVENTS: {
3200 struct kvm_vcpu_events events;
3201
3202 r = -EFAULT;
3203 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3204 break;
3205
3206 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3207 break;
3208 }
a1efbe77
JK		 3209 case KVM_GET_DEBUGREGS: {
3210 struct kvm_debugregs dbgregs;
3211
3212 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3213
3214 r = -EFAULT;
3215 if (copy_to_user(argp, &dbgregs,
3216 sizeof(struct kvm_debugregs)))
3217 break;
3218 r = 0;
3219 break;
3220 }
3221 case KVM_SET_DEBUGREGS: {
3222 struct kvm_debugregs dbgregs;
3223
3224 r = -EFAULT;
3225 if (copy_from_user(&dbgregs, argp,
3226 sizeof(struct kvm_debugregs)))
3227 break;
3228
3229 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3230 break;
3231 }
2d5b5a66 3232 case KVM_GET_XSAVE: {
d1ac91d8 3233 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3234 r = -ENOMEM;
d1ac91d8 3235 if (!u.xsave)
2d5b5a66
SY		 3236 break;
3237
d1ac91d8 3238 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3239
3240 r = -EFAULT;
d1ac91d8 3241 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3242 break;
3243 r = 0;
3244 break;
3245 }
3246 case KVM_SET_XSAVE: {
ff5c2c03 3247 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3248 if (IS_ERR(u.xsave))
3249 return PTR_ERR(u.xsave);
2d5b5a66 3250
d1ac91d8 3251 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3252 break;
3253 }
3254 case KVM_GET_XCRS: {
d1ac91d8 3255 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3256 r = -ENOMEM;
d1ac91d8 3257 if (!u.xcrs)
2d5b5a66
SY		 3258 break;
3259
d1ac91d8 3260 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3261
3262 r = -EFAULT;
d1ac91d8 3263 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3264 sizeof(struct kvm_xcrs)))
3265 break;
3266 r = 0;
3267 break;
3268 }
3269 case KVM_SET_XCRS: {
ff5c2c03 3270 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3271 if (IS_ERR(u.xcrs))
3272 return PTR_ERR(u.xcrs);
2d5b5a66 3273
d1ac91d8 3274 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3275 break;
3276 }
92a1f12d
JR		 3277 case KVM_SET_TSC_KHZ: {
3278 u32 user_tsc_khz;
3279
3280 r = -EINVAL;
92a1f12d
JR		 3281 user_tsc_khz = (u32)arg;
3282
3283 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3284 goto out;
3285
cc578287
ZA		 3286 if (user_tsc_khz == 0)
3287 user_tsc_khz = tsc_khz;
3288
3289 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3290
3291 r = 0;
3292 goto out;
3293 }
3294 case KVM_GET_TSC_KHZ: {
cc578287 3295 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3296 goto out;
3297 }
1c0b28c2
EM		 3298 case KVM_KVMCLOCK_CTRL: {
3299 r = kvm_set_guest_paused(vcpu);
3300 goto out;
3301 }
313a3dc7
CO		 3302 default:
3303 r = -EINVAL;
3304 }
3305out:
d1ac91d8 3306 kfree(u.buffer);
313a3dc7
CO		 3307 return r;
3308}
3309
5b1c1493
CO		 3310int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3311{
3312 return VM_FAULT_SIGBUS;
3313}
3314
1fe779f8
CO		 3315static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3316{
3317 int ret;
3318
3319 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3320 return -EINVAL;
1fe779f8
CO		 3321 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3322 return ret;
3323}
3324
b927a3ce
SY		 3325static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3326 u64 ident_addr)
3327{
3328 kvm->arch.ept_identity_map_addr = ident_addr;
3329 return 0;
3330}
3331
1fe779f8
CO		 3332static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3333 u32 kvm_nr_mmu_pages)
3334{
3335 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3336 return -EINVAL;
3337
79fac95e 3338 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3339
3340 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3341 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3342
79fac95e 3343 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3344 return 0;
3345}
3346
3347static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3348{
39de71ec 3349 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3350}
3351
1fe779f8
CO		 3352static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3353{
3354 int r;
3355
3356 r = 0;
3357 switch (chip->chip_id) {
3358 case KVM_IRQCHIP_PIC_MASTER:
3359 memcpy(&chip->chip.pic,
3360 &pic_irqchip(kvm)->pics[0],
3361 sizeof(struct kvm_pic_state));
3362 break;
3363 case KVM_IRQCHIP_PIC_SLAVE:
3364 memcpy(&chip->chip.pic,
3365 &pic_irqchip(kvm)->pics[1],
3366 sizeof(struct kvm_pic_state));
3367 break;
3368 case KVM_IRQCHIP_IOAPIC:
eba0226b 3369 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3370 break;
3371 default:
3372 r = -EINVAL;
3373 break;
3374 }
3375 return r;
3376}
3377
3378static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3379{
3380 int r;
3381
3382 r = 0;
3383 switch (chip->chip_id) {
3384 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3385 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3386 memcpy(&pic_irqchip(kvm)->pics[0],
3387 &chip->chip.pic,
3388 sizeof(struct kvm_pic_state));
f4f51050 3389 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3390 break;
3391 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3392 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3393 memcpy(&pic_irqchip(kvm)->pics[1],
3394 &chip->chip.pic,
3395 sizeof(struct kvm_pic_state));
f4f51050 3396 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3397 break;
3398 case KVM_IRQCHIP_IOAPIC:
eba0226b 3399 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3400 break;
3401 default:
3402 r = -EINVAL;
3403 break;
3404 }
3405 kvm_pic_update_irq(pic_irqchip(kvm));
3406 return r;
3407}
3408
e0f63cb9
SY		 3409static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3410{
3411 int r = 0;
3412
894a9c55 3413 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3414 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3415 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3416 return r;
3417}
3418
3419static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3420{
3421 int r = 0;
3422
894a9c55 3423 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3424 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3425 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3426 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3427 return r;
3428}
3429
3430static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3431{
3432 int r = 0;
3433
3434 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3435 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3436 sizeof(ps->channels));
3437 ps->flags = kvm->arch.vpit->pit_state.flags;
3438 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3439 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3440 return r;
3441}
3442
3443static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3444{
3445 int r = 0, start = 0;
3446 u32 prev_legacy, cur_legacy;
3447 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3448 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3449 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3450 if (!prev_legacy && cur_legacy)
3451 start = 1;
3452 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3453 sizeof(kvm->arch.vpit->pit_state.channels));
3454 kvm->arch.vpit->pit_state.flags = ps->flags;
3455 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3456 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3457 return r;
3458}
3459
52d939a0
MT		 3460static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3461 struct kvm_reinject_control *control)
3462{
3463 if (!kvm->arch.vpit)
3464 return -ENXIO;
894a9c55 3465 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3466 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3467 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3468 return 0;
3469}
3470
95d4c16c 3471/**
60c34612
TY		 3472 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3473 * @kvm: kvm instance
3474 * @log: slot id and address to which we copy the log
95d4c16c 3475 *
60c34612
TY		 3476 * We need to keep it in mind that VCPU threads can write to the bitmap
3477 * concurrently. So, to avoid losing data, we keep the following order for
3478 * each bit:
95d4c16c 3479 *
60c34612
TY		 3480 * 1. Take a snapshot of the bit and clear it if needed.
3481 * 2. Write protect the corresponding page.
3482 * 3. Flush TLB's if needed.
3483 * 4. Copy the snapshot to the userspace.
95d4c16c 3484 *
60c34612
TY		 3485 * Between 2 and 3, the guest may write to the page using the remaining TLB
3486 * entry. This is not a problem because the page will be reported dirty at
3487 * step 4 using the snapshot taken before and step 3 ensures that successive
3488 * writes will be logged for the next call.
5bb064dc 3489 */
60c34612 3490int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3491{
7850ac54 3492 int r;
5bb064dc 3493 struct kvm_memory_slot *memslot;
60c34612
TY		 3494 unsigned long n, i;
3495 unsigned long *dirty_bitmap;
3496 unsigned long *dirty_bitmap_buffer;
3497 bool is_dirty = false;
5bb064dc 3498
79fac95e 3499 mutex_lock(&kvm->slots_lock);
5bb064dc 3500
b050b015 3501 r = -EINVAL;
bbacc0c1 3502 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3503 goto out;
3504
28a37544 3505 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3506
3507 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3508 r = -ENOENT;
60c34612 3509 if (!dirty_bitmap)
b050b015
MT		 3510 goto out;
3511
87bf6e7d 3512 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3513
60c34612
TY		 3514 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3515 memset(dirty_bitmap_buffer, 0, n);
b050b015 3516
60c34612 3517 spin_lock(&kvm->mmu_lock);
b050b015 3518
60c34612
TY		 3519 for (i = 0; i < n / sizeof(long); i++) {
3520 unsigned long mask;
3521 gfn_t offset;
cdfca7b3 3522
60c34612
TY		 3523 if (!dirty_bitmap[i])
3524 continue;
b050b015 3525
60c34612 3526 is_dirty = true;
914ebccd 3527
60c34612
TY		 3528 mask = xchg(&dirty_bitmap[i], 0);
3529 dirty_bitmap_buffer[i] = mask;
edde99ce 3530
60c34612
TY		 3531 offset = i * BITS_PER_LONG;
3532 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3533 }
60c34612
TY		 3534 if (is_dirty)
3535 kvm_flush_remote_tlbs(kvm);
3536
3537 spin_unlock(&kvm->mmu_lock);
3538
3539 r = -EFAULT;
3540 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3541 goto out;
b050b015 3542
5bb064dc
ZX		 3543 r = 0;
3544out:
79fac95e 3545 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3546 return r;
3547}
3548
aa2fbe6d
YZ		 3549int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3550 bool line_status)
23d43cf9
CD		 3551{
3552 if (!irqchip_in_kernel(kvm))
3553 return -ENXIO;
3554
3555 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3556 irq_event->irq, irq_event->level,
3557 line_status);
23d43cf9
CD		 3558 return 0;
3559}
3560
1fe779f8
CO		 3561long kvm_arch_vm_ioctl(struct file *filp,
3562 unsigned int ioctl, unsigned long arg)
3563{
3564 struct kvm *kvm = filp->private_data;
3565 void __user *argp = (void __user *)arg;
367e1319 3566 int r = -ENOTTY;
f0d66275
DH		 3567 /*
3568 * This union makes it completely explicit to gcc-3.x
3569 * that these two variables' stack usage should be
3570 * combined, not added together.
3571 */
3572 union {
3573 struct kvm_pit_state ps;
e9f42757 3574 struct kvm_pit_state2 ps2;
c5ff41ce 3575 struct kvm_pit_config pit_config;
f0d66275 3576 } u;
1fe779f8
CO		 3577
3578 switch (ioctl) {
3579 case KVM_SET_TSS_ADDR:
3580 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3581 break;
b927a3ce
SY		 3582 case KVM_SET_IDENTITY_MAP_ADDR: {
3583 u64 ident_addr;
3584
3585 r = -EFAULT;
3586 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3587 goto out;
3588 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3589 break;
3590 }
1fe779f8
CO		 3591 case KVM_SET_NR_MMU_PAGES:
3592 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3593 break;
3594 case KVM_GET_NR_MMU_PAGES:
3595 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3596 break;
3ddea128
MT		 3597 case KVM_CREATE_IRQCHIP: {
3598 struct kvm_pic *vpic;
3599
3600 mutex_lock(&kvm->lock);
3601 r = -EEXIST;
3602 if (kvm->arch.vpic)
3603 goto create_irqchip_unlock;
3e515705
AK		 3604 r = -EINVAL;
3605 if (atomic_read(&kvm->online_vcpus))
3606 goto create_irqchip_unlock;
1fe779f8 3607 r = -ENOMEM;
3ddea128
MT		 3608 vpic = kvm_create_pic(kvm);
3609 if (vpic) {
1fe779f8
CO		 3610 r = kvm_ioapic_init(kvm);
3611 if (r) {
175504cd 3612 mutex_lock(&kvm->slots_lock);
72bb2fcd 3613 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3614 &vpic->dev_master);
3615 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3616 &vpic->dev_slave);
3617 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3618 &vpic->dev_eclr);
175504cd 3619 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3620 kfree(vpic);
3621 goto create_irqchip_unlock;
1fe779f8
CO		 3622 }
3623 } else
3ddea128
MT		 3624 goto create_irqchip_unlock;
3625 smp_wmb();
3626 kvm->arch.vpic = vpic;
3627 smp_wmb();
399ec807
AK		 3628 r = kvm_setup_default_irq_routing(kvm);
3629 if (r) {
175504cd 3630 mutex_lock(&kvm->slots_lock);
3ddea128 3631 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3632 kvm_ioapic_destroy(kvm);
3633 kvm_destroy_pic(kvm);
3ddea128 3634 mutex_unlock(&kvm->irq_lock);
175504cd 3635 mutex_unlock(&kvm->slots_lock);
399ec807 3636 }
3ddea128
MT		 3637 create_irqchip_unlock:
3638 mutex_unlock(&kvm->lock);
1fe779f8 3639 break;
3ddea128 3640 }
7837699f 3641 case KVM_CREATE_PIT:
c5ff41ce
JK		 3642 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3643 goto create_pit;
3644 case KVM_CREATE_PIT2:
3645 r = -EFAULT;
3646 if (copy_from_user(&u.pit_config, argp,
3647 sizeof(struct kvm_pit_config)))
3648 goto out;
3649 create_pit:
79fac95e 3650 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3651 r = -EEXIST;
3652 if (kvm->arch.vpit)
3653 goto create_pit_unlock;
7837699f 3654 r = -ENOMEM;
c5ff41ce 3655 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3656 if (kvm->arch.vpit)
3657 r = 0;
269e05e4 3658 create_pit_unlock:
79fac95e 3659 mutex_unlock(&kvm->slots_lock);
7837699f 3660 break;
1fe779f8
CO		 3661 case KVM_GET_IRQCHIP: {
3662 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3663 struct kvm_irqchip *chip;
1fe779f8 3664
ff5c2c03
SL		 3665 chip = memdup_user(argp, sizeof(*chip));
3666 if (IS_ERR(chip)) {
3667 r = PTR_ERR(chip);
1fe779f8 3668 goto out;
ff5c2c03
SL		 3669 }
3670
1fe779f8
CO		 3671 r = -ENXIO;
3672 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3673 goto get_irqchip_out;
3674 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3675 if (r)
f0d66275 3676 goto get_irqchip_out;
1fe779f8 3677 r = -EFAULT;
f0d66275
DH		 3678 if (copy_to_user(argp, chip, sizeof *chip))
3679 goto get_irqchip_out;
1fe779f8 3680 r = 0;
f0d66275
DH		 3681 get_irqchip_out:
3682 kfree(chip);
1fe779f8
CO		 3683 break;
3684 }
3685 case KVM_SET_IRQCHIP: {
3686 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3687 struct kvm_irqchip *chip;
1fe779f8 3688
ff5c2c03
SL		 3689 chip = memdup_user(argp, sizeof(*chip));
3690 if (IS_ERR(chip)) {
3691 r = PTR_ERR(chip);
1fe779f8 3692 goto out;
ff5c2c03
SL		 3693 }
3694
1fe779f8
CO		 3695 r = -ENXIO;
3696 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3697 goto set_irqchip_out;
3698 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3699 if (r)
f0d66275 3700 goto set_irqchip_out;
1fe779f8 3701 r = 0;
f0d66275
DH		 3702 set_irqchip_out:
3703 kfree(chip);
1fe779f8
CO		 3704 break;
3705 }
e0f63cb9 3706 case KVM_GET_PIT: {
e0f63cb9 3707 r = -EFAULT;
f0d66275 3708 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3709 goto out;
3710 r = -ENXIO;
3711 if (!kvm->arch.vpit)
3712 goto out;
f0d66275 3713 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3714 if (r)
3715 goto out;
3716 r = -EFAULT;
f0d66275 3717 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3718 goto out;
3719 r = 0;
3720 break;
3721 }
3722 case KVM_SET_PIT: {
e0f63cb9 3723 r = -EFAULT;
f0d66275 3724 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3725 goto out;
3726 r = -ENXIO;
3727 if (!kvm->arch.vpit)
3728 goto out;
f0d66275 3729 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3730 break;
3731 }
e9f42757
BK		 3732 case KVM_GET_PIT2: {
3733 r = -ENXIO;
3734 if (!kvm->arch.vpit)
3735 goto out;
3736 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3737 if (r)
3738 goto out;
3739 r = -EFAULT;
3740 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3741 goto out;
3742 r = 0;
3743 break;
3744 }
3745 case KVM_SET_PIT2: {
3746 r = -EFAULT;
3747 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3748 goto out;
3749 r = -ENXIO;
3750 if (!kvm->arch.vpit)
3751 goto out;
3752 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3753 break;
3754 }
52d939a0
MT		 3755 case KVM_REINJECT_CONTROL: {
3756 struct kvm_reinject_control control;
3757 r = -EFAULT;
3758 if (copy_from_user(&control, argp, sizeof(control)))
3759 goto out;
3760 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3761 break;
3762 }
ffde22ac
ES		 3763 case KVM_XEN_HVM_CONFIG: {
3764 r = -EFAULT;
3765 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3766 sizeof(struct kvm_xen_hvm_config)))
3767 goto out;
3768 r = -EINVAL;
3769 if (kvm->arch.xen_hvm_config.flags)
3770 goto out;
3771 r = 0;
3772 break;
3773 }
afbcf7ab 3774 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3775 struct kvm_clock_data user_ns;
3776 u64 now_ns;
3777 s64 delta;
3778
3779 r = -EFAULT;
3780 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3781 goto out;
3782
3783 r = -EINVAL;
3784 if (user_ns.flags)
3785 goto out;
3786
3787 r = 0;
395c6b0a 3788 local_irq_disable();
759379dd 3789 now_ns = get_kernel_ns();
afbcf7ab 3790 delta = user_ns.clock - now_ns;
395c6b0a 3791 local_irq_enable();
afbcf7ab
GC		 3792 kvm->arch.kvmclock_offset = delta;
3793 break;
3794 }
3795 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3796 struct kvm_clock_data user_ns;
3797 u64 now_ns;
3798
395c6b0a 3799 local_irq_disable();
759379dd 3800 now_ns = get_kernel_ns();
afbcf7ab 3801 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3802 local_irq_enable();
afbcf7ab 3803 user_ns.flags = 0;
97e69aa6 3804 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3805
3806 r = -EFAULT;
3807 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3808 goto out;
3809 r = 0;
3810 break;
3811 }
3812
1fe779f8
CO		 3813 default:
3814 ;
3815 }
3816out:
3817 return r;
3818}
3819
a16b043c 3820static void kvm_init_msr_list(void)
043405e1
CO		 3821{
3822 u32 dummy[2];
3823 unsigned i, j;
3824
e3267cbb
GC		 3825 /* skip the first msrs in the list. KVM-specific */
3826 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3827 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3828 continue;
3829 if (j < i)
3830 msrs_to_save[j] = msrs_to_save[i];
3831 j++;
3832 }
3833 num_msrs_to_save = j;
3834}
3835
bda9020e
MT		 3836static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3837 const void *v)
bbd9b64e 3838{
70252a10
AK		 3839 int handled = 0;
3840 int n;
3841
3842 do {
3843 n = min(len, 8);
3844 if (!(vcpu->arch.apic &&
3845 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3846 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3847 break;
3848 handled += n;
3849 addr += n;
3850 len -= n;
3851 v += n;
3852 } while (len);
bbd9b64e 3853
70252a10 3854 return handled;
bbd9b64e
CO		 3855}
3856
bda9020e 3857static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3858{
70252a10
AK		 3859 int handled = 0;
3860 int n;
3861
3862 do {
3863 n = min(len, 8);
3864 if (!(vcpu->arch.apic &&
3865 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3866 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3867 break;
3868 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3869 handled += n;
3870 addr += n;
3871 len -= n;
3872 v += n;
3873 } while (len);
bbd9b64e 3874
70252a10 3875 return handled;
bbd9b64e
CO		 3876}
3877
2dafc6c2
GN		 3878static void kvm_set_segment(struct kvm_vcpu *vcpu,
3879 struct kvm_segment *var, int seg)
3880{
3881 kvm_x86_ops->set_segment(vcpu, var, seg);
3882}
3883
3884void kvm_get_segment(struct kvm_vcpu *vcpu,
3885 struct kvm_segment *var, int seg)
3886{
3887 kvm_x86_ops->get_segment(vcpu, var, seg);
3888}
3889
e459e322 3890gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3891{
3892 gpa_t t_gpa;
ab9ae313 3893 struct x86_exception exception;
02f59dc9
JR		 3894
3895 BUG_ON(!mmu_is_nested(vcpu));
3896
3897 /* NPT walks are always user-walks */
3898 access |= PFERR_USER_MASK;
ab9ae313 3899 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3900
3901 return t_gpa;
3902}
3903
ab9ae313
AK		 3904gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3905 struct x86_exception *exception)
1871c602
GN		 3906{
3907 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3908 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3909}
3910
ab9ae313
AK		 3911 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3912 struct x86_exception *exception)
1871c602
GN		 3913{
3914 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3915 access |= PFERR_FETCH_MASK;
ab9ae313 3916 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3917}
3918
ab9ae313
AK		 3919gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3920 struct x86_exception *exception)
1871c602
GN		 3921{
3922 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3923 access |= PFERR_WRITE_MASK;
ab9ae313 3924 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3925}
3926
3927/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3928gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3929 struct x86_exception *exception)
1871c602 3930{
ab9ae313 3931 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3932}
3933
3934static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3935 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3936 struct x86_exception *exception)
bbd9b64e
CO		 3937{
3938 void *data = val;
10589a46 3939 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3940
3941 while (bytes) {
14dfe855 3942 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3943 exception);
bbd9b64e 3944 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3945 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3946 int ret;
3947
bcc55cba 3948 if (gpa == UNMAPPED_GVA)
ab9ae313 3949 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3950 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3951 if (ret < 0) {
c3cd7ffa 3952 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3953 goto out;
3954 }
bbd9b64e 3955
77c2002e
IE		 3956 bytes -= toread;
3957 data += toread;
3958 addr += toread;
bbd9b64e 3959 }
10589a46 3960out:
10589a46 3961 return r;
bbd9b64e 3962}
77c2002e 3963
1871c602 3964/* used for instruction fetching */
0f65dd70
AK		 3965static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3966 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3967 struct x86_exception *exception)
1871c602 3968{
0f65dd70 3969 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3970 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3971
1871c602 3972 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3973 access | PFERR_FETCH_MASK,
3974 exception);
1871c602
GN		 3975}
3976
064aea77 3977int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3978 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3979 struct x86_exception *exception)
1871c602 3980{
0f65dd70 3981 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3982 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3983
1871c602 3984 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3985 exception);
1871c602 3986}
064aea77 3987EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3988
0f65dd70
AK		 3989static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3990 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3991 struct x86_exception *exception)
1871c602 3992{
0f65dd70 3993 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3994 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3995}
3996
6a4d7550 3997int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3998 gva_t addr, void *val,
2dafc6c2 3999 unsigned int bytes,
bcc55cba 4000 struct x86_exception *exception)
77c2002e 4001{
0f65dd70 4002 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4003 void *data = val;
4004 int r = X86EMUL_CONTINUE;
4005
4006 while (bytes) {
14dfe855
JR		 4007 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4008 PFERR_WRITE_MASK,
ab9ae313 4009 exception);
77c2002e
IE		 4010 unsigned offset = addr & (PAGE_SIZE-1);
4011 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4012 int ret;
4013
bcc55cba 4014 if (gpa == UNMAPPED_GVA)
ab9ae313 4015 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4016 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4017 if (ret < 0) {
c3cd7ffa 4018 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4019 goto out;
4020 }
4021
4022 bytes -= towrite;
4023 data += towrite;
4024 addr += towrite;
4025 }
4026out:
4027 return r;
4028}
6a4d7550 4029EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4030
af7cc7d1
XG		 4031static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4032 gpa_t *gpa, struct x86_exception *exception,
4033 bool write)
4034{
97d64b78
AK		 4035 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4036 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4037
97d64b78
AK		 4038 if (vcpu_match_mmio_gva(vcpu, gva)
4039 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4040 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4041 (gva & (PAGE_SIZE - 1));
4f022648 4042 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4043 return 1;
4044 }
4045
af7cc7d1
XG		 4046 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4047
4048 if (*gpa == UNMAPPED_GVA)
4049 return -1;
4050
4051 /* For APIC access vmexit */
4052 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4053 return 1;
4054
4f022648
XG		 4055 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4056 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4057 return 1;
4f022648 4058 }
bebb106a 4059
af7cc7d1
XG		 4060 return 0;
4061}
4062
3200f405 4063int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4064 const void *val, int bytes)
bbd9b64e
CO		 4065{
4066 int ret;
4067
4068 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4069 if (ret < 0)
bbd9b64e 4070 return 0;
f57f2ef5 4071 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4072 return 1;
4073}
4074
77d197b2
XG		 4075struct read_write_emulator_ops {
4076 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4077 int bytes);
4078 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4079 void *val, int bytes);
4080 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4081 int bytes, void *val);
4082 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4083 void *val, int bytes);
4084 bool write;
4085};
4086
4087static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4088{
4089 if (vcpu->mmio_read_completed) {
77d197b2 4090 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4091 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4092 vcpu->mmio_read_completed = 0;
4093 return 1;
4094 }
4095
4096 return 0;
4097}
4098
4099static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4100 void *val, int bytes)
4101{
4102 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4103}
4104
4105static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4106 void *val, int bytes)
4107{
4108 return emulator_write_phys(vcpu, gpa, val, bytes);
4109}
4110
4111static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4112{
4113 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4114 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4115}
4116
4117static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4118 void *val, int bytes)
4119{
4120 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4121 return X86EMUL_IO_NEEDED;
4122}
4123
4124static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4125 void *val, int bytes)
4126{
f78146b0
AK		 4127 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4128
87da7e66 4129 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4130 return X86EMUL_CONTINUE;
4131}
4132
0fbe9b0b 4133static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4134 .read_write_prepare = read_prepare,
4135 .read_write_emulate = read_emulate,
4136 .read_write_mmio = vcpu_mmio_read,
4137 .read_write_exit_mmio = read_exit_mmio,
4138};
4139
0fbe9b0b 4140static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4141 .read_write_emulate = write_emulate,
4142 .read_write_mmio = write_mmio,
4143 .read_write_exit_mmio = write_exit_mmio,
4144 .write = true,
4145};
4146
22388a3c
XG		 4147static int emulator_read_write_onepage(unsigned long addr, void *val,
4148 unsigned int bytes,
4149 struct x86_exception *exception,
4150 struct kvm_vcpu *vcpu,
0fbe9b0b 4151 const struct read_write_emulator_ops *ops)
bbd9b64e 4152{
af7cc7d1
XG		 4153 gpa_t gpa;
4154 int handled, ret;
22388a3c 4155 bool write = ops->write;
f78146b0 4156 struct kvm_mmio_fragment *frag;
10589a46 4157
22388a3c 4158 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4159
af7cc7d1 4160 if (ret < 0)
bbd9b64e 4161 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4162
4163 /* For APIC access vmexit */
af7cc7d1 4164 if (ret)
bbd9b64e
CO		 4165 goto mmio;
4166
22388a3c 4167 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4168 return X86EMUL_CONTINUE;
4169
4170mmio:
4171 /*
4172 * Is this MMIO handled locally?
4173 */
22388a3c 4174 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4175 if (handled == bytes)
bbd9b64e 4176 return X86EMUL_CONTINUE;
bbd9b64e 4177
70252a10
AK		 4178 gpa += handled;
4179 bytes -= handled;
4180 val += handled;
4181
87da7e66
XG		 4182 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4183 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4184 frag->gpa = gpa;
4185 frag->data = val;
4186 frag->len = bytes;
f78146b0 4187 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4188}
4189
22388a3c
XG		 4190int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4191 void *val, unsigned int bytes,
4192 struct x86_exception *exception,
0fbe9b0b 4193 const struct read_write_emulator_ops *ops)
bbd9b64e 4194{
0f65dd70 4195 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4196 gpa_t gpa;
4197 int rc;
4198
4199 if (ops->read_write_prepare &&
4200 ops->read_write_prepare(vcpu, val, bytes))
4201 return X86EMUL_CONTINUE;
4202
4203 vcpu->mmio_nr_fragments = 0;
0f65dd70 4204
bbd9b64e
CO		 4205 /* Crossing a page boundary? */
4206 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4207 int now;
bbd9b64e
CO		 4208
4209 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4210 rc = emulator_read_write_onepage(addr, val, now, exception,
4211 vcpu, ops);
4212
bbd9b64e
CO		 4213 if (rc != X86EMUL_CONTINUE)
4214 return rc;
4215 addr += now;
4216 val += now;
4217 bytes -= now;
4218 }
22388a3c 4219
f78146b0
AK		 4220 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4221 vcpu, ops);
4222 if (rc != X86EMUL_CONTINUE)
4223 return rc;
4224
4225 if (!vcpu->mmio_nr_fragments)
4226 return rc;
4227
4228 gpa = vcpu->mmio_fragments[0].gpa;
4229
4230 vcpu->mmio_needed = 1;
4231 vcpu->mmio_cur_fragment = 0;
4232
87da7e66 4233 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4234 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4235 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4236 vcpu->run->mmio.phys_addr = gpa;
4237
4238 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4239}
4240
4241static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4242 unsigned long addr,
4243 void *val,
4244 unsigned int bytes,
4245 struct x86_exception *exception)
4246{
4247 return emulator_read_write(ctxt, addr, val, bytes,
4248 exception, &read_emultor);
4249}
4250
4251int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4252 unsigned long addr,
4253 const void *val,
4254 unsigned int bytes,
4255 struct x86_exception *exception)
4256{
4257 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4258 exception, &write_emultor);
bbd9b64e 4259}
bbd9b64e 4260
daea3e73
AK		 4261#define CMPXCHG_TYPE(t, ptr, old, new) \
4262 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4263
4264#ifdef CONFIG_X86_64
4265# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4266#else
4267# define CMPXCHG64(ptr, old, new) \
9749a6c0 4268 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4269#endif
4270
0f65dd70
AK		 4271static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4272 unsigned long addr,
bbd9b64e
CO		 4273 const void *old,
4274 const void *new,
4275 unsigned int bytes,
0f65dd70 4276 struct x86_exception *exception)
bbd9b64e 4277{
0f65dd70 4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4279 gpa_t gpa;
4280 struct page *page;
4281 char *kaddr;
4282 bool exchanged;
2bacc55c 4283
daea3e73
AK		 4284 /* guests cmpxchg8b have to be emulated atomically */
4285 if (bytes > 8 || (bytes & (bytes - 1)))
4286 goto emul_write;
10589a46 4287
daea3e73 4288 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4289
daea3e73
AK		 4290 if (gpa == UNMAPPED_GVA ||
4291 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4292 goto emul_write;
2bacc55c 4293
daea3e73
AK		 4294 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4295 goto emul_write;
72dc67a6 4296
daea3e73 4297 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4298 if (is_error_page(page))
c19b8bd6 4299 goto emul_write;
72dc67a6 4300
8fd75e12 4301 kaddr = kmap_atomic(page);
daea3e73
AK		 4302 kaddr += offset_in_page(gpa);
4303 switch (bytes) {
4304 case 1:
4305 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4306 break;
4307 case 2:
4308 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4309 break;
4310 case 4:
4311 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4312 break;
4313 case 8:
4314 exchanged = CMPXCHG64(kaddr, old, new);
4315 break;
4316 default:
4317 BUG();
2bacc55c 4318 }
8fd75e12 4319 kunmap_atomic(kaddr);
daea3e73
AK		 4320 kvm_release_page_dirty(page);
4321
4322 if (!exchanged)
4323 return X86EMUL_CMPXCHG_FAILED;
4324
f57f2ef5 4325 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4326
4327 return X86EMUL_CONTINUE;
4a5f48f6 4328
3200f405 4329emul_write:
daea3e73 4330 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4331
0f65dd70 4332 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4333}
4334
cf8f70bf
GN		 4335static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4336{
4337 /* TODO: String I/O for in kernel device */
4338 int r;
4339
4340 if (vcpu->arch.pio.in)
4341 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4342 vcpu->arch.pio.size, pd);
4343 else
4344 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4345 vcpu->arch.pio.port, vcpu->arch.pio.size,
4346 pd);
4347 return r;
4348}
4349
6f6fbe98
XG		 4350static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4351 unsigned short port, void *val,
4352 unsigned int count, bool in)
cf8f70bf 4353{
6f6fbe98 4354 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4355
4356 vcpu->arch.pio.port = port;
6f6fbe98 4357 vcpu->arch.pio.in = in;
7972995b 4358 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4359 vcpu->arch.pio.size = size;
4360
4361 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4362 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4363 return 1;
4364 }
4365
4366 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4367 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4368 vcpu->run->io.size = size;
4369 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4370 vcpu->run->io.count = count;
4371 vcpu->run->io.port = port;
4372
4373 return 0;
4374}
4375
6f6fbe98
XG		 4376static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4377 int size, unsigned short port, void *val,
4378 unsigned int count)
cf8f70bf 4379{
ca1d4a9e 4380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4381 int ret;
ca1d4a9e 4382
6f6fbe98
XG		 4383 if (vcpu->arch.pio.count)
4384 goto data_avail;
cf8f70bf 4385
6f6fbe98
XG		 4386 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4387 if (ret) {
4388data_avail:
4389 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4390 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4391 return 1;
4392 }
4393
cf8f70bf
GN		 4394 return 0;
4395}
4396
6f6fbe98
XG		 4397static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4398 int size, unsigned short port,
4399 const void *val, unsigned int count)
4400{
4401 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4402
4403 memcpy(vcpu->arch.pio_data, val, size * count);
4404 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4405}
4406
bbd9b64e
CO		 4407static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4408{
4409 return kvm_x86_ops->get_segment_base(vcpu, seg);
4410}
4411
3cb16fe7 4412static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4413{
3cb16fe7 4414 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4415}
4416
f5f48ee1
SY		 4417int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4418{
4419 if (!need_emulate_wbinvd(vcpu))
4420 return X86EMUL_CONTINUE;
4421
4422 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4423 int cpu = get_cpu();
4424
4425 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4426 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4427 wbinvd_ipi, NULL, 1);
2eec7343 4428 put_cpu();
f5f48ee1 4429 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4430 } else
4431 wbinvd();
f5f48ee1
SY		 4432 return X86EMUL_CONTINUE;
4433}
4434EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4435
bcaf5cc5
AK		 4436static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4437{
4438 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4439}
4440
717746e3 4441int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4442{
717746e3 4443 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4444}
4445
717746e3 4446int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4447{
338dbc97 4448
717746e3 4449 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4450}
4451
52a46617 4452static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4453{
52a46617 4454 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4455}
4456
717746e3 4457static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4458{
717746e3 4459 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4460 unsigned long value;
4461
4462 switch (cr) {
4463 case 0:
4464 value = kvm_read_cr0(vcpu);
4465 break;
4466 case 2:
4467 value = vcpu->arch.cr2;
4468 break;
4469 case 3:
9f8fe504 4470 value = kvm_read_cr3(vcpu);
52a46617
GN		 4471 break;
4472 case 4:
4473 value = kvm_read_cr4(vcpu);
4474 break;
4475 case 8:
4476 value = kvm_get_cr8(vcpu);
4477 break;
4478 default:
a737f256 4479 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4480 return 0;
4481 }
4482
4483 return value;
4484}
4485
717746e3 4486static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4487{
717746e3 4488 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4489 int res = 0;
4490
52a46617
GN		 4491 switch (cr) {
4492 case 0:
49a9b07e 4493 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4494 break;
4495 case 2:
4496 vcpu->arch.cr2 = val;
4497 break;
4498 case 3:
2390218b 4499 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4500 break;
4501 case 4:
a83b29c6 4502 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4503 break;
4504 case 8:
eea1cff9 4505 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4506 break;
4507 default:
a737f256 4508 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4509 res = -1;
52a46617 4510 }
0f12244f
GN		 4511
4512 return res;
52a46617
GN		 4513}
4514
4cee4798
KW		 4515static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4516{
4517 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4518}
4519
717746e3 4520static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4521{
717746e3 4522 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4523}
4524
4bff1e86 4525static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4526{
4bff1e86 4527 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4528}
4529
4bff1e86 4530static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4531{
4bff1e86 4532 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4533}
4534
1ac9d0cf
AK		 4535static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4536{
4537 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4538}
4539
4540static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4541{
4542 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4543}
4544
4bff1e86
AK		 4545static unsigned long emulator_get_cached_segment_base(
4546 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4547{
4bff1e86 4548 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4549}
4550
1aa36616
AK		 4551static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4552 struct desc_struct *desc, u32 *base3,
4553 int seg)
2dafc6c2
GN		 4554{
4555 struct kvm_segment var;
4556
4bff1e86 4557 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4558 *selector = var.selector;
2dafc6c2 4559
378a8b09
GN		 4560 if (var.unusable) {
4561 memset(desc, 0, sizeof(*desc));
2dafc6c2 4562 return false;
378a8b09 4563 }
2dafc6c2
GN		 4564
4565 if (var.g)
4566 var.limit >>= 12;
4567 set_desc_limit(desc, var.limit);
4568 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4569#ifdef CONFIG_X86_64
4570 if (base3)
4571 *base3 = var.base >> 32;
4572#endif
2dafc6c2
GN		 4573 desc->type = var.type;
4574 desc->s = var.s;
4575 desc->dpl = var.dpl;
4576 desc->p = var.present;
4577 desc->avl = var.avl;
4578 desc->l = var.l;
4579 desc->d = var.db;
4580 desc->g = var.g;
4581
4582 return true;
4583}
4584
1aa36616
AK		 4585static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4586 struct desc_struct *desc, u32 base3,
4587 int seg)
2dafc6c2 4588{
4bff1e86 4589 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4590 struct kvm_segment var;
4591
1aa36616 4592 var.selector = selector;
2dafc6c2 4593 var.base = get_desc_base(desc);
5601d05b
GN		 4594#ifdef CONFIG_X86_64
4595 var.base |= ((u64)base3) << 32;
4596#endif
2dafc6c2
GN		 4597 var.limit = get_desc_limit(desc);
4598 if (desc->g)
4599 var.limit = (var.limit << 12) | 0xfff;
4600 var.type = desc->type;
4601 var.present = desc->p;
4602 var.dpl = desc->dpl;
4603 var.db = desc->d;
4604 var.s = desc->s;
4605 var.l = desc->l;
4606 var.g = desc->g;
4607 var.avl = desc->avl;
4608 var.present = desc->p;
4609 var.unusable = !var.present;
4610 var.padding = 0;
4611
4612 kvm_set_segment(vcpu, &var, seg);
4613 return;
4614}
4615
717746e3
AK		 4616static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4617 u32 msr_index, u64 *pdata)
4618{
4619 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4620}
4621
4622static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4623 u32 msr_index, u64 data)
4624{
8fe8ab46
WA		 4625 struct msr_data msr;
4626
4627 msr.data = data;
4628 msr.index = msr_index;
4629 msr.host_initiated = false;
4630 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4631}
4632
222d21aa
AK		 4633static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4634 u32 pmc, u64 *pdata)
4635{
4636 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4637}
4638
6c3287f7
AK		 4639static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4640{
4641 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4642}
4643
5037f6f3
AK		 4644static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4645{
4646 preempt_disable();
5197b808 4647 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4648 /*
4649 * CR0.TS may reference the host fpu state, not the guest fpu state,
4650 * so it may be clear at this point.
4651 */
4652 clts();
4653}
4654
4655static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4656{
4657 preempt_enable();
4658}
4659
2953538e 4660static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4661 struct x86_instruction_info *info,
c4f035c6
AK		 4662 enum x86_intercept_stage stage)
4663{
2953538e 4664 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4665}
4666
0017f93a 4667static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4668 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4669{
0017f93a 4670 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4671}
4672
dd856efa
AK		 4673static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4674{
4675 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4676}
4677
4678static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4679{
4680 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4681}
4682
0225fb50 4683static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4684 .read_gpr = emulator_read_gpr,
4685 .write_gpr = emulator_write_gpr,
1871c602 4686 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4687 .write_std = kvm_write_guest_virt_system,
1871c602 4688 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4689 .read_emulated = emulator_read_emulated,
4690 .write_emulated = emulator_write_emulated,
4691 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4692 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4693 .pio_in_emulated = emulator_pio_in_emulated,
4694 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4695 .get_segment = emulator_get_segment,
4696 .set_segment = emulator_set_segment,
5951c442 4697 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4698 .get_gdt = emulator_get_gdt,
160ce1f1 4699 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4700 .set_gdt = emulator_set_gdt,
4701 .set_idt = emulator_set_idt,
52a46617
GN		 4702 .get_cr = emulator_get_cr,
4703 .set_cr = emulator_set_cr,
4cee4798 4704 .set_rflags = emulator_set_rflags,
9c537244 4705 .cpl = emulator_get_cpl,
35aa5375
GN		 4706 .get_dr = emulator_get_dr,
4707 .set_dr = emulator_set_dr,
717746e3
AK		 4708 .set_msr = emulator_set_msr,
4709 .get_msr = emulator_get_msr,
222d21aa 4710 .read_pmc = emulator_read_pmc,
6c3287f7 4711 .halt = emulator_halt,
bcaf5cc5 4712 .wbinvd = emulator_wbinvd,
d6aa1000 4713 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4714 .get_fpu = emulator_get_fpu,
4715 .put_fpu = emulator_put_fpu,
c4f035c6 4716 .intercept = emulator_intercept,
bdb42f5a 4717 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4718};
4719
95cb2295
GN		 4720static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4721{
4722 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4723 /*
4724 * an sti; sti; sequence only disable interrupts for the first
4725 * instruction. So, if the last instruction, be it emulated or
4726 * not, left the system with the INT_STI flag enabled, it
4727 * means that the last instruction is an sti. We should not
4728 * leave the flag on in this case. The same goes for mov ss
4729 */
4730 if (!(int_shadow & mask))
4731 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4732}
4733
54b8486f
GN		 4734static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4735{
4736 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4737 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4738 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4739 else if (ctxt->exception.error_code_valid)
4740 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4741 ctxt->exception.error_code);
54b8486f 4742 else
da9cb575 4743 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4744}
4745
dd856efa 4746static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4747{
9dac77fa 4748 memset(&ctxt->twobyte, 0,
dd856efa 4749 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4750
9dac77fa
AK		 4751 ctxt->fetch.start = 0;
4752 ctxt->fetch.end = 0;
4753 ctxt->io_read.pos = 0;
4754 ctxt->io_read.end = 0;
4755 ctxt->mem_read.pos = 0;
4756 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4757}
4758
8ec4722d
MG		 4759static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4760{
adf52235 4761 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4762 int cs_db, cs_l;
4763
8ec4722d
MG		 4764 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4765
adf52235
TY		 4766 ctxt->eflags = kvm_get_rflags(vcpu);
4767 ctxt->eip = kvm_rip_read(vcpu);
4768 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4769 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4770 cs_l ? X86EMUL_MODE_PROT64 :
4771 cs_db ? X86EMUL_MODE_PROT32 :
4772 X86EMUL_MODE_PROT16;
4773 ctxt->guest_mode = is_guest_mode(vcpu);
4774
dd856efa 4775 init_decode_cache(ctxt);
7ae441ea 4776 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4777}
4778
71f9833b 4779int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4780{
9d74191a 4781 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4782 int ret;
4783
4784 init_emulate_ctxt(vcpu);
4785
9dac77fa
AK		 4786 ctxt->op_bytes = 2;
4787 ctxt->ad_bytes = 2;
4788 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4789 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4790
4791 if (ret != X86EMUL_CONTINUE)
4792 return EMULATE_FAIL;
4793
9dac77fa 4794 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4795 kvm_rip_write(vcpu, ctxt->eip);
4796 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4797
4798 if (irq == NMI_VECTOR)
7460fb4a 4799 vcpu->arch.nmi_pending = 0;
63995653
MG		 4800 else
4801 vcpu->arch.interrupt.pending = false;
4802
4803 return EMULATE_DONE;
4804}
4805EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4806
6d77dbfc
GN		 4807static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4808{
fc3a9157
JR		 4809 int r = EMULATE_DONE;
4810
6d77dbfc
GN		 4811 ++vcpu->stat.insn_emulation_fail;
4812 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4813 if (!is_guest_mode(vcpu)) {
4814 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4815 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4816 vcpu->run->internal.ndata = 0;
4817 r = EMULATE_FAIL;
4818 }
6d77dbfc 4819 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4820
4821 return r;
6d77dbfc
GN		 4822}
4823
93c05d3e 4824static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4825 bool write_fault_to_shadow_pgtable,
4826 int emulation_type)
a6f177ef 4827{
95b3cf69 4828 gpa_t gpa = cr2;
8e3d9d06 4829 pfn_t pfn;
a6f177ef 4830
991eebf9
GN		 4831 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4832 return false;
4833
95b3cf69
XG		 4834 if (!vcpu->arch.mmu.direct_map) {
4835 /*
4836 * Write permission should be allowed since only
4837 * write access need to be emulated.
4838 */
4839 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4840
95b3cf69
XG		 4841 /*
4842 * If the mapping is invalid in guest, let cpu retry
4843 * it to generate fault.
4844 */
4845 if (gpa == UNMAPPED_GVA)
4846 return true;
4847 }
a6f177ef 4848
8e3d9d06
XG		 4849 /*
4850 * Do not retry the unhandleable instruction if it faults on the
4851 * readonly host memory, otherwise it will goto a infinite loop:
4852 * retry instruction -> write #PF -> emulation fail -> retry
4853 * instruction -> ...
4854 */
4855 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4856
4857 /*
4858 * If the instruction failed on the error pfn, it can not be fixed,
4859 * report the error to userspace.
4860 */
4861 if (is_error_noslot_pfn(pfn))
4862 return false;
4863
4864 kvm_release_pfn_clean(pfn);
4865
4866 /* The instructions are well-emulated on direct mmu. */
4867 if (vcpu->arch.mmu.direct_map) {
4868 unsigned int indirect_shadow_pages;
4869
4870 spin_lock(&vcpu->kvm->mmu_lock);
4871 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4872 spin_unlock(&vcpu->kvm->mmu_lock);
4873
4874 if (indirect_shadow_pages)
4875 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4876
a6f177ef 4877 return true;
8e3d9d06 4878 }
a6f177ef 4879
95b3cf69
XG		 4880 /*
4881 * if emulation was due to access to shadowed page table
4882 * and it failed try to unshadow page and re-enter the
4883 * guest to let CPU execute the instruction.
4884 */
4885 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4886
4887 /*
4888 * If the access faults on its page table, it can not
4889 * be fixed by unprotecting shadow page and it should
4890 * be reported to userspace.
4891 */
4892 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4893}
4894
1cb3f3ae
XG		 4895static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4896 unsigned long cr2, int emulation_type)
4897{
4898 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4899 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4900
4901 last_retry_eip = vcpu->arch.last_retry_eip;
4902 last_retry_addr = vcpu->arch.last_retry_addr;
4903
4904 /*
4905 * If the emulation is caused by #PF and it is non-page_table
4906 * writing instruction, it means the VM-EXIT is caused by shadow
4907 * page protected, we can zap the shadow page and retry this
4908 * instruction directly.
4909 *
4910 * Note: if the guest uses a non-page-table modifying instruction
4911 * on the PDE that points to the instruction, then we will unmap
4912 * the instruction and go to an infinite loop. So, we cache the
4913 * last retried eip and the last fault address, if we meet the eip
4914 * and the address again, we can break out of the potential infinite
4915 * loop.
4916 */
4917 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4918
4919 if (!(emulation_type & EMULTYPE_RETRY))
4920 return false;
4921
4922 if (x86_page_table_writing_insn(ctxt))
4923 return false;
4924
4925 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4926 return false;
4927
4928 vcpu->arch.last_retry_eip = ctxt->eip;
4929 vcpu->arch.last_retry_addr = cr2;
4930
4931 if (!vcpu->arch.mmu.direct_map)
4932 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4933
22368028 4934 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4935
4936 return true;
4937}
4938
716d51ab
GN		 4939static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4940static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4941
51d8b661
AP		 4942int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4943 unsigned long cr2,
dc25e89e
AP		 4944 int emulation_type,
4945 void *insn,
4946 int insn_len)
bbd9b64e 4947{
95cb2295 4948 int r;
9d74191a 4949 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4950 bool writeback = true;
93c05d3e 4951 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4952
93c05d3e
XG		 4953 /*
4954 * Clear write_fault_to_shadow_pgtable here to ensure it is
4955 * never reused.
4956 */
4957 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4958 kvm_clear_exception_queue(vcpu);
8d7d8102 4959
571008da 4960 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4961 init_emulate_ctxt(vcpu);
9d74191a
TY		 4962 ctxt->interruptibility = 0;
4963 ctxt->have_exception = false;
4964 ctxt->perm_ok = false;
bbd9b64e 4965
9d74191a 4966 ctxt->only_vendor_specific_insn
4005996e
AK		 4967 = emulation_type & EMULTYPE_TRAP_UD;
4968
9d74191a 4969 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4970
e46479f8 4971 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4972 ++vcpu->stat.insn_emulation;
1d2887e2 4973 if (r != EMULATION_OK) {
4005996e
AK		 4974 if (emulation_type & EMULTYPE_TRAP_UD)
4975 return EMULATE_FAIL;
991eebf9
GN		 4976 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4977 emulation_type))
bbd9b64e 4978 return EMULATE_DONE;
6d77dbfc
GN		 4979 if (emulation_type & EMULTYPE_SKIP)
4980 return EMULATE_FAIL;
4981 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4982 }
4983 }
4984
ba8afb6b 4985 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4986 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4987 return EMULATE_DONE;
4988 }
4989
1cb3f3ae
XG		 4990 if (retry_instruction(ctxt, cr2, emulation_type))
4991 return EMULATE_DONE;
4992
7ae441ea 4993 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4994 changes registers values during IO operation */
7ae441ea
GN		 4995 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4996 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4997 emulator_invalidate_register_cache(ctxt);
7ae441ea 4998 }
4d2179e1 4999
5cd21917 5000restart:
9d74191a 5001 r = x86_emulate_insn(ctxt);
bbd9b64e 5002
775fde86
JR		 5003 if (r == EMULATION_INTERCEPTED)
5004 return EMULATE_DONE;
5005
d2ddd1c4 5006 if (r == EMULATION_FAILED) {
991eebf9
GN		 5007 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5008 emulation_type))
c3cd7ffa
GN		 5009 return EMULATE_DONE;
5010
6d77dbfc 5011 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5012 }
5013
9d74191a 5014 if (ctxt->have_exception) {
54b8486f 5015 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5016 r = EMULATE_DONE;
5017 } else if (vcpu->arch.pio.count) {
3457e419
GN		 5018 if (!vcpu->arch.pio.in)
5019 vcpu->arch.pio.count = 0;
716d51ab 5020 else {
7ae441ea 5021 writeback = false;
716d51ab
GN		 5022 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5023 }
e85d28f8 5024 r = EMULATE_DO_MMIO;
7ae441ea
GN		 5025 } else if (vcpu->mmio_needed) {
5026 if (!vcpu->mmio_is_write)
5027 writeback = false;
e85d28f8 5028 r = EMULATE_DO_MMIO;
716d51ab 5029 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5030 } else if (r == EMULATION_RESTART)
5cd21917 5031 goto restart;
d2ddd1c4
GN		 5032 else
5033 r = EMULATE_DONE;
f850e2e6 5034
7ae441ea 5035 if (writeback) {
9d74191a
TY		 5036 toggle_interruptibility(vcpu, ctxt->interruptibility);
5037 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 5038 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5039 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5040 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 5041 } else
5042 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5043
5044 return r;
de7d789a 5045}
51d8b661 5046EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5047
cf8f70bf 5048int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5049{
cf8f70bf 5050 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5051 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5052 size, port, &val, 1);
cf8f70bf 5053 /* do not return to emulator after return from userspace */
7972995b 5054 vcpu->arch.pio.count = 0;
de7d789a
CO		 5055 return ret;
5056}
cf8f70bf 5057EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5058
8cfdc000
ZA		 5059static void tsc_bad(void *info)
5060{
0a3aee0d 5061 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5062}
5063
5064static void tsc_khz_changed(void *data)
c8076604 5065{
8cfdc000
ZA		 5066 struct cpufreq_freqs *freq = data;
5067 unsigned long khz = 0;
5068
5069 if (data)
5070 khz = freq->new;
5071 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5072 khz = cpufreq_quick_get(raw_smp_processor_id());
5073 if (!khz)
5074 khz = tsc_khz;
0a3aee0d 5075 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5076}
5077
c8076604
GH		 5078static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5079 void *data)
5080{
5081 struct cpufreq_freqs *freq = data;
5082 struct kvm *kvm;
5083 struct kvm_vcpu *vcpu;
5084 int i, send_ipi = 0;
5085
8cfdc000
ZA		 5086 /*
5087 * We allow guests to temporarily run on slowing clocks,
5088 * provided we notify them after, or to run on accelerating
5089 * clocks, provided we notify them before. Thus time never
5090 * goes backwards.
5091 *
5092 * However, we have a problem. We can't atomically update
5093 * the frequency of a given CPU from this function; it is
5094 * merely a notifier, which can be called from any CPU.
5095 * Changing the TSC frequency at arbitrary points in time
5096 * requires a recomputation of local variables related to
5097 * the TSC for each VCPU. We must flag these local variables
5098 * to be updated and be sure the update takes place with the
5099 * new frequency before any guests proceed.
5100 *
5101 * Unfortunately, the combination of hotplug CPU and frequency
5102 * change creates an intractable locking scenario; the order
5103 * of when these callouts happen is undefined with respect to
5104 * CPU hotplug, and they can race with each other. As such,
5105 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5106 * undefined; you can actually have a CPU frequency change take
5107 * place in between the computation of X and the setting of the
5108 * variable. To protect against this problem, all updates of
5109 * the per_cpu tsc_khz variable are done in an interrupt
5110 * protected IPI, and all callers wishing to update the value
5111 * must wait for a synchronous IPI to complete (which is trivial
5112 * if the caller is on the CPU already). This establishes the
5113 * necessary total order on variable updates.
5114 *
5115 * Note that because a guest time update may take place
5116 * anytime after the setting of the VCPU's request bit, the
5117 * correct TSC value must be set before the request. However,
5118 * to ensure the update actually makes it to any guest which
5119 * starts running in hardware virtualization between the set
5120 * and the acquisition of the spinlock, we must also ping the
5121 * CPU after setting the request bit.
5122 *
5123 */
5124
c8076604
GH		 5125 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5126 return 0;
5127 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5128 return 0;
8cfdc000
ZA		 5129
5130 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5131
e935b837 5132 raw_spin_lock(&kvm_lock);
c8076604 5133 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5134 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5135 if (vcpu->cpu != freq->cpu)
5136 continue;
c285545f 5137 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5138 if (vcpu->cpu != smp_processor_id())
8cfdc000 5139 send_ipi = 1;
c8076604
GH		 5140 }
5141 }
e935b837 5142 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5143
5144 if (freq->old < freq->new && send_ipi) {
5145 /*
5146 * We upscale the frequency. Must make the guest
5147 * doesn't see old kvmclock values while running with
5148 * the new frequency, otherwise we risk the guest sees
5149 * time go backwards.
5150 *
5151 * In case we update the frequency for another cpu
5152 * (which might be in guest context) send an interrupt
5153 * to kick the cpu out of guest context. Next time
5154 * guest context is entered kvmclock will be updated,
5155 * so the guest will not see stale values.
5156 */
8cfdc000 5157 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5158 }
5159 return 0;
5160}
5161
5162static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5163 .notifier_call = kvmclock_cpufreq_notifier
5164};
5165
5166static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5167 unsigned long action, void *hcpu)
5168{
5169 unsigned int cpu = (unsigned long)hcpu;
5170
5171 switch (action) {
5172 case CPU_ONLINE:
5173 case CPU_DOWN_FAILED:
5174 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5175 break;
5176 case CPU_DOWN_PREPARE:
5177 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5178 break;
5179 }
5180 return NOTIFY_OK;
5181}
5182
5183static struct notifier_block kvmclock_cpu_notifier_block = {
5184 .notifier_call = kvmclock_cpu_notifier,
5185 .priority = -INT_MAX
c8076604
GH		 5186};
5187
b820cc0c
ZA		 5188static void kvm_timer_init(void)
5189{
5190 int cpu;
5191
c285545f 5192 max_tsc_khz = tsc_khz;
8cfdc000 5193 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5194 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5195#ifdef CONFIG_CPU_FREQ
5196 struct cpufreq_policy policy;
5197 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5198 cpu = get_cpu();
5199 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5200 if (policy.cpuinfo.max_freq)
5201 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5202 put_cpu();
c285545f 5203#endif
b820cc0c
ZA		 5204 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5205 CPUFREQ_TRANSITION_NOTIFIER);
5206 }
c285545f 5207 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5208 for_each_online_cpu(cpu)
5209 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5210}
5211
ff9d07a0
ZY		 5212static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5213
f5132b01 5214int kvm_is_in_guest(void)
ff9d07a0 5215{
086c9855 5216 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5217}
5218
5219static int kvm_is_user_mode(void)
5220{
5221 int user_mode = 3;
dcf46b94 5222
086c9855
AS		 5223 if (__this_cpu_read(current_vcpu))
5224 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5225
ff9d07a0
ZY		 5226 return user_mode != 0;
5227}
5228
5229static unsigned long kvm_get_guest_ip(void)
5230{
5231 unsigned long ip = 0;
dcf46b94 5232
086c9855
AS		 5233 if (__this_cpu_read(current_vcpu))
5234 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5235
ff9d07a0
ZY		 5236 return ip;
5237}
5238
5239static struct perf_guest_info_callbacks kvm_guest_cbs = {
5240 .is_in_guest = kvm_is_in_guest,
5241 .is_user_mode = kvm_is_user_mode,
5242 .get_guest_ip = kvm_get_guest_ip,
5243};
5244
5245void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5246{
086c9855 5247 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5248}
5249EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5250
5251void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5252{
086c9855 5253 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5254}
5255EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5256
ce88decf
XG		 5257static void kvm_set_mmio_spte_mask(void)
5258{
5259 u64 mask;
5260 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5261
5262 /*
5263 * Set the reserved bits and the present bit of an paging-structure
5264 * entry to generate page fault with PFER.RSV = 1.
5265 */
5266 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5267 mask |= 1ull;
5268
5269#ifdef CONFIG_X86_64
5270 /*
5271 * If reserved bit is not supported, clear the present bit to disable
5272 * mmio page fault.
5273 */
5274 if (maxphyaddr == 52)
5275 mask &= ~1ull;
5276#endif
5277
5278 kvm_mmu_set_mmio_spte_mask(mask);
5279}
5280
16e8d74d
MT		 5281#ifdef CONFIG_X86_64
5282static void pvclock_gtod_update_fn(struct work_struct *work)
5283{
d828199e
MT		 5284 struct kvm *kvm;
5285
5286 struct kvm_vcpu *vcpu;
5287 int i;
5288
5289 raw_spin_lock(&kvm_lock);
5290 list_for_each_entry(kvm, &vm_list, vm_list)
5291 kvm_for_each_vcpu(i, vcpu, kvm)
5292 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5293 atomic_set(&kvm_guest_has_master_clock, 0);
5294 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5295}
5296
5297static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5298
5299/*
5300 * Notification about pvclock gtod data update.
5301 */
5302static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5303 void *priv)
5304{
5305 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5306 struct timekeeper *tk = priv;
5307
5308 update_pvclock_gtod(tk);
5309
5310 /* disable master clock if host does not trust, or does not
5311 * use, TSC clocksource
5312 */
5313 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5314 atomic_read(&kvm_guest_has_master_clock) != 0)
5315 queue_work(system_long_wq, &pvclock_gtod_work);
5316
5317 return 0;
5318}
5319
5320static struct notifier_block pvclock_gtod_notifier = {
5321 .notifier_call = pvclock_gtod_notify,
5322};
5323#endif
5324
f8c16bba 5325int kvm_arch_init(void *opaque)
043405e1 5326{
b820cc0c 5327 int r;
f8c16bba
ZX		 5328 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5329
f8c16bba
ZX		 5330 if (kvm_x86_ops) {
5331 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5332 r = -EEXIST;
5333 goto out;
f8c16bba
ZX		 5334 }
5335
5336 if (!ops->cpu_has_kvm_support()) {
5337 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5338 r = -EOPNOTSUPP;
5339 goto out;
f8c16bba
ZX		 5340 }
5341 if (ops->disabled_by_bios()) {
5342 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5343 r = -EOPNOTSUPP;
5344 goto out;
f8c16bba
ZX		 5345 }
5346
013f6a5d
MT		 5347 r = -ENOMEM;
5348 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5349 if (!shared_msrs) {
5350 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5351 goto out;
5352 }
5353
97db56ce
AK		 5354 r = kvm_mmu_module_init();
5355 if (r)
013f6a5d 5356 goto out_free_percpu;
97db56ce 5357
ce88decf 5358 kvm_set_mmio_spte_mask();
97db56ce
AK		 5359 kvm_init_msr_list();
5360
f8c16bba 5361 kvm_x86_ops = ops;
7b52345e 5362 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5363 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5364
b820cc0c 5365 kvm_timer_init();
c8076604 5366
ff9d07a0
ZY		 5367 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5368
2acf923e
DC		 5369 if (cpu_has_xsave)
5370 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5371
c5cc421b 5372 kvm_lapic_init();
16e8d74d
MT		 5373#ifdef CONFIG_X86_64
5374 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5375#endif
5376
f8c16bba 5377 return 0;
56c6d28a 5378
013f6a5d
MT		 5379out_free_percpu:
5380 free_percpu(shared_msrs);
56c6d28a 5381out:
56c6d28a 5382 return r;
043405e1 5383}
8776e519 5384
f8c16bba
ZX		 5385void kvm_arch_exit(void)
5386{
ff9d07a0
ZY		 5387 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5388
888d256e
JK		 5389 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5390 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5391 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5392 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5393#ifdef CONFIG_X86_64
5394 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5395#endif
f8c16bba 5396 kvm_x86_ops = NULL;
56c6d28a 5397 kvm_mmu_module_exit();
013f6a5d 5398 free_percpu(shared_msrs);
56c6d28a 5399}
f8c16bba 5400
8776e519
HB		 5401int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5402{
5403 ++vcpu->stat.halt_exits;
5404 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5405 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5406 return 1;
5407 } else {
5408 vcpu->run->exit_reason = KVM_EXIT_HLT;
5409 return 0;
5410 }
5411}
5412EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5413
55cd8e5a
GN		 5414int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5415{
5416 u64 param, ingpa, outgpa, ret;
5417 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5418 bool fast, longmode;
5419 int cs_db, cs_l;
5420
5421 /*
5422 * hypercall generates UD from non zero cpl and real mode
5423 * per HYPER-V spec
5424 */
3eeb3288 5425 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5426 kvm_queue_exception(vcpu, UD_VECTOR);
5427 return 0;
5428 }
5429
5430 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5431 longmode = is_long_mode(vcpu) && cs_l == 1;
5432
5433 if (!longmode) {
ccd46936
GN		 5434 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5435 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5436 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5437 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5438 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5439 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5440 }
5441#ifdef CONFIG_X86_64
5442 else {
5443 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5444 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5445 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5446 }
5447#endif
5448
5449 code = param & 0xffff;
5450 fast = (param >> 16) & 0x1;
5451 rep_cnt = (param >> 32) & 0xfff;
5452 rep_idx = (param >> 48) & 0xfff;
5453
5454 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5455
c25bc163
GN		 5456 switch (code) {
5457 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5458 kvm_vcpu_on_spin(vcpu);
5459 break;
5460 default:
5461 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5462 break;
5463 }
55cd8e5a
GN		 5464
5465 ret = res | (((u64)rep_done & 0xfff) << 32);
5466 if (longmode) {
5467 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5468 } else {
5469 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5470 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5471 }
5472
5473 return 1;
5474}
5475
8776e519
HB		 5476int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5477{
5478 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5479 int r = 1;
8776e519 5480
55cd8e5a
GN		 5481 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5482 return kvm_hv_hypercall(vcpu);
5483
5fdbf976
MT		 5484 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5485 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5486 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5487 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5488 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5489
229456fc 5490 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5491
8776e519
HB		 5492 if (!is_long_mode(vcpu)) {
5493 nr &= 0xFFFFFFFF;
5494 a0 &= 0xFFFFFFFF;
5495 a1 &= 0xFFFFFFFF;
5496 a2 &= 0xFFFFFFFF;
5497 a3 &= 0xFFFFFFFF;
5498 }
5499
07708c4a
JK		 5500 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5501 ret = -KVM_EPERM;
5502 goto out;
5503 }
5504
8776e519 5505 switch (nr) {
b93463aa
AK		 5506 case KVM_HC_VAPIC_POLL_IRQ:
5507 ret = 0;
5508 break;
8776e519
HB		 5509 default:
5510 ret = -KVM_ENOSYS;
5511 break;
5512 }
07708c4a 5513out:
5fdbf976 5514 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5515 ++vcpu->stat.hypercalls;
2f333bcb 5516 return r;
8776e519
HB		 5517}
5518EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5519
b6785def 5520static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5521{
d6aa1000 5522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5523 char instruction[3];
5fdbf976 5524 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5525
8776e519 5526 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5527
9d74191a 5528 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5529}
5530
b6c7a5dc
HB		 5531/*
5532 * Check if userspace requested an interrupt window, and that the
5533 * interrupt window is open.
5534 *
5535 * No need to exit to userspace if we already have an interrupt queued.
5536 */
851ba692 5537static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5538{
8061823a 5539 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5540 vcpu->run->request_interrupt_window &&
5df56646 5541 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5542}
5543
851ba692 5544static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5545{
851ba692
AK		 5546 struct kvm_run *kvm_run = vcpu->run;
5547
91586a3b 5548 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5549 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5550 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5551 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5552 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5553 else
b6c7a5dc 5554 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5555 kvm_arch_interrupt_allowed(vcpu) &&
5556 !kvm_cpu_has_interrupt(vcpu) &&
5557 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5558}
5559
4484141a 5560static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5561{
5562 struct kvm_lapic *apic = vcpu->arch.apic;
5563 struct page *page;
5564
5565 if (!apic || !apic->vapic_addr)
4484141a 5566 return 0;
b93463aa
AK		 5567
5568 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5569 if (is_error_page(page))
5570 return -EFAULT;
72dc67a6
IE		 5571
5572 vcpu->arch.apic->vapic_page = page;
4484141a 5573 return 0;
b93463aa
AK		 5574}
5575
5576static void vapic_exit(struct kvm_vcpu *vcpu)
5577{
5578 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5579 int idx;
b93463aa
AK		 5580
5581 if (!apic || !apic->vapic_addr)
5582 return;
5583
f656ce01 5584 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5585 kvm_release_page_dirty(apic->vapic_page);
5586 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5587 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5588}
5589
95ba8273
GN		 5590static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5591{
5592 int max_irr, tpr;
5593
5594 if (!kvm_x86_ops->update_cr8_intercept)
5595 return;
5596
88c808fd
AK		 5597 if (!vcpu->arch.apic)
5598 return;
5599
8db3baa2
GN		 5600 if (!vcpu->arch.apic->vapic_addr)
5601 max_irr = kvm_lapic_find_highest_irr(vcpu);
5602 else
5603 max_irr = -1;
95ba8273
GN		 5604
5605 if (max_irr != -1)
5606 max_irr >>= 4;
5607
5608 tpr = kvm_lapic_get_cr8(vcpu);
5609
5610 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5611}
5612
851ba692 5613static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5614{
5615 /* try to reinject previous events if any */
b59bb7bd 5616 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5617 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5618 vcpu->arch.exception.has_error_code,
5619 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5620 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5621 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5622 vcpu->arch.exception.error_code,
5623 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5624 return;
5625 }
5626
95ba8273
GN		 5627 if (vcpu->arch.nmi_injected) {
5628 kvm_x86_ops->set_nmi(vcpu);
5629 return;
5630 }
5631
5632 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5633 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5634 return;
5635 }
5636
5637 /* try to inject new event if pending */
5638 if (vcpu->arch.nmi_pending) {
5639 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5640 --vcpu->arch.nmi_pending;
95ba8273
GN		 5641 vcpu->arch.nmi_injected = true;
5642 kvm_x86_ops->set_nmi(vcpu);
5643 }
c7c9c56c 5644 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5645 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5646 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5647 false);
5648 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5649 }
5650 }
5651}
5652
7460fb4a
AK		 5653static void process_nmi(struct kvm_vcpu *vcpu)
5654{
5655 unsigned limit = 2;
5656
5657 /*
5658 * x86 is limited to one NMI running, and one NMI pending after it.
5659 * If an NMI is already in progress, limit further NMIs to just one.
5660 * Otherwise, allow two (and we'll inject the first one immediately).
5661 */
5662 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5663 limit = 1;
5664
5665 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5666 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5667 kvm_make_request(KVM_REQ_EVENT, vcpu);
5668}
5669
d828199e
MT		 5670static void kvm_gen_update_masterclock(struct kvm *kvm)
5671{
5672#ifdef CONFIG_X86_64
5673 int i;
5674 struct kvm_vcpu *vcpu;
5675 struct kvm_arch *ka = &kvm->arch;
5676
5677 spin_lock(&ka->pvclock_gtod_sync_lock);
5678 kvm_make_mclock_inprogress_request(kvm);
5679 /* no guest entries from this point */
5680 pvclock_update_vm_gtod_copy(kvm);
5681
5682 kvm_for_each_vcpu(i, vcpu, kvm)
5683 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5684
5685 /* guest entries allowed */
5686 kvm_for_each_vcpu(i, vcpu, kvm)
5687 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5688
5689 spin_unlock(&ka->pvclock_gtod_sync_lock);
5690#endif
5691}
5692
3d81bc7e 5693static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5694{
5695 u64 eoi_exit_bitmap[4];
cf9e65b7 5696 u32 tmr[8];
c7c9c56c 5697
3d81bc7e
YZ		 5698 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5699 return;
c7c9c56c
YZ		 5700
5701 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5702 memset(tmr, 0, 32);
c7c9c56c 5703
cf9e65b7 5704 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5705 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5706 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5707}
5708
851ba692 5709static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5710{
5711 int r;
6a8b1d13 5712 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5713 vcpu->run->request_interrupt_window;
730dca42 5714 bool req_immediate_exit = false;
b6c7a5dc 5715
3e007509 5716 if (vcpu->requests) {
a8eeb04a 5717 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5718 kvm_mmu_unload(vcpu);
a8eeb04a 5719 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5720 __kvm_migrate_timers(vcpu);
d828199e
MT		 5721 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5722 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5723 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5724 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5725 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5726 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5727 if (unlikely(r))
5728 goto out;
5729 }
a8eeb04a 5730 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5731 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5732 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5733 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5734 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5735 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5736 r = 0;
5737 goto out;
5738 }
a8eeb04a 5739 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5740 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5741 r = 0;
5742 goto out;
5743 }
a8eeb04a 5744 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5745 vcpu->fpu_active = 0;
5746 kvm_x86_ops->fpu_deactivate(vcpu);
5747 }
af585b92
GN		 5748 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5749 /* Page is swapped out. Do synthetic halt */
5750 vcpu->arch.apf.halted = true;
5751 r = 1;
5752 goto out;
5753 }
c9aaa895
GC		 5754 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5755 record_steal_time(vcpu);
7460fb4a
AK		 5756 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5757 process_nmi(vcpu);
f5132b01
GN		 5758 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5759 kvm_handle_pmu_event(vcpu);
5760 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5761 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5762 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5763 vcpu_scan_ioapic(vcpu);
2f52d58c 5764 }
b93463aa 5765
b463a6f7 5766 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5767 kvm_apic_accept_events(vcpu);
5768 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5769 r = 1;
5770 goto out;
5771 }
5772
b463a6f7
AK		 5773 inject_pending_event(vcpu);
5774
5775 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5776 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5777 req_immediate_exit =
5778 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5779 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5780 req_immediate_exit =
5781 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5782
5783 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5784 /*
5785 * Update architecture specific hints for APIC
5786 * virtual interrupt delivery.
5787 */
5788 if (kvm_x86_ops->hwapic_irr_update)
5789 kvm_x86_ops->hwapic_irr_update(vcpu,
5790 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5791 update_cr8_intercept(vcpu);
5792 kvm_lapic_sync_to_vapic(vcpu);
5793 }
5794 }
5795
d8368af8
AK		 5796 r = kvm_mmu_reload(vcpu);
5797 if (unlikely(r)) {
d905c069 5798 goto cancel_injection;
d8368af8
AK		 5799 }
5800
b6c7a5dc
HB		 5801 preempt_disable();
5802
5803 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5804 if (vcpu->fpu_active)
5805 kvm_load_guest_fpu(vcpu);
2acf923e 5806 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5807
6b7e2d09
XG		 5808 vcpu->mode = IN_GUEST_MODE;
5809
5810 /* We should set ->mode before check ->requests,
5811 * see the comment in make_all_cpus_request.
5812 */
5813 smp_mb();
b6c7a5dc 5814
d94e1dc9 5815 local_irq_disable();
32f88400 5816
6b7e2d09 5817 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5818 || need_resched() || signal_pending(current)) {
6b7e2d09 5819 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5820 smp_wmb();
6c142801
AK		 5821 local_irq_enable();
5822 preempt_enable();
5823 r = 1;
d905c069 5824 goto cancel_injection;
6c142801
AK		 5825 }
5826
f656ce01 5827 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5828
d6185f20
NHE		 5829 if (req_immediate_exit)
5830 smp_send_reschedule(vcpu->cpu);
5831
b6c7a5dc
HB		 5832 kvm_guest_enter();
5833
42dbaa5a 5834 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5835 set_debugreg(0, 7);
5836 set_debugreg(vcpu->arch.eff_db[0], 0);
5837 set_debugreg(vcpu->arch.eff_db[1], 1);
5838 set_debugreg(vcpu->arch.eff_db[2], 2);
5839 set_debugreg(vcpu->arch.eff_db[3], 3);
5840 }
b6c7a5dc 5841
229456fc 5842 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5843 kvm_x86_ops->run(vcpu);
b6c7a5dc 5844
24f1e32c
FW		 5845 /*
5846 * If the guest has used debug registers, at least dr7
5847 * will be disabled while returning to the host.
5848 * If we don't have active breakpoints in the host, we don't
5849 * care about the messed up debug address registers. But if
5850 * we have some of them active, restore the old state.
5851 */
59d8eb53 5852 if (hw_breakpoint_active())
24f1e32c 5853 hw_breakpoint_restore();
42dbaa5a 5854
886b470c
MT		 5855 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5856 native_read_tsc());
1d5f066e 5857
6b7e2d09 5858 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5859 smp_wmb();
a547c6db
YZ		 5860
5861 /* Interrupt is enabled by handle_external_intr() */
5862 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 5863
5864 ++vcpu->stat.exits;
5865
5866 /*
5867 * We must have an instruction between local_irq_enable() and
5868 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5869 * the interrupt shadow. The stat.exits increment will do nicely.
5870 * But we need to prevent reordering, hence this barrier():
5871 */
5872 barrier();
5873
5874 kvm_guest_exit();
5875
5876 preempt_enable();
5877
f656ce01 5878 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5879
b6c7a5dc
HB		 5880 /*
5881 * Profile KVM exit RIPs:
5882 */
5883 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5884 unsigned long rip = kvm_rip_read(vcpu);
5885 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5886 }
5887
cc578287
ZA		 5888 if (unlikely(vcpu->arch.tsc_always_catchup))
5889 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5890
5cfb1d5a
MT		 5891 if (vcpu->arch.apic_attention)
5892 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5893
851ba692 5894 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5895 return r;
5896
5897cancel_injection:
5898 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5899 if (unlikely(vcpu->arch.apic_attention))
5900 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5901out:
5902 return r;
5903}
b6c7a5dc 5904
09cec754 5905
851ba692 5906static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5907{
5908 int r;
f656ce01 5909 struct kvm *kvm = vcpu->kvm;
d7690175 5910
f656ce01 5911 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5912 r = vapic_enter(vcpu);
5913 if (r) {
5914 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5915 return r;
5916 }
d7690175
MT		 5917
5918 r = 1;
5919 while (r > 0) {
af585b92
GN		 5920 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5921 !vcpu->arch.apf.halted)
851ba692 5922 r = vcpu_enter_guest(vcpu);
d7690175 5923 else {
f656ce01 5924 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5925 kvm_vcpu_block(vcpu);
f656ce01 5926 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 5927 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5928 kvm_apic_accept_events(vcpu);
09cec754
GN		 5929 switch(vcpu->arch.mp_state) {
5930 case KVM_MP_STATE_HALTED:
d7690175 5931 vcpu->arch.mp_state =
09cec754
GN		 5932 KVM_MP_STATE_RUNNABLE;
5933 case KVM_MP_STATE_RUNNABLE:
af585b92 5934 vcpu->arch.apf.halted = false;
09cec754 5935 break;
66450a21
JK		 5936 case KVM_MP_STATE_INIT_RECEIVED:
5937 break;
09cec754
GN		 5938 default:
5939 r = -EINTR;
5940 break;
5941 }
5942 }
d7690175
MT		 5943 }
5944
09cec754
GN		 5945 if (r <= 0)
5946 break;
5947
5948 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5949 if (kvm_cpu_has_pending_timer(vcpu))
5950 kvm_inject_pending_timer_irqs(vcpu);
5951
851ba692 5952 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5953 r = -EINTR;
851ba692 5954 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5955 ++vcpu->stat.request_irq_exits;
5956 }
af585b92
GN		 5957
5958 kvm_check_async_pf_completion(vcpu);
5959
09cec754
GN		 5960 if (signal_pending(current)) {
5961 r = -EINTR;
851ba692 5962 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5963 ++vcpu->stat.signal_exits;
5964 }
5965 if (need_resched()) {
f656ce01 5966 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5967 kvm_resched(vcpu);
f656ce01 5968 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5969 }
b6c7a5dc
HB		 5970 }
5971
f656ce01 5972 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5973
b93463aa
AK		 5974 vapic_exit(vcpu);
5975
b6c7a5dc
HB		 5976 return r;
5977}
5978
716d51ab
GN		 5979static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5980{
5981 int r;
5982 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5983 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5984 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5985 if (r != EMULATE_DONE)
5986 return 0;
5987 return 1;
5988}
5989
5990static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5991{
5992 BUG_ON(!vcpu->arch.pio.count);
5993
5994 return complete_emulated_io(vcpu);
5995}
5996
f78146b0
AK		 5997/*
5998 * Implements the following, as a state machine:
5999 *
6000 * read:
6001 * for each fragment
87da7e66
XG		 6002 * for each mmio piece in the fragment
6003 * write gpa, len
6004 * exit
6005 * copy data
f78146b0
AK		 6006 * execute insn
6007 *
6008 * write:
6009 * for each fragment
87da7e66
XG		 6010 * for each mmio piece in the fragment
6011 * write gpa, len
6012 * copy data
6013 * exit
f78146b0 6014 */
716d51ab 6015static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6016{
6017 struct kvm_run *run = vcpu->run;
f78146b0 6018 struct kvm_mmio_fragment *frag;
87da7e66 6019 unsigned len;
5287f194 6020
716d51ab 6021 BUG_ON(!vcpu->mmio_needed);
5287f194 6022
716d51ab 6023 /* Complete previous fragment */
87da7e66
XG		 6024 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6025 len = min(8u, frag->len);
716d51ab 6026 if (!vcpu->mmio_is_write)
87da7e66
XG		 6027 memcpy(frag->data, run->mmio.data, len);
6028
6029 if (frag->len <= 8) {
6030 /* Switch to the next fragment. */
6031 frag++;
6032 vcpu->mmio_cur_fragment++;
6033 } else {
6034 /* Go forward to the next mmio piece. */
6035 frag->data += len;
6036 frag->gpa += len;
6037 frag->len -= len;
6038 }
6039
716d51ab
GN		 6040 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6041 vcpu->mmio_needed = 0;
cef4dea0 6042 if (vcpu->mmio_is_write)
716d51ab
GN		 6043 return 1;
6044 vcpu->mmio_read_completed = 1;
6045 return complete_emulated_io(vcpu);
6046 }
87da7e66 6047
716d51ab
GN		 6048 run->exit_reason = KVM_EXIT_MMIO;
6049 run->mmio.phys_addr = frag->gpa;
6050 if (vcpu->mmio_is_write)
87da7e66
XG		 6051 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6052 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6053 run->mmio.is_write = vcpu->mmio_is_write;
6054 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6055 return 0;
5287f194
AK		 6056}
6057
716d51ab 6058
b6c7a5dc
HB		 6059int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6060{
6061 int r;
6062 sigset_t sigsaved;
6063
e5c30142
AK		 6064 if (!tsk_used_math(current) && init_fpu(current))
6065 return -ENOMEM;
6066
ac9f6dc0
AK		 6067 if (vcpu->sigset_active)
6068 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6069
a4535290 6070 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6071 kvm_vcpu_block(vcpu);
66450a21 6072 kvm_apic_accept_events(vcpu);
d7690175 6073 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6074 r = -EAGAIN;
6075 goto out;
b6c7a5dc
HB		 6076 }
6077
b6c7a5dc 6078 /* re-sync apic's tpr */
eea1cff9
AP		 6079 if (!irqchip_in_kernel(vcpu->kvm)) {
6080 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6081 r = -EINVAL;
6082 goto out;
6083 }
6084 }
b6c7a5dc 6085
716d51ab
GN		 6086 if (unlikely(vcpu->arch.complete_userspace_io)) {
6087 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6088 vcpu->arch.complete_userspace_io = NULL;
6089 r = cui(vcpu);
6090 if (r <= 0)
6091 goto out;
6092 } else
6093 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6094
851ba692 6095 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6096
6097out:
f1d86e46 6098 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6099 if (vcpu->sigset_active)
6100 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6101
b6c7a5dc
HB		 6102 return r;
6103}
6104
6105int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6106{
7ae441ea
GN		 6107 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6108 /*
6109 * We are here if userspace calls get_regs() in the middle of
6110 * instruction emulation. Registers state needs to be copied
4a969980 6111 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6112 * that usually, but some bad designed PV devices (vmware
6113 * backdoor interface) need this to work
6114 */
dd856efa 6115 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6116 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6117 }
5fdbf976
MT		 6118 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6119 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6120 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6121 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6122 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6123 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6124 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6125 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6126#ifdef CONFIG_X86_64
5fdbf976
MT		 6127 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6128 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6129 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6130 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6131 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6132 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6133 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6134 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6135#endif
6136
5fdbf976 6137 regs->rip = kvm_rip_read(vcpu);
91586a3b 6138 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6139
b6c7a5dc
HB		 6140 return 0;
6141}
6142
6143int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6144{
7ae441ea
GN		 6145 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6146 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6147
5fdbf976
MT		 6148 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6149 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6150 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6151 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6152 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6153 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6154 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6155 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6156#ifdef CONFIG_X86_64
5fdbf976
MT		 6157 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6158 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6159 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6160 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6161 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6162 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6163 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6164 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6165#endif
6166
5fdbf976 6167 kvm_rip_write(vcpu, regs->rip);
91586a3b 6168 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6169
b4f14abd
JK		 6170 vcpu->arch.exception.pending = false;
6171
3842d135
AK		 6172 kvm_make_request(KVM_REQ_EVENT, vcpu);
6173
b6c7a5dc
HB		 6174 return 0;
6175}
6176
b6c7a5dc
HB		 6177void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6178{
6179 struct kvm_segment cs;
6180
3e6e0aab 6181 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6182 *db = cs.db;
6183 *l = cs.l;
6184}
6185EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6186
6187int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6188 struct kvm_sregs *sregs)
6189{
89a27f4d 6190 struct desc_ptr dt;
b6c7a5dc 6191
3e6e0aab
GT		 6192 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6193 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6194 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6195 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6196 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6197 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6198
3e6e0aab
GT		 6199 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6200 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6201
6202 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6203 sregs->idt.limit = dt.size;
6204 sregs->idt.base = dt.address;
b6c7a5dc 6205 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6206 sregs->gdt.limit = dt.size;
6207 sregs->gdt.base = dt.address;
b6c7a5dc 6208
4d4ec087 6209 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6210 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6211 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6212 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6213 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6214 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6215 sregs->apic_base = kvm_get_apic_base(vcpu);
6216
923c61bb 6217 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6218
36752c9b 6219 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6220 set_bit(vcpu->arch.interrupt.nr,
6221 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6222
b6c7a5dc
HB		 6223 return 0;
6224}
6225
62d9f0db
MT		 6226int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6227 struct kvm_mp_state *mp_state)
6228{
66450a21 6229 kvm_apic_accept_events(vcpu);
62d9f0db 6230 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6231 return 0;
6232}
6233
6234int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6235 struct kvm_mp_state *mp_state)
6236{
66450a21
JK		 6237 if (!kvm_vcpu_has_lapic(vcpu) &&
6238 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6239 return -EINVAL;
6240
6241 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6242 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6243 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6244 } else
6245 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6246 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6247 return 0;
6248}
6249
7f3d35fd
KW		 6250int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6251 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6252{
9d74191a 6253 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6254 int ret;
e01c2426 6255
8ec4722d 6256 init_emulate_ctxt(vcpu);
c697518a 6257
7f3d35fd 6258 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6259 has_error_code, error_code);
c697518a 6260
c697518a 6261 if (ret)
19d04437 6262 return EMULATE_FAIL;
37817f29 6263
9d74191a
TY		 6264 kvm_rip_write(vcpu, ctxt->eip);
6265 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6266 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6267 return EMULATE_DONE;
37817f29
IE		 6268}
6269EXPORT_SYMBOL_GPL(kvm_task_switch);
6270
b6c7a5dc
HB		 6271int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6272 struct kvm_sregs *sregs)
6273{
6274 int mmu_reset_needed = 0;
63f42e02 6275 int pending_vec, max_bits, idx;
89a27f4d 6276 struct desc_ptr dt;
b6c7a5dc 6277
6d1068b3
PM		 6278 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6279 return -EINVAL;
6280
89a27f4d
GN		 6281 dt.size = sregs->idt.limit;
6282 dt.address = sregs->idt.base;
b6c7a5dc 6283 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6284 dt.size = sregs->gdt.limit;
6285 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6286 kvm_x86_ops->set_gdt(vcpu, &dt);
6287
ad312c7c 6288 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6289 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6290 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6291 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6292
2d3ad1f4 6293 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6294
f6801dff 6295 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6296 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6297 kvm_set_apic_base(vcpu, sregs->apic_base);
6298
4d4ec087 6299 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6300 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6301 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6302
fc78f519 6303 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6304 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6305 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6306 kvm_update_cpuid(vcpu);
63f42e02
XG		 6307
6308 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6309 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6310 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6311 mmu_reset_needed = 1;
6312 }
63f42e02 6313 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6314
6315 if (mmu_reset_needed)
6316 kvm_mmu_reset_context(vcpu);
6317
a50abc3b 6318 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6319 pending_vec = find_first_bit(
6320 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6321 if (pending_vec < max_bits) {
66fd3f7f 6322 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6323 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6324 }
6325
3e6e0aab
GT		 6326 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6327 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6328 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6329 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6330 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6331 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6332
3e6e0aab
GT		 6333 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6334 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6335
5f0269f5
ME		 6336 update_cr8_intercept(vcpu);
6337
9c3e4aab 6338 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6339 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6340 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6341 !is_protmode(vcpu))
9c3e4aab
MT		 6342 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6343
3842d135
AK		 6344 kvm_make_request(KVM_REQ_EVENT, vcpu);
6345
b6c7a5dc
HB		 6346 return 0;
6347}
6348
d0bfb940
JK		 6349int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6350 struct kvm_guest_debug *dbg)
b6c7a5dc 6351{
355be0b9 6352 unsigned long rflags;
ae675ef0 6353 int i, r;
b6c7a5dc 6354
4f926bf2
JK		 6355 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6356 r = -EBUSY;
6357 if (vcpu->arch.exception.pending)
2122ff5e 6358 goto out;
4f926bf2
JK		 6359 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6360 kvm_queue_exception(vcpu, DB_VECTOR);
6361 else
6362 kvm_queue_exception(vcpu, BP_VECTOR);
6363 }
6364
91586a3b
JK		 6365 /*
6366 * Read rflags as long as potentially injected trace flags are still
6367 * filtered out.
6368 */
6369 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6370
6371 vcpu->guest_debug = dbg->control;
6372 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6373 vcpu->guest_debug = 0;
6374
6375 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6376 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6377 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6378 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6379 } else {
6380 for (i = 0; i < KVM_NR_DB_REGS; i++)
6381 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6382 }
c8639010 6383 kvm_update_dr7(vcpu);
ae675ef0 6384
f92653ee
JK		 6385 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6386 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6387 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6388
91586a3b
JK		 6389 /*
6390 * Trigger an rflags update that will inject or remove the trace
6391 * flags.
6392 */
6393 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6394
c8639010 6395 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6396
4f926bf2 6397 r = 0;
d0bfb940 6398
2122ff5e 6399out:
b6c7a5dc
HB		 6400
6401 return r;
6402}
6403
8b006791
ZX		 6404/*
6405 * Translate a guest virtual address to a guest physical address.
6406 */
6407int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6408 struct kvm_translation *tr)
6409{
6410 unsigned long vaddr = tr->linear_address;
6411 gpa_t gpa;
f656ce01 6412 int idx;
8b006791 6413
f656ce01 6414 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6415 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6416 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6417 tr->physical_address = gpa;
6418 tr->valid = gpa != UNMAPPED_GVA;
6419 tr->writeable = 1;
6420 tr->usermode = 0;
8b006791
ZX		 6421
6422 return 0;
6423}
6424
d0752060
HB		 6425int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6426{
98918833
SY		 6427 struct i387_fxsave_struct *fxsave =
6428 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6429
d0752060
HB		 6430 memcpy(fpu->fpr, fxsave->st_space, 128);
6431 fpu->fcw = fxsave->cwd;
6432 fpu->fsw = fxsave->swd;
6433 fpu->ftwx = fxsave->twd;
6434 fpu->last_opcode = fxsave->fop;
6435 fpu->last_ip = fxsave->rip;
6436 fpu->last_dp = fxsave->rdp;
6437 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6438
d0752060
HB		 6439 return 0;
6440}
6441
6442int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6443{
98918833
SY		 6444 struct i387_fxsave_struct *fxsave =
6445 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6446
d0752060
HB		 6447 memcpy(fxsave->st_space, fpu->fpr, 128);
6448 fxsave->cwd = fpu->fcw;
6449 fxsave->swd = fpu->fsw;
6450 fxsave->twd = fpu->ftwx;
6451 fxsave->fop = fpu->last_opcode;
6452 fxsave->rip = fpu->last_ip;
6453 fxsave->rdp = fpu->last_dp;
6454 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6455
d0752060
HB		 6456 return 0;
6457}
6458
10ab25cd 6459int fx_init(struct kvm_vcpu *vcpu)
d0752060 6460{
10ab25cd
JK		 6461 int err;
6462
6463 err = fpu_alloc(&vcpu->arch.guest_fpu);
6464 if (err)
6465 return err;
6466
98918833 6467 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6468
2acf923e
DC		 6469 /*
6470 * Ensure guest xcr0 is valid for loading
6471 */
6472 vcpu->arch.xcr0 = XSTATE_FP;
6473
ad312c7c 6474 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6475
6476 return 0;
d0752060
HB		 6477}
6478EXPORT_SYMBOL_GPL(fx_init);
6479
98918833
SY		 6480static void fx_free(struct kvm_vcpu *vcpu)
6481{
6482 fpu_free(&vcpu->arch.guest_fpu);
6483}
6484
d0752060
HB		 6485void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6486{
2608d7a1 6487 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6488 return;
6489
2acf923e
DC		 6490 /*
6491 * Restore all possible states in the guest,
6492 * and assume host would use all available bits.
6493 * Guest xcr0 would be loaded later.
6494 */
6495 kvm_put_guest_xcr0(vcpu);
d0752060 6496 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6497 __kernel_fpu_begin();
98918833 6498 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6499 trace_kvm_fpu(1);
d0752060 6500}
d0752060
HB		 6501
6502void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6503{
2acf923e
DC		 6504 kvm_put_guest_xcr0(vcpu);
6505
d0752060
HB		 6506 if (!vcpu->guest_fpu_loaded)
6507 return;
6508
6509 vcpu->guest_fpu_loaded = 0;
98918833 6510 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6511 __kernel_fpu_end();
f096ed85 6512 ++vcpu->stat.fpu_reload;
a8eeb04a 6513 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6514 trace_kvm_fpu(0);
d0752060 6515}
e9b11c17
ZX		 6516
6517void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6518{
12f9a48f 6519 kvmclock_reset(vcpu);
7f1ea208 6520
f5f48ee1 6521 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6522 fx_free(vcpu);
e9b11c17
ZX		 6523 kvm_x86_ops->vcpu_free(vcpu);
6524}
6525
6526struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6527 unsigned int id)
6528{
6755bae8
ZA		 6529 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6530 printk_once(KERN_WARNING
6531 "kvm: SMP vm created on host with unstable TSC; "
6532 "guest TSC will not be reliable\n");
26e5215f
AK		 6533 return kvm_x86_ops->vcpu_create(kvm, id);
6534}
e9b11c17 6535
26e5215f
AK		 6536int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6537{
6538 int r;
e9b11c17 6539
0bed3b56 6540 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6541 r = vcpu_load(vcpu);
6542 if (r)
6543 return r;
57f252f2
JK		 6544 kvm_vcpu_reset(vcpu);
6545 r = kvm_mmu_setup(vcpu);
e9b11c17 6546 vcpu_put(vcpu);
e9b11c17 6547
26e5215f 6548 return r;
e9b11c17
ZX		 6549}
6550
42897d86
MT		 6551int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6552{
6553 int r;
8fe8ab46 6554 struct msr_data msr;
42897d86
MT		 6555
6556 r = vcpu_load(vcpu);
6557 if (r)
6558 return r;
8fe8ab46
WA		 6559 msr.data = 0x0;
6560 msr.index = MSR_IA32_TSC;
6561 msr.host_initiated = true;
6562 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6563 vcpu_put(vcpu);
6564
6565 return r;
6566}
6567
d40ccc62 6568void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6569{
9fc77441 6570 int r;
344d9588
GN		 6571 vcpu->arch.apf.msr_val = 0;
6572
9fc77441
MT		 6573 r = vcpu_load(vcpu);
6574 BUG_ON(r);
e9b11c17
ZX		 6575 kvm_mmu_unload(vcpu);
6576 vcpu_put(vcpu);
6577
98918833 6578 fx_free(vcpu);
e9b11c17
ZX		 6579 kvm_x86_ops->vcpu_free(vcpu);
6580}
6581
66450a21 6582void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6583{
7460fb4a
AK		 6584 atomic_set(&vcpu->arch.nmi_queued, 0);
6585 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6586 vcpu->arch.nmi_injected = false;
6587
42dbaa5a
JK		 6588 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6589 vcpu->arch.dr6 = DR6_FIXED_1;
6590 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6591 kvm_update_dr7(vcpu);
42dbaa5a 6592
3842d135 6593 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6594 vcpu->arch.apf.msr_val = 0;
c9aaa895 6595 vcpu->arch.st.msr_val = 0;
3842d135 6596
12f9a48f
GC		 6597 kvmclock_reset(vcpu);
6598
af585b92
GN		 6599 kvm_clear_async_pf_completion_queue(vcpu);
6600 kvm_async_pf_hash_reset(vcpu);
6601 vcpu->arch.apf.halted = false;
3842d135 6602
f5132b01
GN		 6603 kvm_pmu_reset(vcpu);
6604
66f7b72e
JS		 6605 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6606 vcpu->arch.regs_avail = ~0;
6607 vcpu->arch.regs_dirty = ~0;
6608
57f252f2 6609 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6610}
6611
66450a21
JK		 6612void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6613{
6614 struct kvm_segment cs;
6615
6616 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6617 cs.selector = vector << 8;
6618 cs.base = vector << 12;
6619 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6620 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6621}
6622
10474ae8 6623int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6624{
ca84d1a2
ZA		 6625 struct kvm *kvm;
6626 struct kvm_vcpu *vcpu;
6627 int i;
0dd6a6ed
ZA		 6628 int ret;
6629 u64 local_tsc;
6630 u64 max_tsc = 0;
6631 bool stable, backwards_tsc = false;
18863bdd
AK		 6632
6633 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6634 ret = kvm_x86_ops->hardware_enable(garbage);
6635 if (ret != 0)
6636 return ret;
6637
6638 local_tsc = native_read_tsc();
6639 stable = !check_tsc_unstable();
6640 list_for_each_entry(kvm, &vm_list, vm_list) {
6641 kvm_for_each_vcpu(i, vcpu, kvm) {
6642 if (!stable && vcpu->cpu == smp_processor_id())
6643 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6644 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6645 backwards_tsc = true;
6646 if (vcpu->arch.last_host_tsc > max_tsc)
6647 max_tsc = vcpu->arch.last_host_tsc;
6648 }
6649 }
6650 }
6651
6652 /*
6653 * Sometimes, even reliable TSCs go backwards. This happens on
6654 * platforms that reset TSC during suspend or hibernate actions, but
6655 * maintain synchronization. We must compensate. Fortunately, we can
6656 * detect that condition here, which happens early in CPU bringup,
6657 * before any KVM threads can be running. Unfortunately, we can't
6658 * bring the TSCs fully up to date with real time, as we aren't yet far
6659 * enough into CPU bringup that we know how much real time has actually
6660 * elapsed; our helper function, get_kernel_ns() will be using boot
6661 * variables that haven't been updated yet.
6662 *
6663 * So we simply find the maximum observed TSC above, then record the
6664 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6665 * the adjustment will be applied. Note that we accumulate
6666 * adjustments, in case multiple suspend cycles happen before some VCPU
6667 * gets a chance to run again. In the event that no KVM threads get a
6668 * chance to run, we will miss the entire elapsed period, as we'll have
6669 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6670 * loose cycle time. This isn't too big a deal, since the loss will be
6671 * uniform across all VCPUs (not to mention the scenario is extremely
6672 * unlikely). It is possible that a second hibernate recovery happens
6673 * much faster than a first, causing the observed TSC here to be
6674 * smaller; this would require additional padding adjustment, which is
6675 * why we set last_host_tsc to the local tsc observed here.
6676 *
6677 * N.B. - this code below runs only on platforms with reliable TSC,
6678 * as that is the only way backwards_tsc is set above. Also note
6679 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6680 * have the same delta_cyc adjustment applied if backwards_tsc
6681 * is detected. Note further, this adjustment is only done once,
6682 * as we reset last_host_tsc on all VCPUs to stop this from being
6683 * called multiple times (one for each physical CPU bringup).
6684 *
4a969980 6685 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6686 * will be compensated by the logic in vcpu_load, which sets the TSC to
6687 * catchup mode. This will catchup all VCPUs to real time, but cannot
6688 * guarantee that they stay in perfect synchronization.
6689 */
6690 if (backwards_tsc) {
6691 u64 delta_cyc = max_tsc - local_tsc;
6692 list_for_each_entry(kvm, &vm_list, vm_list) {
6693 kvm_for_each_vcpu(i, vcpu, kvm) {
6694 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6695 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6696 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6697 &vcpu->requests);
0dd6a6ed
ZA		 6698 }
6699
6700 /*
6701 * We have to disable TSC offset matching.. if you were
6702 * booting a VM while issuing an S4 host suspend....
6703 * you may have some problem. Solving this issue is
6704 * left as an exercise to the reader.
6705 */
6706 kvm->arch.last_tsc_nsec = 0;
6707 kvm->arch.last_tsc_write = 0;
6708 }
6709
6710 }
6711 return 0;
e9b11c17
ZX		 6712}
6713
6714void kvm_arch_hardware_disable(void *garbage)
6715{
6716 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6717 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6718}
6719
6720int kvm_arch_hardware_setup(void)
6721{
6722 return kvm_x86_ops->hardware_setup();
6723}
6724
6725void kvm_arch_hardware_unsetup(void)
6726{
6727 kvm_x86_ops->hardware_unsetup();
6728}
6729
6730void kvm_arch_check_processor_compat(void *rtn)
6731{
6732 kvm_x86_ops->check_processor_compatibility(rtn);
6733}
6734
3e515705
AK		 6735bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6736{
6737 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6738}
6739
54e9818f
GN		 6740struct static_key kvm_no_apic_vcpu __read_mostly;
6741
e9b11c17
ZX		 6742int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6743{
6744 struct page *page;
6745 struct kvm *kvm;
6746 int r;
6747
6748 BUG_ON(vcpu->kvm == NULL);
6749 kvm = vcpu->kvm;
6750
9aabc88f 6751 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6752 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6753 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6754 else
a4535290 6755 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6756
6757 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6758 if (!page) {
6759 r = -ENOMEM;
6760 goto fail;
6761 }
ad312c7c 6762 vcpu->arch.pio_data = page_address(page);
e9b11c17 6763
cc578287 6764 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6765
e9b11c17
ZX		 6766 r = kvm_mmu_create(vcpu);
6767 if (r < 0)
6768 goto fail_free_pio_data;
6769
6770 if (irqchip_in_kernel(kvm)) {
6771 r = kvm_create_lapic(vcpu);
6772 if (r < 0)
6773 goto fail_mmu_destroy;
54e9818f
GN		 6774 } else
6775 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6776
890ca9ae
HY		 6777 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6778 GFP_KERNEL);
6779 if (!vcpu->arch.mce_banks) {
6780 r = -ENOMEM;
443c39bc 6781 goto fail_free_lapic;
890ca9ae
HY		 6782 }
6783 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6784
f1797359
WY		 6785 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6786 r = -ENOMEM;
f5f48ee1 6787 goto fail_free_mce_banks;
f1797359 6788 }
f5f48ee1 6789
66f7b72e
JS		 6790 r = fx_init(vcpu);
6791 if (r)
6792 goto fail_free_wbinvd_dirty_mask;
6793
ba904635 6794 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6795 vcpu->arch.pv_time_enabled = false;
af585b92 6796 kvm_async_pf_hash_reset(vcpu);
f5132b01 6797 kvm_pmu_init(vcpu);
af585b92 6798
e9b11c17 6799 return 0;
66f7b72e
JS		 6800fail_free_wbinvd_dirty_mask:
6801 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6802fail_free_mce_banks:
6803 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6804fail_free_lapic:
6805 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6806fail_mmu_destroy:
6807 kvm_mmu_destroy(vcpu);
6808fail_free_pio_data:
ad312c7c 6809 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6810fail:
6811 return r;
6812}
6813
6814void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6815{
f656ce01
MT		 6816 int idx;
6817
f5132b01 6818 kvm_pmu_destroy(vcpu);
36cb93fd 6819 kfree(vcpu->arch.mce_banks);
e9b11c17 6820 kvm_free_lapic(vcpu);
f656ce01 6821 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6822 kvm_mmu_destroy(vcpu);
f656ce01 6823 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6824 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6825 if (!irqchip_in_kernel(vcpu->kvm))
6826 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6827}
d19a9cd2 6828
e08b9637 6829int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6830{
e08b9637
CO		 6831 if (type)
6832 return -EINVAL;
6833
f05e70ac 6834 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6835 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6836
5550af4d
SY		 6837 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6838 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6839 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6840 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6841 &kvm->arch.irq_sources_bitmap);
5550af4d 6842
038f8c11 6843 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6844 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6845 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6846
6847 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6848
d89f5eff 6849 return 0;
d19a9cd2
ZX		 6850}
6851
6852static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6853{
9fc77441
MT		 6854 int r;
6855 r = vcpu_load(vcpu);
6856 BUG_ON(r);
d19a9cd2
ZX		 6857 kvm_mmu_unload(vcpu);
6858 vcpu_put(vcpu);
6859}
6860
6861static void kvm_free_vcpus(struct kvm *kvm)
6862{
6863 unsigned int i;
988a2cae 6864 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6865
6866 /*
6867 * Unpin any mmu pages first.
6868 */
af585b92
GN		 6869 kvm_for_each_vcpu(i, vcpu, kvm) {
6870 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6871 kvm_unload_vcpu_mmu(vcpu);
af585b92 6872 }
988a2cae
GN		 6873 kvm_for_each_vcpu(i, vcpu, kvm)
6874 kvm_arch_vcpu_free(vcpu);
6875
6876 mutex_lock(&kvm->lock);
6877 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6878 kvm->vcpus[i] = NULL;
d19a9cd2 6879
988a2cae
GN		 6880 atomic_set(&kvm->online_vcpus, 0);
6881 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6882}
6883
ad8ba2cd
SY		 6884void kvm_arch_sync_events(struct kvm *kvm)
6885{
ba4cef31 6886 kvm_free_all_assigned_devices(kvm);
aea924f6 6887 kvm_free_pit(kvm);
ad8ba2cd
SY		 6888}
6889
d19a9cd2
ZX		 6890void kvm_arch_destroy_vm(struct kvm *kvm)
6891{
27469d29
AH		 6892 if (current->mm == kvm->mm) {
6893 /*
6894 * Free memory regions allocated on behalf of userspace,
6895 * unless the the memory map has changed due to process exit
6896 * or fd copying.
6897 */
6898 struct kvm_userspace_memory_region mem;
6899 memset(&mem, 0, sizeof(mem));
6900 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6901 kvm_set_memory_region(kvm, &mem);
6902
6903 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6904 kvm_set_memory_region(kvm, &mem);
6905
6906 mem.slot = TSS_PRIVATE_MEMSLOT;
6907 kvm_set_memory_region(kvm, &mem);
6908 }
6eb55818 6909 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6910 kfree(kvm->arch.vpic);
6911 kfree(kvm->arch.vioapic);
d19a9cd2 6912 kvm_free_vcpus(kvm);
3d45830c
AK		 6913 if (kvm->arch.apic_access_page)
6914 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6915 if (kvm->arch.ept_identity_pagetable)
6916 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6917 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6918}
0de10343 6919
db3fe4eb
TY		 6920void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6921 struct kvm_memory_slot *dont)
6922{
6923 int i;
6924
d89cc617
TY		 6925 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6926 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6927 kvm_kvfree(free->arch.rmap[i]);
6928 free->arch.rmap[i] = NULL;
77d11309 6929 }
d89cc617
TY		 6930 if (i == 0)
6931 continue;
6932
6933 if (!dont || free->arch.lpage_info[i - 1] !=
6934 dont->arch.lpage_info[i - 1]) {
6935 kvm_kvfree(free->arch.lpage_info[i - 1]);
6936 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6937 }
6938 }
6939}
6940
6941int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6942{
6943 int i;
6944
d89cc617 6945 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6946 unsigned long ugfn;
6947 int lpages;
d89cc617 6948 int level = i + 1;
db3fe4eb
TY		 6949
6950 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6951 slot->base_gfn, level) + 1;
6952
d89cc617
TY		 6953 slot->arch.rmap[i] =
6954 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6955 if (!slot->arch.rmap[i])
77d11309 6956 goto out_free;
d89cc617
TY		 6957 if (i == 0)
6958 continue;
77d11309 6959
d89cc617
TY		 6960 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6961 sizeof(*slot->arch.lpage_info[i - 1]));
6962 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6963 goto out_free;
6964
6965 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6966 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6967 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6968 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6969 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6970 /*
6971 * If the gfn and userspace address are not aligned wrt each
6972 * other, or if explicitly asked to, disable large page
6973 * support for this slot
6974 */
6975 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6976 !kvm_largepages_enabled()) {
6977 unsigned long j;
6978
6979 for (j = 0; j < lpages; ++j)
d89cc617 6980 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6981 }
6982 }
6983
6984 return 0;
6985
6986out_free:
d89cc617
TY		 6987 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6988 kvm_kvfree(slot->arch.rmap[i]);
6989 slot->arch.rmap[i] = NULL;
6990 if (i == 0)
6991 continue;
6992
6993 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6994 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6995 }
6996 return -ENOMEM;
6997}
6998
f7784b8e
MT		 6999int kvm_arch_prepare_memory_region(struct kvm *kvm,
7000 struct kvm_memory_slot *memslot,
f7784b8e 7001 struct kvm_userspace_memory_region *mem,
7b6195a9 7002 enum kvm_mr_change change)
0de10343 7003{
7a905b14
TY		 7004 /*
7005 * Only private memory slots need to be mapped here since
7006 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7007 */
7b6195a9 7008 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7009 unsigned long userspace_addr;
604b38ac 7010
7a905b14
TY		 7011 /*
7012 * MAP_SHARED to prevent internal slot pages from being moved
7013 * by fork()/COW.
7014 */
7b6195a9 7015 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7016 PROT_READ | PROT_WRITE,
7017 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7018
7a905b14
TY		 7019 if (IS_ERR((void *)userspace_addr))
7020 return PTR_ERR((void *)userspace_addr);
604b38ac 7021
7a905b14 7022 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7023 }
7024
f7784b8e
MT		 7025 return 0;
7026}
7027
7028void kvm_arch_commit_memory_region(struct kvm *kvm,
7029 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7030 const struct kvm_memory_slot *old,
7031 enum kvm_mr_change change)
f7784b8e
MT		 7032{
7033
8482644a 7034 int nr_mmu_pages = 0;
f7784b8e 7035
8482644a 7036 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7037 int ret;
7038
8482644a
TY		 7039 ret = vm_munmap(old->userspace_addr,
7040 old->npages * PAGE_SIZE);
f7784b8e
MT		 7041 if (ret < 0)
7042 printk(KERN_WARNING
7043 "kvm_vm_ioctl_set_memory_region: "
7044 "failed to munmap memory\n");
7045 }
7046
48c0e4e9
XG		 7047 if (!kvm->arch.n_requested_mmu_pages)
7048 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7049
48c0e4e9 7050 if (nr_mmu_pages)
0de10343 7051 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7052 /*
7053 * Write protect all pages for dirty logging.
7054 * Existing largepage mappings are destroyed here and new ones will
7055 * not be created until the end of the logging.
7056 */
8482644a 7057 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7058 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 7059 /*
7060 * If memory slot is created, or moved, we need to clear all
7061 * mmio sptes.
7062 */
a2ae1622 7063 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE))
982b3394 7064 kvm_mmu_zap_mmio_sptes(kvm);
0de10343 7065}
1d737c8a 7066
2df72e9b 7067void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7068{
6ca18b69 7069 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7070}
7071
2df72e9b
MT		 7072void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7073 struct kvm_memory_slot *slot)
7074{
6ca18b69 7075 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7076}
7077
1d737c8a
ZX		 7078int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7079{
af585b92
GN		 7080 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7081 !vcpu->arch.apf.halted)
7082 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7083 || kvm_apic_has_events(vcpu)
7460fb4a 7084 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7085 (kvm_arch_interrupt_allowed(vcpu) &&
7086 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7087}
5736199a 7088
b6d33834 7089int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7090{
b6d33834 7091 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7092}
78646121
GN		 7093
7094int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7095{
7096 return kvm_x86_ops->interrupt_allowed(vcpu);
7097}
229456fc 7098
f92653ee
JK		 7099bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7100{
7101 unsigned long current_rip = kvm_rip_read(vcpu) +
7102 get_segment_base(vcpu, VCPU_SREG_CS);
7103
7104 return current_rip == linear_rip;
7105}
7106EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7107
94fe45da
JK		 7108unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7109{
7110 unsigned long rflags;
7111
7112 rflags = kvm_x86_ops->get_rflags(vcpu);
7113 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7114 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7115 return rflags;
7116}
7117EXPORT_SYMBOL_GPL(kvm_get_rflags);
7118
7119void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7120{
7121 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7122 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7123 rflags |= X86_EFLAGS_TF;
94fe45da 7124 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7125 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7126}
7127EXPORT_SYMBOL_GPL(kvm_set_rflags);
7128
56028d08
GN		 7129void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7130{
7131 int r;
7132
fb67e14f 7133 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7134 is_error_page(work->page))
56028d08
GN		 7135 return;
7136
7137 r = kvm_mmu_reload(vcpu);
7138 if (unlikely(r))
7139 return;
7140
fb67e14f
XG		 7141 if (!vcpu->arch.mmu.direct_map &&
7142 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7143 return;
7144
56028d08
GN		 7145 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7146}
7147
af585b92
GN		 7148static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7149{
7150 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7151}
7152
7153static inline u32 kvm_async_pf_next_probe(u32 key)
7154{
7155 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7156}
7157
7158static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7159{
7160 u32 key = kvm_async_pf_hash_fn(gfn);
7161
7162 while (vcpu->arch.apf.gfns[key] != ~0)
7163 key = kvm_async_pf_next_probe(key);
7164
7165 vcpu->arch.apf.gfns[key] = gfn;
7166}
7167
7168static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7169{
7170 int i;
7171 u32 key = kvm_async_pf_hash_fn(gfn);
7172
7173 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7174 (vcpu->arch.apf.gfns[key] != gfn &&
7175 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7176 key = kvm_async_pf_next_probe(key);
7177
7178 return key;
7179}
7180
7181bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7182{
7183 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7184}
7185
7186static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7187{
7188 u32 i, j, k;
7189
7190 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7191 while (true) {
7192 vcpu->arch.apf.gfns[i] = ~0;
7193 do {
7194 j = kvm_async_pf_next_probe(j);
7195 if (vcpu->arch.apf.gfns[j] == ~0)
7196 return;
7197 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7198 /*
7199 * k lies cyclically in ]i,j]
7200 * | i.k.j |
7201 * |....j i.k.| or |.k..j i...|
7202 */
7203 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7204 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7205 i = j;
7206 }
7207}
7208
7c90705b
GN		 7209static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7210{
7211
7212 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7213 sizeof(val));
7214}
7215
af585b92
GN		 7216void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7217 struct kvm_async_pf *work)
7218{
6389ee94
AK		 7219 struct x86_exception fault;
7220
7c90705b 7221 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7222 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7223
7224 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7225 (vcpu->arch.apf.send_user_only &&
7226 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7227 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7228 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7229 fault.vector = PF_VECTOR;
7230 fault.error_code_valid = true;
7231 fault.error_code = 0;
7232 fault.nested_page_fault = false;
7233 fault.address = work->arch.token;
7234 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7235 }
af585b92
GN		 7236}
7237
7238void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7239 struct kvm_async_pf *work)
7240{
6389ee94
AK		 7241 struct x86_exception fault;
7242
7c90705b
GN		 7243 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7244 if (is_error_page(work->page))
7245 work->arch.token = ~0; /* broadcast wakeup */
7246 else
7247 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7248
7249 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7250 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7251 fault.vector = PF_VECTOR;
7252 fault.error_code_valid = true;
7253 fault.error_code = 0;
7254 fault.nested_page_fault = false;
7255 fault.address = work->arch.token;
7256 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7257 }
e6d53e3b 7258 vcpu->arch.apf.halted = false;
a4fa1635 7259 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7260}
7261
7262bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7263{
7264 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7265 return true;
7266 else
7267 return !kvm_event_needs_reinjection(vcpu) &&
7268 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7269}
7270
229456fc
MT		 7271EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7272EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7273EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7274EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7275EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7276EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7277EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7278EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7279EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7280EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7281EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7282EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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